STM32L486xx HAL User Manual: STM32L4xx HAL Drivers

STM32L486xx HAL User Manual
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STM32L4xx HAL Drivers

HAL Drivers User Manual

This document contains the User Manual (UM) of the STM32L486xx HAL (Hardware Abstraction Layer) drivers.

Document tabsheets description:

  • "Modules" : List the different modules.
  • "Files" : List all the files and globals.
  • "Directories" : Firmware Directory hierarchy.
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC

  • Data Structures
  • Files
  • Directories
Modules
ADC
STM32L4xx_LL_Driver

Modules

ADC Private Constants
ADC Private Macros
ADC Exported Init structure
ADC Exported Constants
ADC Exported Macros
ADC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for ADC registers.

Register | Bit | Function
AWD2CR | AWD2CH | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
AWD3CR | AWD3CH | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
CALFACT | CALFACT_D | LL_ADC_GetCalibrationFactor
 |  | LL_ADC_SetCalibrationFactor
 | CALFACT_S | LL_ADC_GetCalibrationFactor
 |  | LL_ADC_SetCalibrationFactor
CCR | CKMODE | LL_ADC_GetCommonClock
 |  | LL_ADC_SetCommonClock
 | DELAY | LL_ADC_GetMultiTwoSamplingDelay
 |  | LL_ADC_SetMultiTwoSamplingDelay
 | DMACFG | LL_ADC_GetMultiDMATransfer
 |  | LL_ADC_SetMultiDMATransfer
 | DUAL | LL_ADC_GetMultimode
 |  | LL_ADC_SetMultimode
 | MDMA | LL_ADC_GetMultiDMATransfer
 |  | LL_ADC_SetMultiDMATransfer
 | PRESC | LL_ADC_GetCommonClock
 |  | LL_ADC_SetCommonClock
 | TSEN | LL_ADC_GetCommonPathInternalCh
 |  | LL_ADC_SetCommonPathInternalCh
 | VBATEN | LL_ADC_GetCommonPathInternalCh
 |  | LL_ADC_SetCommonPathInternalCh
 | VREFEN | LL_ADC_GetCommonPathInternalCh
 |  | LL_ADC_SetCommonPathInternalCh
CDR | RDATA_MST | LL_ADC_DMA_GetRegAddr
 |  | LL_ADC_REG_ReadMultiConversionData32
 | RDATA_SLV | LL_ADC_DMA_GetRegAddr
 |  | LL_ADC_REG_ReadMultiConversionData32
CFGR | ALIGN | LL_ADC_GetDataAlignment
 |  | LL_ADC_SetDataAlignment
 | AUTDLY | LL_ADC_GetLowPowerMode
 |  | LL_ADC_SetLowPowerMode
 | AWD1CH | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | AWD1EN | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | AWD1SGL | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | CONT | LL_ADC_REG_GetContinuousMode
 |  | LL_ADC_REG_SetContinuousMode
 | DISCEN | LL_ADC_REG_GetSequencerDiscont
 |  | LL_ADC_REG_SetSequencerDiscont
 | DISCNUM | LL_ADC_REG_GetSequencerDiscont
 |  | LL_ADC_REG_SetSequencerDiscont
 | DMACFG | LL_ADC_REG_GetDMATransfer
 |  | LL_ADC_REG_SetDMATransfer
 | DMAEN | LL_ADC_REG_GetDMATransfer
 |  | LL_ADC_REG_SetDMATransfer
 | EXTEN | LL_ADC_REG_GetTriggerEdge
 |  | LL_ADC_REG_GetTriggerSource
 |  | LL_ADC_REG_IsTriggerSourceSWStart
 |  | LL_ADC_REG_SetTriggerEdge
 |  | LL_ADC_REG_SetTriggerSource
 | EXTSEL | LL_ADC_REG_GetTriggerSource
 |  | LL_ADC_REG_SetTriggerSource
 | JAUTO | LL_ADC_INJ_GetTrigAuto
 |  | LL_ADC_INJ_SetTrigAuto
 | JAWD1EN | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | JDISCEN | LL_ADC_INJ_GetSequencerDiscont
 |  | LL_ADC_INJ_SetSequencerDiscont
 | JQDIS | LL_ADC_INJ_GetQueueMode
 |  | LL_ADC_INJ_SetQueueMode
 | JQM | LL_ADC_INJ_GetQueueMode
 |  | LL_ADC_INJ_SetQueueMode
 | OVRMOD | LL_ADC_REG_GetOverrun
 |  | LL_ADC_REG_SetOverrun
 | RES | LL_ADC_GetResolution
 |  | LL_ADC_SetResolution
CFGR2 | JOVSE | LL_ADC_GetOverSamplingScope
 |  | LL_ADC_SetOverSamplingScope
 | OVSR | LL_ADC_ConfigOverSamplingRatioShift
 |  | LL_ADC_GetOverSamplingRatio
 | OVSS | LL_ADC_ConfigOverSamplingRatioShift
 |  | LL_ADC_GetOverSamplingShift
 | ROVSE | LL_ADC_GetOverSamplingScope
 |  | LL_ADC_SetOverSamplingScope
 | ROVSM | LL_ADC_GetOverSamplingScope
 |  | LL_ADC_SetOverSamplingScope
 | TROVS | LL_ADC_GetOverSamplingDiscont
 |  | LL_ADC_SetOverSamplingDiscont
CR | ADCAL | LL_ADC_IsCalibrationOnGoing
 |  | LL_ADC_StartCalibration
 | ADCALDIF | LL_ADC_StartCalibration
 | ADDIS | LL_ADC_Disable
 |  | LL_ADC_IsDisableOngoing
 | ADEN | LL_ADC_Enable
 |  | LL_ADC_IsEnabled
 | ADSTART | LL_ADC_REG_IsConversionOngoing
 |  | LL_ADC_REG_StartConversion
 | ADSTP | LL_ADC_REG_IsStopConversionOngoing
 |  | LL_ADC_REG_StopConversion
 | ADVREGEN | LL_ADC_DisableInternalRegulator
 |  | LL_ADC_EnableInternalRegulator
 |  | LL_ADC_IsInternalRegulatorEnabled
 | DEEPPWD | LL_ADC_DisableDeepPowerDown
 |  | LL_ADC_EnableDeepPowerDown
 |  | LL_ADC_IsDeepPowerDownEnabled
 | JADSTART | LL_ADC_INJ_IsConversionOngoing
 |  | LL_ADC_INJ_StartConversion
 | JADSTP | LL_ADC_INJ_IsStopConversionOngoing
 |  | LL_ADC_INJ_StopConversion
CSR | ADRDY_MST | LL_ADC_IsActiveFlag_MST_ADRDY
 | ADRDY_SLV | LL_ADC_IsActiveFlag_SLV_ADRDY
 | AWD1_MST | LL_ADC_IsActiveFlag_MST_AWD1
 | AWD1_SLV | LL_ADC_IsActiveFlag_SLV_AWD1
 | AWD2_MST | LL_ADC_IsActiveFlag_MST_AWD2
 | AWD2_SLV | LL_ADC_IsActiveFlag_SLV_AWD2
 | AWD3_MST | LL_ADC_IsActiveFlag_MST_AWD3
 | AWD3_SLV | LL_ADC_IsActiveFlag_SLV_AWD3
 | EOC_MST | LL_ADC_IsActiveFlag_MST_EOC
 | EOC_SLV | LL_ADC_IsActiveFlag_SLV_EOC
 | EOSMP_MST | LL_ADC_IsActiveFlag_MST_EOSMP
 | EOSMP_SLV | LL_ADC_IsActiveFlag_SLV_EOSMP
 | EOS_MST | LL_ADC_IsActiveFlag_MST_EOS
 | EOS_SLV | LL_ADC_IsActiveFlag_SLV_EOS
 | JEOC_MST | LL_ADC_IsActiveFlag_MST_JEOC
 | JEOC_SLV | LL_ADC_IsActiveFlag_SLV_JEOC
 | JEOS_MST | LL_ADC_IsActiveFlag_MST_JEOS
 | JEOS_SLV | LL_ADC_IsActiveFlag_SLV_JEOS
 | JQOVF_MST | LL_ADC_IsActiveFlag_MST_JQOVF
 | JQOVF_SLV | LL_ADC_IsActiveFlag_SLV_JQOVF
 | OVR_MST | LL_ADC_IsActiveFlag_MST_OVR
 | OVR_SLV | LL_ADC_IsActiveFlag_SLV_OVR
DIFSEL | DIFSEL | LL_ADC_GetChannelSamplingTime
DR | RDATA | LL_ADC_DMA_GetRegAddr
 |  | LL_ADC_REG_ReadConversionData10
 |  | LL_ADC_REG_ReadConversionData12
 |  | LL_ADC_REG_ReadConversionData32
 |  | LL_ADC_REG_ReadConversionData6
 |  | LL_ADC_REG_ReadConversionData8
IER | ADRDYIE | LL_ADC_DisableIT_ADRDY
 |  | LL_ADC_EnableIT_ADRDY
 |  | LL_ADC_IsEnabledIT_ADRDY
 | AWD1IE | LL_ADC_DisableIT_AWD1
 |  | LL_ADC_EnableIT_AWD1
 |  | LL_ADC_IsEnabledIT_AWD1
 | AWD2IE | LL_ADC_DisableIT_AWD2
 |  | LL_ADC_EnableIT_AWD2
 |  | LL_ADC_IsEnabledIT_AWD2
 | AWD3IE | LL_ADC_DisableIT_AWD3
 |  | LL_ADC_EnableIT_AWD3
 |  | LL_ADC_IsEnabledIT_AWD3
 | EOCIE | LL_ADC_DisableIT_EOC
 |  | LL_ADC_EnableIT_EOC
 |  | LL_ADC_IsEnabledIT_EOC
 | EOSIE | LL_ADC_DisableIT_EOS
 |  | LL_ADC_EnableIT_EOS
 |  | LL_ADC_IsEnabledIT_EOS
 | EOSMPIE | LL_ADC_DisableIT_EOSMP
 |  | LL_ADC_EnableIT_EOSMP
 |  | LL_ADC_IsEnabledIT_EOSMP
 | JEOCIE | LL_ADC_DisableIT_JEOC
 |  | LL_ADC_EnableIT_JEOC
 |  | LL_ADC_IsEnabledIT_JEOC
 | JEOSIE | LL_ADC_DisableIT_JEOS
 |  | LL_ADC_EnableIT_JEOS
 |  | LL_ADC_IsEnabledIT_JEOS
 | JQOVFIE | LL_ADC_DisableIT_JQOVF
 |  | LL_ADC_EnableIT_JQOVF
 |  | LL_ADC_IsEnabledIT_JQOVF
 | OVRIE | LL_ADC_DisableIT_OVR
 |  | LL_ADC_EnableIT_OVR
 |  | LL_ADC_IsEnabledIT_OVR
ISR | ADRDY | LL_ADC_ClearFlag_ADRDY
 |  | LL_ADC_IsActiveFlag_ADRDY
 | AWD1 | LL_ADC_ClearFlag_AWD1
 |  | LL_ADC_IsActiveFlag_AWD1
 | AWD2 | LL_ADC_ClearFlag_AWD2
 |  | LL_ADC_IsActiveFlag_AWD2
 | AWD3 | LL_ADC_ClearFlag_AWD3
 |  | LL_ADC_IsActiveFlag_AWD3
 | EOC | LL_ADC_ClearFlag_EOC
 |  | LL_ADC_IsActiveFlag_EOC
 | EOS | LL_ADC_ClearFlag_EOS
 |  | LL_ADC_IsActiveFlag_EOS
 | EOSMP | LL_ADC_ClearFlag_EOSMP
 |  | LL_ADC_IsActiveFlag_EOSMP
 | JEOC | LL_ADC_ClearFlag_JEOC
 |  | LL_ADC_IsActiveFlag_JEOC
 | JEOS | LL_ADC_ClearFlag_JEOS
 |  | LL_ADC_IsActiveFlag_JEOS
 | JQOVF | LL_ADC_ClearFlag_JQOVF
 |  | LL_ADC_IsActiveFlag_JQOVF
 | OVR | LL_ADC_ClearFlag_OVR
 |  | LL_ADC_IsActiveFlag_OVR
JDR1 | JDATA | LL_ADC_INJ_ReadConversionData10
 |  | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
 |  | LL_ADC_INJ_ReadConversionData6
 |  | LL_ADC_INJ_ReadConversionData8
JDR2 | JDATA | LL_ADC_INJ_ReadConversionData10
 |  | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
 |  | LL_ADC_INJ_ReadConversionData6
 |  | LL_ADC_INJ_ReadConversionData8
JDR3 | JDATA | LL_ADC_INJ_ReadConversionData10
 |  | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
 |  | LL_ADC_INJ_ReadConversionData6
 |  | LL_ADC_INJ_ReadConversionData8
JDR4 | JDATA | LL_ADC_INJ_ReadConversionData10
 |  | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
 |  | LL_ADC_INJ_ReadConversionData6
 |  | LL_ADC_INJ_ReadConversionData8
JSQR | JEXTEN | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetTriggerEdge
 |  | LL_ADC_INJ_GetTriggerSource
 |  | LL_ADC_INJ_IsTriggerSourceSWStart
 |  | LL_ADC_INJ_SetTriggerEdge
 |  | LL_ADC_INJ_SetTriggerSource
 | JEXTSEL | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetTriggerSource
 |  | LL_ADC_INJ_SetTriggerSource
 | JL | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetSequencerLength
 |  | LL_ADC_INJ_SetSequencerLength
 | JSQ1 | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetSequencerRanks
 |  | LL_ADC_INJ_SetSequencerRanks
 | JSQ2 | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetSequencerRanks
 |  | LL_ADC_INJ_SetSequencerRanks
 | JSQ3 | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetSequencerRanks
 |  | LL_ADC_INJ_SetSequencerRanks
 | JSQ4 | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetSequencerRanks
 |  | LL_ADC_INJ_SetSequencerRanks
OFR1 | OFFSET1 | LL_ADC_GetOffsetLevel
 |  | LL_ADC_SetOffset
 | OFFSET1_CH | LL_ADC_GetOffsetChannel
 |  | LL_ADC_SetOffset
 | OFFSET1_EN | LL_ADC_GetOffsetState
 |  | LL_ADC_SetOffset
 |  | LL_ADC_SetOffsetState
OFR2 | OFFSET2 | LL_ADC_GetOffsetLevel
 |  | LL_ADC_SetOffset
 | OFFSET2_CH | LL_ADC_GetOffsetChannel
 |  | LL_ADC_SetOffset
 | OFFSET2_EN | LL_ADC_GetOffsetState
 |  | LL_ADC_SetOffset
 |  | LL_ADC_SetOffsetState
OFR3 | OFFSET3 | LL_ADC_GetOffsetLevel
 |  | LL_ADC_SetOffset
 | OFFSET3_CH | LL_ADC_GetOffsetChannel
 |  | LL_ADC_SetOffset
 | OFFSET3_EN | LL_ADC_GetOffsetState
 |  | LL_ADC_SetOffset
 |  | LL_ADC_SetOffsetState
OFR4 | OFFSET4 | LL_ADC_GetOffsetLevel
 |  | LL_ADC_SetOffset
 | OFFSET4_CH | LL_ADC_GetOffsetChannel
 |  | LL_ADC_SetOffset
 | OFFSET4_EN | LL_ADC_GetOffsetState
 |  | LL_ADC_SetOffset
 |  | LL_ADC_SetOffsetState
SMPR1 | SMP0 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP1 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP2 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP3 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP4 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP5 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP6 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP7 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP8 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP9 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
SMPR2 | SMP10 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP11 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP12 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP13 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP14 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP15 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP16 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP17 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP18 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
SQR1 | L | LL_ADC_REG_GetSequencerLength
 |  | LL_ADC_REG_SetSequencerLength
 | SQ1 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ2 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ3 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ4 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SQR2 | SQ5 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ6 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ7 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ8 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ9 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SQR3 | SQ10 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ11 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ12 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ13 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ14 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SQR4 | SQ15 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ16 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
TR1 | HT1 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
 | LT1 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
TR2 | HT2 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
 | LT2 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
TR3 | HT3 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
 | LT3 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
#define | ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
#define | ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
#define | ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
#define | ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
#define | ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
#define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
#define | ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
#define | ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
#define | ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
#define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
#define | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
#define | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
#define | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
#define | ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_REG_TRIG_SOURCE_MASK
#define | ADC_REG_TRIG_EDGE_MASK
#define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
#define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
#define | ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_INJ_TRIG_SOURCE_MASK
#define | ADC_INJ_TRIG_EDGE_MASK
#define | ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
#define | ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define | ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
#define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
#define | ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
#define | ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
#define | ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
#define | ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
#define | ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define | ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define | ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define | ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define | ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define | ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define | ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define | ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define | ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define | ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define | ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define | ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define | ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define | ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define | ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define | ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define | ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define | ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define | ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
#define | ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
#define | ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
#define | ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
#define | ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
#define | ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
#define | ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
#define | ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
#define | ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
#define | ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
#define | ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
#define | ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
#define | ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
#define | ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
#define | ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
#define | ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
#define | ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
#define | ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
#define | ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
#define | ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define | ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
#define | ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define | ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
#define | ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00100000U)
#define | ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00200000U)
#define | ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024U)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define | ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define | ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define | ADC_OFR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_OFR2_REGOFFSET ((uint32_t)0x00000001U)
#define | ADC_OFR3_REGOFFSET ((uint32_t)0x00000002U)
#define | ADC_OFR4_REGOFFSET ((uint32_t)0x00000003U)
#define | ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
#define | ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
#define | ADC_CFGR_AWD1SGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
#define | ADC_CFGR_AWD1EN_BITOFFSET_POS ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
#define | ADC_CFGR_JAWD1EN_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
#define | ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
#define | ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define | VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | VREFINT_CAL_VREF ((uint32_t) 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

Define Documentation

#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)

Definition at line 310 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024U)

Definition at line 311 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

Definition at line 315 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 304 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 316 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00100000U)

Definition at line 305 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00200000U)

Definition at line 306 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

Definition at line 317 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

Definition at line 313 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)

Definition at line 320 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)

Definition at line 321 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)

Definition at line 322 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

Definition at line 323 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_CFGR_AWD1EN_BITOFFSET_POS ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */

Definition at line 338 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_CFGR_AWD1SGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */

Definition at line 337 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_CFGR_JAWD1EN_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */

Definition at line 339 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */

Definition at line 336 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)

Definition at line 239 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)

Definition at line 217 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */

Definition at line 261 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)

Definition at line 249 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )

Definition at line 227 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */

Definition at line 271 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)

Definition at line 250 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 228 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */

Definition at line 272 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)

Definition at line 251 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )

Definition at line 229 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */

Definition at line 273 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)

Definition at line 252 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 230 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */

Definition at line 274 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)

Definition at line 253 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )

Definition at line 231 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */

Definition at line 275 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)

Definition at line 254 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 232 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */

Definition at line 276 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)

Definition at line 255 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )

Definition at line 233 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */

Definition at line 277 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)

Definition at line 256 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)

Definition at line 234 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */

Definition at line 278 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)

Definition at line 257 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )

Definition at line 235 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */

Definition at line 279 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)

Definition at line 240 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)

Definition at line 218 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */

Definition at line 262 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)

Definition at line 241 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )

Definition at line 219 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */

Definition at line 263 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)

Definition at line 242 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 220 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */

Definition at line 264 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)

Definition at line 243 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )

Definition at line 221 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */

Definition at line 265 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)

Definition at line 244 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 222 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */

Definition at line 266 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)

Definition at line 245 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )

Definition at line 223 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */

Definition at line 267 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)

Definition at line 246 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 224 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */

Definition at line 268 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)

Definition at line 247 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )

Definition at line 225 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */

Definition at line 269 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)

Definition at line 248 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)

Definition at line 226 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */

Definition at line 270 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 195 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */

Definition at line 202 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */

Definition at line 203 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)

Definition at line 204 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Definition at line 197 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */

Definition at line 196 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)

Definition at line 194 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), and LL_ADC_SetOffset().

#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */

Definition at line 199 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

Definition at line 210 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)

Definition at line 212 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */

Definition at line 213 of file stm32l4xx_ll_adc.h.

#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)

Definition at line 85 of file stm32l4xx_ll_adc.c.

#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

Definition at line 344 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_Disable(), LL_ADC_DisableDeepPowerDown(), LL_ADC_DisableInternalRegulator(), LL_ADC_Enable(), LL_ADC_EnableDeepPowerDown(), LL_ADC_EnableInternalRegulator(), LL_ADC_INJ_StartConversion(), LL_ADC_INJ_StopConversion(), LL_ADC_REG_StartConversion(), LL_ADC_REG_StopConversion(), and LL_ADC_StartCalibration().

#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

Definition at line 115 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData6(), and LL_ADC_INJ_ReadConversionData8().

#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */

Definition at line 120 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */

Definition at line 121 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */

Definition at line 122 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */

Definition at line 123 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 116 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), and LL_ADC_INJ_SetSequencerRanks().

#define ADC_INJ_TRIG_EDGE_MASK
Value:
(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1U)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2U)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3U))  )

Definition at line 172 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

Definition at line 159 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */

Definition at line 179 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */

Definition at line 178 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_TRIG_SOURCE_MASK
Value:
(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \
                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 1U)) | \
                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 2U)) | \
                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 3U))  )

Definition at line 164 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 110 of file stm32l4xx_ll_adc.h.

#define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)

Definition at line 111 of file stm32l4xx_ll_adc.h.

#define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)

Definition at line 112 of file stm32l4xx_ll_adc.h.

#define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)

Definition at line 113 of file stm32l4xx_ll_adc.h.

#define ADC_OFR1_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 328 of file stm32l4xx_ll_adc.h.

#define ADC_OFR2_REGOFFSET ((uint32_t)0x00000001U)

Definition at line 329 of file stm32l4xx_ll_adc.h.

#define ADC_OFR3_REGOFFSET ((uint32_t)0x00000002U)

Definition at line 330 of file stm32l4xx_ll_adc.h.

#define ADC_OFR4_REGOFFSET ((uint32_t)0x00000003U)

Definition at line 331 of file stm32l4xx_ll_adc.h.

#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)

Definition at line 332 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */

Definition at line 93 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */

Definition at line 94 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */

Definition at line 95 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */

Definition at line 96 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */

Definition at line 97 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */

Definition at line 98 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */

Definition at line 99 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */

Definition at line 84 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */

Definition at line 85 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */

Definition at line 86 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */

Definition at line 87 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */

Definition at line 88 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */

Definition at line 89 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */

Definition at line 90 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */

Definition at line 91 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */

Definition at line 92 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 80 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

Definition at line 79 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_TRIG_EDGE_MASK
Value:
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1U)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2U)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3U))  )

Definition at line 144 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

Definition at line 131 of file stm32l4xx_ll_adc.h.

#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */

Definition at line 151 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */

Definition at line 150 of file stm32l4xx_ll_adc.h.

#define ADC_REG_TRIG_SOURCE_MASK
Value:
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 1U)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 2U)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 3U))  )

Definition at line 136 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)

Definition at line 289 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetCalibrationFactor(), and LL_ADC_SetCalibrationFactor().

#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)

Definition at line 288 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_StartCalibration().

#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */

Definition at line 290 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSingleDiff(), and LL_ADC_SetChannelSingleDiff().

#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */

Definition at line 291 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_SetChannelSingleDiff().

#define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 208 of file stm32l4xx_ll_adc.h.

#define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)

Definition at line 209 of file stm32l4xx_ll_adc.h.

#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 74 of file stm32l4xx_ll_adc.h.

#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)

Definition at line 75 of file stm32l4xx_ll_adc.h.

#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)

Definition at line 76 of file stm32l4xx_ll_adc.h.

#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)

Definition at line 77 of file stm32l4xx_ll_adc.h.

#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)

Definition at line 86 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)

Definition at line 87 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */

Definition at line 340 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds().

#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 352 of file stm32l4xx_ll_adc.h.

#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 354 of file stm32l4xx_ll_adc.h.

#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 353 of file stm32l4xx_ll_adc.h.

#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 355 of file stm32l4xx_ll_adc.h.

#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

Definition at line 356 of file stm32l4xx_ll_adc.h.

#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 349 of file stm32l4xx_ll_adc.h.

#define VREFINT_CAL_VREF ((uint32_t) 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

Definition at line 350 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__)
#define | IS_LL_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_LOW_POWER(__LOW_POWER__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)
#define | IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)
#define | IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)
#define | IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)
#define | __ADC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __ADC_MASK_SHIFT | ( | __BITS__,
 |  | __MASK__
 | ) | (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))

Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).

Parameters:
__BITS__ | Bits in register 32 bits
__MASK__ | Mask in register 32 bits
Return values:
Bits in register 32 bits

Definition at line 377 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDMonitChannels(), LL_ADC_GetAnalogWDThresholds(), LL_ADC_GetChannelSamplingTime(), LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData6(), LL_ADC_INJ_ReadConversionData8(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetAnalogWDMonitChannels(), LL_ADC_SetAnalogWDThresholds(), and LL_ADC_SetChannelSamplingTime().

#define __ADC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 388 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDMonitChannels(), LL_ADC_GetAnalogWDThresholds(), LL_ADC_GetChannelSamplingTime(), LL_ADC_GetOffsetChannel(), LL_ADC_GetOffsetLevel(), LL_ADC_GetOffsetState(), LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData6(), LL_ADC_INJ_ReadConversionData8(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetAnalogWDMonitChannels(), LL_ADC_SetAnalogWDThresholds(), LL_ADC_SetChannelSamplingTime(), and LL_ADC_SetOffset().

#define IS_LL_ADC_COMMON_CLOCK ( __CLOCK__ )
Value:
(   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
  )

Definition at line 101 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_DATA_ALIGN ( __DATA_ALIGN__ )
Value:
(   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
  )

Definition at line 128 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE ( __INJ_SEQ_DISCONT_MODE__ )
Value:
(   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
  )

Definition at line 247 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH ( __INJ_SEQ_SCAN_LENGTH__ )
Value:
(   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
  )

Definition at line 240 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_AUTO ( __INJ_TRIG_AUTO__ )
Value:
(   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
  )

Definition at line 235 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_EXT_EDGE ( __INJ_TRIG_EXT_EDGE__ )
Value:
(   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
  )

Definition at line 229 of file stm32l4xx_ll_adc.c.

#define IS_LL_ADC_INJ_TRIG_SOURCE ( __INJ_TRIG_SOURCE__ )
Value:
(   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
  )

Definition at line 209 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_LOW_POWER ( __LOW_POWER__ )
Value:
(   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
  )

Definition at line 133 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_MULTI_DMA_TRANSFER ( __MULTI_DMA_TRANSFER__ )
Value:
(   ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)              \
   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B)       \
   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B)         \
   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B)       \
   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B)         \
  )

Definition at line 266 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_MULTI_MASTER_SLAVE ( __MULTI_MASTER_SLAVE__ )
Value:
(   ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                        \
   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
  )

Definition at line 289 of file stm32l4xx_ll_adc.c.

#define IS_LL_ADC_MULTI_MODE ( __MULTI_MODE__ )
Value:
(   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
  )

Definition at line 255 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_MULTI_TWOSMP_DELAY ( __MULTI_TWOSMP_DELAY__ )
Value:
(   ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)           \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)          \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)         \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)         \
   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)         \
  )

Definition at line 274 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_REG_CONTINUOUS_MODE ( __REG_CONTINUOUS_MODE__ )
Value:
(   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
  )

Definition at line 160 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_DMA_TRANSFER ( __REG_DMA_TRANSFER__ )
Value:
(   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
  )

Definition at line 165 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR ( __REG_OVR_DATA_BEHAVIOR__ )
Value:
(   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
  )

Definition at line 171 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE ( __REG_SEQ_DISCONT_MODE__ )
Value:
(   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
  )

Definition at line 195 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH ( __REG_SEQ_SCAN_LENGTH__ )
Value:
(   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
  )

Definition at line 176 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_TRIG_SOURCE ( __REG_TRIG_SOURCE__ )
Value:
(   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
  )

Definition at line 140 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_RESOLUTION ( __RESOLUTION__ )
Value:
(   ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
  )

Definition at line 121 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_Init().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_ADC_CommonInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_CommonInitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...

#include <stm32l4xx_ll_adc.h>

Data Fields

uint32_t | CommonClock
uint32_t | Multimode
uint32_t | MultiDMATransfer
uint32_t | MultiTwoSamplingDelay

Detailed Description

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance).

Note:
The setting of these parameters by function LL_ADC_CommonInit() is conditioned to ADC instances state (all ADC instances sharing the same ADC common instance): All ADC instances sharing the same ADC common instance must be disabled.

Definition at line 412 of file stm32l4xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_CommonInitTypeDef::CommonClock

Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of ADC common - Clock source

Note:
On this STM32 serie, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual.

This feature can be modified afterwards using unitary function LL_ADC_SetCommonClock().

Definition at line 414 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

uint32_t LL_ADC_CommonInitTypeDef::MultiDMATransfer

Set ADC multimode conversion data transfer: no transfer or transfer by DMA. This parameter can be a value of Multimode - DMA transfer

This feature can be modified afterwards using unitary function LL_ADC_SetMultiDMATransfer().

Definition at line 428 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

uint32_t LL_ADC_CommonInitTypeDef::Multimode

Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). This parameter can be a value of Multimode - Mode

This feature can be modified afterwards using unitary function LL_ADC_SetMultimode().

Definition at line 423 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

uint32_t LL_ADC_CommonInitTypeDef::MultiTwoSamplingDelay

Set ADC multimode delay between 2 sampling phases. This parameter can be a value of Multimode - Delay between two sampling phases

This feature can be modified afterwards using unitary function LL_ADC_SetMultiTwoSamplingDelay().

Definition at line 433 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_adc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC instance. More...

#include <stm32l4xx_ll_adc.h>

Data Fields

uint32_t | Resolution
uint32_t | DataAlignment
uint32_t | LowPowerMode

Detailed Description

Structure definition of some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 families). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 461 of file stm32l4xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_InitTypeDef::DataAlignment

Set ADC conversion data alignment. This parameter can be a value of ADC instance - Data alignment

This feature can be modified afterwards using unitary function LL_ADC_SetDataAlignment().

Definition at line 468 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::LowPowerMode

Set ADC low power mode. This parameter can be a value of ADC instance - Low power mode

This feature can be modified afterwards using unitary function LL_ADC_SetLowPowerMode().

Definition at line 473 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::Resolution

Set ADC resolution. This parameter can be a value of ADC instance - Resolution

This feature can be modified afterwards using unitary function LL_ADC_SetResolution().

Definition at line 463 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_adc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_ADC_REG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_REG_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group regular. More...

#include <stm32l4xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | ContinuousMode
uint32_t | DMATransfer
uint32_t | Overrun

Detailed Description

Structure definition of some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_REG_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 499 of file stm32l4xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_REG_InitTypeDef::ContinuousMode

Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of ADC group regular - Continuous mode Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

This feature can be modified afterwards using unitary function LL_ADC_REG_SetContinuousMode().

Definition at line 521 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::DMATransfer

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of ADC group regular - DMA transfer of ADC conversion data

This feature can be modified afterwards using unitary function LL_ADC_REG_SetDMATransfer().

Definition at line 527 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::Overrun

Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of ADC group regular - Overrun behavior on conversion data

This feature can be modified afterwards using unitary function LL_ADC_REG_SetOverrun().

Definition at line 532 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerDiscont

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group regular - Sequencer discontinuous mode

Note:
This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerDiscont().

Definition at line 514 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerLength

Set ADC group regular sequencer length. This parameter can be a value of ADC group regular - Sequencer scan length

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerLength().

Definition at line 509 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::TriggerSource

Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). This parameter can be a value of ADC group regular - Trigger source

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTriggerEdge().

This feature can be modified afterwards using unitary function LL_ADC_REG_SetTriggerSource().

Definition at line 501 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_adc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_ADC_INJ_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_INJ_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group injected. More...

#include <stm32l4xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | TrigAuto

Detailed Description

Structure definition of some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_INJ_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 559 of file stm32l4xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_INJ_InitTypeDef::SequencerDiscont

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group injected - Sequencer discontinuous mode

Note:
This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerDiscont().

Definition at line 574 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::SequencerLength

Set ADC group injected sequencer length. This parameter can be a value of ADC group injected - Sequencer scan length

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerLength().

Definition at line 569 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TrigAuto

Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of ADC group injected - Automatic trigger mode Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTrigAuto().

Definition at line 581 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TriggerSource

Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). This parameter can be a value of ADC group injected - Trigger source

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_INJ_SetTriggerEdge().

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTriggerSource().

Definition at line 561 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_adc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC flags

Defines
ADC flags
ADC Exported Constants

Flags defines which can be used with LL_ADC_ReadReg function. More...

Defines

#define | LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define | LL_ADC_FLAG_EOC ADC_ISR_EOC
#define | LL_ADC_FLAG_EOS ADC_ISR_EOS
#define | LL_ADC_FLAG_OVR ADC_ISR_OVR
#define | LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | LL_ADC_FLAG_JEOC ADC_ISR_JEOC
#define | LL_ADC_FLAG_JEOS ADC_ISR_JEOS
#define | LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST
#define | LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV
#define | LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST
#define | LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV
#define | LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST
#define | LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV
#define | LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST
#define | LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV
#define | LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST
#define | LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV
#define | LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST
#define | LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV
#define | LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST
#define | LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV
#define | LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST
#define | LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV
#define | LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST
#define | LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV
#define | LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST
#define | LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV
#define | LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST
#define | LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV

Detailed Description

Flags defines which can be used with LL_ADC_ReadReg function.

Define Documentation

#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY

ADC flag ADC instance ready

Definition at line 603 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_ADRDY(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_ADRDY().

#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST

ADC flag ADC multimode master instance ready

Definition at line 615 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_ADRDY().

#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV

ADC flag ADC multimode slave instance ready

Definition at line 616 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_ADRDY().

#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC flag ADC analog watchdog 1

Definition at line 611 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD1(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD1().

#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST

ADC flag ADC multimode master analog watchdog 1 of the ADC master

Definition at line 631 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_AWD1().

#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV

ADC flag ADC multimode slave analog watchdog 1 of the ADC slave

Definition at line 632 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_AWD1().

#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC flag ADC analog watchdog 2

Definition at line 612 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD2(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD2().

#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST

ADC flag ADC multimode master analog watchdog 2 of the ADC master

Definition at line 633 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_AWD2().

#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV

ADC flag ADC multimode slave analog watchdog 2 of the ADC slave

Definition at line 634 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_AWD2().

#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC flag ADC analog watchdog 3

Definition at line 613 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD3(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD3().

#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST

ADC flag ADC multimode master analog watchdog 3 of the ADC master

Definition at line 635 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_AWD3().

#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV

ADC flag ADC multimode slave analog watchdog 3 of the ADC slave

Definition at line 636 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_AWD3().

#define LL_ADC_FLAG_EOC ADC_ISR_EOC

ADC flag ADC group regular end of unitary conversion

Definition at line 604 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOC(), and LL_ADC_DeInit().

#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST

ADC flag ADC multimode master group regular end of unitary conversion

Definition at line 617 of file stm32l4xx_ll_adc.h.

#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV

ADC flag ADC multimode slave group regular end of unitary conversion

Definition at line 618 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_EOC(), and LL_ADC_IsActiveFlag_SLV_EOC().

#define LL_ADC_FLAG_EOS ADC_ISR_EOS

ADC flag ADC group regular end of sequence conversions

Definition at line 605 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOS().

#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST

ADC flag ADC multimode master group regular end of sequence conversions

Definition at line 619 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_EOS().

#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV

ADC flag ADC multimode slave group regular end of sequence conversions

Definition at line 620 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_EOS().

#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC flag ADC group regular end of sampling phase

Definition at line 607 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOSMP(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOSMP().

#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST

ADC flag ADC multimode master group regular end of sampling phase

Definition at line 623 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_EOSMP().

#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV

ADC flag ADC multimode slave group regular end of sampling phase

Definition at line 624 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_EOSMP().

#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC

ADC flag ADC group injected end of unitary conversion

Definition at line 608 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JEOC(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JEOC().

#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST

ADC flag ADC multimode master group injected end of unitary conversion

Definition at line 625 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_JEOC().

#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV

ADC flag ADC multimode slave group injected end of unitary conversion

Definition at line 626 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_JEOC().

#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS

ADC flag ADC group injected end of sequence conversions

Definition at line 609 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JEOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JEOS().

#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST

ADC flag ADC multimode master group injected end of sequence conversions

Definition at line 627 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_JEOS().

#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV

ADC flag ADC multimode slave group injected end of sequence conversions

Definition at line 628 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_JEOS().

#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF

ADC flag ADC group injected contexts queue overflow

Definition at line 610 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JQOVF(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JQOVF().

#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST

ADC flag ADC multimode master group injected contexts queue overflow

Definition at line 629 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_JQOVF().

#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV

ADC flag ADC multimode slave group injected contexts queue overflow

Definition at line 630 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_JQOVF().

#define LL_ADC_FLAG_OVR ADC_ISR_OVR

ADC flag ADC group regular overrun

Definition at line 606 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_OVR(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_OVR().

#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST

ADC flag ADC multimode master group regular overrun

Definition at line 621 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_MST_OVR().

#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV

ADC flag ADC multimode slave group regular overrun

Definition at line 622 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_OVR().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC interruptions for configuration (interruption enable or disable)

Defines
ADC interruptions for configuration (interruption enable or disable)
ADC Exported Constants

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions. More...

Defines

#define | LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define | LL_ADC_IT_EOC ADC_IER_EOCIE
#define | LL_ADC_IT_EOS ADC_IER_EOSIE
#define | LL_ADC_IT_OVR ADC_IER_OVRIE
#define | LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | LL_ADC_IT_JEOC ADC_IER_JEOCIE
#define | LL_ADC_IT_JEOS ADC_IER_JEOSIE
#define | LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define | LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define | LL_ADC_IT_AWD3 ADC_IER_AWD3IE

Detailed Description

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

Define Documentation

#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE

ADC interruption ADC instance ready

Definition at line 646 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_ADRDY(), LL_ADC_EnableIT_ADRDY(), and LL_ADC_IsEnabledIT_ADRDY().

#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE

ADC interruption ADC analog watchdog 1

Definition at line 654 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD1(), LL_ADC_EnableIT_AWD1(), and LL_ADC_IsEnabledIT_AWD1().

#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE

ADC interruption ADC analog watchdog 2

Definition at line 655 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD2(), LL_ADC_EnableIT_AWD2(), and LL_ADC_IsEnabledIT_AWD2().

#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE

ADC interruption ADC analog watchdog 3

Definition at line 656 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD3(), LL_ADC_EnableIT_AWD3(), and LL_ADC_IsEnabledIT_AWD3().

#define LL_ADC_IT_EOC ADC_IER_EOCIE

ADC interruption ADC group regular end of unitary conversion

Definition at line 647 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOC(), LL_ADC_EnableIT_EOC(), and LL_ADC_IsEnabledIT_EOC().

#define LL_ADC_IT_EOS ADC_IER_EOSIE

ADC interruption ADC group regular end of sequence conversions

Definition at line 648 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOS(), LL_ADC_EnableIT_EOS(), and LL_ADC_IsEnabledIT_EOS().

#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE

ADC interruption ADC group regular end of sampling phase

Definition at line 650 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOSMP(), LL_ADC_EnableIT_EOSMP(), and LL_ADC_IsEnabledIT_EOSMP().

#define LL_ADC_IT_JEOC ADC_IER_JEOCIE

ADC interruption ADC group injected end of unitary conversion

Definition at line 651 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_JEOC(), LL_ADC_EnableIT_JEOC(), and LL_ADC_IsEnabledIT_JEOC().

#define LL_ADC_IT_JEOS ADC_IER_JEOSIE

ADC interruption ADC group injected end of sequence conversions

Definition at line 652 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_JEOS(), LL_ADC_EnableIT_JEOS(), and LL_ADC_IsEnabledIT_JEOS().

#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE

ADC interruption ADC group injected contexts queue overflow

Definition at line 653 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_JQOVF(), LL_ADC_EnableIT_JQOVF(), and LL_ADC_IsEnabledIT_JQOVF().

#define LL_ADC_IT_OVR ADC_IER_OVRIE

ADC interruption ADC group regular overrun

Definition at line 649 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_OVR(), LL_ADC_EnableIT_OVR(), and LL_ADC_IsEnabledIT_OVR().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC registers compliant with specific purpose

Defines
ADC registers compliant with specific purpose
ADC Exported Constants

Defines

#define | LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define | LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */

Define Documentation

#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

Definition at line 667 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DMA_GetRegAddr().

#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */

Definition at line 669 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC common - Clock source

Defines
ADC common - Clock source
ADC Exported Constants

Defines

#define | LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U)
#define | LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
#define | LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define | LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

Define Documentation

#define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U)

ADC asynchronous clock without prescaler

Definition at line 681 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 10

Definition at line 686 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )

ADC asynchronous clock with prescaler division by 12

Definition at line 687 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)

ADC asynchronous clock with prescaler division by 128

Definition at line 691 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 16

Definition at line 688 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 2

Definition at line 682 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 256

Definition at line 692 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)

ADC asynchronous clock with prescaler division by 32

Definition at line 689 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )

ADC asynchronous clock with prescaler division by 4

Definition at line 683 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 6

Definition at line 684 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 64

Definition at line 690 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )

ADC asynchronous clock with prescaler division by 8

Definition at line 685 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)

ADC synchronous clock derived from AHB clock without prescaler

Definition at line 678 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )

ADC synchronous clock derived from AHB clock with prescaler division by 2

Definition at line 679 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_CommonStructInit().

#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)

ADC synchronous clock derived from AHB clock with prescaler division by 4

Definition at line 680 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: ADC common - Measurement path to internal channels

Defines
ADC common - Measurement path to internal channels
ADC Exported Constants

Defines

#define | LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
#define | LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)

Define Documentation

#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)

ADC measurement pathes all disabled

Definition at line 705 of file stm32l4xx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)

ADC measurement path to internal channel temperature sensor

Definition at line 707 of file stm32l4xx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)

ADC measurement path to internal channel Vbat

Definition at line 708 of file stm32l4xx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)

ADC measurement path to internal channel VrefInt

Definition at line 706 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define | LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define | LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)
#define | LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )
#define | LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)

Define Documentation

#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)

ADC resolution 10 bits

Definition at line 717 of file stm32l4xx_ll_adc.h.

#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U)

ADC resolution 12 bits

Definition at line 716 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)

ADC resolution 6 bits

Definition at line 719 of file stm32l4xx_ll_adc.h.

#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )

ADC resolution 8 bits

Definition at line 718 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC instance - Data alignment

Defines
ADC instance - Data alignment
ADC Exported Constants

Defines

#define | LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)

Define Documentation

#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)

ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)

Definition at line 728 of file stm32l4xx_ll_adc.h.

#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)

ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)

Definition at line 727 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC instance - Low power mode

Defines
ADC instance - Low power mode
ADC Exported Constants

Defines

#define | LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)

Define Documentation

#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)

ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function LL_ADC_SetLowPowerMode().

Definition at line 737 of file stm32l4xx_ll_adc.h.

#define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U)

No ADC low power mode activated

Definition at line 736 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC instance - Offset number

Defines
ADC instance - Offset number
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
#define | LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
#define | LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
#define | LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET

Define Documentation

#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET

ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 745 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET

ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 746 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET

ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 747 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET

ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 748 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC instance - Offset state

Defines
ADC instance - Offset state
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)

Define Documentation

#define LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000U)

ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4)

Definition at line 756 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)

ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4)

Definition at line 757 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Exported Constants

Defines

#define | LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U)
#define | LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U)
#define | LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U)

Define Documentation

#define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U)

ADC group injected (not available on all STM32 devices)

Definition at line 766 of file stm32l4xx_ll_adc.h.

#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U)

ADC group regular (available on all STM32 devices)

Definition at line 765 of file stm32l4xx_ll_adc.h.

#define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U)

ADC both groups regular and injected

Definition at line 767 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)
#define | LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH)

Define Documentation

#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN0

Definition at line 775 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN1

Definition at line 776 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN10

Definition at line 785 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN11

Definition at line 786 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN12

Definition at line 787 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN13

Definition at line 788 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN14

Definition at line 789 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN15

Definition at line 790 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN16

Definition at line 791 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN17

Definition at line 792 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN18

Definition at line 793 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN2

Definition at line 777 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN3

Definition at line 778 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN4

Definition at line 779 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN5

Definition at line 780 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN6

Definition at line 781 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN7

Definition at line 782 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN8

Definition at line 783 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN9

Definition at line 784 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)

ADC internal channel connected to DAC1 channel 1, channel specific to ADC2

Definition at line 801 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to DAC1 channel 1, channel specific to ADC3

Definition at line 804 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)

ADC internal channel connected to DAC1 channel 2, channel specific to ADC2

Definition at line 802 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to DAC1 channel 2, channel specific to ADC3

Definition at line 805 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3.

Definition at line 795 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3.

Definition at line 796 of file stm32l4xx_ll_adc.h.

#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1.

Definition at line 794 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC group regular - Trigger source

Defines
ADC group regular - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting).

Definition at line 831 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 830 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 818 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 819 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 820 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 816 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 817 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 822 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 821 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 824 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 823 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 826 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 825 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 827 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 828 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 829 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U)

ADC group regular conversion trigger internal: SW start.

Definition at line 815 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_REG_IsTriggerSourceSWStart(), and LL_ADC_REG_StructInit().

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STM32L486xx HAL User Manual: ADC group regular - Trigger edge

Defines
ADC group regular - Trigger edge
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )
#define | LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )

ADC group regular conversion trigger polarity set to falling edge

Definition at line 840 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)

ADC group regular conversion trigger polarity set to rising edge

Definition at line 839 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)

ADC group regular conversion trigger polarity set to both rising and falling edges

Definition at line 841 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: ADC group regular - Continuous mode

Defines
ADC group regular - Continuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)

Define Documentation

#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)

ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically

Definition at line 850 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U)

ADC conversions are performed in single mode: one conversion per trigger

Definition at line 849 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

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STM32L486xx HAL User Manual: ADC group regular - DMA transfer of ADC conversion data

Defines
ADC group regular - DMA transfer of ADC conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)

Define Documentation

#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN)

ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.

Definition at line 859 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U)

ADC conversions are not transferred by DMA

Definition at line 858 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)

ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

Definition at line 860 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC group regular - Overrun behavior on conversion data

Defines
ADC group regular - Overrun behavior on conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)
#define | LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)

Define Documentation

#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)

ADC group regular behavior in case of overrun: data overwritten

Definition at line 869 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

#define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)

ADC group regular behavior in case of overrun: data preserved

Definition at line 868 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: ADC group regular - Sequencer scan length

Defines
ADC group regular - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

Define Documentation

#define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)

ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 877 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 10 ranks in the sequence

Definition at line 886 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 11 ranks in the sequence

Definition at line 887 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 12 ranks in the sequence

Definition at line 888 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )

ADC group regular sequencer enable with 13 ranks in the sequence

Definition at line 889 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 14 ranks in the sequence

Definition at line 890 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 15 ranks in the sequence

Definition at line 891 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 16 ranks in the sequence

Definition at line 892 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)

ADC group regular sequencer enable with 2 ranks in the sequence

Definition at line 878 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )

ADC group regular sequencer enable with 3 ranks in the sequence

Definition at line 879 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 4 ranks in the sequence

Definition at line 880 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )

ADC group regular sequencer enable with 5 ranks in the sequence

Definition at line 881 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 6 ranks in the sequence

Definition at line 882 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 7 ranks in the sequence

Definition at line 883 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 8 ranks in the sequence

Definition at line 884 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )

ADC group regular sequencer enable with 9 ranks in the sequence

Definition at line 885 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: ADC group regular - Sequencer discontinuous mode

Defines
ADC group regular - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

Define Documentation

#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 901 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks

Definition at line 902 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks

Definition at line 903 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks

Definition at line 904 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks

Definition at line 905 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks

Definition at line 906 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks

Definition at line 907 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks

Definition at line 908 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)

ADC group regular sequencer discontinuous mode disable

Definition at line 900 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

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STM32L486xx HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

Define Documentation

#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 1

Definition at line 916 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 10

Definition at line 925 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 11

Definition at line 926 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 12

Definition at line 927 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 13

Definition at line 928 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 14

Definition at line 929 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 15

Definition at line 930 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 16

Definition at line 931 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 2

Definition at line 917 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 3

Definition at line 918 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 4

Definition at line 919 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 5

Definition at line 920 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 6

Definition at line 921 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 7

Definition at line 922 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 8

Definition at line 923 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 9

Definition at line 924 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: ADC group injected - Trigger source

Defines
ADC group injected - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting).

Definition at line 955 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 954 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 942 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 940 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 941 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 944 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 943 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 946 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 947 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 948 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 945 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 949 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 950 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 951 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 952 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 953 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U)

ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting).

Definition at line 939 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_IsTriggerSourceSWStart(), and LL_ADC_INJ_StructInit().

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STM32L486xx HAL User Manual: ADC group injected - Trigger edge

Defines
ADC group injected - Trigger edge
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
#define | LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )

ADC group injected conversion trigger polarity set to falling edge

Definition at line 964 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)

ADC group injected conversion trigger polarity set to rising edge

Definition at line 963 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)

ADC group injected conversion trigger polarity set to both rising and falling edges

Definition at line 965 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: ADC group injected - Automatic trigger mode

Defines
ADC group injected - Automatic trigger mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)

Define Documentation

#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)

ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.

Definition at line 974 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)

ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger.

Definition at line 973 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_StructInit().

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STM32L486xx HAL User Manual: ADC group injected - Context queue mode

Defines
ADC group injected - Context queue mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
#define | LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

Define Documentation

#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */

Definition at line 983 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */

Definition at line 982 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

Definition at line 984 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: ADC group injected - Sequencer scan length

Defines
ADC group injected - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

Define Documentation

#define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)

ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 992 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)

ADC group injected sequencer enable with 2 ranks in the sequence

Definition at line 993 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )

ADC group injected sequencer enable with 3 ranks in the sequence

Definition at line 994 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

ADC group injected sequencer enable with 4 ranks in the sequence

Definition at line 995 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: ADC group injected - Sequencer discontinuous mode

Defines
ADC group injected - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)

Define Documentation

#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)

ADC group injected sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 1004 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)

ADC group injected sequencer discontinuous mode disable

Definition at line 1003 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_StructInit().

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STM32L486xx HAL User Manual: ADC group injected - Sequencer ranks

Defines
ADC group injected - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)

Define Documentation

#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 1

Definition at line 1012 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 2

Definition at line 1013 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 3

Definition at line 1014 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 4

Definition at line 1015 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

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STM32L486xx HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000U)
#define | LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 )
#define | LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)

Define Documentation

#define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 )

Sampling time 12.5 ADC clock cycles

Definition at line 1025 of file stm32l4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )

Sampling time 247.5 ADC clock cycles

Definition at line 1029 of file stm32l4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)

Sampling time 24.5 ADC clock cycles

Definition at line 1026 of file stm32l4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000U)

Sampling time 2.5 ADC clock cycles

Definition at line 1023 of file stm32l4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 )

Sampling time 47.5 ADC clock cycles

Definition at line 1027 of file stm32l4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)

Sampling time 640.5 ADC clock cycles

Definition at line 1030 of file stm32l4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0)

Sampling time 6.5 ADC clock cycles

Definition at line 1024 of file stm32l4xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)

Sampling time 92.5 ADC clock cycles

Definition at line 1028 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: Channel - Single or differential ending

Defines
Channel - Single or differential ending
ADC Exported Constants

Defines

#define | LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
#define | LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
#define | LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)

Define Documentation

#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)

ADC channel ending set to both single ended and differential (literal used only to set calibration factors)

Definition at line 1040 of file stm32l4xx_ll_adc.h.

#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)

ADC channel ending set to differential (literal also used to set calibration mode)

Definition at line 1039 of file stm32l4xx_ll_adc.h.

#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)

ADC channel ending set to single ended (literal also used to set calibration mode)

Definition at line 1038 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: Analog watchdog - Analog watchdog number

Defines
Analog watchdog - Analog watchdog number
ADC Exported Constants

Defines

#define | LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define | LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
#define | LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)

Define Documentation

#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)

ADC analog watchdog number 1

Definition at line 1048 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)

ADC analog watchdog number 2

Definition at line 1049 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)

ADC analog watchdog number 3

Definition at line 1050 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Analog watchdog - Monitored channels

Defines
Analog watchdog - Monitored channels
ADC Exported Constants

Defines

#define | LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

Define Documentation

#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )

ADC analog watchdog monitoring of all channels, converted by group injected only

Definition at line 1060 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )

ADC analog watchdog monitoring of all channels, converted by group regular only

Definition at line 1059 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )

ADC analog watchdog monitoring of all channels, converted by either group regular or injected

Definition at line 1061 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only

Definition at line 1137 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only

Definition at line 1136 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected

Definition at line 1138 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only

Definition at line 1144 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only

Definition at line 1143 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected

Definition at line 1145 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only

Definition at line 1140 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only

Definition at line 1139 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected

Definition at line 1141 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only

Definition at line 1147 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only

Definition at line 1146 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected

Definition at line 1148 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only

Definition at line 1123 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only

Definition at line 1122 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected

Definition at line 1124 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only

Definition at line 1126 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only

Definition at line 1125 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda

Definition at line 1127 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only

Definition at line 1120 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only

Definition at line 1119 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected

Definition at line 1121 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only

Definition at line 1063 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only

Definition at line 1062 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected

Definition at line 1064 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only

Definition at line 1093 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only

Definition at line 1092 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected

Definition at line 1094 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only

Definition at line 1096 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only

Definition at line 1095 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected

Definition at line 1097 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only

Definition at line 1099 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only

Definition at line 1098 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected

Definition at line 1100 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only

Definition at line 1102 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only

Definition at line 1101 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected

Definition at line 1103 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only

Definition at line 1105 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only

Definition at line 1104 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected

Definition at line 1106 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only

Definition at line 1108 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only

Definition at line 1107 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected

Definition at line 1109 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only

Definition at line 1111 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only

Definition at line 1110 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected

Definition at line 1112 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only

Definition at line 1114 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only

Definition at line 1113 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected

Definition at line 1115 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only

Definition at line 1117 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only

Definition at line 1116 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected

Definition at line 1118 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only

Definition at line 1066 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only

Definition at line 1065 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected

Definition at line 1067 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only

Definition at line 1069 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only

Definition at line 1068 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected

Definition at line 1070 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only

Definition at line 1072 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only

Definition at line 1071 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected

Definition at line 1073 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only

Definition at line 1075 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only

Definition at line 1074 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected

Definition at line 1076 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only

Definition at line 1078 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only

Definition at line 1077 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected

Definition at line 1079 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only

Definition at line 1081 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only

Definition at line 1080 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected

Definition at line 1082 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only

Definition at line 1084 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only

Definition at line 1083 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected

Definition at line 1085 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only

Definition at line 1087 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only

Definition at line 1086 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected

Definition at line 1088 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only

Definition at line 1090 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only

Definition at line 1089 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected

Definition at line 1091 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U)

ADC analog watchdog monitoring disabled

Definition at line 1058 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Analog watchdog - Thresholds

Defines
Analog watchdog - Thresholds
ADC Exported Constants

Defines

#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 )
#define | LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1)
#define | LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1)

Define Documentation

#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 )

ADC analog watchdog threshold high

Definition at line 1158 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1)

ADC analog watchdog threshold low

Definition at line 1159 of file stm32l4xx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1)

ADC analog watchdog both thresholds high and low concatenated into the same data

Definition at line 1160 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Oversampling - Oversampling scope

Defines
Oversampling - Oversampling scope
ADC Exported Constants

Defines

#define | LL_ADC_OVS_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )
#define | LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)

Define Documentation

#define LL_ADC_OVS_DISABLE ((uint32_t)0x00000000U)

ADC oversampling disabled.

Definition at line 1168 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)

ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset).

Definition at line 1172 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )

ADC oversampling on conversions of ADC group injected.

Definition at line 1171 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards.

Definition at line 1169 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset).

Definition at line 1170 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Oversampling - Discontinuous mode

Defines
Oversampling - Discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_OVS_REG_CONT ((uint32_t)0x00000000U)
#define | LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)

Define Documentation

#define LL_ADC_OVS_REG_CONT ((uint32_t)0x00000000U)

ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger)

Definition at line 1180 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)

ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger)

Definition at line 1181 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Oversampling - Ratio

Defines
Oversampling - Ratio
ADC Exported Constants

Defines

#define | LL_ADC_OVS_RATIO_2 ((uint32_t)0x00000000U)
#define | LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )
#define | LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)

Define Documentation

#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 )

ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1195 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1192 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_2 ((uint32_t)0x00000000U)

ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1189 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1196 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )

ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1193 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1190 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1194 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )

ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1191 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Oversampling - Data shift

Defines
Oversampling - Data shift
ADC Exported Constants

Defines

#define | LL_ADC_OVS_SHIFT_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
#define | LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )

Define Documentation

#define LL_ADC_OVS_SHIFT_NONE ((uint32_t)0x00000000U)

ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data)

Definition at line 1204 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)

ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data)

Definition at line 1205 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )

ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data)

Definition at line 1206 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data)

Definition at line 1207 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )

ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data)

Definition at line 1208 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data)

Definition at line 1209 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )

ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data)

Definition at line 1210 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data)

Definition at line 1211 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )

ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data)

Definition at line 1212 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: Multimode - Mode

Defines
Multimode - Mode
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000U)
#define | LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 )
#define | LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 )
#define | LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)

Define Documentation

#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)

ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start)

Definition at line 1225 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)

ADC dual mode enabled: group injected simultaneous

Definition at line 1224 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous

Definition at line 1228 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular interleaved

Definition at line 1223 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 )

ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger

Definition at line 1227 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0)

ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous

Definition at line 1226 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 )

ADC dual mode enabled: group regular simultaneous

Definition at line 1222 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000U)

ADC dual mode disabled (ADC independent mode)

Definition at line 1221 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Multimode - DMA transfer

Defines
Multimode - DMA transfer
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000U)
#define | LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 )
#define | LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)
#define | LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 )
#define | LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)

Define Documentation

#define LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000U)

ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings

Definition at line 1236 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_CommonStructInit().

#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 )

ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits

Definition at line 1237 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits

Definition at line 1238 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 )

ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits

Definition at line 1239 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits

Definition at line 1240 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Multimode - Delay between two sampling phases

Defines
Multimode - Delay between two sampling phases
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000U)
#define | LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

Define Documentation

#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 10 ADC clock cycles

Definition at line 1257 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 )

ADC multimode delay between two sampling phases: 11 ADC clock cycles

Definition at line 1258 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 12 ADC clock cycles

Definition at line 1259 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000U)

ADC multimode delay between two sampling phases: 1 ADC clock cycle

Definition at line 1248 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_CommonStructInit().

#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 2 ADC clock cycles

Definition at line 1249 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 )

ADC multimode delay between two sampling phases: 3 ADC clock cycles

Definition at line 1250 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 4 ADC clock cycles

Definition at line 1251 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 )

ADC multimode delay between two sampling phases: 5 ADC clock cycles

Definition at line 1252 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 6 ADC clock cycles

Definition at line 1253 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 )

ADC multimode delay between two sampling phases: 7 ADC clock cycles

Definition at line 1254 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)

ADC multimode delay between two sampling phases: 8 ADC clock cycles

Definition at line 1255 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 )

ADC multimode delay between two sampling phases: 9 ADC clock cycles

Definition at line 1256 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Multimode - ADC master or slave

Defines
Multimode - ADC master or slave
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)
#define | LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )
#define | LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)

Define Documentation

#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)

In multimode, selection among several ADC instances: ADC master

Definition at line 1267 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)

In multimode, selection among several ADC instances: both ADC master and ADC slave

Definition at line 1269 of file stm32l4xx_ll_adc.h.

#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )

In multimode, selection among several ADC instances: ADC slave

Definition at line 1268 of file stm32l4xx_ll_adc.h.

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STM32L486xx HAL User Manual: ADC literals legacy naming

Defines
ADC literals legacy naming
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
#define | LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
#define | LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
#define | LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
#define | LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define | LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define | LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define | LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define | LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define | LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define | LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define | LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define | LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)

Definition at line 1288 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)

Definition at line 1289 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)

Definition at line 1290 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)

Definition at line 1291 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)

Definition at line 1292 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)

Definition at line 1293 of file stm32l4xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE)

Definition at line 1287 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)

Definition at line 1296 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)

Definition at line 1297 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)

Definition at line 1298 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)

Definition at line 1299 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)

Definition at line 1300 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)

Definition at line 1301 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)

Definition at line 1302 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)

Definition at line 1303 of file stm32l4xx_ll_adc.h.

#define LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)

Definition at line 1295 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)

Definition at line 1280 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)

Definition at line 1281 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)

Definition at line 1282 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)

Definition at line 1283 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)

Definition at line 1284 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)

Definition at line 1285 of file stm32l4xx_ll_adc.h.

#define LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE)

Definition at line 1279 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Definitions of ADC hardware constraints delays

Defines
Definitions of ADC hardware constraints delays
ADC Exported Constants

Defines

#define | LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U)
#define | LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 12U)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U)
#define | LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U)

Detailed Description

Note:
Only ADC IP HW delays are defined in ADC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U)

Delay required between ADC end of calibration and ADC enable

Definition at line 1361 of file stm32l4xx_ll_adc.h.

#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U)

Delay for ADC stabilization time (ADC voltage regulator start-up time)

Definition at line 1340 of file stm32l4xx_ll_adc.h.

#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U)

Delay for temperature sensor stabilization time

Definition at line 1352 of file stm32l4xx_ll_adc.h.

#define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 12U)

Delay for internal voltage reference stabilization time

Definition at line 1346 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common write and read registers Macros

Defines
Common write and read registers Macros
ADC Exported Macros

Defines

#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.

Define Documentation

#define LL_ADC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1396 of file stm32l4xx_ll_adc.h.

#define LL_ADC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1388 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC helper macro

Defines
ADC helper macro
ADC Exported Macros

Defines

#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.
#define | __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))
Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.
#define | __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC123_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE()
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __LL_ADC_ANALOGWD_CHANNEL_GROUP | ( | __CHANNEL__,
 |  | __GROUP__
 | ) |
Value:
(((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                        \
      :                                                                                                   \
      ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
       ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                    \
         :                                                                                                \
         (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  \
  )

Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.

Note:
To be used with function LL_ADC_SetAnalogWDMonitChannels(). Example: LL_ADC_SetAnalogWDMonitChannels( ADC1, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(1, 2, 3, 4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
__GROUP__ This parameter can be one of the following values:
  • LL_ADC_GROUP_REGULAR
  • LL_ADC_GROUP_INJECTED
  • LL_ADC_GROUP_REGULAR_INJECTED
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (0)(1)
  • LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
  • LL_ADC_AWD_CH_VBAT_REG (0)(4)
  • LL_ADC_AWD_CH_VBAT_INJ (0)(4)
  • LL_ADC_AWD_CH_VBAT_REG_INJ (4)
  • LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
  • LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
  • LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
  • LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
  • LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
  • LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
(0) On STM32L4, parameter available only on analog watchdog number: AWD1.
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. (5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.

Definition at line 1907 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD_12_BITS__
 | ) | ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to get the value of analog watchdog threshold high (on 8 bits): < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION (LL_ADC_RESOLUTION_8B, LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1959 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD__
 | ) | ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_ConfigAnalogWDThresholds() or LL_ADC_SetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to set the value of analog watchdog threshold high (on 8 bits): LL_ADC_SetAnalogWDThresholds (< ADCx param >, __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1937 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW | ( | __AWD_THRESHOLD_TYPE__,
 |  | __AWD_THRESHOLDS__
 | ) | (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)

Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, to get analog watchdog threshold high from the register raw value: __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
Parameters:
__AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
__AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1974 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
  )

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 2121 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_CALC_DATA_VOLTAGE ( ) __LL_ADC_CALC_DATA_TO_VOLTAGE()

Definition at line 2129 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE | ( | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
                                                    (__ADC_RESOLUTION__),          \
                                                    LL_ADC_RESOLUTION_12B)         \
                   * (__VREFANALOG_VOLTAGE__))                                     \
                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
   ) + TEMPSENSOR_CAL1_TEMP                                                        \
  )

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor calibration values stored in system memory for each device during production.
Calculation formula: Temperature = ((TS_ADC_DATA - TS_CAL1) * (TS_CAL2_TEMP - TS_CAL1_TEMP)) / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC Avg_Slope = (TS_CAL2 - TS_CAL1) / (TS_CAL2_TEMP - TS_CAL1_TEMP) TS_CAL1 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL1 (calibrated in factory) TS_CAL2 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL2 (calibrated in factory) Caution: Calculation relevancy under reserve that calibration parameters are correct (address and data). To calculate temperature using temperature sensor datasheet typical values (generic values less, therefore less accurate than calibrated values), use helper macro __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
On this STM32 serie, calibration data of temperature sensor corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of temperature sensor. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 2209 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((( (                                                                        \
       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
                 * 1000)                                                       \
       -                                                                       \
       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
                 * 1000)                                                       \
      )                                                                        \
    ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
   ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
  )

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
ADC measurement data must correspond to a resolution of 12bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 12 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32L4, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 2267 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_CALC_VREFANALOG_VOLTAGE | ( | __VREFINT_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \
                                       (__ADC_RESOLUTION__),                   \
                                       LL_ADC_RESOLUTION_12B)                  \
  )

Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.

Note:
Computation is using VrefInt calibration value stored in system memory for each device during production.
This voltage depends on user board environment: voltage level connected to pin Vref+. On devices with small package, the pin Vref+ is not present and internally bonded to pin Vdda.
On this STM32 serie, calibration data of internal voltage reference VrefInt corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of internal voltage reference VrefInt. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFINT_ADC_DATA__,: ADC conversion data (resolution 12 bits) of internal voltage reference VrefInt (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Analog reference voltage (unit: mV)

Definition at line 2156 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF | ( | __CALIB_FACTOR_SINGLE_ENDED__,
 |  | __CALIB_FACTOR_DIFFERENTIAL__
 | ) | (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))

Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.

Note:
To be used with function LL_ADC_SetCalibrationFactor(). Example, to set calibration factors single ended to 0x55 and differential ended to 0x2A: LL_ADC_SetCalibrationFactor( ADC1, __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
Parameters:
__CALIB_FACTOR_SINGLE_ENDED__ | Value between Min_Data=0x00 and Max_Data=0x7F
__CALIB_FACTOR_DIFFERENTIAL__ | Value between Min_Data=0x00 and Max_Data=0x7F
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 1990 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18

Definition at line 1662 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ )
Value:
((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U)                                  \
    ? (                                                                                    \
       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
      )                                                                                    \
      :                                                                                    \
      (                                                                                    \
       POSITION_VAL((__CHANNEL__))                                                         \
      )                                                                                    \
  )

Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.

Note:
Example: __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 1454 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_COMMON_INSTANCE ( __ADCx__ ) (ADC123_COMMON)

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 2022 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DMA_GetRegAddr().

#define __LL_ADC_CONVERT_DATA_RESOLUTION | ( | __DATA__,
 |  | __ADC_RESOLUTION_CURRENT__,
 |  | __ADC_RESOLUTION_TARGET__
 | ) |
Value:
(((__DATA__)                                                                 \
    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))    \
   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))       \
  )

Helper macro to convert the ADC conversion data from a resolution to another resolution.

Parameters:
__DATA__ ADC conversion data to be converted
__ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__ADC_RESOLUTION_TARGET__ Resolution of the data after conversion This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data to the requested resolution

Definition at line 2097 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ )
Value:
(((__DECIMAL_NB__) <= 9U)                                                                                     \
    ? (                                                                                                         \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \
       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                       |        \
       (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \
      )                                                                                                         \
      :                                                                                                         \
      (                                                                                                         \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \
       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                              | \
       (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
      )                                                                                                         \
  )

Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.

Note:
Example: __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "LL_ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__,: Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(1, 2, 3, 4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 1514 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 2076 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

Definition at line 1587 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__ADC_INSTANCE__) == ADC1)                                                \
    ? (                                                                        \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                  \
      )                                                                        \
      :                                                                        \
      ((__ADC_INSTANCE__) == ADC2)                                             \
      ? (                                                                      \
         ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                     \
         ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                     \
         ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                        \
        )                                                                      \
        :                                                                      \
        ((__ADC_INSTANCE__) == ADC3)                                           \
        ? (                                                                    \
           ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                   \
           ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                   \
           ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                   \
           ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) ||                   \
           ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3)                      \
          )                                                                    \
          :                                                                    \
          (0U)                                                                 \
  )

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 1700 of file stm32l4xx_ll_adc.h.

#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ )
Value:
(LL_ADC_IsEnabled(ADC1) |                                                    \
   LL_ADC_IsEnabled(ADC2) |                                                    \
   LL_ADC_IsEnabled(ADC3)  )

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" if all ADC instances sharing the same ADC common instance are disabled. Value "1" if at least one ADC instance sharing the same ADC common instance is enabled.

Definition at line 2050 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit().

#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE | ( | __ADC_MULTI_MASTER_SLAVE__,
 |  | __ADC_MULTI_CONV_DATA__
 | ) | (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)

Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.

Note:
This macro is intended to be used when multimode transfer by DMA is enabled: refer to function LL_ADC_SetMultiDMATransfer(). In this case the transferred data need to processed with this macro to separate the conversion data of ADC master and ADC slave.
Parameters:
__ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
  • LL_ADC_MULTI_MASTER
  • LL_ADC_MULTI_SLAVE
__ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 2007 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC DMA management

Functions
ADC DMA management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Note:
These ADC registers are data registers: when ADC conversion data is available in ADC data registers, ADC generates a DMA transfer request.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), (uint32_t)&< array or variable >, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
For devices with several ADC: in multimode, some devices use a different data register outside of ADC instance scope (common data register). This macro manages this register difference, only ADC instance has to be set as parameter.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_DMA_GetRegAddr
CDR RDATA_MST LL_ADC_DMA_GetRegAddr
CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
Parameters:
ADCx ADC instance
Register This parameter can be one of the following values:
  • LL_ADC_DMA_REG_REGULAR_DATA
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
(1) Available on devices with several ADC instances.
Return values:
ADC register address

Definition at line 2337 of file stm32l4xx_ll_adc.h.

References __LL_ADC_COMMON_INSTANCE, and LL_ADC_DMA_REG_REGULAR_DATA.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of ADC hierarchical scope: common to several ADC instances

Functions
Configuration of ADC hierarchical scope: common to several ADC instances
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCommonClock ( ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: Clock source and prescaler.

Reference Manual to LL API cross reference:
CCR CKMODE LL_ADC_GetCommonClock
CCR PRESC LL_ADC_GetCommonClock
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV1
  • LL_ADC_CLOCK_ASYNC_DIV2
  • LL_ADC_CLOCK_ASYNC_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV6
  • LL_ADC_CLOCK_ASYNC_DIV8
  • LL_ADC_CLOCK_ASYNC_DIV10
  • LL_ADC_CLOCK_ASYNC_DIV12
  • LL_ADC_CLOCK_ASYNC_DIV16
  • LL_ADC_CLOCK_ASYNC_DIV32
  • LL_ADC_CLOCK_ASYNC_DIV64
  • LL_ADC_CLOCK_ASYNC_DIV128
  • LL_ADC_CLOCK_ASYNC_DIV256

Definition at line 2432 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh ( ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_GetCommonPathInternalCh
CCR TSEN LL_ADC_GetCommonPathInternalCh
CCR VBATEN LL_ADC_GetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT

Definition at line 2494 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetCommonClock | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | CommonClock
 | ) |  |

Set parameter common to several ADC: Clock source and prescaler.

Note:
On this STM32 serie, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual.
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR CKMODE LL_ADC_SetCommonClock
CCR PRESC LL_ADC_SetCommonClock
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
CommonClock This parameter can be one of the following values:
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV1
  • LL_ADC_CLOCK_ASYNC_DIV2
  • LL_ADC_CLOCK_ASYNC_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV6
  • LL_ADC_CLOCK_ASYNC_DIV8
  • LL_ADC_CLOCK_ASYNC_DIV10
  • LL_ADC_CLOCK_ASYNC_DIV12
  • LL_ADC_CLOCK_ASYNC_DIV16
  • LL_ADC_CLOCK_ASYNC_DIV32
  • LL_ADC_CLOCK_ASYNC_DIV64
  • LL_ADC_CLOCK_ASYNC_DIV128
  • LL_ADC_CLOCK_ASYNC_DIV256
Return values:
None

Definition at line 2404 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_CommonInit().

__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Stabilization time of measurement path to internal channel: After enabling internal paths, before starting ADC conversion, a delay is required for internal voltage reference and temperature sensor stabilization time. Refer to device datasheet. Refer to literal LL_ADC_DELAY_VREFINT_STAB_US. Refer to literal LL_ADC_DELAY_TEMPSENSOR_STAB_US.
ADC internal channel sampling time constraint: For ADC conversion of internal channels, a sampling time minimum value is required. Refer to device datasheet.
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_SetCommonPathInternalCh
CCR TSEN LL_ADC_SetCommonPathInternalCh
CCR VBATEN LL_ADC_SetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT
Return values:
None

Definition at line 2472 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of ADC hierarchical scope: ADC instance

Functions
Configuration of ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void | LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution.
__STATIC_INLINE uint32_t | LL_ADC_GetResolution (ADC_TypeDef *ADCx)
Get ADC resolution.
__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
__STATIC_INLINE uint32_t | LL_ADC_GetLowPowerMode (ADC_TypeDef *ADCx)
Get ADC low power mode:
__STATIC_INLINE void | LL_ADC_SetOffset (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
Set ADC selected offset number 1, 2, 3 or 4.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetChannel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetLevel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void | LL_ADC_SetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
Set for the ADC selected offset number 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: offset state disabled or enabled.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff
 | ) |  |

Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).

Note:
Calibration factors are set by hardware after performing a calibration run using function LL_ADC_StartCalibration().
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes
Reference Manual to LL API cross reference:
CALFACT CALFACT_S LL_ADC_GetCalibrationFactor
CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
Parameters:
ADCx ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
Value between Min_Data=0x00 and Max_Data=0x7F

Definition at line 2561 of file stm32l4xx_ll_adc.h.

References ADC_SINGLEDIFF_CALIB_FACTOR_MASK.

__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment ( ADC_TypeDef * ADCx )

Get ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
Reference Manual to LL API cross reference:
CFGR ALIGN LL_ADC_GetDataAlignment
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT

Definition at line 2639 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode ( ADC_TypeDef * ADCx )

Get ADC low power mode:

Note:
Description of ADC low power modes:
  • ADC low power mode "auto wait": Dynamic low power mode, ADC conversions occurrences are limited to the minimum necessary in order to reduce power consumption. New ADC conversion starts only when the previous unitary conversion data (for ADC group regular) or previous sequence conversions data (for ADC group injected) has been retrieved by user software. In the meantime, ADC remains idle: does not performs any other conversion. This mode allows to automatically adapt the ADC conversions triggers to the speed of the software that reads the data. Moreover, this avoids risk of overrun for low frequency applications. How to use this low power mode:
    • Do not use with interruption or DMA since these modes have to clear immediately the EOC flag to free the IRQ vector sequencer.
    • Do use with polling: 1. Start conversion, 2. Later on, when conversion data is needed: poll for end of conversion to ensure that conversion is completed and retrieve ADC conversion data. This will trig another ADC conversion start.
  • ADC low power mode "auto power-off" (feature available on this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): the ADC automatically powers-off after a conversion and automatically wakes up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with low power mode "auto wait".
With ADC low power mode "auto wait", the ADC conversion data read is corresponding to previous ADC conversion start, independently of delay during which ADC was idle. Therefore, the ADC conversion data may be outdated: does not correspond to the current voltage level on the selected ADC channel.
Reference Manual to LL API cross reference:
CFGR AUTDLY LL_ADC_GetLowPowerMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_LP_MODE_NONE
  • LL_ADC_LP_AUTOWAIT

Definition at line 2740 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
On STM32L4, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
Reference Manual to LL API cross reference:
OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel
OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel
OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel
OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(1, 2, 3, 4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 2904 of file stm32l4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).

Note:
Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
Reference Manual to LL API cross reference:
OFR1 OFFSET1 LL_ADC_GetOffsetLevel
OFR2 OFFSET2 LL_ADC_GetOffsetLevel
OFR3 OFFSET3 LL_ADC_GetOffsetLevel
OFR4 OFFSET4 LL_ADC_GetOffsetLevel
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 2930 of file stm32l4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetState | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset number 1, 2, 3 or 4: offset state disabled or enabled.

Reference Manual to LL API cross reference:
OFR1 OFFSET1_EN LL_ADC_GetOffsetState
OFR2 OFFSET2_EN LL_ADC_GetOffsetState
OFR3 OFFSET3_EN LL_ADC_GetOffsetState
OFR4 OFFSET4_EN LL_ADC_GetOffsetState
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_OFFSET_DISABLE
  • LL_ADC_OFFSET_ENABLE

Definition at line 2990 of file stm32l4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE uint32_t LL_ADC_GetResolution ( ADC_TypeDef * ADCx )

Get ADC resolution.

Refer to reference manual for alignments formats dependencies to ADC resolutions.

Reference Manual to LL API cross reference:
CFGR RES LL_ADC_GetResolution
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B

Definition at line 2604 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetCalibrationFactor | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).

Note:
This function is intended to set calibration parameters without having to perform a new calibration using LL_ADC_StartCalibration().
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes (calibration factor must be specified for each of these differential modes, if used afterwards and if the application requires their calibration).
In case of setting calibration factors of both modes single ended and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): both calibration factors must be concatenated. To perform this processing, use helper macro __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled, without calibration on going, without conversion on going on group regular.
Reference Manual to LL API cross reference:
CALFACT CALFACT_S LL_ADC_SetCalibrationFactor
CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
Parameters:
ADCx | ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED
CalibrationFactor | Value between Min_Data=0x00 and Max_Data=0x7F
Return values:
None

Definition at line 2538 of file stm32l4xx_ll_adc.h.

References ADC_SINGLEDIFF_CALIB_FACTOR_MASK.

__STATIC_INLINE void LL_ADC_SetDataAlignment | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DataAlignment
 | ) |  |

Set ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR ALIGN LL_ADC_SetDataAlignment
Parameters:
ADCx ADC instance
DataAlignment This parameter can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT
Return values:
None

Definition at line 2624 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetLowPowerMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | LowPowerMode
 | ) |  |

Set ADC low power mode.

Note:
Description of ADC low power modes:
  • ADC low power mode "auto wait": Dynamic low power mode, ADC conversions occurrences are limited to the minimum necessary in order to reduce power consumption. New ADC conversion starts only when the previous unitary conversion data (for ADC group regular) or previous sequence conversions data (for ADC group injected) has been retrieved by user software. In the meantime, ADC remains idle: does not performs any other conversion. This mode allows to automatically adapt the ADC conversions triggers to the speed of the software that reads the data. Moreover, this avoids risk of overrun for low frequency applications. How to use this low power mode:
    • Do not use with interruption or DMA since these modes have to clear immediately the EOC flag to free the IRQ vector sequencer.
    • Do use with polling: 1. Start conversion, 2. Later on, when conversion data is needed: poll for end of conversion to ensure that conversion is completed and retrieve ADC conversion data. This will trig another ADC conversion start.
  • ADC low power mode "auto power-off" (feature available on this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): the ADC automatically powers-off after a conversion and automatically wakes up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with low power mode "auto wait".
With ADC low power mode "auto wait", the ADC conversion data read is corresponding to previous ADC conversion start, independently of delay during which ADC was idle. Therefore, the ADC conversion data may be outdated: does not correspond to the current voltage level on the selected ADC channel.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AUTDLY LL_ADC_SetLowPowerMode
Parameters:
ADCx ADC instance
LowPowerMode This parameter can be one of the following values:
  • LL_ADC_LP_MODE_NONE
  • LL_ADC_LP_AUTOWAIT
Return values:
None

Definition at line 2692 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | Channel,
 |  | uint32_t | OffsetLevel
 | ) |  |

Set ADC selected offset number 1, 2, 3 or 4.

Note:
This function set the 2 items of offset configuration:
  • ADC channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
  • Offset level (offset to be subtracted from the raw converted data).
Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
This function enables the offset, by default. It can be forced to disable state using function LL_ADC_SetOffsetState().
If a channel is mapped on several offsets numbers, only the offset with the lowest value is considered for the subtraction.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
On STM32L4, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
Reference Manual to LL API cross reference:
OFR1 OFFSET1_CH LL_ADC_SetOffset
OFR1 OFFSET1 LL_ADC_SetOffset
OFR1 OFFSET1_EN LL_ADC_SetOffset
OFR2 OFFSET2_CH LL_ADC_SetOffset
OFR2 OFFSET2 LL_ADC_SetOffset
OFR2 OFFSET2_EN LL_ADC_SetOffset
OFR3 OFFSET3_CH LL_ADC_SetOffset
OFR3 OFFSET3 LL_ADC_SetOffset
OFR3 OFFSET3_EN LL_ADC_SetOffset
OFR4 OFFSET4_CH LL_ADC_SetOffset
OFR4 OFFSET4 LL_ADC_SetOffset
OFR4 OFFSET4_EN LL_ADC_SetOffset
Parameters:
ADCx | ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
OffsetLevel | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 2825 of file stm32l4xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, and ADC_CHANNEL_ID_NUMBER_MASK.

__STATIC_INLINE void LL_ADC_SetOffsetState | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | OffsetState
 | ) |  |

Set for the ADC selected offset number 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.

Note:
This function should be needed only in case of offset to be enabled-disabled dynamically, and should not be needed in other cases: function LL_ADC_SetOffset() automatically enables the offset.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
OFR1 OFFSET1_EN LL_ADC_SetOffsetState
OFR2 OFFSET2_EN LL_ADC_SetOffsetState
OFR3 OFFSET3_EN LL_ADC_SetOffsetState
OFR4 OFFSET4_EN LL_ADC_SetOffsetState
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
OffsetState This parameter can be one of the following values:
  • LL_ADC_OFFSET_DISABLE
  • LL_ADC_OFFSET_ENABLE
Return values:
None

Definition at line 2963 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetResolution | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Resolution
 | ) |  |

Set ADC resolution.

Refer to reference manual for alignments formats dependencies to ADC resolutions.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR RES LL_ADC_SetResolution
Parameters:
ADCx ADC instance
Resolution This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
None

Definition at line 2587 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of ADC hierarchical scope: group regular

Functions
Configuration of ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void | LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetOverrun (ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode ( ADC_TypeDef * ADCx )

Get ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
Reference Manual to LL API cross reference:
CFGR CONT LL_ADC_REG_GetContinuousMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS

Definition at line 3568 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
For devices with several ADC instances: ADC multimode DMA settings are available using function LL_ADC_GetMultiDMATransfer().
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CFGR DMAEN LL_ADC_REG_GetDMATransfer
CFGR DMACFG LL_ADC_REG_GetDMATransfer
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_LIMITED
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED

Definition at line 3643 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun ( ADC_TypeDef * ADCx )

Get ADC group regular behavior in case of overrun: data preserved or overwritten.

Reference Manual to LL API cross reference:
CFGR OVRMOD LL_ADC_REG_GetOverrun
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_OVR_DATA_PRESERVED
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN

Definition at line 3683 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CFGR DISCEN LL_ADC_REG_GetSequencerDiscont
CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS

Definition at line 3314 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

Definition at line 3259 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group regular sequence: channel on the selected scan sequence rank.

Note:
On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
SQR1 SQ1 LL_ADC_REG_GetSequencerRanks
SQR1 SQ2 LL_ADC_REG_GetSequencerRanks
SQR1 SQ3 LL_ADC_REG_GetSequencerRanks
SQR1 SQ4 LL_ADC_REG_GetSequencerRanks
SQR2 SQ5 LL_ADC_REG_GetSequencerRanks
SQR2 SQ6 LL_ADC_REG_GetSequencerRanks
SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
SQR3 SQ10 LL_ADC_REG_GetSequencerRanks
SQR3 SQ11 LL_ADC_REG_GetSequencerRanks
SQR3 SQ12 LL_ADC_REG_GetSequencerRanks
SQR3 SQ13 LL_ADC_REG_GetSequencerRanks
SQR3 SQ14 LL_ADC_REG_GetSequencerRanks
SQR4 SQ15 LL_ADC_REG_GetSequencerRanks
SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(1, 2, 3, 4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 3522 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0, ADC_REG_RANK_ID_SQRX_MASK, and ADC_REG_SQRX_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger polarity.

Note:
Applicable only for trigger source set to external trigger.
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_GetTriggerEdge
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
  • LL_ADC_REG_TRIG_EXT_FALLING
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING

Definition at line 3145 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

Note:
To determine whether group regular trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") use function LL_ADC_REG_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CFGR EXTSEL LL_ADC_REG_GetTriggerSource
CFGR EXTEN LL_ADC_REG_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11

Definition at line 3083 of file stm32l4xx_ll_adc.h.

References ADC_REG_TRIG_EDGE_MASK, ADC_REG_TRIG_EXTEN_BITOFFSET_POS, and ADC_REG_TRIG_SOURCE_MASK.

__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source internal (SW start) or external.

Note:
In case of group regular trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_REG_GetTriggerSource().
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 3110 of file stm32l4xx_ll_adc.h.

References LL_ADC_REG_TRIG_SOFTWARE.

__STATIC_INLINE void LL_ADC_REG_SetContinuousMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Continuous
 | ) |  |

Set ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR CONT LL_ADC_REG_SetContinuousMode
Parameters:
ADCx ADC instance
Continuous This parameter can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS
Return values:
None

Definition at line 3551 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetDMATransfer | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DMATransfer
 | ) |  |

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
For devices with several ADC instances: ADC multimode DMA settings are available using function LL_ADC_SetMultiDMATransfer().
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR DMAEN LL_ADC_REG_SetDMATransfer
CFGR DMACFG LL_ADC_REG_SetDMATransfer
Parameters:
ADCx ADC instance
DMATransfer This parameter can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_LIMITED
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED
Return values:
None

Definition at line 3608 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetOverrun | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Overrun
 | ) |  |

Set ADC group regular behavior in case of overrun: data preserved or overwritten.

Note:
Compatibility with devices without feature overrun: other devices without this feature have a behavior equivalent to data overwritten. The default setting of overrun is data preserved. Therefore, for compatibility with all devices, parameter overrun should be set to data overwritten.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR OVRMOD LL_ADC_REG_SetOverrun
Parameters:
ADCx ADC instance
Overrun This parameter can be one of the following values:
  • LL_ADC_REG_OVR_DATA_PRESERVED
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN
Return values:
None

Definition at line 3669 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
It is not possible to enable both ADC auto-injected mode and ADC group regular sequencer discontinuous mode.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR DISCEN LL_ADC_REG_SetSequencerDiscont
CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS
Return values:
None

Definition at line 3291 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
Return values:
None

Definition at line 3205 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_Init().

__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group regular sequence: channel on the selected scan sequence rank.

Note:
This function performs configuration of:
  • Channels ordering into each rank of scan sequence: whatever channel can be placed into whatever rank.
On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
SQR1 SQ1 LL_ADC_REG_SetSequencerRanks
SQR1 SQ2 LL_ADC_REG_SetSequencerRanks
SQR1 SQ3 LL_ADC_REG_SetSequencerRanks
SQR1 SQ4 LL_ADC_REG_SetSequencerRanks
SQR2 SQ5 LL_ADC_REG_SetSequencerRanks
SQR2 SQ6 LL_ADC_REG_SetSequencerRanks
SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
SQR3 SQ10 LL_ADC_REG_SetSequencerRanks
SQR3 SQ11 LL_ADC_REG_SetSequencerRanks
SQR3 SQ12 LL_ADC_REG_SetSequencerRanks
SQR3 SQ13 LL_ADC_REG_SetSequencerRanks
SQR3 SQ14 LL_ADC_REG_SetSequencerRanks
SQR4 SQ15 LL_ADC_REG_SetSequencerRanks
SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
None

Definition at line 3413 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0, ADC_REG_RANK_ID_SQRX_MASK, and ADC_REG_SQRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Set ADC group regular conversion trigger polarity.

Note:
Applicable only for trigger source set to external trigger.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_SetTriggerEdge
Parameters:
ADCx ADC instance
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
  • LL_ADC_REG_TRIG_EXT_FALLING
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING
Return values:
None

Definition at line 3130 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTriggerEdge().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR EXTSEL LL_ADC_REG_SetTriggerSource
CFGR EXTEN LL_ADC_REG_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11
Return values:
None

Definition at line 3044 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of ADC hierarchical scope: group injected

Functions
Configuration of ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group injected conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetQueueMode (ADC_TypeDef *ADCx, uint32_t QueueMode)
Set ADC group injected contexts queue mode.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetQueueMode (ADC_TypeDef *ADCx)
Get ADC group injected context queue mode.
__STATIC_INLINE void | LL_ADC_INJ_ConfigQueueContext (ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
Set one context on ADC group injected that will be checked in contexts queue.

Function Documentation

__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource,
 |  | uint32_t | ExternalTriggerEdge,
 |  | uint32_t | SequencerNbRanks,
 |  | uint32_t | Rank1_Channel,
 |  | uint32_t | Rank2_Channel,
 |  | uint32_t | Rank3_Channel,
 |  | uint32_t | Rank4_Channel
 | ) |  |

Set one context on ADC group injected that will be checked in contexts queue.

Note:
A context is a setting of group injected sequencer:
  • group injected trigger
  • sequencer length
  • sequencer ranks This function is intended to be used when contexts queue is enabled, because the sequence must be fully configured in one time (functions to set separately injected trigger and sequencer channels cannot be used): Refer to function LL_ADC_INJ_SetQueueMode().
In the contexts queue, only the active context can be read. The parameters of this function can be read using functions:
  • LL_ADC_INJ_GetTriggerSource()
  • LL_ADC_INJ_GetTriggerEdge()
  • LL_ADC_INJ_GetSequencerRanks()
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 serie, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext
JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext
JSQR JL LL_ADC_INJ_ConfigQueueContext
JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING
Note: This parameter is discarded in case of SW start: parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Rank1_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Rank2_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Rank3_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Rank4_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
None

Definition at line 4402 of file stm32l4xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, ADC_INJ_RANK_ID_JSQR_MASK, LL_ADC_INJ_RANK_1, LL_ADC_INJ_RANK_2, LL_ADC_INJ_RANK_3, LL_ADC_INJ_RANK_4, and LL_ADC_INJ_TRIG_SOFTWARE.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode ( ADC_TypeDef * ADCx )

Get ADC group injected context queue mode.

Reference Manual to LL API cross reference:
CFGR JQM LL_ADC_INJ_GetQueueMode
CFGR JQDIS LL_ADC_INJ_GetQueueMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_QUEUE_DISABLE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

Definition at line 4178 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK

Definition at line 3916 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group injected sequencer length and scan direction.

Note:
This function retrieves:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

Definition at line 3883 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(1, 2, 3, 4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 4065 of file stm32l4xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, and ADC_INJ_RANK_ID_JSQR_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger: independent or from ADC group regular.

Reference Manual to LL API cross reference:
CFGR JAUTO LL_ADC_INJ_GetTrigAuto
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

Definition at line 4117 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger polarity.

Applicable only for trigger source set to external trigger.

Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING

Definition at line 3836 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

Note:
To determine whether group injected trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") use function LL_ADC_INJ_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource
JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

Definition at line 3774 of file stm32l4xx_ll_adc.h.

References ADC_INJ_TRIG_EDGE_MASK, ADC_INJ_TRIG_EXTEN_BITOFFSET_POS, and ADC_INJ_TRIG_SOURCE_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source internal (SW start) or external.

Note:
In case of group injected trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_INJ_GetTriggerSource.
Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 3801 of file stm32l4xx_ll_adc.h.

References LL_ADC_INJ_TRIG_SOFTWARE.

__STATIC_INLINE void LL_ADC_INJ_SetQueueMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | QueueMode
 | ) |  |

Set ADC group injected contexts queue mode.

Note:
A context is a setting of group injected sequencer:
  • group injected trigger
  • sequencer length
  • sequencer ranks If contexts queue is disabled:
  • only 1 sequence can be configured and is active perpetually. If contexts queue is enabled:
  • up to 2 contexts can be queued and are checked in and out as a FIFO stack (first-in, first-out).
  • If a new context is set when queues is full, error is triggered by interruption "Injected Queue Overflow".
  • Two behaviors are possible when all contexts have been processed: the contexts queue can maintain the last context active perpetually or can be empty and injected group triggers are disabled.
  • Triggers can be only external (not internal SW start)
  • Caution: The sequence must be fully configured in one time (one write of register JSQR makes a check-in of a new context into the queue). Therefore functions to set separately injected trigger and sequencer channels cannot be used, register JSQR must be set using function LL_ADC_INJ_ConfigQueueContext().
This parameter can be modified only when no conversion is on going on either groups regular or injected.
A modification of the context mode (bit JQDIS) causes the contexts queue to be flushed and the register JSQR is cleared.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR JQM LL_ADC_INJ_SetQueueMode
CFGR JQDIS LL_ADC_INJ_SetQueueMode
Parameters:
ADCx ADC instance
QueueMode This parameter can be one of the following values:
  • LL_ADC_INJ_QUEUE_DISABLE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
Return values:
None

Definition at line 4163 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK
Return values:
None

Definition at line 3901 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group injected sequencer length and scan direction.

Note:
This function performs configuration of:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Return values:
None

Definition at line 3862 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 serie, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
None

Definition at line 3986 of file stm32l4xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, and ADC_INJ_RANK_ID_JSQR_MASK.

__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TrigAuto
 | ) |  |

Set ADC group injected conversion trigger: independent or from ADC group regular.

Note:
This mode can be used to extend number of data registers updated after one ADC conversion trigger and with data permanently kept (not erased by successive conversions of scan of ADC sequencer ranks), up to 5 data registers: 1 data register on ADC group regular, 4 data registers on ADC group injected.
If ADC group injected injected trigger source is set to an external trigger, this feature must be must be set to independent trigger. ADC group injected automatic trigger is compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR JAUTO LL_ADC_INJ_SetTrigAuto
Parameters:
ADCx ADC instance
TrigAuto This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
Return values:
None

Definition at line 4103 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Set ADC group injected conversion trigger polarity.

Applicable only for trigger source set to external trigger.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
Parameters:
ADCx ADC instance
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING
Return values:
None

Definition at line 3821 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_INJ_SetTriggerEdge().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource
JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
Return values:
None

Definition at line 3735 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of ADC hierarchical scope: channels

Functions
Configuration of ADC hierarchical scope: channels
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
Set mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel)
Get mode single-ended or differential input of the selected ADC channel.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
Conversion time is the addition of sampling time and processing time. On this STM32 serie, ADC processing time is:
  • 12.5 ADC clock cycles at ADC resolution 12 bits
  • 10.5 ADC clock cycles at ADC resolution 10 bits
  • 8.5 ADC clock cycles at ADC resolution 8 bits
  • 6.5 ADC clock cycles at ADC resolution 6 bits
Reference Manual to LL API cross reference:
SMPR1 SMP0 LL_ADC_GetChannelSamplingTime
SMPR1 SMP1 LL_ADC_GetChannelSamplingTime
SMPR1 SMP2 LL_ADC_GetChannelSamplingTime
SMPR1 SMP3 LL_ADC_GetChannelSamplingTime
SMPR1 SMP4 LL_ADC_GetChannelSamplingTime
SMPR1 SMP5 LL_ADC_GetChannelSamplingTime
SMPR1 SMP6 LL_ADC_GetChannelSamplingTime
SMPR1 SMP7 LL_ADC_GetChannelSamplingTime
SMPR1 SMP8 LL_ADC_GetChannelSamplingTime
SMPR1 SMP9 LL_ADC_GetChannelSamplingTime
SMPR2 SMP10 LL_ADC_GetChannelSamplingTime
SMPR2 SMP11 LL_ADC_GetChannelSamplingTime
SMPR2 SMP12 LL_ADC_GetChannelSamplingTime
SMPR2 SMP13 LL_ADC_GetChannelSamplingTime
SMPR2 SMP14 LL_ADC_GetChannelSamplingTime
SMPR2 SMP15 LL_ADC_GetChannelSamplingTime
SMPR2 SMP16 LL_ADC_GetChannelSamplingTime
SMPR2 SMP17 LL_ADC_GetChannelSamplingTime
SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Returned value can be one of the following values:
  • LL_ADC_SAMPLINGTIME_2CYCLES_5
  • LL_ADC_SAMPLINGTIME_6CYCLES_5
  • LL_ADC_SAMPLINGTIME_12CYCLES_5
  • LL_ADC_SAMPLINGTIME_24CYCLES_5
  • LL_ADC_SAMPLINGTIME_47CYCLES_5
  • LL_ADC_SAMPLINGTIME_92CYCLES_5
  • LL_ADC_SAMPLINGTIME_247CYCLES_5
  • LL_ADC_SAMPLINGTIME_640CYCLES_5

Definition at line 4630 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, and ADC_CHANNEL_SMPx_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get mode single-ended or differential input of the selected ADC channel.

Note:
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Therefore, to ensure a channel is configured in single-ended mode, the configuration of channel itself and the channel 'i-1' must be read back (to ensure that the selected channel channel has not been configured in differential mode by the previous channel).
Refer to Reference Manual to ensure the selected channel is available in differential mode. For example, internal channels (VrefInt, TempSensor, ...) are not available in differential mode.
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) are internally fixed to single-ended inputs configuration.
One or several values can be selected. In this case, the value returned is null if all channels are in single ended-mode. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be a combination of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
Return values:
0,: channel in single-ended mode, else: channel in differential mode

Definition at line 4737 of file stm32l4xx_ll_adc.h.

References ADC_SINGLEDIFF_CHANNEL_MASK.

__STATIC_INLINE void LL_ADC_SetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SamplingTime
 | ) |  |

Set sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
In case of internal channel (VrefInt, TempSensor, ...) to be converted: sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values (parameters TS_vrefint, TS_temp, ...).
Conversion time is the addition of sampling time and processing time. On this STM32 serie, ADC processing time is:
  • 12.5 ADC clock cycles at ADC resolution 12 bits
  • 10.5 ADC clock cycles at ADC resolution 10 bits
  • 8.5 ADC clock cycles at ADC resolution 8 bits
  • 6.5 ADC clock cycles at ADC resolution 6 bits
In case of ADC conversion of internal channel (VrefInt, temperature sensor, ...), a sampling time minimum value is required. Refer to device datasheet.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
SMPR1 SMP0 LL_ADC_SetChannelSamplingTime
SMPR1 SMP1 LL_ADC_SetChannelSamplingTime
SMPR1 SMP2 LL_ADC_SetChannelSamplingTime
SMPR1 SMP3 LL_ADC_SetChannelSamplingTime
SMPR1 SMP4 LL_ADC_SetChannelSamplingTime
SMPR1 SMP5 LL_ADC_SetChannelSamplingTime
SMPR1 SMP6 LL_ADC_SetChannelSamplingTime
SMPR1 SMP7 LL_ADC_SetChannelSamplingTime
SMPR1 SMP8 LL_ADC_SetChannelSamplingTime
SMPR1 SMP9 LL_ADC_SetChannelSamplingTime
SMPR2 SMP10 LL_ADC_SetChannelSamplingTime
SMPR2 SMP11 LL_ADC_SetChannelSamplingTime
SMPR2 SMP12 LL_ADC_SetChannelSamplingTime
SMPR2 SMP13 LL_ADC_SetChannelSamplingTime
SMPR2 SMP14 LL_ADC_SetChannelSamplingTime
SMPR2 SMP15 LL_ADC_SetChannelSamplingTime
SMPR2 SMP16 LL_ADC_SetChannelSamplingTime
SMPR2 SMP17 LL_ADC_SetChannelSamplingTime
SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
  • LL_ADC_CHANNEL_DAC1CH1 (5)
  • LL_ADC_CHANNEL_DAC1CH2 (5)
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
(5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
(7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
SamplingTime This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_2CYCLES_5
  • LL_ADC_SAMPLINGTIME_6CYCLES_5
  • LL_ADC_SAMPLINGTIME_12CYCLES_5
  • LL_ADC_SAMPLINGTIME_24CYCLES_5
  • LL_ADC_SAMPLINGTIME_47CYCLES_5
  • LL_ADC_SAMPLINGTIME_92CYCLES_5
  • LL_ADC_SAMPLINGTIME_247CYCLES_5
  • LL_ADC_SAMPLINGTIME_640CYCLES_5
Return values:
None

Definition at line 4538 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, and ADC_CHANNEL_SMPx_BITOFFSET_MASK.

__STATIC_INLINE void LL_ADC_SetChannelSingleDiff | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SingleDiff
 | ) |  |

Set mode single-ended or differential input of the selected ADC channel.

Note:
Channel ending is on channel scope: independently of channel mapped on ADC group regular or injected. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
Refer to Reference Manual to ensure the selected channel is available in differential mode. For example, internal channels (VrefInt, TempSensor, ...) are not available in differential mode.
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) are internally fixed to single-ended inputs configuration.
For ADC channels configured in differential mode, both inputs should be biased at (Vref+)/2 +/-200mV. (Vref+ is the analog voltage reference)
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
One or several values can be selected. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
SingleDiff This parameter can be a combination of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
None

Definition at line 4687 of file stm32l4xx_ll_adc.h.

References ADC_SINGLEDIFF_CHANNEL_MASK, and ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of ADC transversal scope: analog watchdog

Functions
Configuration of ADC transversal scope: analog watchdog
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_ConfigAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.

Function Documentation

__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdHighValue,
 |  | uint32_t | AWDThresholdLowValue
 | ) |  |

Set ADC analog watchdog thresholds value of both thresholds high and low.

Note:
If value of only one threshold high or low must be set, use function LL_ADC_SetAnalogWDThresholds().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_ConfigAnalogWDThresholds
TR2 HT2 LL_ADC_ConfigAnalogWDThresholds
TR3 HT3 LL_ADC_ConfigAnalogWDThresholds
TR1 LT1 LL_ADC_ConfigAnalogWDThresholds
TR2 LT2 LL_ADC_ConfigAnalogWDThresholds
TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
Parameters:
ADCx | ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdHighValue | Value between Min_Data=0x000 and Max_Data=0xFFF
AWDThresholdLowValue | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 5127 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_AWD_TRX_REGOFFSET_MASK, and ADC_TR1_HT1_BITOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy
 | ) |  |

Get ADC analog watchdog monitored channel.

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Applicable only when the analog watchdog is set to monitor one channel.
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels
CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels
CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels
CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels
AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels
AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2 (1)
  • LL_ADC_AWD3 (1)
(1) On this AWD number, monitored channel can be retrieved if only 1 channel is programmed (or none or all channels). This function cannot retrieve monitored channel if multiple channels are programmed simultaneously by bitfield.
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
(0) On STM32L4, parameter available only on analog watchdog number: AWD1.

Definition at line 5030 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_AWD_CR12_REGOFFSETGAP_MASK, ADC_AWD_CR12_REGOFFSETGAP_VAL, ADC_AWD_CR23_CHANNEL_MASK, ADC_AWD_CR_ALL_CHANNEL_MASK, ADC_AWD_CRX_REGOFFSET_MASK, ADC_CFGR_AWD1EN_BITOFFSET_POS, ADC_CFGR_AWD1SGL_BITOFFSET_POS, ADC_CFGR_JAWD1EN_BITOFFSET_POS, ADC_CHANNEL_ID_BITFIELD_MASK, and ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdsHighLow
 | ) |  |

Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.

Note:
If raw data with ADC thresholds high and low is retrieved, the data of each threshold high or low can be isolated using helper macro: __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_GetAnalogWDThresholds
TR2 HT2 LL_ADC_GetAnalogWDThresholds
TR3 HT3 LL_ADC_GetAnalogWDThresholds
TR1 LT1 LL_ADC_GetAnalogWDThresholds
TR2 LT2 LL_ADC_GetAnalogWDThresholds
TR3 LT3 LL_ADC_GetAnalogWDThresholds
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 5233 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_AWD_TRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDChannelGroup
 | ) |  |

Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.

Note:
Once monitored channels are selected, analog watchdog is enabled.
In case of need to define a single channel to monitor with analog watchdog from sequencer channel definition, use helper macro __LL_ADC_ANALOGWD_CHANNEL_GROUP().
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels
CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels
CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels
CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels
AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels
AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDChannelGroup This parameter can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (0)(1)
  • LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
  • LL_ADC_AWD_CH_VBAT_REG (0)(4)
  • LL_ADC_AWD_CH_VBAT_INJ (0)(4)
  • LL_ADC_AWD_CH_VBAT_REG_INJ (4)
  • LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
  • LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
  • LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
  • LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
  • LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
  • LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
(0) On STM32L4, parameter available only on analog watchdog number: AWD1.
(1) On STM32L4, parameter available only on ADC instance: ADC1.
(2) On STM32L4, parameter available only on ADC instance: ADC2.
(3) On STM32L4, parameter available only on ADC instance: ADC3.
(4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. (5) On STM32L4, parameter available on devices with only 1 ADC instance.
(6) On STM32L4, parameter available on devices with several ADC instances.
Return values:
None

Definition at line 4894 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_AWD_CR12_REGOFFSETGAP_MASK, ADC_AWD_CR12_REGOFFSETGAP_VAL, ADC_AWD_CR_ALL_CHANNEL_MASK, and ADC_AWD_CRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdsHighLow,
 |  | uint32_t | AWDThresholdValue
 | ) |  |

Set ADC analog watchdog threshold value of threshold high or low.

Note:
If values of both thresholds high or low must be set, use function LL_ADC_ConfigAnalogWDThresholds().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_SetAnalogWDThresholds
TR2 HT2 LL_ADC_SetAnalogWDThresholds
TR3 HT3 LL_ADC_SetAnalogWDThresholds
TR1 LT1 LL_ADC_SetAnalogWDThresholds
TR2 LT2 LL_ADC_SetAnalogWDThresholds
TR3 LT3 LL_ADC_SetAnalogWDThresholds
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
AWDThresholdValue,: Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 5191 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_AWD_TRX_REGOFFSET_MASK.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of ADC transversal scope: oversampling

Functions
Configuration of ADC transversal scope: oversampling
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingScope (ADC_TypeDef *ADCx)
Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE void | LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingDiscont (ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void | LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingRatio (ADC_TypeDef *ADCx)
Get ADC oversampling ratio (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingShift (ADC_TypeDef *ADCx)
Get ADC oversampling shift (impacting both ADC groups regular and injected)

Function Documentation

__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Ratio,
 |  | uint32_t | Shift
 | ) |  |

Set ADC oversampling (impacting both ADC groups regular and injected)

Note:
This function set the 2 items of oversampling configuration:
  • ratio
  • shift
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift
CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
Parameters:
ADCx ADC instance
Ratio This parameter can be one of the following values:
  • LL_ADC_OVS_RATIO_2
  • LL_ADC_OVS_RATIO_4
  • LL_ADC_OVS_RATIO_8
  • LL_ADC_OVS_RATIO_16
  • LL_ADC_OVS_RATIO_32
  • LL_ADC_OVS_RATIO_64
  • LL_ADC_OVS_RATIO_128
  • LL_ADC_OVS_RATIO_256
Shift This parameter can be one of the following values:
  • LL_ADC_OVS_SHIFT_NONE
  • LL_ADC_OVS_SHIFT_RIGHT_1
  • LL_ADC_OVS_SHIFT_RIGHT_2
  • LL_ADC_OVS_SHIFT_RIGHT_3
  • LL_ADC_OVS_SHIFT_RIGHT_4
  • LL_ADC_OVS_SHIFT_RIGHT_5
  • LL_ADC_OVS_SHIFT_RIGHT_6
  • LL_ADC_OVS_SHIFT_RIGHT_7
  • LL_ADC_OVS_SHIFT_RIGHT_8
Return values:
None

Definition at line 5386 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont ( ADC_TypeDef * ADCx )

Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.

Note:
Number of oversampled conversions are done either in:
  • continuous mode (all conversions of oversampling ratio are done from 1 trigger)
  • discontinuous mode (each conversion of oversampling ratio needs a trigger)
Reference Manual to LL API cross reference:
CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_OVS_REG_CONT
  • LL_ADC_OVS_REG_DISCONT

Definition at line 5347 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio ( ADC_TypeDef * ADCx )

Get ADC oversampling ratio (impacting both ADC groups regular and injected)

Reference Manual to LL API cross reference:
CFGR2 OVSR LL_ADC_GetOverSamplingRatio
Parameters:
ADCx ADC instance
Return values:
Ratio This parameter can be one of the following values:
  • LL_ADC_OVS_RATIO_2
  • LL_ADC_OVS_RATIO_4
  • LL_ADC_OVS_RATIO_8
  • LL_ADC_OVS_RATIO_16
  • LL_ADC_OVS_RATIO_32
  • LL_ADC_OVS_RATIO_64
  • LL_ADC_OVS_RATIO_128
  • LL_ADC_OVS_RATIO_256

Definition at line 5406 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope ( ADC_TypeDef * ADCx )

Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).

Note:
If both groups regular and injected are selected, specify behavior of ADC group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is either temporary stopped and continued, or resumed from start (oversampler buffer reset).
Reference Manual to LL API cross reference:
CFGR2 ROVSE LL_ADC_GetOverSamplingScope
CFGR2 JOVSE LL_ADC_GetOverSamplingScope
CFGR2 ROVSM LL_ADC_GetOverSamplingScope
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_OVS_DISABLE
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED
  • LL_ADC_OVS_GRP_REGULAR_RESUMED
  • LL_ADC_OVS_GRP_INJECTED
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED

Definition at line 5301 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift ( ADC_TypeDef * ADCx )

Get ADC oversampling shift (impacting both ADC groups regular and injected)

Reference Manual to LL API cross reference:
CFGR2 OVSS LL_ADC_GetOverSamplingShift
Parameters:
ADCx ADC instance
Return values:
Shift This parameter can be one of the following values:
  • LL_ADC_OVS_SHIFT_NONE
  • LL_ADC_OVS_SHIFT_RIGHT_1
  • LL_ADC_OVS_SHIFT_RIGHT_2
  • LL_ADC_OVS_SHIFT_RIGHT_3
  • LL_ADC_OVS_SHIFT_RIGHT_4
  • LL_ADC_OVS_SHIFT_RIGHT_5
  • LL_ADC_OVS_SHIFT_RIGHT_6
  • LL_ADC_OVS_SHIFT_RIGHT_7
  • LL_ADC_OVS_SHIFT_RIGHT_8

Definition at line 5427 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | OverSamplingDiscont
 | ) |  |

Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.

Note:
Number of oversampled conversions are done either in:
  • continuous mode (all conversions of oversampling ratio are done from 1 trigger)
  • discontinuous mode (each conversion of oversampling ratio needs a trigger)
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
On this STM32 serie, oversampling discontinuous mode (triggered mode) can be used only when oversampling is set on group regular only and in resumed mode.
Reference Manual to LL API cross reference:
CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
Parameters:
ADCx ADC instance
OverSamplingDiscont This parameter can be one of the following values:
  • LL_ADC_OVS_REG_CONT
  • LL_ADC_OVS_REG_DISCONT
Return values:
None

Definition at line 5328 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOverSamplingScope | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | OvsScope
 | ) |  |

Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).

Note:
If both groups regular and injected are selected, specify behavior of ADC group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is either temporary stopped and continued, or resumed from start (oversampler buffer reset).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR2 ROVSE LL_ADC_SetOverSamplingScope
CFGR2 JOVSE LL_ADC_SetOverSamplingScope
CFGR2 ROVSM LL_ADC_SetOverSamplingScope
Parameters:
ADCx ADC instance
OvsScope This parameter can be one of the following values:
  • LL_ADC_OVS_DISABLE
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED
  • LL_ADC_OVS_GRP_REGULAR_RESUMED
  • LL_ADC_OVS_GRP_INJECTED
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED
Return values:
None

Definition at line 5276 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of ADC hierarchical scope: multimode

Functions
Configuration of ADC hierarchical scope: multimode
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetMultimode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t | LL_ADC_GetMultimode (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE void | LL_ADC_SetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE void | LL_ADC_SetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
Set ADC multimode delay between 2 sampling phases.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode delay between 2 sampling phases.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer ( ADC_Common_TypeDef * ADCxy_COMMON )

Get ADC multimode conversion data transfer: no transfer or transfer by DMA.

Note:
If ADC multimode transfer by DMA is not selected: each ADC uses its own DMA channel, with its individual DMA transfer settings. If ADC multimode transfer by DMA is selected: One DMA channel is used for both ADC (DMA of ADC master) Specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
How to retrieve multimode conversion data: Whatever multimode transfer by DMA setting: using function LL_ADC_REG_ReadMultiConversionData32(). If ADC multimode transfer by DMA is selected: conversion data is a raw data with ADC master and slave concatenated. A macro is available to get the conversion data of ADC master or ADC slave: see helper macro __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
Reference Manual to LL API cross reference:
CCR MDMA LL_ADC_GetMultiDMATransfer
CCR DMACFG LL_ADC_GetMultiDMATransfer
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_MULTI_REG_DMA_EACH_ADC
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B

Definition at line 5588 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetMultimode ( ADC_Common_TypeDef * ADCxy_COMMON )

Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

Note:
If multimode configuration: the selected ADC instance is either master or slave depending on hardware. Refer to reference manual.
Reference Manual to LL API cross reference:
CCR DUAL LL_ADC_GetMultimode
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_MULTI_INDEPENDENT
  • LL_ADC_MULTI_DUAL_REG_SIMULT
  • LL_ADC_MULTI_DUAL_REG_INTERL
  • LL_ADC_MULTI_DUAL_INJ_SIMULT
  • LL_ADC_MULTI_DUAL_INJ_ALTERN
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

Definition at line 5491 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay ( ADC_Common_TypeDef * ADCxy_COMMON )

Get ADC multimode delay between 2 sampling phases.

Reference Manual to LL API cross reference:
CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
  • LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
(1) Parameter available only if ADC resolution is 12, 10 or 8 bits.
(2) Parameter available only if ADC resolution is 12 or 10 bits.
(3) Parameter available only if ADC resolution is 12 bits.

Definition at line 5656 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetMultiDMATransfer | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | MultiDMATransfer
 | ) |  |

Set ADC multimode conversion data transfer: no transfer or transfer by DMA.

Note:
If ADC multimode transfer by DMA is not selected: each ADC uses its own DMA channel, with its individual DMA transfer settings. If ADC multimode transfer by DMA is selected: One DMA channel is used for both ADC (DMA of ADC master) Specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
How to retrieve multimode conversion data: Whatever multimode transfer by DMA setting: using function LL_ADC_REG_ReadMultiConversionData32(). If ADC multimode transfer by DMA is selected: conversion data is a raw data with ADC master and slave concatenated. A macro is available to get the conversion data of ADC master or ADC slave: see helper macro __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CCR MDMA LL_ADC_SetMultiDMATransfer
CCR DMACFG LL_ADC_SetMultiDMATransfer
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
MultiDMATransfer This parameter can be one of the following values:
  • LL_ADC_MULTI_REG_DMA_EACH_ADC
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
Return values:
None

Definition at line 5542 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetMultimode | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | Multimode
 | ) |  |

Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

Note:
If multimode configuration: the selected ADC instance is either master or slave depending on hardware. Refer to reference manual.
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR DUAL LL_ADC_SetMultimode
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Multimode This parameter can be one of the following values:
  • LL_ADC_MULTI_INDEPENDENT
  • LL_ADC_MULTI_DUAL_REG_SIMULT
  • LL_ADC_MULTI_DUAL_REG_INTERL
  • LL_ADC_MULTI_DUAL_INJ_SIMULT
  • LL_ADC_MULTI_DUAL_INJ_ALTERN
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
Return values:
None

Definition at line 5467 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | MultiTwoSamplingDelay
 | ) |  |

Set ADC multimode delay between 2 sampling phases.

Note:
The sampling delay range depends on ADC resolution:
  • ADC resolution 12 bits can have maximum delay of 12 cycles.
  • ADC resolution 10 bits can have maximum delay of 10 cycles.
  • ADC resolution 8 bits can have maximum delay of 8 cycles.
  • ADC resolution 6 bits can have maximum delay of 6 cycles.
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
MultiTwoSamplingDelay This parameter can be one of the following values:
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
  • LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
  • LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
(1) Parameter available only if ADC resolution is 12, 10 or 8 bits.
(2) Parameter available only if ADC resolution is 12 or 10 bits.
(3) Parameter available only if ADC resolution is 12 bits.
Return values:
None

Definition at line 5628 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of ADC alternate functions name

Functions
Configuration of ADC alternate functions name
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_SetTrigSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
__STATIC_INLINE void | LL_ADC_INJ_SetTrigSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)

Function Documentation

__STATIC_INLINE void LL_ADC_INJ_SetTrigSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Definition at line 5674 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetTrigSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Definition at line 5670 of file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Operation on ADC hierarchical scope: ADC instance

Functions
Operation on ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableDeepPowerDown (ADC_TypeDef *ADCx)
Put ADC instance in deep power down state.
__STATIC_INLINE void | LL_ADC_DisableDeepPowerDown (ADC_TypeDef *ADCx)
Disable ADC deep power down mode.
__STATIC_INLINE uint32_t | LL_ADC_IsDeepPowerDownEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance deep power down state.
__STATIC_INLINE void | LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
__STATIC_INLINE void | LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t | LL_ADC_IsInternalRegulatorEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t | LL_ADC_IsDisableOngoing (ADC_TypeDef *ADCx)
Get the selected ADC instance disable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.

Function Documentation

__STATIC_INLINE void LL_ADC_Disable ( ADC_TypeDef * ADCx )

Disable the selected ADC instance.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be not disabled. Must be enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CR ADDIS LL_ADC_Disable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5827 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_DisableDeepPowerDown ( ADC_TypeDef * ADCx )

Disable ADC deep power down mode.

Note:
In case of ADC calibration necessary: When ADC is in deep-power-down state, the internal analog calibration is lost. After exiting from deep power down, calibration must be relaunched or calibration factor (preliminarily saved) must be set back into calibration register.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_DisableDeepPowerDown
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5723 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

__STATIC_INLINE void LL_ADC_DisableInternalRegulator ( ADC_TypeDef * ADCx )

Disable ADC internal voltage regulator.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_DisableInternalRegulator
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5775 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

__STATIC_INLINE void LL_ADC_Enable ( ADC_TypeDef * ADCx )

Enable the selected ADC instance.

Note:
On this STM32 serie, after ADC enable, a delay for ADC internal analog stabilization is required before performing a ADC conversion start. Refer to device datasheet, parameter tSTAB.
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled and ADC internal voltage regulator enabled.
Reference Manual to LL API cross reference:
CR ADEN LL_ADC_Enable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5807 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

__STATIC_INLINE void LL_ADC_EnableDeepPowerDown ( ADC_TypeDef * ADCx )

Put ADC instance in deep power down state.

Note:
In case of ADC calibration necessary: When ADC is in deep-power-down state, the internal analog calibration is lost. After exiting from deep power down, calibration must be relaunched or calibration factor (preliminarily saved) must be set back into calibration register.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_EnableDeepPowerDown
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5700 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

__STATIC_INLINE void LL_ADC_EnableInternalRegulator ( ADC_TypeDef * ADCx )

Enable ADC instance internal voltage regulator.

Note:
On this STM32 serie, after ADC internal voltage regulator enable, a delay for ADC internal voltage regulator stabilization is required before performing a ADC calibration or ADC enable. Refer to device datasheet, parameter tADCVREG_STUP. Refer to literal LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_EnableInternalRegulator
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5756 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing ( ADC_TypeDef * ADCx )

Get ADC calibration state.

Reference Manual to LL API cross reference:
CR ADCAL LL_ADC_IsCalibrationOnGoing
Parameters:
ADCx ADC instance
Return values:
0,: calibration complete, 1: calibration in progress.

Definition at line 5901 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance deep power down state.

Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
Parameters:
ADCx ADC instance
Return values:
0,: deep power down is disabled, 1: deep power down is enabled.

Definition at line 5737 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing ( ADC_TypeDef * ADCx )

Get the selected ADC instance disable state.

Reference Manual to LL API cross reference:
CR ADDIS LL_ADC_IsDisableOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no ADC disable command on going.

Definition at line 5857 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_IsEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance enable state.

Note:
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
CR ADEN LL_ADC_IsEnabled
Parameters:
ADCx ADC instance
Return values:
0,: ADC is disabled, 1: ADC is enabled.

Definition at line 5846 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance internal voltage regulator state.

Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
Parameters:
ADCx ADC instance
Return values:
0,: internal regulator is disabled, 1: internal regulator is enabled.

Definition at line 5786 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_StartCalibration | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff
 | ) |  |

Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).

Note:
On this STM32 serie, a minimum number of ADC clock cycles are required between ADC end of calibration and ADC enable. Refer to literal LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes (calibration run must be performed for each of these differential modes, if used afterwards and if the application requires their calibration).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADCAL LL_ADC_StartCalibration
CR ADCALDIF LL_ADC_StartCalibration
Parameters:
ADCx ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
None

Definition at line 5885 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS, and ADC_SINGLEDIFF_CALIB_START_MASK.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Operation on ADC hierarchical scope: group regular

Functions
Operation on ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular conversion state.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData10 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData8 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData6 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadMultiConversionData32 (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group regular conversion state.

Reference Manual to LL API cross reference:
CR ADSTART LL_ADC_REG_IsConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no conversion is on going on ADC group regular.

Definition at line 5967 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group regular command of conversion stop state.

Reference Manual to LL API cross reference:
CR ADSTP LL_ADC_REG_IsStopConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no command of conversion stop is on going on ADC group regular.

Definition at line 5978 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 10 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData10
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 6022 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData12
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 6007 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData32
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 5992 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 6 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData6
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 6052 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 8 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData8
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 6037 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32 | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | ConversionData
 | ) |  |

Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.

Note:
If raw data with ADC master and slave concatenated is retrieved, a macro is available to get the conversion data of ADC master or ADC slave: see helper macro __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). (however this macro is mainly intended for multimode transfer by DMA, because this function can do the same by getting multimode conversion data of ADC master or ADC slave separately).
Reference Manual to LL API cross reference:
CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32
CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
ConversionData This parameter can be one of the following values:
  • LL_ADC_MULTI_MASTER
  • LL_ADC_MULTI_SLAVE
  • LL_ADC_MULTI_MASTER_SLAVE
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 6079 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group regular conversion.

Note:
On this STM32 serie, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group regular, without conversion stop command on going on group regular.
Reference Manual to LL API cross reference:
CR ADSTART LL_ADC_REG_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5931 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

__STATIC_INLINE void LL_ADC_REG_StopConversion ( ADC_TypeDef * ADCx )

Stop ADC group regular conversion.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled with conversion on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR ADSTP LL_ADC_REG_StopConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5951 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by LL_ADC_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Operation on ADC hierarchical scope: group injected

Functions
Operation on ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group injected conversion.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected conversion state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData10 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData8 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData6 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 6 bits.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group injected conversion state.

Reference Manual to LL API cross reference:
CR JADSTART LL_ADC_INJ_IsConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no conversion is on going on ADC group injected.

Definition at line 6149 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group injected command of conversion stop state.

Reference Manual to LL API cross reference:
CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no command of conversion stop is on going on ADC group injected.

Definition at line 6160 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 10 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData10
JDR2 JDATA LL_ADC_INJ_ReadConversionData10
JDR3 JDATA LL_ADC_INJ_ReadConversionData10
JDR4 JDATA LL_ADC_INJ_ReadConversionData10
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 6236 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JDRX_REGOFFSET_MASK.

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData12
JDR2 JDATA LL_ADC_INJ_ReadConversionData12
JDR3 JDATA LL_ADC_INJ_ReadConversionData12
JDR4 JDATA LL_ADC_INJ_ReadConversionData12
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 6209 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JDRX_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData32
JDR2 JDATA LL_ADC_INJ_ReadConversionData32
JDR3 JDATA LL_ADC_INJ_ReadConversionData32
JDR4 JDATA LL_ADC_INJ_ReadConversionData32
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 6182 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JDRX_REGOFFSET_MASK.

__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 6 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData6
JDR2 JDATA LL_ADC_INJ_ReadConversionData6
JDR3 JDATA LL_ADC_INJ_ReadConversionData6
JDR4 JDATA LL_ADC_INJ_ReadConversionData6
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 6290 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JDRX_REGOFFSET_MASK.

__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 8 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData8
JDR2 JDATA LL_ADC_INJ_ReadConversionData8
JDR3 JDATA LL_ADC_INJ_ReadConversionData8
JDR4 JDATA LL_ADC_INJ_ReadConversionData8
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 6263 of file stm32l4xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JDRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_INJ_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group injected conversion.

Note:
On this STM32 serie, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group injected, without conversion stop command on going on group injected.
Reference Manual to LL API cross reference:
CR JADSTART LL_ADC_INJ_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6113 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

__STATIC_INLINE void LL_ADC_INJ_StopConversion ( ADC_TypeDef * ADCx )

Stop ADC group injected conversion.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled with conversion on going on group injected, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR JADSTP LL_ADC_INJ_StopConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6133 of file stm32l4xx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by LL_ADC_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC flag management

Functions
ADC flag management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_ADRDY (ADC_TypeDef *ADCx)
Get flag ADC ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOC (ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_OVR (ADC_TypeDef *ADCx)
Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOSMP (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOC (ADC_TypeDef *ADCx)
Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JQOVF (ADC_TypeDef *ADCx)
Get flag ADC group injected contexts queue overflow.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD2 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD3 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
Clear flag ADC ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOC (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JQOVF (ADC_TypeDef *ADCx)
Clear flag ADC group injected contexts queue overflow.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_ADRDY (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_ADRDY (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOSMP (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOSMP (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JQOVF (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JQOVF (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 1 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode analog watchdog 1 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD2 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD2 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD3 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD3 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC slave.

Function Documentation

__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY ( ADC_TypeDef * ADCx )

Clear flag ADC ready.

Note:
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
ISR ADRDY LL_ADC_ClearFlag_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6440 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY.

__STATIC_INLINE void LL_ADC_ClearFlag_AWD1 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 1.

Reference Manual to LL API cross reference:
ISR AWD1 LL_ADC_ClearFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6528 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE void LL_ADC_ClearFlag_AWD2 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 2.

Reference Manual to LL API cross reference:
ISR AWD2 LL_ADC_ClearFlag_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6539 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD2.

__STATIC_INLINE void LL_ADC_ClearFlag_AWD3 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 3.

Reference Manual to LL API cross reference:
ISR AWD3 LL_ADC_ClearFlag_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6550 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD3.

__STATIC_INLINE void LL_ADC_ClearFlag_EOC ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
ISR EOC LL_ADC_ClearFlag_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6451 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOC.

__STATIC_INLINE void LL_ADC_ClearFlag_EOS ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
ISR EOS LL_ADC_ClearFlag_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6462 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sampling phase.

Reference Manual to LL API cross reference:
ISR EOSMP LL_ADC_ClearFlag_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6484 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP.

__STATIC_INLINE void LL_ADC_ClearFlag_JEOC ( ADC_TypeDef * ADCx )

Clear flag ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
ISR JEOC LL_ADC_ClearFlag_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6495 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JEOC.

__STATIC_INLINE void LL_ADC_ClearFlag_JEOS ( ADC_TypeDef * ADCx )

Clear flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
ISR JEOS LL_ADC_ClearFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6506 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JEOS.

__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF ( ADC_TypeDef * ADCx )

Clear flag ADC group injected contexts queue overflow.

Reference Manual to LL API cross reference:
ISR JQOVF LL_ADC_ClearFlag_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6517 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF.

__STATIC_INLINE void LL_ADC_ClearFlag_OVR ( ADC_TypeDef * ADCx )

Clear flag ADC group regular overrun.

Reference Manual to LL API cross reference:
ISR OVR LL_ADC_ClearFlag_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6473 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY ( ADC_TypeDef * ADCx )

Get flag ADC ready.

Note:
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6316 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 1 flag.

Reference Manual to LL API cross reference:
ISR AWD1 LL_ADC_IsActiveFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6404 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 2.

Reference Manual to LL API cross reference:
ISR AWD2 LL_ADC_IsActiveFlag_AWD2
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6415 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD2.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 3.

Reference Manual to LL API cross reference:
ISR AWD3 LL_ADC_IsActiveFlag_AWD3
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6426 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD3.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
ISR EOC LL_ADC_IsActiveFlag_EOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6327 of file stm32l4xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
ISR EOS LL_ADC_IsActiveFlag_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6338 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of sampling phase.

Reference Manual to LL API cross reference:
ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6360 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC ( ADC_TypeDef * ADCx )

Get flag ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
ISR JEOC LL_ADC_IsActiveFlag_JEOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6371 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JEOC.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS ( ADC_TypeDef * ADCx )

Get flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
ISR JEOS LL_ADC_IsActiveFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6382 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF ( ADC_TypeDef * ADCx )

Get flag ADC group injected contexts queue overflow.

Reference Manual to LL API cross reference:
ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6393 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC ready of the ADC master.

Reference Manual to LL API cross reference:
CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6563 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 1 of the ADC master.

Reference Manual to LL API cross reference:
CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6755 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD1_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 2 of the ADC master.

Reference Manual to LL API cross reference:
CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6779 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD2_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 3 of the ADC master.

Reference Manual to LL API cross reference:
CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6803 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD3_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of unitary conversion of the ADC master.

Reference Manual to LL API cross reference:
CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6587 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOC_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sequence conversions of the ADC master.

Reference Manual to LL API cross reference:
CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6611 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOS_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sampling of the ADC master.

Reference Manual to LL API cross reference:
CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6659 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of unitary conversion of the ADC master.

Reference Manual to LL API cross reference:
CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6683 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JEOC_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of sequence conversions of the ADC master.

Reference Manual to LL API cross reference:
CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6707 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JEOS_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected context queue overflow of the ADC master.

Reference Manual to LL API cross reference:
CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6731 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular overrun of the ADC master.

Reference Manual to LL API cross reference:
CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6635 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_OVR_MST.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR ( ADC_TypeDef * ADCx )

Get flag ADC group regular overrun.

Reference Manual to LL API cross reference:
ISR OVR LL_ADC_IsActiveFlag_OVR
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6349 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC ready of the ADC slave.

Reference Manual to LL API cross reference:
CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6575 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_ADRDY_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode analog watchdog 1 of the ADC slave.

Reference Manual to LL API cross reference:
CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6767 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD1_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 2 of the ADC slave.

Reference Manual to LL API cross reference:
CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6791 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD2_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 3 of the ADC slave.

Reference Manual to LL API cross reference:
CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6815 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_AWD3_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of unitary conversion of the ADC slave.

Reference Manual to LL API cross reference:
CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6599 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOC_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sequence conversions of the ADC slave.

Reference Manual to LL API cross reference:
CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6623 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOS_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sampling of the ADC slave.

Reference Manual to LL API cross reference:
CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6671 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_EOSMP_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of unitary conversion of the ADC slave.

Reference Manual to LL API cross reference:
CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6695 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JEOC_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of sequence conversions of the ADC slave.

Reference Manual to LL API cross reference:
CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6719 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JEOS_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected context queue overflow of the ADC slave.

Reference Manual to LL API cross reference:
CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6743 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_JQOVF_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular overrun of the ADC slave.

Reference Manual to LL API cross reference:
CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 6647 of file stm32l4xx_ll_adc.h.

References LL_ADC_FLAG_OVR_SLV.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC IT management

Functions
ADC IT management
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
Enable ADC ready.
__STATIC_INLINE void | LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun.
__STATIC_INLINE void | LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOC (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JQOVF (ADC_TypeDef *ADCx)
Enable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
Disable interruption ADC ready.
__STATIC_INLINE void | LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JQOVF (ADC_TypeDef *ADCx)
Disable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_ADRDY (ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_OVR (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOSMP (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JQOVF (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD2 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD3 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).

Function Documentation

__STATIC_INLINE void LL_ADC_DisableIT_ADRDY ( ADC_TypeDef * ADCx )

Disable interruption ADC ready.

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_DisableIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6956 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE void LL_ADC_DisableIT_AWD1 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_DisableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7044 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE void LL_ADC_DisableIT_AWD2 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 2.

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_DisableIT_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7055 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_AWD2.

__STATIC_INLINE void LL_ADC_DisableIT_AWD3 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 3.

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_DisableIT_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7066 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_AWD3.

__STATIC_INLINE void LL_ADC_DisableIT_EOC ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_DisableIT_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6967 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE void LL_ADC_DisableIT_EOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_DisableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6978 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE void LL_ADC_DisableIT_EOSMP ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sampling.

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_DisableIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7000 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE void LL_ADC_DisableIT_JEOC ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_DisableIT_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7011 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_JEOC.

__STATIC_INLINE void LL_ADC_DisableIT_JEOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_DisableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7022 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE void LL_ADC_DisableIT_JQOVF ( ADC_TypeDef * ADCx )

Disable interruption ADC group injected context queue overflow.

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_DisableIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 7033 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_JQOVF.

__STATIC_INLINE void LL_ADC_DisableIT_OVR ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular overrun.

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_DisableIT_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6989 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_OVR.

__STATIC_INLINE void LL_ADC_EnableIT_ADRDY ( ADC_TypeDef * ADCx )

Enable ADC ready.

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_EnableIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6835 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE void LL_ADC_EnableIT_AWD1 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6923 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE void LL_ADC_EnableIT_AWD2 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 2.

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_EnableIT_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6934 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_AWD2.

__STATIC_INLINE void LL_ADC_EnableIT_AWD3 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 3.

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_EnableIT_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6945 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_AWD3.

__STATIC_INLINE void LL_ADC_EnableIT_EOC ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_EnableIT_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6846 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE void LL_ADC_EnableIT_EOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_EnableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6857 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE void LL_ADC_EnableIT_EOSMP ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sampling.

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_EnableIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6879 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE void LL_ADC_EnableIT_JEOC ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_EnableIT_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6890 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_JEOC.

__STATIC_INLINE void LL_ADC_EnableIT_JEOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_EnableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6901 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE void LL_ADC_EnableIT_JQOVF ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected context queue overflow.

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_EnableIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6912 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_JQOVF.

__STATIC_INLINE void LL_ADC_EnableIT_OVR ( ADC_TypeDef * ADCx )

Enable ADC group regular interruption overrun.

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_EnableIT_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 6868 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY ( ADC_TypeDef * ADCx )

Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7078 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1 ( ADC_TypeDef * ADCx )

Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_IsEnabledIT_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7174 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2 ( ADC_TypeDef * ADCx )

Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_IsEnabledIT_AWD2
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7186 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_AWD2.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3 ( ADC_TypeDef * ADCx )

Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_IsEnabledIT_AWD3
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7198 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_AWD3.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_IsEnabledIT_EOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7090 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_IsEnabledIT_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7102 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7126 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_IsEnabledIT_JEOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7138 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_JEOC.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_IsEnabledIT_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7150 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7162 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_JQOVF.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_IsEnabledIT_OVR
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 7114 of file stm32l4xx_ll_adc.h.

References LL_ADC_IT_OVR.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_ADC_CommonDeInit ( ADC_Common_TypeDef * ADCxy_COMMON )

De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.

Note:
This function is performing a hard reset, using high level clock source RCC ADC reset. Caution: On this STM32 serie, if several ADC instances are available on the selected device, RCC ADC reset will reset all ADC instances belonging to the common ADC instance. To de-initialize only 1 ADC instance, use function LL_ADC_DeInit().
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are de-initialized
  • ERROR: not applicable

Definition at line 328 of file stm32l4xx_ll_adc.c.

References assert_param, LL_AHB2_GRP1_ForceReset(), LL_AHB2_GRP1_PERIPH_ADC, and LL_AHB2_GRP1_ReleaseReset().

ErrorStatus LL_ADC_CommonInit | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | LL_ADC_CommonInitTypeDef * | ADC_CommonInitStruct
 | ) |  |

Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).

Note:
The setting of ADC common parameters is conditioned to ADC instances state: All ADC instances belonging to the same ADC common instance must be disabled.
Parameters:
ADCxy_COMMON | ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
ADC_CommonInitStruct | Pointer to a LL_ADC_CommonInitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are initialized
  • ERROR: ADC common registers are not initialized

Definition at line 357 of file stm32l4xx_ll_adc.c.

References __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, assert_param, LL_ADC_CommonInitTypeDef::CommonClock, IS_LL_ADC_COMMON_CLOCK, IS_LL_ADC_MULTI_DMA_TRANSFER, IS_LL_ADC_MULTI_MODE, IS_LL_ADC_MULTI_TWOSMP_DELAY, LL_ADC_MULTI_INDEPENDENT, LL_ADC_SetCommonClock(), LL_ADC_CommonInitTypeDef::MultiDMATransfer, LL_ADC_CommonInitTypeDef::Multimode, and LL_ADC_CommonInitTypeDef::MultiTwoSamplingDelay.

void LL_ADC_CommonStructInit ( LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct )

Set each LL_ADC_CommonInitTypeDef field to default value.

Parameters:
ADC_CommonInitStruct Pointer to a LL_ADC_CommonInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 439 of file stm32l4xx_ll_adc.c.

References LL_ADC_CommonInitTypeDef::CommonClock, LL_ADC_CLOCK_SYNC_PCLK_DIV2, LL_ADC_MULTI_INDEPENDENT, LL_ADC_MULTI_REG_DMA_EACH_ADC, LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE, LL_ADC_CommonInitTypeDef::MultiDMATransfer, LL_ADC_CommonInitTypeDef::Multimode, and LL_ADC_CommonInitTypeDef::MultiTwoSamplingDelay.

ErrorStatus LL_ADC_DeInit ( ADC_TypeDef * ADCx )

De-initialize registers of the selected ADC instance to their default reset values.

Note:
To reset all ADC instances quickly (perform a hard reset), use function LL_ADC_CommonDeInit().
If this functions returns error status, it means that ADC instance is in an unknown state. In this case, perform a hard reset using high level clock source RCC ADC reset. Caution: On this STM32 serie, if several ADC instances are available on the selected device, RCC ADC reset will reset all ADC instances belonging to the common ADC instance. Refer to function LL_ADC_CommonDeInit().
Parameters:
ADCx ADC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are de-initialized
  • ERROR: ADC registers are not de-initialized

Definition at line 472 of file stm32l4xx_ll_adc.c.

References ADC_TIMEOUT_DISABLE_CPU_CYCLES, ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES, assert_param, LL_ADC_Disable(), LL_ADC_FLAG_ADRDY, LL_ADC_FLAG_AWD1, LL_ADC_FLAG_AWD2, LL_ADC_FLAG_AWD3, LL_ADC_FLAG_EOC, LL_ADC_FLAG_EOS, LL_ADC_FLAG_EOSMP, LL_ADC_FLAG_JEOC, LL_ADC_FLAG_JEOS, LL_ADC_FLAG_JQOVF, LL_ADC_FLAG_OVR, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_IsStopConversionOngoing(), LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY, LL_ADC_INJ_SetQueueMode(), LL_ADC_INJ_SetTriggerSource(), LL_ADC_INJ_StopConversion(), LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_IsDisableOngoing(), LL_ADC_IsEnabled(), LL_ADC_IT_ADRDY, LL_ADC_IT_AWD1, LL_ADC_IT_AWD2, LL_ADC_IT_AWD3, LL_ADC_IT_EOC, LL_ADC_IT_EOS, LL_ADC_IT_EOSMP, LL_ADC_IT_JEOC, LL_ADC_IT_JEOS, LL_ADC_IT_JQOVF, LL_ADC_IT_OVR, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsStopConversionOngoing(), LL_ADC_REG_SetTriggerSource(), LL_ADC_REG_StopConversion(), and LL_ADC_REG_TRIG_SOFTWARE.

ErrorStatus LL_ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_InitTypeDef * | ADC_InitStruct
 | ) |  |

Initialize some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 families). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, some other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 741 of file stm32l4xx_ll_adc.c.

References assert_param, LL_ADC_InitTypeDef::DataAlignment, IS_LL_ADC_DATA_ALIGN, IS_LL_ADC_LOW_POWER, IS_LL_ADC_RESOLUTION, LL_ADC_IsEnabled(), LL_ADC_InitTypeDef::LowPowerMode, and LL_ADC_InitTypeDef::Resolution.

ErrorStatus LL_ADC_INJ_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_INJ_InitTypeDef * | ADC_INJ_InitStruct
 | ) |  |

Initialize some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_INJ_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_INJ_InitStruct | Pointer to a LL_ADC_INJ_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 961 of file stm32l4xx_ll_adc.c.

References assert_param, IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_INJ_SEQ_SCAN_LENGTH, IS_LL_ADC_INJ_TRIG_AUTO, IS_LL_ADC_INJ_TRIG_SOURCE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

void LL_ADC_INJ_StructInit ( LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct )

Set each LL_ADC_INJ_InitTypeDef field to default value.

Parameters:
ADC_INJ_InitStruct Pointer to a LL_ADC_INJ_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 1032 of file stm32l4xx_ll_adc.c.

References LL_ADC_INJ_SEQ_DISCONT_DISABLE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_INJ_TRIG_INDEPENDENT, LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

ErrorStatus LL_ADC_REG_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_REG_InitTypeDef * | ADC_REG_InitStruct
 | ) |  |

Initialize some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_REG_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 828 of file stm32l4xx_ll_adc.c.

References assert_param, LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, IS_LL_ADC_REG_CONTINUOUS_MODE, IS_LL_ADC_REG_DMA_TRANSFER, IS_LL_ADC_REG_OVR_DATA_BEHAVIOR, IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_REG_SEQ_SCAN_LENGTH, IS_LL_ADC_REG_TRIG_SOURCE, LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_SetSequencerLength(), LL_ADC_REG_InitTypeDef::Overrun, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_REG_StructInit ( LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct )

Set each LL_ADC_REG_InitTypeDef field to default value.

Parameters:
ADC_REG_InitStruct Pointer to a LL_ADC_REG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 915 of file stm32l4xx_ll_adc.c.

References LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, LL_ADC_REG_CONV_SINGLE, LL_ADC_REG_DMA_TRANSFER_NONE, LL_ADC_REG_OVR_DATA_OVERWRITTEN, LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_TRIG_SOFTWARE, LL_ADC_REG_InitTypeDef::Overrun, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_StructInit ( LL_ADC_InitTypeDef * ADC_InitStruct )

Set each LL_ADC_InitTypeDef field to default value.

Parameters:
ADC_InitStruct Pointer to a LL_ADC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 786 of file stm32l4xx_ll_adc.c.

References LL_ADC_InitTypeDef::DataAlignment, LL_ADC_DATA_ALIGN_RIGHT, LL_ADC_LP_MODE_NONE, LL_ADC_RESOLUTION_12B, LL_ADC_InitTypeDef::LowPowerMode, and LL_ADC_InitTypeDef::Resolution.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: BUS

Modules
BUS
STM32L4xx_LL_Driver

Modules

BUS Exported Constants
BUS Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for BUS registers.

Register | Bit | Function
AHB1ENR | CRCEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | DMA1EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | DMA2EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | FLASHEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | TSCEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
AHB1RSTR | CRCRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | DMA1RST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | DMA2RST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | FLASHRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | TSCRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
AHB1SMENR | CRCSMEN | LL_AHB1_GRP1_DisableClockStopSleep
 |  | LL_AHB1_GRP1_EnableClockStopSleep
 | DMA1SMEN | LL_AHB1_GRP1_DisableClockStopSleep
 |  | LL_AHB1_GRP1_EnableClockStopSleep
 | DMA2SMEN | LL_AHB1_GRP1_DisableClockStopSleep
 |  | LL_AHB1_GRP1_EnableClockStopSleep
 | FLASHSMEN | LL_AHB1_GRP1_DisableClockStopSleep
 |  | LL_AHB1_GRP1_EnableClockStopSleep
 | SRAM1SMEN | LL_AHB1_GRP1_DisableClockStopSleep
 |  | LL_AHB1_GRP1_EnableClockStopSleep
 | TSCSMEN | LL_AHB1_GRP1_DisableClockStopSleep
 |  | LL_AHB1_GRP1_EnableClockStopSleep
AHB2ENR | ADCEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | AESEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOAEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOBEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOCEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIODEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOEEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOFEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOGEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOHEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | OTGFSEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | RNGEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
AHB2RSTR | ADCRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | AESRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOARST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOBRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOCRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIODRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOERST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOFRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOGRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOHRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | OTGFSRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | RNGRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
AHB2SMENR | ADCSMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | AESSMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | GPIOASMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | GPIOBSMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | GPIOCSMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | GPIODSMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | GPIOESMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | GPIOFSMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | GPIOGSMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | GPIOHSMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | OTGFSSMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | RNGSMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
 | SRAM2SMEN | LL_AHB2_GRP1_DisableClockStopSleep
 |  | LL_AHB2_GRP1_EnableClockStopSleep
AHB3ENR | FMCEN | LL_AHB3_GRP1_DisableClock
 |  | LL_AHB3_GRP1_EnableClock
 |  | LL_AHB3_GRP1_IsEnabledClock
 | QSPIEN | LL_AHB3_GRP1_DisableClock
 |  | LL_AHB3_GRP1_EnableClock
 |  | LL_AHB3_GRP1_IsEnabledClock
AHB3RSTR | FMCRST | LL_AHB3_GRP1_ForceReset
 |  | LL_AHB3_GRP1_ReleaseReset
 | QSPIRST | LL_AHB3_GRP1_ForceReset
 |  | LL_AHB3_GRP1_ReleaseReset
AHB3SMENR | FMCSMEN | LL_AHB3_GRP1_DisableClockStopSleep
 |  | LL_AHB3_GRP1_EnableClockStopSleep
 | QSPISMEN | LL_AHB3_GRP1_DisableClockStopSleep
 |  | LL_AHB3_GRP1_EnableClockStopSleep
APB1ENR1 | CAN1EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | CRSEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | DAC1EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | I2C1EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | I2C2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | I2C3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | LCDEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | LPTIM1EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | OPAMPEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | PWREN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | RTCAPBEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | SPI2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | SPI3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM4EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM5EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM6EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM7EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | UART4EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | UART5EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | USART2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | USART3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | WWDGEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
APB1ENR2 | LPTIM2EN | LL_APB1_GRP2_DisableClock
 |  | LL_APB1_GRP2_EnableClock
 |  | LL_APB1_GRP2_IsEnabledClock
 | LPUART1EN | LL_APB1_GRP2_DisableClock
 |  | LL_APB1_GRP2_EnableClock
 |  | LL_APB1_GRP2_IsEnabledClock
 | SWPMI1EN | LL_APB1_GRP2_DisableClock
 |  | LL_APB1_GRP2_EnableClock
 |  | LL_APB1_GRP2_IsEnabledClock
APB1RSTR1 | CAN1RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | CRSRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | DAC1RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | I2C1RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | I2C2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | I2C3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | LCDRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | LPTIM1RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | OPAMPRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | PWRRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | SPI2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | SPI3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM4RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM5RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM6RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM7RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | UART4RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | UART5RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | USART2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | USART3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
APB1RSTR2 | LPTIM2RST | LL_APB1_GRP2_ForceReset
 |  | LL_APB1_GRP2_ReleaseReset
 | LPUART1RST | LL_APB1_GRP2_ForceReset
 |  | LL_APB1_GRP2_ReleaseReset
 | SWPMI1RST | LL_APB1_GRP2_ForceReset
 |  | LL_APB1_GRP2_ReleaseReset
APB1SMENR1 | CAN1SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | CRSSMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | DAC1SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | I2C1SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | I2C2SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | I2C3SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | LCDSMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | LPTIM1SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | OPAMPSMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | PWRSMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | RTCAPBSMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | SPI2SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | SPI3SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | TIM2SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | TIM3SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | TIM4SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | TIM5SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | TIM6SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | TIM7SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | UART4SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | UART5SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | USART2SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | USART3SMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
 | WWDGSMEN | LL_APB1_GRP1_DisableClockStopSleep
 |  | LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR2 | LPTIM2SMEN | LL_APB1_GRP2_DisableClockStopSleep
 |  | LL_APB1_GRP2_EnableClockStopSleep
 | LPUART1SMEN | LL_APB1_GRP2_DisableClockStopSleep
 |  | LL_APB1_GRP2_EnableClockStopSleep
 | SWPMI1SMEN | LL_APB1_GRP2_DisableClockStopSleep
 |  | LL_APB1_GRP2_EnableClockStopSleep
APB2ENR | DFSDM1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | FWEN | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SAI1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SAI2EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SDMMC1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SPI1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SYSCFGEN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM15EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM16EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM17EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM8EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | USART1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
APB2RSTR | DFSDM1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SAI1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SAI2RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SDMMC1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SPI1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SYSCFGRST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM15RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM16RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM17RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM8RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | USART1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
APB2SMENR | DFSDM1SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | SAI1SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | SAI2SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | SDMMC1SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | SPI1SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | SYSCFGSMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | TIM15SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | TIM16SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | TIM17SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | TIM1SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | TIM8SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
 | USART1SMEN | LL_APB2_GRP1_DisableClockStopSleep
 |  | LL_APB2_GRP1_EnableClockStopSleep
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB1 GRP1 PERIPH

Defines
AHB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
#define | LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN

Define Documentation

#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 92 of file stm32l4xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN

Definition at line 96 of file stm32l4xx_ll_bus.h.

Referenced by LL_CRC_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN

Definition at line 93 of file stm32l4xx_ll_bus.h.

Referenced by LL_DMA_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN

Definition at line 94 of file stm32l4xx_ll_bus.h.

Referenced by LL_DMA_DeInit().

#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN

Definition at line 95 of file stm32l4xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN

Definition at line 98 of file stm32l4xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN

Definition at line 97 of file stm32l4xx_ll_bus.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB2 GRP1 PERIPH

Defines
AHB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
#define | LL_AHB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
#define | LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
#define | LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
#define | LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
#define | LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
#define | LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
#define | LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
#define | LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
#define | LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
#define | LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
#define | LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
#define | LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN

Define Documentation

#define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN

Definition at line 127 of file stm32l4xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit().

#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN

Definition at line 129 of file stm32l4xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 107 of file stm32l4xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN

Definition at line 108 of file stm32l4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN

Definition at line 109 of file stm32l4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN

Definition at line 110 of file stm32l4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN

Definition at line 112 of file stm32l4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN

Definition at line 115 of file stm32l4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN

Definition at line 118 of file stm32l4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN

Definition at line 121 of file stm32l4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN

Definition at line 123 of file stm32l4xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN

Definition at line 125 of file stm32l4xx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN

Definition at line 131 of file stm32l4xx_ll_bus.h.

Referenced by LL_RNG_DeInit().

#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN

Definition at line 106 of file stm32l4xx_ll_bus.h.

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STM32L486xx HAL User Manual: AHB3 GRP1 PERIPH

Defines
AHB3 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB3_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
#define | LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN

Define Documentation

#define LL_AHB3_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 139 of file stm32l4xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN

Definition at line 141 of file stm32l4xx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN

Definition at line 143 of file stm32l4xx_ll_bus.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB1 GRP1 PERIPH

Defines
APB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
#define | LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
#define | LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
#define | LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
#define | LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
#define | LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
#define | LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
#define | LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
#define | LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
#define | LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
#define | LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
#define | LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
#define | LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
#define | LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN

Define Documentation

#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 151 of file stm32l4xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN

Definition at line 193 of file stm32l4xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN

Definition at line 198 of file stm32l4xx_ll_bus.h.

Referenced by LL_DAC_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN

Definition at line 185 of file stm32l4xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN

Definition at line 187 of file stm32l4xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN

Definition at line 189 of file stm32l4xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN

Definition at line 165 of file stm32l4xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN

Definition at line 200 of file stm32l4xx_ll_bus.h.

Referenced by LL_LPTIM_DeInit().

#define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN

Definition at line 199 of file stm32l4xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN

Definition at line 197 of file stm32l4xx_ll_bus.h.

Referenced by LL_PWR_DeInit().

#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN

Definition at line 172 of file stm32l4xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN

Definition at line 174 of file stm32l4xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN

Definition at line 152 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN

Definition at line 154 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN

Definition at line 157 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN

Definition at line 160 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN

Definition at line 162 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN

Definition at line 163 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN

Definition at line 180 of file stm32l4xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN

Definition at line 183 of file stm32l4xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN

Definition at line 175 of file stm32l4xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN

Definition at line 177 of file stm32l4xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN

Definition at line 170 of file stm32l4xx_ll_bus.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB1 GRP2 PERIPH

Defines
APB1 GRP2 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
#define | LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
#define | LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN

Define Documentation

#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 209 of file stm32l4xx_ll_bus.h.

#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN

Definition at line 212 of file stm32l4xx_ll_bus.h.

Referenced by LL_LPTIM_DeInit().

#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN

Definition at line 210 of file stm32l4xx_ll_bus.h.

Referenced by LL_LPUART_DeInit().

#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN

Definition at line 211 of file stm32l4xx_ll_bus.h.

Referenced by LL_SWPMI_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB2 GRP1 PERIPH

Defines
APB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
#define | LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
#define | LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define | LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define | LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
#define | LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
#define | LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN

Define Documentation

#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 220 of file stm32l4xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN

Definition at line 242 of file stm32l4xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN

Definition at line 222 of file stm32l4xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN

Definition at line 237 of file stm32l4xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN

Definition at line 239 of file stm32l4xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN

Definition at line 224 of file stm32l4xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN

Definition at line 227 of file stm32l4xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN

Definition at line 221 of file stm32l4xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN

Definition at line 226 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN

Definition at line 232 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN

Definition at line 233 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN

Definition at line 235 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN

Definition at line 229 of file stm32l4xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN

Definition at line 231 of file stm32l4xx_ll_bus.h.

Referenced by LL_USART_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB1

Functions
AHB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB1 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_AHB1_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock
AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock
AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 334 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable AHB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_SRAM1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 428 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock
AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock
AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 288 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable AHB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_SRAM1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 401 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ForceReset ( uint32_t Periphs )

Force AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset
AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 356 of file stm32l4xx_ll_bus.h.

Referenced by LL_CRC_DeInit(), and LL_DMA_DeInit().

__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
State of Periphs (1 or 0).

Definition at line 313 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 378 of file stm32l4xx_ll_bus.h.

Referenced by LL_CRC_DeInit(), and LL_DMA_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB2

Functions
AHB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
Disable AHB2 peripherals clock.
__STATIC_INLINE void | LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
Force AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB2 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_AHB2_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB2 peripherals clock.

Reference Manual to LL API cross reference:
AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock
AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock
AHB2ENR AESEN LL_AHB2_GRP1_DisableClock
AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 548 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable AHB2 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_SRAM2
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 702 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB2 peripherals clock.

Reference Manual to LL API cross reference:
AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock
AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock
AHB2ENR AESEN LL_AHB2_GRP1_EnableClock
AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 472 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable AHB2 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_SRAM2
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 660 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_ForceReset ( uint32_t Periphs )

Force AHB2 peripherals reset.

Reference Manual to LL API cross reference:
AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset
AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset
AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset
AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_ALL
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 585 of file stm32l4xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_GPIO_DeInit(), and LL_RNG_DeInit().

__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 512 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB2 peripherals reset.

Reference Manual to LL API cross reference:
AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_ALL
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_RNG
(*) value not defined in all devices.
Return values:
None

Definition at line 622 of file stm32l4xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_GPIO_DeInit(), and LL_RNG_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB3

Functions
AHB3
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
Disable AHB3 peripherals clock.
__STATIC_INLINE void | LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
Force AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB3 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB3 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_AHB3_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB3 peripherals clock.

Reference Manual to LL API cross reference:
AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock
AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI
(*) value not defined in all devices.
Return values:
None

Definition at line 762 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable AHB3 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep
AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI
(*) value not defined in all devices.
Return values:
None

Definition at line 832 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB3 peripherals clock.

Reference Manual to LL API cross reference:
AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock
AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI
(*) value not defined in all devices.
Return values:
None

Definition at line 726 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable AHB3 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep
AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI
(*) value not defined in all devices.
Return values:
None

Definition at line 812 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_ForceReset ( uint32_t Periphs )

Force AHB3 peripherals reset.

Reference Manual to LL API cross reference:
AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset
AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_ALL
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI
(*) value not defined in all devices.
Return values:
None

Definition at line 779 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB3 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 746 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB3 peripherals reset.

Reference Manual to LL API cross reference:
AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_ALL
  • LL_AHB3_GRP1_PERIPH_FMC (*)
  • LL_AHB3_GRP1_PERIPH_QSPI
(*) value not defined in all devices.
Return values:
None

Definition at line 796 of file stm32l4xx_ll_bus.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB1

Functions
APB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE uint32_t | LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClockStopSleep (uint32_t Periphs)
Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClockStopSleep (uint32_t Periphs)
Disable APB1 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_APB1_GRP1_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock
APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock
APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock
APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock
APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock
APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock
APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock
APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock
APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock
APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock
APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock
APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock
APB1ENR1 PWREN LL_APB1_GRP1_DisableClock
APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock
APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_LCD (*)
  • LL_APB1_GRP1_PERIPH_RTCAPB (*)
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS (*)
  • LL_APB1_GRP1_PERIPH_CAN1
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_OPAMP
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 1063 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable APB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_LCD (*)
  • LL_APB1_GRP1_PERIPH_RTCAPB (*)
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS (*)
  • LL_APB1_GRP1_PERIPH_CAN1
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_OPAMP
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 1375 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock
APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock
APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock
APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock
APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock
APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock
APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock
APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock
APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock
APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock
APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock
APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock
APB1ENR1 PWREN LL_APB1_GRP1_EnableClock
APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock
APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_LCD (*)
  • LL_APB1_GRP1_PERIPH_RTCAPB (*)
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS (*)
  • LL_APB1_GRP1_PERIPH_CAN1
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_OPAMP
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 901 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable APB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_LCD (*)
  • LL_APB1_GRP1_PERIPH_RTCAPB (*)
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS (*)
  • LL_APB1_GRP1_PERIPH_CAN1
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_OPAMP
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 1290 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset
APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset
APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset
APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset
APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset
APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset
APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset
APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset
APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_ALL
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_LCD (*)
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS (*)
  • LL_APB1_GRP1_PERIPH_CAN1
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_OPAMP
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 1137 of file stm32l4xx_ll_bus.h.

Referenced by LL_DAC_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_PWR_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_LCD (*)
  • LL_APB1_GRP1_PERIPH_RTCAPB (*)
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS (*)
  • LL_APB1_GRP1_PERIPH_CAN1
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_OPAMP
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 986 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_ALL
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3 (*)
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6
  • LL_APB1_GRP1_PERIPH_TIM7
  • LL_APB1_GRP1_PERIPH_LCD (*)
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS (*)
  • LL_APB1_GRP1_PERIPH_CAN1
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_DAC1
  • LL_APB1_GRP1_PERIPH_OPAMP
  • LL_APB1_GRP1_PERIPH_LPTIM1
(*) value not defined in all devices.
Return values:
None

Definition at line 1212 of file stm32l4xx_ll_bus.h.

Referenced by LL_DAC_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_PWR_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE void LL_APB1_GRP2_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock
APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock
APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1079 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep ( uint32_t Periphs )

Disable APB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep
APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep
APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1391 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock
APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock
APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 921 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep ( uint32_t Periphs )

Enable APB1 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep
APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep
APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1310 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset
APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset
APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_ALL
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1154 of file stm32l4xx_ll_bus.h.

Referenced by LL_LPTIM_DeInit(), LL_LPUART_DeInit(), and LL_SWPMI_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock
APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock
APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
State of Periphs (1 or 0).

Definition at line 1002 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset
APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset
APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_ALL
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_SWPMI1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1229 of file stm32l4xx_ll_bus.h.

Referenced by LL_LPTIM_DeInit(), LL_LPUART_DeInit(), and LL_SWPMI_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB2

Functions
APB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB2 peripheral clocks in Sleep and Stop modes.

Function Documentation

__STATIC_INLINE void LL_APB2_GRP1_DisableClock ( uint32_t Periphs )

Disable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock
APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock
APB2ENR TIM1EN LL_APB2_GRP1_DisableClock
APB2ENR SPI1EN LL_APB2_GRP1_DisableClock
APB2ENR TIM8EN LL_APB2_GRP1_DisableClock
APB2ENR USART1EN LL_APB2_GRP1_DisableClock
APB2ENR TIM15EN LL_APB2_GRP1_DisableClock
APB2ENR TIM16EN LL_APB2_GRP1_DisableClock
APB2ENR TIM17EN LL_APB2_GRP1_DisableClock
APB2ENR SAI1EN LL_APB2_GRP1_DisableClock
APB2ENR SAI2EN LL_APB2_GRP1_DisableClock
APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_SDMMC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1515 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep ( uint32_t Periphs )

Disable APB2 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep
APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_SDMMC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1665 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClock ( uint32_t Periphs )

Enable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock
APB2ENR FWEN LL_APB2_GRP1_EnableClock
APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock
APB2ENR TIM1EN LL_APB2_GRP1_EnableClock
APB2ENR SPI1EN LL_APB2_GRP1_EnableClock
APB2ENR TIM8EN LL_APB2_GRP1_EnableClock
APB2ENR USART1EN LL_APB2_GRP1_EnableClock
APB2ENR TIM15EN LL_APB2_GRP1_EnableClock
APB2ENR TIM16EN LL_APB2_GRP1_EnableClock
APB2ENR TIM17EN LL_APB2_GRP1_EnableClock
APB2ENR SAI1EN LL_APB2_GRP1_EnableClock
APB2ENR SAI2EN LL_APB2_GRP1_EnableClock
APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_FW
  • LL_APB2_GRP1_PERIPH_SDMMC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1437 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep ( uint32_t Periphs )

Enable APB2 peripheral clocks in Sleep and Stop modes.

Reference Manual to LL API cross reference:
APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep
APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_SDMMC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1625 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ForceReset ( uint32_t Periphs )

Force APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset
APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset
APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset
APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset
APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset
APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset
APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ALL
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_SDMMC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1552 of file stm32l4xx_ll_bus.h.

Referenced by LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock
APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock
APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock
APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock
APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_FW
  • LL_APB2_GRP1_PERIPH_SDMMC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1 (*)
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 1479 of file stm32l4xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset
APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset
APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset
APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ALL
  • LL_APB2_GRP1_PERIPH_SYSCFG
  • LL_APB2_GRP1_PERIPH_SDMMC1 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM15
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_SAI1
  • LL_APB2_GRP1_PERIPH_SAI2 (*)
  • LL_APB2_GRP1_PERIPH_DFSDM1 (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1589 of file stm32l4xx_ll_bus.h.

Referenced by LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP

Modules
COMP
STM32L4xx_LL_Driver

Modules

COMP Private Constants
COMP Exported Init structure
COMP Exported Constants
COMP Exported Macros
COMP Exported Functions
COMP_LL_Private_Macros

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for COMP registers.

Register | Bit | Function
CSR | BLANKING | LL_COMP_GetOutputBlankingSource
 |  | LL_COMP_SetOutputBlankingSource
 | BRGEN | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputMinus
 |  | LL_COMP_SetInputMinus
 | EN | LL_COMP_Disable
 |  | LL_COMP_Enable
 |  | LL_COMP_IsEnabled
 | HYST | LL_COMP_GetInputHysteresis
 |  | LL_COMP_SetInputHysteresis
 | INMSEL | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputMinus
 |  | LL_COMP_SetInputMinus
 | INPSEL | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputPlus
 |  | LL_COMP_SetInputPlus
 | LOCK | LL_COMP_IsLocked
 |  | LL_COMP_Lock
 | POLARITY | LL_COMP_GetOutputPolarity
 |  | LL_COMP_SetOutputPolarity
 | PWRMODE | LL_COMP_GetPowerMode
 |  | LL_COMP_SetPowerMode
 | SCALEN | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputMinus
 |  | LL_COMP_SetInputMinus
 | VALUE | LL_COMP_ReadOutputLevel
 | WINMODE | LL_COMP_GetCommonWindowMode
 |  | LL_COMP_SetCommonWindowMode
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STM32L486xx HAL User Manual: COMP Private Constants

Defines
COMP Private Constants
COMP

Defines

#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */

Define Documentation

#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */

Definition at line 67 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_ReadOutputLevel().

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STM32L486xx HAL User Manual: LL_COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_COMP_InitTypeDef Struct Reference
COMP Exported Init structure

Structure definition of some features of COMP instance. More...

#include <stm32l4xx_ll_comp.h>

Data Fields

uint32_t | PowerMode
uint32_t | InputPlus
uint32_t | InputMinus
uint32_t | InputHysteresis
uint32_t | OutputPolarity
uint32_t | OutputBlankingSource

Detailed Description

Structure definition of some features of COMP instance.

Definition at line 83 of file stm32l4xx_ll_comp.h.

Field Documentation

uint32_t LL_COMP_InitTypeDef::InputHysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of Comparator input - Hysteresis

This feature can be modified afterwards using unitary function LL_COMP_SetInputHysteresis().

Definition at line 100 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputMinus

Set comparator input minus (inverting input). This parameter can be a value of Comparator inputs - Input minus (input inverting) selection

This feature can be modified afterwards using unitary function LL_COMP_SetInputMinus().

Definition at line 95 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputPlus

Set comparator input plus (non-inverting input). This parameter can be a value of Comparator inputs - Input plus (input non-inverting) selection

This feature can be modified afterwards using unitary function LL_COMP_SetInputPlus().

Definition at line 90 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputBlankingSource

Set comparator blanking source. This parameter can be a value of Comparator output - Blanking source

This feature can be modified afterwards using unitary function LL_COMP_SetOutputBlankingSource().

Definition at line 110 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputPolarity

Set comparator output polarity. This parameter can be a value of Comparator output - Output polarity

This feature can be modified afterwards using unitary function LL_COMP_SetOutputPolarity().

Definition at line 105 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::PowerMode

Set comparator operating mode to adjust power and speed. This parameter can be a value of Comparator modes - Power mode

This feature can be modified afterwards using unitary function LL_COMP_SetPowerMode().

Definition at line 85 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_comp.h
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STM32L486xx HAL User Manual: Comparator common modes - Window mode

Defines
Comparator common modes - Window mode
COMP Exported Constants

Defines

#define | LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U)
#define | LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)

Define Documentation

#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)

Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible).

Definition at line 131 of file stm32l4xx_ll_comp.h.

#define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U)

Window mode disable: Comparators 1 and 2 are independent

Definition at line 130 of file stm32l4xx_ll_comp.h.

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STM32L486xx HAL User Manual: Comparator modes - Power mode

Defines
Comparator modes - Power mode
COMP Exported Constants

Defines

#define | LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U)
#define | LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)
#define | LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0)

Define Documentation

#define LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U)

COMP power mode to high speed

Definition at line 139 of file stm32l4xx_ll_comp.h.

#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)

COMP power mode to medium speed

Definition at line 140 of file stm32l4xx_ll_comp.h.

#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0)

COMP power mode to ultra-low power

Definition at line 141 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Comparator inputs - Input plus (input non-inverting) selection

Defines
Comparator inputs - Input plus (input non-inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U)
#define | LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)

Define Documentation

#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U)

Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2)

Definition at line 149 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)

Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2)

Definition at line 150 of file stm32l4xx_ll_comp.h.

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STM32L486xx HAL User Manual: Comparator inputs - Input minus (input inverting) selection

Defines
Comparator inputs - Input minus (input inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Define Documentation

#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/2 VrefInt

Definition at line 162 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/4 VrefInt

Definition at line 161 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 3/4 VrefInt

Definition at line 163 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)

Definition at line 165 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)

Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)

Definition at line 166 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )

Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2)

Definition at line 167 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2)

Definition at line 168 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )

Comparator input minus connected to VrefInt

Definition at line 164 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

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STM32L486xx HAL User Manual: Comparator inputs legacy literals name

Defines
Comparator inputs legacy literals name
COMP Exported Constants

Defines

#define | LL_COMP_WINDOWMODE_ENABLE LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
#define | LL_COMP_INVERTINGINPUT_1_4VREFINT LL_COMP_INPUT_MINUS_1_4VREFINT
#define | LL_COMP_INVERTINGINPUT_1_2VREFINT LL_COMP_INPUT_MINUS_1_2VREFINT
#define | LL_COMP_INVERTINGINPUT_3_4VREFINT LL_COMP_INPUT_MINUS_3_4VREFINT
#define | LL_COMP_INVERTINGINPUT_VREFINT LL_COMP_INPUT_MINUS_VREFINT
#define | LL_COMP_INVERTINGINPUT_DAC1 LL_COMP_INPUT_MINUS_DAC1_CH1
#define | LL_COMP_INVERTINGINPUT_DAC2 LL_COMP_INPUT_MINUS_DAC1_CH2
#define | LL_COMP_INVERTINGINPUT_IO1 LL_COMP_INPUT_MINUS_IO1
#define | LL_COMP_INVERTINGINPUT_IO2 LL_COMP_INPUT_MINUS_IO2
#define | LL_COMP_NONINVERTINGINPUT_IO1 LL_COMP_INPUT_PLUS_IO1
#define | LL_COMP_NONINVERTINGINPUT_IO2 LL_COMP_INPUT_PLUS_IO2

Define Documentation

#define LL_COMP_INVERTINGINPUT_1_2VREFINT LL_COMP_INPUT_MINUS_1_2VREFINT

Definition at line 184 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INVERTINGINPUT_1_4VREFINT LL_COMP_INPUT_MINUS_1_4VREFINT

Definition at line 183 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INVERTINGINPUT_3_4VREFINT LL_COMP_INPUT_MINUS_3_4VREFINT

Definition at line 185 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INVERTINGINPUT_DAC1 LL_COMP_INPUT_MINUS_DAC1_CH1

Definition at line 187 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INVERTINGINPUT_DAC2 LL_COMP_INPUT_MINUS_DAC1_CH2

Definition at line 188 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INVERTINGINPUT_IO1 LL_COMP_INPUT_MINUS_IO1

Definition at line 189 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INVERTINGINPUT_IO2 LL_COMP_INPUT_MINUS_IO2

Definition at line 190 of file stm32l4xx_ll_comp.h.

#define LL_COMP_INVERTINGINPUT_VREFINT LL_COMP_INPUT_MINUS_VREFINT

Definition at line 186 of file stm32l4xx_ll_comp.h.

#define LL_COMP_NONINVERTINGINPUT_IO1 LL_COMP_INPUT_PLUS_IO1

Definition at line 197 of file stm32l4xx_ll_comp.h.

#define LL_COMP_NONINVERTINGINPUT_IO2 LL_COMP_INPUT_PLUS_IO2

Definition at line 198 of file stm32l4xx_ll_comp.h.

#define LL_COMP_WINDOWMODE_ENABLE LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

Definition at line 181 of file stm32l4xx_ll_comp.h.

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STM32L486xx HAL User Manual: Comparator input - Hysteresis

Defines
Comparator input - Hysteresis
COMP Exported Constants

Defines

#define | LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U)
#define | LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )
#define | LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Define Documentation

#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Hysteresis level high

Definition at line 212 of file stm32l4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)

Hysteresis level low

Definition at line 210 of file stm32l4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )

Hysteresis level medium

Definition at line 211 of file stm32l4xx_ll_comp.h.

#define LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U)

No hysteresis

Definition at line 209 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

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STM32L486xx HAL User Manual: Comparator output - Output polarity

Defines
Comparator output - Output polarity
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

Define Documentation

#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input

Definition at line 221 of file stm32l4xx_ll_comp.h.

#define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U)

COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input

Definition at line 220 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Comparator output - Blanking source

Defines
Comparator output - Blanking source
COMP Exported Constants

Defines

#define | LL_COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000U)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 (COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 (COMP_CSR_BLANKING_1)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 (COMP_CSR_BLANKING_2)
#define | LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 (COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_1)
#define | LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2)

Define Documentation

#define LL_COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000U)

Comparator output without blanking

Definition at line 229 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2)

Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP2)

Definition at line 235 of file stm32l4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 (COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1)

Definition at line 230 of file stm32l4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 (COMP_CSR_BLANKING_1)

Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1)

Definition at line 231 of file stm32l4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 (COMP_CSR_BLANKING_2)

Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1)

Definition at line 232 of file stm32l4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 (COMP_CSR_BLANKING_0)

Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP2)

Definition at line 233 of file stm32l4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_1)

Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2)

Definition at line 234 of file stm32l4xx_ll_comp.h.

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STM32L486xx HAL User Manual: Comparator output blanking source legacy literals name

Defines
Comparator output blanking source legacy literals name
COMP Exported Constants

Defines

#define | LL_COMP_BLANKINGSRC_TIM1_OC5 (LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3 (LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3 (LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)
#define | LL_COMP_BLANKINGSRC_TIM3_OC4 (LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2)
#define | LL_COMP_BLANKINGSRC_TIM8_OC5 (LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)
#define | LL_COMP_BLANKINGSRC_TIM15_OC1 (LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2)

Define Documentation

#define LL_COMP_BLANKINGSRC_TIM15_OC1 (LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2)

Definition at line 249 of file stm32l4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM1_OC5 (LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)

Definition at line 243 of file stm32l4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM2_OC3 (LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)

Definition at line 244 of file stm32l4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC3 (LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)

Definition at line 245 of file stm32l4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM3_OC4 (LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2)

Definition at line 247 of file stm32l4xx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM8_OC5 (LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)

Definition at line 248 of file stm32l4xx_ll_comp.h.

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STM32L486xx HAL User Manual: Comparator output - Output level

Defines
Comparator output - Output level
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U)
#define | LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U)

Define Documentation

#define LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U)

Comparator output level high (if the polarity is not inverted, otherwise to be complemented)

Definition at line 258 of file stm32l4xx_ll_comp.h.

#define LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U)

Comparator output level low (if the polarity is not inverted, otherwise to be complemented)

Definition at line 257 of file stm32l4xx_ll_comp.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Definitions of COMP hardware constraints delays

Defines
Definitions of COMP hardware constraints delays
COMP Exported Constants

Defines

#define | LL_COMP_DELAY_STARTUP_US ((uint32_t) 80U)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)

Detailed Description

Note:
Only COMP IP HW delays are defined in COMP LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 80U)

Delay for COMP startup time

Definition at line 276 of file stm32l4xx_ll_comp.h.

#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)

Delay for COMP voltage scaler stabilization time

Definition at line 284 of file stm32l4xx_ll_comp.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common write and read registers macro

Defines
Common write and read registers macro
COMP Exported Macros

Defines

#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in COMP register.

Define Documentation

#define LL_COMP_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 317 of file stm32l4xx_ll_comp.h.

#define LL_COMP_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 309 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP helper macro

Defines
COMP helper macro
COMP Exported Macros

Defines

#define __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Define Documentation

#define __LL_COMP_COMMON_INSTANCE ( __COMPx__ ) (COMP12_COMMON)

Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Note:
COMP common register instance can be used to set parameters common to several COMP instances. Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
__COMPx__ COMP instance
Return values:
COMP common instance or value "0" if there is no COMP common instance.

Definition at line 335 of file stm32l4xx_ll_comp.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of COMP hierarchical scope: common to several COMP instances

Functions
Configuration of COMP hierarchical scope: common to several COMP instances
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON)
Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode ( COMP_Common_TypeDef * COMPxy_COMMON )

Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CSR WINMODE LL_COMP_GetCommonWindowMode
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_COMP_WINDOWMODE_DISABLE
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

Definition at line 383 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetCommonWindowMode | ( | COMP_Common_TypeDef * | COMPxy_COMMON,
 |  | uint32_t | WindowMode
 | ) |  |

Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CSR WINMODE LL_COMP_SetCommonWindowMode
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
WindowMode This parameter can be one of the following values:
  • LL_COMP_WINDOWMODE_DISABLE
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
Return values:
None

Definition at line 366 of file stm32l4xx_ll_comp.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of comparator modes

Functions
Configuration of comparator modes
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetPowerMode (COMP_TypeDef *COMPx, uint32_t PowerMode)
Set comparator instance operating mode to adjust power and speed.
__STATIC_INLINE uint32_t | LL_COMP_GetPowerMode (COMP_TypeDef *COMPx)
Get comparator instance operating mode to adjust power and speed.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetPowerMode ( COMP_TypeDef * COMPx )

Get comparator instance operating mode to adjust power and speed.

Reference Manual to LL API cross reference:
CSR PWRMODE LL_COMP_GetPowerMode
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_POWERMODE_HIGHSPEED
  • LL_COMP_POWERMODE_MEDIUMSPEED
  • LL_COMP_POWERMODE_ULTRALOWPOWER

Definition at line 420 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetPowerMode | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | PowerMode
 | ) |  |

Set comparator instance operating mode to adjust power and speed.

Reference Manual to LL API cross reference:
CSR PWRMODE LL_COMP_SetPowerMode
Parameters:
COMPx Comparator instance
PowerMode This parameter can be one of the following values:
  • LL_COMP_POWERMODE_HIGHSPEED
  • LL_COMP_POWERMODE_MEDIUMSPEED
  • LL_COMP_POWERMODE_ULTRALOWPOWER
Return values:
None

Definition at line 406 of file stm32l4xx_ll_comp.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of comparator inputs

Functions
Configuration of comparator inputs
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.

Function Documentation

__STATIC_INLINE void LL_COMP_ConfigInputs | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator inputs minus (inverting) and plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
On this STM32 serie, scaler bridge is configurable: to optimize power consumption, this function enables the voltage scaler bridge only when required (when selecting comparator input based on VrefInt: VrefInt or subdivision of VrefInt).
  • For scaler bridge power consumption values, refer to device datasheet, parameter "IDDA(SCALER)".
  • Voltage scaler requires a delay for voltage stabilization. Refer to device datasheet, parameter "tSTART_SCALER".
  • Scaler bridge is common for all comparator instances, therefore if at least one of the comparator instance is requiring the scaler bridge, it remains enabled.
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_ConfigInputs
CSR INPSEL LL_COMP_ConfigInputs
CSR BRGEN LL_COMP_ConfigInputs
CSR SCALEN LL_COMP_ConfigInputs
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3 (*)
  • LL_COMP_INPUT_MINUS_IO4 (*)
  • LL_COMP_INPUT_MINUS_IO5 (*)
(*) Parameter not available on all devices.
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
  • LL_COMP_INPUT_PLUS_IO3 (*)
(*) Parameter not available on all devices.
Return values:
None

Definition at line 477 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis ( COMP_TypeDef * COMPx )

Get comparator instance hysteresis mode of the minus (inverting) input.

Reference Manual to LL API cross reference:
CSR HYST LL_COMP_GetInputHysteresis
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH

Definition at line 634 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputMinus ( COMP_TypeDef * COMPx )

Get comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_GetInputMinus
CSR BRGEN LL_COMP_GetInputMinus
CSR SCALEN LL_COMP_GetInputMinus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3 (*)
  • LL_COMP_INPUT_MINUS_IO4 (*)
  • LL_COMP_INPUT_MINUS_IO5 (*)
(*) Parameter not available on all devices.

Definition at line 599 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_GetInputInverting().

__STATIC_INLINE uint32_t LL_COMP_GetInputPlus ( COMP_TypeDef * COMPx )

Get comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INPSEL LL_COMP_GetInputPlus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
  • LL_COMP_INPUT_PLUS_IO3 (*)
(*) Parameter not available on all devices.

Definition at line 524 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_GetInputNonInverting().

__STATIC_INLINE void LL_COMP_SetInputHysteresis | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputHysteresis
 | ) |  |

Set comparator instance hysteresis mode of the input minus (inverting input).

Reference Manual to LL API cross reference:
CSR HYST LL_COMP_SetInputHysteresis
Parameters:
COMPx Comparator instance
InputHysteresis This parameter can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH
Return values:
None

Definition at line 619 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputMinus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus
 | ) |  |

Set comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
On this STM32 serie, scaler bridge is configurable: to optimize power consumption, this function enables the voltage scaler bridge only when required (when selecting comparator input based on VrefInt: VrefInt or subdivision of VrefInt).
  • For scaler bridge power consumption values, refer to device datasheet, parameter "IDDA(SCALER)".
  • Voltage scaler requires a delay for voltage stabilization. Refer to device datasheet, parameter "tSTART_SCALER".
  • Scaler bridge is common for all comparator instances, therefore if at least one of the comparator instance is requiring the scaler bridge, it remains enabled.
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_SetInputMinus
CSR BRGEN LL_COMP_SetInputMinus
CSR SCALEN LL_COMP_SetInputMinus
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_DAC1_CH1
  • LL_COMP_INPUT_MINUS_DAC1_CH2
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3 (*)
  • LL_COMP_INPUT_MINUS_IO4 (*)
  • LL_COMP_INPUT_MINUS_IO5 (*)
(*) Parameter not available on all devices.
Return values:
None

Definition at line 566 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_SetInputInverting().

__STATIC_INLINE void LL_COMP_SetInputPlus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INPSEL LL_COMP_SetInputPlus
Parameters:
COMPx Comparator instance
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
  • LL_COMP_INPUT_PLUS_IO3 (*)
(*) Parameter not available on all devices.
Return values:
None

Definition at line 505 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_SetInputNonInverting().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of comparator output

Functions
Configuration of comparator output
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_SetOutputBlankingSource (COMP_TypeDef *COMPx, uint32_t BlankingSource)
Set comparator instance blanking source.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputBlankingSource (COMP_TypeDef *COMPx)
Get comparator instance blanking source.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource ( COMP_TypeDef * COMPx )

Get comparator instance blanking source.

Note:
Availability of parameters of blanking source from timer depends on timers availability on the selected device.
Blanking source may be specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR BLANKING LL_COMP_GetOutputBlankingSource
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_BLANKINGSRC_NONE
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 (1)(2)
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 (1)(2)
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 (1)(2)
  • LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 (1)(3)
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (1)(3)
  • LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (1)(3)
(1) Parameter availability depending on timer availability on the selected device. (2) On STM32L4, parameter available only on comparator instance: COMP1. (3) On STM32L4, parameter available only on comparator instance: COMP2.

Definition at line 724 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity ( COMP_TypeDef * COMPx )

Get comparator instance output polarity.

Reference Manual to LL API cross reference:
CSR POLARITY LL_COMP_GetOutputPolarity
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED

Definition at line 669 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputBlankingSource | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | BlankingSource
 | ) |  |

Set comparator instance blanking source.

Note:
Blanking source may be specific to each comparator instance. Refer to description of parameters or to reference manual.
Availability of parameters of blanking source from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CSR BLANKING LL_COMP_SetOutputBlankingSource
Parameters:
COMPx Comparator instance
BlankingSource This parameter can be one of the following values:
  • LL_COMP_BLANKINGSRC_NONE
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 (1)(2)
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 (1)(2)
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 (1)(2)
  • LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 (1)(3)
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (1)(3)
  • LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (1)(3)
(1) Parameter availability depending on timer availability on the selected device. (2) On STM32L4, parameter available only on comparator instance: COMP1. (3) On STM32L4, parameter available only on comparator instance: COMP2.
Return values:
None

Definition at line 697 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputPolarity | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | OutputPolarity
 | ) |  |

Set comparator instance output polarity.

Reference Manual to LL API cross reference:
CSR POLARITY LL_COMP_SetOutputPolarity
Parameters:
COMPx Comparator instance
OutputPolarity This parameter can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED
Return values:
None

Definition at line 656 of file stm32l4xx_ll_comp.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of COMP, legacy functions name

Functions
Configuration of COMP, legacy functions name
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetInputNonInverting (COMP_TypeDef *COMPx, uint32_t InputNonInverting)
__STATIC_INLINE uint32_t | LL_COMP_GetInputNonInverting (COMP_TypeDef *COMPx)
__STATIC_INLINE void | LL_COMP_SetInputInverting (COMP_TypeDef *COMPx, uint32_t InputInverting)
__STATIC_INLINE uint32_t | LL_COMP_GetInputInverting (COMP_TypeDef *COMPx)

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetInputInverting ( COMP_TypeDef * COMPx )

Definition at line 751 of file stm32l4xx_ll_comp.h.

References LL_COMP_GetInputMinus().

__STATIC_INLINE uint32_t LL_COMP_GetInputNonInverting ( COMP_TypeDef * COMPx )

Definition at line 742 of file stm32l4xx_ll_comp.h.

References LL_COMP_GetInputPlus().

__STATIC_INLINE void LL_COMP_SetInputInverting | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputInverting
 | ) |  |

Definition at line 747 of file stm32l4xx_ll_comp.h.

References LL_COMP_SetInputMinus().

__STATIC_INLINE void LL_COMP_SetInputNonInverting | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputNonInverting
 | ) |  |

Definition at line 738 of file stm32l4xx_ll_comp.h.

References LL_COMP_SetInputPlus().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Operation on comparator instance

Functions
Operation on comparator instance
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (COMP_TypeDef *COMPx)
Read comparator instance output level.

Function Documentation

__STATIC_INLINE void LL_COMP_Disable ( COMP_TypeDef * COMPx )

Disable comparator instance.

Reference Manual to LL API cross reference:
CSR EN LL_COMP_Disable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 784 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE void LL_COMP_Enable ( COMP_TypeDef * COMPx )

Enable comparator instance.

Note:
After enable from off state, comparator requires a delay to reach reach propagation delay specification. Refer to device datasheet, parameter "tSTART".
Reference Manual to LL API cross reference:
CSR EN LL_COMP_Enable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 773 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_IsEnabled ( COMP_TypeDef * COMPx )

Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)

Reference Manual to LL API cross reference:
CSR EN LL_COMP_IsEnabled
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 796 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_IsLocked ( COMP_TypeDef * COMPx )

Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CSR LOCK LL_COMP_IsLocked
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 823 of file stm32l4xx_ll_comp.h.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

__STATIC_INLINE void LL_COMP_Lock ( COMP_TypeDef * COMPx )

Lock comparator instance.

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CSR LOCK LL_COMP_Lock
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 809 of file stm32l4xx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel ( COMP_TypeDef * COMPx )

Read comparator instance output level.

Note:
The comparator output level depends on the selected polarity (Refer to function LL_COMP_SetOutputPolarity()). If the comparator polarity is not inverted:
  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus If the comparator polarity is inverted:
  • Comparator output is high when the input plus is at a lower voltage than the input minus
  • Comparator output is low when the input plus is at a higher voltage than the input minus
Reference Manual to LL API cross reference:
CSR VALUE LL_COMP_ReadOutputLevel
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUT_LEVEL_LOW
  • LL_COMP_OUTPUT_LEVEL_HIGH

Definition at line 848 of file stm32l4xx_ll_comp.h.

References LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
COMP Exported Functions

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_COMP_DeInit ( COMP_TypeDef * COMPx )

De-initialize registers of the selected COMP instance to their default reset values.

Note:
If comparator is locked, de-initialization by software is not possible. The only way to unlock the comparator is a device hardware reset.
Parameters:
COMPx COMP instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are de-initialized
  • ERROR: COMP registers are not de-initialized

Definition at line 173 of file stm32l4xx_ll_comp.c.

References assert_param, LL_COMP_IsLocked(), and LL_COMP_WriteReg.

ErrorStatus LL_COMP_Init | ( | COMP_TypeDef * | COMPx,
 |  | LL_COMP_InitTypeDef * | COMP_InitStruct
 | ) |  |

Initialize some features of COMP instance.

Note:
This function configures features of the selected COMP instance. Some features are also available at scope COMP common instance (common to several COMP instances). Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
COMPx | COMP instance
COMP_InitStruct | Pointer to a LL_COMP_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are initialized
  • ERROR: COMP registers are not initialized

Definition at line 210 of file stm32l4xx_ll_comp.c.

References assert_param, LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, IS_LL_COMP_INPUT_HYSTERESIS, IS_LL_COMP_INPUT_MINUS, IS_LL_COMP_INPUT_PLUS, IS_LL_COMP_OUTPUT_BLANKING_SOURCE, IS_LL_COMP_OUTPUT_POLARITY, IS_LL_COMP_POWER_MODE, LL_COMP_IsLocked(), LL_COMP_InitTypeDef::OutputBlankingSource, LL_COMP_InitTypeDef::OutputPolarity, and LL_COMP_InitTypeDef::PowerMode.

void LL_COMP_StructInit ( LL_COMP_InitTypeDef * COMP_InitStruct )

Set each LL_COMP_InitTypeDef field to default value.

Parameters:
COMP_InitStruct,: pointer to a LL_COMP_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 289 of file stm32l4xx_ll_comp.c.

References LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, LL_COMP_BLANKINGSRC_NONE, LL_COMP_HYSTERESIS_NONE, LL_COMP_INPUT_MINUS_VREFINT, LL_COMP_INPUT_PLUS_IO1, LL_COMP_OUTPUTPOL_NONINVERTED, LL_COMP_POWERMODE_ULTRALOWPOWER, LL_COMP_InitTypeDef::OutputBlankingSource, LL_COMP_InitTypeDef::OutputPolarity, and LL_COMP_InitTypeDef::PowerMode.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP_LL_Private_Macros

Defines
COMP_LL_Private_Macros
COMP

Defines

#define | IS_LL_COMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)

Define Documentation

#define IS_LL_COMP_INPUT_HYSTERESIS ( __INPUT_HYSTERESIS__ )
Value:
(   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
  )

Definition at line 124 of file stm32l4xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
  )

Definition at line 112 of file stm32l4xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
  )

Definition at line 87 of file stm32l4xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE ( __OUTPUT_BLANKING_SOURCE__ )
Value:
(   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)               \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)     \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)     \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)     \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2)     \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)     \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2)    \
  )

Definition at line 136 of file stm32l4xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
   || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
  )

Definition at line 131 of file stm32l4xx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_POWER_MODE ( __POWER_MODE__ )
Value:
(   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
   || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
   || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
  )

Definition at line 70 of file stm32l4xx_ll_comp.c.

Referenced by LL_COMP_Init().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX

Modules
CORTEX
STM32L4xx_LL_Driver

Modules

CORTEX Exported Constants
CORTEX Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for CORTEX registers.

Register | Bit | Function
MPU_CTRL | ENABLE | LL_MPU_Disable
 |  | LL_MPU_Enable
 |  | LL_MPU_IsEnabled
MPU_RASR | AP | LL_MPU_ConfigRegion
 | B | LL_MPU_ConfigRegion
 | C | LL_MPU_ConfigRegion
 | ENABLE | LL_MPU_DisableRegion
 |  | LL_MPU_EnableRegion
 | S | LL_MPU_ConfigRegion
 | SIZE | LL_MPU_ConfigRegion
 | XN | LL_MPU_ConfigRegion
MPU_RBAR | ADDR | LL_MPU_ConfigRegion
 | REGION | LL_MPU_ConfigRegion
MPU_RNR | REGION | LL_MPU_ConfigRegion
 |  | LL_MPU_DisableRegion
SCB_CPUID | ARCHITECTURE | LL_CPUID_GetConstant
 | IMPLEMENTER | LL_CPUID_GetImplementer
 | PARTNO | LL_CPUID_GetParNo
 | REVISION | LL_CPUID_GetRevision
 | VARIANT | LL_CPUID_GetVariant
SCB_SCR | SEVEONPEND | LL_LPM_DisableEventOnPend
 |  | LL_LPM_EnableEventOnPend
 | SLEEPDEEP | LL_LPM_EnableDeepSleep
 |  | LL_LPM_EnableSleep
 | SLEEPONEXIT | LL_LPM_DisableSleepOnExit
 |  | LL_LPM_EnableSleepOnExit
SCB_SHCSR | MEMFAULTENA | LL_HANDLER_DisableFault
 |  | LL_HANDLER_EnableFault
STK_CTRL | CLKSOURCE | LL_SYSTICK_GetClkSource
 |  | LL_SYSTICK_SetClkSource
 | COUNTFLAG | LL_SYSTICK_IsActiveCounterFlag
 | TICKINT | LL_SYSTICK_DisableIT
 |  | LL_SYSTICK_EnableIT
 |  | LL_SYSTICK_IsEnabledIT
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSTICK Clock Source

Defines
SYSTICK Clock Source
CORTEX Exported Constants

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
#define | LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk)

Define Documentation

#define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk)

AHB clock selected as SysTick clock source.

Definition at line 89 of file stm32l4xx_ll_cortex.h.

Referenced by LL_SYSTICK_GetClkSource(), and LL_SYSTICK_SetClkSource().

#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)

AHB clock divided by 8 selected as SysTick clock source.

Definition at line 88 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Handler Fault type

Defines
Handler Fault type
CORTEX Exported Constants

Defines

#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Define Documentation

#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk

Bus fault

Definition at line 98 of file stm32l4xx_ll_cortex.h.

#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Memory management fault

Definition at line 99 of file stm32l4xx_ll_cortex.h.

#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk

Usage fault

Definition at line 97 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU Control

Defines
MPU Control
CORTEX Exported Constants

Defines

#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Define Documentation

#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk

Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers

Definition at line 110 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Enable NMI and privileged SW access

Definition at line 112 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)

Disable NMI and privileged SW access

Definition at line 109 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk

Enable privileged software access to default memory map

Definition at line 111 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU Region Number

Defines
MPU Region Number
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U)
#define | LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U)
#define | LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U)
#define | LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U)
#define | LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U)
#define | LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U)
#define | LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U)
#define | LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U)

Define Documentation

#define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U)

REGION Number 0

Definition at line 120 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U)

REGION Number 1

Definition at line 121 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U)

REGION Number 2

Definition at line 122 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U)

REGION Number 3

Definition at line 123 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U)

REGION Number 4

Definition at line 124 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U)

REGION Number 5

Definition at line 125 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U)

REGION Number 6

Definition at line 126 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U)

REGION Number 7

Definition at line 127 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU Region Size

Defines
MPU Region Size
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos))

Define Documentation

#define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos))

128B Size of the MPU protection region

Definition at line 137 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos))

128KB Size of the MPU protection region

Definition at line 147 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos))

128MB Size of the MPU protection region

Definition at line 157 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos))

16KB Size of the MPU protection region

Definition at line 144 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos))

16MB Size of the MPU protection region

Definition at line 154 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos))

1GB Size of the MPU protection region

Definition at line 160 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos))

1KB Size of the MPU protection region

Definition at line 140 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos))

1MB Size of the MPU protection region

Definition at line 150 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos))

256B Size of the MPU protection region

Definition at line 138 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos))

256KB Size of the MPU protection region

Definition at line 148 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos))

256MB Size of the MPU protection region

Definition at line 158 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos))

2GB Size of the MPU protection region

Definition at line 161 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos))

2KB Size of the MPU protection region

Definition at line 141 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos))

2MB Size of the MPU protection region

Definition at line 151 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos))

32B Size of the MPU protection region

Definition at line 135 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos))

32KB Size of the MPU protection region

Definition at line 145 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos))

32MB Size of the MPU protection region

Definition at line 155 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos))

4GB Size of the MPU protection region

Definition at line 162 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos))

4KB Size of the MPU protection region

Definition at line 142 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos))

4MB Size of the MPU protection region

Definition at line 152 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos))

512B Size of the MPU protection region

Definition at line 139 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos))

512KB Size of the MPU protection region

Definition at line 149 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos))

512MB Size of the MPU protection region

Definition at line 159 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos))

64B Size of the MPU protection region

Definition at line 136 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos))

64KB Size of the MPU protection region

Definition at line 146 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos))

64MB Size of the MPU protection region

Definition at line 156 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos))

8KB Size of the MPU protection region

Definition at line 143 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos))

8MB Size of the MPU protection region

Definition at line 153 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU Region Privileges

Defines
MPU Region Privileges
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos))
#define | LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos))
#define | LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos))
#define | LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos))
#define | LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos))
#define | LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos))

Define Documentation

#define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos))

RW privileged & user (Full access)

Definition at line 173 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos))

No access

Definition at line 170 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos))

RO privileged (privileged read only)

Definition at line 174 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos))

RO privileged & user (read only)

Definition at line 175 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos))

RW privileged (privileged access only)

Definition at line 171 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos))

RW privileged - RO user (Write in a user program generates a fault)

Definition at line 172 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU TEX Level

Defines
MPU TEX Level
CORTEX Exported Constants

Defines

#define | LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos))
#define | LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos))
#define | LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos))
#define | LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos))

Define Documentation

#define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos))

b000 for TEX bits

Definition at line 183 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos))

b001 for TEX bits

Definition at line 184 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos))

b010 for TEX bits

Definition at line 185 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos))

b100 for TEX bits

Definition at line 186 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU Instruction Access

Defines
MPU Instruction Access
CORTEX Exported Constants

Defines

#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U)
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Define Documentation

#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Instruction fetches disabled

Definition at line 195 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U)

Instruction fetches enabled

Definition at line 194 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU Shareable Access

Defines
MPU Shareable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U)

Define Documentation

#define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U)

Not Shareable memory attribute

Definition at line 204 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk

Shareable memory attribute

Definition at line 203 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU Cacheable Access

Defines
MPU Cacheable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U)

Define Documentation

#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk

Cacheable memory attribute

Definition at line 212 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U)

Not Cacheable memory attribute

Definition at line 213 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU Bufferable Access

Defines
MPU Bufferable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U)

Define Documentation

#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk

Bufferable memory attribute

Definition at line 221 of file stm32l4xx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U)

Not Bufferable memory attribute

Definition at line 222 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSTICK

Functions
SYSTICK
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_SYSTICK_DisableIT ( void )

Disable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_DisableIT
Return values:
None

Definition at line 300 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_EnableIT ( void )

Enable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_EnableIT
Return values:
None

Definition at line 290 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource ( void )

Get the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
Return values:
Returned value can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK

Definition at line 280 of file stm32l4xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag ( void )

This function checks if the Systick counter flag is active or not.

Note:
It can be used in timeout function on application side.
Reference Manual to LL API cross reference:
STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
Return values:
State of bit (1 or 0).

Definition at line 248 of file stm32l4xx_ll_cortex.h.

Referenced by LL_RTC_EnterInitMode(), and LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT ( void )

Checks if the SYSTICK interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
Return values:
State of bit (1 or 0).

Definition at line 310 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_SetClkSource ( uint32_t Source )

Configures the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK
Return values:
None

Definition at line 261 of file stm32l4xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LOW POWER MODE

Functions
LOW POWER MODE
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Function Documentation

__STATIC_INLINE void LL_LPM_DisableEventOnPend ( void )

Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
Return values:
None

Definition at line 387 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_DisableSleepOnExit ( void )

Do not sleep when returning to Thread mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
Return values:
None

Definition at line 363 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableDeepSleep ( void )

Processor uses deep sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
Return values:
None

Definition at line 339 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableEventOnPend ( void )

Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
Return values:
None

Definition at line 375 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleep ( void )

Processor uses sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
Return values:
None

Definition at line 328 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleepOnExit ( void )

Configures sleep-on-exit when returning from Handler mode to Thread mode.

Note:
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
Return values:
None

Definition at line 352 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HANDLER

Functions
HANDLER
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)

Function Documentation

__STATIC_INLINE void LL_HANDLER_DisableFault ( uint32_t Fault )

Disable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 425 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_HANDLER_EnableFault ( uint32_t Fault )

Enable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 410 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MCU INFO

Functions
MCU INFO
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetConstant (void)
Get Constant number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Function Documentation

__STATIC_INLINE uint32_t LL_CPUID_GetConstant ( void )

Get Constant number.

Reference Manual to LL API cross reference:
SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
Return values:
Value should be equal to 0xF for Cortex-M4 devices

Definition at line 464 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetImplementer ( void )

Get Implementer code.

Reference Manual to LL API cross reference:
SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
Return values:
Value should be equal to 0x41 for ARM

Definition at line 444 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetParNo ( void )

Get Part number.

Reference Manual to LL API cross reference:
SCB_CPUID PARTNO LL_CPUID_GetParNo
Return values:
Value should be equal to 0xC24 for Cortex-M4

Definition at line 474 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetRevision ( void )

Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Reference Manual to LL API cross reference:
SCB_CPUID REVISION LL_CPUID_GetRevision
Return values:
Value between 0 and 255 (0x1: patch 1)

Definition at line 484 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetVariant ( void )

Get Variant number (The r value in the rnpn product revision identifier)

Reference Manual to LL API cross reference:
SCB_CPUID VARIANT LL_CPUID_GetVariant
Return values:
Value between 0 and 255 (0x0: revision 0)

Definition at line 454 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU

Functions
MPU
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Function Documentation

__STATIC_INLINE void LL_MPU_ConfigRegion | ( | uint32_t | Region,
 |  | uint32_t | SubRegionDisable,
 |  | uint32_t | Address,
 |  | uint32_t | Attributes
 | ) |  |

Configure and enable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_ConfigRegion
MPU_RBAR REGION LL_MPU_ConfigRegion
MPU_RBAR ADDR LL_MPU_ConfigRegion
MPU_RASR XN LL_MPU_ConfigRegion
MPU_RASR AP LL_MPU_ConfigRegion
MPU_RASR S LL_MPU_ConfigRegion
MPU_RASR C LL_MPU_ConfigRegion
MPU_RASR B LL_MPU_ConfigRegion
MPU_RASR SIZE LL_MPU_ConfigRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Address | Value of region base address
SubRegionDisable | Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
Attributes This parameter can be a combination of the following values:
  • LL_MPU_REGION_SIZE_32B or LL_MPU_REGION_SIZE_64B or LL_MPU_REGION_SIZE_128B or LL_MPU_REGION_SIZE_256B or LL_MPU_REGION_SIZE_512B or LL_MPU_REGION_SIZE_1KB or LL_MPU_REGION_SIZE_2KB or LL_MPU_REGION_SIZE_4KB or LL_MPU_REGION_SIZE_8KB or LL_MPU_REGION_SIZE_16KB or LL_MPU_REGION_SIZE_32KB or LL_MPU_REGION_SIZE_64KB or LL_MPU_REGION_SIZE_128KB or LL_MPU_REGION_SIZE_256KB or LL_MPU_REGION_SIZE_512KB or LL_MPU_REGION_SIZE_1MB or LL_MPU_REGION_SIZE_2MB or LL_MPU_REGION_SIZE_4MB or LL_MPU_REGION_SIZE_8MB or LL_MPU_REGION_SIZE_16MB or LL_MPU_REGION_SIZE_32MB or LL_MPU_REGION_SIZE_64MB or LL_MPU_REGION_SIZE_128MB or LL_MPU_REGION_SIZE_256MB or LL_MPU_REGION_SIZE_512MB or LL_MPU_REGION_SIZE_1GB or LL_MPU_REGION_SIZE_2GB or LL_MPU_REGION_SIZE_4GB
  • LL_MPU_REGION_NO_ACCESS or LL_MPU_REGION_PRIV_RW or LL_MPU_REGION_PRIV_RW_URO or LL_MPU_REGION_FULL_ACCESS or LL_MPU_REGION_PRIV_RO or LL_MPU_REGION_PRIV_RO_URO
  • LL_MPU_TEX_LEVEL0 or LL_MPU_TEX_LEVEL1 or LL_MPU_TEX_LEVEL2 or LL_MPU_TEX_LEVEL4
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE or LL_MPU_INSTRUCTION_ACCESS_DISABLE
  • LL_MPU_ACCESS_SHAREABLE or LL_MPU_ACCESS_NOT_SHAREABLE
  • LL_MPU_ACCESS_CACHEABLE or LL_MPU_ACCESS_NOT_CACHEABLE
  • LL_MPU_ACCESS_BUFFERABLE or LL_MPU_ACCESS_NOT_BUFFERABLE
Return values:
None

Definition at line 601 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Disable ( void )

Disable MPU.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Disable
Return values:
None

Definition at line 523 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_DisableRegion ( uint32_t Region )

Disable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_DisableRegion
MPU_RASR ENABLE LL_MPU_DisableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Return values:
None

Definition at line 626 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Enable ( uint32_t Options )

Enable MPU with input options.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Enable
Parameters:
Options This parameter can be one of the following values:
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
  • LL_MPU_CTRL_HARDFAULT_NMI
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT
  • LL_MPU_CTRL_HFNMI_PRIVDEF
Return values:
None

Definition at line 508 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_EnableRegion ( uint32_t Region )

Enable a MPU region.

Reference Manual to LL API cross reference:
MPU_RASR ENABLE LL_MPU_EnableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Return values:
None

Definition at line 555 of file stm32l4xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_MPU_IsEnabled ( void )

Check if MPU is enabled or not.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 536 of file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC

Modules
CRC
STM32L4xx_LL_Driver

Modules

CRC Exported Constants
CRC Exported Macros
CRC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for CRC registers.

Register | Bit | Function
CR | POLYSIZE | LL_CRC_GetPolynomialSize
 |  | LL_CRC_SetPolynomialSize
 | RESET | LL_CRC_ResetCRCCalculationUnit
 | REV_IN | LL_CRC_GetInputDataReverseMode
 |  | LL_CRC_SetInputDataReverseMode
 | REV_OUT | LL_CRC_GetOutputDataReverseMode
 |  | LL_CRC_SetOutputDataReverseMode
DR | DR | LL_CRC_FeedData16
 |  | LL_CRC_FeedData32
 |  | LL_CRC_FeedData8
 |  | LL_CRC_ReadData16
 |  | LL_CRC_ReadData32
 |  | LL_CRC_ReadData7
 |  | LL_CRC_ReadData8
IDR | IDR | LL_CRC_Read_IDR
 |  | LL_CRC_Write_IDR
INIT | INIT | LL_CRC_GetInitialData
 |  | LL_CRC_SetInitialData
POL | POL | LL_CRC_GetPolynomialCoef
 |  | LL_CRC_SetPolynomialCoef
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Polynomial length

Defines
Polynomial length
CRC Exported Constants

Defines

#define | LL_CRC_POLYLENGTH_32B (uint32_t)0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

Define Documentation

#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0

16 bits Polynomial size

Definition at line 74 of file stm32l4xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_32B (uint32_t)0x00000000U

32 bits Polynomial size

Definition at line 73 of file stm32l4xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

7 bits Polynomial size

Definition at line 76 of file stm32l4xx_ll_crc.h.

#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1

8 bits Polynomial size

Definition at line 75 of file stm32l4xx_ll_crc.h.

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STM32L486xx HAL User Manual: Input Data Reverse

Defines
Input Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_INDATA_REVERSE_NONE (uint32_t)0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Define Documentation

#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0

Input Data bit reversal done by byte

Definition at line 85 of file stm32l4xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1

Input Data bit reversal done by half-word

Definition at line 86 of file stm32l4xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_NONE (uint32_t)0x00000000U

Input Data bit order not affected

Definition at line 84 of file stm32l4xx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Input Data bit reversal done by word

Definition at line 87 of file stm32l4xx_ll_crc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Output Data Reverse

Defines
Output Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_OUTDATA_REVERSE_NONE (uint32_t)0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Define Documentation

#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Output Data bit reversal done by bit

Definition at line 96 of file stm32l4xx_ll_crc.h.

#define LL_CRC_OUTDATA_REVERSE_NONE (uint32_t)0x00000000U

Output Data bit order not affected

Definition at line 95 of file stm32l4xx_ll_crc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Default CRC generating polynomial value

Defines
Default CRC generating polynomial value
CRC Exported Constants

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . More...

Defines

#define LL_CRC_DEFAULT_CRC32_POLY (uint32_t)0x04C11DB7U

Detailed Description

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Define Documentation

#define LL_CRC_DEFAULT_CRC32_POLY (uint32_t)0x04C11DB7U

Default CRC generating polynomial value

Definition at line 106 of file stm32l4xx_ll_crc.h.

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STM32L486xx HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define LL_CRC_DEFAULT_CRC_INITVALUE (uint32_t)0xFFFFFFFFU

Define Documentation

#define LL_CRC_DEFAULT_CRC_INITVALUE (uint32_t)0xFFFFFFFFU

Default CRC computation initialization value

Definition at line 114 of file stm32l4xx_ll_crc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRC Exported Macros

Defines

#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Define Documentation

#define LL_CRC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 147 of file stm32l4xx_ll_crc.h.

#define LL_CRC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 139 of file stm32l4xx_ll_crc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC Configuration functions

Functions
CRC Configuration functions
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (CRC_TypeDef *CRCx)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (CRC_TypeDef *CRCx)
Return current Programmable polynomial value.

Function Documentation

__STATIC_INLINE uint32_t LL_CRC_GetInitialData ( CRC_TypeDef * CRCx )

Return current Initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to read the correct value
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_GetInitialData
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable initial CRC value register

Definition at line 292 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode ( CRC_TypeDef * CRCx )

Return type of reversal for input data bit order.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_GetInputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD

Definition at line 237 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode ( CRC_TypeDef * CRCx )

Configure the reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_GetOutputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT

Definition at line 264 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef ( CRC_TypeDef * CRCx )

Return current Programmable polynomial value.

Note:
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_GetPolynomialCoef
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable Polynomial value register

Definition at line 323 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize ( CRC_TypeDef * CRCx )

Return size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_GetPolynomialSize
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B

Definition at line 206 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit ( CRC_TypeDef * CRCx )

Reset the CRC calculation unit.

Note:
If Programmable Initial CRC value feature is available, also set the Data Register to the value stored in the CRC_INIT register, otherwise, reset Data Register to its default value.
Reference Manual to LL API cross reference:
CR RESET LL_CRC_ResetCRCCalculationUnit
Parameters:
CRCx CRC Instance
Return values:
None

Definition at line 175 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetInitialData | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InitCrc
 | ) |  |

Initialize the Programmable initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to write the correct value
LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_SetInitialData
Parameters:
CRCx | CRC Instance
InitCrc | Value to be programmed in Programmable initial CRC value register
Return values:
None

Definition at line 279 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetInputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the input data.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_SetInputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD
Return values:
None

Definition at line 222 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_SetOutputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT
Return values:
None

Definition at line 251 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetPolynomialCoef | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolynomCoef
 | ) |  |

Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).

Note:
LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_SetPolynomialCoef
Parameters:
CRCx | CRC Instance
PolynomCoef | Value to be programmed in Programmable Polynomial value register
Return values:
None

Definition at line 309 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetPolynomialSize | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolySize
 | ) |  |

Configure size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_SetPolynomialSize
Parameters:
CRCx CRC Instance
PolySize This parameter can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B
Return values:
None

Definition at line 191 of file stm32l4xx_ll_crc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data_Management

Functions
Data_Management
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.

Function Documentation

__STATIC_INLINE void LL_CRC_FeedData16 | ( | CRC_TypeDef * | CRCx,
 |  | uint16_t | InData
 | ) |  |

Write given 16-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData16
Parameters:
CRCx | CRC Instance
InData | 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
Return values:
None

Definition at line 355 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData32 | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Write given 32-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData32
Parameters:
CRCx | CRC Instance
InData | value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 343 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData8 | ( | CRC_TypeDef * | CRCx,
 |  | uint8_t | InData
 | ) |  |

Write given 8-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData8
Parameters:
CRCx | CRC Instance
InData | 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 367 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_Read_IDR ( CRC_TypeDef * CRCx )

Return data stored in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one byte.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Read_IDR
Parameters:
CRCx CRC Instance
Return values:
Value stored in CRC_IDR register (General-purpose 8-bit data register).

Definition at line 426 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE uint16_t LL_CRC_ReadData16 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

16 bits value is returned.

Note:
This function is expected to be used in a 16 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData16
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (16 bits).

Definition at line 390 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_ReadData32 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

32 bits value is returned.

Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData32
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (32 bits).

Definition at line 378 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData7 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

7 bits value is returned.

Note:
This function is expected to be used in a 7 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData7
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (7 bits).

Definition at line 414 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData8 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

8 bits value is returned.

Note:
This function is expected to be used in a 8 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData8
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (8 bits).

Definition at line 402 of file stm32l4xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_Write_IDR | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Store data in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one byte.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Write_IDR
Parameters:
CRCx | CRC Instance
InData | value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 439 of file stm32l4xx_ll_crc.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Functions

ErrorStatus LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Function Documentation

ErrorStatus LL_CRC_DeInit ( CRC_TypeDef * CRCx )

De-initialize CRC registers (Registers restored to their default values).

Parameters:
CRCx CRC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRC registers are de-initialized
  • ERROR: CRC registers are not de-initialized

Definition at line 81 of file stm32l4xx_ll_crc.c.

References assert_param, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_CRC, and LL_AHB1_GRP1_ReleaseReset().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC

Modules
DAC
STM32L4xx_LL_Driver

Modules

DAC Private Constants
DAC Private Macros
DAC Exported Init structure
DAC Exported Constants
DAC Exported Macros
DAC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for DAC registers.

Register | Bit | Function
CCR | OTRIM1 | LL_DAC_GetTrimmingValue
 |  | LL_DAC_SetTrimmingValue
 | OTRIM2 | LL_DAC_GetTrimmingValue
 |  | LL_DAC_SetTrimmingValue
CR | CEN1 | LL_DAC_GetMode
 |  | LL_DAC_SetMode
 | CEN2 | LL_DAC_GetMode
 |  | LL_DAC_SetMode
 | DMAEN1 | LL_DAC_DisableDMAReq
 |  | LL_DAC_EnableDMAReq
 |  | LL_DAC_IsDMAReqEnabled
 | DMAEN2 | LL_DAC_DisableDMAReq
 |  | LL_DAC_EnableDMAReq
 |  | LL_DAC_IsDMAReqEnabled
 | DMAUDRIE1 | LL_DAC_DisableIT_DMAUDR1
 |  | LL_DAC_EnableIT_DMAUDR1
 |  | LL_DAC_IsEnabledIT_DMAUDR1
 | DMAUDRIE2 | LL_DAC_DisableIT_DMAUDR2
 |  | LL_DAC_EnableIT_DMAUDR2
 |  | LL_DAC_IsEnabledIT_DMAUDR2
 | EN1 | LL_DAC_Disable
 |  | LL_DAC_Enable
 |  | LL_DAC_IsEnabled
 | EN2 | LL_DAC_Disable
 |  | LL_DAC_Enable
 |  | LL_DAC_IsEnabled
 | MAMP1 | LL_DAC_GetWaveNoiseLFSR
 |  | LL_DAC_GetWaveTriangleAmplitude
 |  | LL_DAC_SetWaveNoiseLFSR
 |  | LL_DAC_SetWaveTriangleAmplitude
 | MAMP2 | LL_DAC_GetWaveNoiseLFSR
 |  | LL_DAC_GetWaveTriangleAmplitude
 |  | LL_DAC_SetWaveNoiseLFSR
 |  | LL_DAC_SetWaveTriangleAmplitude
 | MODE1 | LL_DAC_ConfigOutput
 |  | LL_DAC_GetOutputBuffer
 |  | LL_DAC_GetOutputConnection
 |  | LL_DAC_GetOutputMode
 |  | LL_DAC_SetOutputBuffer
 |  | LL_DAC_SetOutputConnection
 |  | LL_DAC_SetOutputMode
 | MODE2 | LL_DAC_ConfigOutput
 |  | LL_DAC_GetOutputBuffer
 |  | LL_DAC_GetOutputConnection
 |  | LL_DAC_GetOutputMode
 |  | LL_DAC_SetOutputBuffer
 |  | LL_DAC_SetOutputConnection
 |  | LL_DAC_SetOutputMode
 | TEN1 | LL_DAC_DisableTrigger
 |  | LL_DAC_EnableTrigger
 |  | LL_DAC_IsTriggerEnabled
 | TEN2 | LL_DAC_DisableTrigger
 |  | LL_DAC_EnableTrigger
 |  | LL_DAC_IsTriggerEnabled
 | TSEL1 | LL_DAC_GetTriggerSource
 |  | LL_DAC_SetTriggerSource
 | TSEL2 | LL_DAC_GetTriggerSource
 |  | LL_DAC_SetTriggerSource
 | WAVE1 | LL_DAC_GetWaveAutoGeneration
 |  | LL_DAC_SetWaveAutoGeneration
 | WAVE2 | LL_DAC_GetWaveAutoGeneration
 |  | LL_DAC_SetWaveAutoGeneration
DHR12L1 | DACC1DHR | LL_DAC_ConvertData12LeftAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR12L2 | DACC2DHR | LL_DAC_ConvertData12LeftAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR12LD | DACC1DHR | LL_DAC_ConvertDualData12LeftAligned
 | DACC2DHR | LL_DAC_ConvertDualData12LeftAligned
DHR12R1 | DACC1DHR | LL_DAC_ConvertData12RightAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR12R2 | DACC2DHR | LL_DAC_ConvertData12RightAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR12RD | DACC1DHR | LL_DAC_ConvertDualData12RightAligned
 | DACC2DHR | LL_DAC_ConvertDualData12RightAligned
DHR8R1 | DACC1DHR | LL_DAC_ConvertData8RightAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR8R2 | DACC2DHR | LL_DAC_ConvertData8RightAligned
 |  | LL_DAC_DMA_GetRegAddr
DHR8RD | DACC1DHR | LL_DAC_ConvertDualData8RightAligned
 | DACC2DHR | LL_DAC_ConvertDualData8RightAligned
DOR1 | DACC1DOR | LL_DAC_RetrieveOutputData
DOR2 | DACC2DOR | LL_DAC_RetrieveOutputData
SHHR | THOLD1 | LL_DAC_GetSampleAndHoldHoldTime
 |  | LL_DAC_SetSampleAndHoldHoldTime
 | THOLD2 | LL_DAC_GetSampleAndHoldHoldTime
 |  | LL_DAC_SetSampleAndHoldHoldTime
SHRR | TREFRESH1 | LL_DAC_GetSampleAndHoldRefreshTime
 |  | LL_DAC_SetSampleAndHoldRefreshTime
 | TREFRESH2 | LL_DAC_GetSampleAndHoldRefreshTime
 |  | LL_DAC_SetSampleAndHoldRefreshTime
SHSR1 | TSAMPLE1 | LL_DAC_GetSampleAndHoldSampleTime
 |  | LL_DAC_SetSampleAndHoldSampleTime
SHSR2 | TSAMPLE2 | LL_DAC_GetSampleAndHoldSampleTime
 |  | LL_DAC_SetSampleAndHoldSampleTime
SR | BWST1 | LL_DAC_IsActiveFlag_BWST1
 | BWST2 | LL_DAC_IsActiveFlag_BWST2
 | CAL_FLAG1 | LL_DAC_IsActiveFlag_CAL1
 | CAL_FLAG2 | LL_DAC_IsActiveFlag_CAL2
 | DMAUDR1 | LL_DAC_ClearFlag_DMAUDR1
 |  | LL_DAC_IsActiveFlag_DMAUDR1
 | DMAUDR2 | LL_DAC_ClearFlag_DMAUDR2
 |  | LL_DAC_IsActiveFlag_DMAUDR2
SWTRIGR | SWTRIG1 | LL_DAC_TrigSWConversion
 | SWTRIG2 | LL_DAC_TrigSWConversion
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Private Constants

Defines
DAC Private Constants
DAC

Defines

#define | DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
#define | DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
#define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
#define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define | DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
#define | DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
#define | DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
#define | DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
#define | DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U)
#define | DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define | DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
#define | DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
#define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define | DAC_REG_SHSR1_REGOFFSET ((uint32_t)0x00000000U) /* Register SHSRx channel 1 taken as reference */
#define | DAC_REG_SHSR2_REGOFFSET ((uint32_t)0x00001000U) /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */
#define | DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
#define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
#define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
#define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
#define | DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */

Define Documentation

#define DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */

Definition at line 75 of file stm32l4xx_ll_dac.h.

#define DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */

Definition at line 76 of file stm32l4xx_ll_dac.h.

#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)

Definition at line 77 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ConfigOutput(), LL_DAC_Disable(), LL_DAC_DisableDMAReq(), LL_DAC_DisableTrigger(), LL_DAC_Enable(), LL_DAC_EnableDMAReq(), LL_DAC_EnableTrigger(), LL_DAC_GetMode(), LL_DAC_GetOutputBuffer(), LL_DAC_GetOutputConnection(), LL_DAC_GetOutputMode(), LL_DAC_GetSampleAndHoldHoldTime(), LL_DAC_GetSampleAndHoldRefreshTime(), LL_DAC_GetTriggerSource(), LL_DAC_GetTrimmingValue(), LL_DAC_GetWaveAutoGeneration(), LL_DAC_GetWaveNoiseLFSR(), LL_DAC_GetWaveTriangleAmplitude(), LL_DAC_Init(), LL_DAC_IsDMAReqEnabled(), LL_DAC_IsEnabled(), LL_DAC_IsTriggerEnabled(), LL_DAC_SetMode(), LL_DAC_SetOutputBuffer(), LL_DAC_SetOutputConnection(), LL_DAC_SetOutputMode(), LL_DAC_SetSampleAndHoldHoldTime(), LL_DAC_SetSampleAndHoldRefreshTime(), LL_DAC_SetTriggerSource(), LL_DAC_SetTrimmingValue(), LL_DAC_SetWaveAutoGeneration(), LL_DAC_SetWaveNoiseLFSR(), and LL_DAC_SetWaveTriangleAmplitude().

#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */

Definition at line 104 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData12LeftAligned().

#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */

Definition at line 103 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData12RightAligned().

#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */

Definition at line 105 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ConvertDualData8RightAligned().

#define DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */

Definition at line 108 of file stm32l4xx_ll_dac.h.

#define DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */

Definition at line 84 of file stm32l4xx_ll_dac.h.

#define DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */

Definition at line 87 of file stm32l4xx_ll_dac.h.

#define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)

Definition at line 90 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned().

#define DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */

Definition at line 83 of file stm32l4xx_ll_dac.h.

#define DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */

Definition at line 86 of file stm32l4xx_ll_dac.h.

#define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)

Definition at line 89 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12RightAligned().

#define DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */

Definition at line 85 of file stm32l4xx_ll_dac.h.

#define DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */

Definition at line 88 of file stm32l4xx_ll_dac.h.

#define DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U)

Definition at line 91 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ConvertData8RightAligned().

#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)

Definition at line 92 of file stm32l4xx_ll_dac.h.

#define DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */

Definition at line 94 of file stm32l4xx_ll_dac.h.

#define DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */

Definition at line 95 of file stm32l4xx_ll_dac.h.

#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)

Definition at line 96 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_RetrieveOutputData().

#define DAC_REG_SHSR1_REGOFFSET ((uint32_t)0x00000000U) /* Register SHSRx channel 1 taken as reference */

Definition at line 98 of file stm32l4xx_ll_dac.h.

#define DAC_REG_SHSR2_REGOFFSET ((uint32_t)0x00001000U) /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */

Definition at line 99 of file stm32l4xx_ll_dac.h.

#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)

Definition at line 100 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_GetSampleAndHoldSampleTime(), and LL_DAC_SetSampleAndHoldSampleTime().

#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */

Definition at line 79 of file stm32l4xx_ll_dac.h.

#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */

Definition at line 80 of file stm32l4xx_ll_dac.h.

#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)

Definition at line 81 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_TrigSWConversion().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)
#define | IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__)
#define | IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)
#define | IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)
#define | IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)
#define | __DAC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define | __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __DAC_MASK_SHIFT | ( | __BITS__,
 |  | __MASK__
 | ) | (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))

Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).

Parameters:
__BITS__ | Bits in register 32 bits
__MASK__ | Mask in register 32 bits
Return values:
Bits in register 32 bits

Definition at line 128 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData12RightAligned(), LL_DAC_ConvertData8RightAligned(), LL_DAC_DMA_GetRegAddr(), LL_DAC_GetSampleAndHoldSampleTime(), LL_DAC_RetrieveOutputData(), and LL_DAC_SetSampleAndHoldSampleTime().

#define __DAC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 139 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ConvertData12LeftAligned(), LL_DAC_ConvertData12RightAligned(), LL_DAC_ConvertData8RightAligned(), LL_DAC_DMA_GetRegAddr(), LL_DAC_GetSampleAndHoldSampleTime(), LL_DAC_RetrieveOutputData(), and LL_DAC_SetSampleAndHoldSampleTime().

#define IS_LL_DAC_CHANNEL | ( | __DACX__,
 |  | __DAC_CHANNEL__
 | ) |
Value:
(                                                                            \
      ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                  \
   || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                                  \
  )

Definition at line 68 of file stm32l4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_BUFFER ( __OUTPUT_BUFFER__ )
Value:
(   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
   || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
  )

Definition at line 118 of file stm32l4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_CONNECTION ( __OUTPUT_CONNECTION__ )
Value:
(   ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                  \
   || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)              \
  )

Definition at line 123 of file stm32l4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_OUTPUT_MODE ( __OUTPUT_MODE__ )
Value:
(   ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                         \
   || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)                \
  )

Definition at line 128 of file stm32l4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_TRIGGER_SOURCE ( __TRIGGER_SOURCE__ )
Value:
(   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)                      \
   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
  )

Definition at line 74 of file stm32l4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG ( __WAVE_AUTO_GENERATION_CONFIG__ )
Value:
(   ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)     \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)  \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)       \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)       \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)       \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)      \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)      \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)      \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)     \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)     \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)     \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)    \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)    \
   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)    \
  )

Definition at line 91 of file stm32l4xx_ll_dac.c.

Referenced by LL_DAC_Init().

#define IS_LL_DAC_WAVE_AUTO_GENER_MODE ( __WAVE_AUTO_GENERATION_MODE__ )
Value:
(   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)     \
   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
  )

Definition at line 85 of file stm32l4xx_ll_dac.c.

Referenced by LL_DAC_Init().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_DAC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DAC_InitTypeDef Struct Reference
DAC Exported Init structure

Structure definition of some features of DAC instance. More...

#include <stm32l4xx_ll_dac.h>

Data Fields

uint32_t | TriggerSource
uint32_t | WaveAutoGeneration
uint32_t | WaveAutoGenerationConfig
uint32_t | OutputBuffer
uint32_t | OutputConnection
uint32_t | OutputMode

Detailed Description

Structure definition of some features of DAC instance.

Definition at line 156 of file stm32l4xx_ll_dac.h.

Field Documentation

uint32_t LL_DAC_InitTypeDef::OutputBuffer

Set the output buffer for the selected DAC channel. This parameter can be a value of DAC channel output buffer

This feature can be modified afterwards using unitary function LL_DAC_SetOutputBuffer().

Definition at line 175 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::OutputConnection

Set the output connection for the selected DAC channel. This parameter can be a value of DAC channel output connection

This feature can be modified afterwards using unitary function LL_DAC_SetOutputConnection().

Definition at line 180 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::OutputMode

Set the output mode normal or sample-and-hold for the selected DAC channel. This parameter can be a value of DAC channel output mode

This feature can be modified afterwards using unitary function LL_DAC_SetOutputMode().

Definition at line 185 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::TriggerSource

Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). This parameter can be a value of DAC trigger source

This feature can be modified afterwards using unitary function LL_DAC_SetTriggerSource().

Definition at line 158 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::WaveAutoGeneration

Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of DAC waveform automatic generation mode

This feature can be modified afterwards using unitary function LL_DAC_SetWaveAutoGeneration().

Definition at line 163 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

uint32_t LL_DAC_InitTypeDef::WaveAutoGenerationConfig

Set the waveform automatic generation mode for the selected DAC channel. If waveform automatic generation mode is set to noise, this parameter can be a value of DAC wave generation - Noise LFSR unmask bits If waveform automatic generation mode is set to triangle, this parameter can be a value of DAC wave generation - Triangle amplitude

Note:
If waveform automatic generation mode is disabled, this parameter is discarded.

This feature can be modified afterwards using unitary function LL_DAC_SetWaveNoiseLFSR() or LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected.

Definition at line 168 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_dac.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC flags

Defines
DAC flags
DAC Exported Constants

Flags defines which can be used with LL_DAC_ReadReg function. More...

Defines

#define | LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)
#define | LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)
#define | LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)
#define | LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)

Detailed Description

Flags defines which can be used with LL_DAC_ReadReg function.

Define Documentation

#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)

DAC channel 1 flag busy writing sample time

Definition at line 209 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_BWST1().

#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)

DAC channel 2 flag busy writing sample time

Definition at line 214 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_BWST2().

#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)

DAC channel 1 flag offset calibration status

Definition at line 208 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_CAL1().

#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)

DAC channel 2 flag offset calibration status

Definition at line 213 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_IsActiveFlag_CAL2().

#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)

DAC channel 1 flag DMA underrun

Definition at line 207 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ClearFlag_DMAUDR1(), and LL_DAC_IsActiveFlag_DMAUDR1().

#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)

DAC channel 2 flag DMA underrun

Definition at line 212 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_ClearFlag_DMAUDR2(), and LL_DAC_IsActiveFlag_DMAUDR2().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC interruptions

Defines
DAC interruptions
DAC Exported Constants

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions. More...

Defines

#define | LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
#define | LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)

Detailed Description

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions.

Define Documentation

#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)

DAC channel 1 interruption DMA underrun

Definition at line 223 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_DisableIT_DMAUDR1(), LL_DAC_EnableIT_DMAUDR1(), and LL_DAC_IsEnabledIT_DMAUDR1().

#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)

DAC channel 2 interruption DMA underrun

Definition at line 224 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_DisableIT_DMAUDR2(), LL_DAC_EnableIT_DMAUDR2(), and LL_DAC_IsEnabledIT_DMAUDR2().

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STM32L486xx HAL User Manual: DAC channels

Defines
DAC channels
DAC Exported Constants

Defines

#define | LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
#define | LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)

Define Documentation

#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)

DAC channel 1

Definition at line 232 of file stm32l4xx_ll_dac.h.

#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)

DAC channel 2

Definition at line 233 of file stm32l4xx_ll_dac.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC operating mode

Defines
DAC operating mode
DAC Exported Constants

Defines

#define | LL_DAC_MODE_NORMAL_OPERATION ((uint32_t)0x00000000U)
#define | LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)

Define Documentation

#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)

DAC channel in mode calibration

Definition at line 242 of file stm32l4xx_ll_dac.h.

#define LL_DAC_MODE_NORMAL_OPERATION ((uint32_t)0x00000000U)

DAC channel in mode normal operation

Definition at line 241 of file stm32l4xx_ll_dac.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC trigger source

Defines
DAC trigger source
DAC Exported Constants

Defines

#define | LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U)
#define | LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

Define Documentation

#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )

DAC channel conversion trigger from external IP: external interrupt line 9.

Definition at line 257 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 )

DAC channel conversion trigger from external IP: TIM2 TRGO.

Definition at line 251 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external IP: TIM4 TRGO.

Definition at line 252 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC channel conversion trigger from external IP: TIM5 TRGO.

Definition at line 253 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U)

DAC channel conversion trigger from external IP: TIM6 TRGO.

Definition at line 254 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 )

DAC channel conversion trigger from external IP: TIM7 TRGO.

Definition at line 255 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0)

DAC channel conversion trigger from external IP: TIM8 TRGO.

Definition at line 256 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)

DAC channel conversion trigger internal (SW start)

Definition at line 250 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

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STM32L486xx HAL User Manual: DAC waveform automatic generation mode

Defines
DAC waveform automatic generation mode
DAC Exported Constants

Defines

#define | LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U)
#define | LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)

Define Documentation

#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0)

DAC channel wave auto generation mode enabled, set generated noise waveform.

Definition at line 266 of file stm32l4xx_ll_dac.h.

#define LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U)

DAC channel wave auto generation mode disabled.

Definition at line 265 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_Init(), and LL_DAC_StructInit().

#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)

DAC channel wave auto generation mode enabled, set generated triangle waveform.

Definition at line 267 of file stm32l4xx_ll_dac.h.

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STM32L486xx HAL User Manual: DAC wave generation - Noise LFSR unmask bits

Defines
DAC wave generation - Noise LFSR unmask bits
DAC Exported Constants

Defines

#define | LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U)

Noise wave generation, unmask LFSR bit0, for the selected DAC channel

Definition at line 275 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel

Definition at line 285 of file stm32l4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel

Definition at line 286 of file stm32l4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel

Definition at line 276 of file stm32l4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel

Definition at line 277 of file stm32l4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel

Definition at line 278 of file stm32l4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )

Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel

Definition at line 279 of file stm32l4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel

Definition at line 280 of file stm32l4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel

Definition at line 281 of file stm32l4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel

Definition at line 282 of file stm32l4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )

Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel

Definition at line 283 of file stm32l4xx_ll_dac.h.

#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel

Definition at line 284 of file stm32l4xx_ll_dac.h.

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STM32L486xx HAL User Manual: DAC wave generation - Triangle amplitude

Defines
DAC wave generation - Triangle amplitude
DAC Exported Constants

Defines

#define | LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U)
#define | LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U)

Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel

Definition at line 294 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel

Definition at line 303 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel

Definition at line 300 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel

Definition at line 297 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel

Definition at line 304 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel

Definition at line 301 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel

Definition at line 295 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )

Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel

Definition at line 298 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel

Definition at line 305 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )

Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel

Definition at line 302 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel

Definition at line 299 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )

Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel

Definition at line 296 of file stm32l4xx_ll_dac.h.

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STM32L486xx HAL User Manual: DAC channel output mode

Defines
DAC channel output mode
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_MODE_NORMAL ((uint32_t)0x00000000U)
#define | LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)

Define Documentation

#define LL_DAC_OUTPUT_MODE_NORMAL ((uint32_t)0x00000000U)

The selected DAC channel output is on mode normal.

Definition at line 313 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)

The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function LL_DAC_ConfigOutput() or LL_DAC_SetOutputMode().

Definition at line 314 of file stm32l4xx_ll_dac.h.

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STM32L486xx HAL User Manual: DAC channel output buffer

Defines
DAC channel output buffer
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U)
#define | LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)

Define Documentation

#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)

The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption

Definition at line 323 of file stm32l4xx_ll_dac.h.

#define LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U)

The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption

Definition at line 322 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

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STM32L486xx HAL User Manual: DAC channel output connection

Defines
DAC channel output connection
DAC Exported Constants

Defines

#define | LL_DAC_OUTPUT_CONNECT_GPIO ((uint32_t)0x00000000U)
#define | LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)

Define Documentation

#define LL_DAC_OUTPUT_CONNECT_GPIO ((uint32_t)0x00000000U)

The selected DAC channel output is connected to external pin

Definition at line 331 of file stm32l4xx_ll_dac.h.

Referenced by LL_DAC_StructInit().

#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)

The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function LL_DAC_SetOutputConnection().

Definition at line 332 of file stm32l4xx_ll_dac.h.

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STM32L486xx HAL User Manual: DAC literals legacy naming

Defines
DAC literals legacy naming
DAC Exported Constants

Defines

#define | LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
#define | LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
#define | LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
#define | LL_DAC_TRIGGER_TIM5_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO)
#define | LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
#define | LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
#define | LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
#define | LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
#define | LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
#define | LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
#define | LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
#define | LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
#define | LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)

Define Documentation

#define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)

Definition at line 353 of file stm32l4xx_ll_dac.h.

#define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)

Definition at line 354 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)

Definition at line 347 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)

Definition at line 340 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)

Definition at line 341 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)

Definition at line 342 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM5_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO)

Definition at line 343 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)

Definition at line 344 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)

Definition at line 345 of file stm32l4xx_ll_dac.h.

#define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)

Definition at line 346 of file stm32l4xx_ll_dac.h.

#define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)

Definition at line 350 of file stm32l4xx_ll_dac.h.

#define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)

Definition at line 349 of file stm32l4xx_ll_dac.h.

#define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)

Definition at line 351 of file stm32l4xx_ll_dac.h.

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STM32L486xx HAL User Manual: DAC channel output resolution

Defines
DAC channel output resolution
DAC Exported Constants

Defines

#define | LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define | LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U)

Define Documentation

#define LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U)

DAC channel resolution 12 bits

Definition at line 363 of file stm32l4xx_ll_dac.h.

#define LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U)

DAC channel resolution 8 bits

Definition at line 364 of file stm32l4xx_ll_dac.h.

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STM32L486xx HAL User Manual: DAC registers compliant with specific purpose

Defines
DAC registers compliant with specific purpose
DAC Exported Constants

Defines

#define | LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK
#define | LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK
#define | LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK

Define Documentation

#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK

DAC channel data holding register 12 bits left aligned

Definition at line 376 of file stm32l4xx_ll_dac.h.

#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK

DAC channel data holding register 12 bits right aligned

Definition at line 375 of file stm32l4xx_ll_dac.h.

#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK

DAC channel data holding register 8 bits right aligned

Definition at line 377 of file stm32l4xx_ll_dac.h.

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STM32L486xx HAL User Manual: Definitions of DAC hardware constraints delays

Defines
Definitions of DAC hardware constraints delays
DAC Exported Constants

Defines

#define | LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 8U)
#define | LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 2U)

Detailed Description

Note:
Only DAC IP HW delays are defined in DAC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 8U)

Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable)

Definition at line 402 of file stm32l4xx_ll_dac.h.

#define LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 2U)

Delay for DAC channel voltage settling time

Definition at line 416 of file stm32l4xx_ll_dac.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common write and read registers macros

Defines
Common write and read registers macros
DAC Exported Macros

Defines

#define | LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DAC register.
#define | LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DAC register.

Define Documentation

#define LL_DAC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DAC register.

Parameters:
__INSTANCE__ | DAC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 450 of file stm32l4xx_ll_dac.h.

#define LL_DAC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DAC register.

Parameters:
__INSTANCE__ | DAC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 442 of file stm32l4xx_ll_dac.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC helper macro

Defines
DAC helper macro
DAC Exported Macros

Defines

#define | __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.
#define | __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.
#define | __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.
#define | __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)
Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Define Documentation

#define __LL_DAC_CALC_VOLTAGE_TO_DATA | ( | __VREFANALOG_VOLTAGE__,
 |  | __DAC_VOLTAGE__,
 |  | __DAC_RESOLUTION__
 | ) |
Value:
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
   / (__VREFANALOG_VOLTAGE__)                                                  \
  )

Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Note:
This helper macro is intended to provide input data in voltage rather than digital value, to be used with LL DAC functions such as LL_DAC_ConvertData12RightAligned().
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__DAC_VOLTAGE__ | Voltage to be generated by DAC channel (unit: mVolt).
__DAC_RESOLUTION__ This parameter can be one of the following values:
  • LL_DAC_RESOLUTION_12B
  • LL_DAC_RESOLUTION_8B
Return values:
DAC conversion data (unit: digital value)

Definition at line 538 of file stm32l4xx_ll_dac.h.

#define __LL_DAC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)

Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.

Example: __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) will return decimal number "1".

Note:
The input can be a value from functions where a channel number is returned.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
1...2

Definition at line 473 of file stm32l4xx_ll_dac.h.

#define __LL_DAC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ )
Value:
(((__DECIMAL_NB__) == 1U)                                                     \
    ? (                                                                        \
       LL_DAC_CHANNEL_1                                                        \
      )                                                                        \
      :                                                                        \
      (((__DECIMAL_NB__) == 2U)                                                 \
        ? (                                                                    \
           LL_DAC_CHANNEL_2                                                    \
          )                                                                    \
          :                                                                    \
          (                                                                    \
           0                                                                   \
          )                                                                    \
      )                                                                        \
  )

Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.

Example: __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) will return a data equivalent to "LL_DAC_CHANNEL_1".

Note:
If the input parameter does not correspond to a DAC channel, this macro returns value '0'.
Parameters:
__DECIMAL_NB__ 1...2
Return values:
Returned value can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2

Definition at line 489 of file stm32l4xx_ll_dac.h.

#define __LL_DAC_DIGITAL_SCALE ( __DAC_RESOLUTION__ ) (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))

Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.

Note:
DAC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__DAC_RESOLUTION__ This parameter can be one of the following values:
  • LL_DAC_RESOLUTION_12B
  • LL_DAC_RESOLUTION_8B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 517 of file stm32l4xx_ll_dac.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of DAC channels

Functions
Configuration of DAC channels
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_SetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
Set the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE uint32_t | LL_DAC_GetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE void | LL_DAC_SetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
Set the offset trimming value for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the offset trimming value for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the conversion trigger source for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the conversion trigger source for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
Set the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE uint32_t | LL_DAC_GetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE void | LL_DAC_SetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE void | LL_DAC_ConfigOutput (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
Set the output for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
Set the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
Set the output buffer for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output buffer state for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
Set the output connection for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output connection for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
Set the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
Set the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
Set the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: refresh time.

Function Documentation

__STATIC_INLINE void LL_DAC_ConfigOutput | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputMode,
 |  | uint32_t | OutputBuffer,
 |  | uint32_t | OutputConnection
 | ) |  |

Set the output for the selected DAC channel.

Note:
This function set several features:
  • mode normal or sample-and-hold
  • buffer
  • connection to GPIO or internal path. These features can also be set individually using dedicated functions:
  • LL_DAC_SetOutputBuffer()
  • LL_DAC_SetOutputMode()
  • LL_DAC_SetOutputConnection()
On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Mode sample-and-hold requires an external capacitor to be connected between DAC channel output and ground. Capacitor value depends on load on DAC channel output and sample-and-hold timings configured. As indication, capacitor typical value is 100nF (refer to device datasheet, parameter "CSH").
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_ConfigOutput
CR MODE2 LL_DAC_ConfigOutput
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputMode This parameter can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
OutputBuffer This parameter can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE
OutputConnection This parameter can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL
Return values:
None

Definition at line 922 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the operating mode for the selected DAC channel: calibration or normal operating mode.

Reference Manual to LL API cross reference:
CR CEN1 LL_DAC_GetMode
CR CEN2 LL_DAC_GetMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_MODE_NORMAL_OPERATION
  • LL_DAC_MODE_CALIBRATION

Definition at line 596 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output buffer state for the selected DAC channel.

Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputBuffer
CR MODE2 LL_DAC_GetOutputBuffer
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE

Definition at line 1011 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output connection for the selected DAC channel.

Note:
On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputConnection
CR MODE2 LL_DAC_GetOutputConnection
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL

Definition at line 1070 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetOutputMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the output mode normal or sample-and-hold for the selected DAC channel.

Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_GetOutputMode
CR MODE2 LL_DAC_GetOutputMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD

Definition at line 968 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: hold time.

Reference Manual to LL API cross reference:
SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime
SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 1150 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: refresh time.

Reference Manual to LL API cross reference:
SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime
SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1187 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the sample-and-hold timing for the selected DAC channel: sample time.

Reference Manual to LL API cross reference:
SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime
SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 1113 of file stm32l4xx_ll_dac.h.

References __DAC_MASK_SHIFT, __DAC_PTR_REG_OFFSET, and DAC_REG_SHSRX_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the conversion trigger source for the selected DAC channel.

Note:
For conversion trigger source to be effective, DAC trigger must be enabled using function LL_DAC_EnableTrigger().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR TSEL1 LL_DAC_GetTriggerSource
CR TSEL2 LL_DAC_GetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM4_TRGO
  • LL_DAC_TRIG_EXT_TIM5_TRGO
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM8_TRGO
  • LL_DAC_TRIGGER_EXT_IT9

Definition at line 696 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the offset trimming value for the selected DAC channel.

Trimming has an impact when output buffer is enabled and is intended to replace factory calibration default values.

Reference Manual to LL API cross reference:
CCR OTRIM1 LL_DAC_GetTrimmingValue
CCR OTRIM2 LL_DAC_GetTrimmingValue
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F

Definition at line 635 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get the waveform automatic generation mode for the selected DAC channel.

Reference Manual to LL API cross reference:
CR WAVE1 LL_DAC_GetWaveAutoGeneration
CR WAVE2 LL_DAC_GetWaveAutoGeneration
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_WAVE_AUTO_GENERATION_NONE
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE

Definition at line 739 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Referenced by LL_DAC_GetWaveMode().

__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).

Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_GetWaveNoiseLFSR
CR MAMP2 LL_DAC_GetWaveNoiseLFSR
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0

Definition at line 805 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.

Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_GetWaveTriangleAmplitude
CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Returned value can be one of the following values:
  • LL_DAC_TRIANGLE_AMPLITUDE_1
  • LL_DAC_TRIANGLE_AMPLITUDE_3
  • LL_DAC_TRIANGLE_AMPLITUDE_7
  • LL_DAC_TRIANGLE_AMPLITUDE_15
  • LL_DAC_TRIANGLE_AMPLITUDE_31
  • LL_DAC_TRIANGLE_AMPLITUDE_63
  • LL_DAC_TRIANGLE_AMPLITUDE_127
  • LL_DAC_TRIANGLE_AMPLITUDE_255
  • LL_DAC_TRIANGLE_AMPLITUDE_511
  • LL_DAC_TRIANGLE_AMPLITUDE_1023
  • LL_DAC_TRIANGLE_AMPLITUDE_2047
  • LL_DAC_TRIANGLE_AMPLITUDE_4095

Definition at line 871 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | ChannelMode
 | ) |  |

Set the operating mode for the selected DAC channel: calibration or normal operating mode.

Reference Manual to LL API cross reference:
CR CEN1 LL_DAC_SetMode
CR CEN2 LL_DAC_SetMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
ChannelMode This parameter can be one of the following values:
  • LL_DAC_MODE_NORMAL_OPERATION
  • LL_DAC_MODE_CALIBRATION
Return values:
None

Definition at line 576 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetOutputBuffer | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputBuffer
 | ) |  |

Set the output buffer for the selected DAC channel.

Note:
On this STM32 serie, when buffer is enabled, its offset can be trimmed: factory calibration default values can be replaced by user trimming values, using function LL_DAC_SetTrimmingValue().
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputBuffer
CR MODE2 LL_DAC_SetOutputBuffer
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputBuffer This parameter can be one of the following values:
  • LL_DAC_OUTPUT_BUFFER_ENABLE
  • LL_DAC_OUTPUT_BUFFER_DISABLE
Return values:
None

Definition at line 992 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetOutputConnection | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputConnection
 | ) |  |

Set the output connection for the selected DAC channel.

Note:
On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state.
  • if output connection is set to internal path and output buffer is enabled (whatever output mode): output connection is also connected to GPIO pin (both connections to GPIO pin and internal path).
  • if output connection is set to GPIO pin, output buffer is disabled, output mode set to sample and hold: output connection is also connected to internal path (both connections to GPIO pin and internal path).
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputConnection
CR MODE2 LL_DAC_SetOutputConnection
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputConnection This parameter can be one of the following values:
  • LL_DAC_OUTPUT_CONNECT_GPIO
  • LL_DAC_OUTPUT_CONNECT_INTERNAL
Return values:
None

Definition at line 1041 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetOutputMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | OutputMode
 | ) |  |

Set the output mode normal or sample-and-hold for the selected DAC channel.

Note:
Mode sample-and-hold requires an external capacitor to be connected between DAC channel output and ground. Capacitor value depends on load on DAC channel output and sample-and-hold timings configured. As indication, capacitor typical value is 100nF (refer to device datasheet, parameter "CSH").
Reference Manual to LL API cross reference:
CR MODE1 LL_DAC_SetOutputMode
CR MODE2 LL_DAC_SetOutputMode
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
OutputMode This parameter can be one of the following values:
  • LL_DAC_OUTPUT_MODE_NORMAL
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
Return values:
None

Definition at line 949 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | HoldTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: hold time.

Reference Manual to LL API cross reference:
SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime
SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
HoldTime | Value between Min_Data=0x000 and Max_Data=0x3FF
Return values:
None

Definition at line 1132 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | RefreshTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: refresh time.

Reference Manual to LL API cross reference:
SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime
SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
RefreshTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1169 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | SampleTime
 | ) |  |

Set the sample-and-hold timing for the selected DAC channel: sample time.

Note:
Sample time must be set when DAC channel is disabled or during DAC operation when DAC channel flag BWSTx is reset, otherwise the setting is ignored. Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
Reference Manual to LL API cross reference:
SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime
SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
SampleTime | Value between Min_Data=0x000 and Max_Data=0x3FF
Return values:
None

Definition at line 1093 of file stm32l4xx_ll_dac.h.

References __DAC_MASK_SHIFT, __DAC_PTR_REG_OFFSET, and DAC_REG_SHSRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetTriggerSource | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriggerSource
 | ) |  |

Set the conversion trigger source for the selected DAC channel.

Note:
For conversion trigger source to be effective, DAC trigger must be enabled using function LL_DAC_EnableTrigger().
To set conversion trigger source, DAC channel must be disabled. Otherwise, the setting is discarded.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR TSEL1 LL_DAC_SetTriggerSource
CR TSEL2 LL_DAC_SetTriggerSource
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
TriggerSource This parameter can be one of the following values:
  • LL_DAC_TRIG_SOFTWARE
  • LL_DAC_TRIG_EXT_TIM2_TRGO
  • LL_DAC_TRIG_EXT_TIM4_TRGO
  • LL_DAC_TRIG_EXT_TIM5_TRGO
  • LL_DAC_TRIG_EXT_TIM6_TRGO
  • LL_DAC_TRIG_EXT_TIM7_TRGO
  • LL_DAC_TRIG_EXT_TIM8_TRGO
  • LL_DAC_TRIG_EXT_EXTI_LINE9
Return values:
None

Definition at line 667 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetTrimmingValue | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TrimmingValue
 | ) |  |

Set the offset trimming value for the selected DAC channel.

Trimming has an impact when output buffer is enabled and is intended to replace factory calibration default values.

Reference Manual to LL API cross reference:
CCR OTRIM1 LL_DAC_SetTrimmingValue
CCR OTRIM2 LL_DAC_SetTrimmingValue
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
TrimmingValue | Value between Min_Data=0x00 and Max_Data=0x1F
Return values:
None

Definition at line 616 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | WaveAutoGeneration
 | ) |  |

Set the waveform automatic generation mode for the selected DAC channel.

Reference Manual to LL API cross reference:
CR WAVE1 LL_DAC_SetWaveAutoGeneration
CR WAVE2 LL_DAC_SetWaveAutoGeneration
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
WaveAutoGeneration This parameter can be one of the following values:
  • LL_DAC_WAVE_AUTO_GENERATION_NONE
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
Return values:
None

Definition at line 718 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Referenced by LL_DAC_SetWaveMode().

__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | NoiseLFSRMask
 | ) |  |

Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_SetWaveNoiseLFSR
CR MAMP2 LL_DAC_SetWaveNoiseLFSR
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
NoiseLFSRMask This parameter can be one of the following values:
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
Return values:
None

Definition at line 775 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | TriangleAmplitude
 | ) |  |

Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.

Note:
For wave generation to be effective, DAC channel wave generation mode must be enabled using function LL_DAC_SetWaveAutoGeneration().
This setting can be set when the selected DAC channel is disabled (otherwise, the setting operation is ignored).
Reference Manual to LL API cross reference:
CR MAMP1 LL_DAC_SetWaveTriangleAmplitude
CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
TriangleAmplitude This parameter can be one of the following values:
  • LL_DAC_TRIANGLE_AMPLITUDE_1
  • LL_DAC_TRIANGLE_AMPLITUDE_3
  • LL_DAC_TRIANGLE_AMPLITUDE_7
  • LL_DAC_TRIANGLE_AMPLITUDE_15
  • LL_DAC_TRIANGLE_AMPLITUDE_31
  • LL_DAC_TRIANGLE_AMPLITUDE_63
  • LL_DAC_TRIANGLE_AMPLITUDE_127
  • LL_DAC_TRIANGLE_AMPLITUDE_255
  • LL_DAC_TRIANGLE_AMPLITUDE_511
  • LL_DAC_TRIANGLE_AMPLITUDE_1023
  • LL_DAC_TRIANGLE_AMPLITUDE_2047
  • LL_DAC_TRIANGLE_AMPLITUDE_4095
Return values:
None

Definition at line 841 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC configuration, legacy functions name

Functions
DAC configuration, legacy functions name
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_SetWaveMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveMode)
__STATIC_INLINE uint32_t | LL_DAC_GetWaveMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)

Function Documentation

__STATIC_INLINE uint32_t LL_DAC_GetWaveMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Definition at line 1207 of file stm32l4xx_ll_dac.h.

References LL_DAC_GetWaveAutoGeneration().

__STATIC_INLINE void LL_DAC_SetWaveMode | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | WaveMode
 | ) |  |

Definition at line 1203 of file stm32l4xx_ll_dac.h.

References LL_DAC_SetWaveAutoGeneration().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Management

Functions
DMA Management
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_EnableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA transfer request of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA transfer request of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMAReqEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA transfer request state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_DMA_GetRegAddr (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE void LL_DAC_DisableDMAReq | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC DMA transfer request of the selected channel.

Note:
To configure DMA source address (peripheral address), use function LL_DAC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_DisableDMAReq
CR DMAEN2 LL_DAC_DisableDMAReq
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1250 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.

Note:
These DAC registers are data holding registers: when DAC conversion is requested, DAC generates a DMA transfer request to have data available in DAC data holding registers.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, (uint32_t)&< array or variable >, LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
Reference Manual to LL API cross reference:
DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr
DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr
DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr
DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Register This parameter can be one of the following values:
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
Return values:
DAC register address

Definition at line 1305 of file stm32l4xx_ll_dac.h.

References __DAC_MASK_SHIFT, and __DAC_PTR_REG_OFFSET.

__STATIC_INLINE void LL_DAC_EnableDMAReq | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC DMA transfer request of the selected channel.

Note:
To configure DMA source address (peripheral address), use function LL_DAC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_EnableDMAReq
CR DMAEN2 LL_DAC_EnableDMAReq
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1232 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC DMA transfer request state of the selected channel.

(0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)

Reference Manual to LL API cross reference:
CR DMAEN1 LL_DAC_IsDMAReqEnabled
CR DMAEN2 LL_DAC_IsDMAReqEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
State of bit (1 or 0).

Definition at line 1267 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Operation on DAC channels

Functions
Operation on DAC channels
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_Enable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC selected channel.
__STATIC_INLINE void | LL_DAC_Disable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC enable state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC trigger of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC trigger of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsTriggerEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC trigger state of the selected channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by software for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12LeftAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData8RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertDualData12RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData12LeftAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData8RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE uint32_t | LL_DAC_RetrieveOutputData (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Retrieve output data currently generated for the selected DAC channel.

Function Documentation

__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned
DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Data | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1490 of file stm32l4xx_ll_dac.h.

References __DAC_MASK_SHIFT, __DAC_PTR_REG_OFFSET, and DAC_REG_DHR12LX_REGOFFSET_MASK.

__STATIC_INLINE void LL_DAC_ConvertData12RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned
DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Data | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1468 of file stm32l4xx_ll_dac.h.

References __DAC_MASK_SHIFT, __DAC_PTR_REG_OFFSET, and DAC_REG_DHR12RX_REGOFFSET_MASK.

__STATIC_INLINE void LL_DAC_ConvertData8RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | uint32_t | Data
 | ) |  |

Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.

Reference Manual to LL API cross reference:
DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned
DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1512 of file stm32l4xx_ll_dac.h.

References __DAC_MASK_SHIFT, __DAC_PTR_REG_OFFSET, and DAC_REG_DHR8RX_REGOFFSET_MASK.

__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.

Reference Manual to LL API cross reference:
DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned
DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x000 and Max_Data=0xFFF
DataChannel2 | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1550 of file stm32l4xx_ll_dac.h.

References DAC_DHR12LD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.

Reference Manual to LL API cross reference:
DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned
DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x000 and Max_Data=0xFFF
DataChannel2 | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 1532 of file stm32l4xx_ll_dac.h.

References DAC_DHR12RD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DataChannel1,
 |  | uint32_t | DataChannel2
 | ) |  |

Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.

Reference Manual to LL API cross reference:
DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned
DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
Parameters:
DACx | DAC instance
DataChannel1 | Value between Min_Data=0x00 and Max_Data=0xFF
DataChannel2 | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1571 of file stm32l4xx_ll_dac.h.

References DAC_DHR8RD_DACC2DHR_BITOFFSET_POS.

__STATIC_INLINE void LL_DAC_Disable | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC selected channel.

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_Disable
CR EN2 LL_DAC_Disable
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1348 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_DisableTrigger | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Disable DAC trigger of the selected channel.

Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_DisableTrigger
CR TEN2 LL_DAC_DisableTrigger
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1406 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_Enable | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC selected channel.

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_Enable
CR EN2 LL_DAC_Enable
Note:
After enable from off state, DAC channel requires a delay for output voltage to reach accuracy +/- 1 LSB. Refer to device datasheet, parameter "tWAKEUP".
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1332 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE void LL_DAC_EnableTrigger | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Enable DAC trigger of the selected channel.

Note:
- If DAC trigger is disabled, DAC conversion is performed automatically once the data holding register is updated, using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": LL_DAC_ConvertData12RightAligned(), ...
  • If DAC trigger is enabled, DAC conversion is performed only when a hardware of software trigger event is occurring. Select trigger source using function LL_DAC_SetTriggerSource().
Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_EnableTrigger
CR TEN2 LL_DAC_EnableTrigger
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1390 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_IsEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC enable state of the selected channel.

(0: DAC channel is disabled, 1: DAC channel is enabled)

Reference Manual to LL API cross reference:
CR EN1 LL_DAC_IsEnabled
CR EN2 LL_DAC_IsEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
State of bit (1 or 0).

Definition at line 1365 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

Referenced by LL_DAC_Init().

__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Get DAC trigger state of the selected channel.

(0: DAC trigger is disabled, 1: DAC trigger is enabled)

Reference Manual to LL API cross reference:
CR TEN1 LL_DAC_IsTriggerEnabled
CR TEN2 LL_DAC_IsTriggerEnabled
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
State of bit (1 or 0).

Definition at line 1423 of file stm32l4xx_ll_dac.h.

References DAC_CR_CHX_BITOFFSET_MASK.

__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Retrieve output data currently generated for the selected DAC channel.

Note:
Whatever alignment and resolution settings (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": LL_DAC_ConvertData12RightAligned(), ...), output data format is 12 bits right aligned (LSB aligned on bit 0).
Reference Manual to LL API cross reference:
DOR1 DACC1DOR LL_DAC_RetrieveOutputData
DOR2 DACC2DOR LL_DAC_RetrieveOutputData
Parameters:
DACx DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1592 of file stm32l4xx_ll_dac.h.

References __DAC_MASK_SHIFT, __DAC_PTR_REG_OFFSET, and DAC_REG_DORX_REGOFFSET_MASK.

__STATIC_INLINE void LL_DAC_TrigSWConversion | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel
 | ) |  |

Trig DAC conversion by software for the selected DAC channel.

Note:
Preliminarily, DAC trigger must be set to software trigger using function LL_DAC_SetTriggerSource() with parameter "LL_DAC_TRIGGER_SOFTWARE". and DAC trigger must be enabled using function LL_DAC_EnableTrigger().
For devices featuring DAC with 2 channels: this function can perform a SW start of both DAC channels simultaneously. Two channels can be selected as parameter. Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
Reference Manual to LL API cross reference:
SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion
SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
Parameters:
DACx DAC instance
DAC_Channel This parameter can a combination of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
Return values:
None

Definition at line 1449 of file stm32l4xx_ll_dac.h.

References DAC_SWTR_CHX_MASK.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG Management

Functions
FLAG Management
DAC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL1 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL2 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST1 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST2 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR1 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR2 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR1 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 1.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR2 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 2.

Function Documentation

__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1 ( DAC_TypeDef * DACx )

Clear DAC underrun flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1678 of file stm32l4xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR1.

__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2 ( DAC_TypeDef * DACx )

Clear DAC underrun flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1689 of file stm32l4xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1 ( DAC_TypeDef * DACx )

Get DAC busy writing sample time flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR BWST1 LL_DAC_IsActiveFlag_BWST1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1634 of file stm32l4xx_ll_dac.h.

References LL_DAC_FLAG_BWST1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2 ( DAC_TypeDef * DACx )

Get DAC busy writing sample time flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR BWST2 LL_DAC_IsActiveFlag_BWST2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1645 of file stm32l4xx_ll_dac.h.

References LL_DAC_FLAG_BWST2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1 ( DAC_TypeDef * DACx )

Get DAC calibration offset flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1612 of file stm32l4xx_ll_dac.h.

References LL_DAC_FLAG_CAL1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2 ( DAC_TypeDef * DACx )

Get DAC calibration offset flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1623 of file stm32l4xx_ll_dac.h.

References LL_DAC_FLAG_CAL2.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1 ( DAC_TypeDef * DACx )

Get DAC underrun flag for DAC channel 1.

Reference Manual to LL API cross reference:
SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1656 of file stm32l4xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR1.

__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2 ( DAC_TypeDef * DACx )

Get DAC underrun flag for DAC channel 2.

Reference Manual to LL API cross reference:
SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1667 of file stm32l4xx_ll_dac.h.

References LL_DAC_FLAG_DMAUDR2.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT management

Functions
IT management
DAC Exported Functions

Functions

__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR1 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR2 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR1 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR2 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR1 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR2 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 2.

Function Documentation

__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1 ( DAC_TypeDef * DACx )

Disable DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1730 of file stm32l4xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2 ( DAC_TypeDef * DACx )

Disable DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1741 of file stm32l4xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1 ( DAC_TypeDef * DACx )

Enable DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1708 of file stm32l4xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2 ( DAC_TypeDef * DACx )

Enable DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
None

Definition at line 1719 of file stm32l4xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1 ( DAC_TypeDef * DACx )

Get DMA underrun interrupt for DAC channel 1.

Reference Manual to LL API cross reference:
CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1752 of file stm32l4xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE1.

__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2 ( DAC_TypeDef * DACx )

Get DMA underrun interrupt for DAC channel 2.

Reference Manual to LL API cross reference:
CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
Parameters:
DACx DAC instance
Return values:
State of bit (1 or 0).

Definition at line 1763 of file stm32l4xx_ll_dac.h.

References LL_DAC_IT_DMAUDRIE2.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Functions

ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC instance.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_DAC_DeInit ( DAC_TypeDef * DACx )

De-initialize registers of the selected DAC instance to their default reset values.

Parameters:
DACx DAC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DAC registers are de-initialized
  • ERROR: not applicable

Definition at line 157 of file stm32l4xx_ll_dac.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_DAC1, and LL_APB1_GRP1_ReleaseReset().

ErrorStatus LL_DAC_Init | ( | DAC_TypeDef * | DACx,
 |  | uint32_t | DAC_Channel,
 |  | LL_DAC_InitTypeDef * | DAC_InitStruct
 | ) |  |

Initialize some features of DAC instance.

Note:
The setting of these parameters by function LL_DAC_Init() is conditioned to DAC state: DAC instance must be disabled.
Parameters:
DACx | DAC instance
DAC_Channel This parameter can be one of the following values:
  • LL_DAC_CHANNEL_1
  • LL_DAC_CHANNEL_2
DAC_InitStruct | Pointer to a LL_DAC_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DAC registers are initialized
  • ERROR: DAC registers are not initialized

Definition at line 185 of file stm32l4xx_ll_dac.c.

References assert_param, DAC_CR_CHX_BITOFFSET_MASK, IS_LL_DAC_CHANNEL, IS_LL_DAC_OUTPUT_BUFFER, IS_LL_DAC_OUTPUT_CONNECTION, IS_LL_DAC_OUTPUT_MODE, IS_LL_DAC_TRIGGER_SOURCE, IS_LL_DAC_WAVE_AUTO_GENER_CONFIG, IS_LL_DAC_WAVE_AUTO_GENER_MODE, LL_DAC_IsEnabled(), LL_DAC_WAVE_AUTO_GENERATION_NONE, LL_DAC_InitTypeDef::OutputBuffer, LL_DAC_InitTypeDef::OutputConnection, LL_DAC_InitTypeDef::OutputMode, LL_DAC_InitTypeDef::TriggerSource, LL_DAC_InitTypeDef::WaveAutoGeneration, and LL_DAC_InitTypeDef::WaveAutoGenerationConfig.

void LL_DAC_StructInit ( LL_DAC_InitTypeDef * DAC_InitStruct )

Set each LL_DAC_InitTypeDef field to default value.

Parameters:
DAC_InitStruct pointer to a LL_DAC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 265 of file stm32l4xx_ll_dac.c.

References LL_DAC_NOISE_LFSR_UNMASK_BIT0, LL_DAC_OUTPUT_BUFFER_ENABLE, LL_DAC_OUTPUT_CONNECT_GPIO, LL_DAC_OUTPUT_MODE_NORMAL, LL_DAC_TRIG_SOFTWARE, LL_DAC_WAVE_AUTO_GENERATION_NONE, LL_DAC_InitTypeDef::OutputBuffer, LL_DAC_InitTypeDef::OutputConnection, LL_DAC_InitTypeDef::OutputMode, LL_DAC_InitTypeDef::TriggerSource, LL_DAC_InitTypeDef::WaveAutoGeneration, and LL_DAC_InitTypeDef::WaveAutoGenerationConfig.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA

Modules
DMA
STM32L4xx_LL_Driver

Modules

DMA Private Variables
DMA Private Constants
DMA Private Macros
DMA Exported Init structure
DMA Exported Constants
DMA Exported Macros
DMA Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for DMA registers.

Register | Bit | Function
CCR | CIRC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMode
 |  | LL_DMA_SetMode
 | DIR | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetDataTransferDirection
 |  | LL_DMA_SetDataTransferDirection
 | EN | LL_DMA_DisableChannel
 |  | LL_DMA_EnableChannel
 |  | LL_DMA_IsEnabledChannel
 | HTIE | LL_DMA_DisableIT_HT
 |  | LL_DMA_EnableIT_HT
 |  | LL_DMA_IsEnabledIT_HT
 | MEM2MEM | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetDataTransferDirection
 |  | LL_DMA_SetDataTransferDirection
 | MINC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMemoryIncMode
 |  | LL_DMA_SetMemoryIncMode
 | MSIZE | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMemorySize
 |  | LL_DMA_SetMemorySize
 | PINC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetPeriphIncMode
 |  | LL_DMA_SetPeriphIncMode
 | PL | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetChannelPriorityLevel
 |  | LL_DMA_SetChannelPriorityLevel
 | PSIZE | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetPeriphSize
 |  | LL_DMA_SetPeriphSize
 | TCIE | LL_DMA_DisableIT_TC
 |  | LL_DMA_EnableIT_TC
 |  | LL_DMA_IsEnabledIT_TC
 | TEIE | LL_DMA_DisableIT_TE
 |  | LL_DMA_EnableIT_TE
 |  | LL_DMA_IsEnabledIT_TE
CMAR | MA | LL_DMA_ConfigAddresses
 |  | LL_DMA_GetM2MDstAddress
 |  | LL_DMA_GetMemoryAddress
 |  | LL_DMA_SetM2MDstAddress
 |  | LL_DMA_SetMemoryAddress
CNDTR | NDT | LL_DMA_GetDataLength
 |  | LL_DMA_SetDataLength
CPAR | PA | LL_DMA_ConfigAddresses
 |  | LL_DMA_GetM2MSrcAddress
 |  | LL_DMA_GetPeriphAddress
 |  | LL_DMA_SetM2MSrcAddress
 |  | LL_DMA_SetPeriphAddress
CSELR | C1S | LL_DMA_GetPeriphRequest
 |  | LL_DMA_SetPeriphRequest
 | C2S | LL_DMA_GetPeriphRequest
 |  | LL_DMA_SetPeriphRequest
 | C3S | LL_DMA_GetPeriphRequest
 |  | LL_DMA_SetPeriphRequest
 | C4S | LL_DMA_GetPeriphRequest
 |  | LL_DMA_SetPeriphRequest
 | C5S | LL_DMA_GetPeriphRequest
 |  | LL_DMA_SetPeriphRequest
 | C6S | LL_DMA_GetPeriphRequest
 |  | LL_DMA_SetPeriphRequest
 | C7S | LL_DMA_GetPeriphRequest
 |  | LL_DMA_SetPeriphRequest
IFCR | CGIF1 | LL_DMA_ClearFlag_GI1
 | CGIF2 | LL_DMA_ClearFlag_GI2
 | CGIF3 | LL_DMA_ClearFlag_GI3
 | CGIF4 | LL_DMA_ClearFlag_GI4
 | CGIF5 | LL_DMA_ClearFlag_GI5
 | CGIF6 | LL_DMA_ClearFlag_GI6
 | CGIF7 | LL_DMA_ClearFlag_GI7
 | CHTIF1 | LL_DMA_ClearFlag_HT1
 | CHTIF2 | LL_DMA_ClearFlag_HT2
 | CHTIF3 | LL_DMA_ClearFlag_HT3
 | CHTIF4 | LL_DMA_ClearFlag_HT4
 | CHTIF5 | LL_DMA_ClearFlag_HT5
 | CHTIF6 | LL_DMA_ClearFlag_HT6
 | CHTIF7 | LL_DMA_ClearFlag_HT7
 | CTCIF1 | LL_DMA_ClearFlag_TC1
 | CTCIF2 | LL_DMA_ClearFlag_TC2
 | CTCIF3 | LL_DMA_ClearFlag_TC3
 | CTCIF4 | LL_DMA_ClearFlag_TC4
 | CTCIF5 | LL_DMA_ClearFlag_TC5
 | CTCIF6 | LL_DMA_ClearFlag_TC6
 | CTCIF7 | LL_DMA_ClearFlag_TC7
 | CTEIF1 | LL_DMA_ClearFlag_TE1
 | CTEIF2 | LL_DMA_ClearFlag_TE2
 | CTEIF3 | LL_DMA_ClearFlag_TE3
 | CTEIF4 | LL_DMA_ClearFlag_TE4
 | CTEIF5 | LL_DMA_ClearFlag_TE5
 | CTEIF6 | LL_DMA_ClearFlag_TE6
 | CTEIF7 | LL_DMA_ClearFlag_TE7
ISR | GIF1 | LL_DMA_IsActiveFlag_GI1
 | GIF2 | LL_DMA_IsActiveFlag_GI2
 | GIF3 | LL_DMA_IsActiveFlag_GI3
 | GIF4 | LL_DMA_IsActiveFlag_GI4
 | GIF5 | LL_DMA_IsActiveFlag_GI5
 | GIF6 | LL_DMA_IsActiveFlag_GI6
 | GIF7 | LL_DMA_IsActiveFlag_GI7
 | HTIF1 | LL_DMA_IsActiveFlag_HT1
 | HTIF2 | LL_DMA_IsActiveFlag_HT2
 | HTIF3 | LL_DMA_IsActiveFlag_HT3
 | HTIF4 | LL_DMA_IsActiveFlag_HT4
 | HTIF5 | LL_DMA_IsActiveFlag_HT5
 | HTIF6 | LL_DMA_IsActiveFlag_HT6
 | HTIF7 | LL_DMA_IsActiveFlag_HT7
 | TCIF1 | LL_DMA_IsActiveFlag_TC1
 | TCIF2 | LL_DMA_IsActiveFlag_TC2
 | TCIF3 | LL_DMA_IsActiveFlag_TC3
 | TCIF4 | LL_DMA_IsActiveFlag_TC4
 | TCIF5 | LL_DMA_IsActiveFlag_TC5
 | TCIF6 | LL_DMA_IsActiveFlag_TC6
 | TCIF7 | LL_DMA_IsActiveFlag_TC7
 | TEIF1 | LL_DMA_IsActiveFlag_TE1
 | TEIF2 | LL_DMA_IsActiveFlag_TE2
 | TEIF3 | LL_DMA_IsActiveFlag_TE3
 | TEIF4 | LL_DMA_IsActiveFlag_TE4
 | TEIF5 | LL_DMA_IsActiveFlag_TE5
 | TEIF6 | LL_DMA_IsActiveFlag_TE6
 | TEIF7 | LL_DMA_IsActiveFlag_TE7
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Private Variables

Variables
DMA Private Variables
DMA

Variables

static const uint8_t CHANNEL_OFFSET_TAB []

Variable Documentation

const uint8_t CHANNEL_OFFSET_TAB[] [static]
Initial value:
{
  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
}

Definition at line 65 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Private Constants

Defines
DMA Private Constants
DMA

Defines

#define | DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
#define | DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))

Define Documentation

#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)

Definition at line 84 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_GetPeriphRequest(), and LL_DMA_SetPeriphRequest().

#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))

Definition at line 87 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_GetPeriphRequest(), and LL_DMA_SetPeriphRequest().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU)
#define | IS_LL_DMA_PERIPHREQUEST(__VALUE__)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Define Documentation

#define IS_LL_DMA_ALL_CHANNEL_INSTANCE | ( | INSTANCE,
 |  | CHANNEL
 | ) |
Value:
((((INSTANCE) == DMA1) && \
                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
                                                         (((INSTANCE) == DMA2) && \
                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))))

Definition at line 104 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

#define IS_LL_DMA_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))

Definition at line 65 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))

Definition at line 82 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))

Definition at line 75 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MODE_NORMAL) || \
                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))

Definition at line 69 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_NBDATA ( __VALUE__ ) ((__VALUE__) <= (uint32_t)0x0000FFFFU)

Definition at line 86 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))

Definition at line 78 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))

Definition at line 72 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHREQUEST ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_REQUEST_0)  || \
                                                 ((__VALUE__) == LL_DMA_REQUEST_1)  || \
                                                 ((__VALUE__) == LL_DMA_REQUEST_2)  || \
                                                 ((__VALUE__) == LL_DMA_REQUEST_3)  || \
                                                 ((__VALUE__) == LL_DMA_REQUEST_4)  || \
                                                 ((__VALUE__) == LL_DMA_REQUEST_5)  || \
                                                 ((__VALUE__) == LL_DMA_REQUEST_6)  || \
                                                 ((__VALUE__) == LL_DMA_REQUEST_7))

Definition at line 88 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PRIORITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))

Definition at line 97 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_Init().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DMA_InitTypeDef Struct Reference
DMA Exported Init structure

#include <stm32l4xx_ll_dma.h>

Data Fields

uint32_t | PeriphOrM2MSrcAddress
uint32_t | MemoryOrM2MDstAddress
uint32_t | Direction
uint32_t | Mode
uint32_t | PeriphOrM2MSrcIncMode
uint32_t | MemoryOrM2MDstIncMode
uint32_t | PeriphOrM2MSrcDataSize
uint32_t | MemoryOrM2MDstDataSize
uint32_t | NbData
uint32_t | PeriphRequest
uint32_t | Priority

Detailed Description

Definition at line 107 of file stm32l4xx_ll_dma.h.

Field Documentation

uint32_t LL_DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of Transfer Direction

This feature can be modified afterwards using unitary function LL_DMA_SetDataTransferDirection().

Definition at line 119 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstAddress

Specifies the memory base address for DMA transfer or as Destination base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 114 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize

Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Memory data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetMemorySize().

Definition at line 150 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode

Specifies whether the Memory address or Destination address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Memory increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetMemoryIncMode().

Definition at line 138 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Mode

Specifies the normal or circular operation mode. This parameter can be a value of Transfer mode

Note:
: The circular buffer mode cannot be used if the memory to memory data transfer direction is configured on the selected Channel

This feature can be modified afterwards using unitary function LL_DMA_SetMode().

Definition at line 125 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::NbData

Specifies the number of data to transfer, in data unit. The data unit is equal to the source buffer configuration set in PeripheralSize or MemorySize parameters depending in the transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF

This feature can be modified afterwards using unitary function LL_DMA_SetDataLength().

Definition at line 156 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress

Specifies the peripheral base address for DMA transfer or as Source base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 109 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize

Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Peripheral data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphSize().

Definition at line 144 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode

Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Peripheral increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphIncMode().

Definition at line 132 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphRequest

Specifies the peripheral request. This parameter can be a value of Transfer peripheral request

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphRequest().

Definition at line 163 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Priority

Specifies the channel priority level. This parameter can be a value of Transfer Priority level

This feature can be modified afterwards using unitary function LL_DMA_SetChannelPriorityLevel().

Definition at line 168 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_dma.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_WriteReg function. More...

Defines

#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
#define | LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
#define | LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
#define | LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7

Detailed Description

Flags defines which can be used with LL_DMA_WriteReg function.

Define Documentation

#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1

Channel 1 global flag

Definition at line 187 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2

Channel 2 global flag

Definition at line 191 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3

Channel 3 global flag

Definition at line 195 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4

Channel 4 global flag

Definition at line 199 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5

Channel 5 global flag

Definition at line 203 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6

Channel 6 global flag

Definition at line 207 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7

Channel 7 global flag

Definition at line 211 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1

Channel 1 half transfer flag

Definition at line 189 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2

Channel 2 half transfer flag

Definition at line 193 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3

Channel 3 half transfer flag

Definition at line 197 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4

Channel 4 half transfer flag

Definition at line 201 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5

Channel 5 half transfer flag

Definition at line 205 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6

Channel 6 half transfer flag

Definition at line 209 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7

Channel 7 half transfer flag

Definition at line 213 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1

Channel 1 transfer complete flag

Definition at line 188 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2

Channel 2 transfer complete flag

Definition at line 192 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3

Channel 3 transfer complete flag

Definition at line 196 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4

Channel 4 transfer complete flag

Definition at line 200 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5

Channel 5 transfer complete flag

Definition at line 204 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6

Channel 6 transfer complete flag

Definition at line 208 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7

Channel 7 transfer complete flag

Definition at line 212 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1

Channel 1 transfer error flag

Definition at line 190 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2

Channel 2 transfer error flag

Definition at line 194 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3

Channel 3 transfer error flag

Definition at line 198 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4

Channel 4 transfer error flag

Definition at line 202 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5

Channel 5 transfer error flag

Definition at line 206 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6

Channel 6 transfer error flag

Definition at line 210 of file stm32l4xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7

Channel 7 transfer error flag

Definition at line 214 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_ReadReg function. More...

Defines

#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_ISR_GIF7 DMA_ISR_GIF7
#define | LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
#define | LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
#define | LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7

Detailed Description

Flags defines which can be used with LL_DMA_ReadReg function.

Define Documentation

#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1

Channel 1 global flag

Definition at line 223 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2

Channel 2 global flag

Definition at line 227 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3

Channel 3 global flag

Definition at line 231 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4

Channel 4 global flag

Definition at line 235 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5

Channel 5 global flag

Definition at line 239 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6

Channel 6 global flag

Definition at line 243 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7

Channel 7 global flag

Definition at line 247 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1

Channel 1 half transfer flag

Definition at line 225 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2

Channel 2 half transfer flag

Definition at line 229 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3

Channel 3 half transfer flag

Definition at line 233 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4

Channel 4 half transfer flag

Definition at line 237 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5

Channel 5 half transfer flag

Definition at line 241 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6

Channel 6 half transfer flag

Definition at line 245 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7

Channel 7 half transfer flag

Definition at line 249 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1

Channel 1 transfer complete flag

Definition at line 224 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2

Channel 2 transfer complete flag

Definition at line 228 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3

Channel 3 transfer complete flag

Definition at line 232 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4

Channel 4 transfer complete flag

Definition at line 236 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5

Channel 5 transfer complete flag

Definition at line 240 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6

Channel 6 transfer complete flag

Definition at line 244 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7

Channel 7 transfer complete flag

Definition at line 248 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1

Channel 1 transfer error flag

Definition at line 226 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2

Channel 2 transfer error flag

Definition at line 230 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3

Channel 3 transfer error flag

Definition at line 234 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4

Channel 4 transfer error flag

Definition at line 238 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5

Channel 5 transfer error flag

Definition at line 242 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6

Channel 6 transfer error flag

Definition at line 246 of file stm32l4xx_ll_dma.h.

#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7

Channel 7 transfer error flag

Definition at line 250 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
DMA Exported Constants

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions. More...

Defines

#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE

Detailed Description

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

Define Documentation

#define LL_DMA_CCR_HTIE DMA_CCR_HTIE

Half Transfer interrupt

Definition at line 260 of file stm32l4xx_ll_dma.h.

#define LL_DMA_CCR_TCIE DMA_CCR_TCIE

Transfer complete interrupt

Definition at line 259 of file stm32l4xx_ll_dma.h.

#define LL_DMA_CCR_TEIE DMA_CCR_TEIE

Transfer error interrupt

Definition at line 261 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CHANNEL

Defines
CHANNEL
DMA Exported Constants

Defines

#define | LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U)
#define | LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U)
#define | LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U)
#define | LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U)
#define | LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U)
#define | LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U)
#define | LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U)
#define | LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U)

Define Documentation

#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U)

DMA Channel 1

Definition at line 269 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U)

DMA Channel 2

Definition at line 270 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U)

DMA Channel 3

Definition at line 271 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U)

DMA Channel 4

Definition at line 272 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U)

DMA Channel 5

Definition at line 273 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U)

DMA Channel 6

Definition at line 274 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U)

DMA Channel 7

Definition at line 275 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U)

DMA Channel all (used only for function LL_DMA_DeInit().

Definition at line 277 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Transfer Direction

Defines
Transfer Direction
DMA Exported Constants

Defines

#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Define Documentation

#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Memory to memory direction

Definition at line 288 of file stm32l4xx_ll_dma.h.

#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR

Memory to peripheral direction

Definition at line 287 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_ConfigAddresses().

#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)

Peripheral to memory direction

Definition at line 286 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Transfer mode

Defines
Transfer mode
DMA Exported Constants

Defines

#define | LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U)
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Define Documentation

#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Circular Mode

Definition at line 297 of file stm32l4xx_ll_dma.h.

#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U)

Normal Mode

Definition at line 296 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral increment mode

Defines
Peripheral increment mode
DMA Exported Constants

Defines

#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U)

Define Documentation

#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC

Peripheral increment mode Enable

Definition at line 305 of file stm32l4xx_ll_dma.h.

#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U)

Peripheral increment mode Disable

Definition at line 306 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Memory increment mode

Defines
Memory increment mode
DMA Exported Constants

Defines

#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U)

Define Documentation

#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC

Memory increment mode Enable

Definition at line 314 of file stm32l4xx_ll_dma.h.

#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U)

Memory increment mode Disable

Definition at line 315 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral data alignment

Defines
Peripheral data alignment
DMA Exported Constants

Defines

#define | LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Define Documentation

#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)

Peripheral data alignment : Byte

Definition at line 323 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0

Peripheral data alignment : HalfWord

Definition at line 324 of file stm32l4xx_ll_dma.h.

#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Peripheral data alignment : Word

Definition at line 325 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Memory data alignment

Defines
Memory data alignment
DMA Exported Constants

Defines

#define | LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Define Documentation

#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)

Memory data alignment : Byte

Definition at line 333 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0

Memory data alignment : HalfWord

Definition at line 334 of file stm32l4xx_ll_dma.h.

#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Memory data alignment : Word

Definition at line 335 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Transfer Priority level

Defines
Transfer Priority level
DMA Exported Constants

Defines

#define | LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Define Documentation

#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1

Priority level : High

Definition at line 345 of file stm32l4xx_ll_dma.h.

#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U)

Priority level : Low

Definition at line 343 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0

Priority level : Medium

Definition at line 344 of file stm32l4xx_ll_dma.h.

#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Priority level : Very_High

Definition at line 346 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Transfer peripheral request

Defines
Transfer peripheral request
DMA Exported Constants

Defines

#define | LL_DMA_REQUEST_0 ((uint32_t)0x00000000U)
#define | LL_DMA_REQUEST_1 ((uint32_t)0x00000001U)
#define | LL_DMA_REQUEST_2 ((uint32_t)0x00000002U)
#define | LL_DMA_REQUEST_3 ((uint32_t)0x00000003U)
#define | LL_DMA_REQUEST_4 ((uint32_t)0x00000004U)
#define | LL_DMA_REQUEST_5 ((uint32_t)0x00000005U)
#define | LL_DMA_REQUEST_6 ((uint32_t)0x00000006U)
#define | LL_DMA_REQUEST_7 ((uint32_t)0x00000007U)

Define Documentation

#define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U)

DMA peripheral request 0

Definition at line 354 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit(), and LL_DMA_StructInit().

#define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U)

DMA peripheral request 1

Definition at line 355 of file stm32l4xx_ll_dma.h.

#define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U)

DMA peripheral request 2

Definition at line 356 of file stm32l4xx_ll_dma.h.

#define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U)

DMA peripheral request 3

Definition at line 357 of file stm32l4xx_ll_dma.h.

#define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U)

DMA peripheral request 4

Definition at line 358 of file stm32l4xx_ll_dma.h.

#define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U)

DMA peripheral request 5

Definition at line 359 of file stm32l4xx_ll_dma.h.

#define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U)

DMA peripheral request 6

Definition at line 360 of file stm32l4xx_ll_dma.h.

#define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U)

DMA peripheral request 7

Definition at line 361 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMA Exported Macros

Defines

#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.

Define Documentation

#define LL_DMA_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 393 of file stm32l4xx_ll_dma.h.

#define LL_DMA_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 385 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Convert DMAxChannely

Defines
Convert DMAxChannely
DMA Exported Macros

Defines

#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Define Documentation

#define __LL_DMA_GET_CHANNEL ( __CHANNEL_INSTANCE__ )
Value:
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
 LL_DMA_CHANNEL_7)

Convert DMAx_Channely into LL_DMA_CHANNEL_y.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
LL_DMA_CHANNEL_y

Definition at line 420 of file stm32l4xx_ll_dma.h.

#define __LL_DMA_GET_CHANNEL_INSTANCE | ( | __DMA_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
 DMA2_Channel7)

Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Parameters:
__DMA_INSTANCE__ | DMAx
__CHANNEL__ | LL_DMA_CHANNEL_y
Return values:
DMAx_Channely

Definition at line 468 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define __LL_DMA_GET_INSTANCE ( __CHANNEL_INSTANCE__ ) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)

Convert DMAx_Channely into DMAx.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
DMAx

Definition at line 407 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration

Functions
Configuration
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_DMA_SetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
Set DMA request for DMA instance on Channel x.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA request for DMA instance on Channel x.

Function Documentation

__STATIC_INLINE void LL_DMA_ConfigAddresses | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Direction
 | ) |  |

Configure the Source and Destination addresses.

Note:
Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_ConfigAddresses
CMAR MA LL_DMA_ConfigAddresses
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
SrcAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
DstAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 1015 of file stm32l4xx_ll_dma.h.

References LL_DMA_DIRECTION_MEMORY_TO_PERIPH.

__STATIC_INLINE void LL_DMA_ConfigTransfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure all parameters link to DMA transfer.

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_ConfigTransfer
CCR MEM2MEM LL_DMA_ConfigTransfer
CCR CIRC LL_DMA_ConfigTransfer
CCR PINC LL_DMA_ConfigTransfer
CCR MINC LL_DMA_ConfigTransfer
CCR PSIZE LL_DMA_ConfigTransfer
CCR MSIZE LL_DMA_ConfigTransfer
CCR PL LL_DMA_ConfigTransfer
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Configuration This parameter must be a combination of all the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH or LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  • LL_DMA_MODE_NORMAL or LL_DMA_MODE_CIRCULAR
  • LL_DMA_PERIPH_INCREMENT or LL_DMA_PERIPH_NOINCREMENT
  • LL_DMA_MEMORY_INCREMENT or LL_DMA_MEMORY_NOINCREMENT
  • LL_DMA_PDATAALIGN_BYTE or LL_DMA_PDATAALIGN_HALFWORD or LL_DMA_PDATAALIGN_WORD
  • LL_DMA_MDATAALIGN_BYTE or LL_DMA_MDATAALIGN_HALFWORD or LL_DMA_MDATAALIGN_WORD
  • LL_DMA_PRIORITY_LOW or LL_DMA_PRIORITY_MEDIUM or LL_DMA_PRIORITY_HIGH or LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 612 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_DisableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_DisableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 558 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_EnableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 539 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_GetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH

Definition at line 942 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Number of data to transfer.

Note:
Once the channel is enabled, the return value indicate the remaining bytes to be transmitted.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_GetDataLength
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 987 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_GetDataTransferDirection
CCR MEM2MEM LL_DMA_GetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Definition at line 662 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetM2MDstAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1202 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetM2MSrcAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1181 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetMemoryAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1095 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_GetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT

Definition at line 799 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_GetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD

Definition at line 893 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get DMA mode circular or normal.

Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_GetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR

Definition at line 709 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetPeriphAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1116 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_GetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT

Definition at line 754 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get DMA request for DMA instance on Channel x.

Reference Manual to LL API cross reference:
CSELR C1S LL_DMA_GetPeriphRequest
CSELR C2S LL_DMA_GetPeriphRequest
CSELR C3S LL_DMA_GetPeriphRequest
CSELR C4S LL_DMA_GetPeriphRequest
CSELR C5S LL_DMA_GetPeriphRequest
CSELR C6S LL_DMA_GetPeriphRequest
CSELR C7S LL_DMA_GetPeriphRequest
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_REQUEST_0
  • LL_DMA_REQUEST_1
  • LL_DMA_REQUEST_2
  • LL_DMA_REQUEST_3
  • LL_DMA_REQUEST_4
  • LL_DMA_REQUEST_5
  • LL_DMA_REQUEST_6
  • LL_DMA_REQUEST_7

Definition at line 1272 of file stm32l4xx_ll_dma.h.

References DMA_CSELR_OFFSET, and DMA_POSITION_CSELR_CXS.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_GetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD

Definition at line 846 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if DMA channel is enabled or disabled.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_IsEnabledChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 577 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Priority
 | ) |  |

Set Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_SetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Priority This parameter can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 918 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | NbData
 | ) |  |

Set Number of data to transfer.

Note:
This action has no effect if channel is enabled.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_SetDataLength
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
NbData | Between Min_Data = 0 and Max_Data = 0x0000FFFF
Return values:
None

Definition at line 965 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Direction
 | ) |  |

Set Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_SetDataTransferDirection
CCR MEM2MEM LL_DMA_SetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 638 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetM2MDstAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1160 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetM2MSrcAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1138 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetMemoryAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1052 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstIncMode
 | ) |  |

Set Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_SetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryOrM2MDstIncMode This parameter can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT
Return values:
None

Definition at line 777 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstDataSize
 | ) |  |

Set Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_SetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryOrM2MDstDataSize This parameter can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD
Return values:
None

Definition at line 870 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Set DMA mode circular or normal.

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel.
Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_SetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Mode This parameter can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR
Return values:
None

Definition at line 687 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphAddress
 | ) |  |

Set the Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetPeriphAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1074 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcIncMode
 | ) |  |

Set Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_SetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphOrM2MSrcIncMode This parameter can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT
Return values:
None

Definition at line 732 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphRequest | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphRequest
 | ) |  |

Set DMA request for DMA instance on Channel x.

Note:
Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
Reference Manual to LL API cross reference:
CSELR C1S LL_DMA_SetPeriphRequest
CSELR C2S LL_DMA_SetPeriphRequest
CSELR C3S LL_DMA_SetPeriphRequest
CSELR C4S LL_DMA_SetPeriphRequest
CSELR C5S LL_DMA_SetPeriphRequest
CSELR C6S LL_DMA_SetPeriphRequest
CSELR C7S LL_DMA_SetPeriphRequest
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphRequest This parameter can be one of the following values:
  • LL_DMA_REQUEST_0
  • LL_DMA_REQUEST_1
  • LL_DMA_REQUEST_2
  • LL_DMA_REQUEST_3
  • LL_DMA_REQUEST_4
  • LL_DMA_REQUEST_5
  • LL_DMA_REQUEST_6
  • LL_DMA_REQUEST_7
Return values:
None

Definition at line 1238 of file stm32l4xx_ll_dma.h.

References DMA_CSELR_OFFSET, and DMA_POSITION_CSELR_CXS.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcDataSize
 | ) |  |

Set Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_SetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphOrM2MSrcDataSize This parameter can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD
Return values:
None

Definition at line 823 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMA Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI7 (DMA_TypeDef *DMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI7 (DMA_TypeDef *DMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer error flag.

Function Documentation

__STATIC_INLINE void LL_DMA_ClearFlag_GI1 ( DMA_TypeDef * DMAx )

Clear Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF1 LL_DMA_ClearFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1600 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI2 ( DMA_TypeDef * DMAx )

Clear Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF2 LL_DMA_ClearFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1611 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI3 ( DMA_TypeDef * DMAx )

Clear Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF3 LL_DMA_ClearFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1622 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI4 ( DMA_TypeDef * DMAx )

Clear Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF4 LL_DMA_ClearFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1633 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI5 ( DMA_TypeDef * DMAx )

Clear Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF5 LL_DMA_ClearFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1644 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI6 ( DMA_TypeDef * DMAx )

Clear Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF6 LL_DMA_ClearFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1655 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI7 ( DMA_TypeDef * DMAx )

Clear Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF7 LL_DMA_ClearFlag_GI7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1666 of file stm32l4xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_HT1 ( DMA_TypeDef * DMAx )

Clear Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF1 LL_DMA_ClearFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1754 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT2 ( DMA_TypeDef * DMAx )

Clear Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF2 LL_DMA_ClearFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1765 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT3 ( DMA_TypeDef * DMAx )

Clear Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF3 LL_DMA_ClearFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1776 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT4 ( DMA_TypeDef * DMAx )

Clear Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF4 LL_DMA_ClearFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1787 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT5 ( DMA_TypeDef * DMAx )

Clear Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF5 LL_DMA_ClearFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1798 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT6 ( DMA_TypeDef * DMAx )

Clear Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF6 LL_DMA_ClearFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1809 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT7 ( DMA_TypeDef * DMAx )

Clear Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF7 LL_DMA_ClearFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1820 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF1 LL_DMA_ClearFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1677 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF2 LL_DMA_ClearFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1688 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF3 LL_DMA_ClearFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1699 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF4 LL_DMA_ClearFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1710 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF5 LL_DMA_ClearFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1721 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF6 LL_DMA_ClearFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1732 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC7 ( DMA_TypeDef * DMAx )

Clear Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF7 LL_DMA_ClearFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1743 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF1 LL_DMA_ClearFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1831 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF2 LL_DMA_ClearFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1842 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF3 LL_DMA_ClearFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1853 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF4 LL_DMA_ClearFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1864 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF5 LL_DMA_ClearFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1875 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF6 LL_DMA_ClearFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1886 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE7 ( DMA_TypeDef * DMAx )

Clear Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF7 LL_DMA_ClearFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1897 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1 ( DMA_TypeDef * DMAx )

Get Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF1 LL_DMA_IsActiveFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1292 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2 ( DMA_TypeDef * DMAx )

Get Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF2 LL_DMA_IsActiveFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1303 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3 ( DMA_TypeDef * DMAx )

Get Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF3 LL_DMA_IsActiveFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1314 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4 ( DMA_TypeDef * DMAx )

Get Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF4 LL_DMA_IsActiveFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1325 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5 ( DMA_TypeDef * DMAx )

Get Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF5 LL_DMA_IsActiveFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1336 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6 ( DMA_TypeDef * DMAx )

Get Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF6 LL_DMA_IsActiveFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1347 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7 ( DMA_TypeDef * DMAx )

Get Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF7 LL_DMA_IsActiveFlag_GI7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1358 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1 ( DMA_TypeDef * DMAx )

Get Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF1 LL_DMA_IsActiveFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1446 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2 ( DMA_TypeDef * DMAx )

Get Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF2 LL_DMA_IsActiveFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1457 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3 ( DMA_TypeDef * DMAx )

Get Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF3 LL_DMA_IsActiveFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1468 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4 ( DMA_TypeDef * DMAx )

Get Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF4 LL_DMA_IsActiveFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1479 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5 ( DMA_TypeDef * DMAx )

Get Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF5 LL_DMA_IsActiveFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1490 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6 ( DMA_TypeDef * DMAx )

Get Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF6 LL_DMA_IsActiveFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1501 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7 ( DMA_TypeDef * DMAx )

Get Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF7 LL_DMA_IsActiveFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1512 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF1 LL_DMA_IsActiveFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1369 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF2 LL_DMA_IsActiveFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1380 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF3 LL_DMA_IsActiveFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1391 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF4 LL_DMA_IsActiveFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1402 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF5 LL_DMA_IsActiveFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1413 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF6 LL_DMA_IsActiveFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1424 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7 ( DMA_TypeDef * DMAx )

Get Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF7 LL_DMA_IsActiveFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1435 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF1 LL_DMA_IsActiveFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1523 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF2 LL_DMA_IsActiveFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1534 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF3 LL_DMA_IsActiveFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1545 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF4 LL_DMA_IsActiveFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1556 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF5 LL_DMA_IsActiveFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1567 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF6 LL_DMA_IsActiveFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1578 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7 ( DMA_TypeDef * DMAx )

Get Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF7 LL_DMA_IsActiveFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1589 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT_Management

Functions
IT_Management
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_DMA_DisableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_DisableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1999 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_DisableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1980 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_DisableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 2018 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_EnableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1942 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_EnableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1923 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_EnableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1961 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Half transfer Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_IsEnabledIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2057 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer complete Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_IsEnabledIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2037 of file stm32l4xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer error Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_IsEnabledIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2077 of file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Functions

uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Function Documentation

uint32_t LL_DMA_DeInit | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

De-initialize the DMA registers to their default reset values.

Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
  • LL_DMA_CHANNEL_ALL
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are de-initialized
  • ERROR: DMA registers are not de-initialized

Definition at line 177 of file stm32l4xx_ll_dma.c.

References __LL_DMA_GET_CHANNEL_INSTANCE, assert_param, IS_LL_DMA_ALL_CHANNEL_INSTANCE, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_DMA1, LL_AHB1_GRP1_PERIPH_DMA2, LL_AHB1_GRP1_ReleaseReset(), LL_DMA_CHANNEL_1, LL_DMA_CHANNEL_2, LL_DMA_CHANNEL_3, LL_DMA_CHANNEL_4, LL_DMA_CHANNEL_5, LL_DMA_CHANNEL_6, LL_DMA_CHANNEL_7, LL_DMA_CHANNEL_ALL, LL_DMA_ClearFlag_GI1(), LL_DMA_ClearFlag_GI2(), LL_DMA_ClearFlag_GI3(), LL_DMA_ClearFlag_GI4(), LL_DMA_ClearFlag_GI5(), LL_DMA_ClearFlag_GI6(), LL_DMA_ClearFlag_GI7(), LL_DMA_REQUEST_0, LL_DMA_SetPeriphRequest(), and LL_DMA_WriteReg.

uint32_t LL_DMA_Init | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | LL_DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initialize the DMA registers according to the specified parameters in DMA_InitStruct.

Note:
To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
  • __LL_DMA_GET_INSTANCE
  • __LL_DMA_GET_CHANNEL
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
DMA_InitStruct | pointer to a LL_DMA_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are initialized
  • ERROR: Not applicable

Definition at line 296 of file stm32l4xx_ll_dma.c.

References assert_param, LL_DMA_InitTypeDef::Direction, IS_LL_DMA_ALL_CHANNEL_INSTANCE, IS_LL_DMA_DIRECTION, IS_LL_DMA_MEMORYDATASIZE, IS_LL_DMA_MEMORYINCMODE, IS_LL_DMA_MODE, IS_LL_DMA_NBDATA, IS_LL_DMA_PERIPHDATASIZE, IS_LL_DMA_PERIPHINCMODE, IS_LL_DMA_PERIPHREQUEST, IS_LL_DMA_PRIORITY, LL_DMA_ConfigTransfer(), LL_DMA_SetDataLength(), LL_DMA_SetMemoryAddress(), LL_DMA_SetPeriphAddress(), LL_DMA_SetPeriphRequest(), LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_DMA_InitTypeDef::PeriphRequest, and LL_DMA_InitTypeDef::Priority.

void LL_DMA_StructInit ( LL_DMA_InitTypeDef * DMA_InitStruct )

Set each LL_DMA_InitTypeDef field to default value.

Parameters:
DMA_InitStruct Pointer to a LL_DMA_InitTypeDef structure.
Return values:
None

Definition at line 364 of file stm32l4xx_ll_dma.c.

References LL_DMA_InitTypeDef::Direction, LL_DMA_DIRECTION_PERIPH_TO_MEMORY, LL_DMA_MDATAALIGN_BYTE, LL_DMA_MEMORY_NOINCREMENT, LL_DMA_MODE_NORMAL, LL_DMA_PDATAALIGN_BYTE, LL_DMA_PERIPH_NOINCREMENT, LL_DMA_PRIORITY_LOW, LL_DMA_REQUEST_0, LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_DMA_InitTypeDef::PeriphRequest, and LL_DMA_InitTypeDef::Priority.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: EXTI

Modules
EXTI
STM32L4xx_LL_Driver

Modules

EXTI Private Macros
EXTI Exported Init structure
EXTI Exported Constants
EXTI Exported Macros
EXTI Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for EXTI registers.

Register | Bit | Function
EMR1 | EMx | LL_EXTI_DisableEvent_0_31
 |  | LL_EXTI_EnableEvent_0_31
 |  | LL_EXTI_IsEnabledEvent_0_31
EMR2 | EMx | LL_EXTI_DisableEvent_32_63
 |  | LL_EXTI_EnableEvent_32_63
 |  | LL_EXTI_IsEnabledEvent_32_63
FTSR1 | FTx | LL_EXTI_DisableFallingTrig_0_31
 |  | LL_EXTI_EnableFallingTrig_0_31
 |  | LL_EXTI_IsEnabledFallingTrig_0_31
FTSR2 | FTx | LL_EXTI_DisableFallingTrig_32_63
 |  | LL_EXTI_EnableFallingTrig_32_63
 |  | LL_EXTI_IsEnabledFallingTrig_32_63
IMR1 | IMx | LL_EXTI_DisableIT_0_31
 |  | LL_EXTI_EnableIT_0_31
 |  | LL_EXTI_IsEnabledIT_0_31
IMR2 | IMx | LL_EXTI_DisableIT_32_63
 |  | LL_EXTI_EnableIT_32_63
 |  | LL_EXTI_IsEnabledIT_32_63
PR1 | PIFx | LL_EXTI_ClearFlag_0_31
 |  | LL_EXTI_IsActiveFlag_0_31
 |  | LL_EXTI_ReadFlag_0_31
PR2 | PIFx | LL_EXTI_ClearFlag_32_63
 |  | LL_EXTI_IsActiveFlag_32_63
 |  | LL_EXTI_ReadFlag_32_63
RTSR1 | RTx | LL_EXTI_DisableRisingTrig_0_31
 |  | LL_EXTI_EnableRisingTrig_0_31
 |  | LL_EXTI_IsEnabledRisingTrig_0_31
RTSR2 | RTx | LL_EXTI_DisableRisingTrig_32_63
 |  | LL_EXTI_EnableRisingTrig_32_63
 |  | LL_EXTI_IsEnabledRisingTrig_32_63
SWIER1 | SWIx | LL_EXTI_GenerateSWI_0_31
SWIER2 | SWIx | LL_EXTI_GenerateSWI_32_63
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Define Documentation

#define IS_LL_EXTI_LINE_0_31 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)

Definition at line 65 of file stm32l4xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_LINE_32_63 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)

Definition at line 66 of file stm32l4xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_MODE_IT)            \
                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))

Definition at line 68 of file stm32l4xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_TRIGGER ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))

Definition at line 73 of file stm32l4xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_EXTI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_EXTI_InitTypeDef Struct Reference
EXTI Exported Init structure

#include <stm32l4xx_ll_exti.h>

Data Fields

uint32_t | Line_0_31
uint32_t | Line_32_63
FunctionalState | LineCommand
uint8_t | Mode
uint8_t | Trigger

Detailed Description

Definition at line 76 of file stm32l4xx_ll_exti.h.

Field Documentation

uint32_t LL_EXTI_InitTypeDef::Line_0_31

Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 This parameter can be any combination of LINE

Definition at line 79 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint32_t LL_EXTI_InitTypeDef::Line_32_63

Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 This parameter can be any combination of LINE

Definition at line 82 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

FunctionalState LL_EXTI_InitTypeDef::LineCommand

Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE

Definition at line 85 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Mode

Specifies the mode for the EXTI lines. This parameter can be a value of Mode.

Definition at line 88 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Trigger

Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of Edge Trigger.

Definition at line 91 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_exti.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LINE

Defines
LINE
EXTI Exported Constants

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR1_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR1_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR1_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR1_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR1_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR1_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR1_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR1_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR1_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR1_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR1_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR1_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR1_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR1_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR1_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR1_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR1_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR1_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR1_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR1_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR1_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR1_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR1_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR1_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR1_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR1_IM25
#define | LL_EXTI_LINE_26 EXTI_IMR1_IM26
#define | LL_EXTI_LINE_27 EXTI_IMR1_IM27
#define | LL_EXTI_LINE_28 EXTI_IMR1_IM28
#define | LL_EXTI_LINE_29 EXTI_IMR1_IM29
#define | LL_EXTI_LINE_30 EXTI_IMR1_IM30
#define | LL_EXTI_LINE_31 EXTI_IMR1_IM31
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM
#define | LL_EXTI_LINE_32 EXTI_IMR2_IM32
#define | LL_EXTI_LINE_33 EXTI_IMR2_IM33
#define | LL_EXTI_LINE_34 EXTI_IMR2_IM34
#define | LL_EXTI_LINE_35 EXTI_IMR2_IM35
#define | LL_EXTI_LINE_36 EXTI_IMR2_IM36
#define | LL_EXTI_LINE_37 EXTI_IMR2_IM37
#define | LL_EXTI_LINE_38 EXTI_IMR2_IM38
#define | LL_EXTI_LINE_39 EXTI_IMR2_IM39
#define | LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM
#define | LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE ((uint32_t)0x00000000U)

Define Documentation

#define LL_EXTI_LINE_0 EXTI_IMR1_IM0

Extended line 0

Definition at line 108 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_1 EXTI_IMR1_IM1

Extended line 1

Definition at line 109 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_10 EXTI_IMR1_IM10

Extended line 10

Definition at line 118 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_11 EXTI_IMR1_IM11

Extended line 11

Definition at line 119 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_12 EXTI_IMR1_IM12

Extended line 12

Definition at line 120 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_13 EXTI_IMR1_IM13

Extended line 13

Definition at line 121 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_14 EXTI_IMR1_IM14

Extended line 14

Definition at line 122 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_15 EXTI_IMR1_IM15

Extended line 15

Definition at line 123 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_16 EXTI_IMR1_IM16

Extended line 16

Definition at line 125 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_17 EXTI_IMR1_IM17

Extended line 17

Definition at line 127 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_18 EXTI_IMR1_IM18

Extended line 18

Definition at line 128 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_19 EXTI_IMR1_IM19

Extended line 19

Definition at line 129 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_2 EXTI_IMR1_IM2

Extended line 2

Definition at line 110 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_20 EXTI_IMR1_IM20

Extended line 20

Definition at line 131 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_21 EXTI_IMR1_IM21

Extended line 21

Definition at line 134 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_22 EXTI_IMR1_IM22

Extended line 22

Definition at line 137 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_23 EXTI_IMR1_IM23

Extended line 23

Definition at line 139 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_24 EXTI_IMR1_IM24

Extended line 24

Definition at line 141 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_25 EXTI_IMR1_IM25

Extended line 25

Definition at line 144 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_26 EXTI_IMR1_IM26

Extended line 26

Definition at line 147 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_27 EXTI_IMR1_IM27

Extended line 27

Definition at line 150 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_28 EXTI_IMR1_IM28

Extended line 28

Definition at line 153 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_29 EXTI_IMR1_IM29

Extended line 29

Definition at line 156 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_3 EXTI_IMR1_IM3

Extended line 3

Definition at line 111 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_30 EXTI_IMR1_IM30

Extended line 30

Definition at line 159 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_31 EXTI_IMR1_IM31

Extended line 31

Definition at line 162 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_32 EXTI_IMR2_IM32

Extended line 32

Definition at line 166 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_33 EXTI_IMR2_IM33

Extended line 33

Definition at line 167 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_34 EXTI_IMR2_IM34

Extended line 34

Definition at line 168 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_35 EXTI_IMR2_IM35

Extended line 35

Definition at line 169 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_36 EXTI_IMR2_IM36

Extended line 36

Definition at line 170 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_37 EXTI_IMR2_IM37

Extended line 37

Definition at line 171 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_38 EXTI_IMR2_IM38

Extended line 38

Definition at line 172 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_39 EXTI_IMR2_IM39

Extended line 39

Definition at line 173 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_4 EXTI_IMR1_IM4

Extended line 4

Definition at line 112 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_5 EXTI_IMR1_IM5

Extended line 5

Definition at line 113 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_6 EXTI_IMR1_IM6

Extended line 6

Definition at line 114 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_7 EXTI_IMR1_IM7

Extended line 7

Definition at line 115 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_8 EXTI_IMR1_IM8

Extended line 8

Definition at line 116 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_9 EXTI_IMR1_IM9

Extended line 9

Definition at line 117 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU)

All Extended line

Definition at line 176 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM

All Extended line not reserved

Definition at line 164 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM

All Extended line not reserved

Definition at line 174 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U)

None Extended line

Definition at line 179 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Mode

Defines
Mode
EXTI Exported Constants

Defines

#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Define Documentation

#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U)

Event Mode

Definition at line 191 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_MODE_IT ((uint8_t)0x00U)

Interrupt Mode

Definition at line 190 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Interrupt & Event Mode

Definition at line 192 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Edge Trigger

Defines
Edge Trigger
EXTI Exported Constants

Defines

#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Define Documentation

#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)

Trigger Falling Mode

Definition at line 202 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)

No Trigger Mode

Definition at line 200 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)

Trigger Rising Mode

Definition at line 201 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Trigger Rising & Falling Mode

Definition at line 203 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
EXTI Exported Macros

Defines

#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Define Documentation

#define LL_EXTI_ReadReg ( __REG__ ) READ_REG(EXTI->__REG__)

Read a value in EXTI register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 239 of file stm32l4xx_ll_exti.h.

#define LL_EXTI_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(EXTI->__REG__, (__VALUE__))

Write a value in EXTI register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 232 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_DeInit().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT_Management

Functions
IT_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableIT_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_DisableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 372 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableIT_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 32 to 63.

Note:
The reset value for the direct lines (lines from 32 to 34, line 39) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_DisableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 395 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_EnableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 302 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 32 to 63.

Note:
The reset value for the direct lines (lines from 32 to 34, line 39) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_EnableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 324 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_IsEnabledIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 443 of file stm32l4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.

Note:
The reset value for the direct lines (lines from 32 to 34, line 39) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_IsEnabledIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_ALL_32_63
Return values:
State of bit (1 or 0).

Definition at line 466 of file stm32l4xx_ll_exti.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Event_Management

Functions
Event_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableEvent_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_DisableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 585 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableEvent_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_DisableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 605 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_EnableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 519 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_EnableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 540 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_26
  • LL_EXTI_LINE_27
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 650 of file stm32l4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_32
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_34
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_ALL_32_63
Return values:
State of bit (1 or 0).

Definition at line 671 of file stm32l4xx_ll_exti.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Rising_Trigger_Management

Functions
Rising_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_32_63 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 789 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
Return values:
None

Definition at line 812 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 723 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set.Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
Return values:
None

Definition at line 745 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 849 of file stm32l4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
Return values:
State of bit (1 or 0).

Definition at line 864 of file stm32l4xx_ll_exti.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Falling_Trigger_Management

Functions
Falling_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_32_63 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 981 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
Return values:
None

Definition at line 1002 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 916 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
Return values:
None

Definition at line 938 of file stm32l4xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1039 of file stm32l4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
Return values:
State of bit (1 or 0).

Definition at line 1054 of file stm32l4xx_ll_exti.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Software_Interrupt_Management

Functions
Software_Interrupt_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_32_63 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 0 to 31.

Note:
If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1104 of file stm32l4xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 32 to 63.

Note:
If the interrupt is enabled on this line inthe EXTI_IMR, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
Return values:
None

Definition at line 1124 of file stm32l4xx_ll_exti.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Flag_Management

Functions
Flag_Management
EXTI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_ClearFlag_0_31 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_ClearFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1284 of file stm32l4xx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_ClearFlag_32_63 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_ClearFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
Return values:
None

Definition at line 1301 of file stm32l4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_IsActiveFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1171 of file stm32l4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_IsActiveFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
Return values:
State of bit (1 or 0).

Definition at line 1188 of file stm32l4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_ReadFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1227 of file stm32l4xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_ReadFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_35
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1245 of file stm32l4xx_ll_exti.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
EXTI Exported Functions

Functions

uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Function Documentation

uint32_t LL_EXTI_DeInit ( void )

De-initialize the EXTI registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: EXTI registers are de-initialized
  • ERROR: not applicable

Definition at line 99 of file stm32l4xx_ll_exti.c.

References LL_EXTI_WriteReg.

uint32_t LL_EXTI_Init ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.

Parameters:
EXTI_InitStruct pointer to a LL_EXTI_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: EXTI registers are initialized
  • ERROR: not applicable

Definition at line 137 of file stm32l4xx_ll_exti.c.

References assert_param, IS_LL_EXTI_LINE_0_31, IS_LL_EXTI_LINE_32_63, IS_LL_EXTI_MODE, IS_LL_EXTI_TRIGGER, LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::Line_32_63, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_DisableEvent_0_31(), LL_EXTI_DisableEvent_32_63(), LL_EXTI_DisableFallingTrig_0_31(), LL_EXTI_DisableFallingTrig_32_63(), LL_EXTI_DisableIT_0_31(), LL_EXTI_DisableIT_32_63(), LL_EXTI_DisableRisingTrig_0_31(), LL_EXTI_DisableRisingTrig_32_63(), LL_EXTI_EnableEvent_0_31(), LL_EXTI_EnableEvent_32_63(), LL_EXTI_EnableFallingTrig_0_31(), LL_EXTI_EnableFallingTrig_32_63(), LL_EXTI_EnableIT_0_31(), LL_EXTI_EnableIT_32_63(), LL_EXTI_EnableRisingTrig_0_31(), LL_EXTI_EnableRisingTrig_32_63(), LL_EXTI_LINE_NONE, LL_EXTI_MODE_EVENT, LL_EXTI_MODE_IT, LL_EXTI_MODE_IT_EVENT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_TRIGGER_NONE, LL_EXTI_TRIGGER_RISING, LL_EXTI_TRIGGER_RISING_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

void LL_EXTI_StructInit ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Set each LL_EXTI_InitTypeDef field to default value.

Parameters:
EXTI_InitStruct Pointer to a LL_EXTI_InitTypeDef structure.
Return values:
None

Definition at line 274 of file stm32l4xx_ll_exti.c.

References LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::Line_32_63, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_LINE_NONE, LL_EXTI_MODE_IT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO

Modules
GPIO
STM32L4xx_LL_Driver

Modules

GPIO Private Macros
GPIO Exported Init structures
GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for GPIO registers.

Register | Bit | Function
AFRH | AFSELy | LL_GPIO_GetAFPin_8_15
 |  | LL_GPIO_SetAFPin_8_15
AFRL | AFSELy | LL_GPIO_GetAFPin_0_7
 |  | LL_GPIO_SetAFPin_0_7
ASCR | ASCy | LL_GPIO_DisablePinAnalogControl
 |  | LL_GPIO_EnablePinAnalogControl
BRR | BRy | LL_GPIO_ResetOutputPin
BSRR | BSy | LL_GPIO_SetOutputPin
IDR | IDy | LL_GPIO_IsInputPinSet
 |  | LL_GPIO_ReadInputPort
LCKR | LCKK | LL_GPIO_IsAnyPinLocked
 |  | LL_GPIO_LockPin
 | LCKy | LL_GPIO_IsPinLocked
MODER | MODEy | LL_GPIO_GetPinMode
 |  | LL_GPIO_SetPinMode
ODR | ODy | LL_GPIO_IsOutputPinSet
 |  | LL_GPIO_ReadOutputPort
 |  | LL_GPIO_TogglePin
 |  | LL_GPIO_WriteOutputPort
OSPEEDR | OSPEEDy | LL_GPIO_GetPinSpeed
 |  | LL_GPIO_SetPinSpeed
OTYPER | OTy | LL_GPIO_GetPinOutputType
 |  | LL_GPIO_SetPinOutputType
PUPDR | PUPDy | LL_GPIO_GetPinPull
 |  | LL_GPIO_SetPinPull
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Define Documentation

#define IS_LL_GPIO_ALTERNATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_AF_0  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_15 ))

Definition at line 84 of file stm32l4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))

Definition at line 67 of file stm32l4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_OUTPUT_TYPE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))

Definition at line 72 of file stm32l4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PIN ( __VALUE__ ) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))

Definition at line 65 of file stm32l4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PULL ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_PULL_NO)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))

Definition at line 80 of file stm32l4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_SPEED ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 75 of file stm32l4xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_GPIO_InitTypeDef Struct Reference
GPIO Exported Init structures

LL GPIO Init Structure definition. More...

#include <stm32l4xx_ll_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Speed
uint32_t | OutputType
uint32_t | Pull
uint32_t | Alternate

Detailed Description

LL GPIO Init Structure definition.

Definition at line 82 of file stm32l4xx_ll_gpio.h.

Field Documentation

uint32_t LL_GPIO_InitTypeDef::Alternate

Specifies the Peripheral to be connected to the selected pins. This parameter can be a value of Alternate Function.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().

Definition at line 107 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of Mode.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinMode().

Definition at line 87 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::OutputType

Specifies the operating output type for the selected pins. This parameter can be a value of Output Type.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinOutputType().

Definition at line 97 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of PIN

Definition at line 84 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pull

Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of Pull Up Pull Down.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinPull().

Definition at line 102 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of Output Speed.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinSpeed().

Definition at line 92 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_gpio.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PIN

Defines
PIN
GPIO Exported Constants

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS15
#define | LL_GPIO_PIN_ALL

Define Documentation

#define LL_GPIO_PIN_0 GPIO_BSRR_BS0

Select pin 0

Definition at line 126 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_1 GPIO_BSRR_BS1

Select pin 1

Definition at line 127 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_10 GPIO_BSRR_BS10

Select pin 10

Definition at line 136 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_11 GPIO_BSRR_BS11

Select pin 11

Definition at line 137 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_12 GPIO_BSRR_BS12

Select pin 12

Definition at line 138 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_13 GPIO_BSRR_BS13

Select pin 13

Definition at line 139 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_14 GPIO_BSRR_BS14

Select pin 14

Definition at line 140 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_15 GPIO_BSRR_BS15

Select pin 15

Definition at line 141 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_2 GPIO_BSRR_BS2

Select pin 2

Definition at line 128 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_3 GPIO_BSRR_BS3

Select pin 3

Definition at line 129 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_4 GPIO_BSRR_BS4

Select pin 4

Definition at line 130 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_5 GPIO_BSRR_BS5

Select pin 5

Definition at line 131 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_6 GPIO_BSRR_BS6

Select pin 6

Definition at line 132 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_7 GPIO_BSRR_BS7

Select pin 7

Definition at line 133 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_8 GPIO_BSRR_BS8

Select pin 8

Definition at line 134 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_9 GPIO_BSRR_BS9

Select pin 9

Definition at line 135 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PIN_ALL
Value:
(GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
                                           GPIO_BSRR_BS15)

Select all pins

Definition at line 142 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Mode

Defines
Mode
GPIO Exported Constants

Defines

#define | LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0

Define Documentation

#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1

Select alternate function mode

Definition at line 157 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0

Select analog mode

Definition at line 158 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U)

Select input mode

Definition at line 155 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0

Select output mode

Definition at line 156 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Output Type

Defines
Output Type
GPIO Exported Constants

Defines

#define | LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0

Define Documentation

#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0

Select open-drain as output type

Definition at line 167 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U)

Select push-pull as output type

Definition at line 166 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Output Speed

Defines
Output Speed
GPIO Exported Constants

Defines

#define | LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1
#define | LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0

Define Documentation

#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1

Select I/O fast output speed

Definition at line 177 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U)

Select I/O low output speed

Definition at line 175 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0

Select I/O medium output speed

Definition at line 176 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0

Select I/O high output speed

Definition at line 178 of file stm32l4xx_ll_gpio.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Pull Up Pull Down

Defines
Pull Up Pull Down
GPIO Exported Constants

Defines

#define | LL_GPIO_PULL_NO ((uint32_t)0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1

Define Documentation

#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1

Select I/O pull down

Definition at line 193 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_PULL_NO ((uint32_t)0x00000000U)

Select I/O no pull

Definition at line 191 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0

Select I/O pull up

Definition at line 192 of file stm32l4xx_ll_gpio.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Alternate Function

Defines
Alternate Function
GPIO Exported Constants

Defines

#define | LL_GPIO_AF_0 ((uint32_t)0x0000000U)
#define | LL_GPIO_AF_1 ((uint32_t)0x0000001U)
#define | LL_GPIO_AF_2 ((uint32_t)0x0000002U)
#define | LL_GPIO_AF_3 ((uint32_t)0x0000003U)
#define | LL_GPIO_AF_4 ((uint32_t)0x0000004U)
#define | LL_GPIO_AF_5 ((uint32_t)0x0000005U)
#define | LL_GPIO_AF_6 ((uint32_t)0x0000006U)
#define | LL_GPIO_AF_7 ((uint32_t)0x0000007U)
#define | LL_GPIO_AF_8 ((uint32_t)0x0000008U)
#define | LL_GPIO_AF_9 ((uint32_t)0x0000009U)
#define | LL_GPIO_AF_10 ((uint32_t)0x000000AU)
#define | LL_GPIO_AF_11 ((uint32_t)0x000000BU)
#define | LL_GPIO_AF_12 ((uint32_t)0x000000CU)
#define | LL_GPIO_AF_13 ((uint32_t)0x000000DU)
#define | LL_GPIO_AF_14 ((uint32_t)0x000000EU)
#define | LL_GPIO_AF_15 ((uint32_t)0x000000FU)

Define Documentation

#define LL_GPIO_AF_0 ((uint32_t)0x0000000U)

Select alternate function 0

Definition at line 201 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_AF_1 ((uint32_t)0x0000001U)

Select alternate function 1

Definition at line 202 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_10 ((uint32_t)0x000000AU)

Select alternate function 10

Definition at line 211 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_11 ((uint32_t)0x000000BU)

Select alternate function 11

Definition at line 212 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_12 ((uint32_t)0x000000CU)

Select alternate function 12

Definition at line 213 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_13 ((uint32_t)0x000000DU)

Select alternate function 13

Definition at line 214 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_14 ((uint32_t)0x000000EU)

Select alternate function 14

Definition at line 215 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_15 ((uint32_t)0x000000FU)

Select alternate function 15

Definition at line 216 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_2 ((uint32_t)0x0000002U)

Select alternate function 2

Definition at line 203 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_3 ((uint32_t)0x0000003U)

Select alternate function 3

Definition at line 204 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_4 ((uint32_t)0x0000004U)

Select alternate function 4

Definition at line 205 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_5 ((uint32_t)0x0000005U)

Select alternate function 5

Definition at line 206 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_6 ((uint32_t)0x0000006U)

Select alternate function 6

Definition at line 207 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_7 ((uint32_t)0x0000007U)

Select alternate function 7

Definition at line 208 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_8 ((uint32_t)0x0000008U)

Select alternate function 8

Definition at line 209 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_AF_9 ((uint32_t)0x0000009U)

Select alternate function 9

Definition at line 210 of file stm32l4xx_ll_gpio.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO Exported Constants

Modules | Defines
GPIO Exported Constants
GPIO

Modules

PIN
Mode
Output Type
Output Speed
Pull Up Pull Down
Alternate Function

Defines

#define | LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define | LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define | LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define | LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH

Define Documentation

#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH

Definition at line 184 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH

Definition at line 185 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW

Definition at line 182 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM

Definition at line 183 of file stm32l4xx_ll_gpio.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
GPIO Exported Macros

Defines

#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Define Documentation

#define LL_GPIO_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 249 of file stm32l4xx_ll_gpio.h.

#define LL_GPIO_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 241 of file stm32l4xx_ll_gpio.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Port Configuration

Functions
Port Configuration
GPIO Exported Functions

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_EnablePinAnalogControl (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Connect analog switch to ADC input of several pins for a dedicated port.
__STATIC_INLINE void | LL_GPIO_DisablePinAnalogControl (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Disconnect analog switch to ADC input of several pins for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.

Function Documentation

__STATIC_INLINE void LL_GPIO_DisablePinAnalogControl | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Disconnect analog switch to ADC input of several pins for a dedicated port.

Reference Manual to LL API cross reference:
ASCR ASCy LL_GPIO_DisablePinAnalogControl
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 758 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_EnablePinAnalogControl | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Connect analog switch to ADC input of several pins for a dedicated port.

Note:
This bit must be set prior to the ADC conversion. Only the IO which connected to the ADC input are effective. Other IO must be kept reset value
Reference Manual to LL API cross reference:
ASCR ASCy LL_GPIO_EnablePinAnalogControl
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 729 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_GetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15

Definition at line 617 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_GetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15

Definition at line 695 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_GetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG

Definition at line 331 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_GetPinOutputType
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
Returned value can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN

Definition at line 400 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_GetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN

Definition at line 540 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
  • LL_GPIO_SPEED_FREQ_VERY_HIGH

Definition at line 474 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked ( GPIO_TypeDef * GPIOx )

Return 1 if one of the pin of a dedicated port is locked.

else return 0.

Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_IsAnyPinLocked
Parameters:
GPIOx GPIO Port
Return values:
State of bit (1 or 0).

Definition at line 838 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return 1 if all pins passed as parameter, of a dedicated port, are locked.

else Return 0.

Reference Manual to LL API cross reference:
LCKR LCKy LL_GPIO_IsPinLocked
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 827 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Lock configuration of several pins for a dedicated port.

Note:
When the lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next reset.
Each lock bit freezes a specific configuration register (control and alternate function registers).
Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_LockPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 793 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_SetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15
Return values:
None

Definition at line 580 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_SetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15
Return values:
None

Definition at line 657 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Mode
 | ) |  |

Configure gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_SetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Mode This parameter can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG
Return values:
None

Definition at line 297 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask,
 |  | uint32_t | OutputType
 | ) |  |

Configure gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_SetPinOutputType
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
OutputType This parameter can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN
Return values:
None

Definition at line 366 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Pull
 | ) |  |

Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_SetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Pull This parameter can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN
Return values:
None

Definition at line 508 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Speed
 | ) |  |

Configure gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Speed This parameter can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
  • LL_GPIO_SPEED_FREQ_VERY_HIGH
Return values:
None

Definition at line 437 of file stm32l4xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Access

Functions
Data Access
GPIO Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_IsInputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 886 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_IsOutputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 938 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort ( GPIO_TypeDef * GPIOx )

Return full input data register value for a dedicated port.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_ReadInputPort
Parameters:
GPIOx GPIO Port
Return values:
Input data register value of port

Definition at line 857 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort ( GPIO_TypeDef * GPIOx )

Return full output data register value for a dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_ReadOutputPort
Parameters:
GPIOx GPIO Port
Return values:
Output data register value of port

Definition at line 909 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_ResetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to low level on dedicated gpio port.

Reference Manual to LL API cross reference:
BRR BRy LL_GPIO_ResetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 996 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to high level on dedicated gpio port.

Reference Manual to LL API cross reference:
BSRR BSy LL_GPIO_SetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 967 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Toggle data value for several pin of dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_TogglePin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 1025 of file stm32l4xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_WriteOutputPort | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PortValue
 | ) |  |

Write output data register for the port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_WriteOutputPort
Parameters:
GPIOx | GPIO Port
PortValue | Level value for each pin of the port
Return values:
None

Definition at line 898 of file stm32l4xx_ll_gpio.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_GPIO_DeInit ( GPIO_TypeDef * GPIOx )

De-initialize GPIO registers (Registers restored to their default values).

Parameters:
GPIOx GPIO Port
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are de-initialized
  • ERROR: Wrong GPIO Port

Definition at line 122 of file stm32l4xx_ll_gpio.c.

References assert_param, LL_AHB2_GRP1_ForceReset(), LL_AHB2_GRP1_PERIPH_GPIOA, LL_AHB2_GRP1_PERIPH_GPIOB, LL_AHB2_GRP1_PERIPH_GPIOC, LL_AHB2_GRP1_PERIPH_GPIOD, LL_AHB2_GRP1_PERIPH_GPIOE, LL_AHB2_GRP1_PERIPH_GPIOF, LL_AHB2_GRP1_PERIPH_GPIOG, LL_AHB2_GRP1_PERIPH_GPIOH, and LL_AHB2_GRP1_ReleaseReset().

ErrorStatus LL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | LL_GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.

Parameters:
GPIOx GPIO Port
GPIO_InitStruct,: pointer to a LL_GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
  • ERROR: Not applicable

Definition at line 204 of file stm32l4xx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, assert_param, IS_LL_GPIO_ALTERNATE, IS_LL_GPIO_MODE, IS_LL_GPIO_OUTPUT_TYPE, IS_LL_GPIO_PIN, IS_LL_GPIO_PULL, IS_LL_GPIO_SPEED, LL_GPIO_MODE_ALTERNATE, LL_GPIO_MODE_OUTPUT, LL_GPIO_SetAFPin_0_7(), LL_GPIO_SetAFPin_8_15(), LL_GPIO_SetPinMode(), LL_GPIO_SetPinOutputType(), LL_GPIO_SetPinPull(), LL_GPIO_SetPinSpeed(), LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

void LL_GPIO_StructInit ( LL_GPIO_InitTypeDef * GPIO_InitStruct )

Set each LL_GPIO_InitTypeDef field to default value.

Parameters:
GPIO_InitStruct,: pointer to a LL_GPIO_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 280 of file stm32l4xx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, LL_GPIO_AF_0, LL_GPIO_MODE_ANALOG, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PIN_ALL, LL_GPIO_PULL_NO, LL_GPIO_SPEED_FREQ_LOW, LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C

Modules
I2C
STM32L4xx_LL_Driver

Modules

I2C Private Constants
I2C Private Macros
I2C Exported Init structure
I2C Exported Constants
I2C Exported Macros
I2C Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for I2C registers.

Register | Bit | Function
CR1 | ADDRIE | LL_I2C_DisableIT_ADDR
 |  | LL_I2C_EnableIT_ADDR
 |  | LL_I2C_IsEnabledIT_ADDR
 | ALERTEN | LL_I2C_DisableSMBusAlert
 |  | LL_I2C_EnableSMBusAlert
 |  | LL_I2C_IsEnabledSMBusAlert
 | ANFOFF | LL_I2C_ConfigFilters
 |  | LL_I2C_DisableAnalogFilter
 |  | LL_I2C_EnableAnalogFilter
 |  | LL_I2C_IsEnabledAnalogFilter
 | DNF | LL_I2C_ConfigFilters
 |  | LL_I2C_GetDigitalFilter
 |  | LL_I2C_SetDigitalFilter
 | ERRIE | LL_I2C_DisableIT_ERR
 |  | LL_I2C_EnableIT_ERR
 |  | LL_I2C_IsEnabledIT_ERR
 | GCEN | LL_I2C_DisableGeneralCall
 |  | LL_I2C_EnableGeneralCall
 |  | LL_I2C_IsEnabledGeneralCall
 | NACKIE | LL_I2C_DisableIT_NACK
 |  | LL_I2C_EnableIT_NACK
 |  | LL_I2C_IsEnabledIT_NACK
 | NOSTRETCH | LL_I2C_DisableClockStretching
 |  | LL_I2C_EnableClockStretching
 |  | LL_I2C_IsEnabledClockStretching
 | PE | LL_I2C_Disable
 |  | LL_I2C_Enable
 |  | LL_I2C_IsEnabled
 | PECEN | LL_I2C_DisableSMBusPEC
 |  | LL_I2C_EnableSMBusPEC
 |  | LL_I2C_IsEnabledSMBusPEC
 | RXDMAEN | LL_I2C_DisableDMAReq_RX
 |  | LL_I2C_EnableDMAReq_RX
 |  | LL_I2C_IsEnabledDMAReq_RX
 | RXIE | LL_I2C_DisableIT_RX
 |  | LL_I2C_EnableIT_RX
 |  | LL_I2C_IsEnabledIT_RX
 | SBC | LL_I2C_DisableSlaveByteControl
 |  | LL_I2C_EnableSlaveByteControl
 |  | LL_I2C_IsEnabledSlaveByteControl
 | SMBDEN | LL_I2C_GetMode
 |  | LL_I2C_SetMode
 | SMBHEN | LL_I2C_GetMode
 |  | LL_I2C_SetMode
 | STOPIE | LL_I2C_DisableIT_STOP
 |  | LL_I2C_EnableIT_STOP
 |  | LL_I2C_IsEnabledIT_STOP
 | TCIE | LL_I2C_DisableIT_TC
 |  | LL_I2C_EnableIT_TC
 |  | LL_I2C_IsEnabledIT_TC
 | TXDMAEN | LL_I2C_DisableDMAReq_TX
 |  | LL_I2C_EnableDMAReq_TX
 |  | LL_I2C_IsEnabledDMAReq_TX
 | TXIE | LL_I2C_DisableIT_TX
 |  | LL_I2C_EnableIT_TX
 |  | LL_I2C_IsEnabledIT_TX
 | WUPEN | LL_I2C_DisableWakeUpFromStop
 |  | LL_I2C_EnableWakeUpFromStop
 |  | LL_I2C_IsEnabledWakeUpFromStop
CR2 | ADD10 | LL_I2C_GetMasterAddressingMode
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetMasterAddressingMode
 | AUTOEND | LL_I2C_DisableAutoEndMode
 |  | LL_I2C_EnableAutoEndMode
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_IsEnabledAutoEndMode
 | HEAD10R | LL_I2C_DisableAuto10BitRead
 |  | LL_I2C_EnableAuto10BitRead
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_IsEnabledAuto10BitRead
 | NACK | LL_I2C_AcknowledgeNextData
 | NBYTES | LL_I2C_GetTransferSize
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetTransferSize
 | PECBYTE | LL_I2C_EnableSMBusPECCompare
 |  | LL_I2C_IsEnabledSMBusPECCompare
 | RD_WRN | LL_I2C_GetTransferRequest
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetTransferRequest
 | RELOAD | LL_I2C_DisableReloadMode
 |  | LL_I2C_EnableReloadMode
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_IsEnabledReloadMode
 | SADD | LL_I2C_GetSlaveAddr
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetSlaveAddr
 | START | LL_I2C_GenerateStartCondition
 |  | LL_I2C_HandleTransfer
 | STOP | LL_I2C_GenerateStopCondition
 |  | LL_I2C_HandleTransfer
ICR | ADDRCF | LL_I2C_ClearFlag_ADDR
 | ALERTCF | LL_I2C_ClearSMBusFlag_ALERT
 | ARLOCF | LL_I2C_ClearFlag_ARLO
 | BERRCF | LL_I2C_ClearFlag_BERR
 | NACKCF | LL_I2C_ClearFlag_NACK
 | OVRCF | LL_I2C_ClearFlag_OVR
 | PECCF | LL_I2C_ClearSMBusFlag_PECERR
 | STOPCF | LL_I2C_ClearFlag_STOP
 | TIMOUTCF | LL_I2C_ClearSMBusFlag_TIMEOUT
ISR | ADDCODE | LL_I2C_GetAddressMatchCode
 | ADDR | LL_I2C_IsActiveFlag_ADDR
 | ALERT | LL_I2C_IsActiveSMBusFlag_ALERT
 | ARLO | LL_I2C_IsActiveFlag_ARLO
 | BERR | LL_I2C_IsActiveFlag_BERR
 | BUSY | LL_I2C_IsActiveFlag_BUSY
 | DIR | LL_I2C_GetTransferDirection
 | NACKF | LL_I2C_IsActiveFlag_NACK
 | OVR | LL_I2C_IsActiveFlag_OVR
 | PECERR | LL_I2C_IsActiveSMBusFlag_PECERR
 | RXNE | LL_I2C_IsActiveFlag_RXNE
 | STOPF | LL_I2C_IsActiveFlag_STOP
 | TC | LL_I2C_IsActiveFlag_TC
 | TCR | LL_I2C_IsActiveFlag_TCR
 | TIMEOUT | LL_I2C_IsActiveSMBusFlag_TIMEOUT
 | TXE | LL_I2C_ClearFlag_TXE
 |  | LL_I2C_IsActiveFlag_TXE
 | TXIS | LL_I2C_IsActiveFlag_TXIS
OAR1 | OA1 | LL_I2C_SetOwnAddress1
 | OA1EN | LL_I2C_DisableOwnAddress1
 |  | LL_I2C_EnableOwnAddress1
 |  | LL_I2C_IsEnabledOwnAddress1
 | OA1MODE | LL_I2C_SetOwnAddress1
OAR2 | OA2 | LL_I2C_SetOwnAddress2
 | OA2EN | LL_I2C_DisableOwnAddress2
 |  | LL_I2C_EnableOwnAddress2
 |  | LL_I2C_IsEnabledOwnAddress2
 | OA2MSK | LL_I2C_SetOwnAddress2
PECR | PEC | LL_I2C_GetSMBusPEC
RXDR | RXDATA | LL_I2C_DMA_GetRegAddr
 |  | LL_I2C_ReceiveData8
TIMEOUTR | TEXTEN | LL_I2C_DisableSMBusTimeout
 |  | LL_I2C_EnableSMBusTimeout
 |  | LL_I2C_IsEnabledSMBusTimeout
 | TIDLE | LL_I2C_ConfigSMBusTimeout
 |  | LL_I2C_GetSMBusTimeoutAMode
 |  | LL_I2C_SetSMBusTimeoutAMode
 | TIMEOUTA | LL_I2C_ConfigSMBusTimeout
 |  | LL_I2C_GetSMBusTimeoutA
 |  | LL_I2C_SetSMBusTimeoutA
 | TIMEOUTB | LL_I2C_ConfigSMBusTimeout
 |  | LL_I2C_GetSMBusTimeoutB
 |  | LL_I2C_SetSMBusTimeoutB
 | TIMOUTEN | LL_I2C_DisableSMBusTimeout
 |  | LL_I2C_EnableSMBusTimeout
 |  | LL_I2C_IsEnabledSMBusTimeout
TIMINGR | PRESC | LL_I2C_GetTimingPrescaler
 | SCLDEL | LL_I2C_GetDataSetupTime
 | SCLH | LL_I2C_GetClockHighPeriod
 | SCLL | LL_I2C_GetClockLowPeriod
 | SDADEL | LL_I2C_GetDataHoldTime
 | TIMINGR | LL_I2C_SetTiming
TXDR | TXDATA | LL_I2C_DMA_GetRegAddr
 |  | LL_I2C_TransmitData8
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Private Constants

Defines
I2C Private Constants
I2C

Defines

#define | I2C_POSITION_CR1_DNF (uint32_t)POSITION_VAL(I2C_CR1_DNF)
#define | I2C_POSITION_CR2_NBYTES (uint32_t)POSITION_VAL(I2C_CR2_NBYTES)
#define | I2C_POSITION_TIMINGR_PRESC (uint32_t)POSITION_VAL(I2C_TIMINGR_PRESC)
#define | I2C_POSITION_TIMINGR_SCLDEL (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLDEL)
#define | I2C_POSITION_TIMINGR_SDADEL (uint32_t)POSITION_VAL(I2C_TIMINGR_SDADEL)
#define | I2C_POSITION_TIMINGR_SCLH (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLH)
#define | I2C_POSITION_TIMINGR_SCLL (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLL)
#define | I2C_POSITION_ISR_ADDCODE (uint32_t)POSITION_VAL(I2C_ISR_ADDCODE)
#define | I2C_POSITION_TIMEOUTR_TIMEOUTB (uint32_t)POSITION_VAL(I2C_TIMEOUTR_TIMEOUTB)

Define Documentation

#define I2C_POSITION_CR1_DNF (uint32_t)POSITION_VAL(I2C_CR1_DNF)

Definition at line 67 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_ConfigFilters(), LL_I2C_GetDigitalFilter(), and LL_I2C_SetDigitalFilter().

#define I2C_POSITION_CR2_NBYTES (uint32_t)POSITION_VAL(I2C_CR2_NBYTES)

Definition at line 68 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_GetTransferSize(), LL_I2C_HandleTransfer(), and LL_I2C_SetTransferSize().

#define I2C_POSITION_ISR_ADDCODE (uint32_t)POSITION_VAL(I2C_ISR_ADDCODE)

Definition at line 74 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_GetAddressMatchCode().

#define I2C_POSITION_TIMEOUTR_TIMEOUTB (uint32_t)POSITION_VAL(I2C_TIMEOUTR_TIMEOUTB)

Definition at line 75 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_ConfigSMBusTimeout(), LL_I2C_GetSMBusTimeoutB(), and LL_I2C_SetSMBusTimeoutB().

#define I2C_POSITION_TIMINGR_PRESC (uint32_t)POSITION_VAL(I2C_TIMINGR_PRESC)

Definition at line 69 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_GetTimingPrescaler().

#define I2C_POSITION_TIMINGR_SCLDEL (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLDEL)

Definition at line 70 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_GetDataSetupTime().

#define I2C_POSITION_TIMINGR_SCLH (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLH)

Definition at line 72 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_GetClockHighPeriod().

#define I2C_POSITION_TIMINGR_SCLL (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLL)

Definition at line 73 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_GetClockLowPeriod().

#define I2C_POSITION_TIMINGR_SDADEL (uint32_t)POSITION_VAL(I2C_TIMINGR_SDADEL)

Definition at line 71 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_GetDataHoldTime().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= (uint32_t)0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Define Documentation

#define IS_LL_I2C_ANALOG_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))

Definition at line 71 of file stm32l4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_DIGITAL_FILTER ( __VALUE__ ) ((__VALUE__) <= 0x0000000FU)

Definition at line 74 of file stm32l4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRESS1 ( __VALUE__ ) ((__VALUE__) <= (uint32_t)0x000003FFU)

Definition at line 76 of file stm32l4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRSIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))

Definition at line 81 of file stm32l4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_PERIPHERAL_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_MODE_I2C)          || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))

Definition at line 66 of file stm32l4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_TYPE_ACKNOWLEDGE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ACK) || \
                                                 ((__VALUE__) == LL_I2C_NACK))

Definition at line 78 of file stm32l4xx_ll_i2c.c.

Referenced by LL_I2C_Init().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2C_InitTypeDef Struct Reference
I2C Exported Init structure

#include <stm32l4xx_ll_i2c.h>

Data Fields

uint32_t | PeripheralMode
uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | DigitalFilter
uint32_t | OwnAddress1
uint32_t | TypeAcknowledge
uint32_t | OwnAddrSize

Detailed Description

Definition at line 95 of file stm32l4xx_ll_i2c.h.

Field Documentation

uint32_t LL_I2C_InitTypeDef::AnalogFilter

Enables or disables analog noise filter. This parameter can be a value of Analog Filter Selection

This feature can be modified afterwards using unitary functions LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter().

Definition at line 108 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::DigitalFilter

Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F

This feature can be modified afterwards using unitary function LL_I2C_SetDigitalFilter().

Definition at line 113 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddress1

Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 118 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddrSize

Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of Own Address 1 Length

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 128 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::PeripheralMode

Specifies the peripheral mode. This parameter can be a value of Peripheral Mode

This feature can be modified afterwards using unitary function LL_I2C_SetMode().

Definition at line 97 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::Timing

Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro __LL_I2C_CONVERT_TIMINGS()

This feature can be modified afterwards using unitary function LL_I2C_SetTiming().

Definition at line 102 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::TypeAcknowledge

Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. This parameter can be a value of Acknowledge Generation

This feature can be modified afterwards using unitary function LL_I2C_AcknowledgeNextData().

Definition at line 123 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_i2c.h
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STM32L486xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_WriteReg function. More...

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Detailed Description

Flags defines which can be used with LL_I2C_WriteReg function.

Define Documentation

#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF

Address Matched flag

Definition at line 147 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Alert flag

Definition at line 155 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF

Arbitration Lost flag

Definition at line 151 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF

Bus error flag

Definition at line 150 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF

Not Acknowledge flag

Definition at line 148 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF

Overrun/Underrun flag

Definition at line 152 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ICR_PECCF I2C_ICR_PECCF

PEC error flag

Definition at line 153 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF

Stop detection flag

Definition at line 149 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF

Timeout detection flag

Definition at line 154 of file stm32l4xx_ll_i2c.h.

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STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_ReadReg function. More...

Defines

#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY

Detailed Description

Flags defines which can be used with LL_I2C_ReadReg function.

Define Documentation

#define LL_I2C_ISR_ADDR I2C_ISR_ADDR

Address matched (slave mode)

Definition at line 167 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_ALERT I2C_ISR_ALERT

SMBus alert (SMBus mode)

Definition at line 177 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_ARLO I2C_ISR_ARLO

Arbitration lost

Definition at line 173 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_BERR I2C_ISR_BERR

Bus error

Definition at line 172 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_BUSY I2C_ISR_BUSY

Bus busy

Definition at line 178 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_NACKF I2C_ISR_NACKF

Not Acknowledge received flag

Definition at line 168 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_OVR I2C_ISR_OVR

Overrun/Underrun (slave mode)

Definition at line 174 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_PECERR I2C_ISR_PECERR

PEC Error in reception (SMBus mode)

Definition at line 175 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_RXNE I2C_ISR_RXNE

Receive data register not empty

Definition at line 166 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_STOPF I2C_ISR_STOPF

Stop detection flag

Definition at line 169 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_TC I2C_ISR_TC

Transfer Complete (master mode)

Definition at line 170 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_TCR I2C_ISR_TCR

Transfer Complete Reload

Definition at line 171 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT

Timeout detection flag (SMBus mode)

Definition at line 176 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_TXE I2C_ISR_TXE

Transmit data register empty

Definition at line 164 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ISR_TXIS I2C_ISR_TXIS

Transmit interrupt status

Definition at line 165 of file stm32l4xx_ll_i2c.h.

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STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
I2C Exported Constants

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions. More...

Defines

#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Detailed Description

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Define Documentation

#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE

Address match Interrupt enable (slave only)

Definition at line 189 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Error interrupts enable

Definition at line 193 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE

Not acknowledge received Interrupt enable

Definition at line 190 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_CR1_RXIE I2C_CR1_RXIE

RX Interrupt enable

Definition at line 188 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE

STOP detection Interrupt enable

Definition at line 191 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_CR1_TCIE I2C_CR1_TCIE

Transfer Complete interrupt enable

Definition at line 192 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_CR1_TXIE I2C_CR1_TXIE

TX Interrupt enable

Definition at line 187 of file stm32l4xx_ll_i2c.h.

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STM32L486xx HAL User Manual: Peripheral Mode

Defines
Peripheral Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_I2C ((uint32_t)0x00000000U)
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U)
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

Define Documentation

#define LL_I2C_MODE_I2C ((uint32_t)0x00000000U)

I2C Master or Slave mode

Definition at line 201 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

#define LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U)

SMBus Device default mode (Default address not acknowledge)

Definition at line 203 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

SMBus Device Default address acknowledge

Definition at line 204 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN

SMBus Host address acknowledge

Definition at line 202 of file stm32l4xx_ll_i2c.h.

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STM32L486xx HAL User Manual: Analog Filter Selection

Defines
Analog Filter Selection
I2C Exported Constants

Defines

#define | LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Analog filter is disabled.

Definition at line 213 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)

Analog filter is enabled.

Definition at line 212 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

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STM32L486xx HAL User Manual: Master Addressing Mode

Defines
Master Addressing Mode
I2C Exported Constants

Defines

#define | LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U)
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Master operates in 10-bit addressing mode.

Definition at line 222 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U)

Master operates in 7-bit addressing mode.

Definition at line 221 of file stm32l4xx_ll_i2c.h.

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STM32L486xx HAL User Manual: Own Address 1 Length

Defines
Own Address 1 Length
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U)
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Define Documentation

#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Own address 1 is a 10-bit address.

Definition at line 231 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U)

Own address 1 is a 7-bit address.

Definition at line 230 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

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STM32L486xx HAL User Manual: Own Address 2 Masks

Defines
Own Address 2 Masks
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

Define Documentation

#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01

Only Address2 bits[7:2] are compared.

Definition at line 240 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02

Only Address2 bits[7:3] are compared.

Definition at line 241 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03

Only Address2 bits[7:4] are compared.

Definition at line 242 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04

Only Address2 bits[7:5] are compared.

Definition at line 243 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05

Only Address2 bits[7:6] are compared.

Definition at line 244 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06

Only Address2 bits[7] are compared.

Definition at line 245 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

No comparison is done. All Address2 are acknowledged.

Definition at line 246 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK

Own Address2 No mask.

Definition at line 239 of file stm32l4xx_ll_i2c.h.

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STM32L486xx HAL User Manual: Acknowledge Generation

Defines
Acknowledge Generation
I2C Exported Constants

Defines

#define | LL_I2C_ACK ((uint32_t) 0x00000000U)
#define | LL_I2C_NACK I2C_CR2_NACK

Define Documentation

#define LL_I2C_ACK ((uint32_t) 0x00000000U)

ACK is sent after current received byte.

Definition at line 254 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_NACK I2C_CR2_NACK

NACK is sent after current received byte.

Definition at line 255 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

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STM32L486xx HAL User Manual: Slave Address Length

Defines
Slave Address Length
I2C Exported Constants

Defines

#define | LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U)
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Slave Address in 10-bit.

Definition at line 264 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U)

Slave Address in 7-bit.

Definition at line 263 of file stm32l4xx_ll_i2c.h.

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STM32L486xx HAL User Manual: Transfer Request Direction

Defines
Transfer Request Direction
I2C Exported Constants

Defines

#define | LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U)
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Define Documentation

#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Master request a read transfer.

Definition at line 273 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U)

Master request a write transfer.

Definition at line 272 of file stm32l4xx_ll_i2c.h.

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STM32L486xx HAL User Manual: Transfer End Mode

Defines
Transfer End Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U)
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Define Documentation

#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND

Enable I2C Automatic end mode with no HW PEC comparison.

Definition at line 282 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD

Enable I2C Reload mode.

Definition at line 281 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 285 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 287 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 284 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 286 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 288 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U)

Enable I2C Software end mode with no HW PEC comparison.

Definition at line 283 of file stm32l4xx_ll_i2c.h.

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STM32L486xx HAL User Manual: Start And Stop Generation

Defines
Start And Stop Generation
I2C Exported Constants

Defines

#define | LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U)
#define | LL_I2C_GENERATE_STOP I2C_CR2_STOP
#define | LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE I2C_CR2_START
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START
#define | LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START

Define Documentation

#define LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U)

Don't Generate Stop and Start condition.

Definition at line 296 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)

Generate Restart for read request, slave 10Bit address.

Definition at line 302 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START

Generate Restart for write request, slave 10Bit address.

Definition at line 303 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Restart for read request, slave 7Bit address.

Definition at line 300 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START

Generate Restart for write request, slave 7Bit address.

Definition at line 301 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Start for read request.

Definition at line 298 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START

Generate Start for write request.

Definition at line 299 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_GENERATE_STOP I2C_CR2_STOP

Generate Stop condition (Size should be set to 0).

Definition at line 297 of file stm32l4xx_ll_i2c.h.

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STM32L486xx HAL User Manual: Read Write Direction

Defines
Read Write Direction
I2C Exported Constants

Defines

#define | LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U)
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR

Define Documentation

#define LL_I2C_DIRECTION_READ I2C_ISR_DIR

Read transfer request by master, slave enters transmitter mode.

Definition at line 312 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U)

Write transfer request by master, slave enters receiver mode.

Definition at line 311 of file stm32l4xx_ll_i2c.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
I2C Exported Constants

Defines

#define | LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U)
#define | LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U)

Define Documentation

#define LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U)

Get address of data register used for reception

Definition at line 321 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U)

Get address of data register used for transmission

Definition at line 320 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_DMA_GetRegAddr().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBus TimeoutA Mode SCL SDA Timeout

Defines
SMBus TimeoutA Mode SCL SDA Timeout
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U)
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

Define Documentation

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U)

TimeoutA is used to detect SCL low level timeout.

Definition at line 329 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

TimeoutA is used to detect both SCL and SDA high level timeout.

Definition at line 330 of file stm32l4xx_ll_i2c.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBus Timeout Selection

Defines
SMBus Timeout Selection
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)

Define Documentation

#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)

TimeoutA and TimeoutB (extended clock) enable bits

Definition at line 340 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN

TimeoutA enable bit

Definition at line 338 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN

TimeoutB (extended clock) enable bit

Definition at line 339 of file stm32l4xx_ll_i2c.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2C Exported Macros

Defines

#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.

Define Documentation

#define LL_I2C_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 373 of file stm32l4xx_ll_i2c.h.

#define LL_I2C_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 365 of file stm32l4xx_ll_i2c.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Convert SDA SCL timings

Defines
Convert SDA SCL timings
I2C Exported Macros

Defines

#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Define Documentation

#define __LL_I2C_CONVERT_TIMINGS | ( | __PRESCALER__,
 |  | __DATA_SETUP_TIME__,
 |  | __DATA_HOLD_TIME__,
 |  | __CLOCK_HIGH_PERIOD__,
 |  | __CLOCK_LOW_PERIOD__
 | ) |
Value:
((((uint32_t)(__PRESCALER__)         << I2C_POSITION_TIMINGR_PRESC)  & I2C_TIMINGR_PRESC)   | \
         (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL)  | \
         (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL)  | \
         (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH)   & I2C_TIMINGR_SCLH)    | \
         (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_POSITION_TIMINGR_SCLL)   & I2C_TIMINGR_SCLL))

Configure the SDA setup, hold time and the SCL high, low period.

Parameters:
__PRESCALER__ | This parameter must be a value between 0 and 0xF.
__DATA_SETUP_TIME__ | This parameter must be a value between 0 and 0xF. (tscldel = (SCLDEL+1)xtpresc)
__DATA_HOLD_TIME__ | This parameter must be a value between 0 and 0xF. (tsdadel = SDADELxtpresc)
__CLOCK_HIGH_PERIOD__ | This parameter must be a value between 0 and 0xFF. (tsclh = (SCLH+1)xtpresc)
__CLOCK_LOW_PERIOD__ | This parameter must be a value between 0 and 0xFF. (tscll = (SCLL+1)xtpresc)
Return values:
Value between 0 and 0xFFFFFFFF

Definition at line 390 of file stm32l4xx_ll_i2c.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration

Functions
Configuration
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (I2C_TypeDef *I2Cx)
Get the SMBus Extented Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_ConfigFilters | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AnalogFilter,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Noise Filters (Analog and Digital).

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. The filters can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_ConfigFilters
CR1 DNF LL_I2C_ConfigFilters
Parameters:
I2Cx | I2C Instance.
AnalogFilter This parameter can be one of the following values:
  • LL_I2C_ANALOGFILTER_ENABLE
  • LL_I2C_ANALOGFILTER_DISABLE
DigitalFilter | This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 464 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_CR1_DNF.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA,
 |  | uint32_t | TimeoutAMode,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
TimeoutB
Note:
This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
Return values:
None

Definition at line 1112 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_TIMEOUTR_TIMEOUTB.

__STATIC_INLINE void LL_I2C_Disable ( I2C_TypeDef * I2Cx )

Disable I2C peripheral (PE = 0).

Note:
When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Disable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 433 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAnalogFilter ( I2C_TypeDef * I2Cx )

Disable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_DisableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 515 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableClockStretching ( I2C_TypeDef * I2Cx )

Disable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_DisableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 644 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_RX ( I2C_TypeDef * I2Cx )

Disable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 581 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_TX ( I2C_TypeDef * I2Cx )

Disable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 548 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableGeneralCall ( I2C_TypeDef * I2Cx )

Disable General Call.

Note:
When disabled the Address 0x00 is NACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_DisableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 752 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableOwnAddress1 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_DisableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 829 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableOwnAddress2 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_DisableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 885 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSlaveByteControl ( I2C_TypeDef * I2Cx )

Disable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_DisableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 677 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusAlert ( I2C_TypeDef * I2Cx )

Disable SMBus alert (Host or Device mode)

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is not drived (can be used as a standard GPIO) and Alert Response Address Header acknowledge is disabled. SMBus Host mode:
  • SMBus Alert pin management is not supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_DisableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1038 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusPEC ( I2C_TypeDef * I2Cx )

Disable SMBus Packet Error Calculation (PEC).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_DisableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1077 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Disable the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1238 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Disable Wakeup from STOP.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_DisableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 715 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_DMA_GetRegAddr
RXDR RXDATA LL_I2C_DMA_GetRegAddr
Parameters:
I2Cx I2C Instance
Direction This parameter can be one of the following values:
  • LL_I2C_DMA_REG_DATA_TRANSMIT
  • LL_I2C_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 607 of file stm32l4xx_ll_i2c.h.

References LL_I2C_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_I2C_Enable ( I2C_TypeDef * I2Cx )

Enable I2C peripheral (PE = 1).

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Enable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 419 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableAnalogFilter ( I2C_TypeDef * I2Cx )

Enable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_EnableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 503 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableClockStretching ( I2C_TypeDef * I2Cx )

Enable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_EnableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 632 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_RX ( I2C_TypeDef * I2Cx )

Enable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 570 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_TX ( I2C_TypeDef * I2Cx )

Enable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 537 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableGeneralCall ( I2C_TypeDef * I2Cx )

Enable General Call.

Note:
When enabled the Address 0x00 is ACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_EnableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 740 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableOwnAddress1 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_EnableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 818 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableOwnAddress2 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_EnableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 874 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSlaveByteControl ( I2C_TypeDef * I2Cx )

Enable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_EnableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 666 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusAlert ( I2C_TypeDef * I2Cx )

Enable SMBus alert (Host or Device mode)

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is drived low and Alert Response Address Header acknowledge is enabled. SMBus Host mode:
  • SMBus Alert pin management is supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_EnableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1020 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPEC ( I2C_TypeDef * I2Cx )

Enable SMBus Packet Error Calculation (PEC).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_EnableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1064 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Enable the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1220 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Enable Wakeup from STOP.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
This bit can only be programmed when Digital Filter is disabled.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_EnableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 702 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod ( I2C_TypeDef * I2Cx )

Get the SCL high period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLH LL_I2C_GetClockHighPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 943 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_TIMINGR_SCLH.

__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod ( I2C_TypeDef * I2Cx )

Get the SCL low period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLL LL_I2C_GetClockLowPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 932 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_TIMINGR_SCLL.

__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime ( I2C_TypeDef * I2Cx )

Get the SDA hold time.

Reference Manual to LL API cross reference:
TIMINGR SDADEL LL_I2C_GetDataHoldTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 954 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_TIMINGR_SDADEL.

__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime ( I2C_TypeDef * I2Cx )

Get the SDA setup time.

Reference Manual to LL API cross reference:
TIMINGR SCLDEL LL_I2C_GetDataSetupTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 965 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_TIMINGR_SCLDEL.

__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter ( I2C_TypeDef * I2Cx )

Get the current Digital Noise Filter configuration.

Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_GetDigitalFilter
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 491 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_CR1_DNF.

__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode ( I2C_TypeDef * I2Cx )

Get the Master addressing mode.

Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_GetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT

Definition at line 791 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMode ( I2C_TypeDef * I2Cx )

Get peripheral mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_GetMode
CR1 SMBDEN LL_I2C_GetMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP

Definition at line 1002 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA ( I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA setting.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1142 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode ( I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH

Definition at line 1174 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB ( I2C_TypeDef * I2Cx )

Get the SMBus Extented Cumulative Clock TimeoutB setting.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1202 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_TIMEOUTR_TIMEOUTB.

__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler ( I2C_TypeDef * I2Cx )

Get the Timing Prescaler setting.

Reference Manual to LL API cross reference:
TIMINGR PRESC LL_I2C_GetTimingPrescaler
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 921 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_TIMINGR_PRESC.

__STATIC_INLINE uint32_t LL_I2C_IsEnabled ( I2C_TypeDef * I2Cx )

Check if the I2C peripheral is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_IsEnabled
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 444 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter ( I2C_TypeDef * I2Cx )

Check if Analog Noise Filter is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 526 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching ( I2C_TypeDef * I2Cx )

Check if Clock stretching is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 655 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX ( I2C_TypeDef * I2Cx )

Check if DMA reception requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 592 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX ( I2C_TypeDef * I2Cx )

Check if DMA transmission requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 559 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall ( I2C_TypeDef * I2Cx )

Check if General Call is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_IsEnabledGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 763 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 840 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 896 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl ( I2C_TypeDef * I2Cx )

Check if hardware byte control in slave mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_IsEnabledSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 688 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert ( I2C_TypeDef * I2Cx )

Check if SMBus alert (Host or Device mode) is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1051 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC ( I2C_TypeDef * I2Cx )

Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_IsEnabledSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1090 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Check if the SMBus Clock Timeout is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
State of bit (1 or 0).

Definition at line 1256 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop ( I2C_TypeDef * I2Cx )

Check if Wakeup from STOP is enabled or disabled.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 728 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetDigitalFilter | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital Noise Filter.

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_SetDigitalFilter
Parameters:
I2Cx | I2C Instance.
DigitalFilter | This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 480 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_CR1_DNF.

__STATIC_INLINE void LL_I2C_SetMasterAddressingMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AddressingMode
 | ) |  |

Configure the Master to operate in 7-bit or 10-bit addressing mode.

Note:
Changing this bit is not allowed, when the START bit is set.
Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_SetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
AddressingMode This parameter can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT
Return values:
None

Definition at line 778 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | PeripheralMode
 | ) |  |

Configure peripheral mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_SetMode
CR1 SMBDEN LL_I2C_SetMode
Parameters:
I2Cx I2C Instance.
PeripheralMode This parameter can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP
Return values:
None

Definition at line 984 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress1 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress1,
 |  | uint32_t | OwnAddrSize
 | ) |  |

Set the Own Address1.

Reference Manual to LL API cross reference:
OAR1 OA1 LL_I2C_SetOwnAddress1
OAR1 OA1MODE LL_I2C_SetOwnAddress1
Parameters:
I2Cx | I2C Instance.
OwnAddress1 | This parameter must be a value between 0 and 0x3FF.
OwnAddrSize This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS1_7BIT
  • LL_I2C_OWNADDRESS1_10BIT
Return values:
None

Definition at line 807 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress2 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress2,
 |  | uint32_t | OwnAddrMask
 | ) |  |

Set the 7bits Own Address2.

Note:
This action has no effect if own address2 is enabled.
Reference Manual to LL API cross reference:
OAR2 OA2 LL_I2C_SetOwnAddress2
OAR2 OA2MSK LL_I2C_SetOwnAddress2
Parameters:
I2Cx | I2C Instance.
OwnAddress2 | Value between 0 and 0x7F.
OwnAddrMask This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS2_NOMASK
  • LL_I2C_OWNADDRESS2_MASK01
  • LL_I2C_OWNADDRESS2_MASK02
  • LL_I2C_OWNADDRESS2_MASK03
  • LL_I2C_OWNADDRESS2_MASK04
  • LL_I2C_OWNADDRESS2_MASK05
  • LL_I2C_OWNADDRESS2_MASK06
  • LL_I2C_OWNADDRESS2_MASK07
Return values:
None

Definition at line 863 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA
 | ) |  |

Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1129 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutAMode
 | ) |  |

Set the SMBus Clock TimeoutA mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This bit can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
Return values:
None

Definition at line 1159 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutB is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
Parameters:
I2Cx | I2C Instance.
TimeoutB | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1189 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_TIMEOUTR_TIMEOUTB.

__STATIC_INLINE void LL_I2C_SetTiming | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Timing
 | ) |  |

Configure the SDA setup, hold time and the SCL high, low period.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
TIMINGR TIMINGR LL_I2C_SetTiming
Parameters:
I2Cx | I2C Instance.
Timing | This parameter must be a value between 0 and 0xFFFFFFFF.
Note:
This parameter is computed with the STM32CubeMX Tool.
Return values:
None

Definition at line 910 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT_Management

Functions
IT_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts is enabled of disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_DisableIT_ADDR ( I2C_TypeDef * I2Cx )

Disable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_DisableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1352 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_ERR ( I2C_TypeDef * I2Cx )

Disable Error interrupts.

Note:
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_DisableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1508 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_NACK ( I2C_TypeDef * I2Cx )

Disable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_DisableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1385 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_RX ( I2C_TypeDef * I2Cx )

Disable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_DisableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1319 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_STOP ( I2C_TypeDef * I2Cx )

Disable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_DisableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1418 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TC ( I2C_TypeDef * I2Cx )

Disable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_DisableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1457 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TX ( I2C_TypeDef * I2Cx )

Disable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_DisableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1286 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ADDR ( I2C_TypeDef * I2Cx )

Enable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_EnableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1341 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ERR ( I2C_TypeDef * I2Cx )

Enable Error interrupts.

Note:
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_EnableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1488 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_NACK ( I2C_TypeDef * I2Cx )

Enable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_EnableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1374 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_RX ( I2C_TypeDef * I2Cx )

Enable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_EnableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1308 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_STOP ( I2C_TypeDef * I2Cx )

Enable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_EnableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1407 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TC ( I2C_TypeDef * I2Cx )

Enable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_EnableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1443 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TX ( I2C_TypeDef * I2Cx )

Enable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_EnableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1275 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR ( I2C_TypeDef * I2Cx )

Check if Address match interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1363 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR ( I2C_TypeDef * I2Cx )

Check if Error interrupts is enabled of disabled.

Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_IsEnabledIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1519 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK ( I2C_TypeDef * I2Cx )

Check if Not acknowledge received interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_IsEnabledIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1396 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX ( I2C_TypeDef * I2Cx )

Check if the RXNE Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_IsEnabledIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1330 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP ( I2C_TypeDef * I2Cx )

Check if STOP detection interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_IsEnabledIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1429 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC ( I2C_TypeDef * I2Cx )

Check if Transfer Complete interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_IsEnabledIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1468 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX ( I2C_TypeDef * I2Cx )

Check if the TXIS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_IsEnabledIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1297 of file stm32l4xx_ll_i2c.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG_management

Functions
FLAG_management
I2C Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.

Function Documentation

__STATIC_INLINE void LL_I2C_ClearFlag_ADDR ( I2C_TypeDef * I2Cx )

Clear Address Matched flag.

Reference Manual to LL API cross reference:
ICR ADDRCF LL_I2C_ClearFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1694 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_ARLO ( I2C_TypeDef * I2Cx )

Clear Arbitration lost flag.

Reference Manual to LL API cross reference:
ICR ARLOCF LL_I2C_ClearFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1750 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_BERR ( I2C_TypeDef * I2Cx )

Clear Bus error flag.

Reference Manual to LL API cross reference:
ICR BERRCF LL_I2C_ClearFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1739 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_NACK ( I2C_TypeDef * I2Cx )

Clear Not Acknowledge flag.

Reference Manual to LL API cross reference:
ICR NACKCF LL_I2C_ClearFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1705 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_OVR ( I2C_TypeDef * I2Cx )

Clear Overrun/Underrun flag.

Reference Manual to LL API cross reference:
ICR OVRCF LL_I2C_ClearFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1761 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_STOP ( I2C_TypeDef * I2Cx )

Clear Stop detection flag.

Reference Manual to LL API cross reference:
ICR STOPCF LL_I2C_ClearFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1716 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_TXE ( I2C_TypeDef * I2Cx )

Clear Transmit data register empty flag (TXE).

Note:
This bit can be clear by software in order to flush the transmit data register (TXDR).
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_ClearFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1728 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Clear SMBus Alert flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1846 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Clear SMBus PEC error flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1820 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Clear SMBus Timeout detection flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1833 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR ( I2C_TypeDef * I2Cx )

Indicate the status of Address matched flag (slave mode).

Note:
RESET: Clear default value. SET: When the received slave address matched with one of the enabled slave address.
Reference Manual to LL API cross reference:
ISR ADDR LL_I2C_IsActiveFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1579 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO ( I2C_TypeDef * I2Cx )

Indicate the status of Arbitration lost flag.

Note:
RESET: Clear default value. SET: When arbitration lost.
Reference Manual to LL API cross reference:
ISR ARLO LL_I2C_IsActiveFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1657 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR ( I2C_TypeDef * I2Cx )

Indicate the status of Bus error flag.

Note:
RESET: Clear default value. SET: When a misplaced Start or Stop condition is detected.
Reference Manual to LL API cross reference:
ISR BERR LL_I2C_IsActiveFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1644 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY ( I2C_TypeDef * I2Cx )

Indicate the status of Bus Busy flag.

Note:
RESET: Clear default value. SET: When a Start condition is detected.
Reference Manual to LL API cross reference:
ISR BUSY LL_I2C_IsActiveFlag_BUSY
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1683 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK ( I2C_TypeDef * I2Cx )

Indicate the status of Not Acknowledge received flag.

Note:
RESET: Clear default value. SET: When a NACK is received after a byte transmission.
Reference Manual to LL API cross reference:
ISR NACKF LL_I2C_IsActiveFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1592 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR ( I2C_TypeDef * I2Cx )

Indicate the status of Overrun/Underrun flag (slave mode).

Note:
RESET: Clear default value. SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
Reference Manual to LL API cross reference:
ISR OVR LL_I2C_IsActiveFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1670 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE ( I2C_TypeDef * I2Cx )

Indicate the status of Receive data register not empty flag.

Note:
RESET: When Receive data register is read. SET: When the received data is copied in Receive data register.
Reference Manual to LL API cross reference:
ISR RXNE LL_I2C_IsActiveFlag_RXNE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1566 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP ( I2C_TypeDef * I2Cx )

Indicate the status of Stop detection flag.

Note:
RESET: Clear default value. SET: When a Stop condition is detected.
Reference Manual to LL API cross reference:
ISR STOPF LL_I2C_IsActiveFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1605 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC ( I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TC LL_I2C_IsActiveFlag_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1618 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR ( I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=1 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TCR LL_I2C_IsActiveFlag_TCR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1631 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit data register empty flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_IsActiveFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1540 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit interrupt flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXIS LL_I2C_IsActiveFlag_TXIS
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1553 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus alert flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When SMBus host configuration, SMBus alert enabled and a falling edge event occurs on SMBA pin.
Reference Manual to LL API cross reference:
ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1807 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus PEC error flag in reception.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When the received PEC does not match with the PEC register content.
Reference Manual to LL API cross reference:
ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1776 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus Timeout detection flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When a timeout or extended clock timeout occurs.
Reference Manual to LL API cross reference:
ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1791 of file stm32l4xx_ll_i2c.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data_Management

Functions
Data_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .

Function Documentation

__STATIC_INLINE void LL_I2C_AcknowledgeNextData | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TypeAcknowledge
 | ) |  |

Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.

Note:
Usage in Slave mode only.
Reference Manual to LL API cross reference:
CR2 NACK LL_I2C_AcknowledgeNextData
Parameters:
I2Cx I2C Instance.
TypeAcknowledge This parameter can be one of the following values:
  • LL_I2C_ACK
  • LL_I2C_NACK
Return values:
None

Definition at line 1964 of file stm32l4xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAuto10BitRead ( I2C_TypeDef * I2Cx )

Disable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master only sends the first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_DisableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2013 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableAutoEndMode ( I2C_TypeDef * I2Cx )

Disable automatic STOP condition generation (master mode).

Note:
Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_DisableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1879 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableReloadMode ( I2C_TypeDef * I2Cx )

Disable reload mode (master mode).

Note:
The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_DisableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1914 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAuto10BitRead ( I2C_TypeDef * I2Cx )

Enable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master sends the complete 10bit slave address read sequence : Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_EnableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2001 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAutoEndMode ( I2C_TypeDef * I2Cx )

Enable automatic STOP condition generation (master mode).

Note:
Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. This bit has no effect in slave mode or when RELOAD bit is set.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_EnableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1867 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableReloadMode ( I2C_TypeDef * I2Cx )

Enable reload mode (master mode).

Note:
The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_EnableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1902 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare ( I2C_TypeDef * I2Cx )

Enable internal comparison of Packet Error byte (transmission or reception mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. This bit has no effect when RELOAD bit is set. This bit has no effect in device mode when SBC bit is not set.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2164 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStartCondition ( I2C_TypeDef * I2Cx )

Generate a START or RESTART condition.

Note:
The START bit can be set even if bus is BUSY or I2C is in slave mode. This action has no effect when RELOAD is set.
Reference Manual to LL API cross reference:
CR2 START LL_I2C_GenerateStartCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1988 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStopCondition ( I2C_TypeDef * I2Cx )

Generate a STOP condition after the current byte transfer (master mode).

Reference Manual to LL API cross reference:
CR2 STOP LL_I2C_GenerateStopCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1975 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode ( I2C_TypeDef * I2Cx )

Return the slave matched address.

Reference Manual to LL API cross reference:
ISR ADDCODE LL_I2C_GetAddressMatchCode
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 2148 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_ISR_ADDCODE.

__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr ( I2C_TypeDef * I2Cx )

Get the slave address programmed for transfer.

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_GetSlaveAddr
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0x3F

Definition at line 2076 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC ( I2C_TypeDef * I2Cx )

Get the Packet Error byte calculated.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
PECR PEC LL_I2C_GetSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2190 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection ( I2C_TypeDef * I2Cx )

Indicate the value of transfer direction (slave mode).

Note:
RESET: Write transfer, Slave enters in receiver mode. SET: Read transfer, Slave enters in transmitter mode.
Reference Manual to LL API cross reference:
ISR DIR LL_I2C_GetTransferDirection
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_DIRECTION_WRITE
  • LL_I2C_DIRECTION_READ

Definition at line 2137 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest ( I2C_TypeDef * I2Cx )

Get the transfer direction requested (master mode).

Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_GetTransferRequest
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ

Definition at line 2052 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferSize ( I2C_TypeDef * I2Cx )

Get the number of bytes configured for transfer.

Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_GetTransferSize
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xFF

Definition at line 1949 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_CR2_NBYTES.

__STATIC_INLINE void LL_I2C_HandleTransfer | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr,
 |  | uint32_t | SlaveAddrSize,
 |  | uint32_t | TransferSize,
 |  | uint32_t | EndMode,
 |  | uint32_t | Request
 | ) |  |

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_HandleTransfer
CR2 ADD10 LL_I2C_HandleTransfer
CR2 RD_WRN LL_I2C_HandleTransfer
CR2 START LL_I2C_HandleTransfer
CR2 STOP LL_I2C_HandleTransfer
CR2 RELOAD LL_I2C_HandleTransfer
CR2 NBYTES LL_I2C_HandleTransfer
CR2 AUTOEND LL_I2C_HandleTransfer
CR2 HEAD10R LL_I2C_HandleTransfer
Parameters:
I2Cx | I2C Instance.
SlaveAddr | Specifies the slave address to be programmed.
SlaveAddrSize This parameter can be one of the following values:
  • LL_I2C_ADDRSLAVE_7BIT
  • LL_I2C_ADDRSLAVE_10BIT
TransferSize | Specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
EndMode This parameter can be one of the following values:
  • LL_I2C_MODE_RELOAD
  • LL_I2C_MODE_AUTOEND
  • LL_I2C_MODE_SOFTEND
  • LL_I2C_MODE_SMBUS_RELOAD
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
Request This parameter can be one of the following values:
  • LL_I2C_GENERATE_NOSTARTSTOP
  • LL_I2C_GENERATE_STOP
  • LL_I2C_GENERATE_START_READ
  • LL_I2C_GENERATE_START_WRITE
  • LL_I2C_GENERATE_RESTART_7BIT_READ
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE
  • LL_I2C_GENERATE_RESTART_10BIT_READ
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE
Return values:
None

Definition at line 2119 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_CR2_NBYTES.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead ( I2C_TypeDef * I2Cx )

Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 2024 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode ( I2C_TypeDef * I2Cx )

Check if automatic STOP condition is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1890 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode ( I2C_TypeDef * I2Cx )

Check if reload mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_IsEnabledReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1925 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare ( I2C_TypeDef * I2Cx )

Check if Packet Error byte internal comparison is requested or not.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 2177 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE uint8_t LL_I2C_ReceiveData8 ( I2C_TypeDef * I2Cx )

Read Receive Data register.

Reference Manual to LL API cross reference:
RXDR RXDATA LL_I2C_ReceiveData8
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2201 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSlaveAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr
 | ) |  |

Configure the slave address for transfer (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_SetSlaveAddr
Parameters:
I2Cx | I2C Instance.
SlaveAddr | This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
Return values:
None

Definition at line 2065 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferRequest | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferRequest
 | ) |  |

Configure the transfer direction (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_SetTransferRequest
Parameters:
I2Cx I2C Instance.
TransferRequest This parameter can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ
Return values:
None

Definition at line 2039 of file stm32l4xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferSize | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferSize
 | ) |  |

Configure the number of bytes for transfer.

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_SetTransferSize
Parameters:
I2Cx | I2C Instance.
TransferSize | This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 1938 of file stm32l4xx_ll_i2c.h.

References I2C_POSITION_CR2_NBYTES.

__STATIC_INLINE void LL_I2C_TransmitData8 | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Write in Transmit Data Register .

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_TransmitData8
Parameters:
I2Cx | I2C Instance.
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2213 of file stm32l4xx_ll_i2c.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Functions

uint32_t | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
uint32_t | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Function Documentation

uint32_t LL_I2C_DeInit ( I2C_TypeDef * I2Cx )

De-initialize the I2C registers to their default reset values.

Parameters:
I2Cx I2C Instance.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are de-initialized
  • ERROR: I2C registers are not de-initialized

Definition at line 105 of file stm32l4xx_ll_i2c.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_I2C1, LL_APB1_GRP1_PERIPH_I2C2, LL_APB1_GRP1_PERIPH_I2C3, and LL_APB1_GRP1_ReleaseReset().

uint32_t LL_I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | LL_I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initialize the I2C registers according to the specified parameters in I2C_InitStruct.

Parameters:
I2Cx | I2C Instance.
I2C_InitStruct | pointer to a LL_I2C_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are initialized
  • ERROR: Not applicable

Definition at line 155 of file stm32l4xx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, assert_param, LL_I2C_InitTypeDef::DigitalFilter, IS_LL_I2C_ANALOG_FILTER, IS_LL_I2C_DIGITAL_FILTER, IS_LL_I2C_OWN_ADDRESS1, IS_LL_I2C_OWN_ADDRSIZE, IS_LL_I2C_PERIPHERAL_MODE, IS_LL_I2C_TYPE_ACKNOWLEDGE, LL_I2C_AcknowledgeNextData(), LL_I2C_ConfigFilters(), LL_I2C_Disable(), LL_I2C_DisableOwnAddress1(), LL_I2C_Enable(), LL_I2C_EnableOwnAddress1(), LL_I2C_SetMode(), LL_I2C_SetOwnAddress1(), LL_I2C_SetTiming(), LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

void LL_I2C_StructInit ( LL_I2C_InitTypeDef * I2C_InitStruct )

Set each LL_I2C_InitTypeDef field to default value.

Parameters:
I2C_InitStruct Pointer to a LL_I2C_InitTypeDef structure.
Return values:
None

Definition at line 218 of file stm32l4xx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, LL_I2C_InitTypeDef::DigitalFilter, LL_I2C_ANALOGFILTER_ENABLE, LL_I2C_MODE_I2C, LL_I2C_NACK, LL_I2C_OWNADDRESS1_7BIT, LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG

Modules
IWDG
STM32L4xx_LL_Driver

Modules

IWDG Private Constants
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for IWDG registers.

Register | Bit | Function
KR | KEY | LL_IWDG_DisableWriteAccess
 |  | LL_IWDG_Enable
 |  | LL_IWDG_EnableWriteAccess
 |  | LL_IWDG_ReloadCounter
PR | PR | LL_IWDG_GetPrescaler
 |  | LL_IWDG_SetPrescaler
RLR | RL | LL_IWDG_GetReloadCounter
 |  | LL_IWDG_SetReloadCounter
SR | PVU | LL_IWDG_IsActiveFlag_PVU
 |  | LL_IWDG_IsReady
 | RVU | LL_IWDG_IsActiveFlag_RVU
 |  | LL_IWDG_IsReady
 | WVU | LL_IWDG_IsActiveFlag_WVU
 |  | LL_IWDG_IsReady
WINR | WIN | LL_IWDG_GetWindow
 |  | LL_IWDG_SetWindow
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | LL_IWDG_KEY_RELOAD ((uint32_t)0x0000AAAAU)
#define | LL_IWDG_KEY_ENABLE ((uint32_t)0x0000CCCCU)
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE ((uint32_t)0x00005555U)
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define LL_IWDG_KEY_ENABLE ((uint32_t)0x0000CCCCU)

IWDG Peripheral Enable

Definition at line 68 of file stm32l4xx_ll_iwdg.h.

Referenced by LL_IWDG_Enable().

#define LL_IWDG_KEY_RELOAD ((uint32_t)0x0000AAAAU)

IWDG Reload Counter Enable

Definition at line 67 of file stm32l4xx_ll_iwdg.h.

Referenced by LL_IWDG_ReloadCounter().

#define LL_IWDG_KEY_WR_ACCESS_DISABLE ((uint32_t)0x00000000U)

IWDG KR Write Access Disable

Definition at line 70 of file stm32l4xx_ll_iwdg.h.

Referenced by LL_IWDG_DisableWriteAccess().

#define LL_IWDG_KEY_WR_ACCESS_ENABLE ((uint32_t)0x00005555U)

IWDG KR Write Access Enable

Definition at line 69 of file stm32l4xx_ll_iwdg.h.

Referenced by LL_IWDG_EnableWriteAccess().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
IWDG Exported Constants

Flags defines which can be used with LL_IWDG_ReadReg function. More...

Defines

#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU

Detailed Description

Flags defines which can be used with LL_IWDG_ReadReg function.

Define Documentation

#define LL_IWDG_SR_PVU IWDG_SR_PVU

Watchdog prescaler value update

Definition at line 88 of file stm32l4xx_ll_iwdg.h.

#define LL_IWDG_SR_RVU IWDG_SR_RVU

Watchdog counter reload value update

Definition at line 89 of file stm32l4xx_ll_iwdg.h.

#define LL_IWDG_SR_WVU IWDG_SR_WVU

Watchdog counter window value update

Definition at line 90 of file stm32l4xx_ll_iwdg.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Prescaler Divider

Defines
Prescaler Divider
IWDG Exported Constants

Defines

#define | LL_IWDG_PRESCALER_4 ((uint32_t)0x00000000U)
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

Divider by 128

Definition at line 104 of file stm32l4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)

Divider by 16

Definition at line 101 of file stm32l4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Divider by 256

Definition at line 105 of file stm32l4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

Divider by 32

Definition at line 102 of file stm32l4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_4 ((uint32_t)0x00000000U)

Divider by 4

Definition at line 99 of file stm32l4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)

Divider by 64

Definition at line 103 of file stm32l4xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)

Divider by 8

Definition at line 100 of file stm32l4xx_ll_iwdg.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
IWDG Exported Macros

Defines

#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Define Documentation

#define LL_IWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 138 of file stm32l4xx_ll_iwdg.h.

#define LL_IWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 130 of file stm32l4xx_ll_iwdg.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration

Functions
Configuration
IWDG Exported Functions

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.

Function Documentation

__STATIC_INLINE void LL_IWDG_DisableWriteAccess ( IWDG_TypeDef * IWDGx )

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_DisableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 196 of file stm32l4xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_DISABLE.

__STATIC_INLINE void LL_IWDG_Enable ( IWDG_TypeDef * IWDGx )

Start the Independent Watchdog.

Note:
Except if the hardware watchdog option is selected
Reference Manual to LL API cross reference:
KR KEY LL_IWDG_Enable
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 163 of file stm32l4xx_ll_iwdg.h.

References LL_IWDG_KEY_ENABLE.

__STATIC_INLINE void LL_IWDG_EnableWriteAccess ( IWDG_TypeDef * IWDGx )

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_EnableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 185 of file stm32l4xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_ENABLE.

__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler ( IWDG_TypeDef * IWDGx )

Get the selected prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_GetPrescaler
Parameters:
IWDGx IWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256

Definition at line 233 of file stm32l4xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter ( IWDG_TypeDef * IWDGx )

Get the specified IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_GetReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 256 of file stm32l4xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetWindow ( IWDG_TypeDef * IWDGx )

Get the high limit of the window value specified.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_GetWindow
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 279 of file stm32l4xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_ReloadCounter ( IWDG_TypeDef * IWDGx )

Reloads IWDG counter with value defined in the reload register.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_ReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 174 of file stm32l4xx_ll_iwdg.h.

References LL_IWDG_KEY_RELOAD.

__STATIC_INLINE void LL_IWDG_SetPrescaler | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Select the prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_SetPrescaler
Parameters:
IWDGx IWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256
Return values:
None

Definition at line 215 of file stm32l4xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetReloadCounter | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Counter
 | ) |  |

Specify the IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_SetReloadCounter
Parameters:
IWDGx | IWDG Instance
Counter | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 245 of file stm32l4xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetWindow | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Window
 | ) |  |

Specify high limit of the window value to be compared to the down-counter.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_SetWindow
Parameters:
IWDGx | IWDG Instance
Window | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 268 of file stm32l4xx_ll_iwdg.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
IWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Function Documentation

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU ( IWDG_TypeDef * IWDGx )

Check if flag Prescaler Value Update is set or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsActiveFlag_PVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 298 of file stm32l4xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU ( IWDG_TypeDef * IWDGx )

Check if flag Reload Value Update is set or not.

Reference Manual to LL API cross reference:
SR RVU LL_IWDG_IsActiveFlag_RVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 309 of file stm32l4xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU ( IWDG_TypeDef * IWDGx )

Check if flag Window Value Update is set or not.

Reference Manual to LL API cross reference:
SR WVU LL_IWDG_IsActiveFlag_WVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 320 of file stm32l4xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsReady ( IWDG_TypeDef * IWDGx )

Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsReady
SR WVU LL_IWDG_IsReady
SR RVU LL_IWDG_IsReady
Parameters:
IWDGx IWDG Instance
Return values:
State of bits (1 or 0).

Definition at line 333 of file stm32l4xx_ll_iwdg.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM

Modules
LPTIM
STM32L4xx_LL_Driver

Modules

LPTIM Private Macros
LPTIM Exported Init structure
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for LPTIM registers.

Register | Bit | Function
ARR | ARR | LL_LPTIM_GetAutoReload
 |  | LL_LPTIM_SetAutoReload
CFGR | CKFLT | LL_LPTIM_ConfigClock
 |  | LL_LPTIM_GetClockFilter
 | CKPOL | LL_LPTIM_ConfigClock
 |  | LL_LPTIM_GetClockPolarity
 |  | LL_LPTIM_GetEncoderMode
 |  | LL_LPTIM_SetEncoderMode
 | CKSEL | LL_LPTIM_GetClockSource
 |  | LL_LPTIM_SetClockSource
 | COUNTMODE | LL_LPTIM_GetCounterMode
 |  | LL_LPTIM_SetCounterMode
 | ENC | LL_LPTIM_DisableEncoderMode
 |  | LL_LPTIM_EnableEncoderMode
 |  | LL_LPTIM_IsEnabledEncoderMode
 | PRELOAD | LL_LPTIM_GetUpdateMode
 |  | LL_LPTIM_SetUpdateMode
 | PRESC | LL_LPTIM_GetPrescaler
 |  | LL_LPTIM_SetPrescaler
 | TIMOUT | LL_LPTIM_DisableTimeout
 |  | LL_LPTIM_EnableTimeout
 |  | LL_LPTIM_IsEnabledTimeout
 | TRGFLT | LL_LPTIM_ConfigTrigger
 |  | LL_LPTIM_GetTriggerFilter
 | TRIGEN | LL_LPTIM_ConfigTrigger
 |  | LL_LPTIM_GetTriggerPolarity
 |  | LL_LPTIM_TrigSw
 | TRIGSEL | LL_LPTIM_ConfigTrigger
 |  | LL_LPTIM_GetTriggerSource
 | WAVE | LL_LPTIM_ConfigOutput
 |  | LL_LPTIM_GetWaveform
 |  | LL_LPTIM_SetWaveform
 | WAVPOL | LL_LPTIM_ConfigOutput
 |  | LL_LPTIM_GetPolarity
 |  | LL_LPTIM_SetPolarity
CMP | CMP | LL_LPTIM_GetCompare
 |  | LL_LPTIM_SetCompare
CNT | CNT | LL_LPTIM_GetCounter
CR | CNTSTRT | LL_LPTIM_StartCounter
 | ENABLE | LL_LPTIM_Disable
 |  | LL_LPTIM_Enable
 |  | LL_LPTIM_IsEnabled
 | SNGSTRT | LL_LPTIM_StartCounter
ICR | ARRMCF | LL_LPTIM_ClearFLAG_ARRM
 | ARROKCF | LL_LPTIM_ClearFlag_ARROK
 | CMPMCF | LL_LPTIM_ClearFLAG_CMPM
 | CMPOKCF | LL_LPTIM_ClearFlag_CMPOK
 | DOWNCF | LL_LPTIM_ClearFlag_DOWN
 | EXTTRIGCF | LL_LPTIM_ClearFlag_EXTTRIG
 | UPCF | LL_LPTIM_ClearFlag_UP
IER | ARRMIE | LL_LPTIM_DisableIT_ARRM
 |  | LL_LPTIM_EnableIT_ARRM
 |  | LL_LPTIM_IsEnabledIT_ARRM
 | ARROKIE | LL_LPTIM_DisableIT_ARROK
 |  | LL_LPTIM_EnableIT_ARROK
 |  | LL_LPTIM_IsEnabledIT_ARROK
 | CMPMIE | LL_LPTIM_DisableIT_CMPM
 |  | LL_LPTIM_EnableIT_CMPM
 |  | LL_LPTIM_IsEnabledIT_CMPM
 | CMPOKIE | LL_LPTIM_DisableIT_CMPOK
 |  | LL_LPTIM_EnableIT_CMPOK
 |  | LL_LPTIM_IsEnabledIT_CMPOK
 | DOWNIE | LL_LPTIM_DisableIT_DOWN
 |  | LL_LPTIM_EnableIT_DOWN
 |  | LL_LPTIM_IsEnabledIT_DOWN
 | EXTTRIGIE | LL_LPTIM_DisableIT_EXTTRIG
 |  | LL_LPTIM_EnableIT_EXTTRIG
 |  | LL_LPTIM_IsEnabledIT_EXTTRIG
 | UPIE | LL_LPTIM_DisableIT_UP
 |  | LL_LPTIM_EnableIT_UP
 |  | LL_LPTIM_IsEnabledIT_UP
ISR | ARRM | LL_LPTIM_IsActiveFlag_ARRM
 | ARROK | LL_LPTIM_IsActiveFlag_ARROK
 | CMPM | LL_LPTIM_IsActiveFlag_CMPM
 | CMPOK | LL_LPTIM_IsActiveFlag_CMPOK
 | DOWN | LL_LPTIM_IsActiveFlag_DOWN
 | EXTTRIG | LL_LPTIM_IsActiveFlag_EXTTRIG
 | UP | LL_LPTIM_IsActiveFlag_UP
OR | OR_0 | LL_LPTIM_SetInput1Src
 |  | LL_LPTIM_SetInput2Src
 | OR_1 | LL_LPTIM_SetInput1Src
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LPTIM_CLOCK_SOURCE(__VALUE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__VALUE__)
#define | IS_LPTIM_WAVEFORM(__VALUE__)
#define | IS_LPTIM_OUTPUT_POLARITY(__VALUE__)

Define Documentation

#define IS_LPTIM_CLOCK_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))

Definition at line 69 of file stm32l4xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LPTIM_CLOCK_SOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
                                       || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))

Definition at line 66 of file stm32l4xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LPTIM_OUTPUT_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
                                          || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))

Definition at line 81 of file stm32l4xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LPTIM_WAVEFORM ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
                                   || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))

Definition at line 78 of file stm32l4xx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_LPTIM_InitTypeDef Struct Reference
LPTIM Exported Init structure

LPTIM Init structure definition. More...

#include <stm32l4xx_ll_lptim.h>

Data Fields

uint32_t | ClockSource
uint32_t | Prescaler
uint32_t | Waveform
uint32_t | Polarity

Detailed Description

LPTIM Init structure definition.

Definition at line 83 of file stm32l4xx_ll_lptim.h.

Field Documentation

uint32_t LL_LPTIM_InitTypeDef::ClockSource

Specifies the source of the clock used by the LPTIM instance. This parameter can be a value of Clock Source.

This feature can be modified afterwards using unitary function LL_LPTIM_SetClockSource().

Definition at line 85 of file stm32l4xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Polarity

Specifies waveform polarity. This parameter can be a value of Output Polarity.

This feature can be modified afterwards using unitary function LL_LPTIM_ConfigOutput().

Definition at line 100 of file stm32l4xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Prescaler

Specifies the prescaler division ratio. This parameter can be a value of Prescaler Value.

This feature can be modified afterwards using using unitary function LL_LPTIM_SetPrescaler().

Definition at line 90 of file stm32l4xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Waveform

Specifies the waveform shape. This parameter can be a value of Output Waveform Type.

This feature can be modified afterwards using unitary function LL_LPTIM_ConfigOutput().

Definition at line 95 of file stm32l4xx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_lptim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
LPTIM Exported Constants

Flags defines which can be used with LL_LPTIM_ReadReg function. More...

Defines

#define | LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM
#define | LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM
#define | LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK
#define | LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK
#define | LL_LPTIM_ISR_UP LPTIM_ISR_UP
#define | LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Detailed Description

Flags defines which can be used with LL_LPTIM_ReadReg function.

Define Documentation

#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM

Autoreload match

Definition at line 121 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK

Autoreload register update OK

Definition at line 124 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM

Compare match

Definition at line 120 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK

Compare register update OK

Definition at line 123 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Counter direction change up to down

Definition at line 126 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG

External trigger edge event

Definition at line 122 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_ISR_UP LPTIM_ISR_UP

Counter direction change down to up

Definition at line 125 of file stm32l4xx_ll_lptim.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
LPTIM Exported Constants

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions. More...

Defines

#define | LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE
#define | LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE
#define | LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE
#define | LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE
#define | LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE
#define | LL_LPTIM_IER_UPIE LPTIM_IER_UPIE
#define | LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE

Detailed Description

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions.

Define Documentation

#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE

Autoreload match Interrupt Enable

Definition at line 136 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE

Autoreload register update OK Interrupt Enable

Definition at line 139 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE

Compare match Interrupt Enable

Definition at line 135 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE

Compare register update OK Interrupt Enable

Definition at line 138 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE

Direction change to down Interrupt Enable

Definition at line 141 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE

External trigger valid edge Interrupt Enable

Definition at line 137 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE

Direction change to UP Interrupt Enable

Definition at line 140 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Operating Mode

Defines
Operating Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT
#define | LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

Define Documentation

#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT

LP Timer starts in continuous mode

Definition at line 149 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

LP Tilmer starts in single mode

Definition at line 150 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Update Mode

Defines
Update Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_UPDATE_MODE_IMMEDIATE ((uint32_t)0x00000000U)
#define | LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

preload is enabled: registers are updated at the end of the current LPTIM period

Definition at line 159 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_UPDATE_MODE_IMMEDIATE ((uint32_t)0x00000000U)

Preload is disabled: registers are updated after each APB bus write access

Definition at line 158 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Counter Mode

Defines
Counter Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_COUNTER_MODE_INTERNAL ((uint32_t)0x00000000U)
#define | LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

The counter is incremented following each valid clock pulse on the LPTIM external Input1

Definition at line 168 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_COUNTER_MODE_INTERNAL ((uint32_t)0x00000000U)

The counter is incremented following each internal clock pulse

Definition at line 167 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Output Waveform Type

Defines
Output Waveform Type
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OUTPUT_WAVEFORM_PWM ((uint32_t)0x00000000U)
#define | LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

Define Documentation

#define LL_LPTIM_OUTPUT_WAVEFORM_PWM ((uint32_t)0x00000000U)

LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE

Definition at line 176 of file stm32l4xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

LPTIM generates a Set Once waveform

Definition at line 177 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Output Polarity

Defines
Output Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OUTPUT_POLARITY_REGULAR ((uint32_t) 0x00000000U)
#define | LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL

Define Documentation

#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL

The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers

Definition at line 186 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_OUTPUT_POLARITY_REGULAR ((uint32_t) 0x00000000U)

The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers

Definition at line 185 of file stm32l4xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

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STM32L486xx HAL User Manual: Prescaler Value

Defines
Prescaler Value
LPTIM Exported Constants

Defines

#define | LL_LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
#define | LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)
#define | LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Define Documentation

#define LL_LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)

Prescaler division factor is set to 1

Definition at line 194 of file stm32l4xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Prescaler division factor is set to 128

Definition at line 201 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Prescaler division factor is set to 16

Definition at line 198 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Prescaler division factor is set to 2

Definition at line 195 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 32

Definition at line 199 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Prescaler division factor is set to 4

Definition at line 196 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)

Prescaler division factor is set to 64

Definition at line 200 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 8

Definition at line 197 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Trigger Source

Defines
Trigger Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_SOURCE_GPIO ((uint32_t)0x00000000U)
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)
#define | LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL

Define Documentation

#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)

External input trigger is connected to COMP1 output

Definition at line 215 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL

External input trigger is connected to COMP2 output

Definition at line 216 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_GPIO ((uint32_t)0x00000000U)

External input trigger is connected to TIMx_ETR input

Definition at line 209 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0

External input trigger is connected to RTC Alarm A

Definition at line 210 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1

External input trigger is connected to RTC Alarm B

Definition at line 211 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 1

Definition at line 212 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2

External input trigger is connected to RTC Tamper 2

Definition at line 213 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 3

Definition at line 214 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Trigger Filter

Defines
Trigger Filter
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_FILTER_NONE ((uint32_t)0x00000000U)
#define | LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0
#define | LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1
#define | LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Define Documentation

#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0

Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger

Definition at line 225 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1

Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger

Definition at line 226 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

Definition at line 227 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_NONE ((uint32_t)0x00000000U)

Any trigger active level change is considered as a valid trigger

Definition at line 224 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Trigger Polarity

Defines
Trigger Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0
#define | LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1
#define | LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1

LPTIM counter starts when a falling edge is detected

Definition at line 236 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0

LPTIM counter starts when a rising edge is detected

Definition at line 235 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

LPTIM counter starts when a rising or a falling edge is detected

Definition at line 237 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Clock Source

Defines
Clock Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_SOURCE_INTERNAL ((uint32_t)0x00000000U)
#define | LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

Define Documentation

#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

LPTIM is clocked by an external clock source through the LPTIM external Input1

Definition at line 246 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_CLK_SOURCE_INTERNAL ((uint32_t)0x00000000U)

LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)

Definition at line 245 of file stm32l4xx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

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STM32L486xx HAL User Manual: Clock Filter

Defines
Clock Filter
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_FILTER_NONE ((uint32_t)0x00000000U)
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

Define Documentation

#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0

External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition

Definition at line 255 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1

External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition

Definition at line 256 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

Definition at line 257 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_NONE ((uint32_t)0x00000000U)

Any external clock signal level change is considered as a valid transition

Definition at line 254 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_POLARITY_RISING ((uint32_t)0x00000000U)
#define | LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

Definition at line 266 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_CLK_POLARITY_RISING ((uint32_t)0x00000000U)

The rising edge is the active edge used for counting

Definition at line 265 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Definition at line 267 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Encoder Mode

Defines
Encoder Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_ENCODER_MODE_RISING ((uint32_t)0x00000000U)
#define | LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

Definition at line 276 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_ENCODER_MODE_RISING ((uint32_t)0x00000000U)

The rising edge is the active edge used for counting

Definition at line 275 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Definition at line 277 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Input1 Source

Defines
Input1 Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_INPUT1_SRC_GPIO ((uint32_t)0x00000000U)
#define | LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0
#define | LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1
#define | LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR

Define Documentation

#define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0

For LPTIM1 and LPTIM2

Definition at line 287 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR

For LPTIM2

Definition at line 289 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1

For LPTIM2

Definition at line 288 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_GPIO ((uint32_t)0x00000000U)

For LPTIM1 and LPTIM2

Definition at line 286 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Input2 Source

Defines
Input2 Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_INPUT2_SRC_GPIO ((uint32_t)0x00000000U)
#define | LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1

Define Documentation

#define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1

For LPTIM1

Definition at line 299 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_INPUT2_SRC_GPIO ((uint32_t)0x00000000U)

For LPTIM1

Definition at line 298 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
LPTIM Exported Macros

Defines

#define | LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPTIM register.
#define | LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPTIM register.

Define Documentation

#define LL_LPTIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in LPTIM register.

Parameters:
__INSTANCE__ | LPTIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 332 of file stm32l4xx_ll_lptim.h.

#define LL_LPTIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in LPTIM register.

Parameters:
__INSTANCE__ | LPTIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 324 of file stm32l4xx_ll_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Configuration

Functions
LPTIM Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_Enable (LPTIM_TypeDef *LPTIMx)
Enable the LPTIM instance.
__STATIC_INLINE void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabled (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM instance is enabled.
__STATIC_INLINE void | LL_LPTIM_StartCounter (LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
Starts the LPTIM counter in the desired mode.
__STATIC_INLINE void | LL_LPTIM_SetUpdateMode (LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
Set the LPTIM registers update mode (enable/disable register preload)
__STATIC_INLINE uint32_t | LL_LPTIM_GetUpdateMode (LPTIM_TypeDef *LPTIMx)
Get the LPTIM registers update mode.
__STATIC_INLINE void | LL_LPTIM_SetAutoReload (LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
Set the auto reload value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetAutoReload (LPTIM_TypeDef *LPTIMx)
Get actual auto reload value.
__STATIC_INLINE void | LL_LPTIM_SetCompare (LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
Set the compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCompare (LPTIM_TypeDef *LPTIMx)
Get actual compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounter (LPTIM_TypeDef *LPTIMx)
Get actual counter value.
__STATIC_INLINE void | LL_LPTIM_SetCounterMode (LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
Set the counter mode (selection of the LPTIM counter clock source).
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounterMode (LPTIM_TypeDef *LPTIMx)
Get the counter mode.
__STATIC_INLINE void | LL_LPTIM_ConfigOutput (LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
Configure the LPTIM instance output (LPTIMx_OUT)
__STATIC_INLINE void | LL_LPTIM_SetWaveform (LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
Set waveform shape.
__STATIC_INLINE uint32_t | LL_LPTIM_GetWaveform (LPTIM_TypeDef *LPTIMx)
Get actual waveform shape.
__STATIC_INLINE void | LL_LPTIM_SetPolarity (LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
Set output polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPolarity (LPTIM_TypeDef *LPTIMx)
Get actual output polarity.
__STATIC_INLINE void | LL_LPTIM_SetPrescaler (LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
Set actual prescaler division ratio.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPrescaler (LPTIM_TypeDef *LPTIMx)
Get actual prescaler division ratio.
__STATIC_INLINE void | LL_LPTIM_SetInput1Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 1 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_SetInput2Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 2 source (default GPIO).

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigOutput | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Waveform,
 |  | uint32_t | Polarity
 | ) |  |

Configure the LPTIM instance output (LPTIMx_OUT)

Note:
This function must be called when the LPTIM instance is disabled.
Regarding the LPTIM output polarity the change takes effect immediately, so the output default value will change immediately after the polarity is re-configured, even before the timer is enabled.
Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_ConfigOutput
CFGR WAVPOL LL_LPTIM_ConfigOutput
Parameters:
LPTIMx Low-Power Timer instance
Waveform This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Polarity This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE
Return values:
None

Definition at line 548 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_Disable ( LPTIM_TypeDef * LPTIMx )

Disable the LPTIM instance.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Disable
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 370 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_Enable ( LPTIM_TypeDef * LPTIMx )

Enable the LPTIM instance.

Note:
After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM instance is actually enabled.
Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Enable
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 359 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload ( LPTIM_TypeDef * LPTIMx )

Get actual auto reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_LPTIM_GetAutoReload
Parameters:
LPTIMx Low-Power Timer instance
Return values:
AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 456 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCompare ( LPTIM_TypeDef * LPTIMx )

Get actual compare value.

Reference Manual to LL API cross reference:
CMP CMP LL_LPTIM_GetCompare
Parameters:
LPTIMx Low-Power Timer instance
Return values:
CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 483 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCounter ( LPTIM_TypeDef * LPTIMx )

Get actual counter value.

Note:
When the LPTIM instance is running with an asynchronous clock, reading the LPTIMx_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
Reference Manual to LL API cross reference:
CNT CNT LL_LPTIM_GetCounter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Counter value

Definition at line 498 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode ( LPTIM_TypeDef * LPTIMx )

Get the counter mode.

Reference Manual to LL API cross reference:
CFGR COUNTMODE LL_LPTIM_GetCounterMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_COUNTER_MODE_INTERNAL
  • LL_LPTIM_COUNTER_MODE_EXTERNAL

Definition at line 526 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity ( LPTIM_TypeDef * LPTIMx )

Get actual output polarity.

Reference Manual to LL API cross reference:
CFGR WAVPOL LL_LPTIM_GetPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE

Definition at line 602 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler ( LPTIM_TypeDef * LPTIMx )

Get actual prescaler division ratio.

Reference Manual to LL API cross reference:
CFGR PRESC LL_LPTIM_GetPrescaler
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_PRESCALER_DIV1
  • LL_LPTIM_PRESCALER_DIV2
  • LL_LPTIM_PRESCALER_DIV4
  • LL_LPTIM_PRESCALER_DIV8
  • LL_LPTIM_PRESCALER_DIV16
  • LL_LPTIM_PRESCALER_DIV32
  • LL_LPTIM_PRESCALER_DIV64
  • LL_LPTIM_PRESCALER_DIV128

Definition at line 646 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode ( LPTIM_TypeDef * LPTIMx )

Get the LPTIM registers update mode.

Reference Manual to LL API cross reference:
CFGR PRELOAD LL_LPTIM_GetUpdateMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD

Definition at line 427 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform ( LPTIM_TypeDef * LPTIMx )

Get actual waveform shape.

Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_GetWaveform
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE

Definition at line 575 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled ( LPTIM_TypeDef * LPTIMx )

Indicates whether the LPTIM instance is enabled.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_IsEnabled
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 381 of file stm32l4xx_ll_lptim.h.

Referenced by LL_LPTIM_Init().

__STATIC_INLINE void LL_LPTIM_SetAutoReload | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto reload value.

Note:
The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
After a write to the LPTIMx_ARR register a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before the ARROK flag be set, will lead to unpredictable results.
autoreload value be strictly greater than the compare value.
Reference Manual to LL API cross reference:
ARR ARR LL_LPTIM_SetAutoReload
Parameters:
LPTIMx | Low-Power Timer instance
AutoReload | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 445 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetCompare | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set the compare value.

Note:
After a write to the LPTIMx_CMP register a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before the CMPOK flag be set, will lead to unpredictable results.
Reference Manual to LL API cross reference:
CMP CMP LL_LPTIM_SetCompare
Parameters:
LPTIMx | Low-Power Timer instance
CompareValue | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 472 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetCounterMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the counter mode (selection of the LPTIM counter clock source).

Note:
The counter mode can be set only when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR COUNTMODE LL_LPTIM_SetCounterMode
Parameters:
LPTIMx Low-Power Timer instance
CounterMode This parameter can be one of the following values:
  • LL_LPTIM_COUNTER_MODE_INTERNAL
  • LL_LPTIM_COUNTER_MODE_EXTERNAL
Return values:
None

Definition at line 513 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetInput1Src | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Src
 | ) |  |

Set LPTIM input 1 source (default GPIO).

Reference Manual to LL API cross reference:
OR OR_0 LL_LPTIM_SetInput1Src
Reference Manual to LL API cross reference:
OR OR_1 LL_LPTIM_SetInput1Src
Parameters:
LPTIMx Low-Power Timer instance
Src This parameter can be one of the following values:
  • LL_LPTIM_INPUT1_SRC_GPIO
  • LL_LPTIM_INPUT1_SRC_COMP1
  • LL_LPTIM_INPUT1_SRC_COMP2
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2
Return values:
None

Definition at line 663 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetInput2Src | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Src
 | ) |  |

Set LPTIM input 2 source (default GPIO).

Reference Manual to LL API cross reference:
OR OR_0 LL_LPTIM_SetInput2Src
Parameters:
LPTIMx Low-Power Timer instance
Src This parameter can be one of the following values:
  • LL_LPTIM_INPUT2_SRC_GPIO
  • LL_LPTIM_INPUT2_SRC_COMP2
Return values:
None

Definition at line 677 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetPolarity | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Polarity
 | ) |  |

Set output polarity.

Reference Manual to LL API cross reference:
CFGR WAVPOL LL_LPTIM_SetPolarity
Parameters:
LPTIMx Low-Power Timer instance
Polarity This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE
Return values:
None

Definition at line 589 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetPrescaler | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set actual prescaler division ratio.

Note:
This function must be called when the LPTIM instance is disabled.
When the LPTIM is configured to be clocked by an internal clock source and the LPTIM counter is configured to be updated by active edges detected on the LPTIM external Input1, the internal clock provided to the LPTIM must be not be prescaled.
Reference Manual to LL API cross reference:
CFGR PRESC LL_LPTIM_SetPrescaler
Parameters:
LPTIMx Low-Power Timer instance
Prescaler This parameter can be one of the following values:
  • LL_LPTIM_PRESCALER_DIV1
  • LL_LPTIM_PRESCALER_DIV2
  • LL_LPTIM_PRESCALER_DIV4
  • LL_LPTIM_PRESCALER_DIV8
  • LL_LPTIM_PRESCALER_DIV16
  • LL_LPTIM_PRESCALER_DIV32
  • LL_LPTIM_PRESCALER_DIV64
  • LL_LPTIM_PRESCALER_DIV128
Return values:
None

Definition at line 627 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetUpdateMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | UpdateMode
 | ) |  |

Set the LPTIM registers update mode (enable/disable register preload)

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR PRELOAD LL_LPTIM_SetUpdateMode
Parameters:
LPTIMx Low-Power Timer instance
UpdateMode This parameter can be one of the following values:
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
Return values:
None

Definition at line 414 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetWaveform | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Waveform
 | ) |  |

Set waveform shape.

Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_SetWaveform
Parameters:
LPTIMx Low-Power Timer instance
Waveform This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Return values:
None

Definition at line 562 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_StartCounter | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | OperatingMode
 | ) |  |

Starts the LPTIM counter in the desired mode.

Note:
LPTIM instance must be enabled before starting the counter.
It is possible to change on the fly from One Shot mode to Continuous mode.
Reference Manual to LL API cross reference:
CR CNTSTRT LL_LPTIM_StartCounter
CR SNGSTRT LL_LPTIM_StartCounter
Parameters:
LPTIMx Low-Power Timer instance
OperatingMode This parameter can be one of the following values:
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS
  • LL_LPTIM_OPERATING_MODE_ONESHOT
Return values:
None

Definition at line 399 of file stm32l4xx_ll_lptim.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Trigger Configuration

Functions
Trigger Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_EnableTimeout (LPTIM_TypeDef *LPTIMx)
Enable the timeout function.
__STATIC_INLINE void | LL_LPTIM_DisableTimeout (LPTIM_TypeDef *LPTIMx)
Disable the timeout function.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledTimeout (LPTIM_TypeDef *LPTIMx)
Indicate whether the timeout function is enabled.
__STATIC_INLINE void | LL_LPTIM_TrigSw (LPTIM_TypeDef *LPTIMx)
Start the LPTIM counter.
__STATIC_INLINE void | LL_LPTIM_ConfigTrigger (LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
Configure the external trigger used as a trigger event for the LPTIM.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerSource (LPTIM_TypeDef *LPTIMx)
Get actual external trigger source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerFilter (LPTIM_TypeDef *LPTIMx)
Get actual external trigger filter.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerPolarity (LPTIM_TypeDef *LPTIMx)
Get actual external trigger polarity.

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigTrigger | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Source,
 |  | uint32_t | Filter,
 |  | uint32_t | Polarity
 | ) |  |

Configure the external trigger used as a trigger event for the LPTIM.

Note:
This function must be called when the LPTIM instance is disabled.
An internal clock source must be present when a digital filter is required for the trigger.
Reference Manual to LL API cross reference:
CFGR TRIGSEL LL_LPTIM_ConfigTrigger
CFGR TRGFLT LL_LPTIM_ConfigTrigger
CFGR TRIGEN LL_LPTIM_ConfigTrigger
Parameters:
LPTIMx Low-Power Timer instance
Source This parameter can be one of the following values:
  • LL_LPTIM_TRIG_SOURCE_GPIO
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3
  • LL_LPTIM_TRIG_SOURCE_COMP1
  • LL_LPTIM_TRIG_SOURCE_COMP2
Filter This parameter can be one of the following values:
  • LL_LPTIM_TRIG_FILTER_NONE
  • LL_LPTIM_TRIG_FILTER_2
  • LL_LPTIM_TRIG_FILTER_4
  • LL_LPTIM_TRIG_FILTER_8
Polarity This parameter can be one of the following values:
  • LL_LPTIM_TRIG_POLARITY_RISING
  • LL_LPTIM_TRIG_POLARITY_FALLING
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING
Return values:
None

Definition at line 773 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableTimeout ( LPTIM_TypeDef * LPTIMx )

Disable the timeout function.

Note:
This function must be called when the LPTIM instance is disabled.
A trigger event arriving when the timer is already started will be ignored.
Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_DisableTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 716 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableTimeout ( LPTIM_TypeDef * LPTIMx )

Enable the timeout function.

Note:
This function must be called when the LPTIM instance is disabled.
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart.
The timeout value corresponds to the compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by the compare match event.
Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_EnableTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 702 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter ( LPTIM_TypeDef * LPTIMx )

Get actual external trigger filter.

Reference Manual to LL API cross reference:
CFGR TRGFLT LL_LPTIM_GetTriggerFilter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_FILTER_NONE
  • LL_LPTIM_TRIG_FILTER_2
  • LL_LPTIM_TRIG_FILTER_4
  • LL_LPTIM_TRIG_FILTER_8

Definition at line 807 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity ( LPTIM_TypeDef * LPTIMx )

Get actual external trigger polarity.

Reference Manual to LL API cross reference:
CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_POLARITY_RISING
  • LL_LPTIM_TRIG_POLARITY_FALLING
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING

Definition at line 821 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource ( LPTIM_TypeDef * LPTIMx )

Get actual external trigger source.

Reference Manual to LL API cross reference:
CFGR TRIGSEL LL_LPTIM_GetTriggerSource
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_SOURCE_GPIO
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3
  • LL_LPTIM_TRIG_SOURCE_COMP1
  • LL_LPTIM_TRIG_SOURCE_COMP2

Definition at line 792 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout ( LPTIM_TypeDef * LPTIMx )

Indicate whether the timeout function is enabled.

Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 727 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_TrigSw ( LPTIM_TypeDef * LPTIMx )

Start the LPTIM counter.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR TRIGEN LL_LPTIM_TrigSw
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 739 of file stm32l4xx_ll_lptim.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Clock Configuration

Functions
Clock Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_SetClockSource (LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
Set the source of the clock used by the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockSource (LPTIM_TypeDef *LPTIMx)
Get actual LPTIM instance clock source.
__STATIC_INLINE void | LL_LPTIM_ConfigClock (LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockPolarity (LPTIM_TypeDef *LPTIMx)
Get actual clock polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockFilter (LPTIM_TypeDef *LPTIMx)
Get actual clock digital filter.

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigClock | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | ClockFilter,
 |  | uint32_t | ClockPolarity
 | ) |  |

Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.

Note:
This function must be called when the LPTIM instance is disabled.
When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.
An internal clock source must be present when a digital filter is required for external clock.
Reference Manual to LL API cross reference:
CFGR CKFLT LL_LPTIM_ConfigClock
CFGR CKPOL LL_LPTIM_ConfigClock
Parameters:
LPTIMx Low-Power Timer instance
ClockFilter This parameter can be one of the following values:
  • LL_LPTIM_CLK_FILTER_NONE
  • LL_LPTIM_CLK_FILTER_2
  • LL_LPTIM_CLK_FILTER_4
  • LL_LPTIM_CLK_FILTER_8
ClockPolarity This parameter can be one of the following values:
  • LL_LPTIM_CLK_POLARITY_RISING
  • LL_LPTIM_CLK_POLARITY_FALLING
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING
Return values:
None

Definition at line 884 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter ( LPTIM_TypeDef * LPTIMx )

Get actual clock digital filter.

Reference Manual to LL API cross reference:
CFGR CKFLT LL_LPTIM_GetClockFilter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_FILTER_NONE
  • LL_LPTIM_CLK_FILTER_2
  • LL_LPTIM_CLK_FILTER_4
  • LL_LPTIM_CLK_FILTER_8

Definition at line 913 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity ( LPTIM_TypeDef * LPTIMx )

Get actual clock polarity.

Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_GetClockPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_POLARITY_RISING
  • LL_LPTIM_CLK_POLARITY_FALLING
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING

Definition at line 898 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource ( LPTIM_TypeDef * LPTIMx )

Get actual LPTIM instance clock source.

Reference Manual to LL API cross reference:
CFGR CKSEL LL_LPTIM_GetClockSource
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_SOURCE_INTERNAL
  • LL_LPTIM_CLK_SOURCE_EXTERNAL

Definition at line 857 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetClockSource | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the source of the clock used by the LPTIM instance.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR CKSEL LL_LPTIM_SetClockSource
Parameters:
LPTIMx Low-Power Timer instance
ClockSource This parameter can be one of the following values:
  • LL_LPTIM_CLK_SOURCE_INTERNAL
  • LL_LPTIM_CLK_SOURCE_EXTERNAL
Return values:
None

Definition at line 844 of file stm32l4xx_ll_lptim.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Encoder Mode

Functions
Encoder Mode
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_SetEncoderMode (LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
Configure the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_GetEncoderMode (LPTIM_TypeDef *LPTIMx)
Get actual encoder mode.
__STATIC_INLINE void | LL_LPTIM_EnableEncoderMode (LPTIM_TypeDef *LPTIMx)
Enable the encoder mode.
__STATIC_INLINE void | LL_LPTIM_DisableEncoderMode (LPTIM_TypeDef *LPTIMx)
Disable the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledEncoderMode (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM operates in encoder mode.

Function Documentation

__STATIC_INLINE void LL_LPTIM_DisableEncoderMode ( LPTIM_TypeDef * LPTIMx )

Disable the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_DisableEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 979 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableEncoderMode ( LPTIM_TypeDef * LPTIMx )

Enable the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
In this mode the LPTIM instance must be clocked by an internal clock source. Also, the prescaler division ratio must be equal to 1.
LPTIM instance must be configured in continuous mode prior enabling the encoder mode.
Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_EnableEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 967 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode ( LPTIM_TypeDef * LPTIMx )

Get actual encoder mode.

Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_GetEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_ENCODER_MODE_RISING
  • LL_LPTIM_ENCODER_MODE_FALLING
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING

Definition at line 951 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode ( LPTIM_TypeDef * LPTIMx )

Indicates whether the LPTIM operates in encoder mode.

Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_IsEnabledEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 990 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetEncoderMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Configure the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_SetEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_LPTIM_ENCODER_MODE_RISING
  • LL_LPTIM_ENCODER_MODE_FALLING
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING
Return values:
None

Definition at line 937 of file stm32l4xx_ll_lptim.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG Management

Functions
FLAG Management
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_ClearFLAG_CMPM (LPTIM_TypeDef *LPTIMx)
Clear the compare match flag (CMPMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPM (LPTIM_TypeDef *LPTIMx)
Inform application whether a compare match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_ARRM (LPTIM_TypeDef *LPTIMx)
Clear the autoreload match flag (ARRMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARRM (LPTIM_TypeDef *LPTIMx)
Inform application whether a autoreload match interrupt has occured.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Clear the external trigger valid edge flag(EXTTRIGCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Inform application whether a valid edge on the selected external trigger input has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_UP (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to up interrupt flag (UPCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_UP (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_ClearFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to down interrupt flag (DOWNCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

Function Documentation

__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM ( LPTIM_TypeDef * LPTIMx )

Clear the autoreload match flag (ARRMCF)

Reference Manual to LL API cross reference:
ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1031 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK ( LPTIM_TypeDef * LPTIMx )

Clear the autoreload register update interrupt flag (ARROKCF).

Reference Manual to LL API cross reference:
ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1097 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM ( LPTIM_TypeDef * LPTIMx )

Clear the compare match flag (CMPMCF)

Reference Manual to LL API cross reference:
ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1009 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK ( LPTIM_TypeDef * LPTIMx )

Clear the compare register update interrupt flag (CMPOKCF).

Reference Manual to LL API cross reference:
ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1075 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN ( LPTIM_TypeDef * LPTIMx )

Clear the counter direction change to down interrupt flag (DOWNCF).

Reference Manual to LL API cross reference:
ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1141 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Clear the external trigger valid edge flag(EXTTRIGCF).

Reference Manual to LL API cross reference:
ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1053 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_UP ( LPTIM_TypeDef * LPTIMx )

Clear the counter direction change to up interrupt flag (UPCF).

Reference Manual to LL API cross reference:
ICR UPCF LL_LPTIM_ClearFlag_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1119 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM ( LPTIM_TypeDef * LPTIMx )

Inform application whether a autoreload match interrupt has occured.

Reference Manual to LL API cross reference:
ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1042 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK ( LPTIM_TypeDef * LPTIMx )

Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.

Reference Manual to LL API cross reference:
ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1108 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM ( LPTIM_TypeDef * LPTIMx )

Inform application whether a compare match interrupt has occurred.

Reference Manual to LL API cross reference:
ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1020 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK ( LPTIM_TypeDef * LPTIMx )

Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.

Reference Manual to LL API cross reference:
ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1086 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN ( LPTIM_TypeDef * LPTIMx )

Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

Reference Manual to LL API cross reference:
ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1152 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Inform application whether a valid edge on the selected external trigger input has occurred.

Reference Manual to LL API cross reference:
ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1064 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP ( LPTIM_TypeDef * LPTIMx )

Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).

Reference Manual to LL API cross reference:
ISR UP LL_LPTIM_IsActiveFlag_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1130 of file stm32l4xx_ll_lptim.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Enable compare match interrupt (CMPMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Disable compare match interrupt (CMPMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPM (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare match interrupt (CMPMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Enable autoreload match interrupt (ARRMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Disable autoreload match interrupt (ARRMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARRM (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Enable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Disable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Enable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Disable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Enable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Disable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARROK (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_UP (LPTIM_TypeDef *LPTIMx)
Enable direction change to up interrupt (UPIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_UP (LPTIM_TypeDef *LPTIMx)
Disable direction change to up interrupt (UPIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_UP (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to up interrupt (UPIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Enable direction change to down interrupt (DOWNIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Disable direction change to down interrupt (DOWNIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_DOWN (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Disable autoreload match interrupt (ARRMIE).

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_DisableIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1215 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Disable autoreload register write completed interrupt (ARROKIE).

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_DisableIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1314 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Disable compare match interrupt (CMPMIE).

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_DisableIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1182 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Disable compare register write completed interrupt (CMPOKIE).

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1281 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Disable direction change to down interrupt (DOWNIE).

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_DisableIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1380 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Disable external trigger valid edge interrupt (EXTTRIGIE).

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1248 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_UP ( LPTIM_TypeDef * LPTIMx )

Disable direction change to up interrupt (UPIE).

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_DisableIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1347 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Enable autoreload match interrupt (ARRMIE).

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_EnableIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1204 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Enable autoreload register write completed interrupt (ARROKIE).

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_EnableIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1303 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Enable compare match interrupt (CMPMIE).

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_EnableIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1171 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Enable compare register write completed interrupt (CMPOKIE).

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1270 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Enable direction change to down interrupt (DOWNIE).

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_EnableIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1369 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Enable external trigger valid edge interrupt (EXTTRIGIE).

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1237 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_UP ( LPTIM_TypeDef * LPTIMx )

Enable direction change to up interrupt (UPIE).

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_EnableIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1336 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Indicates whether the autoreload match interrupt (ARRMIE) is enabled.

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1226 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1325 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Indicates whether the compare match interrupt (CMPMIE) is enabled.

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1193 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1292 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1391 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1259 of file stm32l4xx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP ( LPTIM_TypeDef * LPTIMx )

Indicates whether the direction change to up interrupt (UPIE) is enabled.

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_IsEnabledIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1358 of file stm32l4xx_ll_lptim.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
LPTIM Exported Functions

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.

Function Documentation

ErrorStatus LL_LPTIM_DeInit ( LPTIM_TypeDef * LPTIMx )

Set LPTIMx registers to their reset values.

Parameters:
LPTIMx LP Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPTIMx registers are de-initialized
  • ERROR: invalid LPTIMx instance

Definition at line 105 of file stm32l4xx_ll_lptim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_LPTIM1, LL_APB1_GRP1_ReleaseReset(), LL_APB1_GRP2_ForceReset(), LL_APB1_GRP2_PERIPH_LPTIM2, and LL_APB1_GRP2_ReleaseReset().

ErrorStatus LL_LPTIM_Init | ( | LPTIM_TypeDef * | LPTIMx,
 |  | LL_LPTIM_InitTypeDef * | LPTIM_InitStruct
 | ) |  |

Configure the LPTIMx peripheral according to the specified parameters.

Note:
LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
LPTIMx can be disabled using unitary function LL_LPTIM_Disable().
Parameters:
LPTIMx | LP Timer Instance
LPTIM_InitStruct | pointer to a LL_LPTIM_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPTIMx instance has been initialized
  • ERROR: LPTIMx instance hasn't been initialized

Definition at line 157 of file stm32l4xx_ll_lptim.c.

References assert_param, LL_LPTIM_InitTypeDef::ClockSource, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_WAVEFORM, LL_LPTIM_IsEnabled(), LL_LPTIM_InitTypeDef::Polarity, LL_LPTIM_InitTypeDef::Prescaler, and LL_LPTIM_InitTypeDef::Waveform.

void LL_LPTIM_StructInit ( LL_LPTIM_InitTypeDef * LPTIM_InitStruct )

Set each fields of the LPTIM_InitStruct structure to its default value.

Parameters:
LPTIM_InitStruct pointer to a LL_LPTIM_InitTypeDef structure
Return values:
None

Definition at line 138 of file stm32l4xx_ll_lptim.c.

References LL_LPTIM_InitTypeDef::ClockSource, LL_LPTIM_CLK_SOURCE_INTERNAL, LL_LPTIM_OUTPUT_POLARITY_REGULAR, LL_LPTIM_OUTPUT_WAVEFORM_PWM, LL_LPTIM_PRESCALER_DIV1, LL_LPTIM_InitTypeDef::Polarity, LL_LPTIM_InitTypeDef::Prescaler, and LL_LPTIM_InitTypeDef::Waveform.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPUART

Modules
LPUART
STM32L4xx_LL_Driver

Modules

LPUART Private Constants
LPUART Private Macros
LPUART Exported Init structures
LPUART Exported Constants
LPUART Exported Macros
LPUART Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for LPUART registers.

Register | Bit | Function
BRR | BRR | LL_LPUART_GetBaudRate
 |  | LL_LPUART_SetBaudRate
CR1 | CMIE | LL_LPUART_DisableIT_CM
 |  | LL_LPUART_EnableIT_CM
 |  | LL_LPUART_IsEnabledIT_CM
 | DEAT | LL_LPUART_GetDEAssertionTime
 |  | LL_LPUART_SetDEAssertionTime
 | DEDT | LL_LPUART_GetDEDeassertionTime
 |  | LL_LPUART_SetDEDeassertionTime
 | IDLEIE | LL_LPUART_DisableIT_IDLE
 |  | LL_LPUART_EnableIT_IDLE
 |  | LL_LPUART_IsEnabledIT_IDLE
 | M | LL_LPUART_ConfigCharacter
 |  | LL_LPUART_GetDataWidth
 |  | LL_LPUART_SetDataWidth
 | MME | LL_LPUART_DisableMuteMode
 |  | LL_LPUART_EnableMuteMode
 |  | LL_LPUART_IsEnabledMuteMode
 | PCE | LL_LPUART_ConfigCharacter
 |  | LL_LPUART_GetParity
 |  | LL_LPUART_SetParity
 | PEIE | LL_LPUART_DisableIT_PE
 |  | LL_LPUART_EnableIT_PE
 |  | LL_LPUART_IsEnabledIT_PE
 | PS | LL_LPUART_ConfigCharacter
 |  | LL_LPUART_GetParity
 |  | LL_LPUART_SetParity
 | RE | LL_LPUART_DisableDirectionRx
 |  | LL_LPUART_EnableDirectionRx
 |  | LL_LPUART_GetTransferDirection
 |  | LL_LPUART_SetTransferDirection
 | RXNEIE | LL_LPUART_DisableIT_RXNE
 |  | LL_LPUART_EnableIT_RXNE
 |  | LL_LPUART_IsEnabledIT_RXNE
 | TCIE | LL_LPUART_DisableIT_TC
 |  | LL_LPUART_EnableIT_TC
 |  | LL_LPUART_IsEnabledIT_TC
 | TE | LL_LPUART_DisableDirectionTx
 |  | LL_LPUART_EnableDirectionTx
 |  | LL_LPUART_GetTransferDirection
 |  | LL_LPUART_SetTransferDirection
 | TXEIE | LL_LPUART_DisableIT_TXE
 |  | LL_LPUART_EnableIT_TXE
 |  | LL_LPUART_IsEnabledIT_TXE
 | UE | LL_LPUART_Disable
 |  | LL_LPUART_Enable
 |  | LL_LPUART_IsEnabled
 | UESM | LL_LPUART_DisableInStopMode
 |  | LL_LPUART_EnableInStopMode
 |  | LL_LPUART_IsEnabledInStopMode
 | WAKE | LL_LPUART_GetWakeUpMethod
 |  | LL_LPUART_SetWakeUpMethod
CR2 | ADD | LL_LPUART_ConfigNodeAddress
 |  | LL_LPUART_GetNodeAddress
 | ADDM7 | LL_LPUART_ConfigNodeAddress
 |  | LL_LPUART_GetNodeAddressLen
 | DATAINV | LL_LPUART_GetBinaryDataLogic
 |  | LL_LPUART_SetBinaryDataLogic
 | MSBFIRST | LL_LPUART_GetTransferBitOrder
 |  | LL_LPUART_SetTransferBitOrder
 | RXINV | LL_LPUART_GetRXPinLevel
 |  | LL_LPUART_SetRXPinLevel
 | STOP | LL_LPUART_ConfigCharacter
 |  | LL_LPUART_GetStopBitsLength
 |  | LL_LPUART_SetStopBitsLength
 | SWAP | LL_LPUART_GetTXRXSwap
 |  | LL_LPUART_SetTXRXSwap
 | TXINV | LL_LPUART_GetTXPinLevel
 |  | LL_LPUART_SetTXPinLevel
CR3 | CTSE | LL_LPUART_DisableCTSHWFlowCtrl
 |  | LL_LPUART_EnableCTSHWFlowCtrl
 |  | LL_LPUART_GetHWFlowCtrl
 |  | LL_LPUART_SetHWFlowCtrl
 | CTSIE | LL_LPUART_DisableIT_CTS
 |  | LL_LPUART_EnableIT_CTS
 |  | LL_LPUART_IsEnabledIT_CTS
 | DDRE | LL_LPUART_DisableDMADeactOnRxErr
 |  | LL_LPUART_EnableDMADeactOnRxErr
 |  | LL_LPUART_IsEnabledDMADeactOnRxErr
 | DEM | LL_LPUART_DisableDEMode
 |  | LL_LPUART_EnableDEMode
 |  | LL_LPUART_IsEnabledDEMode
 | DEP | LL_LPUART_GetDESignalPolarity
 |  | LL_LPUART_SetDESignalPolarity
 | DMAR | LL_LPUART_DisableDMAReq_RX
 |  | LL_LPUART_EnableDMAReq_RX
 |  | LL_LPUART_IsEnabledDMAReq_RX
 | DMAT | LL_LPUART_DisableDMAReq_TX
 |  | LL_LPUART_EnableDMAReq_TX
 |  | LL_LPUART_IsEnabledDMAReq_TX
 | EIE | LL_LPUART_DisableIT_ERROR
 |  | LL_LPUART_EnableIT_ERROR
 |  | LL_LPUART_IsEnabledIT_ERROR
 | HDSEL | LL_LPUART_DisableHalfDuplex
 |  | LL_LPUART_EnableHalfDuplex
 |  | LL_LPUART_IsEnabledHalfDuplex
 | OVRDIS | LL_LPUART_DisableOverrunDetect
 |  | LL_LPUART_EnableOverrunDetect
 |  | LL_LPUART_IsEnabledOverrunDetect
 | RTSE | LL_LPUART_DisableRTSHWFlowCtrl
 |  | LL_LPUART_EnableRTSHWFlowCtrl
 |  | LL_LPUART_GetHWFlowCtrl
 |  | LL_LPUART_SetHWFlowCtrl
 | WUFIE | LL_LPUART_DisableIT_WKUP
 |  | LL_LPUART_EnableIT_WKUP
 |  | LL_LPUART_IsEnabledIT_WKUP
 | WUS | LL_LPUART_GetWKUPType
 |  | LL_LPUART_SetWKUPType
ICR | CMCF | LL_LPUART_ClearFlag_CM
 | CTSCF | LL_LPUART_ClearFlag_nCTS
 | FECF | LL_LPUART_ClearFlag_FE
 | IDLECF | LL_LPUART_ClearFlag_IDLE
 | NCF | LL_LPUART_ClearFlag_NE
 | ORECF | LL_LPUART_ClearFlag_ORE
 | PECF | LL_LPUART_ClearFlag_PE
 | TCCF | LL_LPUART_ClearFlag_TC
 | WUCF | LL_LPUART_ClearFlag_WKUP
ISR | BUSY | LL_LPUART_IsActiveFlag_BUSY
 | CMF | LL_LPUART_IsActiveFlag_CM
 | CTS | LL_LPUART_IsActiveFlag_CTS
 | CTSIF | LL_LPUART_IsActiveFlag_nCTS
 | FE | LL_LPUART_IsActiveFlag_FE
 | IDLE | LL_LPUART_IsActiveFlag_IDLE
 | NE | LL_LPUART_IsActiveFlag_NE
 | ORE | LL_LPUART_IsActiveFlag_ORE
 | PE | LL_LPUART_IsActiveFlag_PE
 | REACK | LL_LPUART_IsActiveFlag_REACK
 | RWU | LL_LPUART_IsActiveFlag_RWU
 | RXNE | LL_LPUART_IsActiveFlag_RXNE
 | SBKF | LL_LPUART_IsActiveFlag_SBK
 | TC | LL_LPUART_IsActiveFlag_TC
 | TEACK | LL_LPUART_IsActiveFlag_TEACK
 | TXE | LL_LPUART_IsActiveFlag_TXE
 | WUF | LL_LPUART_IsActiveFlag_WKUP
RDR | RDR | LL_LPUART_DMA_GetRegAddr
 |  | LL_LPUART_ReceiveData8
 |  | LL_LPUART_ReceiveData9
RQR | MMRQ | LL_LPUART_RequestEnterMuteMode
 | RXFRQ | LL_LPUART_RequestRxDataFlush
 | SBKRQ | LL_LPUART_RequestBreakSending
TDR | TDR | LL_LPUART_DMA_GetRegAddr
 |  | LL_LPUART_TransmitData8
 |  | LL_LPUART_TransmitData9
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPUART Private Constants

Defines
LPUART Private Constants
LPUART

Defines

#define | LPUART_POSITION_CR1_DEDT (uint32_t)POSITION_VAL(USART_CR1_DEDT)
#define | LPUART_POSITION_CR1_DEAT (uint32_t)POSITION_VAL(USART_CR1_DEAT)
#define | LPUART_POSITION_CR2_ADD (uint32_t)POSITION_VAL(USART_CR2_ADD)
#define | LPUART_LPUARTDIV_FREQ_MUL (uint32_t)(256U)
#define | LPUART_BRR_MASK (uint32_t)(0x000FFFFFU)
#define | LPUART_BRR_MIN_VALUE (uint32_t)(0x00000300U)

Define Documentation

#define LPUART_BRR_MASK (uint32_t)(0x000FFFFFU)

Definition at line 74 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_BRR_MIN_VALUE (uint32_t)(0x00000300U)

Definition at line 75 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_LPUARTDIV_FREQ_MUL (uint32_t)(256U)

Definition at line 73 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_POSITION_CR1_DEAT (uint32_t)POSITION_VAL(USART_CR1_DEAT)

Definition at line 69 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_GetDEAssertionTime(), and LL_LPUART_SetDEAssertionTime().

#define LPUART_POSITION_CR1_DEDT (uint32_t)POSITION_VAL(USART_CR1_DEDT)

Definition at line 68 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_GetDEDeassertionTime(), and LL_LPUART_SetDEDeassertionTime().

#define LPUART_POSITION_CR2_ADD (uint32_t)POSITION_VAL(USART_CR2_ADD)

Definition at line 70 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_ConfigNodeAddress(), and LL_LPUART_GetNodeAddress().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPUART Private Macros

Defines
LPUART Private Macros
LPUART

Defines

#define | IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 26000000U) && ((__BAUDRATE__) >= 8U))
#define | IS_LL_LPUART_DIRECTION(__VALUE__)
#define | IS_LL_LPUART_PARITY(__VALUE__)
#define | IS_LL_LPUART_DATAWIDTH(__VALUE__)
#define | IS_LL_LPUART_STOPBITS(__VALUE__)
#define | IS_LL_LPUART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_LPUART_BAUDRATE ( __BAUDRATE__ ) (((__BAUDRATE__) <= 26000000U) && ((__BAUDRATE__) >= 8U))

Definition at line 84 of file stm32l4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
                                        || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
                                        || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))

Definition at line 95 of file stm32l4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
                                        || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
                                        || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
                                        || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))

Definition at line 86 of file stm32l4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))

Definition at line 102 of file stm32l4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_PARITY_NONE) \
                                     || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
                                     || ((__VALUE__) == LL_LPUART_PARITY_ODD))

Definition at line 91 of file stm32l4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_STOPBITS_1) \
                                       || ((__VALUE__) == LL_LPUART_STOPBITS_2))

Definition at line 99 of file stm32l4xx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_LPUART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_LPUART_InitTypeDef Struct Reference
LPUART Exported Init structures

LL LPUART Init Structure definition. More...

#include <stm32l4xx_ll_lpuart.h>

Data Fields

uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl

Detailed Description

LL LPUART Init Structure definition.

Definition at line 100 of file stm32l4xx_ll_lpuart.h.

Field Documentation

uint32_t LL_LPUART_InitTypeDef::BaudRate

This field defines expected LPUART communication baud rate.

This feature can be modified afterwards using unitary function LL_LPUART_SetBaudRate().

Definition at line 102 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_LPUART_SetDataWidth().

Definition at line 106 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_LPUART_SetHWFlowCtrl().

Definition at line 126 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_LPUART_SetParity().

Definition at line 116 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_LPUART_SetStopBitsLength().

Definition at line 111 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Direction.

This feature can be modified afterwards using unitary function LL_LPUART_SetTransferDirection().

Definition at line 121 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_lpuart.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
LPUART Exported Constants

Flags defines which can be used with LL_LPUART_WriteReg function. More...

Defines

#define | LL_LPUART_ICR_PECF USART_ICR_PECF
#define | LL_LPUART_ICR_FECF USART_ICR_FECF
#define | LL_LPUART_ICR_NCF USART_ICR_NCF
#define | LL_LPUART_ICR_ORECF USART_ICR_ORECF
#define | LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_LPUART_ICR_TCCF USART_ICR_TCCF
#define | LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_LPUART_ICR_CMCF USART_ICR_CMCF
#define | LL_LPUART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_LPUART_WriteReg function.

Define Documentation

#define LL_LPUART_ICR_CMCF USART_ICR_CMCF

Character match flag

Definition at line 154 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF

CTS flag

Definition at line 153 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ICR_FECF USART_ICR_FECF

Framing error flag

Definition at line 148 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected flag

Definition at line 151 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ICR_NCF USART_ICR_NCF

Noise detected flag

Definition at line 149 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ICR_ORECF USART_ICR_ORECF

Overrun error flag

Definition at line 150 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ICR_PECF USART_ICR_PECF

Parity error flag

Definition at line 147 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ICR_TCCF USART_ICR_TCCF

Transmission complete flag

Definition at line 152 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode flag

Definition at line 155 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
LPUART Exported Constants

Flags defines which can be used with LL_LPUART_ReadReg function. More...

Defines

#define | LL_LPUART_ISR_PE USART_ISR_PE
#define | LL_LPUART_ISR_FE USART_ISR_FE
#define | LL_LPUART_ISR_NE USART_ISR_NE
#define | LL_LPUART_ISR_ORE USART_ISR_ORE
#define | LL_LPUART_ISR_IDLE USART_ISR_IDLE
#define | LL_LPUART_ISR_RXNE USART_ISR_RXNE
#define | LL_LPUART_ISR_TC USART_ISR_TC
#define | LL_LPUART_ISR_TXE USART_ISR_TXE
#define | LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_LPUART_ISR_CTS USART_ISR_CTS
#define | LL_LPUART_ISR_BUSY USART_ISR_BUSY
#define | LL_LPUART_ISR_CMF USART_ISR_CMF
#define | LL_LPUART_ISR_SBKF USART_ISR_SBKF
#define | LL_LPUART_ISR_RWU USART_ISR_RWU
#define | LL_LPUART_ISR_WUF USART_ISR_WUF
#define | LL_LPUART_ISR_TEACK USART_ISR_TEACK
#define | LL_LPUART_ISR_REACK USART_ISR_REACK

Detailed Description

Flags defines which can be used with LL_LPUART_ReadReg function.

Define Documentation

#define LL_LPUART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 174 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 175 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 173 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 172 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 165 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 168 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 166 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 167 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 164 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 180 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 177 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_RXNE USART_ISR_RXNE

Read data register not empty flag

Definition at line 169 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 176 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 170 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 179 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_TXE USART_ISR_TXE

Transmit data register empty flag

Definition at line 171 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 178 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
LPUART Exported Constants

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions. More...

Defines

#define | LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE
#define | LL_LPUART_CR1_TCIE USART_CR1_TCIE
#define | LL_LPUART_CR1_TXEIE USART_CR1_TXEIE
#define | LL_LPUART_CR1_PEIE USART_CR1_PEIE
#define | LL_LPUART_CR1_CMIE USART_CR1_CMIE
#define | LL_LPUART_CR3_EIE USART_CR3_EIE
#define | LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_LPUART_CR3_WUFIE USART_CR3_WUFIE

Detailed Description

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions.

Define Documentation

#define LL_LPUART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 194 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 189 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 193 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE

Read data register not empty interrupt enable

Definition at line 190 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 191 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE

Transmit data register empty interrupt enable

Definition at line 192 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 196 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 195 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 197 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Direction

Defines
Direction
LPUART Exported Constants

Defines

#define | LL_LPUART_DIRECTION_NONE (uint32_t)0x00000000U
#define | LL_LPUART_DIRECTION_RX USART_CR1_RE
#define | LL_LPUART_DIRECTION_TX USART_CR1_TE
#define | LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_LPUART_DIRECTION_NONE (uint32_t)0x00000000U

Transmitter and Receiver are disabled

Definition at line 205 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 206 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 207 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 208 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

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STM32L486xx HAL User Manual: Parity Control

Defines
Parity Control
LPUART Exported Constants

Defines

#define | LL_LPUART_PARITY_NONE (uint32_t)0x00000000U
#define | LL_LPUART_PARITY_EVEN USART_CR1_PCE
#define | LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_LPUART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 217 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_PARITY_NONE (uint32_t)0x00000000U

Parity control disabled

Definition at line 216 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 218 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: Wakeup

Defines
Wakeup
LPUART Exported Constants

Defines

#define | LL_LPUART_WAKEUP_IDLELINE (uint32_t)0x00000000U
#define | LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

LPUART wake up from Mute mode on Address Mark

Definition at line 227 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_IDLELINE (uint32_t)0x00000000U

LPUART wake up from Mute mode on Idle Line

Definition at line 226 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: Datawidth

Defines
Datawidth
LPUART Exported Constants

Defines

#define | LL_LPUART_DATAWIDTH_7B USART_CR1_M1
#define | LL_LPUART_DATAWIDTH_8B (uint32_t)0x00000000U
#define | LL_LPUART_DATAWIDTH_9B USART_CR1_M0

Define Documentation

#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

Definition at line 235 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_DATAWIDTH_8B (uint32_t)0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 236 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 237 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: Stop Bits

Defines
Stop Bits
LPUART Exported Constants

Defines

#define | LL_LPUART_STOPBITS_1 (uint32_t)0x00000000U
#define | LL_LPUART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_LPUART_STOPBITS_1 (uint32_t)0x00000000U

1 stop bit

Definition at line 245 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 246 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
LPUART Exported Constants

Defines

#define | LL_LPUART_TXRX_STANDARD (uint32_t)0x00000000U
#define | LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_LPUART_TXRX_STANDARD (uint32_t)0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 254 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 255 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U
#define | LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 264 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U

RX pin signal works using the standard logic levels

Definition at line 263 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U
#define | LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 273 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U

TX pin signal works using the standard logic levels

Definition at line 272 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U
#define | LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 282 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 281 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: Bit Order

Defines
Bit Order
LPUART Exported Constants

Defines

#define | LL_LPUART_BITORDER_LSBFIRST (uint32_t)0x00000000U
#define | LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_LPUART_BITORDER_LSBFIRST (uint32_t)0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 290 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 291 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Address Length Detection

Defines
Address Length Detection
LPUART Exported Constants

Defines

#define | LL_LPUART_ADDRESS_DETECT_4B (uint32_t)0x00000000U
#define | LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_LPUART_ADDRESS_DETECT_4B (uint32_t)0x00000000U

4-bit address detection method selected

Definition at line 299 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 300 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: Hardware Control

Defines
Hardware Control
LPUART Exported Constants

Defines

#define | LL_LPUART_HWCONTROL_NONE (uint32_t)0x00000000U
#define | LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 310 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_HWCONTROL_NONE (uint32_t)0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 308 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 309 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 311 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
LPUART Exported Constants

Defines

#define | LL_LPUART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U
#define | LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_LPUART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U

Wake up active on address match

Definition at line 319 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 321 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 320 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
LPUART Exported Constants

Defines

#define | LL_LPUART_DE_POLARITY_HIGH (uint32_t)0x00000000U
#define | LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_LPUART_DE_POLARITY_HIGH (uint32_t)0x00000000U

DE signal is active high

Definition at line 329 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 330 of file stm32l4xx_ll_lpuart.h.

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STM32L486xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
LPUART Exported Constants

Defines

#define | LL_LPUART_DMA_REG_DATA_TRANSMIT (uint32_t)0U
#define | LL_LPUART_DMA_REG_DATA_RECEIVE (uint32_t)1U

Define Documentation

#define LL_LPUART_DMA_REG_DATA_RECEIVE (uint32_t)1U

Get address of data register used for reception

Definition at line 339 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_DMA_REG_DATA_TRANSMIT (uint32_t)0U

Get address of data register used for transmission

Definition at line 338 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_DMA_GetRegAddr().

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STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
LPUART Exported Macros

Defines

#define | LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPUART register.
#define | LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPUART register.

Define Documentation

#define LL_LPUART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in LPUART register.

Parameters:
__INSTANCE__ | LPUART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 372 of file stm32l4xx_ll_lpuart.h.

#define LL_LPUART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in LPUART register.

Parameters:
__INSTANCE__ | LPUART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 364 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Helper Macros

Defines
Helper Macros
LPUART Exported Macros

Defines

#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Define Documentation

#define __LL_LPUART_DIV | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)

Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for LPUART Instance
__BAUDRATE__ | Baud Rate value to achieve
Return values:
LPUARTDIV value to be used for BRR register filling

Definition at line 388 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_SetBaudRate().

Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration functions

Functions
Configuration functions
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_Enable (USART_TypeDef *LPUARTx)
LPUART Enable.
__STATIC_INLINE void | LL_LPUART_Disable (USART_TypeDef *LPUARTx)
LPUART Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabled (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled.
__STATIC_INLINE void | LL_LPUART_EnableInStopMode (USART_TypeDef *LPUARTx)
LPUART enabled in STOP Mode.
__STATIC_INLINE void | LL_LPUART_DisableInStopMode (USART_TypeDef *LPUARTx)
LPUART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledInStopMode (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_LPUART_EnableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_LPUART_DisableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Disable.
__STATIC_INLINE void | LL_LPUART_EnableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_LPUART_DisableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_LPUART_SetTransferDirection (USART_TypeDef *LPUARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferDirection (USART_TypeDef *LPUARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_LPUART_SetParity (USART_TypeDef *LPUARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled)
__STATIC_INLINE uint32_t | LL_LPUART_GetParity (USART_TypeDef *LPUARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_LPUART_SetWakeUpMethod (USART_TypeDef *LPUARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_LPUART_GetWakeUpMethod (USART_TypeDef *LPUARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_LPUART_SetDataWidth (USART_TypeDef *LPUARTx, uint32_t DataWidth)
Set Word length (nb of data bits, excluding start and stop bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetDataWidth (USART_TypeDef *LPUARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_LPUART_EnableMuteMode (USART_TypeDef *LPUARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_LPUART_DisableMuteMode (USART_TypeDef *LPUARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledMuteMode (USART_TypeDef *LPUARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_LPUART_SetStopBitsLength (USART_TypeDef *LPUARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_LPUART_GetStopBitsLength (USART_TypeDef *LPUARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_LPUART_ConfigCharacter (USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_LPUART_SetTXRXSwap (USART_TypeDef *LPUARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXRXSwap (USART_TypeDef *LPUARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_LPUART_SetRXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXPinLevel (USART_TypeDef *LPUARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetTXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXPinLevel (USART_TypeDef *LPUARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetBinaryDataLogic (USART_TypeDef *LPUARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetBinaryDataLogic (USART_TypeDef *LPUARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_LPUART_SetTransferBitOrder (USART_TypeDef *LPUARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferBitOrder (USART_TypeDef *LPUARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_LPUART_ConfigNodeAddress (USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the LPUART node.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddress (USART_TypeDef *LPUARTx)
Return 8 bit Address of the LPUART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddressLen (USART_TypeDef *LPUARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_LPUART_EnableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_EnableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_SetHWFlowCtrl (USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_LPUART_GetHWFlowCtrl (USART_TypeDef *LPUARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_LPUART_EnableOverrunDetect (USART_TypeDef *LPUARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_LPUART_DisableOverrunDetect (USART_TypeDef *LPUARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledOverrunDetect (USART_TypeDef *LPUARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_LPUART_SetWKUPType (USART_TypeDef *LPUARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetWKUPType (USART_TypeDef *LPUARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_LPUART_SetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
Configure LPUART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_LPUART_GetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk)
Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.

Function Documentation

__STATIC_INLINE void LL_LPUART_ConfigCharacter | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_LPUART_SetDataWidth() function
  • Parity Control and mode configuration using LL_LPUART_SetParity() function
  • Stop bits configuration using LL_LPUART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_ConfigCharacter
CR1 PCE LL_LPUART_ConfigCharacter
CR1 M LL_LPUART_ConfigCharacter
CR2 STOP LL_LPUART_ConfigCharacter
Parameters:
LPUARTx LPUART Instance
DataWidth This parameter can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2
Return values:
None

Definition at line 737 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ConfigNodeAddress | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the LPUART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_LPUART_ConfigNodeAddress
CR2 ADDM7 LL_LPUART_ConfigNodeAddress
Parameters:
LPUARTx | LPUART Instance
AddressLen This parameter can be one of the following values:
  • LL_LPUART_ADDRESS_DETECT_4B
  • LL_LPUART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the LPUART node.
Return values:
None

Definition at line 909 of file stm32l4xx_ll_lpuart.h.

References LPUART_POSITION_CR2_ADD.

__STATIC_INLINE void LL_LPUART_Disable ( USART_TypeDef * LPUARTx )

LPUART Disable.

Note:
When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUARTx_ISR are set to their default values.
In order to go into low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit.
Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_Disable
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 432 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Disable CTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 982 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDirectionRx ( USART_TypeDef * LPUARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_DisableDirectionRx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 502 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDirectionTx ( USART_TypeDef * LPUARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_LPUART_DisableDirectionTx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 524 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableInStopMode ( USART_TypeDef * LPUARTx )

LPUART disabled in STOP Mode.

Note:
When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_DisableInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 468 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableMuteMode ( USART_TypeDef * LPUARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_DisableMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 670 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableOverrunDetect ( USART_TypeDef * LPUARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_DisableOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1037 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Disable RTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 960 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_Enable ( USART_TypeDef * LPUARTx )

LPUART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_Enable
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 413 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Enable CTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 971 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDirectionRx ( USART_TypeDef * LPUARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_EnableDirectionRx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 491 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDirectionTx ( USART_TypeDef * LPUARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_LPUART_EnableDirectionTx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 513 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableInStopMode ( USART_TypeDef * LPUARTx )

LPUART enabled in STOP Mode.

Note:
When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that LPUART clock selection is HSI or LSE in RCC.
Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_EnableInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 456 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableMuteMode ( USART_TypeDef * LPUARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_EnableMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 659 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableOverrunDetect ( USART_TypeDef * LPUARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_EnableOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1026 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Enable RTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 949 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PeriphClk
 | ) |  |

Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
Reference Manual to LL API cross reference:
BRR BRR LL_LPUART_GetBaudRate
Parameters:
LPUARTx | LPUART Instance
PeriphClk | Peripheral Clock
Return values:
Baud Rate

Definition at line 1112 of file stm32l4xx_ll_lpuart.h.

References LPUART_BRR_MASK, LPUART_BRR_MIN_VALUE, and LPUART_LPUARTDIV_FREQ_MUL.

__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic ( USART_TypeDef * LPUARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_LPUART_GetBinaryDataLogic
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_BINARY_LOGIC_POSITIVE
  • LL_LPUART_BINARY_LOGIC_NEGATIVE

Definition at line 850 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth ( USART_TypeDef * LPUARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_LPUART_GetDataWidth
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B

Definition at line 648 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl ( USART_TypeDef * LPUARTx )

Return HW Flow Control configuration (both CTS and RTS)

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_GetHWFlowCtrl
CR3 CTSE LL_LPUART_GetHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_HWCONTROL_NONE
  • LL_LPUART_HWCONTROL_RTS
  • LL_LPUART_HWCONTROL_CTS
  • LL_LPUART_HWCONTROL_RTS_CTS

Definition at line 1015 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress ( USART_TypeDef * LPUARTx )

Return 8 bit Address of the LPUART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_LPUART_GetNodeAddress
Parameters:
LPUARTx LPUART Instance
Return values:
Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 925 of file stm32l4xx_ll_lpuart.h.

References LPUART_POSITION_CR2_ADD.

__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen ( USART_TypeDef * LPUARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_LPUART_GetNodeAddressLen
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_ADDRESS_DETECT_4B
  • LL_LPUART_ADDRESS_DETECT_7B

Definition at line 938 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetParity ( USART_TypeDef * LPUARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_GetParity
CR1 PCE LL_LPUART_GetParity
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD

Definition at line 592 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel ( USART_TypeDef * LPUARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_LPUART_GetRXPinLevel
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_RXPIN_LEVEL_STANDARD
  • LL_LPUART_RXPIN_LEVEL_INVERTED

Definition at line 793 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength ( USART_TypeDef * LPUARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_LPUART_GetStopBitsLength
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2

Definition at line 708 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder ( USART_TypeDef * LPUARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_BITORDER_LSBFIRST
  • LL_LPUART_BITORDER_MSBFIRST

Definition at line 881 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection ( USART_TypeDef * LPUARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_GetTransferDirection
CR1 TE LL_LPUART_GetTransferDirection
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DIRECTION_NONE
  • LL_LPUART_DIRECTION_RX
  • LL_LPUART_DIRECTION_TX
  • LL_LPUART_DIRECTION_TX_RX

Definition at line 558 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel ( USART_TypeDef * LPUARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_LPUART_GetTXPinLevel
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_TXPIN_LEVEL_STANDARD
  • LL_LPUART_TXPIN_LEVEL_INVERTED

Definition at line 820 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap ( USART_TypeDef * LPUARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_LPUART_GetTXRXSwap
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_TXRX_STANDARD
  • LL_LPUART_TXRX_SWAPPED

Definition at line 766 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod ( USART_TypeDef * LPUARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_LPUART_GetWakeUpMethod
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_WAKEUP_IDLELINE
  • LL_LPUART_WAKEUP_ADDRESSMARK

Definition at line 619 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType ( USART_TypeDef * LPUARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Reference Manual to LL API cross reference:
CR3 WUS LL_LPUART_GetWKUPType
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_WAKEUP_ON_ADDRESS
  • LL_LPUART_WAKEUP_ON_STARTBIT
  • LL_LPUART_WAKEUP_ON_RXNE

Definition at line 1077 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabled ( USART_TypeDef * LPUARTx )

Indicate if LPUART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_IsEnabled
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 443 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode ( USART_TypeDef * LPUARTx )

Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_IsEnabledInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 480 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode ( USART_TypeDef * LPUARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_IsEnabledMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 681 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect ( USART_TypeDef * LPUARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1048 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetBaudRate | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | BaudRate
 | ) |  |

Configure LPUART BRR register for achieving expected Baud Rate value.

Note:
Compute and set LPUARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock and expected Baud Rate values
Peripheral clock and Baud Rate values provided as function parameters should be valid (Baud rate value != 0).
Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, a care should be taken when generating high baud rates using high PeriphClk values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
Reference Manual to LL API cross reference:
BRR BRR LL_LPUART_SetBaudRate
Parameters:
LPUARTx | LPUART Instance
PeriphClk | Peripheral Clock
BaudRate | Baud Rate
Return values:
None

Definition at line 1098 of file stm32l4xx_ll_lpuart.h.

References __LL_LPUART_DIV.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_LPUART_SetBinaryDataLogic
Parameters:
LPUARTx LPUART Instance
DataLogic This parameter can be one of the following values:
  • LL_LPUART_BINARY_LOGIC_POSITIVE
  • LL_LPUART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 837 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDataWidth | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_LPUART_SetDataWidth
Parameters:
LPUARTx LPUART Instance
DataWidth This parameter can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B
Return values:
None

Definition at line 634 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_SetHWFlowCtrl
CR3 CTSE LL_LPUART_SetHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_LPUART_HWCONTROL_NONE
  • LL_LPUART_HWCONTROL_RTS
  • LL_LPUART_HWCONTROL_CTS
  • LL_LPUART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 999 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetParity | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled)

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_SetParity
CR1 PCE LL_LPUART_SetParity
Parameters:
LPUARTx LPUART Instance
Parity This parameter can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD
Return values:
None

Definition at line 577 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetRXPinLevel | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_LPUART_SetRXPinLevel
Parameters:
LPUARTx LPUART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_LPUART_RXPIN_LEVEL_STANDARD
  • LL_LPUART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 780 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetStopBitsLength | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_LPUART_SetStopBitsLength
Parameters:
LPUARTx LPUART Instance
StopBits This parameter can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2
Return values:
None

Definition at line 695 of file stm32l4xx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetTransferBitOrder | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
Parameters:
LPUARTx LPUART Instance
BitOrder This parameter can be one of the following values:
  • LL_LPUART_BITORDER_LSBFIRST
  • LL_LPUART_BITORDER_MSBFIRST
Return values:
None

Definition at line 866 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTransferDirection | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_SetTransferDirection
CR1 TE LL_LPUART_SetTransferDirection
Parameters:
LPUARTx LPUART Instance
TransferDirection This parameter can be one of the following values:
  • LL_LPUART_DIRECTION_NONE
  • LL_LPUART_DIRECTION_RX
  • LL_LPUART_DIRECTION_TX
  • LL_LPUART_DIRECTION_TX_RX
Return values:
None

Definition at line 542 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXPinLevel | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_LPUART_SetTXPinLevel
Parameters:
LPUARTx LPUART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_LPUART_TXPIN_LEVEL_STANDARD
  • LL_LPUART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 807 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXRXSwap | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_LPUART_SetTXRXSwap
Parameters:
LPUARTx LPUART Instance
SwapConfig This parameter can be one of the following values:
  • LL_LPUART_TXRX_STANDARD
  • LL_LPUART_TXRX_SWAPPED
Return values:
None

Definition at line 753 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetWakeUpMethod | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_LPUART_SetWakeUpMethod
Parameters:
LPUARTx LPUART Instance
Method This parameter can be one of the following values:
  • LL_LPUART_WAKEUP_IDLELINE
  • LL_LPUART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 606 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetWKUPType | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Reference Manual to LL API cross reference:
CR3 WUS LL_LPUART_SetWKUPType
Parameters:
LPUARTx LPUART Instance
Type This parameter can be one of the following values:
  • LL_LPUART_WAKEUP_ON_ADDRESS
  • LL_LPUART_WAKEUP_ON_STARTBIT
  • LL_LPUART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1063 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableHalfDuplex (USART_TypeDef *LPUARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_LPUART_DisableHalfDuplex (USART_TypeDef *LPUARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledHalfDuplex (USART_TypeDef *LPUARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableHalfDuplex ( USART_TypeDef * LPUARTx )

Disable Single Wire Half-Duplex mode.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_DisableHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1152 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableHalfDuplex ( USART_TypeDef * LPUARTx )

Enable Single Wire Half-Duplex mode.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_EnableHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1141 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex ( USART_TypeDef * LPUARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1163 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_SetDEDeassertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEDeassertionTime (USART_TypeDef *LPUARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_LPUART_SetDEAssertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEAssertionTime (USART_TypeDef *LPUARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_LPUART_EnableDEMode (USART_TypeDef *LPUARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_LPUART_DisableDEMode (USART_TypeDef *LPUARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDEMode (USART_TypeDef *LPUARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDESignalPolarity (USART_TypeDef *LPUARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_GetDESignalPolarity (USART_TypeDef *LPUARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableDEMode ( USART_TypeDef * LPUARTx )

Disable Driver Enable (DE) Mode.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_DisableDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1239 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDEMode ( USART_TypeDef * LPUARTx )

Enable Driver Enable (DE) Mode.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_EnableDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1228 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime ( USART_TypeDef * LPUARTx )

Return DEAT (Driver Enable Assertion Time)

Reference Manual to LL API cross reference:
CR1 DEAT LL_LPUART_GetDEAssertionTime
Parameters:
LPUARTx LPUART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31

Definition at line 1217 of file stm32l4xx_ll_lpuart.h.

References LPUART_POSITION_CR1_DEAT.

__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime ( USART_TypeDef * LPUARTx )

Return DEDT (Driver Enable De-Assertion Time)

Reference Manual to LL API cross reference:
CR1 DEDT LL_LPUART_GetDEDeassertionTime
Parameters:
LPUARTx LPUART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : c

Definition at line 1194 of file stm32l4xx_ll_lpuart.h.

References LPUART_POSITION_CR1_DEDT.

__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity ( USART_TypeDef * LPUARTx )

Return Driver Enable Polarity.

Reference Manual to LL API cross reference:
CR3 DEP LL_LPUART_GetDESignalPolarity
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DE_POLARITY_HIGH
  • LL_LPUART_DE_POLARITY_LOW

Definition at line 1277 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode ( USART_TypeDef * LPUARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_IsEnabledDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1250 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDEAssertionTime | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Reference Manual to LL API cross reference:
CR1 DEAT LL_LPUART_SetDEAssertionTime
Parameters:
LPUARTx | LPUART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1206 of file stm32l4xx_ll_lpuart.h.

References LPUART_POSITION_CR1_DEAT.

__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Reference Manual to LL API cross reference:
CR1 DEDT LL_LPUART_SetDEDeassertionTime
Parameters:
LPUARTx | LPUART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1183 of file stm32l4xx_ll_lpuart.h.

References LPUART_POSITION_CR1_DEDT.

__STATIC_INLINE void LL_LPUART_SetDESignalPolarity | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Reference Manual to LL API cross reference:
CR3 DEP LL_LPUART_SetDESignalPolarity
Parameters:
LPUARTx LPUART Instance
Polarity This parameter can be one of the following values:
  • LL_LPUART_DE_POLARITY_HIGH
  • LL_LPUART_DE_POLARITY_LOW
Return values:
None

Definition at line 1264 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
LPUART Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_FE (USART_TypeDef *LPUARTx)
Check if the LPUART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_NE (USART_TypeDef *LPUARTx)
Check if the LPUART Noise detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_ORE (USART_TypeDef *LPUARTx)
Check if the LPUART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXNE (USART_TypeDef *LPUARTx)
Check if the LPUART Read Data Register Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXE (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Data Register Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_nCTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_BUSY (USART_TypeDef *LPUARTx)
Check if the LPUART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_SBK (USART_TypeDef *LPUARTx)
Check if the LPUART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RWU (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TEACK (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_REACK (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE void | LL_LPUART_ClearFlag_PE (USART_TypeDef *LPUARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_FE (USART_TypeDef *LPUARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_NE (USART_TypeDef *LPUARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_ORE (USART_TypeDef *LPUARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_IDLE (USART_TypeDef *LPUARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TC (USART_TypeDef *LPUARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_nCTS (USART_TypeDef *LPUARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_CM (USART_TypeDef *LPUARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_WKUP (USART_TypeDef *LPUARTx)
Clear Wake Up from stop mode Flag.

Function Documentation

__STATIC_INLINE void LL_LPUART_ClearFlag_CM ( USART_TypeDef * LPUARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_LPUART_ClearFlag_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1560 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_FE ( USART_TypeDef * LPUARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_LPUART_ClearFlag_FE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1494 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE ( USART_TypeDef * LPUARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_LPUART_ClearFlag_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1527 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS ( USART_TypeDef * LPUARTx )

Clear CTS Interrupt Flag.

Reference Manual to LL API cross reference:
ICR CTSCF LL_LPUART_ClearFlag_nCTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1549 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_NE ( USART_TypeDef * LPUARTx )

Clear Noise detected Flag.

Reference Manual to LL API cross reference:
ICR NCF LL_LPUART_ClearFlag_NE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1505 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_ORE ( USART_TypeDef * LPUARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_LPUART_ClearFlag_ORE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1516 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_PE ( USART_TypeDef * LPUARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_LPUART_ClearFlag_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1483 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_TC ( USART_TypeDef * LPUARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_LPUART_ClearFlag_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1538 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP ( USART_TypeDef * LPUARTx )

Clear Wake Up from stop mode Flag.

Reference Manual to LL API cross reference:
ICR WUCF LL_LPUART_ClearFlag_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1571 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY ( USART_TypeDef * LPUARTx )

Check if the LPUART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_LPUART_IsActiveFlag_BUSY
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1406 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM ( USART_TypeDef * LPUARTx )

Check if the LPUART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_LPUART_IsActiveFlag_CM
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1417 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS ( USART_TypeDef * LPUARTx )

Check if the LPUART CTS Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTS LL_LPUART_IsActiveFlag_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1395 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE ( USART_TypeDef * LPUARTx )

Check if the LPUART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_LPUART_IsActiveFlag_FE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1307 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE ( USART_TypeDef * LPUARTx )

Check if the LPUART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_LPUART_IsActiveFlag_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1340 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS ( USART_TypeDef * LPUARTx )

Check if the LPUART CTS interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1384 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE ( USART_TypeDef * LPUARTx )

Check if the LPUART Noise detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NE LL_LPUART_IsActiveFlag_NE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1318 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE ( USART_TypeDef * LPUARTx )

Check if the LPUART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_LPUART_IsActiveFlag_ORE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1329 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE ( USART_TypeDef * LPUARTx )

Check if the LPUART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_LPUART_IsActiveFlag_PE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1296 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK ( USART_TypeDef * LPUARTx )

Check if the LPUART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_LPUART_IsActiveFlag_REACK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1472 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU ( USART_TypeDef * LPUARTx )

Check if the LPUART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_LPUART_IsActiveFlag_RWU
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1439 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE ( USART_TypeDef * LPUARTx )

Check if the LPUART Read Data Register Not Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXNE LL_LPUART_IsActiveFlag_RXNE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1351 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK ( USART_TypeDef * LPUARTx )

Check if the LPUART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_LPUART_IsActiveFlag_SBK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1428 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_LPUART_IsActiveFlag_TC
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1362 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_LPUART_IsActiveFlag_TEACK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1461 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmit Data Register Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXE LL_LPUART_IsActiveFlag_TXE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1373 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP ( USART_TypeDef * LPUARTx )

Check if the LPUART Wake Up from stop mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR WUF LL_LPUART_IsActiveFlag_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1450 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT_Management

Functions
IT_Management
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableIT_IDLE (USART_TypeDef *LPUARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXNE (USART_TypeDef *LPUARTx)
Enable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TC (USART_TypeDef *LPUARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXE (USART_TypeDef *LPUARTx)
Enable TX Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_PE (USART_TypeDef *LPUARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CM (USART_TypeDef *LPUARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_ERROR (USART_TypeDef *LPUARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CTS (USART_TypeDef *LPUARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_WKUP (USART_TypeDef *LPUARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_IDLE (USART_TypeDef *LPUARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXNE (USART_TypeDef *LPUARTx)
Disable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TC (USART_TypeDef *LPUARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXE (USART_TypeDef *LPUARTx)
Disable TX Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_PE (USART_TypeDef *LPUARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CM (USART_TypeDef *LPUARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_ERROR (USART_TypeDef *LPUARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CTS (USART_TypeDef *LPUARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_WKUP (USART_TypeDef *LPUARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXNE (USART_TypeDef *LPUARTx)
Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXE (USART_TypeDef *LPUARTx)
Check if the LPUART TX Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_ERROR (USART_TypeDef *LPUARTx)
Check if the LPUART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableIT_CM ( USART_TypeDef * LPUARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_DisableIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1748 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_CTS ( USART_TypeDef * LPUARTx )

Disable CTS Interrupt.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_DisableIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1774 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_ERROR ( USART_TypeDef * LPUARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
  • 0: Interrupt is inhibited
  • 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_DisableIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1763 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_IDLE ( USART_TypeDef * LPUARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_DisableIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1693 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_PE ( USART_TypeDef * LPUARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_DisableIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1737 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXNE ( USART_TypeDef * LPUARTx )

Disable RX Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_LPUART_DisableIT_RXNE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1704 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TC ( USART_TypeDef * LPUARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_DisableIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1715 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXE ( USART_TypeDef * LPUARTx )

Disable TX Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_LPUART_DisableIT_TXE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1726 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_WKUP ( USART_TypeDef * LPUARTx )

Disable Wake Up from Stop Mode Interrupt.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_DisableIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1785 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_CM ( USART_TypeDef * LPUARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_EnableIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1645 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_CTS ( USART_TypeDef * LPUARTx )

Enable CTS Interrupt.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_EnableIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1671 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_ERROR ( USART_TypeDef * LPUARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
  • 0: Interrupt is inhibited
  • 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_EnableIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1660 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_IDLE ( USART_TypeDef * LPUARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_EnableIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1590 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_PE ( USART_TypeDef * LPUARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_EnableIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1634 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXNE ( USART_TypeDef * LPUARTx )

Enable RX Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_LPUART_EnableIT_RXNE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1601 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TC ( USART_TypeDef * LPUARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_EnableIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1612 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXE ( USART_TypeDef * LPUARTx )

Enable TX Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_LPUART_EnableIT_TXE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1623 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_WKUP ( USART_TypeDef * LPUARTx )

Enable Wake Up from Stop Mode Interrupt.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_EnableIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1682 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM ( USART_TypeDef * LPUARTx )

Check if the LPUART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_IsEnabledIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1851 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS ( USART_TypeDef * LPUARTx )

Check if the LPUART CTS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1873 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR ( USART_TypeDef * LPUARTx )

Check if the LPUART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_IsEnabledIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1862 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE ( USART_TypeDef * LPUARTx )

Check if the LPUART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1796 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE ( USART_TypeDef * LPUARTx )

Check if the LPUART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_IsEnabledIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1840 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE ( USART_TypeDef * LPUARTx )

Check if the LPUART RX Not Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1807 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_IsEnabledIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1818 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE ( USART_TypeDef * LPUARTx )

Check if the LPUART TX Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_LPUART_IsEnabledIT_TXE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1829 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP ( USART_TypeDef * LPUARTx )

Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1884 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA_Management

Functions
DMA_Management
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableDMAReq_RX (USART_TypeDef *LPUARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_RX (USART_TypeDef *LPUARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_RX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_TX (USART_TypeDef *LPUARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_TX (USART_TypeDef *LPUARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_TX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_LPUART_EnableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_LPUART_DisableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_LPUART_DMA_GetRegAddr (USART_TypeDef *LPUARTx, uint32_t Direction)
Get the LPUART data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1980 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX ( USART_TypeDef * LPUARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_DisableDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1914 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX ( USART_TypeDef * LPUARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_DisableDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1947 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the LPUART data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_DMA_GetRegAddr
Parameters:
LPUARTx LPUART Instance
Direction This parameter can be one of the following values:
  • LL_LPUART_DMA_REG_DATA_TRANSMIT
  • LL_LPUART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 2006 of file stm32l4xx_ll_lpuart.h.

References LL_LPUART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1969 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX ( USART_TypeDef * LPUARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_EnableDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1903 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX ( USART_TypeDef * LPUARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_EnableDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1936 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1991 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX ( USART_TypeDef * LPUARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1925 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX ( USART_TypeDef * LPUARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1958 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data_Management

Functions
Data_Management
LPUART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_LPUART_ReceiveData8 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_LPUART_ReceiveData9 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData8 (USART_TypeDef *LPUARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData9 (USART_TypeDef *LPUARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8 ( USART_TypeDef * LPUARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_ReceiveData8
Parameters:
LPUARTx LPUART Instance
Return values:
Time Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2038 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9 ( USART_TypeDef * LPUARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_ReceiveData9
Parameters:
LPUARTx LPUART Instance
Return values:
Time Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 2049 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_TransmitData8 | ( | USART_TypeDef * | LPUARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_TransmitData8
Parameters:
LPUARTx | LPUART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2061 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_TransmitData9 | ( | USART_TypeDef * | LPUARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_TransmitData9
Parameters:
LPUARTx | LPUART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 2073 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Execution

Functions
Execution
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_RequestBreakSending (USART_TypeDef *LPUARTx)
Request Break sending.
__STATIC_INLINE void | LL_LPUART_RequestEnterMuteMode (USART_TypeDef *LPUARTx)
Put LPUART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_LPUART_RequestRxDataFlush (USART_TypeDef *LPUARTx)
Request a Receive Data flush.

Function Documentation

__STATIC_INLINE void LL_LPUART_RequestBreakSending ( USART_TypeDef * LPUARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_LPUART_RequestBreakSending
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2092 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode ( USART_TypeDef * LPUARTx )

Put LPUART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_LPUART_RequestEnterMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2103 of file stm32l4xx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_RequestRxDataFlush ( USART_TypeDef * LPUARTx )

Request a Receive Data flush.

Reference Manual to LL API cross reference:
RQR RXFRQ LL_LPUART_RequestRxDataFlush
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2114 of file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
LPUART Exported Functions

Functions

ErrorStatus | LL_LPUART_DeInit (USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_LPUART_DeInit ( USART_TypeDef * LPUARTx )

De-initialize LPUART registers (Registers restored to their default values).

Parameters:
LPUARTx LPUART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPUART registers are de-initialized
  • ERROR: not applicable

Definition at line 129 of file stm32l4xx_ll_lpuart.c.

References assert_param, LL_APB1_GRP2_ForceReset(), LL_APB1_GRP2_PERIPH_LPUART1, and LL_APB1_GRP2_ReleaseReset().

ErrorStatus LL_LPUART_Init | ( | USART_TypeDef * | LPUARTx,
 |  | LL_LPUART_InitTypeDef * | LPUART_InitStruct
 | ) |  |

Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.

Note:
As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0), LPUART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
LPUARTx | LPUART Instance
LPUART_InitStruct | pointer to a LL_LPUART_InitTypeDef structure that contains the configuration information for the specified LPUART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
  • ERROR: Problem occurred during LPUART Registers initialization

Definition at line 158 of file stm32l4xx_ll_lpuart.c.

References assert_param, LL_LPUART_InitTypeDef::BaudRate, LL_LPUART_InitTypeDef::DataWidth, LL_LPUART_InitTypeDef::HardwareFlowControl, IS_LL_LPUART_BAUDRATE, IS_LL_LPUART_DATAWIDTH, IS_LL_LPUART_DIRECTION, IS_LL_LPUART_HWCONTROL, IS_LL_LPUART_PARITY, IS_LL_LPUART_STOPBITS, LL_LPUART_IsEnabled(), LL_LPUART_SetBaudRate(), LL_LPUART_SetHWFlowCtrl(), LL_LPUART_SetStopBitsLength(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_LPUART1_CLKSOURCE, LL_RCC_PERIPH_FREQUENCY_NO, LL_LPUART_InitTypeDef::Parity, LL_LPUART_InitTypeDef::StopBits, and LL_LPUART_InitTypeDef::TransferDirection.

void LL_LPUART_StructInit ( LL_LPUART_InitTypeDef * LPUART_InitStruct )

Set each LL_LPUART_InitTypeDef field to default value.

Parameters:
LPUART_InitStruct pointer to a LL_LPUART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 227 of file stm32l4xx_ll_lpuart.c.

References LL_LPUART_InitTypeDef::BaudRate, LL_LPUART_InitTypeDef::DataWidth, LL_LPUART_InitTypeDef::HardwareFlowControl, LL_LPUART_DATAWIDTH_8B, LL_LPUART_DIRECTION_TX_RX, LL_LPUART_HWCONTROL_NONE, LL_LPUART_PARITY_NONE, LL_LPUART_STOPBITS_1, LL_LPUART_InitTypeDef::Parity, LL_LPUART_InitTypeDef::StopBits, and LL_LPUART_InitTypeDef::TransferDirection.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP

Modules
OPAMP
STM32L4xx_LL_Driver

Modules

OPAMP Private Constants
OPAMP Private Macros
OPAMP Exported Init structure
OPAMP Exported Constants
OPAMP Exported Macros
OPAMP Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for OPAMP registers.

Register | Bit | Function
CSR | CALON | LL_OPAMP_GetMode
 |  | LL_OPAMP_SetMode
 | CALOUT | LL_OPAMP_IsCalibrationOutputSet
 | CALSEL | LL_OPAMP_GetCalibrationSelection
 |  | LL_OPAMP_SetCalibrationSelection
 | OPALPM | LL_OPAMP_GetPowerMode
 |  | LL_OPAMP_SetPowerMode
 | OPAMODE | LL_OPAMP_GetFunctionalMode
 |  | LL_OPAMP_SetFunctionalMode
 | OPAMPXEN | LL_OPAMP_Disable
 |  | LL_OPAMP_Enable
 |  | LL_OPAMP_IsEnabled
 | OPARANGE | LL_OPAMP_GetCommonPowerRange
 |  | LL_OPAMP_SetCommonPowerRange
 | PGGAIN | LL_OPAMP_GetPGAGain
 |  | LL_OPAMP_SetPGAGain
 | USERTRIM | LL_OPAMP_GetTrimmingMode
 |  | LL_OPAMP_SetTrimmingMode
 | VMSEL | LL_OPAMP_GetInputInverting
 |  | LL_OPAMP_SetInputInverting
 | VPSEL | LL_OPAMP_GetInputNonInverting
 |  | LL_OPAMP_SetInputNonInverting
LPOTR | TRIMLPOFFSETN | LL_OPAMP_SetTrimmingValue
 | TRIMLPOFFSETP | LL_OPAMP_SetTrimmingValue
OTR | TRIMOFFSETN | LL_OPAMP_SetTrimmingValue
 | TRIMOFFSETP | LL_OPAMP_SetTrimmingValue
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STM32L486xx HAL User Manual: OPAMP Private Constants

Defines
OPAMP Private Constants
OPAMP

Defines

#define | OPAMP_POWERMODE_OTR_REGOFFSET ((uint32_t)0x00000000U)
#define | OPAMP_POWERMODE_LPOTR_REGOFFSET ((uint32_t)0x00000001U)
#define | OPAMP_POWERMODE_OTR_REGOFFSET_MASK (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET)
#define | OPAMP_POWERMODE_CSR_BIT_MASK (OPAMP_CSR_OPALPM)
#define | OPAMP_TRIMMING_SELECT_MASK (OPAMP1_CSR_CALSEL)
#define | OPAMP_TRIMMING_VALUE_MASK (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)

Define Documentation

#define OPAMP_POWERMODE_CSR_BIT_MASK (OPAMP_CSR_OPALPM)

Definition at line 78 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_SetPowerMode().

#define OPAMP_POWERMODE_LPOTR_REGOFFSET ((uint32_t)0x00000001U)

Definition at line 74 of file stm32l4xx_ll_opamp.h.

#define OPAMP_POWERMODE_OTR_REGOFFSET ((uint32_t)0x00000000U)

Definition at line 73 of file stm32l4xx_ll_opamp.h.

#define OPAMP_POWERMODE_OTR_REGOFFSET_MASK (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET)

Definition at line 75 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_GetTrimmingValue(), and LL_OPAMP_SetTrimmingValue().

#define OPAMP_TRIMMING_SELECT_MASK (OPAMP1_CSR_CALSEL)

Definition at line 85 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_SetCalibrationSelection().

#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)

Definition at line 86 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_GetTrimmingValue(), and LL_OPAMP_SetTrimmingValue().

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STM32L486xx HAL User Manual: OPAMP Private Macros

Defines
OPAMP Private Macros
OPAMP

Defines

#define | IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)
#define | IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__)
#define | IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__)
#define | __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __OPAMP_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFSET__
 | ) | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Register address

Definition at line 106 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_GetTrimmingValue(), and LL_OPAMP_SetTrimmingValue().

#define IS_LL_OPAMP_FUNCTIONAL_MODE ( __FUNCTIONAL_MODE__ )
Value:
(   ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE)                      \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER)                        \
   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA)                             \
  )

Definition at line 74 of file stm32l4xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

#define IS_LL_OPAMP_INPUT_INVERTING | ( | __OPAMPX__,
 |  | __INPUT_INVERTING__
 | ) |
Value:
(   ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0)                     \
   || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1)                     \
   || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO)              \
  )

Definition at line 93 of file stm32l4xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

#define IS_LL_OPAMP_INPUT_NONINVERTING | ( | __OPAMPX__,
 |  | __INPUT_NONINVERTING__
 | ) |
Value:
(   ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)               \
   || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC1_CH1)          \
  )

Definition at line 84 of file stm32l4xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

#define IS_LL_OPAMP_POWER_MODE ( __POWER_MODE__ )
Value:
(   ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMAL)                          \
   || ((__POWER_MODE__) == LL_OPAMP_POWERMODE_LOWPOWER))

Definition at line 70 of file stm32l4xx_ll_opamp.c.

Referenced by LL_OPAMP_Init().

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STM32L486xx HAL User Manual: LL_OPAMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_OPAMP_InitTypeDef Struct Reference
OPAMP Exported Init structure

Structure definition of some features of OPAMP instance. More...

#include <stm32l4xx_ll_opamp.h>

Data Fields

uint32_t | PowerMode
uint32_t | FunctionalMode
uint32_t | InputNonInverting
uint32_t | InputInverting

Detailed Description

Structure definition of some features of OPAMP instance.

Definition at line 126 of file stm32l4xx_ll_opamp.h.

Field Documentation

uint32_t LL_OPAMP_InitTypeDef::FunctionalMode

Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ... This parameter can be a value of OPAMP functional mode

Note:
If OPAMP is configured in mode PGA, the gain can be configured using function LL_OPAMP_SetPGAGain().

This feature can be modified afterwards using unitary function LL_OPAMP_SetFunctionalMode().

Definition at line 133 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

uint32_t LL_OPAMP_InitTypeDef::InputInverting

Set OPAMP inverting input connection. This parameter can be a value of OPAMP input inverting

Note:
OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.

This feature can be modified afterwards using unitary function LL_OPAMP_SetInputInverting().

Definition at line 144 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

uint32_t LL_OPAMP_InitTypeDef::InputNonInverting

Set OPAMP input non-inverting connection. This parameter can be a value of OPAMP input non-inverting

This feature can be modified afterwards using unitary function LL_OPAMP_SetInputNonInverting().

Definition at line 139 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

uint32_t LL_OPAMP_InitTypeDef::PowerMode

Set OPAMP power mode. This parameter can be a value of OPAMP power mode

This feature can be modified afterwards using unitary function LL_OPAMP_SetPowerMode().

Definition at line 128 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_opamp.h
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STM32L486xx HAL User Manual: OPAMP power supply range

Defines
OPAMP power supply range
OPAMP Exported Constants

Defines

#define | LL_OPAMP_POWERSUPPLY_RANGE_LOW ((uint32_t)0x00000000U)
#define | LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP1_CSR_OPARANGE)

Define Documentation

#define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP1_CSR_OPARANGE)

Power supply range high. On STM32L4 serie: Vdda higher than 2.4V.

Definition at line 166 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_POWERSUPPLY_RANGE_LOW ((uint32_t)0x00000000U)

Power supply range low. On STM32L4 serie: Vdda lower than 2.4V.

Definition at line 165 of file stm32l4xx_ll_opamp.h.

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STM32L486xx HAL User Manual: OPAMP power mode

Defines
OPAMP power mode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_POWERMODE_NORMAL (OPAMP_POWERMODE_OTR_REGOFFSET)
#define | LL_OPAMP_POWERMODE_LOWPOWER (OPAMP_POWERMODE_LPOTR_REGOFFSET | OPAMP_CSR_OPALPM)

Define Documentation

#define LL_OPAMP_POWERMODE_LOWPOWER (OPAMP_POWERMODE_LPOTR_REGOFFSET | OPAMP_CSR_OPALPM)

OPAMP power mode low-power

Definition at line 175 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_POWERMODE_NORMAL (OPAMP_POWERMODE_OTR_REGOFFSET)

OPAMP power mode normal

Definition at line 174 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_StructInit().

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STM32L486xx HAL User Manual: OPAMP mode calibration or functional.

Defines
OPAMP mode calibration or functional.
OPAMP Exported Constants

Defines

#define | LL_OPAMP_MODE_FUNCTIONAL ((uint32_t)0x00000000U)
#define | LL_OPAMP_MODE_CALIBRATION (OPAMP1_CSR_CALON)

Define Documentation

#define LL_OPAMP_MODE_CALIBRATION (OPAMP1_CSR_CALON)

OPAMP calibration mode

Definition at line 184 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_MODE_FUNCTIONAL ((uint32_t)0x00000000U)

OPAMP functional mode

Definition at line 183 of file stm32l4xx_ll_opamp.h.

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STM32L486xx HAL User Manual: OPAMP functional mode

Defines
OPAMP functional mode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_MODE_STANDALONE ((uint32_t)0x00000000U)
#define | LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_OPAMODE_1 | OPAMP_CSR_OPAMODE_0)
#define | LL_OPAMP_MODE_PGA (OPAMP_CSR_OPAMODE_1)

Define Documentation

#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_OPAMODE_1 | OPAMP_CSR_OPAMODE_0)

OPAMP functional mode, OPAMP operation in follower

Definition at line 193 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

#define LL_OPAMP_MODE_PGA (OPAMP_CSR_OPAMODE_1)

OPAMP functional mode, OPAMP operation in PGA

Definition at line 194 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_MODE_STANDALONE ((uint32_t)0x00000000U)

OPAMP functional mode, OPAMP operation in standalone

Definition at line 192 of file stm32l4xx_ll_opamp.h.

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STM32L486xx HAL User Manual: OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)

Defines
OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
OPAMP Exported Constants

Defines

#define | LL_OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000U)
#define | LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGGAIN_0)
#define | LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGGAIN_1)
#define | LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 )

Define Documentation

#define LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 )

OPAMP PGA gain 16

Definition at line 205 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000U)

OPAMP PGA gain 2

Definition at line 202 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGGAIN_0)

OPAMP PGA gain 4

Definition at line 203 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGGAIN_1)

OPAMP PGA gain 8

Definition at line 204 of file stm32l4xx_ll_opamp.h.

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STM32L486xx HAL User Manual: OPAMP input non-inverting

Defines
OPAMP input non-inverting
OPAMP Exported Constants

Defines

#define | LL_OPAMP_INPUT_NONINVERT_IO0 ((uint32_t)0x00000000U)
#define | LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 (OPAMP1_CSR_VPSEL)

Define Documentation

#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 (OPAMP1_CSR_VPSEL)

OPAMP non inverting input connected to DAC1 channel1 output

Definition at line 214 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_NONINVERT_IO0 ((uint32_t)0x00000000U)

OPAMP non inverting input connected to GPIO pin

Definition at line 213 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_StructInit().

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STM32L486xx HAL User Manual: OPAMP input inverting

Defines
OPAMP input inverting
OPAMP Exported Constants

Defines

#define | LL_OPAMP_INPUT_INVERT_IO0 ((uint32_t)0x00000000U)
#define | LL_OPAMP_INPUT_INVERT_IO1 (OPAMP1_CSR_VMSEL_0)
#define | LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP1_CSR_VMSEL_1)

Define Documentation

#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP1_CSR_VMSEL_1)

OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering)

Definition at line 224 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_Init(), and LL_OPAMP_StructInit().

#define LL_OPAMP_INPUT_INVERT_IO0 ((uint32_t)0x00000000U)

OPAMP inverting input connected to GPIO pin (valid also in PGA mode for filtering). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).

Definition at line 222 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP1_CSR_VMSEL_0)

OPAMP inverting input (low leakage input) connected to GPIO pin (available only on package BGA132). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).

Definition at line 223 of file stm32l4xx_ll_opamp.h.

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STM32L486xx HAL User Manual: OPAMP inputs legacy literals name

Defines
OPAMP inputs legacy literals name
OPAMP Exported Constants

Defines

#define | LL_OPAMP_NONINVERTINGINPUT_IO0 LL_OPAMP_INPUT_NONINVERT_IO0
#define | LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINVERT_DAC1_CH1
#define | LL_OPAMP_INVERTINGINPUT_IO0 LL_OPAMP_INPUT_INVERT_IO0
#define | LL_OPAMP_INVERTINGINPUT_IO1 LL_OPAMP_INPUT_INVERT_IO1
#define | LL_OPAMP_INVERTINGINPUT_CONNECT_NO LL_OPAMP_INPUT_INVERT_CONNECT_NO

Define Documentation

#define LL_OPAMP_INVERTINGINPUT_CONNECT_NO LL_OPAMP_INPUT_INVERT_CONNECT_NO

Definition at line 237 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_INVERTINGINPUT_IO0 LL_OPAMP_INPUT_INVERT_IO0

Definition at line 235 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_INVERTINGINPUT_IO1 LL_OPAMP_INPUT_INVERT_IO1

Definition at line 236 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINVERT_DAC1_CH1

Definition at line 233 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_NONINVERTINGINPUT_IO0 LL_OPAMP_INPUT_NONINVERT_IO0

Definition at line 232 of file stm32l4xx_ll_opamp.h.

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STM32L486xx HAL User Manual: OPAMP trimming mode

Defines
OPAMP trimming mode
OPAMP Exported Constants

Defines

#define | LL_OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000U)
#define | LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM)

Define Documentation

#define LL_OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000U)

OPAMP trimming factors set to factory values

Definition at line 245 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM)

OPAMP trimming factors set to user values

Definition at line 246 of file stm32l4xx_ll_opamp.h.

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STM32L486xx HAL User Manual: OPAMP trimming of transistors differential pair NMOS or PMOS

Defines
OPAMP trimming of transistors differential pair NMOS or PMOS
OPAMP Exported Constants

Defines

#define | LL_OPAMP_TRIMMING_NMOS (OPAMP_OTR_TRIMOFFSETN)
#define | LL_OPAMP_TRIMMING_PMOS (OPAMP_OTR_TRIMOFFSETP | OPAMP1_CSR_CALSEL)

Define Documentation

#define LL_OPAMP_TRIMMING_NMOS (OPAMP_OTR_TRIMOFFSETN)

OPAMP trimming of transistors differential pair NMOS

Definition at line 254 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_TRIMMING_PMOS (OPAMP_OTR_TRIMOFFSETP | OPAMP1_CSR_CALSEL)

OPAMP trimming of transistors differential pair PMOS

Definition at line 255 of file stm32l4xx_ll_opamp.h.

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STM32L486xx HAL User Manual: Common write and read registers macro

Defines
Common write and read registers macro
OPAMP Exported Macros

Defines

#define | LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in OPAMP register.
#define | LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in OPAMP register.

Define Documentation

#define LL_OPAMP_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in OPAMP register.

Parameters:
__INSTANCE__ | OPAMP Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 286 of file stm32l4xx_ll_opamp.h.

#define LL_OPAMP_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in OPAMP register.

Parameters:
__INSTANCE__ | OPAMP Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 278 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_DeInit().

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STM32L486xx HAL User Manual: OPAMP helper macro

Defines
OPAMP helper macro
OPAMP Exported Macros

Defines

#define | __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__) (OPAMP12_COMMON)
Helper macro to select the OPAMP common instance to which is belonging the selected OPAMP instance.
#define | __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()
Helper macro to check if all OPAMP instances sharing the same OPAMP common instance are disabled.

Define Documentation

#define __LL_OPAMP_COMMON_INSTANCE ( __OPAMPx__ ) (OPAMP12_COMMON)

Helper macro to select the OPAMP common instance to which is belonging the selected OPAMP instance.

Note:
OPAMP common register instance can be used to set parameters common to several OPAMP instances. Refer to functions having argument "OPAMPxy_COMMON" as parameter.
Parameters:
__OPAMPx__ OPAMP instance
Return values:
OPAMP common instance

Definition at line 305 of file stm32l4xx_ll_opamp.h.

#define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE ( )
Value:
(LL_OPAMP_IsEnabled(OPAMP1) |                                                \
   LL_OPAMP_IsEnabled(OPAMP2)  )

Helper macro to check if all OPAMP instances sharing the same OPAMP common instance are disabled.

Note:
This check is required by functions with setting conditioned to OPAMP state: All OPAMP instances of the OPAMP common group must be disabled. Refer to functions having argument "OPAMPxy_COMMON" as parameter.
Return values:
0,: All OPAMP instances sharing the same OPAMP common instance are disabled. 1: At least one OPAMP instance sharing the same OPAMP common instance is enabled

Definition at line 325 of file stm32l4xx_ll_opamp.h.

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STM32L486xx HAL User Manual: Configuration of OPAMP hierarchical scope: common to several OPAMP instances

Functions
Configuration of OPAMP hierarchical scope: common to several OPAMP instances
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetCommonPowerRange (OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange)
Set OPAMP power range.
__STATIC_INLINE uint32_t | LL_OPAMP_GetCommonPowerRange (OPAMP_Common_TypeDef *OPAMPxy_COMMON)
Get OPAMP power range.

Function Documentation

__STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange ( OPAMP_Common_TypeDef * OPAMPxy_COMMON )

Get OPAMP power range.

Note:
The OPAMP power range applies to several OPAMP instances (if several OPAMP instances available on the selected device).
Reference Manual to LL API cross reference:
CSR OPARANGE LL_OPAMP_GetCommonPowerRange
Parameters:
OPAMPxy_COMMON OPAMP common instance (can be set directly from CMSIS definition or by using helper macro __LL_OPAMP_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_POWERSUPPLY_RANGE_LOW
  • LL_OPAMP_POWERSUPPLY_RANGE_HIGH

Definition at line 384 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange | ( | OPAMP_Common_TypeDef * | OPAMPxy_COMMON,
 |  | uint32_t | PowerRange
 | ) |  |

Set OPAMP power range.

Note:
The OPAMP power range applies to several OPAMP instances (if several OPAMP instances available on the selected device).
On this STM32 serie, setting of this feature is conditioned to OPAMP state: All OPAMP instances of the OPAMP common group must be disabled. This check can be done with function LL_OPAMP_IsEnabled() for each OPAMP instance or by using helper macro __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CSR OPARANGE LL_OPAMP_SetCommonPowerRange
Parameters:
OPAMPxy_COMMON OPAMP common instance (can be set directly from CMSIS definition or by using helper macro __LL_OPAMP_COMMON_INSTANCE() )
PowerRange This parameter can be one of the following values:
  • LL_OPAMP_POWERSUPPLY_RANGE_LOW
  • LL_OPAMP_POWERSUPPLY_RANGE_HIGH
Return values:
None

Definition at line 368 of file stm32l4xx_ll_opamp.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of OPAMP hierarchical scope: OPAMP instance

Functions
Configuration of OPAMP hierarchical scope: OPAMP instance
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetPowerMode (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
Set OPAMP power mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPowerMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP power mode.
__STATIC_INLINE void | LL_OPAMP_SetMode (OPAMP_TypeDef *OPAMPx, uint32_t Mode)
Set OPAMP mode calibration or functional.
__STATIC_INLINE uint32_t | LL_OPAMP_GetMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP mode calibration or functional.
__STATIC_INLINE void | LL_OPAMP_SetFunctionalMode (OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
Set OPAMP functional mode by setting internal connections.
__STATIC_INLINE uint32_t | LL_OPAMP_GetFunctionalMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP functional mode from setting of internal connections.
__STATIC_INLINE void | LL_OPAMP_SetPGAGain (OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
Set OPAMP PGA gain.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPGAGain (OPAMP_TypeDef *OPAMPx)
Get OPAMP PGA gain.

Function Documentation

__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP functional mode from setting of internal connections.

OPAMP operation in standalone, follower, ...

Reference Manual to LL API cross reference:
CSR OPAMODE LL_OPAMP_GetFunctionalMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_MODE_STANDALONE
  • LL_OPAMP_MODE_FOLLOWER
  • LL_OPAMP_MODE_PGA

Definition at line 502 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP mode calibration or functional.

Note:
OPAMP mode corresponds to functional or calibration mode:
  • functional mode: OPAMP operation in standalone, follower, ... Set functional mode using function LL_OPAMP_SetFunctionalMode().
  • calibration mode: offset calibration of the selected transistors differential pair NMOS or PMOS.
Reference Manual to LL API cross reference:
CSR CALON LL_OPAMP_GetMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_MODE_FUNCTIONAL
  • LL_OPAMP_MODE_CALIBRATION

Definition at line 466 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain ( OPAMP_TypeDef * OPAMPx )

Get OPAMP PGA gain.

Note:
Preliminarily, OPAMP must be set in mode PGA using function LL_OPAMP_SetFunctionalMode().
Reference Manual to LL API cross reference:
CSR PGGAIN LL_OPAMP_GetPGAGain
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_PGA_GAIN_2
  • LL_OPAMP_PGA_GAIN_4
  • LL_OPAMP_PGA_GAIN_8
  • LL_OPAMP_PGA_GAIN_16

Definition at line 537 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP power mode.

Reference Manual to LL API cross reference:
CSR OPALPM LL_OPAMP_GetPowerMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_POWERMODE_NORMAL
  • LL_OPAMP_POWERMODE_LOWPOWER

Definition at line 420 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetFunctionalMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | FunctionalMode
 | ) |  |

Set OPAMP functional mode by setting internal connections.

OPAMP operation in standalone, follower, ...

Note:
This function reset bit of calibration mode to ensure to be in functional mode, in order to have OPAMP parameters (inputs selection, ...) set with the corresponding OPAMP mode to be effective.
Reference Manual to LL API cross reference:
CSR OPAMODE LL_OPAMP_SetFunctionalMode
Parameters:
OPAMPx OPAMP instance
FunctionalMode This parameter can be one of the following values:
  • LL_OPAMP_MODE_STANDALONE
  • LL_OPAMP_MODE_FOLLOWER
  • LL_OPAMP_MODE_PGA
Return values:
None

Definition at line 486 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | Mode
 | ) |  |

Set OPAMP mode calibration or functional.

Note:
OPAMP mode corresponds to functional or calibration mode:
  • functional mode: OPAMP operation in standalone, follower, ... Set functional mode using function LL_OPAMP_SetFunctionalMode().
  • calibration mode: offset calibration of the selected transistors differential pair NMOS or PMOS.
On this STM32 serie, during calibration, OPAMP functional mode must be set to standalone or follower mode (in order to open internal connections to resistors of PGA mode). Refer to function LL_OPAMP_SetFunctionalMode().
Reference Manual to LL API cross reference:
CSR CALON LL_OPAMP_SetMode
Parameters:
OPAMPx OPAMP instance
Mode This parameter can be one of the following values:
  • LL_OPAMP_MODE_FUNCTIONAL
  • LL_OPAMP_MODE_CALIBRATION
Return values:
None

Definition at line 447 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetPGAGain | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | PGAGain
 | ) |  |

Set OPAMP PGA gain.

Note:
Preliminarily, OPAMP must be set in mode PGA using function LL_OPAMP_SetFunctionalMode().
Reference Manual to LL API cross reference:
CSR PGGAIN LL_OPAMP_SetPGAGain
Parameters:
OPAMPx OPAMP instance
PGAGain This parameter can be one of the following values:
  • LL_OPAMP_PGA_GAIN_2
  • LL_OPAMP_PGA_GAIN_4
  • LL_OPAMP_PGA_GAIN_8
  • LL_OPAMP_PGA_GAIN_16
Return values:
None

Definition at line 520 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetPowerMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | PowerMode
 | ) |  |

Set OPAMP power mode.

Note:
The OPAMP must be disabled to change this configuration.
Reference Manual to LL API cross reference:
CSR OPALPM LL_OPAMP_SetPowerMode
Parameters:
OPAMPx OPAMP instance
PowerMode This parameter can be one of the following values:
  • LL_OPAMP_POWERMODE_NORMAL
  • LL_OPAMP_POWERMODE_LOWPOWER
Return values:
None

Definition at line 407 of file stm32l4xx_ll_opamp.h.

References OPAMP_POWERMODE_CSR_BIT_MASK.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of OPAMP inputs

Functions
Configuration of OPAMP inputs
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetInputNonInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
Set OPAMP non-inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputNonInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP non-inverting input connection.
__STATIC_INLINE void | LL_OPAMP_SetInputInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
Set OPAMP inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP inverting input connection.

Function Documentation

__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting ( OPAMP_TypeDef * OPAMPx )

Get OPAMP inverting input connection.

Reference Manual to LL API cross reference:
CSR VMSEL LL_OPAMP_GetInputInverting
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_INPUT_INVERT_IO0
  • LL_OPAMP_INPUT_INVERT_IO1
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO

Definition at line 605 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting ( OPAMP_TypeDef * OPAMPx )

Get OPAMP non-inverting input connection.

Reference Manual to LL API cross reference:
CSR VPSEL LL_OPAMP_GetInputNonInverting
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_INPUT_NONINVERT_IO0
  • LL_OPAMP_INPUT_NONINVERT_DAC1_CH1

Definition at line 572 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetInputInverting | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InputInverting
 | ) |  |

Set OPAMP inverting input connection.

Note:
OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).
Reference Manual to LL API cross reference:
CSR VMSEL LL_OPAMP_SetInputInverting
Parameters:
OPAMPx OPAMP instance
InputInverting This parameter can be one of the following values:
  • LL_OPAMP_INPUT_INVERT_IO0
  • LL_OPAMP_INPUT_INVERT_IO1
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO
Return values:
None

Definition at line 591 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_SetInvertingInput().

__STATIC_INLINE void LL_OPAMP_SetInputNonInverting | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InputNonInverting
 | ) |  |

Set OPAMP non-inverting input connection.

Reference Manual to LL API cross reference:
CSR VPSEL LL_OPAMP_SetInputNonInverting
Parameters:
OPAMPx OPAMP instance
InputNonInverting This parameter can be one of the following values:
  • LL_OPAMP_INPUT_NONINVERT_IO0
  • LL_OPAMP_INPUT_NONINVERT_DAC1_CH1
Return values:
None

Definition at line 559 of file stm32l4xx_ll_opamp.h.

Referenced by LL_OPAMP_SetNonInvertingInput().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration of OPAMP, legacy functions name

Functions
Configuration of OPAMP, legacy functions name
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetNonInvertingInput (OPAMP_TypeDef *OPAMPx, uint32_t NonInvertingInput)
__STATIC_INLINE void | LL_OPAMP_SetInvertingInput (OPAMP_TypeDef *OPAMPx, uint32_t InvertingInput)

Function Documentation

__STATIC_INLINE void LL_OPAMP_SetInvertingInput | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | InvertingInput
 | ) |  |

Definition at line 624 of file stm32l4xx_ll_opamp.h.

References LL_OPAMP_SetInputInverting().

__STATIC_INLINE void LL_OPAMP_SetNonInvertingInput | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | NonInvertingInput
 | ) |  |

Definition at line 619 of file stm32l4xx_ll_opamp.h.

References LL_OPAMP_SetInputNonInverting().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration and operation of OPAMP trimming

Functions
Configuration and operation of OPAMP trimming
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_SetTrimmingMode (OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
Set OPAMP trimming mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP trimming mode.
__STATIC_INLINE void | LL_OPAMP_SetCalibrationSelection (OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
Set OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_GetCalibrationSelection (OPAMP_TypeDef *OPAMPx)
Get OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_IsCalibrationOutputSet (OPAMP_TypeDef *OPAMPx)
Get OPAMP calibration result of toggling output.
__STATIC_INLINE void | LL_OPAMP_SetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
Set OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
Get OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.

Function Documentation

__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection ( OPAMP_TypeDef * OPAMPx )

Get OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.

Note:
Preliminarily, OPAMP must be set in mode calibration using function LL_OPAMP_SetMode().
Reference Manual to LL API cross reference:
CSR CALSEL LL_OPAMP_GetCalibrationSelection
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS
  • LL_OPAMP_TRIMMING_PMOS

Definition at line 694 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode ( OPAMP_TypeDef * OPAMPx )

Get OPAMP trimming mode.

Reference Manual to LL API cross reference:
CSR USERTRIM LL_OPAMP_GetTrimmingMode
Parameters:
OPAMPx OPAMP instance
Return values:
Returned value can be one of the following values:
  • LL_OPAMP_TRIMMING_FACTORY
  • LL_OPAMP_TRIMMING_USER

Definition at line 659 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | PowerMode,
 |  | uint32_t | TransistorsDiffPair
 | ) |  |

Get OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.

Reference Manual to LL API cross reference:
OTR TRIMOFFSETN LL_OPAMP_SetTrimmingValue
OTR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
LPOTR TRIMLPOFFSETN LL_OPAMP_SetTrimmingValue
LPOTR TRIMLPOFFSETP LL_OPAMP_SetTrimmingValue
Parameters:
OPAMPx OPAMP instance
PowerMode This parameter can be one of the following values:
  • LL_OPAMP_POWERMODE_NORMAL
  • LL_OPAMP_POWERMODE_LOWPOWER
TransistorsDiffPair This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS
  • LL_OPAMP_TRIMMING_PMOS
Return values:
0x0...0x1F

Definition at line 764 of file stm32l4xx_ll_opamp.h.

References __OPAMP_PTR_REG_OFFSET, OPAMP_POWERMODE_OTR_REGOFFSET_MASK, and OPAMP_TRIMMING_VALUE_MASK.

__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet ( OPAMP_TypeDef * OPAMPx )

Get OPAMP calibration result of toggling output.

Note:
This functions returns: 0 if OPAMP calibration output is reset 1 if OPAMP calibration output is set
Reference Manual to LL API cross reference:
CSR CALOUT LL_OPAMP_IsCalibrationOutputSet
Parameters:
OPAMPx OPAMP instance
Return values:
State of bit (1 or 0).

Definition at line 711 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | TransistorsDiffPair
 | ) |  |

Set OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.

Note:
Preliminarily, OPAMP must be set in mode calibration using function LL_OPAMP_SetMode().
Reference Manual to LL API cross reference:
CSR CALSEL LL_OPAMP_SetCalibrationSelection
Parameters:
OPAMPx OPAMP instance
TransistorsDiffPair This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS
  • LL_OPAMP_TRIMMING_PMOS
Return values:
None

Definition at line 676 of file stm32l4xx_ll_opamp.h.

References OPAMP_TRIMMING_SELECT_MASK.

__STATIC_INLINE void LL_OPAMP_SetTrimmingMode | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | TrimmingMode
 | ) |  |

Set OPAMP trimming mode.

Reference Manual to LL API cross reference:
CSR USERTRIM LL_OPAMP_SetTrimmingMode
Parameters:
OPAMPx OPAMP instance
TrimmingMode This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_FACTORY
  • LL_OPAMP_TRIMMING_USER
Return values:
None

Definition at line 646 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_SetTrimmingValue | ( | OPAMP_TypeDef * | OPAMPx,
 |  | uint32_t | PowerMode,
 |  | uint32_t | TransistorsDiffPair,
 |  | uint32_t | TrimmingValue
 | ) |  |

Set OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.

Reference Manual to LL API cross reference:
OTR TRIMOFFSETN LL_OPAMP_SetTrimmingValue
OTR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
LPOTR TRIMLPOFFSETN LL_OPAMP_SetTrimmingValue
LPOTR TRIMLPOFFSETP LL_OPAMP_SetTrimmingValue
Parameters:
OPAMPx | OPAMP instance
PowerMode This parameter can be one of the following values:
  • LL_OPAMP_POWERMODE_NORMAL
  • LL_OPAMP_POWERMODE_LOWPOWER
TransistorsDiffPair This parameter can be one of the following values:
  • LL_OPAMP_TRIMMING_NMOS
  • LL_OPAMP_TRIMMING_PMOS
TrimmingValue | 0x00...0x1F
Return values:
None

Definition at line 734 of file stm32l4xx_ll_opamp.h.

References __OPAMP_PTR_REG_OFFSET, OPAMP_POWERMODE_OTR_REGOFFSET_MASK, and OPAMP_TRIMMING_VALUE_MASK.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Operation on OPAMP instance

Functions
Operation on OPAMP instance
OPAMP Exported Functions

Functions

__STATIC_INLINE void | LL_OPAMP_Enable (OPAMP_TypeDef *OPAMPx)
Enable OPAMP instance.
__STATIC_INLINE void | LL_OPAMP_Disable (OPAMP_TypeDef *OPAMPx)
Disable OPAMP instance.
__STATIC_INLINE uint32_t | LL_OPAMP_IsEnabled (OPAMP_TypeDef *OPAMPx)
Get OPAMP instance enable state (0: OPAMP is disabled, 1: OPAMP is enabled)

Function Documentation

__STATIC_INLINE void LL_OPAMP_Disable ( OPAMP_TypeDef * OPAMPx )

Disable OPAMP instance.

Reference Manual to LL API cross reference:
CSR OPAMPXEN LL_OPAMP_Disable
Parameters:
OPAMPx OPAMP instance
Return values:
None

Definition at line 804 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE void LL_OPAMP_Enable ( OPAMP_TypeDef * OPAMPx )

Enable OPAMP instance.

Note:
After enable from off state, OPAMP requires a delay to fullfill wake up time specification. Refer to device datasheet, parameter "tWAKEUP".
Reference Manual to LL API cross reference:
CSR OPAMPXEN LL_OPAMP_Enable
Parameters:
OPAMPx OPAMP instance
Return values:
None

Definition at line 793 of file stm32l4xx_ll_opamp.h.

__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled ( OPAMP_TypeDef * OPAMPx )

Get OPAMP instance enable state (0: OPAMP is disabled, 1: OPAMP is enabled)

Reference Manual to LL API cross reference:
CSR OPAMPXEN LL_OPAMP_IsEnabled
Parameters:
OPAMPx OPAMP instance
Return values:
State of bit (1 or 0).

Definition at line 816 of file stm32l4xx_ll_opamp.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
OPAMP Exported Functions

Functions

ErrorStatus | LL_OPAMP_DeInit (OPAMP_TypeDef *OPAMPx)
De-initialize registers of the selected OPAMP instance to their default reset values.
ErrorStatus | LL_OPAMP_Init (OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Initialize some features of OPAMP instance.
void | LL_OPAMP_StructInit (LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Set each LL_OPAMP_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_OPAMP_DeInit ( OPAMP_TypeDef * OPAMPx )

De-initialize registers of the selected OPAMP instance to their default reset values.

Parameters:
OPAMPx OPAMP instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: OPAMP registers are de-initialized
  • ERROR: OPAMP registers are not de-initialized

Definition at line 123 of file stm32l4xx_ll_opamp.c.

References assert_param, and LL_OPAMP_WriteReg.

ErrorStatus LL_OPAMP_Init | ( | OPAMP_TypeDef * | OPAMPx,
 |  | LL_OPAMP_InitTypeDef * | OPAMP_InitStruct
 | ) |  |

Initialize some features of OPAMP instance.

Note:
This function reset bit of calibration mode to ensure to be in functional mode, in order to have OPAMP parameters (inputs selection, ...) set with the corresponding OPAMP mode to be effective.
This function configures features of the selected OPAMP instance. Some features are also available at scope OPAMP common instance (common to several OPAMP instances). Refer to functions having argument "OPAMPxy_COMMON" as parameter.
Parameters:
OPAMPx | OPAMP instance
OPAMP_InitStruct | Pointer to a LL_OPAMP_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: OPAMP registers are initialized
  • ERROR: OPAMP registers are not initialized

Definition at line 151 of file stm32l4xx_ll_opamp.c.

References assert_param, LL_OPAMP_InitTypeDef::FunctionalMode, LL_OPAMP_InitTypeDef::InputInverting, LL_OPAMP_InitTypeDef::InputNonInverting, IS_LL_OPAMP_FUNCTIONAL_MODE, IS_LL_OPAMP_INPUT_INVERTING, IS_LL_OPAMP_INPUT_NONINVERTING, IS_LL_OPAMP_POWER_MODE, LL_OPAMP_INPUT_INVERT_CONNECT_NO, LL_OPAMP_MODE_FOLLOWER, OPAMP_POWERMODE_CSR_BIT_MASK, and LL_OPAMP_InitTypeDef::PowerMode.

void LL_OPAMP_StructInit ( LL_OPAMP_InitTypeDef * OPAMP_InitStruct )

Set each LL_OPAMP_InitTypeDef field to default value.

Parameters:
OPAMP_InitStruct pointer to a LL_OPAMP_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 214 of file stm32l4xx_ll_opamp.c.

References LL_OPAMP_InitTypeDef::FunctionalMode, LL_OPAMP_InitTypeDef::InputInverting, LL_OPAMP_InitTypeDef::InputNonInverting, LL_OPAMP_INPUT_INVERT_CONNECT_NO, LL_OPAMP_INPUT_NONINVERT_IO0, LL_OPAMP_MODE_FOLLOWER, LL_OPAMP_POWERMODE_NORMAL, and LL_OPAMP_InitTypeDef::PowerMode.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR

Modules
PWR
STM32L4xx_LL_Driver

Modules

PWR Exported Constants
PWR Exported Macros
PWR Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for PWR registers.

Register | Bit | Function
CR1 | DBP | LL_PWR_DisableBkUpAccess
 |  | LL_PWR_EnableBkUpAccess
 |  | LL_PWR_IsEnabledBkUpAccess
 | LPMS | LL_PWR_GetPowerMode
 |  | LL_PWR_SetPowerMode
 | LPR | LL_PWR_DisableLowPowerRunMode
 |  | LL_PWR_EnableLowPowerRunMode
 |  | LL_PWR_EnterLowPowerRunMode
 |  | LL_PWR_ExitLowPowerRunMode
 |  | LL_PWR_IsEnabledLowPowerRunMode
 | VOS | LL_PWR_GetRegulVoltageScaling
 |  | LL_PWR_SetRegulVoltageScaling
CR2 | IOSV | LL_PWR_DisableVddIO2
 |  | LL_PWR_EnableVddIO2
 |  | LL_PWR_IsEnabledVddIO2
 | PLS | LL_PWR_GetPVDLevel
 |  | LL_PWR_SetPVDLevel
 | PVDE | LL_PWR_DisablePVD
 |  | LL_PWR_EnablePVD
 |  | LL_PWR_IsEnabledPVD
 | PVME1 | LL_PWR_DisablePVM
 |  | LL_PWR_EnablePVM
 |  | LL_PWR_IsEnabledPVM
 | PVME2 | LL_PWR_DisablePVM
 |  | LL_PWR_EnablePVM
 |  | LL_PWR_IsEnabledPVM
 | PVME3 | LL_PWR_DisablePVM
 |  | LL_PWR_EnablePVM
 |  | LL_PWR_IsEnabledPVM
 | PVME4 | LL_PWR_DisablePVM
 |  | LL_PWR_EnablePVM
 |  | LL_PWR_IsEnabledPVM
 | USV | LL_PWR_DisableVddUSB
 |  | LL_PWR_EnableVddUSB
 |  | LL_PWR_IsEnabledVddUSB
CR3 | APC | LL_PWR_DisablePUPDCfg
 |  | LL_PWR_EnablePUPDCfg
 |  | LL_PWR_IsEnabledPUPDCfg
 | EIWF | LL_PWR_DisableInternWU
 |  | LL_PWR_EnableInternWU
 |  | LL_PWR_IsEnabledInternWU
 | EWUP1 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | EWUP2 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | EWUP3 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | EWUP4 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | EWUP5 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | RRS | LL_PWR_DisableSRAM2Retention
 |  | LL_PWR_EnableSRAM2Retention
 |  | LL_PWR_IsEnabledSRAM2Retention
CR4 | VBE | LL_PWR_DisableBatteryCharging
 |  | LL_PWR_EnableBatteryCharging
 |  | LL_PWR_IsEnabledBatteryCharging
 | VBRS | LL_PWR_GetBattChargResistor
 |  | LL_PWR_SetBattChargResistor
 | WP1 | LL_PWR_IsWakeUpPinPolarityLow
 |  | LL_PWR_SetWakeUpPinPolarityHigh
 |  | LL_PWR_SetWakeUpPinPolarityLow
 | WP2 | LL_PWR_IsWakeUpPinPolarityLow
 |  | LL_PWR_SetWakeUpPinPolarityHigh
 |  | LL_PWR_SetWakeUpPinPolarityLow
 | WP3 | LL_PWR_IsWakeUpPinPolarityLow
 |  | LL_PWR_SetWakeUpPinPolarityHigh
 |  | LL_PWR_SetWakeUpPinPolarityLow
 | WP4 | LL_PWR_IsWakeUpPinPolarityLow
 |  | LL_PWR_SetWakeUpPinPolarityHigh
 |  | LL_PWR_SetWakeUpPinPolarityLow
 | WP5 | LL_PWR_IsWakeUpPinPolarityLow
 |  | LL_PWR_SetWakeUpPinPolarityHigh
 |  | LL_PWR_SetWakeUpPinPolarityLow
PDCRA | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRB | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRC | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRD | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRE | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRF | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRG | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRH | PD0-1 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PUCRA | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRB | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRC | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRD | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRE | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRF | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRG | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRH | PU0-1 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
SCR | CSBF | LL_PWR_ClearFlag_SB
 | CWUF | LL_PWR_ClearFlag_WU
 | CWUF1 | LL_PWR_ClearFlag_WU1
 | CWUF2 | LL_PWR_ClearFlag_WU2
 | CWUF3 | LL_PWR_ClearFlag_WU3
 | CWUF4 | LL_PWR_ClearFlag_WU4
 | CWUF5 | LL_PWR_ClearFlag_WU5
SR1 | SBF | LL_PWR_IsActiveFlag_SB
 | WUF1 | LL_PWR_IsActiveFlag_WU1
 | WUF2 | LL_PWR_IsActiveFlag_WU2
 | WUF3 | LL_PWR_IsActiveFlag_WU3
 | WUF4 | LL_PWR_IsActiveFlag_WU4
 | WUF5 | LL_PWR_IsActiveFlag_WU5
 | WUFI | LL_PWR_IsActiveFlag_InternWU
SR2 | PVDO | LL_PWR_IsActiveFlag_PVDO
 | PVMO1 | LL_PWR_IsActiveFlag_PVMO1
 | PVMO2 | LL_PWR_IsActiveFlag_PVMO2
 | PVMO3 | LL_PWR_IsActiveFlag_PVMO3
 | PVMO4 | LL_PWR_IsActiveFlag_PVMO4
 | REGLPF | LL_PWR_IsActiveFlag_REGLPF
 | REGLPS | LL_PWR_IsActiveFlag_REGLPS
 | VOSF | LL_PWR_IsActiveFlag_VOSF
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STM32L486xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_WriteReg function. More...

Defines

#define | LL_PWR_SCR_CSBF PWR_SCR_CSBF
#define | LL_PWR_SCR_CWUF PWR_SCR_CWUF
#define | LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
#define | LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
#define | LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
#define | LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
#define | LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1

Detailed Description

Flags defines which can be used with LL_PWR_WriteReg function.

Define Documentation

#define LL_PWR_SCR_CSBF PWR_SCR_CSBF

Definition at line 76 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF PWR_SCR_CWUF

Definition at line 77 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1

Definition at line 82 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2

Definition at line 81 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3

Definition at line 80 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4

Definition at line 79 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5

Definition at line 78 of file stm32l4xx_ll_pwr.h.

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STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_ReadReg function. More...

Defines

#define | LL_PWR_SR1_WUFI PWR_SR1_WUFI
#define | LL_PWR_SR1_SBF PWR_SR1_SBF
#define | LL_PWR_SR1_WUF5 PWR_SR1_WUF5
#define | LL_PWR_SR1_WUF4 PWR_SR1_WUF4
#define | LL_PWR_SR1_WUF3 PWR_SR1_WUF3
#define | LL_PWR_SR1_WUF2 PWR_SR1_WUF2
#define | LL_PWR_SR1_WUF1 PWR_SR1_WUF1
#define | LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
#define | LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
#define | LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
#define | LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
#define | LL_PWR_SR2_PVDO PWR_SR2_PVDO
#define | LL_PWR_SR2_VOSF PWR_SR2_VOSF
#define | LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
#define | LL_PWR_SR2_REGLPS PWR_SR2_REGLPS

Detailed Description

Flags defines which can be used with LL_PWR_ReadReg function.

Define Documentation

#define LL_PWR_SR1_SBF PWR_SR1_SBF

Definition at line 92 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1

Definition at line 97 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2

Definition at line 96 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3

Definition at line 95 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4

Definition at line 94 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5

Definition at line 93 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR1_WUFI PWR_SR1_WUFI

Definition at line 91 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR2_PVDO PWR_SR2_PVDO

Definition at line 104 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1

Definition at line 103 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2

Definition at line 101 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3

Definition at line 99 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4

Definition at line 98 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF

Definition at line 106 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS

Definition at line 107 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_SR2_VOSF PWR_SR2_VOSF

Definition at line 105 of file stm32l4xx_ll_pwr.h.

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STM32L486xx HAL User Manual: REGU VOLTAGE

Defines
REGU VOLTAGE
PWR Exported Constants

Defines

#define | LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
#define | LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)

Define Documentation

#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)

Definition at line 115 of file stm32l4xx_ll_pwr.h.

Referenced by UTILS_SetFlashLatency().

#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)

Definition at line 116 of file stm32l4xx_ll_pwr.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MODE PWR

Defines
MODE PWR
PWR Exported Constants

Defines

#define | LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
#define | LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
#define | LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2)
#define | LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
#define | LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)

Define Documentation

#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)

Definition at line 128 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)

Definition at line 127 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)

Definition at line 124 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)

Definition at line 125 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2)

Definition at line 126 of file stm32l4xx_ll_pwr.h.

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STM32L486xx HAL User Manual: PVM VDDUSB 1

Defines
PVM VDDUSB 1
PWR Exported Constants

Defines

#define | LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */
#define | LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */
#define | LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
#define | LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */

Define Documentation

#define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */

Definition at line 142 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */

Definition at line 143 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */

Definition at line 140 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */

Definition at line 137 of file stm32l4xx_ll_pwr.h.

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STM32L486xx HAL User Manual: PVDLEVEL

Defines
PVDLEVEL
PWR Exported Constants

Defines

#define | LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
#define | LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
#define | LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
#define | LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
#define | LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
#define | LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
#define | LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
#define | LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */

Define Documentation

#define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */

Definition at line 151 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */

Definition at line 152 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */

Definition at line 153 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */

Definition at line 154 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */

Definition at line 155 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */

Definition at line 156 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */

Definition at line 157 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */

Definition at line 158 of file stm32l4xx_ll_pwr.h.

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STM32L486xx HAL User Manual: WAKEUP

Defines
WAKEUP
PWR Exported Constants

Defines

#define | LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
#define | LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
#define | LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
#define | LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
#define | LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)

Define Documentation

#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)

Definition at line 166 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)

Definition at line 167 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)

Definition at line 168 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)

Definition at line 169 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)

Definition at line 170 of file stm32l4xx_ll_pwr.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: BATT CHARG RESISTOR

Defines
BATT CHARG RESISTOR
PWR Exported Constants

Defines

#define | LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
#define | LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)

Define Documentation

#define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)

Definition at line 178 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)

Definition at line 179 of file stm32l4xx_ll_pwr.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO

Defines
GPIO
PWR Exported Constants

Defines

#define | LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
#define | LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
#define | LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
#define | LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
#define | LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
#define | LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
#define | LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
#define | LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))

Define Documentation

#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))

Definition at line 187 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))

Definition at line 188 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))

Definition at line 189 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))

Definition at line 190 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))

Definition at line 191 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))

Definition at line 193 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))

Definition at line 196 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))

Definition at line 198 of file stm32l4xx_ll_pwr.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO BIT

Defines
GPIO BIT
PWR Exported Constants

Defines

#define | LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
#define | LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
#define | LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
#define | LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
#define | LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
#define | LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
#define | LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
#define | LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
#define | LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
#define | LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
#define | LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
#define | LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
#define | LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
#define | LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
#define | LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
#define | LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)

Define Documentation

#define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)

Definition at line 206 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)

Definition at line 207 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)

Definition at line 216 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)

Definition at line 217 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)

Definition at line 218 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)

Definition at line 219 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)

Definition at line 220 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)

Definition at line 221 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)

Definition at line 208 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)

Definition at line 209 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)

Definition at line 210 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)

Definition at line 211 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)

Definition at line 212 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)

Definition at line 213 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)

Definition at line 214 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)

Definition at line 215 of file stm32l4xx_ll_pwr.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
PWR Exported Macros

Defines

#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Define Documentation

#define LL_PWR_ReadReg ( __REG__ ) READ_REG(PWR->__REG__)

Read a value in PWR register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 252 of file stm32l4xx_ll_pwr.h.

#define LL_PWR_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(PWR->__REG__, (__VALUE__))

Write a value in PWR register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 245 of file stm32l4xx_ll_pwr.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration

Functions
Configuration
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_EnableLowPowerRunMode (void)
Switch the regulator from main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_DisableLowPowerRunMode (void)
Switch the regulator from low-power mode to main mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledLowPowerRunMode (void)
Check if the regulator is in low-power mode.
__STATIC_INLINE void | LL_PWR_EnterLowPowerRunMode (void)
Switch from run main mode to run low-power mode.
__STATIC_INLINE void | LL_PWR_ExitLowPowerRunMode (void)
Switch from run main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_SetRegulVoltageScaling (uint32_t VoltageScaling)
Set the main internal regulator output voltage.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulVoltageScaling (void)
Get the main internal regulator output voltage.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t LowPowerMode)
Set Low-Power mode.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Low-Power mode.
__STATIC_INLINE void | LL_PWR_EnableVddUSB (void)
Enable VDDUSB supply.
__STATIC_INLINE void | LL_PWR_DisableVddUSB (void)
Disable VDDUSB supply.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledVddUSB (void)
Check if VDDUSB supply is enabled.
__STATIC_INLINE void | LL_PWR_EnableVddIO2 (void)
Enable VDDIO2 supply.
__STATIC_INLINE void | LL_PWR_DisableVddIO2 (void)
Disable VDDIO2 supply.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledVddIO2 (void)
Check if VDDIO2 supply is enabled.
__STATIC_INLINE void | LL_PWR_EnablePVM (uint32_t PeriphVoltage)
Enable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE void | LL_PWR_DisablePVM (uint32_t PeriphVoltage)
Disable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVM (uint32_t PeriphVoltage)
Check if Power Voltage Monitoring is enabled on a peripheral.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableInternWU (void)
Enable Internal Wake-up line.
__STATIC_INLINE void | LL_PWR_DisableInternWU (void)
Disable Internal Wake-up line.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledInternWU (void)
Check if Internal Wake-up line is enabled.
__STATIC_INLINE void | LL_PWR_EnablePUPDCfg (void)
Enable pull-up and pull-down configuration.
__STATIC_INLINE void | LL_PWR_DisablePUPDCfg (void)
Disable pull-up and pull-down configuration.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPUPDCfg (void)
Check if pull-up and pull-down configuration is enabled.
__STATIC_INLINE void | LL_PWR_EnableSRAM2Retention (void)
Enable SRAM2 content retention in Standby mode.
__STATIC_INLINE void | LL_PWR_DisableSRAM2Retention (void)
Disable SRAM2 content retention in Standby mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSRAM2Retention (void)
Check if SRAM2 content retention in Standby mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_PWR_SetBattChargResistor (uint32_t Resistor)
Set the resistor impedance.
__STATIC_INLINE uint32_t | LL_PWR_GetBattChargResistor (void)
Get the resistor impedance.
__STATIC_INLINE void | LL_PWR_EnableBatteryCharging (void)
Enable battery charging.
__STATIC_INLINE void | LL_PWR_DisableBatteryCharging (void)
Disable battery charging.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBatteryCharging (void)
Check if battery charging is enabled.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityLow (uint32_t WakeUpPin)
Set the Wake-Up pin polarity low for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityHigh (uint32_t WakeUpPin)
Set the Wake-Up pin polarity high for the event detection.
__STATIC_INLINE uint32_t | LL_PWR_IsWakeUpPinPolarityLow (uint32_t WakeUpPin)
Get the Wake-Up pin polarity for the event detection.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-up state is enabled.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-down state is enabled.

Function Documentation

__STATIC_INLINE void LL_PWR_DisableBatteryCharging ( void )

Disable battery charging.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_DisableBatteryCharging
Return values:
None

Definition at line 792 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_DisableBkUpAccess
Return values:
None

Definition at line 361 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-down state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_DisableGPIOPullDown
PDCRB PD0-15 LL_PWR_DisableGPIOPullDown
PDCRC PD0-15 LL_PWR_DisableGPIOPullDown
PDCRD PD0-15 LL_PWR_DisableGPIOPullDown
PDCRE PD0-15 LL_PWR_DisableGPIOPullDown
PDCRF PD0-15 LL_PWR_DisableGPIOPullDown
PDCRG PD0-15 LL_PWR_DisableGPIOPullDown
PDCRH PD0-1 LL_PWR_DisableGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F (*)
  • LL_PWR_GPIO_G (*)
  • LL_PWR_GPIO_H
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1088 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-up state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_DisableGPIOPullUp
PUCRB PU0-15 LL_PWR_DisableGPIOPullUp
PUCRC PU0-15 LL_PWR_DisableGPIOPullUp
PUCRD PU0-15 LL_PWR_DisableGPIOPullUp
PUCRE PU0-15 LL_PWR_DisableGPIOPullUp
PUCRF PU0-15 LL_PWR_DisableGPIOPullUp
PUCRG PU0-15 LL_PWR_DisableGPIOPullUp
PUCRH PU0-1 LL_PWR_DisableGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F (*)
  • LL_PWR_GPIO_G (*)
  • LL_PWR_GPIO_H
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 952 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableInternWU ( void )

Disable Internal Wake-up line.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_DisableInternWU
Return values:
None

Definition at line 617 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode ( void )

Switch the regulator from low-power mode to main mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_DisableLowPowerRunMode
Return values:
None

Definition at line 286 of file stm32l4xx_ll_pwr.h.

Referenced by LL_PWR_ExitLowPowerRunMode().

__STATIC_INLINE void LL_PWR_DisablePUPDCfg ( void )

Disable pull-up and pull-down configuration.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_DisablePUPDCfg
Return values:
None

Definition at line 647 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVD ( void )

Disable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_DisablePVD
Return values:
None

Definition at line 587 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVM ( uint32_t PeriphVoltage )

Disable the Power Voltage Monitoring on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVME1 LL_PWR_DisablePVM
CR2 PVME2 LL_PWR_DisablePVM
CR2 PVME3 LL_PWR_DisablePVM
CR2 PVME4 LL_PWR_DisablePVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_VDDUSB_1_2V (*)
  • LL_PWR_PVM_VDDIO2_0_9V (*)
  • LL_PWR_PVM_VDDA_1_62V
  • LL_PWR_PVM_VDDA_2_2V
(*) value not defined in all devices
Return values:
None

Definition at line 510 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableSRAM2Retention ( void )

Disable SRAM2 content retention in Standby mode.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_DisableSRAM2Retention
Return values:
None

Definition at line 677 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableVddIO2 ( void )

Disable VDDIO2 supply.

Reference Manual to LL API cross reference:
CR2 IOSV LL_PWR_DisableVddIO2
Return values:
None

Definition at line 459 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableVddUSB ( void )

Disable VDDUSB supply.

Reference Manual to LL API cross reference:
CR2 USV LL_PWR_DisableVddUSB
Return values:
None

Definition at line 425 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_DisableWakeUpPin
CR3 EWUP2 LL_PWR_DisableWakeUpPin
CR3 EWUP3 LL_PWR_DisableWakeUpPin
CR3 EWUP4 LL_PWR_DisableWakeUpPin
CR3 EWUP5 LL_PWR_DisableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
None

Definition at line 727 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBatteryCharging ( void )

Enable battery charging.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_EnableBatteryCharging
Return values:
None

Definition at line 782 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_EnableBkUpAccess
Return values:
None

Definition at line 351 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-down state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_EnableGPIOPullDown
PDCRB PD0-15 LL_PWR_EnableGPIOPullDown
PDCRC PD0-15 LL_PWR_EnableGPIOPullDown
PDCRD PD0-15 LL_PWR_EnableGPIOPullDown
PDCRE PD0-15 LL_PWR_EnableGPIOPullDown
PDCRF PD0-15 LL_PWR_EnableGPIOPullDown
PDCRG PD0-15 LL_PWR_EnableGPIOPullDown
PDCRH PD0-1 LL_PWR_EnableGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F (*)
  • LL_PWR_GPIO_G (*)
  • LL_PWR_GPIO_H
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1042 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-up state in Standby and Shutdown modes.

Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_EnableGPIOPullUp
PUCRB PU0-15 LL_PWR_EnableGPIOPullUp
PUCRC PU0-15 LL_PWR_EnableGPIOPullUp
PUCRD PU0-15 LL_PWR_EnableGPIOPullUp
PUCRE PU0-15 LL_PWR_EnableGPIOPullUp
PUCRF PU0-15 LL_PWR_EnableGPIOPullUp
PUCRG PU0-15 LL_PWR_EnableGPIOPullUp
PUCRH PU0-1 LL_PWR_EnableGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F (*)
  • LL_PWR_GPIO_G (*)
  • LL_PWR_GPIO_H
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 907 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableInternWU ( void )

Enable Internal Wake-up line.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_EnableInternWU
Return values:
None

Definition at line 607 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode ( void )

Switch the regulator from main mode to low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_EnableLowPowerRunMode
Return values:
None

Definition at line 276 of file stm32l4xx_ll_pwr.h.

Referenced by LL_PWR_EnterLowPowerRunMode().

__STATIC_INLINE void LL_PWR_EnablePUPDCfg ( void )

Enable pull-up and pull-down configuration.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_EnablePUPDCfg
Return values:
None

Definition at line 637 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVD ( void )

Enable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_EnablePVD
Return values:
None

Definition at line 577 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVM ( uint32_t PeriphVoltage )

Enable the Power Voltage Monitoring on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVME1 LL_PWR_EnablePVM
CR2 PVME2 LL_PWR_EnablePVM
CR2 PVME3 LL_PWR_EnablePVM
CR2 PVME4 LL_PWR_EnablePVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_VDDUSB_1_2V (*)
  • LL_PWR_PVM_VDDIO2_0_9V (*)
  • LL_PWR_PVM_VDDA_1_62V
  • LL_PWR_PVM_VDDA_2_2V
(*) value not defined in all devices
Return values:
None

Definition at line 490 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableSRAM2Retention ( void )

Enable SRAM2 content retention in Standby mode.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_EnableSRAM2Retention
Return values:
None

Definition at line 667 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableVddIO2 ( void )

Enable VDDIO2 supply.

Reference Manual to LL API cross reference:
CR2 IOSV LL_PWR_EnableVddIO2
Return values:
None

Definition at line 449 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableVddUSB ( void )

Enable VDDUSB supply.

Reference Manual to LL API cross reference:
CR2 USV LL_PWR_EnableVddUSB
Return values:
None

Definition at line 413 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableWakeUpPin ( uint32_t WakeUpPin )

Enable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_EnableWakeUpPin
CR3 EWUP2 LL_PWR_EnableWakeUpPin
CR3 EWUP3 LL_PWR_EnableWakeUpPin
CR3 EWUP4 LL_PWR_EnableWakeUpPin
CR3 EWUP5 LL_PWR_EnableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
None

Definition at line 707 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode ( void )

Switch from run main mode to run low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_EnterLowPowerRunMode
Return values:
None

Definition at line 306 of file stm32l4xx_ll_pwr.h.

References LL_PWR_EnableLowPowerRunMode().

__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode ( void )

Switch from run main mode to low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_ExitLowPowerRunMode
Return values:
None

Definition at line 316 of file stm32l4xx_ll_pwr.h.

References LL_PWR_DisableLowPowerRunMode().

__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor ( void )

Get the resistor impedance.

Reference Manual to LL API cross reference:
CR4 VBRS LL_PWR_GetBattChargResistor
Return values:
Returned value can be one of the following values:
  • LL_PWR_BATT_CHARG_RESISTOR_5K
  • LL_PWR_BATT_CHARGRESISTOR_1_5K

Definition at line 772 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPowerMode ( void )

Get Low-Power mode.

Reference Manual to LL API cross reference:
CR1 LPMS LL_PWR_GetPowerMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_MODE_STOP0
  • LL_PWR_MODE_STOP1
  • LL_PWR_MODE_STOP2
  • LL_PWR_MODE_STANDBY
  • LL_PWR_MODE_SHUTDOWN

Definition at line 402 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel ( void )

Get the voltage threshold detection.

Reference Manual to LL API cross reference:
CR2 PLS LL_PWR_GetPVDLevel
Return values:
Returned value can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7

Definition at line 567 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling ( void )

Get the main internal regulator output voltage.

Reference Manual to LL API cross reference:
CR1 VOS LL_PWR_GetRegulVoltageScaling
Return values:
Returned value can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SCALE1
  • LL_PWR_REGU_VOLTAGE_SCALE2

Definition at line 341 of file stm32l4xx_ll_pwr.h.

Referenced by UTILS_SetFlashLatency().

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging ( void )

Check if battery charging is enabled.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_IsEnabledBatteryCharging
Return values:
State of bit (1 or 0).

Definition at line 802 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess ( void )

Check if the backup domain is enabled.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_IsEnabledBkUpAccess
Return values:
State of bit (1 or 0).

Definition at line 371 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Check if GPIO pull-down state is enabled.

Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRH PD0-1 LL_PWR_IsEnabledGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F (*)
  • LL_PWR_GPIO_G (*)
  • LL_PWR_GPIO_H
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
State of bit (1 or 0).

Definition at line 1134 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Check if GPIO pull-up state is enabled.

Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRH PU0-1 LL_PWR_IsEnabledGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_F (*)
  • LL_PWR_GPIO_G (*)
  • LL_PWR_GPIO_H
(*) value not defined in all devices
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
State of bit (1 or 0).

Definition at line 997 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU ( void )

Check if Internal Wake-up line is enabled.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_IsEnabledInternWU
Return values:
State of bit (1 or 0).

Definition at line 627 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode ( void )

Check if the regulator is in low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
Return values:
State of bit (1 or 0).

Definition at line 296 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg ( void )

Check if pull-up and pull-down configuration is enabled.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_IsEnabledPUPDCfg
Return values:
State of bit (1 or 0).

Definition at line 657 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD ( void )

Check if Power Voltage Detector is enabled.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_IsEnabledPVD
Return values:
State of bit (1 or 0).

Definition at line 597 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM ( uint32_t PeriphVoltage )

Check if Power Voltage Monitoring is enabled on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVME1 LL_PWR_IsEnabledPVM
CR2 PVME2 LL_PWR_IsEnabledPVM
CR2 PVME3 LL_PWR_IsEnabledPVM
CR2 PVME4 LL_PWR_IsEnabledPVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_VDDUSB_1_2V (*)
  • LL_PWR_PVM_VDDIO2_0_9V (*)
  • LL_PWR_PVM_VDDA_1_62V
  • LL_PWR_PVM_VDDA_2_2V
(*) value not defined in all devices
Return values:
State of bit (1 or 0).

Definition at line 530 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention ( void )

Check if SRAM2 content retention in Standby mode is enabled.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_IsEnabledSRAM2Retention
Return values:
State of bit (1 or 0).

Definition at line 687 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2 ( void )

Check if VDDIO2 supply is enabled.

Reference Manual to LL API cross reference:
CR2 IOSV LL_PWR_IsEnabledVddIO2
Return values:
State of bit (1 or 0).

Definition at line 469 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB ( void )

Check if VDDUSB supply is enabled.

Reference Manual to LL API cross reference:
CR2 USV LL_PWR_IsEnabledVddUSB
Return values:
State of bit (1 or 0).

Definition at line 437 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin ( uint32_t WakeUpPin )

Check if the WakeUp PINx functionality is enabled.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
State of bit (1 or 0).

Definition at line 747 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow ( uint32_t WakeUpPin )

Get the Wake-Up pin polarity for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
State of bit (1 or 0).

Definition at line 862 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetBattChargResistor ( uint32_t Resistor )

Set the resistor impedance.

Reference Manual to LL API cross reference:
CR4 VBRS LL_PWR_SetBattChargResistor
Parameters:
Resistor This parameter can be one of the following values:
  • LL_PWR_BATT_CHARG_RESISTOR_5K
  • LL_PWR_BATT_CHARGRESISTOR_1_5K
Return values:
None

Definition at line 760 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPowerMode ( uint32_t LowPowerMode )

Set Low-Power mode.

Reference Manual to LL API cross reference:
CR1 LPMS LL_PWR_SetPowerMode
Parameters:
LowPowerMode This parameter can be one of the following values:
  • LL_PWR_MODE_STOP0
  • LL_PWR_MODE_STOP1
  • LL_PWR_MODE_STOP2
  • LL_PWR_MODE_STANDBY
  • LL_PWR_MODE_SHUTDOWN
Return values:
None

Definition at line 387 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPVDLevel ( uint32_t PVDLevel )

Configure the voltage threshold detected by the Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PLS LL_PWR_SetPVDLevel
Parameters:
PVDLevel This parameter can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7
Return values:
None

Definition at line 549 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling ( uint32_t VoltageScaling )

Set the main internal regulator output voltage.

Reference Manual to LL API cross reference:
CR1 VOS LL_PWR_SetRegulVoltageScaling
Parameters:
VoltageScaling This parameter can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SCALE1
  • LL_PWR_REGU_VOLTAGE_SCALE2
Return values:
None

Definition at line 329 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh ( uint32_t WakeUpPin )

Set the Wake-Up pin polarity high for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
None

Definition at line 842 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow ( uint32_t WakeUpPin )

Set the Wake-Up pin polarity low for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2
  • LL_PWR_WAKEUP_PIN3
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5
Return values:
None

Definition at line 822 of file stm32l4xx_ll_pwr.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: De-initialization function

Functions
De-initialization function
FLAG_Management | PWR Exported Functions

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Function Documentation

ErrorStatus LL_PWR_DeInit ( void )

De-initialize the PWR registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PWR registers are de-initialized
  • ERROR: not applicable

Definition at line 74 of file stm32l4xx_ll_pwr.c.

References LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_PWR, and LL_APB1_GRP1_ReleaseReset().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG_Management

Modules | Functions
FLAG_Management
PWR Exported Functions

Modules

De-initialization function

Functions

__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_InternWU (void)
Get Internal Wake-up line Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SB (void)
Get Stand-By Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU5 (void)
Get Wake-up Flag 5.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU4 (void)
Get Wake-up Flag 4.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU3 (void)
Get Wake-up Flag 3.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU2 (void)
Get Wake-up Flag 2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU1 (void)
Get Wake-up Flag 1.
__STATIC_INLINE void | LL_PWR_ClearFlag_SB (void)
Clear Stand-By Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU5 (void)
Clear Wake-up Flag 5.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU4 (void)
Clear Wake-up Flag 4.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU3 (void)
Clear Wake-up Flag 3.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU2 (void)
Clear Wake-up Flag 2.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU1 (void)
Clear Wake-up Flag 1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO4 (void)
Indicate whether VDDA voltage is below or above PVM4 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO3 (void)
Indicate whether VDDA voltage is below or above PVM3 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO2 (void)
Indicate whether VDDIO2 voltage is below or above PVM2 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO1 (void)
Indicate whether VDDUSB voltage is below or above PVM1 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below or above the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VOSF (void)
Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPF (void)
Indicate whether the regulator is ready in main mode or is in low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPS (void)
Indicate whether or not the low-power regulator is ready.

Function Documentation

__STATIC_INLINE void LL_PWR_ClearFlag_SB ( void )

Clear Stand-By Flag.

Reference Manual to LL API cross reference:
SCR CSBF LL_PWR_ClearFlag_SB
Return values:
None

Definition at line 1223 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU ( void )

Clear Wake-up Flags.

Reference Manual to LL API cross reference:
SCR CWUF LL_PWR_ClearFlag_WU
Return values:
None

Definition at line 1233 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU1 ( void )

Clear Wake-up Flag 1.

Reference Manual to LL API cross reference:
SCR CWUF1 LL_PWR_ClearFlag_WU1
Return values:
None

Definition at line 1283 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU2 ( void )

Clear Wake-up Flag 2.

Reference Manual to LL API cross reference:
SCR CWUF2 LL_PWR_ClearFlag_WU2
Return values:
None

Definition at line 1273 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU3 ( void )

Clear Wake-up Flag 3.

Reference Manual to LL API cross reference:
SCR CWUF3 LL_PWR_ClearFlag_WU3
Return values:
None

Definition at line 1263 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU4 ( void )

Clear Wake-up Flag 4.

Reference Manual to LL API cross reference:
SCR CWUF4 LL_PWR_ClearFlag_WU4
Return values:
None

Definition at line 1253 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU5 ( void )

Clear Wake-up Flag 5.

Reference Manual to LL API cross reference:
SCR CWUF5 LL_PWR_ClearFlag_WU5
Return values:
None

Definition at line 1243 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU ( void )

Get Internal Wake-up line Flag.

Reference Manual to LL API cross reference:
SR1 WUFI LL_PWR_IsActiveFlag_InternWU
Return values:
State of bit (1 or 0).

Definition at line 1153 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO ( void )

Indicate whether VDD voltage is below or above the selected PVD threshold.

Reference Manual to LL API cross reference:
SR2 PVDO LL_PWR_IsActiveFlag_PVDO
Return values:
State of bit (1 or 0).

Definition at line 1337 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1 ( void )

Indicate whether VDDUSB voltage is below or above PVM1 threshold.

Reference Manual to LL API cross reference:
SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
Return values:
State of bit (1 or 0).

Definition at line 1326 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2 ( void )

Indicate whether VDDIO2 voltage is below or above PVM2 threshold.

Reference Manual to LL API cross reference:
SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
Return values:
State of bit (1 or 0).

Definition at line 1314 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3 ( void )

Indicate whether VDDA voltage is below or above PVM3 threshold.

Reference Manual to LL API cross reference:
SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
Return values:
State of bit (1 or 0).

Definition at line 1303 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4 ( void )

Indicate whether VDDA voltage is below or above PVM4 threshold.

Reference Manual to LL API cross reference:
SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
Return values:
State of bit (1 or 0).

Definition at line 1293 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF ( void )

Indicate whether the regulator is ready in main mode or is in low-power mode.

Note:
: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
Reference Manual to LL API cross reference:
SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
Return values:
State of bit (1 or 0).

Definition at line 1358 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS ( void )

Indicate whether or not the low-power regulator is ready.

Reference Manual to LL API cross reference:
SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
Return values:
State of bit (1 or 0).

Definition at line 1368 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB ( void )

Get Stand-By Flag.

Reference Manual to LL API cross reference:
SR1 SBF LL_PWR_IsActiveFlag_SB
Return values:
State of bit (1 or 0).

Definition at line 1163 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF ( void )

Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.

Reference Manual to LL API cross reference:
SR2 VOSF LL_PWR_IsActiveFlag_VOSF
Return values:
State of bit (1 or 0).

Definition at line 1347 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1 ( void )

Get Wake-up Flag 1.

Reference Manual to LL API cross reference:
SR1 WUF1 LL_PWR_IsActiveFlag_WU1
Return values:
State of bit (1 or 0).

Definition at line 1213 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2 ( void )

Get Wake-up Flag 2.

Reference Manual to LL API cross reference:
SR1 WUF2 LL_PWR_IsActiveFlag_WU2
Return values:
State of bit (1 or 0).

Definition at line 1203 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3 ( void )

Get Wake-up Flag 3.

Reference Manual to LL API cross reference:
SR1 WUF3 LL_PWR_IsActiveFlag_WU3
Return values:
State of bit (1 or 0).

Definition at line 1193 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4 ( void )

Get Wake-up Flag 4.

Reference Manual to LL API cross reference:
SR1 WUF4 LL_PWR_IsActiveFlag_WU4
Return values:
State of bit (1 or 0).

Definition at line 1183 of file stm32l4xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5 ( void )

Get Wake-up Flag 5.

Reference Manual to LL API cross reference:
SR1 WUF5 LL_PWR_IsActiveFlag_WU5
Return values:
State of bit (1 or 0).

Definition at line 1173 of file stm32l4xx_ll_pwr.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC

Modules
RCC
STM32L4xx_LL_Driver

Modules

RCC Private functions
RCC Private Variables
RCC Private Constants
RCC Private Macros
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for RCC registers.

Register | Bit | Function
BDCR | BDRST | LL_RCC_ForceBackupDomainReset
 |  | LL_RCC_ReleaseBackupDomainReset
 | LSCOEN | LL_RCC_LSCO_Disable
 |  | LL_RCC_LSCO_Enable
 | LSCOSEL | LL_RCC_LSCO_GetSource
 |  | LL_RCC_LSCO_SetSource
 | LSEBYP | LL_RCC_LSE_DisableBypass
 |  | LL_RCC_LSE_EnableBypass
 | LSECSSD | LL_RCC_LSE_IsCSSDetected
 | LSECSSON | LL_RCC_LSE_DisableCSS
 |  | LL_RCC_LSE_EnableCSS
 | LSEDRV | LL_RCC_LSE_GetDriveCapability
 |  | LL_RCC_LSE_SetDriveCapability
 | LSEON | LL_RCC_LSE_Disable
 |  | LL_RCC_LSE_Enable
 | LSERDY | LL_RCC_LSE_IsReady
 | RTCEN | LL_RCC_DisableRTC
 |  | LL_RCC_EnableRTC
 |  | LL_RCC_IsEnabledRTC
 | RTCSEL | LL_RCC_GetRTCClockSource
 |  | LL_RCC_SetRTCClockSource
CCIPR | ADCSEL | LL_RCC_GetADCClockSource
 |  | LL_RCC_SetADCClockSource
 | CLK48SEL | LL_RCC_GetRNGClockSource
 |  | LL_RCC_GetSDMMCClockSource
 |  | LL_RCC_GetUSBClockSource
 |  | LL_RCC_SetRNGClockSource
 |  | LL_RCC_SetSDMMCClockSource
 |  | LL_RCC_SetUSBClockSource
 | DFSDM1SEL | LL_RCC_GetDFSDMClockSource
 |  | LL_RCC_SetDFSDMClockSource
 | I2CxSEL | LL_RCC_GetI2CClockSource
 |  | LL_RCC_SetI2CClockSource
 | LPTIMxSEL | LL_RCC_GetLPTIMClockSource
 |  | LL_RCC_SetLPTIMClockSource
 | LPUART1SEL | LL_RCC_GetLPUARTClockSource
 |  | LL_RCC_SetLPUARTClockSource
 | SAIxSEL | LL_RCC_GetSAIClockSource
 |  | LL_RCC_SetSAIClockSource
 | SWPMI1SEL | LL_RCC_GetSWPMIClockSource
 |  | LL_RCC_SetSWPMIClockSource
 | UARTxSEL | LL_RCC_GetUARTClockSource
 |  | LL_RCC_SetUARTClockSource
 | USARTxSEL | LL_RCC_GetUSARTClockSource
 |  | LL_RCC_SetUSARTClockSource
CFGR | HPRE | LL_RCC_GetAHBPrescaler
 |  | LL_RCC_SetAHBPrescaler
 | MCOPRE | LL_RCC_ConfigMCO
 | MCOSEL | LL_RCC_ConfigMCO
 | PPRE1 | LL_RCC_GetAPB1Prescaler
 |  | LL_RCC_SetAPB1Prescaler
 | PPRE2 | LL_RCC_GetAPB2Prescaler
 |  | LL_RCC_SetAPB2Prescaler
 | STOPWUCK | LL_RCC_GetClkAfterWakeFromStop
 |  | LL_RCC_SetClkAfterWakeFromStop
 | SW | LL_RCC_SetSysClkSource
 | SWS | LL_RCC_GetSysClkSource
CICR | CSSC | LL_RCC_ClearFlag_HSECSS
 | HSERDYC | LL_RCC_ClearFlag_HSERDY
 | HSIRDYC | LL_RCC_ClearFlag_HSIRDY
 | LSECSSC | LL_RCC_ClearFlag_LSECSS
 | LSERDYC | LL_RCC_ClearFlag_LSERDY
 | LSIRDYC | LL_RCC_ClearFlag_LSIRDY
 | MSIRDYC | LL_RCC_ClearFlag_MSIRDY
 | PLLRDYC | LL_RCC_ClearFlag_PLLRDY
 | PLLSAI1RDYC | LL_RCC_ClearFlag_PLLSAI1RDY
 | PLLSAI2RDYC | LL_RCC_ClearFlag_PLLSAI2RDY
CIER | HSERDYIE | LL_RCC_DisableIT_HSERDY
 |  | LL_RCC_EnableIT_HSERDY
 |  | LL_RCC_IsEnabledIT_HSERDY
 | HSIRDYIE | LL_RCC_DisableIT_HSIRDY
 |  | LL_RCC_EnableIT_HSIRDY
 |  | LL_RCC_IsEnabledIT_HSIRDY
 | LSECSSIE | LL_RCC_DisableIT_LSECSS
 |  | LL_RCC_EnableIT_LSECSS
 |  | LL_RCC_IsEnabledIT_LSECSS
 | LSERDYIE | LL_RCC_DisableIT_LSERDY
 |  | LL_RCC_EnableIT_LSERDY
 |  | LL_RCC_IsEnabledIT_LSERDY
 | LSIRDYIE | LL_RCC_DisableIT_LSIRDY
 |  | LL_RCC_EnableIT_LSIRDY
 |  | LL_RCC_IsEnabledIT_LSIRDY
 | MSIRDYIE | LL_RCC_DisableIT_MSIRDY
 |  | LL_RCC_EnableIT_MSIRDY
 |  | LL_RCC_IsEnabledIT_MSIRDY
 | PLLRDYIE | LL_RCC_DisableIT_PLLRDY
 |  | LL_RCC_EnableIT_PLLRDY
 |  | LL_RCC_IsEnabledIT_PLLRDY
 | PLLSAI1RDYIE | LL_RCC_DisableIT_PLLSAI1RDY
 |  | LL_RCC_EnableIT_PLLSAI1RDY
 |  | LL_RCC_IsEnabledIT_PLLSAI1RDY
 | PLLSAI2RDYIE | LL_RCC_DisableIT_PLLSAI2RDY
 |  | LL_RCC_EnableIT_PLLSAI2RDY
 |  | LL_RCC_IsEnabledIT_PLLSAI2RDY
CIFR | CSSF | LL_RCC_IsActiveFlag_HSECSS
 | HSERDYF | LL_RCC_IsActiveFlag_HSERDY
 | HSIRDYF | LL_RCC_IsActiveFlag_HSIRDY
 | LSECSSF | LL_RCC_IsActiveFlag_LSECSS
 | LSERDYF | LL_RCC_IsActiveFlag_LSERDY
 | LSIRDYF | LL_RCC_IsActiveFlag_LSIRDY
 | MSIRDYF | LL_RCC_IsActiveFlag_MSIRDY
 | PLLRDYF | LL_RCC_IsActiveFlag_PLLRDY
 | PLLSAI1RDYF | LL_RCC_IsActiveFlag_PLLSAI1RDY
 | PLLSAI2RDYF | LL_RCC_IsActiveFlag_PLLSAI2RDY
CR | CSSON | LL_RCC_HSE_EnableCSS
 | HSEBYP | LL_RCC_HSE_DisableBypass
 |  | LL_RCC_HSE_EnableBypass
 | HSEON | LL_RCC_HSE_Disable
 |  | LL_RCC_HSE_Enable
 | HSERDY | LL_RCC_HSE_IsReady
 | HSIASFS | LL_RCC_HSI_DisableAutoFromStop
 |  | LL_RCC_HSI_EnableAutoFromStop
 | HSIKERON | LL_RCC_HSI_DisableInStopMode
 |  | LL_RCC_HSI_EnableInStopMode
 | HSION | LL_RCC_HSI_Disable
 |  | LL_RCC_HSI_Enable
 | HSIRDY | LL_RCC_HSI_IsReady
 | MSION | LL_RCC_MSI_Disable
 |  | LL_RCC_MSI_Enable
 | MSIPLLEN | LL_RCC_MSI_DisablePLLMode
 |  | LL_RCC_MSI_EnablePLLMode
 | MSIRANGE | LL_RCC_MSI_GetRange
 |  | LL_RCC_MSI_SetRange
 | MSIRDY | LL_RCC_MSI_IsReady
 | MSIRGSEL | LL_RCC_MSI_EnableRangeSelection
 |  | LL_RCC_MSI_IsEnabledRangeSelect
 | PLLON | LL_RCC_PLL_Disable
 |  | LL_RCC_PLL_Enable
 | PLLRDY | LL_RCC_PLL_IsReady
 | PLLSAI1ON | LL_RCC_PLLSAI1_Disable
 |  | LL_RCC_PLLSAI1_Enable
 | PLLSAI1RDY | LL_RCC_PLLSAI1_IsReady
 | PLLSAI2ON | LL_RCC_PLLSAI2_Disable
 |  | LL_RCC_PLLSAI2_Enable
 | PLLSAI2RDY | LL_RCC_PLLSAI2_IsReady
CSR | BORRSTF | LL_RCC_IsActiveFlag_BORRST
 | FWRSTF | LL_RCC_IsActiveFlag_FWRST
 | IWDGRSTF | LL_RCC_IsActiveFlag_IWDGRST
 | LPWRRSTF | LL_RCC_IsActiveFlag_LPWRRST
 | LSION | LL_RCC_LSI_Disable
 |  | LL_RCC_LSI_Enable
 | LSIRDY | LL_RCC_LSI_IsReady
 | MSISRANGE | LL_RCC_MSI_GetRangeAfterStandby
 |  | LL_RCC_MSI_SetRangeAfterStandby
 | OBLRSTF | LL_RCC_IsActiveFlag_OBLRST
 | PINRSTF | LL_RCC_IsActiveFlag_PINRST
 | RMVF | LL_RCC_ClearResetFlags
 | SFTRSTF | LL_RCC_IsActiveFlag_SFTRST
 | WWDGRSTF | LL_RCC_IsActiveFlag_WWDGRST
ICSCR | HSICAL | LL_RCC_HSI_GetCalibration
 | HSITRIM | LL_RCC_HSI_GetCalibTrimming
 |  | LL_RCC_HSI_SetCalibTrimming
 | MSICAL | LL_RCC_MSI_GetCalibration
 | MSITRIM | LL_RCC_MSI_GetCalibTrimming
 |  | LL_RCC_MSI_SetCalibTrimming
PLLCFGR | PLLM | LL_RCC_PLLSAI1_ConfigDomain_48M
 |  | LL_RCC_PLLSAI1_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI1_ConfigDomain_SAI
 |  | LL_RCC_PLLSAI2_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI2_ConfigDomain_SAI
 |  | LL_RCC_PLL_ConfigDomain_48M
 |  | LL_RCC_PLL_ConfigDomain_SAI
 |  | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetDivider
 | PLLN | LL_RCC_PLL_ConfigDomain_48M
 |  | LL_RCC_PLL_ConfigDomain_SAI
 |  | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetN
 | PLLP | LL_RCC_PLL_ConfigDomain_SAI
 |  | LL_RCC_PLL_GetP
 | PLLPEN | LL_RCC_PLL_DisableDomain_SAI
 |  | LL_RCC_PLL_EnableDomain_SAI
 | PLLQ | LL_RCC_PLL_ConfigDomain_48M
 |  | LL_RCC_PLL_GetQ
 | PLLQEN | LL_RCC_PLL_DisableDomain_48M
 |  | LL_RCC_PLL_EnableDomain_48M
 | PLLR | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetR
 | PLLREN | LL_RCC_PLL_DisableDomain_SYS
 |  | LL_RCC_PLL_EnableDomain_SYS
 | PLLSRC | LL_RCC_PLLSAI1_ConfigDomain_48M
 |  | LL_RCC_PLLSAI1_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI1_ConfigDomain_SAI
 |  | LL_RCC_PLLSAI2_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI2_ConfigDomain_SAI
 |  | LL_RCC_PLL_ConfigDomain_48M
 |  | LL_RCC_PLL_ConfigDomain_SAI
 |  | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetMainSource
PLLSAI1CFGR | PLLSAI1N | LL_RCC_PLLSAI1_ConfigDomain_48M
 |  | LL_RCC_PLLSAI1_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI1_ConfigDomain_SAI
 |  | LL_RCC_PLLSAI1_GetN
 | PLLSAI1P | LL_RCC_PLLSAI1_ConfigDomain_SAI
 |  | LL_RCC_PLLSAI1_GetP
 | PLLSAI1PEN | LL_RCC_PLLSAI1_DisableDomain_SAI
 |  | LL_RCC_PLLSAI1_EnableDomain_SAI
 | PLLSAI1Q | LL_RCC_PLLSAI1_ConfigDomain_48M
 |  | LL_RCC_PLLSAI1_GetQ
 | PLLSAI1QEN | LL_RCC_PLLSAI1_DisableDomain_48M
 |  | LL_RCC_PLLSAI1_EnableDomain_48M
 | PLLSAI1R | LL_RCC_PLLSAI1_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI1_GetR
 | PLLSAI1REN | LL_RCC_PLLSAI1_DisableDomain_ADC
 |  | LL_RCC_PLLSAI1_EnableDomain_ADC
PLLSAI2CFGR | PLLSAI2N | LL_RCC_PLLSAI2_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI2_ConfigDomain_SAI
 |  | LL_RCC_PLLSAI2_GetN
 | PLLSAI2P | LL_RCC_PLLSAI2_ConfigDomain_SAI
 |  | LL_RCC_PLLSAI2_GetP
 | PLLSAI2PEN | LL_RCC_PLLSAI2_DisableDomain_SAI
 |  | LL_RCC_PLLSAI2_EnableDomain_SAI
 | PLLSAI2R | LL_RCC_PLLSAI2_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI2_GetR
 | PLLSAI2REN | LL_RCC_PLLSAI2_DisableDomain_ADC
 |  | LL_RCC_PLLSAI2_EnableDomain_ADC
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Private functions

Functions
RCC Private functions
RCC

Functions

uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock frequency used for system domain.
uint32_t | RCC_PLL_GetFreqDomain_SAI (void)
Return PLL clock frequency used for SAI domain.
uint32_t | RCC_PLL_GetFreqDomain_48M (void)
Return PLL clock frequency used for 48 MHz domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_SAI (void)
Return PLLSAI1 clock frequency used for SAI domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_48M (void)
Return PLLSAI1 clock frequency used for 48Mhz domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_ADC (void)
Return PLLSAI1 clock frequency used for ADC domain.
uint32_t | RCC_PLLSAI2_GetFreqDomain_SAI (void)
Return PLLSAI2 clock frequency used for SAI domain.
uint32_t | RCC_PLLSAI2_GetFreqDomain_ADC (void)
Return PLLSAI2 clock frequency used for ADC domain.

Function Documentation

uint32_t RCC_GetHCLKClockFreq ( uint32_t SYSCLK_Frequency )

Return HCLK clock frequency.

Parameters:
SYSCLK_Frequency SYSCLK clock frequency
Return values:
HCLK clock frequency (in Hz)

Definition at line 1122 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_HCLK_FREQ, and LL_RCC_GetAHBPrescaler().

Referenced by LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSWPMIClockFreq(), LL_RCC_GetSystemClocksFreq(), LL_RCC_GetUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetPCLK1ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK1 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1133 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_PCLK1_FREQ, and LL_RCC_GetAPB1Prescaler().

Referenced by LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSWPMIClockFreq(), LL_RCC_GetSystemClocksFreq(), LL_RCC_GetUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetPCLK2ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK2 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 1144 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_PCLK2_FREQ, and LL_RCC_GetAPB2Prescaler().

Referenced by LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetSystemClockFreq ( void )

Return SYSTEM clock frequency.

Return values:
SYSTEM clock frequency (in Hz)

Definition at line 1080 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_GetSysClkSource(), LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_SYS_CLKSOURCE_STATUS_HSE, LL_RCC_SYS_CLKSOURCE_STATUS_HSI, LL_RCC_SYS_CLKSOURCE_STATUS_MSI, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, and RCC_PLL_GetFreqDomain_SYS().

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSWPMIClockFreq(), LL_RCC_GetSystemClocksFreq(), LL_RCC_GetUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_PLL_GetFreqDomain_48M ( void )

Return PLL clock frequency used for 48 MHz domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1235 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLCLK_48M_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetRNGClockFreq(), LL_RCC_GetSDMMCClockFreq(), and LL_RCC_GetUSBClockFreq().

uint32_t RCC_PLL_GetFreqDomain_SAI ( void )

Return PLL clock frequency used for SAI domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1194 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLCLK_SAI_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetSAIClockFreq().

uint32_t RCC_PLL_GetFreqDomain_SYS ( void )

Return PLL clock frequency used for system domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 1154 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLCLK_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by RCC_GetSystemClockFreq().

uint32_t RCC_PLLSAI1_GetFreqDomain_48M ( void )

Return PLLSAI1 clock frequency used for 48Mhz domain.

Return values:
PLLSAI1 clock frequency (in Hz)

Definition at line 1317 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI1_48M_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetRNGClockFreq(), LL_RCC_GetSDMMCClockFreq(), and LL_RCC_GetUSBClockFreq().

uint32_t RCC_PLLSAI1_GetFreqDomain_ADC ( void )

Return PLLSAI1 clock frequency used for ADC domain.

Return values:
PLLSAI1 clock frequency (in Hz)

Definition at line 1358 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI1_ADC_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetADCClockFreq().

uint32_t RCC_PLLSAI1_GetFreqDomain_SAI ( void )

Return PLLSAI1 clock frequency used for SAI domain.

Return values:
PLLSAI1 clock frequency (in Hz)

Definition at line 1276 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI1_SAI_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetSAIClockFreq().

uint32_t RCC_PLLSAI2_GetFreqDomain_ADC ( void )

Return PLLSAI2 clock frequency used for ADC domain.

Return values:
PLLSAI2 clock frequency (in Hz)

Definition at line 1441 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI2_ADC_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetADCClockFreq().

uint32_t RCC_PLLSAI2_GetFreqDomain_SAI ( void )

Return PLLSAI2 clock frequency used for SAI domain.

Return values:
PLLSAI2 clock frequency (in Hz)

Definition at line 1400 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI2_SAI_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetSAIClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Private Variables

Variables
RCC Private Variables
RCC

Variables

static const uint8_t aRCC_APBAHBPrescTable [8] = {0, 0, 0, 0, 1, 2, 3, 4}

Variable Documentation

const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4} [static]

Definition at line 65 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Private Constants

Defines
RCC Private Constants
RCC

Defines

#define | RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)
#define | RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)
#define | RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)
#define | RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL)
#define | RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM)
#define | RCC_POSITION_MSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL)
#define | RCC_POSITION_MSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM)
#define | RCC_POSITION_PLLN (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLN)
#define | RCC_POSITION_PLLM (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLM)
#define | RCC_POSITION_PLLR (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLR)
#define | RCC_POSITION_PLLP (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLP)
#define | RCC_POSITION_PLLQ (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLQ)
#define | RCC_POSITION_PLLSAI1N (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)
#define | RCC_POSITION_PLLSAI1P (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)
#define | RCC_POSITION_PLLSAI1Q (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)
#define | RCC_POSITION_PLLSAI1R (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)
#define | RCC_POSITION_PLLSAI2N (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)
#define | RCC_POSITION_PLLSAI2P (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)
#define | RCC_POSITION_PLLSAI2R (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)

Define Documentation

#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)

Definition at line 76 of file stm32l4xx_ll_rcc.h.

#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL)

Definition at line 79 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_HSI_GetCalibration().

#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM)

Definition at line 80 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_HSI_GetCalibTrimming(), and LL_RCC_HSI_SetCalibTrimming().

#define RCC_POSITION_MSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL)

Definition at line 81 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_MSI_GetCalibration().

#define RCC_POSITION_MSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM)

Definition at line 82 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_MSI_GetCalibTrimming(), and LL_RCC_MSI_SetCalibTrimming().

#define RCC_POSITION_PLLM (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLM)

Definition at line 87 of file stm32l4xx_ll_rcc.h.

Referenced by UTILS_GetPLLOutputFrequency().

#define RCC_POSITION_PLLN (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLN)

Definition at line 86 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), LL_RCC_PLL_ConfigDomain_48M(), LL_RCC_PLL_ConfigDomain_SAI(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLL_GetN(), and UTILS_GetPLLOutputFrequency().

#define RCC_POSITION_PLLP (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLP)

Definition at line 92 of file stm32l4xx_ll_rcc.h.

#define RCC_POSITION_PLLQ (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLQ)

Definition at line 94 of file stm32l4xx_ll_rcc.h.

#define RCC_POSITION_PLLR (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLR)

Definition at line 88 of file stm32l4xx_ll_rcc.h.

Referenced by UTILS_GetPLLOutputFrequency().

#define RCC_POSITION_PLLSAI1N (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)

Definition at line 95 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), LL_RCC_PLLSAI1_ConfigDomain_48M(), LL_RCC_PLLSAI1_ConfigDomain_ADC(), LL_RCC_PLLSAI1_ConfigDomain_SAI(), and LL_RCC_PLLSAI1_GetN().

#define RCC_POSITION_PLLSAI1P (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)

Definition at line 99 of file stm32l4xx_ll_rcc.h.

#define RCC_POSITION_PLLSAI1Q (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)

Definition at line 101 of file stm32l4xx_ll_rcc.h.

#define RCC_POSITION_PLLSAI1R (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)

Definition at line 102 of file stm32l4xx_ll_rcc.h.

#define RCC_POSITION_PLLSAI2N (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)

Definition at line 104 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), LL_RCC_PLLSAI2_ConfigDomain_ADC(), LL_RCC_PLLSAI2_ConfigDomain_SAI(), and LL_RCC_PLLSAI2_GetN().

#define RCC_POSITION_PLLSAI2P (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)

Definition at line 105 of file stm32l4xx_ll_rcc.h.

#define RCC_POSITION_PLLSAI2R (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)

Definition at line 106 of file stm32l4xx_ll_rcc.h.

#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)

Definition at line 77 of file stm32l4xx_ll_rcc.h.

#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)

Definition at line 78 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_UART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
#define | IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
#define | IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))
#define | IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))

Define Documentation

#define IS_LL_RCC_ADC_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))

Definition at line 114 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq().

#define IS_LL_RCC_DFSDM_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))

Definition at line 118 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetDFSDMClockFreq().

#define IS_LL_RCC_I2C_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))

Definition at line 84 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetI2CClockFreq().

#define IS_LL_RCC_LPTIM_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))

Definition at line 96 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define IS_LL_RCC_LPUART_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))

Definition at line 81 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define IS_LL_RCC_RNG_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))

Definition at line 108 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetRNGClockFreq().

#define IS_LL_RCC_SAI_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))

Definition at line 100 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetSAIClockFreq().

#define IS_LL_RCC_SDMMC_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))

Definition at line 106 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetSDMMCClockFreq().

#define IS_LL_RCC_SWPMI_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))

Definition at line 116 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetSWPMIClockFreq().

#define IS_LL_RCC_UART_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
                                             || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))

Definition at line 73 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetUARTClockFreq().

#define IS_LL_RCC_USART_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))

Definition at line 64 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetUSARTClockFreq().

#define IS_LL_RCC_USB_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))

Definition at line 111 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetUSBClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_RCC_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RCC_ClocksTypeDef Struct Reference
Clocks Frequency Structure

RCC Clocks Frequency Structure. More...

#include <stm32l4xx_ll_rcc.h>

Data Fields

uint32_t | SYSCLK_Frequency
uint32_t | HCLK_Frequency
uint32_t | PCLK1_Frequency
uint32_t | PCLK2_Frequency

Detailed Description

RCC Clocks Frequency Structure.

Definition at line 135 of file stm32l4xx_ll_rcc.h.

Field Documentation

uint32_t LL_RCC_ClocksTypeDef::HCLK_Frequency

HCLK clock frequency

Definition at line 138 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK1_Frequency

PCLK1 clock frequency

Definition at line 139 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK2_Frequency

PCLK2 clock frequency

Definition at line 140 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::SYSCLK_Frequency

SYSCLK clock frequency

Definition at line 137 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_rcc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Oscillator Values adaptation

Defines
Oscillator Values adaptation
RCC Exported Constants

Defines used to adapt values of different oscillators. More...

Defines

#define | HSE_VALUE ((uint32_t)8000000)
#define | HSI_VALUE ((uint32_t)16000000)
#define | LSE_VALUE ((uint32_t)32768)
#define | LSI_VALUE ((uint32_t)32000)

Detailed Description

Defines used to adapt values of different oscillators.

Note:
These values could be modified in the user environment according to HW set-up.

Define Documentation

#define HSE_VALUE ((uint32_t)8000000)

Value of the HSE oscillator in Hz

Definition at line 164 of file stm32l4xx_ll_rcc.h.

#define HSI_VALUE ((uint32_t)16000000)

Value of the HSI oscillator in Hz

Definition at line 168 of file stm32l4xx_ll_rcc.h.

#define LSE_VALUE ((uint32_t)32768)

Value of the LSE oscillator in Hz

Definition at line 172 of file stm32l4xx_ll_rcc.h.

#define LSI_VALUE ((uint32_t)32000)

Value of the LSI oscillator in Hz

Definition at line 176 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_WriteReg function. More...

Defines

#define | LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC
#define | LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
#define | LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC
#define | LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
#define | LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
#define | LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
#define | LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC
#define | LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC
#define | LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
#define | LL_RCC_CICR_CSSC RCC_CICR_CSSC

Detailed Description

Flags defines which can be used with LL_RCC_WriteReg function.

Define Documentation

#define LL_RCC_CICR_CSSC RCC_CICR_CSSC

Clock Security System Interrupt Clear

Definition at line 206 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC

HSE Ready Interrupt Clear

Definition at line 196 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC

HSI Ready Interrupt Clear

Definition at line 195 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC

LSE Clock Security System Interrupt Clear

Definition at line 205 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC

LSE Ready Interrupt Clear

Definition at line 193 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC

LSI Ready Interrupt Clear

Definition at line 192 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC

MSI Ready Interrupt Clear

Definition at line 194 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC

PLL Ready Interrupt Clear

Definition at line 197 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC

PLLSAI1 Ready Interrupt Clear

Definition at line 201 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC

PLLSAI2 Ready Interrupt Clear

Definition at line 203 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_ReadReg function. More...

Defines

#define | LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF
#define | LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
#define | LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF
#define | LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
#define | LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
#define | LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
#define | LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF
#define | LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF
#define | LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
#define | LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
#define | LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF

Detailed Description

Flags defines which can be used with LL_RCC_ReadReg function.

Define Documentation

#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF

Clock Security System Interrupt flag

Definition at line 229 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF

HSE Ready Interrupt flag

Definition at line 219 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF

HSI Ready Interrupt flag

Definition at line 218 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF

LSE Clock Security System Interrupt flag

Definition at line 228 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF

LSE Ready Interrupt flag

Definition at line 216 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF

LSI Ready Interrupt flag

Definition at line 215 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF

MSI Ready Interrupt flag

Definition at line 217 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF

PLL Ready Interrupt flag

Definition at line 220 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF

PLLSAI1 Ready Interrupt flag

Definition at line 224 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF

PLLSAI2 Ready Interrupt flag

Definition at line 226 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF

BOR reset flag

Definition at line 237 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF

Firewall reset flag

Definition at line 230 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF

Independent Watchdog reset flag

Definition at line 235 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF

Low-Power reset flag

Definition at line 231 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF

OBL reset flag

Definition at line 232 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF

PIN reset flag

Definition at line 233 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF

Software Reset flag

Definition at line 234 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF

Window watchdog reset flag

Definition at line 236 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
RCC Exported Constants

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions. More...

Defines

#define | LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE
#define | LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
#define | LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE
#define | LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
#define | LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
#define | LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
#define | LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE
#define | LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE
#define | LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE

Detailed Description

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

Define Documentation

#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE

HSE Ready Interrupt Enable

Definition at line 250 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE

HSI Ready Interrupt Enable

Definition at line 249 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE

LSE CSS Interrupt Enable

Definition at line 259 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE

LSE Ready Interrupt Enable

Definition at line 247 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE

LSI Ready Interrupt Enable

Definition at line 246 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE

MSI Ready Interrupt Enable

Definition at line 248 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE

PLL Ready Interrupt Enable

Definition at line 251 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE

PLLSAI1 Ready Interrupt Enable

Definition at line 255 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE

PLLSAI2 Ready Interrupt Enable

Definition at line 257 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LSE oscillator drive capability

Defines
LSE oscillator drive capability
RCC Exported Constants

Defines

#define | LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
#define | LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Xtal mode higher driving capability

Definition at line 270 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)

Xtal mode lower driving capability

Definition at line 267 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

Xtal mode medium high driving capability

Definition at line 269 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

Xtal mode medium low driving capability

Definition at line 268 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MSI clock ranges

Defines
MSI clock ranges
RCC Exported Constants

Defines

#define | LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0
#define | LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1
#define | LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2
#define | LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3
#define | LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4
#define | LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5
#define | LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6
#define | LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7
#define | LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8
#define | LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9
#define | LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10
#define | LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11

Define Documentation

#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0

MSI = 100 KHz

Definition at line 278 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1

MSI = 200 KHz

Definition at line 279 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10

MSI = 32 MHz

Definition at line 288 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11

MSI = 48 MHz

Definition at line 289 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2

MSI = 400 KHz

Definition at line 280 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3

MSI = 800 KHz

Definition at line 281 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4

MSI = 1 MHz

Definition at line 282 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5

MSI = 2 MHz

Definition at line 283 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6

MSI = 4 MHz

Definition at line 284 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI(), and LL_RCC_DeInit().

#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7

MSI = 8 MHz

Definition at line 285 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8

MSI = 16 MHz

Definition at line 286 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9

MSI = 24 MHz

Definition at line 287 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MSI range after Standby mode

Defines
MSI range after Standby mode
RCC Exported Constants

Defines

#define | LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1
#define | LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2
#define | LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4
#define | LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8

Define Documentation

#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1

MSI = 1 MHz

Definition at line 297 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2

MSI = 2 MHz

Definition at line 298 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4

MSI = 4 MHz

Definition at line 299 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8

MSI = 8 MHz

Definition at line 300 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

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STM32L486xx HAL User Manual: LSCO Selection

Defines
LSCO Selection
RCC Exported Constants

Defines

#define | LL_RCC_LSCO_CLKSOURCE_LSI (uint32_t)0x00000000
#define | LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL

Define Documentation

#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL

LSE selection for low speed clock

Definition at line 309 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_LSCO_CLKSOURCE_LSI (uint32_t)0x00000000

LSI selection for low speed clock

Definition at line 308 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: System clock switch

Defines
System clock switch
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI
#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE

HSE selection as system clock

Definition at line 319 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI

HSI selection as system clock

Definition at line 318 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI

MSI selection as system clock

Definition at line 317 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL

PLL selection as system clock

Definition at line 320 of file stm32l4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

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STM32L486xx HAL User Manual: System clock switch status

Defines
System clock switch status
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 330 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 329 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI

MSI used as system clock

Definition at line 328 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL

PLL used as system clock

Definition at line 331 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB prescaler

Defines
AHB prescaler
RCC Exported Constants

Defines

#define | LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
#define | LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
#define | LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
#define | LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
#define | LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
#define | LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
#define | LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
#define | LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512

Define Documentation

#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1

SYSCLK not divided

Definition at line 339 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128

SYSCLK divided by 128

Definition at line 345 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16

SYSCLK divided by 16

Definition at line 343 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2

SYSCLK divided by 2

Definition at line 340 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256

SYSCLK divided by 256

Definition at line 346 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4

SYSCLK divided by 4

Definition at line 341 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512

SYSCLK divided by 512

Definition at line 347 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64

SYSCLK divided by 64

Definition at line 344 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8

SYSCLK divided by 8

Definition at line 342 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: APB low-speed prescaler (APB1)

Defines
APB low-speed prescaler (APB1)
RCC Exported Constants

Defines

#define | LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
#define | LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
#define | LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
#define | LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16

Define Documentation

#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1

HCLK not divided

Definition at line 355 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16

HCLK divided by 16

Definition at line 359 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2

HCLK divided by 2

Definition at line 356 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4

HCLK divided by 4

Definition at line 357 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8

HCLK divided by 8

Definition at line 358 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB high-speed prescaler (APB2)

Defines
APB high-speed prescaler (APB2)
RCC Exported Constants

Defines

#define | LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
#define | LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
#define | LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
#define | LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16

Define Documentation

#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1

HCLK not divided

Definition at line 366 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16

HCLK divided by 16

Definition at line 370 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2

HCLK divided by 2

Definition at line 367 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4

HCLK divided by 4

Definition at line 368 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8

HCLK divided by 8

Definition at line 369 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: Wakeup from Stop and CSS backup clock selection

Defines
Wakeup from Stop and CSS backup clock selection
RCC Exported Constants

Defines

#define | LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000)
#define | LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK

Define Documentation

#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK

HSI selection after wake-up from STOP

Definition at line 378 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000)

MSI selection after wake-up from STOP

Definition at line 377 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MCO1 SOURCE selection

Defines
MCO1 SOURCE selection
RCC Exported Constants

Defines

#define | LL_RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000)
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1
#define | LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

Define Documentation

#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2

HSE selection as MCO1 source

Definition at line 390 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)

HSI16 selection as MCO1 source

Definition at line 389 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSE selection as MCO1 source

Definition at line 393 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSI selection as MCO1 source

Definition at line 392 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1

MSI selection as MCO1 source

Definition at line 388 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000)

MCO output disabled, no clock on MCO

Definition at line 386 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)

Main PLL selection as MCO1 source

Definition at line 391 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0

SYSCLK selection as MCO1 source

Definition at line 387 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: MCO1 prescaler

Defines
MCO1 prescaler
RCC Exported Constants

Defines

#define | LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1
#define | LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2
#define | LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4
#define | LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8
#define | LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16

Define Documentation

#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1

MCO not divided

Definition at line 404 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16

MCO divided by 16

Definition at line 408 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2

MCO divided by 2

Definition at line 405 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4

MCO divided by 4

Definition at line 406 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8

MCO divided by 8

Definition at line 407 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral clock frequency

Defines
Peripheral clock frequency
RCC Exported Constants

Defines

#define | LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000
#define | LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU

Define Documentation

#define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU

Frequency cannot be provided as external clock

Definition at line 418 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), and LL_RCC_GetUSBClockFreq().

#define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000

No clock enabled for the peripheral

Definition at line 417 of file stm32l4xx_ll_rcc.h.

Referenced by LL_LPUART_Init(), LL_RCC_GetADCClockFreq(), LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetSWPMIClockFreq(), LL_RCC_GetUARTClockFreq(), LL_RCC_GetUSARTClockFreq(), LL_RCC_GetUSBClockFreq(), and LL_USART_Init().

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STM32L486xx HAL User Manual: Peripheral USART clock source selection

Defines
Peripheral USART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16) | 0x00000000)
#define | LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_0)
#define | LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_1)
#define | LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL)
#define | LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16) | 0x00000000)
#define | LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_0)
#define | LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_1)
#define | LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL)
#define | LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART3SEL << 16) | 0x00000000)
#define | LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_0)
#define | LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_1)
#define | LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL)

Define Documentation

#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_1)

HSI clock used as USART1 clock source

Definition at line 429 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL)

LSE clock used as USART1 clock source

Definition at line 430 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16) | 0x00000000)

PCLK2 clock used as USART1 clock source

Definition at line 427 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_0)

SYSCLK clock used as USART1 clock source

Definition at line 428 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_1)

HSI clock used as USART2 clock source

Definition at line 433 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL)

LSE clock used as USART2 clock source

Definition at line 434 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16) | 0x00000000)

PCLK1 clock used as USART2 clock source

Definition at line 431 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_0)

SYSCLK clock used as USART2 clock source

Definition at line 432 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_1)

HSI clock used as USART3 clock source

Definition at line 438 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL)

LSE clock used as USART3 clock source

Definition at line 439 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART3SEL << 16) | 0x00000000)

PCLK1 clock used as USART3 clock source

Definition at line 436 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_0)

SYSCLK clock used as USART3 clock source

Definition at line 437 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

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STM32L486xx HAL User Manual: Peripheral UART clock source selection

Defines
Peripheral UART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART4SEL << 16) | 0x00000000)
#define | LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_0)
#define | LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_1)
#define | LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL)
#define | LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART5SEL << 16) | 0x00000000)
#define | LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_0)
#define | LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_1)
#define | LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL)

Define Documentation

#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_1)

HSI clock used as UART4 clock source

Definition at line 452 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL)

LSE clock used as UART4 clock source

Definition at line 453 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART4SEL << 16) | 0x00000000)

PCLK1 clock used as UART4 clock source

Definition at line 450 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_0)

SYSCLK clock used as UART4 clock source

Definition at line 451 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_1)

HSI clock used as UART5 clock source

Definition at line 458 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL)

LSE clock used as UART5 clock source

Definition at line 459 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART5SEL << 16) | 0x00000000)

PCLK1 clock used as UART5 clock source

Definition at line 456 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_0)

SYSCLK clock used as UART5 clock source

Definition at line 457 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral LPUART clock source selection

Defines
Peripheral LPUART clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000
#define | LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL

Define Documentation

#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1

HSI clock used as LPUART1 clock source

Definition at line 471 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL

LSE clock used as LPUART1 clock source

Definition at line 472 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000

PCLK1 clock used as LPUART1 clock source

Definition at line 469 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0

SYSCLK clock used as LPUART1 clock source

Definition at line 470 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral I2C clock source selection

Defines
Peripheral I2C clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000 >> 4))
#define | LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4))
#define | LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4))
#define | LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (0x00000000 >> 4))
#define | LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_0 >> 4))
#define | LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_1 >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000 >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4))

Define Documentation

#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4))

HSI clock used as I2C1 clock source

Definition at line 482 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000 >> 4))

PCLK1 clock used as I2C1 clock source

Definition at line 480 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4))

SYSCLK clock used as I2C1 clock source

Definition at line 481 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_1 >> 4))

HSI clock used as I2C2 clock source

Definition at line 486 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (0x00000000 >> 4))

PCLK1 clock used as I2C2 clock source

Definition at line 484 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_0 >> 4))

SYSCLK clock used as I2C2 clock source

Definition at line 485 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4))

HSI clock used as I2C3 clock source

Definition at line 490 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000 >> 4))

PCLK1 clock used as I2C3 clock source

Definition at line 488 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4))

SYSCLK clock used as I2C3 clock source

Definition at line 489 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral LPTIM clock source selection

Defines
Peripheral LPTIM clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000 >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000 >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16))

Define Documentation

#define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16))

HSI clock used as LPTIM1 clock source

Definition at line 500 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16))

LSE clock used as LPTIM1 clock source

Definition at line 501 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16))

LSI clock used as LPTIM1 clock source

Definition at line 499 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000 >> 16))

PCLK1 clock used as LPTIM1 clock source

Definition at line 498 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16))

HSI clock used as LPTIM2 clock source

Definition at line 504 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16))

LSE clock used as LPTIM2 clock source

Definition at line 505 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16))

LSI clock used as LPTIM2 clock source

Definition at line 503 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000 >> 16))

PCLK1 clock used as LPTIM2 clock source

Definition at line 502 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral SAI clock source selection

Defines
Peripheral SAI clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI1SEL | (0x00000000 >> 16))
#define | LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16))
#define | LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16))
#define | LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16))
#define | LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI2SEL | (0x00000000 >> 16))
#define | LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16))
#define | LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16))
#define | LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16))

Define Documentation

#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16))

External input clock used as SAI1 clock source

Definition at line 518 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16))

PLL clock used as SAI1 clock source

Definition at line 517 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI1SEL | (0x00000000 >> 16))

PLLSAI1 clock used as SAI1 clock source

Definition at line 513 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16))

PLLSAI2 clock used as SAI1 clock source

Definition at line 515 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16))

External input clock used as SAI2 clock source

Definition at line 525 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16))

PLL clock used as SAI2 clock source

Definition at line 524 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI2SEL | (0x00000000 >> 16))

PLLSAI1 clock used as SAI2 clock source

Definition at line 520 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16))

PLLSAI2 clock used as SAI2 clock source

Definition at line 522 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral SDMMC clock source selection

Defines
Peripheral SDMMC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_SDMMC1_CLKSOURCE_NONE (uint32_t)(0x00000000)
#define | LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)
#define | LL_RCC_SDMMC1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)
#define | LL_RCC_SDMMC1_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)

Define Documentation

#define LL_RCC_SDMMC1_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)

MSI clock used as SDMMC1 clock source

Definition at line 537 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSDMMCClockFreq().

#define LL_RCC_SDMMC1_CLKSOURCE_NONE (uint32_t)(0x00000000)

No clock used as SDMMC1 clock source

Definition at line 534 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSDMMCClockFreq().

#define LL_RCC_SDMMC1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)

PLL clock used as SDMMC1 clock source

Definition at line 536 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSDMMCClockFreq().

#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)

PLLSAI1 clock used as SDMMC1 clock source

Definition at line 535 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSDMMCClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral RNG clock source selection

Defines
Peripheral RNG clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RNG_CLKSOURCE_NONE (uint32_t)(0x00000000)
#define | LL_RCC_RNG_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)
#define | LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)
#define | LL_RCC_RNG_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)

Define Documentation

#define LL_RCC_RNG_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)

MSI clock used as RNG clock source

Definition at line 548 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_NONE (uint32_t)(0x00000000)

No clock used as RNG clock source

Definition at line 545 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)

PLL clock used as RNG clock source

Definition at line 547 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)

PLLSAI1 clock used as RNG clock source

Definition at line 546 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral USB clock source selection

Defines
Peripheral USB clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USB_CLKSOURCE_NONE (uint32_t)(0x00000000)
#define | LL_RCC_USB_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)
#define | LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)
#define | LL_RCC_USB_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)

Define Documentation

#define LL_RCC_USB_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)

MSI clock used as USB clock source

Definition at line 560 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_NONE (uint32_t)(0x00000000)

No clock used as USB clock source

Definition at line 557 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)

PLL clock used as USB clock source

Definition at line 559 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)

PLLSAI1 clock used as USB clock source

Definition at line 558 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral ADC clock source selection

Defines
Peripheral ADC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_ADC_CLKSOURCE_NONE (uint32_t)(0x00000000)
#define | LL_RCC_ADC_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_ADCSEL_0)
#define | LL_RCC_ADC_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_ADCSEL_1)
#define | LL_RCC_ADC_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_ADCSEL)

Define Documentation

#define LL_RCC_ADC_CLKSOURCE_NONE (uint32_t)(0x00000000)

No clock used as ADC clock source

Definition at line 570 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_ADCSEL_0)

PLLSAI1 clock used as ADC clock source

Definition at line 571 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_ADCSEL_1)

PLLSAI2 clock used as ADC clock source

Definition at line 573 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_ADCSEL)

SYSCLK clock used as ADC clock source

Definition at line 575 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral SWPMI clock source selection

Defines
Peripheral SWPMI clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_SWPMI1_CLKSOURCE_PCLK (uint32_t)(0x00000000)
#define | LL_RCC_SWPMI1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_SWPMI1SEL)

Define Documentation

#define LL_RCC_SWPMI1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_SWPMI1SEL)

HSI used as SWPMI1 clock source

Definition at line 584 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSWPMIClockFreq().

#define LL_RCC_SWPMI1_CLKSOURCE_PCLK (uint32_t)(0x00000000)

PCLK used as SWPMI1 clock source

Definition at line 583 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSWPMIClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral DFSDM clock source selection

Defines
Peripheral DFSDM clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_DFSDM1_CLKSOURCE_PCLK (uint32_t)(0x00000000)
#define | LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_DFSDM1SEL)

Define Documentation

#define LL_RCC_DFSDM1_CLKSOURCE_PCLK (uint32_t)(0x00000000)

PCLK used as DFSDM1 clock source

Definition at line 593 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDMClockFreq().

#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_DFSDM1SEL)

SYSCLK used as DFSDM1 clock source

Definition at line 594 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDMClockFreq().

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STM32L486xx HAL User Manual: Peripheral USART get clock source

Defines
Peripheral USART get clock source
RCC Exported Constants

Defines

#define | LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL
#define | LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL
#define | LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL

Define Documentation

#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL

USART1 Clock source selection

Definition at line 603 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL

USART2 Clock source selection

Definition at line 604 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL

USART3 Clock source selection

Definition at line 606 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

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STM32L486xx HAL User Manual: Peripheral UART get clock source

Defines
Peripheral UART get clock source
RCC Exported Constants

Defines

#define | LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL
#define | LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL

Define Documentation

#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL

UART4 Clock source selection

Definition at line 617 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq(), and LL_USART_Init().

#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL

UART5 Clock source selection

Definition at line 620 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq(), and LL_USART_Init().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral LPUART get clock source

Defines
Peripheral LPUART get clock source
RCC Exported Constants

Defines

#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL

Define Documentation

#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL

LPUART1 Clock source selection

Definition at line 630 of file stm32l4xx_ll_rcc.h.

Referenced by LL_LPUART_Init().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral I2C get clock source

Defines
Peripheral I2C get clock source
RCC Exported Constants

Defines

#define | LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL
#define | LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL
#define | LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL

Define Documentation

#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL

I2C1 Clock source selection

Definition at line 638 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL

I2C2 Clock source selection

Definition at line 640 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL

I2C3 Clock source selection

Definition at line 642 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

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STM32L486xx HAL User Manual: Peripheral LPTIM get clock source

Defines
Peripheral LPTIM get clock source
RCC Exported Constants

Defines

#define | LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL
#define | LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL

Define Documentation

#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL

LPTIM1 Clock source selection

Definition at line 650 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL

LPTIM2 Clock source selection

Definition at line 651 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

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STM32L486xx HAL User Manual: Peripheral SAI get clock source

Defines
Peripheral SAI get clock source
RCC Exported Constants

Defines

#define | LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL
#define | LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL

Define Documentation

#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL

SAI1 Clock source selection

Definition at line 659 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL

SAI2 Clock source selection

Definition at line 661 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

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STM32L486xx HAL User Manual: Peripheral SDMMC get clock source

Defines
Peripheral SDMMC get clock source
RCC Exported Constants

Defines

#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL

Define Documentation

#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL

SDMMC1 Clock source selection

Definition at line 670 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: Peripheral RNG get clock source

Defines
Peripheral RNG get clock source
RCC Exported Constants

Defines

#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL

Define Documentation

#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL

RNG Clock source selection

Definition at line 678 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: Peripheral USB get clock source

Defines
Peripheral USB get clock source
RCC Exported Constants

Defines

#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL

Define Documentation

#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL

USB Clock source selection

Definition at line 687 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: Peripheral ADC get clock source

Defines
Peripheral ADC get clock source
RCC Exported Constants

Defines

#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL

Define Documentation

#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL

ADC Clock source selection

Definition at line 697 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: Peripheral SWPMI get clock source

Defines
Peripheral SWPMI get clock source
RCC Exported Constants

Defines

#define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL

Define Documentation

#define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL

SWPMI1 Clock source selection

Definition at line 705 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: Peripheral DFSDM get clock source

Defines
Peripheral DFSDM get clock source
RCC Exported Constants

Defines

#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL

Define Documentation

#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL

DFSDM1 Clock source selection

Definition at line 714 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: RTC clock source selection

Defines
RTC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000)
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

Define Documentation

#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

HSE oscillator clock divided by 32 used as RTC clock

Definition at line 726 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0

LSE oscillator clock used as RTC clock

Definition at line 724 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1

LSI oscillator clock used as RTC clock

Definition at line 725 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000)

No clock used as RTC clock

Definition at line 723 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: PLL, PLLSAI1 and PLLSAI2 entry clock source

Defines
PLL, PLLSAI1 and PLLSAI2 entry clock source
RCC Exported Constants

Defines

#define | LL_RCC_PLLSOURCE_NONE (uint32_t)0x00000000
#define | LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI
#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

Define Documentation

#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

HSE clock selected as PLL entry clock source

Definition at line 737 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI

HSI16 clock selected as PLL entry clock source

Definition at line 736 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI

MSI clock selected as PLL entry clock source

Definition at line 735 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

#define LL_RCC_PLLSOURCE_NONE (uint32_t)0x00000000

No clock

Definition at line 734 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: PLL, PLLSAI1 and PLLSAI2 division factor

Defines
PLL, PLLSAI1 and PLLSAI2 division factor
RCC Exported Constants

Defines

#define | LL_RCC_PLLM_DIV_1 ((uint32_t)0x00000000)
#define | LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)
#define | LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1))
#define | LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM)

Define Documentation

#define LL_RCC_PLLM_DIV_1 ((uint32_t)0x00000000)

PLL, PLLSAI1 and PLLSAI2 division factor by 1

Definition at line 745 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)

PLL, PLLSAI1 and PLLSAI2 division factor by 2

Definition at line 746 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)

PLL, PLLSAI1 and PLLSAI2 division factor by 3

Definition at line 747 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0))

PLL, PLLSAI1 and PLLSAI2 division factor by 4

Definition at line 748 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)

PLL, PLLSAI1 and PLLSAI2 division factor by 5

Definition at line 749 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0))

PLL, PLLSAI1 and PLLSAI2 division factor by 6

Definition at line 750 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1))

PLL, PLLSAI1 and PLLSAI2 division factor by 7

Definition at line 751 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM)

PLL, PLLSAI1 and PLLSAI2 division factor by 8

Definition at line 752 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: PLL division factor (PLLR)

Defines
PLL division factor (PLLR)
RCC Exported Constants

Defines

#define | LL_RCC_PLLR_DIV_2 ((uint32_t)0x00000000)
#define | LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)

Define Documentation

#define LL_RCC_PLLR_DIV_2 ((uint32_t)0x00000000)

Main PLL division factor for PLLCLK (system clock) by 2

Definition at line 760 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0)

Main PLL division factor for PLLCLK (system clock) by 4

Definition at line 761 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1)

Main PLL division factor for PLLCLK (system clock) by 6

Definition at line 762 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)

Main PLL division factor for PLLCLK (system clock) by 8

Definition at line 763 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: PLL division factor (PLLP)

Defines
PLL division factor (PLLP)
RCC Exported Constants

Defines

#define | LL_RCC_PLLP_DIV_7 ((uint32_t)0x00000000)
#define | LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP)

Define Documentation

#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP)

Main PLL division factor for PLLP output by 17

Definition at line 804 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_7 ((uint32_t)0x00000000)

Main PLL division factor for PLLP output by 7

Definition at line 803 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: PLL division factor (PLLQ)

Defines
PLL division factor (PLLQ)
RCC Exported Constants

Defines

#define | LL_RCC_PLLQ_DIV_2 ((uint32_t)0x00000000)
#define | LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)

Define Documentation

#define LL_RCC_PLLQ_DIV_2 ((uint32_t)0x00000000)

Main PLL division factor for PLLQ output by 2

Definition at line 813 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0)

Main PLL division factor for PLLQ output by 4

Definition at line 814 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1)

Main PLL division factor for PLLQ output by 6

Definition at line 815 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)

Main PLL division factor for PLLQ output by 8

Definition at line 816 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: PLLSAI1 division factor (PLLSAI1Q)

Defines
PLLSAI1 division factor (PLLSAI1Q)
RCC Exported Constants

Defines

#define | LL_RCC_PLLSAI1Q_DIV_2 ((uint32_t)0x00000000)
#define | LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0)
#define | LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1)
#define | LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q)

Define Documentation

#define LL_RCC_PLLSAI1Q_DIV_2 ((uint32_t)0x00000000)

PLLSAI1 division factor for PLLSAI1Q output by 2

Definition at line 824 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0)

PLLSAI1 division factor for PLLSAI1Q output by 4

Definition at line 825 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1)

PLLSAI1 division factor for PLLSAI1Q output by 6

Definition at line 826 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q)

PLLSAI1 division factor for PLLSAI1Q output by 8

Definition at line 827 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: PLLSAI1 division factor (PLLSAI1P)

Defines
PLLSAI1 division factor (PLLSAI1P)
RCC Exported Constants

Defines

#define | LL_RCC_PLLSAI1P_DIV_7 ((uint32_t)0x00000000)
#define | LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P)

Define Documentation

#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P)

PLLSAI1 division factor for PLLSAI1P output by 17

Definition at line 868 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_7 ((uint32_t)0x00000000)

PLLSAI1 division factor for PLLSAI1P output by 7

Definition at line 867 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: PLLSAI1 division factor (PLLSAI1R)

Defines
PLLSAI1 division factor (PLLSAI1R)
RCC Exported Constants

Defines

#define | LL_RCC_PLLSAI1R_DIV_2 ((uint32_t)0x00000000)
#define | LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0)
#define | LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1)
#define | LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R)

Define Documentation

#define LL_RCC_PLLSAI1R_DIV_2 ((uint32_t)0x00000000)

PLLSAI1 division factor for PLLSAI1R output by 2

Definition at line 877 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0)

PLLSAI1 division factor for PLLSAI1R output by 4

Definition at line 878 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1)

PLLSAI1 division factor for PLLSAI1R output by 6

Definition at line 879 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R)

PLLSAI1 division factor for PLLSAI1R output by 8

Definition at line 880 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: PLLSAI2 division factor (PLLSAI2P)

Defines
PLLSAI2 division factor (PLLSAI2P)
RCC Exported Constants

Defines

#define | LL_RCC_PLLSAI2P_DIV_7 ((uint32_t)0x00000000)
#define | LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P)

Define Documentation

#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P)

PLLSAI2 division factor for PLLSAI2P output by 17

Definition at line 890 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI2P_DIV_7 ((uint32_t)0x00000000)

PLLSAI2 division factor for PLLSAI2P output by 7

Definition at line 889 of file stm32l4xx_ll_rcc.h.

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STM32L486xx HAL User Manual: PLLSAI2 division factor (PLLSAI2R)

Defines
PLLSAI2 division factor (PLLSAI2R)
RCC Exported Constants

Defines

#define | LL_RCC_PLLSAI2R_DIV_2 ((uint32_t)0x00000000)
#define | LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0)
#define | LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1)
#define | LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R)

Define Documentation

#define LL_RCC_PLLSAI2R_DIV_2 ((uint32_t)0x00000000)

PLLSAI2 division factor for PLLSAI2R output by 2

Definition at line 898 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0)

PLLSAI2 division factor for PLLSAI2R output by 4

Definition at line 899 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1)

PLLSAI2 division factor for PLLSAI2R output by 6

Definition at line 900 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R)

PLLSAI2 division factor for PLLSAI2R output by 8

Definition at line 901 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MSI clock range selection

Defines
MSI clock range selection
RCC Exported Constants

Defines

#define | LL_RCC_MSIRANGESEL_STANDBY (uint32_t)0
#define | LL_RCC_MSIRANGESEL_RUN (uint32_t)1

Define Documentation

#define LL_RCC_MSIRANGESEL_RUN (uint32_t)1

MSI Range is provided by MSIRANGE

Definition at line 911 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_MSIRANGESEL_STANDBY (uint32_t)0

MSI Range is provided by MSISRANGE

Definition at line 910 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RCC Exported Macros

Defines

#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.

Define Documentation

#define LL_RCC_ReadReg ( __REG__ ) READ_REG(RCC->__REG__)

Read a value in RCC register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 954 of file stm32l4xx_ll_rcc.h.

#define LL_RCC_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(RCC->__REG__, (__VALUE__))

Write a value in RCC register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 947 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Calculate frequencies

Defines
Calculate frequencies
RCC Exported Macros

Defines

#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)
Helper macro to calculate the PLLCLK frequency on system domain.
#define | __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLCLK frequency used on SAI domain.
#define | __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLCLK frequency used on 48M domain.
#define | __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__)
Helper macro to calculate the PLLSAI1 frequency used for SAI domain.
#define | __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__)
Helper macro to calculate the PLLSAI1 frequency used on 48M domain.
#define | __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__)
Helper macro to calculate the PLLSAI1 frequency used on ADC domain.
#define | __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__)
Helper macro to calculate the PLLSAI2 frequency used for SAI domain.
#define | __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__)
Helper macro to calculate the PLLSAI2 frequency used on ADC domain.
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE])
Helper macro to calculate the HCLK frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2])
Helper macro to calculate the PCLK2 frequency (ABP2)
#define | __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__)
Helper macro to calculate the MSI frequency (in Hz)

Define Documentation

#define __LL_RCC_CALC_HCLK_FREQ | ( | __SYSCLKFREQ__,
 |  | __AHBPRESCALER__
 | ) | ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE])

Helper macro to calculate the HCLK frequency.

Parameters:
__SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
__AHBPRESCALER__ This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
HCLK clock frequency (in Hz)

Definition at line 1279 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

#define __LL_RCC_CALC_MSI_FREQ | ( | __MSISEL__,
 |  | __MSIRANGE__
 | ) |
Value:
(((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
                           (MSIRangeTable[(__MSIRANGE__) >> 8]) : \
                           (MSIRangeTable[(__MSIRANGE__) >> 4]))

Helper macro to calculate the MSI frequency (in Hz)

Note:
: __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect
: if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY, __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby else by LL_RCC_MSI_GetRange ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), (LL_RCC_MSI_IsEnabledRangeSelect()? LL_RCC_MSI_GetRange(): LL_RCC_MSI_GetRangeAfterStandby()))
Parameters:
__MSISEL__ This parameter can be one of the following values:
  • LL_RCC_MSIRANGESEL_STANDBY
  • LL_RCC_MSIRANGESEL_RUN
__MSIRANGE__ This parameter can be one of the following values:
  • LL_RCC_MSIRANGE_0
  • LL_RCC_MSIRANGE_1
  • LL_RCC_MSIRANGE_2
  • LL_RCC_MSIRANGE_3
  • LL_RCC_MSIRANGE_4
  • LL_RCC_MSIRANGE_5
  • LL_RCC_MSIRANGE_6
  • LL_RCC_MSIRANGE_7
  • LL_RCC_MSIRANGE_8
  • LL_RCC_MSIRANGE_9
  • LL_RCC_MSIRANGE_10
  • LL_RCC_MSIRANGE_11
  • LL_RCC_MSISRANGE_4
  • LL_RCC_MSISRANGE_5
  • LL_RCC_MSISRANGE_6
  • LL_RCC_MSISRANGE_7
Return values:
MSI clock frequency (in Hz)

Definition at line 1339 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetUSBClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

#define __LL_RCC_CALC_PCLK1_FREQ | ( | __HCLKFREQ__,
 |  | __APB1PRESCALER__
 | ) | ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])

Helper macro to calculate the PCLK1 frequency (ABP1)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB1PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1292 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

#define __LL_RCC_CALC_PCLK2_FREQ | ( | __HCLKFREQ__,
 |  | __APB2PRESCALER__
 | ) | ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2])

Helper macro to calculate the PCLK2 frequency (ABP2)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB2PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 1305 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

#define __LL_RCC_CALC_PLLCLK_48M_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLQ__
 | ) |
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
                   ((((__PLLQ__) >> RCC_POSITION_PLLQ) + 1) << 1))

Helper macro to calculate the PLLCLK frequency used on 48M domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetQ ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between 8 and 86
__PLLQ__ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 1087 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M().

#define __LL_RCC_CALC_PLLCLK_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLR__
 | ) |
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
                   ((((__PLLR__) >> RCC_POSITION_PLLR ) + 1 ) * 2))

Helper macro to calculate the PLLCLK frequency on system domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetR ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between 8 and 86
__PLLR__ This parameter can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 985 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

#define __LL_RCC_CALC_PLLCLK_SAI_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__
 | ) |
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
                   (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7 : 17))

Helper macro to calculate the PLLCLK frequency used on SAI domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetP ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between 8 and 86
__PLLP__ This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_17
Return values:
PLL clock frequency (in Hz)

Definition at line 1061 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SAI().

#define __LL_RCC_CALC_PLLSAI1_48M_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLSAI1N__,
 |  | __PLLSAI1Q__
 | ) |
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
                   ((((__PLLSAI1Q__) >> RCC_POSITION_PLLSAI1Q) + 1) << 1))

Helper macro to calculate the PLLSAI1 frequency used on 48M domain.

Note:
ex: __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI1_GetN (), LL_RCC_PLLSAI1_GetQ ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLSAI1N__ | Between 8 and 86
__PLLSAI1Q__ This parameter can be one of the following values:
  • LL_RCC_PLLSAI1Q_DIV_2
  • LL_RCC_PLLSAI1Q_DIV_4
  • LL_RCC_PLLSAI1Q_DIV_6
  • LL_RCC_PLLSAI1Q_DIV_8
Return values:
PLLSAI1 clock frequency (in Hz)

Definition at line 1188 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_48M().

#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLSAI1N__,
 |  | __PLLSAI1R__
 | ) |
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
                   ((((__PLLSAI1R__) >> RCC_POSITION_PLLSAI1R ) + 1 ) * 2))

Helper macro to calculate the PLLSAI1 frequency used on ADC domain.

Note:
ex: __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI1_GetN (), LL_RCC_PLLSAI1_GetR ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLSAI1N__ | Between 8 and 86
__PLLSAI1R__ This parameter can be one of the following values:
  • LL_RCC_PLLSAI1R_DIV_2
  • LL_RCC_PLLSAI1R_DIV_4
  • LL_RCC_PLLSAI1R_DIV_6
  • LL_RCC_PLLSAI1R_DIV_8
Return values:
PLLSAI1 clock frequency (in Hz)

Definition at line 1213 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_ADC().

#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLSAI1N__,
 |  | __PLLSAI1P__
 | ) |
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
                   (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7 : 17))

Helper macro to calculate the PLLSAI1 frequency used for SAI domain.

Note:
ex: __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI1_GetN (), LL_RCC_PLLSAI1_GetP ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLSAI1N__ | Between 8 and 86
__PLLSAI1P__ This parameter can be one of the following values:
  • LL_RCC_PLLSAI1P_DIV_7
  • LL_RCC_PLLSAI1P_DIV_17
Return values:
PLLSAI1 clock frequency (in Hz)

Definition at line 1162 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_SAI().

#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLSAI2N__,
 |  | __PLLSAI2R__
 | ) |
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI2N__) / \
                   ((((__PLLSAI2R__) >> RCC_POSITION_PLLSAI2R ) + 1 ) * 2))

Helper macro to calculate the PLLSAI2 frequency used on ADC domain.

Note:
ex: __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI2_GetN (), LL_RCC_PLLSAI2_GetR ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLSAI2N__ | Between 8 and 86
__PLLSAI2R__ This parameter can be one of the following values:
  • LL_RCC_PLLSAI2R_DIV_2
  • LL_RCC_PLLSAI2R_DIV_4
  • LL_RCC_PLLSAI2R_DIV_6
  • LL_RCC_PLLSAI2R_DIV_8
Return values:
PLLSAI2 clock frequency (in Hz)

Definition at line 1261 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI2_GetFreqDomain_ADC().

#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLSAI2N__,
 |  | __PLLSAI2P__
 | ) |
Value:
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI2N__) / \
                   (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7 : 17))

Helper macro to calculate the PLLSAI2 frequency used for SAI domain.

Note:
ex: __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI2_GetN (), LL_RCC_PLLSAI2_GetP ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLSAI2N__ | Between 8 and 86
__PLLSAI2P__ This parameter can be one of the following values:
  • LL_RCC_PLLSAI2P_DIV_7
  • LL_RCC_PLLSAI2P_DIV_17
Return values:
PLLSAI2 clock frequency (in Hz)

Definition at line 1236 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI2_GetFreqDomain_SAI().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HSE

Functions
HSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_HSE_Disable ( void )

Disable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Disable
Return values:
None

Definition at line 1405 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSE_DisableBypass ( void )

Disable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_DisableBypass
Return values:
None

Definition at line 1385 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_HSE_Enable ( void )

Enable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Enable
Return values:
None

Definition at line 1395 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableBypass ( void )

Enable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_EnableBypass
Return values:
None

Definition at line 1375 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableCSS ( void )

Enable the Clock Security System.

Reference Manual to LL API cross reference:
CR CSSON LL_RCC_HSE_EnableCSS
Return values:
None

Definition at line 1365 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady ( void )

Check if HSE oscillator Ready.

Reference Manual to LL API cross reference:
CR HSERDY LL_RCC_HSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1415 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HSI

Functions
HSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI_EnableInStopMode (void)
Enable HSI even in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableInStopMode (void)
Disable HSI in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE void | LL_RCC_HSI_EnableAutoFromStop (void)
Enable HSI Automatic from stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableAutoFromStop (void)
Disable HSI Automatic from stop mode.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI_Disable ( void )

Disable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Disable
Return values:
None

Definition at line 1464 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop ( void )

Disable HSI Automatic from stop mode.

Reference Manual to LL API cross reference:
CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
Return values:
None

Definition at line 1494 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode ( void )

Disable HSI in stop mode.

Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_DisableInStopMode
Return values:
None

Definition at line 1444 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_Enable ( void )

Enable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Enable
Return values:
None

Definition at line 1454 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop ( void )

Enable HSI Automatic from stop mode.

Reference Manual to LL API cross reference:
CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
Return values:
None

Definition at line 1484 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode ( void )

Enable HSI even in stop mode.

Note:
HSI oscillator is forced ON even in Stop mode
Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_EnableInStopMode
Return values:
None

Definition at line 1434 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration ( void )

Get HSI Calibration value.

Note:
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value
Reference Manual to LL API cross reference:
ICSCR HSICAL LL_RCC_HSI_GetCalibration
Return values:
Between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 1505 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_HSICAL.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming ( void )

Get HSI Calibration trimming.

Reference Manual to LL API cross reference:
ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
Return values:
Between Min_Data = 0 and Max_Data = 31

Definition at line 1529 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_HSITRIM.

__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady ( void )

Check if HSI clock is ready.

Reference Manual to LL API cross reference:
CR HSIRDY LL_RCC_HSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1474 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSWPMIClockFreq(), LL_RCC_GetUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming ( uint32_t Value )

Set HSI Calibration trimming.

Note:
user-programmable trimming value that is added to the HSICAL
Default value is 16, which, when added to the HSICAL value, should trim the HSI to 16 MHz +/- 1 %
Reference Manual to LL API cross reference:
ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
Parameters:
Value Between Min_Data = 0 and Max_Data = 31
Return values:
None

Definition at line 1519 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_HSITRIM.

Referenced by LL_RCC_DeInit().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LSE

Functions
LSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void)
Enable Clock security system on LSE.
__STATIC_INLINE void | LL_RCC_LSE_DisableCSS (void)
Disable Clock security system on LSE.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsCSSDetected (void)
Check if CSS on LSE failure Detection.

Function Documentation

__STATIC_INLINE void LL_RCC_LSE_Disable ( void )

Disable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Disable
Return values:
None

Definition at line 1607 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableBypass ( void )

Disable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_DisableBypass
Return values:
None

Definition at line 1627 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableCSS ( void )

Disable Clock security system on LSE.

Note:
Clock security system can be disabled only after a LSE failure detection. In that case it MUST be disabled by software.
Reference Manual to LL API cross reference:
BDCR LSECSSON LL_RCC_LSE_DisableCSS
Return values:
None

Definition at line 1679 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_Enable ( void )

Enable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Enable
Return values:
None

Definition at line 1597 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableBypass ( void )

Enable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_EnableBypass
Return values:
None

Definition at line 1617 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableCSS ( void )

Enable Clock security system on LSE.

Reference Manual to LL API cross reference:
BDCR LSECSSON LL_RCC_LSE_EnableCSS
Return values:
None

Definition at line 1667 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability ( void )

Get LSE oscillator drive capability.

Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
Return values:
Returned value can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH

Definition at line 1657 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected ( void )

Check if CSS on LSE failure Detection.

Reference Manual to LL API cross reference:
BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
Return values:
State of bit (1 or 0).

Definition at line 1699 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady ( void )

Check if LSE oscillator Ready.

Reference Manual to LL API cross reference:
BDCR LSERDY LL_RCC_LSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1689 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetUARTClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability ( uint32_t LSEDrive )

Set LSE oscillator drive capability.

Note:
The oscillator is in Xtal mode when it is not in bypass mode.
Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
Parameters:
LSEDrive This parameter can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH
Return values:
None

Definition at line 1643 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LSI

Functions
LSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_LSI_Disable ( void )

Disable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Disable
Return values:
None

Definition at line 1727 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSI_Enable ( void )

Enable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Enable
Return values:
None

Definition at line 1717 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady ( void )

Check if LSI is Ready.

Reference Manual to LL API cross reference:
CSR LSIRDY LL_RCC_LSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1737 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MSI

Functions
MSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_MSI_Enable (void)
Enable MSI oscillator.
__STATIC_INLINE void | LL_RCC_MSI_Disable (void)
Disable MSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_MSI_IsReady (void)
Check if MSI oscillator Ready.
__STATIC_INLINE void | LL_RCC_MSI_EnablePLLMode (void)
Enable MSI PLL-mode (Hardware auto calibration with LSE)
__STATIC_INLINE void | LL_RCC_MSI_DisablePLLMode (void)
Disable MSI-PLL mode.
__STATIC_INLINE void | LL_RCC_MSI_EnableRangeSelection (void)
Enable MSI clock range selection with MSIRANGE register.
__STATIC_INLINE uint32_t | LL_RCC_MSI_IsEnabledRangeSelect (void)
Check if MSI clock range is selected with MSIRANGE register.
__STATIC_INLINE void | LL_RCC_MSI_SetRange (uint32_t Range)
Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetRange (void)
Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
__STATIC_INLINE void | LL_RCC_MSI_SetRangeAfterStandby (uint32_t Range)
Configure MSI range used after standby.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetRangeAfterStandby (void)
Get MSI range used after standby.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetCalibration (void)
Get MSI Calibration value.
__STATIC_INLINE void | LL_RCC_MSI_SetCalibTrimming (uint32_t Value)
Set MSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetCalibTrimming (void)
Get MSI Calibration trimming.

Function Documentation

__STATIC_INLINE void LL_RCC_MSI_Disable ( void )

Disable MSI oscillator.

Reference Manual to LL API cross reference:
CR MSION LL_RCC_MSI_Disable
Return values:
None

Definition at line 1765 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode ( void )

Disable MSI-PLL mode.

Note:
cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure
Reference Manual to LL API cross reference:
CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
Return values:
None

Definition at line 1801 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_MSI_Enable ( void )

Enable MSI oscillator.

Reference Manual to LL API cross reference:
CR MSION LL_RCC_MSI_Enable
Return values:
None

Definition at line 1755 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI(), and LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode ( void )

Enable MSI PLL-mode (Hardware auto calibration with LSE)

Note:
MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware)
hardware protection to avoid enabling MSIPLLEN if LSE is not ready
Reference Manual to LL API cross reference:
CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
Return values:
None

Definition at line 1789 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection ( void )

Enable MSI clock range selection with MSIRANGE register.

Note:
Write 0 has no effect. After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE
Reference Manual to LL API cross reference:
CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
Return values:
None

Definition at line 1814 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration ( void )

Get MSI Calibration value.

Note:
When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value
Reference Manual to LL API cross reference:
ICSCR MSICAL LL_RCC_MSI_GetCalibration
Return values:
Between Min_Data = 0 and Max_Data = 255

Definition at line 1910 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_MSICAL.

__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming ( void )

Get MSI Calibration trimming.

Reference Manual to LL API cross reference:
ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
Return values:
Between 0 and 255

Definition at line 1932 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_MSITRIM.

__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange ( void )

Get the Internal Multi Speed oscillator (MSI) clock range in run mode.

Reference Manual to LL API cross reference:
CR MSIRANGE LL_RCC_MSI_GetRange
Return values:
Returned value can be one of the following values:
  • LL_RCC_MSIRANGE_0
  • LL_RCC_MSIRANGE_1
  • LL_RCC_MSIRANGE_2
  • LL_RCC_MSIRANGE_3
  • LL_RCC_MSIRANGE_4
  • LL_RCC_MSIRANGE_5
  • LL_RCC_MSIRANGE_6
  • LL_RCC_MSIRANGE_7
  • LL_RCC_MSIRANGE_8
  • LL_RCC_MSIRANGE_9
  • LL_RCC_MSIRANGE_10
  • LL_RCC_MSIRANGE_11

Definition at line 1869 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetUSBClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby ( void )

Get MSI range used after standby.

Reference Manual to LL API cross reference:
CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
Return values:
Returned value can be one of the following values:
  • LL_RCC_MSISRANGE_4
  • LL_RCC_MSISRANGE_5
  • LL_RCC_MSISRANGE_6
  • LL_RCC_MSISRANGE_7

Definition at line 1898 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetUSBClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect ( void )

Check if MSI clock range is selected with MSIRANGE register.

Reference Manual to LL API cross reference:
CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
Return values:
State of bit (1 or 0).

Definition at line 1824 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetUSBClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady ( void )

Check if MSI oscillator Ready.

Reference Manual to LL API cross reference:
CR MSIRDY LL_RCC_MSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1775 of file stm32l4xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI(), LL_RCC_DeInit(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSDMMCClockFreq(), and LL_RCC_GetUSBClockFreq().

__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming ( uint32_t Value )

Set MSI Calibration trimming.

Note:
user-programmable trimming value that is added to the MSICAL
Reference Manual to LL API cross reference:
ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
Parameters:
Value Between Min_Data = 0 and Max_Data = 255
Return values:
None

Definition at line 1922 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_MSITRIM.

Referenced by LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_MSI_SetRange ( uint32_t Range )

Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.

Reference Manual to LL API cross reference:
CR MSIRANGE LL_RCC_MSI_SetRange
Parameters:
Range This parameter can be one of the following values:
  • LL_RCC_MSIRANGE_0
  • LL_RCC_MSIRANGE_1
  • LL_RCC_MSIRANGE_2
  • LL_RCC_MSIRANGE_3
  • LL_RCC_MSIRANGE_4
  • LL_RCC_MSIRANGE_5
  • LL_RCC_MSIRANGE_6
  • LL_RCC_MSIRANGE_7
  • LL_RCC_MSIRANGE_8
  • LL_RCC_MSIRANGE_9
  • LL_RCC_MSIRANGE_10
  • LL_RCC_MSIRANGE_11
Return values:
None

Definition at line 1847 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby ( uint32_t Range )

Configure MSI range used after standby.

Reference Manual to LL API cross reference:
CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
Parameters:
Range This parameter can be one of the following values:
  • LL_RCC_MSISRANGE_4
  • LL_RCC_MSISRANGE_5
  • LL_RCC_MSISRANGE_6
  • LL_RCC_MSISRANGE_7
Return values:
None

Definition at line 1884 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LSCO

Functions
LSCO
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSCO_Enable (void)
Enable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_Disable (void)
Disable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_SetSource (uint32_t Source)
Configure Low speed clock selection.
__STATIC_INLINE uint32_t | LL_RCC_LSCO_GetSource (void)
Get Low speed clock selection.

Function Documentation

__STATIC_INLINE void LL_RCC_LSCO_Disable ( void )

Disable Low speed clock.

Reference Manual to LL API cross reference:
BDCR LSCOEN LL_RCC_LSCO_Disable
Return values:
None

Definition at line 1960 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSCO_Enable ( void )

Enable Low speed clock.

Reference Manual to LL API cross reference:
BDCR LSCOEN LL_RCC_LSCO_Enable
Return values:
None

Definition at line 1950 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource ( void )

Get Low speed clock selection.

Reference Manual to LL API cross reference:
BDCR LSCOSEL LL_RCC_LSCO_GetSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_LSCO_CLKSOURCE_LSI
  • LL_RCC_LSCO_CLKSOURCE_LSE

Definition at line 1985 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSCO_SetSource ( uint32_t Source )

Configure Low speed clock selection.

Reference Manual to LL API cross reference:
BDCR LSCOSEL LL_RCC_LSCO_SetSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_LSCO_CLKSOURCE_LSI
  • LL_RCC_LSCO_CLKSOURCE_LSE
Return values:
None

Definition at line 1973 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: System

Functions
System
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.
__STATIC_INLINE void | LL_RCC_SetClkAfterWakeFromStop (uint32_t Clock)
Set Clock After Wake-Up From Stop mode.
__STATIC_INLINE uint32_t | LL_RCC_GetClkAfterWakeFromStop (void)
Get Clock After Wake-Up From Stop mode.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler ( void )

Get AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_GetAHBPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512

Definition at line 2093 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler ( void )

Get APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE1 LL_RCC_GetAPB1Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16

Definition at line 2108 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler ( void )

Get APB2 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE2 LL_RCC_GetAPB2Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16

Definition at line 2123 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop ( void )

Get Clock After Wake-Up From Stop mode.

Reference Manual to LL API cross reference:
CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
Return values:
Returned value can be one of the following values:
  • LL_RCC_STOP_WAKEUPCLOCK_MSI
  • LL_RCC_STOP_WAKEUPCLOCK_HSI

Definition at line 2149 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource ( void )

Get the system clock source.

Reference Manual to LL API cross reference:
CFGR SWS LL_RCC_GetSysClkSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_STATUS_MSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL

Definition at line 2022 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAHBPrescaler ( uint32_t Prescaler )

Set AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_SetAHBPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
None

Definition at line 2042 of file stm32l4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB1Prescaler ( uint32_t Prescaler )

Set APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE1 LL_RCC_SetAPB1Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
None

Definition at line 2058 of file stm32l4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB2Prescaler ( uint32_t Prescaler )

Set APB2 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE2 LL_RCC_SetAPB2Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
None

Definition at line 2074 of file stm32l4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop ( uint32_t Clock )

Set Clock After Wake-Up From Stop mode.

Reference Manual to LL API cross reference:
CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
Parameters:
Clock This parameter can be one of the following values:
  • LL_RCC_STOP_WAKEUPCLOCK_MSI
  • LL_RCC_STOP_WAKEUPCLOCK_HSI
Return values:
None

Definition at line 2137 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSysClkSource ( uint32_t Source )

Configure the system clock source.

Reference Manual to LL API cross reference:
CFGR SW LL_RCC_SetSysClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_MSI
  • LL_RCC_SYS_CLKSOURCE_HSI
  • LL_RCC_SYS_CLKSOURCE_HSE
  • LL_RCC_SYS_CLKSOURCE_PLL
Return values:
None

Definition at line 2008 of file stm32l4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MCO

Functions
MCO
RCC Exported Functions

Functions

__STATIC_INLINE void LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.

Function Documentation

__STATIC_INLINE void LL_RCC_ConfigMCO | ( | uint32_t | MCOxSource,
 |  | uint32_t | MCOxPrescaler
 | ) |  |

Configure MCOx.

Reference Manual to LL API cross reference:
CFGR MCOSEL LL_RCC_ConfigMCO
CFGR MCOPRE LL_RCC_ConfigMCO
Parameters:
MCOxSource This parameter can be one of the following values:
  • LL_RCC_MCO1SOURCE_NOCLOCK
  • LL_RCC_MCO1SOURCE_SYSCLK
  • LL_RCC_MCO1SOURCE_MSI
  • LL_RCC_MCO1SOURCE_HSI
  • LL_RCC_MCO1SOURCE_HSE
  • LL_RCC_MCO1SOURCE_HSI48 (*)
  • LL_RCC_MCO1SOURCE_PLLCLK
  • LL_RCC_MCO1SOURCE_LSI
  • LL_RCC_MCO1SOURCE_LSE
(*) value not defined in all devices.
MCOxPrescaler This parameter can be one of the following values:
  • LL_RCC_MCO1_DIV_1
  • LL_RCC_MCO1_DIV_2
  • LL_RCC_MCO1_DIV_4
  • LL_RCC_MCO1_DIV_8
  • LL_RCC_MCO1_DIV_16
Return values:
None

Definition at line 2186 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Clock Source

Functions
Peripheral Clock Source
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetUARTClockSource (uint32_t UARTxSource)
Configure UARTx clock source.
__STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t LPUARTxSource)
Configure LPUART1x clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t LPTIMxSource)
Configure LPTIMx clock source.
__STATIC_INLINE void | LL_RCC_SetSAIClockSource (uint32_t SAIxSource)
Configure SAIx clock source.
__STATIC_INLINE void | LL_RCC_SetSDMMCClockSource (uint32_t SDMMCxSource)
Configure SDMMC1 clock source.
__STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t RNGxSource)
Configure RNG clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE void | LL_RCC_SetSWPMIClockSource (uint32_t SWPMIxSource)
Configure SWPMI clock source.
__STATIC_INLINE void | LL_RCC_SetDFSDMClockSource (uint32_t DFSDMxSource)
Configure DFSDM clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t USARTx)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUARTClockSource (uint32_t UARTx)
Get UARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t LPUARTx)
Get LPUARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t I2Cx)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t LPTIMx)
Get LPTIMx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSAIClockSource (uint32_t SAIx)
Get SAIx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSDMMCClockSource (uint32_t SDMMCx)
Get SDMMCx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t RNGx)
Get RNGx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSWPMIClockSource (uint32_t SPWMIx)
Get SWPMIx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetDFSDMClockSource (uint32_t DFSDMx)
Get DFSDMx clock source.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource ( uint32_t ADCx )

Get ADCx clock source.

Reference Manual to LL API cross reference:
CCIPR ADCSEL LL_RCC_GetADCClockSource
Parameters:
ADCx This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE_NONE
  • LL_RCC_ADC_CLKSOURCE_PLLSAI1
  • LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
  • LL_RCC_ADC_CLKSOURCE_SYSCLK
(*) value not defined in all devices.

Definition at line 2619 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource ( uint32_t DFSDMx )

Get DFSDMx clock source.

Reference Manual to LL API cross reference:
CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
Parameters:
DFSDMx This parameter can be one of the following values:
  • LL_RCC_DFSDM1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_DFSDM1_CLKSOURCE_PCLK
  • LL_RCC_DFSDM1_CLKSOURCE_SYSCLK

Definition at line 2648 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetDFSDMClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource ( uint32_t I2Cx )

Get I2Cx clock source.

Reference Manual to LL API cross reference:
CCIPR I2CxSEL LL_RCC_GetI2CClockSource
Parameters:
I2Cx This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE
  • LL_RCC_I2C2_CLKSOURCE (*)
  • LL_RCC_I2C3_CLKSOURCE
(*) value not defined in all devices.
Return values:
Returned value can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE_PCLK1
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK
  • LL_RCC_I2C1_CLKSOURCE_HSI
  • LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
  • LL_RCC_I2C2_CLKSOURCE_HSI (*)
  • LL_RCC_I2C3_CLKSOURCE_PCLK1
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK
  • LL_RCC_I2C3_CLKSOURCE_HSI
(*) value not defined in all devices.

Definition at line 2505 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource ( uint32_t LPTIMx )

Get LPTIMx clock source.

Reference Manual to LL API cross reference:
CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
Parameters:
LPTIMx This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE
  • LL_RCC_LPTIM2_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_HSI
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM2_CLKSOURCE_LSI
  • LL_RCC_LPTIM2_CLKSOURCE_HSI
  • LL_RCC_LPTIM2_CLKSOURCE_LSE

Definition at line 2526 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPTIMClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource ( uint32_t LPUARTx )

Get LPUARTx clock source.

Reference Manual to LL API cross reference:
CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
Parameters:
LPUARTx This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK
  • LL_RCC_LPUART1_CLKSOURCE_HSI
  • LL_RCC_LPUART1_CLKSOURCE_LSE

Definition at line 2478 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource ( uint32_t RNGx )

Get RNGx clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_GetRNGClockSource
Parameters:
RNGx This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_NONE
  • LL_RCC_RNG_CLKSOURCE_PLLSAI1
  • LL_RCC_RNG_CLKSOURCE_PLL
  • LL_RCC_RNG_CLKSOURCE_MSI

Definition at line 2583 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource ( uint32_t SAIx )

Get SAIx clock source.

Reference Manual to LL API cross reference:
CCIPR SAIxSEL LL_RCC_GetSAIClockSource
Parameters:
SAIx This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE
  • LL_RCC_SAI2_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
Returned value can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI1
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
  • LL_RCC_SAI1_CLKSOURCE_PLL
  • LL_RCC_SAI1_CLKSOURCE_PIN
  • LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
  • LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
  • LL_RCC_SAI2_CLKSOURCE_PLL (*)
  • LL_RCC_SAI2_CLKSOURCE_PIN (*)
(*) value not defined in all devices.

Definition at line 2551 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource ( uint32_t SDMMCx )

Get SDMMCx clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
Parameters:
SDMMCx This parameter can be one of the following values:
  • LL_RCC_SDMMC1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_SDMMC1_CLKSOURCE_NONE
  • LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
  • LL_RCC_SDMMC1_CLKSOURCE_PLL
  • LL_RCC_SDMMC1_CLKSOURCE_MSI

Definition at line 2567 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSDMMCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource ( uint32_t SPWMIx )

Get SWPMIx clock source.

Reference Manual to LL API cross reference:
CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
Parameters:
SPWMIx This parameter can be one of the following values:
  • LL_RCC_SWPMI1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_SWPMI1_CLKSOURCE_PCLK
  • LL_RCC_SWPMI1_CLKSOURCE_HSI

Definition at line 2633 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetSWPMIClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource ( uint32_t UARTx )

Get UARTx clock source.

Reference Manual to LL API cross reference:
CCIPR UARTxSEL LL_RCC_GetUARTClockSource
Parameters:
UARTx This parameter can be one of the following values:
  • LL_RCC_UART4_CLKSOURCE
  • LL_RCC_UART5_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_UART4_CLKSOURCE_PCLK1
  • LL_RCC_UART4_CLKSOURCE_SYSCLK
  • LL_RCC_UART4_CLKSOURCE_HSI
  • LL_RCC_UART4_CLKSOURCE_LSE
  • LL_RCC_UART5_CLKSOURCE_PCLK1
  • LL_RCC_UART5_CLKSOURCE_SYSCLK
  • LL_RCC_UART5_CLKSOURCE_HSI
  • LL_RCC_UART5_CLKSOURCE_LSE

Definition at line 2461 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource ( uint32_t USARTx )

Get USARTx clock source.

Reference Manual to LL API cross reference:
CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
Parameters:
USARTx This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE
  • LL_RCC_USART2_CLKSOURCE
  • LL_RCC_USART3_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
Returned value can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE_PCLK2
  • LL_RCC_USART1_CLKSOURCE_SYSCLK
  • LL_RCC_USART1_CLKSOURCE_HSI
  • LL_RCC_USART1_CLKSOURCE_LSE
  • LL_RCC_USART2_CLKSOURCE_PCLK1
  • LL_RCC_USART2_CLKSOURCE_SYSCLK
  • LL_RCC_USART2_CLKSOURCE_HSI
  • LL_RCC_USART2_CLKSOURCE_LSE
  • LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
  • LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
  • LL_RCC_USART3_CLKSOURCE_HSI (*)
  • LL_RCC_USART3_CLKSOURCE_LSE (*)
(*) value not defined in all devices.

Definition at line 2439 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource ( uint32_t USBx )

Get USBx clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_GetUSBClockSource
Parameters:
USBx This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_NONE
  • LL_RCC_USB_CLKSOURCE_PLLSAI1
  • LL_RCC_USB_CLKSOURCE_PLL
  • LL_RCC_USB_CLKSOURCE_MSI

Definition at line 2600 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

__STATIC_INLINE void LL_RCC_SetADCClockSource ( uint32_t ADCxSource )

Configure ADC clock source.

Reference Manual to LL API cross reference:
CCIPR ADCSEL LL_RCC_SetADCClockSource
Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE_NONE
  • LL_RCC_ADC_CLKSOURCE_PLLSAI1
  • LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
  • LL_RCC_ADC_CLKSOURCE_SYSCLK
(*) value not defined in all devices.
Return values:
None

Definition at line 2381 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetDFSDMClockSource ( uint32_t DFSDMxSource )

Configure DFSDM clock source.

Reference Manual to LL API cross reference:
CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
Parameters:
DFSDMxSource This parameter can be one of the following values:
  • LL_RCC_DFSDM1_CLKSOURCE_PCLK
  • LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
Return values:
None

Definition at line 2408 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetI2CClockSource ( uint32_t I2CxSource )

Configure I2Cx clock source.

Reference Manual to LL API cross reference:
CCIPR I2CxSEL LL_RCC_SetI2CClockSource
Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE_PCLK1
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK
  • LL_RCC_I2C1_CLKSOURCE_HSI
  • LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
  • LL_RCC_I2C2_CLKSOURCE_HSI (*)
  • LL_RCC_I2C3_CLKSOURCE_PCLK1
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK
  • LL_RCC_I2C3_CLKSOURCE_HSI
(*) value not defined in all devices.
Return values:
None

Definition at line 2277 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetLPTIMClockSource ( uint32_t LPTIMxSource )

Configure LPTIMx clock source.

Reference Manual to LL API cross reference:
CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
Parameters:
LPTIMxSource This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_HSI
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM2_CLKSOURCE_LSI
  • LL_RCC_LPTIM2_CLKSOURCE_HSI
  • LL_RCC_LPTIM2_CLKSOURCE_LSE
Return values:
None

Definition at line 2296 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetLPUARTClockSource ( uint32_t LPUARTxSource )

Configure LPUART1x clock source.

Reference Manual to LL API cross reference:
CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
Parameters:
LPUARTxSource This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK
  • LL_RCC_LPUART1_CLKSOURCE_HSI
  • LL_RCC_LPUART1_CLKSOURCE_LSE
Return values:
None

Definition at line 2255 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRNGClockSource ( uint32_t RNGxSource )

Configure RNG clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_SetRNGClockSource
Parameters:
RNGxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_NONE
  • LL_RCC_RNG_CLKSOURCE_PLLSAI1
  • LL_RCC_RNG_CLKSOURCE_PLL
  • LL_RCC_RNG_CLKSOURCE_MSI
Return values:
None

Definition at line 2347 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSAIClockSource ( uint32_t SAIxSource )

Configure SAIx clock source.

Reference Manual to LL API cross reference:
CCIPR SAIxSEL LL_RCC_SetSAIClockSource
Parameters:
SAIxSource This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI1
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
  • LL_RCC_SAI1_CLKSOURCE_PLL
  • LL_RCC_SAI1_CLKSOURCE_PIN
  • LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
  • LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
  • LL_RCC_SAI2_CLKSOURCE_PLL (*)
  • LL_RCC_SAI2_CLKSOURCE_PIN (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2317 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSDMMCClockSource ( uint32_t SDMMCxSource )

Configure SDMMC1 clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
Parameters:
SDMMCxSource This parameter can be one of the following values:
  • LL_RCC_SDMMC1_CLKSOURCE_NONE
  • LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
  • LL_RCC_SDMMC1_CLKSOURCE_PLL
  • LL_RCC_SDMMC1_CLKSOURCE_MSI
Return values:
None

Definition at line 2332 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSWPMIClockSource ( uint32_t SWPMIxSource )

Configure SWPMI clock source.

Reference Manual to LL API cross reference:
CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
Parameters:
SWPMIxSource This parameter can be one of the following values:
  • LL_RCC_SWPMI1_CLKSOURCE_PCLK
  • LL_RCC_SWPMI1_CLKSOURCE_HSI
Return values:
None

Definition at line 2394 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUARTClockSource ( uint32_t UARTxSource )

Configure UARTx clock source.

Reference Manual to LL API cross reference:
CCIPR UARTxSEL LL_RCC_SetUARTClockSource
Parameters:
UARTxSource This parameter can be one of the following values:
  • LL_RCC_UART4_CLKSOURCE_PCLK1
  • LL_RCC_UART4_CLKSOURCE_SYSCLK
  • LL_RCC_UART4_CLKSOURCE_HSI
  • LL_RCC_UART4_CLKSOURCE_LSE
  • LL_RCC_UART5_CLKSOURCE_PCLK1
  • LL_RCC_UART5_CLKSOURCE_SYSCLK
  • LL_RCC_UART5_CLKSOURCE_HSI
  • LL_RCC_UART5_CLKSOURCE_LSE
Return values:
None

Definition at line 2239 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSARTClockSource ( uint32_t USARTxSource )

Configure USARTx clock source.

Reference Manual to LL API cross reference:
CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE_PCLK2
  • LL_RCC_USART1_CLKSOURCE_SYSCLK
  • LL_RCC_USART1_CLKSOURCE_HSI
  • LL_RCC_USART1_CLKSOURCE_LSE
  • LL_RCC_USART2_CLKSOURCE_PCLK1
  • LL_RCC_USART2_CLKSOURCE_SYSCLK
  • LL_RCC_USART2_CLKSOURCE_HSI
  • LL_RCC_USART2_CLKSOURCE_LSE
  • LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
  • LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
  • LL_RCC_USART3_CLKSOURCE_HSI (*)
  • LL_RCC_USART3_CLKSOURCE_LSE (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 2219 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSBClockSource ( uint32_t USBxSource )

Configure USB clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_SetUSBClockSource
Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_NONE
  • LL_RCC_USB_CLKSOURCE_PLLSAI1
  • LL_RCC_USB_CLKSOURCE_PLL
  • LL_RCC_USB_CLKSOURCE_MSI
Return values:
None

Definition at line 2363 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC

Functions
RTC
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableRTC ( void )

Disable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_DisableRTC
Return values:
None

Definition at line 2709 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableRTC ( void )

Enable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_EnableRTC
Return values:
None

Definition at line 2699 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ForceBackupDomainReset ( void )

Force the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ForceBackupDomainReset
Return values:
None

Definition at line 2729 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource ( void )

Get RTC Clock Source.

Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_GetRTCClockSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32

Definition at line 2689 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC ( void )

Check if RTC has been enabled or not.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_IsEnabledRTC
Return values:
State of bit (1 or 0).

Definition at line 2719 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset ( void )

Release the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ReleaseBackupDomainReset
Return values:
None

Definition at line 2739 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRTCClockSource ( uint32_t Source )

Set RTC Clock Source.

Note:
Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.
Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_SetRTCClockSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32
Return values:
None

Definition at line 2675 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PLL

Functions
PLL
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for 48Mhz domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetN (void)
Get Main PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetP (void)
Get Main PLL division factor for PLLP.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetQ (void)
Get Main PLL division factor for PLLQ.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetR (void)
Get Main PLL division factor for PLLR.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetDivider (void)
Get Division factor for the main PLL and other PLL.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SAI (void)
Enable PLL output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SAI (void)
Disable PLL output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_48M (void)
Enable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_48M (void)
Disable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SYS (void)
Enable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SYS (void)
Disable PLL output mapped on SYSCLK domain.

Function Documentation

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLQ
 | ) |  |

Configure PLL used for 48Mhz domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
PLLN/PLLQ can be written only when PLL is disabled
This can be selected for USB, RNG, SDMMC
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLQ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_8
Return values:
None

Definition at line 2954 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLN.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLP
 | ) |  |

Configure PLL used for SAI domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
PLLN/PLLP can be written only when PLL is disabled
This can be selected for SAI1 or SAI2 (*)
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLP This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_17
Return values:
None

Definition at line 2911 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLN.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLR
 | ) |  |

Configure PLL used for SYSCLK Domain.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
PLLN/PLLR can be written only when PLL is disabled
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLR This parameter can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_8
Return values:
None

Definition at line 2814 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLN.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and LL_PLL_ConfigSystemClock_MSI().

__STATIC_INLINE void LL_RCC_PLL_Disable ( void )

Disable PLL.

Note:
Cannot be disabled if the PLL clock is used as the system clock
Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Disable
Return values:
None

Definition at line 2768 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M ( void )

Disable PLL output mapped on 48MHz domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
Return values:
None

Definition at line 3131 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI ( void )

Disable PLL output mapped on SAI domain clock.

Note:
Cannot be disabled if the PLL clock is used as the system clock
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
Return values:
None

Definition at line 3107 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS ( void )

Disable PLL output mapped on SYSCLK domain.

Note:
Cannot be disabled if the PLL clock is used as the system clock
In order to save power, when the PLLCLK of the PLL is not used, Main PLL should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
Return values:
None

Definition at line 3155 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_Enable ( void )

Enable PLL.

Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Enable
Return values:
None

Definition at line 2757 of file stm32l4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M ( void )

Enable PLL output mapped on 48MHz domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
Return values:
None

Definition at line 3117 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI ( void )

Enable PLL output mapped on SAI domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
Return values:
None

Definition at line 3093 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS ( void )

Enable PLL output mapped on SYSCLK domain.

Reference Manual to LL API cross reference:
PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
Return values:
None

Definition at line 3141 of file stm32l4xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider ( void )

Get Division factor for the main PLL and other PLL.

Reference Manual to LL API cross reference:
PLLCFGR PLLM LL_RCC_PLL_GetDivider
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8

Definition at line 3083 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource ( void )

Get the oscillator used as PLL clock source.

Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE

Definition at line 3065 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetN ( void )

Get Main PLL multiplication factor for VCO.

Reference Manual to LL API cross reference:
PLLCFGR PLLN LL_RCC_PLL_GetN
Return values:
Between 8 and 86

Definition at line 2965 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLN.

Referenced by RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), and RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetP ( void )

Get Main PLL division factor for PLLP.

Note:
used for PLLSAI3CLK (SAI1 and SAI2 clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLP LL_RCC_PLL_GetP
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_17

Definition at line 3020 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ ( void )

Get Main PLL division factor for PLLQ.

Note:
used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLQ LL_RCC_PLL_GetQ
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_8

Definition at line 3036 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetR ( void )

Get Main PLL division factor for PLLR.

Note:
used for PLLCLK (system clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLR LL_RCC_PLL_GetR
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_8

Definition at line 3051 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady ( void )

Check if PLL Ready.

Reference Manual to LL API cross reference:
CR PLLRDY LL_RCC_PLL_IsReady
Return values:
State of bit (1 or 0).

Definition at line 2778 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetUSBClockFreq(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_PLL_IsBusy().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PLLSAI1

Functions
PLLSAI1
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_PLLSAI1_Enable (void)
Enable PLLSAI1.
__STATIC_INLINE void | LL_RCC_PLLSAI1_Disable (void)
Disable PLLSAI1.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_IsReady (void)
Check if PLLSAI1 Ready.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLLSAI1 used for 48Mhz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLLSAI1 used for SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLLSAI1 used for ADC domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetN (void)
Get SAI1PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetP (void)
Get SAI1PLL division factor for PLLSAI1P.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetQ (void)
Get SAI1PLL division factor for PLLSAI1Q.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetR (void)
Get PLLSAI1 division factor for PLLSAIR.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_SAI (void)
Enable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_SAI (void)
Disable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_48M (void)
Enable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_48M (void)
Disable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_ADC (void)
Enable PLLSAI1 output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_ADC (void)
Disable PLLSAI1 output mapped on ADC domain clock.

Function Documentation

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLQ
 | ) |  |

Configure PLLSAI1 used for 48Mhz domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
PLLN/PLLQ can be written only when PLLSAI1 is disabled
This can be selected for USB, RNG, SDMMC
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLQ This parameter can be one of the following values:
  • LL_RCC_PLLSAI1Q_DIV_2
  • LL_RCC_PLLSAI1Q_DIV_4
  • LL_RCC_PLLSAI1Q_DIV_6
  • LL_RCC_PLLSAI1Q_DIV_8
Return values:
None

Definition at line 3230 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLSAI1N.

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLR
 | ) |  |

Configure PLLSAI1 used for ADC domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
PLLN/PLLR can be written only when PLLSAI1 is disabled
This can be selected for ADC
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLR This parameter can be one of the following values:
  • LL_RCC_PLLSAI1R_DIV_2
  • LL_RCC_PLLSAI1R_DIV_4
  • LL_RCC_PLLSAI1R_DIV_6
  • LL_RCC_PLLSAI1R_DIV_8
Return values:
None

Definition at line 3370 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLSAI1N.

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLP
 | ) |  |

Configure PLLSAI1 used for SAI domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled
PLLN/PLLP can be written only when PLLSAI1 is disabled
This can be selected for SAI1 or SAI2 (*)
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLP This parameter can be one of the following values:
  • LL_RCC_PLLSAI1P_DIV_7
  • LL_RCC_PLLSAI1P_DIV_17
Return values:
None

Definition at line 3327 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLSAI1N.

__STATIC_INLINE void LL_RCC_PLLSAI1_Disable ( void )

Disable PLLSAI1.

Reference Manual to LL API cross reference:
CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
Return values:
None

Definition at line 3183 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M ( void )

Disable PLLSAI1 output mapped on 48MHz domain clock.

Note:
In order to save power, when of the PLLSAI1 is not used, should be 0
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
Return values:
None

Definition at line 3511 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC ( void )

Disable PLLSAI1 output mapped on ADC domain clock.

Note:
In order to save power, when of the PLLSAI1 is not used, Main PLLSAI1 should be 0
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
Return values:
None

Definition at line 3533 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI ( void )

Disable PLLSAI1 output mapped on SAI domain clock.

Note:
In order to save power, when of the PLLSAI1 is not used, should be 0
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
Return values:
None

Definition at line 3489 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_Enable ( void )

Enable PLLSAI1.

Reference Manual to LL API cross reference:
CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
Return values:
None

Definition at line 3173 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M ( void )

Enable PLLSAI1 output mapped on 48MHz domain clock.

Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
Return values:
None

Definition at line 3499 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC ( void )

Enable PLLSAI1 output mapped on ADC domain clock.

Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
Return values:
None

Definition at line 3521 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI ( void )

Enable PLLSAI1 output mapped on SAI domain clock.

Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
Return values:
None

Definition at line 3477 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN ( void )

Get SAI1PLL multiplication factor for VCO.

Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
Return values:
Between 8 and 86

Definition at line 3381 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLSAI1N.

Referenced by RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), and RCC_PLLSAI1_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP ( void )

Get SAI1PLL division factor for PLLSAI1P.

Note:
used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSAI1P_DIV_7
  • LL_RCC_PLLSAI1P_DIV_17

Definition at line 3433 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ ( void )

Get SAI1PLL division factor for PLLSAI1Q.

Note:
used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSAI1Q_DIV_2
  • LL_RCC_PLLSAI1Q_DIV_4
  • LL_RCC_PLLSAI1Q_DIV_6
  • LL_RCC_PLLSAI1Q_DIV_8

Definition at line 3452 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_48M().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR ( void )

Get PLLSAI1 division factor for PLLSAIR.

Note:
used for PLLADC1CLK (ADC clock)
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSAI1R_DIV_2
  • LL_RCC_PLLSAI1R_DIV_4
  • LL_RCC_PLLSAI1R_DIV_6
  • LL_RCC_PLLSAI1R_DIV_8

Definition at line 3467 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_ADC().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady ( void )

Check if PLLSAI1 Ready.

Reference Manual to LL API cross reference:
CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
Return values:
State of bit (1 or 0).

Definition at line 3193 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetUSBClockFreq(), and UTILS_PLL_IsBusy().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PLLSAI2

Functions
PLLSAI2
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_PLLSAI2_Enable (void)
Enable PLLSAI2.
__STATIC_INLINE void | LL_RCC_PLLSAI2_Disable (void)
Disable PLLSAI2.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI2_IsReady (void)
Check if PLLSAI2 Ready.
__STATIC_INLINE void | LL_RCC_PLLSAI2_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLLSAI2 used for SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI2_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLLSAI2 used for ADC domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI2_GetN (void)
Get SAI2PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI2_GetP (void)
Get SAI2PLL division factor for PLLSAI2P.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI2_GetR (void)
Get SAI2PLL division factor for PLLSAI2R.
__STATIC_INLINE void | LL_RCC_PLLSAI2_EnableDomain_SAI (void)
Enable PLLSAI2 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI2_DisableDomain_SAI (void)
Disable PLLSAI2 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI2_EnableDomain_ADC (void)
Enable PLLSAI2 output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI2_DisableDomain_ADC (void)
Disable PLLSAI2 output mapped on ADC domain clock.

Function Documentation

__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLR
 | ) |  |

Configure PLLSAI2 used for ADC domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI2 and PLLSAI2 are disabled
PLLN/PLLR can be written only when PLLSAI2 is disabled
This can be selected for ADC
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC
PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC
PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC
PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLR This parameter can be one of the following values:
  • LL_RCC_PLLSAI2R_DIV_2
  • LL_RCC_PLLSAI2R_DIV_4
  • LL_RCC_PLLSAI2R_DIV_6
  • LL_RCC_PLLSAI2R_DIV_8
Return values:
None

Definition at line 3645 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLSAI2N.

__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLP
 | ) |  |

Configure PLLSAI2 used for SAI domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL, PLLSAI2 and PLLSAI2 are disabled
PLLN/PLLP can be written only when PLLSAI2 is disabled
This can be selected for SAI1 or SAI2
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 8 and 86
PLLP This parameter can be one of the following values:
  • LL_RCC_PLLSAI2P_DIV_7
  • LL_RCC_PLLSAI2P_DIV_17
Return values:
None

Definition at line 3607 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLSAI2N.

__STATIC_INLINE void LL_RCC_PLLSAI2_Disable ( void )

Disable PLLSAI2.

Reference Manual to LL API cross reference:
CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
Return values:
None

Definition at line 3562 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC ( void )

Disable PLLSAI2 output mapped on ADC domain clock.

Note:
In order to save power, when of the PLLSAI2 is not used, Main PLLSAI2 should be 0
Reference Manual to LL API cross reference:
PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
Return values:
None

Definition at line 3728 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI ( void )

Disable PLLSAI2 output mapped on SAI domain clock.

Note:
In order to save power, when of the PLLSAI2 is not used, should be 0
Reference Manual to LL API cross reference:
PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
Return values:
None

Definition at line 3706 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI2_Enable ( void )

Enable PLLSAI2.

Reference Manual to LL API cross reference:
CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
Return values:
None

Definition at line 3552 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC ( void )

Enable PLLSAI2 output mapped on ADC domain clock.

Reference Manual to LL API cross reference:
PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
Return values:
None

Definition at line 3716 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI ( void )

Enable PLLSAI2 output mapped on SAI domain clock.

Reference Manual to LL API cross reference:
PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
Return values:
None

Definition at line 3694 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN ( void )

Get SAI2PLL multiplication factor for VCO.

Reference Manual to LL API cross reference:
PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
Return values:
Between 8 and 86

Definition at line 3656 of file stm32l4xx_ll_rcc.h.

References RCC_POSITION_PLLSAI2N.

Referenced by RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP ( void )

Get SAI2PLL division factor for PLLSAI2P.

Note:
used for PLLSAI2CLK (SAI1 or SAI2 clock).
Reference Manual to LL API cross reference:
PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSAI2P_DIV_7
  • LL_RCC_PLLSAI2P_DIV_17

Definition at line 3669 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI2_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR ( void )

Get SAI2PLL division factor for PLLSAI2R.

Note:
used for PLLADC2CLK (ADC clock)
Reference Manual to LL API cross reference:
PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSAI2R_DIV_2
  • LL_RCC_PLLSAI2R_DIV_4
  • LL_RCC_PLLSAI2R_DIV_6
  • LL_RCC_PLLSAI2R_DIV_8

Definition at line 3684 of file stm32l4xx_ll_rcc.h.

Referenced by RCC_PLLSAI2_GetFreqDomain_ADC().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady ( void )

Check if PLLSAI2 Ready.

Reference Manual to LL API cross reference:
CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
Return values:
State of bit (1 or 0).

Definition at line 3572 of file stm32l4xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetSAIClockFreq(), and UTILS_PLL_IsBusy().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG Management

Functions
FLAG Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_MSIRDY (void)
Clear MSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLSAI1RDY (void)
Clear PLLSAI1 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLSAI2RDY (void)
Clear PLLSAI1 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void)
Clear LSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_MSIRDY (void)
Check if MSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLSAI1RDY (void)
Check if PLLSAI1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLSAI2RDY (void)
Check if PLLSAI1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void)
Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_FWRST (void)
Check if RCC flag FW reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_OBLRST (void)
Check if RCC flag is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_BORRST (void)
Check if RCC flag BOR reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.

Function Documentation

__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS ( void )

Clear Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CICR CSSC LL_RCC_ClearFlag_HSECSS
Return values:
None

Definition at line 3841 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY ( void )

Clear HSE ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSERDYC LL_RCC_ClearFlag_HSERDY
Return values:
None

Definition at line 3787 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY ( void )

Clear HSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
Return values:
None

Definition at line 3777 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS ( void )

Clear LSE Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CICR LSECSSC LL_RCC_ClearFlag_LSECSS
Return values:
None

Definition at line 3851 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY ( void )

Clear LSE ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSERDYC LL_RCC_ClearFlag_LSERDY
Return values:
None

Definition at line 3757 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY ( void )

Clear LSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
Return values:
None

Definition at line 3747 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY ( void )

Clear MSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
Return values:
None

Definition at line 3767 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY ( void )

Clear PLL ready interrupt flag.

Reference Manual to LL API cross reference:
CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
Return values:
None

Definition at line 3797 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY ( void )

Clear PLLSAI1 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
Return values:
None

Definition at line 3819 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY ( void )

Clear PLLSAI1 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
Return values:
None

Definition at line 3830 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearResetFlags ( void )

Set RMVF bit to clear the reset flags.

Reference Manual to LL API cross reference:
CSR RMVF LL_RCC_ClearResetFlags
Return values:
None

Definition at line 4056 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST ( void )

Check if RCC flag BOR reset is set or not.

Reference Manual to LL API cross reference:
CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
Return values:
State of bit (1 or 0).

Definition at line 4046 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST ( void )

Check if RCC flag FW reset is set or not.

Reference Manual to LL API cross reference:
CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
Return values:
State of bit (1 or 0).

Definition at line 3976 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS ( void )

Check if Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
Return values:
State of bit (1 or 0).

Definition at line 3955 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY ( void )

Check if HSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 3901 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY ( void )

Check if HSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 3891 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST ( void )

Check if RCC flag Independent Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
Return values:
State of bit (1 or 0).

Definition at line 3986 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST ( void )

Check if RCC flag Low Power reset is set or not.

Reference Manual to LL API cross reference:
CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
Return values:
State of bit (1 or 0).

Definition at line 3996 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS ( void )

Check if LSE Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
Return values:
State of bit (1 or 0).

Definition at line 3965 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY ( void )

Check if LSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 3871 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY ( void )

Check if LSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 3861 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY ( void )

Check if MSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
Return values:
State of bit (1 or 0).

Definition at line 3881 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST ( void )

Check if RCC flag is set or not.

Reference Manual to LL API cross reference:
CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
Return values:
State of bit (1 or 0).

Definition at line 4006 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST ( void )

Check if RCC flag Pin reset is set or not.

Reference Manual to LL API cross reference:
CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
Return values:
State of bit (1 or 0).

Definition at line 4016 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY ( void )

Check if PLL ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 3911 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY ( void )

Check if PLLSAI1 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
Return values:
State of bit (1 or 0).

Definition at line 3933 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY ( void )

Check if PLLSAI1 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
Return values:
State of bit (1 or 0).

Definition at line 3944 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST ( void )

Check if RCC flag Software reset is set or not.

Reference Manual to LL API cross reference:
CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
Return values:
State of bit (1 or 0).

Definition at line 4026 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST ( void )

Check if RCC flag Window Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
Return values:
State of bit (1 or 0).

Definition at line 4036 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Management

Functions
IT Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_MSIRDY (void)
Enable MSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLSAI1RDY (void)
Enable PLLSAI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLSAI2RDY (void)
Enable PLLSAI2 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSECSS (void)
Enable LSE clock security system interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_MSIRDY (void)
Disable MSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLSAI1RDY (void)
Disable PLLSAI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLSAI2RDY (void)
Disable PLLSAI2 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSECSS (void)
Disable LSE clock security system interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_MSIRDY (void)
Checks if MSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLSAI1RDY (void)
Checks if PLLSAI1 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLSAI2RDY (void)
Checks if PLLSAI2 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSECSS (void)
Checks if LSECSS interrupt source is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableIT_HSERDY ( void )

Disable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_DisableIT_HSERDY
Return values:
None

Definition at line 4218 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY ( void )

Disable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
Return values:
None

Definition at line 4208 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSECSS ( void )

Disable LSE clock security system interrupt.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_DisableIT_LSECSS
Return values:
None

Definition at line 4272 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSERDY ( void )

Disable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_DisableIT_LSERDY
Return values:
None

Definition at line 4188 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY ( void )

Disable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
Return values:
None

Definition at line 4178 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY ( void )

Disable MSI ready interrupt.

Reference Manual to LL API cross reference:
CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
Return values:
None

Definition at line 4198 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY ( void )

Disable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
Return values:
None

Definition at line 4228 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY ( void )

Disable PLLSAI1 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
Return values:
None

Definition at line 4250 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY ( void )

Disable PLLSAI2 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
Return values:
None

Definition at line 4261 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSERDY ( void )

Enable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_EnableIT_HSERDY
Return values:
None

Definition at line 4114 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY ( void )

Enable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
Return values:
None

Definition at line 4104 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSECSS ( void )

Enable LSE clock security system interrupt.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_EnableIT_LSECSS
Return values:
None

Definition at line 4168 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSERDY ( void )

Enable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_EnableIT_LSERDY
Return values:
None

Definition at line 4084 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY ( void )

Enable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
Return values:
None

Definition at line 4074 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY ( void )

Enable MSI ready interrupt.

Reference Manual to LL API cross reference:
CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
Return values:
None

Definition at line 4094 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY ( void )

Enable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
Return values:
None

Definition at line 4124 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY ( void )

Enable PLLSAI1 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
Return values:
None

Definition at line 4146 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY ( void )

Enable PLLSAI2 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
Return values:
None

Definition at line 4157 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY ( void )

Checks if HSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 4322 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY ( void )

Checks if HSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 4312 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS ( void )

Checks if LSECSS interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
Return values:
State of bit (1 or 0).

Definition at line 4376 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY ( void )

Checks if LSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 4292 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY ( void )

Checks if LSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 4282 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY ( void )

Checks if MSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
Return values:
State of bit (1 or 0).

Definition at line 4302 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY ( void )

Checks if PLL ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 4332 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY ( void )

Checks if PLLSAI1 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
Return values:
State of bit (1 or 0).

Definition at line 4354 of file stm32l4xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY ( void )

Checks if PLLSAI2 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
Return values:
State of bit (1 or 0).

Definition at line 4365 of file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: De-initialization function

Functions
De-initialization function
RCC Exported Functions

Functions

ErrorStatus LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.

Function Documentation

ErrorStatus LL_RCC_DeInit ( void )

Reset the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • MSI ON and used as system clock source
  • HSE, HSI, PLL and PLLSAIxSource OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RCC registers are de-initialized
  • ERROR: not applicable

Definition at line 171 of file stm32l4xx_ll_rcc.c.

References LL_RCC_HSE_DisableBypass(), LL_RCC_HSI_SetCalibTrimming(), LL_RCC_MSI_Enable(), LL_RCC_MSI_IsReady(), LL_RCC_MSI_SetCalibTrimming(), LL_RCC_MSI_SetRange(), LL_RCC_MSIRANGE_6, LL_RCC_WriteReg, RCC_POSITION_PLLN, RCC_POSITION_PLLSAI1N, and RCC_POSITION_PLLSAI2N.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get system and peripherals clocks frequency functions

Functions
Get system and peripherals clocks frequency functions
RCC Exported Functions

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device. More...

Functions

void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetUARTClockFreq (uint32_t UARTxSource)
Return UARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetSDMMCClockFreq (uint32_t SDMMCxSource)
Return SDMMCx clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetSWPMIClockFreq (uint32_t SWPMIxSource)
Return SWPMIx clock frequency.
uint32_t | LL_RCC_GetDFSDMClockFreq (uint32_t DFSDMxSource)
Return DFSDMx clock frequency.

Detailed Description

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device.

Note:
If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
(*) MSI_VALUE is a constant defined in this file (default value 4 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSI_VALUE is a constant defined in this file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(***) HSE_VALUE is a constant defined in this file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be incorrect when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.

Function Documentation

uint32_t LL_RCC_GetADCClockFreq ( uint32_t ADCxSource )

Return ADCx clock frequency.

Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
ADC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 962 of file stm32l4xx_ll_rcc.c.

References assert_param, IS_LL_RCC_ADC_CLKSOURCE, LL_RCC_ADC_CLKSOURCE_NONE, LL_RCC_ADC_CLKSOURCE_PLLSAI1, LL_RCC_ADC_CLKSOURCE_PLLSAI2, LL_RCC_ADC_CLKSOURCE_SYSCLK, LL_RCC_GetADCClockSource(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLLSAI1_IsReady(), LL_RCC_PLLSAI2_IsReady(), RCC_GetSystemClockFreq(), RCC_PLLSAI1_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_ADC().

uint32_t LL_RCC_GetDFSDMClockFreq ( uint32_t DFSDMxSource )

Return DFSDMx clock frequency.

Parameters:
DFSDMxSource This parameter can be one of the following values:
  • LL_RCC_DFSDM1_CLKSOURCE
Return values:
DFSDM clock frequency (in Hz)

Definition at line 1040 of file stm32l4xx_ll_rcc.c.

References assert_param, IS_LL_RCC_DFSDM_CLKSOURCE, LL_RCC_DFSDM1_CLKSOURCE_PCLK, LL_RCC_DFSDM1_CLKSOURCE_SYSCLK, LL_RCC_GetDFSDMClockSource(), LL_RCC_PERIPH_FREQUENCY_NO, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetI2CClockFreq ( uint32_t I2CxSource )

Return I2Cx clock frequency.

Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE
  • LL_RCC_I2C2_CLKSOURCE (*)
(*) value not defined in all devices.
  • LL_RCC_I2C3_CLKSOURCE
Return values:
I2C clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready

Definition at line 492 of file stm32l4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_I2C_CLKSOURCE, LL_RCC_GetI2CClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_I2C1_CLKSOURCE, LL_RCC_I2C1_CLKSOURCE_HSI, LL_RCC_I2C1_CLKSOURCE_PCLK1, LL_RCC_I2C1_CLKSOURCE_SYSCLK, LL_RCC_I2C2_CLKSOURCE, LL_RCC_I2C2_CLKSOURCE_HSI, LL_RCC_I2C2_CLKSOURCE_PCLK1, LL_RCC_I2C2_CLKSOURCE_SYSCLK, LL_RCC_I2C3_CLKSOURCE, LL_RCC_I2C3_CLKSOURCE_HSI, LL_RCC_I2C3_CLKSOURCE_PCLK1, LL_RCC_I2C3_CLKSOURCE_SYSCLK, LL_RCC_PERIPH_FREQUENCY_NO, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetLPTIMClockFreq ( uint32_t LPTIMxSource )

Return LPTIMx clock frequency.

Parameters:
LPTIMxSource This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE
  • LL_RCC_LPTIM2_CLKSOURCE
Return values:
LPTIM clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 626 of file stm32l4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_LPTIM_CLKSOURCE, LL_RCC_GetLPTIMClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LPTIM1_CLKSOURCE, LL_RCC_LPTIM1_CLKSOURCE_HSI, LL_RCC_LPTIM1_CLKSOURCE_LSE, LL_RCC_LPTIM1_CLKSOURCE_LSI, LL_RCC_LPTIM1_CLKSOURCE_PCLK1, LL_RCC_LPTIM2_CLKSOURCE, LL_RCC_LPTIM2_CLKSOURCE_HSI, LL_RCC_LPTIM2_CLKSOURCE_LSE, LL_RCC_LPTIM2_CLKSOURCE_LSI, LL_RCC_LPTIM2_CLKSOURCE_PCLK1, LL_RCC_LSE_IsReady(), LL_RCC_LSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LSE_VALUE, LSI_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetLPUARTClockFreq ( uint32_t LPUARTxSource )

Return LPUARTx clock frequency.

Parameters:
LPUARTxSource This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE
Return values:
LPUART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 581 of file stm32l4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_LPUART_CLKSOURCE, LL_RCC_GetLPUARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LPUART1_CLKSOURCE_HSI, LL_RCC_LPUART1_CLKSOURCE_LSE, LL_RCC_LPUART1_CLKSOURCE_PCLK1, LL_RCC_LPUART1_CLKSOURCE_SYSCLK, LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LSE_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_LPUART_Init().

uint32_t LL_RCC_GetRNGClockFreq ( uint32_t RNGxSource )

Return RNGx clock frequency.

Parameters:
RNGxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
RNG clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 858 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, assert_param, IS_LL_RCC_RNG_CLKSOURCE, LL_RCC_GetRNGClockSource(), LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_MSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), LL_RCC_RNG_CLKSOURCE_MSI, LL_RCC_RNG_CLKSOURCE_NONE, LL_RCC_RNG_CLKSOURCE_PLL, LL_RCC_RNG_CLKSOURCE_PLLSAI1, RCC_PLL_GetFreqDomain_48M(), and RCC_PLLSAI1_GetFreqDomain_48M().

uint32_t LL_RCC_GetSAIClockFreq ( uint32_t SAIxSource )

Return SAIx clock frequency.

Parameters:
SAIxSource This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE
  • LL_RCC_SAI2_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
SAI clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used

Definition at line 715 of file stm32l4xx_ll_rcc.c.

References assert_param, IS_LL_RCC_SAI_CLKSOURCE, LL_RCC_GetSAIClockSource(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), LL_RCC_PLLSAI2_IsReady(), LL_RCC_SAI1_CLKSOURCE, LL_RCC_SAI1_CLKSOURCE_PIN, LL_RCC_SAI1_CLKSOURCE_PLL, LL_RCC_SAI1_CLKSOURCE_PLLSAI1, LL_RCC_SAI1_CLKSOURCE_PLLSAI2, LL_RCC_SAI2_CLKSOURCE, LL_RCC_SAI2_CLKSOURCE_PIN, LL_RCC_SAI2_CLKSOURCE_PLL, LL_RCC_SAI2_CLKSOURCE_PLLSAI1, LL_RCC_SAI2_CLKSOURCE_PLLSAI2, RCC_PLL_GetFreqDomain_SAI(), RCC_PLLSAI1_GetFreqDomain_SAI(), and RCC_PLLSAI2_GetFreqDomain_SAI().

uint32_t LL_RCC_GetSDMMCClockFreq ( uint32_t SDMMCxSource )

Return SDMMCx clock frequency.

Parameters:
SDMMCxSource This parameter can be one of the following values:
  • LL_RCC_SDMMC1_CLKSOURCE
Return values:
SDMMC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 807 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, assert_param, IS_LL_RCC_SDMMC_CLKSOURCE, LL_RCC_GetSDMMCClockSource(), LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_MSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), LL_RCC_SDMMC1_CLKSOURCE_MSI, LL_RCC_SDMMC1_CLKSOURCE_NONE, LL_RCC_SDMMC1_CLKSOURCE_PLL, LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1, RCC_PLL_GetFreqDomain_48M(), and RCC_PLLSAI1_GetFreqDomain_48M().

uint32_t LL_RCC_GetSWPMIClockFreq ( uint32_t SWPMIxSource )

Return SWPMIx clock frequency.

Parameters:
SWPMIxSource This parameter can be one of the following values:
  • LL_RCC_SWPMI1_CLKSOURCE
Return values:
SWPMI clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready

Definition at line 1007 of file stm32l4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_SWPMI_CLKSOURCE, LL_RCC_GetSWPMIClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_SWPMI1_CLKSOURCE_HSI, LL_RCC_SWPMI1_CLKSOURCE_PCLK, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

void LL_RCC_GetSystemClocksFreq ( LL_RCC_ClocksTypeDef * RCC_Clocks )

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.

Note:
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update structure fields. Otherwise, any configuration based on this function will be incorrect.
Parameters:
RCC_Clocks pointer to a LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
Return values:
None

Definition at line 269 of file stm32l4xx_ll_rcc.c.

References LL_RCC_ClocksTypeDef::HCLK_Frequency, LL_RCC_ClocksTypeDef::PCLK1_Frequency, LL_RCC_ClocksTypeDef::PCLK2_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), RCC_GetSystemClockFreq(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

uint32_t LL_RCC_GetUARTClockFreq ( uint32_t UARTxSource )

Return UARTx clock frequency.

Parameters:
UARTxSource This parameter can be one of the following values:
  • LL_RCC_UART4_CLKSOURCE
  • LL_RCC_UART5_CLKSOURCE
Return values:
UART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 406 of file stm32l4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_UART_CLKSOURCE, LL_RCC_GetUARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_UART4_CLKSOURCE, LL_RCC_UART4_CLKSOURCE_HSI, LL_RCC_UART4_CLKSOURCE_LSE, LL_RCC_UART4_CLKSOURCE_PCLK1, LL_RCC_UART4_CLKSOURCE_SYSCLK, LL_RCC_UART5_CLKSOURCE, LL_RCC_UART5_CLKSOURCE_HSI, LL_RCC_UART5_CLKSOURCE_LSE, LL_RCC_UART5_CLKSOURCE_PCLK1, LL_RCC_UART5_CLKSOURCE_SYSCLK, LSE_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_USART_Init().

uint32_t LL_RCC_GetUSARTClockFreq ( uint32_t USARTxSource )

Return USARTx clock frequency.

Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE
  • LL_RCC_USART2_CLKSOURCE
  • LL_RCC_USART3_CLKSOURCE (*)
(*) value not defined in all devices.
Return values:
USART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 295 of file stm32l4xx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_USART_CLKSOURCE, LL_RCC_GetUSARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_USART1_CLKSOURCE, LL_RCC_USART1_CLKSOURCE_HSI, LL_RCC_USART1_CLKSOURCE_LSE, LL_RCC_USART1_CLKSOURCE_PCLK2, LL_RCC_USART1_CLKSOURCE_SYSCLK, LL_RCC_USART2_CLKSOURCE, LL_RCC_USART2_CLKSOURCE_HSI, LL_RCC_USART2_CLKSOURCE_LSE, LL_RCC_USART2_CLKSOURCE_PCLK1, LL_RCC_USART2_CLKSOURCE_SYSCLK, LL_RCC_USART3_CLKSOURCE, LL_RCC_USART3_CLKSOURCE_HSI, LL_RCC_USART3_CLKSOURCE_LSE, LL_RCC_USART3_CLKSOURCE_PCLK1, LL_RCC_USART3_CLKSOURCE_SYSCLK, LSE_VALUE, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_USART_Init().

uint32_t LL_RCC_GetUSBClockFreq ( uint32_t USBxSource )

Return USBx clock frequency.

Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
USB clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 910 of file stm32l4xx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, assert_param, IS_LL_RCC_USB_CLKSOURCE, LL_RCC_GetUSBClockSource(), LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_MSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), LL_RCC_USB_CLKSOURCE_MSI, LL_RCC_USB_CLKSOURCE_NONE, LL_RCC_USB_CLKSOURCE_PLL, LL_RCC_USB_CLKSOURCE_PLLSAI1, RCC_PLL_GetFreqDomain_48M(), and RCC_PLLSAI1_GetFreqDomain_48M().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG

Modules
RNG
STM32L4xx_LL_Driver

Modules

RNG Exported Constants
RNG Exported Macros
RNG Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for RNG registers.

Register | Bit | Function
CR | IE | LL_RNG_DisableIT
 |  | LL_RNG_EnableIT
 |  | LL_RNG_IsEnabledIT
 | RNGEN | LL_RNG_Disable
 |  | LL_RNG_Enable
 |  | LL_RNG_IsEnabled
DR | RNDATA | LL_RNG_ReadRandData32
SR | CECS | LL_RNG_IsActiveFlag_CECS
 | CEIS | LL_RNG_ClearFlag_CEIS
 |  | LL_RNG_IsActiveFlag_CEIS
 | DRDY | LL_RNG_IsActiveFlag_DRDY
 | SECS | LL_RNG_IsActiveFlag_SECS
 | SEIS | LL_RNG_ClearFlag_SEIS
 |  | LL_RNG_IsActiveFlag_SEIS
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RNG Exported Constants

Flags defines which can be used with LL_RNG_ReadReg function. More...

Defines

#define | LL_RNG_SR_DRDY RNG_SR_DRDY
#define | LL_RNG_SR_CECS RNG_SR_CECS
#define | LL_RNG_SR_SECS RNG_SR_SECS
#define | LL_RNG_SR_CEIS RNG_SR_CEIS
#define | LL_RNG_SR_SEIS RNG_SR_SEIS

Detailed Description

Flags defines which can be used with LL_RNG_ReadReg function.

Define Documentation

#define LL_RNG_SR_CECS RNG_SR_CECS

Clock error current status

Definition at line 75 of file stm32l4xx_ll_rng.h.

#define LL_RNG_SR_CEIS RNG_SR_CEIS

Clock error interrupt status

Definition at line 77 of file stm32l4xx_ll_rng.h.

#define LL_RNG_SR_DRDY RNG_SR_DRDY

Register contains valid random data

Definition at line 74 of file stm32l4xx_ll_rng.h.

#define LL_RNG_SR_SECS RNG_SR_SECS

Seed error current status

Definition at line 76 of file stm32l4xx_ll_rng.h.

#define LL_RNG_SR_SEIS RNG_SR_SEIS

Seed error interrupt status

Definition at line 78 of file stm32l4xx_ll_rng.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
RNG Exported Constants

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros. More...

Defines

#define LL_RNG_CR_IE RNG_CR_IE

Detailed Description

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros.

Define Documentation

#define LL_RNG_CR_IE RNG_CR_IE

RNG Interrupt enable

Definition at line 87 of file stm32l4xx_ll_rng.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RNG Exported Macros

Defines

#define | LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RNG register.
#define | LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RNG register.

Define Documentation

#define LL_RNG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in RNG register.

Parameters:
__INSTANCE__ | RNG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 120 of file stm32l4xx_ll_rng.h.

#define LL_RNG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in RNG register.

Parameters:
__INSTANCE__ | RNG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 112 of file stm32l4xx_ll_rng.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG Configuration functions

Functions
RNG Configuration functions
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_Enable (RNG_TypeDef *RNGx)
Enable Random Number Generation.
__STATIC_INLINE void | LL_RNG_Disable (RNG_TypeDef *RNGx)
Disable Random Number Generation.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabled (RNG_TypeDef *RNGx)
Check if Random Number Generator is enabled.

Function Documentation

__STATIC_INLINE void LL_RNG_Disable ( RNG_TypeDef * RNGx )

Disable Random Number Generation.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_Disable
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 155 of file stm32l4xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_Enable ( RNG_TypeDef * RNGx )

Enable Random Number Generation.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_Enable
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 144 of file stm32l4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabled ( RNG_TypeDef * RNGx )

Check if Random Number Generator is enabled.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_IsEnabled
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 166 of file stm32l4xx_ll_rng.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG Management

Functions
FLAG Management
RNG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_DRDY (RNG_TypeDef *RNGx)
Indicate if the RNG Data ready Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CECS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SECS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CEIS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Interrupt Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SEIS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Interrupt Status Flag is set or not.
__STATIC_INLINE void | LL_RNG_ClearFlag_CEIS (RNG_TypeDef *RNGx)
Clear Clock Error interrupt Status (CEIS) Flag.
__STATIC_INLINE void | LL_RNG_ClearFlag_SEIS (RNG_TypeDef *RNGx)
Clear Seed Error interrupt Status (SEIS) Flag.

Function Documentation

__STATIC_INLINE void LL_RNG_ClearFlag_CEIS ( RNG_TypeDef * RNGx )

Clear Clock Error interrupt Status (CEIS) Flag.

Reference Manual to LL API cross reference:
SR CEIS LL_RNG_ClearFlag_CEIS
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 240 of file stm32l4xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_ClearFlag_SEIS ( RNG_TypeDef * RNGx )

Clear Seed Error interrupt Status (SEIS) Flag.

Reference Manual to LL API cross reference:
SR SEIS LL_RNG_ClearFlag_SEIS
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 251 of file stm32l4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS ( RNG_TypeDef * RNGx )

Indicate if the Clock Error Current Status Flag is set or not.

Reference Manual to LL API cross reference:
SR CECS LL_RNG_IsActiveFlag_CECS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 196 of file stm32l4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS ( RNG_TypeDef * RNGx )

Indicate if the Clock Error Interrupt Status Flag is set or not.

Reference Manual to LL API cross reference:
SR CEIS LL_RNG_IsActiveFlag_CEIS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 218 of file stm32l4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY ( RNG_TypeDef * RNGx )

Indicate if the RNG Data ready Flag is set or not.

Reference Manual to LL API cross reference:
SR DRDY LL_RNG_IsActiveFlag_DRDY
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 185 of file stm32l4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS ( RNG_TypeDef * RNGx )

Indicate if the Seed Error Current Status Flag is set or not.

Reference Manual to LL API cross reference:
SR SECS LL_RNG_IsActiveFlag_SECS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 207 of file stm32l4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS ( RNG_TypeDef * RNGx )

Indicate if the Seed Error Interrupt Status Flag is set or not.

Reference Manual to LL API cross reference:
SR SEIS LL_RNG_IsActiveFlag_SEIS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 229 of file stm32l4xx_ll_rng.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Management

Functions
IT Management
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_EnableIT (RNG_TypeDef *RNGx)
Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE void | LL_RNG_DisableIT (RNG_TypeDef *RNGx)
Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledIT (RNG_TypeDef *RNGx)
Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)

Function Documentation

__STATIC_INLINE void LL_RNG_DisableIT ( RNG_TypeDef * RNGx )

Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_DisableIT
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 283 of file stm32l4xx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableIT ( RNG_TypeDef * RNGx )

Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_EnableIT
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 271 of file stm32l4xx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT ( RNG_TypeDef * RNGx )

Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_IsEnabledIT
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 295 of file stm32l4xx_ll_rng.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Management

Functions
Data Management
RNG Exported Functions

Functions

__STATIC_INLINE uint32_t LL_RNG_ReadRandData32 (RNG_TypeDef *RNGx)
Return32-bit Random Number value.

Function Documentation

__STATIC_INLINE uint32_t LL_RNG_ReadRandData32 ( RNG_TypeDef * RNGx )

Return32-bit Random Number value.

Reference Manual to LL API cross reference:
DR RNDATA LL_RNG_ReadRandData32
Parameters:
RNGx RNG Instance
Return values:
Generated 32-bit random value

Definition at line 314 of file stm32l4xx_ll_rng.h.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RNG Exported Functions

Functions

ErrorStatus LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).

Function Documentation

ErrorStatus LL_RNG_DeInit ( RNG_TypeDef * RNGx )

De-initialize RNG registers (Registers restored to their default values).

Parameters:
RNGx RNG Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RNG registers are de-initialized
  • ERROR: not applicable

Definition at line 81 of file stm32l4xx_ll_rng.c.

References assert_param, LL_AHB2_GRP1_ForceReset(), LL_AHB2_GRP1_PERIPH_RNG, and LL_AHB2_GRP1_ReleaseReset().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC

Modules
RTC
STM32L4xx_LL_Driver

Modules

RTC Private Constants
RTC Private Macros
RTC Exported Init structure
RTC Exported Constants
RTC Exported Macros
RTC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for RTC registers.

Register | Bit | Function
ALRMAR | DT | LL_RTC_ALMA_GetDay
 |  | LL_RTC_ALMA_SetDay
 | DU | LL_RTC_ALMA_GetDay
 |  | LL_RTC_ALMA_GetWeekDay
 |  | LL_RTC_ALMA_SetDay
 |  | LL_RTC_ALMA_SetWeekDay
 | HT | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetHour
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetHour
 | HU | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetHour
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetHour
 | MNT | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetMinute
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetMinute
 | MNU | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetMinute
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetMinute
 | MSK1 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | MSK2 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | MSK3 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | MSK4 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | PM | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetTimeFormat
 |  | LL_RTC_ALMA_SetTimeFormat
 | ST | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetSecond
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetSecond
 | SU | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetSecond
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetSecond
 | WDSEL | LL_RTC_ALMA_DisableWeekday
 |  | LL_RTC_ALMA_EnableWeekday
ALRMASSR | MASKSS | LL_RTC_ALMA_GetSubSecondMask
 |  | LL_RTC_ALMA_SetSubSecondMask
 | SS | LL_RTC_ALMA_GetSubSecond
 |  | LL_RTC_ALMA_SetSubSecond
ALRMBR | DT | LL_RTC_ALMB_GetDay
 |  | LL_RTC_ALMB_SetDay
 | DU | LL_RTC_ALMB_GetDay
 |  | LL_RTC_ALMB_GetWeekDay
 |  | LL_RTC_ALMB_SetDay
 |  | LL_RTC_ALMB_SetWeekDay
 | HT | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetHour
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetHour
 | HU | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetHour
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetHour
 | MNT | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetMinute
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetMinute
 | MNU | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetMinute
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetMinute
 | MSK1 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | MSK2 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | MSK3 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | MSK4 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | PM | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetTimeFormat
 |  | LL_RTC_ALMB_SetTimeFormat
 | ST | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetSecond
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetSecond
 | SU | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetSecond
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetSecond
 | WDSEL | LL_RTC_ALMB_DisableWeekday
 |  | LL_RTC_ALMB_EnableWeekday
ALRMBSSR | MASKSS | LL_RTC_ALMB_GetSubSecondMask
 |  | LL_RTC_ALMB_SetSubSecondMask
 | SS | LL_RTC_ALMB_GetSubSecond
 |  | LL_RTC_ALMB_SetSubSecond
BKPxR | BKP | LL_RTC_BAK_GetRegister
 |  | LL_RTC_BAK_SetRegister
CALR | CALM | LL_RTC_CAL_GetMinus
 |  | LL_RTC_CAL_SetMinus
 | CALP | LL_RTC_CAL_IsPulseInserted
 |  | LL_RTC_CAL_SetPulse
 | CALW16 | LL_RTC_CAL_GetPeriod
 |  | LL_RTC_CAL_SetPeriod
 | CALW8 | LL_RTC_CAL_GetPeriod
 |  | LL_RTC_CAL_SetPeriod
CR | ADD1H | LL_RTC_TIME_IncHour
 | ALRAE | LL_RTC_ALMA_Disable
 |  | LL_RTC_ALMA_Enable
 | ALRAIE | LL_RTC_DisableIT_ALRA
 |  | LL_RTC_EnableIT_ALRA
 |  | LL_RTC_IsEnabledIT_ALRA
 | ALRBE | LL_RTC_ALMB_Disable
 |  | LL_RTC_ALMB_Enable
 | ALRBIE | LL_RTC_DisableIT_ALRB
 |  | LL_RTC_EnableIT_ALRB
 |  | LL_RTC_IsEnabledIT_ALRB
 | BCK | LL_RTC_TIME_DisableDayLightStore
 |  | LL_RTC_TIME_EnableDayLightStore
 |  | LL_RTC_TIME_IsDayLightStoreEnabled
 | BYPSHAD | LL_RTC_DisableShadowRegBypass
 |  | LL_RTC_EnableShadowRegBypass
 |  | LL_RTC_IsShadowRegBypassEnabled
 | COE | LL_RTC_CAL_GetOutputFreq
 |  | LL_RTC_CAL_SetOutputFreq
 | COSEL | LL_RTC_CAL_GetOutputFreq
 |  | LL_RTC_CAL_SetOutputFreq
 | FMT | LL_RTC_GetHourFormat
 |  | LL_RTC_SetHourFormat
 | ITSE | LL_RTC_TS_DisableInternalEvent
 |  | LL_RTC_TS_EnableInternalEvent
 | OSEL | LL_RTC_GetAlarmOutEvent
 |  | LL_RTC_SetAlarmOutEvent
 | POL | LL_RTC_GetOutputPolarity
 |  | LL_RTC_SetOutputPolarity
 | REFCKON | LL_RTC_DisableRefClock
 |  | LL_RTC_EnableRefClock
 | SUB1H | LL_RTC_TIME_DecHour
 | TSE | LL_RTC_TS_Disable
 |  | LL_RTC_TS_Enable
 | TSEDGE | LL_RTC_TS_GetActiveEdge
 |  | LL_RTC_TS_SetActiveEdge
 | TSIE | LL_RTC_DisableIT_TS
 |  | LL_RTC_EnableIT_TS
 |  | LL_RTC_IsEnabledIT_TS
 | WUCKSEL | LL_RTC_WAKEUP_GetClock
 |  | LL_RTC_WAKEUP_SetClock
 | WUTE | LL_RTC_WAKEUP_Disable
 |  | LL_RTC_WAKEUP_Enable
 |  | LL_RTC_WAKEUP_IsEnabled
 | WUTIE | LL_RTC_DisableIT_WUT
 |  | LL_RTC_EnableIT_WUT
 |  | LL_RTC_IsEnabledIT_WUT
DR | DT | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetDay
 |  | LL_RTC_DATE_SetDay
 | DU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetDay
 |  | LL_RTC_DATE_SetDay
 | MT | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetMonth
 |  | LL_RTC_DATE_SetMonth
 | MU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetMonth
 |  | LL_RTC_DATE_SetMonth
 | WDU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetWeekDay
 |  | LL_RTC_DATE_SetWeekDay
 | YT | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetYear
 |  | LL_RTC_DATE_SetYear
 | YU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetYear
 |  | LL_RTC_DATE_SetYear
ISR | ALRAF | LL_RTC_ClearFlag_ALRA
 |  | LL_RTC_IsActiveFlag_ALRA
 | ALRAWF | LL_RTC_IsActiveFlag_ALRAW
 | ALRBF | LL_RTC_ClearFlag_ALRB
 |  | LL_RTC_IsActiveFlag_ALRB
 | ALRBWF | LL_RTC_IsActiveFlag_ALRBW
 | INIT | LL_RTC_DisableInitMode
 |  | LL_RTC_EnableInitMode
 | INITF | LL_RTC_IsActiveFlag_INIT
 | INITS | LL_RTC_IsActiveFlag_INITS
 | ITSF | LL_RTC_ClearFlag_ITS
 |  | LL_RTC_IsActiveFlag_ITS
 | RECALPF | LL_RTC_IsActiveFlag_RECALP
 | RSF | LL_RTC_ClearFlag_RS
 |  | LL_RTC_IsActiveFlag_RS
 | SHPF | LL_RTC_IsActiveFlag_SHP
 | TAMP1F | LL_RTC_ClearFlag_TAMP1
 |  | LL_RTC_IsActiveFlag_TAMP1
 | TAMP2F | LL_RTC_ClearFlag_TAMP2
 |  | LL_RTC_IsActiveFlag_TAMP2
 | TAMP3F | LL_RTC_ClearFlag_TAMP3
 |  | LL_RTC_IsActiveFlag_TAMP3
 | TSF | LL_RTC_ClearFlag_TS
 |  | LL_RTC_IsActiveFlag_TS
 | TSOVF | LL_RTC_ClearFlag_TSOV
 |  | LL_RTC_IsActiveFlag_TSOV
 | WUTF | LL_RTC_ClearFlag_WUT
 |  | LL_RTC_IsActiveFlag_WUT
 | WUTWF | LL_RTC_IsActiveFlag_WUTW
OR | ALARMOUTTYPE | LL_RTC_GetAlarmOutputType
 |  | LL_RTC_SetAlarmOutputType
 | OUT_RMP | LL_RTC_DisableOutRemap
 |  | LL_RTC_EnableOutRemap
PRER | PREDIV_A | LL_RTC_GetAsynchPrescaler
 |  | LL_RTC_SetAsynchPrescaler
 | PREDIV_S | LL_RTC_GetSynchPrescaler
 |  | LL_RTC_SetSynchPrescaler
SHIFTR | ADD1S | LL_RTC_TIME_Synchronize
 | SUBFS | LL_RTC_TIME_Synchronize
SSR | SS | LL_RTC_TIME_GetSubSecond
TAMPCR | TAMP1E | LL_RTC_TAMPER_Disable
 |  | LL_RTC_TAMPER_Enable
 | TAMP1IE | LL_RTC_DisableIT_TAMP1
 |  | LL_RTC_EnableIT_TAMP1
 |  | LL_RTC_IsEnabledIT_TAMP1
 | TAMP1MF | LL_RTC_TAMPER_DisableMask
 |  | LL_RTC_TAMPER_EnableMask
 | TAMP1NOERASE | LL_RTC_TAMPER_DisableEraseBKP
 |  | LL_RTC_TAMPER_EnableEraseBKP
 | TAMP1TRG | LL_RTC_TAMPER_DisableActiveLevel
 |  | LL_RTC_TAMPER_EnableActiveLevel
 | TAMP2E | LL_RTC_TAMPER_Disable
 |  | LL_RTC_TAMPER_Enable
 | TAMP2IE | LL_RTC_DisableIT_TAMP2
 |  | LL_RTC_EnableIT_TAMP2
 |  | LL_RTC_IsEnabledIT_TAMP2
 | TAMP2MF | LL_RTC_TAMPER_DisableMask
 |  | LL_RTC_TAMPER_EnableMask
 | TAMP2NOERASE | LL_RTC_TAMPER_DisableEraseBKP
 |  | LL_RTC_TAMPER_EnableEraseBKP
 | TAMP2TRG | LL_RTC_TAMPER_DisableActiveLevel
 |  | LL_RTC_TAMPER_EnableActiveLevel
 | TAMP3E | LL_RTC_TAMPER_Disable
 |  | LL_RTC_TAMPER_Enable
 | TAMP3IE | LL_RTC_DisableIT_TAMP3
 |  | LL_RTC_EnableIT_TAMP3
 |  | LL_RTC_IsEnabledIT_TAMP3
 | TAMP3MF | LL_RTC_TAMPER_DisableMask
 |  | LL_RTC_TAMPER_EnableMask
 | TAMP3NOERASE | LL_RTC_TAMPER_DisableEraseBKP
 |  | LL_RTC_TAMPER_EnableEraseBKP
 | TAMP3TRG | LL_RTC_TAMPER_DisableActiveLevel
 |  | LL_RTC_TAMPER_EnableActiveLevel
 | TAMPFLT | LL_RTC_TAMPER_GetFilterCount
 |  | LL_RTC_TAMPER_SetFilterCount
 | TAMPFREQ | LL_RTC_TAMPER_GetSamplingFreq
 |  | LL_RTC_TAMPER_SetSamplingFreq
 | TAMPIE | LL_RTC_DisableIT_TAMP
 |  | LL_RTC_EnableIT_TAMP
 |  | LL_RTC_IsEnabledIT_TAMP
 | TAMPPRCH | LL_RTC_TAMPER_GetPrecharge
 |  | LL_RTC_TAMPER_SetPrecharge
 | TAMPPUDIS | LL_RTC_TAMPER_DisablePullUp
 |  | LL_RTC_TAMPER_EnablePullUp
 | TAMPTS | LL_RTC_TS_DisableOnTamper
 |  | LL_RTC_TS_EnableOnTamper
TR | HT | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetHour
 |  | LL_RTC_TIME_SetHour
 | HU | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetHour
 |  | LL_RTC_TIME_SetHour
 | MNT | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetMinute
 |  | LL_RTC_TIME_SetMinute
 | MNU | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetMinute
 |  | LL_RTC_TIME_SetMinute
 | PM | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_GetFormat
 |  | LL_RTC_TIME_SetFormat
 | ST | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetSecond
 |  | LL_RTC_TIME_SetSecond
 | SU | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetSecond
 |  | LL_RTC_TIME_SetSecond
TSDR | DT | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetDay
 | DU | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetDay
 | MT | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetMonth
 | MU | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetMonth
 | WDU | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetWeekDay
TSSSR | SS | LL_RTC_TS_GetSubSecond
TSTR | HT | LL_RTC_TS_GetHour
 |  | LL_RTC_TS_GetTime
 | HU | LL_RTC_TS_GetHour
 |  | LL_RTC_TS_GetTime
 | MNT | LL_RTC_TS_GetMinute
 |  | LL_RTC_TS_GetTime
 | MNU | LL_RTC_TS_GetMinute
 |  | LL_RTC_TS_GetTime
 | PM | LL_RTC_TS_GetTimeFormat
 | ST | LL_RTC_TS_GetSecond
 |  | LL_RTC_TS_GetTime
 | SU | LL_RTC_TS_GetSecond
 |  | LL_RTC_TS_GetTime
WPR | KEY | LL_RTC_DisableWriteProtection
 |  | LL_RTC_EnableWriteProtection
WUTR | WUT | LL_RTC_WAKEUP_GetAutoReload
 |  | LL_RTC_WAKEUP_SetAutoReload
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU)
#define | RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU)
#define | RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define | RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
#define | RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
#define | RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
#define | RTC_POSITION_TR_HT (uint32_t)POSITION_VAL(RTC_TR_HT)
#define | RTC_POSITION_TR_HU (uint32_t)POSITION_VAL(RTC_TR_HU)
#define | RTC_POSITION_TR_MT (uint32_t)POSITION_VAL(RTC_TR_MNT)
#define | RTC_POSITION_TR_MU (uint32_t)POSITION_VAL(RTC_TR_MNU)
#define | RTC_POSITION_TR_ST (uint32_t)POSITION_VAL(RTC_TR_ST)
#define | RTC_POSITION_TR_SU (uint32_t)POSITION_VAL(RTC_TR_SU)
#define | RTC_POSITION_DR_YT (uint32_t)POSITION_VAL(RTC_DR_YT)
#define | RTC_POSITION_DR_YU (uint32_t)POSITION_VAL(RTC_DR_YU)
#define | RTC_POSITION_DR_MT (uint32_t)POSITION_VAL(RTC_DR_MT)
#define | RTC_POSITION_DR_MU (uint32_t)POSITION_VAL(RTC_DR_MU)
#define | RTC_POSITION_DR_DT (uint32_t)POSITION_VAL(RTC_DR_DT)
#define | RTC_POSITION_DR_DU (uint32_t)POSITION_VAL(RTC_DR_DU)
#define | RTC_POSITION_DR_WDU (uint32_t)POSITION_VAL(RTC_DR_WDU)
#define | RTC_POSITION_ALMA_DT (uint32_t)POSITION_VAL(RTC_ALRMAR_DT)
#define | RTC_POSITION_ALMA_DU (uint32_t)POSITION_VAL(RTC_ALRMAR_DU)
#define | RTC_POSITION_ALMA_HT (uint32_t)POSITION_VAL(RTC_ALRMAR_HT)
#define | RTC_POSITION_ALMA_HU (uint32_t)POSITION_VAL(RTC_ALRMAR_HU)
#define | RTC_POSITION_ALMA_MT (uint32_t)POSITION_VAL(RTC_ALRMAR_MNT)
#define | RTC_POSITION_ALMA_MU (uint32_t)POSITION_VAL(RTC_ALRMAR_MNU)
#define | RTC_POSITION_ALMA_SU (uint32_t)POSITION_VAL(RTC_ALRMAR_SU)
#define | RTC_POSITION_ALMA_ST (uint32_t)POSITION_VAL(RTC_ALRMAR_ST)
#define | RTC_POSITION_ALMB_DT (uint32_t)POSITION_VAL(RTC_ALRMBR_DT)
#define | RTC_POSITION_ALMB_DU (uint32_t)POSITION_VAL(RTC_ALRMBR_DU)
#define | RTC_POSITION_ALMB_HT (uint32_t)POSITION_VAL(RTC_ALRMBR_HT)
#define | RTC_POSITION_ALMB_HU (uint32_t)POSITION_VAL(RTC_ALRMBR_HU)
#define | RTC_POSITION_ALMB_MT (uint32_t)POSITION_VAL(RTC_ALRMBR_MNT)
#define | RTC_POSITION_ALMB_MU (uint32_t)POSITION_VAL(RTC_ALRMBR_MNU)
#define | RTC_POSITION_ALMB_SU (uint32_t)POSITION_VAL(RTC_ALRMBR_SU)
#define | RTC_POSITION_ALMB_ST (uint32_t)POSITION_VAL(RTC_ALRMBR_ST)
#define | RTC_POSITION_PRER_PREDIV_A (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)
#define | RTC_POSITION_ALMA_MASKSS (uint32_t)POSITION_VAL(RTC_ALRMASSR_MASKSS)
#define | RTC_POSITION_ALMB_MASKSS (uint32_t)POSITION_VAL(RTC_ALRMBSSR_MASKSS)
#define | RTC_POSITION_TS_HU (uint32_t)POSITION_VAL(RTC_TSTR_HU)
#define | RTC_POSITION_TS_MNU (uint32_t)POSITION_VAL(RTC_TSTR_MNU)
#define | RTC_POSITION_TS_WDU (uint32_t)POSITION_VAL(RTC_TSDR_WDU)
#define | RTC_POSITION_TS_MU (uint32_t)POSITION_VAL(RTC_TSDR_MU)
#define | RTC_OFFSET_WEEKDAY (uint32_t)24U
#define | RTC_OFFSET_DAY (uint32_t)16U
#define | RTC_OFFSET_MONTH (uint32_t)8U
#define | RTC_OFFSET_HOUR (uint32_t)16U
#define | RTC_OFFSET_MINUTE (uint32_t)8U

Define Documentation

#define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU)

Definition at line 65 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_StructInit().

#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)

Definition at line 66 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_EnableInitMode().

#define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */

Definition at line 69 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_EnterInitMode().

#define RTC_OFFSET_DAY (uint32_t)16U

Definition at line 114 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_HOUR (uint32_t)16U

Definition at line 116 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MINUTE (uint32_t)8U

Definition at line 117 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MONTH (uint32_t)8U

Definition at line 115 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_WEEKDAY (uint32_t)24U

Definition at line 113 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_POSITION_ALMA_DT (uint32_t)POSITION_VAL(RTC_ALRMAR_DT)

Definition at line 88 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetDay(), and LL_RTC_ALMA_SetDay().

#define RTC_POSITION_ALMA_DU (uint32_t)POSITION_VAL(RTC_ALRMAR_DU)

Definition at line 89 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetDay(), LL_RTC_ALMA_GetWeekDay(), LL_RTC_ALMA_SetDay(), and LL_RTC_ALMA_SetWeekDay().

#define RTC_POSITION_ALMA_HT (uint32_t)POSITION_VAL(RTC_ALRMAR_HT)

Definition at line 90 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_GetHour(), and LL_RTC_ALMA_SetHour().

#define RTC_POSITION_ALMA_HU (uint32_t)POSITION_VAL(RTC_ALRMAR_HU)

Definition at line 91 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_GetHour(), and LL_RTC_ALMA_SetHour().

#define RTC_POSITION_ALMA_MASKSS (uint32_t)POSITION_VAL(RTC_ALRMASSR_MASKSS)

Definition at line 105 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetSubSecondMask(), and LL_RTC_ALMA_SetSubSecondMask().

#define RTC_POSITION_ALMA_MT (uint32_t)POSITION_VAL(RTC_ALRMAR_MNT)

Definition at line 92 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_GetMinute(), and LL_RTC_ALMA_SetMinute().

#define RTC_POSITION_ALMA_MU (uint32_t)POSITION_VAL(RTC_ALRMAR_MNU)

Definition at line 93 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_GetMinute(), and LL_RTC_ALMA_SetMinute().

#define RTC_POSITION_ALMA_ST (uint32_t)POSITION_VAL(RTC_ALRMAR_ST)

Definition at line 95 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_GetSecond(), and LL_RTC_ALMA_SetSecond().

#define RTC_POSITION_ALMA_SU (uint32_t)POSITION_VAL(RTC_ALRMAR_SU)

Definition at line 94 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_GetSecond(), and LL_RTC_ALMA_SetSecond().

#define RTC_POSITION_ALMB_DT (uint32_t)POSITION_VAL(RTC_ALRMBR_DT)

Definition at line 96 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetDay(), and LL_RTC_ALMB_SetDay().

#define RTC_POSITION_ALMB_DU (uint32_t)POSITION_VAL(RTC_ALRMBR_DU)

Definition at line 97 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetDay(), LL_RTC_ALMB_GetWeekDay(), LL_RTC_ALMB_SetDay(), and LL_RTC_ALMB_SetWeekDay().

#define RTC_POSITION_ALMB_HT (uint32_t)POSITION_VAL(RTC_ALRMBR_HT)

Definition at line 98 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_GetHour(), and LL_RTC_ALMB_SetHour().

#define RTC_POSITION_ALMB_HU (uint32_t)POSITION_VAL(RTC_ALRMBR_HU)

Definition at line 99 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_GetHour(), and LL_RTC_ALMB_SetHour().

#define RTC_POSITION_ALMB_MASKSS (uint32_t)POSITION_VAL(RTC_ALRMBSSR_MASKSS)

Definition at line 106 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetSubSecondMask(), and LL_RTC_ALMB_SetSubSecondMask().

#define RTC_POSITION_ALMB_MT (uint32_t)POSITION_VAL(RTC_ALRMBR_MNT)

Definition at line 100 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_GetMinute(), and LL_RTC_ALMB_SetMinute().

#define RTC_POSITION_ALMB_MU (uint32_t)POSITION_VAL(RTC_ALRMBR_MNU)

Definition at line 101 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_GetMinute(), and LL_RTC_ALMB_SetMinute().

#define RTC_POSITION_ALMB_ST (uint32_t)POSITION_VAL(RTC_ALRMBR_ST)

Definition at line 103 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_GetSecond(), and LL_RTC_ALMB_SetSecond().

#define RTC_POSITION_ALMB_SU (uint32_t)POSITION_VAL(RTC_ALRMBR_SU)

Definition at line 102 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_GetSecond(), and LL_RTC_ALMB_SetSecond().

#define RTC_POSITION_DR_DT (uint32_t)POSITION_VAL(RTC_DR_DT)

Definition at line 85 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Config(), LL_RTC_DATE_GetDay(), and LL_RTC_DATE_SetDay().

#define RTC_POSITION_DR_DU (uint32_t)POSITION_VAL(RTC_DR_DU)

Definition at line 86 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Config(), LL_RTC_DATE_GetDay(), and LL_RTC_DATE_SetDay().

#define RTC_POSITION_DR_MT (uint32_t)POSITION_VAL(RTC_DR_MT)

Definition at line 83 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Config(), LL_RTC_DATE_GetMonth(), and LL_RTC_DATE_SetMonth().

#define RTC_POSITION_DR_MU (uint32_t)POSITION_VAL(RTC_DR_MU)

Definition at line 84 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Config(), LL_RTC_DATE_GetMonth(), and LL_RTC_DATE_SetMonth().

#define RTC_POSITION_DR_WDU (uint32_t)POSITION_VAL(RTC_DR_WDU)

Definition at line 87 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Config(), LL_RTC_DATE_GetWeekDay(), and LL_RTC_DATE_SetWeekDay().

#define RTC_POSITION_DR_YT (uint32_t)POSITION_VAL(RTC_DR_YT)

Definition at line 81 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Config(), LL_RTC_DATE_GetYear(), and LL_RTC_DATE_SetYear().

#define RTC_POSITION_DR_YU (uint32_t)POSITION_VAL(RTC_DR_YU)

Definition at line 82 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Config(), LL_RTC_DATE_GetYear(), and LL_RTC_DATE_SetYear().

#define RTC_POSITION_PRER_PREDIV_A (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)

Definition at line 104 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_GetAsynchPrescaler(), and LL_RTC_SetAsynchPrescaler().

#define RTC_POSITION_TR_HT (uint32_t)POSITION_VAL(RTC_TR_HT)

Definition at line 75 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TIME_Config(), LL_RTC_TIME_GetHour(), and LL_RTC_TIME_SetHour().

#define RTC_POSITION_TR_HU (uint32_t)POSITION_VAL(RTC_TR_HU)

Definition at line 76 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TIME_Config(), LL_RTC_TIME_GetHour(), and LL_RTC_TIME_SetHour().

#define RTC_POSITION_TR_MT (uint32_t)POSITION_VAL(RTC_TR_MNT)

Definition at line 77 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TIME_Config(), LL_RTC_TIME_GetMinute(), and LL_RTC_TIME_SetMinute().

#define RTC_POSITION_TR_MU (uint32_t)POSITION_VAL(RTC_TR_MNU)

Definition at line 78 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TIME_Config(), LL_RTC_TIME_GetMinute(), and LL_RTC_TIME_SetMinute().

#define RTC_POSITION_TR_ST (uint32_t)POSITION_VAL(RTC_TR_ST)

Definition at line 79 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TIME_Config(), LL_RTC_TIME_GetSecond(), and LL_RTC_TIME_SetSecond().

#define RTC_POSITION_TR_SU (uint32_t)POSITION_VAL(RTC_TR_SU)

Definition at line 80 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TIME_Config(), LL_RTC_TIME_GetSecond(), and LL_RTC_TIME_SetSecond().

#define RTC_POSITION_TS_HU (uint32_t)POSITION_VAL(RTC_TSTR_HU)

Definition at line 107 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TS_GetHour().

#define RTC_POSITION_TS_MNU (uint32_t)POSITION_VAL(RTC_TSTR_MNU)

Definition at line 108 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TS_GetMinute().

#define RTC_POSITION_TS_MU (uint32_t)POSITION_VAL(RTC_TSDR_MU)

Definition at line 110 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TS_GetMonth().

#define RTC_POSITION_TS_WDU (uint32_t)POSITION_VAL(RTC_TSDR_WDU)

Definition at line 109 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TS_GetWeekDay().

#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)

Definition at line 67 of file stm32l4xx_ll_rtc.h.

#define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU)

Definition at line 66 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_DeInit(), and LL_RTC_StructInit().

#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */

Definition at line 70 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_WaitForSynchro().

#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)

Definition at line 70 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_EnableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)

Definition at line 71 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)

Definition at line 72 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Private Macros

Defines
RTC Private Macros
RTC

Defines

#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
#define | IS_LL_RTC_MONTH(__VALUE__)
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Define Documentation

#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 138 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMA_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))

Definition at line 123 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 141 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ALMB_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))

Definition at line 130 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ASYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= (uint32_t)0x7FU)

Definition at line 83 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_DAY ( __DAY__ ) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))

Definition at line 106 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_FORMAT_BIN) \
                                  || ((__VALUE__) == LL_RTC_FORMAT_BCD))

Definition at line 87 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR12 ( __HOUR__ ) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))

Definition at line 93 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR24 ( __HOUR__ ) ((__HOUR__) <= 23U)

Definition at line 94 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOURFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
                                      || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))

Definition at line 80 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_MINUTES ( __MINUTES__ ) ((__MINUTES__) <= 59U)

Definition at line 95 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_MONTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_MONTH_JANUARY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
                                 || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
                                 || ((__VALUE__) == LL_RTC_MONTH_MAY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
                                 || ((__VALUE__) == LL_RTC_MONTH_JULY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
                                 || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))

Definition at line 108 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

#define IS_LL_RTC_SECONDS ( __SECONDS__ ) ((__SECONDS__) <= 59U)

Definition at line 96 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_SYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= (uint32_t)0x7FFFU)

Definition at line 85 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_TIME_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
                                       || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))

Definition at line 90 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_WEEKDAY ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))

Definition at line 98 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_YEAR ( __YEAR__ ) ((__YEAR__) <= 99U)

Definition at line 121 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_InitTypeDef Struct Reference
RTC Exported Init structure

RTC Init structures definition. More...

#include <stm32l4xx_ll_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrescaler
uint32_t | SynchPrescaler

Detailed Description

RTC Init structures definition.

Definition at line 142 of file stm32l4xx_ll_rtc.h.

Field Documentation

uint32_t LL_RTC_InitTypeDef::AsynchPrescaler

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

This feature can be modified afterwards using unitary function LL_RTC_SetAsynchPrescaler().

Definition at line 150 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::HourFormat

Specifies the RTC Hours Format. This parameter can be a value of HOUR FORMAT

This feature can be modified afterwards using unitary function LL_RTC_SetHourFormat().

Definition at line 144 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::SynchPrescaler

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

This feature can be modified afterwards using unitary function LL_RTC_SetSynchPrescaler().

Definition at line 156 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_rtc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_TimeTypeDef Struct Reference
RTC Exported Init structure

RTC Time structure definition. More...

#include <stm32l4xx_ll_rtc.h>

Data Fields

uint32_t | TimeFormat
uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds

Detailed Description

RTC Time structure definition.

Definition at line 166 of file stm32l4xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_TimeTypeDef::Hours

Specifies the RTC Time Hours. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the LL_RTC_TIME_FORMAT_PM is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the LL_RTC_TIME_FORMAT_AM_OR_24 is selected.

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetHour().

Definition at line 173 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetMinute().

Definition at line 179 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetSecond().

Definition at line 184 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint32_t LL_RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of TIME FORMAT

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetFormat().

Definition at line 168 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_rtc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_DateTypeDef Struct Reference
RTC Exported Init structure

RTC Date structure definition. More...

#include <stm32l4xx_ll_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Day
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 193 of file stm32l4xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_DateTypeDef::Day

Specifies the RTC Date Day. This parameter must be a number between Min_Data = 1 and Max_Data = 31

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetDay().

Definition at line 205 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Month

Specifies the RTC Date Month. This parameter can be a value of MONTH

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetMonth().

Definition at line 200 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of WEEK DAY

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetWeekDay().

Definition at line 195 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetYear().

Definition at line 210 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_rtc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_AlarmTypeDef Struct Reference
RTC Exported Init structure

RTC Alarm structure definition. More...

#include <stm32l4xx_ll_rtc.h>

Data Fields

LL_RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay

Detailed Description

RTC Alarm structure definition.

Definition at line 219 of file stm32l4xx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Day/WeekDay. If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetDay() for ALARM A or LL_RTC_ALMB_SetDay() for ALARM B.

If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of WEEK DAY.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetWeekDay() for ALARM A or LL_RTC_ALMB_SetWeekDay() for ALARM B.

Definition at line 237 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on day or WeekDay. This parameter can be a value of RTC Alarm A Date WeekDay for ALARM A or RTC Alarm B Date WeekDay for ALARM B

This feature can be modified afterwards using unitary function LL_RTC_ALMA_EnableWeekday() or LL_RTC_ALMA_DisableWeekday() for ALARM A or LL_RTC_ALMB_EnableWeekday() or LL_RTC_ALMB_DisableWeekday() for ALARM B

Definition at line 230 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of ALARMA MASK for ALARM A or ALARMB MASK for ALARM B.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetMask() for ALARM A or LL_RTC_ALMB_SetMask() for ALARM B

Definition at line 223 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

LL_RTC_TimeTypeDef LL_RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members.

Definition at line 221 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_rtc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FORMAT

Defines
FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_FORMAT_BIN ((uint32_t)0x000000000U)
#define | LL_RTC_FORMAT_BCD ((uint32_t)0x000000001U)

Define Documentation

#define LL_RTC_FORMAT_BCD ((uint32_t)0x000000001U)

BCD data format

Definition at line 265 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_FORMAT_BIN ((uint32_t)0x000000000U)

Binary data format

Definition at line 264 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Alarm A Date WeekDay

Defines
RTC Alarm A Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)

Alarm A Date is selected

Definition at line 273 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), and LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Alarm A WeekDay is selected

Definition at line 274 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Alarm B Date WeekDay

Defines
RTC Alarm B Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Define Documentation

#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)

Alarm B Date is selected

Definition at line 282 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Alarm B WeekDay is selected

Definition at line 283 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RTC Exported Constants

Flags defines which can be used with LL_RTC_ReadReg function. More...

Defines

#define | LL_RTC_ISR_ITSF RTC_ISR_ITSF
#define | LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
#define | LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
#define | LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
#define | LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
#define | LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
#define | LL_RTC_ISR_TSF RTC_ISR_TSF
#define | LL_RTC_ISR_WUTF RTC_ISR_WUTF
#define | LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
#define | LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
#define | LL_RTC_ISR_INITF RTC_ISR_INITF
#define | LL_RTC_ISR_RSF RTC_ISR_RSF
#define | LL_RTC_ISR_INITS RTC_ISR_INITS
#define | LL_RTC_ISR_SHPF RTC_ISR_SHPF
#define | LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
#define | LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
#define | LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF

Detailed Description

Flags defines which can be used with LL_RTC_ReadReg function.

Define Documentation

#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF

Definition at line 303 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF

Definition at line 310 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF

Definition at line 302 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF

Definition at line 309 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_INITF RTC_ISR_INITF

Definition at line 304 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_INITS RTC_ISR_INITS

Definition at line 306 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_ITSF RTC_ISR_ITSF

Definition at line 294 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF

Definition at line 295 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_RSF RTC_ISR_RSF

Definition at line 305 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_SHPF RTC_ISR_SHPF

Definition at line 307 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F

Definition at line 298 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F

Definition at line 297 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F

Definition at line 296 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_TSF RTC_ISR_TSF

Definition at line 300 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF

Definition at line 299 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_WUTF RTC_ISR_WUTF

Definition at line 301 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF

Definition at line 308 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
RTC Exported Constants

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions. More...

Defines

#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
#define | LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE
#define | LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE
#define | LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE
#define | LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE

Detailed Description

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

Define Documentation

#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE

Definition at line 322 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE

Definition at line 321 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_CR_TSIE RTC_CR_TSIE

Definition at line 319 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_CR_WUTIE RTC_CR_WUTIE

Definition at line 320 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE

Definition at line 325 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE

Definition at line 324 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE

Definition at line 323 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE

Definition at line 326 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: WEEK DAY

Defines
WEEK DAY
RTC Exported Constants

Defines

#define | LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Define Documentation

#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)

Friday

Definition at line 338 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)

Monday

Definition at line 334 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)

Saturday

Definition at line 339 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Sunday

Definition at line 340 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)

Thrusday

Definition at line 337 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)

Tuesday

Definition at line 335 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)

Wednesday

Definition at line 336 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: MONTH

Defines
MONTH
RTC Exported Constants

Defines

#define | LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | LL_RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | LL_RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | LL_RTC_MONTH_MAY ((uint8_t)0x05U)
#define | LL_RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | LL_RTC_MONTH_JULY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Define Documentation

#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U)

April

Definition at line 351 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)

August

Definition at line 355 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)

December

Definition at line 359 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)

February

Definition at line 349 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)

January

Definition at line 348 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_MONTH_JULY ((uint8_t)0x07U)

July

Definition at line 354 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U)

June

Definition at line 353 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U)

March

Definition at line 350 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_MONTH_MAY ((uint8_t)0x05U)

May

Definition at line 352 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)

November

Definition at line 358 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)

October

Definition at line 357 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)

September

Definition at line 356 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HOUR FORMAT

Defines
HOUR FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_HOURFORMAT_24HOUR (uint32_t)0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

Define Documentation

#define LL_RTC_HOURFORMAT_24HOUR (uint32_t)0x00000000U

24 hour/day format

Definition at line 367 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_StructInit(), and LL_RTC_TIME_Init().

#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

AM/PM hour format

Definition at line 368 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: ALARM OUTPUT

Defines
ALARM OUTPUT
RTC Exported Constants

Defines

#define | LL_RTC_ALARMOUT_DISABLE ((uint32_t)0x00000000U)
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Define Documentation

#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0

Alarm A output enabled

Definition at line 377 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1

Alarm B output enabled

Definition at line 378 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_DISABLE ((uint32_t)0x00000000U)

Output disabled

Definition at line 376 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Wakeup output enabled

Definition at line 379 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: ALARM OUTPUT TYPE

Defines
ALARM OUTPUT TYPE
RTC Exported Constants

Defines

#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN (uint32_t)0x00000000U
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE

Define Documentation

#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN (uint32_t)0x00000000U

RTC_ALARM, when mapped on PC13, is open-drain output

Definition at line 387 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE

RTC_ALARM, when mapped on PC13, is push-pull output

Definition at line 388 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: OUTPUT POLARITY PIN

Defines
OUTPUT POLARITY PIN
RTC Exported Constants

Defines

#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH (uint32_t)0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Define Documentation

#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH (uint32_t)0x00000000U

Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 396 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 397 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: TIME FORMAT

Defines
TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TIME_FORMAT_AM_OR_24 (uint32_t)0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM

Define Documentation

#define LL_RTC_TIME_FORMAT_AM_OR_24 (uint32_t)0x00000000U

AM or 24-hour format

Definition at line 405 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_TIME_StructInit().

#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM

PM

Definition at line 406 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: SHIFT SECOND

Defines
SHIFT SECOND
RTC Exported Constants

Defines

#define | LL_RTC_SHIFT_SECOND_DELAY (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Define Documentation

#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Definition at line 415 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_SHIFT_SECOND_DELAY (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */

Definition at line 414 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: ALARMA MASK

Defines
ALARMA MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_MASK_NONE ((uint32_t)0x00000000U)
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Define Documentation

#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Masks all

Definition at line 428 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Date/day do not care in Alarm A comparison

Definition at line 424 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3

Hours do not care in Alarm A comparison

Definition at line 425 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2

Minutes do not care in Alarm A comparison

Definition at line 426 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_NONE ((uint32_t)0x00000000U)

No masks applied on Alarm A

Definition at line 423 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1

Seconds do not care in Alarm A comparison

Definition at line 427 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: ALARMA TIME FORMAT

Defines
ALARMA TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_TIME_FORMAT_AM (uint32_t)0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

Define Documentation

#define LL_RTC_ALMA_TIME_FORMAT_AM (uint32_t)0x00000000U

AM or 24-hour format

Definition at line 436 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

PM

Definition at line 437 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: ALARMB MASK

Defines
ALARMB MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_MASK_NONE ((uint32_t)0x00000000U)
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Define Documentation

#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Masks all

Definition at line 450 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4

Date/day do not care in Alarm B comparison

Definition at line 446 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3

Hours do not care in Alarm B comparison

Definition at line 447 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2

Minutes do not care in Alarm B comparison

Definition at line 448 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_NONE ((uint32_t)0x00000000U)

No masks applied on Alarm B

Definition at line 445 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1

Seconds do not care in Alarm B comparison

Definition at line 449 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: ALARMB TIME FORMAT

Defines
ALARMB TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_TIME_FORMAT_AM (uint32_t)0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

Define Documentation

#define LL_RTC_ALMB_TIME_FORMAT_AM (uint32_t)0x00000000U

AM or 24-hour format

Definition at line 458 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

PM

Definition at line 459 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: TIMESTAMP EDGE

Defines
TIMESTAMP EDGE
RTC Exported Constants

Defines

#define | LL_RTC_TIMESTAMP_EDGE_RISING (uint32_t)0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

RTC_TS input falling edge generates a time-stamp even

Definition at line 468 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TIMESTAMP_EDGE_RISING (uint32_t)0x00000000U

RTC_TS input rising edge generates a time-stamp event

Definition at line 467 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIMESTAMP TIME FORMAT

Defines
TIMESTAMP TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TS_TIME_FORMAT_AM (uint32_t)0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

Define Documentation

#define LL_RTC_TS_TIME_FORMAT_AM (uint32_t)0x00000000U

AM or 24-hour format

Definition at line 476 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

PM

Definition at line 477 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: TAMPER

Defines
TAMPER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

Define Documentation

#define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E

RTC_TAMP1 input detection

Definition at line 486 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E

RTC_TAMP2 input detection

Definition at line 489 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

RTC_TAMP3 input detection

Definition at line 492 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: TAMPER MASK

Defines
TAMPER MASK
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF
#define | LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF
#define | LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF

Define Documentation

#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF

Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased

Definition at line 502 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF

Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased.

Definition at line 505 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF

Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased

Definition at line 508 of file stm32l4xx_ll_rtc.h.

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STM32L486xx HAL User Manual: TAMPER NO ERASE

Defines
TAMPER NO ERASE
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE

Define Documentation

#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE

Tamper 1 event does not erase the backup registers.

Definition at line 518 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE

Tamper 2 event does not erase the backup registers.

Definition at line 521 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE

Tamper 3 event does not erase the backup registers.

Definition at line 524 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TAMPER DURATION

Defines
TAMPER DURATION
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_DURATION_1RTCCLK ((uint32_t)0x00000000U)
#define | LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH

Define Documentation

#define LL_RTC_TAMPER_DURATION_1RTCCLK ((uint32_t)0x00000000U)

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 534 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 535 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 536 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 537 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TAMPER FILTER

Defines
TAMPER FILTER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT

Define Documentation

#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 548 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 549 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active level.

Definition at line 550 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_DISABLE ((uint32_t)0x00000000U)

Tamper filter is disabled

Definition at line 547 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TAMPER SAMPLING FREQUENCY DIVIDER

Defines
TAMPER SAMPLING FREQUENCY DIVIDER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 ((uint32_t)0x00000000U)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ

Define Documentation

#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 565 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 561 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 564 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 567 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 ((uint32_t)0x00000000U)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 560 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 563 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 566 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 562 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TAMPER ACTIVE LEVEL

Defines
TAMPER ACTIVE LEVEL
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG

Define Documentation

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG

RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 577 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG

RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 580 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG

RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 583 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WAKEUP CLOCK DIV

Defines
WAKEUP CLOCK DIV
RTC Exported Constants

Defines

#define | LL_RTC_WAKEUPCLOCK_DIV_16 ((uint32_t)0x00000000U)
#define | LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1)
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

Define Documentation

#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2)

ck_spre (usually 1 Hz) clock is selected

Definition at line 596 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value

Definition at line 597 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_16 ((uint32_t)0x00000000U)

RTC/16 clock is selected

Definition at line 592 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)

RTC/2 clock is selected

Definition at line 595 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1)

RTC/4 clock is selected

Definition at line 594 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0)

RTC/8 clock is selected

Definition at line 593 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: BACKUP

Defines
BACKUP
RTC Exported Constants

Defines

#define | LL_RTC_BKP_DR0 ((uint32_t)0x00000000U)
#define | LL_RTC_BKP_DR1 ((uint32_t)0x00000001U)
#define | LL_RTC_BKP_DR2 ((uint32_t)0x00000002U)
#define | LL_RTC_BKP_DR3 ((uint32_t)0x00000003U)
#define | LL_RTC_BKP_DR4 ((uint32_t)0x00000004U)
#define | LL_RTC_BKP_DR5 ((uint32_t)0x00000005U)
#define | LL_RTC_BKP_DR6 ((uint32_t)0x00000006U)
#define | LL_RTC_BKP_DR7 ((uint32_t)0x00000007U)
#define | LL_RTC_BKP_DR8 ((uint32_t)0x00000008U)
#define | LL_RTC_BKP_DR9 ((uint32_t)0x00000009U)
#define | LL_RTC_BKP_DR10 ((uint32_t)0x0000000AU)
#define | LL_RTC_BKP_DR11 ((uint32_t)0x0000000BU)
#define | LL_RTC_BKP_DR12 ((uint32_t)0x0000000CU)
#define | LL_RTC_BKP_DR13 ((uint32_t)0x0000000DU)
#define | LL_RTC_BKP_DR14 ((uint32_t)0x0000000EU)
#define | LL_RTC_BKP_DR15 ((uint32_t)0x0000000FU)
#define | LL_RTC_BKP_DR16 ((uint32_t)0x00000010U)
#define | LL_RTC_BKP_DR17 ((uint32_t)0x00000011U)
#define | LL_RTC_BKP_DR18 ((uint32_t)0x00000012U)
#define | LL_RTC_BKP_DR19 ((uint32_t)0x00000013U)
#define | LL_RTC_BKP_DR20 ((uint32_t)0x00000014U)
#define | LL_RTC_BKP_DR21 ((uint32_t)0x00000015U)
#define | LL_RTC_BKP_DR22 ((uint32_t)0x00000016U)
#define | LL_RTC_BKP_DR23 ((uint32_t)0x00000017U)
#define | LL_RTC_BKP_DR24 ((uint32_t)0x00000018U)
#define | LL_RTC_BKP_DR25 ((uint32_t)0x00000019U)
#define | LL_RTC_BKP_DR26 ((uint32_t)0x0000001AU)
#define | LL_RTC_BKP_DR27 ((uint32_t)0x0000001BU)
#define | LL_RTC_BKP_DR28 ((uint32_t)0x0000001CU)
#define | LL_RTC_BKP_DR29 ((uint32_t)0x0000001DU)
#define | LL_RTC_BKP_DR30 ((uint32_t)0x0000001EU)
#define | LL_RTC_BKP_DR31 ((uint32_t)0x0000001FU)

Define Documentation

#define LL_RTC_BKP_DR0 ((uint32_t)0x00000000U)

Definition at line 606 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR1 ((uint32_t)0x00000001U)

Definition at line 607 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR10 ((uint32_t)0x0000000AU)

Definition at line 617 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR11 ((uint32_t)0x0000000BU)

Definition at line 618 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR12 ((uint32_t)0x0000000CU)

Definition at line 619 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR13 ((uint32_t)0x0000000DU)

Definition at line 620 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR14 ((uint32_t)0x0000000EU)

Definition at line 621 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR15 ((uint32_t)0x0000000FU)

Definition at line 622 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR16 ((uint32_t)0x00000010U)

Definition at line 626 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR17 ((uint32_t)0x00000011U)

Definition at line 627 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR18 ((uint32_t)0x00000012U)

Definition at line 628 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR19 ((uint32_t)0x00000013U)

Definition at line 629 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR2 ((uint32_t)0x00000002U)

Definition at line 608 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR20 ((uint32_t)0x00000014U)

Definition at line 633 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR21 ((uint32_t)0x00000015U)

Definition at line 634 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR22 ((uint32_t)0x00000016U)

Definition at line 635 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR23 ((uint32_t)0x00000017U)

Definition at line 636 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR24 ((uint32_t)0x00000018U)

Definition at line 637 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR25 ((uint32_t)0x00000019U)

Definition at line 638 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR26 ((uint32_t)0x0000001AU)

Definition at line 639 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR27 ((uint32_t)0x0000001BU)

Definition at line 640 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR28 ((uint32_t)0x0000001CU)

Definition at line 641 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR29 ((uint32_t)0x0000001DU)

Definition at line 642 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR3 ((uint32_t)0x00000003U)

Definition at line 609 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR30 ((uint32_t)0x0000001EU)

Definition at line 643 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR31 ((uint32_t)0x0000001FU)

Definition at line 644 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR4 ((uint32_t)0x00000004U)

Definition at line 610 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR5 ((uint32_t)0x00000005U)

Definition at line 612 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR6 ((uint32_t)0x00000006U)

Definition at line 613 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR7 ((uint32_t)0x00000007U)

Definition at line 614 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR8 ((uint32_t)0x00000008U)

Definition at line 615 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_BKP_DR9 ((uint32_t)0x00000009U)

Definition at line 616 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Calibration output

Defines
Calibration output
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_OUTPUT_NONE (uint32_t)0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE)

Define Documentation

#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)

Calibration output is 512 Hz

Definition at line 655 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE)

Calibration output is 1 Hz

Definition at line 656 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_NONE (uint32_t)0x00000000U

Calibration output disabled

Definition at line 654 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Calibration pulse insertion

Defines
Calibration pulse insertion
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_INSERTPULSE_NONE (uint32_t)0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

Define Documentation

#define LL_RTC_CALIB_INSERTPULSE_NONE (uint32_t)0x00000000U

No RTCCLK pulses are added

Definition at line 664 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm)

Definition at line 665 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Calibration period

Defines
Calibration period
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_PERIOD_32SEC (uint32_t)0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16

Use a 16-second calibration cycle period

Definition at line 674 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_32SEC (uint32_t)0x00000000U

Use a 32-second calibration cycle period

Definition at line 673 of file stm32l4xx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Use a 8-second calibration cycle period

Definition at line 675 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RTC Exported Macros

Defines

#define | LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RTC register.
#define | LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RTC register.

Define Documentation

#define LL_RTC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in RTC register.

Parameters:
__INSTANCE__ | RTC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 708 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DeInit().

#define LL_RTC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in RTC register.

Parameters:
__INSTANCE__ | RTC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 700 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DeInit().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Convert helper Macros

Defines
Convert helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
Helper macro to convert a value from BCD format to 2 digit decimal format.

Define Documentation

#define __LL_RTC_CONVERT_BCD2BIN ( __VALUE__ ) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))

Helper macro to convert a value from BCD format to 2 digit decimal format.

Parameters:
__VALUE__ BCD value to be converted
Return values:
Converted byte

Definition at line 729 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define __LL_RTC_CONVERT_BIN2BCD ( __VALUE__ ) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))

Helper macro to convert a value from 2 digit decimal format to BCD format.

Parameters:
__VALUE__ Byte to be converted
Return values:
Converted byte

Definition at line 722 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Date helper Macros

Defines
Date helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.

Define Documentation

#define __LL_RTC_GET_DAY ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)

Helper macro to retrieve Day in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Day in BCD format (0x01 . . . 0x31)

Definition at line 784 of file stm32l4xx_ll_rtc.h.

#define __LL_RTC_GET_MONTH ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)

Helper macro to retrieve Month in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 777 of file stm32l4xx_ll_rtc.h.

#define __LL_RTC_GET_WEEKDAY ( __RTC_DATE__ ) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)

Helper macro to retrieve weekday.

Parameters:
__RTC_DATE__ Date returned by LL_RTC_DATE_Get function.
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 751 of file stm32l4xx_ll_rtc.h.

#define __LL_RTC_GET_YEAR ( __RTC_DATE__ ) ((__RTC_DATE__) & 0x000000FFU)

Helper macro to retrieve Year in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Year in BCD format (0x00 . . . 0x99)

Definition at line 758 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Time helper Macros

Defines
Time helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Define Documentation

#define __LL_RTC_GET_HOUR ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)

Helper macro to retrieve hour in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)

Definition at line 799 of file stm32l4xx_ll_rtc.h.

#define __LL_RTC_GET_MINUTE ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)

Helper macro to retrieve minute in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Minutes in BCD format (0x00. . .0x59)

Definition at line 806 of file stm32l4xx_ll_rtc.h.

#define __LL_RTC_GET_SECOND ( __RTC_TIME__ ) ((__RTC_TIME__) & 0x000000FFU)

Helper macro to retrieve second in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Seconds in format (0x00. . .0x59)

Definition at line 813 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration

Functions
Configuration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_EnableOutRemap (RTC_TypeDef *RTCx)
Enable RTC_OUT remap.
__STATIC_INLINE void | LL_RTC_DisableOutRemap (RTC_TypeDef *RTCx)
Disable RTC_OUT remap.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableInitMode ( RTC_TypeDef * RTCx )

Disable initialization mode (Free running mode)

Reference Manual to LL API cross reference:
ISR INIT LL_RTC_DisableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 943 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), LL_RTC_ExitInitMode(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_DisableOutRemap ( RTC_TypeDef * RTCx )

Disable RTC_OUT remap.

Reference Manual to LL API cross reference:
OR OUT_RMP LL_RTC_DisableOutRemap
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1123 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableRefClock ( RTC_TypeDef * RTCx )

Disable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
CR REFCKON LL_RTC_DisableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1032 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableShadowRegBypass ( RTC_TypeDef * RTCx )

Disable Bypass the shadow registers.

Reference Manual to LL API cross reference:
CR BYPSHAD LL_RTC_DisableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 995 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableWriteProtection ( RTC_TypeDef * RTCx )

Disable the write protection for RTC registers.

Reference Manual to LL API cross reference:
WPR KEY LL_RTC_DisableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1100 of file stm32l4xx_ll_rtc.h.

References RTC_WRITE_PROTECTION_ENABLE_1, and RTC_WRITE_PROTECTION_ENABLE_2.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_EnableInitMode ( RTC_TypeDef * RTCx )

Enable initialization mode.

Note:
Initialization mode is used to program time and date register (RTC_TR and RTC_DR) and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
Reference Manual to LL API cross reference:
ISR INIT LL_RTC_EnableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 931 of file stm32l4xx_ll_rtc.h.

References RTC_INIT_MASK.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE void LL_RTC_EnableOutRemap ( RTC_TypeDef * RTCx )

Enable RTC_OUT remap.

Reference Manual to LL API cross reference:
OR OUT_RMP LL_RTC_EnableOutRemap
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1112 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableRefClock ( RTC_TypeDef * RTCx )

Enable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
CR REFCKON LL_RTC_EnableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1019 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableShadowRegBypass ( RTC_TypeDef * RTCx )

Enable Bypass the shadow registers.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR BYPSHAD LL_RTC_EnableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 984 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableWriteProtection ( RTC_TypeDef * RTCx )

Enable the write protection for RTC registers.

Reference Manual to LL API cross reference:
WPR KEY LL_RTC_EnableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1089 of file stm32l4xx_ll_rtc.h.

References RTC_WRITE_PROTECTION_DISABLE.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent ( RTC_TypeDef * RTCx )

Get the flag to be routed to RTC_ALARM output.

Reference Manual to LL API cross reference:
CR OSEL LL_RTC_GetAlarmOutEvent
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP

Definition at line 888 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType ( RTC_TypeDef * RTCx )

Get RTC_ALARM output type (ALARM in push-pull or open-drain output)

Note:
used only when RTC_ALARM is mapped on PC13
Reference Manual to LL API cross reference:
OR ALARMOUTTYPE LL_RTC_GetAlarmOutputType
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL

Definition at line 917 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler ( RTC_TypeDef * RTCx )

Get Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_A LL_RTC_GetAsynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7F

Definition at line 1067 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_PRER_PREDIV_A.

__STATIC_INLINE uint32_t LL_RTC_GetHourFormat ( RTC_TypeDef * RTCx )

Get Hours format (24 hour/day or AM/PM hour format)

Reference Manual to LL API cross reference:
CR FMT LL_RTC_GetHourFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM

Definition at line 856 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity ( RTC_TypeDef * RTCx )

Get Output polarity.

Reference Manual to LL API cross reference:
CR POL LL_RTC_GetOutputPolarity
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW

Definition at line 972 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler ( RTC_TypeDef * RTCx )

Get Synchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_S LL_RTC_GetSynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7FFF

Definition at line 1078 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled ( RTC_TypeDef * RTCx )

Check if Shadow registers bypass is enabled or not.

Reference Manual to LL API cross reference:
CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1006 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_SetAlarmOutEvent | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AlarmOutput
 | ) |  |

Select the flag to be routed to RTC_ALARM output.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR OSEL LL_RTC_SetAlarmOutEvent
Parameters:
RTCx RTC Instance
AlarmOutput This parameter can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP
Return values:
None

Definition at line 873 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAlarmOutputType | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Output
 | ) |  |

Set RTC_ALARM output type (ALARM in push-pull or open-drain output)

Note:
Used only when RTC_ALARM is mapped on PC13
Reference Manual to LL API cross reference:
OR ALARMOUTTYPE LL_RTC_SetAlarmOutputType
Parameters:
RTCx RTC Instance
Output This parameter can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
Return values:
None

Definition at line 903 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAsynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AsynchPrescaler
 | ) |  |

Set Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_A LL_RTC_SetAsynchPrescaler
Parameters:
RTCx | RTC Instance
AsynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7F
Return values:
None

Definition at line 1044 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_PRER_PREDIV_A.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetHourFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | HourFormat
 | ) |  |

Set Hours format (24 hour/day or AM/PM hour format)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
CR FMT LL_RTC_SetHourFormat
Parameters:
RTCx RTC Instance
HourFormat This parameter can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM
Return values:
None

Definition at line 843 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetOutputPolarity | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Polarity
 | ) |  |

Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR POL LL_RTC_SetOutputPolarity
Parameters:
RTCx RTC Instance
Polarity This parameter can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW
Return values:
None

Definition at line 959 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetSynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | SynchPrescaler
 | ) |  |

Set Synchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_S LL_RTC_SetSynchPrescaler
Parameters:
RTCx | RTC Instance
SynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7FFF
Return values:
None

Definition at line 1056 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Time

Functions
Time
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.

Function Documentation

__STATIC_INLINE void LL_RTC_TIME_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set time (hour, minute and second) in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
TimeFormat and Hours should follow the same format
Reference Manual to LL API cross reference:
TR PM LL_RTC_TIME_Config
TR HT LL_RTC_TIME_Config
TR HU LL_RTC_TIME_Config
TR MNT LL_RTC_TIME_Config
TR MNU LL_RTC_TIME_Config
TR ST LL_RTC_TIME_Config
TR SU LL_RTC_TIME_Config
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1304 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TR_HT, RTC_POSITION_TR_HU, RTC_POSITION_TR_MT, RTC_POSITION_TR_MU, RTC_POSITION_TR_ST, and RTC_POSITION_TR_SU.

Referenced by LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_TIME_DecHour ( RTC_TypeDef * RTCx )

Subtract 1 hour (winter time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR SUB1H LL_RTC_TIME_DecHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1379 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore ( RTC_TypeDef * RTCx )

Disable memorization whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR BCK LL_RTC_TIME_DisableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1356 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore ( RTC_TypeDef * RTCx )

Memorize whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR BCK LL_RTC_TIME_EnableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1344 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_Get ( RTC_TypeDef * RTCx )

Get time (hour, minute and second) in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
TR HT LL_RTC_TIME_Get
TR HU LL_RTC_TIME_Get
TR MNT LL_RTC_TIME_Get
TR MNU LL_RTC_TIME_Get
TR ST LL_RTC_TIME_Get
TR SU LL_RTC_TIME_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds (Format: 0x00HHMMSS).

Definition at line 1332 of file stm32l4xx_ll_rtc.h.

References LL_RTC_TIME_GetHour(), LL_RTC_TIME_GetMinute(), LL_RTC_TIME_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat ( RTC_TypeDef * RTCx )

Get time format (AM or PM notation)

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
Reference Manual to LL API cross reference:
TR PM LL_RTC_TIME_GetFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM

Definition at line 1164 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour ( RTC_TypeDef * RTCx )

Get Hours in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to Binary format
Reference Manual to LL API cross reference:
TR HT LL_RTC_TIME_GetHour
TR HU LL_RTC_TIME_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1199 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TR_HT, and RTC_POSITION_TR_HU.

Referenced by LL_RTC_TIME_Get().

__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute ( RTC_TypeDef * RTCx )

Get Minutes in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD to Binary format
Reference Manual to LL API cross reference:
TR MNT LL_RTC_TIME_GetMinute
TR MNU LL_RTC_TIME_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1237 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TR_MT, and RTC_POSITION_TR_MU.

Referenced by LL_RTC_TIME_Get().

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond ( RTC_TypeDef * RTCx )

Get Seconds in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
TR ST LL_RTC_TIME_GetSecond
TR SU LL_RTC_TIME_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1275 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TR_ST, and RTC_POSITION_TR_SU.

Referenced by LL_RTC_TIME_Get().

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond ( RTC_TypeDef * RTCx )

Get Sub second value in the synchronous prescaler counter.

Note:
You can use both SubSeconds value and SecondFraction (PREDIV_S through LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar SubSeconds value in second fraction ratio with time unit following generic formula: ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS.
Reference Manual to LL API cross reference:
SSR SS LL_RTC_TIME_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Sub second value (number between 0 and 65535)

Definition at line 1409 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_IncHour ( RTC_TypeDef * RTCx )

Add 1 hour (summer time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ADD1H LL_RTC_TIME_IncHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1391 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled ( RTC_TypeDef * RTCx )

Check if RTC Day Light Saving stored operation has been enabled or not.

Reference Manual to LL API cross reference:
CR BCK LL_RTC_TIME_IsDayLightStoreEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1367 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set time format (AM/24-hour or PM notation)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
TR PM LL_RTC_TIME_SetFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Return values:
None

Definition at line 1147 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set Hours in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
Reference Manual to LL API cross reference:
TR HT LL_RTC_TIME_SetHour
TR HU LL_RTC_TIME_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1180 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TR_HT, and RTC_POSITION_TR_HU.

__STATIC_INLINE void LL_RTC_TIME_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set Minutes in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
TR MNT LL_RTC_TIME_SetMinute
TR MNU LL_RTC_TIME_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1218 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TR_MT, and RTC_POSITION_TR_MU.

__STATIC_INLINE void LL_RTC_TIME_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set Seconds in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
TR ST LL_RTC_TIME_SetSecond
TR SU LL_RTC_TIME_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1256 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TR_ST, and RTC_POSITION_TR_SU.

__STATIC_INLINE void LL_RTC_TIME_Synchronize | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | ShiftSecond,
 |  | uint32_t | Fraction
 | ) |  |

Synchronize to a remote clock with a high degree of precision.

Note:
This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
When REFCKON is set, firmware must not write to Shift control register.
Reference Manual to LL API cross reference:
SHIFTR ADD1S LL_RTC_TIME_Synchronize
SHIFTR SUBFS LL_RTC_TIME_Synchronize
Parameters:
RTCx | RTC Instance
ShiftSecond This parameter can be one of the following values:
  • LL_RTC_SHIFT_SECOND_DELAY
  • LL_RTC_SHIFT_SECOND_ADVANCE
Fraction | Number of Seconds Fractions (any value from 0 to 0x7FFF)
Return values:
None

Definition at line 1428 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Date

Functions
Date
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.

Function Documentation

__STATIC_INLINE void LL_RTC_DATE_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay,
 |  | uint32_t | Day,
 |  | uint32_t | Month,
 |  | uint32_t | Year
 | ) |  |

Set date (WeekDay, Day, Month and Year) in BCD format.

Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_Config
DR MT LL_RTC_DATE_Config
DR MU LL_RTC_DATE_Config
DR DT LL_RTC_DATE_Config
DR DU LL_RTC_DATE_Config
DR YT LL_RTC_DATE_Config
DR YU LL_RTC_DATE_Config
Parameters:
RTCx | RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Day | Value between Min_Data=0x01 and Max_Data=0x31
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1638 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_DR_DT, RTC_POSITION_DR_DU, RTC_POSITION_DR_MT, RTC_POSITION_DR_MU, RTC_POSITION_DR_WDU, RTC_POSITION_DR_YT, and RTC_POSITION_DR_YU.

Referenced by LL_RTC_DATE_Init().

__STATIC_INLINE uint32_t LL_RTC_DATE_Get ( RTC_TypeDef * RTCx )

Get date (WeekDay, Day, Month and Year) in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_Get
DR MT LL_RTC_DATE_Get
DR MU LL_RTC_DATE_Get
DR DT LL_RTC_DATE_Get
DR DU LL_RTC_DATE_Get
DR YT LL_RTC_DATE_Get
DR YU LL_RTC_DATE_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).

Definition at line 1666 of file stm32l4xx_ll_rtc.h.

References LL_RTC_DATE_GetDay(), LL_RTC_DATE_GetMonth(), LL_RTC_DATE_GetWeekDay(), LL_RTC_DATE_GetYear(), RTC_OFFSET_DAY, RTC_OFFSET_MONTH, and RTC_OFFSET_WEEKDAY.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay ( RTC_TypeDef * RTCx )

Get Day in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
DR DT LL_RTC_DATE_GetDay
DR DU LL_RTC_DATE_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1595 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_DR_DT, and RTC_POSITION_DR_DU.

Referenced by LL_RTC_DATE_Get().

__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth ( RTC_TypeDef * RTCx )

Get Month in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
DR MT LL_RTC_DATE_GetMonth
DR MU LL_RTC_DATE_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 1562 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_DR_MT, and RTC_POSITION_DR_MU.

Referenced by LL_RTC_DATE_Get().

__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay ( RTC_TypeDef * RTCx )

Get Week day.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1508 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_DR_WDU.

Referenced by LL_RTC_DATE_Get().

__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear ( RTC_TypeDef * RTCx )

Get Year in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
Reference Manual to LL API cross reference:
DR YT LL_RTC_DATE_GetYear
DR YU LL_RTC_DATE_GetYear
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x99

Definition at line 1466 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_DR_YT, and RTC_POSITION_DR_YU.

Referenced by LL_RTC_DATE_Get().

__STATIC_INLINE void LL_RTC_DATE_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
DR DT LL_RTC_DATE_SetDay
DR DU LL_RTC_DATE_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1579 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_DR_DT, and RTC_POSITION_DR_DU.

__STATIC_INLINE void LL_RTC_DATE_SetMonth | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Month
 | ) |  |

Set Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
Reference Manual to LL API cross reference:
DR MT LL_RTC_DATE_SetMonth
DR MU LL_RTC_DATE_SetMonth
Parameters:
RTCx RTC Instance
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Return values:
None

Definition at line 1534 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_DR_MT, and RTC_POSITION_DR_MU.

__STATIC_INLINE void LL_RTC_DATE_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set Week day.

Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1488 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_DR_WDU.

__STATIC_INLINE void LL_RTC_DATE_SetYear | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Year
 | ) |  |

Set Year in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
Reference Manual to LL API cross reference:
DR YT LL_RTC_DATE_SetYear
DR YU LL_RTC_DATE_SetYear
Parameters:
RTCx | RTC Instance
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1450 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_DR_YT, and RTC_POSITION_DR_YU.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ALARMA

Functions
ALARMA
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMA_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm A Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
ALRMAR PM LL_RTC_ALMA_ConfigTime
ALRMAR HT LL_RTC_ALMA_ConfigTime
ALRMAR HU LL_RTC_ALMA_ConfigTime
ALRMAR MNT LL_RTC_ALMA_ConfigTime
ALRMAR MNU LL_RTC_ALMA_ConfigTime
ALRMAR ST LL_RTC_ALMA_ConfigTime
ALRMAR SU LL_RTC_ALMA_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1972 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_HT, RTC_POSITION_ALMA_HU, RTC_POSITION_ALMA_MT, RTC_POSITION_ALMA_MU, RTC_POSITION_ALMA_ST, and RTC_POSITION_ALMA_SU.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Disable ( RTC_TypeDef * RTCx )

Disable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAE LL_RTC_ALMA_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1698 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmA Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1761 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Enable ( RTC_TypeDef * RTCx )

Enable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAE LL_RTC_ALMA_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1686 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmA Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1750 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay ( RTC_TypeDef * RTCx )

Get ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR DT LL_RTC_ALMA_GetDay
ALRMAR DU LL_RTC_ALMA_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1789 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_DT, and RTC_POSITION_ALMA_DU.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour ( RTC_TypeDef * RTCx )

Get ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR HT LL_RTC_ALMA_GetHour
ALRMAR HU LL_RTC_ALMA_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1884 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_HT, and RTC_POSITION_ALMA_HU.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm A masks.

Reference Manual to LL API cross reference:
ALRMAR MSK4 LL_RTC_ALMA_GetMask
ALRMAR MSK3 LL_RTC_ALMA_GetMask
ALRMAR MSK2 LL_RTC_ALMA_GetMask
ALRMAR MSK1 LL_RTC_ALMA_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL

Definition at line 1739 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR MNT LL_RTC_ALMA_GetMinute
ALRMAR MNU LL_RTC_ALMA_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1915 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_MT, and RTC_POSITION_ALMA_MU.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR ST LL_RTC_ALMA_GetSecond
ALRMAR SU LL_RTC_ALMA_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1946 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_ST, and RTC_POSITION_ALMA_SU.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
ALRMASSR SS LL_RTC_ALMA_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 2044 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm A Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 2021 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_MASKSS.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
ALRMAR HT LL_RTC_ALMA_GetTime
ALRMAR HU LL_RTC_ALMA_GetTime
ALRMAR MNT LL_RTC_ALMA_GetTime
ALRMAR MNU LL_RTC_ALMA_GetTime
ALRMAR ST LL_RTC_ALMA_GetTime
ALRMAR SU LL_RTC_ALMA_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 1996 of file stm32l4xx_ll_rtc.h.

References LL_RTC_ALMA_GetHour(), LL_RTC_ALMA_GetMinute(), LL_RTC_ALMA_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Alarm A time format (AM or PM notation)

Reference Manual to LL API cross reference:
ALRMAR PM LL_RTC_ALMA_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM

Definition at line 1856 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM A Weekday.

Reference Manual to LL API cross reference:
ALRMAR DU LL_RTC_ALMA_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1829 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_DU.

__STATIC_INLINE void LL_RTC_ALMA_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR DT LL_RTC_ALMA_SetDay
ALRMAR DU LL_RTC_ALMA_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1775 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_DT, and RTC_POSITION_ALMA_DU.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR HT LL_RTC_ALMA_SetHour
ALRMAR HU LL_RTC_ALMA_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1870 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_HT, and RTC_POSITION_ALMA_HU.

__STATIC_INLINE void LL_RTC_ALMA_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm A masks.

Reference Manual to LL API cross reference:
ALRMAR MSK4 LL_RTC_ALMA_SetMask
ALRMAR MSK3 LL_RTC_ALMA_SetMask
ALRMAR MSK2 LL_RTC_ALMA_SetMask
ALRMAR MSK1 LL_RTC_ALMA_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL
Return values:
None

Definition at line 1719 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR MNT LL_RTC_ALMA_SetMinute
ALRMAR MNU LL_RTC_ALMA_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1901 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_MT, and RTC_POSITION_ALMA_MU.

__STATIC_INLINE void LL_RTC_ALMA_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR ST LL_RTC_ALMA_SetSecond
ALRMAR SU LL_RTC_ALMA_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1932 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_ST, and RTC_POSITION_ALMA_SU.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
ALRMASSR SS LL_RTC_ALMA_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 2033 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm A Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 2010 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_MASKSS.

__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set Alarm A time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
ALRMAR PM LL_RTC_ALMA_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Return values:
None

Definition at line 1843 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM A Weekday.

Reference Manual to LL API cross reference:
ALRMAR DU LL_RTC_ALMA_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1811 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMA_DU.

Referenced by LL_RTC_ALMA_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ALARMB

Functions
ALARMB
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMB_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm B Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
ALRMBR PM LL_RTC_ALMB_ConfigTime
ALRMBR HT LL_RTC_ALMB_ConfigTime
ALRMBR HU LL_RTC_ALMB_ConfigTime
ALRMBR MNT LL_RTC_ALMB_ConfigTime
ALRMBR MNU LL_RTC_ALMB_ConfigTime
ALRMBR ST LL_RTC_ALMB_ConfigTime
ALRMBR SU LL_RTC_ALMB_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2350 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_HT, RTC_POSITION_ALMB_HU, RTC_POSITION_ALMB_MT, RTC_POSITION_ALMB_MU, RTC_POSITION_ALMB_ST, and RTC_POSITION_ALMB_SU.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Disable ( RTC_TypeDef * RTCx )

Disable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBE LL_RTC_ALMB_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2076 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmB Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2139 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Enable ( RTC_TypeDef * RTCx )

Enable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBE LL_RTC_ALMB_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2064 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmB Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2128 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay ( RTC_TypeDef * RTCx )

Get ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR DT LL_RTC_ALMB_GetDay
ALRMBR DU LL_RTC_ALMB_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2167 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_DT, and RTC_POSITION_ALMB_DU.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour ( RTC_TypeDef * RTCx )

Get ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR HT LL_RTC_ALMB_GetHour
ALRMBR HU LL_RTC_ALMB_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2262 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_HT, and RTC_POSITION_ALMB_HU.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm B masks.

Reference Manual to LL API cross reference:
ALRMBR MSK4 LL_RTC_ALMB_GetMask
ALRMBR MSK3 LL_RTC_ALMB_GetMask
ALRMBR MSK2 LL_RTC_ALMB_GetMask
ALRMBR MSK1 LL_RTC_ALMB_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL

Definition at line 2117 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR MNT LL_RTC_ALMB_GetMinute
ALRMBR MNU LL_RTC_ALMB_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2293 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_MT, and RTC_POSITION_ALMB_MU.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR ST LL_RTC_ALMB_GetSecond
ALRMBR SU LL_RTC_ALMB_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2324 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_ST, and RTC_POSITION_ALMB_SU.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 2422 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm B Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 2399 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_MASKSS.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
ALRMBR HT LL_RTC_ALMB_GetTime
ALRMBR HU LL_RTC_ALMB_GetTime
ALRMBR MNT LL_RTC_ALMB_GetTime
ALRMBR MNU LL_RTC_ALMB_GetTime
ALRMBR ST LL_RTC_ALMB_GetTime
ALRMBR SU LL_RTC_ALMB_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2374 of file stm32l4xx_ll_rtc.h.

References LL_RTC_ALMB_GetHour(), LL_RTC_ALMB_GetMinute(), LL_RTC_ALMB_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat ( RTC_TypeDef * RTCx )

Get ALARM B time format (AM or PM notation)

Reference Manual to LL API cross reference:
ALRMBR PM LL_RTC_ALMB_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM

Definition at line 2234 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM B Weekday.

Reference Manual to LL API cross reference:
ALRMBR DU LL_RTC_ALMB_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2207 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_DU.

__STATIC_INLINE void LL_RTC_ALMB_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR DT LL_RTC_ALMB_SetDay
ALRMBR DU LL_RTC_ALMB_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 2153 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_DT, and RTC_POSITION_ALMB_DU.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR HT LL_RTC_ALMB_SetHour
ALRMBR HU LL_RTC_ALMB_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 2248 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_HT, and RTC_POSITION_ALMB_HU.

__STATIC_INLINE void LL_RTC_ALMB_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm B masks.

Reference Manual to LL API cross reference:
ALRMBR MSK4 LL_RTC_ALMB_SetMask
ALRMBR MSK3 LL_RTC_ALMB_SetMask
ALRMBR MSK2 LL_RTC_ALMB_SetMask
ALRMBR MSK1 LL_RTC_ALMB_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL
Return values:
None

Definition at line 2097 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR MNT LL_RTC_ALMB_SetMinute
ALRMBR MNU LL_RTC_ALMB_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2279 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_MT, and RTC_POSITION_ALMB_MU.

__STATIC_INLINE void LL_RTC_ALMB_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR ST LL_RTC_ALMB_SetSecond
ALRMBR SU LL_RTC_ALMB_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2310 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_ST, and RTC_POSITION_ALMB_SU.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 2411 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm B Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 2388 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_MASKSS.

__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set ALARM B time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
ALRMBR PM LL_RTC_ALMB_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Return values:
None

Definition at line 2221 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM B Weekday.

Reference Manual to LL API cross reference:
ALRMBR DU LL_RTC_ALMB_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 2189 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_ALMB_DU.

Referenced by LL_RTC_ALMB_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Timestamp

Functions
Timestamp
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TS_EnableInternalEvent (RTC_TypeDef *RTCx)
Enable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_DisableInternalEvent (RTC_TypeDef *RTCx)
Disable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.

Function Documentation

__STATIC_INLINE void LL_RTC_TS_Disable ( RTC_TypeDef * RTCx )

Disable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSE LL_RTC_TS_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2478 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent ( RTC_TypeDef * RTCx )

Disable internal event timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ITSE LL_RTC_TS_DisableInternalEvent
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2454 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_DisableOnTamper ( RTC_TypeDef * RTCx )

Disable timestamp on tamper detection event.

Reference Manual to LL API cross reference:
TAMPCR TAMPTS LL_RTC_TS_DisableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2686 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_Enable ( RTC_TypeDef * RTCx )

Enable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSE LL_RTC_TS_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2466 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent ( RTC_TypeDef * RTCx )

Enable internal event timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ITSE LL_RTC_TS_EnableInternalEvent
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2442 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableOnTamper ( RTC_TypeDef * RTCx )

Activate timestamp on tamper detection event.

Reference Manual to LL API cross reference:
TAMPCR TAMPTS LL_RTC_TS_EnableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2675 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge ( RTC_TypeDef * RTCx )

Get Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSEDGE LL_RTC_TS_GetActiveEdge
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING

Definition at line 2508 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDate ( RTC_TypeDef * RTCx )

Get Timestamp date (WeekDay, Day and Month) in BCD format.

Note:
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
TSDR WDU LL_RTC_TS_GetDate
TSDR MT LL_RTC_TS_GetDate
TSDR MU LL_RTC_TS_GetDate
TSDR DT LL_RTC_TS_GetDate
TSDR DU LL_RTC_TS_GetDate
Parameters:
RTCx RTC Instance
Return values:
Combination of Weekday, Day and Month

Definition at line 2652 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDay ( RTC_TypeDef * RTCx )

Get Timestamp Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
TSDR DT LL_RTC_TS_GetDay
TSDR DU LL_RTC_TS_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2635 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetHour ( RTC_TypeDef * RTCx )

Get Timestamp Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
TSTR HT LL_RTC_TS_GetHour
TSTR HU LL_RTC_TS_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2534 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TS_HU.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute ( RTC_TypeDef * RTCx )

Get Timestamp Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
TSTR MNT LL_RTC_TS_GetMinute
TSTR MNU LL_RTC_TS_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2547 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TS_MNU.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth ( RTC_TypeDef * RTCx )

Get Timestamp Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
TSDR MT LL_RTC_TS_GetMonth
TSDR MU LL_RTC_TS_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 2622 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TS_MU.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond ( RTC_TypeDef * RTCx )

Get Timestamp Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
TSTR ST LL_RTC_TS_GetSecond
TSTR SU LL_RTC_TS_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2560 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond ( RTC_TypeDef * RTCx )

Get time-stamp sub second value.

Reference Manual to LL API cross reference:
TSSSR SS LL_RTC_TS_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 2663 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTime ( RTC_TypeDef * RTCx )

Get Timestamp time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
TSTR HT LL_RTC_TS_GetTime
TSTR HU LL_RTC_TS_GetTime
TSTR MNT LL_RTC_TS_GetTime
TSTR MNU LL_RTC_TS_GetTime
TSTR ST LL_RTC_TS_GetTime
TSTR SU LL_RTC_TS_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2578 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Timestamp AM/PM notation (AM or 24-hour format)

Reference Manual to LL API cross reference:
TSTR PM LL_RTC_TS_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TS_TIME_FORMAT_AM
  • LL_RTC_TS_TIME_FORMAT_PM

Definition at line 2521 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay ( RTC_TypeDef * RTCx )

Get Timestamp Week day.

Reference Manual to LL API cross reference:
TSDR WDU LL_RTC_TS_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2597 of file stm32l4xx_ll_rtc.h.

References RTC_POSITION_TS_WDU.

__STATIC_INLINE void LL_RTC_TS_SetActiveEdge | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Edge
 | ) |  |

Set Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
Reference Manual to LL API cross reference:
CR TSEDGE LL_RTC_TS_SetActiveEdge
Parameters:
RTCx RTC Instance
Edge This parameter can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING
Return values:
None

Definition at line 2494 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Tamper

Functions
Tamper
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TAMPER_Enable (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (RTC_TypeDef *RTCx, uint32_t Tamper)
Clear RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Enable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Disable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (RTC_TypeDef *RTCx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (RTC_TypeDef *RTCx)
Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (RTC_TypeDef *RTCx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (RTC_TypeDef *RTCx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (RTC_TypeDef *RTCx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (RTC_TypeDef *RTCx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (RTC_TypeDef *RTCx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (RTC_TypeDef *RTCx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable Active level for Tamper input.

Function Documentation

__STATIC_INLINE void LL_RTC_TAMPER_Disable | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Clear RTC_TAMPx input detection.

Reference Manual to LL API cross reference:
TAMPCR TAMP1E LL_RTC_TAMPER_Disable
TAMPCR TAMP2E LL_RTC_TAMPER_Disable
TAMPCR TAMP3E LL_RTC_TAMPER_Disable
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1
  • LL_RTC_TAMPER_2
  • LL_RTC_TAMPER_3
Return values:
None

Definition at line 2731 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Disable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAMPCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel
TAMPCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel
TAMPCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
Return values:
None

Definition at line 2971 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Disable backup register erase after Tamper event detection.

Reference Manual to LL API cross reference:
TAMPCR TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP
TAMPCR TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP
TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_NOERASE_TAMPER1
  • LL_RTC_TAMPER_NOERASE_TAMPER2
  • LL_RTC_TAMPER_NOERASE_TAMPER3
Return values:
None

Definition at line 2804 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Disable Tamper mask flag.

Reference Manual to LL API cross reference:
TAMPCR TAMP1MF LL_RTC_TAMPER_DisableMask
TAMPCR TAMP2MF LL_RTC_TAMPER_DisableMask
TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_MASK_TAMPER1
  • LL_RTC_TAMPER_MASK_TAMPER2
  • LL_RTC_TAMPER_MASK_TAMPER3
Return values:
None

Definition at line 2768 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp ( RTC_TypeDef * RTCx )

Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)

Reference Manual to LL API cross reference:
TAMPCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2816 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_Enable | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable RTC_TAMPx input detection.

Reference Manual to LL API cross reference:
TAMPCR TAMP1E LL_RTC_TAMPER_Enable
TAMPCR TAMP2E LL_RTC_TAMPER_Enable
TAMPCR TAMP3E LL_RTC_TAMPER_Enable
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1
  • LL_RTC_TAMPER_2
  • LL_RTC_TAMPER_3
Return values:
None

Definition at line 2713 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAMPCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel
TAMPCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel
TAMPCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
Return values:
None

Definition at line 2953 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable backup register erase after Tamper event detection.

Reference Manual to LL API cross reference:
TAMPCR TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP
TAMPCR TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP
TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_NOERASE_TAMPER1
  • LL_RTC_TAMPER_NOERASE_TAMPER2
  • LL_RTC_TAMPER_NOERASE_TAMPER3
Return values:
None

Definition at line 2786 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Enable Tamper mask flag.

Note:
Associated Tamper IT must not enabled when tamper mask is set.
Reference Manual to LL API cross reference:
TAMPCR TAMP1MF LL_RTC_TAMPER_EnableMask
TAMPCR TAMP2MF LL_RTC_TAMPER_EnableMask
TAMPCR TAMP3MF LL_RTC_TAMPER_EnableMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_MASK_TAMPER1
  • LL_RTC_TAMPER_MASK_TAMPER2
  • LL_RTC_TAMPER_MASK_TAMPER3
Return values:
None

Definition at line 2750 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp ( RTC_TypeDef * RTCx )

Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)

Reference Manual to LL API cross reference:
TAMPCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2827 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount ( RTC_TypeDef * RTCx )

Get RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAMPCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE

Definition at line 2893 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge ( RTC_TypeDef * RTCx )

Get RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAMPCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK

Definition at line 2860 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq ( RTC_TypeDef * RTCx )

Get Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAMPCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256

Definition at line 2934 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | FilterCount
 | ) |  |

Set RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAMPCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
Parameters:
RTCx RTC Instance
FilterCount This parameter can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE
Return values:
None

Definition at line 2878 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Duration
 | ) |  |

Set RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAMPCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
Parameters:
RTCx RTC Instance
Duration This parameter can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK
Return values:
None

Definition at line 2845 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | SamplingFreq
 | ) |  |

Set Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAMPCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
Parameters:
RTCx RTC Instance
SamplingFreq This parameter can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256
Return values:
None

Definition at line 2915 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Wakeup

Functions
Wakeup
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.

Function Documentation

__STATIC_INLINE void LL_RTC_WAKEUP_Disable ( RTC_TypeDef * RTCx )

Disable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTE LL_RTC_WAKEUP_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3004 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_Enable ( RTC_TypeDef * RTCx )

Enable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTE LL_RTC_WAKEUP_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2992 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload ( RTC_TypeDef * RTCx )

Get Wakeup auto-reload value.

Reference Manual to LL API cross reference:
WUTR WUT LL_RTC_WAKEUP_GetAutoReload
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 3076 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock ( RTC_TypeDef * RTCx )

Get Wakeup clock.

Reference Manual to LL API cross reference:
CR WUCKSEL LL_RTC_WAKEUP_GetClock
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT

Definition at line 3052 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled ( RTC_TypeDef * RTCx )

Check if Wakeup timer is enabled or not.

Reference Manual to LL API cross reference:
CR WUTE LL_RTC_WAKEUP_IsEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3015 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Value
 | ) |  |

Set Wakeup auto-reload value.

Note:
Bit can be written only when WUTWF is set to 1 in RTC_ISR
Reference Manual to LL API cross reference:
WUTR WUT LL_RTC_WAKEUP_SetAutoReload
Parameters:
RTCx | RTC Instance
Value | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 3065 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetClock | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WakeupClock
 | ) |  |

Select Wakeup clock.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
Reference Manual to LL API cross reference:
CR WUCKSEL LL_RTC_WAKEUP_SetClock
Parameters:
RTCx RTC Instance
WakeupClock This parameter can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
Return values:
None

Definition at line 3035 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Backup_Registers

Functions
Backup_Registers
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_BAK_SetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
__STATIC_INLINE uint32_t | LL_RTC_BAK_GetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Reference Manual to LL API cross reference:
BKPxR BKP LL_RTC_BAK_GetRegister
Parameters:
RTCx RTC Instance
BackupRegister This parameter can be one of the following values:
  • LL_RTC_BKP_DR0
  • LL_RTC_BKP_DR1
  • LL_RTC_BKP_DR2
  • LL_RTC_BKP_DR3
  • LL_RTC_BKP_DR4
  • LL_RTC_BKP_DR5
  • LL_RTC_BKP_DR6
  • LL_RTC_BKP_DR7
  • LL_RTC_BKP_DR8
  • LL_RTC_BKP_DR9
  • LL_RTC_BKP_DR10
  • LL_RTC_BKP_DR11
  • LL_RTC_BKP_DR12
  • LL_RTC_BKP_DR13
  • LL_RTC_BKP_DR14
  • LL_RTC_BKP_DR15
  • LL_RTC_BKP_DR16
  • LL_RTC_BKP_DR17
  • LL_RTC_BKP_DR18
  • LL_RTC_BKP_DR19
  • LL_RTC_BKP_DR20
  • LL_RTC_BKP_DR21
  • LL_RTC_BKP_DR22
  • LL_RTC_BKP_DR23
  • LL_RTC_BKP_DR24
  • LL_RTC_BKP_DR25
  • LL_RTC_BKP_DR26
  • LL_RTC_BKP_DR27
  • LL_RTC_BKP_DR28
  • LL_RTC_BKP_DR29
  • LL_RTC_BKP_DR30
  • LL_RTC_BKP_DR31
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF

Definition at line 3181 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_BAK_SetRegister | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified RTC Backup data register.

Reference Manual to LL API cross reference:
BKPxR BKP LL_RTC_BAK_SetRegister
Parameters:
RTCx | RTC Instance
BackupRegister This parameter can be one of the following values:
  • LL_RTC_BKP_DR0
  • LL_RTC_BKP_DR1
  • LL_RTC_BKP_DR2
  • LL_RTC_BKP_DR3
  • LL_RTC_BKP_DR4
  • LL_RTC_BKP_DR5
  • LL_RTC_BKP_DR6
  • LL_RTC_BKP_DR7
  • LL_RTC_BKP_DR8
  • LL_RTC_BKP_DR9
  • LL_RTC_BKP_DR10
  • LL_RTC_BKP_DR11
  • LL_RTC_BKP_DR12
  • LL_RTC_BKP_DR13
  • LL_RTC_BKP_DR14
  • LL_RTC_BKP_DR15
  • LL_RTC_BKP_DR16
  • LL_RTC_BKP_DR17
  • LL_RTC_BKP_DR18
  • LL_RTC_BKP_DR19
  • LL_RTC_BKP_DR20
  • LL_RTC_BKP_DR21
  • LL_RTC_BKP_DR22
  • LL_RTC_BKP_DR23
  • LL_RTC_BKP_DR24
  • LL_RTC_BKP_DR25
  • LL_RTC_BKP_DR26
  • LL_RTC_BKP_DR27
  • LL_RTC_BKP_DR28
  • LL_RTC_BKP_DR29
  • LL_RTC_BKP_DR30
  • LL_RTC_BKP_DR31
Data | Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 3131 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Calibration

Functions
Calibration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus ( RTC_TypeDef * RTCx )

Get Calibration minus.

Reference Manual to LL API cross reference:
CALR CALM LL_RTC_CAL_GetMinus
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data= 0x1FF

Definition at line 3313 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq ( RTC_TypeDef * RTCx )

Get Calibration output frequency (1 Hz or 512 Hz)

Reference Manual to LL API cross reference:
CR COE LL_RTC_CAL_GetOutputFreq
CR COSEL LL_RTC_CAL_GetOutputFreq
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ

Definition at line 3228 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod ( RTC_TypeDef * RTCx )

Get the calibration cycle period.

Reference Manual to LL API cross reference:
CALR CALW8 LL_RTC_CAL_GetPeriod
CALR CALW16 LL_RTC_CAL_GetPeriod
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC

Definition at line 3288 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted ( RTC_TypeDef * RTCx )

Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)

Reference Manual to LL API cross reference:
CALR CALP LL_RTC_CAL_IsPulseInserted
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3255 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetMinus | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | CalibMinus
 | ) |  |

Set Calibration minus.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
CALR CALM LL_RTC_CAL_SetMinus
Parameters:
RTCx | RTC Instance
CalibMinus | Value between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 3302 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Frequency
 | ) |  |

Set Calibration output frequency (1 Hz or 512 Hz)

Note:
Bits are write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR COE LL_RTC_CAL_SetOutputFreq
CR COSEL LL_RTC_CAL_SetOutputFreq
Parameters:
RTCx RTC Instance
Frequency This parameter can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ
Return values:
None

Definition at line 3213 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPeriod | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Period
 | ) |  |

Set the calibration cycle period.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
CALR CALW8 LL_RTC_CAL_SetPeriod
CALR CALW16 LL_RTC_CAL_SetPeriod
Parameters:
RTCx RTC Instance
Period This parameter can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC
Return values:
None

Definition at line 3273 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPulse | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Pulse
 | ) |  |

Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
CALR CALP LL_RTC_CAL_SetPulse
Parameters:
RTCx RTC Instance
Pulse This parameter can be one of the following values:
  • LL_RTC_CALIB_INSERTPULSE_NONE
  • LL_RTC_CALIB_INSERTPULSE_SET
Return values:
None

Definition at line 3244 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
RTC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITS (RTC_TypeDef *RTCx)
Get Internal Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (RTC_TypeDef *RTCx)
Get RTC_TAMP3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (RTC_TypeDef *RTCx)
Get RTC_TAMP2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (RTC_TypeDef *RTCx)
Get RTC_TAMP1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITS (RTC_TypeDef *RTCx)
Clear Internal Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (RTC_TypeDef *RTCx)
Clear RTC_TAMP3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (RTC_TypeDef *RTCx)
Clear RTC_TAMP2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (RTC_TypeDef *RTCx)
Clear RTC_TAMP1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.

Function Documentation

__STATIC_INLINE void LL_RTC_ClearFlag_ALRA ( RTC_TypeDef * RTCx )

Clear Alarm A flag.

Reference Manual to LL API cross reference:
ISR ALRAF LL_RTC_ClearFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3546 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ALRB ( RTC_TypeDef * RTCx )

Clear Alarm B flag.

Reference Manual to LL API cross reference:
ISR ALRBF LL_RTC_ClearFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3535 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ITS ( RTC_TypeDef * RTCx )

Clear Internal Time-stamp flag.

Reference Manual to LL API cross reference:
ISR ITSF LL_RTC_ClearFlag_ITS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3450 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_RS ( RTC_TypeDef * RTCx )

Clear Registers synchronization flag.

Reference Manual to LL API cross reference:
ISR RSF LL_RTC_ClearFlag_RS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3579 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1 ( RTC_TypeDef * RTCx )

Clear RTC_TAMP1 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP1F LL_RTC_ClearFlag_TAMP1
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3488 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2 ( RTC_TypeDef * RTCx )

Clear RTC_TAMP2 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP2F LL_RTC_ClearFlag_TAMP2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3475 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3 ( RTC_TypeDef * RTCx )

Clear RTC_TAMP3 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP3F LL_RTC_ClearFlag_TAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3462 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TS ( RTC_TypeDef * RTCx )

Clear Time-stamp flag.

Reference Manual to LL API cross reference:
ISR TSF LL_RTC_ClearFlag_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3511 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TSOV ( RTC_TypeDef * RTCx )

Clear Time-stamp overflow flag.

Reference Manual to LL API cross reference:
ISR TSOVF LL_RTC_ClearFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3500 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_WUT ( RTC_TypeDef * RTCx )

Clear Wakeup timer flag.

Reference Manual to LL API cross reference:
ISR WUTF LL_RTC_ClearFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3523 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA ( RTC_TypeDef * RTCx )

Get Alarm A flag.

Reference Manual to LL API cross reference:
ISR ALRAF LL_RTC_IsActiveFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3439 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW ( RTC_TypeDef * RTCx )

Get Alarm A write flag.

Reference Manual to LL API cross reference:
ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3636 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB ( RTC_TypeDef * RTCx )

Get Alarm B flag.

Reference Manual to LL API cross reference:
ISR ALRBF LL_RTC_IsActiveFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3428 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW ( RTC_TypeDef * RTCx )

Get Alarm B write flag.

Reference Manual to LL API cross reference:
ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3625 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT ( RTC_TypeDef * RTCx )

Get Initialization flag.

Reference Manual to LL API cross reference:
ISR INITF LL_RTC_IsActiveFlag_INIT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3557 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS ( RTC_TypeDef * RTCx )

Get Initialization status flag.

Reference Manual to LL API cross reference:
ISR INITS LL_RTC_IsActiveFlag_INITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3590 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS ( RTC_TypeDef * RTCx )

Get Internal Time-stamp flag.

Reference Manual to LL API cross reference:
ISR ITSF LL_RTC_IsActiveFlag_ITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3332 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP ( RTC_TypeDef * RTCx )

Get Recalibration pending Flag.

Reference Manual to LL API cross reference:
ISR RECALPF LL_RTC_IsActiveFlag_RECALP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3343 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS ( RTC_TypeDef * RTCx )

Get Registers synchronization flag.

Reference Manual to LL API cross reference:
ISR RSF LL_RTC_IsActiveFlag_RS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3568 of file stm32l4xx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP ( RTC_TypeDef * RTCx )

Get Shift operation pending flag.

Reference Manual to LL API cross reference:
ISR SHPF LL_RTC_IsActiveFlag_SHP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3601 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1 ( RTC_TypeDef * RTCx )

Get RTC_TAMP1 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3381 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2 ( RTC_TypeDef * RTCx )

Get RTC_TAMP2 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3368 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3 ( RTC_TypeDef * RTCx )

Get RTC_TAMP3 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP3F LL_RTC_IsActiveFlag_TAMP3
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3355 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS ( RTC_TypeDef * RTCx )

Get Time-stamp flag.

Reference Manual to LL API cross reference:
ISR TSF LL_RTC_IsActiveFlag_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3404 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV ( RTC_TypeDef * RTCx )

Get Time-stamp overflow flag.

Reference Manual to LL API cross reference:
ISR TSOVF LL_RTC_IsActiveFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3393 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT ( RTC_TypeDef * RTCx )

Get Wakeup timer flag.

Reference Manual to LL API cross reference:
ISR WUTF LL_RTC_IsActiveFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3416 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW ( RTC_TypeDef * RTCx )

Get Wakeup timer write flag.

Reference Manual to LL API cross reference:
ISR WUTWF LL_RTC_IsActiveFlag_WUTW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3613 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT_Management

Functions
IT_Management
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP3 (RTC_TypeDef *RTCx)
Enable Tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP3 (RTC_TypeDef *RTCx)
Disable Tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP2 (RTC_TypeDef *RTCx)
Enable Tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP2 (RTC_TypeDef *RTCx)
Disable Tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP1 (RTC_TypeDef *RTCx)
Enable Tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP1 (RTC_TypeDef *RTCx)
Disable Tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP (RTC_TypeDef *RTCx)
Enable all Tamper Interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP (RTC_TypeDef *RTCx)
Disable all Tamper Interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP3 (RTC_TypeDef *RTCx)
Check if Tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP2 (RTC_TypeDef *RTCx)
Check if Tamper 2 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP1 (RTC_TypeDef *RTCx)
Check if Tamper 1 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP (RTC_TypeDef *RTCx)
Check if all the TAMPER interrupts are enabled or not.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableIT_ALRA ( RTC_TypeDef * RTCx )

Disable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAIE LL_RTC_DisableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3742 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ALRB ( RTC_TypeDef * RTCx )

Disable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBIE LL_RTC_DisableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3718 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP ( RTC_TypeDef * RTCx )

Disable all Tamper Interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMPIE LL_RTC_DisableIT_TAMP
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3836 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP1 ( RTC_TypeDef * RTCx )

Disable Tamper 1 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP1IE LL_RTC_DisableIT_TAMP1
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3813 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP2 ( RTC_TypeDef * RTCx )

Disable Tamper 2 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP2IE LL_RTC_DisableIT_TAMP2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3789 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP3 ( RTC_TypeDef * RTCx )

Disable Tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP3IE LL_RTC_DisableIT_TAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3765 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TS ( RTC_TypeDef * RTCx )

Disable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSIE LL_RTC_DisableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3668 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_WUT ( RTC_TypeDef * RTCx )

Disable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTIE LL_RTC_DisableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3693 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRA ( RTC_TypeDef * RTCx )

Enable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAIE LL_RTC_EnableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3730 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRB ( RTC_TypeDef * RTCx )

Enable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBIE LL_RTC_EnableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3706 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP ( RTC_TypeDef * RTCx )

Enable all Tamper Interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMPIE LL_RTC_EnableIT_TAMP
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3825 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP1 ( RTC_TypeDef * RTCx )

Enable Tamper 1 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP1IE LL_RTC_EnableIT_TAMP1
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3802 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP2 ( RTC_TypeDef * RTCx )

Enable Tamper 2 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP2IE LL_RTC_EnableIT_TAMP2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3778 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP3 ( RTC_TypeDef * RTCx )

Enable Tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP3IE LL_RTC_EnableIT_TAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3754 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TS ( RTC_TypeDef * RTCx )

Enable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSIE LL_RTC_EnableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3656 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_WUT ( RTC_TypeDef * RTCx )

Enable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTIE LL_RTC_EnableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3681 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA ( RTC_TypeDef * RTCx )

Check if Alarm A interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ALRAIE LL_RTC_IsEnabledIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3882 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB ( RTC_TypeDef * RTCx )

Check if Alarm B interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ALRBIE LL_RTC_IsEnabledIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3871 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP ( RTC_TypeDef * RTCx )

Check if all the TAMPER interrupts are enabled or not.

Reference Manual to LL API cross reference:
TAMPCR TAMPIE LL_RTC_IsEnabledIT_TAMP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3935 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1 ( RTC_TypeDef * RTCx )

Check if Tamper 1 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMPCR TAMP1IE LL_RTC_IsEnabledIT_TAMP1
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3922 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2 ( RTC_TypeDef * RTCx )

Check if Tamper 2 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMPCR TAMP2IE LL_RTC_IsEnabledIT_TAMP2
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3908 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3 ( RTC_TypeDef * RTCx )

Check if Tamper 3 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMPCR TAMP3IE LL_RTC_IsEnabledIT_TAMP3
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3894 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS ( RTC_TypeDef * RTCx )

Check if Time-stamp interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR TSIE LL_RTC_IsEnabledIT_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3847 of file stm32l4xx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT ( RTC_TypeDef * RTCx )

Check if Wakeup timer interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR WUTIE LL_RTC_IsEnabledIT_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3859 of file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Function Documentation

ErrorStatus LL_RTC_ALMA_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm A.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use LL_RTC_ALMA_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMA registers are configured
  • ERROR: ALARMA registers are not configured

Definition at line 483 of file stm32l4xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMA_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_DisableWeekday(), LL_RTC_ALMA_EnableWeekday(), LL_RTC_ALMA_SetDay(), LL_RTC_ALMA_SetMask(), LL_RTC_ALMA_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMA_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 711 of file stm32l4xx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_MASK_NONE, LL_RTC_ALMA_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_ALMB_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm B.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (LL_RTC_ALMB_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMB registers are configured
  • ERROR: ALARMB registers are not configured

Definition at line 601 of file stm32l4xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMB_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_DisableWeekday(), LL_RTC_ALMB_EnableWeekday(), LL_RTC_ALMB_SetDay(), LL_RTC_ALMB_SetMask(), LL_RTC_ALMB_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMB_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 733 of file stm32l4xx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_MASK_NONE, LL_RTC_ALMB_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_DATE_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_DateTypeDef * | RTC_DateStruct
 | ) |  |

Set the RTC current date.

Parameters:
RTCx RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_DateStruct,: pointer to a RTC_DateTypeDef structure that contains the date configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Day register is configured
  • ERROR: RTC Day register is not configured

Definition at line 393 of file stm32l4xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_DateTypeDef::Day, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_MONTH, IS_LL_RTC_WEEKDAY, IS_LL_RTC_YEAR, LL_RTC_DATE_Config(), LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_WaitForSynchro(), LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

void LL_RTC_DATE_StructInit ( LL_RTC_DateTypeDef * RTC_DateStruct )

Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)

Parameters:
RTC_DateStruct pointer to a LL_RTC_DateTypeDef structure which will be initialized.
Return values:
None

Definition at line 460 of file stm32l4xx_ll_rtc.c.

References LL_RTC_DateTypeDef::Day, LL_RTC_MONTH_JANUARY, LL_RTC_WEEKDAY_MONDAY, LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

ErrorStatus LL_RTC_DeInit ( RTC_TypeDef * RTCx )

De-Initializes the RTC registers to their default reset values.

Note:
This function doesn't reset the RTC Clock source and RTC Backup Data registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are de-initialized
  • ERROR: RTC registers are not de-initialized

Definition at line 167 of file stm32l4xx_ll_rtc.c.

References assert_param, LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_ReadReg, LL_RTC_WaitForSynchro(), LL_RTC_WriteReg, and RTC_SYNCH_PRESC_DEFAULT.

ErrorStatus LL_RTC_EnterInitMode ( RTC_TypeDef * RTCx )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC is in Init mode
  • ERROR: RTC is not in Init mode

Definition at line 758 of file stm32l4xx_ll_rtc.c.

References assert_param, LL_RTC_EnableInitMode(), LL_RTC_IsActiveFlag_INIT(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_INITMODE_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

ErrorStatus LL_RTC_ExitInitMode ( RTC_TypeDef * RTCx )

Exit the RTC Initialization mode.

Note:
When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles.
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC exited from in Init mode
  • ERROR: Not applicable

Definition at line 802 of file stm32l4xx_ll_rtc.c.

References assert_param, and LL_RTC_DisableInitMode().

ErrorStatus LL_RTC_Init | ( | RTC_TypeDef * | RTCx,
 |  | LL_RTC_InitTypeDef * | RTC_InitStruct
 | ) |  |

Initializes the RTC registers according to the specified parameters in RTC_InitStruct.

Parameters:
RTCx | RTC Instance
RTC_InitStruct | pointer to a LL_RTC_InitTypeDef structure that contains the configuration information for the RTC peripheral.
Note:
The RTC Prescaler register is write protected and can be written in initialization mode only.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are initialized
  • ERROR: RTC registers are not initialized

Definition at line 231 of file stm32l4xx_ll_rtc.c.

References assert_param, LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, IS_LL_RTC_ASYNCH_PREDIV, IS_LL_RTC_HOURFORMAT, IS_LL_RTC_SYNCH_PREDIV, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_SetAsynchPrescaler(), LL_RTC_SetHourFormat(), LL_RTC_SetSynchPrescaler(), and LL_RTC_InitTypeDef::SynchPrescaler.

void LL_RTC_StructInit ( LL_RTC_InitTypeDef * RTC_InitStruct )

Set each LL_RTC_InitTypeDef field to default value.

Parameters:
RTC_InitStruct pointer to a LL_RTC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 270 of file stm32l4xx_ll_rtc.c.

References LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, LL_RTC_HOURFORMAT_24HOUR, RTC_ASYNCH_PRESC_DEFAULT, RTC_SYNCH_PRESC_DEFAULT, and LL_RTC_InitTypeDef::SynchPrescaler.

ErrorStatus LL_RTC_TIME_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_TimeTypeDef * | RTC_TimeStruct
 | ) |  |

Set the RTC current time.

Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_TimeStruct | pointer to a RTC_TimeTypeDef structure that contains the time configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Time register is configured
  • ERROR: RTC Time register is not configured

Definition at line 290 of file stm32l4xx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_TIME_Config(), LL_RTC_WaitForSynchro(), LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_TIME_StructInit ( LL_RTC_TimeTypeDef * RTC_TimeStruct )

Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).

Parameters:
RTC_TimeStruct pointer to a LL_RTC_TimeTypeDef structure which will be initialized.
Return values:
None

Definition at line 372 of file stm32l4xx_ll_rtc.c.

References LL_RTC_TimeTypeDef::Hours, LL_RTC_TIME_FORMAT_AM_OR_24, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_WaitForSynchro ( RTC_TypeDef * RTCx )

Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are synchronised
  • ERROR: RTC registers are not synchronised

Definition at line 829 of file stm32l4xx_ll_rtc.c.

References assert_param, LL_RTC_ClearFlag_RS(), LL_RTC_IsActiveFlag_RS(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_SYNCHRO_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), and LL_RTC_TIME_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI

Modules
SPI
STM32L4xx_LL_Driver

Modules

SPI Private Constants
SPI Private Macros
SPI Exported Init structure
SPI Exported Constants
SPI Exported Macros
SPI Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for SPI registers.

Register | Bit | Function
CR1 | BIDIMODE | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | BIDIOE | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | BR | LL_SPI_GetBaudRatePrescaler
 |  | LL_SPI_SetBaudRatePrescaler
 | CPHA | LL_SPI_GetClockPhase
 |  | LL_SPI_SetClockPhase
 | CPOL | LL_SPI_GetClockPolarity
 |  | LL_SPI_SetClockPolarity
 | CRCEN | LL_SPI_DisableCRC
 |  | LL_SPI_EnableCRC
 |  | LL_SPI_IsEnabledCRC
 | CRCL | LL_SPI_GetCRCWidth
 |  | LL_SPI_SetCRCWidth
 | CRCNEXT | LL_SPI_SetCRCNext
 | LSBFIRST | LL_SPI_GetTransferBitOrder
 |  | LL_SPI_SetTransferBitOrder
 | MSTR | LL_SPI_GetMode
 |  | LL_SPI_SetMode
 | RXONLY | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | SPE | LL_SPI_Disable
 |  | LL_SPI_Enable
 |  | LL_SPI_IsEnabled
 | SSI | LL_SPI_GetMode
 |  | LL_SPI_SetMode
 | SSM | LL_SPI_GetNSSMode
 |  | LL_SPI_SetNSSMode
CR2 | DS | LL_SPI_GetDataWidth
 |  | LL_SPI_SetDataWidth
 | ERRIE | LL_SPI_DisableIT_ERR
 |  | LL_SPI_EnableIT_ERR
 |  | LL_SPI_IsEnabledIT_ERR
 | FRF | LL_SPI_GetStandard
 |  | LL_SPI_SetStandard
 | FRXTH | LL_SPI_GetRxFIFOThreshold
 |  | LL_SPI_SetRxFIFOThreshold
 | LDMARX | LL_SPI_GetDMAParity_RX
 |  | LL_SPI_SetDMAParity_RX
 | LDMATX | LL_SPI_GetDMAParity_TX
 |  | LL_SPI_SetDMAParity_TX
 | NSSP | LL_SPI_DisableNSSPulseMgt
 |  | LL_SPI_EnableNSSPulseMgt
 |  | LL_SPI_IsEnabledNSSPulse
 | RXDMAEN | LL_SPI_DisableDMAReq_RX
 |  | LL_SPI_EnableDMAReq_RX
 |  | LL_SPI_IsEnabledDMAReq_RX
 | RXNEIE | LL_SPI_DisableIT_RXNE
 |  | LL_SPI_EnableIT_RXNE
 |  | LL_SPI_IsEnabledIT_RXNE
 | SSOE | LL_SPI_GetNSSMode
 |  | LL_SPI_SetNSSMode
 | TXDMAEN | LL_SPI_DisableDMAReq_TX
 |  | LL_SPI_EnableDMAReq_TX
 |  | LL_SPI_IsEnabledDMAReq_TX
 | TXEIE | LL_SPI_DisableIT_TXE
 |  | LL_SPI_EnableIT_TXE
 |  | LL_SPI_IsEnabledIT_TXE
CRCPR | CRCPOLY | LL_SPI_GetCRCPolynomial
 |  | LL_SPI_SetCRCPolynomial
DR | DR | LL_SPI_DMA_GetRegAddr
 |  | LL_SPI_ReceiveData16
 |  | LL_SPI_ReceiveData8
 |  | LL_SPI_TransmitData16
 |  | LL_SPI_TransmitData8
RXCRCR | RXCRC | LL_SPI_GetRxCRC
SR | BSY | LL_SPI_IsActiveFlag_BSY
 | CRCERR | LL_SPI_ClearFlag_CRCERR
 |  | LL_SPI_IsActiveFlag_CRCERR
 | FRE | LL_SPI_ClearFlag_FRE
 |  | LL_SPI_IsActiveFlag_FRE
 | FRLVL | LL_SPI_GetRxFIFOLevel
 | FTLVL | LL_SPI_GetTxFIFOLevel
 | MODF | LL_SPI_ClearFlag_MODF
 |  | LL_SPI_IsActiveFlag_MODF
 | OVR | LL_SPI_ClearFlag_OVR
 |  | LL_SPI_IsActiveFlag_OVR
 | RXNE | LL_SPI_IsActiveFlag_RXNE
 | TXE | LL_SPI_IsActiveFlag_TXE
TXCRCR | TXCRC | LL_SPI_GetTxCRC
Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_CR1_CLEAR_MASK

Define Documentation

#define SPI_CR1_CLEAR_MASK
Value:
(SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
                                            SPI_CR1_BIDIMODE)

Definition at line 67 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)

Define Documentation

#define IS_LL_SPI_BAUDRATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))

Definition at line 112 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_BITORDER ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_LSB_FIRST) \
                                    || ((__VALUE__) == LL_SPI_MSB_FIRST))

Definition at line 121 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRC_POLYNOMIAL ( __VALUE__ ) ((__VALUE__) >= 0x1U)

Definition at line 127 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRCCALCULATION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
                                          || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))

Definition at line 124 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))

Definition at line 88 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_MODE_MASTER) \
                                || ((__VALUE__) == LL_SPI_MODE_SLAVE))

Definition at line 85 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_NSS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_NSS_SOFT) \
                               || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
                               || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))

Definition at line 108 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_PHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_PHASE_1EDGE) \
                                 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))

Definition at line 105 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_POLARITY_LOW) \
                                    || ((__VALUE__) == LL_SPI_POLARITY_HIGH))

Definition at line 102 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_TRANSFER_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
                                              || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
                                              || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
                                              || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))

Definition at line 80 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_SPI_InitTypeDef Struct Reference
SPI Exported Init structure

SPI Init structures definition. More...

#include <stm32l4xx_ll_spi.h>

Data Fields

uint32_t | TransferDirection
uint32_t | Mode
uint32_t | DataWidth
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | NSS
uint32_t | BaudRate
uint32_t | BitOrder
uint32_t | CRCCalculation
uint32_t | CRCPoly

Detailed Description

SPI Init structures definition.

Definition at line 72 of file stm32l4xx_ll_spi.h.

Field Documentation

uint32_t LL_SPI_InitTypeDef::BaudRate

Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of Baud Rate Prescaler.

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

This feature can be modified afterwards using unitary function LL_SPI_SetBaudRatePrescaler().

Definition at line 104 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::BitOrder

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of Transmission Bit Order.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferBitOrder().

Definition at line 110 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of Clock Phase.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPhase().

Definition at line 94 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPolarity

Specifies the serial clock steady state. This parameter can be a value of Clock Polarity.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPolarity().

Definition at line 89 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of CRC Calculation.

This feature can be modified afterwards using unitary functions LL_SPI_EnableCRC() and LL_SPI_DisableCRC().

Definition at line 115 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCPoly

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_SPI_SetCRCPolynomial().

Definition at line 120 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::DataWidth

Specifies the SPI data width. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_SPI_SetDataWidth().

Definition at line 84 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::Mode

Specifies the SPI mode (Master/Slave). This parameter can be a value of Operation Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetMode().

Definition at line 79 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of Slave Select Pin Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetNSSMode().

Definition at line 99 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::TransferDirection

Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of Transfer Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferDirection().

Definition at line 74 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_spi.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
SPI Exported Constants

Flags defines which can be used with LL_SPI_ReadReg function. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_UDR SPI_SR_UDR
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE

Detailed Description

Flags defines which can be used with LL_SPI_ReadReg function.

Define Documentation

#define LL_SPI_SR_BSY SPI_SR_BSY

Busy flag

Definition at line 143 of file stm32l4xx_ll_spi.h.

#define LL_SPI_SR_CRCERR SPI_SR_CRCERR

CRC error flag

Definition at line 145 of file stm32l4xx_ll_spi.h.

#define LL_SPI_SR_FRE SPI_SR_FRE

TI mode frame format error flag

Definition at line 148 of file stm32l4xx_ll_spi.h.

#define LL_SPI_SR_MODF SPI_SR_MODF

Mode fault flag

Definition at line 146 of file stm32l4xx_ll_spi.h.

#define LL_SPI_SR_OVR SPI_SR_OVR

Overrun flag

Definition at line 147 of file stm32l4xx_ll_spi.h.

#define LL_SPI_SR_RXNE SPI_SR_RXNE

Rx buffer not empty flag

Definition at line 141 of file stm32l4xx_ll_spi.h.

#define LL_SPI_SR_TXE SPI_SR_TXE

Tx buffer empty flag

Definition at line 142 of file stm32l4xx_ll_spi.h.

#define LL_SPI_SR_UDR SPI_SR_UDR

Underrun flag

Definition at line 144 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
SPI Exported Constants

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions. More...

Defines

#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE

Detailed Description

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Define Documentation

#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE

Error interrupt enable

Definition at line 159 of file stm32l4xx_ll_spi.h.

#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE

Rx buffer not empty interrupt enable

Definition at line 157 of file stm32l4xx_ll_spi.h.

#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE

Tx buffer empty interrupt enable

Definition at line 158 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: Operation Mode

Defines
Operation Mode
SPI Exported Constants

Defines

#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U)

Define Documentation

#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Master configuration

Definition at line 167 of file stm32l4xx_ll_spi.h.

#define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U)

Slave configuration

Definition at line 168 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Serial Protocol

Defines
Serial Protocol
SPI Exported Constants

Defines

#define | LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U)
#define | LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)

Define Documentation

#define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U)

Motorola mode. Used as default value

Definition at line 176 of file stm32l4xx_ll_spi.h.

#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)

TI mode

Definition at line 177 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: Clock Phase

Defines
Clock Phase
SPI Exported Constants

Defines

#define | LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U)
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Define Documentation

#define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U)

First clock transition is the first data capture edge

Definition at line 185 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Second clock transition is the first data capture edge

Definition at line 186 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
SPI Exported Constants

Defines

#define | LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U)
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Define Documentation

#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Clock to 1 when idle

Definition at line 195 of file stm32l4xx_ll_spi.h.

#define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U)

Clock to 0 when idle

Definition at line 194 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

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STM32L486xx HAL User Manual: Baud Rate Prescaler

Defines
Baud Rate Prescaler
SPI Exported Constants

Defines

#define | LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U)
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)

BaudRate control equal to fPCLK/128

Definition at line 209 of file stm32l4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/16

Definition at line 206 of file stm32l4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U)

BaudRate control equal to fPCLK/2

Definition at line 203 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/256

Definition at line 210 of file stm32l4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)

BaudRate control equal to fPCLK/32

Definition at line 207 of file stm32l4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)

BaudRate control equal to fPCLK/4

Definition at line 204 of file stm32l4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/64

Definition at line 208 of file stm32l4xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)

BaudRate control equal to fPCLK/8

Definition at line 205 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: Transmission Bit Order

Defines
Transmission Bit Order
SPI Exported Constants

Defines

#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST ((uint32_t)0x00000000U)

Define Documentation

#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)

Data is transmitted/received with the LSB first

Definition at line 218 of file stm32l4xx_ll_spi.h.

#define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U)

Data is transmitted/received with the MSB first

Definition at line 219 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

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STM32L486xx HAL User Manual: Transfer Mode

Defines
Transfer Mode
SPI Exported Constants

Defines

#define | LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U)
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Define Documentation

#define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U)

Full-Duplex mode. Rx and Tx transfer on 2 lines

Definition at line 227 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)

Half-Duplex Rx mode. Rx transfer on 1 line

Definition at line 229 of file stm32l4xx_ll_spi.h.

#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Half-Duplex Tx mode. Tx transfer on 1 line

Definition at line 230 of file stm32l4xx_ll_spi.h.

#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)

Simplex Rx mode. Rx transfer only on 1 line

Definition at line 228 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: Slave Select Pin Mode

Defines
Slave Select Pin Mode
SPI Exported Constants

Defines

#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

Define Documentation

#define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)

NSS pin used in Input. Only used in Master mode

Definition at line 239 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

NSS pin used in Output. Only used in Slave mode as chip select

Definition at line 240 of file stm32l4xx_ll_spi.h.

#define LL_SPI_NSS_SOFT (SPI_CR1_SSM)

NSS managed internally. NSS pin not used and free

Definition at line 238 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: Datawidth

Defines
Datawidth
SPI Exported Constants

Defines

#define | LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Define Documentation

#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)

Data length for SPI transfer: 10 bits

Definition at line 254 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)

Data length for SPI transfer: 11 bits

Definition at line 255 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 12 bits

Definition at line 256 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)

Data length for SPI transfer: 13 bits

Definition at line 257 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)

Data length for SPI transfer: 14 bits

Definition at line 258 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)

Data length for SPI transfer: 15 bits

Definition at line 259 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 16 bits

Definition at line 260 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)

Data length for SPI transfer: 4 bits

Definition at line 248 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)

Data length for SPI transfer: 5 bits

Definition at line 249 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)

Data length for SPI transfer: 6 bits

Definition at line 250 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)

Data length for SPI transfer: 7 bits

Definition at line 251 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 8 bits

Definition at line 252 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)

Data length for SPI transfer: 9 bits

Definition at line 253 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: CRC Calculation

Defines
CRC Calculation
SPI Exported Constants

Defines

#define | LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

Define Documentation

#define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)

CRC calculation disabled

Definition at line 269 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

CRC calculation enabled

Definition at line 270 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init().

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STM32L486xx HAL User Manual: CRC Length

Defines
CRC Length
SPI Exported Constants

Defines

#define | LL_SPI_CRC_8BIT ((uint32_t)0x00000000U)
#define | LL_SPI_CRC_16BIT (SPI_CR1_CRCL)

Define Documentation

#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL)

16-bit CRC length

Definition at line 280 of file stm32l4xx_ll_spi.h.

#define LL_SPI_CRC_8BIT ((uint32_t)0x00000000U)

8-bit CRC length

Definition at line 279 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: RX FIFO Threshold

Defines
RX FIFO Threshold
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_TH_HALF ((uint32_t)0x00000000U)
#define | LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)

Define Documentation

#define LL_SPI_RX_FIFO_TH_HALF ((uint32_t)0x00000000U)

RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit)

Definition at line 288 of file stm32l4xx_ll_spi.h.

#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)

RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit)

Definition at line 289 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: RX FIFO Level

Defines
RX FIFO Level
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_EMPTY ((uint32_t)0x00000000U)
#define | LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)
#define | LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)
#define | LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)

Define Documentation

#define LL_SPI_RX_FIFO_EMPTY ((uint32_t)0x00000000U)

FIFO reception empty

Definition at line 297 of file stm32l4xx_ll_spi.h.

#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)

FIFO reception full

Definition at line 300 of file stm32l4xx_ll_spi.h.

#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)

FIFO reception 1/2

Definition at line 299 of file stm32l4xx_ll_spi.h.

#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)

FIFO reception 1/4

Definition at line 298 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: TX FIFO Level

Defines
TX FIFO Level
SPI Exported Constants

Defines

#define | LL_SPI_TX_FIFO_EMPTY ((uint32_t)0x00000000U)
#define | LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)
#define | LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)
#define | LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)

Define Documentation

#define LL_SPI_TX_FIFO_EMPTY ((uint32_t)0x00000000U)

FIFO transmission empty

Definition at line 308 of file stm32l4xx_ll_spi.h.

#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)

FIFO transmission full

Definition at line 311 of file stm32l4xx_ll_spi.h.

#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)

FIFO transmission 1/2

Definition at line 310 of file stm32l4xx_ll_spi.h.

#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)

FIFO transmission 1/4

Definition at line 309 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: DMA Parity

Defines
DMA Parity
SPI Exported Constants

Defines

#define | LL_SPI_DMA_PARITY_EVEN ((uint32_t)0x00000000U)
#define | LL_SPI_DMA_PARITY_ODD ((uint32_t)0x00000001U)

Define Documentation

#define LL_SPI_DMA_PARITY_EVEN ((uint32_t)0x00000000U)

Select DMA parity Even

Definition at line 319 of file stm32l4xx_ll_spi.h.

#define LL_SPI_DMA_PARITY_ODD ((uint32_t)0x00000001U)

Select DMA parity Odd

Definition at line 320 of file stm32l4xx_ll_spi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
SPI Exported Macros

Defines

#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.

Define Documentation

#define LL_SPI_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 354 of file stm32l4xx_ll_spi.h.

#define LL_SPI_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 346 of file stm32l4xx_ll_spi.h.

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STM32L486xx HAL User Manual: Configuration

Functions
Configuration
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_SetRxFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.

Function Documentation

__STATIC_INLINE void LL_SPI_Disable ( SPI_TypeDef * SPIx )

Disable SPI peripheral.

Note:
When disabling the SPI, follow the procedure described in the Reference Manual.
Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 390 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_Enable ( SPI_TypeDef * SPIx )

Enable SPI peripheral.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 378 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler ( SPI_TypeDef * SPIx )

Get baud rate prescaler.

Reference Manual to LL API cross reference:
CR1 BR LL_SPI_GetBaudRatePrescaler
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256

Definition at line 557 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPhase ( SPI_TypeDef * SPIx )

Get clock phase.

Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_GetClockPhase
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE

Definition at line 488 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity ( SPI_TypeDef * SPIx )

Get clock polarity.

Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH

Definition at line 517 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDataWidth ( SPI_TypeDef * SPIx )

Get frame data width.

Reference Manual to LL API cross reference:
CR2 DS LL_SPI_GetDataWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT

Definition at line 671 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetMode ( SPI_TypeDef * SPIx )

Get SPI operation mode (Master or Slave)

Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_GetMode
CR1 SSI LL_SPI_GetMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE

Definition at line 431 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold ( SPI_TypeDef * SPIx )

Get threshold of RXFIFO that triggers an RXNE event.

Reference Manual to LL API cross reference:
CR2 FRXTH LL_SPI_GetRxFIFOThreshold
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_TH_HALF
  • LL_SPI_RX_FIFO_TH_QUARTER

Definition at line 698 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetStandard ( SPI_TypeDef * SPIx )

Get serial protocol used.

Reference Manual to LL API cross reference:
CR2 FRF LL_SPI_GetStandard
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI

Definition at line 459 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder ( SPI_TypeDef * SPIx )

Get transfer bit order.

Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_GetTransferBitOrder
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST

Definition at line 585 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection ( SPI_TypeDef * SPIx )

Get transfer direction mode.

Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_GetTransferDirection
CR1 BIDIMODE LL_SPI_GetTransferDirection
CR1 BIDIOE LL_SPI_GetTransferDirection
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX

Definition at line 622 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabled ( SPI_TypeDef * SPIx )

Check if SPI peripheral is enabled.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 401 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BaudRate
 | ) |  |

Set baud rate prescaler.

Note:
These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
Reference Manual to LL API cross reference:
CR1 BR LL_SPI_SetBaudRatePrescaler
Parameters:
SPIx SPI Instance
BaudRate This parameter can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256
Return values:
None

Definition at line 538 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPhase | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPhase
 | ) |  |

Set clock phase.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_SetClockPhase
Parameters:
SPIx SPI Instance
ClockPhase This parameter can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE
Return values:
None

Definition at line 475 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set clock polarity.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH
Return values:
None

Definition at line 504 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDataWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataWidth
 | ) |  |

Set frame data width.

Reference Manual to LL API cross reference:
CR2 DS LL_SPI_SetDataWidth
Parameters:
SPIx SPI Instance
DataWidth This parameter can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT
Return values:
None

Definition at line 647 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set SPI operation mode to Master or Slave.

Note:
This bit should not be changed when communication is ongoing.
Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_SetMode
CR1 SSI LL_SPI_SetMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE
Return values:
None

Definition at line 417 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Threshold
 | ) |  |

Set threshold of RXFIFO that triggers an RXNE event.

Reference Manual to LL API cross reference:
CR2 FRXTH LL_SPI_SetRxFIFOThreshold
Parameters:
SPIx SPI Instance
Threshold This parameter can be one of the following values:
  • LL_SPI_RX_FIFO_TH_HALF
  • LL_SPI_RX_FIFO_TH_QUARTER
Return values:
None

Definition at line 685 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set serial protocol used.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR2 FRF LL_SPI_SetStandard
Parameters:
SPIx SPI Instance
Standard This parameter can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI
Return values:
None

Definition at line 446 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferBitOrder | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BitOrder
 | ) |  |

Set transfer bit order.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_SetTransferBitOrder
Parameters:
SPIx SPI Instance
BitOrder This parameter can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST
Return values:
None

Definition at line 572 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferDirection | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | TransferDirection
 | ) |  |

Set transfer direction mode.

Note:
For Half-Duplex mode, Rx Direction is set by default. In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_SetTransferDirection
CR1 BIDIMODE LL_SPI_SetTransferDirection
CR1 BIDIOE LL_SPI_SetTransferDirection
Parameters:
SPIx SPI Instance
TransferDirection This parameter can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX
Return values:
None

Definition at line 605 of file stm32l4xx_ll_spi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC Management

Functions
CRC Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableCRC ( SPI_TypeDef * SPIx )

Disable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_DisableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 730 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableCRC ( SPI_TypeDef * SPIx )

Enable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_EnableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 718 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Get polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 805 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth ( SPI_TypeDef * SPIx )

Get CRC Length.

Reference Manual to LL API cross reference:
CR1 CRCL LL_SPI_GetCRCWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_16BIT

Definition at line 770 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxCRC ( SPI_TypeDef * SPIx )

Get Rx CRC.

Reference Manual to LL API cross reference:
RXCRCR RXCRC LL_SPI_GetRxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 816 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxCRC ( SPI_TypeDef * SPIx )

Get Tx CRC.

Reference Manual to LL API cross reference:
TXCRCR TXCRC LL_SPI_GetTxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 827 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC ( SPI_TypeDef * SPIx )

Check if CRC is enabled.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_IsEnabledCRC
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 742 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCNext ( SPI_TypeDef * SPIx )

Set CRCNext to transfer CRC on the line.

Note:
This bit has to be written as soon as the last data is written in the SPIx_DR register.
Reference Manual to LL API cross reference:
CR1 CRCNEXT LL_SPI_SetCRCNext
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 782 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCPolynomial | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCPoly
 | ) |  |

Set polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
Parameters:
SPIx | SPI Instance
CRCPoly | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
Return values:
None

Definition at line 794 of file stm32l4xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetCRCWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCLength
 | ) |  |

Set CRC Length.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCL LL_SPI_SetCRCWidth
Parameters:
SPIx SPI Instance
CRCLength This parameter can be one of the following values:
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_16BIT
Return values:
None

Definition at line 757 of file stm32l4xx_ll_spi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Slave Select Pin Management

Functions
Slave Select Pin Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse management.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse management.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt ( SPI_TypeDef * SPIx )

Disable NSS pulse management.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_DisableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 894 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt ( SPI_TypeDef * SPIx )

Enable NSS pulse management.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_EnableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 882 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetNSSMode ( SPI_TypeDef * SPIx )

Get NSS mode.

Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_GetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_GetNSSMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT

Definition at line 868 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse ( SPI_TypeDef * SPIx )

Check if NSS pulse is enabled.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_IsEnabledNSSPulse
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 906 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetNSSMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | NSS
 | ) |  |

Set NSS mode.

Note:
LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_SetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_SetNSSMode
Parameters:
SPIx SPI Instance
NSS This parameter can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT
Return values:
None

Definition at line 852 of file stm32l4xx_ll_spi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG Management

Functions
FLAG Management
SPI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t | LL_SPI_GetTxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.

Function Documentation

__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR ( SPI_TypeDef * SPIx )

Clear CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_ClearFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1039 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear frame format error flag.

Note:
Clearing this flag is done by reading SPIx_SR register
Reference Manual to LL API cross reference:
SR FRE LL_SPI_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1085 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_MODF ( SPI_TypeDef * SPIx )

Clear mode fault error flag.

Note:
Clearing this flag is done by a read access to the SPIx_SR register followed by a write access to the SPIx_CR1 register
Reference Manual to LL API cross reference:
SR MODF LL_SPI_ClearFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1052 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear overrun error flag.

Note:
Clearing this flag is done by a read access to the SPIx_DR register followed by a read access to the SPIx_SR register
Reference Manual to LL API cross reference:
SR OVR LL_SPI_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1069 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel ( SPI_TypeDef * SPIx )

Get FIFO reception Level.

Reference Manual to LL API cross reference:
SR FRLVL LL_SPI_GetRxFIFOLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_EMPTY
  • LL_SPI_RX_FIFO_QUARTER_FULL
  • LL_SPI_RX_FIFO_HALF_FULL
  • LL_SPI_RX_FIFO_FULL

Definition at line 1013 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel ( SPI_TypeDef * SPIx )

Get FIFO Transmission Level.

Reference Manual to LL API cross reference:
SR FTLVL LL_SPI_GetTxFIFOLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_TX_FIFO_EMPTY
  • LL_SPI_TX_FIFO_QUARTER_FULL
  • LL_SPI_TX_FIFO_HALF_FULL
  • LL_SPI_TX_FIFO_FULL

Definition at line 1028 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY ( SPI_TypeDef * SPIx )

Get busy flag.

Note:
The BSY flag is cleared under any one of the following conditions: -When the SPI is correctly disabled -When a fault is detected in Master mode (MODF bit set to 1) -In Master mode, when it finishes a data transmission and no new data is ready to be sent -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between each data transfer.
Reference Manual to LL API cross reference:
SR BSY LL_SPI_IsActiveFlag_BSY
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 987 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR ( SPI_TypeDef * SPIx )

Get CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_IsActiveFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 947 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_SPI_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 998 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF ( SPI_TypeDef * SPIx )

Get mode fault error flag.

Reference Manual to LL API cross reference:
SR MODF LL_SPI_IsActiveFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 958 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_SPI_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 969 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer is not empty.

Reference Manual to LL API cross reference:
SR RXNE LL_SPI_IsActiveFlag_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 925 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer is empty.

Reference Manual to LL API cross reference:
SR TXE LL_SPI_IsActiveFlag_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 936 of file stm32l4xx_ll_spi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableIT_ERR ( SPI_TypeDef * SPIx )

Disable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_DisableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1141 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableIT_RXNE ( SPI_TypeDef * SPIx )

Disable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_DisableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1152 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableIT_TXE ( SPI_TypeDef * SPIx )

Disable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_DisableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1163 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_ERR ( SPI_TypeDef * SPIx )

Enable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_EnableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1107 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_RXNE ( SPI_TypeDef * SPIx )

Enable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_EnableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1118 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_TXE ( SPI_TypeDef * SPIx )

Enable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_EnableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1129 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR ( SPI_TypeDef * SPIx )

Check if error interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_IsEnabledIT_ERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1174 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer not empty interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1185 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_IsEnabledIT_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1196 of file stm32l4xx_ll_spi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Management

Functions
DMA Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void | LL_SPI_SetDMAParity_RX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA reception.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_RX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA reception.
__STATIC_INLINE void | LL_SPI_SetDMAParity_TX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_TX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1226 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1259 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr ( SPI_TypeDef * SPIx )

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
DR DR LL_SPI_DMA_GetRegAddr
Parameters:
SPIx SPI Instance
Return values:
Address of data register

Definition at line 1335 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1215 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1248 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX ( SPI_TypeDef * SPIx )

Get parity configuration for Last DMA reception.

Reference Manual to LL API cross reference:
CR2 LDMARX LL_SPI_GetDMAParity_RX
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN

Definition at line 1297 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX ( SPI_TypeDef * SPIx )

Get parity configuration for Last DMA transmission.

Reference Manual to LL API cross reference:
CR2 LDMATX LL_SPI_GetDMAParity_TX
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN

Definition at line 1324 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1237 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1270 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDMAParity_RX | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Parity
 | ) |  |

Set parity of Last DMA reception.

Reference Manual to LL API cross reference:
CR2 LDMARX LL_SPI_SetDMAParity_RX
Parameters:
SPIx SPI Instance
Parity This parameter can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN
Return values:
None

Definition at line 1284 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDMAParity_TX | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Parity
 | ) |  |

Set parity of Last DMA transmission.

Reference Manual to LL API cross reference:
CR2 LDMATX LL_SPI_SetDMAParity_TX
Parameters:
SPIx SPI Instance
Parity This parameter can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN
Return values:
None

Definition at line 1311 of file stm32l4xx_ll_spi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DATA Management

Functions
DATA Management
SPI Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.

Function Documentation

__STATIC_INLINE uint16_t LL_SPI_ReceiveData16 ( SPI_TypeDef * SPIx )

Read 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 1365 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE uint8_t LL_SPI_ReceiveData8 ( SPI_TypeDef * SPIx )

Read 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData8
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1354 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 1389 of file stm32l4xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_TransmitData8 | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | TxData
 | ) |  |

Write 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData8
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1377 of file stm32l4xx_ll_spi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_SPI_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 151 of file stm32l4xx_ll_spi.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_SPI2, LL_APB1_GRP1_PERIPH_SPI3, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_SPI1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initialize the SPI registers according to the specified parameters in SPI_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
SPI_InitStruct | pointer to a LL_SPI_InitTypeDef structure
Return values:
An ErrorStatus enumeration value. (Return always SUCCESS)

Definition at line 206 of file stm32l4xx_ll_spi.c.

References assert_param, LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, IS_LL_SPI_BAUDRATE, IS_LL_SPI_BITORDER, IS_LL_SPI_CRC_POLYNOMIAL, IS_LL_SPI_CRCCALCULATION, IS_LL_SPI_DATAWIDTH, IS_LL_SPI_MODE, IS_LL_SPI_NSS, IS_LL_SPI_PHASE, IS_LL_SPI_POLARITY, IS_LL_SPI_TRANSFER_DIRECTION, LL_SPI_CRCCALCULATION_ENABLE, LL_SPI_IsEnabled(), LL_SPI_SetCRCPolynomial(), LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, SPI_CR1_CLEAR_MASK, and LL_SPI_InitTypeDef::TransferDirection.

void LL_SPI_StructInit ( LL_SPI_InitTypeDef * SPI_InitStruct )

Set each LL_SPI_InitTypeDef field to default value.

Parameters:
SPI_InitStruct pointer to a LL_SPI_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 274 of file stm32l4xx_ll_spi.c.

References LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, LL_SPI_BAUDRATEPRESCALER_DIV2, LL_SPI_CRCCALCULATION_DISABLE, LL_SPI_DATAWIDTH_8BIT, LL_SPI_FULL_DUPLEX, LL_SPI_MODE_SLAVE, LL_SPI_MSB_FIRST, LL_SPI_NSS_HARD_INPUT, LL_SPI_PHASE_1EDGE, LL_SPI_POLARITY_LOW, LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, and LL_SPI_InitTypeDef::TransferDirection.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI

Modules
SWPMI
STM32L4xx_LL_Driver

Modules

SWPMI Private Macros
SWPMI Exported Init structure
SWPMI Exported Constants
SWPMI Exported Macros
SWPMI Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for SWPMI registers.

Register | Bit | Function
BRR | BR | LL_SWPMI_GetBitRatePrescaler
 |  | LL_SWPMI_SetBitRatePrescaler
CR | DEACT | LL_SWPMI_RequestDeactivation
 | LPBK | LL_SWPMI_DisableLoopback
 |  | LL_SWPMI_EnableLoopback
 | RXDMA | LL_SWPMI_DisableDMAReq_RX
 |  | LL_SWPMI_EnableDMAReq_RX
 |  | LL_SWPMI_IsEnabledDMAReq_RX
 | RXMODE | LL_SWPMI_GetReceptionMode
 |  | LL_SWPMI_SetReceptionMode
 | SWPACT | LL_SWPMI_Activate
 |  | LL_SWPMI_Deactivate
 | TXDMA | LL_SWPMI_DisableDMAReq_TX
 |  | LL_SWPMI_EnableDMAReq_TX
 |  | LL_SWPMI_IsEnabledDMAReq_TX
 | TXMODE | LL_SWPMI_GetTransmissionMode
 |  | LL_SWPMI_SetTransmissionMode
ICR | CRXBERF | LL_SWPMI_ClearFlag_RXBER
 | CRXBFF | LL_SWPMI_ClearFlag_RXBF
 | CRXOVRF | LL_SWPMI_ClearFlag_RXOVR
 | CSRF | LL_SWPMI_ClearFlag_SR
 | CTCF | LL_SWPMI_ClearFlag_TC
 | CTXBEF | LL_SWPMI_ClearFlag_TXBE
 | CTXUNRF | LL_SWPMI_ClearFlag_TXUNR
IER | RIE | LL_SWPMI_DisableIT_RX
 |  | LL_SWPMI_EnableIT_RX
 |  | LL_SWPMI_IsEnabledIT_RX
 | RXBERIE | LL_SWPMI_DisableIT_RXBER
 |  | LL_SWPMI_EnableIT_RXBER
 |  | LL_SWPMI_IsEnabledIT_RXBER
 | RXBFIE | LL_SWPMI_DisableIT_RXBF
 |  | LL_SWPMI_EnableIT_RXBF
 |  | LL_SWPMI_IsEnabledIT_RXBF
 | RXOVRIE | LL_SWPMI_DisableIT_RXOVR
 |  | LL_SWPMI_EnableIT_RXOVR
 |  | LL_SWPMI_IsEnabledIT_RXOVR
 | SRIE | LL_SWPMI_DisableIT_SR
 |  | LL_SWPMI_EnableIT_SR
 |  | LL_SWPMI_IsEnabledIT_SR
 | TCIE | LL_SWPMI_DisableIT_TC
 |  | LL_SWPMI_EnableIT_TC
 |  | LL_SWPMI_IsEnabledIT_TC
 | TIE | LL_SWPMI_DisableIT_TX
 |  | LL_SWPMI_EnableIT_TX
 |  | LL_SWPMI_IsEnabledIT_TX
 | TXBEIE | LL_SWPMI_DisableIT_TXBE
 |  | LL_SWPMI_EnableIT_TXBE
 |  | LL_SWPMI_IsEnabledIT_TXBE
 | TXUNRIE | LL_SWPMI_DisableIT_TXUNR
 |  | LL_SWPMI_EnableIT_TXUNR
 |  | LL_SWPMI_IsEnabledIT_TXUNR
ISR | DEACTF | LL_SWPMI_IsActiveFlag_DEACT
 | RXBERF | LL_SWPMI_IsActiveFlag_RXBER
 | RXBFF | LL_SWPMI_IsActiveFlag_RXBF
 | RXNE | LL_SWPMI_IsActiveFlag_RXNE
 | RXOVRF | LL_SWPMI_IsActiveFlag_RXOVR
 | SRF | LL_SWPMI_IsActiveFlag_SR
 | SUSP | LL_SWPMI_IsActiveFlag_SUSP
 | TCF | LL_SWPMI_IsActiveFlag_TC
 | TXBEF | LL_SWPMI_IsActiveFlag_TXBE
 | TXE | LL_SWPMI_IsActiveFlag_TXE
 | TXUNRF | LL_SWPMI_IsActiveFlag_TXUNR
OR | CLASS | LL_SWPMI_GetVoltageClass
 |  | LL_SWPMI_SetVoltageClass
 | TBYP | LL_SWPMI_DisableTXBypass
 |  | LL_SWPMI_EnableTXBypass
RDR | RD | LL_SWPMI_DMA_GetRegAddr
 |  | LL_SWPMI_ReceiveData32
RFL | RFL | LL_SWPMI_GetReceiveFrameLength
TDR | TD | LL_SWPMI_DMA_GetRegAddr
 |  | LL_SWPMI_TransmitData32
Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Private Macros

Defines
SWPMI Private Macros
SWPMI

Defines

#define | IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
#define | IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__)
#define | IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__)
#define | IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__)

Define Documentation

#define IS_LL_SWPMI_BITRATE_VALUE ( __VALUE__ ) (((__VALUE__) <= 63))

Definition at line 66 of file stm32l4xx_ll_swpmi.c.

Referenced by LL_SWPMI_Init().

#define IS_LL_SWPMI_SW_BUFFER_RX ( __VALUE__ )
Value:
(((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \
                                          || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI))

Definition at line 68 of file stm32l4xx_ll_swpmi.c.

Referenced by LL_SWPMI_Init().

#define IS_LL_SWPMI_SW_BUFFER_TX ( __VALUE__ )
Value:
(((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_SINGLE) \
                                          || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI))

Definition at line 71 of file stm32l4xx_ll_swpmi.c.

Referenced by LL_SWPMI_Init().

#define IS_LL_SWPMI_VOLTAGE_CLASS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_C) \
                                           || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B))

Definition at line 74 of file stm32l4xx_ll_swpmi.c.

Referenced by LL_SWPMI_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_SWPMI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_SWPMI_InitTypeDef Struct Reference
SWPMI Exported Init structure

SWPMI Init structures definition. More...

#include <stm32l4xx_ll_swpmi.h>

Data Fields

uint32_t | VoltageClass
uint32_t | BitRatePrescaler
uint32_t | TxBufferingMode
uint32_t | RxBufferingMode

Detailed Description

SWPMI Init structures definition.

Definition at line 81 of file stm32l4xx_ll_swpmi.h.

Field Documentation

uint32_t LL_SWPMI_InitTypeDef::BitRatePrescaler

Specifies the SWPMI bitrate prescaler. This parameter must be a number between Min_Data=0 and Max_Data=63.

The value can be calculated thanks to helper macro __LL_SWPMI_CALC_BITRATE_PRESCALER

This feature can be modified afterwards using unitary function LL_SWPMI_SetBitRatePrescaler.

Definition at line 88 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init(), and LL_SWPMI_StructInit().

uint32_t LL_SWPMI_InitTypeDef::RxBufferingMode

Specifies the reception buffering mode. This parameter can be a value of SW BUFFER RX

This feature can be modified afterwards using unitary function LL_SWPMI_SetReceptionMode.

Definition at line 100 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init(), and LL_SWPMI_StructInit().

uint32_t LL_SWPMI_InitTypeDef::TxBufferingMode

Specifies the transmission buffering mode. This parameter can be a value of SW BUFFER TX

This feature can be modified afterwards using unitary function LL_SWPMI_SetTransmissionMode.

Definition at line 95 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init(), and LL_SWPMI_StructInit().

uint32_t LL_SWPMI_InitTypeDef::VoltageClass

Specifies the SWP Voltage Class. This parameter can be a value of VOLTAGE CLASS

This feature can be modified afterwards using unitary function LL_SWPMI_SetVoltageClass.

Definition at line 83 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init(), and LL_SWPMI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_swpmi.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
SWPMI Exported Constants

Flags defines which can be used with LL_SWPMI_WriteReg function. More...

Defines

#define | LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF
#define | LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF
#define | LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF
#define | LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF
#define | LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF
#define | LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF
#define | LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF

Detailed Description

Flags defines which can be used with LL_SWPMI_WriteReg function.

Define Documentation

#define LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF

Clear receive CRC error flag

Definition at line 122 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF

Clear receive buffer full flag

Definition at line 120 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF

Clear receive overrun error flag

Definition at line 123 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF

Clear slave resume flag

Definition at line 126 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF

Clear transfer complete flag

Definition at line 125 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF

Clear transmit buffer empty flag

Definition at line 121 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF

Clear transmit underrun error flag

Definition at line 124 of file stm32l4xx_ll_swpmi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
SWPMI Exported Constants

Flags defines which can be used with LL_SWPMI_ReadReg function. More...

Defines

#define | LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF
#define | LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF
#define | LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF
#define | LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF
#define | LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF
#define | LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE
#define | LL_SWPMI_ISR_TXE SWPMI_ISR_TXE
#define | LL_SWPMI_ISR_TCF SWPMI_ISR_TCF
#define | LL_SWPMI_ISR_SRF SWPMI_ISR_SRF
#define | LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP
#define | LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF

Detailed Description

Flags defines which can be used with LL_SWPMI_ReadReg function.

Define Documentation

#define LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF

DEACTIVATED flag

Definition at line 145 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF

Receive CRC error flag

Definition at line 137 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF

Receive buffer full flag

Definition at line 135 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE

Receive data register not empty

Definition at line 140 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF

Receive overrun error flag

Definition at line 138 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ISR_SRF SWPMI_ISR_SRF

Slave resume flag

Definition at line 143 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP

SUSPEND flag

Definition at line 144 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ISR_TCF SWPMI_ISR_TCF

Transfer complete flag

Definition at line 142 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF

Transmit buffer empty flag

Definition at line 136 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ISR_TXE SWPMI_ISR_TXE

Transmit data register empty

Definition at line 141 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF

Transmit underrun error flag

Definition at line 139 of file stm32l4xx_ll_swpmi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
SWPMI Exported Constants

IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions. More...

Defines

#define | LL_SWPMI_IER_SRIE SWPMI_IER_SRIE
#define | LL_SWPMI_IER_TCIE SWPMI_IER_TCIE
#define | LL_SWPMI_IER_TIE SWPMI_IER_TIE
#define | LL_SWPMI_IER_RIE SWPMI_IER_RIE
#define | LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE
#define | LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE
#define | LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE
#define | LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE
#define | LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE

Detailed Description

IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions.

Define Documentation

#define LL_SWPMI_IER_RIE SWPMI_IER_RIE

Receive interrupt enable

Definition at line 157 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE

Receive CRC error interrupt enable

Definition at line 160 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE

Receive buffer full interrupt enable

Definition at line 162 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE

Receive overrun error interrupt enable

Definition at line 159 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_IER_SRIE SWPMI_IER_SRIE

Slave resume interrupt enable

Definition at line 154 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_IER_TCIE SWPMI_IER_TCIE

Transmit complete interrupt enable

Definition at line 155 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_IER_TIE SWPMI_IER_TIE

Transmit interrupt enable

Definition at line 156 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE

Transmit buffer empty interrupt enable

Definition at line 161 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE

Transmit underrun error interrupt enable

Definition at line 158 of file stm32l4xx_ll_swpmi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SW BUFFER RX

Defines
SW BUFFER RX
SWPMI Exported Constants

Defines

#define | LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)
#define | LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE

Define Documentation

#define LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE

Multi software buffermode for reception

Definition at line 171 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)

Single software buffer mode for reception

Definition at line 170 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_StructInit().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SW BUFFER TX

Defines
SW BUFFER TX
SWPMI Exported Constants

Defines

#define | LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)
#define | LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE

Define Documentation

#define LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE

Multi software buffermode for transmission

Definition at line 180 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)

Single software buffer mode for transmission

Definition at line 179 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_StructInit().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: VOLTAGE CLASS

Defines
VOLTAGE CLASS
SWPMI Exported Constants

Defines

#define | LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define | LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS

Define Documentation

#define LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS

SWPMI_IO uses an internal voltage regulator to operate in class B

Definition at line 189 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)

SWPMI_IO uses directly VDD voltage to operate in class C

Definition at line 188 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_StructInit().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA register data

Defines
DMA register data
SWPMI Exported Constants

Defines

#define | LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0
#define | LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1

Define Documentation

#define LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1

Get address of data register used for reception

Definition at line 198 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0

Get address of data register used for transmission

Definition at line 197 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_DMA_GetRegAddr().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
SWPMI Exported Macros

Defines

#define | LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SWPMI register.
#define | LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SWPMI register.

Define Documentation

#define LL_SWPMI_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in SWPMI register.

Parameters:
__INSTANCE__ | SWPMI Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 231 of file stm32l4xx_ll_swpmi.h.

#define LL_SWPMI_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in SWPMI register.

Parameters:
__INSTANCE__ | SWPMI Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 223 of file stm32l4xx_ll_swpmi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Bit rate calculation helper Macros

Defines
Bit rate calculation helper Macros
SWPMI Exported Macros

Defines

#define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
Helper macro to calculate bit rate value to set in BRR register (LL_SWPMI_SetBitRatePrescaler function)

Define Documentation

#define __LL_SWPMI_CALC_BITRATE_PRESCALER | ( | __FSWP__,
 |  | __FSWPCLK__
 | ) | ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))

Helper macro to calculate bit rate value to set in BRR register (LL_SWPMI_SetBitRatePrescaler function)

Note:
ex: __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
Parameters:
__FSWP__ | Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
__FSWPCLK__ | PCLK or HSI frequency (in Hz)
Return values:
Bitrate prescaler (BRR register)

Definition at line 247 of file stm32l4xx_ll_swpmi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration

Functions
Configuration
SWPMI Exported Functions

Functions

__STATIC_INLINE void | LL_SWPMI_SetReceptionMode (SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
Set Reception buffering mode.
__STATIC_INLINE uint32_t | LL_SWPMI_GetReceptionMode (SWPMI_TypeDef *SWPMIx)
Get Reception buffering mode.
__STATIC_INLINE void | LL_SWPMI_SetTransmissionMode (SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
Set Transmission buffering mode.
__STATIC_INLINE uint32_t | LL_SWPMI_GetTransmissionMode (SWPMI_TypeDef *SWPMIx)
Get Transmission buffering mode.
__STATIC_INLINE void | LL_SWPMI_EnableLoopback (SWPMI_TypeDef *SWPMIx)
Enable loopback mode.
__STATIC_INLINE void | LL_SWPMI_DisableLoopback (SWPMI_TypeDef *SWPMIx)
Disable loopback mode.
__STATIC_INLINE void | LL_SWPMI_Activate (SWPMI_TypeDef *SWPMIx)
Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActivated (SWPMI_TypeDef *SWPMIx)
Check if Single wire protocol bus is in ACTIVATED state.
__STATIC_INLINE void | LL_SWPMI_Deactivate (SWPMI_TypeDef *SWPMIx)
Deactivate immediately Single wire protocol bus (immediate transition to DEACTIVATED state)
__STATIC_INLINE void | LL_SWPMI_RequestDeactivation (SWPMI_TypeDef *SWPMIx)
Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED state if no resume from slave)
__STATIC_INLINE void | LL_SWPMI_SetBitRatePrescaler (SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)
__STATIC_INLINE uint32_t | LL_SWPMI_GetBitRatePrescaler (SWPMI_TypeDef *SWPMIx)
Get Bitrate prescaler.
__STATIC_INLINE void | LL_SWPMI_SetVoltageClass (SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
Set SWP Voltage Class.
__STATIC_INLINE uint32_t | LL_SWPMI_GetVoltageClass (SWPMI_TypeDef *SWPMIx)
Get SWP Voltage Class.

Function Documentation

__STATIC_INLINE void LL_SWPMI_Activate ( SWPMI_TypeDef * SWPMIx )

Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)

Note:
SWP bus stays in the ACTIVATED state as long as there is a communication with the slave, either in transmission or in reception. The SWP bus switches back to the SUSPENDED state as soon as there is no more transmission or reception activity, after 7 idle bits.
Reference Manual to LL API cross reference:
CR SWPACT LL_SWPMI_Activate
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 354 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_Deactivate ( SWPMI_TypeDef * SWPMIx )

Deactivate immediately Single wire protocol bus (immediate transition to DEACTIVATED state)

Reference Manual to LL API cross reference:
CR SWPACT LL_SWPMI_Deactivate
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 381 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableLoopback ( SWPMI_TypeDef * SWPMIx )

Disable loopback mode.

Reference Manual to LL API cross reference:
CR LPBK LL_SWPMI_DisableLoopback
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 339 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableLoopback ( SWPMI_TypeDef * SWPMIx )

Enable loopback mode.

Reference Manual to LL API cross reference:
CR LPBK LL_SWPMI_EnableLoopback
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 328 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler ( SWPMI_TypeDef * SWPMIx )

Get Bitrate prescaler.

Reference Manual to LL API cross reference:
BRR BR LL_SWPMI_GetBitRatePrescaler
Parameters:
SWPMIx SWPMI Instance
Return values:
A number between Min_Data=0 and Max_Data=63

Definition at line 416 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode ( SWPMI_TypeDef * SWPMIx )

Get Reception buffering mode.

Reference Manual to LL API cross reference:
CR RXMODE LL_SWPMI_GetReceptionMode
Parameters:
SWPMIx SWPMI Instance
Return values:
Returned value can be one of the following values:
  • LL_SWPMI_SW_BUFFER_RX_SINGLE
  • LL_SWPMI_SW_BUFFER_RX_MULTI

Definition at line 289 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode ( SWPMI_TypeDef * SWPMIx )

Get Transmission buffering mode.

Reference Manual to LL API cross reference:
CR TXMODE LL_SWPMI_GetTransmissionMode
Parameters:
SWPMIx SWPMI Instance
Return values:
Returned value can be one of the following values:
  • LL_SWPMI_SW_BUFFER_TX_SINGLE
  • LL_SWPMI_SW_BUFFER_TX_MULTI

Definition at line 317 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass ( SWPMI_TypeDef * SWPMIx )

Get SWP Voltage Class.

Reference Manual to LL API cross reference:
OR CLASS LL_SWPMI_GetVoltageClass
Parameters:
SWPMIx SWPMI Instance
Return values:
Returned value can be one of the following values:
  • LL_SWPMI_VOLTAGE_CLASS_C
  • LL_SWPMI_VOLTAGE_CLASS_B

Definition at line 443 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActivated ( SWPMI_TypeDef * SWPMIx )

Check if Single wire protocol bus is in ACTIVATED state.

Reference Manual to LL API cross reference:
CR SWPACT LL_SWPMI_Activate
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 369 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init().

__STATIC_INLINE void LL_SWPMI_RequestDeactivation ( SWPMI_TypeDef * SWPMIx )

Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED state if no resume from slave)

Reference Manual to LL API cross reference:
CR DEACT LL_SWPMI_RequestDeactivation
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 393 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | BitRatePrescaler
 | ) |  |

Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)

Reference Manual to LL API cross reference:
BRR BR LL_SWPMI_SetBitRatePrescaler
Parameters:
SWPMIx | SWPMI Instance
BitRatePrescaler | A number between Min_Data=0 and Max_Data=63
Return values:
None

Definition at line 405 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init().

__STATIC_INLINE void LL_SWPMI_SetReceptionMode | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | RxBufferingMode
 | ) |  |

Set Reception buffering mode.

Note:
If Multi software buffer mode is chosen, RXDMA bits must also be set.
Reference Manual to LL API cross reference:
CR RXMODE LL_SWPMI_SetReceptionMode
Parameters:
SWPMIx SWPMI Instance
RxBufferingMode This parameter can be one of the following values:
  • LL_SWPMI_SW_BUFFER_RX_SINGLE
  • LL_SWPMI_SW_BUFFER_RX_MULTI
Return values:
None

Definition at line 276 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_SetTransmissionMode | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | TxBufferingMode
 | ) |  |

Set Transmission buffering mode.

Note:
If Multi software buffer mode is chosen, TXDMA bits must also be set.
Reference Manual to LL API cross reference:
CR TXMODE LL_SWPMI_SetTransmissionMode
Parameters:
SWPMIx SWPMI Instance
TxBufferingMode This parameter can be one of the following values:
  • LL_SWPMI_SW_BUFFER_TX_SINGLE
  • LL_SWPMI_SW_BUFFER_TX_MULTI
Return values:
None

Definition at line 304 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_SetVoltageClass | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | VoltageClass
 | ) |  |

Set SWP Voltage Class.

Reference Manual to LL API cross reference:
OR CLASS LL_SWPMI_SetVoltageClass
Parameters:
SWPMIx SWPMI Instance
VoltageClass This parameter can be one of the following values:
  • LL_SWPMI_VOLTAGE_CLASS_C
  • LL_SWPMI_VOLTAGE_CLASS_B
Return values:
None

Definition at line 430 of file stm32l4xx_ll_swpmi.h.

Referenced by LL_SWPMI_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
SWPMI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXBF (SWPMI_TypeDef *SWPMIx)
Check if the last word of the frame under reception has arrived in SWPMI_RDR.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXBE (SWPMI_TypeDef *SWPMIx)
Check if Frame transmission buffer has been emptied.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXBER (SWPMI_TypeDef *SWPMIx)
Check if CRC error in reception has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXOVR (SWPMI_TypeDef *SWPMIx)
Check if Overrun in reception has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXUNR (SWPMI_TypeDef *SWPMIx)
Check if underrun error in transmission has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXNE (SWPMI_TypeDef *SWPMIx)
Check if Receive data register not empty (it means that Received data is ready to be read in the SWPMI_RDR register)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXE (SWPMI_TypeDef *SWPMIx)
Check if Transmit data register is empty (it means that Data written in transmit data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TC (SWPMI_TypeDef *SWPMIx)
Check if Both transmission and reception are completed and SWP is switched to the SUSPENDED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_SR (SWPMI_TypeDef *SWPMIx)
Check if a Resume by slave state has been detected during the SWP bus SUSPENDED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_SUSP (SWPMI_TypeDef *SWPMIx)
Check if SWP bus is in SUSPENDED or DEACTIVATED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_DEACT (SWPMI_TypeDef *SWPMIx)
Check if SWP bus is in DEACTIVATED state.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXBF (SWPMI_TypeDef *SWPMIx)
Clear receive buffer full flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TXBE (SWPMI_TypeDef *SWPMIx)
Clear transmit buffer empty flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXBER (SWPMI_TypeDef *SWPMIx)
Clear receive CRC error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXOVR (SWPMI_TypeDef *SWPMIx)
Clear receive overrun error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TXUNR (SWPMI_TypeDef *SWPMIx)
Clear transmit underrun error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TC (SWPMI_TypeDef *SWPMIx)
Clear transfer complete flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_SR (SWPMI_TypeDef *SWPMIx)
Clear slave resume flag.

Function Documentation

__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER ( SWPMI_TypeDef * SWPMIx )

Clear receive CRC error flag.

Reference Manual to LL API cross reference:
ICR CRXBERF LL_SWPMI_ClearFlag_RXBER
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 609 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF ( SWPMI_TypeDef * SWPMIx )

Clear receive buffer full flag.

Reference Manual to LL API cross reference:
ICR CRXBFF LL_SWPMI_ClearFlag_RXBF
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 587 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR ( SWPMI_TypeDef * SWPMIx )

Clear receive overrun error flag.

Reference Manual to LL API cross reference:
ICR CRXOVRF LL_SWPMI_ClearFlag_RXOVR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 620 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_SR ( SWPMI_TypeDef * SWPMIx )

Clear slave resume flag.

Reference Manual to LL API cross reference:
ICR CSRF LL_SWPMI_ClearFlag_SR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 653 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_TC ( SWPMI_TypeDef * SWPMIx )

Clear transfer complete flag.

Reference Manual to LL API cross reference:
ICR CTCF LL_SWPMI_ClearFlag_TC
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 642 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE ( SWPMI_TypeDef * SWPMIx )

Clear transmit buffer empty flag.

Reference Manual to LL API cross reference:
ICR CTXBEF LL_SWPMI_ClearFlag_TXBE
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 598 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR ( SWPMI_TypeDef * SWPMIx )

Clear transmit underrun error flag.

Reference Manual to LL API cross reference:
ICR CTXUNRF LL_SWPMI_ClearFlag_TXUNR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 631 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT ( SWPMI_TypeDef * SWPMIx )

Check if SWP bus is in DEACTIVATED state.

Reference Manual to LL API cross reference:
ISR DEACTF LL_SWPMI_IsActiveFlag_DEACT
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 576 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER ( SWPMI_TypeDef * SWPMIx )

Check if CRC error in reception has been detected.

Reference Manual to LL API cross reference:
ISR RXBERF LL_SWPMI_IsActiveFlag_RXBER
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 484 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF ( SWPMI_TypeDef * SWPMIx )

Check if the last word of the frame under reception has arrived in SWPMI_RDR.

Reference Manual to LL API cross reference:
ISR RXBFF LL_SWPMI_IsActiveFlag_RXBF
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 462 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE ( SWPMI_TypeDef * SWPMIx )

Check if Receive data register not empty (it means that Received data is ready to be read in the SWPMI_RDR register)

Reference Manual to LL API cross reference:
ISR RXNE LL_SWPMI_IsActiveFlag_RXNE
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 518 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR ( SWPMI_TypeDef * SWPMIx )

Check if Overrun in reception has been detected.

Reference Manual to LL API cross reference:
ISR RXOVRF LL_SWPMI_IsActiveFlag_RXOVR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 495 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR ( SWPMI_TypeDef * SWPMIx )

Check if a Resume by slave state has been detected during the SWP bus SUSPENDED state.

Reference Manual to LL API cross reference:
ISR SRF LL_SWPMI_IsActiveFlag_SR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 554 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP ( SWPMI_TypeDef * SWPMIx )

Check if SWP bus is in SUSPENDED or DEACTIVATED state.

Reference Manual to LL API cross reference:
ISR SUSP LL_SWPMI_IsActiveFlag_SUSP
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 565 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC ( SWPMI_TypeDef * SWPMIx )

Check if Both transmission and reception are completed and SWP is switched to the SUSPENDED state.

Reference Manual to LL API cross reference:
ISR TCF LL_SWPMI_IsActiveFlag_TC
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 542 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE ( SWPMI_TypeDef * SWPMIx )

Check if Frame transmission buffer has been emptied.

Reference Manual to LL API cross reference:
ISR TXBEF LL_SWPMI_IsActiveFlag_TXBE
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 473 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE ( SWPMI_TypeDef * SWPMIx )

Check if Transmit data register is empty (it means that Data written in transmit data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)

Reference Manual to LL API cross reference:
ISR TXE LL_SWPMI_IsActiveFlag_TXE
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 530 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR ( SWPMI_TypeDef * SWPMIx )

Check if underrun error in transmission has been detected.

Reference Manual to LL API cross reference:
ISR TXUNRF LL_SWPMI_IsActiveFlag_TXUNR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 506 of file stm32l4xx_ll_swpmi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT_Management

Functions
IT_Management
SWPMI Exported Functions

Functions

__STATIC_INLINE void | LL_SWPMI_EnableIT_SR (SWPMI_TypeDef *SWPMIx)
Enable Slave resume interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TC (SWPMI_TypeDef *SWPMIx)
Enable Transmit complete interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TX (SWPMI_TypeDef *SWPMIx)
Enable Transmit interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RX (SWPMI_TypeDef *SWPMIx)
Enable Receive interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Enable Transmit underrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Enable Receive overrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXBER (SWPMI_TypeDef *SWPMIx)
Enable Receive CRC error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TXBE (SWPMI_TypeDef *SWPMIx)
Enable Transmit buffer empty interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXBF (SWPMI_TypeDef *SWPMIx)
Enable Receive buffer full interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_SR (SWPMI_TypeDef *SWPMIx)
Disable Slave resume interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TC (SWPMI_TypeDef *SWPMIx)
Disable Transmit complete interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TX (SWPMI_TypeDef *SWPMIx)
Disable Transmit interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RX (SWPMI_TypeDef *SWPMIx)
Disable Receive interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Disable Transmit underrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Disable Receive overrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXBER (SWPMI_TypeDef *SWPMIx)
Disable Receive CRC error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TXBE (SWPMI_TypeDef *SWPMIx)
Disable Transmit buffer empty interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXBF (SWPMI_TypeDef *SWPMIx)
Disable Receive buffer full interrupt.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_SR (SWPMI_TypeDef *SWPMIx)
Check if Slave resume interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TC (SWPMI_TypeDef *SWPMIx)
Check if Transmit complete interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TX (SWPMI_TypeDef *SWPMIx)
Check if Transmit interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RX (SWPMI_TypeDef *SWPMIx)
Check if Receive interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Check if Transmit underrun error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Check if Receive overrun error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXBER (SWPMI_TypeDef *SWPMIx)
Check if Receive CRC error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TXBE (SWPMI_TypeDef *SWPMIx)
Check if Transmit buffer empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXBF (SWPMI_TypeDef *SWPMIx)
Check if Receive buffer full interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_SWPMI_DisableIT_RX ( SWPMI_TypeDef * SWPMIx )

Disable Receive interrupt.

Reference Manual to LL API cross reference:
IER RIE LL_SWPMI_DisableIT_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 804 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_RXBER ( SWPMI_TypeDef * SWPMIx )

Disable Receive CRC error interrupt.

Reference Manual to LL API cross reference:
IER RXBERIE LL_SWPMI_DisableIT_RXBER
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 837 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_RXBF ( SWPMI_TypeDef * SWPMIx )

Disable Receive buffer full interrupt.

Reference Manual to LL API cross reference:
IER RXBFIE LL_SWPMI_DisableIT_RXBF
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 859 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR ( SWPMI_TypeDef * SWPMIx )

Disable Receive overrun error interrupt.

Reference Manual to LL API cross reference:
IER RXOVRIE LL_SWPMI_DisableIT_RXOVR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 826 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_SR ( SWPMI_TypeDef * SWPMIx )

Disable Slave resume interrupt.

Reference Manual to LL API cross reference:
IER SRIE LL_SWPMI_DisableIT_SR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 771 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_TC ( SWPMI_TypeDef * SWPMIx )

Disable Transmit complete interrupt.

Reference Manual to LL API cross reference:
IER TCIE LL_SWPMI_DisableIT_TC
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 782 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_TX ( SWPMI_TypeDef * SWPMIx )

Disable Transmit interrupt.

Reference Manual to LL API cross reference:
IER TIE LL_SWPMI_DisableIT_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 793 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_TXBE ( SWPMI_TypeDef * SWPMIx )

Disable Transmit buffer empty interrupt.

Reference Manual to LL API cross reference:
IER TXBEIE LL_SWPMI_DisableIT_TXBE
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 848 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR ( SWPMI_TypeDef * SWPMIx )

Disable Transmit underrun error interrupt.

Reference Manual to LL API cross reference:
IER TXUNRIE LL_SWPMI_DisableIT_TXUNR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 815 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_RX ( SWPMI_TypeDef * SWPMIx )

Enable Receive interrupt.

Reference Manual to LL API cross reference:
IER RIE LL_SWPMI_EnableIT_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 705 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_RXBER ( SWPMI_TypeDef * SWPMIx )

Enable Receive CRC error interrupt.

Reference Manual to LL API cross reference:
IER RXBERIE LL_SWPMI_EnableIT_RXBER
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 738 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_RXBF ( SWPMI_TypeDef * SWPMIx )

Enable Receive buffer full interrupt.

Reference Manual to LL API cross reference:
IER RXBFIE LL_SWPMI_EnableIT_RXBF
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 760 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR ( SWPMI_TypeDef * SWPMIx )

Enable Receive overrun error interrupt.

Reference Manual to LL API cross reference:
IER RXOVRIE LL_SWPMI_EnableIT_RXOVR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 727 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_SR ( SWPMI_TypeDef * SWPMIx )

Enable Slave resume interrupt.

Reference Manual to LL API cross reference:
IER SRIE LL_SWPMI_EnableIT_SR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 672 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_TC ( SWPMI_TypeDef * SWPMIx )

Enable Transmit complete interrupt.

Reference Manual to LL API cross reference:
IER TCIE LL_SWPMI_EnableIT_TC
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 683 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_TX ( SWPMI_TypeDef * SWPMIx )

Enable Transmit interrupt.

Reference Manual to LL API cross reference:
IER TIE LL_SWPMI_EnableIT_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 694 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_TXBE ( SWPMI_TypeDef * SWPMIx )

Enable Transmit buffer empty interrupt.

Reference Manual to LL API cross reference:
IER TXBEIE LL_SWPMI_EnableIT_TXBE
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 749 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR ( SWPMI_TypeDef * SWPMIx )

Enable Transmit underrun error interrupt.

Reference Manual to LL API cross reference:
IER TXUNRIE LL_SWPMI_EnableIT_TXUNR
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 716 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX ( SWPMI_TypeDef * SWPMIx )

Check if Receive interrupt is enabled.

Reference Manual to LL API cross reference:
IER RIE LL_SWPMI_IsEnabledIT_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 903 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER ( SWPMI_TypeDef * SWPMIx )

Check if Receive CRC error interrupt is enabled.

Reference Manual to LL API cross reference:
IER RXBERIE LL_SWPMI_IsEnabledIT_RXBER
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 936 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF ( SWPMI_TypeDef * SWPMIx )

Check if Receive buffer full interrupt is enabled.

Reference Manual to LL API cross reference:
IER RXBFIE LL_SWPMI_IsEnabledIT_RXBF
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 958 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR ( SWPMI_TypeDef * SWPMIx )

Check if Receive overrun error interrupt is enabled.

Reference Manual to LL API cross reference:
IER RXOVRIE LL_SWPMI_IsEnabledIT_RXOVR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 925 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR ( SWPMI_TypeDef * SWPMIx )

Check if Slave resume interrupt is enabled.

Reference Manual to LL API cross reference:
IER SRIE LL_SWPMI_IsEnabledIT_SR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 870 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC ( SWPMI_TypeDef * SWPMIx )

Check if Transmit complete interrupt is enabled.

Reference Manual to LL API cross reference:
IER TCIE LL_SWPMI_IsEnabledIT_TC
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 881 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX ( SWPMI_TypeDef * SWPMIx )

Check if Transmit interrupt is enabled.

Reference Manual to LL API cross reference:
IER TIE LL_SWPMI_IsEnabledIT_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 892 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE ( SWPMI_TypeDef * SWPMIx )

Check if Transmit buffer empty interrupt is enabled.

Reference Manual to LL API cross reference:
IER TXBEIE LL_SWPMI_IsEnabledIT_TXBE
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 947 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR ( SWPMI_TypeDef * SWPMIx )

Check if Transmit underrun error interrupt is enabled.

Reference Manual to LL API cross reference:
IER TXUNRIE LL_SWPMI_IsEnabledIT_TXUNR
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 914 of file stm32l4xx_ll_swpmi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA_Management

Functions
DMA_Management
SWPMI Exported Functions

Functions

__STATIC_INLINE void | LL_SWPMI_EnableDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Enable DMA mode for reception.
__STATIC_INLINE void | LL_SWPMI_DisableDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Disable DMA mode for reception.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Check if DMA mode for reception is enabled.
__STATIC_INLINE void | LL_SWPMI_EnableDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Enable DMA mode for transmission.
__STATIC_INLINE void | LL_SWPMI_DisableDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Disable DMA mode for transmission.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Check if DMA mode for transmission is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_DMA_GetRegAddr (SWPMI_TypeDef *SWPMIx, uint32_t Direction)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX ( SWPMI_TypeDef * SWPMIx )

Disable DMA mode for reception.

Reference Manual to LL API cross reference:
CR RXDMA LL_SWPMI_DisableDMAReq_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 988 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX ( SWPMI_TypeDef * SWPMIx )

Disable DMA mode for transmission.

Reference Manual to LL API cross reference:
CR TXDMA LL_SWPMI_DisableDMAReq_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 1021 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
TDR TD LL_SWPMI_DMA_GetRegAddr
RDR RD LL_SWPMI_DMA_GetRegAddr
Parameters:
SWPMIx SWPMI Instance
Direction This parameter can be one of the following values:
  • LL_SWPMI_DMA_REG_DATA_TRANSMIT
  • LL_SWPMI_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 1047 of file stm32l4xx_ll_swpmi.h.

References LL_SWPMI_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX ( SWPMI_TypeDef * SWPMIx )

Enable DMA mode for reception.

Reference Manual to LL API cross reference:
CR RXDMA LL_SWPMI_EnableDMAReq_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 977 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX ( SWPMI_TypeDef * SWPMIx )

Enable DMA mode for transmission.

Reference Manual to LL API cross reference:
CR TXDMA LL_SWPMI_EnableDMAReq_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 1010 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX ( SWPMI_TypeDef * SWPMIx )

Check if DMA mode for reception is enabled.

Reference Manual to LL API cross reference:
CR RXDMA LL_SWPMI_IsEnabledDMAReq_RX
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 999 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX ( SWPMI_TypeDef * SWPMIx )

Check if DMA mode for transmission is enabled.

Reference Manual to LL API cross reference:
CR TXDMA LL_SWPMI_IsEnabledDMAReq_TX
Parameters:
SWPMIx SWPMI Instance
Return values:
State of bit (1 or 0).

Definition at line 1032 of file stm32l4xx_ll_swpmi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data_Management

Functions
Data_Management
SWPMI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SWPMI_GetReceiveFrameLength (SWPMI_TypeDef *SWPMIx)
Retrieve number of data bytes present in payload of received frame.
__STATIC_INLINE void | LL_SWPMI_TransmitData32 (SWPMI_TypeDef *SWPMIx, uint32_t TxData)
Transmit Data Register.
__STATIC_INLINE uint32_t | LL_SWPMI_ReceiveData32 (SWPMI_TypeDef *SWPMIx)
Receive Data Register.
__STATIC_INLINE void | LL_SWPMI_EnableTXBypass (SWPMI_TypeDef *SWPMIx)
Enable SWP Transceiver Bypass.
__STATIC_INLINE void | LL_SWPMI_DisableTXBypass (SWPMI_TypeDef *SWPMIx)
Disable SWP Transceiver Bypass.

Function Documentation

__STATIC_INLINE void LL_SWPMI_DisableTXBypass ( SWPMI_TypeDef * SWPMIx )

Disable SWP Transceiver Bypass.

Note:
SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate function on GPIOs. This configuration is selected to connect an external transceiver
Reference Manual to LL API cross reference:
OR TBYP LL_SWPMI_DisableTXBypass
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 1128 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_EnableTXBypass ( SWPMI_TypeDef * SWPMIx )

Enable SWP Transceiver Bypass.

Note:
The external interface for SWPMI is SWPMI_IO (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
Reference Manual to LL API cross reference:
OR TBYP LL_SWPMI_EnableTXBypass
Parameters:
SWPMIx SWPMI Instance
Return values:
None

Definition at line 1115 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength ( SWPMI_TypeDef * SWPMIx )

Retrieve number of data bytes present in payload of received frame.

Reference Manual to LL API cross reference:
RFL RFL LL_SWPMI_GetReceiveFrameLength
Parameters:
SWPMIx SWPMI Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x1F

Definition at line 1079 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32 ( SWPMI_TypeDef * SWPMIx )

Receive Data Register.

Reference Manual to LL API cross reference:
RDR RD LL_SWPMI_ReceiveData32
Parameters:
SWPMIx SWPMI Instance
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 1102 of file stm32l4xx_ll_swpmi.h.

__STATIC_INLINE void LL_SWPMI_TransmitData32 | ( | SWPMI_TypeDef * | SWPMIx,
 |  | uint32_t | TxData
 | ) |  |

Transmit Data Register.

Reference Manual to LL API cross reference:
TDR TD LL_SWPMI_TransmitData32
Parameters:
SWPMIx | SWPMI Instance
TxData | Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 1091 of file stm32l4xx_ll_swpmi.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SWPMI Exported Functions

Functions

ErrorStatus | LL_SWPMI_DeInit (SWPMI_TypeDef *SWPMIx)
De-initialize the SWPMI peripheral registers to their default reset values.
ErrorStatus | LL_SWPMI_Init (SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
void | LL_SWPMI_StructInit (LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Set each LL_SWPMI_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_SWPMI_DeInit ( SWPMI_TypeDef * SWPMIx )

De-initialize the SWPMI peripheral registers to their default reset values.

Parameters:
SWPMIx SWPMI Instance
Return values:
An ErrorStatus enumeration value
  • SUCCESS: SWPMI registers are de-initialized
  • ERROR: Not applicable

Definition at line 99 of file stm32l4xx_ll_swpmi.c.

References assert_param, LL_APB1_GRP2_ForceReset(), LL_APB1_GRP2_PERIPH_SWPMI1, and LL_APB1_GRP2_ReleaseReset().

ErrorStatus LL_SWPMI_Init | ( | SWPMI_TypeDef * | SWPMIx,
 |  | LL_SWPMI_InitTypeDef * | SWPMI_InitStruct
 | ) |  |

Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.

Note:
As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated (SWPMI_CR_SWPACT bit = 0), SWPMI IP should be in deactivated state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SWPMIx | SWPMI Instance
SWPMI_InitStruct | pointer to a LL_SWPMI_InitTypeDef structure that contains the configuration information for the SWPMI peripheral.
Return values:
An ErrorStatus enumeration value
  • SUCCESS: SWPMI registers are initialized
  • ERROR: SWPMI registers are not initialized

Definition at line 121 of file stm32l4xx_ll_swpmi.c.

References assert_param, LL_SWPMI_InitTypeDef::BitRatePrescaler, IS_LL_SWPMI_BITRATE_VALUE, IS_LL_SWPMI_SW_BUFFER_RX, IS_LL_SWPMI_SW_BUFFER_TX, IS_LL_SWPMI_VOLTAGE_CLASS, LL_SWPMI_IsActivated(), LL_SWPMI_SetBitRatePrescaler(), LL_SWPMI_SetVoltageClass(), LL_SWPMI_InitTypeDef::RxBufferingMode, LL_SWPMI_InitTypeDef::TxBufferingMode, and LL_SWPMI_InitTypeDef::VoltageClass.

void LL_SWPMI_StructInit ( LL_SWPMI_InitTypeDef * SWPMI_InitStruct )

Set each LL_SWPMI_InitTypeDef field to default value.

Parameters:
SWPMI_InitStruct pointer to a LL_SWPMI_InitTypeDef structure that contains the configuration information for the SWPMI peripheral.
Return values:
None

Definition at line 161 of file stm32l4xx_ll_swpmi.c.

References LL_SWPMI_InitTypeDef::BitRatePrescaler, LL_SWPMI_SW_BUFFER_RX_SINGLE, LL_SWPMI_SW_BUFFER_TX_SINGLE, LL_SWPMI_VOLTAGE_CLASS_C, LL_SWPMI_InitTypeDef::RxBufferingMode, LL_SWPMI_InitTypeDef::TxBufferingMode, and LL_SWPMI_InitTypeDef::VoltageClass.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSTEM

Modules
SYSTEM
STM32L4xx_LL_Driver

Modules

SYSTEM Private Constants
SYSTEM Exported Constants
SYSTEM Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for SYSTEM registers.

Register | Bit | Function
DBGMCU_APB1FZR1 | DBG_xxxx_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_APB1FZR2 | DBG_xxxx_STOP | LL_DBGMCU_APB1_GRP2_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP2_UnFreezePeriph
DBGMCU_APB2FZ | DBG_TIMx_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB2_GRP1_UnFreezePeriph
DBGMCU_CR | DBG_SLEEP | LL_DBGMCU_DisableDBGSleepMode
 |  | LL_DBGMCU_EnableDBGSleepMode
 | DBG_STANDBY | LL_DBGMCU_DisableDBGStandbyMode
 |  | LL_DBGMCU_EnableDBGStandbyMode
 | DBG_STOP | LL_DBGMCU_DisableDBGStopMode
 |  | LL_DBGMCU_EnableDBGStopMode
 | TRACE_IOEN | LL_DBGMCU_GetTracePinAssignment
 |  | LL_DBGMCU_SetTracePinAssignment
 | TRACE_MODE | LL_DBGMCU_GetTracePinAssignment
 |  | LL_DBGMCU_SetTracePinAssignment
DBGMCU_IDCODE | DEV_ID | LL_DBGMCU_GetDeviceID
 | REV_ID | LL_DBGMCU_GetRevisionID
FLASH_ACR | DCEN | LL_FLASH_DisableDataCache
 |  | LL_FLASH_EnableDataCache
 | DCRST | LL_FLASH_DisableDataCacheReset
 |  | LL_FLASH_EnableDataCacheReset
 | ICEN | LL_FLASH_DisableInstCache
 |  | LL_FLASH_EnableInstCache
 | ICRST | LL_FLASH_DisableInstCacheReset
 |  | LL_FLASH_EnableInstCacheReset
 | LATENCY | LL_FLASH_GetLatency
 |  | LL_FLASH_SetLatency
 | PRFTEN | LL_FLASH_DisablePrefetch
 |  | LL_FLASH_EnablePrefetch
 |  | LL_FLASH_IsPrefetchEnabled
 | RUN_PD | LL_FLASH_DisableRunPowerDown
 |  | LL_FLASH_EnableRunPowerDown
 | SLEEP_PD | LL_FLASH_DisableSleepPowerDown
 |  | LL_FLASH_EnableSleepPowerDown
FLASH_PDKEYR | PDKEY1 | LL_FLASH_DisableRunPowerDown
 |  | LL_FLASH_EnableRunPowerDown
 | PDKEY2 | LL_FLASH_DisableRunPowerDown
 |  | LL_FLASH_EnableRunPowerDown
SYSCFG_CFGR1 | BOOSTEN | LL_SYSCFG_DisableAnalogBooster
 |  | LL_SYSCFG_EnableAnalogBooster
 | FPU_IE_0 | LL_SYSCFG_DisableIT_FPU_IOC
 |  | LL_SYSCFG_EnableIT_FPU_IOC
 |  | LL_SYSCFG_IsEnabledIT_FPU_IOC
 | FPU_IE_1 | LL_SYSCFG_DisableIT_FPU_DZC
 |  | LL_SYSCFG_EnableIT_FPU_DZC
 |  | LL_SYSCFG_IsEnabledIT_FPU_DZC
 | FPU_IE_2 | LL_SYSCFG_DisableIT_FPU_UFC
 |  | LL_SYSCFG_EnableIT_FPU_UFC
 |  | LL_SYSCFG_IsEnabledIT_FPU_UFC
 | FPU_IE_3 | LL_SYSCFG_DisableIT_FPU_OFC
 |  | LL_SYSCFG_EnableIT_FPU_OFC
 |  | LL_SYSCFG_IsEnabledIT_FPU_OFC
 | FPU_IE_4 | LL_SYSCFG_DisableIT_FPU_IDC
 |  | LL_SYSCFG_EnableIT_FPU_IDC
 |  | LL_SYSCFG_IsEnabledIT_FPU_IDC
 | FPU_IE_5 | LL_SYSCFG_DisableIT_FPU_IXC
 |  | LL_SYSCFG_EnableIT_FPU_IXC
 |  | LL_SYSCFG_IsEnabledIT_FPU_IXC
 | FWDIS | LL_SYSCFG_EnableFirewall
 |  | LL_SYSCFG_IsEnabledFirewall
 | I2C_PBx_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
 | I2Cx_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR2 | CLL | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
 | ECCL | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
 | PVDL | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
 | SPF | LL_SYSCFG_ClearFlag_SP
 |  | LL_SYSCFG_IsActiveFlag_SP
 | SPL | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
SYSCFG_EXTICR1 | EXTIx | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 | EXTIx | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 | EXTIx | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 | EXTIx | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_MEMRMP | FB_MODE | LL_SYSCFG_GetFlashBankMode
 |  | LL_SYSCFG_SetFlashBankMode
 | MEM_MODE | LL_SYSCFG_GetRemapMemory
 |  | LL_SYSCFG_SetRemapMemory
SYSCFG_SCSR | SRAM2BSY | LL_SYSCFG_IsSRAM2EraseOngoing
 | SRAM2ER | LL_SYSCFG_EnableSRAM2Erase
SYSCFG_SKR | KEY | LL_SYSCFG_LockSRAM2WRP
 |  | LL_SYSCFG_UnlockSRAM2WRP
SYSCFG_SWPR | PAGEx | LL_SYSCFG_EnableSRAM2PageWRP
VREFBUF_CCR | TRIM | LL_VREFBUF_GetTrimming
 |  | LL_VREFBUF_SetTrimming
VREFBUF_CSR | ENVR | LL_VREFBUF_Disable
 |  | LL_VREFBUF_Enable
 | HIZ | LL_VREFBUF_DisableHIZ
 |  | LL_VREFBUF_EnableHIZ
 | VRR | LL_VREFBUF_IsVREFReady
 | VRS | LL_VREFBUF_GetVoltageScaling
 |  | LL_VREFBUF_SetVoltageScaling
Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSTEM Private Constants

Defines
SYSTEM Private Constants
SYSTEM

Defines

#define | DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
#define | FLASH_PDKEY1 ((uint32_t)0x04152637U)
Power-down in Run mode Flash key.
#define | FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU)

Define Documentation

#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)

Definition at line 81 of file stm32l4xx_ll_system.h.

Referenced by LL_DBGMCU_GetRevisionID().

#define FLASH_PDKEY1 ((uint32_t)0x04152637U)

Power-down in Run mode Flash key.

Flash power down key1

Definition at line 86 of file stm32l4xx_ll_system.h.

Referenced by LL_FLASH_DisableRunPowerDown(), and LL_FLASH_EnableRunPowerDown().

#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU)

Flash power down key2: used with FLASH_PDKEY1 to unlock the RUN_PD bit in FLASH_ACR

Definition at line 87 of file stm32l4xx_ll_system.h.

Referenced by LL_FLASH_DisableRunPowerDown(), and LL_FLASH_EnableRunPowerDown().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSCFG REMAP

Defines
SYSCFG REMAP
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000
#define | LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#define | LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#define | LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1
#define | LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)

Define Documentation

#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000

Main Flash memory mapped at 0x00000000

Definition at line 105 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1

FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000

Definition at line 109 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)

QUADSPI memory mapped at 0x00000000

Definition at line 111 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)

SRAM1 mapped at 0x00000000

Definition at line 107 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0

System Flash memory mapped at 0x00000000

Definition at line 106 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSCFG BANK MODE

Defines
SYSCFG BANK MODE
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000
#define | LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE

Define Documentation

#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000

Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000)

Definition at line 120 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE

Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000)

Definition at line 122 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSCFG I2C FASTMODEPLUS

Defines
SYSCFG I2C FASTMODEPLUS
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Define Documentation

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 140 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Enable Fast Mode Plus on I2C2 pins

Definition at line 142 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable Fast Mode Plus on I2C3 pins

Definition at line 144 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 132 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 133 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 135 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 138 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSCFG EXTI PORT

Defines
SYSCFG EXTI PORT
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_EXTI_PORTA (uint32_t)0
#define | LL_SYSCFG_EXTI_PORTB (uint32_t)1
#define | LL_SYSCFG_EXTI_PORTC (uint32_t)2
#define | LL_SYSCFG_EXTI_PORTD (uint32_t)3
#define | LL_SYSCFG_EXTI_PORTE (uint32_t)4
#define | LL_SYSCFG_EXTI_PORTF (uint32_t)5
#define | LL_SYSCFG_EXTI_PORTG (uint32_t)6
#define | LL_SYSCFG_EXTI_PORTH (uint32_t)7

Define Documentation

#define LL_SYSCFG_EXTI_PORTA (uint32_t)0

EXTI PORT A

Definition at line 152 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTB (uint32_t)1

EXTI PORT B

Definition at line 153 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTC (uint32_t)2

EXTI PORT C

Definition at line 154 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTD (uint32_t)3

EXTI PORT D

Definition at line 155 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTE (uint32_t)4

EXTI PORT E

Definition at line 156 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTF (uint32_t)5

EXTI PORT F

Definition at line 158 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTG (uint32_t)6

EXTI PORT G

Definition at line 161 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTH (uint32_t)7

EXTI PORT H

Definition at line 163 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSCFG EXTI LINE

Defines
SYSCFG EXTI LINE
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /* !< EXTI_POSITION_0 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /* !< EXTI_POSITION_4 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /* !< EXTI_POSITION_8 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /* !< EXTI_POSITION_12 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /* !< EXTI_POSITION_0 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /* !< EXTI_POSITION_4 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /* !< EXTI_POSITION_8 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /* !< EXTI_POSITION_12 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /* !< EXTI_POSITION_0 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /* !< EXTI_POSITION_4 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /* !< EXTI_POSITION_8 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /* !< EXTI_POSITION_12 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /* !< EXTI_POSITION_0 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /* !< EXTI_POSITION_4 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /* !< EXTI_POSITION_8 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /* !< EXTI_POSITION_12 | EXTICR[3] */

Define Documentation

#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /* !< EXTI_POSITION_0 | EXTICR[0] */

Definition at line 171 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /* !< EXTI_POSITION_4 | EXTICR[0] */

Definition at line 172 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /* !< EXTI_POSITION_8 | EXTICR[2] */

Definition at line 181 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /* !< EXTI_POSITION_12 | EXTICR[2] */

Definition at line 182 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /* !< EXTI_POSITION_0 | EXTICR[3] */

Definition at line 183 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /* !< EXTI_POSITION_4 | EXTICR[3] */

Definition at line 184 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /* !< EXTI_POSITION_8 | EXTICR[3] */

Definition at line 185 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /* !< EXTI_POSITION_12 | EXTICR[3] */

Definition at line 186 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /* !< EXTI_POSITION_8 | EXTICR[0] */

Definition at line 173 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /* !< EXTI_POSITION_12 | EXTICR[0] */

Definition at line 174 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /* !< EXTI_POSITION_0 | EXTICR[1] */

Definition at line 175 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /* !< EXTI_POSITION_4 | EXTICR[1] */

Definition at line 176 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /* !< EXTI_POSITION_8 | EXTICR[1] */

Definition at line 177 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /* !< EXTI_POSITION_12 | EXTICR[1] */

Definition at line 178 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /* !< EXTI_POSITION_0 | EXTICR[2] */

Definition at line 179 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /* !< EXTI_POSITION_4 | EXTICR[2] */

Definition at line 180 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSCFG TIMER BREAK

Defines
SYSCFG TIMER BREAK
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL
#define | LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL
#define | LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL

Define Documentation

#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17

Definition at line 194 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17

Definition at line 201 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 196 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL

Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17

Definition at line 199 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSCFG SRAM2 WRP

Defines
SYSCFG SRAM2 WRP
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0
#define | LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1
#define | LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2
#define | LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3
#define | LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4
#define | LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5
#define | LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6
#define | LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7
#define | LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8
#define | LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9
#define | LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10
#define | LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11
#define | LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12
#define | LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13
#define | LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14
#define | LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15
#define | LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16
#define | LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17
#define | LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18
#define | LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19
#define | LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20
#define | LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21
#define | LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22
#define | LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23
#define | LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24
#define | LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25
#define | LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26
#define | LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27
#define | LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28
#define | LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29
#define | LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30
#define | LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31

Define Documentation

#define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0

SRAM2 Write protection page 0

Definition at line 210 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1

SRAM2 Write protection page 1

Definition at line 211 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10

SRAM2 Write protection page 10

Definition at line 220 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11

SRAM2 Write protection page 11

Definition at line 221 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12

SRAM2 Write protection page 12

Definition at line 222 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13

SRAM2 Write protection page 13

Definition at line 223 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14

SRAM2 Write protection page 14

Definition at line 224 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15

SRAM2 Write protection page 15

Definition at line 225 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16

SRAM2 Write protection page 16

Definition at line 227 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17

SRAM2 Write protection page 17

Definition at line 228 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18

SRAM2 Write protection page 18

Definition at line 229 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19

SRAM2 Write protection page 19

Definition at line 230 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2

SRAM2 Write protection page 2

Definition at line 212 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20

SRAM2 Write protection page 20

Definition at line 231 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21

SRAM2 Write protection page 21

Definition at line 232 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22

SRAM2 Write protection page 22

Definition at line 233 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23

SRAM2 Write protection page 23

Definition at line 234 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24

SRAM2 Write protection page 24

Definition at line 235 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25

SRAM2 Write protection page 25

Definition at line 236 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26

SRAM2 Write protection page 26

Definition at line 237 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27

SRAM2 Write protection page 27

Definition at line 238 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28

SRAM2 Write protection page 28

Definition at line 239 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29

SRAM2 Write protection page 29

Definition at line 240 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3

SRAM2 Write protection page 3

Definition at line 213 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30

SRAM2 Write protection page 30

Definition at line 241 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31

SRAM2 Write protection page 31

Definition at line 242 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4

SRAM2 Write protection page 4

Definition at line 214 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5

SRAM2 Write protection page 5

Definition at line 215 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6

SRAM2 Write protection page 6

Definition at line 216 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7

SRAM2 Write protection page 7

Definition at line 217 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8

SRAM2 Write protection page 8

Definition at line 218 of file stm32l4xx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9

SRAM2 Write protection page 9

Definition at line 219 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DBGMCU TRACE Pin Assignment

Defines
DBGMCU TRACE Pin Assignment
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000U
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)

Define Documentation

#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN

TRACE pin assignment for Asynchronous Mode

Definition at line 252 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000U

TRACE pins not assigned (default state)

Definition at line 251 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1

Definition at line 253 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2

Definition at line 254 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4

Definition at line 255 of file stm32l4xx_ll_system.h.

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STM32L486xx HAL User Manual: DBGMCU APB1 GRP1 STOP IP

Defines
DBGMCU APB1 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP
#define | LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP

Define Documentation

#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP

The bxCAN receive registers are frozen

Definition at line 285 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP

The I2C1 SMBus timeout is frozen

Definition at line 280 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP

The I2C2 SMBus timeout is frozen

Definition at line 282 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP

The I2C3 SMBus timeout is frozen

Definition at line 284 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP

The independent watchdog counter clock is stopped when the core is halted

Definition at line 279 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP

The counter clock of LPTIM1 is stopped when the core is halted

Definition at line 286 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP

The clock of the RTC counter is stopped when the core is halted

Definition at line 277 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP

The counter clock of TIM2 is stopped when the core is halted

Definition at line 263 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP

The counter clock of TIM3 is stopped when the core is halted

Definition at line 265 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP

The counter clock of TIM4 is stopped when the core is halted

Definition at line 268 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP

The counter clock of TIM5 is stopped when the core is halted

Definition at line 271 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP

The counter clock of TIM6 is stopped when the core is halted

Definition at line 273 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP

The counter clock of TIM7 is stopped when the core is halted

Definition at line 275 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP

The window watchdog counter clock is stopped when the core is halted

Definition at line 278 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DBGMCU APB1 GRP2 STOP IP

Defines
DBGMCU APB1 GRP2 STOP IP
SYSTEM Exported Constants

Defines

#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP

Define Documentation

#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP

The counter clock of LPTIM2 is stopped when the core is halted

Definition at line 294 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DBGMCU APB2 GRP1 STOP IP

Defines
DBGMCU APB2 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP

Define Documentation

#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP

The counter clock of TIM15 is stopped when the core is halted

Definition at line 306 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP

The counter clock of TIM16 is stopped when the core is halted

Definition at line 307 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP

The counter clock of TIM17 is stopped when the core is halted

Definition at line 309 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP

The counter clock of TIM1 is stopped when the core is halted

Definition at line 302 of file stm32l4xx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP

The counter clock of TIM8 is stopped when the core is halted

Definition at line 304 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: VREFBUF VOLTAGE

Defines
VREFBUF VOLTAGE
SYSTEM Exported Constants

Defines

#define | LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
#define | LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS

Define Documentation

#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)

Voltage reference scale 0 (VREF_OUT1)

Definition at line 319 of file stm32l4xx_ll_system.h.

#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS

Voltage reference scale 1 (VREF_OUT2)

Definition at line 320 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH LATENCY

Defines
FLASH LATENCY
SYSTEM Exported Constants

Defines

#define | LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

Define Documentation

#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero wait state

Definition at line 329 of file stm32l4xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One wait state

Definition at line 330 of file stm32l4xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two wait states

Definition at line 331 of file stm32l4xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three wait states

Definition at line 332 of file stm32l4xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

FLASH Four wait states

Definition at line 333 of file stm32l4xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSCFG

Functions
SYSCFG
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_SYSCFG_SetRemapMemory (uint32_t Memory)
Set memory mapping at address 0x00000000.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetRemapMemory (void)
Get memory mapping at address 0x00000000.
__STATIC_INLINE void | LL_SYSCFG_SetFlashBankMode (uint32_t Bank)
Select Flash bank mode (Bank flashed at 0x08000000)
__STATIC_INLINE uint32_t | LL_SYSCFG_GetFlashBankMode (void)
Get Flash bank mode (Bank flashed at 0x08000000)
__STATIC_INLINE void | LL_SYSCFG_EnableFirewall (void)
Firewall protection enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledFirewall (void)
Check if Firewall protection is enabled or not.
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogBooster (void)
Enable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogBooster (void)
Disable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IOC (void)
Enable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_DZC (void)
Enable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_UFC (void)
Enable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_OFC (void)
Enable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IDC (void)
Enable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IXC (void)
Enable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IOC (void)
Disable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_DZC (void)
Disable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_UFC (void)
Disable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_OFC (void)
Disable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IDC (void)
Disable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IXC (void)
Disable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IOC (void)
Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_DZC (void)
Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_UFC (void)
Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_OFC (void)
Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IDC (void)
Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IXC (void)
Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
__STATIC_INLINE void | LL_SYSCFG_EnableSRAM2Erase (void)
Enable SRAM2 Erase (starts a hardware SRAM2 erase operation.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsSRAM2EraseOngoing (void)
Check if SRAM2 erase operation is on going.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIM1/8/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIM1/8/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SP (void)
Check if SRAM2 parity error detected.
__STATIC_INLINE void | LL_SYSCFG_ClearFlag_SP (void)
Clear SRAM2 parity error flag.
__STATIC_INLINE void | LL_SYSCFG_EnableSRAM2PageWRP (uint32_t SRAM2WRP)
Enable SRAM2 page write protection.
__STATIC_INLINE void | LL_SYSCFG_LockSRAM2WRP (void)
SRAM2 page write protection lock prior to erase.
__STATIC_INLINE void | LL_SYSCFG_UnlockSRAM2WRP (void)
SRAM2 page write protection unlock prior to erase.

Function Documentation

__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP ( void )

Clear SRAM2 parity error flag.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
Return values:
None

Definition at line 854 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster ( void )

Disable I/O analog switch voltage booster.

Note:
When voltage booster is enabled, I/O analog switches are supplied by a dedicated voltage booster, from VDD power domain. This is the recommended configuration with low VDDA voltage operation.
The I/O analog switch voltage booster is relevant for peripherals using I/O in analog input: ADC, COMP, OPAMP. However, COMP and OPAMP inputs have a high impedance and voltage booster do not impact performance significantly. Therefore, the voltage booster is mainly intended for usage with ADC.
Reference Manual to LL API cross reference:
SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
Return values:
None

Definition at line 468 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
(*) value not defined in all devices
Return values:
None

Definition at line 510 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC ( void )

Disable Floating Point Unit Divide-by-zero Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
Return values:
None

Definition at line 590 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC ( void )

Disable Floating Point Unit Input denormal Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
Return values:
None

Definition at line 620 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC ( void )

Disable Floating Point Unit Invalid operation Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
Return values:
None

Definition at line 580 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC ( void )

Disable Floating Point Unit Inexact Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
Return values:
None

Definition at line 630 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC ( void )

Disable Floating Point Unit Overflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
Return values:
None

Definition at line 610 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC ( void )

Disable Floating Point Unit Underflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
Return values:
None

Definition at line 600 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster ( void )

Enable I/O analog switch voltage booster.

Note:
When voltage booster is enabled, I/O analog switches are supplied by a dedicated voltage booster, from VDD power domain. This is the recommended configuration with low VDDA voltage operation.
The I/O analog switch voltage booster is relevant for peripherals using I/O in analog input: ADC, COMP, OPAMP. However, COMP and OPAMP inputs have a high impedance and voltage booster do not impact performance significantly. Therefore, the voltage booster is mainly intended for usage with ADC.
Reference Manual to LL API cross reference:
SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
Return values:
None

Definition at line 449 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
(*) value not defined in all devices
Return values:
None

Definition at line 489 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableFirewall ( void )

Firewall protection enabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall
Return values:
None

Definition at line 420 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC ( void )

Enable Floating Point Unit Divide-by-zero Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
Return values:
None

Definition at line 530 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC ( void )

Enable Floating Point Unit Input denormal Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
Return values:
None

Definition at line 560 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC ( void )

Enable Floating Point Unit Invalid operation Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
Return values:
None

Definition at line 520 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC ( void )

Enable Floating Point Unit Inexact Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
Return values:
None

Definition at line 570 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC ( void )

Enable Floating Point Unit Overflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
Return values:
None

Definition at line 550 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC ( void )

Enable Floating Point Unit Underflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
Return values:
None

Definition at line 540 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase ( void )

Enable SRAM2 Erase (starts a hardware SRAM2 erase operation.

This bit is automatically cleared at the end of the SRAM2 erase operation.)

Note:
This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.
Reference Manual to LL API cross reference:
SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
Return values:
None

Definition at line 784 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP ( uint32_t SRAM2WRP )

Enable SRAM2 page write protection.

Note:
Write protection is cleared only by a system reset
Reference Manual to LL API cross reference:
SYSCFG_SWPR PAGEx LL_SYSCFG_EnableSRAM2PageWRP
Parameters:
SRAM2WRP This parameter can be a combination of the following values:
  • LL_SYSCFG_SRAM2WRP_PAGE0
  • LL_SYSCFG_SRAM2WRP_PAGE1
  • LL_SYSCFG_SRAM2WRP_PAGE2
  • LL_SYSCFG_SRAM2WRP_PAGE3
  • LL_SYSCFG_SRAM2WRP_PAGE4
  • LL_SYSCFG_SRAM2WRP_PAGE5
  • LL_SYSCFG_SRAM2WRP_PAGE6
  • LL_SYSCFG_SRAM2WRP_PAGE7
  • LL_SYSCFG_SRAM2WRP_PAGE8
  • LL_SYSCFG_SRAM2WRP_PAGE9
  • LL_SYSCFG_SRAM2WRP_PAGE10
  • LL_SYSCFG_SRAM2WRP_PAGE11
  • LL_SYSCFG_SRAM2WRP_PAGE12
  • LL_SYSCFG_SRAM2WRP_PAGE13
  • LL_SYSCFG_SRAM2WRP_PAGE14
  • LL_SYSCFG_SRAM2WRP_PAGE15
  • LL_SYSCFG_SRAM2WRP_PAGE16 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE17 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE18 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE19 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE20 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE21 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE22 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE23 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE24 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE25 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE26 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE27 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE28 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE29 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE30 (*)
  • LL_SYSCFG_SRAM2WRP_PAGE31 (*)
(*) value not defined in all devices
Return values:
None

Definition at line 900 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource ( uint32_t Line )

Get the configured defined for specific EXTI Line.

Reference Manual to LL API cross reference:
SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
Parameters:
Line This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_LINE0
  • LL_SYSCFG_EXTI_LINE1
  • LL_SYSCFG_EXTI_LINE2
  • LL_SYSCFG_EXTI_LINE3
  • LL_SYSCFG_EXTI_LINE4
  • LL_SYSCFG_EXTI_LINE5
  • LL_SYSCFG_EXTI_LINE6
  • LL_SYSCFG_EXTI_LINE7
  • LL_SYSCFG_EXTI_LINE8
  • LL_SYSCFG_EXTI_LINE9
  • LL_SYSCFG_EXTI_LINE10
  • LL_SYSCFG_EXTI_LINE11
  • LL_SYSCFG_EXTI_LINE12
  • LL_SYSCFG_EXTI_LINE13
  • LL_SYSCFG_EXTI_LINE14
  • LL_SYSCFG_EXTI_LINE15
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_EXTI_PORTA
  • LL_SYSCFG_EXTI_PORTB
  • LL_SYSCFG_EXTI_PORTC
  • LL_SYSCFG_EXTI_PORTD
  • LL_SYSCFG_EXTI_PORTE
  • LL_SYSCFG_EXTI_PORTF (*)
  • LL_SYSCFG_EXTI_PORTG (*)
  • LL_SYSCFG_EXTI_PORTH
(*) value not defined in all devices

Definition at line 771 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode ( void )

Get Flash bank mode (Bank flashed at 0x08000000)

Reference Manual to LL API cross reference:
SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_BANKMODE_BANK1
  • LL_SYSCFG_BANKMODE_BANK2

Definition at line 409 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory ( void )

Get memory mapping at address 0x00000000.

Reference Manual to LL API cross reference:
SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_REMAP_FLASH
  • LL_SYSCFG_REMAP_SYSTEMFLASH
  • LL_SYSCFG_REMAP_SRAM
  • LL_SYSCFG_REMAP_FMC (*)
  • LL_SYSCFG_REMAP_QUADSPI
(*) value not defined in all devices

Definition at line 383 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs ( void )

Get connections to TIM1/8/15/16/17 Break inputs.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
Return values:
Returned value can be can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_ECC
  • LL_SYSCFG_TIMBREAK_PVD
  • LL_SYSCFG_TIMBREAK_SRAM2_PARITY
  • LL_SYSCFG_TIMBREAK_LOCKUP

Definition at line 834 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP ( void )

Check if SRAM2 parity error detected.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
Return values:
State of bit (1 or 0).

Definition at line 844 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall ( void )

Check if Firewall protection is enabled or not.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall
Return values:
State of bit (1 or 0).

Definition at line 430 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC ( void )

Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
Return values:
State of bit (1 or 0).

Definition at line 650 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC ( void )

Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
Return values:
State of bit (1 or 0).

Definition at line 680 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC ( void )

Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
Return values:
State of bit (1 or 0).

Definition at line 640 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC ( void )

Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
Return values:
State of bit (1 or 0).

Definition at line 690 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC ( void )

Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
Return values:
State of bit (1 or 0).

Definition at line 670 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC ( void )

Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
Return values:
State of bit (1 or 0).

Definition at line 660 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing ( void )

Check if SRAM2 erase operation is on going.

Reference Manual to LL API cross reference:
SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
Return values:
State of bit (1 or 0).

Definition at line 799 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP ( void )

SRAM2 page write protection lock prior to erase.

Reference Manual to LL API cross reference:
SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
Return values:
None

Definition at line 910 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetEXTISource | ( | uint32_t | Port,
 |  | uint32_t | Line
 | ) |  |

Configure source input for the EXTI external interrupt.

Reference Manual to LL API cross reference:
SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
Parameters:
Port This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_PORTA
  • LL_SYSCFG_EXTI_PORTB
  • LL_SYSCFG_EXTI_PORTC
  • LL_SYSCFG_EXTI_PORTD
  • LL_SYSCFG_EXTI_PORTE
  • LL_SYSCFG_EXTI_PORTF (*)
  • LL_SYSCFG_EXTI_PORTG (*)
  • LL_SYSCFG_EXTI_PORTH
(*) value not defined in all devices
Line This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_LINE0
  • LL_SYSCFG_EXTI_LINE1
  • LL_SYSCFG_EXTI_LINE2
  • LL_SYSCFG_EXTI_LINE3
  • LL_SYSCFG_EXTI_LINE4
  • LL_SYSCFG_EXTI_LINE5
  • LL_SYSCFG_EXTI_LINE6
  • LL_SYSCFG_EXTI_LINE7
  • LL_SYSCFG_EXTI_LINE8
  • LL_SYSCFG_EXTI_LINE9
  • LL_SYSCFG_EXTI_LINE10
  • LL_SYSCFG_EXTI_LINE11
  • LL_SYSCFG_EXTI_LINE12
  • LL_SYSCFG_EXTI_LINE13
  • LL_SYSCFG_EXTI_LINE14
  • LL_SYSCFG_EXTI_LINE15
Return values:
None

Definition at line 731 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode ( uint32_t Bank )

Select Flash bank mode (Bank flashed at 0x08000000)

Reference Manual to LL API cross reference:
SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
Parameters:
Bank This parameter can be one of the following values:
  • LL_SYSCFG_BANKMODE_BANK1
  • LL_SYSCFG_BANKMODE_BANK2
Return values:
None

Definition at line 397 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetRemapMemory ( uint32_t Memory )

Set memory mapping at address 0x00000000.

Reference Manual to LL API cross reference:
SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
Parameters:
Memory This parameter can be one of the following values:
  • LL_SYSCFG_REMAP_FLASH
  • LL_SYSCFG_REMAP_SYSTEMFLASH
  • LL_SYSCFG_REMAP_SRAM
  • LL_SYSCFG_REMAP_FMC (*)
  • LL_SYSCFG_REMAP_QUADSPI
(*) value not defined in all devices
Return values:
None

Definition at line 366 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs ( uint32_t Break )

Set connections to TIM1/8/15/16/17 Break inputs.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
Parameters:
Break This parameter can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_ECC
  • LL_SYSCFG_TIMBREAK_PVD
  • LL_SYSCFG_TIMBREAK_SRAM2_PARITY
  • LL_SYSCFG_TIMBREAK_LOCKUP
Return values:
None

Definition at line 817 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP ( void )

SRAM2 page write protection unlock prior to erase.

Reference Manual to LL API cross reference:
SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
Return values:
None

Definition at line 921 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DBGMCU

Functions
DBGMCU
SYSTEM Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_SetTracePinAssignment (uint32_t PinAssignment)
Set Trace pin assignment control.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetTracePinAssignment (void)
Get Trace pin assignment control.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.

Function Documentation

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP
  • LL_DBGMCU_APB1_GRP1_CAN_STOP
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
(*) value not defined in all devices.
Return values:
None

Definition at line 1073 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP
  • LL_DBGMCU_APB1_GRP1_CAN_STOP
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
(*) value not defined in all devices.
Return values:
None

Definition at line 1112 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph ( uint32_t Periphs )

Freeze APB1 peripherals (group2 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
Return values:
None

Definition at line 1085 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB1 peripherals (group2 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
Return values:
None

Definition at line 1124 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1142 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 1160 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
Return values:
None

Definition at line 973 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
Return values:
None

Definition at line 1013 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
Return values:
None

Definition at line 993 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
Return values:
None

Definition at line 963 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
Return values:
None

Definition at line 1003 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
Return values:
None

Definition at line 983 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID ( void )

Return the device identifier.

Reference Manual to LL API cross reference:
DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)

Definition at line 942 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID ( void )

Return the device revision identifier.

Note:
This field indicates the revision of the device.
Reference Manual to LL API cross reference:
DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 953 of file stm32l4xx_ll_system.h.

References DBGMCU_REVID_POSITION.

__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment ( void )

Get Trace pin assignment control.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment
DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
Return values:
Returned value can be one of the following values:
  • LL_DBGMCU_TRACE_NONE
  • LL_DBGMCU_TRACE_ASYNCH
  • LL_DBGMCU_TRACE_SYNCH_SIZE1
  • LL_DBGMCU_TRACE_SYNCH_SIZE2
  • LL_DBGMCU_TRACE_SYNCH_SIZE4

Definition at line 1046 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment ( uint32_t PinAssignment )

Set Trace pin assignment control.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment
DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
Parameters:
PinAssignment This parameter can be one of the following values:
  • LL_DBGMCU_TRACE_NONE
  • LL_DBGMCU_TRACE_ASYNCH
  • LL_DBGMCU_TRACE_SYNCH_SIZE1
  • LL_DBGMCU_TRACE_SYNCH_SIZE2
  • LL_DBGMCU_TRACE_SYNCH_SIZE4
Return values:
None

Definition at line 1030 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: VREFBUF

Functions
VREFBUF
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_VREFBUF_Enable (void)
Enable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_Disable (void)
Disable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_EnableHIZ (void)
Enable high impedance (VREF+pin is high impedance)
__STATIC_INLINE void | LL_VREFBUF_DisableHIZ (void)
Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
__STATIC_INLINE void | LL_VREFBUF_SetVoltageScaling (uint32_t Scale)
Set the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetVoltageScaling (void)
Get the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_IsVREFReady (void)
Check if Voltage reference buffer is ready.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetTrimming (void)
Get the trimming code for VREFBUF calibration.
__STATIC_INLINE void | LL_VREFBUF_SetTrimming (uint32_t Value)
Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)

Function Documentation

__STATIC_INLINE void LL_VREFBUF_Disable ( void )

Disable Internal voltage reference.

Reference Manual to LL API cross reference:
VREFBUF_CSR ENVR LL_VREFBUF_Disable
Return values:
None

Definition at line 1189 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_DisableHIZ ( void )

Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)

Reference Manual to LL API cross reference:
VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
Return values:
None

Definition at line 1209 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_Enable ( void )

Enable Internal voltage reference.

Reference Manual to LL API cross reference:
VREFBUF_CSR ENVR LL_VREFBUF_Enable
Return values:
None

Definition at line 1179 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_EnableHIZ ( void )

Enable high impedance (VREF+pin is high impedance)

Reference Manual to LL API cross reference:
VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
Return values:
None

Definition at line 1199 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming ( void )

Get the trimming code for VREFBUF calibration.

Reference Manual to LL API cross reference:
VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
Return values:
Between 0 and 0x3F

Definition at line 1254 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling ( void )

Get the Voltage reference scale.

Reference Manual to LL API cross reference:
VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
Return values:
Returned value can be one of the following values:
  • LL_VREFBUF_VOLTAGE_SCALE0
  • LL_VREFBUF_VOLTAGE_SCALE1

Definition at line 1234 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady ( void )

Check if Voltage reference buffer is ready.

Reference Manual to LL API cross reference:
VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
Return values:
State of bit (1 or 0).

Definition at line 1244 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_SetTrimming ( uint32_t Value )

Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)

Reference Manual to LL API cross reference:
VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
Parameters:
Value Between 0 and 0x3F
Return values:
None

Definition at line 1265 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling ( uint32_t Scale )

Set the Voltage reference scale.

Reference Manual to LL API cross reference:
VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
Parameters:
Scale This parameter can be one of the following values:
  • LL_VREFBUF_VOLTAGE_SCALE0
  • LL_VREFBUF_VOLTAGE_SCALE1
Return values:
None

Definition at line 1222 of file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH

Functions
FLASH
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.
__STATIC_INLINE void | LL_FLASH_EnableInstCache (void)
Enable Instruction cache.
__STATIC_INLINE void | LL_FLASH_DisableInstCache (void)
Disable Instruction cache.
__STATIC_INLINE void | LL_FLASH_EnableDataCache (void)
Enable Data cache.
__STATIC_INLINE void | LL_FLASH_DisableDataCache (void)
Disable Data cache.
__STATIC_INLINE void | LL_FLASH_EnableInstCacheReset (void)
Enable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_DisableInstCacheReset (void)
Disable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_EnableDataCacheReset (void)
Enable Data cache reset.
__STATIC_INLINE void | LL_FLASH_DisableDataCacheReset (void)
Disable Data cache reset.
__STATIC_INLINE void | LL_FLASH_EnableRunPowerDown (void)
Enable Flash Power-down mode during run mode or Low-power run mode.
__STATIC_INLINE void | LL_FLASH_DisableRunPowerDown (void)
Disable Flash Power-down mode during run mode or Low-power run mode.
__STATIC_INLINE void | LL_FLASH_EnableSleepPowerDown (void)
Enable Flash Power-down mode during Sleep or Low-power sleep mode.
__STATIC_INLINE void | LL_FLASH_DisableSleepPowerDown (void)
Disable Flash Power-down mode during Sleep or Low-power sleep mode.

Function Documentation

__STATIC_INLINE void LL_FLASH_DisableDataCache ( void )

Disable Data cache.

Reference Manual to LL API cross reference:
FLASH_ACR DCEN LL_FLASH_DisableDataCache
Return values:
None

Definition at line 1375 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableDataCacheReset ( void )

Disable Data cache reset.

Reference Manual to LL API cross reference:
FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
Return values:
None

Definition at line 1417 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableInstCache ( void )

Disable Instruction cache.

Reference Manual to LL API cross reference:
FLASH_ACR ICEN LL_FLASH_DisableInstCache
Return values:
None

Definition at line 1355 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableInstCacheReset ( void )

Disable Instruction cache reset.

Reference Manual to LL API cross reference:
FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
Return values:
None

Definition at line 1396 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisablePrefetch ( void )

Disable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
Return values:
None

Definition at line 1325 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableRunPowerDown ( void )

Disable Flash Power-down mode during run mode or Low-power run mode.

Reference Manual to LL API cross reference:
FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown
FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown
FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
Return values:
None

Definition at line 1450 of file stm32l4xx_ll_system.h.

References FLASH_PDKEY1, and FLASH_PDKEY2.

__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown ( void )

Disable Flash Power-down mode during Sleep or Low-power sleep mode.

Reference Manual to LL API cross reference:
FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
Return values:
None

Definition at line 1476 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableDataCache ( void )

Enable Data cache.

Reference Manual to LL API cross reference:
FLASH_ACR DCEN LL_FLASH_EnableDataCache
Return values:
None

Definition at line 1365 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableDataCacheReset ( void )

Enable Data cache reset.

Note:
bit can be written only when the data cache is disabled
Reference Manual to LL API cross reference:
FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
Return values:
None

Definition at line 1407 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableInstCache ( void )

Enable Instruction cache.

Reference Manual to LL API cross reference:
FLASH_ACR ICEN LL_FLASH_EnableInstCache
Return values:
None

Definition at line 1345 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableInstCacheReset ( void )

Enable Instruction cache reset.

Note:
bit can be written only when the instruction cache is disabled
Reference Manual to LL API cross reference:
FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
Return values:
None

Definition at line 1386 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnablePrefetch ( void )

Enable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
Return values:
None

Definition at line 1315 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableRunPowerDown ( void )

Enable Flash Power-down mode during run mode or Low-power run mode.

Note:
Flash memory can be put in power-down mode only when the code is executed from RAM
Flash must not be accessed when power down is enabled
Flash must not be put in power-down while a program or an erase operation is on-going
Reference Manual to LL API cross reference:
FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown
FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown
FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
Return values:
None

Definition at line 1434 of file stm32l4xx_ll_system.h.

References FLASH_PDKEY1, and FLASH_PDKEY2.

__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown ( void )

Enable Flash Power-down mode during Sleep or Low-power sleep mode.

Note:
Flash must not be put in power-down while a program or an erase operation is on-going
Reference Manual to LL API cross reference:
FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
Return values:
None

Definition at line 1466 of file stm32l4xx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_GetLatency ( void )

Get FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_GetLatency
Return values:
Returned value can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
  • LL_FLASH_LATENCY_3
  • LL_FLASH_LATENCY_4

Definition at line 1305 of file stm32l4xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled ( void )

Check if Prefetch buffer is enabled.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
Return values:
State of bit (1 or 0).

Definition at line 1335 of file stm32l4xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_SetLatency ( uint32_t Latency )

Set FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_SetLatency
Parameters:
Latency This parameter can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
  • LL_FLASH_LATENCY_3
  • LL_FLASH_LATENCY_4
Return values:
None

Definition at line 1290 of file stm32l4xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM

Modules
TIM
STM32L4xx_LL_Driver

Modules

TIM Private Functions

Private functions.

TIM Private Variables
TIM Private Constants
TIM Private Macros
TIM Exported Init structure
TIM Exported Constants
TIM Exported Macros
TIM Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for TIM registers.

Register | Bit | Function
ARR | ARR | LL_TIM_GetAutoReload
 |  | LL_TIM_SetAutoReload
BDTR | AOE | LL_TIM_DisableAutomaticOutput
 |  | LL_TIM_EnableAutomaticOutput
 |  | LL_TIM_IsEnabledAutomaticOutput
 | BK2E | LL_TIM_DisableBRK2
 |  | LL_TIM_EnableBRK2
 | BK2F | LL_TIM_ConfigBRK2
 | BK2P | LL_TIM_ConfigBRK2
 | BKE | LL_TIM_DisableBRK
 |  | LL_TIM_EnableBRK
 | BKF | LL_TIM_ConfigBRK
 | BKP | LL_TIM_ConfigBRK
 | DTG | LL_TIM_OC_SetDeadTime
 | LOCK | LL_TIM_CC_SetLockLevel
 | MOE | LL_TIM_DisableAllOutputs
 |  | LL_TIM_EnableAllOutputs
 |  | LL_TIM_IsEnabledAllOutputs
 | OSSI | LL_TIM_SetOffStates
 | OSSR | LL_TIM_SetOffStates
CCER | CC1E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC1NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC1NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC1P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC2E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC2NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC2NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC2P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC3E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC3NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC3NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC3P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC4E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC4NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 | CC4P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC5E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC5P | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC6E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC6P | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
CCMR1 | CC1S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | CC2S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | IC1F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC1PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | IC2F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC2PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | OC1CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC1FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC1M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC1PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
 | OC2CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC2FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC2M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC2PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
CCMR2 | CC3S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | CC4S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | IC3F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC3PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | IC4F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC4PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | OC3CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC3FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC3M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC3PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
 | OC4CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC4FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC4M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC4PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
CCMR3 | CC5S | LL_TIM_OC_ConfigOutput
 | CC6S | LL_TIM_OC_ConfigOutput
 | OC5CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC5FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC5M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC5PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
 | OC6CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC6FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC6M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC6PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
CCR1 | CCR1 | LL_TIM_IC_GetCaptureCH1
 |  | LL_TIM_OC_GetCompareCH1
 |  | LL_TIM_OC_SetCompareCH1
CCR2 | CCR2 | LL_TIM_IC_GetCaptureCH2
 |  | LL_TIM_OC_GetCompareCH2
 |  | LL_TIM_OC_SetCompareCH2
CCR3 | CCR3 | LL_TIM_IC_GetCaptureCH3
 |  | LL_TIM_OC_GetCompareCH3
 |  | LL_TIM_OC_SetCompareCH3
CCR4 | CCR4 | LL_TIM_IC_GetCaptureCH4
 |  | LL_TIM_OC_GetCompareCH4
 |  | LL_TIM_OC_SetCompareCH4
CCR5 | CCR5 | LL_TIM_OC_GetCompareCH5
 |  | LL_TIM_OC_SetCompareCH5
 | GC5C1 | LL_TIM_SetCH5CombinedChannels
 | GC5C2 | LL_TIM_SetCH5CombinedChannels
 | GC5C3 | LL_TIM_SetCH5CombinedChannels
CCR6 | CCR6 | LL_TIM_OC_GetCompareCH6
 |  | LL_TIM_OC_SetCompareCH6
CNT | CNT | LL_TIM_GetCounter
 |  | LL_TIM_SetCounter
CR1 | ARPE | LL_TIM_DisableARRPreload
 |  | LL_TIM_EnableARRPreload
 |  | LL_TIM_IsEnabledARRPreload
 | CEN | LL_TIM_DisableCounter
 |  | LL_TIM_EnableCounter
 |  | LL_TIM_IsEnabledCounter
 | CKD | LL_TIM_GetClockDivision
 |  | LL_TIM_SetClockDivision
 | CMS | LL_TIM_GetCounterMode
 |  | LL_TIM_SetCounterMode
 | DIR | LL_TIM_GetCounterMode
 |  | LL_TIM_GetDirection
 |  | LL_TIM_SetCounterMode
 | OPM | LL_TIM_GetOnePulseMode
 |  | LL_TIM_SetOnePulseMode
 | UDIS | LL_TIM_DisableUpdateEvent
 |  | LL_TIM_EnableUpdateEvent
 |  | LL_TIM_IsEnabledUpdateEvent
 | UIFREMAP | LL_TIM_DisableUIFRemap
 |  | LL_TIM_EnableUIFRemap
 | URS | LL_TIM_GetUpdateSource
 |  | LL_TIM_SetUpdateSource
CR2 | CCDS | LL_TIM_CC_GetDMAReqTrigger
 |  | LL_TIM_CC_SetDMAReqTrigger
 | CCPC | LL_TIM_CC_DisablePreload
 |  | LL_TIM_CC_EnablePreload
 | CCUS | LL_TIM_CC_SetUpdate
 | MMS | LL_TIM_SetTriggerOutput
 | MMS2 | LL_TIM_SetTriggerOutput2
 | OIS1 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS2 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS2N | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS3 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS3N | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS4 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS5 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS6 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | TI1S | LL_TIM_IC_DisableXORCombination
 |  | LL_TIM_IC_EnableXORCombination
 |  | LL_TIM_IC_IsEnabledXORCombination
DCR | DBA | LL_TIM_ConfigDMABurst
 | DBL | LL_TIM_ConfigDMABurst
DIER | BIE | LL_TIM_DisableIT_BRK
 |  | LL_TIM_EnableIT_BRK
 |  | LL_TIM_IsEnabledIT_BRK
 | CC1DE | LL_TIM_DisableDMAReq_CC1
 |  | LL_TIM_EnableDMAReq_CC1
 |  | LL_TIM_IsEnabledDMAReq_CC1
 | CC1IE | LL_TIM_DisableIT_CC1
 |  | LL_TIM_EnableIT_CC1
 |  | LL_TIM_IsEnabledIT_CC1
 | CC2DE | LL_TIM_DisableDMAReq_CC2
 |  | LL_TIM_EnableDMAReq_CC2
 |  | LL_TIM_IsEnabledDMAReq_CC2
 | CC2IE | LL_TIM_DisableIT_CC2
 |  | LL_TIM_EnableIT_CC2
 |  | LL_TIM_IsEnabledIT_CC2
 | CC3DE | LL_TIM_DisableDMAReq_CC3
 |  | LL_TIM_EnableDMAReq_CC3
 |  | LL_TIM_IsEnabledDMAReq_CC3
 | CC3IE | LL_TIM_DisableIT_CC3
 |  | LL_TIM_EnableIT_CC3
 |  | LL_TIM_IsEnabledIT_CC3
 | CC4DE | LL_TIM_DisableDMAReq_CC4
 |  | LL_TIM_EnableDMAReq_CC4
 |  | LL_TIM_IsEnabledDMAReq_CC4
 | CC4IE | LL_TIM_DisableIT_CC4
 |  | LL_TIM_EnableIT_CC4
 |  | LL_TIM_IsEnabledIT_CC4
 | COMDE | LL_TIM_DisableDMAReq_COM
 |  | LL_TIM_EnableDMAReq_COM
 |  | LL_TIM_IsEnabledDMAReq_COM
 | COMIE | LL_TIM_DisableIT_COM
 |  | LL_TIM_EnableIT_COM
 |  | LL_TIM_IsEnabledIT_COM
 | TDE | LL_TIM_DisableDMAReq_TRIG
 |  | LL_TIM_EnableDMAReq_TRIG
 |  | LL_TIM_IsEnabledDMAReq_TRIG
 | TIE | LL_TIM_DisableIT_TRIG
 |  | LL_TIM_EnableIT_TRIG
 |  | LL_TIM_IsEnabledIT_TRIG
 | UDE | LL_TIM_DisableDMAReq_UPDATE
 |  | LL_TIM_EnableDMAReq_UPDATE
 |  | LL_TIM_IsEnabledDMAReq_UPDATE
 | UIE | LL_TIM_DisableIT_UPDATE
 |  | LL_TIM_EnableIT_UPDATE
 |  | LL_TIM_IsEnabledIT_UPDATE
EGR | B2G | LL_TIM_GenerateEvent_BRK2
 | BG | LL_TIM_GenerateEvent_BRK
 | CC1G | LL_TIM_GenerateEvent_CC1
 | CC2G | LL_TIM_GenerateEvent_CC2
 | CC3G | LL_TIM_GenerateEvent_CC3
 | CC4G | LL_TIM_GenerateEvent_CC4
 | COMG | LL_TIM_GenerateEvent_COM
 | TG | LL_TIM_GenerateEvent_TRIG
 | UG | LL_TIM_GenerateEvent_UPDATE
OR2 | BKCMP1E | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 |  | LL_TIM_SetBreakInputSourcePolarity
 | BKCMP2E | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 |  | LL_TIM_SetBreakInputSourcePolarity
 | BKDFBK0E | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 | BKINE | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 |  | LL_TIM_SetBreakInputSourcePolarity
 | BKINP | LL_TIM_SetBreakInputSourcePolarity
 | ETRSEL | LL_TIM_SetETRSource
OR3 | BKCMP1E | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 |  | LL_TIM_SetBreakInputSourcePolarity
 | BKCMP2E | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 |  | LL_TIM_SetBreakInputSourcePolarity
 | BKDFBK0E | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 | BKINE | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 |  | LL_TIM_SetBreakInputSourcePolarity
 | BKINP | LL_TIM_SetBreakInputSourcePolarity
PSC | PSC | LL_TIM_GetPrescaler
 |  | LL_TIM_SetPrescaler
RCR | REP | LL_TIM_GetRepetitionCounter
 |  | LL_TIM_SetRepetitionCounter
SMCR | ECE | LL_TIM_DisableExternalClock
 |  | LL_TIM_EnableExternalClock
 |  | LL_TIM_IsEnabledExternalClock
 |  | LL_TIM_SetClockSource
 | ETF | LL_TIM_ConfigETR
 | ETP | LL_TIM_ConfigETR
 | ETPS | LL_TIM_ConfigETR
 | MSM | LL_TIM_DisableMasterSlaveMode
 |  | LL_TIM_EnableMasterSlaveMode
 |  | LL_TIM_IsEnabledMasterSlaveMode
 | OCCS | LL_TIM_SetOCRefClearInputSource
 | SMS | LL_TIM_SetClockSource
 |  | LL_TIM_SetEncoderMode
 |  | LL_TIM_SetSlaveMode
 | TS | LL_TIM_SetTriggerInput
SR | B2IF | LL_TIM_ClearFlag_BRK2
 |  | LL_TIM_IsActiveFlag_BRK2
 | BIF | LL_TIM_ClearFlag_BRK
 |  | LL_TIM_IsActiveFlag_BRK
 | CC1IF | LL_TIM_ClearFlag_CC1
 |  | LL_TIM_IsActiveFlag_CC1
 | CC1OF | LL_TIM_ClearFlag_CC1OVR
 |  | LL_TIM_IsActiveFlag_CC1OVR
 | CC2IF | LL_TIM_ClearFlag_CC2
 |  | LL_TIM_IsActiveFlag_CC2
 | CC2OF | LL_TIM_ClearFlag_CC2OVR
 |  | LL_TIM_IsActiveFlag_CC2OVR
 | CC3IF | LL_TIM_ClearFlag_CC3
 |  | LL_TIM_IsActiveFlag_CC3
 | CC3OF | LL_TIM_ClearFlag_CC3OVR
 |  | LL_TIM_IsActiveFlag_CC3OVR
 | CC4IF | LL_TIM_ClearFlag_CC4
 |  | LL_TIM_IsActiveFlag_CC4
 | CC4OF | LL_TIM_ClearFlag_CC4OVR
 |  | LL_TIM_IsActiveFlag_CC4OVR
 | CC5IF | LL_TIM_ClearFlag_CC5
 |  | LL_TIM_IsActiveFlag_CC5
 | CC6IF | LL_TIM_ClearFlag_CC6
 |  | LL_TIM_IsActiveFlag_CC6
 | COMIF | LL_TIM_ClearFlag_COM
 |  | LL_TIM_IsActiveFlag_COM
 | SBIF | LL_TIM_ClearFlag_SYSBRK
 |  | LL_TIM_IsActiveFlag_SYSBRK
 | TIF | LL_TIM_ClearFlag_TRIG
 |  | LL_TIM_IsActiveFlag_TRIG
 | UIF | LL_TIM_ClearFlag_UPDATE
 |  | LL_TIM_IsActiveFlag_UPDATE
TIM15_OR1 | ENCODER_MODE | LL_TIM_SetRemap
 | TI1_RMP | LL_TIM_SetRemap
TIM16_OR1 | TI1_RMP | LL_TIM_SetRemap
TIM17_OR1 | TI1_RMP | LL_TIM_SetRemap
TIM1_OR1 | ETR_ADC1_RMP | LL_TIM_SetRemap
 | ETR_ADC3_RMP | LL_TIM_SetRemap
 | TI1_RMP | LL_TIM_SetRemap
TIM2_OR1 | ITR1_RMP | LL_TIM_SetRemap
 | TI1_RMP | LL_TIM_SetRemap
 | TI4_RMP | LL_TIM_SetRemap
TIM3_OR1 | TI1_RMP | LL_TIM_SetRemap
TIM8_OR1 | ETR_ADC2_RMP | LL_TIM_SetRemap
 | ETR_ADC3_RMP | LL_TIM_SetRemap
 | TI1_RMP | LL_TIM_SetRemap
Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Private functions. More...

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | OC5Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 5.
static ErrorStatus | OC6Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 6.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.

Detailed Description

Private functions.

Function Documentation

static ErrorStatus IC1Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 1.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1084 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC2Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 2.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1117 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC3Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 3.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1150 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC4Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 4.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1183 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus OC1Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 1.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 656 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH1(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC2Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 2.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 735 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH2(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC3Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 3.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 814 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH3(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC4Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 4.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 893 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH4(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC5Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 5.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 5 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 963 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH5(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC6Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 6.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 6 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1024 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH6(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Private Variables

Variables
TIM Private Variables
TIM

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Variable Documentation

const uint8_t OFFSET_TAB_CCMRx[] [static]
Initial value:

  {
    0x00U,
    0x00U,
    0x00U,
    0x00U,
    0x04U,
    0x04U,
    0x04U,
    0x3CU,
    0x3CU
  }

Definition at line 64 of file stm32l4xx_ll_tim.h.

const uint8_t SHIFT_TAB_CCxP[] [static]
Initial value:
{
  0U,
  2U,
  4U,
  6U,
  8U,
  10U,
  12U,
  16U,
  20U
}

Definition at line 103 of file stm32l4xx_ll_tim.h.

const uint8_t SHIFT_TAB_ICxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  0U
}

Definition at line 90 of file stm32l4xx_ll_tim.h.

const uint8_t SHIFT_TAB_OCxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  8U
}

Definition at line 77 of file stm32l4xx_ll_tim.h.

const uint8_t SHIFT_TAB_OISx[] [static]
Initial value:
{
  0U,
  1U,
  2U,
  3U,
  4U,
  5U,
  6U,
  8U,
  10U
}

Definition at line 116 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Bit Position Value

Defines
Bit Position Value
TIM Private Constants

Position of the bit in the register. More...

Defines

#define TIM_POSITION_ICPSC POSITION_VAL(TIM_CCMR1_IC1PSC)

Detailed Description

Position of the bit in the register.

Define Documentation

#define TIM_POSITION_ICPSC POSITION_VAL(TIM_CCMR1_IC1PSC)

Definition at line 141 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Private Constants

Modules | Defines
TIM Private Constants
TIM

Modules

Bit Position Value

Position of the bit in the register.

Defines

#define | TIMx_OR2_BKINE TIM1_OR2_BKINE
#define | TIMx_OR2_BKCOMP1E TIM1_OR2_BKCMP1E
#define | TIMx_OR2_BKCOMP2E TIM1_OR2_BKCMP2E
#define | TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E
#define | TIMx_OR2_BKINP TIM1_OR2_BKINP
#define | TIMx_OR2_BKCOMP1P TIM1_OR2_BKCMP1P
#define | TIMx_OR2_BKCOMP2P TIM1_OR2_BKCMP2P
#define | TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL
#define | TIMx_OR3_BK2INE TIM1_OR3_BK2INE
#define | TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E
#define | TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E
#define | TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E
#define | TIMx_OR3_BK2INP TIM1_OR3_BK2INP
#define | TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P
#define | TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P
#define | TIMx_OR1_RMP_SHIFT ((uint32_t)16U)
#define | TIMx_OR1_RMP_MASK ((uint32_t)0x0000FFFFU)
#define | TIM1_OR1_RMP_MASK ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | TIM2_OR1_RMP_MASK ((uint32_t)((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | TIM3_OR1_RMP_MASK ((uint32_t)(TIM3_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
#define | TIM8_OR1_RMP_MASK ((uint32_t)((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | TIM15_OR1_RMP_MASK ((uint32_t)((TIM15_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | TIM16_OR1_RMP_MASK ((uint32_t)((TIM16_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | TIM17_OR1_RMP_MASK ((uint32_t)((TIM17_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | DT_DELAY_1 ((uint8_t)0x7FU)
#define | DT_DELAY_2 ((uint8_t)0x3FU)
#define | DT_DELAY_3 ((uint8_t)0x1FU)
#define | DT_DELAY_4 ((uint8_t)0x1FU)
#define | DT_RANGE_1 ((uint8_t)0x00U)
#define | DT_RANGE_2 ((uint8_t)0x80U)
#define | DT_RANGE_3 ((uint8_t)0xC0U)
#define | DT_RANGE_4 ((uint8_t)0xE0U)

Define Documentation

#define DT_DELAY_1 ((uint8_t)0x7FU)

Definition at line 185 of file stm32l4xx_ll_tim.h.

#define DT_DELAY_2 ((uint8_t)0x3FU)

Definition at line 186 of file stm32l4xx_ll_tim.h.

#define DT_DELAY_3 ((uint8_t)0x1FU)

Definition at line 187 of file stm32l4xx_ll_tim.h.

#define DT_DELAY_4 ((uint8_t)0x1FU)

Definition at line 188 of file stm32l4xx_ll_tim.h.

#define DT_RANGE_1 ((uint8_t)0x00U)

Definition at line 191 of file stm32l4xx_ll_tim.h.

#define DT_RANGE_2 ((uint8_t)0x80U)

Definition at line 192 of file stm32l4xx_ll_tim.h.

#define DT_RANGE_3 ((uint8_t)0xC0U)

Definition at line 193 of file stm32l4xx_ll_tim.h.

#define DT_RANGE_4 ((uint8_t)0xE0U)

Definition at line 194 of file stm32l4xx_ll_tim.h.

#define TIM15_OR1_RMP_MASK ((uint32_t)((TIM15_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))

Definition at line 180 of file stm32l4xx_ll_tim.h.

#define TIM16_OR1_RMP_MASK ((uint32_t)((TIM16_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))

Definition at line 181 of file stm32l4xx_ll_tim.h.

#define TIM17_OR1_RMP_MASK ((uint32_t)((TIM17_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))

Definition at line 182 of file stm32l4xx_ll_tim.h.

#define TIM1_OR1_RMP_MASK ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))

Definition at line 173 of file stm32l4xx_ll_tim.h.

#define TIM2_OR1_RMP_MASK ((uint32_t)((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT))

Definition at line 177 of file stm32l4xx_ll_tim.h.

#define TIM3_OR1_RMP_MASK ((uint32_t)(TIM3_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)

Definition at line 178 of file stm32l4xx_ll_tim.h.

#define TIM8_OR1_RMP_MASK ((uint32_t)((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))

Definition at line 179 of file stm32l4xx_ll_tim.h.

#define TIMx_OR1_RMP_MASK ((uint32_t)0x0000FFFFU)

Definition at line 171 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_SetRemap().

#define TIMx_OR1_RMP_SHIFT ((uint32_t)16U)

Definition at line 170 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_SetRemap().

#define TIMx_OR2_BKCOMP1E TIM1_OR2_BKCMP1E

BRK COMP1 enable

Definition at line 148 of file stm32l4xx_ll_tim.h.

#define TIMx_OR2_BKCOMP1P TIM1_OR2_BKCMP1P

BRK COMP1 input polarity

Definition at line 154 of file stm32l4xx_ll_tim.h.

#define TIMx_OR2_BKCOMP2E TIM1_OR2_BKCMP2E

BRK COMP2 enable

Definition at line 149 of file stm32l4xx_ll_tim.h.

#define TIMx_OR2_BKCOMP2P TIM1_OR2_BKCMP2P

BRK COMP2 input polarity

Definition at line 155 of file stm32l4xx_ll_tim.h.

#define TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E

BRK DFSDM1_BREAK[0] enable

Definition at line 151 of file stm32l4xx_ll_tim.h.

#define TIMx_OR2_BKINE TIM1_OR2_BKINE

BRK BKIN input enable

Definition at line 147 of file stm32l4xx_ll_tim.h.

#define TIMx_OR2_BKINP TIM1_OR2_BKINP

BRK BKIN input polarity

Definition at line 153 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_SetBreakInputSourcePolarity().

#define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL

TIMx ETR source selection

Definition at line 156 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_SetETRSource().

#define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E

BRK2 COMP1 enable

Definition at line 160 of file stm32l4xx_ll_tim.h.

#define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P

BRK2 COMP1 input polarity

Definition at line 166 of file stm32l4xx_ll_tim.h.

#define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E

BRK2 COMP2 enable

Definition at line 161 of file stm32l4xx_ll_tim.h.

#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P

BRK2 COMP2 input polarity

Definition at line 167 of file stm32l4xx_ll_tim.h.

#define TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E

BRK2 DFSDM1_BREAK[1] enable

Definition at line 163 of file stm32l4xx_ll_tim.h.

#define TIMx_OR3_BK2INE TIM1_OR3_BK2INE

BRK2 BKIN2 input enable

Definition at line 159 of file stm32l4xx_ll_tim.h.

#define TIMx_OR3_BK2INP TIM1_OR3_BK2INP

BRK2 BKIN2 input polarity

Definition at line 165 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).

Define Documentation

#define IS_LL_TIM_ACTIVEINPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
                                       || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
                                       || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))

Definition at line 100 of file stm32l4xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_ENCODER_Init().

#define IS_LL_TIM_CLOCKDIVISION ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
                                         || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
                                         || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))

Definition at line 72 of file stm32l4xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_COUNTERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))

Definition at line 66 of file stm32l4xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_ENCODERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
                                       || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
                                       || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))

Definition at line 130 of file stm32l4xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init().

#define IS_LL_TIM_IC_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))

Definition at line 109 of file stm32l4xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_IC_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                       || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
                                       || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))

Definition at line 126 of file stm32l4xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), and IC4Config().

#define IS_LL_TIM_IC_POLARITY_ENCODER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                               || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))

Definition at line 134 of file stm32l4xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_ICPSC ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ICPSC_DIV1) \
                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))

Definition at line 104 of file stm32l4xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_OCIDLESTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
                                       || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))

Definition at line 97 of file stm32l4xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))

Definition at line 76 of file stm32l4xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
                                      || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))

Definition at line 94 of file stm32l4xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCSTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
                                   || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))

Definition at line 91 of file stm32l4xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define TIM_CALC_DTS | ( | __TIMCLK__,
 |  | __CKD__
 | ) |
Value:
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
     ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
     ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))

Calculate the deadtime sampling period(in ps).

Parameters:
__TIMCLK__ timer input clock frequency (in Hz).
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
none

Definition at line 247 of file stm32l4xx_ll_tim.h.

#define TIM_GET_CHANNEL_INDEX ( __CHANNEL__ )
Value:
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)

Convert channel id into channel index.

Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
none

Definition at line 229 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_IC_Config(), LL_TIM_IC_GetActiveInput(), LL_TIM_IC_GetFilter(), LL_TIM_IC_GetPolarity(), LL_TIM_IC_GetPrescaler(), LL_TIM_IC_SetActiveInput(), LL_TIM_IC_SetFilter(), LL_TIM_IC_SetPolarity(), LL_TIM_IC_SetPrescaler(), LL_TIM_OC_ConfigOutput(), LL_TIM_OC_DisableClear(), LL_TIM_OC_DisableFast(), LL_TIM_OC_DisablePreload(), LL_TIM_OC_EnableClear(), LL_TIM_OC_EnableFast(), LL_TIM_OC_EnablePreload(), LL_TIM_OC_GetIdleState(), LL_TIM_OC_GetMode(), LL_TIM_OC_GetPolarity(), LL_TIM_OC_IsEnabledClear(), LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload(), LL_TIM_OC_SetIdleState(), LL_TIM_OC_SetMode(), and LL_TIM_OC_SetPolarity().

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_TIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Time Base configuration structure definition. More...

#include <stm32l4xx_ll_tim.h>

Data Fields

uint16_t | Prescaler
uint32_t | CounterMode
uint32_t | Autoreload
uint32_t | ClockDivision
uint8_t | RepetitionCounter

Detailed Description

TIM Time Base configuration structure definition.

Definition at line 265 of file stm32l4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_InitTypeDef::Autoreload

Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between 0x0000 and 0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetAutoReload().

Definition at line 277 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of Clock Division.

This feature can be modified afterwards using unitary function LL_TIM_SetClockDivision().

Definition at line 284 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of Counter Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetCounterMode().

Definition at line 272 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint16_t LL_TIM_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between 0x0000 and 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetPrescaler().

Definition at line 267 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint8_t LL_TIM_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between 0x00 and 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_SetRepetitionCounter().

Definition at line 289 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_tim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_OC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Output Compare configuration structure definition. More...

#include <stm32l4xx_ll_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | OCState
uint32_t | OCNState
uint32_t | CompareValue
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare configuration structure definition.

Definition at line 303 of file stm32l4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_OC_InitTypeDef::CompareValue

Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between 0x0000 and 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).

Definition at line 320 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 335 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCMode

Specifies the output mode. This parameter can be a value of Output Configuration Mode.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetMode().

Definition at line 305 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 340 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 330 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNState

Specifies the TIM complementary Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 315 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 325 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCState

Specifies the TIM Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 310 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_tim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_IC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Input Capture configuration structure definition. More...

#include <stm32l4xx_ll_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICActiveInput
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture configuration structure definition.

Definition at line 350 of file stm32l4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_IC_InitTypeDef::ICActiveInput

Specifies the input. This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 358 of file stm32l4xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 368 of file stm32l4xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 353 of file stm32l4xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 363 of file stm32l4xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_tim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_TIM_ENCODER_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_ENCODER_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Encoder interface configuration structure definition. More...

#include <stm32l4xx_ll_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1ActiveInput
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2ActiveInput
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder interface configuration structure definition.

Definition at line 378 of file stm32l4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_ENCODER_InitTypeDef::EncoderMode

Specifies the encoder resolution (x2 or x4). This parameter can be a value of Encoder Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetEncoderMode().

Definition at line 380 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput

Specifies the TI1 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 390 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 400 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 385 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 395 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput

Specifies the TI2 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 410 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Filter

Specifies the TI2 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 420 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Polarity

Specifies the active edge of TI2 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 405 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Prescaler

Specifies the TI2 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 415 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_tim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_TIM_HALLSENSOR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_HALLSENSOR_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Hall sensor interface configuration structure definition. More...

#include <stm32l4xx_ll_tim.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | CommutationDelay

Detailed Description

TIM Hall sensor interface configuration structure definition.

Definition at line 430 of file stm32l4xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay

Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCH2().

Definition at line 450 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 445 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 433 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 438 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_tim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
TIM Exported Constants

Flags defines which can be used with LL_TIM_ReadReg function. More...

Defines

#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_CC5IF TIM_SR_CC5IF
#define | LL_TIM_SR_CC6IF TIM_SR_CC6IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_SR_SBIF TIM_SR_SBIF

Detailed Description

Flags defines which can be used with LL_TIM_ReadReg function.

Define Documentation

#define LL_TIM_SR_B2IF TIM_SR_B2IF

Second break interrupt flag

Definition at line 482 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_BIF TIM_SR_BIF

Break interrupt flag

Definition at line 481 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_CC1IF TIM_SR_CC1IF

Capture/compare 1 interrupt flag

Definition at line 473 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_CC1OF TIM_SR_CC1OF

Capture/Compare 1 overcapture flag

Definition at line 483 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_CC2IF TIM_SR_CC2IF

Capture/compare 2 interrupt flag

Definition at line 474 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_CC2OF TIM_SR_CC2OF

Capture/Compare 2 overcapture flag

Definition at line 484 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_CC3IF TIM_SR_CC3IF

Capture/compare 3 interrupt flag

Definition at line 475 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_CC3OF TIM_SR_CC3OF

Capture/Compare 3 overcapture flag

Definition at line 485 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_CC4IF TIM_SR_CC4IF

Capture/compare 4 interrupt flag

Definition at line 476 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_CC4OF TIM_SR_CC4OF

Capture/Compare 4 overcapture flag

Definition at line 486 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_CC5IF TIM_SR_CC5IF

Capture/compare 5 interrupt flag

Definition at line 477 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_CC6IF TIM_SR_CC6IF

Capture/compare 6 interrupt flag

Definition at line 478 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_COMIF TIM_SR_COMIF

COM interrupt flag

Definition at line 479 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_SBIF TIM_SR_SBIF

System Break interrupt flag

Definition at line 487 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_TIF TIM_SR_TIF

Trigger interrupt flag

Definition at line 480 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SR_UIF TIM_SR_UIF

Update interrupt flag

Definition at line 472 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
TIM Exported Constants

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. More...

Defines

#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE

Detailed Description

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Define Documentation

#define LL_TIM_DIER_BIE TIM_DIER_BIE

Break interrupt enable

Definition at line 503 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE

Capture/compare 1 interrupt enable

Definition at line 497 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE

Capture/compare 2 interrupt enable

Definition at line 498 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE

Capture/compare 3 interrupt enable

Definition at line 499 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE

Capture/compare 4 interrupt enable

Definition at line 500 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DIER_COMIE TIM_DIER_COMIE

COM interrupt enable

Definition at line 501 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DIER_TIE TIM_DIER_TIE

Trigger interrupt enable

Definition at line 502 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DIER_UIE TIM_DIER_UIE

Update interrupt enable

Definition at line 496 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Update Source

Defines
Update Source
TIM Exported Constants

Defines

#define | LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U)
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Define Documentation

#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Only counter overflow/underflow generates an update request

Definition at line 512 of file stm32l4xx_ll_tim.h.

#define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U)

Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request

Definition at line 511 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: One Pulse Mode

Defines
One Pulse Mode
TIM Exported Constants

Defines

#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U)

Define Documentation

#define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U)

Counter stops counting at the next update event

Definition at line 521 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM

Counter is not stopped at update event

Definition at line 520 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Counter Mode

Defines
Counter Mode
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U)
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

Define Documentation

#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up

Definition at line 532 of file stm32l4xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down.

Definition at line 531 of file stm32l4xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down.

Definition at line 533 of file stm32l4xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as downcounter

Definition at line 530 of file stm32l4xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U)

Counter used as upcounter

Definition at line 529 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

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STM32L486xx HAL User Manual: Clock Division

Defines
Clock Division
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U)

tDTS=tCK_INT

Definition at line 541 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

tDTS=2*tCK_INT

Definition at line 542 of file stm32l4xx_ll_tim.h.

#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

tDTS=4*tCK_INT

Definition at line 543 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Counter Direction

Defines
Counter Direction
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000U)
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Define Documentation

#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Timer counter counts down

Definition at line 552 of file stm32l4xx_ll_tim.h.

#define LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000U)

Timer counter counts up

Definition at line 551 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Capture Compare Update Source

Defines
Capture Compare Update Source
TIM Exported Constants

Defines

#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY ((uint32_t)0x00000000U)
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Define Documentation

#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI)

Definition at line 561 of file stm32l4xx_ll_tim.h.

#define LL_TIM_CCUPDATESOURCE_COMG_ONLY ((uint32_t)0x00000000U)

Capture/compare control bits are updated by setting the COMG bit only

Definition at line 560 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Capture Compare DMA Request

Defines
Capture Compare DMA Request
TIM Exported Constants

Defines

#define | LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000U)
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

Define Documentation

#define LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000U)

CCx DMA request sent when CCx event occurs

Definition at line 569 of file stm32l4xx_ll_tim.h.

#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

CCx DMA requests sent when update event occurs

Definition at line 570 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Lock Level

Defines
Lock Level
TIM Exported Constants

Defines

#define | LL_TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U)
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 579 of file stm32l4xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 580 of file stm32l4xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 581 of file stm32l4xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U)

LOCK OFF - No bit is write protected

Definition at line 578 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Channel

Defines
Channel
TIM Exported Constants

Defines

#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E
#define | LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Define Documentation

#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E

Timer input/output channel 1

Definition at line 589 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE

Timer complementary output channel 1

Definition at line 590 of file stm32l4xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E

Timer input/output channel 2

Definition at line 591 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE

Timer complementary output channel 2

Definition at line 592 of file stm32l4xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E

Timer input/output channel 3

Definition at line 593 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE

Timer complementary output channel 3

Definition at line 594 of file stm32l4xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E

Timer input/output channel 4

Definition at line 595 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E

Timer output channel 5

Definition at line 596 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Timer output channel 6

Definition at line 597 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_Init().

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STM32L486xx HAL User Manual: Output Configuration State

Defines
Output Configuration State
TIM Exported Constants

Defines

#define | LL_TIM_OCSTATE_DISABLE ((uint32_t)0x00000000U)
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define LL_TIM_OCSTATE_DISABLE ((uint32_t)0x00000000U)

OCx is not active

Definition at line 606 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

OCx signal is output on the corresponding output pin

Definition at line 607 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Output Configuration Mode

Defines
Output Configuration Mode
TIM Exported Constants

Defines

#define | LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000U)
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3
#define | LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Define Documentation

#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

OCyREF is forced high on compare match

Definition at line 617 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Asymmetric PWM mode 1

Definition at line 628 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Asymmetric PWM mode 2

Definition at line 629 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Combined PWM mode 1

Definition at line 626 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Combined PWM mode 2

Definition at line 627 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

OCyREF is forced high

Definition at line 621 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)

OCyREF is forced low

Definition at line 620 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000U)

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level

Definition at line 616 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

OCyREF is forced low on compare match

Definition at line 618 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.

Definition at line 622 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive

Definition at line 623 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3

Retrigerrable OPM mode 1

Definition at line 624 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Retrigerrable OPM mode 2

Definition at line 625 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

OCyREF toggles on compare match

Definition at line 619 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Output Configuration Polarity

Defines
Output Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U)

OCxactive high

Definition at line 637 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

OCxactive low

Definition at line 638 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Output Configuration Idle State

Defines
Output Configuration Idle State
TIM Exported Constants

Defines

#define | LL_TIM_OCIDLESTATE_LOW ((uint32_t)0x00000000U)
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

Define Documentation

#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

OCx=1 (after a dead-time if OC is implemented) when MOE=0

Definition at line 647 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCIDLESTATE_LOW ((uint32_t)0x00000000U)

OCx=0 (after a dead-time if OC is implemented) when MOE=0

Definition at line 646 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GROUPCH5

Defines
GROUPCH5
TIM Exported Constants

Defines

#define | LL_TIM_GROUPCH5_NONE (uint32_t)0x00000000U
#define | LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

Define Documentation

#define LL_TIM_GROUPCH5_NONE (uint32_t)0x00000000U

No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC

Definition at line 655 of file stm32l4xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1

OC1REFC is the logical AND of OC1REFC and OC5REF

Definition at line 656 of file stm32l4xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2

OC2REFC is the logical AND of OC2REFC and OC5REF

Definition at line 657 of file stm32l4xx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

OC3REFC is the logical AND of OC3REFC and OC5REF

Definition at line 658 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Active Input Selection

Defines
Active Input Selection
TIM Exported Constants

Defines

#define | LL_TIM_ACTIVEINPUT_DIRECTTI (uint32_t)(TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (uint32_t)(TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (uint32_t)(TIM_CCMR1_CC1S << 16U)

Define Documentation

#define LL_TIM_ACTIVEINPUT_DIRECTTI (uint32_t)(TIM_CCMR1_CC1S_0 << 16U)

ICx is mapped on TIx

Definition at line 666 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ACTIVEINPUT_INDIRECTTI (uint32_t)(TIM_CCMR1_CC1S_1 << 16U)

ICx is mapped on TIy

Definition at line 667 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ACTIVEINPUT_TRC (uint32_t)(TIM_CCMR1_CC1S << 16U)

ICx is mapped on TRC

Definition at line 668 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

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STM32L486xx HAL User Manual: Input Configuration Prescaler

Defines
Input Configuration Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_ICPSC_DIV2 (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (uint32_t)(TIM_CCMR1_IC1PSC << 16U)

Define Documentation

#define LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000U)

No prescaler, capture is done each time an edge is detected on the capture input

Definition at line 676 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ICPSC_DIV2 (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U)

Capture is done once every 2 events

Definition at line 677 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV4 (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U)

Capture is done once every 4 events

Definition at line 678 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV8 (uint32_t)(TIM_CCMR1_IC1PSC << 16U)

Capture is done once every 8 events

Definition at line 679 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Input Configuration Filter

Defines
Input Configuration Filter
TIM Exported Constants

Defines

#define | LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_IC_FILTER_FDIV1_N2 (uint32_t)(TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (uint32_t)(TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (uint32_t)(TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (uint32_t)(TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (uint32_t)(TIM_CCMR1_IC1F << 16U)

Define Documentation

#define LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000U)

No filter, sampling is done at fDTS

Definition at line 687 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_IC_FILTER_FDIV16_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/16, N=5

Definition at line 697 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/16, N=6

Definition at line 698 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)

fSAMPLING=fDTS/16, N=8

Definition at line 699 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N2 (uint32_t)(TIM_CCMR1_IC1F_0 << 16U)

fSAMPLING=fCK_INT, N=2

Definition at line 688 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N4 (uint32_t)(TIM_CCMR1_IC1F_1 << 16U)

fSAMPLING=fCK_INT, N=4

Definition at line 689 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N8 (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fCK_INT, N=8

Definition at line 690 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N6 (uint32_t)(TIM_CCMR1_IC1F_2 << 16U)

fSAMPLING=fDTS/2, N=6

Definition at line 691 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/2, N=8

Definition at line 692 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/32, N=5

Definition at line 700 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/32, N=6

Definition at line 701 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N8 (uint32_t)(TIM_CCMR1_IC1F << 16U)

fSAMPLING=fDTS/32, N=8

Definition at line 702 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N6 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/4, N=6

Definition at line 693 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/4, N=8

Definition at line 694 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N6 (uint32_t)(TIM_CCMR1_IC1F_3 << 16U)

fSAMPLING=fDTS/8, N=6

Definition at line 695 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/8, N=8

Definition at line 696 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input Configuration Polarity

Defines
Input Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000U)
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted

Definition at line 712 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P

The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted

Definition at line 711 of file stm32l4xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000U)

The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted

Definition at line 710 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Clock Source

Defines
Clock Source
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 )
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Define Documentation

#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 )

Counter counts at each rising or falling edge on a selected inpu t

Definition at line 721 of file stm32l4xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Counter counts at each rising or falling edge on the external trigger input ETR

Definition at line 722 of file stm32l4xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000U)

The timer is clocked by the internal clock provided from the RCC

Definition at line 720 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Encoder Mode

Defines
Encoder Mode
TIM Exported Constants

Defines

#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0

Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level

Definition at line 730 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit().

#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1

Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 731 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l

Definition at line 732 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Trigger Output

Defines
Trigger Output
TIM Exported Constants

Defines

#define | LL_TIM_TRGO_RESET ((uint32_t)0x00000000U)
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Define Documentation

#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

CC1 capture or a compare match is used as trigger output

Definition at line 743 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0

Counter Enable signal (CNT_EN) is used as trigger output

Definition at line 741 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output

Definition at line 744 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output

Definition at line 745 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output

Definition at line 746 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output

Definition at line 747 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO_RESET ((uint32_t)0x00000000U)

UG bit from the TIMx_EGR register is used as trigger output

Definition at line 740 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output

Definition at line 742 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Trigger Output 2

Defines
Trigger Output 2
TIM Exported Constants

Defines

#define | LL_TIM_TRGO2_RESET ((uint32_t)0x00000000U)
#define | LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2
#define | LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3
#define | LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Define Documentation

#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

CC1 capture or a compare match is used as trigger output 2

Definition at line 758 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0

Counter Enable signal (CNT_EN) is used as trigger output 2

Definition at line 756 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2

OC1REF signal is used as trigger output 2

Definition at line 759 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC2REF signal is used as trigger output 2

Definition at line 760 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)

OC3REF signal is used as trigger output 2

Definition at line 761 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC4REF signal is used as trigger output 2

Definition at line 762 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC4REF rising or OC6REF falling edges are used as trigger output 2

Definition at line 768 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)

OC4REF or OC6REF rising edges are used as trigger output 2

Definition at line 767 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)

OC4REF rising or falling edges are used as trigger output 2

Definition at line 765 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3

OC5REF signal is used as trigger output 2

Definition at line 763 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC5REF rising or OC6REF falling edges are used as trigger output 2

Definition at line 770 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)

OC5REF or OC6REF rising edges are used as trigger output 2

Definition at line 769 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)

OC6REF signal is used as trigger output 2

Definition at line 764 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC6REF rising or falling edges are used as trigger output 2

Definition at line 766 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_RESET ((uint32_t)0x00000000U)

UG bit from the TIMx_EGR register is used as trigger output 2

Definition at line 755 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1

Update event is used as trigger output 2

Definition at line 757 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Slave Mode

Defines
Slave Mode
TIM Exported Constants

Defines

#define | LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000U)
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Define Documentation

#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter

Definition at line 782 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000U)

Slave mode disabled

Definition at line 778 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high

Definition at line 780 of file stm32l4xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter

Definition at line 779 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode - The counter starts at a rising edge of the trigger TRGI

Definition at line 781 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: Trigger Selection

Defines
Trigger Selection
TIM Exported Constants

Defines

#define | LL_TIM_TS_ITR0 ((uint32_t)0x00000000U)
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF TIM_SMCR_TS

Define Documentation

#define LL_TIM_TS_ETRF TIM_SMCR_TS

Filtered external Trigger (ETRF) is used as trigger input

Definition at line 797 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TS_ITR0 ((uint32_t)0x00000000U)

Internal Trigger 0 (ITR0) is used as trigger input

Definition at line 790 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1) is used as trigger input

Definition at line 791 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2) is used as trigger input

Definition at line 792 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3) is used as trigger input

Definition at line 793 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED) is used as trigger input

Definition at line 794 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)

Filtered Timer Input 1 (TI1FP1) is used as trigger input

Definition at line 795 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)

Filtered Timer Input 2 (TI12P2) is used as trigger input

Definition at line 796 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: External Trigger Polarity

Defines
External Trigger Polarity
TIM Exported Constants

Defines

#define | LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000U)
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

Define Documentation

#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

ETR is inverted, active at low level or falling edge

Definition at line 806 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000U)

ETR is non-inverted, active at high level or rising edge

Definition at line 805 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: External Trigger Prescaler

Defines
External Trigger Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000U)

ETR prescaler OFF

Definition at line 814 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR frequency is divided by 2

Definition at line 815 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR frequency is divided by 4

Definition at line 816 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

ETR frequency is divided by 8

Definition at line 817 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: External Trigger Filter

Defines
External Trigger Filter
TIM Exported Constants

Defines

#define | LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 )
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 )
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 )
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

Define Documentation

#define LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000U)

No filter, sampling is done at fDTS

Definition at line 825 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 )

fSAMPLING=fDTS/16, N=6

Definition at line 835 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=8

Definition at line 836 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 )

fSAMPLING=fDTS/16, N=5

Definition at line 837 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0

fSAMPLING=fCK_INT, N=2

Definition at line 826 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1

fSAMPLING=fCK_INT, N=4

Definition at line 827 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fCK_INT, N=8

Definition at line 828 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2

fSAMPLING=fDTS/2, N=6

Definition at line 829 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/2, N=8

Definition at line 830 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/32, N=5

Definition at line 838 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/32, N=6

Definition at line 839 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

fSAMPLING=fDTS/32, N=8

Definition at line 840 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 )

fSAMPLING=fDTS/4, N=6

Definition at line 831 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/4, N=8

Definition at line 832 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3

fSAMPLING=fDTS/8, N=8

Definition at line 833 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=5

Definition at line 834 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: External Trigger Source

Defines
External Trigger Source
TIM Exported Constants

Defines

#define | LL_TIM_ETRSOURCE_LEGACY ((uint32_t)(0x00000000U))
#define | LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0
#define | LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1

Define Documentation

#define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0

COMP1 output connected to ETR input

Definition at line 849 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1

COMP2 output connected to ETR input

Definition at line 850 of file stm32l4xx_ll_tim.h.

#define LL_TIM_ETRSOURCE_LEGACY ((uint32_t)(0x00000000U))

ETR legacy mode

Definition at line 848 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: break polarity

Defines
break polarity
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_POLARITY_LOW ((uint32_t)0x00000000U)
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 859 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_POLARITY_LOW ((uint32_t)0x00000000U)

Break input BRK is active low

Definition at line 858 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: break filter

Defines
break filter
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_FILTER_FDIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_BREAK_FILTER_FDIV1_N2 ((uint32_t)0x00010000U)
#define | LL_TIM_BREAK_FILTER_FDIV1_N4 ((uint32_t)0x00020000U)
#define | LL_TIM_BREAK_FILTER_FDIV1_N8 ((uint32_t)0x00030000U)
#define | LL_TIM_BREAK_FILTER_FDIV2_N6 ((uint32_t)0x00040000U)
#define | LL_TIM_BREAK_FILTER_FDIV2_N8 ((uint32_t)0x00050000U)
#define | LL_TIM_BREAK_FILTER_FDIV4_N6 ((uint32_t)0x00060000U)
#define | LL_TIM_BREAK_FILTER_FDIV4_N8 ((uint32_t)0x00070000U)
#define | LL_TIM_BREAK_FILTER_FDIV8_N6 ((uint32_t)0x00080000U)
#define | LL_TIM_BREAK_FILTER_FDIV8_N8 ((uint32_t)0x00090000U)
#define | LL_TIM_BREAK_FILTER_FDIV16_N5 ((uint32_t)0x000A0000U)
#define | LL_TIM_BREAK_FILTER_FDIV16_N6 ((uint32_t)0x000B0000U)
#define | LL_TIM_BREAK_FILTER_FDIV16_N8 ((uint32_t)0x000C0000U)
#define | LL_TIM_BREAK_FILTER_FDIV32_N5 ((uint32_t)0x000D0000U)
#define | LL_TIM_BREAK_FILTER_FDIV32_N6 ((uint32_t)0x000E0000U)
#define | LL_TIM_BREAK_FILTER_FDIV32_N8 ((uint32_t)0x000F0000U)

Define Documentation

#define LL_TIM_BREAK_FILTER_FDIV1 ((uint32_t)0x00000000U)

No filter, BRK acts asynchronously

Definition at line 867 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N5 ((uint32_t)0x000A0000U)

fSAMPLING=fDTS/16, N=5

Definition at line 877 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N6 ((uint32_t)0x000B0000U)

fSAMPLING=fDTS/16, N=6

Definition at line 878 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N8 ((uint32_t)0x000C0000U)

fSAMPLING=fDTS/16, N=8

Definition at line 879 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N2 ((uint32_t)0x00010000U)

fSAMPLING=fCK_INT, N=2

Definition at line 868 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N4 ((uint32_t)0x00020000U)

fSAMPLING=fCK_INT, N=4

Definition at line 869 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N8 ((uint32_t)0x00030000U)

fSAMPLING=fCK_INT, N=8

Definition at line 870 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV2_N6 ((uint32_t)0x00040000U)

fSAMPLING=fDTS/2, N=6

Definition at line 871 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV2_N8 ((uint32_t)0x00050000U)

fSAMPLING=fDTS/2, N=8

Definition at line 872 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N5 ((uint32_t)0x000D0000U)

fSAMPLING=fDTS/32, N=5

Definition at line 880 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N6 ((uint32_t)0x000E0000U)

fSAMPLING=fDTS/32, N=6

Definition at line 881 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N8 ((uint32_t)0x000F0000U)

fSAMPLING=fDTS/32, N=8

Definition at line 882 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV4_N6 ((uint32_t)0x00060000U)

fSAMPLING=fDTS/4, N=6

Definition at line 873 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV4_N8 ((uint32_t)0x00070000U)

fSAMPLING=fDTS/4, N=8

Definition at line 874 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV8_N6 ((uint32_t)0x00080000U)

fSAMPLING=fDTS/8, N=6

Definition at line 875 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV8_N8 ((uint32_t)0x00090000U)

fSAMPLING=fDTS/8, N=8

Definition at line 876 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: BREAK2 POLARITY

Defines
BREAK2 POLARITY
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_POLARITY_LOW ((uint32_t)0x00000000U)
#define | LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P

Define Documentation

#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P

Break input BRK2 is active high

Definition at line 891 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_POLARITY_LOW ((uint32_t)0x00000000U)

Break input BRK2 is active low

Definition at line 890 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: BREAK2 FILTER

Defines
BREAK2 FILTER
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_FILTER_FDIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_BREAK2_FILTER_FDIV1_N2 ((uint32_t)0x00100000U)
#define | LL_TIM_BREAK2_FILTER_FDIV1_N4 ((uint32_t)0x00200000U)
#define | LL_TIM_BREAK2_FILTER_FDIV1_N8 ((uint32_t)0x00300000U)
#define | LL_TIM_BREAK2_FILTER_FDIV2_N6 ((uint32_t)0x00400000U)
#define | LL_TIM_BREAK2_FILTER_FDIV2_N8 ((uint32_t)0x00500000U)
#define | LL_TIM_BREAK2_FILTER_FDIV4_N6 ((uint32_t)0x00600000U)
#define | LL_TIM_BREAK2_FILTER_FDIV4_N8 ((uint32_t)0x00700000U)
#define | LL_TIM_BREAK2_FILTER_FDIV8_N6 ((uint32_t)0x00800000U)
#define | LL_TIM_BREAK2_FILTER_FDIV8_N8 ((uint32_t)0x00900000U)
#define | LL_TIM_BREAK2_FILTER_FDIV16_N5 ((uint32_t)0x00A00000U)
#define | LL_TIM_BREAK2_FILTER_FDIV16_N6 ((uint32_t)0x00B00000U)
#define | LL_TIM_BREAK2_FILTER_FDIV16_N8 ((uint32_t)0x00C00000U)
#define | LL_TIM_BREAK2_FILTER_FDIV32_N5 ((uint32_t)0x00D00000U)
#define | LL_TIM_BREAK2_FILTER_FDIV32_N6 ((uint32_t)0x00E00000U)
#define | LL_TIM_BREAK2_FILTER_FDIV32_N8 ((uint32_t)0x00F00000U)

Define Documentation

#define LL_TIM_BREAK2_FILTER_FDIV1 ((uint32_t)0x00000000U)

No filter, BRK acts asynchronously

Definition at line 899 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N5 ((uint32_t)0x00A00000U)

fSAMPLING=fDTS/16, N=5

Definition at line 909 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N6 ((uint32_t)0x00B00000U)

fSAMPLING=fDTS/16, N=6

Definition at line 910 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N8 ((uint32_t)0x00C00000U)

fSAMPLING=fDTS/16, N=8

Definition at line 911 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N2 ((uint32_t)0x00100000U)

fSAMPLING=fCK_INT, N=2

Definition at line 900 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N4 ((uint32_t)0x00200000U)

fSAMPLING=fCK_INT, N=4

Definition at line 901 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N8 ((uint32_t)0x00300000U)

fSAMPLING=fCK_INT, N=8

Definition at line 902 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV2_N6 ((uint32_t)0x00400000U)

fSAMPLING=fDTS/2, N=6

Definition at line 903 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV2_N8 ((uint32_t)0x00500000U)

fSAMPLING=fDTS/2, N=8

Definition at line 904 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N5 ((uint32_t)0x00D00000U)

fSAMPLING=fDTS/32, N=5

Definition at line 912 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N6 ((uint32_t)0x00E00000U)

fSAMPLING=fDTS/32, N=6

Definition at line 913 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N8 ((uint32_t)0x00F00000U)

fSAMPLING=fDTS/32, N=8

Definition at line 914 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV4_N6 ((uint32_t)0x00600000U)

fSAMPLING=fDTS/4, N=6

Definition at line 905 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV4_N8 ((uint32_t)0x00700000U)

fSAMPLING=fDTS/4, N=8

Definition at line 906 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV8_N6 ((uint32_t)0x00800000U)

fSAMPLING=fDTS/8, N=6

Definition at line 907 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV8_N8 ((uint32_t)0x00900000U)

fSAMPLING=fDTS/8, N=8

Definition at line 908 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OSSI

Defines
OSSI
TIM Exported Constants

Defines

#define | LL_TIM_OSSI_DISABLE ((uint32_t)0x00000000U)
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

Define Documentation

#define LL_TIM_OSSI_DISABLE ((uint32_t)0x00000000U)

When inactive, OCx/OCxN outputs are disabled

Definition at line 922 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime

Definition at line 923 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OSSR

Defines
OSSR
TIM Exported Constants

Defines

#define | LL_TIM_OSSR_DISABLE ((uint32_t)0x00000000U)
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

Define Documentation

#define LL_TIM_OSSR_DISABLE ((uint32_t)0x00000000U)

When inactive, OCx/OCxN outputs are disabled

Definition at line 931 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1

Definition at line 932 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: BREAK INPUT

Defines
BREAK INPUT
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_INPUT_BKIN ((uint32_t)0x00000000U)
#define | LL_TIM_BREAK_INPUT_BKIN2 ((uint32_t)0x00000004U)

Define Documentation

#define LL_TIM_BREAK_INPUT_BKIN ((uint32_t)0x00000000U)

TIMx_BKIN input

Definition at line 940 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BREAK_INPUT_BKIN2 ((uint32_t)0x00000004U)

TIMx_BKIN2 input

Definition at line 941 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: BKIN SOURCE

Defines
BKIN SOURCE
TIM Exported Constants

Defines

#define | LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE
#define | LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E
#define | LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E
#define | LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E

Define Documentation

#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E

internal signal: COMP1 output

Definition at line 950 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E

internal signal: COMP2 output

Definition at line 951 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE

BKIN input from AF controller

Definition at line 949 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E

internal signal: DFSDM1 break output

Definition at line 952 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: BKIN POLARITY

Defines
BKIN POLARITY
TIM Exported Constants

Defines

#define | LL_TIM_BKIN_POLARITY_LOW ((uint32_t)0x00000000U)
#define | LL_TIM_BKIN_POLARITY_HIGH TIM1_OR2_BKINP

Define Documentation

#define LL_TIM_BKIN_POLARITY_HIGH TIM1_OR2_BKINP

BRK BKIN input is active high

Definition at line 961 of file stm32l4xx_ll_tim.h.

#define LL_TIM_BKIN_POLARITY_LOW ((uint32_t)0x00000000U)

BRK BKIN input is active low

Definition at line 960 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Burst Base Address

Defines
DMA Burst Base Address
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000U) /*!< TIMx_CR1 register is the DMA base address for DMA burst */
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

Define Documentation

#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_ARR register is the DMA base address for DMA burst

Definition at line 980 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)

TIMx_BDTR register is the DMA base address for DMA burst

Definition at line 986 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3

TIMx_CCER register is the DMA base address for DMA burst

Definition at line 977 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCMR1 register is the DMA base address for DMA burst

Definition at line 975 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCMR2 register is the DMA base address for DMA burst

Definition at line 976 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)

TIMx_CCMR3 register is the DMA base address for DMA burst

Definition at line 987 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_CCR1 register is the DMA base address for DMA burst

Definition at line 982 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCR2 register is the DMA base address for DMA burst

Definition at line 983 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR3 register is the DMA base address for DMA burst

Definition at line 984 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4

TIMx_CCR4 register is the DMA base address for DMA burst

Definition at line 985 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR5 register is the DMA base address for DMA burst

Definition at line 988 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)

TIMx_CCR6 register is the DMA base address for DMA burst

Definition at line 989 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

TIMx_CNT register is the DMA base address for DMA burst

Definition at line 978 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000U) /*!< TIMx_CR1 register is the DMA base address for DMA burst */

TIMx_CR1 register is the DMA base address for DMA burst

Definition at line 969 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0

TIMx_CR2 register is the DMA base address for DMA burst

Definition at line 970 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_DIER register is the DMA base address for DMA burst

Definition at line 972 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_EGR register is the DMA base address for DMA burst

Definition at line 974 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_OR1 register is the DMA base address for DMA burst

Definition at line 990 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_OR2 register is the DMA base address for DMA burst

Definition at line 991 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_OR3 register is the DMA base address for DMA burst

Definition at line 992 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

TIMx_PSC register is the DMA base address for DMA burst

Definition at line 979 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)

TIMx_RCR register is the DMA base address for DMA burst

Definition at line 981 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1

TIMx_SMCR register is the DMA base address for DMA burst

Definition at line 971 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2

TIMx_SR register is the DMA base address for DMA burst

Definition at line 973 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: DMA Burst Length

Defines
DMA Burst Length
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000U)
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Define Documentation

#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)

Transfer is done to 10 registers starting from the DMA burst base address

Definition at line 1009 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)

Transfer is done to 11 registers starting from the DMA burst base address

Definition at line 1010 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 12 registers starting from the DMA burst base address

Definition at line 1011 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)

Transfer is done to 13 registers starting from the DMA burst base address

Definition at line 1012 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 14 registers starting from the DMA burst base address

Definition at line 1013 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 15 registers starting from the DMA burst base address

Definition at line 1014 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 16 registers starting from the DMA burst base address

Definition at line 1015 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4

Transfer is done to 17 registers starting from the DMA burst base address

Definition at line 1016 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Transfer is done to 18 registers starting from the DMA burst base address

Definition at line 1017 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000U)

Transfer is done to 1 register starting from the DMA burst base address

Definition at line 1000 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0

Transfer is done to 2 registers starting from the DMA burst base address

Definition at line 1001 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1

Transfer is done to 3 registers starting from the DMA burst base address

Definition at line 1002 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 4 registers starting from the DMA burst base address

Definition at line 1003 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2

Transfer is done to 5 registers starting from the DMA burst base address

Definition at line 1004 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 6 registers starting from the DMA burst base address

Definition at line 1005 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 7 registers starting from the DMA burst base address

Definition at line 1006 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 1 registers starting from the DMA burst base address

Definition at line 1007 of file stm32l4xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3

Transfer is done to 9 registers starting from the DMA burst base address

Definition at line 1008 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: TIM1 External Trigger ADC1 Remap

Defines
TIM1 External Trigger ADC1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM1_ETR_ADC1_RMP_NC ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK)

TIM1_ETR is connected to ADC1 analog watchdog 1

Definition at line 1026 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK)

TIM1_ETR is connected to ADC1 analog watchdog 2

Definition at line 1027 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK)

TIM1_ETR is connected to ADC1 analog watchdog 3

Definition at line 1028 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM1_ETR_ADC1_RMP_NC ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)

TIM1_ETR is not connected to ADC1 analog watchdog x

Definition at line 1025 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: TIM1 External Trigger ADC3 Remap

Defines
TIM1 External Trigger ADC3 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM1_ETR_ADC3_RMP_NC ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK)

TIM1_ETR is connected to ADC3 analog watchdog 1

Definition at line 1037 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK)

TIM1_ETR is connected to ADC3 analog watchdog 2

Definition at line 1038 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK)

TIM1_ETR is connected to ADC3 analog watchdog 3

Definition at line 1039 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM1_ETR_ADC3_RMP_NC ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)

TIM1_ETR is not connected to ADC3 analog watchdog x

Definition at line 1036 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: TIM1 External Input Ch1 Remap

Defines
TIM1 External Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM1_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK)

TIM1 input capture 1 is connected to COMP1 output

Definition at line 1048 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM1_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)

TIM1 input capture 1 is connected to GPIO

Definition at line 1047 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: TIM2 Internal Trigger1 Remap TIM8

Defines
TIM2 Internal Trigger1 Remap TIM8
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_ETR_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM2_ETR_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK)

TIM2_ETR is connected to GPIO

Definition at line 1058 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK)

TIM2_ETR is connected to LSE

Definition at line 1059 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK)

TIM2_ITR1 is connected to OTG_FS SOF

Definition at line 1057 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK)

TIM2_ITR1 is connected to TIM8_TRGO

Definition at line 1056 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: TIM2 External Input Ch4 Remap

Defines
TIM2 External Input Ch4 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_TI4_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK)

TIM2 input capture 4 is connected to COMP1_OUT

Definition at line 1068 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK)

TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT

Definition at line 1070 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK)

TIM2 input capture 4 is connected to COMP2_OUT

Definition at line 1069 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM2_TI4_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK)

TIM2 input capture 4 is connected to GPIO

Definition at line 1067 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: TIM3 External Input Ch1 Remap

Defines
TIM3 External Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM3_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM3_OR1_RMP_MASK)
#define | LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK)
#define | LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK)
#define | LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK)

TIM3 input capture 1 is connected to COMP1_OUT

Definition at line 1079 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK)

TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT

Definition at line 1081 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK)

TIM3 input capture 1 is connected to COMP2_OUT

Definition at line 1080 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM3_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM3_OR1_RMP_MASK)

TIM3 input capture 1 is connected to GPIO

Definition at line 1078 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: TIM8 External Trigger ADC2 Remap

Defines
TIM8 External Trigger ADC2 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM8_ETR_ADC2_RMP_NC ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK)

TIM8_ETR is connected to ADC2 analog watchdog

Definition at line 1090 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK)

TIM8_ETR is connected to ADC2 analog watchdog 2

Definition at line 1091 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK)

TIM8_ETR is connected to ADC2 analog watchdog 3

Definition at line 1092 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM8_ETR_ADC2_RMP_NC ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)

TIM8_ETR is not connected to ADC2 analog watchdog x

Definition at line 1089 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: TIM8 External Trigger ADC3 Remap

Defines
TIM8 External Trigger ADC3 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM8_ETR_ADC3_RMP_NC ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK)

TIM8_ETR is connected to ADC3 analog watchdog 1

Definition at line 1101 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK)

TIM8_ETR is connected to ADC3 analog watchdog 2

Definition at line 1102 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK)

TIM8_ETR is connected to ADC3 analog watchdog 3

Definition at line 1103 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM8_ETR_ADC3_RMP_NC ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)

TIM8_ETR is not connected to ADC3 analog watchdog x

Definition at line 1100 of file stm32l4xx_ll_tim.h.

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STM32L486xx HAL User Manual: TIM8 External Input Ch1 Remap

Defines
TIM8 External Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM8_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK)

TIM8 input capture 1 is connected to COMP2 output

Definition at line 1112 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM8_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)

TIM8 input capture 1 is connected to GPIO

Definition at line 1111 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM15 External Input Ch1 Remap

Defines
TIM15 External Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM15_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM15_OR1_RMP_MASK)
#define | LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM15_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM15_OR1_RMP_MASK)

TIM15 input capture 1 is connected to GPIO

Definition at line 1120 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK)

TIM15 input capture 1 is connected to LSE

Definition at line 1121 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM15 ENCODERMODE

Defines
TIM15 ENCODERMODE
TIM Exported Constants

Defines

#define | LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION ((uint32_t)0x00000000U | TIM15_OR1_RMP_MASK)
#define | LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK)
#define | LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK)
#define | LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION ((uint32_t)0x00000000U | TIM15_OR1_RMP_MASK)

No redirection

Definition at line 1129 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK)

TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively

Definition at line 1130 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK)

TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y

Definition at line 1131 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK)

TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively

Definition at line 1132 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM16 External Input Ch1 Remap

Defines
TIM16 External Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM16_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM16_OR1_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM16_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM16_OR1_RMP_MASK)

TIM16 input capture 1 is connected to GPIO

Definition at line 1140 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK)

TIM16 input capture 1 is connected to LSE

Definition at line 1142 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)

TIM16 input capture 1 is connected to LSI

Definition at line 1141 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)

TIM16 input capture 1 is connected to RTC wakeup interrupt

Definition at line 1143 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM17 Timer Input Ch1 Remap

Defines
TIM17 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM17_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM17_OR1_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK)

Define Documentation

#define LL_TIM_TIM17_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM17_OR1_RMP_MASK)

TIM17 input capture 1 is connected to GPIO

Definition at line 1156 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK)

TIM17 input capture 1 is connected to HSE/32

Definition at line 1158 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK)

TIM17 input capture 1 is connected to MCO

Definition at line 1159 of file stm32l4xx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK)

TIM17 input capture 1 is connected to MSI

Definition at line 1157 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OCREF clear input selection

Defines
OCREF clear input selection
TIM Exported Constants

Defines

#define | LL_TIM_OCREF_CLR_INT_NC ((uint32_t)0x00000000U )
#define | LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS

Define Documentation

#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS

OCREF_CLR_INT is connected to ETRF

Definition at line 1168 of file stm32l4xx_ll_tim.h.

#define LL_TIM_OCREF_CLR_INT_NC ((uint32_t)0x00000000U )

OCREF_CLR_INT is not connected

Definition at line 1167 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
TIM Exported Macros

Defines

#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in TIM register.

Define Documentation

#define LL_TIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1208 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define LL_TIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1200 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Exported_Macros

Defines
Exported_Macros
TIM Exported Macros

Defines

#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> POSITION_VAL(TIM_CNT_UIFCPY))
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_POSITION_ICPSC)))
HELPER macro retrieving the ratio of the input capture prescaler.

Define Documentation

#define __LL_TIM_CALC_ARR | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __FREQ__
 | ) | (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U

HELPER macro calculating the auto-reload value to achieve the required output signal frequency.

Note:
ex: __LL_TIM_CALC_ARR (1000000, LL_TIM_GetPrescaler (), 10000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__FREQ__ | output signal frequency (in Hz)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1263 of file stm32l4xx_ll_tim.h.

#define __LL_TIM_CALC_DEADTIME | ( | __TIMCLK__,
 |  | __CKD__,
 |  | __DT__
 | ) |
Value:
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))           ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
      (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
      (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
      (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
       0U)

HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.

Note:
ex: __LL_TIM_CALC_DEADTIME (80000000, LL_TIM_GetClockDivision (), 120);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
__DT__ | deadtime duration (in ns)
Return values:
DTG[0:7]

Definition at line 1238 of file stm32l4xx_ll_tim.h.

#define __LL_TIM_CALC_DELAY | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__
 | ) |
Value:
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
          / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.

Note:
ex: __LL_TIM_CALC_DELAY (1000000, LL_TIM_GetPrescaler (), 10);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
Return values:
Compare value (between Min_Data=0 and Max_Data=65535)

Definition at line 1274 of file stm32l4xx_ll_tim.h.

#define __LL_TIM_CALC_PSC | ( | __TIMCLK__,
 |  | __CNTCLK__
 | ) | ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U

HELPER macro calculating the prescaler value to achieve the required counter clock frequency.

Note:
ex: __LL_TIM_CALC_PSC (80000000, 1000000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CNTCLK__ | counter clock frequency (in Hz)
Return values:
Prescaler value (between Min_Data=0 and Max_Data=65535)

Definition at line 1252 of file stm32l4xx_ll_tim.h.

#define __LL_TIM_CALC_PULSE | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__,
 |  | __PULSE__
 | ) |
Value:
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
           + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))

HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).

Note:
ex: __LL_TIM_CALC_PULSE (1000000, LL_TIM_GetPrescaler (), 10, 20);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
__PULSE__ | pulse duration (in us)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1287 of file stm32l4xx_ll_tim.h.

#define __LL_TIM_GET_ICPSC_RATIO ( __ICPSC__ ) ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_POSITION_ICPSC)))

HELPER macro retrieving the ratio of the input capture prescaler.

Note:
ex: __LL_TIM_GET_ICPSC_RATIO (LL_TIM_IC_GetPrescaler ());
Parameters:
__ICPSC__ This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
Input capture prescaler ratio (1, 2, 4 or 8)

Definition at line 1301 of file stm32l4xx_ll_tim.h.

#define __LL_TIM_GETFLAG_UIFCPY ( __CNT__ ) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> POSITION_VAL(TIM_CNT_UIFCPY))

HELPER macro retrieving the UIFCPY flag from the counter value.

Note:
ex: __LL_TIM_GETFLAG_UIFCPY (LL_TIM_GetCounter ());
Relevant only if UIF flag remapping has been enabled (UIF status bit is copied to TIMx_CNT register bit 31)
Parameters:
__CNT__ Counter value
Return values:
UIF status bit

Definition at line 1224 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Time Base configuration

Functions
Time Base configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_EnableUIFRemap (TIM_TypeDef *TIMx)
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
__STATIC_INLINE void | LL_TIM_DisableUIFRemap (TIM_TypeDef *TIMx)
Disable update interrupt flag (UIF) remapping.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableARRPreload ( TIM_TypeDef * TIMx )

Disable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_DisableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1507 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableCounter ( TIM_TypeDef * TIMx )

Disable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_DisableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1339 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUIFRemap ( TIM_TypeDef * TIMx )

Disable update interrupt flag (UIF) remapping.

Reference Manual to LL API cross reference:
CR1 UIFREMAP LL_TIM_DisableUIFRemap
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1700 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUpdateEvent ( TIM_TypeDef * TIMx )

Disable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_DisableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1372 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableARRPreload ( TIM_TypeDef * TIMx )

Enable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_EnableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1496 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableCounter ( TIM_TypeDef * TIMx )

Enable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_EnableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1328 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUIFRemap ( TIM_TypeDef * TIMx )

Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).

Note:
This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
Reference Manual to LL API cross reference:
CR1 UIFREMAP LL_TIM_EnableUIFRemap
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1689 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUpdateEvent ( TIM_TypeDef * TIMx )

Enable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_EnableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1361 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetAutoReload ( TIM_TypeDef * TIMx )

Get the auto-reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_TIM_GetAutoReload
Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Parameters:
TIMx Timer instance
Return values:
Auto-reload value

Definition at line 1649 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetClockDivision ( TIM_TypeDef * TIMx )

Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_GetClockDivision
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4

Definition at line 1553 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounter ( TIM_TypeDef * TIMx )

Get the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_GetCounter
Parameters:
TIMx Timer instance
Return values:
Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)

Definition at line 1580 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounterMode ( TIM_TypeDef * TIMx )

Get actual counter mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetCounterMode
CR1 CMS LL_TIM_GetCounterMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN

Definition at line 1485 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetDirection ( TIM_TypeDef * TIMx )

Get the current direction of the counter.

Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetDirection
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERDIRECTION_UP
  • LL_TIM_COUNTERDIRECTION_DOWN

Definition at line 1593 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode ( TIM_TypeDef * TIMx )

Get actual one pulse mode.

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_GetOnePulseMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE

Definition at line 1444 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetPrescaler ( TIM_TypeDef * TIMx )

Get the prescaler value.

Reference Manual to LL API cross reference:
PSC PSC LL_TIM_GetPrescaler
Parameters:
TIMx Timer instance
Return values:
Prescaler value between Min_Data=0 and Max_Data=65535

Definition at line 1620 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter ( TIM_TypeDef * TIMx )

Get the repetition counter value.

Note:
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_GetRepetitionCounter
Parameters:
TIMx Timer instance
Return values:
Repetition counter value

Definition at line 1677 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource ( TIM_TypeDef * TIMx )

Get actual event update source.

Reference Manual to LL API cross reference:
CR1 URS LL_TIM_GetUpdateSource
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER

Definition at line 1417 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload ( TIM_TypeDef * TIMx )

Indicates whether auto-reload (ARR) preload is enabled.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_IsEnabledARRPreload
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1518 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter ( TIM_TypeDef * TIMx )

Indicates whether the timer counter is enabled.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_IsEnabledCounter
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1350 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent ( TIM_TypeDef * TIMx )

Indicates whether update event generation is enabled.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_IsEnabledUpdateEvent
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1383 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetAutoReload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto-reload value.

Note:
The counter is blocked while the auto-reload value is null.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Helper macro __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
Reference Manual to LL API cross reference:
ARR ARR LL_TIM_SetAutoReload
Parameters:
TIMx | Timer instance
AutoReload | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1636 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockDivision
 | ) |  |

Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_SetClockDivision
Parameters:
TIMx Timer instance
ClockDivision This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 1536 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Counter
 | ) |  |

Set the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_SetCounter
Parameters:
TIMx | Timer instance
Counter | Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
Return values:
None

Definition at line 1567 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounterMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the timer counter counting mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_SetCounterMode
CR1 CMS LL_TIM_SetCounterMode
Parameters:
TIMx Timer instance
CounterMode This parameter can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN
Return values:
None

Definition at line 1465 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OnePulseMode
 | ) |  |

Set one pulse mode (one shot v.s.

repetitive).

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_SetOnePulseMode
Parameters:
TIMx Timer instance
OnePulseMode This parameter can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE
Return values:
None

Definition at line 1431 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the prescaler value.

Note:
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
The prescaler can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Helper macro __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
Reference Manual to LL API cross reference:
PSC PSC LL_TIM_SetPrescaler
Parameters:
TIMx | Timer instance
Prescaler | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1609 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetRepetitionCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | RepetitionCounter
 | ) |  |

Set the repetition counter value.

Note:
For advanced timer instances RepetitionCounter can be up to 65535.
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_SetRepetitionCounter
Parameters:
TIMx | Timer instance
RepetitionCounter | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 1664 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetUpdateSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | UpdateSource
 | ) |  |

Set update event source.

Note:
Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events generate an update interrupt or DMA request if enabled:
  • Counter overflow/underflow
  • Setting the UG bit
  • Update generation through the slave mode controller
Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Reference Manual to LL API cross reference:
CR1 URS LL_TIM_SetUpdateSource
Parameters:
TIMx Timer instance
UpdateSource This parameter can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER
Return values:
None

Definition at line 1404 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Capture Compare configuration

Functions
Capture Compare configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_CC_DisableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Disable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_DisableChannel
CCER CC1NE LL_TIM_CC_DisableChannel
CCER CC2E LL_TIM_CC_DisableChannel
CCER CC2NE LL_TIM_CC_DisableChannel
CCER CC3E LL_TIM_CC_DisableChannel
CCER CC3NE LL_TIM_CC_DisableChannel
CCER CC4E LL_TIM_CC_DisableChannel
CCER CC5E LL_TIM_CC_DisableChannel
CCER CC6E LL_TIM_CC_DisableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 1856 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_DisablePreload ( TIM_TypeDef * TIMx )

Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_DisablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1736 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Enable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_EnableChannel
CCER CC1NE LL_TIM_CC_EnableChannel
CCER CC2E LL_TIM_CC_EnableChannel
CCER CC2NE LL_TIM_CC_EnableChannel
CCER CC3E LL_TIM_CC_EnableChannel
CCER CC3NE LL_TIM_CC_EnableChannel
CCER CC4E LL_TIM_CC_EnableChannel
CCER CC5E LL_TIM_CC_EnableChannel
CCER CC6E LL_TIM_CC_EnableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 1827 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnablePreload ( TIM_TypeDef * TIMx )

Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs.
Only on channels that have a complementary output.
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_EnablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1723 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger ( TIM_TypeDef * TIMx )

Get actual trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE

Definition at line 1779 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Indicate whether channel(s) is(are) enabled.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_IsEnabledChannel
CCER CC1NE LL_TIM_CC_IsEnabledChannel
CCER CC2E LL_TIM_CC_IsEnabledChannel
CCER CC2NE LL_TIM_CC_IsEnabledChannel
CCER CC3E LL_TIM_CC_IsEnabledChannel
CCER CC3NE LL_TIM_CC_IsEnabledChannel
CCER CC4E LL_TIM_CC_IsEnabledChannel
CCER CC5E LL_TIM_CC_IsEnabledChannel
CCER CC6E LL_TIM_CC_IsEnabledChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 1885 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMAReqTrigger
 | ) |  |

Set the trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
Parameters:
TIMx Timer instance
DMAReqTrigger This parameter can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE
Return values:
None

Definition at line 1766 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetLockLevel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | LockLevel
 | ) |  |

Set the lock level to freeze the configuration of several capture/compare parameters.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not the lock mechanism is supported by a timer instance.
Reference Manual to LL API cross reference:
BDTR LOCK LL_TIM_CC_SetLockLevel
Parameters:
TIMx Timer instance
LockLevel This parameter can be one of the following values:
  • LL_TIM_LOCKLEVEL_OFF
  • LL_TIM_LOCKLEVEL_1
  • LL_TIM_LOCKLEVEL_2
  • LL_TIM_LOCKLEVEL_3
Return values:
None

Definition at line 1798 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetUpdate | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CCUpdateSource
 | ) |  |

Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCUS LL_TIM_CC_SetUpdate
Parameters:
TIMx Timer instance
CCUpdateSource This parameter can be one of the following values:
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
Return values:
None

Definition at line 1752 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Output channel configuration

Functions
Output channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH5 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 5 (TIMx_CCR5).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH6 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 6 (TIMx_CCR6).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH5 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR5) set for output channel 5.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH6 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR6) set for output channel 6.
__STATIC_INLINE void | LL_TIM_SetCH5CombinedChannels (TIM_TypeDef *TIMx, uint32_t GroupCH5)
Select on which reference signal the OC5REF is combined to.

Function Documentation

__STATIC_INLINE void LL_TIM_OC_ConfigOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure an output channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_OC_ConfigOutput
CCMR1 CC2S LL_TIM_OC_ConfigOutput
CCMR2 CC3S LL_TIM_OC_ConfigOutput
CCMR2 CC4S LL_TIM_OC_ConfigOutput
CCMR3 CC5S LL_TIM_OC_ConfigOutput
CCMR3 CC6S LL_TIM_OC_ConfigOutput
CCER CC1P LL_TIM_OC_ConfigOutput
CCER CC2P LL_TIM_OC_ConfigOutput
CCER CC3P LL_TIM_OC_ConfigOutput
CCER CC4P LL_TIM_OC_ConfigOutput
CCER CC5P LL_TIM_OC_ConfigOutput
CCER CC6P LL_TIM_OC_ConfigOutput
CR2 OIS1 LL_TIM_OC_ConfigOutput
CR2 OIS2 LL_TIM_OC_ConfigOutput
CR2 OIS3 LL_TIM_OC_ConfigOutput
CR2 OIS4 LL_TIM_OC_ConfigOutput
CR2 OIS5 LL_TIM_OC_ConfigOutput
CR2 OIS6 LL_TIM_OC_ConfigOutput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_OCPOLARITY_HIGH or LL_TIM_OCPOLARITY_LOW
  • LL_TIM_OCIDLESTATE_LOW or LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 1930 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable clearing the output channel on an external event.

Note:
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_DisableClear
CCMR1 OC2CE LL_TIM_OC_DisableClear
CCMR2 OC3CE LL_TIM_OC_DisableClear
CCMR2 OC4CE LL_TIM_OC_DisableClear
CCMR3 OC5CE LL_TIM_OC_DisableClear
CCMR3 OC6CE LL_TIM_OC_DisableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2356 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable fast mode for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_DisableFast
CCMR1 OC2FE LL_TIM_OC_DisableFast
CCMR2 OC3FE LL_TIM_OC_DisableFast
CCMR2 OC4FE LL_TIM_OC_DisableFast
CCMR3 OC5FE LL_TIM_OC_DisableFast
CCMR3 OC6FE LL_TIM_OC_DisableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2198 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_DisablePreload
CCMR1 OC2PE LL_TIM_OC_DisablePreload
CCMR2 OC3PE LL_TIM_OC_DisablePreload
CCMR2 OC4PE LL_TIM_OC_DisablePreload
CCMR3 OC5PE LL_TIM_OC_DisablePreload
CCMR3 OC6PE LL_TIM_OC_DisablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2275 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable clearing the output channel on an external event.

Note:
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_EnableClear
CCMR1 OC2CE LL_TIM_OC_EnableClear
CCMR2 OC3CE LL_TIM_OC_EnableClear
CCMR2 OC4CE LL_TIM_OC_EnableClear
CCMR3 OC5CE LL_TIM_OC_EnableClear
CCMR3 OC6CE LL_TIM_OC_EnableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2329 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable fast mode for the output channel.

Note:
Acts only if the channel is configured in PWM1 or PWM2 mode.
Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_EnableFast
CCMR1 OC2FE LL_TIM_OC_EnableFast
CCMR2 OC3FE LL_TIM_OC_EnableFast
CCMR2 OC4FE LL_TIM_OC_EnableFast
CCMR3 OC5FE LL_TIM_OC_EnableFast
CCMR3 OC6FE LL_TIM_OC_EnableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2172 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_EnablePreload
CCMR1 OC2PE LL_TIM_OC_EnablePreload
CCMR2 OC3PE LL_TIM_OC_EnablePreload
CCMR2 OC4PE LL_TIM_OC_EnablePreload
CCMR3 OC5PE LL_TIM_OC_EnablePreload
CCMR3 OC6PE LL_TIM_OC_EnablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2250 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR1) set for output channel 1.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_GetCompareCH1
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2515 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR2) set for output channel 2.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_GetCompareCH2
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2531 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR3) set for output channel 3.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_GetCompareCH3
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2547 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR4) set for output channel 4.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_GetCompareCH4
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2563 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR5) set for output channel 5.

Note:
Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not output channel 5 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR5 CCR5 LL_TIM_OC_GetCompareCH5
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2576 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR6) set for output channel 6.

Note:
Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not output channel 6 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR6 CCR6 LL_TIM_OC_GetCompareCH6
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2589 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the IDLE state of an output channel.

Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS2 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS3 LL_TIM_OC_GetIdleState
CR2 OIS3N LL_TIM_OC_GetIdleState
CR2 OIS4 LL_TIM_OC_GetIdleState
CR2 OIS5 LL_TIM_OC_GetIdleState
CR2 OIS6 LL_TIM_OC_GetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH

Definition at line 2147 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the output compare mode of an output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_GetMode
CCMR1 OC2M LL_TIM_OC_GetMode
CCMR2 OC3M LL_TIM_OC_GetMode
CCMR2 OC4M LL_TIM_OC_GetMode
CCMR3 OC5M LL_TIM_OC_GetMode
CCMR3 OC6M LL_TIM_OC_GetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2

Definition at line 2012 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_GetPolarity
CCER CC1NP LL_TIM_OC_GetPolarity
CCER CC2P LL_TIM_OC_GetPolarity
CCER CC2NP LL_TIM_OC_GetPolarity
CCER CC3P LL_TIM_OC_GetPolarity
CCER CC3NP LL_TIM_OC_GetPolarity
CCER CC4P LL_TIM_OC_GetPolarity
CCER CC5P LL_TIM_OC_GetPolarity
CCER CC6P LL_TIM_OC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW

Definition at line 2078 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates clearing the output channel on an external event is enabled for the output channel.

Note:
This function enables clearing the output channel on an external event.
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_IsEnabledClear
CCMR1 OC2CE LL_TIM_OC_IsEnabledClear
CCMR2 OC3CE LL_TIM_OC_IsEnabledClear
CCMR2 OC4CE LL_TIM_OC_IsEnabledClear
CCMR3 OC5CE LL_TIM_OC_IsEnabledClear
CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2385 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether fast mode is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_IsEnabledFast
CCMR1 OC2FE LL_TIM_OC_IsEnabledFast
CCMR2 OC3FE LL_TIM_OC_IsEnabledFast
CCMR2 OC4FE LL_TIM_OC_IsEnabledFast
CCMR3 OC5FE LL_TIM_OC_IsEnabledFast
CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2224 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload
CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload
CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload
CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2300 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetCompareCH1 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 1 (TIMx_CCR1).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_SetCompareCH1
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2420 of file stm32l4xx_ll_tim.h.

Referenced by OC1Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 2 (TIMx_CCR2).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_SetCompareCH2
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2437 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and OC2Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH3 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 3 (TIMx_CCR3).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_SetCompareCH3
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2454 of file stm32l4xx_ll_tim.h.

Referenced by OC3Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH4 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 4 (TIMx_CCR4).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_SetCompareCH4
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2471 of file stm32l4xx_ll_tim.h.

Referenced by OC4Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH5 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 5 (TIMx_CCR5).

Note:
Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not output channel 5 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR5 CCR5 LL_TIM_OC_SetCompareCH5
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2485 of file stm32l4xx_ll_tim.h.

Referenced by OC5Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH6 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 6 (TIMx_CCR6).

Note:
Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not output channel 6 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR6 CCR6 LL_TIM_OC_SetCompareCH6
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2499 of file stm32l4xx_ll_tim.h.

Referenced by OC6Config().

__STATIC_INLINE void LL_TIM_OC_SetDeadTime | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DeadTime
 | ) |  |

Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not dead-time insertion feature is supported by a timer instance.
Helper macro __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
Reference Manual to LL API cross reference:
BDTR DTG LL_TIM_OC_SetDeadTime
Parameters:
TIMx | Timer instance
DeadTime | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 2403 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_OC_SetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | IdleState
 | ) |  |

Set the IDLE state of an output channel.

Note:
This function is significant only for the timer instances supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS2 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS3 LL_TIM_OC_SetIdleState
CR2 OIS3N LL_TIM_OC_SetIdleState
CR2 OIS4 LL_TIM_OC_SetIdleState
CR2 OIS5 LL_TIM_OC_SetIdleState
CR2 OIS6 LL_TIM_OC_SetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
IdleState This parameter can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 2115 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_SetMode
CCMR1 OC2M LL_TIM_OC_SetMode
CCMR2 OC3M LL_TIM_OC_SetMode
CCMR2 OC4M LL_TIM_OC_SetMode
CCMR3 OC5M LL_TIM_OC_SetMode
CCMR3 OC6M LL_TIM_OC_SetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Mode This parameter can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2
Return values:
None

Definition at line 1973 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_SetPolarity
CCER CC1NP LL_TIM_OC_SetPolarity
CCER CC2P LL_TIM_OC_SetPolarity
CCER CC2NP LL_TIM_OC_SetPolarity
CCER CC3P LL_TIM_OC_SetPolarity
CCER CC3NP LL_TIM_OC_SetPolarity
CCER CC4P LL_TIM_OC_SetPolarity
CCER CC5P LL_TIM_OC_SetPolarity
CCER CC6P LL_TIM_OC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Polarity This parameter can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW
Return values:
None

Definition at line 2046 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | GroupCH5
 | ) |  |

Select on which reference signal the OC5REF is combined to.

Note:
Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the combined 3-phase PWM mode.
Reference Manual to LL API cross reference:
CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels
CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels
CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
Parameters:
TIMx Timer instance
GroupCH5 This parameter can be one of the following values:
  • LL_TIM_GROUPCH5_NONE
  • LL_TIM_GROUPCH5_OC1REFC
  • LL_TIM_GROUPCH5_OC2REFC
  • LL_TIM_GROUPCH5_OC3REFC
Return values:
None

Definition at line 2609 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input channel configuration

Functions
Input channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx)
Get captured value for input channel 4.

Function Documentation

__STATIC_INLINE void LL_TIM_IC_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure input channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_Config
CCMR1 IC1PSC LL_TIM_IC_Config
CCMR1 IC1F LL_TIM_IC_Config
CCMR1 CC2S LL_TIM_IC_Config
CCMR1 IC2PSC LL_TIM_IC_Config
CCMR1 IC2F LL_TIM_IC_Config
CCMR2 CC3S LL_TIM_IC_Config
CCMR2 IC3PSC LL_TIM_IC_Config
CCMR2 IC3F LL_TIM_IC_Config
CCMR2 CC4S LL_TIM_IC_Config
CCMR2 IC4PSC LL_TIM_IC_Config
CCMR2 IC4F LL_TIM_IC_Config
CCER CC1P LL_TIM_IC_Config
CCER CC1NP LL_TIM_IC_Config
CCER CC2P LL_TIM_IC_Config
CCER CC2NP LL_TIM_IC_Config
CCER CC3P LL_TIM_IC_Config
CCER CC3NP LL_TIM_IC_Config
CCER CC4P LL_TIM_IC_Config
CCER CC4NP LL_TIM_IC_Config
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI or LL_TIM_ACTIVEINPUT_INDIRECTTI or LL_TIM_ACTIVEINPUT_TRC
  • LL_TIM_ICPSC_DIV1 or ... or LL_TIM_ICPSC_DIV8
  • LL_TIM_IC_FILTER_FDIV1 or ... or LL_TIM_IC_FILTER_FDIV32_N8
  • LL_TIM_IC_POLARITY_RISING or LL_TIM_IC_POLARITY_FALLING or LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 2656 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_DisableXORCombination ( TIM_TypeDef * TIMx )

Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_DisableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2915 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_EnableXORCombination ( TIM_TypeDef * TIMx )

Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_EnableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2902 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_GetActiveInput
CCMR1 CC2S LL_TIM_IC_GetActiveInput
CCMR2 CC3S LL_TIM_IC_GetActiveInput
CCMR2 CC4S LL_TIM_IC_GetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC

Definition at line 2706 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1 ( TIM_TypeDef * TIMx )

Get captured value for input channel 1.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not input channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2944 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2 ( TIM_TypeDef * TIMx )

Get captured value for input channel 2.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not input channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2960 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3 ( TIM_TypeDef * TIMx )

Get captured value for input channel 3.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not input channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2976 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4 ( TIM_TypeDef * TIMx )

Get captured value for input channel 4.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not input channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2992 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_GetFilter
CCMR1 IC2F LL_TIM_IC_GetFilter
CCMR2 IC3F LL_TIM_IC_GetFilter
CCMR2 IC4F LL_TIM_IC_GetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8

Definition at line 2832 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_GetPolarity
CCER CC1NP LL_TIM_IC_GetPolarity
CCER CC2P LL_TIM_IC_GetPolarity
CCER CC2NP LL_TIM_IC_GetPolarity
CCER CC3P LL_TIM_IC_GetPolarity
CCER CC3NP LL_TIM_IC_GetPolarity
CCER CC4P LL_TIM_IC_GetPolarity
CCER CC4NP LL_TIM_IC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE

Definition at line 2888 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current prescaler value acting on an input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_GetPrescaler
CCMR1 IC2PSC LL_TIM_IC_GetPrescaler
CCMR2 IC3PSC LL_TIM_IC_GetPrescaler
CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8

Definition at line 2757 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination ( TIM_TypeDef * TIMx )

Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2928 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_SetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICActiveInput
 | ) |  |

Set the active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_SetActiveInput
CCMR1 CC2S LL_TIM_IC_SetActiveInput
CCMR2 CC3S LL_TIM_IC_SetActiveInput
CCMR2 CC4S LL_TIM_IC_SetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICActiveInput This parameter can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC
Return values:
None

Definition at line 2682 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICFilter
 | ) |  |

Set the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_SetFilter
CCMR1 IC2F LL_TIM_IC_SetFilter
CCMR2 IC3F LL_TIM_IC_SetFilter
CCMR2 IC4F LL_TIM_IC_SetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICFilter This parameter can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8
Return values:
None

Definition at line 2795 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPolarity
 | ) |  |

Set the input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_SetPolarity
CCER CC1NP LL_TIM_IC_SetPolarity
CCER CC2P LL_TIM_IC_SetPolarity
CCER CC2NP LL_TIM_IC_SetPolarity
CCER CC3P LL_TIM_IC_SetPolarity
CCER CC3NP LL_TIM_IC_SetPolarity
CCER CC4P LL_TIM_IC_SetPolarity
CCER CC4NP LL_TIM_IC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPolarity This parameter can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 2861 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPrescaler
 | ) |  |

Set the prescaler of input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_SetPrescaler
CCMR1 IC2PSC LL_TIM_IC_SetPrescaler
CCMR2 IC3PSC LL_TIM_IC_SetPrescaler
CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPrescaler This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
None

Definition at line 2732 of file stm32l4xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Counter clock selection

Functions
Counter clock selection
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableExternalClock ( TIM_TypeDef * TIMx )

Disable external clock mode 2.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_DisableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3026 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableExternalClock ( TIM_TypeDef * TIMx )

Enable external clock mode 2.

Note:
When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_EnableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3013 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock ( TIM_TypeDef * TIMx )

Indicate whether external clock mode 2 is enabled.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_IsEnabledExternalClock
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3039 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetClockSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the clock source of the counter clock.

Note:
when selected clock source is external clock mode 1, the timer input the external clock is applied is selected by calling the LL_TIM_SetTriggerInput() function. This timer input must be configured by calling the LL_TIM_IC_Config() function.
Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode1.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetClockSource
SMCR ECE LL_TIM_SetClockSource
Parameters:
TIMx Timer instance
ClockSource This parameter can be one of the following values:
  • LL_TIM_CLOCKSOURCE_INTERNAL
  • LL_TIM_CLOCKSOURCE_EXT_MODE1
  • LL_TIM_CLOCKSOURCE_EXT_MODE2
Return values:
None

Definition at line 3063 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetEncoderMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Set the encoder interface mode.

Note:
Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the encoder mode.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetEncoderMode
Parameters:
TIMx Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_TIM_ENCODERMODE_X2_TI1
  • LL_TIM_ENCODERMODE_X2_TI2
  • LL_TIM_ENCODERMODE_X4_TI12
Return values:
None

Definition at line 3080 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Timer synchronisation configuration

Functions
Timer synchronisation configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetTriggerOutput2 (TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
Set the trigger output 2 (TRGO2) used for ADC synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_SetETRSource (TIM_TypeDef *TIMx, uint32_t ETRSource)
Select the external trigger (ETR) input source.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigETR | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRPolarity,
 |  | uint32_t | ETRPrescaler,
 |  | uint32_t | ETRFilter
 | ) |  |

Configure the external trigger (ETR) input.

Note:
Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an external trigger input.
Reference Manual to LL API cross reference:
SMCR ETP LL_TIM_ConfigETR
SMCR ETPS LL_TIM_ConfigETR
SMCR ETF LL_TIM_ConfigETR
Parameters:
TIMx Timer instance
ETRPolarity This parameter can be one of the following values:
  • LL_TIM_ETR_POLARITY_NONINVERTED
  • LL_TIM_ETR_POLARITY_INVERTED
ETRPrescaler This parameter can be one of the following values:
  • LL_TIM_ETR_PRESCALER_DIV1
  • LL_TIM_ETR_PRESCALER_DIV2
  • LL_TIM_ETR_PRESCALER_DIV4
  • LL_TIM_ETR_PRESCALER_DIV8
ETRFilter This parameter can be one of the following values:
  • LL_TIM_ETR_FILTER_FDIV1
  • LL_TIM_ETR_FILTER_FDIV1_N2
  • LL_TIM_ETR_FILTER_FDIV1_N4
  • LL_TIM_ETR_FILTER_FDIV1_N8
  • LL_TIM_ETR_FILTER_FDIV2_N6
  • LL_TIM_ETR_FILTER_FDIV2_N8
  • LL_TIM_ETR_FILTER_FDIV4_N6
  • LL_TIM_ETR_FILTER_FDIV4_N8
  • LL_TIM_ETR_FILTER_FDIV8_N6
  • LL_TIM_ETR_FILTER_FDIV8_N8
  • LL_TIM_ETR_FILTER_FDIV16_N5
  • LL_TIM_ETR_FILTER_FDIV16_N6
  • LL_TIM_ETR_FILTER_FDIV16_N8
  • LL_TIM_ETR_FILTER_FDIV32_N5
  • LL_TIM_ETR_FILTER_FDIV32_N6
  • LL_TIM_ETR_FILTER_FDIV32_N8
Return values:
None

Definition at line 3259 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode ( TIM_TypeDef * TIMx )

Disable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_DisableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3206 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode ( TIM_TypeDef * TIMx )

Enable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_EnableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3193 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode ( TIM_TypeDef * TIMx )

Indicates whether the Master/Slave mode is enabled.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3219 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetETRSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRSource
 | ) |  |

Select the external trigger (ETR) input source.

Note:
Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or not a timer instance supports ETR source selection.
Reference Manual to LL API cross reference:
OR2 ETRSEL LL_TIM_SetETRSource
Parameters:
TIMx Timer instance
ETRSource This parameter can be one of the following values:
  • LL_TIM_ETRSOURCE_LEGACY
  • LL_TIM_ETRSOURCE_COMP1
  • LL_TIM_ETRSOURCE_COMP2
Return values:
None

Definition at line 3276 of file stm32l4xx_ll_tim.h.

References TIMx_OR2_ETRSEL.

__STATIC_INLINE void LL_TIM_SetSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | SlaveMode
 | ) |  |

Set the synchronization mode of a slave timer.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetSlaveMode
Parameters:
TIMx Timer instance
SlaveMode This parameter can be one of the following values:
  • LL_TIM_SLAVEMODE_DISABLED
  • LL_TIM_SLAVEMODE_RESET
  • LL_TIM_SLAVEMODE_GATED
  • LL_TIM_SLAVEMODE_TRIGGER
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
Return values:
None

Definition at line 3158 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TriggerInput
 | ) |  |

Set the selects the trigger input to be used to synchronize the counter.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR TS LL_TIM_SetTriggerInput
Parameters:
TIMx Timer instance
TriggerInput This parameter can be one of the following values:
  • LL_TIM_TS_ITR0
  • LL_TIM_TS_ITR1
  • LL_TIM_TS_ITR2
  • LL_TIM_TS_ITR3
  • LL_TIM_TS_TI1F_ED
  • LL_TIM_TS_TI1FP1
  • LL_TIM_TS_TI2FP2
  • LL_TIM_TS_ETRF
Return values:
None

Definition at line 3180 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TimerSynchronization
 | ) |  |

Set the trigger output (TRGO) used for timer synchronization .

Note:
Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a master timer.
Reference Manual to LL API cross reference:
CR2 MMS LL_TIM_SetTriggerOutput
Parameters:
TIMx Timer instance
TimerSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO_RESET
  • LL_TIM_TRGO_ENABLE
  • LL_TIM_TRGO_UPDATE
  • LL_TIM_TRGO_CC1IF
  • LL_TIM_TRGO_OC1REF
  • LL_TIM_TRGO_OC2REF
  • LL_TIM_TRGO_OC3REF
  • LL_TIM_TRGO_OC4REF
Return values:
None

Definition at line 3109 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ADCSynchronization
 | ) |  |

Set the trigger output 2 (TRGO2) used for ADC synchronization .

Note:
Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check whether or not a timer instance can be used for ADC synchronization.
Reference Manual to LL API cross reference:
CR2 MMS2 LL_TIM_SetTriggerOutput2
Parameters:
TIMx Timer Instance
ADCSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO2_RESET
  • LL_TIM_TRGO2_ENABLE
  • LL_TIM_TRGO2_UPDATE
  • LL_TIM_TRGO2_CC1F
  • LL_TIM_TRGO2_OC1
  • LL_TIM_TRGO2_OC2
  • LL_TIM_TRGO2_OC3
  • LL_TIM_TRGO2_OC4
  • LL_TIM_TRGO2_OC5
  • LL_TIM_TRGO2_OC6
  • LL_TIM_TRGO2_OC4_RISINGFALLING
  • LL_TIM_TRGO2_OC6_RISINGFALLING
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
Return values:
None

Definition at line 3139 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Break function configuration

Functions
Break function configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
Configure the break input.
__STATIC_INLINE void | LL_TIM_EnableBRK2 (TIM_TypeDef *TIMx)
Enable the break 2 function.
__STATIC_INLINE void | LL_TIM_DisableBRK2 (TIM_TypeDef *TIMx)
Disable the break 2 function.
__STATIC_INLINE void | LL_TIM_ConfigBRK2 (TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
Configure the break 2 input.
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_EnableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Enable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_DisableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Disable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_SetBreakInputSourcePolarity (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
Set the polarity of the break signal for the timer break input.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigBRK | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakPolarity,
 |  | uint32_t | BreakFilter
 | ) |  |

Configure the break input.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKP LL_TIM_ConfigBRK
BDTR BKF LL_TIM_ConfigBRK
Parameters:
TIMx Timer instance
BreakPolarity This parameter can be one of the following values:
  • LL_TIM_BREAK_POLARITY_LOW
  • LL_TIM_BREAK_POLARITY_HIGH
BreakFilter This parameter can be one of the following values:
  • LL_TIM_BREAK_FILTER_FDIV1
  • LL_TIM_BREAK_FILTER_FDIV1_N2
  • LL_TIM_BREAK_FILTER_FDIV1_N4
  • LL_TIM_BREAK_FILTER_FDIV1_N8
  • LL_TIM_BREAK_FILTER_FDIV2_N6
  • LL_TIM_BREAK_FILTER_FDIV2_N8
  • LL_TIM_BREAK_FILTER_FDIV4_N6
  • LL_TIM_BREAK_FILTER_FDIV4_N8
  • LL_TIM_BREAK_FILTER_FDIV8_N6
  • LL_TIM_BREAK_FILTER_FDIV8_N8
  • LL_TIM_BREAK_FILTER_FDIV16_N5
  • LL_TIM_BREAK_FILTER_FDIV16_N6
  • LL_TIM_BREAK_FILTER_FDIV16_N8
  • LL_TIM_BREAK_FILTER_FDIV32_N5
  • LL_TIM_BREAK_FILTER_FDIV32_N6
  • LL_TIM_BREAK_FILTER_FDIV32_N8
Return values:
None

Definition at line 3344 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ConfigBRK2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Break2Polarity,
 |  | uint32_t | Break2Filter
 | ) |  |

Configure the break 2 input.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2P LL_TIM_ConfigBRK2
BDTR BK2F LL_TIM_ConfigBRK2
Parameters:
TIMx Timer instance
Break2Polarity This parameter can be one of the following values:
  • LL_TIM_BREAK2_POLARITY_LOW
  • LL_TIM_BREAK2_POLARITY_HIGH
Break2Filter This parameter can be one of the following values:
  • LL_TIM_BREAK2_FILTER_FDIV1
  • LL_TIM_BREAK2_FILTER_FDIV1_N2
  • LL_TIM_BREAK2_FILTER_FDIV1_N4
  • LL_TIM_BREAK2_FILTER_FDIV1_N8
  • LL_TIM_BREAK2_FILTER_FDIV2_N6
  • LL_TIM_BREAK2_FILTER_FDIV2_N8
  • LL_TIM_BREAK2_FILTER_FDIV4_N6
  • LL_TIM_BREAK2_FILTER_FDIV4_N8
  • LL_TIM_BREAK2_FILTER_FDIV8_N6
  • LL_TIM_BREAK2_FILTER_FDIV8_N8
  • LL_TIM_BREAK2_FILTER_FDIV16_N5
  • LL_TIM_BREAK2_FILTER_FDIV16_N6
  • LL_TIM_BREAK2_FILTER_FDIV16_N8
  • LL_TIM_BREAK2_FILTER_FDIV32_N5
  • LL_TIM_BREAK2_FILTER_FDIV32_N6
  • LL_TIM_BREAK2_FILTER_FDIV32_N8
Return values:
None

Definition at line 3404 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAllOutputs ( TIM_TypeDef * TIMx )

Disable the outputs (reset the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_DisableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3493 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAutomaticOutput ( TIM_TypeDef * TIMx )

Disable automatic output (MOE can be set only by software).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_DisableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3450 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBreakInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source
 | ) |  |

Disable the signals connected to the designated timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
OR2 BKINE LL_TIM_DisableBreakInputSource
OR2 BKCMP1E LL_TIM_DisableBreakInputSource
OR2 BKCMP2E LL_TIM_DisableBreakInputSource
OR2 BKDFBK0E LL_TIM_DisableBreakInputSource
OR3 BKINE LL_TIM_DisableBreakInputSource
OR3 BKCMP1E LL_TIM_DisableBreakInputSource
OR3 BKCMP2E LL_TIM_DisableBreakInputSource
OR3 BKDFBK0E LL_TIM_DisableBreakInputSource
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
  • LL_TIM_BKIN_SOURCE_DF1BK
Return values:
None

Definition at line 3563 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK ( TIM_TypeDef * TIMx )

Disable the break function.

Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_DisableBRK
Parameters:
TIMx Timer instance
Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Return values:
None

Definition at line 3310 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK2 ( TIM_TypeDef * TIMx )

Disable the break 2 function.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2E LL_TIM_DisableBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3370 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAllOutputs ( TIM_TypeDef * TIMx )

Enable the outputs (set the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_EnableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3478 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAutomaticOutput ( TIM_TypeDef * TIMx )

Enable automatic output (MOE can be set by software or automatically when a break input is active).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_EnableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3437 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBreakInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source
 | ) |  |

Enable the signals connected to the designated timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
OR2 BKINE LL_TIM_EnableBreakInputSource
OR2 BKCMP1E LL_TIM_EnableBreakInputSource
OR2 BKCMP2E LL_TIM_EnableBreakInputSource
OR2 BKDFBK0E LL_TIM_EnableBreakInputSource
OR3 BKINE LL_TIM_EnableBreakInputSource
OR3 BKCMP1E LL_TIM_EnableBreakInputSource
OR3 BKCMP2E LL_TIM_EnableBreakInputSource
OR3 BKDFBK0E LL_TIM_EnableBreakInputSource
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
  • LL_TIM_BKIN_SOURCE_DF1BK
Return values:
None

Definition at line 3534 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK ( TIM_TypeDef * TIMx )

Enable the break function.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_EnableBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3297 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK2 ( TIM_TypeDef * TIMx )

Enable the break 2 function.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2E LL_TIM_EnableBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3357 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs ( TIM_TypeDef * TIMx )

Indicates whether outputs are enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_IsEnabledAllOutputs
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3506 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput ( TIM_TypeDef * TIMx )

Indicate whether automatic output is enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_IsEnabledAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3463 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the break signal for the timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
OR2 BKINE LL_TIM_SetBreakInputSourcePolarity
OR2 BKCMP1E LL_TIM_SetBreakInputSourcePolarity
OR2 BKCMP2E LL_TIM_SetBreakInputSourcePolarity
OR2 BKINP LL_TIM_SetBreakInputSourcePolarity
OR3 BKINE LL_TIM_SetBreakInputSourcePolarity
OR3 BKCMP1E LL_TIM_SetBreakInputSourcePolarity
OR3 BKCMP2E LL_TIM_SetBreakInputSourcePolarity
OR3 BKINP LL_TIM_SetBreakInputSourcePolarity
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1
  • LL_TIM_BKIN_SOURCE_BKCOMP2
Polarity This parameter can be one of the following values:
  • LL_TIM_BKIN_POLARITY_LOW
  • LL_TIM_BKIN_POLARITY_HIGH
Return values:
None

Definition at line 3594 of file stm32l4xx_ll_tim.h.

References TIMx_OR2_BKINP.

__STATIC_INLINE void LL_TIM_SetOffStates | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OffStateIdle,
 |  | uint32_t | OffStateRun
 | ) |  |

Select the outputs off state (enabled v.s.

disabled) in Idle and Run modes.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR OSSI LL_TIM_SetOffStates
BDTR OSSR LL_TIM_SetOffStates
Parameters:
TIMx Timer instance
OffStateIdle This parameter can be one of the following values:
  • LL_TIM_OSSI_DISABLE
  • LL_TIM_OSSI_ENABLE
OffStateRun This parameter can be one of the following values:
  • LL_TIM_OSSR_DISABLE
  • LL_TIM_OSSR_ENABLE
Return values:
None

Definition at line 3424 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA burst mode configuration

Functions
DMA burst mode configuration
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigDMABurst | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMABurstBaseAddress,
 |  | uint32_t | DMABurstLength
 | ) |  |

Configures the timer DMA burst feature.

Note:
Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the DMA burst mode.
Reference Manual to LL API cross reference:
DCR DBL LL_TIM_ConfigDMABurst
DCR DBA LL_TIM_ConfigDMABurst
Parameters:
TIMx Timer instance
DMABurstBaseAddress This parameter can be one of the following values:
  • LL_TIM_DMABURST_BASEADDR_CR1
  • LL_TIM_DMABURST_BASEADDR_CR2
  • LL_TIM_DMABURST_BASEADDR_SMCR
  • LL_TIM_DMABURST_BASEADDR_DIER
  • LL_TIM_DMABURST_BASEADDR_SR
  • LL_TIM_DMABURST_BASEADDR_EGR
  • LL_TIM_DMABURST_BASEADDR_CCMR1
  • LL_TIM_DMABURST_BASEADDR_CCMR2
  • LL_TIM_DMABURST_BASEADDR_CCER
  • LL_TIM_DMABURST_BASEADDR_CNT
  • LL_TIM_DMABURST_BASEADDR_PSC
  • LL_TIM_DMABURST_BASEADDR_ARR
  • LL_TIM_DMABURST_BASEADDR_RCR
  • LL_TIM_DMABURST_BASEADDR_CCR1
  • LL_TIM_DMABURST_BASEADDR_CCR2
  • LL_TIM_DMABURST_BASEADDR_CCR3
  • LL_TIM_DMABURST_BASEADDR_CCR4
  • LL_TIM_DMABURST_BASEADDR_BDTR
  • LL_TIM_DMABURST_BASEADDR_CCMR3
  • LL_TIM_DMABURST_BASEADDR_CCR5
  • LL_TIM_DMABURST_BASEADDR_CCR6
  • LL_TIM_DMABURST_BASEADDR_OR1
  • LL_TIM_DMABURST_BASEADDR_OR2
  • LL_TIM_DMABURST_BASEADDR_OR3
DMABurstLength This parameter can be one of the following values:
  • LL_TIM_DMABURST_LENGTH_1TRANSFER
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS
Return values:
None

Definition at line 3660 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Timer input remapping

Functions
Timer input remapping
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).

Function Documentation

__STATIC_INLINE void LL_TIM_SetRemap | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Remap
 | ) |  |

Remap TIM inputs (input channel, internal/external triggers).

Note:
Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not a some timer inputs can be remapped.
Reference Manual to LL API cross reference:
TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap
TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap
TIM1_OR1 TI1_RMP LL_TIM_SetRemap
TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap
TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap
TIM8_OR1 TI1_RMP LL_TIM_SetRemap
TIM2_OR1 ITR1_RMP LL_TIM_SetRemap
TIM2_OR1 TI4_RMP LL_TIM_SetRemap
TIM2_OR1 TI1_RMP LL_TIM_SetRemap
TIM3_OR1 TI1_RMP LL_TIM_SetRemap
TIM15_OR1 TI1_RMP LL_TIM_SetRemap
TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap
TIM16_OR1 TI1_RMP LL_TIM_SetRemap
TIM17_OR1 TI1_RMP LL_TIM_SetRemap
Parameters:
TIMx | Timer instance
Remap | Remap param depends on the TIMx. Description available only in CHM version of the User Manual (not in .pdf). Otherwise see Reference Manual description of OR registers.

Below description summarizes "Timer Instance" and "Remap" param combinations:

TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where

. . ADC1_RMP can be one of the following values

  • LL_TIM_TIM1_ETR_ADC1_RMP_NC
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD3

. . ADC3_RMP can be one of the following values

  • LL_TIM_TIM1_ETR_ADC3_RMP_NC
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD3

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM1_TI1_RMP_GPIO
  • LL_TIM_TIM1_TI1_RMP_COMP1

TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where

ITR1_RMP can be one of the following values

  • LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
  • LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF

. . ETR1_RMP can be one of the following values

  • LL_TIM_TIM2_ETR_RMP_GPIO
  • LL_TIM_TIM2_ETR_RMP_LSE

. . TI4_RMP can be one of the following values

  • LL_TIM_TIM2_TI4_RMP_GPIO
  • LL_TIM_TIM2_TI4_RMP_COMP1
  • LL_TIM_TIM2_TI4_RMP_COMP2
  • LL_TIM_TIM2_TI4_RMP_COMP1_COMP2

TIM3: one of the following values

  • LL_TIM_TIM3_TI1_RMP_GPIO
  • LL_TIM_TIM3_TI1_RMP_COMP1
  • LL_TIM_TIM3_TI1_RMP_COMP2
  • LL_TIM_TIM3_TI1_RMP_COMP1_COMP2

TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where

. . ADC1_RMP can be one of the following values

  • LL_TIM_TIM8_ETR_ADC2_RMP_NC
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD3

. . ADC3_RMP can be one of the following values

  • LL_TIM_TIM8_ETR_ADC3_RMP_NC
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD3

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM8_TI1_RMP_GPIO
  • LL_TIM_TIM8_TI1_RMP_COMP2

TIM15: any combination of TI1_RMP, ENCODER_MODE where

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM15_TI1_RMP_GPIO
  • LL_TIM_TIM15_TI1_RMP_LSE

. . ENCODER_MODE can be one of the following values

  • LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
  • LL_TIM_TIM15_ENCODERMODE_TIM2
  • LL_TIM_TIM15_ENCODERMODE_TIM3
  • LL_TIM_TIM15_ENCODERMODE_TIM4

TIM16: one of the following values

  • LL_TIM_TIM16_TI1_RMP_GPIO
  • LL_TIM_TIM16_TI1_RMP_LSI
  • LL_TIM_TIM16_TI1_RMP_LSE
  • LL_TIM_TIM16_TI1_RMP_RTC
  • LL_TIM_TIM16_TI1_RMP_MSI (*)
  • LL_TIM_TIM16_TI1_RMP_HSE_32 (*)
  • LL_TIM_TIM16_TI1_RMP_MCO (*)

TIM17: one of the following values

  • LL_TIM_TIM17_TI1_RMP_GPIO
  • LL_TIM_TIM17_TI1_RMP_MSI
  • LL_TIM_TIM17_TI1_RMP_HSE_32
  • LL_TIM_TIM17_TI1_RMP_MCO

(*) Value not defined in all devices.

Return values:
None

Definition at line 3788 of file stm32l4xx_ll_tim.h.

References TIMx_OR1_RMP_MASK, and TIMx_OR1_RMP_SHIFT.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OCREF_Clear_Management

Functions
OCREF_Clear_Management
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource (TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
Set the OCREF clear source.

Function Documentation

__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OCRefClearInputSource
 | ) |  |

Set the OCREF clear source.

Note:
The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
This function can only be used in Output compare and PWM modes.
Reference Manual to LL API cross reference:
SMCR OCCS LL_TIM_SetOCRefClearInputSource
Parameters:
TIMx Timer instance
OCRefClearInputSource This parameter can be one of the following values:
  • LL_TIM_OCREF_CLR_INT_NC
  • LL_TIM_OCREF_CLR_INT_ETR
Return values:
None

Definition at line 3813 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG-Management

Functions
FLAG-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC5 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 5 interrupt flag (CC5F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC5 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC6 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 6 interrupt flag (CC6F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC6 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK2 (TIM_TypeDef *TIMx)
Clear the break 2 interrupt flag (B2IF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK2 (TIM_TypeDef *TIMx)
Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_SYSBRK (TIM_TypeDef *TIMx)
Clear the system break interrupt flag (SBIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_SYSBRK (TIM_TypeDef *TIMx)
Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).

Function Documentation

__STATIC_INLINE void LL_TIM_ClearFlag_BRK ( TIM_TypeDef * TIMx )

Clear the break interrupt flag (BIF).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_ClearFlag_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4029 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_BRK2 ( TIM_TypeDef * TIMx )

Clear the break 2 interrupt flag (B2IF).

Reference Manual to LL API cross reference:
SR B2IF LL_TIM_ClearFlag_BRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4051 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 interrupt flag (CC1F).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_ClearFlag_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3853 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_ClearFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4073 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 interrupt flag (CC2F).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_ClearFlag_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3875 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_ClearFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4095 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 interrupt flag (CC3F).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_ClearFlag_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3897 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_ClearFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4117 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 interrupt flag (CC4F).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_ClearFlag_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3919 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_ClearFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4139 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC5 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 5 interrupt flag (CC5F).

Reference Manual to LL API cross reference:
SR CC5IF LL_TIM_ClearFlag_CC5
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3941 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC6 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 6 interrupt flag (CC6F).

Reference Manual to LL API cross reference:
SR CC6IF LL_TIM_ClearFlag_CC6
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3963 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_COM ( TIM_TypeDef * TIMx )

Clear the commutation interrupt flag (COMIF).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_ClearFlag_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3985 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK ( TIM_TypeDef * TIMx )

Clear the system break interrupt flag (SBIF).

Reference Manual to LL API cross reference:
SR SBIF LL_TIM_ClearFlag_SYSBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4161 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_TRIG ( TIM_TypeDef * TIMx )

Clear the trigger interrupt flag (TIF).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_ClearFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4007 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE ( TIM_TypeDef * TIMx )

Clear the update interrupt flag (UIF).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_ClearFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3831 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK ( TIM_TypeDef * TIMx )

Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_IsActiveFlag_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4040 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2 ( TIM_TypeDef * TIMx )

Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR B2IF LL_TIM_IsActiveFlag_BRK2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4062 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_IsActiveFlag_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3864 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4084 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_IsActiveFlag_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3886 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4106 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_IsActiveFlag_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3908 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4128 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_IsActiveFlag_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3930 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4150 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC5IF LL_TIM_IsActiveFlag_CC5
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3952 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC6IF LL_TIM_IsActiveFlag_CC6
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3974 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM ( TIM_TypeDef * TIMx )

Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_IsActiveFlag_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3996 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK ( TIM_TypeDef * TIMx )

Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).

Reference Manual to LL API cross reference:
SR SBIF LL_TIM_IsActiveFlag_SYSBRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4172 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG ( TIM_TypeDef * TIMx )

Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_IsActiveFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4018 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE ( TIM_TypeDef * TIMx )

Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_IsActiveFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3842 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT-Management

Functions
IT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableIT_BRK ( TIM_TypeDef * TIMx )

Disable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_DisableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4432 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_DisableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4234 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_DisableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4267 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_DisableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4300 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_DisableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4333 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_COM ( TIM_TypeDef * TIMx )

Disable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_DisableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4366 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_DisableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4399 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_UPDATE ( TIM_TypeDef * TIMx )

Disable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_DisableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4201 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_BRK ( TIM_TypeDef * TIMx )

Enable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_EnableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4421 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_EnableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4223 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_EnableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4256 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_EnableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4289 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_EnableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4322 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_COM ( TIM_TypeDef * TIMx )

Enable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_EnableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4355 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_EnableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4388 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_UPDATE ( TIM_TypeDef * TIMx )

Enable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_EnableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4190 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK ( TIM_TypeDef * TIMx )

Indicates whether the break interrupt (BIE) is enabled.

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_IsEnabledIT_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4443 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_IsEnabledIT_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4245 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_IsEnabledIT_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4278 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_IsEnabledIT_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4311 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_IsEnabledIT_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4344 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM ( TIM_TypeDef * TIMx )

Indicates whether the commutation interrupt (COMIE) is enabled.

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_IsEnabledIT_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4377 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG ( TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TIE) is enabled.

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_IsEnabledIT_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4410 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE ( TIM_TypeDef * TIMx )

Indicates whether the update interrupt (UIE) is enabled.

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_IsEnabledIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4212 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA-Management

Functions
DMA-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_DisableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4505 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_DisableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4538 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_DisableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4571 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_DisableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4604 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_COM ( TIM_TypeDef * TIMx )

Disable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_DisableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4637 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_DisableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4670 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Disable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_DisableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4472 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_EnableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4494 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_EnableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4527 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_EnableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4560 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_EnableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4593 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_COM ( TIM_TypeDef * TIMx )

Enable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_EnableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4626 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_EnableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4659 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Enable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_EnableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4461 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4516 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4549 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4582 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4615 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM ( TIM_TypeDef * TIMx )

Indicates whether the commutation DMA request (COMDE) is enabled.

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_IsEnabledDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4648 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG ( TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TDE) is enabled.

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4681 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Indicates whether the update DMA request (UDE) is enabled.

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4483 of file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: EVENT-Management

Functions
EVENT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK2 (TIM_TypeDef *TIMx)
Generate break 2 event.

Function Documentation

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK ( TIM_TypeDef * TIMx )

Generate break event.

Reference Manual to LL API cross reference:
EGR BG LL_TIM_GenerateEvent_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4776 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2 ( TIM_TypeDef * TIMx )

Generate break 2 event.

Reference Manual to LL API cross reference:
EGR B2G LL_TIM_GenerateEvent_BRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4787 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC1 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 1 event.

Reference Manual to LL API cross reference:
EGR CC1G LL_TIM_GenerateEvent_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4710 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC2 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 2 event.

Reference Manual to LL API cross reference:
EGR CC2G LL_TIM_GenerateEvent_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4721 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC3 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 3 event.

Reference Manual to LL API cross reference:
EGR CC3G LL_TIM_GenerateEvent_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4732 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC4 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 4 event.

Reference Manual to LL API cross reference:
EGR CC4G LL_TIM_GenerateEvent_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4743 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_COM ( TIM_TypeDef * TIMx )

Generate commutation event.

Reference Manual to LL API cross reference:
EGR COMG LL_TIM_GenerateEvent_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4754 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG ( TIM_TypeDef * TIMx )

Generate trigger event.

Reference Manual to LL API cross reference:
EGR TG LL_TIM_GenerateEvent_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4765 of file stm32l4xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE ( TIM_TypeDef * TIMx )

Generate an update event.

Reference Manual to LL API cross reference:
EGR UG LL_TIM_GenerateEvent_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4699 of file stm32l4xx_ll_tim.h.

Referenced by LL_TIM_Init().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
TIM Exported Functions

Functions

ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.

Function Documentation

ErrorStatus LL_TIM_DeInit ( TIM_TypeDef * TIMx )

Set TIMx registers to their reset values.

Parameters:
TIMx Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: invalid TIMx instance

Definition at line 175 of file stm32l4xx_ll_tim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_TIM2, LL_APB1_GRP1_PERIPH_TIM3, LL_APB1_GRP1_PERIPH_TIM4, LL_APB1_GRP1_PERIPH_TIM5, LL_APB1_GRP1_PERIPH_TIM6, LL_APB1_GRP1_PERIPH_TIM7, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_TIM1, LL_APB2_GRP1_PERIPH_TIM15, LL_APB2_GRP1_PERIPH_TIM16, LL_APB2_GRP1_PERIPH_TIM17, LL_APB2_GRP1_PERIPH_TIM8, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_TIM_ENCODER_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_ENCODER_InitTypeDef * | TIM_EncoderInitStruct
 | ) |  |

Configure the encoder interface of the timer instance.

Parameters:
TIMx | Timer Instance
TIM_EncoderInitStruct | pointer to a LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 473 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_ENCODERMODE, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ReadReg, LL_TIM_SetEncoderMode(), and LL_TIM_WriteReg.

void LL_TIM_ENCODER_StructInit ( LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct )

Fills each TIM_EncoderInitStruct field with its default value.

Parameters:
TIM_EncoderInitStruct pointer to a LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
Return values:
None

Definition at line 451 of file stm32l4xx_ll_tim.c.

References LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_ENCODERMODE_X2_TI1, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_HALLSENSOR_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_HALLSENSOR_InitTypeDef * | TIM_HallSensorInitStruct
 | ) |  |

Configure the Hall sensor interface of the timer instance.

Note:
TIMx CH1, CH2 and CH3 inputs connected through a XOR to the TI1 input channel
TIMx slave mode controller is configured in reset mode. Selected internal trigger is TI1F_ED.
Channel 1 is configured as input, IC1 is mapped on TRC.
Captured value stored in TIMx_CCR1 correspond to the time elapsed between 2 changes on the inputs. It gives information about motor speed.
Channel 2 is configured in output PWM 2 mode.
Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
OC2REF is selected as trigger output on TRGO.
LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used when TIMx operates in Hall sensor interface mode.
Parameters:
TIMx | Timer Instance
TIM_HallSensorInitStruct | pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 564 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ACTIVEINPUT_TRC, LL_TIM_OC_SetCompareCH2(), LL_TIM_OCMODE_PWM2, LL_TIM_ReadReg, LL_TIM_SLAVEMODE_RESET, LL_TIM_TRGO_OC2REF, LL_TIM_TS_TI1F_ED, and LL_TIM_WriteReg.

void LL_TIM_HALLSENSOR_StructInit ( LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct )

Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.

Parameters:
TIM_HallSensorInitStruct pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
Return values:
None

Definition at line 535 of file stm32l4xx_ll_tim.c.

References LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_IC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | LL_TIM_IC_InitTypeDef * | TIM_IC_InitStruct
 | ) |  |

Configure the TIMx input channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
TIM_IC_InitStruct | pointer to a LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 420 of file stm32l4xx_ll_tim.c.

References IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, and LL_TIM_CHANNEL_CH4.

void LL_TIM_IC_StructInit ( LL_TIM_IC_InitTypeDef * TIM_ICInitStruct )

Set the fields of the TIMx input channel configuration data structure to their default values.

Parameters:
TIM_ICInitStruct pointer to a LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
Return values:
None

Definition at line 398 of file stm32l4xx_ll_tim.c.

References LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_InitTypeDef * | TIM_InitStruct
 | ) |  |

Configure the TIMx time base unit.

Parameters:
TIMx | Timer Instance
TIM_InitStruct | pointer to a LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 279 of file stm32l4xx_ll_tim.c.

References assert_param, LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, IS_LL_TIM_CLOCKDIVISION, IS_LL_TIM_COUNTERMODE, LL_TIM_GenerateEvent_UPDATE(), LL_TIM_ReadReg, LL_TIM_SetAutoReload(), LL_TIM_SetPrescaler(), LL_TIM_SetRepetitionCounter(), LL_TIM_WriteReg, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

ErrorStatus LL_TIM_OC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OC_InitStruct
 | ) |  |

Configure the TIMx output channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
TIM_OC_InitStruct | pointer to a LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 360 of file stm32l4xx_ll_tim.c.

References LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, LL_TIM_CHANNEL_CH4, LL_TIM_CHANNEL_CH5, LL_TIM_CHANNEL_CH6, OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

void LL_TIM_OC_StructInit ( LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct )

Set the fields of the TIMx output channel configuration data structure to their default values.

Parameters:
TIM_OC_InitStruct pointer to a LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
Return values:
None

Definition at line 332 of file stm32l4xx_ll_tim.c.

References LL_TIM_OC_InitTypeDef::CompareValue, LL_TIM_OCIDLESTATE_LOW, LL_TIM_OCMODE_FROZEN, LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCSTATE_DISABLE, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

void LL_TIM_StructInit ( LL_TIM_InitTypeDef * TIM_InitStruct )

Set the fields of the time base unit configuration data structure to their default values.

Parameters:
TIM_InitStruct pointer to a LL_TIM_InitTypeDef structure (time base unit configuration data structure)
Return values:
None

Definition at line 261 of file stm32l4xx_ll_tim.c.

References LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, LL_TIM_CLOCKDIVISION_DIV1, LL_TIM_COUNTERMODE_UP, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART

Modules
USART
STM32L4xx_LL_Driver

Modules

USART Private Constants
USART Private Macros
USART Exported Init structures
USART Exported Constants
USART Exported Macros
USART Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for USART registers.

Register | Bit | Function
BRR | BRR | LL_USART_GetBaudRate
 |  | LL_USART_SetBaudRate
CR1 | CMIE | LL_USART_DisableIT_CM
 |  | LL_USART_EnableIT_CM
 |  | LL_USART_IsEnabledIT_CM
 | DEAT | LL_USART_GetDEAssertionTime
 |  | LL_USART_SetDEAssertionTime
 | DEDT | LL_USART_GetDEDeassertionTime
 |  | LL_USART_SetDEDeassertionTime
 | EOBIE | LL_USART_DisableIT_EOB
 |  | LL_USART_EnableIT_EOB
 |  | LL_USART_IsEnabledIT_EOB
 | IDLEIE | LL_USART_DisableIT_IDLE
 |  | LL_USART_EnableIT_IDLE
 |  | LL_USART_IsEnabledIT_IDLE
 | M0 | LL_USART_ConfigCharacter
 |  | LL_USART_GetDataWidth
 |  | LL_USART_SetDataWidth
 | M1 | LL_USART_ConfigCharacter
 |  | LL_USART_GetDataWidth
 |  | LL_USART_SetDataWidth
 | MME | LL_USART_DisableMuteMode
 |  | LL_USART_EnableMuteMode
 |  | LL_USART_IsEnabledMuteMode
 | OVER8 | LL_USART_GetOverSampling
 |  | LL_USART_SetOverSampling
 | PCE | LL_USART_ConfigCharacter
 |  | LL_USART_GetParity
 |  | LL_USART_SetParity
 | PEIE | LL_USART_DisableIT_PE
 |  | LL_USART_EnableIT_PE
 |  | LL_USART_IsEnabledIT_PE
 | PS | LL_USART_ConfigCharacter
 |  | LL_USART_GetParity
 |  | LL_USART_SetParity
 | RE | LL_USART_DisableDirectionRx
 |  | LL_USART_EnableDirectionRx
 |  | LL_USART_GetTransferDirection
 |  | LL_USART_SetTransferDirection
 | RTOIE | LL_USART_DisableIT_RTO
 |  | LL_USART_EnableIT_RTO
 |  | LL_USART_IsEnabledIT_RTO
 | RXNEIE | LL_USART_DisableIT_RXNE
 |  | LL_USART_EnableIT_RXNE
 |  | LL_USART_IsEnabledIT_RXNE
 | TCIE | LL_USART_DisableIT_TC
 |  | LL_USART_EnableIT_TC
 |  | LL_USART_IsEnabledIT_TC
 | TE | LL_USART_DisableDirectionTx
 |  | LL_USART_EnableDirectionTx
 |  | LL_USART_GetTransferDirection
 |  | LL_USART_SetTransferDirection
 | TXEIE | LL_USART_DisableIT_TXE
 |  | LL_USART_EnableIT_TXE
 |  | LL_USART_IsEnabledIT_TXE
 | UE | LL_USART_Disable
 |  | LL_USART_Enable
 |  | LL_USART_IsEnabled
 | UESM | LL_USART_DisableInStopMode
 |  | LL_USART_EnableInStopMode
 |  | LL_USART_IsEnabledInStopMode
 | WAKE | LL_USART_GetWakeUpMethod
 |  | LL_USART_SetWakeUpMethod
CR2 | ABREN | LL_USART_DisableAutoBaudRate
 |  | LL_USART_EnableAutoBaudRate
 |  | LL_USART_IsEnabledAutoBaud
 | ABRMODE | LL_USART_GetAutoBaudRateMode
 |  | LL_USART_SetAutoBaudRateMode
 | ADD | LL_USART_ConfigNodeAddress
 |  | LL_USART_GetNodeAddress
 | ADDM7 | LL_USART_ConfigNodeAddress
 |  | LL_USART_GetNodeAddressLen
 | CLKEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableSCLKOutput
 |  | LL_USART_EnableSCLKOutput
 |  | LL_USART_IsEnabledSCLKOutput
 | CPHA | LL_USART_ConfigClock
 |  | LL_USART_GetClockPhase
 |  | LL_USART_SetClockPhase
 | CPOL | LL_USART_ConfigClock
 |  | LL_USART_GetClockPolarity
 |  | LL_USART_SetClockPolarity
 | DATAINV | LL_USART_GetBinaryDataLogic
 |  | LL_USART_SetBinaryDataLogic
 | LBCL | LL_USART_ConfigClock
 |  | LL_USART_GetLastClkPulseOutput
 |  | LL_USART_SetLastClkPulseOutput
 | LBDIE | LL_USART_DisableIT_LBD
 |  | LL_USART_EnableIT_LBD
 |  | LL_USART_IsEnabledIT_LBD
 | LBDL | LL_USART_GetLINBrkDetectionLen
 |  | LL_USART_SetLINBrkDetectionLen
 | LINEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableLIN
 |  | LL_USART_EnableLIN
 |  | LL_USART_IsEnabledLIN
 | MSBFIRST | LL_USART_GetTransferBitOrder
 |  | LL_USART_SetTransferBitOrder
 | RTOEN | LL_USART_DisableRxTimeout
 |  | LL_USART_EnableRxTimeout
 |  | LL_USART_IsEnabledRxTimeout
 | RXINV | LL_USART_GetRXPinLevel
 |  | LL_USART_SetRXPinLevel
 | STOP | LL_USART_ConfigCharacter
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_GetStopBitsLength
 |  | LL_USART_SetStopBitsLength
 | SWAP | LL_USART_GetTXRXSwap
 |  | LL_USART_SetTXRXSwap
 | TXINV | LL_USART_GetTXPinLevel
 |  | LL_USART_SetTXPinLevel
CR3 | CTSE | LL_USART_DisableCTSHWFlowCtrl
 |  | LL_USART_EnableCTSHWFlowCtrl
 |  | LL_USART_GetHWFlowCtrl
 |  | LL_USART_SetHWFlowCtrl
 | CTSIE | LL_USART_DisableIT_CTS
 |  | LL_USART_EnableIT_CTS
 |  | LL_USART_IsEnabledIT_CTS
 | DDRE | LL_USART_DisableDMADeactOnRxErr
 |  | LL_USART_EnableDMADeactOnRxErr
 |  | LL_USART_IsEnabledDMADeactOnRxErr
 | DEM | LL_USART_DisableDEMode
 |  | LL_USART_EnableDEMode
 |  | LL_USART_IsEnabledDEMode
 | DEP | LL_USART_GetDESignalPolarity
 |  | LL_USART_SetDESignalPolarity
 | DMAR | LL_USART_DisableDMAReq_RX
 |  | LL_USART_EnableDMAReq_RX
 |  | LL_USART_IsEnabledDMAReq_RX
 | DMAT | LL_USART_DisableDMAReq_TX
 |  | LL_USART_EnableDMAReq_TX
 |  | LL_USART_IsEnabledDMAReq_TX
 | EIE | LL_USART_DisableIT_ERROR
 |  | LL_USART_EnableIT_ERROR
 |  | LL_USART_IsEnabledIT_ERROR
 | HDSEL | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableHalfDuplex
 |  | LL_USART_EnableHalfDuplex
 |  | LL_USART_IsEnabledHalfDuplex
 | IREN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableIrda
 |  | LL_USART_EnableIrda
 |  | LL_USART_IsEnabledIrda
 | IRLP | LL_USART_GetIrdaPowerMode
 |  | LL_USART_SetIrdaPowerMode
 | NACK | LL_USART_DisableSmartcardNACK
 |  | LL_USART_EnableSmartcardNACK
 |  | LL_USART_IsEnabledSmartcardNACK
 | ONEBIT | LL_USART_DisableOneBitSamp
 |  | LL_USART_EnableOneBitSamp
 |  | LL_USART_IsEnabledOneBitSamp
 | OVRDIS | LL_USART_DisableOverrunDetect
 |  | LL_USART_EnableOverrunDetect
 |  | LL_USART_IsEnabledOverrunDetect
 | RTSE | LL_USART_DisableRTSHWFlowCtrl
 |  | LL_USART_EnableRTSHWFlowCtrl
 |  | LL_USART_GetHWFlowCtrl
 |  | LL_USART_SetHWFlowCtrl
 | SCARCNT | LL_USART_GetSmartcardAutoRetryCount
 |  | LL_USART_SetSmartcardAutoRetryCount
 | SCEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableSmartcard
 |  | LL_USART_EnableSmartcard
 |  | LL_USART_IsEnabledSmartcard
 | WUFIE | LL_USART_DisableIT_WKUP
 |  | LL_USART_EnableIT_WKUP
 |  | LL_USART_IsEnabledIT_WKUP
 | WUS | LL_USART_GetWKUPType
 |  | LL_USART_SetWKUPType
GTPR | GT | LL_USART_GetSmartcardGuardTime
 |  | LL_USART_SetSmartcardGuardTime
 | PSC | LL_USART_GetIrdaPrescaler
 |  | LL_USART_GetSmartcardPrescaler
 |  | LL_USART_SetIrdaPrescaler
 |  | LL_USART_SetSmartcardPrescaler
ICR | CMCF | LL_USART_ClearFlag_CM
 | CTSCF | LL_USART_ClearFlag_nCTS
 | EOBCF | LL_USART_ClearFlag_EOB
 | FECF | LL_USART_ClearFlag_FE
 | IDLECF | LL_USART_ClearFlag_IDLE
 | LBDCF | LL_USART_ClearFlag_LBD
 | NCF | LL_USART_ClearFlag_NE
 | ORECF | LL_USART_ClearFlag_ORE
 | PECF | LL_USART_ClearFlag_PE
 | RTOCF | LL_USART_ClearFlag_RTO
 | TCCF | LL_USART_ClearFlag_TC
 | WUCF | LL_USART_ClearFlag_WKUP
ISR | ABRE | LL_USART_IsActiveFlag_ABRE
 | ABRF | LL_USART_IsActiveFlag_ABR
 | BUSY | LL_USART_IsActiveFlag_BUSY
 | CMF | LL_USART_IsActiveFlag_CM
 | CTS | LL_USART_IsActiveFlag_CTS
 | CTSIF | LL_USART_IsActiveFlag_nCTS
 | EOBF | LL_USART_IsActiveFlag_EOB
 | FE | LL_USART_IsActiveFlag_FE
 | IDLE | LL_USART_IsActiveFlag_IDLE
 | LBDF | LL_USART_IsActiveFlag_LBD
 | NF | LL_USART_IsActiveFlag_NE
 | ORE | LL_USART_IsActiveFlag_ORE
 | PE | LL_USART_IsActiveFlag_PE
 | REACK | LL_USART_IsActiveFlag_REACK
 | RTOF | LL_USART_IsActiveFlag_RTO
 | RWU | LL_USART_IsActiveFlag_RWU
 | RXNE | LL_USART_IsActiveFlag_RXNE
 | SBKF | LL_USART_IsActiveFlag_SBK
 | TC | LL_USART_IsActiveFlag_TC
 | TEACK | LL_USART_IsActiveFlag_TEACK
 | TXE | LL_USART_IsActiveFlag_TXE
 | WUF | LL_USART_IsActiveFlag_WKUP
RDR | RDR | LL_USART_DMA_GetRegAddr
 |  | LL_USART_ReceiveData8
 |  | LL_USART_ReceiveData9
RQR | ABRRQ | LL_USART_RequestAutoBaudRate
 | MMRQ | LL_USART_RequestEnterMuteMode
 | RXFRQ | LL_USART_RequestRxDataFlush
 | SBKRQ | LL_USART_RequestBreakSending
 | TXFRQ | LL_USART_RequestTxDataFlush
RTOR | BLEN | LL_USART_GetBlockLength
 |  | LL_USART_SetBlockLength
 | RTO | LL_USART_GetRxTimeout
 |  | LL_USART_SetRxTimeout
TDR | TDR | LL_USART_DMA_GetRegAddr
 |  | LL_USART_TransmitData8
 |  | LL_USART_TransmitData9
Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | USART_POSITION_CR1_DEDT (uint32_t)POSITION_VAL(USART_CR1_DEDT)
#define | USART_POSITION_CR1_DEAT (uint32_t)POSITION_VAL(USART_CR1_DEAT)
#define | USART_POSITION_CR2_ADD (uint32_t)POSITION_VAL(USART_CR2_ADD)
#define | USART_POSITION_CR3_SCARCNT (uint32_t)POSITION_VAL(USART_CR3_SCARCNT)
#define | USART_POSITION_RTOR_BLEN (uint32_t)POSITION_VAL(USART_RTOR_BLEN)
#define | USART_POSITION_GTPR_GT (uint32_t)POSITION_VAL(USART_GTPR_GT)

Define Documentation

#define USART_POSITION_CR1_DEAT (uint32_t)POSITION_VAL(USART_CR1_DEAT)

Definition at line 69 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_GetDEAssertionTime(), and LL_USART_SetDEAssertionTime().

#define USART_POSITION_CR1_DEDT (uint32_t)POSITION_VAL(USART_CR1_DEDT)

Definition at line 68 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_GetDEDeassertionTime(), and LL_USART_SetDEDeassertionTime().

#define USART_POSITION_CR2_ADD (uint32_t)POSITION_VAL(USART_CR2_ADD)

Definition at line 70 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ConfigNodeAddress(), and LL_USART_GetNodeAddress().

#define USART_POSITION_CR3_SCARCNT (uint32_t)POSITION_VAL(USART_CR3_SCARCNT)

Definition at line 71 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_GetSmartcardAutoRetryCount(), and LL_USART_SetSmartcardAutoRetryCount().

#define USART_POSITION_GTPR_GT (uint32_t)POSITION_VAL(USART_GTPR_GT)

Definition at line 73 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_GetSmartcardGuardTime(), and LL_USART_SetSmartcardGuardTime().

#define USART_POSITION_RTOR_BLEN (uint32_t)POSITION_VAL(USART_RTOR_BLEN)

Definition at line 72 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_GetBlockLength(), and LL_USART_SetBlockLength().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 10000000U)

Definition at line 78 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_CLOCKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_CLOCK_DISABLE) \
                                         || ((__VALUE__) == LL_USART_CLOCK_ENABLE))

Definition at line 105 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PHASE_1EDGE) \
                                        || ((__VALUE__) == LL_USART_PHASE_2EDGE))

Definition at line 99 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_POLARITY_LOW) \
                                           || ((__VALUE__) == LL_USART_POLARITY_HIGH))

Definition at line 102 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DATAWIDTH_7B) \
                                       || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
                                       || ((__VALUE__) == LL_USART_DATAWIDTH_9B))

Definition at line 89 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DIRECTION_NONE) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_RX) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_TX) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))

Definition at line 80 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_HWCONTROL_NONE) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))

Definition at line 113 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_LASTBITCLKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
                                              || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))

Definition at line 96 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_OVERSAMPLING ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_OVERSAMPLING_16) \
                                          || ((__VALUE__) == LL_USART_OVERSAMPLING_8))

Definition at line 93 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PARITY_NONE) \
                                    || ((__VALUE__) == LL_USART_PARITY_EVEN) \
                                    || ((__VALUE__) == LL_USART_PARITY_ODD))

Definition at line 85 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_STOPBITS_0_5) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_1) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_2))

Definition at line 108 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_Init().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_InitTypeDef Struct Reference
USART Exported Init structures

LL USART Init Structure definition. More...

#include <stm32l4xx_ll_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl
uint32_t | OverSampling

Detailed Description

LL USART Init Structure definition.

Definition at line 97 of file stm32l4xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_InitTypeDef::BaudRate

This field defines expected Usart communication baud rate.

This feature can be modified afterwards using unitary function LL_USART_SetBaudRate().

Definition at line 99 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_USART_SetDataWidth().

Definition at line 103 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_USART_SetHWFlowCtrl().

Definition at line 123 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::OverSampling

Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of Oversampling.

This feature can be modified afterwards using unitary function LL_USART_SetOverSampling().

Definition at line 128 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_USART_SetParity().

Definition at line 113 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_USART_SetStopBitsLength().

Definition at line 108 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Communication Direction.

This feature can be modified afterwards using unitary function LL_USART_SetTransferDirection().

Definition at line 118 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_usart.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_USART_ClockInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_ClockInitTypeDef Struct Reference
USART Exported Init structures

LL USART Clock Init Structure definition. More...

#include <stm32l4xx_ll_usart.h>

Data Fields

uint32_t | ClockOutput
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | LastBitClockPulse

Detailed Description

LL USART Clock Init Structure definition.

Definition at line 138 of file stm32l4xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_ClockInitTypeDef::ClockOutput

Specifies whether the USART clock is enabled or disabled. This parameter can be a value of Clock Signal.

USART HW configuration can be modified afterwards using unitary functions LL_USART_EnableSCLKOutput() or LL_USART_DisableSCLKOutput(). For more details, refer to description of this function.

Definition at line 140 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of Clock Phase.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPhase(). For more details, refer to description of this function.

Definition at line 153 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPolarity

Specifies the steady state of the serial clock. This parameter can be a value of Clock Polarity.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPolarity(). For more details, refer to description of this function.

Definition at line 147 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::LastBitClockPulse

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of Last Clock Pulse.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function.

Definition at line 159 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_usart.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_WriteReg function. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NCF USART_ICR_NCF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_USART_WriteReg function.

Define Documentation

#define LL_USART_ICR_CMCF USART_ICR_CMCF

Character match flag

Definition at line 195 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_CTSCF USART_ICR_CTSCF

CTS flag

Definition at line 192 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_EOBCF USART_ICR_EOBCF

End of block flag

Definition at line 194 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_FECF USART_ICR_FECF

Framing error flag

Definition at line 183 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected flag

Definition at line 186 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_LBDCF USART_ICR_LBDCF

LIN break detection flag

Definition at line 191 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_NCF USART_ICR_NCF

Noise detected flag

Definition at line 184 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_ORECF USART_ICR_ORECF

Overrun error flag

Definition at line 185 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_PECF USART_ICR_PECF

Parity error flag

Definition at line 182 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_RTOCF USART_ICR_RTOCF

Receiver timeout flag

Definition at line 193 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_TCCF USART_ICR_TCCF

Transmission complete flag

Definition at line 187 of file stm32l4xx_ll_usart.h.

#define LL_USART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode flag

Definition at line 196 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_ReadReg function. More...

Defines

#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE USART_ISR_RXNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE USART_ISR_TXE
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK

Detailed Description

Flags defines which can be used with LL_USART_ReadReg function.

Define Documentation

#define LL_USART_ISR_ABRE USART_ISR_ABRE

Auto baud rate error flag

Definition at line 218 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_ABRF USART_ISR_ABRF

Auto baud rate flag

Definition at line 219 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 220 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 221 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 215 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 214 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_EOBF USART_ISR_EOBF

End of block flag

Definition at line 217 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 206 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 209 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_LBDF USART_ISR_LBDF

LIN break detection flag

Definition at line 213 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 207 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 208 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 205 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 226 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_RTOF USART_ISR_RTOF

Receiver timeout flag

Definition at line 216 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 223 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_RXNE USART_ISR_RXNE

Read data register not empty flag

Definition at line 210 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 222 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 211 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 225 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_TXE USART_ISR_TXE

Transmit data register empty flag

Definition at line 212 of file stm32l4xx_ll_usart.h.

#define LL_USART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 224 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
USART Exported Constants

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions. More...

Defines

#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE USART_CR1_RXNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE USART_CR1_TXEIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE

Detailed Description

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

Define Documentation

#define LL_USART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 243 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR1_EOBIE USART_CR1_EOBIE

End of Block interrupt enable

Definition at line 245 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 238 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 242 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR1_RTOIE USART_CR1_RTOIE

Receiver timeout interrupt enable

Definition at line 244 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE

Read data register not empty interrupt enable

Definition at line 239 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 240 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR1_TXEIE USART_CR1_TXEIE

Transmit data register empty interrupt enable

Definition at line 241 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR2_LBDIE USART_CR2_LBDIE

LIN break detection interrupt enable

Definition at line 246 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 248 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 247 of file stm32l4xx_ll_usart.h.

#define LL_USART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 249 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Communication Direction

Defines
Communication Direction
USART Exported Constants

Defines

#define | LL_USART_DIRECTION_NONE (uint32_t)0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_USART_DIRECTION_NONE (uint32_t)0x00000000U

Transmitter and Receiver are disabled

Definition at line 260 of file stm32l4xx_ll_usart.h.

#define LL_USART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 261 of file stm32l4xx_ll_usart.h.

#define LL_USART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 262 of file stm32l4xx_ll_usart.h.

#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 263 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

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STM32L486xx HAL User Manual: Parity Control

Defines
Parity Control
USART Exported Constants

Defines

#define | LL_USART_PARITY_NONE (uint32_t)0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_USART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 272 of file stm32l4xx_ll_usart.h.

#define LL_USART_PARITY_NONE (uint32_t)0x00000000U

Parity control disabled

Definition at line 271 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 273 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Wakeup

Defines
Wakeup
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_IDLELINE (uint32_t)0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

USART wake up from Mute mode on Address Mark

Definition at line 282 of file stm32l4xx_ll_usart.h.

#define LL_USART_WAKEUP_IDLELINE (uint32_t)0x00000000U

USART wake up from Mute mode on Idle Line

Definition at line 281 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Datawidth

Defines
Datawidth
USART Exported Constants

Defines

#define | LL_USART_DATAWIDTH_7B USART_CR1_M1
#define | LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M0

Define Documentation

#define LL_USART_DATAWIDTH_7B USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

Definition at line 290 of file stm32l4xx_ll_usart.h.

#define LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 291 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_DATAWIDTH_9B USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 292 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Oversampling

Defines
Oversampling
USART Exported Constants

Defines

#define | LL_USART_OVERSAMPLING_16 (uint32_t)0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define LL_USART_OVERSAMPLING_16 (uint32_t)0x00000000U

Oversampling by 16

Definition at line 300 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 301 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_GetBaudRate(), and LL_USART_SetBaudRate().

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STM32L486xx HAL User Manual: Clock Signal

Defines
Clock Signal
USART Exported Constants

Defines

#define | LL_USART_CLOCK_DISABLE (uint32_t)0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define LL_USART_CLOCK_DISABLE (uint32_t)0x00000000U

Clock signal not provided

Definition at line 311 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Clock signal provided

Definition at line 312 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Last Clock Pulse

Defines
Last Clock Pulse
USART Exported Constants

Defines

#define | LL_USART_LASTCLKPULSE_NO_OUTPUT (uint32_t)0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

Define Documentation

#define LL_USART_LASTCLKPULSE_NO_OUTPUT (uint32_t)0x00000000U

The clock pulse of the last data bit is not output to the SCLK pin

Definition at line 321 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

The clock pulse of the last data bit is output to the SCLK pin

Definition at line 322 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Clock Phase

Defines
Clock Phase
USART Exported Constants

Defines

#define | LL_USART_PHASE_1EDGE (uint32_t)0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define LL_USART_PHASE_1EDGE (uint32_t)0x00000000U

The first clock transition is the first data capture edge

Definition at line 330 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_PHASE_2EDGE USART_CR2_CPHA

The second clock transition is the first data capture edge

Definition at line 331 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
USART Exported Constants

Defines

#define | LL_USART_POLARITY_LOW (uint32_t)0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define LL_USART_POLARITY_HIGH USART_CR2_CPOL

Steady high value on SCLK pin outside transmission window

Definition at line 340 of file stm32l4xx_ll_usart.h.

#define LL_USART_POLARITY_LOW (uint32_t)0x00000000U

Steady low value on SCLK pin outside transmission window

Definition at line 339 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

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STM32L486xx HAL User Manual: Stop Bits

Defines
Stop Bits
USART Exported Constants

Defines

#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 (uint32_t)0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0

0.5 stop bit

Definition at line 348 of file stm32l4xx_ll_usart.h.

#define LL_USART_STOPBITS_1 (uint32_t)0x00000000U

1 stop bit

Definition at line 349 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

1.5 stop bits

Definition at line 350 of file stm32l4xx_ll_usart.h.

#define LL_USART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 351 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
USART Exported Constants

Defines

#define | LL_USART_TXRX_STANDARD (uint32_t)0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_USART_TXRX_STANDARD (uint32_t)0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 359 of file stm32l4xx_ll_usart.h.

#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 360 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 369 of file stm32l4xx_ll_usart.h.

#define LL_USART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U

RX pin signal works using the standard logic levels

Definition at line 368 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 378 of file stm32l4xx_ll_usart.h.

#define LL_USART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U

TX pin signal works using the standard logic levels

Definition at line 377 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
USART Exported Constants

Defines

#define | LL_USART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 387 of file stm32l4xx_ll_usart.h.

#define LL_USART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 386 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Bit Order

Defines
Bit Order
USART Exported Constants

Defines

#define | LL_USART_BITORDER_LSBFIRST (uint32_t)0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_USART_BITORDER_LSBFIRST (uint32_t)0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 395 of file stm32l4xx_ll_usart.h.

#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 396 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Autobaud Detection

Defines
Autobaud Detection
USART Exported Constants

Defines

#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT (uint32_t)0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

Define Documentation

#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

0x55 frame detection

Definition at line 407 of file stm32l4xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1

0x7F frame detection

Definition at line 406 of file stm32l4xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0

Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx

Definition at line 405 of file stm32l4xx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT (uint32_t)0x00000000U

Measurement of the start bit is used to detect the baud rate

Definition at line 404 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Address Length Detection

Defines
Address Length Detection
USART Exported Constants

Defines

#define | LL_USART_ADDRESS_DETECT_4B (uint32_t)0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_USART_ADDRESS_DETECT_4B (uint32_t)0x00000000U

4-bit address detection method selected

Definition at line 415 of file stm32l4xx_ll_usart.h.

#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 416 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Hardware Control

Defines
Hardware Control
USART Exported Constants

Defines

#define | LL_USART_HWCONTROL_NONE (uint32_t)0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 426 of file stm32l4xx_ll_usart.h.

#define LL_USART_HWCONTROL_NONE (uint32_t)0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 424 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 425 of file stm32l4xx_ll_usart.h.

#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 427 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_USART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U

Wake up active on address match

Definition at line 435 of file stm32l4xx_ll_usart.h.

#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 437 of file stm32l4xx_ll_usart.h.

#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 436 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: IrDA Power

Defines
IrDA Power
USART Exported Constants

Defines

#define | LL_USART_IRDA_POWER_NORMAL (uint32_t)0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

Define Documentation

#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

IrDA low power mode

Definition at line 446 of file stm32l4xx_ll_usart.h.

#define LL_USART_IRDA_POWER_NORMAL (uint32_t)0x00000000U

IrDA normal power mode

Definition at line 445 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: LIN Break Detection Length

Defines
LIN Break Detection Length
USART Exported Constants

Defines

#define | LL_USART_LINBREAK_DETECT_10B (uint32_t)0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

Define Documentation

#define LL_USART_LINBREAK_DETECT_10B (uint32_t)0x00000000U

10-bit break detection method selected

Definition at line 454 of file stm32l4xx_ll_usart.h.

#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

11-bit break detection method selected

Definition at line 455 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
USART Exported Constants

Defines

#define | LL_USART_DE_POLARITY_HIGH (uint32_t)0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_USART_DE_POLARITY_HIGH (uint32_t)0x00000000U

DE signal is active high

Definition at line 463 of file stm32l4xx_ll_usart.h.

#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 464 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
USART Exported Constants

Defines

#define | LL_USART_DMA_REG_DATA_TRANSMIT (uint32_t)0U
#define | LL_USART_DMA_REG_DATA_RECEIVE (uint32_t)1U

Define Documentation

#define LL_USART_DMA_REG_DATA_RECEIVE (uint32_t)1U

Get address of data register used for reception

Definition at line 473 of file stm32l4xx_ll_usart.h.

#define LL_USART_DMA_REG_DATA_TRANSMIT (uint32_t)0U

Get address of data register used for transmission

Definition at line 472 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_DMA_GetRegAddr().

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STM32L486xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
USART Exported Macros

Defines

#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.

Define Documentation

#define LL_USART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 506 of file stm32l4xx_ll_usart.h.

#define LL_USART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 498 of file stm32l4xx_ll_usart.h.

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STM32L486xx HAL User Manual: Exported_Macros_Helper

Defines
Exported_Macros_Helper
USART Exported Macros

Defines

#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Define Documentation

#define __LL_USART_DIV_SAMPLING16 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_16 case

Definition at line 531 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

#define __LL_USART_DIV_SAMPLING8 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_8 case

Definition at line 522 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

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STM32L486xx HAL User Manual: Configuration functions

Functions
Configuration functions
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (USART_TypeDef *USARTx)
Get Block Length value in reception.

Function Documentation

__STATIC_INLINE void LL_USART_ConfigCharacter | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_USART_SetDataWidth() function
  • Parity Control and mode configuration using LL_USART_SetParity() function
  • Stop bits configuration using LL_USART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_USART_ConfigCharacter
CR1 PCE LL_USART_ConfigCharacter
CR1 M0 LL_USART_ConfigCharacter
CR1 M1 LL_USART_ConfigCharacter
CR2 STOP LL_USART_ConfigCharacter
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1078 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigClock | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Phase,
 |  | uint32_t | Polarity,
 |  | uint32_t | LBCPOutput
 | ) |  |

Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clock Phase configuration using LL_USART_SetClockPhase() function
  • Clock Polarity configuration using LL_USART_SetClockPolarity() function
  • Output of Last bit Clock pulse configuration using LL_USART_SetLastClkPulseOutput() function
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_ConfigClock
CR2 CPOL LL_USART_ConfigClock
CR2 LBCL LL_USART_ConfigClock
Parameters:
USARTx USART Instance
Phase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Polarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
LBCPOutput This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 976 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigNodeAddress | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the USART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_ConfigNodeAddress
CR2 ADDM7 LL_USART_ConfigNodeAddress
Parameters:
USARTx | USART Instance
AddressLen This parameter can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the USART node.
Return values:
None

Definition at line 1356 of file stm32l4xx_ll_usart.h.

References USART_POSITION_CR2_ADD.

__STATIC_INLINE void LL_USART_Disable ( USART_TypeDef * USARTx )

USART Disable (all USART prescalers and outputs are disabled)

Note:
When USART is disabled, USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USARTx_ISR are set to their default values.
Reference Manual to LL API cross reference:
CR1 UE LL_USART_Disable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 571 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableAutoBaudRate ( USART_TypeDef * USARTx )

Disable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_DisableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1247 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1437 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionRx ( USART_TypeDef * USARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_DisableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 646 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_DisableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 668 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableInStopMode ( USART_TypeDef * USARTx )

USART disabled in STOP Mode.

Note:
When this function is disabled, USART is not able to wake up the MCU from Stop mode
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_DisableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 611 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableMuteMode ( USART_TypeDef * USARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_DisableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 816 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOneBitSamp ( USART_TypeDef * USARTx )

Disable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_DisableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1496 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOverrunDetect ( USART_TypeDef * USARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_DisableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1529 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1411 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRxTimeout ( USART_TypeDef * USARTx )

Disable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_DisableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1317 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSCLKOutput ( USART_TypeDef * USARTx )

Disable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_DisableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1002 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ClockInit().

__STATIC_INLINE void LL_USART_Enable ( USART_TypeDef * USARTx )

USART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_Enable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 557 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableAutoBaudRate ( USART_TypeDef * USARTx )

Enable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_EnableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1234 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1424 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionRx ( USART_TypeDef * USARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_USART_EnableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 635 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_EnableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 657 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableInStopMode ( USART_TypeDef * USARTx )

USART enabled in STOP Mode.

Note:
When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that USART clock selection is HSI or LSE in RCC.
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_EnableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 597 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableMuteMode ( USART_TypeDef * USARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_EnableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 805 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOneBitSamp ( USART_TypeDef * USARTx )

Enable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_EnableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1485 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOverrunDetect ( USART_TypeDef * USARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_EnableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1518 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1398 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRxTimeout ( USART_TypeDef * USARTx )

Enable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_EnableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1306 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSCLKOutput ( USART_TypeDef * USARTx )

Enable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_EnableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 989 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode ( USART_TypeDef * USARTx )

Return Auto Baud-Rate mode.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_GetAutoBaudRateMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME

Definition at line 1295 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | OverSampling
 | ) |  |

Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_GetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
Baud Rate

Definition at line 1624 of file stm32l4xx_ll_usart.h.

References LL_USART_OVERSAMPLING_8.

__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic ( USART_TypeDef * USARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_GetBinaryDataLogic
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE

Definition at line 1190 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBlockLength ( USART_TypeDef * USARTx )

Get Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_GetBlockLength
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1690 of file stm32l4xx_ll_usart.h.

References USART_POSITION_RTOR_BLEN.

__STATIC_INLINE uint32_t LL_USART_GetClockPhase ( USART_TypeDef * USARTx )

Return phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_GetClockPhase
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE

Definition at line 917 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPolarity ( USART_TypeDef * USARTx )

Return polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_GetClockPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH

Definition at line 948 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDataWidth ( USART_TypeDef * USARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_GetDataWidth
CR1 M1 LL_USART_GetDataWidth
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B

Definition at line 794 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl ( USART_TypeDef * USARTx )

Return HW Flow Control configuration (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_GetHWFlowCtrl
CR3 CTSE LL_USART_GetHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS

Definition at line 1474 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput ( USART_TypeDef * USARTx )

Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_GetLastClkPulseOutput
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT

Definition at line 886 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddress ( USART_TypeDef * USARTx )

Return 8 bit Address of the USART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_GetNodeAddress
Parameters:
USARTx USART Instance
Return values:
Address of the USART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 1372 of file stm32l4xx_ll_usart.h.

References USART_POSITION_CR2_ADD.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen ( USART_TypeDef * USARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_USART_GetNodeAddressLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B

Definition at line 1385 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetOverSampling ( USART_TypeDef * USARTx )

Return Oversampling mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_GetOverSampling
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8

Definition at line 854 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetParity ( USART_TypeDef * USARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_USART_GetParity
CR1 PCE LL_USART_GetParity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD

Definition at line 736 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel ( USART_TypeDef * USARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_GetRXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED

Definition at line 1134 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRxTimeout ( USART_TypeDef * USARTx )

Get Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_GetRxTimeout
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x00FFFFFF

Definition at line 1667 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength ( USART_TypeDef * USARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_GetStopBitsLength
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2

Definition at line 1046 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder ( USART_TypeDef * USARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_GetTransferBitOrder
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST

Definition at line 1221 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferDirection ( USART_TypeDef * USARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_GetTransferDirection
CR1 TE LL_USART_GetTransferDirection
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX

Definition at line 702 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel ( USART_TypeDef * USARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_GetTXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED

Definition at line 1161 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap ( USART_TypeDef * USARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_GetTXRXSwap
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED

Definition at line 1107 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod ( USART_TypeDef * USARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_GetWakeUpMethod
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK

Definition at line 763 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWKUPType ( USART_TypeDef * USARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_GetWKUPType
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE

Definition at line 1573 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabled ( USART_TypeDef * USARTx )

Indicate if USART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_IsEnabled
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 582 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_Init().

__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud ( USART_TypeDef * USARTx )

Indicate if Auto Baud-Rate Detection mechanism is enabled.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_IsEnabledAutoBaud
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1260 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode ( USART_TypeDef * USARTx )

Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_IsEnabledInStopMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 624 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode ( USART_TypeDef * USARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_IsEnabledMuteMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 827 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp ( USART_TypeDef * USARTx )

Indicate if One bit sampling method is enabled.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1507 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect ( USART_TypeDef * USARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1540 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout ( USART_TypeDef * USARTx )

Indicate if Receiver Timeout feature is enabled.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_IsEnabledRxTimeout
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1328 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput ( USART_TypeDef * USARTx )

Indicate if Clock output on SCLK pin is enabled.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_IsEnabledSCLKOutput
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1015 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetAutoBaudRateMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoBaudRateMode
 | ) |  |

Set Auto Baud-Rate mode bits.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_SetAutoBaudRateMode
Parameters:
USARTx USART Instance
AutoBaudRateMode This parameter can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
Return values:
None

Definition at line 1278 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | OverSampling,
 |  | uint32_t | BaudRate
 | ) |  |

Configure USART BRR register for achieving expected Baud Rate value.

Note:
Compute and set USARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
Peripheral clock and Baud rate values provided as function parameters should be valid (Baud rate value != 0)
Reference Manual to LL API cross reference:
BRR BRR LL_USART_SetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
BaudRate | Baud Rate
Return values:
None

Definition at line 1593 of file stm32l4xx_ll_usart.h.

References __LL_USART_DIV_SAMPLING16, __LL_USART_DIV_SAMPLING8, and LL_USART_OVERSAMPLING_8.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetBinaryDataLogic | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_SetBinaryDataLogic
Parameters:
USARTx USART Instance
DataLogic This parameter can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 1177 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBlockLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BlockLength
 | ) |  |

Set Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_SetBlockLength
Parameters:
USARTx | USART Instance
BlockLength | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1679 of file stm32l4xx_ll_usart.h.

References USART_POSITION_RTOR_BLEN.

__STATIC_INLINE void LL_USART_SetClockPhase | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPhase
 | ) |  |

Select the phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_SetClockPhase
Parameters:
USARTx USART Instance
ClockPhase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Return values:
None

Definition at line 902 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Select the polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_SetClockPolarity
Parameters:
USARTx USART Instance
ClockPolarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
Return values:
None

Definition at line 933 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDataWidth | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_SetDataWidth
CR1 M1 LL_USART_SetDataWidth
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Return values:
None

Definition at line 779 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetHWFlowCtrl | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_SetHWFlowCtrl
CR3 CTSE LL_USART_SetHWFlowCtrl
Parameters:
USARTx USART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 1456 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetLastClkPulseOutput | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LastBitClockPulse
 | ) |  |

Configure if Clock pulse of the last data bit is output to the SCLK pin or not.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_SetLastClkPulseOutput
Parameters:
USARTx USART Instance
LastBitClockPulse This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 870 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetOverSampling | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | OverSampling
 | ) |  |

Set Oversampling to 8-bit or 16-bit mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_SetOverSampling
Parameters:
USARTx USART Instance
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
None

Definition at line 841 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetParity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled).

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (9th or 8th bit depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_USART_SetParity
CR1 PCE LL_USART_SetParity
Parameters:
USARTx USART Instance
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
Return values:
None

Definition at line 721 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_SetRXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1121 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRxTimeout | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Timeout
 | ) |  |

Set Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_SetRxTimeout
Parameters:
USARTx | USART Instance
Timeout | Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
Return values:
None

Definition at line 1656 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetStopBitsLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_SetStopBitsLength
Parameters:
USARTx USART Instance
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1031 of file stm32l4xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetTransferBitOrder | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_SetTransferBitOrder
Parameters:
USARTx USART Instance
BitOrder This parameter can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST
Return values:
None

Definition at line 1206 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTransferDirection | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_SetTransferDirection
CR1 TE LL_USART_SetTransferDirection
Parameters:
USARTx USART Instance
TransferDirection This parameter can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX
Return values:
None

Definition at line 686 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_SetTXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1148 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXRXSwap | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_SetTXRXSwap
Parameters:
USARTx USART Instance
SwapConfig This parameter can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED
Return values:
None

Definition at line 1094 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWakeUpMethod | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_SetWakeUpMethod
Parameters:
USARTx USART Instance
Method This parameter can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 750 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWKUPType | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_SetWKUPType
Parameters:
USARTx USART Instance
Type This parameter can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1557 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration functions related to Irda feature

Functions
Configuration functions related to Irda feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableIrda ( USART_TypeDef * USARTx )

Disable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_DisableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1724 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIrda ( USART_TypeDef * USARTx )

Enable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_EnableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1711 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode ( USART_TypeDef * USARTx )

Retrieve IrDA Power Mode configuration (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_GetIrdaPowerMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_PHASE_2EDGE

Definition at line 1768 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler ( USART_TypeDef * USARTx )

Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetIrdaPrescaler
Parameters:
USARTx USART Instance
Return values:
Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 1797 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda ( USART_TypeDef * USARTx )

Indicate if IrDA mode is enabled.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_IsEnabledIrda
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1737 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPowerMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PowerMode
 | ) |  |

Configure IrDA Power Mode (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_SetIrdaPowerMode
Parameters:
USARTx USART Instance
PowerMode This parameter can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_IRDA_POWER_LOW
Return values:
None

Definition at line 1753 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetIrdaPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1783 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration functions related to Smartcard feature

Functions
Configuration functions related to Smartcard feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableSmartcard ( USART_TypeDef * USARTx )

Disable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_DisableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1870 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSmartcardNACK ( USART_TypeDef * USARTx )

Disable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_DisableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1831 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcard ( USART_TypeDef * USARTx )

Enable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_EnableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1857 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcardNACK ( USART_TypeDef * USARTx )

Enable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_EnableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1818 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount ( USART_TypeDef * USARTx )

Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
Parameters:
USARTx USART Instance
Return values:
Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)

Definition at line 1915 of file stm32l4xx_ll_usart.h.

References USART_POSITION_CR3_SCARCNT.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime ( USART_TypeDef * USARTx )

Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_GetSmartcardGuardTime
Parameters:
USARTx USART Instance
Return values:
Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 1973 of file stm32l4xx_ll_usart.h.

References USART_POSITION_GTPR_GT.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler ( USART_TypeDef * USARTx )

Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetSmartcardPrescaler
Parameters:
USARTx USART Instance
Return values:
Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)

Definition at line 1944 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard ( USART_TypeDef * USARTx )

Indicate if Smartcard mode is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_IsEnabledSmartcard
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1883 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK ( USART_TypeDef * USARTx )

Indicate if Smartcard NACK transmission is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_IsEnabledSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1844 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoRetryCount
 | ) |  |

Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE and PE bits set)
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
Parameters:
USARTx | USART Instance
AutoRetryCount | Value between Min_Data=0 and Max_Data=7
Return values:
None

Definition at line 1902 of file stm32l4xx_ll_usart.h.

References USART_POSITION_CR3_SCARCNT.

__STATIC_INLINE void LL_USART_SetSmartcardGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | GuardTime
 | ) |  |

Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_SetSmartcardGuardTime
Parameters:
USARTx | USART Instance
GuardTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1959 of file stm32l4xx_ll_usart.h.

References USART_POSITION_GTPR_GT.

__STATIC_INLINE void LL_USART_SetSmartcardPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetSmartcardPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1930 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableHalfDuplex ( USART_TypeDef * USARTx )

Disable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_DisableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2007 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableHalfDuplex ( USART_TypeDef * USARTx )

Enable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_EnableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1994 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex ( USART_TypeDef * USARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_IsEnabledHalfDuplex
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2020 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration functions related to LIN feature

Functions
Configuration functions related to LIN feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableLIN ( USART_TypeDef * USARTx )

Disable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_DisableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2085 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableLIN ( USART_TypeDef * USARTx )

Enable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_EnableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2072 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen ( USART_TypeDef * USARTx )

Return LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_GetLINBrkDetectionLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B

Definition at line 2059 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN ( USART_TypeDef * USARTx )

Indicate if LIN mode is enabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_IsEnabledLIN
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2098 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LINBDLength
 | ) |  |

Set LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_SetLINBrkDetectionLen
Parameters:
USARTx USART Instance
LINBDLength This parameter can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B
Return values:
None

Definition at line 2044 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (USART_TypeDef *USARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDEMode ( USART_TypeDef * USARTx )

Disable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_DisableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2186 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDEMode ( USART_TypeDef * USARTx )

Enable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_EnableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2173 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime ( USART_TypeDef * USARTx )

Return DEAT (Driver Enable Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_GetDEAssertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2160 of file stm32l4xx_ll_usart.h.

References USART_POSITION_CR1_DEAT.

__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime ( USART_TypeDef * USARTx )

Return DEDT (Driver Enable De-Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_GetDEDeassertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2133 of file stm32l4xx_ll_usart.h.

References USART_POSITION_CR1_DEDT.

__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity ( USART_TypeDef * USARTx )

Return Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_GetDESignalPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW

Definition at line 2230 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode ( USART_TypeDef * USARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_IsEnabledDEMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2199 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEAssertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_SetDEAssertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2147 of file stm32l4xx_ll_usart.h.

References USART_POSITION_CR1_DEAT.

__STATIC_INLINE void LL_USART_SetDEDeassertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_SetDEDeassertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2120 of file stm32l4xx_ll_usart.h.

References USART_POSITION_CR1_DEDT.

__STATIC_INLINE void LL_USART_SetDESignalPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_SetDESignalPolarity
Parameters:
USARTx USART Instance
Polarity This parameter can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW
Return values:
None

Definition at line 2215 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Advanced Configurations services

Functions
Advanced Configurations services
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Function Documentation

__STATIC_INLINE void LL_USART_ConfigAsyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)

Note:
In UART mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Asynchronous Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigAsyncMode
CR2 CLKEN LL_USART_ConfigAsyncMode
CR3 SCEN LL_USART_ConfigAsyncMode
CR3 IREN LL_USART_ConfigAsyncMode
CR3 HDSEL LL_USART_ConfigAsyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2268 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Half Duplex Mode.

Note:
In Half Duplex mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register, This function also sets the UART/USART in Half Duplex mode.
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Set HDSEL in CR3 using LL_USART_EnableHalfDuplex() function
Other remaining configurations items related to Half Duplex Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigHalfDuplexMode
CR2 CLKEN LL_USART_ConfigHalfDuplexMode
CR3 HDSEL LL_USART_ConfigHalfDuplexMode
CR3 SCEN LL_USART_ConfigHalfDuplexMode
CR3 IREN LL_USART_ConfigHalfDuplexMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2382 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigIrdaMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Irda Mode.

Note:
In IRDA mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the UART/USART in IRDA mode (IREN bit).
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set IREN in CR3 using LL_USART_EnableIrda() function
Other remaining configurations items related to Irda Mode (as Baud Rate, Word length, Power mode, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigIrdaMode
CR2 CLKEN LL_USART_ConfigIrdaMode
CR2 STOP LL_USART_ConfigIrdaMode
CR3 SCEN LL_USART_ConfigIrdaMode
CR3 HDSEL LL_USART_ConfigIrdaMode
CR3 IREN LL_USART_ConfigIrdaMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2465 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigLINMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in LIN Mode.

Note:
In LIN mode, the following bits must be kept cleared:
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also set the UART/USART in LIN mode.
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set LINEN in CR2 using LL_USART_EnableLIN() function
Other remaining configurations items related to LIN Mode (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_ConfigLINMode
CR2 STOP LL_USART_ConfigLINMode
CR2 LINEN LL_USART_ConfigLINMode
CR3 IREN LL_USART_ConfigLINMode
CR3 SCEN LL_USART_ConfigLINMode
CR3 HDSEL LL_USART_ConfigLINMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2344 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigMultiProcessMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Note:
In MultiProcessor mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Multi processor Mode (as Baud Rate, Wake Up Method, Node address, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigMultiProcessMode
CR2 CLKEN LL_USART_ConfigMultiProcessMode
CR3 SCEN LL_USART_ConfigMultiProcessMode
CR3 HDSEL LL_USART_ConfigMultiProcessMode
CR3 IREN LL_USART_ConfigMultiProcessMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2503 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSmartcardMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Smartcard Mode.

Note:
In Smartcard mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also configures Stop bits to 1.5 bits and sets the USART in Smartcard mode (SCEN bit). Clock Output is also enabled (CLKEN).
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
  • Set SCEN in CR3 using LL_USART_EnableSmartcard() function
Other remaining configurations items related to Smartcard Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSmartcardMode
CR2 STOP LL_USART_ConfigSmartcardMode
CR2 CLKEN LL_USART_ConfigSmartcardMode
CR3 HDSEL LL_USART_ConfigSmartcardMode
CR3 SCEN LL_USART_ConfigSmartcardMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2422 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Synchronous Mode.

Note:
In Synchronous mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the USART in Synchronous mode.
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
Other remaining configurations items related to Synchronous Mode (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSyncMode
CR2 CLKEN LL_USART_ConfigSyncMode
CR3 SCEN LL_USART_ConfigSyncMode
CR3 IREN LL_USART_ConfigSyncMode
CR3 HDSEL LL_USART_ConfigSyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2304 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
USART Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE (USART_TypeDef *USARTx)
Check if the USART Read Data Register Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE (USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.

Function Documentation

__STATIC_INLINE void LL_USART_ClearFlag_CM ( USART_TypeDef * USARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_USART_ClearFlag_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2926 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_EOB ( USART_TypeDef * USARTx )

Clear End Of Block Flag.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR EOBCF LL_USART_ClearFlag_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2915 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_FE ( USART_TypeDef * USARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_USART_ClearFlag_FE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2807 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_IDLE ( USART_TypeDef * USARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_USART_ClearFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2840 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_LBD ( USART_TypeDef * USARTx )

Clear LIN Break Detection Flag.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR LBDCF LL_USART_ClearFlag_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2878 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_nCTS ( USART_TypeDef * USARTx )

Clear CTS Interrupt Flag.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR CTSCF LL_USART_ClearFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2891 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_NE ( USART_TypeDef * USARTx )

Clear Noise detected Flag.

Reference Manual to LL API cross reference:
ICR NCF LL_USART_ClearFlag_NE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2818 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_ORE ( USART_TypeDef * USARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_USART_ClearFlag_ORE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2829 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_PE ( USART_TypeDef * USARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_USART_ClearFlag_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2796 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_RTO ( USART_TypeDef * USARTx )

Clear Receiver Time Out Flag.

Reference Manual to LL API cross reference:
ICR RTOCF LL_USART_ClearFlag_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2902 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TC ( USART_TypeDef * USARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_USART_ClearFlag_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2851 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_WKUP ( USART_TypeDef * USARTx )

Clear Wake Up from stop mode Flag.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR WUCF LL_USART_ClearFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2939 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR ( USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRF LL_USART_IsActiveFlag_ABR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2692 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE ( USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Error Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRE LL_USART_IsActiveFlag_ABRE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2679 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY ( USART_TypeDef * USARTx )

Check if the USART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_USART_IsActiveFlag_BUSY
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2703 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM ( USART_TypeDef * USARTx )

Check if the USART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_USART_IsActiveFlag_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2714 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS ( USART_TypeDef * USARTx )

Check if the USART CTS Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTS LL_USART_IsActiveFlag_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2642 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB ( USART_TypeDef * USARTx )

Check if the USART End Of Block Flag is set or not.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR EOBF LL_USART_IsActiveFlag_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2666 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE ( USART_TypeDef * USARTx )

Check if the USART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_USART_IsActiveFlag_FE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2537 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE ( USART_TypeDef * USARTx )

Check if the USART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_USART_IsActiveFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2570 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD ( USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Flag is set or not.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR LBDF LL_USART_IsActiveFlag_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2616 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS ( USART_TypeDef * USARTx )

Check if the USART CTS interrupt Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTSIF LL_USART_IsActiveFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2629 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE ( USART_TypeDef * USARTx )

Check if the USART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NF LL_USART_IsActiveFlag_NE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2548 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE ( USART_TypeDef * USARTx )

Check if the USART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_USART_IsActiveFlag_ORE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2559 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE ( USART_TypeDef * USARTx )

Check if the USART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_USART_IsActiveFlag_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2526 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK ( USART_TypeDef * USARTx )

Check if the USART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_USART_IsActiveFlag_REACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2771 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO ( USART_TypeDef * USARTx )

Check if the USART Receiver Time Out Flag is set or not.

Reference Manual to LL API cross reference:
ISR RTOF LL_USART_IsActiveFlag_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2653 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU ( USART_TypeDef * USARTx )

Check if the USART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_USART_IsActiveFlag_RWU
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2736 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE ( USART_TypeDef * USARTx )

Check if the USART Read Data Register Not Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXNE LL_USART_IsActiveFlag_RXNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2581 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK ( USART_TypeDef * USARTx )

Check if the USART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_USART_IsActiveFlag_SBK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2725 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC ( USART_TypeDef * USARTx )

Check if the USART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_USART_IsActiveFlag_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2592 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK ( USART_TypeDef * USARTx )

Check if the USART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_USART_IsActiveFlag_TEACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2760 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE ( USART_TypeDef * USARTx )

Check if the USART Transmit Data Register Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXE LL_USART_IsActiveFlag_TXE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2603 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP ( USART_TypeDef * USARTx )

Check if the USART Wake Up from stop mode Flag is set or not.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR WUF LL_USART_IsActiveFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2749 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IT_Management

Functions
IT_Management
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE (USART_TypeDef *USARTx)
Enable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE (USART_TypeDef *USARTx)
Enable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE (USART_TypeDef *USARTx)
Disable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE (USART_TypeDef *USARTx)
Disable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE (USART_TypeDef *USARTx)
Check if the USART RX Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE (USART_TypeDef *USARTx)
Check if the USART TX Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableIT_CM ( USART_TypeDef * USARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_DisableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3173 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_CTS ( USART_TypeDef * USARTx )

Disable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_DisableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3238 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_EOB ( USART_TypeDef * USARTx )

Disable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_DisableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3197 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_ERROR ( USART_TypeDef * USARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_DisableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3225 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_IDLE ( USART_TypeDef * USARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_DisableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3118 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_LBD ( USART_TypeDef * USARTx )

Disable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_DisableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3210 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_PE ( USART_TypeDef * USARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_DisableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3162 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RTO ( USART_TypeDef * USARTx )

Disable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_DisableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3184 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXNE ( USART_TypeDef * USARTx )

Disable RX Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_USART_DisableIT_RXNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3129 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TC ( USART_TypeDef * USARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_DisableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3140 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXE ( USART_TypeDef * USARTx )

Disable TX Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_USART_DisableIT_TXE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3151 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_WKUP ( USART_TypeDef * USARTx )

Disable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_DisableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3251 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CM ( USART_TypeDef * USARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_EnableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3013 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CTS ( USART_TypeDef * USARTx )

Enable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_EnableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3078 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_EOB ( USART_TypeDef * USARTx )

Enable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_EnableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3037 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_ERROR ( USART_TypeDef * USARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_EnableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3065 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_IDLE ( USART_TypeDef * USARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_EnableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2958 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_LBD ( USART_TypeDef * USARTx )

Enable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_EnableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3050 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_PE ( USART_TypeDef * USARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_EnableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3002 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RTO ( USART_TypeDef * USARTx )

Enable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_EnableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3024 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXNE ( USART_TypeDef * USARTx )

Enable RX Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_USART_EnableIT_RXNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2969 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TC ( USART_TypeDef * USARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_EnableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2980 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXE ( USART_TypeDef * USARTx )

Enable TX Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_USART_EnableIT_TXE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2991 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_WKUP ( USART_TypeDef * USARTx )

Enable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_EnableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3091 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM ( USART_TypeDef * USARTx )

Check if the USART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_IsEnabledIT_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3333 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS ( USART_TypeDef * USARTx )

Check if the USART CTS Interrupt is enabled or disabled.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_IsEnabledIT_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3394 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB ( USART_TypeDef * USARTx )

Check if the USART End Of Block Interrupt is enabled or disabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_IsEnabledIT_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3357 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR ( USART_TypeDef * USARTx )

Check if the USART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_USART_IsEnabledIT_ERROR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3381 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE ( USART_TypeDef * USARTx )

Check if the USART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3278 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD ( USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Interrupt is enabled or disabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_IsEnabledIT_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3370 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE ( USART_TypeDef * USARTx )

Check if the USART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_IsEnabledIT_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3322 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO ( USART_TypeDef * USARTx )

Check if the USART Receiver Timeout Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_IsEnabledIT_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3344 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE ( USART_TypeDef * USARTx )

Check if the USART RX Not Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3289 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC ( USART_TypeDef * USARTx )

Check if the USART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_IsEnabledIT_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3300 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE ( USART_TypeDef * USARTx )

Check if the USART TX Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_USART_IsEnabledIT_TXE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3311 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP ( USART_TypeDef * USARTx )

Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_IsEnabledIT_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3407 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA_Management

Functions
DMA_Management
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_DisableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3519 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_RX ( USART_TypeDef * USARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_DisableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3453 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_TX ( USART_TypeDef * USARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_DisableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3486 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_USART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_USART_DMA_GetRegAddr
Parameters:
USARTx USART Instance
Direction This parameter can be one of the following values:
  • LL_USART_DMA_REG_DATA_TRANSMIT
  • LL_USART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 3545 of file stm32l4xx_ll_usart.h.

References LL_USART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_EnableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3508 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_RX ( USART_TypeDef * USARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_EnableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3442 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_TX ( USART_TypeDef * USARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_EnableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3475 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr ( USART_TypeDef * USARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3530 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX ( USART_TypeDef * USARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_IsEnabledDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3464 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX ( USART_TypeDef * USARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_IsEnabledDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3497 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data_Management

Functions
Data_Management
USART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_USART_ReceiveData8 ( USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData8
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 3577 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE uint16_t LL_USART_ReceiveData9 ( USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData9
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 3588 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData8 | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData8
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 3600 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData9 | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData9
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 3612 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Execution

Functions
Execution
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data flush.

Function Documentation

__STATIC_INLINE void LL_USART_RequestAutoBaudRate ( USART_TypeDef * USARTx )

Request an Automatic Baud Rate measurement on next received data frame.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR ABRRQ LL_USART_RequestAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3633 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestBreakSending ( USART_TypeDef * USARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_USART_RequestBreakSending
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3644 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestEnterMuteMode ( USART_TypeDef * USARTx )

Put USART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_USART_RequestEnterMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3655 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestRxDataFlush ( USART_TypeDef * USARTx )

Request a Receive Data flush.

Reference Manual to LL API cross reference:
RQR RXFRQ LL_USART_RequestRxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3666 of file stm32l4xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestTxDataFlush ( USART_TypeDef * USARTx )

Request a Transmit data flush.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR TXFRQ LL_USART_RequestTxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3679 of file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Functions

ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Function Documentation

ErrorStatus LL_USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | LL_USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
USARTx USART Instance
USART_ClockInitStruct,: pointer to a LL_USART_ClockInitTypeDef structure that contains the Clock configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 343 of file stm32l4xx_ll_usart.c.

References assert_param, LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, IS_LL_USART_CLOCKOUTPUT, IS_LL_USART_CLOCKPHASE, IS_LL_USART_CLOCKPOLARITY, IS_LL_USART_LASTBITCLKOUTPUT, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_DisableSCLKOutput(), and LL_USART_IsEnabled().

void LL_USART_ClockStructInit ( LL_USART_ClockInitTypeDef * USART_ClockInitStruct )

Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Parameters:
USART_ClockInitStruct,: pointer to a LL_USART_ClockInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 402 of file stm32l4xx_ll_usart.c.

References LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_LASTCLKPULSE_NO_OUTPUT, LL_USART_PHASE_1EDGE, and LL_USART_POLARITY_LOW.

ErrorStatus LL_USART_DeInit ( USART_TypeDef * USARTx )

De-initialize USART registers (Registers restored to their default values).

Parameters:
USARTx USART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are de-initialized
  • ERROR: USART registers are not de-initialized

Definition at line 140 of file stm32l4xx_ll_usart.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_UART4, LL_APB1_GRP1_PERIPH_UART5, LL_APB1_GRP1_PERIPH_USART2, LL_APB1_GRP1_PERIPH_USART3, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_USART1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_USART_Init | ( | USART_TypeDef * | USARTx,
 |  | LL_USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initialize USART registers according to the specified parameters in USART_InitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
USARTx USART Instance
USART_InitStruct,: pointer to a LL_USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are initialized according to USART_InitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 214 of file stm32l4xx_ll_usart.c.

References assert_param, LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, IS_LL_USART_BAUDRATE, IS_LL_USART_DATAWIDTH, IS_LL_USART_DIRECTION, IS_LL_USART_HWCONTROL, IS_LL_USART_OVERSAMPLING, IS_LL_USART_PARITY, IS_LL_USART_STOPBITS, LL_RCC_GetUARTClockFreq(), LL_RCC_GetUSARTClockFreq(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_UART4_CLKSOURCE, LL_RCC_UART5_CLKSOURCE, LL_RCC_USART1_CLKSOURCE, LL_RCC_USART2_CLKSOURCE, LL_RCC_USART3_CLKSOURCE, LL_USART_IsEnabled(), LL_USART_SetBaudRate(), LL_USART_SetHWFlowCtrl(), LL_USART_SetStopBitsLength(), LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

void LL_USART_StructInit ( LL_USART_InitTypeDef * USART_InitStruct )

Set each LL_USART_InitTypeDef field to default value.

Parameters:
USART_InitStruct,: pointer to a LL_USART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 319 of file stm32l4xx_ll_usart.c.

References LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, LL_USART_DATAWIDTH_8B, LL_USART_DIRECTION_TX_RX, LL_USART_HWCONTROL_NONE, LL_USART_OVERSAMPLING_16, LL_USART_PARITY_NONE, LL_USART_STOPBITS_1, LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UTILS Private functions

Functions
UTILS Private functions
UTILS

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_SetFlashLatency (uint32_t HCLK_Frequency)
Update number of Flash wait states in line with new frequency and current voltage range.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.

Function Documentation

static ErrorStatus UTILS_EnablePLLAndSwitchSystem | ( | uint32_t | SYSCLK_Frequency,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  | [static]

Function to enable PLL and switch system clock to PLL.

Parameters:
SYSCLK_Frequency | SYSCLK frequency
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: No problem to switch system to PLL
  • ERROR: Problem to switch system to PLL

Definition at line 665 of file stm32l4xx_ll_utils.c.

References __LL_RCC_CALC_HCLK_FREQ, LL_UTILS_ClkInitTypeDef::AHBCLKDivider, LL_UTILS_ClkInitTypeDef::APB1CLKDivider, LL_UTILS_ClkInitTypeDef::APB2CLKDivider, assert_param, IS_LL_UTILS_APB1_DIV, IS_LL_UTILS_APB2_DIV, IS_LL_UTILS_SYSCLK_DIV, LL_RCC_GetSysClkSource(), LL_RCC_PLL_Enable(), LL_RCC_PLL_EnableDomain_SYS(), LL_RCC_PLL_IsReady(), LL_RCC_SetAHBPrescaler(), LL_RCC_SetAPB1Prescaler(), LL_RCC_SetAPB2Prescaler(), LL_RCC_SetSysClkSource(), LL_RCC_SYS_CLKSOURCE_PLL, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, LL_SetSystemCoreClock(), and UTILS_SetFlashLatency().

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and LL_PLL_ConfigSystemClock_MSI().

static uint32_t UTILS_GetPLLOutputFrequency | ( | uint32_t | PLL_InputFrequency,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct
 | ) |  | [static]

Function to check that PLL can be modified.

Parameters:
PLL_InputFrequency | PLL input frequency (in Hz)
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
Return values:
PLL output frequency (in Hz)

Definition at line 594 of file stm32l4xx_ll_utils.c.

References assert_param, IS_LL_UTILS_PLL_FREQUENCY, IS_LL_UTILS_PLLM_VALUE, IS_LL_UTILS_PLLN_VALUE, IS_LL_UTILS_PLLR_VALUE, IS_LL_UTILS_PLLVCO_INPUT, IS_LL_UTILS_PLLVCO_OUTPUT, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, RCC_POSITION_PLLM, RCC_POSITION_PLLN, and RCC_POSITION_PLLR.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and LL_PLL_ConfigSystemClock_MSI().

static ErrorStatus UTILS_PLL_IsBusy ( void ) [static]

Function to check that PLL can be modified.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PLL modification can be done
  • ERROR: PLL is busy

Definition at line 625 of file stm32l4xx_ll_utils.c.

References LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), and LL_RCC_PLLSAI2_IsReady().

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and LL_PLL_ConfigSystemClock_MSI().

static ErrorStatus UTILS_SetFlashLatency ( uint32_t HCLK_Frequency ) [static]

Update number of Flash wait states in line with new frequency and current voltage range.

Parameters:
HCLK_Frequency HCLK frequency
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Latency has been modified
  • ERROR: Latency cannot be modified

Definition at line 512 of file stm32l4xx_ll_utils.c.

References LL_FLASH_GetLatency(), LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3, LL_FLASH_LATENCY_4, LL_FLASH_SetLatency(), LL_PWR_GetRegulVoltageScaling(), LL_PWR_REGU_VOLTAGE_SCALE1, UTILS_SCALE1_LATENCY1_FREQ, UTILS_SCALE1_LATENCY2_FREQ, UTILS_SCALE1_LATENCY3_FREQ, UTILS_SCALE1_LATENCY4_FREQ, UTILS_SCALE2_LATENCY1_FREQ, UTILS_SCALE2_LATENCY2_FREQ, and UTILS_SCALE2_LATENCY3_FREQ.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UTILS Private Constants

Defines
UTILS Private Constants
UTILS

Defines

#define | UTILS_MAX_FREQUENCY_SCALE1 ((uint32_t)80000000)
#define | UTILS_MAX_FREQUENCY_SCALE2 ((uint32_t)26000000)
#define | UTILS_PLLVCO_INPUT_MIN ((uint32_t)4000000)
#define | UTILS_PLLVCO_INPUT_MAX ((uint32_t)16000000)
#define | UTILS_PLLVCO_OUTPUT_MIN ((uint32_t)64000000)
#define | UTILS_PLLVCO_OUTPUT_MAX ((uint32_t)344000000)
#define | UTILS_HSE_FREQUENCY_MIN ((uint32_t)4000000)
#define | UTILS_HSE_FREQUENCY_MAX ((uint32_t)48000000)
#define | UTILS_SCALE1_LATENCY1_FREQ ((uint32_t)16000000)
#define | UTILS_SCALE1_LATENCY2_FREQ ((uint32_t)32000000)
#define | UTILS_SCALE1_LATENCY3_FREQ ((uint32_t)48000000)
#define | UTILS_SCALE1_LATENCY4_FREQ ((uint32_t)64000000)
#define | UTILS_SCALE2_LATENCY1_FREQ ((uint32_t)6000000)
#define | UTILS_SCALE2_LATENCY2_FREQ ((uint32_t)12000000)
#define | UTILS_SCALE2_LATENCY3_FREQ ((uint32_t)18000000)
#define | LL_MAX_DELAY (uint32_t)0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.

Define Documentation

#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE

Flash size data register base address.

Definition at line 88 of file stm32l4xx_ll_utils.h.

Referenced by LL_GetFlashSize().

#define LL_MAX_DELAY (uint32_t)0xFFFFFFFFU

Definition at line 78 of file stm32l4xx_ll_utils.h.

Referenced by LL_mDelay().

#define PACKAGE_BASE_ADDRESS PACKAGE_BASE

Package data register base address.

Definition at line 93 of file stm32l4xx_ll_utils.h.

Referenced by LL_GetPackageType().

#define UID_BASE_ADDRESS UID_BASE

Unique device ID register base address.

Definition at line 83 of file stm32l4xx_ll_utils.h.

Referenced by LL_GetUID_Word0(), LL_GetUID_Word1(), and LL_GetUID_Word2().

#define UTILS_HSE_FREQUENCY_MAX ((uint32_t)48000000)

Frequency max for HSE frequency, in Hz

Definition at line 73 of file stm32l4xx_ll_utils.c.

#define UTILS_HSE_FREQUENCY_MIN ((uint32_t)4000000)

Frequency min for HSE frequency, in Hz

Definition at line 72 of file stm32l4xx_ll_utils.c.

#define UTILS_MAX_FREQUENCY_SCALE1 ((uint32_t)80000000)

Maximum frequency for system clock at power scale1, in Hz

Definition at line 62 of file stm32l4xx_ll_utils.c.

#define UTILS_MAX_FREQUENCY_SCALE2 ((uint32_t)26000000)

Maximum frequency for system clock at power scale2, in Hz

Definition at line 63 of file stm32l4xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MAX ((uint32_t)16000000)

Frequency max for PLLVCO input, in Hz

Definition at line 67 of file stm32l4xx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MIN ((uint32_t)4000000)

Frequency min for PLLVCO input, in Hz

Definition at line 66 of file stm32l4xx_ll_utils.c.

#define UTILS_PLLVCO_OUTPUT_MAX ((uint32_t)344000000)

Frequency max for PLLVCO output, in Hz

Definition at line 69 of file stm32l4xx_ll_utils.c.

#define UTILS_PLLVCO_OUTPUT_MIN ((uint32_t)64000000)

Frequency min for PLLVCO output, in Hz

Definition at line 68 of file stm32l4xx_ll_utils.c.

#define UTILS_SCALE1_LATENCY1_FREQ ((uint32_t)16000000)

HCLK frequency to set FLASH latency 1 in power scale 1

Definition at line 76 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_SCALE1_LATENCY2_FREQ ((uint32_t)32000000)

HCLK frequency to set FLASH latency 2 in power scale 1

Definition at line 77 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_SCALE1_LATENCY3_FREQ ((uint32_t)48000000)

HCLK frequency to set FLASH latency 3 in power scale 1

Definition at line 78 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_SCALE1_LATENCY4_FREQ ((uint32_t)64000000)

HCLK frequency to set FLASH latency 4 in power scale 1

Definition at line 79 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_SCALE2_LATENCY1_FREQ ((uint32_t)6000000)

HCLK frequency to set FLASH latency 1 in power scale 2

Definition at line 80 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_SCALE2_LATENCY2_FREQ ((uint32_t)12000000)

HCLK frequency to set FLASH latency 2 in power scale 2

Definition at line 81 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_SCALE2_LATENCY3_FREQ ((uint32_t)18000000)

HCLK frequency to set FLASH latency 3 in power scale 2

Definition at line 82 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UTILS Private Macros

Defines
UTILS Private Macros
UTILS

Defines

#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
#define | IS_LL_UTILS_PLLR_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Define Documentation

#define IS_LL_UTILS_APB1_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB1_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))

Definition at line 101 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_APB2_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB2_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))

Definition at line 107 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_HSE_BYPASS ( __STATE__ )
Value:
(((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))

Definition at line 136 of file stm32l4xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_HSE_FREQUENCY ( __FREQUENCY__ ) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Definition at line 139 of file stm32l4xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_PLL_FREQUENCY ( __VALUE__ )
Value:
((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))

Definition at line 133 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLM_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PLLM_DIV_1) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8))

Definition at line 113 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLN_VALUE ( __VALUE__ ) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))

Definition at line 122 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLR_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PLLR_DIV_2) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_8))

Definition at line 124 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLVCO_INPUT ( __VALUE__ ) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))

Definition at line 129 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLVCO_OUTPUT ( __VALUE__ ) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))

Definition at line 131 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_SYSCLK_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))

Definition at line 91 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_UTILS_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_PLLInitTypeDef Struct Reference
UTILS Exported structures

UTILS PLL structure definition. More...

#include <stm32l4xx_ll_utils.h>

Data Fields

uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLR

Detailed Description

UTILS PLL structure definition.

Definition at line 113 of file stm32l4xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_PLLInitTypeDef::PLLM

Division factor for PLL VCO input clock. This parameter can be a value of PLL, PLLSAI1 and PLLSAI2 division factor

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 115 of file stm32l4xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), LL_PLL_ConfigSystemClock_MSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLN

Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 121 of file stm32l4xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), LL_PLL_ConfigSystemClock_MSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLR

Division for the main system clock. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 127 of file stm32l4xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), LL_PLL_ConfigSystemClock_MSI(), and UTILS_GetPLLOutputFrequency().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_utils.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LL_UTILS_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_ClkInitTypeDef Struct Reference
UTILS Exported structures

UTILS System, AHB and APB buses clock configuration structure definition. More...

#include <stm32l4xx_ll_utils.h>

Data Fields

uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

UTILS System, AHB and APB buses clock configuration structure definition.

Definition at line 137 of file stm32l4xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB prescaler

This feature can be modified afterwards using unitary function LL_RCC_SetAHBPrescaler().

Definition at line 139 of file stm32l4xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB low-speed prescaler (APB1)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB1Prescaler().

Definition at line 145 of file stm32l4xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB high-speed prescaler (APB2)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB2Prescaler().

Definition at line 151 of file stm32l4xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

The documentation for this struct was generated from the following file:
  • stm32l4xx_ll_utils.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HSE Bypass activation

Defines
HSE Bypass activation
UTILS Exported Constants

Defines

#define | LL_UTILS_HSEBYPASS_OFF (uint32_t)0x00000000U
#define | LL_UTILS_HSEBYPASS_ON (uint32_t)0x00000001U

Define Documentation

#define LL_UTILS_HSEBYPASS_OFF (uint32_t)0x00000000U

HSE Bypass is not enabled

Definition at line 171 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_HSEBYPASS_ON (uint32_t)0x00000001U

HSE Bypass is enabled

Definition at line 172 of file stm32l4xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PACKAGE TYPE

Defines
PACKAGE TYPE
UTILS Exported Constants

Defines

#define | LL_UTILS_PACKAGETYPE_LQFP64 (uint32_t)0x00000000U
#define | LL_UTILS_PACKAGETYPE_WLCSP64 (uint32_t)0x00000001U
#define | LL_UTILS_PACKAGETYPE_LQFP100 (uint32_t)0x00000002U
#define | LL_UTILS_PACKAGETYPE_BGA132 (uint32_t)0x00000003U
#define | LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (uint32_t)0x00000004U
#define | LL_UTILS_PACKAGETYPE_UFQFPN32 (uint32_t)0x00000008U
#define | LL_UTILS_PACKAGETYPE_UFQFPN48 (uint32_t)0x0000000AU
#define | LL_UTILS_PACKAGETYPE_LQFP48 (uint32_t)0x0000000BU
#define | LL_UTILS_PACKAGETYPE_WLCSP49 (uint32_t)0x0000000CU
#define | LL_UTILS_PACKAGETYPE_UFBGA64 (uint32_t)0x0000000DU
#define | LL_UTILS_PACKAGETYPE_UFBGA100 (uint32_t)0x0000000EU

Define Documentation

#define LL_UTILS_PACKAGETYPE_BGA132 (uint32_t)0x00000003U

BGA132 package type

Definition at line 183 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP100 (uint32_t)0x00000002U

LQFP100 package type

Definition at line 182 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (uint32_t)0x00000004U

LQFP144, WLCSP81 or WLCSP72 package type

Definition at line 184 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP48 (uint32_t)0x0000000BU

LQFP48 package type

Definition at line 187 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_LQFP64 (uint32_t)0x00000000U

LQFP64 package type

Definition at line 180 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFBGA100 (uint32_t)0x0000000EU

UFBGA100 package type

Definition at line 190 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFBGA64 (uint32_t)0x0000000DU

UFBGA64 package type

Definition at line 189 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFQFPN32 (uint32_t)0x00000008U

UFQFPN32 package type

Definition at line 185 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_UFQFPN48 (uint32_t)0x0000000AU

UFQFPN48 package type

Definition at line 186 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_WLCSP49 (uint32_t)0x0000000CU

WLCSP49 package type

Definition at line 188 of file stm32l4xx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_WLCSP64 (uint32_t)0x00000001U

WLCSP64 package type

Definition at line 181 of file stm32l4xx_ll_utils.h.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DEVICE ELECTRONIC SIGNATURE

Functions
DEVICE ELECTRONIC SIGNATURE
UTILS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE uint32_t | LL_GetPackageType (void)
Get Package type.

Function Documentation

__STATIC_INLINE uint32_t LL_GetFlashSize ( void )

Get Flash memory size.

Note:
This bitfield indicates the size of the device Flash memory expressed in Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
Return values:
FLASH_SIZE[15:0],: Flash memory size

Definition at line 243 of file stm32l4xx_ll_utils.h.

References FLASHSIZE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetPackageType ( void )

Get Package type.

Return values:
Returned value can be one of the following values:
  • LL_UTILS_PACKAGETYPE_LQFP64 (*)
  • LL_UTILS_PACKAGETYPE_LQFP100 (*)
  • LL_UTILS_PACKAGETYPE_BGA132 (*)
  • LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (*)
  • LL_UTILS_PACKAGETYPE_UFQFPN32 (*)
  • LL_UTILS_PACKAGETYPE_UFQFPN48 (*)
  • LL_UTILS_PACKAGETYPE_LQFP48 (*)
  • LL_UTILS_PACKAGETYPE_WLCSP49 (*)
  • LL_UTILS_PACKAGETYPE_UFBGA64 (*)
  • LL_UTILS_PACKAGETYPE_UFBGA100 (*)
(*) value not defined in all devices.

Definition at line 264 of file stm32l4xx_ll_utils.h.

References PACKAGE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word0 ( void )

Get Word0 of the unique device identifier (UID based on 96 bits)

Return values:
UID[31:0],: X and Y coordinates on the wafer expressed in BCD format

Definition at line 214 of file stm32l4xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word1 ( void )

Get Word1 of the unique device identifier (UID based on 96 bits)

Return values:
UID[63:32],: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])

Definition at line 223 of file stm32l4xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word2 ( void )

Get Word2 of the unique device identifier (UID based on 96 bits)

Return values:
UID[95:64],: Lot number (ASCII encoded) - LOT_NUM[55:24]

Definition at line 232 of file stm32l4xx_ll_utils.h.

References UID_BASE_ADDRESS.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DELAY

Functions
DELAY
UTILS Exported Functions

Functions

void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.

Function Documentation

void LL_Init1msTick ( uint32_t HCLKFrequency )

This function configures the Cortex-M SysTick source to have 1ms time base.

Note:
When a RTOS is used, it is recommended to avoid changing the Systick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
HCLKFrequency HCLK frequency in Hz
Note:
HCLK frequency can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq
Return values:
None

Definition at line 173 of file stm32l4xx_ll_utils.c.

References LL_InitTick().

__STATIC_INLINE void LL_InitTick | ( | uint32_t | HCLKFrequency,
 |  | uint32_t | Ticks
 | ) |  |

This function configures the Cortex-M SysTick source of the time base.

Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Note:
When a RTOS is used, it is recommended to avoid changing the SysTick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
Ticks Number of ticks
Return values:
None

Definition at line 285 of file stm32l4xx_ll_utils.h.

Referenced by LL_Init1msTick().

void LL_mDelay ( uint32_t Delay )

This function provides accurate delay (in milliseconds) based on SysTick counter flag.

Note:
When a RTOS is used, it is recommended to avoid using blocking delay and use rather osDelay service.
To respect 1ms timebase, user should call LL_Init1msTick function which will configure Systick to 1ms
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 189 of file stm32l4xx_ll_utils.c.

References LL_MAX_DELAY.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSTEM

Functions
SYSTEM
UTILS Exported Functions

System Configuration functions. More...

Functions

void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_MSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with MSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

System Configuration functions.

 ===============================================================================
           ##### System Configuration functions #####
 ===============================================================================
    [..]
         System, AHB and APB buses clocks configuration

         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80000000 Hz.

Function Documentation

ErrorStatus LL_PLL_ConfigSystemClock_HSE | ( | uint32_t | HSEFrequency,
 |  | uint32_t | HSEBypass,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with HSE as clock source of the PLL.

Note:
The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
Function is based on the following formula:
  • PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
  • PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLR: ensure that max frequency at 80 MHz is reach (PLLVCO_output / PLLR)
Parameters:
HSEFrequency | Value between Min_Data = 4000000 and Max_Data = 48000000
HSEBypass This parameter can be one of the following values:
  • LL_UTILS_HSEBYPASS_ON
  • LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 440 of file stm32l4xx_ll_utils.c.

References assert_param, IS_LL_UTILS_HSE_BYPASS, IS_LL_UTILS_HSE_FREQUENCY, LL_RCC_HSE_DisableBypass(), LL_RCC_HSE_Enable(), LL_RCC_HSE_EnableBypass(), LL_RCC_HSE_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSI, LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_HSI | ( | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock at maximum frequency with HSI as clock source of the PLL.

Note:
The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
Function is based on the following formula:
  • PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
  • PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLR: ensure that max frequency at 80 MHz is reach (PLLVCO_output / PLLR)
Parameters:
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 382 of file stm32l4xx_ll_utils.c.

References HSI_VALUE, LL_RCC_HSI_Enable(), LL_RCC_HSI_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSI, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_MSI | ( | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with MSI as clock source of the PLL.

Note:
The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
Function is based on the following formula:
  • PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
  • PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLR: ensure that max frequency at 80 MHz is reach (PLLVCO_output / PLLR)
Parameters:
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 279 of file stm32l4xx_ll_utils.c.

References __LL_RCC_CALC_MSI_FREQ, LL_RCC_MSI_Enable(), LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_MSI_IsReady(), LL_RCC_MSIRANGE_0, LL_RCC_MSIRANGE_1, LL_RCC_MSIRANGE_10, LL_RCC_MSIRANGE_11, LL_RCC_MSIRANGE_2, LL_RCC_MSIRANGE_3, LL_RCC_MSIRANGE_4, LL_RCC_MSIRANGE_5, LL_RCC_MSIRANGE_6, LL_RCC_MSIRANGE_7, LL_RCC_MSIRANGE_8, LL_RCC_MSIRANGE_9, LL_RCC_MSISRANGE_4, LL_RCC_MSISRANGE_5, LL_RCC_MSISRANGE_6, LL_RCC_MSISRANGE_7, LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_MSI, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

void LL_SetSystemCoreClock ( uint32_t HCLKFrequency )

This function sets directly SystemCoreClock CMSIS variable.

Note:
Variable can be calculated also through SystemCoreClockUpdate function.
Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Return values:
None

Definition at line 257 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

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STM32L486xx HAL User Manual: WWDG

Modules
WWDG
STM32L4xx_LL_Driver

Modules

WWDG Exported Constants
WWDG Exported Macros
WWDG Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for WWDG registers.

Register | Bit | Function
CFR | EWI | LL_WWDG_EnableIT_EWKUP
 |  | LL_WWDG_IsEnabledIT_EWKUP
 | W | LL_WWDG_GetWindow
 |  | LL_WWDG_SetWindow
 | WDGTB | LL_WWDG_GetPrescaler
 |  | LL_WWDG_SetPrescaler
CR | T | LL_WWDG_GetCounter
 |  | LL_WWDG_SetCounter
 | WDGA | LL_WWDG_Enable
 |  | LL_WWDG_IsEnabled
SR | EWIF | LL_WWDG_ClearFlag_EWKUP
 |  | LL_WWDG_IsActiveFlag_EWKUP
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STM32L486xx HAL User Manual: IT Defines

Defines
IT Defines
WWDG Exported Constants

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions. More...

Defines

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Detailed Description

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

Define Documentation

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Definition at line 77 of file stm32l4xx_ll_wwdg.h.

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STM32L486xx HAL User Manual: PRESCALER

Defines
PRESCALER
WWDG Exported Constants

Defines

#define | LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)

Define Documentation

#define LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U

WWDG counter clock = (PCLK1/4096)/1

Definition at line 85 of file stm32l4xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 86 of file stm32l4xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 87 of file stm32l4xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 88 of file stm32l4xx_ll_wwdg.h.

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STM32L486xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
WWDG Exported Macros

Defines

#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Define Documentation

#define LL_WWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 119 of file stm32l4xx_ll_wwdg.h.

#define LL_WWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 111 of file stm32l4xx_ll_wwdg.h.

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STM32L486xx HAL User Manual: Configuration

Functions
Configuration
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)

Function Documentation

__STATIC_INLINE void LL_WWDG_Enable ( WWDG_TypeDef * WWDGx )

Enable Window Watchdog.

The watchdog is always disabled after a reset.

Note:
It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_Enable
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 147 of file stm32l4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetCounter ( WWDG_TypeDef * WWDGx )

Return current Watchdog Counter Value (7 bits counter value)

Reference Manual to LL API cross reference:
CR T LL_WWDG_GetCounter
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Counter value

Definition at line 185 of file stm32l4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler ( WWDG_TypeDef * WWDGx )

Return current Watchdog Prescaler Value.

Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_GetPrescaler
Parameters:
WWDGx WWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8

Definition at line 218 of file stm32l4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetWindow ( WWDG_TypeDef * WWDGx )

Return current Watchdog Window Value (7 bits value)

Reference Manual to LL API cross reference:
CFR W LL_WWDG_GetWindow
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Window value

Definition at line 250 of file stm32l4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabled ( WWDG_TypeDef * WWDGx )

Checks if Window Watchdog is enabled.

Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_IsEnabled
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 158 of file stm32l4xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetCounter | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Counter
 | ) |  |

Set the Watchdog counter value to provided value (7-bits T[6:0])

Note:
When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset This counter is decremented every (4096 x 2expWDGTB) PCLK cycles A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
Reference Manual to LL API cross reference:
CR T LL_WWDG_SetCounter
Parameters:
WWDGx | WWDG Instance
Counter | 0..0x7F (7 bit counter value)
Return values:
None

Definition at line 174 of file stm32l4xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetPrescaler | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the time base of the prescaler (WDGTB).

Note:
Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter is decremented every (4096 x 2expWDGTB) PCLK cycles
Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_SetPrescaler
Parameters:
WWDGx WWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
Return values:
None

Definition at line 203 of file stm32l4xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetWindow | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Window
 | ) |  |

Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).

Note:
This window value defines when write in the WWDG_CR register to program Watchdog counter is allowed. Watchdog counter value update must occur only when the counter value is lower than the Watchdog window register value. Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value (in the control register) is refreshed before the downcounter has reached the watchdog window register value. Physically is possible to set the Window lower then 0x40 but it is not recommended. To generate an immediate reset, it is possible to set the Counter lower than 0x40.
Reference Manual to LL API cross reference:
CFR W LL_WWDG_SetWindow
Parameters:
WWDGx | WWDG Instance
Window | 0x00..0x7F (7 bit Window value)
Return values:
None

Definition at line 239 of file stm32l4xx_ll_wwdg.h.

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STM32L486xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
WWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Function Documentation

__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_ClearFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 282 of file stm32l4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.

Note:
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_IsActiveFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 271 of file stm32l4xx_ll_wwdg.h.

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STM32L486xx HAL User Manual: IT_Management

Functions
IT_Management
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP ( WWDG_TypeDef * WWDGx )

Enable the Early Wakeup Interrupt.

Note:
When set, an interrupt occurs whenever the counter reaches value 0x40. This interrupt is only cleared by hardware after a reset
Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_EnableIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 302 of file stm32l4xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP ( WWDG_TypeDef * WWDGx )

Check if Early Wakeup Interrupt is enabled.

Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_IsEnabledIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 313 of file stm32l4xx_ll_wwdg.h.

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STM32L486xx HAL User Manual: Initialization and de-initialization Functions

Functions
Initialization and de-initialization Functions
HAL Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_Init (void)
Configure the Flash prefetch, the Instruction and Data caches, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32l4xx_hal_msp.c.
HAL_StatusTypeDef | HAL_DeInit (void)
De-initialize common part of the HAL and stop the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitialize the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the Flash interface the NVIC allocation and initial time base
          clock configuration.
      (+) De-initialize common part of the HAL.
      (+) Configure the time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) SysTick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __weak
             to make  override possible  in case of other  implementations in user file.

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

De-initialize common part of the HAL and stop the source of time base.

Note:
This function is optional.
Return values:
HAL status

Definition at line 196 of file stm32l4xx_hal.c.

References __HAL_RCC_AHB1_FORCE_RESET, __HAL_RCC_AHB1_RELEASE_RESET, __HAL_RCC_AHB2_FORCE_RESET, __HAL_RCC_AHB2_RELEASE_RESET, __HAL_RCC_AHB3_FORCE_RESET, __HAL_RCC_AHB3_RELEASE_RESET, __HAL_RCC_APB1_FORCE_RESET, __HAL_RCC_APB1_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, and HAL_MspDeInit().

HAL_StatusTypeDef HAL_Init ( void )

Configure the Flash prefetch, the Instruction and Data caches, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32l4xx_hal_msp.c.

Note:
HAL_Init() function is called at the beginning of program after reset and before the clock configuration.
In the default implementation the System Timer (Systick) is used as source of time base. The Systick configuration is based on MSI clock, as MSI is the clock used after a system Reset and the NVIC configuration is set to Priority group 4. Once done, time base tick starts incrementing: the tick variable counter is incremented each 1ms in the SysTick_Handler() interrupt handler.
Return values:
HAL status

Definition at line 159 of file stm32l4xx_hal.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_PREFETCH_BUFFER_ENABLE, HAL_InitTick(), HAL_MspInit(), HAL_NVIC_SetPriorityGrouping(), NVIC_PRIORITYGROUP_4, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority,: Tick interrupt priority.
Return values:
HAL status

Definition at line 259 of file stm32l4xx_hal.c.

References HAL_NVIC_SetPriority(), and HAL_SYSTICK_Config().

Referenced by HAL_Init(), HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

void HAL_MspDeInit ( void )

DeInitialize the MSP.

Return values:
None

Definition at line 236 of file stm32l4xx_hal.c.

Referenced by HAL_DeInit().

void HAL_MspInit ( void )

Initialize the MSP.

Return values:
None

Definition at line 225 of file stm32l4xx_hal.c.

Referenced by HAL_Init().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HAL Control functions

Functions
HAL Control functions
HAL Exported Functions

HAL Control functions. More...

Functions

__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provide a tick value in millisecond.
__weak void | HAL_Delay (uint32_t Delay)
Provide accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Return the HAL revision.
uint32_t | HAL_GetREVID (void)
Return the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Return the device identifier.

Detailed Description

HAL Control functions.

 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device identifier
      (+) Get the device revision identifier

Function Documentation

void HAL_Delay ( uint32_t Delay )

Provide accurate delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters:
Delay,: specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 330 of file stm32l4xx_hal.c.

References HAL_GetTick().

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMPEx_SelfCalibrateAll(), HAL_PCDEx_BCD_VBUSDetect(), and SD_PowerON().

uint32_t HAL_GetDEVID ( void )

Return the device identifier.

Return values:
Device identifier

Definition at line 393 of file stm32l4xx_hal.c.

uint32_t HAL_GetHalVersion ( void )

Return the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 375 of file stm32l4xx_hal.c.

References __STM32L4xx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Return the device revision identifier.

Return values:
Device revision identifier

Definition at line 384 of file stm32l4xx_hal.c.

uint32_t HAL_GetTick ( void )

Provide a tick value in millisecond.

Note:
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 315 of file stm32l4xx_hal.c.

References uwTick.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), CRYP_WaitOnBusyFlagReset(), CRYP_WaitOnCCFlag(), FLASH_WaitForLastOperation(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_CAN_Init(), HAL_CAN_Receive(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_WakeUp(), HAL_DAC_ConfigChannel(), HAL_Delay(), HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DMA_PollForTransfer(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), HAL_IWDG_Init(), HAL_LCD_Clear(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), HAL_LCD_Write(), HAL_NAND_Erase_Block(), HAL_NAND_Write_Page(), HAL_NAND_Write_SpareArea(), HAL_NOR_GetStatus(), HAL_PCDEx_BCD_VBUSDetect(), HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Transmit(), HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_DisablePLLSAI1(), HAL_RCCEx_DisablePLLSAI2(), HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_EnablePLLSAI2(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_GenerateRandomNumber(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), HAL_SMBUS_IsDeviceReady(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SWPMI_Receive(), HAL_SWPMI_Transmit(), HAL_SYSCFG_EnableVREFBUF(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), IRDA_CheckIdleState(), IRDA_WaitOnFlagUntilTimeout(), LCD_WaitForSynchro(), QSPI_WaitFlagStateUntilTimeout(), RCCEx_PLLSAI1_Config(), RCCEx_PLLSAI2_Config(), RTC_EnterInitMode(), SAI_Disable(), SMARTCARD_CheckIdleState(), SMARTCARD_WaitOnFlagUntilTimeout(), SMBUS_WaitOnFlagUntilTimeout(), SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), SWPMI_DMATransmitCplt(), SWPMI_WaitOnFlagSetUntilTimeout(), UART_CheckIdleState(), UART_WaitOnFlagUntilTimeout(), USART_CheckIdleState(), and USART_WaitOnFlagUntilTimeout().

void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in SysTick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 304 of file stm32l4xx_hal.c.

References uwTick.

void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 365 of file stm32l4xx_hal.c.

void HAL_SuspendTick ( void )

Suspend Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 349 of file stm32l4xx_hal.c.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HAL Debug functions

Functions
HAL Debug functions
HAL Exported Functions

HAL Debug functions. More...

Functions

void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.

Detailed Description

HAL Debug functions.

 ===============================================================================
                      ##### HAL Debug functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Enable/Disable Debug module during SLEEP mode
      (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
      (+) Enable/Disable Debug module during STANDBY mode

Function Documentation

void HAL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 431 of file stm32l4xx_hal.c.

void HAL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 467 of file stm32l4xx_hal.c.

void HAL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP0/STOP1/STOP2 modes.

Return values:
None

Definition at line 449 of file stm32l4xx_hal.c.

void HAL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 422 of file stm32l4xx_hal.c.

void HAL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 458 of file stm32l4xx_hal.c.

void HAL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP0/STOP1/STOP2 modes.

Return values:
None

Definition at line 440 of file stm32l4xx_hal.c.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HAL SYSCFG configuration functions

Functions
HAL SYSCFG configuration functions
HAL Exported Functions

HAL SYSCFG configuration functions. More...

Functions

void | HAL_SYSCFG_SRAM2Erase (void)
Start a hardware SRAM2 erase operation.
void | HAL_SYSCFG_EnableMemorySwappingBank (void)
Enable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_DisableMemorySwappingBank (void)
Disable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOAnalogSwitchBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOAnalogSwitchBooster (void)
Disable the I/O analog switch voltage booster.

Detailed Description

HAL SYSCFG configuration functions.

 ===============================================================================
                      ##### HAL SYSCFG configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a hardware SRAM2 erase operation
      (+) Enable/Disable the Internal FLASH Bank Swapping
      (+) Configure the Voltage reference buffer
      (+) Enable/Disable the Voltage reference buffer
      (+) Enable/Disable the I/O analog switch voltage booster

Function Documentation

void HAL_SYSCFG_DisableIOAnalogSwitchBooster ( void )

Disable the I/O analog switch voltage booster.

Return values:
None

Definition at line 638 of file stm32l4xx_hal.c.

void HAL_SYSCFG_DisableMemorySwappingBank ( void )

Disable the Internal FLASH Bank Swapping.

Note:
This function can be used only for STM32L4xx devices.
The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
Return values:
None

Definition at line 534 of file stm32l4xx_hal.c.

References FB_MODE_BB.

void HAL_SYSCFG_DisableVREFBUF ( void )

Disable the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 617 of file stm32l4xx_hal.c.

void HAL_SYSCFG_EnableIOAnalogSwitchBooster ( void )

Enable the I/O analog switch voltage booster.

Return values:
None

Definition at line 628 of file stm32l4xx_hal.c.

void HAL_SYSCFG_EnableMemorySwappingBank ( void )

Enable the Internal FLASH Bank Swapping.

Note:
This function can be used only for STM32L4xx devices.
Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
Return values:
None

Definition at line 519 of file stm32l4xx_hal.c.

References FB_MODE_BB.

HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF ( void )

Enable the Internal Voltage Reference buffer (VREFBUF).

Return values:
HAL_OK/HAL_TIMEOUT

Definition at line 591 of file stm32l4xx_hal.c.

References HAL_GetTick(), and VREFBUF_TIMEOUT_VALUE.

void HAL_SYSCFG_SRAM2Erase ( void )

Start a hardware SRAM2 erase operation.

Note:
As long as SRAM2 is not erased the SRAM2ER bit will be set. This bit is automatically reset at the end of the SRAM2 erase operation.
Return values:
None

Definition at line 500 of file stm32l4xx_hal.c.

References SCSR_SRAM2ER_BB.

void HAL_SYSCFG_VREFBUF_HighImpedanceConfig ( uint32_t Mode )

Configure the internal voltage reference buffer high impedance mode.

Parameters:
Mode,: specifies the high impedance mode This parameter can be one of the following values:
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
Return values:
None

Definition at line 567 of file stm32l4xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE.

void HAL_SYSCFG_VREFBUF_TrimmingConfig ( uint32_t TrimmingValue )

Tune the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 579 of file stm32l4xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_TRIMMING.

void HAL_SYSCFG_VREFBUF_VoltageScalingConfig ( uint32_t VoltageScaling )

Configure the internal voltage reference buffer voltage scale.

Parameters:
VoltageScaling,: specifies the output voltage to achieve This parameter can be one of the following values:
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
Return values:
None

Definition at line 551 of file stm32l4xx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_VOLTAGE_SCALE.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Boot Mode

Defines
Boot Mode
SYSCFG Exported Constants

Defines

#define | SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
#define | SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#define | SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1
#define | SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#define | SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)

Define Documentation

#define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1

Definition at line 70 of file stm32l4xx_hal.h.

#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)

Definition at line 67 of file stm32l4xx_hal.h.

#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)

Definition at line 73 of file stm32l4xx_hal.h.

#define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)

Definition at line 72 of file stm32l4xx_hal.h.

#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0

Definition at line 68 of file stm32l4xx_hal.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FPU Interrupts

Defines
FPU Interrupts
SYSCFG Exported Constants

Defines

#define | SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0
#define | SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1
#define | SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2
#define | SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3
#define | SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4
#define | SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5

Define Documentation

#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1

Floating Point Unit Divide-by-zero Interrupt

Definition at line 83 of file stm32l4xx_hal.h.

#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4

Floating Point Unit Input denormal Interrupt

Definition at line 86 of file stm32l4xx_hal.h.

#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0

Floating Point Unit Invalid operation Interrupt

Definition at line 82 of file stm32l4xx_hal.h.

#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5

Floating Point Unit Inexact Interrupt

Definition at line 87 of file stm32l4xx_hal.h.

#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3

Floating Point Unit Overflow Interrupt

Definition at line 85 of file stm32l4xx_hal.h.

#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2

Floating Point Unit Underflow Interrupt

Definition at line 84 of file stm32l4xx_hal.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SRAM2 Write protection

Defines
SRAM2 Write protection
SYSCFG Exported Constants

Defines

#define | SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0
#define | SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1
#define | SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2
#define | SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3
#define | SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4
#define | SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5
#define | SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6
#define | SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7
#define | SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8
#define | SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9
#define | SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10
#define | SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11
#define | SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12
#define | SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13
#define | SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14
#define | SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15
#define | SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16
#define | SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17
#define | SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18
#define | SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19
#define | SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20
#define | SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21
#define | SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22
#define | SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23
#define | SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24
#define | SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25
#define | SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26
#define | SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27
#define | SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28
#define | SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29
#define | SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30
#define | SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31

Define Documentation

#define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0

SRAM2 Write protection page 0

Definition at line 96 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1

SRAM2 Write protection page 1

Definition at line 97 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10

SRAM2 Write protection page 10

Definition at line 106 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11

SRAM2 Write protection page 11

Definition at line 107 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12

SRAM2 Write protection page 12

Definition at line 108 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13

SRAM2 Write protection page 13

Definition at line 109 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14

SRAM2 Write protection page 14

Definition at line 110 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15

SRAM2 Write protection page 15

Definition at line 111 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16

SRAM2 Write protection page 16

Definition at line 112 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17

SRAM2 Write protection page 17

Definition at line 113 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18

SRAM2 Write protection page 18

Definition at line 114 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19

SRAM2 Write protection page 19

Definition at line 115 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2

SRAM2 Write protection page 2

Definition at line 98 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20

SRAM2 Write protection page 20

Definition at line 116 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21

SRAM2 Write protection page 21

Definition at line 117 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22

SRAM2 Write protection page 22

Definition at line 118 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23

SRAM2 Write protection page 23

Definition at line 119 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24

SRAM2 Write protection page 24

Definition at line 120 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25

SRAM2 Write protection page 25

Definition at line 121 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26

SRAM2 Write protection page 26

Definition at line 122 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27

SRAM2 Write protection page 27

Definition at line 123 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28

SRAM2 Write protection page 28

Definition at line 124 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29

SRAM2 Write protection page 29

Definition at line 125 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3

SRAM2 Write protection page 3

Definition at line 99 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30

SRAM2 Write protection page 30

Definition at line 126 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31

SRAM2 Write protection page 31

Definition at line 127 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4

SRAM2 Write protection page 4

Definition at line 100 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5

SRAM2 Write protection page 5

Definition at line 101 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6

SRAM2 Write protection page 6

Definition at line 102 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7

SRAM2 Write protection page 7

Definition at line 103 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8

SRAM2 Write protection page 8

Definition at line 104 of file stm32l4xx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9

SRAM2 Write protection page 9

Definition at line 105 of file stm32l4xx_hal.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: VREFBUF Voltage Scale

Defines
VREFBUF Voltage Scale
SYSCFG Exported Constants

Defines

#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS

Define Documentation

#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)

Voltage reference scale 0 (VREF_OUT1)

Definition at line 137 of file stm32l4xx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS

Voltage reference scale 1 (VREF_OUT2)

Definition at line 138 of file stm32l4xx_hal.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: VREFBUF High Impedance

Defines
VREFBUF High Impedance
SYSCFG Exported Constants

Defines

#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000)
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

Define Documentation

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000)

VREF_plus pin is internally connected to Voltage reference buffer output

Definition at line 147 of file stm32l4xx_hal.h.

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

VREF_plus pin is high impedance

Definition at line 148 of file stm32l4xx_hal.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Flags

Defines
Flags
SYSCFG Exported Constants

Defines

#define | SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF
#define | SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY

Define Documentation

#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY

SRAM2 busy by erase operation

Definition at line 160 of file stm32l4xx_hal.h.

#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF

SRAM2 parity error

Definition at line 159 of file stm32l4xx_hal.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Fast-mode Plus on GPIO

Defines
Fast-mode Plus on GPIO
SYSCFG Exported Constants

Defines

#define | SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
Fast-mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Define Documentation

#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Fast-mode Plus driving capability on a specific GPIO.

Enable Fast-mode Plus on PB6

Definition at line 172 of file stm32l4xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast-mode Plus on PB7

Definition at line 173 of file stm32l4xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast-mode Plus on PB8

Definition at line 175 of file stm32l4xx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast-mode Plus on PB9

Definition at line 178 of file stm32l4xx_hal.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DBGMCU Exported Macros

Defines
DBGMCU Exported Macros
HAL

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define | __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
#define | __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)

Define Documentation

#define __HAL_DBGMCU_FREEZE_CAN1 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)

Definition at line 258 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)

Definition at line 243 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)

Definition at line 248 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)

Definition at line 253 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_IWDG ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)

Definition at line 238 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM1 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)

Definition at line 263 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM2 ( ) SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)

Definition at line 268 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_RTC ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)

Definition at line 228 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM1 ( ) SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)

Definition at line 273 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM15 ( ) SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)

Definition at line 283 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM16 ( ) SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)

Definition at line 288 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM17 ( ) SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)

Definition at line 293 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM2 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)

Freeze/Unfreeze Peripherals in Debug mode.

Definition at line 198 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM3 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)

Definition at line 203 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM4 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)

Definition at line 208 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM5 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)

Definition at line 213 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM6 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)

Definition at line 218 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM7 ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)

Definition at line 223 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM8 ( ) SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)

Definition at line 278 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_FREEZE_WWDG ( ) SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)

Definition at line 233 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_CAN1 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)

Definition at line 259 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)

Definition at line 244 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)

Definition at line 249 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)

Definition at line 254 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_IWDG ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)

Definition at line 239 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_LPTIM1 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)

Definition at line 264 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_LPTIM2 ( ) CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)

Definition at line 269 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_RTC ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)

Definition at line 229 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM1 ( ) CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)

Definition at line 274 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM15 ( ) CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)

Definition at line 284 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM16 ( ) CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)

Definition at line 289 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM17 ( ) CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)

Definition at line 294 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM2 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)

Definition at line 199 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM3 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)

Definition at line 204 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM4 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)

Definition at line 209 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM5 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)

Definition at line 214 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM6 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)

Definition at line 219 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM7 ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)

Definition at line 224 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM8 ( ) CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)

Definition at line 279 of file stm32l4xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_WWDG ( ) CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)

Definition at line 234 of file stm32l4xx_hal.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSCFG Exported Macros

Defines
SYSCFG Exported Macros
HAL

Defines

#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
Embedded SRAM mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
QUADSPI mapped at 0x00000000.
#define | __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
Return the boot mode as configured by user.
#define | __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__)
SRAM2 page write protection enable macro.
#define | __HAL_SYSCFG_SRAM2_WRP_UNLOCK()
SRAM2 page write protection unlock prior to erase.
#define | __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
SRAM2 erase.
#define | __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)
Floating Point Unit interrupt enable/disable macros.
#define | __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)
#define | __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
SYSCFG Break ECC lock.
#define | __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
SYSCFG Break Cortex-M4 Lockup lock.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
SYSCFG Break PVD lock.
#define | __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
SYSCFG Break SRAM2 parity lock.
#define | __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
Check SYSCFG flag is set or not.
#define | __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
Set the SPF bit to clear the SRAM Parity Error Flag.
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast-mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)

Define Documentation

#define __HAL_SYSCFG_BREAK_ECC_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)

SYSCFG Break ECC lock.

Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 376 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)

SYSCFG Break Cortex-M4 Lockup lock.

Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 382 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_BREAK_PVD_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)

SYSCFG Break PVD lock.

Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 388 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)

SYSCFG Break SRAM2 parity lock.

Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.

Note:
The selected configuration is locked and can be unlocked by system reset.

Definition at line 394 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_CLEAR_FLAG ( ) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)

Set the SPF bit to clear the SRAM Parity Error Flag.

Definition at line 407 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
                                                               }while(0)

Definition at line 420 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
                                                               }while(0)

Fast-mode Plus driving capability enable/disable macros.

Parameters:
__FASTMODEPLUS__,: This parameter can be a value of :
  • SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
  • SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
  • SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
  • SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9

Definition at line 416 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE ( __INTERRUPT__ )
Value:
do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
                                                                CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
                                                            }while(0)

Definition at line 368 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE ( __INTERRUPT__ )
Value:
do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
                                                                SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
                                                            }while(0)

Floating Point Unit interrupt enable/disable macros.

Parameters:
__INTERRUPT__,: This parameter can be a value of FPU Interrupts

Definition at line 364 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_GET_BOOT_MODE ( ) READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)

Return the boot mode as configured by user.

Return values:
The boot mode as configured by user. The returned value can be one of the following values:
  • SYSCFG_BOOT_MAINFLASH
  • SYSCFG_BOOT_SYSTEMFLASH
  • SYSCFG_BOOT_FMC
  • SYSCFG_BOOT_SRAM
  • SYSCFG_BOOT_QUADSPI

Definition at line 339 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_GET_FLAG ( __FLAG__ ) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)

Check SYSCFG flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
  • SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 403 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_FLASH ( ) CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)

Main Flash memory mapped at 0x00000000.

Definition at line 307 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_FMC ( ) MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)

FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.

Definition at line 320 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI ( ) MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))

QUADSPI mapped at 0x00000000.

Definition at line 325 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SRAM ( ) MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))

Embedded SRAM mapped at 0x00000000.

Definition at line 315 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH ( ) MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)

System Flash memory mapped at 0x00000000.

Definition at line 311 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_SRAM2_ERASE ( ) SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)

SRAM2 erase.

Note:
__SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase

Definition at line 359 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_SRAM2_WRP_ENABLE ( __SRAM2WRP__ )
Value:
do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
                                                         SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
                                                        }while(0)

SRAM2 page write protection enable macro.

Parameters:
__SRAM2WRP__,: This parameter can be a value of SRAM2 Write protection
Note:
write protection can only be disabled by a system reset

Definition at line 345 of file stm32l4xx_hal.h.

#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK ( )
Value:
do {SYSCFG->SKR = 0xCA;\
                                                 SYSCFG->SKR = 0x53;\
                                                }while(0)

SRAM2 page write protection unlock prior to erase.

Note:
Writing a wrong key reactivates the write protection

Definition at line 352 of file stm32l4xx_hal.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SYSCFG Private Macros

Defines
SYSCFG Private Macros
HAL

Defines

#define | IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__)
#define | IS_SYSCFG_BREAK_CONFIG(__CONFIG__)
#define | IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)

Define Documentation

#define IS_SYSCFG_BREAK_CONFIG ( __CONFIG__ )
Value:
(((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
                                            ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \
                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))

Definition at line 440 of file stm32l4xx_hal.h.

#define IS_SYSCFG_FASTMODEPLUS ( __PIN__ )
Value:
((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))

Definition at line 458 of file stm32l4xx_hal.h.

#define IS_SYSCFG_FPU_INTERRUPT ( __INTERRUPT__ )
Value:
((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))

Definition at line 433 of file stm32l4xx_hal.h.

#define IS_SYSCFG_SRAM2WRP_PAGE ( __PAGE__ ) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))

Definition at line 445 of file stm32l4xx_hal.h.

#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE ( __VALUE__ )
Value:
(((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))

Definition at line 451 of file stm32l4xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_HighImpedanceConfig().

#define IS_SYSCFG_VREFBUF_TRIMMING ( __VALUE__ ) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

Definition at line 454 of file stm32l4xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_TrimmingConfig().

#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE ( __SCALE__ )
Value:
(((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))

Definition at line 448 of file stm32l4xx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_VoltageScalingConfig().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HAL

Modules | Defines | Variables
HAL
STM32L4xx_HAL_Driver

HAL module driver. More...

Modules

HAL Exported Functions
SYSCFG Exported Constants
DBGMCU Exported Macros
SYSCFG Exported Macros
SYSCFG Private Macros

Defines

#define | __STM32L4xx_HAL_VERSION_MAIN (0x01)
STM32L4xx HAL Driver version number V1.5.1.
#define | __STM32L4xx_HAL_VERSION_SUB1 (0x05)
#define | __STM32L4xx_HAL_VERSION_SUB2 (0x01)
#define | __STM32L4xx_HAL_VERSION_RC (0x00)
#define | __STM32L4xx_HAL_VERSION
#define | VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms (to be confirmed) */
#define | SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
#define | MEMRMP_OFFSET SYSCFG_OFFSET
#define | FB_MODE_BitNumber ((uint8_t)0x8)
#define | FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
#define | SCSR_OFFSET (SYSCFG_OFFSET + 0x18)
#define | BRER_BitNumber ((uint8_t)0x0)
#define | SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4))

Variables

__IO uint32_t | uwTick

Detailed Description

HAL module driver.

Define Documentation

#define __STM32L4xx_HAL_VERSION
Value:
((__STM32L4xx_HAL_VERSION_MAIN << 24)\
                                        |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\
                                        |(__STM32L4xx_HAL_VERSION_SUB2 << 8 )\
                                        |(__STM32L4xx_HAL_VERSION_RC))

Definition at line 76 of file stm32l4xx_hal.c.

Referenced by HAL_GetHalVersion().

#define __STM32L4xx_HAL_VERSION_MAIN (0x01)

STM32L4xx HAL Driver version number V1.5.1.

[31:24] main version

Definition at line 72 of file stm32l4xx_hal.c.

#define __STM32L4xx_HAL_VERSION_RC (0x00)

[7:0] release candidate

Definition at line 75 of file stm32l4xx_hal.c.

#define __STM32L4xx_HAL_VERSION_SUB1 (0x05)

[23:16] sub1 version

Definition at line 73 of file stm32l4xx_hal.c.

#define __STM32L4xx_HAL_VERSION_SUB2 (0x01)

[15:8] sub2 version

Definition at line 74 of file stm32l4xx_hal.c.

#define BRER_BitNumber ((uint8_t)0x0)

Definition at line 96 of file stm32l4xx_hal.c.

#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))

Definition at line 91 of file stm32l4xx_hal.c.

Referenced by HAL_SYSCFG_DisableMemorySwappingBank(), and HAL_SYSCFG_EnableMemorySwappingBank().

#define FB_MODE_BitNumber ((uint8_t)0x8)

Definition at line 90 of file stm32l4xx_hal.c.

#define MEMRMP_OFFSET SYSCFG_OFFSET

Definition at line 89 of file stm32l4xx_hal.c.

#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18)

Definition at line 95 of file stm32l4xx_hal.c.

#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4))

Definition at line 97 of file stm32l4xx_hal.c.

Referenced by HAL_SYSCFG_SRAM2Erase().

#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)

Definition at line 86 of file stm32l4xx_hal.c.

#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms (to be confirmed) */

Definition at line 82 of file stm32l4xx_hal.c.

Referenced by HAL_SYSCFG_EnableVREFBUF().

Variable Documentation

__IO uint32_t uwTick

Definition at line 101 of file stm32l4xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_CFGR_FIELDS_1
#define | ADC_CFGR2_FIELDS
#define | ADC_CFGR_WD_FIELDS
#define | ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN))
#define | ADC_ENABLE_TIMEOUT ((uint32_t) 2)
#define | ADC_DISABLE_TIMEOUT ((uint32_t) 2)
#define | ADC_STAB_DELAY_US ((uint32_t) 10)
#define | ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168)
#define | ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5)
#define | ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120)

Define Documentation

#define ADC_CFGR2_FIELDS
Value:
((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR  |\
                                       ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
                                       ADC_CFGR2_ROVSM))

ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going

Definition at line 174 of file stm32l4xx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_FIELDS_1
Value:
((uint32_t)(ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
                                       ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
                                       ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
                                       ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))

ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going

Definition at line 168 of file stm32l4xx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_WD_FIELDS
Value:
((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \
                                        ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH))

ADC_CFGR fields of Analog Watchdog parameters that can be updated when no conversion (neither regular nor injected) is on-going

Definition at line 179 of file stm32l4xx_hal_adc.c.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168)

ADC conversion completion time-out value

Definition at line 214 of file stm32l4xx_hal_adc.c.

Referenced by ADC_ConversionStop().

#define ADC_DISABLE_TIMEOUT ((uint32_t) 2)

ADC disable time-out value

Definition at line 197 of file stm32l4xx_hal_adc.c.

Referenced by ADC_Disable().

#define ADC_ENABLE_TIMEOUT ((uint32_t) 2)

ADC enable time-out value

Definition at line 196 of file stm32l4xx_hal_adc.c.

Referenced by ADC_Enable().

#define ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN))

ADC_OFR fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going

Definition at line 183 of file stm32l4xx_hal_adc.c.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_STAB_DELAY_US ((uint32_t) 10)

ADC voltage regulator startup time

Definition at line 204 of file stm32l4xx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5)

ADC stop time-out value

Definition at line 656 of file stm32l4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120)

Definition at line 661 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.

Note:
Keep in mind that all ADCs use the same clock: disabling the clock will reset all ADCs.
By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by reducing the leakage currents and is particularly interesting before entering STOP 1 or STOP 2 modes.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 563 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, ADC_ANY_OTHER_ENABLED, ADC_CFGR_FIELDS, ADC_CLEAR_COMMON_CONTROL_REGISTER, ADC_CLEAR_ERRORCODE, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_FLAG_RDY, ADC_IS_ENABLE, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_JQOVF, ADC_IT_OVR, ADC_IT_RDY, ADC_REGULAR_INJECTED_GROUP, ADC_SMPR1_FIELDS, assert_param, ADC_InjectionConfigTypeDef::ChannelCount, ADC_InjectionConfigTypeDef::ContextQueue, HAL_ADC_MspDeInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_RESET, ADC_HandleTypeDef::InjectionConfig, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".

Note:
As prerequisite, ADC clock must be configured at RCC top level depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks or AHB clock.
Possibility to update parameters on the fly: this function initializes the ADC MSP (HAL_ADC_MspInit()) only when coming from ADC state reset. Following calls to this function can be used to reconfigure some parameters of ADC_InitTypeDef structure on the fly, without modifying MSP configuration. If ADC MSP has to be modified again, HAL_ADC_DeInit() must be called before HAL_ADC_Init(). The setting of these parameters is conditioned by ADC state. For parameters constraints, see comments of structure "ADC_InitTypeDef".
This function configures the ADC within 2 scopes: scope of entire ADC and scope of regular group. For parameters details, see comments of structure "ADC_InitTypeDef".
Parameters related to common ADC registers (ADC clock mode) are set only if all ADCs are disabled. If this is not the case, these common parameters setting are bypassed without error reporting: it can be the intended behaviour in case of update of a parameter of ADC_InitTypeDef on the fly, without disabling the other ADCs.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 275 of file stm32l4xx_hal_adc.c.

References ADC_ANY_OTHER_ENABLED, ADC_CFGR2_FIELDS, ADC_CFGR_AUTOWAIT, ADC_CFGR_CONTINUOUS, ADC_CFGR_DFSDM, ADC_CFGR_DISCONTINUOUS_NUM, ADC_CFGR_DMACONTREQ, ADC_CFGR_FIELDS_1, ADC_CFGR_FIELDS_2, ADC_CFGR_REG_DISCONTINUOUS, ADC_CLEAR_ERRORCODE, ADC_COMMON_REGISTER, ADC_EXTERNALTRIGCONVEDGE_NONE, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_IS_ENABLE, ADC_SCAN_DISABLE, ADC_SCAN_ENABLE, ADC_SOFTWARE_START, ADC_STAB_DELAY_US, ADC_STATE_CLR_SET, ADC_TRIGGEREDMODE_SINGLE_TRIGGER, assert_param, ADC_InitTypeDef::ClockPrescaler, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::DataAlign, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InitTypeDef::DMAContinuousRequests, ADC_InitTypeDef::EOCSelection, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConv, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ERROR_INTERNAL, HAL_ADC_MspInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_CLOCKPRESCALER, IS_ADC_DATA_ALIGN, IS_ADC_DFSDMCFG_MODE, IS_ADC_EOC_SELECTION, IS_ADC_EXTTRIG, IS_ADC_EXTTRIG_EDGE, IS_ADC_OVERRUN, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_REGOVERSAMPLING_MODE, IS_ADC_REGULAR_DISCONT_NUMBER, IS_ADC_REGULAR_NB_CONV, IS_ADC_RESOLUTION, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SCAN_MODE, IS_ADC_TRIGGERED_OVERSAMPLING_MODE, ADC_HandleTypeDef::Lock, ADC_InitTypeDef::LowPowerAutoWait, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::NbrOfDiscConversion, ADC_InitTypeDef::Overrun, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_OversamplingTypeDef::OversamplingStopReset, ADC_OversamplingTypeDef::Ratio, ADC_InitTypeDef::Resolution, ADC_OversamplingTypeDef::RightBitShift, ADC_InitTypeDef::ScanConvMode, ADC_HandleTypeDef::State, and ADC_OversamplingTypeDef::TriggeredMode.

void HAL_ADC_MspDeInit ( ADC_HandleTypeDef * hadc )

DeInitialize the ADC MSP.

Parameters:
hadc,: ADC handle
Note:
All ADCs use the same clock: disabling the clock will reset all ADCs.
Return values:
None

Definition at line 764 of file stm32l4xx_hal_adc.c.

Referenced by HAL_ADC_DeInit().

void HAL_ADC_MspInit ( ADC_HandleTypeDef * hadc )

Initialize the ADC MSP.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 748 of file stm32l4xx_hal_adc.c.

Referenced by HAL_ADC_Init().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
ADC Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular and injected groups, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups when interruptions are enabled.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups and disable ADC DMA transfer.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Detailed Description

IO operation functions.

 ===============================================================================
             ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular group.
      (+) Stop conversion of regular group.
      (+) Poll for conversion complete on regular group.
      (+) Poll for conversion event.
      (+) Get result of regular channel conversion.
      (+) Start conversion of regular group and enable interruptions.
      (+) Stop conversion of regular group and disable interruptions.
      (+) Handle ADC interrupt request
      (+) Start conversion of regular group and enable DMA transfer.
      (+) Stop conversion of regular group and disable ADC DMA transfer.

Function Documentation

void HAL_ADC_ConvCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion complete callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 2002 of file stm32l4xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), and HAL_ADC_IRQHandler().

void HAL_ADC_ConvHalfCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion DMA half-transfer callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 2017 of file stm32l4xx_hal_adc.c.

Referenced by ADC_DMAHalfConvCplt().

void HAL_ADC_ErrorCallback ( ADC_HandleTypeDef * hadc )

ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 2048 of file stm32l4xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), and HAL_ADC_IRQHandler().

uint32_t HAL_ADC_GetValue ( ADC_HandleTypeDef * hadc )

Get ADC regular group conversion result.

Parameters:
hadc,: ADC handle
Note:
Reading DR register automatically clears EOC flag. To reset EOS flag, the user must resort to the macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS)
Return values:
Converted value

Definition at line 1666 of file stm32l4xx_hal_adc.c.

References assert_param, and ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handle ADC interrupt request.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1681 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE, ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE, ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IS_DUAL_CONVERSION_ENABLE, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_JQOVF, ADC_IT_OVR, ADC_MASTER_REGISTER, ADC_MULTIMODE_DMA_ENABLED, ADC_OVR_DATA_PRESERVED, assert_param, ADC_InitTypeDef::EOCSelection, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ERROR_JQOVF, HAL_ADC_ERROR_OVR, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_JQOVF, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EOC_SELECTION, ADC_InitTypeDef::Overrun, and ADC_HandleTypeDef::State.

void HAL_ADC_LevelOutOfWindowCallback ( ADC_HandleTypeDef * hadc )

Analog watchdog 1 callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 2032 of file stm32l4xx_hal_adc.c.

Referenced by HAL_ADC_IRQHandler().

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for regular group conversion to be completed.

Parameters:
hadc,: ADC handle
Timeout,: Timeout value in millisecond.
Note:
Depending on hadc->Init.EOCSelection, EOS or EOC is checked and cleared depending on AUTDLY bit status.
HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a DMA-managed conversions configuration: indeed, EOC is immediately reset by the DMA reading the DR register when the converted data is available. Therefore, EOC is set for a too short period to be reliably polled.
Return values:
HAL status

Definition at line 965 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE, ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE, ADC_IS_SOFTWARE_START_REGULAR, ADC_MASTER_REGISTER, ADC_MULTIMODE_DMA_ENABLED, assert_param, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for ADC event.

Parameters:
hadc,: ADC handle
EventType,: the ADC event type. This parameter can be one of the following values:
  • ADC_EOSMP_EVENT ADC End of Sampling event
  • ADC_AWD_EVENT ADC Analog watchdog 1 event
  • ADC_AWD2_EVENT ADC Analog watchdog 2 event
  • ADC_AWD3_EVENT ADC Analog watchdog 3 event
  • ADC_OVR_EVENT ADC Overrun event
  • ADC_JQOVF_EVENT ADC Injected context queue overflow event
Timeout,: Timeout value in millisecond.
Note:
The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. Indeed, the latter is reset only if hadc->Init.Overrun field is set to ADC_OVR_DATA_OVERWRITTEN. Otherwise, DR may be potentially overwritten by a new converted data as soon as OVR is cleared. To reset OVR flag once the preserved data is retrieved, the user can resort to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
Return values:
HAL status

Definition at line 1118 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_AWD2_EVENT, ADC_AWD3_EVENT, ADC_AWD_EVENT, ADC_EOSMP_EVENT, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOSMP, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_JQOVF_EVENT, ADC_OVR_DATA_PRESERVED, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_INJ_JQOVF, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EVENT_TYPE, ADC_InitTypeDef::Overrun, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group.

Note:
Interruptions enabled in this function: None.
Case of multimode enabled (when multimode feature is available): if ADC is Slave, ADC is enabled but conversion is not started, if ADC is master, ADC is enabled and multimode conversion is started.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 810 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_MASTER_REGISTER, ADC_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enable ADC, start conversion of regular group and transfer result through DMA.

Note:
Interruptions enabled in this function: overrun (if applicable), DMA half transfer, DMA transfer complete. Each of these interruptions has its dedicated callback function.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() is designed for single-ADC mode only. For multimode, the dedicated HAL_ADCEx_MultiModeStart_DMA() function must be used.
Parameters:
hadc,: ADC handle
pData,: Destination Buffer address.
Length,: Length of data to be transferred from ADC peripheral to memory (in bytes)
Return values:
None

Definition at line 1477 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE, ADC_IT_OVR, ADC_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), ADC_HandleTypeDef::Instance, ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : EOC (end of conversion), EOS (end of sequence), OVR overrun. Each of these interruptions has its dedicated callback function.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_IT() must be called for ADC Slave first, then for ADC Master. For ADC Slave, ADC is enabled only (conversion is not started). For ADC Master, ADC is enabled and multimode conversion is started.
To guarantee a proper reset of all interruptions once all the needed conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure a correct stop of the IT-based conversions.
By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling interruption. If required (e.g. in case of oversampling with trigger mode), the user must 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) before calling HAL_ADC_Start_IT().
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 1261 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_OVR, ADC_MASTER_REGISTER, ADC_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_OVR_DATA_PRESERVED, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, ADC_InitTypeDef::Overrun, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular and injected groups, disable ADC peripheral.

Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 915 of file stm32l4xx_hal_adc.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular groups and disable ADC DMA transfer.

Note:
Stop as well injected conversions and disable ADC peripheral.
Case of multimode enabled (when multimode feature is available): HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1595 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular groups when interruptions are enabled.

Note:
Stop as well injected conversions and disable ADC peripheral.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1425 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ADC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure the selected channel to be linked to the regular group.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on regular group
      (+) Configure the analog watchdog

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_AnalogWDGConfTypeDef * | AnalogWDGConfig
 | ) |  |

Configure the analog watchdog.

Note:
Possibility to update parameters on the fly: This function initializes the selected analog watchdog, successive calls to this function can be used to reconfigure some parameters of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting the ADC, e.g. to set several channels to monitor simultaneously. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_AnalogWDGConfTypeDef".
Parameters:
hadc,: ADC handle
AnalogWDGConfig,: Structure of ADC analog watchdog configuration
Return values:
HAL status

Definition at line 2398 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_ANALOGWATCHDOG_1, ADC_ANALOGWATCHDOG_2, ADC_ANALOGWATCHDOG_NONE, ADC_ANALOGWATCHDOG_SINGLE_INJEC, ADC_ANALOGWATCHDOG_SINGLE_REG, ADC_ANALOGWATCHDOG_SINGLE_REGINJEC, ADC_AWD1THRESHOLD_SHIFT_RESOLUTION, ADC_AWD23THRESHOLD_SHIFT_RESOLUTION, ADC_CFGR_SET_AWD1CH, ADC_CFGR_SET_AWD23CR, ADC_CFGR_WD_FIELDS, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_GET_RESOLUTION, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_TRX_HIGHTHRESHOLD, assert_param, ADC_AnalogWDGConfTypeDef::Channel, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_ERROR_CONFIG, ADC_AnalogWDGConfTypeDef::HighThreshold, ADC_HandleTypeDef::Instance, IS_ADC_ANALOG_WATCHDOG_MODE, IS_ADC_ANALOG_WATCHDOG_NUMBER, IS_ADC_CHANNEL, IS_ADC_RANGE, ADC_AnalogWDGConfTypeDef::ITMode, ADC_AnalogWDGConfTypeDef::LowThreshold, ADC_HandleTypeDef::State, ADC_AnalogWDGConfTypeDef::WatchdogMode, and ADC_AnalogWDGConfTypeDef::WatchdogNumber.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_ChannelConfTypeDef * | sConfig
 | ) |  |

Configure the selected channel to be linked to the regular group.

Note:
In case of usage of internal measurement channels (Vbat / VrefInt / TempSensor), the recommended sampling time is provided by the datasheet. These internal paths can be disabled using function HAL_ADC_DeInit().
Possibility to update parameters on the fly: HAL_ADC_ConfigChannel() initializes channel into regular group, consecutive calls to this function can be used to reconfigure some parameters of structure "ADC_ChannelConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_ChannelConfTypeDef".
Parameters:
hadc,: ADC handle
sConfig,: Structure ADC channel for regular group.
Return values:
HAL status

Definition at line 2097 of file stm32l4xx_hal_adc.c.

References ADC_ANY_OTHER_ENABLED, ADC_BATTERY_VOLTAGE_INSTANCE, ADC_CHANNEL_10, ADC_CHANNEL_9, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_COMMON_REGISTER, ADC_DIFFERENTIAL_ENDED, ADC_DIFSEL_CHANNEL, ADC_GET_RESOLUTION, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_IS_ENABLE, ADC_OFFSET_1, ADC_OFFSET_2, ADC_OFFSET_3, ADC_OFFSET_4, ADC_OFFSET_NONE, ADC_OFFSET_SHIFT_RESOLUTION, ADC_OFR_CHANNEL, ADC_OFR_FIELDS, ADC_SMPR1_SETTING, ADC_SMPR2_SETTING, ADC_SQR1_RK, ADC_SQR2_RK, ADC_SQR3_RK, ADC_SQR4_RK, ADC_TEMPERATURE_SENSOR_INSTANCE, ADC_TEMPSENSOR_DELAY_US, ADC_VREFINT_INSTANCE, assert_param, ADC_ChannelConfTypeDef::Channel, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_DIFF_CHANNEL, IS_ADC_OFFSET_NUMBER, IS_ADC_RANGE, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, IS_ADC_SINGLE_DIFFERENTIAL, ADC_ChannelConfTypeDef::Offset, ADC_ChannelConfTypeDef::OffsetNumber, ADC_InitTypeDef::OversamplingMode, ADC_ChannelConfTypeDef::Rank, ADC_ChannelConfTypeDef::SamplingTime, ADC_ChannelConfTypeDef::SingleDiff, and ADC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
ADC Exported Functions

ADC Peripheral State functions. More...

Functions

uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

ADC Peripheral State functions.

 ===============================================================================
            ##### Peripheral state and errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions to get in run-time the status of the
    peripheral.
      (+) Check the ADC state
      (+) Check the ADC error code

Function Documentation

uint32_t HAL_ADC_GetError ( ADC_HandleTypeDef * hadc )

Return the ADC error code.

Parameters:
hadc,: ADC handle
Return values:
ADC Error Code (uint32_t bit-map)

Definition at line 2622 of file stm32l4xx_hal_adc.c.

References assert_param, ADC_HandleTypeDef::ErrorCode, and ADC_HandleTypeDef::Instance.

uint32_t HAL_ADC_GetState ( ADC_HandleTypeDef * hadc )

Return the ADC handle state.

Parameters:
hadc,: ADC handle
Return values:
HAL state (uint32_t bit-map)

Definition at line 2607 of file stm32l4xx_hal_adc.c.

References assert_param, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Private Functions

Functions
ADC Private Functions
ADC

Functions

HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

HAL_StatusTypeDef ADC_ConversionStop | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | ConversionGroup
 | ) |  |

Stop ADC conversion.

Parameters:
hadc,: ADC handle
ConversionGroup,: ADC group regular and/or injected. This parameter can be one of the following values:
  • ADC_REGULAR_GROUP ADC regular conversion type.
  • ADC_INJECTED_GROUP ADC injected conversion type.
  • ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
Return values:
HAL status.

Definition at line 2654 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_CONVERSION_TIME_MAX_CPU_CYCLES, ADC_FLAG_JEOS, ADC_INJECTED_GROUP, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_REGULAR_GROUP, ADC_REGULAR_INJECTED_GROUP, ADC_STOP_CONVERSION_TIMEOUT, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_CONVERSION_GROUP, ADC_InitTypeDef::LowPowerAutoWait, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

HAL_StatusTypeDef ADC_Disable ( ADC_HandleTypeDef * hadc )

Disable the selected ADC.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 2837 of file stm32l4xx_hal_adc.c.

References ADC_DISABLE, ADC_DISABLE_TIMEOUT, ADC_DISABLING_CONDITIONS, ADC_IS_ENABLE, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

void ADC_DMAConvCplt ( DMA_HandleTypeDef * hdma )

DMA transfer complete callback.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 2891 of file stm32l4xx_hal_adc.c.

References ADC_FLAG_EOS, ADC_IS_SOFTWARE_START_REGULAR, HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_DMAError ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 2970 of file stm32l4xx_hal_adc.c.

References ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_DMAHalfConvCplt ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 2956 of file stm32l4xx_hal_adc.c.

References HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

HAL_StatusTypeDef ADC_Enable ( ADC_HandleTypeDef * hadc )

Enable the selected ADC.

Note:
Prerequisite condition to use this function: ADC must be disabled and voltage regulator must be enabled (done into HAL_ADC_Init()).
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 2774 of file stm32l4xx_hal_adc.c.

References __HAL_ADC_GET_FLAG, ADC_ENABLE, ADC_ENABLE_TIMEOUT, ADC_ENABLING_CONDITIONS, ADC_FLAG_RDY, ADC_IS_ENABLE, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC States

Defines
ADC States
ADC Exported Types

Defines

#define | HAL_ADC_STATE_RESET ((uint32_t)0x00000000)
HAL ADC state machine: ADC State bitfield definition.
#define | HAL_ADC_STATE_READY ((uint32_t)0x00000001)
#define | HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002)
#define | HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004)
#define | HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010)
#define | HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020)
#define | HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040)
#define | HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100)
#define | HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200)
#define | HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400)
#define | HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800)
#define | HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000)
#define | HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000)
#define | HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000)
#define | HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000)
#define | HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000)
#define | HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000)

Define Documentation

#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000)

Out-of-window occurrence of Analog Watchdog 1

Definition at line 124 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000)

Out-of-window occurrence of Analog Watchdog 2

Definition at line 125 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000)

Out-of-window occurrence of Analog Watchdog 3

Definition at line 126 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002)

ADC is busy because of an internal process (initialization, calibration)

Definition at line 100 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020)

Configuration error occurrence

Definition at line 105 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_PollForConversion(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040)

DMA error occurrence

Definition at line 106 of file stm32l4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), and HAL_ADCEx_RegularStop_DMA().

#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010)

Internal error occurrence

Definition at line 104 of file stm32l4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_Stop_DMA(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000)

An injected conversion is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on, multimode ADC master control when multimode feature available)

Definition at line 117 of file stm32l4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000)

Injected conversion data available

Definition at line 120 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000)

Injected queue overflow occurrence

Definition at line 121 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADCEx_EnableInjectedQueue().

#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000)

ADC in multimode slave state, controlled by another ADC master (when feature available)

Definition at line 129 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_READY ((uint32_t)0x00000001)

ADC peripheral ready for use

Definition at line 99 of file stm32l4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100)

A regular conversion is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on, multimode ADC master control when multimode feature available)

Definition at line 109 of file stm32l4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200)

Regular conversion data available

Definition at line 112 of file stm32l4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800)

End Of Sampling flag raised

Definition at line 114 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400)

Overrun occurrence

Definition at line 113 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000)

HAL ADC state machine: ADC State bitfield definition.

ADC not yet initialized or disabled

Definition at line 98 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_Init().

#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004)

TimeOut occurrence

Definition at line 101 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC_OversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_OversamplingTypeDef Struct Reference
ADC Exported Types

ADC Regular Conversion Oversampling structure definition. More...

#include <stm32l4xx_hal_adc.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift
uint32_t | TriggeredMode
uint32_t | OversamplingStopReset

Detailed Description

ADC Regular Conversion Oversampling structure definition.

Definition at line 66 of file stm32l4xx_hal_adc.h.

Field Documentation

uint32_t ADC_OversamplingTypeDef::OversamplingStopReset

Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected sequence interruption. If oversampling is enabled on both regular and injected groups, this parameter is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed during injection sequence). This parameter can be a value of ADC Extended Regular Oversampling Continued or Resumed Mode

Definition at line 77 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::Ratio

Configures the oversampling ratio. This parameter can be a value of ADC Extended Oversampling Ratio

Definition at line 68 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of ADC Extended Oversampling Right Shift

Definition at line 71 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::TriggeredMode

Selects the regular triggered oversampling mode. This parameter can be a value of ADC Extended Triggered Regular Oversampling

Definition at line 74 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_adc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC_InjectionConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfigTypeDef Struct Reference
ADC Exported Types

ADC Injection Configuration. More...

#include <stm32l4xx_hal_adc.h>

Data Fields

uint32_t | ContextQueue
uint32_t | ChannelCount

Detailed Description

ADC Injection Configuration.

Definition at line 138 of file stm32l4xx_hal_adc.h.

Field Documentation

uint32_t ADC_InjectionConfigTypeDef::ChannelCount

Number of channels in the injected sequence

Definition at line 144 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfigTypeDef::ContextQueue

Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call

Definition at line 140 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_adc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_ChannelConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC channel for regular group. More...

#include <stm32l4xx_hal_adc.h>

Data Fields

uint32_t | Channel
uint32_t | Rank
uint32_t | SamplingTime
uint32_t | SingleDiff
uint32_t | OffsetNumber
uint32_t | Offset

Detailed Description

Structure definition of ADC channel for regular group.

Note:
The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned by ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
  • For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
  • For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 161 of file stm32l4xx_hal_adc.h.

Field Documentation

uint32_t ADC_ChannelConfTypeDef::Channel

Specifies the channel to configure into ADC regular group. This parameter can be a value of ADC Channels Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability.

Definition at line 163 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Offset

Defines the offset to be subtracted from the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 194 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::OffsetNumber

Selects the offset number This parameter can be a value of ADC Extended Offset Number Caution: Only one offset is allowed per channel. This parameter overwrites the last setting.

Definition at line 191 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Rank

Specifies the rank in the regular group sequencer. This parameter can be a value of ADC Extended Regular Channel Rank Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted)

Definition at line 166 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of ADC Sampling Times Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time setting) Refer to device DataSheet for timings values.

Definition at line 170 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SingleDiff

Selection of single-ended or differential input. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of ADC Extended Single-ended/Differential input mode Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)

Definition at line 180 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_adc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC_AnalogWDGConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_AnalogWDGConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC analog watchdog. More...

#include <stm32l4xx_hal_adc.h>

Data Fields

uint32_t | WatchdogNumber
uint32_t | WatchdogMode
uint32_t | Channel
uint32_t | ITMode
uint32_t | HighThreshold
uint32_t | LowThreshold

Detailed Description

Structure definition of ADC analog watchdog.

Note:
The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned by ADC state. ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.

Definition at line 208 of file stm32l4xx_hal_adc.h.

Field Documentation

uint32_t ADC_AnalogWDGConfTypeDef::Channel

Selects which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel. Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of ADC Channels.

Definition at line 218 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::HighThreshold

Configures the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.

Definition at line 225 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::ITMode

Specifies whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE

Definition at line 223 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::LowThreshold

Configures the ADC analog watchdog Low threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.

Definition at line 230 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogMode

For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group. For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored. This parameter can be a value of ADC Extended Analog Watchdog Mode.

Definition at line 214 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogNumber

Selects which ADC analog watchdog is applied to the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of ADC Extended Analog Watchdog Selection.

Definition at line 210 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_adc.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Error Code

Defines
ADC Error Code
ADC Exported Constants

Defines

#define | HAL_ADC_ERROR_NONE ((uint32_t)0x00)
#define | HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01)
#define | HAL_ADC_ERROR_OVR ((uint32_t)0x02)
#define | HAL_ADC_ERROR_DMA ((uint32_t)0x04)
#define | HAL_ADC_ERROR_JQOVF ((uint32_t)0x08)

Define Documentation

#define HAL_ADC_ERROR_DMA ((uint32_t)0x04)

DMA transfer error

Definition at line 254 of file stm32l4xx_hal_adc.h.

Referenced by ADC_DMAError(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01)

ADC IP internal error: problem of clocking, enable/disable, erroneous state

Definition at line 251 of file stm32l4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08)

Injected context queue overflow error

Definition at line 255 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_ERROR_NONE ((uint32_t)0x00)

No error

Definition at line 250 of file stm32l4xx_hal_adc.h.

#define HAL_ADC_ERROR_OVR ((uint32_t)0x02)

Overrun error

Definition at line 253 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Clock Prescaler

Defines
ADC Clock Prescaler
ADC Exported Constants

Defines

#define | ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE)
#define | ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
#define | ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
#define | ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
#define | ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000)
#define | ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0)
#define | ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1)
#define | ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2))
#define | ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1))
#define | ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3))
#define | ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1))
#define | ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))

Define Documentation

#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000)

ADC asynchronous clock not divided

Definition at line 271 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0))

ADC asynchronous clock divided by 10

Definition at line 276 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1))

ADC asynchronous clock divided by 12

Definition at line 277 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1))

ADC asynchronous clock divided by 128

Definition at line 281 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))

ADC asynchronous clock divided by 16

Definition at line 278 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0)

ADC asynchronous clock divided by 2

Definition at line 272 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))

ADC asynchronous clock divided by 256

Definition at line 282 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3))

ADC asynchronous clock divided by 32

Definition at line 279 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1)

ADC asynchronous clock divided by 4

Definition at line 273 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))

ADC asynchronous clock divided by 6

Definition at line 274 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0))

ADC asynchronous clock divided by 64

Definition at line 280 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2))

ADC asynchronous clock divided by 8

Definition at line 275 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0)

ADC synchronous clock derived from AHB clock not divided

Definition at line 263 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1)

ADC synchronous clock derived from AHB clock divided by 2

Definition at line 264 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE)

ADC synchronous clock derived from AHB clock divided by 4

Definition at line 265 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1

Obsolete naming, kept for compatibility with some other devices

Definition at line 267 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2

Obsolete naming, kept for compatibility with some other devices

Definition at line 268 of file stm32l4xx_hal_adc.h.

#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4

Obsolete naming, kept for compatibility with some other devices

Definition at line 269 of file stm32l4xx_hal_adc.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Resolution

Defines
ADC Resolution
ADC Exported Constants

Defines

#define | ADC_RESOLUTION_12B ((uint32_t)0x00000000)
#define | ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0)
#define | ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1)
#define | ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES)

Define Documentation

#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0)

ADC 10-bit resolution

Definition at line 292 of file stm32l4xx_hal_adc.h.

#define ADC_RESOLUTION_12B ((uint32_t)0x00000000)

ADC 12-bit resolution

Definition at line 291 of file stm32l4xx_hal_adc.h.

#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES)

ADC 6-bit resolution

Definition at line 294 of file stm32l4xx_hal_adc.h.

#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1)

ADC 8-bit resolution

Definition at line 293 of file stm32l4xx_hal_adc.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Data Alignment

Defines
ADC Data Alignment
ADC Exported Constants

Defines

#define | ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define | ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN)

Define Documentation

#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN)

Data left alignment

Definition at line 303 of file stm32l4xx_hal_adc.h.

#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)

Data right alignment

Definition at line 302 of file stm32l4xx_hal_adc.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Scan Mode

Defines
ADC Scan Mode
ADC Exported Constants

Defines

#define | ADC_SCAN_DISABLE ((uint32_t)0x00000000)
#define | ADC_SCAN_ENABLE ((uint32_t)0x00000001)

Define Documentation

#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)

Scan mode disabled

Definition at line 311 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SCAN_ENABLE ((uint32_t)0x00000001)

Scan mode enabled

Definition at line 312 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC External Trigger Source Edge for Regular Group

Defines
ADC External Trigger Source Edge for Regular Group
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)

Define Documentation

#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)

Regular conversions hardware trigger detection on the falling edge

Definition at line 322 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)

Regular conversions hardware trigger detection disabled

Definition at line 320 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)

Regular conversions hardware trigger detection on the rising edge

Definition at line 321 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)

Regular conversions hardware trigger detection on both the rising and falling edges

Definition at line 323 of file stm32l4xx_hal_adc.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC External Trigger Source for Regular Group

Defines
ADC External Trigger Source for Regular Group
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define | ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define | ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
#define | ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
#define | ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
#define | ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
#define | ADC_SOFTWARE_START ((uint32_t)0x00000001)

Define Documentation

#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))

Event 6 triggers regular group conversion start

Definition at line 339 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))

Event 14 triggers regular group conversion start

Definition at line 347 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)

Event 0 triggers regular group conversion start

Definition at line 333 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)

Event 1 triggers regular group conversion start

Definition at line 334 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)

Event 2 triggers regular group conversion start

Definition at line 335 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))

Event 9 triggers regular group conversion start

Definition at line 342 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))

Event 10 triggers regular group conversion start

Definition at line 343 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))

Event 3 triggers regular group conversion start

Definition at line 336 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))

Event 11 triggers regular group conversion start

Definition at line 344 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)

Event 15 triggers regular group conversion start

Definition at line 348 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)

Event 4 triggers regular group conversion start

Definition at line 337 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))

Event 5 triggers regular group conversion start

Definition at line 338 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))

Event 12 triggers regular group conversion start

Definition at line 345 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))

Event 13 triggers regular group conversion start

Definition at line 346 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))

Event 7 triggers regular group conversion start

Definition at line 340 of file stm32l4xx_hal_adc.h.

#define ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)

Event 8 triggers regular group conversion start

Definition at line 341 of file stm32l4xx_hal_adc.h.

#define ADC_SOFTWARE_START ((uint32_t)0x00000001)

Software triggers regular group conversion start

Definition at line 350 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC End of Regular Sequence/Conversion

Defines
ADC End of Regular Sequence/Conversion
ADC Exported Constants

Defines

#define | ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
#define | ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS))

Define Documentation

#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)

End of sequence flag

Definition at line 360 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)

End of conversion flag

Definition at line 359 of file stm32l4xx_hal_adc.h.

#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS))

Reserved for future use

Definition at line 361 of file stm32l4xx_hal_adc.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC overrun

Defines
ADC overrun
ADC Exported Constants

Defines

#define | ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
#define | ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD)

Define Documentation

#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD)

Data overwritten in case of overrun

Definition at line 370 of file stm32l4xx_hal_adc.h.

#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)

Data preserved in case of overrun

Definition at line 369 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Channels

Defines
ADC Channels
ADC Exported Constants

Defines

#define | ADC_CHANNEL_0 ((uint32_t)(0x00000000))
#define | ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
#define | ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
#define | ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
#define | ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_17
#define | ADC_CHANNEL_VBAT ADC_CHANNEL_18
#define | ADC_CHANNEL_VREFINT ADC_CHANNEL_0

Define Documentation

#define ADC_CHANNEL_0 ((uint32_t)(0x00000000))

ADC channel 0

Definition at line 378 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))

ADC channel 1

Definition at line 379 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))

ADC channel 10

Definition at line 388 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))

ADC channel 11

Definition at line 389 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))

ADC channel 12

Definition at line 390 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))

ADC channel 13

Definition at line 391 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))

ADC channel 14

Definition at line 392 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))

ADC channel 15

Definition at line 393 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))

ADC channel 16

Definition at line 394 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))

ADC channel 17

Definition at line 395 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))

ADC channel 18

Definition at line 396 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))

ADC channel 2

Definition at line 380 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))

ADC channel 3

Definition at line 381 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))

ADC channel 4

Definition at line 382 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))

ADC channel 5

Definition at line 383 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))

ADC channel 6

Definition at line 384 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))

ADC channel 7

Definition at line 385 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))

ADC channel 8

Definition at line 386 of file stm32l4xx_hal_adc.h.

#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))

ADC channel 9

Definition at line 387 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_17

ADC temperature sensor channel

Definition at line 400 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VBAT ADC_CHANNEL_18

ADC Vbat channel

Definition at line 401 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VREFINT ADC_CHANNEL_0

ADC Vrefint channel

Definition at line 402 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
Return resolution bits in CFGR register RES[1:0] field.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)
Check if conversion is on going on regular group.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clear and set specific bits of the handle State.
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
Verify the length of the scheduled regular conversions group.
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
Verify the number of scheduled regular conversions in discontinuous mode.
#define | IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
Verify the ADC clock setting.
#define | IS_ADC_RESOLUTION(__RESOLUTION__)
Verify the ADC resolution setting.
#define | IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__)
Verify the ADC resolution setting when limited to 6 or 8 bits.
#define | IS_ADC_DATA_ALIGN(__ALIGN__)
Verify the ADC converted data alignment.
#define | IS_ADC_SCAN_MODE(__SCAN_MODE__)
Verify the ADC scan mode.
#define | IS_ADC_EXTTRIG_EDGE(__EDGE__)
Verify the ADC edge trigger setting for regular group.
#define | IS_ADC_EXTTRIG(__REGTRIG__)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
Verify the ADC regular conversions check for converted data availability.
#define | IS_ADC_OVERRUN(__OVR__)
Verify the ADC regular conversions overrun handling.
#define | IS_ADC_SAMPLE_TIME(__TIME__)
Verify the ADC conversions sampling time.

Define Documentation

#define ADC_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").

Parameters:
__HANDLE__,: ADC handle.
Return values:
None

Definition at line 440 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_GET_RESOLUTION ( __HANDLE__ ) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)

Return resolution bits in CFGR register RES[1:0] field.

Parameters:
__HANDLE__,: ADC handle.
Return values:
2-bit field RES of CFGR register.

Definition at line 433 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_IS_CONVERSION_ONGOING_REGULAR ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET             \
        ) ? RESET : SET)

Check if conversion is on going on regular group.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (conversion is on going) or RESET (no conversion is on going)

Definition at line 458 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_IS_ENABLE ( __HANDLE__ )
Value:
(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
          ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
        ) ? SET : RESET)

Verification of ADC state: enabled or disabled.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (ADC enabled) or RESET (ADC disabled)

Definition at line 447 of file stm32l4xx_hal_adc.h.

Referenced by ADC_Disable(), ADC_Enable(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_MultiModeConfigChannel().

#define ADC_IS_SOFTWARE_START_REGULAR ( __HANDLE__ ) (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)

Test if conversion trigger of regular group is software start or external trigger.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (software start) or RESET (external trigger)

Definition at line 425 of file stm32l4xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_STATE_CLR_SET MODIFY_REG

Simultaneously clear and set specific bits of the handle State.

Note:
ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values:
None

Definition at line 470 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define IS_ADC_CLOCKPRESCALER ( __ADC_CLOCK__ )
Value:
(((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )

Verify the ADC clock setting.

Parameters:
__ADC_CLOCK__,: programmed ADC clock.
Return values:
SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)

Definition at line 506 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_DATA_ALIGN ( __ALIGN__ )
Value:
(((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT)    )

Verify the ADC converted data alignment.

Parameters:
__ALIGN__,: programmed ADC converted data alignment.
Return values:
SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)

Definition at line 546 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EOC_SELECTION ( __EOC_SELECTION__ )
Value:
(((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
                                                 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)       || \
                                                 ((__EOC_SELECTION__) == ADC_EOC_SINGLE_SEQ_CONV)  )

Verify the ADC regular conversions check for converted data availability.

Parameters:
__EOC_SELECTION__,: converted data availability check.
Return values:
SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)

Definition at line 601 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define IS_ADC_EXTTRIG ( __REGTRIG__ )
Value:
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)   || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)   || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)   || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)   || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)  || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)   || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)  || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)  || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)  || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)  || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)  || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)   || \
                                                                                \
                                     ((__REGTRIG__) == ADC_SOFTWARE_START)           )

Verify the ADC regular conversions external trigger.

Parameters:
__REGTRIG__,: programmed ADC regular conversions external trigger.
Return values:
SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)

Definition at line 575 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EXTTRIG_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )

Verify the ADC edge trigger setting for regular group.

Parameters:
__EDGE__,: programmed ADC edge trigger setting.
Return values:
SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)

Definition at line 563 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

#define IS_ADC_OVERRUN ( __OVR__ )
Value:
(((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
                                 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )

Verify the ADC regular conversions overrun handling.

Parameters:
__OVR__,: ADC regular conversions overrun handling.
Return values:
SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)

Definition at line 610 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RANGE | ( | __RESOLUTION__,
 |  | __ADC_VALUE__
 | ) |
Value:
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F)))   )

Verify that a given value is aligned with the ADC resolution range.

Parameters:
__RESOLUTION__,: ADC resolution (12, 10, 8 or 6 bits).
__ADC_VALUE__,: value checked against the resolution.
Return values:
SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)

Definition at line 478 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGULAR_DISCONT_NUMBER ( NUMBER ) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))

Verify the number of scheduled regular conversions in discontinuous mode.

Parameters:
NUMBER,: number of scheduled regular conversions in discontinuous mode.
Return values:
SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)

Definition at line 498 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_REGULAR_NB_CONV ( __LENGTH__ ) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))

Verify the length of the scheduled regular conversions group.

Parameters:
__LENGTH__,: number of programmed conversions.
Return values:
SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)

Definition at line 490 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RESOLUTION ( __RESOLUTION__ )
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )

Verify the ADC resolution setting.

Parameters:
__RESOLUTION__,: programmed ADC resolution.
Return values:
SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)

Definition at line 528 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RESOLUTION_8_6_BITS ( __RESOLUTION__ )
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
                                                    ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )

Verify the ADC resolution setting when limited to 6 or 8 bits.

Parameters:
__RESOLUTION__,: programmed ADC resolution when limited to 6 or 8 bits.
Return values:
SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)

Definition at line 538 of file stm32l4xx_hal_adc.h.

#define IS_ADC_SAMPLE_TIME ( __TIME__ )
Value:
(((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
                                      ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
                                      ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
                                      ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )

Verify the ADC conversions sampling time.

Parameters:
__TIME__,: ADC conversions sampling time.
Return values:
SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)

Definition at line 629 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SCAN_MODE ( __SCAN_MODE__ )
Value:
(((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )

Verify the ADC scan mode.

Parameters:
__SCAN_MODE__,: programmed ADC scan mode.
Return values:
SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)

Definition at line 555 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Exported Macros

Defines
ADC Exported Macros
ADC

Defines

#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified ADC interrupt source is enabled or not.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable an ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable an ADC interrupt.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Check whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear a specified ADC flag.

Define Documentation

#define __HAL_ADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR) = (__FLAG__))

Clear a specified ADC flag.

Parameters:
__HANDLE__,: ADC handle.
__FLAG__,: ADC flag to clear This parameter can be one of the following values:
  • ADC_FLAG_RDY, ADC Ready (ADRDY) flag
  • ADC_FLAG_EOSMP, ADC End of Sampling flag
  • ADC_FLAG_EOC, ADC End of Regular Conversion flag
  • ADC_FLAG_EOS, ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR, ADC overrun flag
  • ADC_FLAG_JEOC, ADC End of Injected Conversion flag
  • ADC_FLAG_JEOS, ADC End of Injected sequence of Conversions flag
  • ADC_FLAG_AWD1, ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2, ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3, ADC Analog watchdog 3 flag (additional analog watchdog)
  • ADC_FLAG_JQOVF, ADC Injected Context Queue Overflow flag.
Note:
Bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR).
Return values:
None

Definition at line 780 of file stm32l4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

Disable an ADC interrupt.

Parameters:
__HANDLE__,: ADC handle.
__INTERRUPT__,: ADC Interrupt to disable
  • ADC_IT_RDY, ADC Ready (ADRDY) interrupt source
  • ADC_IT_EOSMP, ADC End of Sampling interrupt source
  • ADC_IT_EOC, ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR, ADC overrun interrupt source
  • ADC_IT_JEOC, ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source.
Return values:
None

Definition at line 739 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define __HAL_ADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

Enable an ADC interrupt.

Parameters:
__HANDLE__,: ADC handle.
__INTERRUPT__,: ADC Interrupt to enable This parameter can be one of the following values:
  • ADC_IT_RDY, ADC Ready (ADRDY) interrupt source
  • ADC_IT_EOSMP, ADC End of Sampling interrupt source
  • ADC_IT_EOC, ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR, ADC overrun interrupt source
  • ADC_IT_JEOC, ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source.
Return values:
None

Definition at line 720 of file stm32l4xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))

Check whether the specified ADC flag is set or not.

Parameters:
__HANDLE__,: ADC handle.
__FLAG__,: ADC flag to check This parameter can be one of the following values:
  • ADC_FLAG_RDY, ADC Ready (ADRDY) flag
  • ADC_FLAG_EOSMP, ADC End of Sampling flag
  • ADC_FLAG_EOC, ADC End of Regular Conversion flag
  • ADC_FLAG_EOS, ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR, ADC overrun flag
  • ADC_FLAG_JEOC, ADC End of Injected Conversion flag
  • ADC_FLAG_JEOS, ADC End of Injected sequence of Conversions flag
  • ADC_FLAG_AWD1, ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2, ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3, ADC Analog watchdog 3 flag (additional analog watchdog)
  • ADC_FLAG_JQOVF, ADC Injected Context Queue Overflow flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 759 of file stm32l4xx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Enable(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define __HAL_ADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)      \
     )? SET : RESET                                                            \
    )

Check whether the specified ADC interrupt source is enabled or not.

Parameters:
__HANDLE__,: ADC handle.
__INTERRUPT__,: ADC interrupt source to check This parameter can be one of the following values:
  • ADC_IT_RDY, ADC Ready (ADRDY) interrupt source
  • ADC_IT_EOSMP, ADC End of Sampling interrupt source
  • ADC_IT_EOC, ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR, ADC overrun interrupt source
  • ADC_IT_JEOC, ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source.
Return values:
State of interruption (SET or RESET)

Definition at line 697 of file stm32l4xx_hal_adc.h.

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

Reset ADC handle state.

Parameters:
__HANDLE__,: ADC handle.
Return values:
None

Definition at line 677 of file stm32l4xx_hal_adc.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Extended Private Constants

Defines
ADC Extended Private Constants
ADCEx

Defines

#define | ADC_JSQR_FIELDS
#define | ADC_CFGR2_INJ_FIELDS
#define | ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000)

Define Documentation

#define ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000)

ADC calibration time-out value

Definition at line 156 of file stm32l4xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start().

#define ADC_CFGR2_INJ_FIELDS
Value:
((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR  |\
                                       ADC_CFGR2_OVSS ))

ADC_CFGR2 injected oversampling parameters that can be updated when no conversion is on-going (neither regular nor injected)

Definition at line 144 of file stm32l4xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_JSQR_FIELDS
Value:
((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
                                     ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
                                      ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))

ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled

Definition at line 139 of file stm32l4xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Input and Output operation functions

Functions
Extended Input and Output operation functions
ADC Extended Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable ADC peripheral if no regular conversion is on going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups when interruptions are enabled, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups and disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.

Detailed Description

Extended IO operation functions.

 ===============================================================================
             ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

      (+) Perform the ADC self-calibration for single or differential ending.
      (+) Get calibration factors for single or differential ending.
      (+) Set calibration factors for single or differential ending.

      (+) Start conversion of injected group.
      (+) Stop conversion of injected group.
      (+) Poll for conversion complete on injected group.
      (+) Get result of injected channel conversion.
      (+) Start conversion of injected group and enable interruptions.
      (+) Stop conversion of injected group and disable interruptions.

      (+) When multimode feature is available, start multimode and enable DMA transfer.
      (+) Stop multimode and disable ADC DMA transfer.
      (+) Get result of multimode conversion.

Function Documentation

uint32_t HAL_ADCEx_Calibration_GetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff
 | ) |  |

Get the calibration factor from automatic conversion result.

Parameters:
hadc,: ADC handle.
SingleDiff,: Selection of single-ended or differential input This parameter can be one of the following values:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
Return values:
Converted value

Definition at line 295 of file stm32l4xx_hal_adc_ex.c.

References ADC_CALFACT_DIFF_GET, ADC_DIFFERENTIAL_ENDED, assert_param, ADC_HandleTypeDef::Instance, and IS_ADC_SINGLE_DIFFERENTIAL.

HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set the calibration factor to overwrite automatic conversion result.

ADC must be enabled and no conversion on going.

Parameters:
hadc,: ADC handle.
SingleDiff,: Selection of single-ended or differential input. This parameter can be one of the following values:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
CalibrationFactor,: Calibration factor (coded on 7 bits maximum)
Return values:
HAL state

Definition at line 324 of file stm32l4xx_hal_adc_ex.c.

References ADC_CALFACT_DIFF_SET, ADC_DIFFERENTIAL_ENDED, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_IS_ENABLE, assert_param, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Instance, IS_ADC_CALFACT, IS_ADC_SINGLE_DIFFERENTIAL, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_Calibration_Start | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff
 | ) |  |

Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).

Parameters:
hadc,: ADC handle.
SingleDiff,: Selection of single-ended or differential input This parameter can be one of the following values:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
Return values:
HAL status

Definition at line 216 of file stm32l4xx_hal_adc_ex.c.

References ADC_CALIBRATION_TIMEOUT, ADC_Disable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, IS_ADC_SINGLE_DIFFERENTIAL, and ADC_HandleTypeDef::State.

void HAL_ADCEx_EndOfSamplingCallback ( ADC_HandleTypeDef * hadc )

End Of Sampling callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1286 of file stm32l4xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

void HAL_ADCEx_InjectedConvCpltCallback ( ADC_HandleTypeDef * hadc )

Injected conversion complete callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1220 of file stm32l4xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

uint32_t HAL_ADCEx_InjectedGetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | InjectedRank
 | ) |  |

Get ADC injected group conversion result.

Parameters:
hadc,: ADC handle
InjectedRank,: the converted ADC injected rank. This parameter can be one of the following values:
  • ADC_INJECTED_RANK_1 Injected Channel1 selected
  • ADC_INJECTED_RANK_2 Injected Channel2 selected
  • ADC_INJECTED_RANK_3 Injected Channel3 selected
  • ADC_INJECTED_RANK_4 Injected Channel4 selected
Note:
Reading JDRy register automatically clears JEOC flag. To reset JEOS flag the user must resort to the macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS).
Return values:
None

Definition at line 1184 of file stm32l4xx_hal_adc_ex.c.

References ADC_INJECTED_RANK_1, ADC_INJECTED_RANK_2, ADC_INJECTED_RANK_3, ADC_INJECTED_RANK_4, assert_param, ADC_HandleTypeDef::Instance, and IS_ADC_INJECTED_RANK.

HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for injected group conversion to be completed.

Parameters:
hadc,: ADC handle
Timeout,: Timeout value in millisecond.
Note:
Depending on hadc->Init.EOCSelection, JEOS or JEOC is checked and cleared depending on AUTDLY bit status.
Return values:
HAL status

Definition at line 563 of file stm32l4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE, ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, ADC_MASTER_REGISTER, assert_param, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

void HAL_ADCEx_InjectedQueueOverflowCallback ( ADC_HandleTypeDef * hadc )

Injected context queue overflow callback.

Note:
This callback is called if injected context queue is enabled (parameter "QueueInjectedContext" in injected channel configuration) and if a new injected context is set when queue is full (maximum 2 contexts).
Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1240 of file stm32l4xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

HAL_StatusTypeDef HAL_ADCEx_InjectedStart ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of injected group.

Note:
Interruptions enabled in this function: None.
Case of multimode enabled when multimode feature is available: HAL_ADCEx_InjectedStart() API must be called for ADC slave first, then for ADC master. For ADC slave, ADC is enabled only (conversion is not started). For ADC master, ADC is enabled and multimode conversion is started.
Parameters:
hadc,: ADC handle.
Return values:
HAL status

Definition at line 380 of file stm32l4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE, ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of injected group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : JEOC (end of conversion) or JEOS (end of sequence)
Case of multimode enabled (when multimode feature is enabled): HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, then for ADC master. For ADC slave, ADC is enabled only (conversion is not started). For ADC master, ADC is enabled and multimode conversion is started.
Parameters:
hadc,: ADC handle.
Return values:
HAL status.

Definition at line 717 of file stm32l4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE, ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IT_JEOC, ADC_IT_JEOS, ADC_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels, disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if regular conversion is on going, function HAL_ADC_Stop() must be used.
In case of auto-injection mode, HAL_ADC_Stop() must be used.
In case of multimode enabled (when multimode feature is available), HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. For ADC master, conversion is stopped and ADC is disabled. For ADC slave, ADC is disabled only (conversion stop of ADC master has already stopped conversion of ADC slave).
Parameters:
hadc,: ADC handle.
Return values:
None

Definition at line 507 of file stm32l4xx_hal_adc_ex.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_INJECTED_GROUP, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels, disable interruption of end-of-conversion.

Note:
Disable ADC peripheral if no regular conversion is on going.
If ADC must be disabled and if regular conversion is on going, function HAL_ADC_Stop must be used first.
Case of multimode enabled (when multimode feature is available): HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, then for ADC slave. For ADC master, conversion is stopped and ADC is disabled. For ADC slave, ADC is disabled only (conversion stop of ADC master has already stopped conversion of ADC slave).
In case of auto-injection mode, HAL_ADC_Stop() must be used.
Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 864 of file stm32l4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_JQOVF, ADC_INJECTED_GROUP, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IT_JEOC, ADC_IT_JEOS, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

void HAL_ADCEx_LevelOutOfWindow2Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 2 callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1255 of file stm32l4xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

void HAL_ADCEx_LevelOutOfWindow3Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 3 callback in non-blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1270 of file stm32l4xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

uint32_t HAL_ADCEx_MultiModeGetValue ( ADC_HandleTypeDef * hadc )

Return the last ADC Master and Slave regular conversions results when in multimode configuration.

Parameters:
hadc,: ADC handle of ADC Master (handle of ADC Slave must not be used)
Return values:
The converted data values.

Definition at line 1154 of file stm32l4xx_hal_adc_ex.c.

References ADC_COMMON_REGISTER, assert_param, and ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enable ADC, start MultiMode conversion and transfer regular results through DMA.

Note:
Multimode must have been previously configured using HAL_ADCEx_MultiModeConfigChannel() function. Interruptions enabled in this function: overrun, DMA half transfer, DMA transfer complete. Each of these interruptions has its dedicated callback function.
State field of Slave ADC handle is not updated in this configuration: user should not rely on it for information related to Slave regular conversions.
Parameters:
hadc,: ADC handle of ADC master (handle of ADC slave must not be used)
pData,: Destination Buffer address.
Length,: Length of data to be transferred from ADC peripheral to memory (in bytes).
Return values:
None

Definition at line 931 of file stm32l4xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_COMMON_REGISTER, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, ADC_InitTypeDef::DMAContinuousRequests, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_EXTTRIG_EDGE, ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.

Note:
Multimode is kept enabled after this function. MultiMode DMA bits (MDMA and DMACFG bits of common CCR register) are maintained. To disable Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can resort to HAL_ADCEx_DisableMultiMode() API.
In case of DMA configured in circular mode, function HAL_ADC_Stop_DMA() must be called after this function with handle of ADC slave, to properly disable the DMA channel.
Parameters:
hadc,: ADC handle of ADC master (handle of ADC slave must not be used)
Return values:
None

Definition at line 1046 of file stm32l4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, ADC_STOP_CONVERSION_TIMEOUT, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_GetTick(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.

Note:
Multimode is kept enabled after this function. Multimode DMA bits (MDMA and DMACFG bits of common CCR register) are maintained. To disable multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can resort to HAL_ADCEx_DisableMultiMode() API.
In case of DMA configured in circular mode, function HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of ADC slave, to properly disable the DMA channel.
Parameters:
hadc,: ADC handle of ADC master (handle of ADC slave must not be used)
Return values:
None

Definition at line 1501 of file stm32l4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IT_OVR, ADC_MULTI_SLAVE, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, ADC_STOP_CONVERSION_TIMEOUT, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_GetTick(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular groups, disable ADC peripheral if no injected conversion is on-going.

Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1303 of file stm32l4xx_hal_adc_ex.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular groups and disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.

Note:
HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. For multimode (when multimode feature is available), HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1414 of file stm32l4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IT_OVR, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular groups when interruptions are enabled, disable ADC peripheral if no injected conversion is on-going.

Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1357 of file stm32l4xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
ADC Extended Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure the ADC injected group and the selected channel to be linked to the injected group.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on injected group
      (+) Configure multimode when multimode feature is available
      (+) Enable or Disable Injected Queue
      (+) Disable ADC voltage regulator
      (+) Enter ADC deep-power-down mode

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue ( ADC_HandleTypeDef * hadc )

Disable Injected Queue.

Note:
This function sets CFGR register JQDIS bit in order to disable the Injected Queue. JQDIS can be written only when ADSTART and JDSTART are both equal to 0 to ensure that no regular nor injected conversion is ongoing.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 2311 of file stm32l4xx_hal_adc_ex.c.

References ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, and ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator ( ADC_HandleTypeDef * hadc )

Disable ADC voltage regulator.

Note:
Disabling voltage regulator allows to save power. This operation can be carried out only when ADC is disabled.
To enable again the voltage regulator, the user is expected to resort to HAL_ADC_Init() API.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 2337 of file stm32l4xx_hal_adc_ex.c.

References ADC_IS_ENABLE, and ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue ( ADC_HandleTypeDef * hadc )

Enable Injected Queue.

Note:
This function resets CFGR register JQDIS bit in order to enable the Injected Queue. JQDIS can be written only when ADSTART and JDSTART are both equal to 0 to ensure that no regular nor injected conversion is ongoing.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 2282 of file stm32l4xx_hal_adc_ex.c.

References ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, HAL_ADC_STATE_INJ_JQOVF, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode ( ADC_HandleTypeDef * hadc )

Enter ADC deep-power-down mode.

Note:
This mode is achieved in setting DEEPPWD bit and allows to save power in reducing leakage currents. It is particularly interesting before entering stop modes.
Setting DEEPPWD automatically clears ADVREGEN bit and disables the ADC voltage regulator. This means that this API encompasses HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal calibration is lost.
To exit the ADC deep-power-down mode, the user is expected to resort to HAL_ADC_Init() API as well as to relaunch a calibration with HAL_ADCEx_Calibration_Start() API or to re-apply a previously saved calibration factor.
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 2368 of file stm32l4xx_hal_adc_ex.c.

References ADC_IS_ENABLE, and ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_InjectionConfTypeDef * | sConfigInjected
 | ) |  |

Configure the ADC injected group and the selected channel to be linked to the injected group.

Note:
Possibility to update parameters on the fly: This function initializes injected group, consecutive calls to this function can be used to reconfigure some parameters of structure "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_InjectionConfTypeDef".
In case of usage of internal measurement channels (Vbat/VrefInt/TempSensor), The internal paths can be disabled using function HAL_ADC_DeInit().
To reset injected sequencer, function HAL_ADCEx_InjectedStop() can be used.
Caution: For Injected Context Queue use, a context must be fully defined before start of injected conversion. All channels are configured consecutively for the same ADC instance. Therefore, the number of calls to HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter InjectedNbrOfConversion for each context.
  • Example 1: If 1 context is intended to be used (or if there is no use of the Injected Queue Context feature) and if the context contains 3 injected ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be called once for each channel (i.e. 3 times) before starting a conversion. This function must not be called to configure a 4th injected channel: it would start a new context into context queue.
  • Example 2: If 2 contexts are intended to be used and each of them contains 3 injected ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and for each context (3 channels x 2 contexts = 6 calls). Conversion can start once the 1st context is set, that is after the first three HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
Parameters:
hadc,: ADC handle
sConfigInjected,: Structure of ADC injected group and ADC channel for injected group.
Return values:
None

Definition at line 1678 of file stm32l4xx_hal_adc_ex.c.

References ADC_ANY_OTHER_ENABLED, ADC_BATTERY_VOLTAGE_INSTANCE, ADC_CFGR2_INJ_FIELDS, ADC_CFGR_INJECT_CONTEXT_QUEUE, ADC_CFGR_INJECT_DISCCONTINUOUS, ADC_CHANNEL_10, ADC_CHANNEL_9, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_COMMON_REGISTER, ADC_DIFFERENTIAL_ENDED, ADC_DIFSEL_CHANNEL, ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, ADC_GET_RESOLUTION, ADC_INJECTED_RANK_1, ADC_INJECTED_SOFTWARE_START, ADC_IS_CONVERSION_ONGOING_INJECTED, ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED, ADC_IS_ENABLE, ADC_JSQR_FIELDS, ADC_JSQR_RK, ADC_OFFSET_1, ADC_OFFSET_2, ADC_OFFSET_3, ADC_OFFSET_4, ADC_OFFSET_NONE, ADC_OFFSET_SHIFT_RESOLUTION, ADC_OFR_CHANNEL, ADC_SCAN_DISABLE, ADC_SMPR1_SETTING, ADC_SMPR2_SETTING, ADC_TEMPERATURE_SENSOR_INSTANCE, ADC_TEMPSENSOR_DELAY_US, ADC_VREFINT_INSTANCE, assert_param, ADC_InjectionConfTypeDef::AutoInjectedConv, ADC_InjectionConfigTypeDef::ChannelCount, ADC_InjectionConfigTypeDef::ContextQueue, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InjectionConfTypeDef::ExternalTrigInjecConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Init, ADC_InjectionConfTypeDef::InjecOversampling, ADC_InjectionConfTypeDef::InjecOversamplingMode, ADC_InjectionConfTypeDef::InjectedChannel, ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode, ADC_InjectionConfTypeDef::InjectedNbrOfConversion, ADC_InjectionConfTypeDef::InjectedOffset, ADC_InjectionConfTypeDef::InjectedOffsetNumber, ADC_InjectionConfTypeDef::InjectedRank, ADC_InjectionConfTypeDef::InjectedSamplingTime, ADC_InjectionConfTypeDef::InjectedSingleDiff, ADC_HandleTypeDef::InjectionConfig, ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_DIFF_CHANNEL, IS_ADC_EXTTRIGINJEC, IS_ADC_EXTTRIGINJEC_EDGE, IS_ADC_INJECTED_NB_CONV, IS_ADC_INJECTED_RANK, IS_ADC_OFFSET_NUMBER, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_RANGE, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SAMPLE_TIME, IS_ADC_SINGLE_DIFFERENTIAL, ADC_InjectionConfTypeDef::QueueInjectedContext, ADC_InjOversamplingTypeDef::Ratio, ADC_InjOversamplingTypeDef::RightBitShift, ADC_InitTypeDef::ScanConvMode, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_MultiModeTypeDef * | multimode
 | ) |  |

Enable ADC multimode and configure multimode parameters.

Note:
Possibility to update parameters on the fly: This function initializes multimode parameters, following calls to this function can be used to reconfigure some parameters of structure "ADC_MultiModeTypeDef" on the fly, without resetting the ADCs. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_MultiModeTypeDef".
To move back configuration from multimode to single mode, ADC must be reset (using function HAL_ADC_Init() ).
Parameters:
hadc,: Master ADC handle
multimode : Structure of ADC multimode configuration
Return values:
HAL status

Definition at line 2182 of file stm32l4xx_hal_adc_ex.c.

References ADC_CCR_MULTI_DMACONTREQ, ADC_COMMON_REGISTER, ADC_IS_CONVERSION_ONGOING_REGULAR, ADC_IS_ENABLE, ADC_MODE_INDEPENDENT, ADC_MULTI_SLAVE, assert_param, ADC_MultiModeTypeDef::DMAAccessMode, ADC_InitTypeDef::DMAContinuousRequests, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_DMA_ACCESS_MULTIMODE, IS_ADC_MULTIMODE, IS_ADC_SAMPLING_DELAY, ADC_MultiModeTypeDef::Mode, ADC_HandleTypeDef::State, and ADC_MultiModeTypeDef::TwoSamplingDelay.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InitTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC initialization and regular group. More...

#include <stm32l4xx_hal_adc_ex.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | Resolution
uint32_t | DataAlign
uint32_t | ScanConvMode
uint32_t | EOCSelection
uint32_t | LowPowerAutoWait
uint32_t | ContinuousConvMode
uint32_t | NbrOfConversion
uint32_t | DiscontinuousConvMode
uint32_t | NbrOfDiscConversion
uint32_t | ExternalTrigConv
uint32_t | ExternalTrigConvEdge
uint32_t | DMAContinuousRequests
uint32_t | Overrun
uint32_t | OversamplingMode
ADC_OversamplingTypeDef Oversampling

Detailed Description

Structure definition of ADC initialization and regular group.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope entire ADC (affects regular and injected groups): ClockPrescaler and ClockDivider, Resolution, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait.
  • Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
The setting of these parameters by function HAL_ADC_Init() is conditioned by ADC state. ADC state can be either:
  • For all parameters: ADC disabled
  • For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on regular group.
  • For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 78 of file stm32l4xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InitTypeDef::ClockPrescaler

Selects ADC clock source (asynchronous System/PLLSAI1/PLLSAI2 clocks or synchronous AHB clock) as well as the division factor applied to the clock. This parameter can be a value of ADC Clock Prescaler. Note: The clock is common for all the ADCs. Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the AHB clock prescaler is set to 1 and if the system clock has a 50% duty cycle. Note: This parameter can be modified only if all ADCs are disabled.

Definition at line 80 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ContinuousConvMode

Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after software start or external trigger occurred. This parameter can be set to ENABLE or DISABLE.

Definition at line 121 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::DataAlign

Specifies ADC data alignment (right or left). See reference manual for alignments formats versus resolutions. This parameter can be a value of ADC Data Alignment

Definition at line 94 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::DiscontinuousConvMode

Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE.

Definition at line 131 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InitTypeDef::DMAContinuousRequests

Specifies whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) or in Continuous mode (DMA transfer unlimited, whatever number of conversions). Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 150 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), HAL_ADCEx_MultiModeConfigChannel(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::EOCSelection

Specifies which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. This parameter can be a value of ADC End of Regular Sequence/Conversion.

Definition at line 106 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

uint32_t ADC_InitTypeDef::ExternalTrigConv

Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC External Trigger Source for Regular Group. Caution: external trigger source is common to ADCs.

Definition at line 141 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ExternalTrigConvEdge

Selects the external trigger edge of regular group. If set to ADC_EXTERNALTRIGCONVEDGE_NONE, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC External Trigger Source Edge for Regular Group

Definition at line 146 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::LowPowerAutoWait

Selects the dynamic low power Auto Delay: new conversion start only when the previous conversion (for regular group) or previous sequence (for injected group) has been processed by user software (EOC bit cleared or DR read for regular conversions, JEOS cleared for injected conversions). This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(), HAL_ADCEx_InjectedStart_IT()) when it is necessary to clear immediately the EOC flag to free the IRQ vector sequencer. Do use with polling: 1. Start conversion with HAL_ADC_Start() or HAL_ADCEx_InjectedStart(), 2. When conversion data is available: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. For injected conversion, resort to HAL_ADCEx_InjectedPollForConversion() then HAL_ADCEx_InjectedGetValue()

Definition at line 109 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfConversion

Specifies the number of ranks that will be converted within the regular group sequencer. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 125 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfDiscConversion

Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8.

Definition at line 137 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::Overrun

Select the behaviour in case of overrun: data overwritten or preserved (default). This parameter applies to regular group only. This parameter can be a value of ADC overrun. Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved by user-developped function HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear). Note: Error reporting with respect to the conversion mode:

  • Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
  • Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register).

Definition at line 157 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

ADC_OversamplingTypeDef ADC_InitTypeDef::Oversampling

Specifies the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 172 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::OversamplingMode

Specifies whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 168 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::Resolution

Configures the ADC resolution. This parameter can be a value of ADC Resolution

Definition at line 91 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ScanConvMode

Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, that defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or'InjectedNbrOfConversion'). Scan direction is upward: from rank 1 to rank 'n'. This parameter can be a value of ADC Scan Mode

Definition at line 98 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_adc_ex.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_HandleTypeDef Struct Reference
ADC Extended Exported Types

ADC handle Structure definition. More...

#include <stm32l4xx_hal_adc_ex.h>

Data Fields

ADC_TypeDef * | Instance
ADC_InitTypeDef Init
DMA_HandleTypeDef * DMA_Handle
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode
ADC_InjectionConfigTypeDef InjectionConfig

Detailed Description

ADC handle Structure definition.

Definition at line 181 of file stm32l4xx_hal_adc_ex.h.

Field Documentation

DMA_HandleTypeDef* ADC_HandleTypeDef::DMA_Handle

Pointer DMA Handler

Definition at line 187 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), and HAL_ADCEx_RegularStop_DMA().

__IO uint32_t ADC_HandleTypeDef::ErrorCode

ADC Error code

Definition at line 193 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAError(), ADC_Enable(), HAL_ADC_GetError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

ADC_InitTypeDef ADC_HandleTypeDef::Init

ADC initialization parameters and regular conversions setting

Definition at line 185 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_MultiModeConfigChannel(), and HAL_ADCEx_MultiModeStart_DMA().

ADC_InjectionConfigTypeDef ADC_HandleTypeDef::InjectionConfig

ADC injected channel configuration build-up structure

Definition at line 195 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

ADC_TypeDef* ADC_HandleTypeDef::Instance

Register base address

Definition at line 183 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

HAL_LockTypeDef ADC_HandleTypeDef::Lock

ADC locking object

Definition at line 189 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

__IO uint32_t ADC_HandleTypeDef::State

ADC communication state (bit-map of ADC states)

Definition at line 191 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_DMAError(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_adc_ex.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC_InjOversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjOversamplingTypeDef Struct Reference
ADC Extended Exported Types

ADC Injected Conversion Oversampling structure definition. More...

#include <stm32l4xx_hal_adc_ex.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift

Detailed Description

ADC Injected Conversion Oversampling structure definition.

Definition at line 202 of file stm32l4xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjOversamplingTypeDef::Ratio

Configures the oversampling ratio. This parameter can be a value of ADC Extended Oversampling Ratio

Definition at line 204 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjOversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of ADC Extended Oversampling Right Shift

Definition at line 207 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_adc_ex.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC_InjectionConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC injected group and ADC channel for injected group. More...

#include <stm32l4xx_hal_adc_ex.h>

Data Fields

uint32_t | InjectedChannel
uint32_t | InjectedRank
uint32_t | InjectedSamplingTime
uint32_t | InjectedSingleDiff
uint32_t | InjectedOffsetNumber
uint32_t | InjectedOffset
uint32_t | InjectedNbrOfConversion
uint32_t | InjectedDiscontinuousConvMode
uint32_t | AutoInjectedConv
uint32_t | QueueInjectedContext
uint32_t | ExternalTrigInjecConv
uint32_t | ExternalTrigInjecConvEdge
uint32_t | InjecOversamplingMode
ADC_InjOversamplingTypeDef InjecOversampling

Detailed Description

Structure definition of ADC injected group and ADC channel for injected group.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
  • Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv, InjecOversamplingMode, InjecOversampling.
The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned by ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
  • For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
  • For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
  • For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on regular and injected groups. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 229 of file stm32l4xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjectionConfTypeDef::AutoInjectedConv

Enables or disables the selected ADC automatic injected group conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled. Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 282 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConv

Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC Extended External Trigger Source for Injected Group. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 300 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge

Selects the external trigger edge of injected group. This parameter can be a value of ADC External Trigger Source Edge for Injected Group. If trigger edge is set to ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, external triggers are disabled and software trigger is used instead. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 305 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

ADC_InjOversamplingTypeDef ADC_InjectionConfTypeDef::InjecOversampling

Specifies the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 315 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjecOversamplingMode

Specifies whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 311 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedChannel

Configure the ADC injected channel. This parameter can be a value of ADC Channels Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability.

Definition at line 231 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode

Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, discontinuous mode converts the sequence channel by channel (only one channel at a time). Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 273 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedNbrOfConversion

Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 268 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffset

Defines the offset to be subtracted from the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 262 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffsetNumber

Selects the offset number. This parameter can be a value of ADC Extended Offset Number. Caution: Only one offset is allowed per channel. This parameter overwrites the last setting.

Definition at line 259 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedRank

The rank in the injected group sequencer. This parameter must be a value of ADC Extended Injected Channel Rank. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted).

Definition at line 234 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles. Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of ADC Sampling Times. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time setting). Refer to device DataSheet for timings values.

Definition at line 238 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSingleDiff

Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of ADC Extended Single-ended/Differential input mode. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)

Definition at line 248 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::QueueInjectedContext

Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).

Definition at line 290 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_adc_ex.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC_MultiModeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_MultiModeTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC multimode. More...

#include <stm32l4xx_hal_adc_ex.h>

Data Fields

uint32_t | Mode
uint32_t | DMAAccessMode
uint32_t | TwoSamplingDelay

Detailed Description

Structure definition of ADC multimode.

Note:
The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). Both Master and Slave ADCs must be disabled.

Definition at line 327 of file stm32l4xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_MultiModeTypeDef::DMAAccessMode

Configures the DMA mode for multimode ADC: selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) This parameter can be a value of ADC Extended DMA Mode for Dual ADC Mode.

Definition at line 331 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::Mode

Configures the ADC to operate in independent or multimode. This parameter can be a value of ADC Extended Dual ADC Mode.

Definition at line 329 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

uint32_t ADC_MultiModeTypeDef::TwoSamplingDelay

Configures the Delay between 2 sampling phases. This parameter can be a value of ADC Extended Delay Between 2 Sampling Phases. Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits.

Definition at line 334 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_adc_ex.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Extended Single-ended/Differential input mode

Defines
ADC Extended Single-ended/Differential input mode
ADC Extended Exported Constants

Defines

#define | ADC_SINGLE_ENDED ((uint32_t)0x00000000)
#define | ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF)

Define Documentation

#define ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF)

ADC channel set in differential mode

Definition at line 356 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SINGLE_ENDED ((uint32_t)0x00000000)

ADC channel set in single-ended input mode

Definition at line 355 of file stm32l4xx_hal_adc_ex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Extended Offset Number

Defines
ADC Extended Offset Number
ADC Extended Exported Constants

Defines

#define | ADC_OFFSET_NONE ((uint32_t)0x00)
#define | ADC_OFFSET_1 ((uint32_t)0x01)
#define | ADC_OFFSET_2 ((uint32_t)0x02)
#define | ADC_OFFSET_3 ((uint32_t)0x03)
#define | ADC_OFFSET_4 ((uint32_t)0x04)

Define Documentation

#define ADC_OFFSET_1 ((uint32_t)0x01)

Offset correction to apply to a first channel

Definition at line 365 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFFSET_2 ((uint32_t)0x02)

Offset correction to apply to a second channel

Definition at line 366 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFFSET_3 ((uint32_t)0x03)

Offset correction to apply to a third channel

Definition at line 367 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFFSET_4 ((uint32_t)0x04)

Offset correction to apply to a fourth channel

Definition at line 368 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFFSET_NONE ((uint32_t)0x00)

No offset correction

Definition at line 364 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

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STM32L486xx HAL User Manual: ADC Extended Regular Channel Rank

Defines
ADC Extended Regular Channel Rank
ADC Extended Exported Constants

Defines

#define | ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
#define | ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
#define | ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
#define | ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
#define | ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
#define | ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
#define | ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
#define | ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
#define | ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
#define | ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
#define | ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
#define | ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
#define | ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
#define | ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
#define | ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
#define | ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)

Define Documentation

#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)

ADC regular conversion rank 1

Definition at line 376 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)

ADC regular conversion rank 10

Definition at line 385 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)

ADC regular conversion rank 11

Definition at line 386 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)

ADC regular conversion rank 12

Definition at line 387 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)

ADC regular conversion rank 13

Definition at line 388 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)

ADC regular conversion rank 14

Definition at line 389 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)

ADC regular conversion rank 15

Definition at line 390 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)

ADC regular conversion rank 16

Definition at line 391 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)

ADC regular conversion rank 2

Definition at line 377 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)

ADC regular conversion rank 3

Definition at line 378 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)

ADC regular conversion rank 4

Definition at line 379 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)

ADC regular conversion rank 5

Definition at line 380 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)

ADC regular conversion rank 6

Definition at line 381 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)

ADC regular conversion rank 7

Definition at line 382 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)

ADC regular conversion rank 8

Definition at line 383 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)

ADC regular conversion rank 9

Definition at line 384 of file stm32l4xx_hal_adc_ex.h.

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STM32L486xx HAL User Manual: ADC Extended Injected Channel Rank

Defines
ADC Extended Injected Channel Rank
ADC Extended Exported Constants

Defines

#define | ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
#define | ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
#define | ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
#define | ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
#define | ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
#define | ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
#define | ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
#define | ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)

Define Documentation

#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)

ADC injected conversion rank 1

Definition at line 602 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)

ADC injected conversion rank 1

Definition at line 602 of file stm32l4xx_hal_adc_ex.h.

#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)

ADC injected conversion rank 2

Definition at line 603 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)

ADC injected conversion rank 2

Definition at line 603 of file stm32l4xx_hal_adc_ex.h.

#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)

ADC injected conversion rank 3

Definition at line 604 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)

ADC injected conversion rank 3

Definition at line 604 of file stm32l4xx_hal_adc_ex.h.

#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)

ADC injected conversion rank 4

Definition at line 605 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)

ADC injected conversion rank 4

Definition at line 605 of file stm32l4xx_hal_adc_ex.h.

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STM32L486xx HAL User Manual: ADC External Trigger Source Edge for Injected Group

Defines
ADC External Trigger Source Edge for Injected Group
ADC Extended Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)

Injected conversions hardware trigger detection on the falling edge

Definition at line 412 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)

Injected conversions hardware trigger detection disabled

Definition at line 410 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)

Injected conversions hardware trigger detection on the rising edge

Definition at line 411 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)

Injected conversions hardware trigger detection on both the rising and falling edges

Definition at line 413 of file stm32l4xx_hal_adc_ex.h.

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STM32L486xx HAL User Manual: ADC Extended External Trigger Source for Injected Group

Defines
ADC Extended External Trigger Source for Injected Group
ADC Extended Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
#define | ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
#define | ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
#define | ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)

Define Documentation

#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))

Event 6 triggers injected group conversion start

Definition at line 427 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)

Event 15 triggers injected group conversion start

Definition at line 436 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)

Event 1 triggers injected group conversion start

Definition at line 422 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)

Event 0 triggers injected group conversion start

Definition at line 421 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)

Event 8 triggers injected group conversion start

Definition at line 429 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))

Event 3 triggers injected group conversion start

Definition at line 424 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)

Event 2 triggers injected group conversion start

Definition at line 423 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))

Event 13 triggers injected group conversion start

Definition at line 434 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))

Event 11 triggers injected group conversion start

Definition at line 432 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)

Event 4 triggers injected group conversion start

Definition at line 425 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))

Event 12 triggers injected group conversion start

Definition at line 433 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))

Event 5 triggers injected group conversion start

Definition at line 426 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))

Event 14 triggers injected group conversion start

Definition at line 435 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))

Event 7 triggers injected group conversion start

Definition at line 428 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))

Event 9 triggers injected group conversion start

Definition at line 430 of file stm32l4xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))

Event 10 triggers injected group conversion start

Definition at line 431 of file stm32l4xx_hal_adc_ex.h.

#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)

Software triggers injected group conversion start

Definition at line 438 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

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STM32L486xx HAL User Manual: ADC Extended Dual ADC Mode

Defines
ADC Extended Dual ADC Mode
ADC Extended Exported Constants

Defines

#define | ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000))
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1))
#define | ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1))
#define | ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0))

Define Documentation

#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0))

Alternate trigger mode only

Definition at line 454 of file stm32l4xx_hal_adc_ex.h.

#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0))

Injected simultaneous mode only

Definition at line 451 of file stm32l4xx_hal_adc_ex.h.

#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))

Interleaved mode only

Definition at line 453 of file stm32l4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))

Combined Interleaved mode + injected simultaneous mode

Definition at line 450 of file stm32l4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1))

Regular simultaneous mode only

Definition at line 452 of file stm32l4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1))

Combined regular simultaneous + alternate trigger mode

Definition at line 449 of file stm32l4xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0))

Combined regular simultaneous + injected simultaneous mode

Definition at line 448 of file stm32l4xx_hal_adc_ex.h.

#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000))

Independent ADC conversions mode

Definition at line 447 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

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STM32L486xx HAL User Manual: ADC Extended DMA Mode for Dual ADC Mode

Defines
ADC Extended DMA Mode for Dual ADC Mode
ADC Extended Exported Constants

Defines

#define | ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000)
#define | ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC_CCR_MDMA_1)
#define | ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC_CCR_MDMA)

Define Documentation

#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC_CCR_MDMA_1)

DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution

Definition at line 463 of file stm32l4xx_hal_adc_ex.h.

#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC_CCR_MDMA)

DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution

Definition at line 464 of file stm32l4xx_hal_adc_ex.h.

#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000)

DMA multimode disabled: each ADC uses its own DMA channel

Definition at line 462 of file stm32l4xx_hal_adc_ex.h.

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STM32L486xx HAL User Manual: ADC Extended Delay Between 2 Sampling Phases

Defines
ADC Extended Delay Between 2 Sampling Phases
ADC Extended Exported Constants

Defines

#define | ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000))
#define | ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2))
#define | ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3))
#define | ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

Define Documentation

#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))

10 ADC clock cycles delay (lower for non 12-bit resolution)

Definition at line 481 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))

11 ADC clock cycles delay (lower for non 12-bit resolution)

Definition at line 482 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

12 ADC clock cycles delay (lower for non 12-bit resolution)

Definition at line 483 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000))

1 ADC clock cycle delay

Definition at line 472 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0))

2 ADC clock cycles delay

Definition at line 473 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1))

3 ADC clock cycles delay

Definition at line 474 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

4 ADC clock cycles delay

Definition at line 475 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2))

5 ADC clock cycles delay

Definition at line 476 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))

6 ADC clock cycles delay

Definition at line 477 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))

7 ADC clock cycles delay (lower for non 12-bit resolution)

Definition at line 478 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))

8 ADC clock cycles delay (lower for non 12-bit resolution)

Definition at line 479 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3))

9 ADC clock cycles delay (lower for non 12-bit resolution)

Definition at line 480 of file stm32l4xx_hal_adc_ex.h.

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STM32L486xx HAL User Manual: ADC Extended Analog Watchdog Selection

Defines
ADC Extended Analog Watchdog Selection
ADC Extended Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001)
#define | ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002)
#define | ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003)

Define Documentation

#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001)

Analog watchdog 1 selection

Definition at line 501 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002)

Analog watchdog 2 selection

Definition at line 502 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003)

Analog watchdog 3 selection

Definition at line 503 of file stm32l4xx_hal_adc_ex.h.

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STM32L486xx HAL User Manual: ADC Extended Analog Watchdog Mode

Defines
ADC Extended Analog Watchdog Mode
ADC Extended Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))

Define Documentation

#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)

Analog watchdog applied to injected group all channels

Definition at line 516 of file stm32l4xx_hal_adc_ex.h.

#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)

Analog watchdog applied to regular group all channels

Definition at line 515 of file stm32l4xx_hal_adc_ex.h.

#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))

Analog watchdog applied to regular and injected groups all channels

Definition at line 517 of file stm32l4xx_hal_adc_ex.h.

#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)

No analog watchdog selected

Definition at line 511 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))

Analog watchdog applied to an injected group single channel

Definition at line 513 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))

Analog watchdog applied to a regular group single channel

Definition at line 512 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))

Analog watchdog applied to a regular and injected groups single channel

Definition at line 514 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

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STM32L486xx HAL User Manual: ADC Extended Conversion Group

Defines
ADC Extended Conversion Group
ADC Extended Exported Constants

Defines

#define | ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
#define | ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))
#define | ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))

Define Documentation

#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))

ADC injected group selection

Definition at line 526 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))

ADC regular group selection

Definition at line 525 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))

ADC regular and injected groups selection

Definition at line 527 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), and HAL_ADCEx_MultiModeStop_DMA().

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STM32L486xx HAL User Manual: ADC Extended Event Type

Defines
ADC Extended Event Type
ADC Extended Exported Constants

Defines

#define | ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
#define | ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF)
#define | ADC_AWD_EVENT ADC_AWD1_EVENT

Define Documentation

#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1)

ADC Analog watchdog 1 event (main analog watchdog)

Definition at line 536 of file stm32l4xx_hal_adc_ex.h.

#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2)

ADC Analog watchdog 2 event (additional analog watchdog)

Definition at line 537 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3)

ADC Analog watchdog 3 event (additional analog watchdog)

Definition at line 538 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_AWD_EVENT ADC_AWD1_EVENT

ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 542 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP)

ADC End of Sampling event

Definition at line 535 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF)

ADC Injected Context Queue Overflow event

Definition at line 540 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)

ADC overrun event

Definition at line 539 of file stm32l4xx_hal_adc_ex.h.

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STM32L486xx HAL User Manual: ADC Extended Interrupts Definition

Defines
ADC Extended Interrupts Definition
ADC Extended Exported Constants

Defines

#define | ADC_IT_RDY ADC_IER_ADRDY
#define | ADC_IT_EOSMP ADC_IER_EOSMP
#define | ADC_IT_EOC ADC_IER_EOC
#define | ADC_IT_EOS ADC_IER_EOS
#define | ADC_IT_OVR ADC_IER_OVR
#define | ADC_IT_JEOC ADC_IER_JEOC
#define | ADC_IT_JEOS ADC_IER_JEOS
#define | ADC_IT_AWD1 ADC_IER_AWD1
#define | ADC_IT_AWD2 ADC_IER_AWD2
#define | ADC_IT_AWD3 ADC_IER_AWD3
#define | ADC_IT_JQOVF ADC_IER_JQOVF
#define | ADC_IT_AWD ADC_IT_AWD1

Define Documentation

#define ADC_IT_AWD ADC_IT_AWD1

ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 562 of file stm32l4xx_hal_adc_ex.h.

#define ADC_IT_AWD1 ADC_IER_AWD1

ADC Analog watchdog 1 interrupt source (main analog watchdog)

Definition at line 557 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD2 ADC_IER_AWD2

ADC Analog watchdog 2 interrupt source (additional analog watchdog)

Definition at line 558 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD3 ADC_IER_AWD3

ADC Analog watchdog 3 interrupt source (additional analog watchdog)

Definition at line 559 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_EOC ADC_IER_EOC

ADC End of regular conversion interrupt source

Definition at line 552 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_IT(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_EOS ADC_IER_EOS

ADC End of regular sequence of conversions interrupt source

Definition at line 553 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_IT(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_EOSMP ADC_IER_EOSMP

ADC End of sampling interrupt source

Definition at line 551 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_JEOC ADC_IER_JEOC

ADC End of injected conversion interrupt source

Definition at line 555 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_JEOS ADC_IER_JEOS

ADC End of injected sequence of conversions interrupt source

Definition at line 556 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_JQOVF ADC_IER_JQOVF

ADC Injected Context Queue Overflow interrupt source

Definition at line 560 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_OVR ADC_IER_OVR

ADC overrun interrupt source

Definition at line 554 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_RDY ADC_IER_ADRDY

ADC Ready (ADRDY) interrupt source

Definition at line 550 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Extended Flags Definition

Defines
ADC Extended Flags Definition
ADC Extended Exported Constants

Defines

#define | ADC_FLAG_RDY ADC_ISR_ADRDY
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_JEOC ADC_ISR_JEOC
#define | ADC_FLAG_JEOS ADC_ISR_JEOS
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | ADC_FLAG_AWD ADC_FLAG_AWD1
#define | ADC_FLAG_ALL
#define | ADC_FLAG_POSTCONV_ALL

Define Documentation

#define ADC_FLAG_ALL
Value:
(ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS |  \
                         ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
                         ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)

ADC all flags

Definition at line 585 of file stm32l4xx_hal_adc_ex.h.

#define ADC_FLAG_AWD ADC_FLAG_AWD1

ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 583 of file stm32l4xx_hal_adc_ex.h.

#define ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC Analog watchdog 1 flag (main analog watchdog)

Definition at line 578 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC Analog watchdog 2 flag (additional analog watchdog)

Definition at line 579 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC Analog watchdog 3 flag (additional analog watchdog)

Definition at line 580 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_EOC ADC_ISR_EOC

ADC End of Regular Conversion flag

Definition at line 573 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_EOS ADC_ISR_EOS

ADC End of Regular sequence of Conversions flag

Definition at line 574 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC End of Sampling flag

Definition at line 572 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_JEOC ADC_ISR_JEOC

ADC End of Injected Conversion flag

Definition at line 576 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JEOS ADC_ISR_JEOS

ADC End of Injected sequence of Conversions flag

Definition at line 577 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JQOVF ADC_ISR_JQOVF

ADC Injected Context Queue Overflow flag

Definition at line 581 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_FLAG_OVR ADC_ISR_OVR

ADC overrun flag

Definition at line 575 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_POSTCONV_ALL
Value:
(ADC_FLAG_EOC | ADC_FLAG_EOS  | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
                               ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
                               ADC_FLAG_JQOVF)

ADC post-conversion all flags

Definition at line 590 of file stm32l4xx_hal_adc_ex.h.

#define ADC_FLAG_RDY ADC_ISR_ADRDY

ADC Ready (ADRDY) flag

Definition at line 571 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_Enable(), and HAL_ADC_DeInit().

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STM32L486xx HAL User Manual: ADC Extended Oversampling Ratio

Defines
ADC Extended Oversampling Ratio
ADC Extended Exported Constants

Defines

#define | ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000)
#define | ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0)
#define | ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1)
#define | ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0))
#define | ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2)
#define | ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0))
#define | ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1))
#define | ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR))

Define Documentation

#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1))

ADC Oversampling ratio 128x

Definition at line 622 of file stm32l4xx_hal_adc_ex.h.

#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0))

ADC Oversampling ratio 16x

Definition at line 619 of file stm32l4xx_hal_adc_ex.h.

#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000)

ADC Oversampling ratio 2x

Definition at line 616 of file stm32l4xx_hal_adc_ex.h.

#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR))

ADC Oversampling ratio 256x

Definition at line 623 of file stm32l4xx_hal_adc_ex.h.

#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2)

ADC Oversampling ratio 32x

Definition at line 620 of file stm32l4xx_hal_adc_ex.h.

#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0)

ADC Oversampling ratio 4x

Definition at line 617 of file stm32l4xx_hal_adc_ex.h.

#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0))

ADC Oversampling ratio 64x

Definition at line 621 of file stm32l4xx_hal_adc_ex.h.

#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1)

ADC Oversampling ratio 8x

Definition at line 618 of file stm32l4xx_hal_adc_ex.h.

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STM32L486xx HAL User Manual: ADC Extended Oversampling Right Shift

Defines
ADC Extended Oversampling Right Shift
ADC Extended Exported Constants

Defines

#define | ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000)
#define | ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0)
#define | ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1)
#define | ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2)
#define | ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1))
#define | ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3)

Define Documentation

#define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0)

ADC 1 bit shift for oversampling

Definition at line 632 of file stm32l4xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1)

ADC 2 bits shift for oversampling

Definition at line 633 of file stm32l4xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))

ADC 3 bits shift for oversampling

Definition at line 634 of file stm32l4xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2)

ADC 4 bits shift for oversampling

Definition at line 635 of file stm32l4xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0))

ADC 5 bits shift for oversampling

Definition at line 636 of file stm32l4xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1))

ADC 6 bits shift for oversampling

Definition at line 637 of file stm32l4xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))

ADC 7 bits shift for oversampling

Definition at line 638 of file stm32l4xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3)

ADC 8 bits shift for oversampling

Definition at line 639 of file stm32l4xx_hal_adc_ex.h.

#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000)

ADC No bit shift for oversampling

Definition at line 631 of file stm32l4xx_hal_adc_ex.h.

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STM32L486xx HAL User Manual: ADC Extended Triggered Regular Oversampling

Defines
ADC Extended Triggered Regular Oversampling
ADC Extended Exported Constants

Defines

#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS)

Define Documentation

#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS)

A trigger for each oversampled conversion

Definition at line 648 of file stm32l4xx_hal_adc_ex.h.

#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000)

A single trigger for all channel oversampled conversions

Definition at line 647 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

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STM32L486xx HAL User Manual: ADC Extended Regular Oversampling Continued or Resumed Mode

Defines
ADC Extended Regular Oversampling Continued or Resumed Mode
ADC Extended Exported Constants

Defines

#define | ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000)
#define | ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM)

Define Documentation

#define ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000)

Oversampling buffer maintained during injection sequence

Definition at line 656 of file stm32l4xx_hal_adc_ex.h.

#define ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM)

Oversampling buffer zeroed during injection sequence

Definition at line 657 of file stm32l4xx_hal_adc_ex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Sampling Times

Defines
ADC Sampling Times
ADC Extended Exported Constants

Defines

#define | ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)0x00000000)
#define | ADC_SAMPLETIME_6CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0)
#define | ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1)
#define | ADC_SAMPLETIME_24CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0))
#define | ADC_SAMPLETIME_47CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2)
#define | ADC_SAMPLETIME_92CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0))
#define | ADC_SAMPLETIME_247CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1))
#define | ADC_SAMPLETIME_640CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10)

Define Documentation

#define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1)

Sampling time 12.5 ADC clock cycles

Definition at line 667 of file stm32l4xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_247CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1))

Sampling time 247.5 ADC clock cycles

Definition at line 671 of file stm32l4xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_24CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0))

Sampling time 24.5 ADC clock cycles

Definition at line 668 of file stm32l4xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)0x00000000)

Sampling time 2.5 ADC clock cycle

Definition at line 665 of file stm32l4xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_47CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2)

Sampling time 47.5 ADC clock cycles

Definition at line 669 of file stm32l4xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_640CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10)

Sampling time 640.5 ADC clock cycles

Definition at line 672 of file stm32l4xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_6CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0)

Sampling time 6.5 ADC clock cycles

Definition at line 666 of file stm32l4xx_hal_adc_ex.h.

#define ADC_SAMPLETIME_92CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0))

Sampling time 92.5 ADC clock cycles

Definition at line 670 of file stm32l4xx_hal_adc_ex.h.

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STM32L486xx HAL User Manual: ADCx CFGR fields

Defines
ADCx CFGR fields
ADC Extended Exported Constants

Defines

#define ADC_CFGR_FIELDS

Define Documentation

#define ADC_CFGR_FIELDS
Value:
(ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
                            ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
                            ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
                            ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
                            ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
                            ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )

Definition at line 680 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

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STM32L486xx HAL User Manual: ADCx SMPR1 fields

Defines
ADCx SMPR1 fields
ADC Extended Exported Constants

Defines

#define ADC_SMPR1_FIELDS

Define Documentation

#define ADC_SMPR1_FIELDS
Value:
(ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
                             ADC_SMPR1_SMP0)

Definition at line 693 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADCx CFGR sub fields

Defines
ADCx CFGR sub fields
ADC Extended Exported Constants

Defines

#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))

Define Documentation

#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))

Definition at line 706 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Extended Private Macros

Defines
ADC Extended Private Macros
ADCEx

Defines

#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)
Check if conversion is on going on regular or injected groups.
#define | ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)
Check if conversion is on going on injected group.
#define | ADC_IS_INDEPENDENT(__HANDLE__)
Check whether or not ADC is independent.
#define | ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
Set the sample time for Channels numbers between 0 and 9.
#define | ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
Set the sample time for Channels numbers between 10 and 18.
#define | ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)
Write SMPR1 register.
#define | ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)
Write SMPR2 register.
#define | ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
Set the selected regular Channel rank for rank between 1 and 4.
#define | ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
Set the selected regular Channel rank for rank between 5 and 9.
#define | ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
Set the selected regular Channel rank for rank between 10 and 14.
#define | ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
Set the selected regular Channel rank for rank between 15 and 16.
#define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2))
Set the selected injected Channel rank.
#define | ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
Set the Analog Watchdog 1 channel.
#define | ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
Configure the channel number in Analog Watchdog 2 or 3.
#define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
Configure ADC injected context queue.
#define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN))
Configure ADC discontinuous conversion mode for injected group.
#define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
Configure ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
Configure the number of discontinuous conversions for regular group.
#define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
Configure the ADC auto delay mode.
#define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
Configure ADC continuous conversion mode.
#define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CFGR_DMACFG))
Configure the ADC DMA continuous request.
#define | ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
Configure the channel number into offset OFRx register.
#define | ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
Configure the channel number into differential mode selection register.
#define | ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
Configure calibration factor in differential mode to be set into calibration register.
#define | ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
Calibration factor in differential mode to be retrieved from calibration register.
#define | ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
#define | ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
Configure the ADC DMA continuous request for ADC multimode.
#define | ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
Enable the ADC peripheral.
#define | ADC_ENABLING_CONDITIONS(__HANDLE__)
Verification of hardware constraints before ADC can be enabled.
#define | ADC_DISABLE(__HANDLE__)
Disable the ADC peripheral.
#define | ADC_DISABLING_CONDITIONS(__HANDLE__)
Verification of hardware constraints before ADC can be disabled.
#define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
Shift the offset with respect to the selected ADC resolution.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
Shift the AWD1 threshold with respect to the selected ADC resolution.
#define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
#define | ADC_COMMON_REGISTER(__HANDLE__) (ADC123_COMMON)
Report ADC common register.
#define | ADC_MASTER_REGISTER(__HANDLE__)
Report Master Instance.
#define | ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__)
Clear Common Control Register.
#define | ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__)
Check whether or not dual conversions are enabled.
#define | ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)
Check whether or not dual regular conversions are enabled.
#define | ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
#define | ADC_INSTANCE_IS_ENABLED(__INSTANCE__)
Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
#define | ADC_ANY_OTHER_ENABLED(__HANDLE__)
Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
#define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
Set handle instance of the ADC slave associated to the ADC master.
#define | ADC_MULTIMODE_DMA_ENABLED()
Check whether or not multimode is configured in DMA mode.
#define | ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
Verify the ADC instance connected to the temperature sensor.
#define | ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
Verify the ADC instance connected to the battery voltage VBAT.
#define | ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
Verify the ADC instance connected to the internal voltage reference VREFINT.
#define | IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
Verify the length of scheduled injected conversions group.
#define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F))
Calibration factor size verification (7 bits maximum).
#define | IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting.
#define | IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting in differential mode.
#define | IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__)
Verify the ADC single-ended input or differential mode setting.
#define | IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__)
Verify the ADC offset management setting.
#define | IS_ADC_REGULAR_RANK(__CHANNEL__)
Verify the ADC regular channel setting.
#define | IS_ADC_INJECTED_RANK(__CHANNEL__)
Verify the ADC injected channel setting.
#define | IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__)
Verify the ADC edge trigger setting for injected group.
#define | IS_ADC_EXTTRIGINJEC(__INJTRIG__)
Verify the ADC injected conversions external trigger.
#define | IS_ADC_MULTIMODE(__MODE__)
Verify the ADC multimode setting.
#define | IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__)
Verify the ADC multimode DMA access setting.
#define | IS_ADC_SAMPLING_DELAY(__DELAY__)
Verify the ADC multimode delay setting.
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__)
Verify the ADC analog watchdog setting.
#define | IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__)
Verify the ADC analog watchdog mode setting.
#define | IS_ADC_CONVERSION_GROUP(__CONVERSION__)
Verify the ADC conversion (regular or injected or both).
#define | IS_ADC_EVENT_TYPE(__EVENT__)
Verify the ADC event type.
#define | IS_ADC_OVERSAMPLING_RATIO(__RATIO__)
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
Verify the ADC oversampling shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling triggered mode.
#define | IS_ADC_REGOVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling regular conversion resumed or continued mode.
#define | IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
Verify the DFSDM mode configuration.
#define | ADC_CFGR_DFSDM(__HANDLE__) (0x0)
Return the DFSDM configuration mode.

Define Documentation

#define ADC_ANY_OTHER_ENABLED ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1)                                      \
    )?                                                                      \
     (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3))     \
     :                                                                      \
     ( ( ((__HANDLE__)->Instance == ADC2)                                   \
       )?                                                                   \
         (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \
        :                                                                   \
          ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \
     )

Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)

Definition at line 1215 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __THRESHOLD__
 | ) | ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))

Shift the AWD1 threshold with respect to the selected ADC resolution.

Note:
Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2 ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If resolution 6 bits, shift of 6 ranks on the left. Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
Parameters:
__HANDLE__,: ADC handle
__THRESHOLD__,: Value to be shifted
Return values:
None

Definition at line 1029 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __THRESHOLD__
 | ) |
Value:
( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
            ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
            (__THRESHOLD__) << 2 )

Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.

Note:
Thresholds have to be left-aligned on bit 7. If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). If resolution 8 bits, no shift. If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
Parameters:
__HANDLE__,: ADC handle
__THRESHOLD__,: Value to be shifted
Return values:
None

Definition at line 1043 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_BATTERY_VOLTAGE_INSTANCE ( __HANDLE__ ) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))

Verify the ADC instance connected to the battery voltage VBAT.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 1281 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CALFACT_DIFF_GET ( __CALIBRATION_FACTOR__ ) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))

Calibration factor in differential mode to be retrieved from calibration register.

Parameters:
__CALIBRATION_FACTOR__,: Calibration factor value.
Return values:
None

Definition at line 942 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_Calibration_GetValue().

#define ADC_CALFACT_DIFF_SET ( __CALIBRATION_FACTOR__ ) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))

Configure calibration factor in differential mode to be set into calibration register.

Parameters:
__CALIBRATION_FACTOR__,: Calibration factor value.
Return values:
None

Definition at line 936 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_Calibration_SetValue().

#define ADC_CCR_MULTI_DMACONTREQ ( __DMACONTREQ_MODE__ ) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))

Configure the ADC DMA continuous request for ADC multimode.

Parameters:
__DMACONTREQ_MODE__,: DMA continuous request mode.
Return values:
None

Definition at line 957 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define ADC_CFGR_AUTOWAIT ( __AUTOWAIT__ ) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))

Configure the ADC auto delay mode.

Parameters:
__AUTOWAIT__,: Auto delay bit enable or disable.
Return values:
None

Definition at line 900 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_CONTINUOUS ( __CONTINUOUS_MODE__ ) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))

Configure ADC continuous conversion mode.

Parameters:
__CONTINUOUS_MODE__,: Continuous mode.
Return values:
None

Definition at line 907 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DFSDM ( __HANDLE__ ) (0x0)

Return the DFSDM configuration mode.

Parameters:
__HANDLE__,: ADC handle.
Note:
When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). For this reason, the input parameter is the ADC handle and not the configuration parameter directly.
Return values:
DFSDM configuration mode

Definition at line 1692 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DISCONTINUOUS_NUM ( __NBR_DISCONTINUOUS_CONV__ ) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))

Configure the number of discontinuous conversions for regular group.

Parameters:
__NBR_DISCONTINUOUS_CONV__,: Number of discontinuous conversions.
Return values:
None

Definition at line 893 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DMACONTREQ ( __DMACONTREQ_MODE__ ) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CFGR_DMACFG))

Configure the ADC DMA continuous request.

Parameters:
__DMACONTREQ_MODE__,: DMA continuous request mode.
Return values:
None

Definition at line 914 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_INJECT_CONTEXT_QUEUE ( __INJECT_CONTEXT_QUEUE_MODE__ ) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))

Configure ADC injected context queue.

Parameters:
__INJECT_CONTEXT_QUEUE_MODE__,: Injected context queue mode.
Return values:
None

Definition at line 873 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_INJECT_DISCCONTINUOUS ( __INJECT_DISCONTINUOUS_MODE__ ) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN))

Configure ADC discontinuous conversion mode for injected group.

Parameters:
__INJECT_DISCONTINUOUS_MODE__,: Injected discontinuous mode.
Return values:
None

Definition at line 880 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_REG_DISCONTINUOUS ( __REG_DISCONTINUOUS_MODE__ ) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))

Configure ADC discontinuous conversion mode for regular group.

Parameters:
__REG_DISCONTINUOUS_MODE__,: Regular discontinuous mode.
Return values:
None

Definition at line 887 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_SET_AWD1CH ( __CHANNEL__ ) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))

Set the Analog Watchdog 1 channel.

Parameters:
__CHANNEL__,: channel to be monitored by Analog Watchdog 1.
Return values:
None

Definition at line 859 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_CFGR_SET_AWD23CR ( __CHANNEL__ ) (1U << (__CHANNEL__))

Configure the channel number in Analog Watchdog 2 or 3.

Parameters:
__CHANNEL__,: ADC Channel
Return values:
None

Definition at line 866 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_CLEAR_COMMON_CONTROL_REGISTER ( __HANDLE__ )
Value:
CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \
                                                                                ADC_CCR_PRESC  | \
                                                                                ADC_CCR_VBATEN | \
                                                                                ADC_CCR_TSEN   | \
                                                                                ADC_CCR_VREFEN | \
                                                                                ADC_CCR_MDMA   | \
                                                                                ADC_CCR_DMACFG | \
                                                                                ADC_CCR_DELAY  | \
                                                                                ADC_CCR_DUAL  )

Clear Common Control Register.

Parameters:
__HANDLE__,: ADC handle.
Return values:
None

Definition at line 1086 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

#define ADC_COMMON_REGISTER ( __HANDLE__ ) (ADC123_COMMON)

Report ADC common register.

Parameters:
__HANDLE__,: ADC handle.
Return values:
Common control register

Definition at line 1055 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_DIFSEL_CHANNEL ( __CHANNEL__ ) (1U << (__CHANNEL__))

Configure the channel number into differential mode selection register.

Parameters:
__CHANNEL__,: ADC Channel.
Return values:
None

Definition at line 929 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_DISABLE ( __HANDLE__ )
Value:
do{                                                                          \
         (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS;                           \
          __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
  } while(0)

Disable the ADC peripheral.

Parameters:
__HANDLE__,: ADC handle.
Return values:
None

Definition at line 984 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_Disable().

#define ADC_DISABLING_CONDITIONS ( __HANDLE__ )
Value:
(( ( ((__HANDLE__)->Instance->CR) &                                     \
            (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
        ) ? SET : RESET)

Verification of hardware constraints before ADC can be disabled.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (ADC can be disabled) or RESET (ADC cannot be disabled)

Definition at line 995 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_Disable().

#define ADC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)

Enable the ADC peripheral.

Parameters:
__HANDLE__,: ADC handle.
Return values:
None

Definition at line 965 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_Enable().

#define ADC_ENABLING_CONDITIONS ( __HANDLE__ )
Value:
(( ( ((__HANDLE__)->Instance->CR) &                                    \
            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART |  \
             ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN                    ) \
           ) == RESET                                                         \
        ) ? SET : RESET)

Verification of hardware constraints before ADC can be enabled.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (ADC can be enabled) or RESET (ADC cannot be enabled)

Definition at line 972 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_Enable().

#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
    )?                                                                     \
     SET                                                                   \
     :                                                                     \
     ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))

Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.

Parameters:
__HANDLE__,: ADC handle.
Note:
Return SET if multimode feature is not available.
Return values:
SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)

Definition at line 1187 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)  \
    )?                                                                      \
     SET                                                                    \
     :                                                                      \
     ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
       ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))

Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.

Parameters:
__HANDLE__,: ADC handle.
Note:
Return SET if multimode feature is not available.
Return values:
SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)

Definition at line 1168 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_IT(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_INSTANCE_IS_ENABLED ( __INSTANCE__ )
Value:
(( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
          ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
        ) ? SET : RESET)

Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.

Parameters:
__INSTANCE__,: ADC instance.
Return values:
SET (ADC enabled) or RESET (ADC disabled)

Definition at line 1204 of file stm32l4xx_hal_adc_ex.h.

#define ADC_IS_CONVERSION_ONGOING_INJECTED ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET            \
        ) ? RESET : SET)

Check if conversion is on going on injected group.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (conversion is on going) or RESET (no conversion is on going).

Definition at line 747 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET  \
        ) ? RESET : SET)

Check if conversion is on going on regular or injected groups.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (conversion is on going) or RESET (no conversion is on going).

Definition at line 737 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_EnableInjectedQueue(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_IS_DUAL_CONVERSION_ENABLE ( __HANDLE__ )
Value:
( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
    )?                                                                           \
     ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)  )          \
     :                                                                           \
     RESET                                                                       \
  )

Check whether or not dual conversions are enabled.

Parameters:
__HANDLE__,: ADC handle.
Note:
Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
Return values:
SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)

Definition at line 1111 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler().

#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE ( __HANDLE__ )
Value:
( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
    )?                                                                           \
     ( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)     &&      \
       (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) &&      \
       (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) )         \
     :                                                                           \
     RESET                                                                       \
  )

Check whether or not dual regular conversions are enabled.

Parameters:
__HANDLE__,: ADC handle.
Note:
Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
Return values:
SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)

Definition at line 1129 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForConversion(), and HAL_ADC_Start_DMA().

#define ADC_IS_INDEPENDENT ( __HANDLE__ )
Value:
( ( ( ((__HANDLE__)->Instance) == ADC3) \
    )?                                    \
     SET                                  \
     :                                    \
     RESET                                \
  )

Check whether or not ADC is independent.

Parameters:
__HANDLE__,: ADC handle.
Note:
When multimode feature is not available, the macro always returns SET.
Return values:
SET (ADC is independent) or RESET (ADC is not).

Definition at line 760 of file stm32l4xx_hal_adc_ex.h.

#define ADC_IS_SOFTWARE_START_INJECTED ( __HANDLE__ ) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)

Test if conversion trigger of injected group is software start or external trigger.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (software start) or RESET (external trigger).

Definition at line 729 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_JSQR_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2))

Set the selected injected Channel rank.

Parameters:
__CHANNELNB__,: Channel number.
__RANKNB__,: Rank number.
Return values:
None

Definition at line 851 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_MASTER_REGISTER ( __HANDLE__ )
Value:
( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
    )?                                                                           \
     ((__HANDLE__)->Instance)                                                    \
     :                                                                           \
     (ADC1)                                                                      \
  )

Report Master Instance.

Parameters:
__HANDLE__,: ADC handle.
Note:
Return same instance if ADC of input handle is independent ADC or if multimode feature is not available.
Return values:
Master Instance

Definition at line 1068 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_IT(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_MULTI_SLAVE | ( | __HANDLE_MASTER__,
 |  | __HANDLE_SLAVE__
 | ) | ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )

Set handle instance of the ADC slave associated to the ADC master.

Parameters:
__HANDLE_MASTER__,: ADC master handle.
__HANDLE_SLAVE__,: ADC slave handle.
Note:
if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL.
Return values:
None

Definition at line 1239 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), and HAL_ADCEx_RegularMultiModeStop_DMA().

#define ADC_MULTIMODE_DMA_ENABLED ( )
Value:
((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \
  || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS))

Check whether or not multimode is configured in DMA mode.

Note:
Return RESET if multimode feature is not available.
Return values:
SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled)

Definition at line 1250 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForConversion().

#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER ( __HANDLE__ )
Value:
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)     \
    )?                                                                         \
     SET                                                                       \
     :                                                                         \
     ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
  )

Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.

Parameters:
__HANDLE__,: ADC handle.
Note:
Return SET if multimode feature is not available.
Return values:
SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode)

Definition at line 1150 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_OFFSET_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __OFFSET__
 | ) | ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))

Shift the offset with respect to the selected ADC resolution.

Note:
Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2 ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If resolution 6 bits, shift of 6 ranks on the left. Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
Parameters:
__HANDLE__,: ADC handle
__OFFSET__,: Value to be shifted
Return values:
None

Definition at line 1013 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFR_CHANNEL ( __CHANNEL__ ) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))

Configure the channel number into offset OFRx register.

Parameters:
__CHANNEL__,: ADC Channel.
Return values:
None

Definition at line 922 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SMPR1 | ( | __SAMPLETIME__,
 |  | __CHANNELNB__
 | ) | ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))

Set the sample time for Channels numbers between 0 and 9.

Parameters:
__SAMPLETIME__,: Sample time parameter.
__CHANNELNB__,: Channel number.
Return values:
None

Definition at line 778 of file stm32l4xx_hal_adc_ex.h.

#define ADC_SMPR1_SETTING | ( | __HANDLE__,
 |  | __SAMPLETIME__,
 |  | __CHANNELNB__
 | ) |
Value:
MODIFY_REG((__HANDLE__)->Instance->SMPR1,                  \
                               ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)),     \
                               ADC_SMPR1((__SAMPLETIME__), (__CHANNELNB__)))

Write SMPR1 register.

Parameters:
__HANDLE__ | : ADC handle.
__SAMPLETIME__,: Sample time parameter.
__CHANNELNB__ | : Channel number.
Return values:
None

Definition at line 795 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SMPR2 | ( | __SAMPLETIME__,
 |  | __CHANNELNB__
 | ) | ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))

Set the sample time for Channels numbers between 10 and 18.

Parameters:
__SAMPLETIME__,: Sample time parameter.
__CHANNELNB__,: Channel number.
Return values:
None

Definition at line 786 of file stm32l4xx_hal_adc_ex.h.

#define ADC_SMPR2_SETTING | ( | __HANDLE__,
 |  | __SAMPLETIME__,
 |  | __CHANNELNB__
 | ) |
Value:
MODIFY_REG((__HANDLE__)->Instance->SMPR2,                  \
                               ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)),    \
                               ADC_SMPR2((__SAMPLETIME__), (__CHANNELNB__)))

Write SMPR2 register.

Parameters:
__HANDLE__ | : ADC handle.
__SAMPLETIME__,: Sample time parameter.
__CHANNELNB__ | : Channel number.
Return values:
None

Definition at line 807 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SQR1_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))

Set the selected regular Channel rank for rank between 1 and 4.

Parameters:
__CHANNELNB__,: Channel number.
__RANKNB__,: Rank number.
Return values:
None

Definition at line 819 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR2_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))

Set the selected regular Channel rank for rank between 5 and 9.

Parameters:
__CHANNELNB__,: Channel number.
__RANKNB__,: Rank number.
Return values:
None

Definition at line 827 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR3_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))

Set the selected regular Channel rank for rank between 10 and 14.

Parameters:
__CHANNELNB__,: Channel number.
__RANKNB__,: Rank number.
Return values:
None

Definition at line 835 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR4_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))

Set the selected regular Channel rank for rank between 15 and 16.

Parameters:
__CHANNELNB__,: Channel number.
__RANKNB__,: Rank number.
Return values:
None

Definition at line 843 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_TEMPERATURE_SENSOR_INSTANCE ( __HANDLE__ ) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))

Verify the ADC instance connected to the temperature sensor.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 1268 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_TRX_HIGHTHRESHOLD ( __THRESHOLD__ ) ((__THRESHOLD__) << 16)

Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.

Parameters:
__THRESHOLD__,: Threshold value.
Return values:
None

Definition at line 949 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_VREFINT_INSTANCE ( __HANDLE__ ) (((__HANDLE__)->Instance) == ADC1)

Verify the ADC instance connected to the internal voltage reference VREFINT.

Parameters:
__HANDLE__,: ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 1290 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_ANALOG_WATCHDOG_MODE ( __WATCHDOG_MODE__ )
Value:
(((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)             || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )

Verify the ADC analog watchdog mode setting.

Parameters:
__WATCHDOG_MODE__,: programmed ADC analog watchdog mode setting.
Return values:
SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)

Definition at line 1599 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_ANALOG_WATCHDOG_NUMBER ( __WATCHDOG__ )
Value:
(((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )

Verify the ADC analog watchdog setting.

Parameters:
__WATCHDOG__,: programmed ADC analog watchdog setting.
Return values:
SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)

Definition at line 1590 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_CALFACT ( __CALIBRATION_FACTOR__ ) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F))

Calibration factor size verification (7 bits maximum).

Parameters:
__CALIBRATION_FACTOR__,: Calibration factor value.
Return values:
SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)

Definition at line 1306 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_Calibration_SetValue().

#define IS_ADC_CHANNEL | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |

Verify the ADC channel setting.

Parameters:
__HANDLE__,: ADC handle.
__CHANNEL__,: programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 1339 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_CONVERSION_GROUP ( __CONVERSION__ )
Value:
(((__CONVERSION__) == ADC_REGULAR_GROUP)     || \
                                             ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
                                             ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )

Verify the ADC conversion (regular or injected or both).

Parameters:
__CONVERSION__,: ADC conversion group.
Return values:
SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)

Definition at line 1612 of file stm32l4xx_hal_adc_ex.h.

Referenced by ADC_ConversionStop().

#define IS_ADC_DFSDMCFG_MODE ( __HANDLE__ ) (SET)

Verify the DFSDM mode configuration.

Parameters:
__HANDLE__,: ADC handle.
Note:
When DMSDFM configuration is not supported, the macro systematically reports SET. For this reason, the input parameter is the ADC handle and not the configuration parameter directly.
Return values:
SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)

Definition at line 1682 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_DIFF_CHANNEL | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
((((((__HANDLE__)->Instance) == ADC1)   || \
                                                         (((__HANDLE__)->Instance) == ADC2))  && \
                                                         (((__CHANNEL__) == ADC_CHANNEL_1)    || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_2)    || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_3)    || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_4)    || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_5)    || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_6)    || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_7)    || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_8)    || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_9)    || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_10)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_11)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_12)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_13)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_14)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_15))) || \
                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
                                                         (((__CHANNEL__) == ADC_CHANNEL_1)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_2)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_3)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_6)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_7)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_8)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_9)   || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_10)  || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_11)  || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_12)   )))

Verify the ADC channel setting in differential mode.

Parameters:
__HANDLE__,: ADC handle.
__CHANNEL__,: programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 1424 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_DMA_ACCESS_MULTIMODE ( __MODE__ )
Value:
(((__MODE__) == ADC_DMAACCESSMODE_DISABLED)   || \
                                               ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
                                               ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS)     )

Verify the ADC multimode DMA access setting.

Parameters:
__MODE__,: programmed ADC multimode DMA access setting.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1562 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_EVENT_TYPE ( __EVENT__ )
Value:
(((__EVENT__) == ADC_EOSMP_EVENT) || \
                                     ((__EVENT__) == ADC_AWD_EVENT)    || \
                                     ((__EVENT__) == ADC_AWD2_EVENT)   || \
                                     ((__EVENT__) == ADC_AWD3_EVENT)   || \
                                     ((__EVENT__) == ADC_OVR_EVENT)    || \
                                     ((__EVENT__) == ADC_JQOVF_EVENT)  )

Verify the ADC event type.

Parameters:
__EVENT__,: ADC event.
Return values:
SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)

Definition at line 1621 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define IS_ADC_EXTTRIGINJEC ( __INJTRIG__ )
Value:
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)    || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
                                                                                \
                                          ((__INJTRIG__) == ADC_SOFTWARE_START)                   )

Verify the ADC injected conversions external trigger.

Parameters:
__INJTRIG__,: programmed ADC injected conversions external trigger.
Return values:
SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)

Definition at line 1522 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_EXTTRIGINJEC_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)        || \
                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )

Verify the ADC edge trigger setting for injected group.

Parameters:
__EDGE__,: programmed ADC edge trigger setting.
Return values:
SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)

Definition at line 1511 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_NB_CONV ( __LENGTH__ ) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))

Verify the length of scheduled injected conversions group.

Parameters:
__LENGTH__,: number of programmed conversions.
Return values:
SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)

Definition at line 1298 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_RANK ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )

Verify the ADC injected channel setting.

Parameters:
__CHANNEL__,: programmed ADC injected channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 1501 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define IS_ADC_MULTIMODE ( __MODE__ )
Value:
(((__MODE__) == ADC_MODE_INDEPENDENT)          || \
                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
                               ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
                               ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
                               ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
                               ((__MODE__) == ADC_DUALMODE_INTERL)                || \
                               ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )

Verify the ADC multimode setting.

Parameters:
__MODE__,: programmed ADC multimode setting.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1548 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_OFFSET_NUMBER ( __OFFSET_NUMBER__ )
Value:
(((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )

Verify the ADC offset management setting.

Parameters:
__OFFSET_NUMBER__,: ADC offset management.
Return values:
SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)

Definition at line 1467 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_OVERSAMPLING_RATIO ( __RATIO__ )
Value:
(((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))

Verify the ADC oversampling ratio.

Parameters:
__RATIO__,: programmed ADC oversampling ratio.
Return values:
SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)

Definition at line 1633 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGOVERSAMPLING_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
                                               ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )

Verify the ADC oversampling regular conversion resumed or continued mode.

Parameters:
__MODE__,: programmed ADC oversampling regular conversion resumed or continued mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1670 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_REGULAR_RANK ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )

Verify the ADC regular channel setting.

Parameters:
__CHANNEL__,: programmed ADC regular channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 1478 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_RIGHT_BIT_SHIFT ( __SHIFT__ )
Value:
(((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))

Verify the ADC oversampling shift.

Parameters:
__SHIFT__,: programmed ADC oversampling shift.
Return values:
SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)

Definition at line 1647 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SAMPLING_DELAY ( __DELAY__ )
Value:
(((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES)   )

Verify the ADC multimode delay setting.

Parameters:
__DELAY__,: programmed ADC multimode delay setting.
Return values:
SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)

Definition at line 1571 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

#define IS_ADC_SINGLE_DIFFERENTIAL ( __SING_DIFF__ )
Value:
(((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
                                                   ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )

Verify the ADC single-ended input or differential mode setting.

Parameters:
__SING_DIFF__,: programmed channel setting.
Return values:
SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)

Definition at line 1459 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )

Verify the ADC oversampling triggered mode.

Parameters:
__MODE__,: programmed ADC oversampling triggered mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1662 of file stm32l4xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Transmit Constants

Defines
CAN Transmit Constants
CAN Private Constants

Defines

#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04)

Define Documentation

#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04)

CAN cell did not provide CAN_TxStatus_NoMailBox

Definition at line 688 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Private Constants

Modules | Defines
CAN Private Constants
CAN

Modules

CAN Transmit Constants

Defines

#define | CAN_TIMEOUT_VALUE 10
#define | CAN_FLAG_MASK ((uint32_t)0x000000FF)

Define Documentation

#define CAN_FLAG_MASK ((uint32_t)0x000000FF)

Definition at line 692 of file stm32l4xx_hal_can.h.

#define CAN_TIMEOUT_VALUE 10

Definition at line 122 of file stm32l4xx_hal_can.c.

Referenced by HAL_CAN_Init(), HAL_CAN_Sleep(), and HAL_CAN_WakeUp().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Private Functions

Functions
CAN Private Functions
CAN

Functions

static HAL_StatusTypeDef | CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receive a correct CAN frame.
static HAL_StatusTypeDef | CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiate and transmit a CAN frame message.

Function Documentation

static HAL_StatusTypeDef CAN_Receive_IT | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber
 | ) |  | [static]

Receive a correct CAN frame.

Parameters:
hcan,: Pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber,: Specify the FIFO number
Return values:
HAL status

Definition at line 1314 of file stm32l4xx_hal_can.c.

References __HAL_CAN_DISABLE_IT, __HAL_CAN_FIFO_RELEASE, CAN_FIFO0, CAN_FIFO1, CAN_ID_STD, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_LEC, CanRxMsgTypeDef::Data, CanRxMsgTypeDef::DLC, CanRxMsgTypeDef::ExtId, CanRxMsgTypeDef::FMI, HAL_CAN_RxCpltCallback(), HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, CanRxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, CAN_HandleTypeDef::pRxMsg, CanRxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanRxMsgTypeDef::StdId.

Referenced by HAL_CAN_IRQHandler().

static HAL_StatusTypeDef CAN_Transmit_IT ( CAN_HandleTypeDef * hcan ) [static]

Initiate and transmit a CAN frame message.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 1270 of file stm32l4xx_hal_can.c.

References __HAL_CAN_DISABLE_IT, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_LEC, CAN_IT_TME, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, HAL_CAN_TxCpltCallback(), and CAN_HandleTypeDef::State.

Referenced by HAL_CAN_IRQHandler().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CAN Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initialize the CAN peripheral according to the specified parameters in the CAN_InitStruct structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configure the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
DeInitialize the CAN peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initialize the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitialize the CAN MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the CAN.
      (+) De-initialize the CAN.

Function Documentation

HAL_StatusTypeDef HAL_CAN_ConfigFilter | ( | CAN_HandleTypeDef * | hcan,
 |  | CAN_FilterConfTypeDef * | sFilterConfig
 | ) |  |

Configure the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
sFilterConfig,: pointer to a CAN_FilterConfTypeDef structure that contains the filter configuration information.
Return values:
None

Definition at line 349 of file stm32l4xx_hal_can.c.

References assert_param, CAN_FilterConfTypeDef::BankNumber, CAN_FILTER_FIFO0, CAN_FILTER_FIFO1, CAN_FILTERMODE_IDMASK, CAN_FILTERSCALE_16BIT, CAN_FILTERSCALE_32BIT, CAN_FilterConfTypeDef::FilterActivation, CAN_FilterConfTypeDef::FilterFIFOAssignment, CAN_FilterConfTypeDef::FilterIdHigh, CAN_FilterConfTypeDef::FilterIdLow, CAN_FilterConfTypeDef::FilterMaskIdHigh, CAN_FilterConfTypeDef::FilterMaskIdLow, CAN_FilterConfTypeDef::FilterMode, CAN_FilterConfTypeDef::FilterNumber, CAN_FilterConfTypeDef::FilterScale, IS_CAN_BANKNUMBER, IS_CAN_FILTER_FIFO, IS_CAN_FILTER_MODE, IS_CAN_FILTER_NUMBER, and IS_CAN_FILTER_SCALE.

HAL_StatusTypeDef HAL_CAN_DeInit ( CAN_HandleTypeDef * hcan )

DeInitialize the CAN peripheral registers to their default reset values.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 449 of file stm32l4xx_hal_can.c.

References assert_param, HAL_CAN_MspDeInit(), HAL_CAN_STATE_BUSY, HAL_CAN_STATE_RESET, CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Init ( CAN_HandleTypeDef * hcan )

Initialize the CAN peripheral according to the specified parameters in the CAN_InitStruct structure and initialize the associated handle.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 166 of file stm32l4xx_hal_can.c.

References CAN_InitTypeDef::ABOM, assert_param, CAN_InitTypeDef::AWUM, CAN_InitTypeDef::BS1, CAN_InitTypeDef::BS2, CAN_INITSTATUS_FAILED, CAN_INITSTATUS_SUCCESS, CAN_TIMEOUT_VALUE, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_NONE, HAL_CAN_MspInit(), HAL_CAN_STATE_BUSY, HAL_CAN_STATE_ERROR, HAL_CAN_STATE_READY, HAL_CAN_STATE_RESET, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Init, CAN_HandleTypeDef::Instance, IS_CAN_BS1, IS_CAN_BS2, IS_CAN_MODE, IS_CAN_PRESCALER, IS_CAN_SJW, CAN_HandleTypeDef::Lock, CAN_InitTypeDef::Mode, CAN_InitTypeDef::NART, CAN_InitTypeDef::Prescaler, CAN_InitTypeDef::RFLM, CAN_InitTypeDef::SJW, CAN_HandleTypeDef::State, CAN_InitTypeDef::TTCM, and CAN_InitTypeDef::TXFP.

void HAL_CAN_MspDeInit ( CAN_HandleTypeDef * hcan )

DeInitialize the CAN MSP.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 498 of file stm32l4xx_hal_can.c.

Referenced by HAL_CAN_DeInit().

void HAL_CAN_MspInit ( CAN_HandleTypeDef * hcan )

Initialize the CAN MSP.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 482 of file stm32l4xx_hal_can.c.

Referenced by HAL_CAN_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
CAN Exported Functions

I/O operation functions. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiate and transmit a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiate and transmit a CAN frame message in Interrupt mode.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receive a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receive a correct CAN frame in Interrupt mode.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enter the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wake up the CAN peripheral from sleep mode (after that the CAN peripheral is in the normal mode).
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handle CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non-blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Reception complete callback in non-blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.

Detailed Description

I/O operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Transmit a CAN frame message.
      (+) Receive a CAN frame message.
      (+) Enter CAN peripheral in sleep mode.
      (+) Wake up the CAN peripheral from sleep mode.

Function Documentation

void HAL_CAN_ErrorCallback ( CAN_HandleTypeDef * hcan )

Error CAN callback.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1200 of file stm32l4xx_hal_can.c.

Referenced by HAL_CAN_IRQHandler().

void HAL_CAN_IRQHandler ( CAN_HandleTypeDef * hcan )

Handle CAN interrupt request.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1051 of file stm32l4xx_hal_can.c.

References __HAL_CAN_GET_FLAG, __HAL_CAN_GET_IT_SOURCE, __HAL_CAN_MSG_PENDING, __HAL_CAN_TRANSMIT_STATUS, CAN_FIFO0, CAN_FIFO1, CAN_FLAG_BOF, CAN_FLAG_EPV, CAN_FLAG_EWG, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_LEC, CAN_IT_TME, CAN_Receive_IT(), CAN_Transmit_IT(), CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_ACK, HAL_CAN_ERROR_BD, HAL_CAN_ERROR_BOF, HAL_CAN_ERROR_BR, HAL_CAN_ERROR_CRC, HAL_CAN_ERROR_EPV, HAL_CAN_ERROR_EWG, HAL_CAN_ERROR_FOR, HAL_CAN_ERROR_NONE, HAL_CAN_ERROR_STF, HAL_CAN_ErrorCallback(), HAL_CAN_STATE_READY, CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Receive | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber,
 |  | uint32_t | Timeout
 | ) |  |

Receive a correct CAN frame.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber,: FIFO number.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 775 of file stm32l4xx_hal_can.c.

References __HAL_CAN_FIFO_RELEASE, __HAL_CAN_MSG_PENDING, assert_param, CAN_FIFO0, CAN_FIFO1, CAN_ID_STD, CanRxMsgTypeDef::Data, CanRxMsgTypeDef::DLC, CanRxMsgTypeDef::ExtId, CanRxMsgTypeDef::FMI, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CanRxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_FIFO, CAN_HandleTypeDef::pRxMsg, CanRxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanRxMsgTypeDef::StdId.

HAL_StatusTypeDef HAL_CAN_Receive_IT | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber
 | ) |  |

Receive a correct CAN frame in Interrupt mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber,: FIFO number.
Return values:
HAL status

Definition at line 878 of file stm32l4xx_hal_can.c.

References __HAL_CAN_ENABLE_IT, assert_param, CAN_FIFO0, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_LEC, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_NONE, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, IS_CAN_FIFO, and CAN_HandleTypeDef::State.

void HAL_CAN_RxCpltCallback ( CAN_HandleTypeDef * hcan )

Reception complete callback in non-blocking mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1184 of file stm32l4xx_hal_can.c.

Referenced by CAN_Receive_IT().

HAL_StatusTypeDef HAL_CAN_Sleep ( CAN_HandleTypeDef * hcan )

Enter the Sleep (low power) mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status.

Definition at line 944 of file stm32l4xx_hal_can.c.

References CAN_TIMEOUT_VALUE, HAL_CAN_STATE_BUSY, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Transmit | ( | CAN_HandleTypeDef * | hcan,
 |  | uint32_t | Timeout
 | ) |  |

Initiate and transmit a CAN frame message.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 536 of file stm32l4xx_hal_can.c.

References __HAL_CAN_TRANSMIT_STATUS, assert_param, CAN_ID_STD, CAN_TXSTATUS_NOMAILBOX, CanTxMsgTypeDef::Data, CanTxMsgTypeDef::DLC, CanTxMsgTypeDef::ExtId, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_ERROR, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CanTxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_DLC, IS_CAN_EXTID, IS_CAN_IDTYPE, IS_CAN_RTR, IS_CAN_STDID, CAN_HandleTypeDef::pTxMsg, CanTxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanTxMsgTypeDef::StdId.

HAL_StatusTypeDef HAL_CAN_Transmit_IT ( CAN_HandleTypeDef * hcan )

Initiate and transmit a CAN frame message in Interrupt mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 663 of file stm32l4xx_hal_can.c.

References __HAL_CAN_ENABLE_IT, assert_param, CAN_ID_STD, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_LEC, CAN_IT_TME, CAN_TXSTATUS_NOMAILBOX, CanTxMsgTypeDef::Data, CanTxMsgTypeDef::DLC, CAN_HandleTypeDef::ErrorCode, CanTxMsgTypeDef::ExtId, HAL_CAN_ERROR_NONE, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, CanTxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_DLC, IS_CAN_EXTID, IS_CAN_IDTYPE, IS_CAN_RTR, IS_CAN_STDID, CAN_HandleTypeDef::pTxMsg, CanTxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanTxMsgTypeDef::StdId.

void HAL_CAN_TxCpltCallback ( CAN_HandleTypeDef * hcan )

Transmission complete callback in non-blocking mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1168 of file stm32l4xx_hal_can.c.

Referenced by CAN_Transmit_IT().

HAL_StatusTypeDef HAL_CAN_WakeUp ( CAN_HandleTypeDef * hcan )

Wake up the CAN peripheral from sleep mode (after that the CAN peripheral is in the normal mode).

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status.

Definition at line 999 of file stm32l4xx_hal_can.c.

References CAN_TIMEOUT_VALUE, HAL_CAN_STATE_BUSY, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
CAN Exported Functions

CAN Peripheral State functions. More...

Functions

HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
Return the CAN handle state.
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.

Detailed Description

CAN Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Check the CAN state.
      (+) Check CAN Errors detected during interrupt process.

Function Documentation

uint32_t HAL_CAN_GetError ( CAN_HandleTypeDef * hcan )

Return the CAN error code.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
CAN Error Code

Definition at line 1248 of file stm32l4xx_hal_can.c.

References CAN_HandleTypeDef::ErrorCode.

HAL_CAN_StateTypeDef HAL_CAN_GetState ( CAN_HandleTypeDef * hcan )

Return the CAN handle state.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL state

Definition at line 1236 of file stm32l4xx_hal_can.c.

References CAN_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Exported Types

Data Structures | Enumerations
CAN Exported Types
CAN

Data Structures

struct | CAN_InitTypeDef
CAN init structure definition. More...
struct | CAN_FilterConfTypeDef
CAN filter configuration structure definition. More...
struct | CanTxMsgTypeDef
CAN Tx message structure definition. More...
struct | CanRxMsgTypeDef
CAN Rx message structure definition. More...
struct | CAN_HandleTypeDef
CAN handle Structure definition. More...

Enumerations

enum HAL_CAN_StateTypeDef {
HAL_CAN_STATE_RESET = 0x00, HAL_CAN_STATE_READY = 0x01, HAL_CAN_STATE_BUSY = 0x02, HAL_CAN_STATE_BUSY_TX = 0x12,
HAL_CAN_STATE_BUSY_RX = 0x22, HAL_CAN_STATE_BUSY_TX_RX = 0x32, HAL_CAN_STATE_TIMEOUT = 0x03, HAL_CAN_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_CAN_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_CAN_STATE_RESET

CAN not yet initialized or disabled

HAL_CAN_STATE_READY

CAN initialized and ready for use

HAL_CAN_STATE_BUSY

CAN process is ongoing

HAL_CAN_STATE_BUSY_TX

CAN process is ongoing

HAL_CAN_STATE_BUSY_RX

CAN process is ongoing

HAL_CAN_STATE_BUSY_TX_RX

CAN process is ongoing

HAL_CAN_STATE_TIMEOUT

Timeout state

HAL_CAN_STATE_ERROR

CAN error state

Definition at line 65 of file stm32l4xx_hal_can.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_InitTypeDef Struct Reference
CAN Exported Types

CAN init structure definition. More...

#include <stm32l4xx_hal_can.h>

Data Fields

uint32_t | Prescaler
uint32_t | Mode
uint32_t | SJW
uint32_t | BS1
uint32_t | BS2
uint32_t | TTCM
uint32_t | ABOM
uint32_t | AWUM
uint32_t | NART
uint32_t | RFLM
uint32_t | TXFP

Detailed Description

CAN init structure definition.

Definition at line 81 of file stm32l4xx_hal_can.h.

Field Documentation

uint32_t CAN_InitTypeDef::ABOM

Enable or disable the automatic bus-off management. This parameter can be set to ENABLE or DISABLE

Definition at line 103 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::AWUM

Enable or disable the automatic wake-up mode. This parameter can be set to ENABLE or DISABLE

Definition at line 106 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::BS1

Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of CAN Time Quantum in Bit Segment 1

Definition at line 94 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::BS2

Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of CAN Time Quantum in Bit Segment 2

Definition at line 97 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::Mode

Specifies the CAN operating mode. This parameter can be a value of CAN Operating Mode

Definition at line 86 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::NART

Enable or disable the non-automatic retransmission mode. This parameter can be set to ENABLE or DISABLE

Definition at line 109 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::Prescaler

Specifies the length of a time quantum. This parameter must be a number between Min_Data = 1 and Max_Data = 1024

Definition at line 83 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::RFLM

Enable or disable the receive FIFO Locked mode. This parameter can be set to ENABLE or DISABLE

Definition at line 112 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::SJW

Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of CAN Synchronization Jump Width

Definition at line 89 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::TTCM

Enable or disable the time triggered communication mode. This parameter can be set to ENABLE or DISABLE.

Definition at line 100 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::TXFP

Enable or disable the transmit FIFO priority. This parameter can be set to ENABLE or DISABLE

Definition at line 115 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_can.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN_FilterConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_FilterConfTypeDef Struct Reference
CAN Exported Types

CAN filter configuration structure definition. More...

#include <stm32l4xx_hal_can.h>

Data Fields

uint32_t | FilterIdHigh
uint32_t | FilterIdLow
uint32_t | FilterMaskIdHigh
uint32_t | FilterMaskIdLow
uint32_t | FilterFIFOAssignment
uint32_t | FilterNumber
uint32_t | FilterMode
uint32_t | FilterScale
uint32_t | FilterActivation
uint32_t | BankNumber

Detailed Description

CAN filter configuration structure definition.

Definition at line 122 of file stm32l4xx_hal_can.h.

Field Documentation

uint32_t CAN_FilterConfTypeDef::BankNumber

Select the start slave bank filter. This parameter must be a number between Min_Data = 0 and Max_Data = 28

Definition at line 157 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterActivation

Enable or disable the filter. This parameter can be set to ENABLE or DISABLE

Definition at line 154 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterFIFOAssignment

Specifies the FIFO (0 or 1) which will be assigned to the filter. This parameter can be a value of CAN Filter FIFO

Definition at line 142 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterIdHigh

Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 124 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterIdLow

Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 128 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMaskIdHigh

Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 132 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMaskIdLow

Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 137 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMode

Specifies the filter mode to be initialized. This parameter can be a value of CAN Filter Mode

Definition at line 148 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterNumber

Specifies the filter which will be initialized. This parameter must be a number between Min_Data = 0 and Max_Data = 27

Definition at line 145 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterScale

Specifies the filter scale. This parameter can be a value of CAN Filter Scale

Definition at line 151 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_can.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CanTxMsgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CanTxMsgTypeDef Struct Reference
CAN Exported Types

CAN Tx message structure definition. More...

#include <stm32l4xx_hal_can.h>

Data Fields

uint32_t | StdId
uint32_t | ExtId
uint32_t | IDE
uint32_t | RTR
uint32_t | DLC
uint8_t | Data [8]

Detailed Description

CAN Tx message structure definition.

Definition at line 165 of file stm32l4xx_hal_can.h.

Field Documentation

uint8_t CanTxMsgTypeDef::Data[8]

Contains the data to be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF

Definition at line 182 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::DLC

Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8

Definition at line 179 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::ExtId

Specifies the extended identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF

Definition at line 170 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::IDE

Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of CAN Identifier Type

Definition at line 173 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::RTR

Specifies the type of frame for the message that will be transmitted. This parameter can be a value of CAN Remote Transmission Request

Definition at line 176 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::StdId

Specifies the standard identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF

Definition at line 167 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_can.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CanRxMsgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CanRxMsgTypeDef Struct Reference
CAN Exported Types

CAN Rx message structure definition. More...

#include <stm32l4xx_hal_can.h>

Data Fields

uint32_t | StdId
uint32_t | ExtId
uint32_t | IDE
uint32_t | RTR
uint32_t | DLC
uint8_t | Data [8]
uint32_t | FMI
uint32_t | FIFONumber

Detailed Description

CAN Rx message structure definition.

Definition at line 190 of file stm32l4xx_hal_can.h.

Field Documentation

uint8_t CanRxMsgTypeDef::Data[8]

Contains the data to be received. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF

Definition at line 207 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::DLC

Specifies the length of the frame that will be received. This parameter must be a number between Min_Data = 0 and Max_Data = 8

Definition at line 204 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::ExtId

Specifies the extended identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF

Definition at line 195 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::FIFONumber

Specifies the receive FIFO number. This parameter can be CAN_FIFO0 or CAN_FIFO1

Definition at line 213 of file stm32l4xx_hal_can.h.

uint32_t CanRxMsgTypeDef::FMI

Specifies the index of the filter the message stored in the mailbox passes through. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF

Definition at line 210 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::IDE

Specifies the type of identifier for the message that will be received. This parameter can be a value of CAN Identifier Type

Definition at line 198 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::RTR

Specifies the type of frame for the received message. This parameter can be a value of CAN Remote Transmission Request

Definition at line 201 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::StdId

Specifies the standard identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF

Definition at line 192 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_can.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_HandleTypeDef Struct Reference
CAN Exported Types

CAN handle Structure definition. More...

#include <stm32l4xx_hal_can.h>

Data Fields

CAN_TypeDef * | Instance
CAN_InitTypeDef Init
CanTxMsgTypeDef * pTxMsg
CanRxMsgTypeDef * pRxMsg
__IO HAL_CAN_StateTypeDef | State
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode

Detailed Description

CAN handle Structure definition.

Definition at line 221 of file stm32l4xx_hal_can.h.

Field Documentation

__IO uint32_t CAN_HandleTypeDef::ErrorCode

CAN Error code

Definition at line 235 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_GetError(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

CAN_InitTypeDef CAN_HandleTypeDef::Init

CAN required parameters

Definition at line 225 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

CAN_TypeDef* CAN_HandleTypeDef::Instance

Register base address

Definition at line 223 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_DeInit(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), and HAL_CAN_WakeUp().

HAL_LockTypeDef CAN_HandleTypeDef::Lock

CAN locking object

Definition at line 233 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

CanRxMsgTypeDef* CAN_HandleTypeDef::pRxMsg

Pointer to reception structure

Definition at line 229 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

CanTxMsgTypeDef* CAN_HandleTypeDef::pTxMsg

Pointer to transmit structure

Definition at line 227 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

__IO HAL_CAN_StateTypeDef CAN_HandleTypeDef::State

CAN communication state

Definition at line 231 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_DeInit(), HAL_CAN_GetState(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), HAL_CAN_Receive_IT(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), and HAL_CAN_WakeUp().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_can.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Error Code

Defines
CAN Error Code
CAN Exported Constants

Defines

#define | HAL_CAN_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_CAN_ERROR_EWG ((uint32_t)0x00000001)
#define | HAL_CAN_ERROR_EPV ((uint32_t)0x00000002)
#define | HAL_CAN_ERROR_BOF ((uint32_t)0x00000004)
#define | HAL_CAN_ERROR_STF ((uint32_t)0x00000008)
#define | HAL_CAN_ERROR_FOR ((uint32_t)0x00000010)
#define | HAL_CAN_ERROR_ACK ((uint32_t)0x00000020)
#define | HAL_CAN_ERROR_BR ((uint32_t)0x00000040)
#define | HAL_CAN_ERROR_BD ((uint32_t)0x00000080)
#define | HAL_CAN_ERROR_CRC ((uint32_t)0x00000100)

Define Documentation

#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020)

Acknowledgment error

Definition at line 257 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080)

LEC dominant

Definition at line 259 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004)

BOF error

Definition at line 254 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040)

Bit recessive

Definition at line 258 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100)

LEC transfer error

Definition at line 260 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002)

EPV error

Definition at line 253 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001)

EWG error

Definition at line 252 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010)

Form error

Definition at line 256 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 251 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008)

Stuff error

Definition at line 255 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN initialization Status

Defines
CAN initialization Status
CAN Exported Constants

Defines

#define | CAN_INITSTATUS_FAILED ((uint32_t)0x00000000)
#define | CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001)

Define Documentation

#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000)

CAN initialization failed

Definition at line 268 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001)

CAN initialization OK

Definition at line 269 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Operating Mode

Defines
CAN Operating Mode
CAN Exported Constants

Defines

#define | CAN_MODE_NORMAL ((uint32_t)0x00000000)
#define | CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)
#define | CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)
#define | CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))

Define Documentation

#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)

Loopback mode

Definition at line 278 of file stm32l4xx_hal_can.h.

#define CAN_MODE_NORMAL ((uint32_t)0x00000000)

Normal mode

Definition at line 277 of file stm32l4xx_hal_can.h.

#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)

Silent mode

Definition at line 279 of file stm32l4xx_hal_can.h.

#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))

Loopback combined with silent mode

Definition at line 280 of file stm32l4xx_hal_can.h.

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STM32L486xx HAL User Manual: CAN Synchronization Jump Width

Defines
CAN Synchronization Jump Width
CAN Exported Constants

Defines

#define | CAN_SJW_1TQ ((uint32_t)0x00000000)
#define | CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)
#define | CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)
#define | CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)

Define Documentation

#define CAN_SJW_1TQ ((uint32_t)0x00000000)

1 time quantum

Definition at line 289 of file stm32l4xx_hal_can.h.

#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)

2 time quantum

Definition at line 290 of file stm32l4xx_hal_can.h.

#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)

3 time quantum

Definition at line 291 of file stm32l4xx_hal_can.h.

#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)

4 time quantum

Definition at line 292 of file stm32l4xx_hal_can.h.

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STM32L486xx HAL User Manual: CAN Time Quantum in Bit Segment 1

Defines
CAN Time Quantum in Bit Segment 1
CAN Exported Constants

Defines

#define | CAN_BS1_1TQ ((uint32_t)0x00000000)
#define | CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)
#define | CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)
#define | CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)
#define | CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)
#define | CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))
#define | CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))
#define | CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))
#define | CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)

Define Documentation

#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))

10 time quantum

Definition at line 309 of file stm32l4xx_hal_can.h.

#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))

11 time quantum

Definition at line 310 of file stm32l4xx_hal_can.h.

#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

12 time quantum

Definition at line 311 of file stm32l4xx_hal_can.h.

#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))

13 time quantum

Definition at line 312 of file stm32l4xx_hal_can.h.

#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))

14 time quantum

Definition at line 313 of file stm32l4xx_hal_can.h.

#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))

15 time quantum

Definition at line 314 of file stm32l4xx_hal_can.h.

#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)

16 time quantum

Definition at line 315 of file stm32l4xx_hal_can.h.

#define CAN_BS1_1TQ ((uint32_t)0x00000000)

1 time quantum

Definition at line 300 of file stm32l4xx_hal_can.h.

#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)

2 time quantum

Definition at line 301 of file stm32l4xx_hal_can.h.

#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)

3 time quantum

Definition at line 302 of file stm32l4xx_hal_can.h.

#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

4 time quantum

Definition at line 303 of file stm32l4xx_hal_can.h.

#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)

5 time quantum

Definition at line 304 of file stm32l4xx_hal_can.h.

#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))

6 time quantum

Definition at line 305 of file stm32l4xx_hal_can.h.

#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))

7 time quantum

Definition at line 306 of file stm32l4xx_hal_can.h.

#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

8 time quantum

Definition at line 307 of file stm32l4xx_hal_can.h.

#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)

9 time quantum

Definition at line 308 of file stm32l4xx_hal_can.h.

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STM32L486xx HAL User Manual: CAN Time Quantum in Bit Segment 2

Defines
CAN Time Quantum in Bit Segment 2
CAN Exported Constants

Defines

#define | CAN_BS2_1TQ ((uint32_t)0x00000000)
#define | CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)
#define | CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)
#define | CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))
#define | CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)
#define | CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))
#define | CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))
#define | CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)

Define Documentation

#define CAN_BS2_1TQ ((uint32_t)0x00000000)

1 time quantum

Definition at line 323 of file stm32l4xx_hal_can.h.

#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)

2 time quantum

Definition at line 324 of file stm32l4xx_hal_can.h.

#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)

3 time quantum

Definition at line 325 of file stm32l4xx_hal_can.h.

#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))

4 time quantum

Definition at line 326 of file stm32l4xx_hal_can.h.

#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)

5 time quantum

Definition at line 327 of file stm32l4xx_hal_can.h.

#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))

6 time quantum

Definition at line 328 of file stm32l4xx_hal_can.h.

#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))

7 time quantum

Definition at line 329 of file stm32l4xx_hal_can.h.

#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)

8 time quantum

Definition at line 330 of file stm32l4xx_hal_can.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Filter Mode

Defines
CAN Filter Mode
CAN Exported Constants

Defines

#define | CAN_FILTERMODE_IDMASK ((uint8_t)0x00)
#define | CAN_FILTERMODE_IDLIST ((uint8_t)0x01)

Define Documentation

#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01)

Identifier list mode

Definition at line 339 of file stm32l4xx_hal_can.h.

#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00)

Identifier mask mode

Definition at line 338 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Filter Scale

Defines
CAN Filter Scale
CAN Exported Constants

Defines

#define | CAN_FILTERSCALE_16BIT ((uint8_t)0x00)
#define | CAN_FILTERSCALE_32BIT ((uint8_t)0x01)

Define Documentation

#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00)

Two 16-bit filters

Definition at line 347 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01)

One 32-bit filter

Definition at line 348 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Filter FIFO

Defines
CAN Filter FIFO
CAN Exported Constants

Defines

#define | CAN_FILTER_FIFO0 ((uint8_t)0x00)
#define | CAN_FILTER_FIFO1 ((uint8_t)0x01)

Define Documentation

#define CAN_FILTER_FIFO0 ((uint8_t)0x00)

Filter FIFO 0 assignment for filter x

Definition at line 356 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define CAN_FILTER_FIFO1 ((uint8_t)0x01)

Filter FIFO 1 assignment for filter x

Definition at line 357 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Identifier Type

Defines
CAN Identifier Type
CAN Exported Constants

Defines

#define | CAN_ID_STD ((uint32_t)0x00000000)
#define | CAN_ID_EXT ((uint32_t)0x00000004)

Define Documentation

#define CAN_ID_EXT ((uint32_t)0x00000004)

Extended Id

Definition at line 366 of file stm32l4xx_hal_can.h.

#define CAN_ID_STD ((uint32_t)0x00000000)

Standard Id

Definition at line 365 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_Receive(), HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Remote Transmission Request

Defines
CAN Remote Transmission Request
CAN Exported Constants

Defines

#define | CAN_RTR_DATA ((uint32_t)0x00000000)
#define | CAN_RTR_REMOTE ((uint32_t)0x00000002)

Define Documentation

#define CAN_RTR_DATA ((uint32_t)0x00000000)

Data frame

Definition at line 374 of file stm32l4xx_hal_can.h.

#define CAN_RTR_REMOTE ((uint32_t)0x00000002)

Remote frame

Definition at line 375 of file stm32l4xx_hal_can.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Receive FIFO Number

Defines
CAN Receive FIFO Number
CAN Exported Constants

Defines

#define | CAN_FIFO0 ((uint8_t)0x00)
#define | CAN_FIFO1 ((uint8_t)0x01)

Define Documentation

#define CAN_FIFO0 ((uint8_t)0x00)

CAN FIFO 0 used to receive

Definition at line 383 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), and HAL_CAN_Receive_IT().

#define CAN_FIFO1 ((uint8_t)0x01)

CAN FIFO 1 used to receive

Definition at line 384 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Flags

Defines
CAN Flags
CAN Exported Constants

Defines

#define | CAN_FLAG_RQCP0 ((uint32_t)0x00000500)
#define | CAN_FLAG_RQCP1 ((uint32_t)0x00000508)
#define | CAN_FLAG_RQCP2 ((uint32_t)0x00000510)
#define | CAN_FLAG_TXOK0 ((uint32_t)0x00000501)
#define | CAN_FLAG_TXOK1 ((uint32_t)0x00000509)
#define | CAN_FLAG_TXOK2 ((uint32_t)0x00000511)
#define | CAN_FLAG_TME0 ((uint32_t)0x0000051A)
#define | CAN_FLAG_TME1 ((uint32_t)0x0000051B)
#define | CAN_FLAG_TME2 ((uint32_t)0x0000051C)
#define | CAN_FLAG_FF0 ((uint32_t)0x00000203)
#define | CAN_FLAG_FOV0 ((uint32_t)0x00000204)
#define | CAN_FLAG_FF1 ((uint32_t)0x00000403)
#define | CAN_FLAG_FOV1 ((uint32_t)0x00000404)
#define | CAN_FLAG_WKU ((uint32_t)0x00000103)
#define | CAN_FLAG_SLAK ((uint32_t)0x00000101)
#define | CAN_FLAG_SLAKI ((uint32_t)0x00000104)
#define | CAN_FLAG_EWG ((uint32_t)0x00000300)
#define | CAN_FLAG_EPV ((uint32_t)0x00000301)
#define | CAN_FLAG_BOF ((uint32_t)0x00000302)

Define Documentation

#define CAN_FLAG_BOF ((uint32_t)0x00000302)

Bus-Off flag

Definition at line 425 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_EPV ((uint32_t)0x00000301)

Error passive flag

Definition at line 424 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_EWG ((uint32_t)0x00000300)

Error warning flag

Definition at line 423 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_FF0 ((uint32_t)0x00000203)

FIFO 0 Full flag

Definition at line 409 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_FF1 ((uint32_t)0x00000403)

FIFO 1 Full flag

Definition at line 412 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_FOV0 ((uint32_t)0x00000204)

FIFO 0 Overrun flag

Definition at line 410 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_FOV1 ((uint32_t)0x00000404)

FIFO 1 Overrun flag

Definition at line 413 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500)

Request MailBox0 flag

Definition at line 398 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508)

Request MailBox1 flag

Definition at line 399 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510)

Request MailBox2 flag

Definition at line 400 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_SLAK ((uint32_t)0x00000101)

Sleep acknowledge flag

Definition at line 417 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_SLAKI ((uint32_t)0x00000104)

Sleep acknowledge flag

Definition at line 418 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_TME0 ((uint32_t)0x0000051A)

Transmit mailbox 0 empty flag

Definition at line 404 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_TME1 ((uint32_t)0x0000051B)

Transmit mailbox 0 empty flag

Definition at line 405 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_TME2 ((uint32_t)0x0000051C)

Transmit mailbox 0 empty flag

Definition at line 406 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501)

Transmission OK MailBox0 flag

Definition at line 401 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509)

Transmission OK MailBox1 flag

Definition at line 402 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511)

Transmission OK MailBox2 flag

Definition at line 403 of file stm32l4xx_hal_can.h.

#define CAN_FLAG_WKU ((uint32_t)0x00000103)

Wake up flag

Definition at line 416 of file stm32l4xx_hal_can.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Interrupts

Defines
CAN Interrupts
CAN Exported Constants

Defines

#define | CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)
#define | CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)
#define | CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)
#define | CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)
#define | CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)
#define | CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)
#define | CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)
#define | CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)
#define | CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)
#define | CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)
#define | CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)
#define | CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)
#define | CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)
#define | CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)

Define Documentation

#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)

Bus-off interrupt

Definition at line 450 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)

Error passive interrupt

Definition at line 449 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)

Error Interrupt

Definition at line 452 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)

Error warning interrupt

Definition at line 448 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)

FIFO 0 full interrupt

Definition at line 437 of file stm32l4xx_hal_can.h.

#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)

FIFO 1 full interrupt

Definition at line 440 of file stm32l4xx_hal_can.h.

#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)

FIFO 0 message pending interrupt

Definition at line 436 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)

FIFO 1 message pending interrupt

Definition at line 439 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)

FIFO 0 overrun interrupt

Definition at line 438 of file stm32l4xx_hal_can.h.

#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)

FIFO 1 overrun interrupt

Definition at line 441 of file stm32l4xx_hal_can.h.

#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)

Last error code interrupt

Definition at line 451 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)

Sleep acknowledge interrupt

Definition at line 445 of file stm32l4xx_hal_can.h.

#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)

Transmit mailbox empty interrupt

Definition at line 433 of file stm32l4xx_hal_can.h.

Referenced by CAN_Transmit_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Transmit_IT().

#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)

Wake-up interrupt

Definition at line 444 of file stm32l4xx_hal_can.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Exported Constants

Modules | Defines
CAN Exported Constants
CAN

Modules

CAN Error Code
CAN initialization Status
CAN Operating Mode
CAN Synchronization Jump Width
CAN Time Quantum in Bit Segment 1
CAN Time Quantum in Bit Segment 2
CAN Filter Mode
CAN Filter Scale
CAN Filter FIFO
CAN Identifier Type
CAN Remote Transmission Request
CAN Receive FIFO Number
CAN Flags
CAN Interrupts

Defines

#define | CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define | CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define | CAN_TXMAILBOX_2 ((uint8_t)0x02)

Define Documentation

#define CAN_TXMAILBOX_0 ((uint8_t)0x00)

Definition at line 459 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_TXMAILBOX_1 ((uint8_t)0x01)

Definition at line 460 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_TXMAILBOX_2 ((uint8_t)0x02)

Definition at line 461 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Exported Macros

Defines
CAN Exported Macros
CAN

Defines

#define | __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
Reset CAN handle state.
#define | __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable the specified CAN interrupt.
#define | __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable the specified CAN interrupt.
#define | __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__)
Return the number of pending received messages.
#define | __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified CAN flag is set or not.
#define | __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified CAN pending flag.
#define | __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified CAN interrupt source is enabled or not.
#define | __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)
Check the transmission status of a CAN Frame.
#define | __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__)
Release the specified receive FIFO.
#define | __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)
Cancel a transmit request.
#define | __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__)
Enable or disable the DBG Freeze for CAN.

Define Documentation

#define __HAL_CAN_CANCEL_TRANSMIT | ( | __HANDLE__,
 |  | __TRANSMITMAILBOX__
 | ) |
Value:
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
 ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))

Cancel a transmit request.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__TRANSMITMAILBOX__,: the number of the mailbox that is used for transmission.
Return values:
None

Definition at line 606 of file stm32l4xx_hal_can.h.

#define __HAL_CAN_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)

Clear the specified CAN pending flag.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • CAN_TSR_RQCP0: Request MailBox0 Flag
  • CAN_TSR_RQCP1: Request MailBox1 Flag
  • CAN_TSR_RQCP2: Request MailBox2 Flag
  • CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
  • CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
  • CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
  • CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
  • CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
  • CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
  • CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
  • CAN_FLAG_FF0: FIFO 0 Full Flag
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
  • CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
  • CAN_FLAG_FF1: FIFO 1 Full Flag
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
  • CAN_FLAG_WKU: Wake up Flag
  • CAN_FLAG_SLAKI: Sleep acknowledge Flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 560 of file stm32l4xx_hal_can.h.

#define __HAL_CAN_DBG_FREEZE | ( | __HANDLE__,
 |  | __NEWSTATE__
 | ) |
Value:
(((__NEWSTATE__) == ENABLE)? \
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))

Enable or disable the DBG Freeze for CAN.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__NEWSTATE__,: new state of the CAN peripheral. This parameter can be: ENABLE (CAN reception/transmission is frozen during debug. Reception FIFO can still be accessed/controlled normally) or DISABLE (CAN is working during debug).
Return values:
None

Definition at line 620 of file stm32l4xx_hal_can.h.

#define __HAL_CAN_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

Disable the specified CAN interrupt.

Parameters:
__HANDLE__,: CAN handle.
__INTERRUPT__,: CAN Interrupt.
Return values:
None

Definition at line 492 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), and CAN_Transmit_IT().

#define __HAL_CAN_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

Enable the specified CAN interrupt.

Parameters:
__HANDLE__,: CAN handle.
__INTERRUPT__,: CAN Interrupt.
Return values:
None

Definition at line 484 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define __HAL_CAN_FIFO_RELEASE | ( | __HANDLE__,
 |  | __FIFONUMBER__
 | ) |
Value:
(((__FIFONUMBER__) == CAN_FIFO0)? \
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))

Release the specified receive FIFO.

Parameters:
__HANDLE__,: CAN handle.
__FIFONUMBER__,: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
Return values:
None

Definition at line 597 of file stm32l4xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

#define __HAL_CAN_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))

Check whether the specified CAN flag is set or not.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • CAN_TSR_RQCP0: Request MailBox0 Flag
  • CAN_TSR_RQCP1: Request MailBox1 Flag
  • CAN_TSR_RQCP2: Request MailBox2 Flag
  • CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
  • CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
  • CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
  • CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
  • CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
  • CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
  • CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
  • CAN_FLAG_FF0: FIFO 0 Full Flag
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
  • CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
  • CAN_FLAG_FF1: FIFO 1 Full Flag
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
  • CAN_FLAG_WKU: Wake up Flag
  • CAN_FLAG_SLAK: Sleep acknowledge Flag
  • CAN_FLAG_SLAKI: Sleep acknowledge Flag
  • CAN_FLAG_EWG: Error Warning Flag
  • CAN_FLAG_EPV: Error Passive Flag
  • CAN_FLAG_BOF: Bus-Off Flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 530 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified CAN interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__INTERRUPT__,: specifies the CAN interrupt source to check. This parameter can be one of the following values:
  • CAN_IT_TME: Transmit mailbox empty interrupt enable
  • CAN_IT_FMP0: FIFO0 message pending interrupt enable
  • CAN_IT_FMP1: FIFO1 message pending interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 576 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_MSG_PENDING | ( | __HANDLE__,
 |  | __FIFONUMBER__
 | ) |
Value:
(((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))

Return the number of pending received messages.

Parameters:
__HANDLE__,: CAN handle.
__FIFONUMBER__,: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
Return values:
The number of pending message.

Definition at line 500 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), and HAL_CAN_Receive().

#define __HAL_CAN_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)

Reset CAN handle state.

Parameters:
__HANDLE__,: CAN handle.
Return values:
None

Definition at line 476 of file stm32l4xx_hal_can.h.

#define __HAL_CAN_TRANSMIT_STATUS | ( | __HANDLE__,
 |  | __TRANSMITMAILBOX__
 | ) |
Value:
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))

Check the transmission status of a CAN Frame.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__TRANSMITMAILBOX__,: the number of the mailbox that is used for transmission.
Return values:
The new status of transmission (TRUE or FALSE).

Definition at line 584 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), and HAL_CAN_Transmit().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Private Macros

Defines
CAN Private Macros
CAN

Defines

#define | IS_CAN_MODE(MODE)
#define | IS_CAN_SJW(SJW)
#define | IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define | IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define | IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
#define | IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
#define | IS_CAN_FILTER_MODE(MODE)
#define | IS_CAN_FILTER_SCALE(SCALE)
#define | IS_CAN_FILTER_FIFO(FIFO)
#define | IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
#define | IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define | IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
#define | IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
#define | IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define | IS_CAN_IDTYPE(IDTYPE)
#define | IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define | IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Define Documentation

#define IS_CAN_BANKNUMBER ( BANKNUMBER ) ((BANKNUMBER) <= 28)

Definition at line 729 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_BS1 ( BS1 ) ((BS1) <= CAN_BS1_16TQ)

Definition at line 712 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_BS2 ( BS2 ) ((BS2) <= CAN_BS2_8TQ)

Definition at line 714 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_DLC ( DLC ) ((DLC) <= ((uint8_t)0x08))

Definition at line 737 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_EXTID ( EXTID ) ((EXTID) <= ((uint32_t)0x1FFFFFFF))

Definition at line 735 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_FIFO ( FIFO ) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Definition at line 744 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Receive(), and HAL_CAN_Receive_IT().

#define IS_CAN_FILTER_FIFO ( FIFO )
Value:
(((FIFO) == CAN_FILTER_FIFO0) || \
                                  ((FIFO) == CAN_FILTER_FIFO1))

Definition at line 726 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_MODE ( MODE )
Value:
(((MODE) == CAN_FILTERMODE_IDMASK) || \
                                  ((MODE) == CAN_FILTERMODE_IDLIST))

Definition at line 720 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_NUMBER ( NUMBER ) ((NUMBER) <= 27)

Definition at line 718 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_SCALE ( SCALE )
Value:
(((SCALE) == CAN_FILTERSCALE_16BIT) || \
                                    ((SCALE) == CAN_FILTERSCALE_32BIT))

Definition at line 723 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_IDTYPE ( IDTYPE )
Value:
(((IDTYPE) == CAN_ID_STD) || \
                                ((IDTYPE) == CAN_ID_EXT))

Definition at line 739 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_MODE ( MODE )
Value:
(((MODE) == CAN_MODE_NORMAL) || \
                           ((MODE) == CAN_MODE_LOOPBACK)|| \
                           ((MODE) == CAN_MODE_SILENT) || \
                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))

Definition at line 704 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))

Definition at line 716 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_RTR ( RTR ) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))

Definition at line 742 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_SJW ( SJW )
Value:
(((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))

Definition at line 709 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_STDID ( STDID ) ((STDID) <= ((uint32_t)0x7FF))

Definition at line 733 of file stm32l4xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_TRANSMITMAILBOX ( TRANSMITMAILBOX ) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))

Definition at line 731 of file stm32l4xx_hal_can.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
COMP Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions to initialize and de-initialize comparators

Function Documentation

HAL_StatusTypeDef HAL_COMP_DeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP peripheral.

Note:
Deinitialization cannot be performed if the COMP configuration is locked. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 402 of file stm32l4xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_MspDeInit(), HAL_COMP_STATE_RESET, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Init ( COMP_HandleTypeDef * hcomp )

Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.

Note:
If the selected comparator is locked, initialization can't be performed. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 222 of file stm32l4xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, COMP_InitTypeDef::BlankingSrce, COMP_DELAY_VOLTAGE_SCALER_STAB_US, COMP_EXTI_EVENT, COMP_EXTI_FALLING, COMP_EXTI_IT, COMP_EXTI_RISING, COMP_GET_EXTI_LINE, COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON, HAL_COMP_MspInit(), HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, COMP_InitTypeDef::Hysteresis, COMP_HandleTypeDef::Init, COMP_HandleTypeDef::Instance, COMP_InitTypeDef::InvertingInput, IS_COMP_BLANKINGSRC_INSTANCE, IS_COMP_HYSTERESIS, IS_COMP_INPUT_MINUS, IS_COMP_INPUT_PLUS, IS_COMP_OUTPUTPOL, IS_COMP_POWERMODE, IS_COMP_TRIGGERMODE, IS_COMP_WINDOWMODE, COMP_HandleTypeDef::Lock, COMP_InitTypeDef::Mode, COMP_InitTypeDef::NonInvertingInput, COMP_InitTypeDef::OutputPol, COMP_HandleTypeDef::State, COMP_InitTypeDef::TriggerMode, and COMP_InitTypeDef::WindowMode.

void HAL_COMP_MspDeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 452 of file stm32l4xx_hal_comp.c.

Referenced by HAL_COMP_DeInit().

void HAL_COMP_MspInit ( COMP_HandleTypeDef * hcomp )

Initialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 437 of file stm32l4xx_hal_comp.c.

Referenced by HAL_COMP_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Start-Stop operation functions

Functions
Start-Stop operation functions
COMP Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.

Detailed Description

Start-Stop operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a comparator instance.
      (+) Stop a comparator instance.

Function Documentation

void HAL_COMP_IRQHandler ( COMP_HandleTypeDef * hcomp )

Comparator IRQ handler.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 570 of file stm32l4xx_hal_comp.c.

References COMP_EXTI_LINE_COMP1, COMP_EXTI_LINE_COMP2, COMP_GET_EXTI_LINE, HAL_COMP_TriggerCallback(), and COMP_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_COMP_Start ( COMP_HandleTypeDef * hcomp )

Start the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 486 of file stm32l4xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_DELAY_STARTUP_US, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Stop ( COMP_HandleTypeDef * hcomp )

Stop the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 533 of file stm32l4xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
COMP Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator callback.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the comparators.

Function Documentation

uint32_t HAL_COMP_GetOutputLevel ( COMP_HandleTypeDef * hcomp )

Return the output level (high or low) of the selected comparator.

The output level depends on the selected polarity. If the polarity is not inverted:

  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus If the polarity is inverted:
  • Comparator output is high when the input plus is at a lower voltage than the input minus
  • Comparator output is low when the input plus is at a higher voltage than the input minus
    Parameters:
    hcomp COMP handle
    Return values:
    Returns the selected comparator output level:
    • COMP_OUTPUT_LEVEL_LOW
    • COMP_OUTPUT_LEVEL_HIGH

Definition at line 673 of file stm32l4xx_hal_comp.c.

References assert_param, COMP_OUTPUT_LEVEL_BITOFFSET_POS, and COMP_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_COMP_Lock ( COMP_HandleTypeDef * hcomp )

Lock the selected comparator configuration.

Note:
A system reset is required to unlock the comparator configuration.
Locking the comparator from reset state is possible if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 627 of file stm32l4xx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, __HAL_COMP_LOCK, assert_param, COMP_STATE_BITFIELD_LOCK, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

void HAL_COMP_TriggerCallback ( COMP_HandleTypeDef * hcomp )

Comparator callback.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 687 of file stm32l4xx_hal_comp.c.

Referenced by HAL_COMP_IRQHandler().

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STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
COMP Exported Functions

Peripheral State functions. More...

Functions

HAL_COMP_StateTypeDef HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral.

Function Documentation

HAL_COMP_StateTypeDef HAL_COMP_GetState ( COMP_HandleTypeDef * hcomp )

Return the COMP handle state.

Parameters:
hcomp COMP handle
Return values:
HAL state

Definition at line 721 of file stm32l4xx_hal_comp.c.

References assert_param, HAL_COMP_STATE_RESET, COMP_HandleTypeDef::Instance, and COMP_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Exported Types

Data Structures | Defines | Enumerations
COMP Exported Types
COMP

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)
HAL COMP state machine: HAL COMP states definition.

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}

Define Documentation

#define COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)

HAL COMP state machine: HAL COMP states definition.

Definition at line 101 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Lock().

Enumeration Type Documentation

enum HAL_COMP_StateTypeDef
Enumerator:
HAL_COMP_STATE_RESET

COMP not yet initialized

HAL_COMP_STATE_RESET_LOCKED

COMP not yet initialized and configuration is locked

HAL_COMP_STATE_READY

COMP initialized and ready for use

HAL_COMP_STATE_READY_LOCKED

COMP initialized but configuration is locked

HAL_COMP_STATE_BUSY

COMP is running

HAL_COMP_STATE_BUSY_LOCKED

COMP is running and configuration is locked

Definition at line 102 of file stm32l4xx_hal_comp.h.

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STM32L486xx HAL User Manual: COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
COMP_InitTypeDef Struct Reference
COMP Exported Types

COMP Init structure definition. More...

#include <stm32l4xx_hal_comp.h>

Data Fields

uint32_t | WindowMode
uint32_t | Mode
uint32_t | NonInvertingInput
uint32_t | InvertingInput
uint32_t | Hysteresis
uint32_t | OutputPol
uint32_t | BlankingSrce
uint32_t | TriggerMode

Detailed Description

COMP Init structure definition.

Definition at line 65 of file stm32l4xx_hal_comp.h.

Field Documentation

uint32_t COMP_InitTypeDef::BlankingSrce

Set comparator blanking source. This parameter can be a value of COMP blanking source

Definition at line 90 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Hysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of COMP hysteresis

Definition at line 84 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::InvertingInput

Set comparator input minus (inverting input). This parameter can be a value of COMP input minus (inverting input)

Definition at line 81 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Mode

Set comparator operating mode to adjust power and speed. Note: For the characteritics of comparator power modes (propagation delay and power consumption), refer to device datasheet. This parameter can be a value of COMP power mode

Definition at line 73 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::NonInvertingInput

Set comparator input plus (non-inverting input). This parameter can be a value of COMP input plus (non-inverting input)

Definition at line 78 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::OutputPol

Set comparator output polarity. This parameter can be a value of COMP output Polarity

Definition at line 87 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::TriggerMode

Set the comparator output triggering External Interrupt Line (EXTI). This parameter can be a value of COMP output to EXTI

Definition at line 93 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::WindowMode

Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP<x> and COMP<x+1>). Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. This parameter can be a value of COMP Window Mode

Definition at line 68 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_comp.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
COMP_HandleTypeDef Struct Reference
COMP Exported Types

COMP Handle Structure definition. More...

#include <stm32l4xx_hal_comp.h>

Data Fields

COMP_TypeDef * | Instance
COMP_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_COMP_StateTypeDef | State

Detailed Description

COMP Handle Structure definition.

Definition at line 115 of file stm32l4xx_hal_comp.h.

Field Documentation

COMP_InitTypeDef COMP_HandleTypeDef::Init

COMP required parameters

Definition at line 118 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

COMP_TypeDef* COMP_HandleTypeDef::Instance

Register base address

Definition at line 117 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_Lock(), HAL_COMP_Start(), and HAL_COMP_Stop().

HAL_LockTypeDef COMP_HandleTypeDef::Lock

Locking object

Definition at line 119 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

__IO HAL_COMP_StateTypeDef COMP_HandleTypeDef::State

COMP communication state

Definition at line 120 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), and HAL_COMP_Stop().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_comp.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Window Mode

Defines
COMP Window Mode
COMP Exported Constants

Defines

#define | COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000)
#define | COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)

Define Documentation

#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)

Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible).

Definition at line 136 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000)

Window mode disable: Comparators instances pair COMP1 and COMP2 are independent

Definition at line 135 of file stm32l4xx_hal_comp.h.

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STM32L486xx HAL User Manual: COMP power mode

Defines
COMP power mode
COMP Exported Constants

Defines

#define | COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000)
#define | COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)
#define | COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE)

Define Documentation

#define COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000)

High Speed

Definition at line 148 of file stm32l4xx_hal_comp.h.

#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)

Medium Speed

Definition at line 149 of file stm32l4xx_hal_comp.h.

#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE)

Ultra-low power mode

Definition at line 150 of file stm32l4xx_hal_comp.h.

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STM32L486xx HAL User Manual: COMP input plus (non-inverting input)

Defines
COMP input plus (non-inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000)
#define | COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)

Define Documentation

#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000)

Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2)

Definition at line 158 of file stm32l4xx_hal_comp.h.

#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)

Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2)

Definition at line 159 of file stm32l4xx_hal_comp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP input minus (inverting input)

Defines
COMP input minus (inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Define Documentation

#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/2 VrefInt

Definition at line 171 of file stm32l4xx_hal_comp.h.

#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/4 VrefInt

Definition at line 170 of file stm32l4xx_hal_comp.h.

#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 3/4 VrefInt

Definition at line 172 of file stm32l4xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 )

Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)

Definition at line 174 of file stm32l4xx_hal_comp.h.

#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)

Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)

Definition at line 175 of file stm32l4xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )

Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2)

Definition at line 176 of file stm32l4xx_hal_comp.h.

#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2)

Definition at line 177 of file stm32l4xx_hal_comp.h.

#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )

Comparator input minus connected to VrefInt

Definition at line 173 of file stm32l4xx_hal_comp.h.

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STM32L486xx HAL User Manual: COMP hysteresis

Defines
COMP hysteresis
COMP Exported Constants

Defines

#define | COMP_HYSTERESIS_NONE ((uint32_t)0x00000000)
#define | COMP_HYSTERESIS_LOW (COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1)
#define | COMP_HYSTERESIS_HIGH (COMP_CSR_HYST)

Define Documentation

#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST)

Hysteresis level high

Definition at line 193 of file stm32l4xx_hal_comp.h.

#define COMP_HYSTERESIS_LOW (COMP_CSR_HYST_0)

Hysteresis level low

Definition at line 191 of file stm32l4xx_hal_comp.h.

#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1)

Hysteresis level medium

Definition at line 192 of file stm32l4xx_hal_comp.h.

#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000)

No hysteresis

Definition at line 190 of file stm32l4xx_hal_comp.h.

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STM32L486xx HAL User Manual: COMP output Polarity

Defines
COMP output Polarity
COMP Exported Constants

Defines

#define | COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

Define Documentation

#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus)

Definition at line 202 of file stm32l4xx_hal_comp.h.

#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000)

COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus)

Definition at line 201 of file stm32l4xx_hal_comp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP blanking source

Defines
COMP blanking source
COMP Exported Constants

Defines

#define | COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000)
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP1 (COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC3_COMP1 (COMP_CSR_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP1 (COMP_CSR_BLANKING_2)
#define | COMP_BLANKINGSRC_TIM3_OC4_COMP2 (COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2)

Define Documentation

#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000)

No blanking source

Definition at line 210 of file stm32l4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2)

Blanking source for COMP2: TIM15 OC1 selected as blanking source for comparator

Definition at line 218 of file stm32l4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5_COMP1 (COMP_CSR_BLANKING_0)

Blanking source for COMP1: TIM1 OC5 selected as blanking source for comparator

Definition at line 212 of file stm32l4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM2_OC3_COMP1 (COMP_CSR_BLANKING_1)

Blanking source for COMP1: TIM2 OC3 selected as blanking source for comparator

Definition at line 213 of file stm32l4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC3_COMP1 (COMP_CSR_BLANKING_2)

Blanking source for COMP1: TIM3 OC3 selected as blanking source for comparator

Definition at line 214 of file stm32l4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM3_OC4_COMP2 (COMP_CSR_BLANKING_0)

Blanking source for COMP2: TIM3 OC4 selected as blanking source for comparator

Definition at line 216 of file stm32l4xx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_1)

Blanking source for COMP2: TIM8 OC5 selected as blanking source for comparator

Definition at line 217 of file stm32l4xx_hal_comp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Output Level

Defines
COMP Output Level
COMP Exported Constants

Defines

#define | COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)
#define | COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)

Define Documentation

#define COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)

Definition at line 235 of file stm32l4xx_hal_comp.h.

#define COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)

Definition at line 232 of file stm32l4xx_hal_comp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP output to EXTI

Defines
COMP output to EXTI
COMP Exported Constants

Defines

#define | COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Define Documentation

#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on falling edge

Definition at line 248 of file stm32l4xx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event only (without interruption), on rising edge

Definition at line 247 of file stm32l4xx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges

Definition at line 249 of file stm32l4xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on falling edge

Definition at line 245 of file stm32l4xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event with interruption, on rising edge

Definition at line 244 of file stm32l4xx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges

Definition at line 246 of file stm32l4xx_hal_comp.h.

#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000)

Comparator output triggering no External Interrupt Line

Definition at line 243 of file stm32l4xx_hal_comp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Handle Management

Defines
COMP Handle Management
COMP Exported Macros

Defines

#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
Reset COMP handle state.
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
Check whether the specified comparator is locked.

Define Documentation

#define __HAL_COMP_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)

Disable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 285 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)

Enable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 278 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_IS_LOCKED ( __HANDLE__ ) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)

Check whether the specified comparator is locked.

Parameters:
__HANDLE__ COMP handle
Return values:
Value 0 if COMP instance is not locked, value 1 if COMP instance is locked

Definition at line 303 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), and HAL_COMP_Stop().

#define __HAL_COMP_LOCK ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)

Lock the specified comparator configuration.

Note:
Using this macro induce HAL COMP handle state machine being no more in line with COMP instance state. To keep HAL COMP handle state machine updated, it is recommended to use function "HAL_COMP_Lock')".
Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 296 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Lock().

#define __HAL_COMP_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)

Reset COMP handle state.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 271 of file stm32l4xx_hal_comp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP external interrupt line management

Defines
COMP external interrupt line management
COMP Exported Macros

Defines

#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI flag.

Define Documentation

#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP1)

Clear the COMP1 EXTI flag.

Return values:
None

Definition at line 395 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in event mode.

Return values:
None

Definition at line 383 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 335 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 365 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 323 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
                                                             } while(0)

Disable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 350 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in event mode.

Return values:
None

Definition at line 377 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 329 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 359 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 317 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
                                                             } while(0)

Enable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 341 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)

Generate a software interrupt on the COMP1 EXTI line.

Return values:
None

Definition at line 371 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GET_FLAG ( ) READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP1)

Check whether the COMP1 EXTI line flag is set.

Return values:
RESET or SET

Definition at line 389 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP2)

Clear the COMP2 EXTI flag.

Return values:
None

Definition at line 479 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line in event mode.

Return values:
None

Definition at line 467 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 419 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line in interrupt mode.

Return values:
None

Definition at line 449 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 407 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
                                                             } while(0)

Disable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 434 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line in event mode.

Return values:
None

Definition at line 461 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 413 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line in interrupt mode.

Return values:
None

Definition at line 443 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 401 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
                                                               __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
                                                             } while(0)

Enable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 425 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)

Generate a software interrupt on the COMP2 EXTI line.

Return values:
None

Definition at line 455 of file stm32l4xx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GET_FLAG ( ) READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP2)

Check whether the COMP2 EXTI line flag is set.

Return values:
RESET or SET

Definition at line 473 of file stm32l4xx_hal_comp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP EXTI Lines

Defines
COMP EXTI Lines
COMP Private Constants

Defines

#define | COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM21)
#define | COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM22)
#define | COMP_EXTI_IT ((uint32_t) 0x01)
#define | COMP_EXTI_EVENT ((uint32_t) 0x02)
#define | COMP_EXTI_RISING ((uint32_t) 0x10)
#define | COMP_EXTI_FALLING ((uint32_t) 0x20)

Define Documentation

#define COMP_EXTI_EVENT ((uint32_t) 0x02)

EXTI line event only (without interruption)

Definition at line 508 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_FALLING ((uint32_t) 0x20)

EXTI line event on falling edge

Definition at line 510 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_IT ((uint32_t) 0x01)

EXTI line event with interruption

Definition at line 507 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM21)

EXTI line 21 connected to COMP1 output

Definition at line 498 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM22)

EXTI line 22 connected to COMP2 output

Definition at line 499 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_RISING ((uint32_t) 0x10)

EXTI line event on rising edge

Definition at line 509 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Private Constants

Modules | Defines
COMP Private Constants
COMP

Modules

COMP EXTI Lines

Defines

#define | COMP_DELAY_STARTUP_US ((uint32_t) 80U)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)
#define | COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t) 30U)

Define Documentation

#define COMP_DELAY_STARTUP_US ((uint32_t) 80U)

Delay for COMP startup time

Definition at line 178 of file stm32l4xx_hal_comp.c.

Referenced by HAL_COMP_Start().

#define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)

Delay for COMP voltage scaler stabilization time

Definition at line 184 of file stm32l4xx_hal_comp.c.

Referenced by HAL_COMP_Init().

#define COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t) 30U)

Definition at line 186 of file stm32l4xx_hal_comp.c.

Referenced by HAL_COMP_GetOutputLevel().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP private macros to get EXTI line associated with comparators

Defines
COMP private macros to get EXTI line associated with comparators
COMP Private Macros

Defines

#define COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.

Define Documentation

#define COMP_GET_EXTI_LINE ( __INSTANCE__ )
Value:
(((__INSTANCE__) == COMP1) ?                 \
                                             COMP_EXTI_LINE_COMP1 : COMP_EXTI_LINE_COMP2)

Get the specified EXTI line for a comparator instance.

Parameters:
__INSTANCE__ specifies the COMP instance.
Return values:
value of COMP EXTI Lines

Definition at line 532 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init(), and HAL_COMP_IRQHandler().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP private macros to check input parameters

Defines
COMP private macros to check input parameters
COMP Private Macros

Defines

#define | IS_COMP_WINDOWMODE(__WINDOWMODE__)
#define | IS_COMP_POWERMODE(__POWERMODE__)
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__SOURCE__)
#define | IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__)
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Define Documentation

#define IS_COMP_BLANKINGSRC_INSTANCE | ( | __INSTANCE__,
 |  | __BLANKINGSRCE__
 | ) |
Value:
((((__INSTANCE__) == COMP1) &&                                     \
    (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)            ||      \
     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
     ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)))        \
    ||                                                                \
    (((__INSTANCE__) == COMP2) &&                                     \
     (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)           ||      \
      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) ||      \
      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) ||      \
      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))

Definition at line 600 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_BLANKINGSRCE ( __SOURCE__ )
Value:
(((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)  || \
                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))

Definition at line 592 of file stm32l4xx_hal_comp.h.

#define IS_COMP_HYSTERESIS ( __HYSTERESIS__ )
Value:
(((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))

Definition at line 584 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))

Definition at line 574 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))

Definition at line 553 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_OUTPUT_LEVEL ( __OUTPUT_LEVEL__ )
Value:
(((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))

Definition at line 621 of file stm32l4xx_hal_comp.h.

#define IS_COMP_OUTPUTPOL ( __POL__ )
Value:
(((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))

Definition at line 589 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_POWERMODE ( __POWERMODE__ )
Value:
(((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
                                             ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )

Definition at line 544 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_TRIGGERMODE ( __MODE__ )
Value:
(((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))

Definition at line 613 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_WINDOWMODE ( __WINDOWMODE__ )
Value:
(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )

Definition at line 541 of file stm32l4xx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU_Region_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MPU_Region_InitTypeDef Struct Reference
MPU Region Initialization Structure Definition

#include <stm32l4xx_hal_cortex.h>

Data Fields

uint8_t | Enable
uint8_t | Number
uint32_t | BaseAddress
uint8_t | Size
uint8_t | SubRegionDisable
uint8_t | TypeExtField
uint8_t | AccessPermission
uint8_t | DisableExec
uint8_t | IsShareable
uint8_t | IsCacheable
uint8_t | IsBufferable

Detailed Description

Definition at line 66 of file stm32l4xx_hal_cortex.h.

Field Documentation

uint8_t MPU_Region_InitTypeDef::AccessPermission

Specifies the region access permission type. This parameter can be a value of CORTEX MPU Region Permission Attributes

Definition at line 79 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint32_t MPU_Region_InitTypeDef::BaseAddress

Specifies the base address of the region to protect.

Definition at line 72 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::DisableExec

Specifies the instruction access status. This parameter can be a value of CORTEX MPU Instruction Access

Definition at line 81 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Enable

Specifies the status of the region. This parameter can be a value of CORTEX MPU Region Enable

Definition at line 68 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsBufferable

Specifies the bufferable status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Bufferable

Definition at line 87 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsCacheable

Specifies the cacheable status of the region protected. This parameter can be a value of CORTEX MPU Instruction Access Cacheable

Definition at line 85 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsShareable

Specifies the shareability status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Shareable

Definition at line 83 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Number

Specifies the number of the region to protect. This parameter can be a value of CORTEX MPU Region Number

Definition at line 70 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Size

Specifies the size of the region to protect. This parameter can be a value of CORTEX MPU Region Size

Definition at line 73 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::SubRegionDisable

Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 75 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::TypeExtField

Specifies the TEX field level. This parameter can be a value of CORTEX MPU TEX Levels

Definition at line 77 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_cortex.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX Preemption Priority Group

Defines
CORTEX Preemption Priority Group
CORTEX Exported Constants

Defines

#define | NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)
#define | NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)
#define | NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)
#define | NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)
#define | NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)

Define Documentation

#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)

0 bit for pre-emption priority, 4 bits for subpriority

Definition at line 108 of file stm32l4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)

1 bit for pre-emption priority, 3 bits for subpriority

Definition at line 110 of file stm32l4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)

2 bits for pre-emption priority, 2 bits for subpriority

Definition at line 112 of file stm32l4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)

3 bits for pre-emption priority, 1 bit for subpriority

Definition at line 114 of file stm32l4xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)

4 bits for pre-emption priority, 0 bit for subpriority

Definition at line 116 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX SysTick clock source

Defines
CORTEX SysTick clock source
CORTEX Exported Constants

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)

Define Documentation

#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)

Definition at line 126 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)

Definition at line 125 of file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX MPU HFNMI and PRIVILEGED Access control

Defines
CORTEX MPU HFNMI and PRIVILEGED Access control
CORTEX Exported Constants

Defines

#define | MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define | MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define | MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)

Define Documentation

#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)

Definition at line 136 of file stm32l4xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)

Definition at line 138 of file stm32l4xx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)

Definition at line 135 of file stm32l4xx_hal_cortex.h.

#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)

Definition at line 137 of file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX MPU Region Enable

Defines
CORTEX MPU Region Enable
CORTEX Exported Constants

Defines

#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)

Define Documentation

#define MPU_REGION_DISABLE ((uint8_t)0x00)

Definition at line 147 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_ENABLE ((uint8_t)0x01)

Definition at line 146 of file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX MPU Instruction Access

Defines
CORTEX MPU Instruction Access
CORTEX Exported Constants

Defines

#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Define Documentation

#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Definition at line 156 of file stm32l4xx_hal_cortex.h.

#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)

Definition at line 155 of file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX MPU Instruction Access Shareable

Defines
CORTEX MPU Instruction Access Shareable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Definition at line 165 of file stm32l4xx_hal_cortex.h.

#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)

Definition at line 164 of file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX MPU Instruction Access Cacheable

Defines
CORTEX MPU Instruction Access Cacheable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)

Definition at line 173 of file stm32l4xx_hal_cortex.h.

#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Definition at line 174 of file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX MPU Instruction Access Bufferable

Defines
CORTEX MPU Instruction Access Bufferable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)

Definition at line 182 of file stm32l4xx_hal_cortex.h.

#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Definition at line 183 of file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX MPU TEX Levels

Defines
CORTEX MPU TEX Levels
CORTEX Exported Constants

Defines

#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)

Define Documentation

#define MPU_TEX_LEVEL0 ((uint8_t)0x00)

Definition at line 191 of file stm32l4xx_hal_cortex.h.

#define MPU_TEX_LEVEL1 ((uint8_t)0x01)

Definition at line 192 of file stm32l4xx_hal_cortex.h.

#define MPU_TEX_LEVEL2 ((uint8_t)0x02)

Definition at line 193 of file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX MPU Region Size

Defines
CORTEX MPU Region Size
CORTEX Exported Constants

Defines

#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Define Documentation

#define MPU_REGION_SIZE_128B ((uint8_t)0x06)

Definition at line 203 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)

Definition at line 213 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)

Definition at line 223 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)

Definition at line 210 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)

Definition at line 220 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)

Definition at line 226 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)

Definition at line 206 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)

Definition at line 216 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_256B ((uint8_t)0x07)

Definition at line 204 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)

Definition at line 214 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)

Definition at line 224 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)

Definition at line 227 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)

Definition at line 207 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)

Definition at line 217 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_32B ((uint8_t)0x04)

Definition at line 201 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)

Definition at line 211 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)

Definition at line 221 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Definition at line 228 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)

Definition at line 208 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)

Definition at line 218 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_512B ((uint8_t)0x08)

Definition at line 205 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)

Definition at line 215 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)

Definition at line 225 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_64B ((uint8_t)0x05)

Definition at line 202 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)

Definition at line 212 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)

Definition at line 222 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)

Definition at line 209 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)

Definition at line 219 of file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX MPU Region Permission Attributes

Defines
CORTEX MPU Region Permission Attributes
CORTEX Exported Constants

Defines

#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Define Documentation

#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)

Definition at line 239 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)

Definition at line 236 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO ((uint8_t)0x05)

Definition at line 240 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Definition at line 241 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW ((uint8_t)0x01)

Definition at line 237 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)

Definition at line 238 of file stm32l4xx_hal_cortex.h.

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STM32L486xx HAL User Manual: CORTEX MPU Region Number

Defines
CORTEX MPU Region Number
CORTEX Exported Constants

Defines

#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)

Define Documentation

#define MPU_REGION_NUMBER0 ((uint8_t)0x00)

Definition at line 249 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_NUMBER1 ((uint8_t)0x01)

Definition at line 250 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_NUMBER2 ((uint8_t)0x02)

Definition at line 251 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_NUMBER3 ((uint8_t)0x03)

Definition at line 252 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_NUMBER4 ((uint8_t)0x04)

Definition at line 253 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_NUMBER5 ((uint8_t)0x05)

Definition at line 254 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_NUMBER6 ((uint8_t)0x06)

Definition at line 255 of file stm32l4xx_hal_cortex.h.

#define MPU_REGION_NUMBER7 ((uint8_t)0x07)

Definition at line 256 of file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX Exported Macros

CORTEX Exported Macros
CORTEX
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
CORTEX Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Set the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.
__STATIC_INLINE void | HAL_MPU_Disable (void)
Disable the MPU.
__STATIC_INLINE void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      SysTick functionalities

Function Documentation

__STATIC_INLINE void HAL_MPU_Disable ( void )

Disable the MPU.

Return values:
None

Definition at line 297 of file stm32l4xx_hal_cortex.h.

__STATIC_INLINE void HAL_MPU_Enable ( uint32_t MPU_Control )

Enable the MPU.

Parameters:
MPU_Control,: Specifies the control mode of the MPU during hard fault, NMI, FAULTMASK and privileged accessto the default memory This parameter can be one of the following values:
  • MPU_HFNMI_PRIVDEF_NONE
  • MPU_HARDFAULT_NMI
  • MPU_PRIVILEGED_DEFAULT
  • MPU_HFNMI_PRIVDEF
Return values:
None

Definition at line 317 of file stm32l4xx_hal_cortex.h.

void HAL_NVIC_DisableIRQ ( IRQn_Type IRQn )

Disable a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
Return values:
None

Definition at line 242 of file stm32l4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_EnableIRQ ( IRQn_Type IRQn )

Enable a device specific interrupt in the NVIC interrupt controller.

Note:
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
Return values:
None

Definition at line 226 of file stm32l4xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_SetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PreemptPriority,
 |  | uint32_t | SubPriority
 | ) |  |

Set the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
PreemptPriority,: The pre-emption priority for the IRQn channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority
SubPriority,: the subpriority level for the IRQ channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority.
Return values:
None

Definition at line 204 of file stm32l4xx_hal_cortex.c.

References assert_param, IS_NVIC_PREEMPTION_PRIORITY, and IS_NVIC_SUB_PRIORITY.

Referenced by HAL_InitTick().

void HAL_NVIC_SetPriorityGrouping ( uint32_t PriorityGroup )

Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.

Parameters:
PriorityGroup,: The priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 1 bit for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 0 bit for subpriority
Note:
When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the subpriority.
Return values:
None

Definition at line 182 of file stm32l4xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by HAL_Init().

void HAL_NVIC_SystemReset ( void )

Initiate a system reset request to reset the MCU.

Return values:
None

Definition at line 255 of file stm32l4xx_hal_cortex.c.

uint32_t HAL_SYSTICK_Config ( uint32_t TicksNumb )

Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.

Parameters:
TicksNumb,: Specifies the ticks Number of ticks between two interrupts.
Return values:
status,: - 0 Function succeeded.
  • 1 Function failed.

Definition at line 268 of file stm32l4xx_hal_cortex.c.

Referenced by HAL_InitTick().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORTEX Exported Functions

Cortex control functions. More...

Functions

uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Get the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Get the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Get active interrupt (read the active register in NVIC and return the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

Cortex control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.

Function Documentation

void HAL_MPU_ConfigRegion ( MPU_Region_InitTypeDef * MPU_Init )

Initialize and configure the Region and the memory to be protected.

Parameters:
MPU_Init,: Pointer to a MPU_Region_InitTypeDef structure that contains the initialization and configuration information.
Return values:
None

Definition at line 435 of file stm32l4xx_hal_cortex.c.

References MPU_Region_InitTypeDef::AccessPermission, assert_param, MPU_Region_InitTypeDef::BaseAddress, MPU_Region_InitTypeDef::DisableExec, MPU_Region_InitTypeDef::Enable, IS_MPU_ACCESS_BUFFERABLE, IS_MPU_ACCESS_CACHEABLE, IS_MPU_ACCESS_SHAREABLE, IS_MPU_INSTRUCTION_ACCESS, IS_MPU_REGION_ENABLE, IS_MPU_REGION_NUMBER, IS_MPU_REGION_PERMISSION_ATTRIBUTE, IS_MPU_REGION_SIZE, IS_MPU_SUB_REGION_DISABLE, IS_MPU_TEX_LEVEL, MPU_Region_InitTypeDef::IsBufferable, MPU_Region_InitTypeDef::IsCacheable, MPU_Region_InitTypeDef::IsShareable, MPU_Region_InitTypeDef::Number, MPU_Region_InitTypeDef::Size, MPU_Region_InitTypeDef::SubRegionDisable, and MPU_Region_InitTypeDef::TypeExtField.

void HAL_NVIC_ClearPendingIRQ ( IRQn_Type IRQn )

Clear the pending bit of an external interrupt.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
Return values:
None

Definition at line 366 of file stm32l4xx_hal_cortex.c.

uint32_t HAL_NVIC_GetActive ( IRQn_Type IRQn )

Get active interrupt (read the active register in NVIC and return the active bit).

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 380 of file stm32l4xx_hal_cortex.c.

uint32_t HAL_NVIC_GetPendingIRQ ( IRQn_Type IRQn )

Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 353 of file stm32l4xx_hal_cortex.c.

void HAL_NVIC_GetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PriorityGroup,
 |  | uint32_t * | pPreemptPriority,
 |  | uint32_t * | pSubPriority
 | ) |  |

Get the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
PriorityGroup,: the priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 1 bit for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 0 bit for subpriority
pPreemptPriority,: Pointer on the Preemptive priority value (starting from 0).
pSubPriority,: Pointer on the Subpriority value (starting from 0).
Return values:
None

Definition at line 323 of file stm32l4xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

uint32_t HAL_NVIC_GetPriorityGrouping ( void )

Get the priority grouping field from the NVIC Interrupt Controller.

Return values:
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)

Definition at line 296 of file stm32l4xx_hal_cortex.c.

void HAL_NVIC_SetPendingIRQ ( IRQn_Type IRQn )

Set Pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
Return values:
None

Definition at line 338 of file stm32l4xx_hal_cortex.c.

void HAL_SYSTICK_Callback ( void )

SYSTICK callback.

Return values:
None

Definition at line 421 of file stm32l4xx_hal_cortex.c.

Referenced by HAL_SYSTICK_IRQHandler().

void HAL_SYSTICK_CLKSourceConfig ( uint32_t CLKSource )

Configure the SysTick clock source.

Parameters:
CLKSource,: specifies the SysTick clock source. This parameter can be one of the following values:
  • SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
  • SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 394 of file stm32l4xx_hal_cortex.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, and SYSTICK_CLKSOURCE_HCLK.

void HAL_SYSTICK_IRQHandler ( void )

Handle SYSTICK interrupt request.

Return values:
None

Definition at line 412 of file stm32l4xx_hal_cortex.c.

References HAL_SYSTICK_Callback().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX Private Macros

Defines
CORTEX Private Macros
CORTEX

Defines

#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)

Define Documentation

#define IS_MPU_ACCESS_BUFFERABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_BUFFERABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

Definition at line 391 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_CACHEABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_CACHEABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

Definition at line 388 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_SHAREABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_SHAREABLE) || \
                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

Definition at line 385 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_INSTRUCTION_ACCESS ( STATE )
Value:
(((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

Definition at line 382 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_ENABLE ( STATE )
Value:
(((STATE) == MPU_REGION_ENABLE) || \
                                     ((STATE) == MPU_REGION_DISABLE))

Definition at line 379 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_NUMBER ( NUMBER )
Value:
(((NUMBER) == MPU_REGION_NUMBER0) || \
                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
                                         ((NUMBER) == MPU_REGION_NUMBER7))

Definition at line 405 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE ( TYPE )
Value:
(((TYPE) == MPU_REGION_NO_ACCESS)   || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))

Definition at line 398 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_SIZE ( SIZE )
Value:
(((SIZE) == MPU_REGION_SIZE_32B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
                                     ((SIZE) == MPU_REGION_SIZE_4GB))

Definition at line 414 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_SUB_REGION_DISABLE ( SUBREGION ) ((SUBREGION) < (uint16_t)0x00FF)

Definition at line 443 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_TEX_LEVEL ( TYPE )
Value:
(((TYPE) == MPU_TEX_LEVEL0)  || \
                                ((TYPE) == MPU_TEX_LEVEL1)  || \
                                ((TYPE) == MPU_TEX_LEVEL2))

Definition at line 394 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_NVIC_DEVICE_IRQ ( IRQ ) ((IRQ) >= 0x00)

Definition at line 373 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_NVIC_DisableIRQ(), and HAL_NVIC_EnableIRQ().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10)

Definition at line 369 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_4))

Definition at line 363 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_NVIC_GetPriority(), and HAL_NVIC_SetPriorityGrouping().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10)

Definition at line 371 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

Definition at line 375 of file stm32l4xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC Private Functions

Functions
CRC Private Functions
CRC

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.

Function Documentation

static uint32_t CRC_Handle_16 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint16_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 16-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer
BufferLength,: input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 508 of file stm32l4xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

static uint32_t CRC_Handle_8 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint8_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 8-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer
BufferLength,: input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 465 of file stm32l4xx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRC according to the specified parameters
          in the CRC_InitTypeDef and create the associated handle
      (+) DeInitialize the CRC peripheral
      (+) Initialize the CRC MSP (MCU Specific Package)
      (+) DeInitialize the CRC MSP

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC peripheral.

Parameters:
hcrc,: CRC handle
Return values:
HAL status

Definition at line 198 of file stm32l4xx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.

Parameters:
hcrc,: CRC handle
Return values:
HAL status

Definition at line 121 of file stm32l4xx_hal_crc.c.

References assert_param, CRC_POLYLENGTH_32B, CRC_InitTypeDef::CRCLength, DEFAULT_CRC32_POLY, DEFAULT_CRC_INITVALUE, DEFAULT_INIT_VALUE_ENABLE, DEFAULT_POLYNOMIAL_ENABLE, CRC_InitTypeDef::DefaultInitValueUse, CRC_InitTypeDef::DefaultPolynomialUse, CRC_InitTypeDef::GeneratingPolynomial, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, HAL_CRCEx_Polynomial_Set(), CRC_HandleTypeDef::Init, CRC_InitTypeDef::InitValue, CRC_HandleTypeDef::InputDataFormat, CRC_InitTypeDef::InputDataInversionMode, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_FORMAT, IS_CRC_INPUTDATA_INVERSION_MODE, IS_CRC_OUTPUTDATA_INVERSION_MODE, IS_DEFAULT_INIT_VALUE, IS_DEFAULT_POLYNOMIAL, CRC_HandleTypeDef::Lock, CRC_InitTypeDef::OutputDataInversionMode, and CRC_HandleTypeDef::State.

void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC MSP.

Parameters:
hcrc,: CRC handle
Return values:
None

Definition at line 257 of file stm32l4xx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initializes the CRC MSP.

Parameters:
hcrc,: CRC handle
Return values:
None

Definition at line 242 of file stm32l4xx_hal_crc.c.

Referenced by HAL_CRC_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CRC Exported Functions

management functions. More...

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Detailed Description

management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          using the combination of the previous CRC value and the new one

       [..]  or

      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          independently of the previous CRC value.

Function Documentation

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength,: input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 306 of file stm32l4xx_hal_crc.c.

References CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Parameters:
hcrc,: CRC handle
pBuffer,: pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength,: input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 366 of file stm32l4xx_hal_crc.c.

References __HAL_CRC_DR_RESET, CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

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STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRC Exported Functions

Peripheral State functions. More...

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Return the CRC handle state.

Parameters:
hcrc,: CRC handle
Return values:
HAL state

Definition at line 439 of file stm32l4xx_hal_crc.c.

References CRC_HandleTypeDef::State.

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STM32L486xx HAL User Manual: CRC Exported Types

Data Structures | Enumerations
CRC Exported Types
CRC

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00, HAL_CRC_STATE_READY = 0x01, HAL_CRC_STATE_BUSY = 0x02, HAL_CRC_STATE_TIMEOUT = 0x03,
HAL_CRC_STATE_ERROR = 0x04
}
CRC HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_CRC_StateTypeDef

CRC HAL State Structure definition.

Enumerator:
HAL_CRC_STATE_RESET

CRC not yet initialized or disabled

HAL_CRC_STATE_READY

CRC initialized and ready for use

HAL_CRC_STATE_BUSY

CRC internal process is ongoing

HAL_CRC_STATE_TIMEOUT

CRC timeout state

HAL_CRC_STATE_ERROR

CRC error state

Definition at line 66 of file stm32l4xx_hal_crc.h.

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STM32L486xx HAL User Manual: CRC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_InitTypeDef Struct Reference
CRC Exported Types

CRC Init Structure definition. More...

#include <stm32l4xx_hal_crc.h>

Data Fields

uint8_t | DefaultPolynomialUse
uint8_t | DefaultInitValueUse
uint32_t | GeneratingPolynomial
uint32_t | CRCLength
uint32_t | InitValue
uint32_t | InputDataInversionMode
uint32_t | OutputDataInversionMode

Detailed Description

CRC Init Structure definition.

Definition at line 80 of file stm32l4xx_hal_crc.h.

Field Documentation

uint32_t CRC_InitTypeDef::CRCLength

This parameter is a value of Polynomial sizes to configure the IP and indicates CRC length. Value can be either one of

  • CRC_POLYLENGTH_32B (32-bit CRC),
  • CRC_POLYLENGTH_16B (16-bit CRC),
  • CRC_POLYLENGTH_8B (8-bit CRC),
  • CRC_POLYLENGTH_7B (7-bit CRC).

Definition at line 98 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultInitValueUse

This parameter is a value of Indicates whether or not default init value is used and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set.

Definition at line 88 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultPolynomialUse

This parameter is a value of Indicates whether or not default polynomial is used and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set.

Definition at line 82 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::GeneratingPolynomial

Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree respectively equal to 7, 8, 16 or 32. This field is written in normal representation, e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.

Definition at line 93 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InitValue

Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse is set to DEFAULT_INIT_VALUE_ENABLE.

Definition at line 105 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InputDataInversionMode

This parameter is a value of Input Data Inversion Modes and specifies input data inversion mode. Can be either one of the following values

  • CRC_INPUTDATA_INVERSION_NONE no input data inversion
  • CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
  • CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
  • CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458

Definition at line 108 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::OutputDataInversionMode

This parameter is a value of Output Data Inversion Modes and specifies output data (i.e. CRC) inversion mode. Can be either

  • CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
  • CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488

Definition at line 115 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_crc.h
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STM32L486xx HAL User Manual: CRC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_HandleTypeDef Struct Reference
CRC Exported Types

CRC Handle Structure definition. More...

#include <stm32l4xx_hal_crc.h>

Data Fields

CRC_TypeDef * | Instance
CRC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_CRC_StateTypeDef | State
uint32_t | InputDataFormat

Detailed Description

CRC Handle Structure definition.

Definition at line 126 of file stm32l4xx_hal_crc.h.

Field Documentation

CRC_InitTypeDef CRC_HandleTypeDef::Init

CRC configuration parameters

Definition at line 130 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_HandleTypeDef::InputDataFormat

This parameter is a value of Input Buffer Format and specifies input data format. Can be either

  • CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
  • CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
  • CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)

Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error must occur if InputBufferFormat is not one of the three values listed above

Definition at line 136 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), and HAL_CRC_Init().

CRC_TypeDef* CRC_HandleTypeDef::Instance

Register base address

Definition at line 128 of file stm32l4xx_hal_crc.h.

Referenced by CRC_Handle_16(), CRC_Handle_8(), HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), and HAL_CRCEx_Polynomial_Set().

HAL_LockTypeDef CRC_HandleTypeDef::Lock

CRC Locking object

Definition at line 132 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

__IO HAL_CRC_StateTypeDef CRC_HandleTypeDef::State

CRC communication state

Definition at line 134 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_GetState(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), and HAL_CRCEx_Output_Data_Reverse().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_crc.h
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STM32L486xx HAL User Manual: Default CRC generating polynomial

Defines
Default CRC generating polynomial
CRC Exported Constants

Defines

#define DEFAULT_CRC32_POLY 0x04C11DB7

Define Documentation

#define DEFAULT_CRC32_POLY 0x04C11DB7

X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1

Definition at line 159 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32L486xx HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF

Define Documentation

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF

Initial CRC default value

Definition at line 167 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32L486xx HAL User Manual: Indicates whether or not default polynomial is used

Defines
Indicates whether or not default polynomial is used
CRC Exported Constants

Defines

#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)

Define Documentation

#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)

Disable default generating polynomial 0x04C11DB7

Definition at line 176 of file stm32l4xx_hal_crc.h.

#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)

Enable default generating polynomial 0x04C11DB7

Definition at line 175 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32L486xx HAL User Manual: Indicates whether or not default init value is used

Defines
Indicates whether or not default init value is used
CRC Exported Constants

Defines

#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)

Define Documentation

#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)

Disable initial CRC default value

Definition at line 185 of file stm32l4xx_hal_crc.h.

#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)

Enable initial CRC default value

Definition at line 184 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32L486xx HAL User Manual: Polynomial sizes to configure the IP

Defines
Polynomial sizes to configure the IP
CRC Exported Constants

Defines

#define | CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
#define | CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define | CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define | CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)

Define Documentation

#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)

Resort to a 16-bit long generating polynomial

Definition at line 194 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)

Resort to a 32-bit long generating polynomial

Definition at line 193 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)

Resort to a 7-bit long generating polynomial

Definition at line 196 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)

Resort to a 8-bit long generating polynomial

Definition at line 195 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32L486xx HAL User Manual: CRC polynomial possible sizes actual definitions

Defines
CRC polynomial possible sizes actual definitions
CRC Exported Constants

Defines

#define | HAL_CRC_LENGTH_32B 32
#define | HAL_CRC_LENGTH_16B 16
#define | HAL_CRC_LENGTH_8B 8
#define | HAL_CRC_LENGTH_7B 7

Define Documentation

#define HAL_CRC_LENGTH_16B 16

16-bit long CRC

Definition at line 205 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_32B 32

32-bit long CRC

Definition at line 204 of file stm32l4xx_hal_crc.h.

#define HAL_CRC_LENGTH_7B 7

7-bit long CRC

Definition at line 207 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_8B 8

8-bit long CRC

Definition at line 206 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32L486xx HAL User Manual: Input Buffer Format

Defines
Input Buffer Format
CRC Exported Constants

Defines

#define | CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
#define | CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
#define | CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
#define | CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)

Define Documentation

#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)

Input data in byte format

Definition at line 220 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)

Input data in half-word format

Definition at line 221 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)

Undefined input data format

Definition at line 219 of file stm32l4xx_hal_crc.h.

#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)

Input data in word format

Definition at line 222 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

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STM32L486xx HAL User Manual: CRC API aliases

Defines
CRC API aliases
CRC Exported Constants

Defines

#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Define Documentation

#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse

Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility

Definition at line 230 of file stm32l4xx_hal_crc.h.

#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility

Definition at line 231 of file stm32l4xx_hal_crc.h.

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STM32L486xx HAL User Manual: CRC Exported Macros

Defines
CRC Exported Macros
CRC

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store a 8-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the 8-bit data stored in the Independent Data(ID) register.

Define Documentation

#define __HAL_CRC_DR_RESET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)

Reset CRC Data Register.

Parameters:
__HANDLE__,: CRC handle
Return values:
None

Definition at line 257 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Calculate(), and HAL_CRC_DeInit().

#define __HAL_CRC_GET_IDR ( __HANDLE__ ) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

Return the 8-bit data stored in the Independent Data(ID) register.

Parameters:
__HANDLE__,: CRC handle
Return values:
8-bit value of the ID register

Definition at line 280 of file stm32l4xx_hal_crc.h.

#define __HAL_CRC_INITIALCRCVALUE_CONFIG | ( | __HANDLE__,
 |  | __INIT__
 | ) | ((__HANDLE__)->Instance->INIT = (__INIT__))

Set CRC INIT non-default value.

Parameters:
__HANDLE__,: CRC handle
__INIT__,: 32-bit initial value
Return values:
None

Definition at line 265 of file stm32l4xx_hal_crc.h.

#define __HAL_CRC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

Reset CRC handle state.

Parameters:
__HANDLE__,: CRC handle.
Return values:
None

Definition at line 250 of file stm32l4xx_hal_crc.h.

#define __HAL_CRC_SET_IDR | ( | __HANDLE__,
 |  | __VALUE__
 | ) | (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))

Store a 8-bit data in the Independent Data(ID) register.

Parameters:
__HANDLE__,: CRC handle
__VALUE__,: 8-bit value to be stored in the ID register
Return values:
None

Definition at line 273 of file stm32l4xx_hal_crc.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC Private Macros

Defines
CRC Private Macros
CRC

Defines

#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Define Documentation

#define IS_CRC_INPUTDATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))

Definition at line 303 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_CRC_POL_LENGTH ( LENGTH )
Value:
(((LENGTH) == CRC_POLYLENGTH_32B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
                                       ((LENGTH) == CRC_POLYLENGTH_7B))

Definition at line 298 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define IS_DEFAULT_INIT_VALUE ( VALUE )
Value:
(((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))

Definition at line 295 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_DEFAULT_POLYNOMIAL ( DEFAULT )
Value:
(((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))

Definition at line 291 of file stm32l4xx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32L486xx HAL User Manual: Extended Initialization/de-initialization functions

Functions
Extended Initialization/de-initialization functions
CRC Extended Exported Functions

Extended Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended Initialization and Configuration functions.

 ===============================================================================
            ##### Extended configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the generating polynomial
      (+) Configure the input data inversion
      (+) Configure the output data inversion

Function Documentation

HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | InputReverseMode
 | ) |  |

Set the Reverse Input data mode.

Parameters:
hcrc,: CRC handle
InputReverseMode,: Input Data inversion mode. This parameter can be one of the following values:
  • CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
  • CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
  • CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
  • CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
Return values:
HAL status

Definition at line 171 of file stm32l4xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | OutputReverseMode
 | ) |  |

Set the Reverse Output data mode.

Parameters:
hcrc,: CRC handle
OutputReverseMode,: Output Data inversion mode. This parameter can be one of the following values:
  • CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
  • CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
Return values:
HAL status

Definition at line 197 of file stm32l4xx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_OUTPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | Pol,
 |  | uint32_t | PolyLength
 | ) |  |

Initialize the CRC polynomial if different from default one.

Parameters:
hcrc,: CRC handle
Pol,: CRC generating polynomial (7, 8, 16 or 32-bit long). This parameter is written in normal representation, e.g.
  • for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
  • for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
PolyLength,: CRC polynomial length. This parameter can be one of the following values:
  • CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
  • CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
  • CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
  • CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
Return values:
HAL status

Definition at line 107 of file stm32l4xx_hal_crc_ex.c.

References assert_param, CRC_POLYLENGTH_16B, CRC_POLYLENGTH_32B, CRC_POLYLENGTH_7B, CRC_POLYLENGTH_8B, HAL_CRC_LENGTH_16B, HAL_CRC_LENGTH_7B, HAL_CRC_LENGTH_8B, CRC_HandleTypeDef::Instance, and IS_CRC_POL_LENGTH.

Referenced by HAL_CRC_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input Data Inversion Modes

Defines
Input Data Inversion Modes
CRCEx Exported Constants

Defines

#define | CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
#define | CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define | CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define | CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)

Define Documentation

#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)

Byte-wise input data inversion

Definition at line 67 of file stm32l4xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)

HalfWord-wise input data inversion

Definition at line 68 of file stm32l4xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)

No input data inversion

Definition at line 66 of file stm32l4xx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)

Word-wise input data inversion

Definition at line 69 of file stm32l4xx_hal_crc_ex.h.

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STM32L486xx HAL User Manual: Output Data Inversion Modes

Defines
Output Data Inversion Modes
CRCEx Exported Constants

Defines

#define | CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)
#define | CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)

Define Documentation

#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)

No output data inversion

Definition at line 77 of file stm32l4xx_hal_crc_ex.h.

#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)

Bit-wise output data inversion

Definition at line 78 of file stm32l4xx_hal_crc_ex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRCEx Exported Macros

Defines
CRCEx Exported Macros
CRCEx

Defines

#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.

Define Documentation

#define __HAL_CRC_OUTPUTREVERSAL_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))

Unset CRC output reversal.

Parameters:
__HANDLE__,: CRC handle
Return values:
None

Definition at line 104 of file stm32l4xx_hal_crc_ex.h.

#define __HAL_CRC_OUTPUTREVERSAL_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)

Set CRC output reversal.

Parameters:
__HANDLE__,: CRC handle
Return values:
None

Definition at line 97 of file stm32l4xx_hal_crc_ex.h.

#define __HAL_CRC_POLYNOMIAL_CONFIG | ( | __HANDLE__,
 |  | __POLYNOMIAL__
 | ) | ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

Set CRC non-default polynomial.

Parameters:
__HANDLE__,: CRC handle
__POLYNOMIAL__,: 7, 8, 16 or 32-bit polynomial
Return values:
None

Definition at line 112 of file stm32l4xx_hal_crc_ex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRCEx Private Macros

Defines
CRCEx Private Macros
CRCEx

Defines

#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Define Documentation

#define IS_CRC_INPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))

Definition at line 123 of file stm32l4xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Input_Data_Reverse().

#define IS_CRC_OUTPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))

Definition at line 129 of file stm32l4xx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Output_Data_Reverse().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYP Private Functions

Functions
CRYP Private Functions
CRYP

Functions

static HAL_StatusTypeDef | CRYP_SetInitVector (CRYP_HandleTypeDef *hcryp)
Write the InitVector/InitCounter in IVRx registers.
static HAL_StatusTypeDef | CRYP_SetKey (CRYP_HandleTypeDef *hcryp)
Write the Key in KeyRx registers.
static HAL_StatusTypeDef | CRYP_AES_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.

Function Documentation

static HAL_StatusTypeDef CRYP_AES_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Handle CRYP block input/output data handling under interruption.

Note:
The function is called under interruption only, once interruptions have been enabled by HAL_CRYPEx_AES_IT().
Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL status

Definition at line 1298 of file stm32l4xx_hal_cryp.c.

References __HAL_CRYP_DISABLE_IT, CRYP_ALGOMODE_KEYDERIVATION, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_KEYSIZE_256B, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_SUSPENDED, HAL_CRYP_SUSPEND, HAL_CRYP_SUSPEND_NONE, HAL_CRYPEx_ComputationCpltCallback(), CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_InitTypeDef::KeySize, CRYP_InitTypeDef::OperatingMode, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::State, and CRYP_HandleTypeDef::SuspendRequest.

Referenced by HAL_CRYP_IRQHandler().

static HAL_StatusTypeDef CRYP_SetInitVector ( CRYP_HandleTypeDef * hcryp ) [static]

Write the InitVector/InitCounter in IVRx registers.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 1257 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_CHAINMODE_AES_CMAC, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, and CRYP_InitTypeDef::pInitVect.

Referenced by HAL_CRYP_Init().

static HAL_StatusTypeDef CRYP_SetKey ( CRYP_HandleTypeDef * hcryp ) [static]

Write the Key in KeyRx registers.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 1216 of file stm32l4xx_hal_cryp.c.

References CRYP_KEYSIZE_256B, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_InitTypeDef::KeySize, and CRYP_InitTypeDef::pKey.

Referenced by HAL_CRYP_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and deinitialization functions

Functions
Initialization and deinitialization functions
CRYP Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initialize the CRYP according to the specified parameters in the CRYP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
DeInitialize the CRYP peripheral.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initialize the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitialize CRYP MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and deinitialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRYP according to the specified parameters
          in the CRYP_InitTypeDef and creates the associated handle
      (+) DeInitialize the CRYP peripheral
      (+) Initialize the CRYP MSP (MCU Specific Package)
      (+) De-Initialize the CRYP MSP

    [..]
    (@) Specific care must be taken to format the key and the Initialization Vector IV!

   [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
        b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
        (+) as a sequence of words where the MSB word comes first (occupies the
          lowest memory address)
        (+) where each word is byte-swapped:
         (++)   address n+0 : 0b b103 .. b96 b111 .. b104 b119 .. b112 b127 .. b120
         (++)   address n+4 : 0b b71 .. b64 b79 .. b72 b87 .. b80 b95 .. b88
         (++)   address n+8 : 0b b39 .. b32 b47 .. b40 b55 .. b48 b63 .. b56
         (++)   address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24
    [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
        The 4 32-bit words that make the key must be stored as follows in MCU memory:
         (+)    address n+0 : 0x B12 B13 B14 B15
         (+)    address n+4 : 0x B8 B9 B10 B11
         (+)    address n+8 : 0x B4 B5 B6 B7
         (+)    address n+C : 0x B0 B1 B2 B3
    [..]  which leads to the expected setting
      (+)       AES_KEYR3 = 0x B15 B14 B13 B12
      (+)       AES_KEYR2 = 0x B11 B10 B9 B8
      (+)       AES_KEYR1 = 0x B7 B6 B5 B4
      (+)       AES_KEYR0 = 0x B3 B2 B1 B0

   [..]  Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
         The 8 32-bit words that make the key must be stored as follows in MCU memory:
         (+)    address n+00 : 0x B28 B29 B30 B31
         (+)    address n+04 : 0x B24 B25 B26 B27
         (+)    address n+08 : 0x B20 B21 B22 B23
         (+)    address n+0C : 0x B16 B17 B18 B19
         (+)    address n+10 : 0x B12 B13 B14 B15
         (+)    address n+14 : 0x B8 B9 B10 B11
         (+)    address n+18 : 0x B4 B5 B6 B7
         (+)    address n+1C : 0x B0 B1 B2 B3
    [..]  which leads to the expected setting
      (+)       AES_KEYR7 = 0x B31 B30 B29 B28
      (+)       AES_KEYR6 = 0x B27 B26 B25 B24
      (+)       AES_KEYR5 = 0x B23 B22 B21 B20
      (+)       AES_KEYR4 = 0x B19 B18 B17 B16
      (+)       AES_KEYR3 = 0x B15 B14 B13 B12
      (+)       AES_KEYR2 = 0x B11 B10 B9 B8
      (+)       AES_KEYR1 = 0x B7 B6 B5 B4
      (+)       AES_KEYR0 = 0x B3 B2 B1 B0

   [..] Initialization Vector IV (4 32-bit words) format must follow the same as
        that of a 128-bit long key.

  [..]

Function Documentation

HAL_StatusTypeDef HAL_CRYP_DeInit ( CRYP_HandleTypeDef * hcryp )

DeInitialize the CRYP peripheral.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 363 of file stm32l4xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_MspDeInit(), HAL_CRYP_PHASE_READY, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_RESET, CRYP_HandleTypeDef::Phase, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_AESCBC_Decrypt(), HAL_CRYP_AESCBC_Decrypt_DMA(), HAL_CRYP_AESCBC_Decrypt_IT(), HAL_CRYP_AESCBC_Encrypt(), HAL_CRYP_AESCBC_Encrypt_DMA(), HAL_CRYP_AESCBC_Encrypt_IT(), HAL_CRYP_AESCTR_Decrypt(), HAL_CRYP_AESCTR_Decrypt_DMA(), HAL_CRYP_AESCTR_Decrypt_IT(), HAL_CRYP_AESCTR_Encrypt(), HAL_CRYP_AESCTR_Encrypt_DMA(), HAL_CRYP_AESCTR_Encrypt_IT(), HAL_CRYP_AESECB_Decrypt(), HAL_CRYP_AESECB_Decrypt_DMA(), HAL_CRYP_AESECB_Decrypt_IT(), HAL_CRYP_AESECB_Encrypt(), HAL_CRYP_AESECB_Encrypt_DMA(), and HAL_CRYP_AESECB_Encrypt_IT().

HAL_StatusTypeDef HAL_CRYP_Init ( CRYP_HandleTypeDef * hcryp )

Initialize the CRYP according to the specified parameters in the CRYP_InitTypeDef and initialize the associated handle.

Note:
Specific care must be taken to format the key and the Initialization Vector IV stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations hereabove.
Return values:
HAL status

Definition at line 207 of file stm32l4xx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, assert_param, CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_KEYDERIVATION, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, CRYP_CHAINMODE_AES_CMAC, CRYP_CHAINMODE_AES_CTR, CRYP_CHAINMODE_AES_ECB, CRYP_CHAINMODE_AES_GCM_GMAC, CRYP_KEY_WRITE_ENABLE, CRYP_SetInitVector(), CRYP_SetKey(), CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_InitTypeDef::DataType, CRYP_HandleTypeDef::ErrorCode, CRYP_InitTypeDef::GCMCMACPhase, HAL_CRYP_ERROR_NONE, HAL_CRYP_MspInit(), HAL_CRYP_PHASE_NOT_USED, HAL_CRYP_PHASE_START, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, HAL_CRYP_SUSPEND_NONE, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, IS_CRYP_ALGOMODE, IS_CRYP_CHAINMODE, IS_CRYP_DATATYPE, IS_CRYP_KEYSIZE, IS_CRYP_WRITE, CRYP_InitTypeDef::KeySize, CRYP_InitTypeDef::KeyWriteFlag, CRYP_HandleTypeDef::Lock, CRYP_InitTypeDef::OperatingMode, CRYP_HandleTypeDef::Phase, CRYP_HandleTypeDef::State, and CRYP_HandleTypeDef::SuspendRequest.

Referenced by HAL_CRYP_AESCBC_Decrypt(), HAL_CRYP_AESCBC_Decrypt_DMA(), HAL_CRYP_AESCBC_Decrypt_IT(), HAL_CRYP_AESCBC_Encrypt(), HAL_CRYP_AESCBC_Encrypt_DMA(), HAL_CRYP_AESCBC_Encrypt_IT(), HAL_CRYP_AESCTR_Decrypt(), HAL_CRYP_AESCTR_Decrypt_DMA(), HAL_CRYP_AESCTR_Decrypt_IT(), HAL_CRYP_AESCTR_Encrypt(), HAL_CRYP_AESCTR_Encrypt_DMA(), HAL_CRYP_AESCTR_Encrypt_IT(), HAL_CRYP_AESECB_Decrypt(), HAL_CRYP_AESECB_Decrypt_DMA(), HAL_CRYP_AESECB_Decrypt_IT(), HAL_CRYP_AESECB_Encrypt(), HAL_CRYP_AESECB_Encrypt_DMA(), and HAL_CRYP_AESECB_Encrypt_IT().

void HAL_CRYP_MspDeInit ( CRYP_HandleTypeDef * hcryp )

DeInitialize CRYP MSP.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 419 of file stm32l4xx_hal_cryp.c.

Referenced by HAL_CRYP_DeInit().

void HAL_CRYP_MspInit ( CRYP_HandleTypeDef * hcryp )

Initialize the CRYP MSP.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 403 of file stm32l4xx_hal_cryp.c.

Referenced by HAL_CRYP_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES processing functions

Functions
AES processing functions
CRYP Exported Functions

Processing functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_AESECB_Encrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
Encrypt pPlainData in AES ECB encryption mode.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Encrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
Encrypt pPlainData in AES CBC encryption mode with key derivation.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Encrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
Encrypt pPlainData in AES CTR encryption mode.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Decrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
Decrypt pCypherData in AES ECB decryption mode with key derivation, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Decrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
Decrypt pCypherData in AES ECB decryption mode with key derivation, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Decrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
Decrypt pCypherData in AES CTR decryption mode, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES ECB encryption mode using Interrupt, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CBC encryption mode using Interrupt, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CTR encryption mode using Interrupt, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES ECB decryption mode using Interrupt, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CBC decryption mode using Interrupt, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CTR decryption mode using Interrupt, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES ECB encryption mode using DMA, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CBC encryption mode using DMA, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CTR encryption mode using DMA, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES ECB decryption mode using DMA, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CBC decryption mode using DMA, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CTR decryption mode using DMA, the decyphered data are available in pPlainData.

Detailed Description

Processing functions.

  ==============================================================================
                      ##### AES processing functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Encrypt plaintext using AES algorithm in different chaining modes
      (+) Decrypt cyphertext using AES algorithm in different chaining modes
    [..]  Three processing functions are available:
      (+) Polling mode
      (+) Interrupt mode
      (+) DMA mode

Function Documentation

HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pCypherData,
 |  | uint16_t | Size,
 |  | uint8_t * | pPlainData,
 |  | uint32_t | Timeout
 | ) |  |

Decrypt pCypherData in AES ECB decryption mode with key derivation, the decyphered data are available in pPlainData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pCypherData,: Pointer to the cyphertext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pPlainData,: Pointer to the plaintext buffer
Timeout,: Specify Timeout value
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
Return values:
HAL status

Definition at line 589 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, CRYP_CHAINMODE_AES_CBC, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pCypherData,
 |  | uint16_t | Size,
 |  | uint8_t * | pPlainData
 | ) |  |

Decrypt pCypherData in AES CBC decryption mode using DMA, the decyphered data are available in pPlainData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pCypherData,: Pointer to the cyphertext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pPlainData,: Pointer to the plaintext buffer
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
Return values:
HAL status

Definition at line 958 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, CRYP_CHAINMODE_AES_CBC, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_DMA(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pCypherData,
 |  | uint16_t | Size,
 |  | uint8_t * | pPlainData
 | ) |  |

Decrypt pCypherData in AES CBC decryption mode using Interrupt, the decyphered data are available in pPlainData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pCypherData,: Pointer to the cyphertext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pPlainData,: Pointer to the plaintext buffer
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
Return values:
HAL status

Definition at line 771 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, CRYP_CHAINMODE_AES_CBC, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_IT(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pPlainData,
 |  | uint16_t | Size,
 |  | uint8_t * | pCypherData,
 |  | uint32_t | Timeout
 | ) |  |

Encrypt pPlainData in AES CBC encryption mode with key derivation.

The cypher data are available in pCypherData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pPlainData,: Pointer to the plaintext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pCypherData,: Pointer to the cyphertext buffer
Timeout,: Specify Timeout value
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
Return values:
HAL status

Definition at line 496 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CHAINMODE_AES_CBC, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pPlainData,
 |  | uint16_t | Size,
 |  | uint8_t * | pCypherData
 | ) |  |

Encrypt pPlainData in AES CBC encryption mode using DMA, the cypher data are available in pCypherData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pPlainData,: Pointer to the plaintext buffer
Size,: Length of the plaintext buffer, must be a multiple of 16.
pCypherData,: Pointer to the cyphertext buffer
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
Return values:
HAL status

Definition at line 865 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CHAINMODE_AES_CBC, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_DMA(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pPlainData,
 |  | uint16_t | Size,
 |  | uint8_t * | pCypherData
 | ) |  |

Encrypt pPlainData in AES CBC encryption mode using Interrupt, the cypher data are available in pCypherData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pPlainData,: Pointer to the plaintext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pCypherData,: Pointer to the cyphertext buffer
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
Return values:
HAL status

Definition at line 680 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CHAINMODE_AES_CBC, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_IT(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pCypherData,
 |  | uint16_t | Size,
 |  | uint8_t * | pPlainData,
 |  | uint32_t | Timeout
 | ) |  |

Decrypt pCypherData in AES CTR decryption mode, the decyphered data are available in pPlainData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pCypherData,: Pointer to the cyphertext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pPlainData,: Pointer to the plaintext buffer
Timeout,: Specify Timeout value
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
Return values:
HAL status

Definition at line 620 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_DECRYPT, CRYP_CHAINMODE_AES_CTR, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pCypherData,
 |  | uint16_t | Size,
 |  | uint8_t * | pPlainData
 | ) |  |

Decrypt pCypherData in AES CTR decryption mode using DMA, the decyphered data are available in pPlainData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pCypherData,: Pointer to the cyphertext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pPlainData,: Pointer to the plaintext buffer
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
Return values:
HAL status

Definition at line 989 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_DECRYPT, CRYP_CHAINMODE_AES_CTR, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_DMA(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pCypherData,
 |  | uint16_t | Size,
 |  | uint8_t * | pPlainData
 | ) |  |

Decrypt pCypherData in AES CTR decryption mode using Interrupt, the decyphered data are available in pPlainData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pCypherData,: Pointer to the cyphertext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pPlainData,: Pointer to the plaintext buffer
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
Return values:
HAL status

Definition at line 801 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_DECRYPT, CRYP_CHAINMODE_AES_CTR, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_IT(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pPlainData,
 |  | uint16_t | Size,
 |  | uint8_t * | pCypherData,
 |  | uint32_t | Timeout
 | ) |  |

Encrypt pPlainData in AES CTR encryption mode.

The cypher data are available in pCypherData

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pPlainData,: Pointer to the plaintext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pCypherData,: Pointer to the cyphertext buffer
Timeout,: Specify Timeout value
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
Return values:
HAL status

Definition at line 527 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CHAINMODE_AES_CTR, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pPlainData,
 |  | uint16_t | Size,
 |  | uint8_t * | pCypherData
 | ) |  |

Encrypt pPlainData in AES CTR encryption mode using DMA, the cypher data are available in pCypherData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pPlainData,: Pointer to the plaintext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pCypherData,: Pointer to the cyphertext buffer.
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
Return values:
HAL status

Definition at line 896 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CHAINMODE_AES_CTR, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_DMA(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pPlainData,
 |  | uint16_t | Size,
 |  | uint8_t * | pCypherData
 | ) |  |

Encrypt pPlainData in AES CTR encryption mode using Interrupt, the cypher data are available in pCypherData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pPlainData,: Pointer to the plaintext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pCypherData,: Pointer to the cyphertext buffer
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
Return values:
HAL status

Definition at line 711 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CHAINMODE_AES_CTR, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_IT(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pCypherData,
 |  | uint16_t | Size,
 |  | uint8_t * | pPlainData,
 |  | uint32_t | Timeout
 | ) |  |

Decrypt pCypherData in AES ECB decryption mode with key derivation, the decyphered data are available in pPlainData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pCypherData,: Pointer to the cyphertext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pPlainData,: Pointer to the plaintext buffer
Timeout,: Specify Timeout value
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
Return values:
HAL status

Definition at line 558 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, CRYP_CHAINMODE_AES_ECB, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pCypherData,
 |  | uint16_t | Size,
 |  | uint8_t * | pPlainData
 | ) |  |

Decrypt pCypherData in AES ECB decryption mode using DMA, the decyphered data are available in pPlainData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pCypherData,: Pointer to the cyphertext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pPlainData,: Pointer to the plaintext buffer
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
Return values:
HAL status

Definition at line 927 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, CRYP_CHAINMODE_AES_ECB, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_DMA(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pCypherData,
 |  | uint16_t | Size,
 |  | uint8_t * | pPlainData
 | ) |  |

Decrypt pCypherData in AES ECB decryption mode using Interrupt, the decyphered data are available in pPlainData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pCypherData,: Pointer to the cyphertext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pPlainData,: Pointer to the plaintext buffer.
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
Return values:
HAL status

Definition at line 741 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, CRYP_CHAINMODE_AES_ECB, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_IT(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pPlainData,
 |  | uint16_t | Size,
 |  | uint8_t * | pCypherData,
 |  | uint32_t | Timeout
 | ) |  |

Encrypt pPlainData in AES ECB encryption mode.

The cypher data are available in pCypherData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pPlainData,: Pointer to the plaintext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pCypherData,: Pointer to the cyphertext buffer
Timeout,: Specify Timeout value
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
Return values:
HAL status

Definition at line 465 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CHAINMODE_AES_ECB, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pPlainData,
 |  | uint16_t | Size,
 |  | uint8_t * | pCypherData
 | ) |  |

Encrypt pPlainData in AES ECB encryption mode using DMA, the cypher data are available in pCypherData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pPlainData,: Pointer to the plaintext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pCypherData,: Pointer to the cyphertext buffer
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
Return values:
HAL status

Definition at line 832 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CHAINMODE_AES_ECB, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_DMA(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pPlainData,
 |  | uint16_t | Size,
 |  | uint8_t * | pCypherData
 | ) |  |

Encrypt pPlainData in AES ECB encryption mode using Interrupt, the cypher data are available in pCypherData.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pPlainData,: Pointer to the plaintext buffer
Size,: Length of the plaintext buffer in bytes, must be a multiple of 16.
pCypherData,: Pointer to the cyphertext buffer
Note:
This API is provided only to maintain compatibility with legacy software. Users should directly resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
Return values:
HAL status

Definition at line 650 of file stm32l4xx_hal_cryp.c.

References CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CHAINMODE_AES_ECB, CRYP_KEY_WRITE_ENABLE, HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_IT(), CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::KeyWriteFlag, and CRYP_InitTypeDef::OperatingMode.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Callback functions

Functions
Callback functions
CRYP Exported Functions

Callback functions. More...

Functions

__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input DMA transfer complete callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output DMA transfer complete callback.

Detailed Description

Callback functions.

  ==============================================================================
                      ##### Callback functions  #####
  ==============================================================================
    [..]  This section provides Interruption and DMA callback functions:
      (+) DMA Input data transfer complete
      (+) DMA Output data transfer complete
      (+) DMA or Interrupt error

Function Documentation

void HAL_CRYP_ErrorCallback ( CRYP_HandleTypeDef * hcryp )

CRYP error callback.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 1034 of file stm32l4xx_hal_cryp.c.

Referenced by CRYP_DMAError(), CRYP_GCMCMAC_DMAError(), CRYP_Padding(), HAL_CRYP_IRQHandler(), and HAL_CRYPEx_Read_SuspendRegisters().

void HAL_CRYP_InCpltCallback ( CRYP_HandleTypeDef * hcryp )

Input DMA transfer complete callback.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 1050 of file stm32l4xx_hal_cryp.c.

Referenced by CRYP_DMAInCplt(), and CRYP_GCMCMAC_DMAInCplt().

void HAL_CRYP_OutCpltCallback ( CRYP_HandleTypeDef * hcryp )

Output DMA transfer complete callback.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 1066 of file stm32l4xx_hal_cryp.c.

Referenced by CRYP_DMAOutCplt(), CRYP_GCMCMAC_DMAOutCplt(), and HAL_CRYPEx_AES_Auth_DMA().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYP IRQ handler

Functions
CRYP IRQ handler
CRYP Exported Functions

AES IRQ handler. More...

Functions

void HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
Handle AES interrupt request.

Detailed Description

AES IRQ handler.

  ==============================================================================
                ##### AES IRQ handler management #####
  ==============================================================================
[..]  This section provides AES IRQ handler function.

Function Documentation

void HAL_CRYP_IRQHandler ( CRYP_HandleTypeDef * hcryp )

Handle AES interrupt request.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 1099 of file stm32l4xx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_GET_FLAG, __HAL_CRYP_GET_IT_SOURCE, CRYP_InitTypeDef::ChainingMode, CRYP_AES_Auth_IT(), CRYP_AES_IT(), CRYP_CCF_CLEAR, CRYP_CHAINMODE_AES_CMAC, CRYP_CHAINMODE_AES_GCM_GMAC, CRYP_ERR_CLEAR, CRYP_IT_CCF, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_IT_RDERR, CRYP_IT_WRERR, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ErrorCallback(), HAL_CRYP_READ_ERROR, HAL_CRYP_STATE_ERROR, HAL_CRYP_WRITE_ERROR, CRYP_HandleTypeDef::Init, and CRYP_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRYP Exported Functions

Peripheral State functions. More...

Functions

HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Return the CRYP handle state.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP peripheral error.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

uint32_t HAL_CRYP_GetError ( CRYP_HandleTypeDef * hcryp )

Return the CRYP peripheral error.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Note:
The returned error is a bit-map combination of possible errors
Return values:
Error bit-map

Definition at line 1192 of file stm32l4xx_hal_cryp.c.

References CRYP_HandleTypeDef::ErrorCode.

HAL_CRYP_STATETypeDef HAL_CRYP_GetState ( CRYP_HandleTypeDef * hcryp )

Return the CRYP handle state.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL state

Definition at line 1179 of file stm32l4xx_hal_cryp.c.

References CRYP_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYP Exported Types

Data Structures | Defines | Enumerations
CRYP Exported Types
CRYP

Data Structures

struct | CRYP_InitTypeDef
CRYP Configuration Structure definition. More...
struct | CRYP_HandleTypeDef
CRYP handle Structure definition. More...

Defines

#define | HAL_CRYP_ERROR_NONE ((uint32_t)0x00000000)
HAL CRYP Error Codes definition.
#define | HAL_CRYP_WRITE_ERROR ((uint32_t)0x00000001)
#define | HAL_CRYP_READ_ERROR ((uint32_t)0x00000002)
#define | HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004)
#define | HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008)

Enumerations

enum HAL_CRYP_STATETypeDef {
HAL_CRYP_STATE_RESET = 0x00, HAL_CRYP_STATE_READY = 0x01, HAL_CRYP_STATE_BUSY = 0x02, HAL_CRYP_STATE_TIMEOUT = 0x03,
HAL_CRYP_STATE_ERROR = 0x04, HAL_CRYP_STATE_SUSPENDED = 0x05
}
HAL CRYP State structures definition. More...
enum HAL_PhaseTypeDef {
HAL_CRYP_PHASE_READY = 0x01, HAL_CRYP_PHASE_PROCESS = 0x02, HAL_CRYP_PHASE_START = 0x03, HAL_CRYP_PHASE_INIT_OVER = 0x04,
HAL_CRYP_PHASE_HEADER_OVER = 0x05, HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, HAL_CRYP_PHASE_FINAL_OVER = 0x07, HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08,
HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, HAL_CRYP_PHASE_NOT_USED = 0x0a
}
HAL CRYP phase structures definition. More...
enum | HAL_SuspendTypeDef { HAL_CRYP_SUSPEND_NONE = 0x00, HAL_CRYP_SUSPEND = 0x01 }
HAL CRYP mode suspend definitions. More...

Define Documentation

#define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008)

Busy flag error

Definition at line 147 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYPEx_Read_SuspendRegisters().

#define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004)

DMA error

Definition at line 146 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_DMAError(), and CRYP_GCMCMAC_DMAError().

#define HAL_CRYP_ERROR_NONE ((uint32_t)0x00000000)

HAL CRYP Error Codes definition.

No error

Definition at line 143 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

#define HAL_CRYP_READ_ERROR ((uint32_t)0x00000002)

Read error

Definition at line 145 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define HAL_CRYP_WRITE_ERROR ((uint32_t)0x00000001)

Write error

Definition at line 144 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

Enumeration Type Documentation

enum HAL_CRYP_STATETypeDef

HAL CRYP State structures definition.

Enumerator:
HAL_CRYP_STATE_RESET

CRYP not yet initialized or disabled

HAL_CRYP_STATE_READY

CRYP initialized and ready for use

HAL_CRYP_STATE_BUSY

CRYP internal processing is ongoing

HAL_CRYP_STATE_TIMEOUT

CRYP timeout state

HAL_CRYP_STATE_ERROR

CRYP error state

HAL_CRYP_STATE_SUSPENDED

CRYP suspended

Definition at line 102 of file stm32l4xx_hal_cryp.h.

enum HAL_PhaseTypeDef

HAL CRYP phase structures definition.

Enumerator:
HAL_CRYP_PHASE_READY

CRYP peripheral is ready for initialization.

HAL_CRYP_PHASE_PROCESS

CRYP peripheral is in processing phase

HAL_CRYP_PHASE_START

CRYP peripheral has been initialized but GCM/GMAC/CMAC initialization phase has not started

HAL_CRYP_PHASE_INIT_OVER

GCM/GMAC/CMAC init phase has been carried out

HAL_CRYP_PHASE_HEADER_OVER

GCM/GMAC/CMAC header phase has been carried out

HAL_CRYP_PHASE_PAYLOAD_OVER

GCM/GMAC/CMAC payload phase has been carried out

HAL_CRYP_PHASE_FINAL_OVER

GCM/GMAC/CMAC final phase has been carried out

HAL_CRYP_PHASE_HEADER_SUSPENDED

GCM/GMAC/CMAC header phase has been suspended

HAL_CRYP_PHASE_PAYLOAD_SUSPENDED

GCM/GMAC payload phase has been suspended

HAL_CRYP_PHASE_NOT_USED

Phase is irrelevant to the current chaining mode

Definition at line 115 of file stm32l4xx_hal_cryp.h.

enum HAL_SuspendTypeDef

HAL CRYP mode suspend definitions.

Enumerator:
HAL_CRYP_SUSPEND_NONE

CRYP peripheral suspension not requested

HAL_CRYP_SUSPEND

CRYP peripheral suspension requested

Definition at line 133 of file stm32l4xx_hal_cryp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRYP_InitTypeDef Struct Reference
CRYP Exported Types

CRYP Configuration Structure definition. More...

#include <stm32l4xx_hal_cryp.h>

Data Fields

uint32_t | DataType
uint32_t | KeySize
uint32_t | OperatingMode
uint32_t | ChainingMode
uint32_t | KeyWriteFlag
uint32_t | GCMCMACPhase
uint8_t * | pKey
uint8_t * | pInitVect
uint8_t * | Header
uint64_t | HeaderSize

Detailed Description

CRYP Configuration Structure definition.

Definition at line 67 of file stm32l4xx_hal_cryp.h.

Field Documentation

uint32_t CRYP_InitTypeDef::ChainingMode

AES chaining mode. This parameter can be a value of AES chaining mode

Definition at line 78 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_SetInitVector(), HAL_CRYP_AESCBC_Decrypt(), HAL_CRYP_AESCBC_Decrypt_DMA(), HAL_CRYP_AESCBC_Decrypt_IT(), HAL_CRYP_AESCBC_Encrypt(), HAL_CRYP_AESCBC_Encrypt_DMA(), HAL_CRYP_AESCBC_Encrypt_IT(), HAL_CRYP_AESCTR_Decrypt(), HAL_CRYP_AESCTR_Decrypt_DMA(), HAL_CRYP_AESCTR_Decrypt_IT(), HAL_CRYP_AESCTR_Encrypt(), HAL_CRYP_AESCTR_Encrypt_DMA(), HAL_CRYP_AESCTR_Encrypt_IT(), HAL_CRYP_AESECB_Decrypt(), HAL_CRYP_AESECB_Decrypt_DMA(), HAL_CRYP_AESECB_Decrypt_IT(), HAL_CRYP_AESECB_Encrypt(), HAL_CRYP_AESECB_Encrypt_DMA(), HAL_CRYP_AESECB_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

uint32_t CRYP_InitTypeDef::DataType

32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of AES Data Type selection

Definition at line 69 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

uint32_t CRYP_InitTypeDef::GCMCMACPhase

Indicates the processing phase of the Galois Counter Mode (GCM), Galois Message Authentication Code (GMAC) or Cipher Message Authentication Code (CMAC) mode. This parameter can be a value of GCM/GMAC and CMAC processing phase selection

Definition at line 84 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_GCMCMAC_DMAInCplt(), CRYP_Padding(), HAL_CRYP_Init(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

uint8_t* CRYP_InitTypeDef::Header

Header used in GCM/GMAC and CMAC modes

Definition at line 93 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

uint64_t CRYP_InitTypeDef::HeaderSize

Header size in bytes

Definition at line 95 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

uint32_t CRYP_InitTypeDef::KeySize

128 or 256-bit key length. This parameter can be a value of Key size selection

Definition at line 72 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_ReadKey(), CRYP_SetKey(), and HAL_CRYP_Init().

uint32_t CRYP_InitTypeDef::KeyWriteFlag

Allows to bypass or not key write-up before decryption. This parameter can be a value of AES decryption key write-up flag

Definition at line 81 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_AESCBC_Decrypt(), HAL_CRYP_AESCBC_Decrypt_DMA(), HAL_CRYP_AESCBC_Decrypt_IT(), HAL_CRYP_AESCBC_Encrypt(), HAL_CRYP_AESCBC_Encrypt_DMA(), HAL_CRYP_AESCBC_Encrypt_IT(), HAL_CRYP_AESCTR_Decrypt(), HAL_CRYP_AESCTR_Decrypt_DMA(), HAL_CRYP_AESCTR_Decrypt_IT(), HAL_CRYP_AESCTR_Encrypt(), HAL_CRYP_AESCTR_Encrypt_DMA(), HAL_CRYP_AESCTR_Encrypt_IT(), HAL_CRYP_AESECB_Decrypt(), HAL_CRYP_AESECB_Decrypt_DMA(), HAL_CRYP_AESECB_Decrypt_IT(), HAL_CRYP_AESECB_Encrypt(), HAL_CRYP_AESECB_Encrypt_DMA(), HAL_CRYP_AESECB_Encrypt_IT(), and HAL_CRYP_Init().

uint32_t CRYP_InitTypeDef::OperatingMode

AES operating mode. This parameter can be a value of AES operating mode

Definition at line 75 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), CRYP_Padding(), HAL_CRYP_AESCBC_Decrypt(), HAL_CRYP_AESCBC_Decrypt_DMA(), HAL_CRYP_AESCBC_Decrypt_IT(), HAL_CRYP_AESCBC_Encrypt(), HAL_CRYP_AESCBC_Encrypt_DMA(), HAL_CRYP_AESCBC_Encrypt_IT(), HAL_CRYP_AESCTR_Decrypt(), HAL_CRYP_AESCTR_Decrypt_DMA(), HAL_CRYP_AESCTR_Decrypt_IT(), HAL_CRYP_AESCTR_Encrypt(), HAL_CRYP_AESCTR_Encrypt_DMA(), HAL_CRYP_AESCTR_Encrypt_IT(), HAL_CRYP_AESECB_Decrypt(), HAL_CRYP_AESECB_Decrypt_DMA(), HAL_CRYP_AESECB_Decrypt_IT(), HAL_CRYP_AESECB_Encrypt(), HAL_CRYP_AESECB_Encrypt_DMA(), HAL_CRYP_AESECB_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYPEx_AES(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_IT(), HAL_CRYPEx_AES_DMA(), and HAL_CRYPEx_AES_IT().

uint8_t* CRYP_InitTypeDef::pInitVect

Initialization Vector used for CTR, CBC, GCM/GMAC and CMAC modes

Definition at line 91 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_SetInitVector().

uint8_t* CRYP_InitTypeDef::pKey

Encryption/Decryption Key

Definition at line 89 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_SetKey().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_cryp.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRYP_HandleTypeDef Struct Reference
CRYP Exported Types

CRYP handle Structure definition. More...

#include <stm32l4xx_hal_cryp.h>

Data Fields

AES_TypeDef * | Instance
CRYP_InitTypeDef Init
uint8_t * | pCrypInBuffPtr
uint8_t * | pCrypOutBuffPtr
uint32_t | CrypInCount
uint32_t | CrypOutCount
HAL_PhaseTypeDef Phase
DMA_HandleTypeDef * hdmain
DMA_HandleTypeDef * hdmaout
HAL_LockTypeDef | Lock
__IO HAL_CRYP_STATETypeDef | State
__IO uint32_t | ErrorCode
HAL_SuspendTypeDef SuspendRequest

Detailed Description

CRYP handle Structure definition.

Definition at line 152 of file stm32l4xx_hal_cryp.h.

Field Documentation

uint32_t CRYP_HandleTypeDef::CrypInCount

Input data size in bytes or, after suspension, the remaining number of bytes to process

Definition at line 162 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), CRYP_GCMCMAC_DMAInCplt(), CRYP_GCMCMAC_DMAOutCplt(), CRYP_ProcessData(), HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), HAL_CRYPEx_AES_Auth_IT(), and HAL_CRYPEx_AES_IT().

uint32_t CRYP_HandleTypeDef::CrypOutCount

Output data size in bytes

Definition at line 165 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_Auth_IT(), and HAL_CRYPEx_AES_IT().

__IO uint32_t CRYP_HandleTypeDef::ErrorCode

CRYP peripheral error code

Definition at line 179 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_DMAError(), CRYP_GCMCMAC_DMAError(), HAL_CRYP_GetError(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), and HAL_CRYPEx_Read_SuspendRegisters().

DMA_HandleTypeDef* CRYP_HandleTypeDef::hdmain

CRYP peripheral Input DMA handle parameters

Definition at line 171 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_GCMCMAC_SetDMAConfig(), and CRYP_SetDMAConfig().

DMA_HandleTypeDef* CRYP_HandleTypeDef::hdmaout

CRYP peripheral Output DMA handle parameters

Definition at line 173 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_GCMCMAC_SetDMAConfig(), and CRYP_SetDMAConfig().

CRYP_InitTypeDef CRYP_HandleTypeDef::Init

CRYP initialization parameters

Definition at line 156 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), CRYP_GCMCMAC_DMAInCplt(), CRYP_Padding(), CRYP_ReadKey(), CRYP_SetInitVector(), CRYP_SetKey(), HAL_CRYP_AESCBC_Decrypt(), HAL_CRYP_AESCBC_Decrypt_DMA(), HAL_CRYP_AESCBC_Decrypt_IT(), HAL_CRYP_AESCBC_Encrypt(), HAL_CRYP_AESCBC_Encrypt_DMA(), HAL_CRYP_AESCBC_Encrypt_IT(), HAL_CRYP_AESCTR_Decrypt(), HAL_CRYP_AESCTR_Decrypt_DMA(), HAL_CRYP_AESCTR_Decrypt_IT(), HAL_CRYP_AESCTR_Encrypt(), HAL_CRYP_AESCTR_Encrypt_DMA(), HAL_CRYP_AESCTR_Encrypt_IT(), HAL_CRYP_AESECB_Decrypt(), HAL_CRYP_AESECB_Decrypt_DMA(), HAL_CRYP_AESECB_Decrypt_IT(), HAL_CRYP_AESECB_Encrypt(), HAL_CRYP_AESECB_Encrypt_DMA(), HAL_CRYP_AESECB_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AES(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), HAL_CRYPEx_AES_Auth_IT(), HAL_CRYPEx_AES_DMA(), and HAL_CRYPEx_AES_IT().

AES_TypeDef* CRYP_HandleTypeDef::Instance

Register base address

Definition at line 154 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCMAC_DMAInCplt(), CRYP_GCMCMAC_DMAOutCplt(), CRYP_GCMCMAC_SetDMAConfig(), CRYP_Padding(), CRYP_ProcessData(), CRYP_ReadKey(), CRYP_SetDMAConfig(), CRYP_SetInitVector(), CRYP_SetKey(), CRYP_WaitOnBusyFlagReset(), CRYP_WaitOnCCFlag(), HAL_CRYP_Init(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), HAL_CRYPEx_AES_Auth_IT(), HAL_CRYPEx_AES_IT(), HAL_CRYPEx_Read_ControlRegister(), HAL_CRYPEx_Read_IVRegisters(), HAL_CRYPEx_Read_KeyRegisters(), HAL_CRYPEx_Read_SuspendRegisters(), HAL_CRYPEx_Write_ControlRegister(), HAL_CRYPEx_Write_IVRegisters(), HAL_CRYPEx_Write_KeyRegisters(), and HAL_CRYPEx_Write_SuspendRegisters().

HAL_LockTypeDef CRYP_HandleTypeDef::Lock

CRYP locking object

Definition at line 175 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

uint8_t* CRYP_HandleTypeDef::pCrypInBuffPtr

Pointer to CRYP processing (encryption, decryption,...) input buffer

Definition at line 158 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), CRYP_Padding(), CRYP_ProcessData(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), HAL_CRYPEx_AES_Auth_IT(), and HAL_CRYPEx_AES_IT().

uint8_t* CRYP_HandleTypeDef::pCrypOutBuffPtr

Pointer to CRYP processing (encryption, decryption,...) output buffer

Definition at line 160 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), CRYP_Padding(), CRYP_ProcessData(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), HAL_CRYPEx_AES_Auth_IT(), and HAL_CRYPEx_AES_IT().

HAL_PhaseTypeDef CRYP_HandleTypeDef::Phase

CRYP peripheral processing phase for GCM, GMAC or CMAC modes. Indicates the last phase carried out to ease phase transitions

Definition at line 167 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_GCMCMAC_DMAInCplt(), CRYP_GCMCMAC_DMAOutCplt(), HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

__IO HAL_CRYP_STATETypeDef CRYP_HandleTypeDef::State

CRYP peripheral state

Definition at line 177 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCMAC_DMAError(), CRYP_GCMCMAC_DMAInCplt(), CRYP_GCMCMAC_DMAOutCplt(), CRYP_Padding(), CRYP_ProcessData(), CRYP_ReadKey(), HAL_CRYP_DeInit(), HAL_CRYP_GetState(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AES(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), HAL_CRYPEx_AES_Auth_IT(), HAL_CRYPEx_AES_DMA(), HAL_CRYPEx_AES_IT(), HAL_CRYPEx_Read_SuspendRegisters(), and HAL_CRYPEx_Write_ControlRegister().

HAL_SuspendTypeDef CRYP_HandleTypeDef::SuspendRequest

CRYP peripheral suspension request flag

Definition at line 181 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), CRYP_ProcessData(), HAL_CRYP_Init(), HAL_CRYPEx_AES_Auth(), and HAL_CRYPEx_ProcessSuspend().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_cryp.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Key size selection

Defines
Key size selection
CRYP Exported Constants

Defines

#define | CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
#define | CRYP_KEYSIZE_256B AES_CR_KEYSIZE

Define Documentation

#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)

128-bit long key

Definition at line 197 of file stm32l4xx_hal_cryp.h.

#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE

256-bit long key

Definition at line 198 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_ReadKey(), CRYP_SetKey(), HAL_CRYPEx_Read_KeyRegisters(), and HAL_CRYPEx_Write_KeyRegisters().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES Data Type selection

Defines
AES Data Type selection
CRYP Exported Constants

Defines

#define | CRYP_DATATYPE_32B ((uint32_t)0x00000000)
#define | CRYP_DATATYPE_16B AES_CR_DATATYPE_0
#define | CRYP_DATATYPE_8B AES_CR_DATATYPE_1
#define | CRYP_DATATYPE_1B AES_CR_DATATYPE

Define Documentation

#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0

16-bit data type (half-word swapping)

Definition at line 207 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

#define CRYP_DATATYPE_1B AES_CR_DATATYPE

1-bit data type (bit swapping)

Definition at line 209 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)

32-bit data type (no swapping)

Definition at line 206 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1

8-bit data type (byte swapping)

Definition at line 208 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES Enable state

Defines
AES Enable state
CRYP Exported Constants

Defines

#define | CRYP_AES_DISABLE ((uint32_t)0x00000000)
#define | CRYP_AES_ENABLE AES_CR_EN

Define Documentation

#define CRYP_AES_DISABLE ((uint32_t)0x00000000)

Disable AES

Definition at line 217 of file stm32l4xx_hal_cryp.h.

#define CRYP_AES_ENABLE AES_CR_EN

Enable AES

Definition at line 218 of file stm32l4xx_hal_cryp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES operating mode

Defines
AES operating mode
CRYP Exported Constants

Defines

#define | CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000)
#define | CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0
#define | CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1
#define | CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
#define | CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000)

Define Documentation

#define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1

Decryption

Definition at line 228 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_AESCTR_Decrypt(), HAL_CRYP_AESCTR_Decrypt_DMA(), and HAL_CRYP_AESCTR_Decrypt_IT().

#define CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000)

Encryption mode

Definition at line 226 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_Padding(), HAL_CRYP_AESCBC_Encrypt(), HAL_CRYP_AESCBC_Encrypt_DMA(), HAL_CRYP_AESCBC_Encrypt_IT(), HAL_CRYP_AESCTR_Encrypt(), HAL_CRYP_AESCTR_Encrypt_DMA(), HAL_CRYP_AESCTR_Encrypt_IT(), HAL_CRYP_AESECB_Encrypt(), HAL_CRYP_AESECB_Encrypt_DMA(), HAL_CRYP_AESECB_Encrypt_IT(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_IT(), and HAL_CRYPEx_Read_SuspendRegisters().

#define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0

Key derivation mode

Definition at line 227 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_IT(), HAL_CRYP_Init(), HAL_CRYPEx_AES(), HAL_CRYPEx_AES_DMA(), and HAL_CRYPEx_AES_IT().

#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE

Key derivation and decryption

Definition at line 229 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_AESCBC_Decrypt(), HAL_CRYP_AESCBC_Decrypt_DMA(), HAL_CRYP_AESCBC_Decrypt_IT(), HAL_CRYP_AESECB_Decrypt(), HAL_CRYP_AESECB_Decrypt_DMA(), HAL_CRYP_AESECB_Decrypt_IT(), and HAL_CRYP_Init().

#define CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000)

GMAC or CMAC authentication tag generation

Definition at line 230 of file stm32l4xx_hal_cryp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES chaining mode

Defines
AES chaining mode
CRYP Exported Constants

Defines

#define | CRYP_CHAINMODE_AES_ECB ((uint32_t)0x00000000)
#define | CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0
#define | CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1
#define | CRYP_CHAINMODE_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1)
#define | CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2

Define Documentation

#define CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0

Cipher block chaining algorithm

Definition at line 239 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_AESCBC_Decrypt(), HAL_CRYP_AESCBC_Decrypt_DMA(), HAL_CRYP_AESCBC_Decrypt_IT(), HAL_CRYP_AESCBC_Encrypt(), HAL_CRYP_AESCBC_Encrypt_DMA(), and HAL_CRYP_AESCBC_Encrypt_IT().

#define CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2

Cipher message authentication code

Definition at line 242 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_SetInitVector(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

#define CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1

Counter mode chaining algorithm

Definition at line 240 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_Padding(), HAL_CRYP_AESCTR_Decrypt(), HAL_CRYP_AESCTR_Decrypt_DMA(), HAL_CRYP_AESCTR_Decrypt_IT(), HAL_CRYP_AESCTR_Encrypt(), HAL_CRYP_AESCTR_Encrypt_DMA(), HAL_CRYP_AESCTR_Encrypt_IT(), HAL_CRYP_Init(), and HAL_CRYPEx_AES_Auth_IT().

#define CRYP_CHAINMODE_AES_ECB ((uint32_t)0x00000000)

Electronic codebook chaining algorithm

Definition at line 238 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_AESECB_Decrypt(), HAL_CRYP_AESECB_Decrypt_DMA(), HAL_CRYP_AESECB_Decrypt_IT(), HAL_CRYP_AESECB_Encrypt(), HAL_CRYP_AESECB_Encrypt_DMA(), HAL_CRYP_AESECB_Encrypt_IT(), and HAL_CRYP_Init().

#define CRYP_CHAINMODE_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1)

Galois counter mode - Galois message authentication code

Definition at line 241 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_Padding(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES decryption key write-up flag

Defines
AES decryption key write-up flag
CRYP Exported Constants

Defines

#define | CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000)
#define | CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001)

Define Documentation

#define CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001)

Disable decryption key writing

Definition at line 251 of file stm32l4xx_hal_cryp.h.

#define CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000)

Enable decryption key writing

Definition at line 250 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_AESCBC_Decrypt(), HAL_CRYP_AESCBC_Decrypt_DMA(), HAL_CRYP_AESCBC_Decrypt_IT(), HAL_CRYP_AESCBC_Encrypt(), HAL_CRYP_AESCBC_Encrypt_DMA(), HAL_CRYP_AESCBC_Encrypt_IT(), HAL_CRYP_AESCTR_Decrypt(), HAL_CRYP_AESCTR_Decrypt_DMA(), HAL_CRYP_AESCTR_Decrypt_IT(), HAL_CRYP_AESCTR_Encrypt(), HAL_CRYP_AESCTR_Encrypt_DMA(), HAL_CRYP_AESCTR_Encrypt_IT(), HAL_CRYP_AESECB_Decrypt(), HAL_CRYP_AESECB_Decrypt_DMA(), HAL_CRYP_AESECB_Decrypt_IT(), HAL_CRYP_AESECB_Encrypt(), HAL_CRYP_AESECB_Encrypt_DMA(), HAL_CRYP_AESECB_Encrypt_IT(), and HAL_CRYP_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Input phase management enable state

Defines
DMA Input phase management enable state
CRYP Exported Constants

Defines

#define | CRYP_DMAIN_DISABLE ((uint32_t)0x00000000)
#define | CRYP_DMAIN_ENABLE AES_CR_DMAINEN

Define Documentation

#define CRYP_DMAIN_DISABLE ((uint32_t)0x00000000)

Disable DMA Input phase management

Definition at line 259 of file stm32l4xx_hal_cryp.h.

#define CRYP_DMAIN_ENABLE AES_CR_DMAINEN

Enable DMA Input phase management

Definition at line 260 of file stm32l4xx_hal_cryp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Output phase management enable state

Defines
DMA Output phase management enable state
CRYP Exported Constants

Defines

#define | CRYP_DMAOUT_DISABLE ((uint32_t)0x00000000)
#define | CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN

Define Documentation

#define CRYP_DMAOUT_DISABLE ((uint32_t)0x00000000)

Disable DMA Output phase management

Definition at line 268 of file stm32l4xx_hal_cryp.h.

#define CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN

Enable DMA Output phase management

Definition at line 269 of file stm32l4xx_hal_cryp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GCM/GMAC and CMAC processing phase selection

Defines
GCM/GMAC and CMAC processing phase selection
CRYP Exported Constants

Defines

#define | CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000)
#define | CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0
#define | CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1
#define | CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH

Define Documentation

#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000)

GCM/GMAC init phase

Definition at line 278 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1

GCM payload phaset

Definition at line 280 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_Padding(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), HAL_CRYPEx_AES_Auth_IT(), and HAL_CRYPEx_Read_SuspendRegisters().

#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH

GCM/GMAC or CMAC final phase

Definition at line 281 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_Padding(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0

GCM/GMAC or CMAC header phase

Definition at line 279 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_GCMCMAC_DMAInCplt(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES status flags

Defines
AES status flags
CRYP Exported Constants

Defines

#define | CRYP_FLAG_BUSY AES_SR_BUSY
#define | CRYP_FLAG_WRERR AES_SR_WRERR
#define | CRYP_FLAG_RDERR AES_SR_RDERR
#define | CRYP_FLAG_CCF AES_SR_CCF

Define Documentation

#define CRYP_FLAG_BUSY AES_SR_BUSY

GCM process suspension forbidden

Definition at line 290 of file stm32l4xx_hal_cryp.h.

#define CRYP_FLAG_CCF AES_SR_CCF

Computation completed

Definition at line 293 of file stm32l4xx_hal_cryp.h.

#define CRYP_FLAG_RDERR AES_SR_RDERR

Read error

Definition at line 292 of file stm32l4xx_hal_cryp.h.

#define CRYP_FLAG_WRERR AES_SR_WRERR

Write Error

Definition at line 291 of file stm32l4xx_hal_cryp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES clearing flags

Defines
AES clearing flags
CRYP Exported Constants

Defines

#define | CRYP_CCF_CLEAR AES_CR_CCFC
#define | CRYP_ERR_CLEAR AES_CR_ERRC

Define Documentation

#define CRYP_CCF_CLEAR AES_CR_CCFC

Computation Complete Flag Clear

Definition at line 302 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_DMAOutCplt(), CRYP_GCMCMAC_DMAOutCplt(), CRYP_Padding(), CRYP_ProcessData(), CRYP_ReadKey(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AES_Auth(), and HAL_CRYPEx_AES_Auth_DMA().

#define CRYP_ERR_CLEAR AES_CR_ERRC

Error Flag Clear

Definition at line 303 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_DMAError(), CRYP_GCMCMAC_DMAError(), and HAL_CRYP_IRQHandler().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES Interrupts Enable bits

Defines
AES Interrupts Enable bits
CRYP Exported Constants

Defines

#define | CRYP_IT_CCFIE AES_CR_CCFIE
#define | CRYP_IT_ERRIE AES_CR_ERRIE

Define Documentation

#define CRYP_IT_CCFIE AES_CR_CCFIE

Computation Complete interrupt enable

Definition at line 311 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AES_Auth_IT(), and HAL_CRYPEx_AES_IT().

#define CRYP_IT_ERRIE AES_CR_ERRIE

Error interrupt enable

Definition at line 312 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AES_Auth_IT(), and HAL_CRYPEx_AES_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES Interrupts flags

Defines
AES Interrupts flags
CRYP Exported Constants

Defines

#define | CRYP_IT_WRERR AES_SR_WRERR
#define | CRYP_IT_RDERR AES_SR_RDERR
#define | CRYP_IT_CCF AES_SR_CCF

Define Documentation

#define CRYP_IT_CCF AES_SR_CCF

Computation completed

Definition at line 322 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define CRYP_IT_RDERR AES_SR_RDERR

Read Error

Definition at line 321 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define CRYP_IT_WRERR AES_SR_WRERR

Write Error

Definition at line 320 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYP Exported Macros

Defines
CRYP Exported Macros
CRYP

Defines

#define | __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
Reset CRYP handle state.
#define | __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN)
Enable the CRYP AES peripheral.
#define | __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN)
Disable the CRYP AES peripheral.
#define | __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))
Set the algorithm operating mode.
#define | __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
Set the algorithm chaining mode.
#define | __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified CRYP status flag is set or not.
#define | __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))
Clear the CRYP pending status flag.
#define | __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt source is enabled or not.
#define | __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt is set or not.
#define | __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))
Clear the CRYP pending interrupt.
#define | __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
Enable the CRYP interrupt.
#define | __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
Disable the CRYP interrupt.

Define Documentation

#define __HAL_CRYP_CLEAR_FLAG ( __FLAG__ ) SET_BIT(AES->CR, (__FLAG__))

Clear the CRYP pending status flag.

Parameters:
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
  • CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
Return values:
None

Definition at line 401 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCMAC_DMAError(), CRYP_GCMCMAC_DMAOutCplt(), CRYP_Padding(), CRYP_ProcessData(), CRYP_ReadKey(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AES_Auth(), and HAL_CRYPEx_AES_Auth_DMA().

#define __HAL_CRYP_CLEAR_IT ( __INTERRUPT__ ) SET_BIT(AES->CR, (__INTERRUPT__))

Clear the CRYP pending interrupt.

Parameters:
__INTERRUPT__,: specifies the IT to clear. This parameter can be one of the following values:
  • CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
  • CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
Return values:
None

Definition at line 434 of file stm32l4xx_hal_cryp.h.

#define __HAL_CRYP_DISABLE ( ) (AES->CR &= ~AES_CR_EN)

Disable the CRYP AES peripheral.

Return values:
None

Definition at line 352 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_DMAOutCplt(), HAL_CRYP_DeInit(), HAL_CRYP_Init(), HAL_CRYPEx_AES_Auth(), and HAL_CRYPEx_AES_Auth_DMA().

#define __HAL_CRYP_DISABLE_IT ( __INTERRUPT__ ) ((AES->CR) &= ~(__INTERRUPT__))

Disable the CRYP interrupt.

Parameters:
__INTERRUPT__,: CRYP Interrupt. This parameter can be one of the following values:
  • CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
  • CRYP_IT_CCFIE Computation Complete interrupt
Return values:
None

Definition at line 456 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_AES_IT(), and HAL_CRYP_IRQHandler().

#define __HAL_CRYP_ENABLE ( ) (AES->CR |= AES_CR_EN)

Enable the CRYP AES peripheral.

Return values:
None

Definition at line 346 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_GCMCMAC_SetDMAConfig(), CRYP_SetDMAConfig(), HAL_CRYP_Init(), HAL_CRYPEx_AES_Auth(), HAL_CRYPEx_AES_Auth_DMA(), and HAL_CRYPEx_AES_Auth_IT().

#define __HAL_CRYP_ENABLE_IT ( __INTERRUPT__ ) ((AES->CR) |= (__INTERRUPT__))

Enable the CRYP interrupt.

Parameters:
__INTERRUPT__,: CRYP Interrupt. This parameter can be one of the following values:
  • CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
  • CRYP_IT_CCFIE Computation Complete interrupt
Return values:
None

Definition at line 445 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYPEx_AES_Auth_IT(), and HAL_CRYPEx_AES_IT().

#define __HAL_CRYP_GET_FLAG ( __FLAG__ ) ((AES->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified CRYP status flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • CRYP_FLAG_BUSY GCM process suspension forbidden
  • CRYP_IT_WRERR Write Error
  • CRYP_IT_RDERR Read Error
  • CRYP_IT_CCF Computation Complete
Return values:
The state of __FLAG__ (TRUE or FALSE).

Definition at line 391 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define __HAL_CRYP_GET_IT ( __INTERRUPT__ ) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified CRYP interrupt is set or not.

Parameters:
__INTERRUPT__,: specifies the interrupt to check. This parameter can be one of the following values:
  • CRYP_IT_WRERR Write Error
  • CRYP_IT_RDERR Read Error
  • CRYP_IT_CCF Computation Complete
Return values:
The state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 423 of file stm32l4xx_hal_cryp.h.

#define __HAL_CRYP_GET_IT_SOURCE ( __INTERRUPT__ ) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified CRYP interrupt source is enabled or not.

Parameters:
__INTERRUPT__,: CRYP interrupt source to check This parameter can be one of the following values:
  • CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
  • CRYP_IT_CCFIE Computation Complete interrupt
Return values:
State of interruption (TRUE or FALSE).

Definition at line 412 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define __HAL_CRYP_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)

Reset CRYP handle state.

Parameters:
__HANDLE__,: specifies the CRYP handle.
Return values:
None

Definition at line 340 of file stm32l4xx_hal_cryp.h.

#define __HAL_CRYP_SET_CHAININGMODE ( __CHAINING_MODE__ ) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))

Set the algorithm chaining mode.

Parameters:
__CHAINING_MODE__,: specifies the chaining mode This parameter can be one of the following values:
  • CRYP_CHAINMODE_AES_ECB Electronic CodeBook
  • CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
  • CRYP_CHAINMODE_AES_CTR CounTeR mode
  • CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code
  • CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code
Return values:
None

Definition at line 378 of file stm32l4xx_hal_cryp.h.

Referenced by CRYP_AES_Auth_IT(), CRYP_Padding(), and HAL_CRYPEx_AES_Auth_IT().

#define __HAL_CRYP_SET_OPERATINGMODE ( __OPERATING_MODE__ ) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))

Set the algorithm operating mode.

Parameters:
__OPERATING_MODE__,: specifies the operating mode This parameter can be one of the following values:
  • CRYP_ALGOMODE_ENCRYPT encryption
  • CRYP_ALGOMODE_KEYDERIVATION key derivation
  • CRYP_ALGOMODE_DECRYPT decryption
  • CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption
Return values:
None

Definition at line 364 of file stm32l4xx_hal_cryp.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYP Private Macros

Defines
CRYP Private Macros
CRYP

Defines

#define | IS_CRYP_KEYSIZE(__KEYSIZE__)
Verify the key size length.
#define | IS_CRYP_DATATYPE(__DATATYPE__)
Verify the input data type.
#define | IS_CRYP_AES(__MODE__)
Verify the CRYP AES IP running mode.
#define | IS_CRYP_ALGOMODE(__ALGOMODE__)
Verify the selected CRYP algorithm.
#define | IS_CRYP_CHAINMODE(__CHAINMODE__)
Verify the selected CRYP chaining algorithm.
#define | IS_CRYP_WRITE(__WRITE__)
Verify the deciphering key write option.
#define | IS_CRYP_DMAIN(__MODE__)
Verify the CRYP input data DMA mode.
#define | IS_CRYP_DMAOUT(__MODE__)
Verify the CRYP output data DMA mode.
#define | IS_CRYP_GCMCMAC_PHASE(__PHASE__)
Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.

Define Documentation

#define IS_CRYP_AES ( __MODE__ )
Value:
(((__MODE__) == CRYP_AES_DISABLE) || \
                               ((__MODE__) == CRYP_AES_ENABLE))

Verify the CRYP AES IP running mode.

Parameters:
__MODE__,: CRYP AES IP running mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 490 of file stm32l4xx_hal_cryp.h.

#define IS_CRYP_ALGOMODE ( __ALGOMODE__ )
Value:
(((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT)        || \
                                        ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION)  || \
                                        ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT)        || \
                                        ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \
                                        ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))

Verify the selected CRYP algorithm.

Parameters:
__ALGOMODE__,: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
Return values:
SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)

Definition at line 498 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

#define IS_CRYP_CHAINMODE ( __CHAINMODE__ )
Value:
(((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB)     || \
                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC)      || \
                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR)      || \
                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))

Verify the selected CRYP chaining algorithm.

Parameters:
__CHAINMODE__,: Selected CRYP chaining algorithm.
Return values:
SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)

Definition at line 509 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

#define IS_CRYP_DATATYPE ( __DATATYPE__ )
Value:
(((__DATATYPE__) == CRYP_DATATYPE_32B) || \
                                        ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
                                        ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \
                                        ((__DATATYPE__) == CRYP_DATATYPE_1B))

Verify the input data type.

Parameters:
__DATATYPE__,: Ciphering/deciphering algorithm input data type.
Return values:
SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)

Definition at line 480 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

#define IS_CRYP_DMAIN ( __MODE__ )
Value:
(((__MODE__) == CRYP_DMAIN_DISABLE) || \
                                 ((__MODE__) == CRYP_DMAIN_ENABLE))

Verify the CRYP input data DMA mode.

Parameters:
__MODE__,: CRYP input data DMA mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 528 of file stm32l4xx_hal_cryp.h.

#define IS_CRYP_DMAOUT ( __MODE__ )
Value:
(((__MODE__) == CRYP_DMAOUT_DISABLE) || \
                                  ((__MODE__) == CRYP_DMAOUT_ENABLE))

Verify the CRYP output data DMA mode.

Parameters:
__MODE__,: CRYP output data DMA mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 536 of file stm32l4xx_hal_cryp.h.

#define IS_CRYP_GCMCMAC_PHASE ( __PHASE__ )
Value:
(((__PHASE__) == CRYP_GCM_INIT_PHASE)       || \
                                          ((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \
                                          ((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE)    || \
                                          ((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE))

Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.

Parameters:
__PHASE__,: CRYP AES ciphering/deciphering/authentication algorithm phase.
Return values:
SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)

Definition at line 544 of file stm32l4xx_hal_cryp.h.

#define IS_CRYP_KEYSIZE ( __KEYSIZE__ )
Value:
(((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \
                                       ((__KEYSIZE__) == CRYP_KEYSIZE_256B))

Verify the key size length.

Parameters:
__KEYSIZE__,: Ciphering/deciphering algorithm key size.
Return values:
SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)

Definition at line 472 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

#define IS_CRYP_WRITE ( __WRITE__ )
Value:
(((__WRITE__) == CRYP_KEY_WRITE_ENABLE)      || \
                                    ((__WRITE__) == CRYP_KEY_WRITE_DISABLE))

Verify the deciphering key write option.

Parameters:
__WRITE__,: deciphering key write option.
Return values:
SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)

Definition at line 520 of file stm32l4xx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYPEx Private Constants

Defines
CRYPEx Private Constants
CRYPEx

Defines

#define | CRYP_CCF_TIMEOUTVALUE 22000
#define | CRYP_BUSY_TIMEOUTVALUE 22000
#define | CRYP_POLLING_OFF 0x0
#define | CRYP_POLLING_ON 0x1

Define Documentation

#define CRYP_BUSY_TIMEOUTVALUE 22000

BUSY flag reset time-out value

Definition at line 63 of file stm32l4xx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AES_Auth(), and HAL_CRYPEx_Read_SuspendRegisters().

#define CRYP_CCF_TIMEOUTVALUE 22000

CCF flag raising time-out value

Definition at line 62 of file stm32l4xx_hal_cryp_ex.c.

Referenced by CRYP_Padding(), and HAL_CRYPEx_AES_Auth_DMA().

#define CRYP_POLLING_OFF 0x0

No polling when padding

Definition at line 65 of file stm32l4xx_hal_cryp_ex.c.

Referenced by CRYP_GCMCMAC_DMAInCplt(), and HAL_CRYPEx_AES_Auth_DMA().

#define CRYP_POLLING_ON 0x1

Polling when padding

Definition at line 66 of file stm32l4xx_hal_cryp_ex.c.

Referenced by CRYP_GCMCMAC_DMAOutCplt(), CRYP_Padding(), HAL_CRYPEx_AES_Auth(), and HAL_CRYPEx_AES_Auth_DMA().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYPEx Private Functions

Functions
CRYPEx Private Functions
CRYPEx

Functions

static HAL_StatusTypeDef | CRYP_ProcessData (CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
Write/read input/output data in polling mode.
static HAL_StatusTypeDef | CRYP_ReadKey (CRYP_HandleTypeDef *hcryp, uint8_t *Output, uint32_t Timeout)
Read derivative key in polling mode when CRYP hardware block is set in key derivation operating mode (mode 2).
static void | CRYP_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
static void | CRYP_GCMCMAC_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer for GCM, GMAC or CMAC chainging modes.
static void | CRYP_GCMCMAC_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP Input Data process complete callback for GCM, GMAC or CMAC chainging modes.
static void | CRYP_GCMCMAC_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback for GCM, GMAC or CMAC chainging modes.
static void | CRYP_GCMCMAC_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP Output Data process complete callback for GCM, GMAC or CMAC chainging modes.
static HAL_StatusTypeDef | CRYP_WaitOnCCFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
static HAL_StatusTypeDef | CRYP_WaitOnBusyFlagReset (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Wait for Busy Flag to be reset during a GCM payload encryption process suspension.
static void | CRYP_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP Input Data process complete callback.
static void | CRYP_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP Output Data process complete callback.
static void | CRYP_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
static void | CRYP_Padding (CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling)
Last header or payload block padding when size is not a multiple of 128 bits.
HAL_StatusTypeDef | CRYP_AES_Auth_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption for GCM, GMAC or CMAC chainging modes.

Function Documentation

HAL_StatusTypeDef CRYP_AES_Auth_IT ( CRYP_HandleTypeDef * hcryp )

Handle CRYP block input/output data handling under interruption for GCM, GMAC or CMAC chainging modes.

Note:
The function is called under interruption only, once interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT().
Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2045 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_SET_CHAININGMODE, CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CCF_CLEAR, CRYP_CHAINMODE_AES_CMAC, CRYP_CHAINMODE_AES_CTR, CRYP_CHAINMODE_AES_GCM_GMAC, CRYP_GCM_INIT_PHASE, CRYP_GCM_PAYLOAD_PHASE, CRYP_GCMCMAC_FINAL_PHASE, CRYP_GCMCMAC_HEADER_PHASE, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_InitTypeDef::GCMCMACPhase, HAL_CRYP_PHASE_FINAL_OVER, HAL_CRYP_PHASE_HEADER_OVER, HAL_CRYP_PHASE_HEADER_SUSPENDED, HAL_CRYP_PHASE_INIT_OVER, HAL_CRYP_PHASE_PAYLOAD_OVER, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_ERROR, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_SUSPENDED, HAL_CRYP_SUSPEND, HAL_CRYP_SUSPEND_NONE, HAL_CRYPEx_ComputationCpltCallback(), CRYP_InitTypeDef::Header, CRYP_InitTypeDef::HeaderSize, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_InitTypeDef::OperatingMode, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_HandleTypeDef::State, and CRYP_HandleTypeDef::SuspendRequest.

Referenced by HAL_CRYP_IRQHandler().

static void CRYP_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP communication error callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 2786 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, CRYP_ERR_CLEAR, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_DMA_ERROR, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_ERROR, and CRYP_HandleTypeDef::State.

Referenced by CRYP_SetDMAConfig().

static void CRYP_DMAInCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP Input Data process complete callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 2745 of file stm32l4xx_hal_cryp_ex.c.

References HAL_CRYP_InCpltCallback(), and CRYP_HandleTypeDef::Instance.

Referenced by CRYP_SetDMAConfig().

static void CRYP_DMAOutCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP Output Data process complete callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 2761 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, CRYP_CCF_CLEAR, HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Instance, and CRYP_HandleTypeDef::State.

Referenced by CRYP_SetDMAConfig().

static void CRYP_GCMCMAC_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP communication error callback for GCM, GMAC or CMAC chainging modes.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2023 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, CRYP_ERR_CLEAR, CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_DMA_ERROR, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_ERROR, and CRYP_HandleTypeDef::State.

Referenced by CRYP_GCMCMAC_SetDMAConfig().

static void CRYP_GCMCMAC_DMAInCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP Input Data process complete callback for GCM, GMAC or CMAC chainging modes.

Note:
Specific setting of hcryp fields are required only in the case of header phase where no output data DMA transfer is on-going (only input data transfer is enabled in such a case).
Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 1946 of file stm32l4xx_hal_cryp_ex.c.

References CRYP_GCMCMAC_HEADER_PHASE, CRYP_Padding(), CRYP_POLLING_OFF, CRYP_HandleTypeDef::CrypInCount, CRYP_InitTypeDef::GCMCMACPhase, HAL_CRYP_InCpltCallback(), HAL_CRYP_PHASE_HEADER_OVER, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::Phase, and CRYP_HandleTypeDef::State.

Referenced by CRYP_GCMCMAC_SetDMAConfig().

static void CRYP_GCMCMAC_DMAOutCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP Output Data process complete callback for GCM, GMAC or CMAC chainging modes.

Note:
This callback is called only in the payload phase.
Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 1987 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, CRYP_CCF_CLEAR, CRYP_Padding(), CRYP_POLLING_ON, CRYP_HandleTypeDef::CrypInCount, HAL_CRYP_OutCpltCallback(), HAL_CRYP_PHASE_PAYLOAD_OVER, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::Phase, and CRYP_HandleTypeDef::State.

Referenced by CRYP_GCMCMAC_SetDMAConfig().

static void CRYP_GCMCMAC_SetDMAConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | inputaddr,
 |  | uint16_t | Size,
 |  | uint32_t | outputaddr
 | ) |  | [static]

Set the DMA configuration and start the DMA transfer for GCM, GMAC or CMAC chainging modes.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
inputaddr,: Address of the Input buffer.
Size,: Size of the Input buffer un bytes, must be a multiple of 16.
outputaddr,: Address of the Output buffer, null pointer when no output DMA stream has to be configured.
Return values:
None

Definition at line 2481 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_ENABLE, CRYP_GCMCMAC_DMAError(), CRYP_GCMCMAC_DMAInCplt(), CRYP_GCMCMAC_DMAOutCplt(), HAL_DMA_Start_IT(), CRYP_HandleTypeDef::hdmain, CRYP_HandleTypeDef::hdmaout, CRYP_HandleTypeDef::Instance, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_CRYPEx_AES_Auth_DMA().

static void CRYP_Padding | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | difflength,
 |  | uint32_t | polling
 | ) |  | [static]

Last header or payload block padding when size is not a multiple of 128 bits.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
difflength,: size remainder after having fed all complete 128-bit blocks.
polling,: specifies whether or not polling on CCF must be done after having entered a complete block.
Return values:
None

Definition at line 2806 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_SET_CHAININGMODE, CRYP_ALGOMODE_ENCRYPT, CRYP_CCF_CLEAR, CRYP_CCF_TIMEOUTVALUE, CRYP_CHAINMODE_AES_CTR, CRYP_CHAINMODE_AES_GCM_GMAC, CRYP_GCM_PAYLOAD_PHASE, CRYP_GCMCMAC_FINAL_PHASE, CRYP_POLLING_ON, CRYP_WaitOnCCFlag(), CRYP_InitTypeDef::GCMCMACPhase, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_InitTypeDef::OperatingMode, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, and CRYP_HandleTypeDef::State.

Referenced by CRYP_GCMCMAC_DMAInCplt(), CRYP_GCMCMAC_DMAOutCplt(), HAL_CRYPEx_AES_Auth(), and HAL_CRYPEx_AES_Auth_DMA().

static HAL_StatusTypeDef CRYP_ProcessData | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | Input,
 |  | uint16_t | Ilength,
 |  | uint8_t * | Output,
 |  | uint32_t | Timeout
 | ) |  | [static]

Write/read input/output data in polling mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Input,: Pointer to the Input buffer.
Ilength,: Length of the Input buffer in bytes, must be a multiple of 16.
Output,: Pointer to the returned buffer.
Timeout,: Specify Timeout value.
Return values:
HAL status

Definition at line 2529 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, CRYP_CCF_CLEAR, CRYP_WaitOnCCFlag(), CRYP_HandleTypeDef::CrypInCount, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_SUSPENDED, HAL_CRYP_SUSPEND, HAL_CRYP_SUSPEND_NONE, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::State, and CRYP_HandleTypeDef::SuspendRequest.

Referenced by HAL_CRYPEx_AES().

static HAL_StatusTypeDef CRYP_ReadKey | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | Output,
 |  | uint32_t | Timeout
 | ) |  | [static]

Read derivative key in polling mode when CRYP hardware block is set in key derivation operating mode (mode 2).

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Output,: Pointer to the returned buffer.
Timeout,: Specify Timeout value.
Return values:
HAL status

Definition at line 2608 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, CRYP_CCF_CLEAR, CRYP_KEYSIZE_256B, CRYP_WaitOnCCFlag(), HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_InitTypeDef::KeySize, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYPEx_AES().

static void CRYP_SetDMAConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | inputaddr,
 |  | uint16_t | Size,
 |  | uint32_t | outputaddr
 | ) |  | [static]

Set the DMA configuration and start the DMA transfer.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
inputaddr,: Address of the Input buffer.
Size,: Size of the Input buffer in bytes, must be a multiple of 16.
outputaddr,: Address of the Output buffer.
Return values:
None

Definition at line 2657 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_ENABLE, CRYP_DMAError(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), HAL_DMA_Start_IT(), CRYP_HandleTypeDef::hdmain, CRYP_HandleTypeDef::hdmaout, CRYP_HandleTypeDef::Instance, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_CRYPEx_AES_DMA().

static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Wait for Busy Flag to be reset during a GCM payload encryption process suspension.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 2718 of file stm32l4xx_hal_cryp_ex.c.

References HAL_GetTick(), and CRYP_HandleTypeDef::Instance.

Referenced by HAL_CRYPEx_AES_Auth(), and HAL_CRYPEx_Read_SuspendRegisters().

static HAL_StatusTypeDef CRYP_WaitOnCCFlag | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 2690 of file stm32l4xx_hal_cryp_ex.c.

References HAL_GetTick(), and CRYP_HandleTypeDef::Instance.

Referenced by CRYP_Padding(), CRYP_ProcessData(), CRYP_ReadKey(), HAL_CRYPEx_AES_Auth(), and HAL_CRYPEx_AES_Auth_DMA().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended callback function

Functions
Extended callback function
CRYPEx Exported Functions

Extended callback functions. More...

Functions

__weak void HAL_CRYPEx_ComputationCpltCallback (CRYP_HandleTypeDef *hcryp)
Computation completed callbacks.

Detailed Description

Extended callback functions.

 ===============================================================================
                 ##### Extended callback functions #####
 ===============================================================================
    [..]  This section provides callback function:
      (+) Computation completed.

Function Documentation

void HAL_CRYPEx_ComputationCpltCallback ( CRYP_HandleTypeDef * hcryp )

Computation completed callbacks.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 122 of file stm32l4xx_hal_cryp_ex.c.

Referenced by CRYP_AES_Auth_IT(), and CRYP_AES_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES extended processing functions

Functions
AES extended processing functions
CRYPEx Exported Functions

Extended processing functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AES (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout)
Carry out in polling mode the ciphering or deciphering operation according to hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and chaining modes ECB, CBC and CTR are managed by this function in polling mode.
HAL_StatusTypeDef | HAL_CRYPEx_AES_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
Carry out in interrupt mode the ciphering or deciphering operation according to hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and chaining modes ECB, CBC and CTR are managed by this function in interrupt mode.
HAL_StatusTypeDef | HAL_CRYPEx_AES_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
Carry out in DMA mode the ciphering or deciphering operation according to hcryp->Init structure fields.
HAL_StatusTypeDef | HAL_CRYPEx_AES_Auth (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout)
Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.
HAL_StatusTypeDef | HAL_CRYPEx_AES_Auth_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.
HAL_StatusTypeDef | HAL_CRYPEx_AES_Auth_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.

Detailed Description

Extended processing functions.

  ==============================================================================
                      ##### AES extended processing functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Encrypt plaintext or decrypt cipher text using AES algorithm in different chaining modes.
          Functions are generic (handles ECB, CBC and CTR and all modes) and are only differentiated
          based on the processing type. Three processing types are available:
          (++) Polling mode
          (++) Interrupt mode
          (++) DMA mode
      (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES
          algorithm in different chaining modes.
          Functions are generic (handles GCM, GMAC and CMAC) and process only one phase so that steps
          can be skipped if so required. Functions are only differentiated based on the processing type.
          Three processing types are available:
          (++) Polling mode
          (++) Interrupt mode
          (++) DMA mode

Function Documentation

HAL_StatusTypeDef HAL_CRYPEx_AES | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pInputData,
 |  | uint16_t | Size,
 |  | uint8_t * | pOutputData,
 |  | uint32_t | Timeout
 | ) |  |

Carry out in polling mode the ciphering or deciphering operation according to hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and chaining modes ECB, CBC and CTR are managed by this function in polling mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pInputData,: Pointer to the plain text in case of encryption or cipher text in case of decryption or key derivation+decryption. Parameter is meaningless in case of key derivation.
Size,: Length of the input data buffer in bytes, must be a multiple of 16. Parameter is meaningless in case of key derivation.
pOutputData,: Pointer to the cipher text in case of encryption or plain text in case of decryption/key derivation+decryption, or pointer to the derivative keys in case of key derivation only.
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 180 of file stm32l4xx_hal_cryp_ex.c.

References CRYP_ALGOMODE_KEYDERIVATION, CRYP_ProcessData(), CRYP_ReadKey(), HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_SUSPENDED, CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::OperatingMode, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_AESCBC_Decrypt(), HAL_CRYP_AESCBC_Encrypt(), HAL_CRYP_AESCTR_Decrypt(), HAL_CRYP_AESCTR_Encrypt(), HAL_CRYP_AESECB_Decrypt(), and HAL_CRYP_AESECB_Encrypt().

HAL_StatusTypeDef HAL_CRYPEx_AES_Auth | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pInputData,
 |  | uint64_t | Size,
 |  | uint8_t * | pOutputData,
 |  | uint32_t | Timeout
 | ) |  |

Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pInputData,:
  • pointer to payload data in GCM payload phase,
  • pointer to B0 block in CMAC header phase,
  • pointer to C block in CMAC final phase.
  • Parameter is meaningless in case of GCM/GMAC init, header and final phases.
Size,:
  • length of the input payload data buffer in bytes,
  • length of B0 block (in bytes) in CMAC header phase,
  • length of C block (in bytes) in CMAC final phase.
  • Parameter is meaningless in case of GCM/GMAC init and header phases.
pOutputData,:
  • pointer to plain or cipher text in GCM payload phase,
  • pointer to authentication tag in GCM/GMAC and CMAC final phases.
  • Parameter is meaningless in case of GCM/GMAC init and header phases and in case of CMAC header phase.
Timeout,: Specify Timeout value
Note:
Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes can be skipped by the user if so required.
Return values:
HAL status

Definition at line 437 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_BUSY_TIMEOUTVALUE, CRYP_CCF_CLEAR, CRYP_CHAINMODE_AES_CMAC, CRYP_CHAINMODE_AES_GCM_GMAC, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_32B, CRYP_DATATYPE_8B, CRYP_GCM_INIT_PHASE, CRYP_GCM_PAYLOAD_PHASE, CRYP_GCMCMAC_FINAL_PHASE, CRYP_GCMCMAC_HEADER_PHASE, CRYP_Padding(), CRYP_POLLING_ON, CRYP_WaitOnBusyFlagReset(), CRYP_WaitOnCCFlag(), CRYP_HandleTypeDef::CrypInCount, CRYP_InitTypeDef::DataType, CRYP_InitTypeDef::GCMCMACPhase, HAL_CRYP_PHASE_FINAL_OVER, HAL_CRYP_PHASE_HEADER_OVER, HAL_CRYP_PHASE_HEADER_SUSPENDED, HAL_CRYP_PHASE_INIT_OVER, HAL_CRYP_PHASE_PAYLOAD_OVER, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_ERROR, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_SUSPENDED, HAL_CRYP_SUSPEND, HAL_CRYP_SUSPEND_NONE, CRYP_InitTypeDef::Header, CRYP_InitTypeDef::HeaderSize, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_InitTypeDef::OperatingMode, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, CRYP_HandleTypeDef::State, and CRYP_HandleTypeDef::SuspendRequest.

HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pInputData,
 |  | uint64_t | Size,
 |  | uint8_t * | pOutputData
 | ) |  |

Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pInputData,:
  • pointer to payload data in GCM payload phase,
  • pointer to B0 block in CMAC header phase,
  • pointer to C block in CMAC final phase.
  • Parameter is meaningless in case of GCM/GMAC init, header and final phases.
Size,:
  • length of the input payload data buffer in bytes,
  • length of B block (in bytes) in CMAC header phase,
  • length of C block (in bytes) in CMAC final phase.
  • Parameter is meaningless in case of GCM/GMAC init and header phases.
pOutputData,:
  • pointer to plain or cipher text in GCM payload phase,
  • pointer to authentication tag in GCM/GMAC and CMAC final phases.
  • Parameter is meaningless in case of GCM/GMAC init and header phases and in case of CMAC header phase.
Note:
Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes can be skipped by the user if so required.
pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
Return values:
HAL status

Definition at line 1283 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_InitTypeDef::ChainingMode, CRYP_CCF_CLEAR, CRYP_CCF_TIMEOUTVALUE, CRYP_CHAINMODE_AES_CMAC, CRYP_CHAINMODE_AES_GCM_GMAC, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_32B, CRYP_DATATYPE_8B, CRYP_GCM_INIT_PHASE, CRYP_GCM_PAYLOAD_PHASE, CRYP_GCMCMAC_FINAL_PHASE, CRYP_GCMCMAC_HEADER_PHASE, CRYP_GCMCMAC_SetDMAConfig(), CRYP_Padding(), CRYP_POLLING_OFF, CRYP_POLLING_ON, CRYP_WaitOnCCFlag(), CRYP_HandleTypeDef::CrypInCount, CRYP_InitTypeDef::DataType, CRYP_InitTypeDef::GCMCMACPhase, HAL_CRYP_OutCpltCallback(), HAL_CRYP_PHASE_FINAL_OVER, HAL_CRYP_PHASE_HEADER_OVER, HAL_CRYP_PHASE_INIT_OVER, HAL_CRYP_PHASE_PAYLOAD_OVER, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_ERROR, HAL_CRYP_STATE_READY, CRYP_InitTypeDef::Header, CRYP_InitTypeDef::HeaderSize, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, and CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pInputData,
 |  | uint64_t | Size,
 |  | uint8_t * | pOutputData
 | ) |  |

Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pInputData,:
  • pointer to payload data in GCM payload phase,
  • pointer to B0 block in CMAC header phase,
  • pointer to C block in CMAC final phase. Parameter is meaningless in case of GCM/GMAC init, header and final phases.
Size,:
  • length of the input payload data buffer in bytes,
  • length of B0 block (in bytes) in CMAC header phase,
  • length of C block (in bytes) in CMAC final phase.
  • Parameter is meaningless in case of GCM/GMAC init and header phases.
pOutputData,:
  • pointer to plain or cipher text in GCM payload phase,
  • pointer to authentication tag in GCM/GMAC and CMAC final phases.
  • Parameter is meaningless in case of GCM/GMAC init and header phases and in case of CMAC header phase.
Note:
Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes can be skipped by the user if so required.
Return values:
HAL status

Definition at line 906 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, __HAL_CRYP_SET_CHAININGMODE, CRYP_InitTypeDef::ChainingMode, CRYP_ALGOMODE_ENCRYPT, CRYP_CHAINMODE_AES_CMAC, CRYP_CHAINMODE_AES_CTR, CRYP_CHAINMODE_AES_GCM_GMAC, CRYP_DATATYPE_16B, CRYP_DATATYPE_1B, CRYP_DATATYPE_32B, CRYP_DATATYPE_8B, CRYP_GCM_INIT_PHASE, CRYP_GCM_PAYLOAD_PHASE, CRYP_GCMCMAC_FINAL_PHASE, CRYP_GCMCMAC_HEADER_PHASE, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, CRYP_InitTypeDef::DataType, CRYP_InitTypeDef::GCMCMACPhase, HAL_CRYP_PHASE_INIT_OVER, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_ERROR, HAL_CRYP_STATE_READY, CRYP_InitTypeDef::Header, CRYP_InitTypeDef::HeaderSize, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_InitTypeDef::OperatingMode, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, CRYP_HandleTypeDef::Phase, and CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYPEx_AES_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pInputData,
 |  | uint16_t | Size,
 |  | uint8_t * | pOutputData
 | ) |  |

Carry out in DMA mode the ciphering or deciphering operation according to hcryp->Init structure fields.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pInputData,: Pointer to the plain text in case of encryption or cipher text in case of decryption or key derivation+decryption.
Size,: Length of the input data buffer in bytes, must be a multiple of 16.
pOutputData,: Pointer to the cipher text in case of encryption or plain text in case of decryption/key derivation+decryption.
Note:
Chaining modes ECB, CBC and CTR are managed by this function in DMA mode.
Supported operating modes are encryption, decryption and key derivation with decryption.
No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx registers must be done by software.
This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs.
pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
Return values:
HAL status

Definition at line 359 of file stm32l4xx_hal_cryp_ex.c.

References CRYP_ALGOMODE_KEYDERIVATION, CRYP_SetDMAConfig(), HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_InitTypeDef::OperatingMode, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_AESCBC_Decrypt_DMA(), HAL_CRYP_AESCBC_Encrypt_DMA(), HAL_CRYP_AESCTR_Decrypt_DMA(), HAL_CRYP_AESCTR_Encrypt_DMA(), HAL_CRYP_AESECB_Decrypt_DMA(), and HAL_CRYP_AESECB_Encrypt_DMA().

HAL_StatusTypeDef HAL_CRYPEx_AES_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | pInputData,
 |  | uint16_t | Size,
 |  | uint8_t * | pOutputData
 | ) |  |

Carry out in interrupt mode the ciphering or deciphering operation according to hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and chaining modes ECB, CBC and CTR are managed by this function in interrupt mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
pInputData,: Pointer to the plain text in case of encryption or cipher text in case of decryption or key derivation+decryption. Parameter is meaningless in case of key derivation.
Size,: Length of the input data buffer in bytes, must be a multiple of 16. Parameter is meaningless in case of key derivation.
pOutputData,: Pointer to the cipher text in case of encryption or plain text in case of decryption/key derivation+decryption, or pointer to the derivative keys in case of key derivation only.
Return values:
HAL status

Definition at line 260 of file stm32l4xx_hal_cryp_ex.c.

References __HAL_CRYP_ENABLE_IT, CRYP_ALGOMODE_KEYDERIVATION, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_HandleTypeDef::CrypInCount, CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Init, CRYP_HandleTypeDef::Instance, CRYP_InitTypeDef::OperatingMode, CRYP_HandleTypeDef::pCrypInBuffPtr, CRYP_HandleTypeDef::pCrypOutBuffPtr, and CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_AESCBC_Decrypt_IT(), HAL_CRYP_AESCBC_Encrypt_IT(), HAL_CRYP_AESCTR_Decrypt_IT(), HAL_CRYP_AESCTR_Encrypt_IT(), HAL_CRYP_AESECB_Decrypt_IT(), and HAL_CRYP_AESECB_Encrypt_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AES suspension/resumption functions

Functions
AES suspension/resumption functions
CRYPEx Exported Functions

Extended processing functions. More...

Functions

void | HAL_CRYPEx_Read_IVRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Output)
In case of message processing suspension, read the Initialization Vector.
void | HAL_CRYPEx_Write_IVRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Input)
In case of message processing resumption, rewrite the Initialization Vector in the AES_IVRx registers.
void | HAL_CRYPEx_Read_SuspendRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Output)
In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers.
void | HAL_CRYPEx_Write_SuspendRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Input)
In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend Registers in the AES_SUSPxR registers.
void | HAL_CRYPEx_Read_KeyRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Output, uint32_t KeySize)
In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers.
void | HAL_CRYPEx_Write_KeyRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint32_t KeySize)
In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key Registers in the AES_KEYRx registers.
void | HAL_CRYPEx_Read_ControlRegister (CRYP_HandleTypeDef *hcryp, uint8_t *Output)
In case of message GCM/GMAC or CMAC processing suspension, read the Control Register.
void | HAL_CRYPEx_Write_ControlRegister (CRYP_HandleTypeDef *hcryp, uint8_t *Input)
In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control Registers in the AES_CR register.
void | HAL_CRYPEx_ProcessSuspend (CRYP_HandleTypeDef *hcryp)
Request CRYP processing suspension when in polling or interruption mode.

Detailed Description

Extended processing functions.

  ==============================================================================
                    ##### AES extended suspension and resumption functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) save in memory the Initialization Vector, the Key registers, the Control register or
          the Suspend registers when a process is suspended by a higher priority message
      (+) write back in CRYP hardware block the saved values listed above when the suspended
          lower priority message processing is resumed.

Function Documentation

void HAL_CRYPEx_ProcessSuspend ( CRYP_HandleTypeDef * hcryp )

Request CRYP processing suspension when in polling or interruption mode.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Note:
Set the handle field SuspendRequest to the appropriate value so that the on-going CRYP processing is suspended as soon as the required conditions are met.
It is advised not to suspend the CRYP processing when the DMA controller is managing the data transfer
Return values:
None

Definition at line 1918 of file stm32l4xx_hal_cryp_ex.c.

References HAL_CRYP_SUSPEND, and CRYP_HandleTypeDef::SuspendRequest.

void HAL_CRYPEx_Read_ControlRegister | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | Output
 | ) |  |

In case of message GCM/GMAC or CMAC processing suspension, read the Control Register.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Output,: Pointer to the buffer containing the saved Control Register.
Note:
This values has to be stored for reuse by writing back the AES_CR register as soon as the interrupted processing has to be resumed.
Return values:
None

Definition at line 1885 of file stm32l4xx_hal_cryp_ex.c.

References CRYP_HandleTypeDef::Instance.

void HAL_CRYPEx_Read_IVRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | Output
 | ) |  |

In case of message processing suspension, read the Initialization Vector.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Output,: Pointer to the buffer containing the saved Initialization Vector.
Note:
This value has to be stored for reuse by writing the AES_IVRx registers as soon as the interrupted processing has to be resumed. Applicable to all chaining modes.
AES must be disabled when reading or resetting the IV values.
Return values:
None

Definition at line 1689 of file stm32l4xx_hal_cryp_ex.c.

References CRYP_HandleTypeDef::Instance.

void HAL_CRYPEx_Read_KeyRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | Output,
 |  | uint32_t | KeySize
 | ) |  |

In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Output,: Pointer to the buffer containing the saved Key Registers.
KeySize,: Indicates the key size (128 or 256 bits).
Note:
These values have to be stored for reuse by writing back the AES_KEYRx registers as soon as the interrupted processing has to be resumed.
Return values:
None

Definition at line 1815 of file stm32l4xx_hal_cryp_ex.c.

References CRYP_KEYSIZE_256B, and CRYP_HandleTypeDef::Instance.

void HAL_CRYPEx_Read_SuspendRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | Output
 | ) |  |

In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Output,: Pointer to the buffer containing the saved Suspend Registers.
Note:
These values have to be stored for reuse by writing back the AES_SUSPxR registers as soon as the interrupted processing has to be resumed.
Return values:
None

Definition at line 1736 of file stm32l4xx_hal_cryp_ex.c.

References CRYP_ALGOMODE_ENCRYPT, CRYP_BUSY_TIMEOUTVALUE, CRYP_GCM_PAYLOAD_PHASE, CRYP_WaitOnBusyFlagReset(), CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_BUSY_ERROR, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_ERROR, CRYP_HandleTypeDef::Instance, and CRYP_HandleTypeDef::State.

void HAL_CRYPEx_Write_ControlRegister | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | Input
 | ) |  |

In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control Registers in the AES_CR register.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Input,: Pointer to the buffer containing the saved Control Register to write back in the CRYP hardware block.
Return values:
None

Definition at line 1899 of file stm32l4xx_hal_cryp_ex.c.

References HAL_CRYP_STATE_READY, CRYP_HandleTypeDef::Instance, and CRYP_HandleTypeDef::State.

void HAL_CRYPEx_Write_IVRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | Input
 | ) |  |

In case of message processing resumption, rewrite the Initialization Vector in the AES_IVRx registers.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Input,: Pointer to the buffer containing the saved Initialization Vector to write back in the CRYP hardware block.
Note:
Applicable to all chaining modes.
AES must be disabled when reading or resetting the IV values.
Return values:
None

Definition at line 1713 of file stm32l4xx_hal_cryp_ex.c.

References CRYP_HandleTypeDef::Instance.

void HAL_CRYPEx_Write_KeyRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | Input,
 |  | uint32_t | KeySize
 | ) |  |

In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key Registers in the AES_KEYRx registers.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Input,: Pointer to the buffer containing the saved key registers to write back in the CRYP hardware block.
KeySize,: Indicates the key size (128 or 256 bits)
Return values:
None

Definition at line 1850 of file stm32l4xx_hal_cryp_ex.c.

References CRYP_KEYSIZE_256B, and CRYP_HandleTypeDef::Instance.

void HAL_CRYPEx_Write_SuspendRegisters | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint8_t * | Input
 | ) |  |

In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend Registers in the AES_SUSPxR registers.

Parameters:
hcryp,: pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Input,: Pointer to the buffer containing the saved suspend registers to write back in the CRYP hardware block.
Return values:
None

Definition at line 1783 of file stm32l4xx_hal_cryp_ex.c.

References CRYP_HandleTypeDef::Instance.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Private Functions

Functions
DAC Private Functions
DAC

Functions

static void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Function Documentation

static void DAC_DMAConvCpltCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1129 of file stm32l4xx_hal_dac.c.

References HAL_DAC_ConvCpltCallbackCh1(), HAL_DAC_STATE_READY, and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAErrorCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1157 of file stm32l4xx_hal_dac.c.

References DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_ErrorCallbackCh1(), HAL_DAC_STATE_READY, and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

static void DAC_DMAHalfConvCpltCh1 ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1144 of file stm32l4xx_hal_dac.c.

References HAL_DAC_ConvHalfCpltCallbackCh1().

Referenced by HAL_DAC_Start_DMA().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DAC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the DAC.
      (+) De-initialize the DAC.

Function Documentation

HAL_StatusTypeDef HAL_DAC_DeInit ( DAC_HandleTypeDef * hdac )

Deinitialize the DAC peripheral registers to their default reset values.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 364 of file stm32l4xx_hal_dac.c.

References assert_param, DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspDeInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Init ( DAC_HandleTypeDef * hdac )

Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL status

Definition at line 326 of file stm32l4xx_hal_dac.c.

References assert_param, DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_NONE, HAL_DAC_MspInit(), HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, DAC_HandleTypeDef::Lock, and DAC_HandleTypeDef::State.

void HAL_DAC_MspDeInit ( DAC_HandleTypeDef * hdac )

DeInitialize the DAC MSP.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 416 of file stm32l4xx_hal_dac.c.

Referenced by HAL_DAC_DeInit().

void HAL_DAC_MspInit ( DAC_HandleTypeDef * hdac )

Initialize the DAC MSP.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 400 of file stm32l4xx_hal_dac.c.

Referenced by HAL_DAC_Init().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
DAC Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.

Detailed Description

IO operation functions.

  ==============================================================================
             ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.

Function Documentation

void HAL_DAC_ConvCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non-blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 814 of file stm32l4xx_hal_dac.c.

Referenced by DAC_DMAConvCpltCh1().

void HAL_DAC_ConvHalfCpltCallbackCh1 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non-blocking mode for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 830 of file stm32l4xx_hal_dac.c.

Referenced by DAC_DMAHalfConvCpltCh1().

void HAL_DAC_DMAUnderrunCallbackCh1 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 862 of file stm32l4xx_hal_dac.c.

Referenced by HAL_DAC_IRQHandler().

void HAL_DAC_ErrorCallbackCh1 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel1.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 846 of file stm32l4xx_hal_dac.c.

Referenced by DAC_DMAErrorCh1().

void HAL_DAC_IRQHandler ( DAC_HandleTypeDef * hdac )

Handles DAC interrupt request This function uses the interruption of DMA underrun.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 720 of file stm32l4xx_hal_dac.c.

References __HAL_DAC_CLEAR_FLAG, __HAL_DAC_GET_FLAG, __HAL_DAC_GET_IT_SOURCE, DAC_FLAG_DMAUDR1, DAC_FLAG_DMAUDR2, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, DAC_HandleTypeDef::ErrorCode, HAL_DAC_DMAUnderrunCallbackCh1(), HAL_DAC_ERROR_DMAUNDERRUNCH1, HAL_DAC_ERROR_DMAUNDERRUNCH2, HAL_DAC_STATE_ERROR, HAL_DACEx_DMAUnderrunCallbackCh2(), DAC_HandleTypeDef::Instance, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_SetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data
 | ) |  |

Set the specified data holding register value for DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Alignment,: Specifies the data alignment. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Data,: Data to be loaded in the selected data holding register.
Return values:
HAL status

Definition at line 782 of file stm32l4xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, and IS_DAC_DATA.

HAL_StatusTypeDef HAL_DAC_Start | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 458 of file stm32l4xx_hal_dac.c.

References __HAL_DAC_ENABLE, assert_param, DAC_CHANNEL_1, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Start_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint32_t | Length,
 |  | uint32_t | Alignment
 | ) |  |

Enables DAC and starts conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
pData,: The destination peripheral Buffer address.
Length,: The length of data to be transferred from memory to DAC peripheral
Alignment,: Specifies the data alignment for DAC channel. This parameter can be one of the following values:
  • DAC_ALIGN_8B_R: 8bit right data alignment selected
  • DAC_ALIGN_12B_L: 12bit left data alignment selected
  • DAC_ALIGN_12B_R: 12bit right data alignment selected
Return values:
HAL status

Definition at line 543 of file stm32l4xx_hal_dac.c.

References __HAL_DAC_ENABLE, __HAL_DAC_ENABLE_IT, assert_param, DAC_ALIGN_12B_L, DAC_ALIGN_12B_R, DAC_ALIGN_8B_R, DAC_CHANNEL_1, DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), DAC_DMAHalfConvCpltCh1(), DAC_DMAHalfConvCpltCh2(), DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, DAC_HandleTypeDef::DMA_Handle1, DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_BUSY, HAL_DMA_Start_IT(), DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, IS_DAC_CHANNEL, DAC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DAC_Stop | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 511 of file stm32l4xx_hal_dac.c.

References __HAL_DAC_DISABLE, assert_param, HAL_DAC_STATE_READY, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DAC_Stop_DMA | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Disables DAC and stop conversion of channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 662 of file stm32l4xx_hal_dac.c.

References __HAL_DAC_DISABLE, __HAL_DAC_DISABLE_IT, assert_param, DAC_CHANNEL_1, DAC_IT_DMAUDR1, DAC_IT_DMAUDR2, DAC_HandleTypeDef::DMA_Handle1, DAC_HandleTypeDef::DMA_Handle2, HAL_DAC_STATE_ERROR, HAL_DAC_STATE_READY, HAL_DMA_Abort(), DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DAC Exported Functions

Peripheral Control functions. More...

Functions

uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.

Detailed Description

Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels.
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

HAL_StatusTypeDef HAL_DAC_ConfigChannel | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig,: DAC configuration structure.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
HAL status

Definition at line 928 of file stm32l4xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_ChannelConfTypeDef::DAC_ConnectOnChipPeripheral, DAC_SampleAndHoldConfTypeDef::DAC_HoldTime, DAC_ChannelConfTypeDef::DAC_OutputBuffer, DAC_SampleAndHoldConfTypeDef::DAC_RefreshTime, DAC_ChannelConfTypeDef::DAC_SampleAndHold, DAC_SAMPLEANDHOLD_ENABLE, DAC_ChannelConfTypeDef::DAC_SampleAndHoldConfig, DAC_SampleAndHoldConfTypeDef::DAC_SampleTime, DAC_ChannelConfTypeDef::DAC_Trigger, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_TIMEOUT, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, HAL_DAC_STATE_TIMEOUT, HAL_Delay(), HAL_GetTick(), DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_CHIP_CONNECTION, IS_DAC_HOLDTIME, IS_DAC_OUTPUT_BUFFER_STATE, IS_DAC_REFRESHTIME, IS_DAC_SAMPLEANDHOLD, IS_DAC_SAMPLETIME, IS_DAC_TRIGGER, IS_DAC_TRIMMING, IS_DAC_TRIMMINGVALUE, DAC_HandleTypeDef::State, and TIMEOUT_DAC_CALIBCONFIG.

uint32_t HAL_DAC_GetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Returns the last data output value of the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
The selected DAC channel data output value.

Definition at line 901 of file stm32l4xx_hal_dac.c.

References assert_param, DAC_CHANNEL_1, DAC_HandleTypeDef::Instance, and IS_DAC_CHANNEL.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DAC Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

Peripheral State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Errors functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DAC state.
      (+) Check the DAC Errors.

Function Documentation

uint32_t HAL_DAC_GetError ( DAC_HandleTypeDef * hdac )

Return the DAC error code.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
DAC Error Code

Definition at line 1106 of file stm32l4xx_hal_dac.c.

References DAC_HandleTypeDef::ErrorCode.

HAL_DAC_StateTypeDef HAL_DAC_GetState ( DAC_HandleTypeDef * hdac )

return the DAC handle state

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
HAL state

Definition at line 1093 of file stm32l4xx_hal_dac.c.

References DAC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Exported Types

Data Structures | Enumerations
DAC Exported Types
DAC

Data Structures

struct | DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_SampleAndHoldConfTypeDef
DAC Configuration sample and hold Channel structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00, HAL_DAC_STATE_READY = 0x01, HAL_DAC_STATE_BUSY = 0x02, HAL_DAC_STATE_TIMEOUT = 0x03,
HAL_DAC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_DAC_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_DAC_STATE_RESET

DAC not yet initialized or disabled

HAL_DAC_STATE_READY

DAC initialized and ready for use

HAL_DAC_STATE_BUSY

DAC internal processing is ongoing

HAL_DAC_STATE_TIMEOUT

DAC timeout state

HAL_DAC_STATE_ERROR

DAC error state

Definition at line 67 of file stm32l4xx_hal_dac.h.

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STM32L486xx HAL User Manual: DAC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_HandleTypeDef Struct Reference
DAC Exported Types

DAC handle Structure definition. More...

#include <stm32l4xx_hal_dac.h>

Data Fields

DAC_TypeDef * | Instance
__IO HAL_DAC_StateTypeDef | State
HAL_LockTypeDef | Lock
DMA_HandleTypeDef * DMA_Handle1
DMA_HandleTypeDef * DMA_Handle2
__IO uint32_t | ErrorCode

Detailed Description

DAC handle Structure definition.

Definition at line 80 of file stm32l4xx_hal_dac.h.

Field Documentation

DMA_HandleTypeDef* DAC_HandleTypeDef::DMA_Handle1

Pointer DMA handler for channel 1

Definition at line 88 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

DMA_HandleTypeDef* DAC_HandleTypeDef::DMA_Handle2

Pointer DMA handler for channel 2

Definition at line 90 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

__IO uint32_t DAC_HandleTypeDef::ErrorCode

DAC Error code

Definition at line 92 of file stm32l4xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetError(), HAL_DAC_Init(), and HAL_DAC_IRQHandler().

DAC_TypeDef* DAC_HandleTypeDef::Instance

Register base address

Definition at line 82 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualGetValue(), HAL_DACEx_DualSetValue(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), and HAL_DACEx_TriangleWaveGenerate().

HAL_LockTypeDef DAC_HandleTypeDef::Lock

DAC locking object

Definition at line 86 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_Init().

__IO HAL_DAC_StateTypeDef DAC_HandleTypeDef::State

DAC communication state

Definition at line 84 of file stm32l4xx_hal_dac.h.

Referenced by DAC_DMAConvCpltCh1(), DAC_DMAConvCpltCh2(), DAC_DMAErrorCh1(), DAC_DMAErrorCh2(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetState(), HAL_DAC_Init(), HAL_DAC_IRQHandler(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_TriangleWaveGenerate().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dac.h
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STM32L486xx HAL User Manual: DAC_SampleAndHoldConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_SampleAndHoldConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration sample and hold Channel structure definition. More...

#include <stm32l4xx_hal_dac.h>

Data Fields

uint32_t | DAC_SampleTime
uint32_t | DAC_HoldTime
uint32_t | DAC_RefreshTime

Detailed Description

DAC Configuration sample and hold Channel structure definition.

Definition at line 99 of file stm32l4xx_hal_dac.h.

Field Documentation

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_HoldTime

Specifies the hold time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023

Definition at line 105 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_RefreshTime

Specifies the refresh time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 255

Definition at line 109 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_SampleAndHoldConfTypeDef::DAC_SampleTime

Specifies the Sample time for the selected channel. This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023

Definition at line 101 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dac.h
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STM32L486xx HAL User Manual: DAC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DAC_ChannelConfTypeDef Struct Reference
DAC Exported Types

DAC Configuration regular Channel structure definition. More...

#include <stm32l4xx_hal_dac.h>

Data Fields

uint32_t | DAC_SampleAndHold
uint32_t | DAC_Trigger
uint32_t | DAC_OutputBuffer
uint32_t | DAC_ConnectOnChipPeripheral
uint32_t | DAC_UserTrimming
uint32_t | DAC_TrimmingValue
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig

Detailed Description

DAC Configuration regular Channel structure definition.

Definition at line 118 of file stm32l4xx_hal_dac.h.

Field Documentation

uint32_t DAC_ChannelConfTypeDef::DAC_ConnectOnChipPeripheral

Specifies whether the DAC output is connected or not to on chip peripheral . This parameter can be a value of DAC ConnectOnChipPeripheral

Definition at line 129 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_OutputBuffer

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC output buffer

Definition at line 126 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_SampleAndHold

Specifies whether the DAC mode. This parameter can be a value of DAC power mode

Definition at line 120 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

DAC_SampleAndHoldConfTypeDef DAC_ChannelConfTypeDef::DAC_SampleAndHoldConfig

Sample and Hold settings

Definition at line 140 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_Trigger

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DAC trigger selection

Definition at line 123 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

uint32_t DAC_ChannelConfTypeDef::DAC_TrimmingValue

Specifies the offset trimming value i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 136 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

uint32_t DAC_ChannelConfTypeDef::DAC_UserTrimming

Specifies the trimming mode This parameter must be a value of DAC User Trimming DAC_UserTrimming is either factory or user trimming

Definition at line 132 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dac.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Error Code

Defines
DAC Error Code
DAC Exported Constants

Defines

#define | HAL_DAC_ERROR_NONE 0x00
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02
#define | HAL_DAC_ERROR_DMA 0x04
#define | HAL_DAC_ERROR_TIMEOUT 0x08

Define Documentation

#define HAL_DAC_ERROR_DMA 0x04

DMA error

Definition at line 160 of file stm32l4xx_hal_dac.h.

Referenced by DAC_DMAErrorCh1(), and DAC_DMAErrorCh2().

#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01

DAC channel1 DMA underrun error

Definition at line 158 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02

DAC channel2 DMA underrun error

Definition at line 159 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define HAL_DAC_ERROR_NONE 0x00

No error

Definition at line 157 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_DeInit(), and HAL_DAC_Init().

#define HAL_DAC_ERROR_TIMEOUT 0x08

Timeout error

Definition at line 161 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

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STM32L486xx HAL User Manual: DAC trigger selection

Defines
DAC trigger selection
DAC Exported Constants

Defines

#define | DAC_TRIGGER_NONE ((uint32_t)0x00000000)
#define | DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))

Define Documentation

#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))

EXTI Line9 event selected as external conversion trigger for DAC channel

Definition at line 189 of file stm32l4xx_hal_dac.h.

#define DAC_TRIGGER_NONE ((uint32_t)0x00000000)

Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger

Definition at line 181 of file stm32l4xx_hal_dac.h.

#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))

Conversion started by software trigger for DAC channel

Definition at line 190 of file stm32l4xx_hal_dac.h.

#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))

TIM2 TRGO selected as external conversion trigger for DAC channel

Definition at line 183 of file stm32l4xx_hal_dac.h.

#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM4 TRGO selected as external conversion trigger for DAC channel

Definition at line 184 of file stm32l4xx_hal_dac.h.

#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM5 TRGO selected as external conversion trigger for DAC channel

Definition at line 185 of file stm32l4xx_hal_dac.h.

#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)

TIM6 TRGO selected as external conversion trigger for DAC channel

Definition at line 186 of file stm32l4xx_hal_dac.h.

#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))

TIM7 TRGO selected as external conversion trigger for DAC channel

Definition at line 187 of file stm32l4xx_hal_dac.h.

#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))

TIM8 TRGO selected as external conversion trigger for DAC channel

Definition at line 188 of file stm32l4xx_hal_dac.h.

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STM32L486xx HAL User Manual: DAC output buffer

Defines
DAC output buffer
DAC Exported Constants

Defines

#define | DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define | DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1)

Define Documentation

#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1)

Definition at line 201 of file stm32l4xx_hal_dac.h.

#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)

Definition at line 200 of file stm32l4xx_hal_dac.h.

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STM32L486xx HAL User Manual: DAC Channel selection

Defines
DAC Channel selection
DAC Exported Constants

Defines

#define | DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define | DAC_CHANNEL_2 ((uint32_t)0x00000010)

Define Documentation

#define DAC_CHANNEL_1 ((uint32_t)0x00000000)

Definition at line 210 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA(), and HAL_DACEx_SelfCalibrate().

#define DAC_CHANNEL_2 ((uint32_t)0x00000010)

Definition at line 211 of file stm32l4xx_hal_dac.h.

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STM32L486xx HAL User Manual: DAC data alignment

Defines
DAC data alignment
DAC Exported Constants

Defines

#define | DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define | DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define | DAC_ALIGN_8B_R ((uint32_t)0x00000008)

Define Documentation

#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)

Definition at line 221 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)

Definition at line 220 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_SelfCalibrate().

#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)

Definition at line 222 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

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STM32L486xx HAL User Manual: DAC flags definition

Defines
DAC flags definition
DAC Exported Constants

Defines

#define | DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Define Documentation

#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)

Definition at line 231 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Definition at line 232 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

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STM32L486xx HAL User Manual: DAC IT definition

Defines
DAC IT definition
DAC Exported Constants

Defines

#define | DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Define Documentation

#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)

Definition at line 241 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)

Definition at line 242 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler(), HAL_DAC_Start_DMA(), and HAL_DAC_Stop_DMA().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC ConnectOnChipPeripheral

Defines
DAC ConnectOnChipPeripheral
DAC Exported Constants

Defines

#define | DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000)
#define | DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0)

Define Documentation

#define DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000)

Definition at line 251 of file stm32l4xx_hal_dac.h.

#define DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0)

Definition at line 252 of file stm32l4xx_hal_dac.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC User Trimming

Defines
DAC User Trimming
DAC Exported Constants

Defines

#define | DAC_TRIMMING_FACTORY ((uint32_t)0x00000000)
#define | DAC_TRIMMING_USER ((uint32_t)0x00000001)

Define Documentation

#define DAC_TRIMMING_FACTORY ((uint32_t)0x00000000)

Factory trimming

Definition at line 262 of file stm32l4xx_hal_dac.h.

#define DAC_TRIMMING_USER ((uint32_t)0x00000001)

User trimming

Definition at line 263 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DACEx_SelfCalibrate(), and HAL_DACEx_SetUserTrimming().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC power mode

Defines
DAC power mode
DAC Exported Constants

Defines

#define | DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000)
#define | DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2)

Define Documentation

#define DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000)

Definition at line 272 of file stm32l4xx_hal_dac.h.

#define DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2)

Definition at line 273 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Exported Macros

Defines
DAC Exported Macros
DAC

Defines

#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.

Define Documentation

#define __HAL_DAC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = (__FLAG__))

Clear the DAC's flag.

Parameters:
__HANDLE__,: specifies the DAC handle.
__FLAG__,: specifies the DAC flag to clear. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
Return values:
None

Definition at line 377 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_DISABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))

Disable the DAC channel.

Parameters:
__HANDLE__,: specifies the DAC handle
__DAC_Channel__,: specifies the DAC channel.
Return values:
None

Definition at line 308 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_Stop(), and HAL_DAC_Stop_DMA().

#define __HAL_DAC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the DAC interrupt.

Parameters:
__HANDLE__,: specifies the DAC handle
__INTERRUPT__,: specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
None

Definition at line 347 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_Stop_DMA().

#define __HAL_DAC_ENABLE | ( | __HANDLE__,
 |  | __DAC_Channel__
 | ) | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))

Enable the DAC channel.

Parameters:
__HANDLE__,: specifies the DAC handle.
__DAC_Channel__,: specifies the DAC channel
Return values:
None

Definition at line 300 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_Start(), and HAL_DAC_Start_DMA().

#define __HAL_DAC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the DAC interrupt.

Parameters:
__HANDLE__,: specifies the DAC handle
__INTERRUPT__,: specifies the DAC interrupt. This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
None

Definition at line 337 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_Start_DMA().

#define __HAL_DAC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected DAC's flag status.

Parameters:
__HANDLE__,: specifies the DAC handle.
__FLAG__,: specifies the DAC flag to get. This parameter can be any combination of the following values:
  • DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
  • DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
Return values:
None

Definition at line 367 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified DAC interrupt source is enabled or not.

Parameters:
__HANDLE__,: DAC handle
__INTERRUPT__,: DAC interrupt source to check This parameter can be any combination of the following values:
  • DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
  • DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
Return values:
State of interruption (SET or RESET)

Definition at line 357 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_IRQHandler().

#define __HAL_DAC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)

Reset DAC handle state.

Parameters:
__HANDLE__,: specifies the DAC handle.
Return values:
None

Definition at line 293 of file stm32l4xx_hal_dac.h.

#define DAC_DHR12R1_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000008) + (__ALIGNMENT__))

Set DHR12R1 alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 315 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_SelfCalibrate().

#define DAC_DHR12R2_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000014) + (__ALIGNMENT__))

Set DHR12R2 alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 321 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_SelfCalibrate().

#define DAC_DHR12RD_ALIGNMENT ( __ALIGNMENT__ ) (((uint32_t)0x00000020) + (__ALIGNMENT__))

Set DHR12RD alignment.

Parameters:
__ALIGNMENT__,: specifies the DAC alignment
Return values:
None

Definition at line 327 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DACEx_DualSetValue().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Private Macros

Defines
DAC Private Macros
DAC

Defines

#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define | IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x0000000FF)

Define Documentation

#define IS_DAC_ALIGN ( ALIGN )
Value:
(((ALIGN) == DAC_ALIGN_12B_R) || \
                             ((ALIGN) == DAC_ALIGN_12B_L) || \
                             ((ALIGN) == DAC_ALIGN_8B_R))

Definition at line 394 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), HAL_DAC_Start_DMA(), and HAL_DACEx_DualSetValue().

#define IS_DAC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DAC_CHANNEL_1) || \
                                ((CHANNEL) == DAC_CHANNEL_2))

Definition at line 391 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel(), HAL_DAC_GetValue(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_DATA ( DATA ) ((DATA) <= 0xFFF0)

Definition at line 398 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_SetValue(), and HAL_DACEx_DualSetValue().

#define IS_DAC_OUTPUT_BUFFER_STATE ( STATE )
Value:
(((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))

Definition at line 388 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_REFRESHTIME ( TIME ) ((TIME) <= 0x0000000FF)

Definition at line 400 of file stm32l4xx_hal_dac.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Private Constants

Defines
DAC Private Constants
DAC

Defines

#define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1ms */

Define Documentation

#define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1ms */

Definition at line 280 of file stm32l4xx_hal_dac.c.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
DACEx Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.

Detailed Description

Extended IO operation functions.

  ==============================================================================
                 ##### Extended features functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion.
      (+) Stop conversion.
      (+) Start conversion and enable DMA transfer.
      (+) Stop conversion and disable DMA transfer.
      (+) Get result of conversion.
      (+) Get result of dual mode conversion.

Function Documentation

void HAL_DACEx_ConvCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion complete callback in non-blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 253 of file stm32l4xx_hal_dac_ex.c.

Referenced by DAC_DMAConvCpltCh2().

void HAL_DACEx_ConvHalfCpltCallbackCh2 ( DAC_HandleTypeDef * hdac )

Conversion half DMA transfer callback in non-blocking mode for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 269 of file stm32l4xx_hal_dac_ex.c.

Referenced by DAC_DMAHalfConvCpltCh2().

void HAL_DACEx_DMAUnderrunCallbackCh2 ( DAC_HandleTypeDef * hdac )

DMA underrun DAC callback for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 301 of file stm32l4xx_hal_dac_ex.c.

Referenced by HAL_DAC_IRQHandler().

HAL_StatusTypeDef HAL_DACEx_DualSetValue | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Alignment,
 |  | uint32_t | Data1,
 |  | uint32_t | Data2
 | ) |  |

Set the specified data holding register value for dual DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Alignment,: Specifies the data alignment for dual channel DAC. This parameter can be one of the following values: DAC_ALIGN_8B_R: 8bit right data alignment selected DAC_ALIGN_12B_L: 12bit left data alignment selected DAC_ALIGN_12B_R: 12bit right data alignment selected
Data1,: Data for DAC Channel2 to be loaded in the selected data holding register.
Data2,: Data for DAC Channel1 to be loaded in the selected data holding register.
Note:
In dual mode, a unique register access is required to write in both DAC channels at the same time.
Return values:
HAL status

Definition at line 218 of file stm32l4xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_8B_R, DAC_DHR12RD_ALIGNMENT, DAC_HandleTypeDef::Instance, IS_DAC_ALIGN, and IS_DAC_DATA.

void HAL_DACEx_ErrorCallbackCh2 ( DAC_HandleTypeDef * hdac )

Error DAC callback for Channel2.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
None

Definition at line 285 of file stm32l4xx_hal_dac_ex.c.

Referenced by DAC_DMAErrorCh2().

uint32_t HAL_DACEx_GetTrimOffset | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the DAC trimming value.

Parameters:
hdac : DAC handle
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Trimming value : range: 0->31

Definition at line 488 of file stm32l4xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enable or disable the selected DAC channel wave generation.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values: DAC_CHANNEL_1 / DAC_CHANNEL_2
Amplitude,: Unmask DAC channel LFSR for noise wave generation. This parameter can be one of the following values:
  • DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
  • DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
  • DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
Return values:
HAL status

Definition at line 176 of file stm32l4xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SelfCalibrate | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Run the self calibration of one DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig,: DAC channel configuration structure.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Updates | DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
HAL | status
Note:
Calibration runs about 7 ms.

Definition at line 325 of file stm32l4xx_hal_dac_ex.c.

References assert_param, DAC_ALIGN_12B_R, DAC_CHANNEL_1, DAC_DHR12R1_ALIGNMENT, DAC_DHR12R2_ALIGNMENT, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, HAL_DAC_STATE_BUSY, HAL_Delay(), DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DACEx_SetUserTrimming | ( | DAC_HandleTypeDef * | hdac,
 |  | DAC_ChannelConfTypeDef * | sConfig,
 |  | uint32_t | Channel,
 |  | uint32_t | NewTrimmingValue
 | ) |  |

Set the trimming mode and trimming value (user trimming mode applied).

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
sConfig,: DAC configuration structure updated with new DAC trimming value.
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
NewTrimmingValue,: DAC new trimming value
Return values:
HAL status

Definition at line 447 of file stm32l4xx_hal_dac_ex.c.

References assert_param, DAC_TRIMMING_USER, DAC_ChannelConfTypeDef::DAC_TrimmingValue, DAC_ChannelConfTypeDef::DAC_UserTrimming, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and IS_DAC_NEWTRIMMINGVALUE.

HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel,
 |  | uint32_t | Amplitude
 | ) |  |

Enable or disable the selected DAC channel wave generation.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Channel,: The selected DAC channel. This parameter can be one of the following values: DAC_CHANNEL_1 / DAC_CHANNEL_2
Amplitude,: Select max triangle amplitude. This parameter can be one of the following values:
  • DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
  • DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
  • DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
  • DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
  • DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
  • DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
  • DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
  • DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
  • DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
  • DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
  • DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
  • DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
Return values:
HAL status

Definition at line 128 of file stm32l4xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_BUSY, HAL_DAC_STATE_READY, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE, and DAC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
DACEx Exported Functions

Extended Peripheral Control functions. More...

Functions

uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.

Detailed Description

Extended Peripheral Control functions.

  ==============================================================================
             ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels.
      (+) Set the specified data holding register value for DAC channel.

Function Documentation

uint32_t HAL_DACEx_DualGetValue ( DAC_HandleTypeDef * hdac )

Return the last data output value of the selected DAC channel.

Parameters:
hdac,: pointer to a DAC_HandleTypeDef structure that contains the configuration information for the specified DAC.
Return values:
The selected DAC channel data output value.

Definition at line 534 of file stm32l4xx_hal_dac_ex.c.

References DAC_HandleTypeDef::Instance.

uint32_t HAL_DACEx_GetTrimOffset | ( | DAC_HandleTypeDef * | hdac,
 |  | uint32_t | Channel
 | ) |  |

Return the DAC trimming value.

Parameters:
hdac : DAC handle
Channel,: The selected DAC channel. This parameter can be one of the following values:
  • DAC_CHANNEL_1: DAC Channel1 selected
  • DAC_CHANNEL_2: DAC Channel2 selected
Return values:
Trimming value : range: 0->31

Definition at line 488 of file stm32l4xx_hal_dac_ex.c.

References assert_param, HAL_DAC_STATE_RESET, DAC_HandleTypeDef::Instance, IS_DAC_CHANNEL, and DAC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DACEx private functions

Functions
DACEx private functions
DACEx

Extended private functions. More...

Functions

void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Extended private functions.

Function Documentation

void DAC_DMAConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA conversion complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 566 of file stm32l4xx_hal_dac_ex.c.

References HAL_DAC_STATE_READY, HAL_DACEx_ConvCpltCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAErrorCh2 ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 594 of file stm32l4xx_hal_dac_ex.c.

References DAC_HandleTypeDef::ErrorCode, HAL_DAC_ERROR_DMA, HAL_DAC_STATE_READY, HAL_DACEx_ErrorCallbackCh2(), and DAC_HandleTypeDef::State.

Referenced by HAL_DAC_Start_DMA().

void DAC_DMAHalfConvCpltCh2 ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 581 of file stm32l4xx_hal_dac_ex.c.

References HAL_DACEx_ConvHalfCpltCallbackCh2().

Referenced by HAL_DAC_Start_DMA().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DACEx lfsrunmask triangleamplitude

Defines
DACEx lfsrunmask triangleamplitude
DACEx Exported Constants

Defines

#define | DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000)
#define | DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000)
#define | DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Define Documentation

#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000)

Unmask DAC channel LFSR bit0 for noise wave generation

Definition at line 72 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[10:0] for noise wave generation

Definition at line 82 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[11:0] for noise wave generation

Definition at line 83 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[1:0] for noise wave generation

Definition at line 73 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[2:0] for noise wave generation

Definition at line 74 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[3:0] for noise wave generation

Definition at line 75 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)

Unmask DAC channel LFSR bit[4:0] for noise wave generation

Definition at line 76 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[5:0] for noise wave generation

Definition at line 77 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)

Unmask DAC channel LFSR bit[6:0] for noise wave generation

Definition at line 78 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[7:0] for noise wave generation

Definition at line 79 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)

Unmask DAC channel LFSR bit[8:0] for noise wave generation

Definition at line 80 of file stm32l4xx_hal_dac_ex.h.

#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Unmask DAC channel LFSR bit[9:0] for noise wave generation

Definition at line 81 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000)

Select max triangle amplitude of 1

Definition at line 84 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 1023

Definition at line 93 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)

Select max triangle amplitude of 127

Definition at line 90 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 15

Definition at line 87 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)

Select max triangle amplitude of 2047

Definition at line 94 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 255

Definition at line 91 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)

Select max triangle amplitude of 3

Definition at line 85 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)

Select max triangle amplitude of 31

Definition at line 88 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 4095

Definition at line 95 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)

Select max triangle amplitude of 511

Definition at line 92 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)

Select max triangle amplitude of 63

Definition at line 89 of file stm32l4xx_hal_dac_ex.h.

#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)

Select max triangle amplitude of 7

Definition at line 86 of file stm32l4xx_hal_dac_ex.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DACEx Private Macros

Defines
DACEx Private Macros
DACEx

Defines

#define | IS_DAC_TRIGGER(TRIGGER)
#define | IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
#define | IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x0000003FF)
#define | IS_DAC_SAMPLEANDHOLD(MODE)
#define | IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_DAC_CHIP_CONNECTION(CONNECT)
#define | IS_DAC_TRIMMING(TRIMMING)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Define Documentation

#define IS_DAC_CHIP_CONNECTION ( CONNECT )
Value:
(((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
                                         ((CONNECT) == DAC_CHIPCONNECT_ENABLE))

Definition at line 146 of file stm32l4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_HOLDTIME ( TIME ) ((TIME) <= 0x0000003FF)

Definition at line 136 of file stm32l4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE ( VALUE )
Value:
(((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))

Definition at line 152 of file stm32l4xx_hal_dac_ex.h.

Referenced by HAL_DACEx_NoiseWaveGenerate(), and HAL_DACEx_TriangleWaveGenerate().

#define IS_DAC_NEWTRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1F)

Definition at line 144 of file stm32l4xx_hal_dac_ex.h.

Referenced by HAL_DACEx_SetUserTrimming().

#define IS_DAC_SAMPLEANDHOLD ( MODE )
Value:
(((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))

Definition at line 138 of file stm32l4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_SAMPLETIME ( TIME ) ((TIME) <= 0x0000003FF)

Definition at line 134 of file stm32l4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == DAC_TRIGGER_NONE) || \
                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))

Definition at line 123 of file stm32l4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == DAC_TRIMMING_FACTORY) || \
                                     ((TRIMMING) == DAC_TRIMMING_USER))

Definition at line 149 of file stm32l4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

#define IS_DAC_TRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1F)

Definition at line 142 of file stm32l4xx_hal_dac_ex.h.

Referenced by HAL_DAC_ConfigChannel().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM Private Define

Defines
DFSDM Private Define
DFSDM

Defines

#define | DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
#define | DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
#define | DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
#define | DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
#define | DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
#define | DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)
#define | DFSDM_FLTCR1_MSB_RCH_OFFSET 8
#define | DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)
#define | DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)
#define | DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)
#define | DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)
#define | DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
#define | DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)
#define | DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
#define | DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
#define | DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
#define | DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
#define | DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
#define | DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
#define | DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
#define | DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
#define | DFSDM_MSB_MASK 0xFFFF0000U
#define | DFSDM_LSB_MASK 0x0000FFFFU
#define | DFSDM_CKAB_TIMEOUT 5000U
#define | DFSDM1_CHANNEL_NUMBER 8U

Define Documentation

#define DFSDM1_CHANNEL_NUMBER 8U

Definition at line 233 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)

Definition at line 210 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelScdStart(), and HAL_DFSDM_ChannelScdStart_IT().

#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)

Definition at line 211 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelInit().

#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)

Definition at line 209 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelInit().

#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)

Definition at line 213 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelInit().

#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)

Definition at line 212 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelInit(), and HAL_DFSDM_ChannelModifyOffset().

#define DFSDM_CKAB_TIMEOUT 5000U

Definition at line 232 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelCkabStart(), and HAL_DFSDM_ChannelCkabStart_IT().

#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)

Definition at line 224 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)

Definition at line 225 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)

Definition at line 229 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)

Definition at line 228 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterGetConvTimeValue().

#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8

Definition at line 215 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)

Definition at line 217 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)

Definition at line 216 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterExdStart().

#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)

Definition at line 226 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterGetExdMaxValue().

#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)

Definition at line 227 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterGetExdMinValue().

#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)

Definition at line 214 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterInit().

#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)

Definition at line 220 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelPollForCkab(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)

Definition at line 221 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStop(), HAL_DFSDM_ChannelScdStop_IT(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)

Definition at line 218 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelPollForCkab(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)

Definition at line 219 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelPollForScd(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)

Definition at line 223 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterGetInjectedValue().

#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)

Definition at line 222 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterGetRegularValue().

#define DFSDM_LSB_MASK 0x0000FFFFU

Definition at line 231 of file stm32l4xx_hal_dfsdm.c.

Referenced by DFSDM_GetInjChannelsNbr(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterConfigInjChannel(), and HAL_DFSDM_FilterExdStart().

#define DFSDM_MSB_MASK 0xFFFF0000U

Definition at line 230 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM Private Variables

Variables
DFSDM Private Variables
DFSDM

Variables

__IO uint32_t | v_dfsdm1ChannelCounter = 0
DFSDM_Channel_HandleTypeDef * | a_dfsdm1ChannelHandle [DFSDM1_CHANNEL_NUMBER] = {NULL}

Variable Documentation

DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL}

Definition at line 244 of file stm32l4xx_hal_dfsdm.c.

__IO uint32_t v_dfsdm1ChannelCounter = 0

Definition at line 243 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelDeInit(), and HAL_DFSDM_ChannelInit().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM Private Functions

Functions
DFSDM Private Functions
DFSDM

Functions

static uint32_t | DFSDM_GetInjChannelsNbr (uint32_t Channels)
This function allows to get the number of injected channels.
static uint32_t | DFSDM_GetChannelFromInstance (DFSDM_Channel_TypeDef *Instance)
This function allows to get the channel number from channel instance.
static void | DFSDM_RegConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start regular conversion.
static void | DFSDM_RegConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop regular conversion.
static void | DFSDM_InjConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start injected conversion.
static void | DFSDM_InjConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop injected conversion.
static void | DFSDM_DMARegularHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for regular conversion.
static void | DFSDM_DMARegularConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for regular conversion.
static void | DFSDM_DMAInjectedHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for injected conversion.
static void | DFSDM_DMAInjectedConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for injected conversion.
static void | DFSDM_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

static void DFSDM_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA error callback.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2762 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_FILTER_ERROR_DMA, DFSDM_Filter_HandleTypeDef::ErrorCode, and HAL_DFSDM_FilterErrorCallback().

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

static void DFSDM_DMAInjectedConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback for injected conversion.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2748 of file stm32l4xx_hal_dfsdm.c.

References HAL_DFSDM_FilterInjConvCpltCallback().

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), and HAL_DFSDM_FilterInjectedStart_DMA().

static void DFSDM_DMAInjectedHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback for injected conversion.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2734 of file stm32l4xx_hal_dfsdm.c.

References HAL_DFSDM_FilterInjConvHalfCpltCallback().

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), and HAL_DFSDM_FilterInjectedStart_DMA().

static void DFSDM_DMARegularConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA transfer complete callback for regular conversion.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2720 of file stm32l4xx_hal_dfsdm.c.

References HAL_DFSDM_FilterRegConvCpltCallback().

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

static void DFSDM_DMARegularHalfConvCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA half transfer complete callback for regular conversion.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 2706 of file stm32l4xx_hal_dfsdm.c.

References HAL_DFSDM_FilterRegConvHalfCpltCallback().

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

static uint32_t DFSDM_GetChannelFromInstance ( DFSDM_Channel_TypeDef * Instance ) [static]

This function allows to get the channel number from channel instance.

Parameters:
Instance : DFSDM channel instance.
Return values:
Channel number.

Definition at line 2802 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStop(), and HAL_DFSDM_ChannelScdStop_IT().

static uint32_t DFSDM_GetInjChannelsNbr ( uint32_t Channels ) [static]

This function allows to get the number of injected channels.

Parameters:
Channels : bitfield of injected channels.
Return values:
Number of injected channels.

Definition at line 2779 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_LSB_MASK.

Referenced by HAL_DFSDM_FilterConfigInjChannel().

static void DFSDM_InjConvStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really start injected conversion.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2925 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_FILTER_SW_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, DFSDM_Filter_HandleTypeDef::ExtTriggerEdge, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), and HAL_DFSDM_FilterInjectedStart_IT().

static void DFSDM_InjConvStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really stop injected conversion.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2969 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_FILTER_EXT_TRIGGER, DFSDM_FILTER_SW_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), and HAL_DFSDM_FilterInjectedStop_IT().

static void DFSDM_RegConvStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really start regular conversion.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2848 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_FILTER_SW_TRIGGER, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_FilterRegularStart_IT().

static void DFSDM_RegConvStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter ) [static]

This function allows to really stop regular conversion.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2889 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_FILTER_SW_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

Referenced by HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), and HAL_DFSDM_FilterRegularStop_IT().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Channel initialization and de-initialization functions

Functions
Channel initialization and de-initialization functions
DFSDM Exported Functions

Channel initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_ChannelInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_ChannelDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
__weak void | HAL_DFSDM_ChannelMspInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
__weak void | HAL_DFSDM_ChannelMspDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.

Detailed Description

Channel initialization and de-initialization functions.

  ==============================================================================
        ##### Channel initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the DFSDM channel.
      (+) De-initialize the DFSDM channel.

Function Documentation

HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

De-initialize the DFSDM channel.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status.

Definition at line 387 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_RESET, HAL_DFSDM_ChannelMspDeInit(), DFSDM_Channel_HandleTypeDef::Instance, DFSDM_Channel_HandleTypeDef::State, and v_dfsdm1ChannelCounter.

HAL_StatusTypeDef HAL_DFSDM_ChannelInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status.

Definition at line 293 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_Channel_OutputClockTypeDef::Activation, assert_param, DFSDM_Channel_InitTypeDef::Awd, DFSDM_Channel_InputTypeDef::DataPacking, DFSDM_CHAWSCDR_FOSR_OFFSET, DFSDM_CHCFGR1_CLK_DIV_OFFSET, DFSDM_CHCFGR2_DTRBS_OFFSET, DFSDM_CHCFGR2_OFFSET_OFFSET, DFSDM_GetChannelFromInstance(), DFSDM_Channel_OutputClockTypeDef::Divider, DFSDM_Channel_AwdTypeDef::FilterOrder, HAL_DFSDM_CHANNEL_STATE_READY, HAL_DFSDM_ChannelMspInit(), DFSDM_Channel_HandleTypeDef::Init, DFSDM_Channel_InitTypeDef::Input, DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_CHANNEL_DATA_PACKING, IS_DFSDM_CHANNEL_FILTER_ORDER, IS_DFSDM_CHANNEL_FILTER_OVS_RATIO, IS_DFSDM_CHANNEL_INPUT, IS_DFSDM_CHANNEL_INPUT_PINS, IS_DFSDM_CHANNEL_OFFSET, IS_DFSDM_CHANNEL_OUTPUT_CLOCK, IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER, IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT, IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE, IS_DFSDM_CHANNEL_SPI_CLOCK, DFSDM_Channel_InputTypeDef::Multiplexer, DFSDM_Channel_InitTypeDef::Offset, DFSDM_Channel_InitTypeDef::OutputClock, DFSDM_Channel_AwdTypeDef::Oversampling, DFSDM_Channel_InputTypeDef::Pins, DFSDM_Channel_InitTypeDef::RightBitShift, DFSDM_Channel_OutputClockTypeDef::Selection, DFSDM_Channel_InitTypeDef::SerialInterface, DFSDM_Channel_SerialInterfaceTypeDef::SpiClock, DFSDM_Channel_HandleTypeDef::State, DFSDM_Channel_SerialInterfaceTypeDef::Type, and v_dfsdm1ChannelCounter.

void HAL_DFSDM_ChannelMspDeInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

De-initialize the DFSDM channel MSP.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
None

Definition at line 448 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelDeInit().

void HAL_DFSDM_ChannelMspInit ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Initialize the DFSDM channel MSP.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
None

Definition at line 433 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_ChannelInit().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Channel operation functions

Functions
Channel operation functions
DFSDM Exported Functions

Channel operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForCkab (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelCkabCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForScd (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelScdCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
int16_t | HAL_DFSDM_ChannelGetAwdValue (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelModifyOffset (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.

Detailed Description

Channel operation functions.

  ==============================================================================
                   ##### Channel operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Manage clock absence detector feature.
      (+) Manage short circuit detector feature.
      (+) Get analog watchdog value.
      (+) Modify offset value.

Function Documentation

void HAL_DFSDM_ChannelCkabCallback ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Clock absence detection callback.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
None

Definition at line 681 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to start clock absence detection in polling mode.

Note:
Same mode has to be used for all channels.
If clock is not available on this channel during 5 seconds, clock absence detection will not be activated and function will return HAL_TIMEOUT error.
Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 487 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_CKAB_TIMEOUT, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_FLTISR_CKABF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to start clock absence detection in interrupt mode.

Note:
Same mode has to be used for all channels.
If clock is not available on this channel during 5 seconds, clock absence detection will not be activated and function will return HAL_TIMEOUT error.
Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 626 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_CKAB_TIMEOUT, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_FLTISR_CKABF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop clock absence detection in polling mode.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 590 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop clock absence detection in interrupt mode.

Note:
Interrupt will be disabled for all channels
Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 697 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

int16_t HAL_DFSDM_ChannelGetAwdValue ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to get channel analog watchdog value.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
Channel analog watchdog value.

Definition at line 951 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_Channel_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | int32_t | Offset
 | ) |  |

This function allows to modify channel offset value.

Parameters:
hdfsdm_channel | : DFSDM channel handle.
Offset | : DFSDM channel offset. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
Return values:
HAL status.

Definition at line 963 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_CHCFGR2_OFFSET_OFFSET, HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_CHANNEL_OFFSET, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the clock absence detection.

Parameters:
hdfsdm_channel | : DFSDM channel handle.
Timeout | : Timeout value in milliseconds.
Return values:
HAL status

Definition at line 540 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_FLTISR_CKABF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the short circuit detection.

Parameters:
hdfsdm_channel | : DFSDM channel handle.
Timeout | : Timeout value in milliseconds.
Return values:
HAL status

Definition at line 774 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRSCDF_OFFSET, DFSDM_FLTISR_SCDF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, HAL_GetTick(), DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

void HAL_DFSDM_ChannelScdCallback ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

Short circuit detection callback.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
None

Definition at line 900 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Threshold,
 |  | uint32_t | BreakSignal
 | ) |  |

This function allows to start short circuit detection in polling mode.

Note:
Same mode has to be used for all channels
Parameters:
hdfsdm_channel | : DFSDM channel handle.
Threshold | : Short circuit detector threshold. This parameter must be a number between Min_Data = 0 and Max_Data = 255.
BreakSignal | : Break signals assigned to short circuit event. This parameter can be a values combination of DFSDM break signals.
Return values:
HAL status

Definition at line 737 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_CHAWSCDR_BKSCD_OFFSET, HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_BREAK_SIGNALS, IS_DFSDM_CHANNEL_SCD_THRESHOLD, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT | ( | DFSDM_Channel_HandleTypeDef * | hdfsdm_channel,
 |  | uint32_t | Threshold,
 |  | uint32_t | BreakSignal
 | ) |  |

This function allows to start short circuit detection in interrupt mode.

Note:
Same mode has to be used for all channels
Parameters:
hdfsdm_channel | : DFSDM channel handle.
Threshold | : Short circuit detector threshold. This parameter must be a number between Min_Data = 0 and Max_Data = 255.
BreakSignal | : Break signals assigned to short circuit event. This parameter can be a values combination of DFSDM break signals.
Return values:
HAL status

Definition at line 861 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_CHAWSCDR_BKSCD_OFFSET, HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, IS_DFSDM_BREAK_SIGNALS, IS_DFSDM_CHANNEL_SCD_THRESHOLD, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop short circuit detection in polling mode.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 824 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRSCDF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to stop short circuit detection in interrupt mode.

Note:
Interrupt will be disabled for all channels
Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
HAL status

Definition at line 916 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTICR_CLRSCDF_OFFSET, DFSDM_GetChannelFromInstance(), HAL_DFSDM_CHANNEL_STATE_READY, DFSDM_Channel_HandleTypeDef::Instance, and DFSDM_Channel_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Channel state function

Functions
Channel state function
DFSDM Exported Functions

Channel state function. More...

Functions

HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.

Detailed Description

Channel state function.

  ==============================================================================
                   ##### Channel state function #####
  ==============================================================================
    [..]  This section provides function allowing to:
      (+) Get channel handle state.

Function Documentation

HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState ( DFSDM_Channel_HandleTypeDef * hdfsdm_channel )

This function allows to get the current DFSDM channel handle state.

Parameters:
hdfsdm_channel : DFSDM channel handle.
Return values:
DFSDM channel state.

Definition at line 1010 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_Channel_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Filter initialization and de-initialization functions

Functions
Filter initialization and de-initialization functions
DFSDM Exported Functions

Filter initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_FilterInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_FilterDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
__weak void | HAL_DFSDM_FilterMspInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
__weak void | HAL_DFSDM_FilterMspDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.

Detailed Description

Filter initialization and de-initialization functions.

  ==============================================================================
        ##### Filter initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the DFSDM filter.
      (+) De-initialize the DFSDM filter.

Function Documentation

HAL_StatusTypeDef HAL_DFSDM_FilterDeInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

De-initializes the DFSDM filter.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status.

Definition at line 1150 of file stm32l4xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_FILTER_STATE_RESET, HAL_DFSDM_FilterMspDeInit(), DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status.

Definition at line 1040 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_FILTER_ERROR_NONE, DFSDM_FILTER_EXT_TRIGGER, DFSDM_FILTER_SYNC_TRIGGER, DFSDM_FLTFCR_FOSR_OFFSET, DFSDM_Filter_RegularParamTypeDef::DmaMode, DFSDM_Filter_InjectedParamTypeDef::DmaMode, DFSDM_Filter_HandleTypeDef::ErrorCode, DFSDM_Filter_InjectedParamTypeDef::ExtTrigger, DFSDM_Filter_InjectedParamTypeDef::ExtTriggerEdge, DFSDM_Filter_HandleTypeDef::ExtTriggerEdge, DFSDM_Filter_RegularParamTypeDef::FastMode, DFSDM_Filter_InitTypeDef::FilterParam, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FilterMspInit(), DFSDM_Filter_HandleTypeDef::Init, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_InitTypeDef::InjectedParam, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_FilterParamTypeDef::IntOversampling, IS_DFSDM_FILTER_EXT_TRIG, IS_DFSDM_FILTER_EXT_TRIG_EDGE, IS_DFSDM_FILTER_INJ_TRIGGER, IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO, IS_DFSDM_FILTER_OVS_RATIO, IS_DFSDM_FILTER_REG_TRIGGER, IS_DFSDM_FILTER_SINC_ORDER, DFSDM_Filter_FilterParamTypeDef::Oversampling, DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_InitTypeDef::RegularParam, DFSDM_Filter_HandleTypeDef::RegularTrigger, DFSDM_Filter_InjectedParamTypeDef::ScanMode, DFSDM_Filter_FilterParamTypeDef::SincOrder, DFSDM_Filter_HandleTypeDef::State, DFSDM_Filter_RegularParamTypeDef::Trigger, and DFSDM_Filter_InjectedParamTypeDef::Trigger.

void HAL_DFSDM_FilterMspDeInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

De-initializes the DFSDM filter MSP.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 1193 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterDeInit().

void HAL_DFSDM_FilterMspInit ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Initializes the DFSDM filter MSP.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 1178 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_FilterInit().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Filter control functions

Functions
Filter control functions
DFSDM Exported Functions

Filter control functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_FilterConfigRegChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigInjChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.

Detailed Description

Filter control functions.

  ==============================================================================
                    ##### Filter control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Select channel and enable/disable continuous mode for regular conversion.
      (+) Select channels for injected conversion.

Function Documentation

HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel
 | ) |  |

This function allows to select channels for injected conversion.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Channels for injected conversion. This parameter can be a values combination of DFSDM Channel Selection.
Return values:
HAL status

Definition at line 1276 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_GetInjChannelsNbr(), DFSDM_LSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_INJECTED_CHANNEL, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel,
 |  | uint32_t | ContinuousMode
 | ) |  |

This function allows to select channel and to enable/disable continuous mode for regular conversion.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Channel for regular conversion. This parameter can be a value of DFSDM Channel Selection.
ContinuousMode | : Enable/disable continuous mode for regular conversion. This parameter can be a value of DFSDM Continuous Mode.
Return values:
HAL status

Definition at line 1231 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_ON, DFSDM_FLTCR1_MSB_RCH_OFFSET, DFSDM_MSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_CONTINUOUS_MODE, IS_DFSDM_REGULAR_CHANNEL, DFSDM_Filter_HandleTypeDef::RegularContMode, and DFSDM_Filter_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Filter operation functions

Functions
Filter operation functions
DFSDM Exported Functions

Filter operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForRegConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetRegularValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForInjConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetInjectedValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
int32_t | HAL_DFSDM_FilterGetExdMaxValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
int32_t | HAL_DFSDM_FilterGetExdMinValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
uint32_t | HAL_DFSDM_FilterGetConvTimeValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
void | HAL_DFSDM_IRQHandler (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
__weak void | HAL_DFSDM_FilterRegConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
__weak void | HAL_DFSDM_FilterRegConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
__weak void | HAL_DFSDM_FilterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
__weak void | HAL_DFSDM_FilterErrorCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.

Detailed Description

Filter operation functions.

  ==============================================================================
                    ##### Filter operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular/injected channel.
      (+) Poll for the end of regular/injected conversion.
      (+) Stop conversion of regular/injected channel.
      (+) Start conversion of regular/injected channel and enable interrupt.
      (+) Call the callback functions at the end of regular/injected conversions.
      (+) Stop conversion of regular/injected channel and disable interrupt.
      (+) Start conversion of regular/injected channel and enable DMA transfer.
      (+) Stop conversion of regular/injected channel and disable DMA transfer.
      (+) Start analog watchdog and enable interrupt.
      (+) Call the callback function when analog watchdog occurs.
      (+) Stop analog watchdog and disable interrupt.
      (+) Start extreme detector.
      (+) Stop extreme detector.
      (+) Get result of regular channel conversion.
      (+) Get result of injected channel conversion.
      (+) Get extreme detector maximum and minimum values.
      (+) Get conversion time.
      (+) Handle DFSDM interrupt request.

Function Documentation

void HAL_DFSDM_FilterAwdCallback | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel,
 |  | uint32_t | Threshold
 | ) |  |

Filter analog watchdog callback.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Corresponding channel.
Threshold | : Low or high threshold has been reached.
Return values:
None

Definition at line 2620 of file stm32l4xx_hal_dfsdm.c.

Referenced by HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | DFSDM_Filter_AwdParamTypeDef * | awdParam
 | ) |  |

This function allows to start filter analog watchdog in interrupt mode.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
awdParam | : DFSDM filter analog watchdog parameters.
Return values:
HAL status

Definition at line 2159 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_Filter_AwdParamTypeDef::Channel, DFSDM_Filter_AwdParamTypeDef::DataSource, DFSDM_FLTAWHTR_THRESHOLD_OFFSET, DFSDM_FLTAWLTR_THRESHOLD_OFFSET, DFSDM_FLTCR2_AWDCH_OFFSET, DFSDM_LSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_AwdParamTypeDef::HighBreakSignal, DFSDM_Filter_AwdParamTypeDef::HighThreshold, DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_BREAK_SIGNALS, IS_DFSDM_FILTER_AWD_DATA_SOURCE, IS_DFSDM_FILTER_AWD_THRESHOLD, IS_DFSDM_INJECTED_CHANNEL, DFSDM_Filter_AwdParamTypeDef::LowBreakSignal, DFSDM_Filter_AwdParamTypeDef::LowThreshold, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop filter analog watchdog in interrupt mode.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 2208 of file stm32l4xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

void HAL_DFSDM_FilterErrorCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Error callback.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2638 of file stm32l4xx_hal_dfsdm.c.

Referenced by DFSDM_DMAError(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), and HAL_DFSDM_IRQHandler().

HAL_StatusTypeDef HAL_DFSDM_FilterExdStart | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Channel
 | ) |  |

This function allows to start extreme detector feature.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Channels where extreme detector is enabled. This parameter can be a values combination of DFSDM Channel Selection.
Return values:
HAL status

Definition at line 2248 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTCR2_EXCH_OFFSET, DFSDM_LSB_MASK, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_HandleTypeDef::Instance, IS_DFSDM_INJECTED_CHANNEL, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterExdStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop extreme detector feature.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 2279 of file stm32l4xx_hal_dfsdm.c.

References assert_param, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_RESET, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

uint32_t HAL_DFSDM_FilterGetConvTimeValue ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to get conversion time value.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
Conversion time value
Note:
To get time in second, this value has to be divided by DFSDM clock frequency.

Definition at line 2372 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTCNVTIMR_DATA_OFFSET, and DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetExdMaxValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get extreme detector maximum value.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Corresponding channel.
Return values:
Extreme detector maximum value This value is between Min_Data = -8388608 and Max_Data = 8388607.

Definition at line 2317 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTEXMAX_DATA_OFFSET, and DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetExdMinValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get extreme detector minimum value.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Corresponding channel.
Return values:
Extreme detector minimum value This value is between Min_Data = -8388608 and Max_Data = 8388607.

Definition at line 2345 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTEXMIN_DATA_OFFSET, and DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetInjectedValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get injected conversion value.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Corresponding channel of injected conversion.
Return values:
Injected conversion value

Definition at line 2132 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTJDATAR_DATA_OFFSET, and DFSDM_Filter_HandleTypeDef::Instance.

int32_t HAL_DFSDM_FilterGetRegularValue | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t * | Channel
 | ) |  |

This function allows to get regular conversion value.

Parameters:
hdfsdm_filter | : DFSDM filter handle.
Channel | : Corresponding channel of regular conversion.
Return values:
Regular conversion value

Definition at line 1722 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FLTRDATAR_DATA_OFFSET, and DFSDM_Filter_HandleTypeDef::Instance.

void HAL_DFSDM_FilterInjConvCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Injected conversion complete callback.

Note:
In interrupt mode, user has to read conversion value in this function using HAL_DFSDM_FilterGetInjectedValue.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2588 of file stm32l4xx_hal_dfsdm.c.

Referenced by DFSDM_DMAInjectedConvCplt(), and HAL_DFSDM_IRQHandler().

void HAL_DFSDM_FilterInjConvHalfCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Half injected conversion complete callback.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2603 of file stm32l4xx_hal_dfsdm.c.

Referenced by DFSDM_DMAInjectedHalfConvCplt().

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int16_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing. Please note that data on buffer will contain signed 16 most significant bits of injected conversion.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
pData | : The destination buffer address.
Length | : The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 2024 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_DMAError(), DFSDM_DMAInjectedConvCplt(), DFSDM_DMAInjectedHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_InjConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DMA_Start_IT(), DFSDM_Filter_HandleTypeDef::hdmaInj, __DMA_HandleTypeDef::Init, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start injected conversion in polling mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1750 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStart(), HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start injected conversion in DMA mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing. Please note that data on buffer will contain signed injected conversion value on 24 most significant bits and corresponding channel on 3 least significant bits.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
pData | : The destination buffer address.
Length | : The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 1949 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_DMAError(), DFSDM_DMAInjectedConvCplt(), DFSDM_DMAInjectedHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_InjConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DMA_Start_IT(), DFSDM_Filter_HandleTypeDef::hdmaInj, __DMA_HandleTypeDef::Init, DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start injected conversion in interrupt mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if regular conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1880 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStart(), HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop injected conversion in polling mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1850 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStop(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop injected conversion in DMA mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 2093 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStop(), HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DMA_Abort(), DFSDM_Filter_HandleTypeDef::hdmaInj, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop injected conversion in interrupt mode.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1911 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_InjConvStop(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the end of injected conversion.

Note:
This function should be called only if injected conversion is ongoing.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
Timeout | : Timeout value in milliseconds.
Return values:
HAL status

Definition at line 1779 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_FILTER_ERROR_INJECTED_OVERRUN, DFSDM_FILTER_SW_TRIGGER, DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DFSDM_FilterErrorCallback(), HAL_GetTick(), DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | uint32_t | Timeout
 | ) |  |

This function allows to poll for the end of regular conversion.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
Timeout | : Timeout value in milliseconds.
Return values:
HAL status

Definition at line 1375 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_FILTER_ERROR_REGULAR_OVERRUN, DFSDM_FILTER_SW_TRIGGER, DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DFSDM_FilterErrorCallback(), HAL_GetTick(), DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

void HAL_DFSDM_FilterRegConvCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Regular conversion complete callback.

Note:
In interrupt mode, user has to read conversion value in this function using HAL_DFSDM_FilterGetRegularValue.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2556 of file stm32l4xx_hal_dfsdm.c.

Referenced by DFSDM_DMARegularConvCplt(), and HAL_DFSDM_IRQHandler().

void HAL_DFSDM_FilterRegConvHalfCpltCallback ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

Half regular conversion complete callback.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2571 of file stm32l4xx_hal_dfsdm.c.

Referenced by DFSDM_DMARegularHalfConvCplt().

HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int16_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing. Please note that data on buffer will contain signed 16 most significant bits of regular conversion.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
pData | : The destination buffer address.
Length | : The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 1612 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_DMAError(), DFSDM_DMARegularConvCplt(), DFSDM_DMARegularHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_RegConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DMA_Start_IT(), DFSDM_Filter_HandleTypeDef::hdmaReg, __DMA_HandleTypeDef::Init, DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_HandleTypeDef::RegularTrigger, DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start regular conversion in polling mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1346 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStart(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA | ( | DFSDM_Filter_HandleTypeDef * | hdfsdm_filter,
 |  | int32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

This function allows to start regular conversion in DMA mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing. Please note that data on buffer will contain signed regular conversion value on 24 most significant bits and corresponding channel on 3 least significant bits.
Parameters:
hdfsdm_filter | : DFSDM filter handle.
pData | : The destination buffer address.
Length | : The length of data to be transferred from DFSDM filter to memory.
Return values:
HAL status

Definition at line 1535 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_DMAError(), DFSDM_DMARegularConvCplt(), DFSDM_DMARegularHalfConvCplt(), DFSDM_FILTER_SW_TRIGGER, DFSDM_RegConvStart(), DMA_CIRCULAR, DMA_NORMAL, HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DMA_Start_IT(), DFSDM_Filter_HandleTypeDef::hdmaReg, __DMA_HandleTypeDef::Init, DFSDM_Filter_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_HandleTypeDef::RegularTrigger, DFSDM_Filter_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to start regular conversion in interrupt mode.

Note:
This function should be called only when DFSDM filter instance is in idle state or if injected conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1466 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStart(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop regular conversion in polling mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1436 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStop(), HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop regular conversion in DMA mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1683 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStop(), HAL_DFSDM_FILTER_STATE_ERROR, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, HAL_DMA_Abort(), DFSDM_Filter_HandleTypeDef::hdmaReg, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to stop regular conversion in interrupt mode.

Note:
This function should be called only if regular conversion is ongoing.
Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
HAL status

Definition at line 1497 of file stm32l4xx_hal_dfsdm.c.

References assert_param, DFSDM_RegConvStop(), HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FILTER_STATE_REG_INJ, DFSDM_Filter_HandleTypeDef::Instance, and DFSDM_Filter_HandleTypeDef::State.

void HAL_DFSDM_IRQHandler ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function handles the DFSDM interrupts.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
None

Definition at line 2395 of file stm32l4xx_hal_dfsdm.c.

References DFSDM1_CHANNEL_NUMBER, DFSDM_AWD_HIGH_THRESHOLD, DFSDM_AWD_LOW_THRESHOLD, DFSDM_CONTINUOUS_CONV_OFF, DFSDM_FILTER_ERROR_INJECTED_OVERRUN, DFSDM_FILTER_ERROR_REGULAR_OVERRUN, DFSDM_FILTER_SW_TRIGGER, DFSDM_FLTAWSR_HIGH_OFFSET, DFSDM_FLTICR_CLRCKABF_OFFSET, DFSDM_FLTICR_CLRSCDF_OFFSET, DFSDM_FLTISR_CKABF_OFFSET, DFSDM_FLTISR_SCDF_OFFSET, DFSDM_Filter_HandleTypeDef::ErrorCode, HAL_DFSDM_ChannelCkabCallback(), HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FILTER_STATE_INJ, HAL_DFSDM_FILTER_STATE_READY, HAL_DFSDM_FILTER_STATE_REG, HAL_DFSDM_FilterAwdCallback(), HAL_DFSDM_FilterErrorCallback(), HAL_DFSDM_FilterInjConvCpltCallback(), HAL_DFSDM_FilterRegConvCpltCallback(), DFSDM_Filter_HandleTypeDef::InjConvRemaining, DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr, DFSDM_Filter_HandleTypeDef::InjectedScanMode, DFSDM_Filter_HandleTypeDef::InjectedTrigger, DFSDM_Filter_HandleTypeDef::Instance, DFSDM_Filter_HandleTypeDef::RegularContMode, DFSDM_Filter_HandleTypeDef::RegularTrigger, and DFSDM_Filter_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Filter state functions

Functions
Filter state functions
DFSDM Exported Functions

Filter state functions. More...

Functions

HAL_DFSDM_Filter_StateTypeDef | HAL_DFSDM_FilterGetState (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
uint32_t | HAL_DFSDM_FilterGetError (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.

Detailed Description

Filter state functions.

  ==============================================================================
                     ##### Filter state functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the DFSDM filter state.
      (+) Get the DFSDM filter error.

Function Documentation

uint32_t HAL_DFSDM_FilterGetError ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to get the current DFSDM filter error.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
DFSDM filter error code.

Definition at line 2682 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_Filter_HandleTypeDef::ErrorCode.

HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState ( DFSDM_Filter_HandleTypeDef * hdfsdm_filter )

This function allows to get the current DFSDM filter handle state.

Parameters:
hdfsdm_filter : DFSDM filter handle.
Return values:
DFSDM filter state.

Definition at line 2671 of file stm32l4xx_hal_dfsdm.c.

References DFSDM_Filter_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM Exported Types

Data Structures | Enumerations
DFSDM Exported Types
DFSDM

Data Structures

struct | DFSDM_Channel_OutputClockTypeDef
DFSDM channel output clock structure definition. More...
struct | DFSDM_Channel_InputTypeDef
DFSDM channel input structure definition. More...
struct | DFSDM_Channel_SerialInterfaceTypeDef
DFSDM channel serial interface structure definition. More...
struct | DFSDM_Channel_AwdTypeDef
DFSDM channel analog watchdog structure definition. More...
struct | DFSDM_Channel_InitTypeDef
DFSDM channel init structure definition. More...
struct | DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition. More...
struct | DFSDM_Filter_RegularParamTypeDef
DFSDM filter regular conversion parameters structure definition. More...
struct | DFSDM_Filter_InjectedParamTypeDef
DFSDM filter injected conversion parameters structure definition. More...
struct | DFSDM_Filter_FilterParamTypeDef
DFSDM filter parameters structure definition. More...
struct | DFSDM_Filter_InitTypeDef
DFSDM filter init structure definition. More...
struct | DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition. More...
struct | DFSDM_Filter_AwdParamTypeDef
DFSDM filter analog watchdog parameters structure definition. More...

Enumerations

enum | HAL_DFSDM_Channel_StateTypeDef { HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU }
HAL DFSDM Channel states definition. More...
enum HAL_DFSDM_Filter_StateTypeDef {
HAL_DFSDM_FILTER_STATE_RESET = 0x00U, HAL_DFSDM_FILTER_STATE_READY = 0x01U, HAL_DFSDM_FILTER_STATE_REG = 0x02U, HAL_DFSDM_FILTER_STATE_INJ = 0x03U,
HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU
}
HAL DFSDM Filter states definition. More...

Enumeration Type Documentation

enum HAL_DFSDM_Channel_StateTypeDef

HAL DFSDM Channel states definition.

Enumerator:
HAL_DFSDM_CHANNEL_STATE_RESET

DFSDM channel not initialized

HAL_DFSDM_CHANNEL_STATE_READY

DFSDM channel initialized and ready for use

HAL_DFSDM_CHANNEL_STATE_ERROR

DFSDM channel state error

Definition at line 66 of file stm32l4xx_hal_dfsdm.h.

enum HAL_DFSDM_Filter_StateTypeDef

HAL DFSDM Filter states definition.

Enumerator:
HAL_DFSDM_FILTER_STATE_RESET

DFSDM filter not initialized

HAL_DFSDM_FILTER_STATE_READY

DFSDM filter initialized and ready for use

HAL_DFSDM_FILTER_STATE_REG

DFSDM filter regular conversion in progress

HAL_DFSDM_FILTER_STATE_INJ

DFSDM filter injected conversion in progress

HAL_DFSDM_FILTER_STATE_REG_INJ

DFSDM filter regular and injected conversions in progress

HAL_DFSDM_FILTER_STATE_ERROR

DFSDM filter state error

Definition at line 148 of file stm32l4xx_hal_dfsdm.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Channel_OutputClockTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_OutputClockTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel output clock structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

FunctionalState | Activation
uint32_t | Selection
uint32_t | Divider

Detailed Description

DFSDM channel output clock structure definition.

Definition at line 76 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

FunctionalState DFSDM_Channel_OutputClockTypeDef::Activation

Output clock enable/disable

Definition at line 78 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_OutputClockTypeDef::Divider

Output clock divider. This parameter must be a number between Min_Data = 2 and Max_Data = 256

Definition at line 81 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_OutputClockTypeDef::Selection

Output clock is system clock or audio clock. This parameter can be a value of DFSDM channel output clock selection

Definition at line 79 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Channel_InputTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_InputTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel input structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

uint32_t | Multiplexer
uint32_t | DataPacking
uint32_t | Pins

Detailed Description

DFSDM channel input structure definition.

Definition at line 88 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Channel_InputTypeDef::DataPacking

Standard, interleaved or dual mode for internal register. This parameter can be a value of DFSDM channel input data packing

Definition at line 92 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_InputTypeDef::Multiplexer

Input is external serial inputs or internal register. This parameter can be a value of DFSDM channel input multiplexer

Definition at line 90 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_InputTypeDef::Pins

Input pins are taken from same or following channel. This parameter can be a value of DFSDM channel input pins

Definition at line 94 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Channel_SerialInterfaceTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_SerialInterfaceTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel serial interface structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

uint32_t | Type
uint32_t | SpiClock

Detailed Description

DFSDM channel serial interface structure definition.

Definition at line 101 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Channel_SerialInterfaceTypeDef::SpiClock

SPI clock select (external or internal with different sampling point). This parameter can be a value of DFSDM channel SPI clock selection

Definition at line 105 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_SerialInterfaceTypeDef::Type

SPI or Manchester modes. This parameter can be a value of DFSDM channel serial interface type

Definition at line 103 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Channel_AwdTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_AwdTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel analog watchdog structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

uint32_t | FilterOrder
uint32_t | Oversampling

Detailed Description

DFSDM channel analog watchdog structure definition.

Definition at line 112 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Channel_AwdTypeDef::FilterOrder

Analog watchdog Sinc filter order. This parameter can be a value of DFSDM channel analog watchdog filter order

Definition at line 114 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_AwdTypeDef::Oversampling

Analog watchdog filter oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 32

Definition at line 116 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Channel_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_InitTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel init structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

DFSDM_Channel_OutputClockTypeDef OutputClock
DFSDM_Channel_InputTypeDef Input
DFSDM_Channel_SerialInterfaceTypeDef SerialInterface
DFSDM_Channel_AwdTypeDef Awd
int32_t | Offset
uint32_t | RightBitShift

Detailed Description

DFSDM channel init structure definition.

Definition at line 123 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

DFSDM_Channel_AwdTypeDef DFSDM_Channel_InitTypeDef::Awd

DFSDM channel analog watchdog parameters

Definition at line 128 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_InputTypeDef DFSDM_Channel_InitTypeDef::Input

DFSDM channel input parameters

Definition at line 126 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

int32_t DFSDM_Channel_InitTypeDef::Offset

DFSDM channel offset. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607

Definition at line 129 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_OutputClockTypeDef DFSDM_Channel_InitTypeDef::OutputClock

DFSDM channel output clock parameters

Definition at line 125 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

uint32_t DFSDM_Channel_InitTypeDef::RightBitShift

DFSDM channel right bit shift. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F

Definition at line 131 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_SerialInterfaceTypeDef DFSDM_Channel_InitTypeDef::SerialInterface

DFSDM channel serial interface parameters

Definition at line 127 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Channel_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Channel_HandleTypeDef Struct Reference
DFSDM Exported Types

DFSDM channel handle structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

DFSDM_Channel_TypeDef * Instance
DFSDM_Channel_InitTypeDef Init
HAL_DFSDM_Channel_StateTypeDef State

Detailed Description

DFSDM channel handle structure definition.

Definition at line 138 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

DFSDM_Channel_InitTypeDef DFSDM_Channel_HandleTypeDef::Init

DFSDM channel init parameters

Definition at line 141 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

DFSDM_Channel_TypeDef* DFSDM_Channel_HandleTypeDef::Instance

DFSDM channel instance

Definition at line 140 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelGetAwdValue(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelModifyOffset(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), HAL_DFSDM_ChannelScdStop(), and HAL_DFSDM_ChannelScdStop_IT().

HAL_DFSDM_Channel_StateTypeDef DFSDM_Channel_HandleTypeDef::State

DFSDM channel state

Definition at line 142 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelGetState(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelModifyOffset(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), HAL_DFSDM_ChannelScdStop(), and HAL_DFSDM_ChannelScdStop_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Filter_RegularParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_RegularParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter regular conversion parameters structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

uint32_t | Trigger
FunctionalState | FastMode
FunctionalState | DmaMode

Detailed Description

DFSDM filter regular conversion parameters structure definition.

Definition at line 161 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

FunctionalState DFSDM_Filter_RegularParamTypeDef::DmaMode

Enable/disable DMA for regular conversion

Definition at line 166 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

FunctionalState DFSDM_Filter_RegularParamTypeDef::FastMode

Enable/disable fast mode for regular conversion

Definition at line 165 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_RegularParamTypeDef::Trigger

Trigger used to start regular conversion: software or synchronous. This parameter can be a value of DFSDM filter conversion trigger

Definition at line 163 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Filter_InjectedParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_InjectedParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter injected conversion parameters structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

uint32_t | Trigger
FunctionalState | ScanMode
FunctionalState | DmaMode
uint32_t | ExtTrigger
uint32_t | ExtTriggerEdge

Detailed Description

DFSDM filter injected conversion parameters structure definition.

Definition at line 172 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

FunctionalState DFSDM_Filter_InjectedParamTypeDef::DmaMode

Enable/disable DMA for injected conversion

Definition at line 177 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_InjectedParamTypeDef::ExtTrigger

External trigger. This parameter can be a value of DFSDM filter external trigger

Definition at line 178 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_InjectedParamTypeDef::ExtTriggerEdge

External trigger edge: rising, falling or both. This parameter can be a value of DFSDM filter external trigger edge

Definition at line 180 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

FunctionalState DFSDM_Filter_InjectedParamTypeDef::ScanMode

Enable/disable scanning mode for injected conversion

Definition at line 176 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_InjectedParamTypeDef::Trigger

Trigger used to start injected conversion: software, external or synchronous. This parameter can be a value of DFSDM filter conversion trigger

Definition at line 174 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Filter_FilterParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_FilterParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter parameters structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

uint32_t | SincOrder
uint32_t | Oversampling
uint32_t | IntOversampling

Detailed Description

DFSDM filter parameters structure definition.

Definition at line 187 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Filter_FilterParamTypeDef::IntOversampling

Integrator oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 256

Definition at line 193 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_FilterParamTypeDef::Oversampling

Filter oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 1024

Definition at line 191 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_FilterParamTypeDef::SincOrder

Sinc filter order. This parameter can be a value of DFSDM filter sinc order

Definition at line 189 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Filter_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_InitTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter init structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

DFSDM_Filter_RegularParamTypeDef RegularParam
DFSDM_Filter_InjectedParamTypeDef InjectedParam
DFSDM_Filter_FilterParamTypeDef FilterParam

Detailed Description

DFSDM filter init structure definition.

Definition at line 200 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

DFSDM_Filter_FilterParamTypeDef DFSDM_Filter_InitTypeDef::FilterParam

DFSDM filter parameters

Definition at line 204 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

DFSDM_Filter_InjectedParamTypeDef DFSDM_Filter_InitTypeDef::InjectedParam

DFSDM injected conversion parameters

Definition at line 203 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

DFSDM_Filter_RegularParamTypeDef DFSDM_Filter_InitTypeDef::RegularParam

DFSDM regular conversion parameters

Definition at line 202 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Filter_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_HandleTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter handle structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

DFSDM_Filter_TypeDef * | Instance
DFSDM_Filter_InitTypeDef Init
DMA_HandleTypeDef * hdmaReg
DMA_HandleTypeDef * hdmaInj
uint32_t | RegularContMode
uint32_t | RegularTrigger
uint32_t | InjectedTrigger
uint32_t | ExtTriggerEdge
FunctionalState | InjectedScanMode
uint32_t | InjectedChannelsNbr
uint32_t | InjConvRemaining
HAL_DFSDM_Filter_StateTypeDef State
uint32_t | ErrorCode

Detailed Description

DFSDM filter handle structure definition.

Definition at line 210 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Filter_HandleTypeDef::ErrorCode

DFSDM filter error code

Definition at line 224 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_DMAError(), HAL_DFSDM_FilterGetError(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), and HAL_DFSDM_IRQHandler().

uint32_t DFSDM_Filter_HandleTypeDef::ExtTriggerEdge

Rising, falling or both edges selected

Definition at line 219 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), and HAL_DFSDM_FilterInit().

DMA_HandleTypeDef* DFSDM_Filter_HandleTypeDef::hdmaInj

Pointer on DMA handler for injected conversions

Definition at line 215 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), and HAL_DFSDM_FilterInjectedStop_DMA().

DMA_HandleTypeDef* DFSDM_Filter_HandleTypeDef::hdmaReg

Pointer on DMA handler for regular conversions

Definition at line 214 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_FilterRegularStop_DMA().

DFSDM_Filter_InitTypeDef DFSDM_Filter_HandleTypeDef::Init

DFSDM filter init parameters

Definition at line 213 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

uint32_t DFSDM_Filter_HandleTypeDef::InjConvRemaining

Injected conversions remaining

Definition at line 222 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

uint32_t DFSDM_Filter_HandleTypeDef::InjectedChannelsNbr

Number of channels in injected sequence

Definition at line 221 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

FunctionalState DFSDM_Filter_HandleTypeDef::InjectedScanMode

Injected scanning mode

Definition at line 220 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

uint32_t DFSDM_Filter_HandleTypeDef::InjectedTrigger

Trigger used for injected conversion

Definition at line 218 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

DFSDM_Filter_TypeDef* DFSDM_Filter_HandleTypeDef::Instance

DFSDM filter instance

Definition at line 212 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterAwdStop_IT(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterDeInit(), HAL_DFSDM_FilterExdStart(), HAL_DFSDM_FilterExdStop(), HAL_DFSDM_FilterGetConvTimeValue(), HAL_DFSDM_FilterGetExdMaxValue(), HAL_DFSDM_FilterGetExdMinValue(), HAL_DFSDM_FilterGetInjectedValue(), HAL_DFSDM_FilterGetRegularValue(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterInjectedStop_IT(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DFSDM_FilterRegularStop_IT(), and HAL_DFSDM_IRQHandler().

uint32_t DFSDM_Filter_HandleTypeDef::RegularContMode

Regular conversion continuous mode

Definition at line 216 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

uint32_t DFSDM_Filter_HandleTypeDef::RegularTrigger

Trigger used for regular conversion

Definition at line 217 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

HAL_DFSDM_Filter_StateTypeDef DFSDM_Filter_HandleTypeDef::State

DFSDM filter state

Definition at line 223 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterAwdStop_IT(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterDeInit(), HAL_DFSDM_FilterExdStart(), HAL_DFSDM_FilterExdStop(), HAL_DFSDM_FilterGetState(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterInjectedStop_IT(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DFSDM_FilterRegularStop_IT(), and HAL_DFSDM_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM_Filter_AwdParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DFSDM_Filter_AwdParamTypeDef Struct Reference
DFSDM Exported Types

DFSDM filter analog watchdog parameters structure definition. More...

#include <stm32l4xx_hal_dfsdm.h>

Data Fields

uint32_t | DataSource
uint32_t | Channel
int32_t | HighThreshold
int32_t | LowThreshold
uint32_t | HighBreakSignal
uint32_t | LowBreakSignal

Detailed Description

DFSDM filter analog watchdog parameters structure definition.

Definition at line 230 of file stm32l4xx_hal_dfsdm.h.

Field Documentation

uint32_t DFSDM_Filter_AwdParamTypeDef::Channel

Analog watchdog channel selection. This parameter can be a values combination of DFSDM Channel Selection

Definition at line 234 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

uint32_t DFSDM_Filter_AwdParamTypeDef::DataSource

Values from digital filter or from channel watchdog filter. This parameter can be a value of DFSDM filter analog watchdog data source

Definition at line 232 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

uint32_t DFSDM_Filter_AwdParamTypeDef::HighBreakSignal

Break signal assigned to analog watchdog high threshold event. This parameter can be a values combination of DFSDM break signals

Definition at line 240 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

int32_t DFSDM_Filter_AwdParamTypeDef::HighThreshold

High threshold for the analog watchdog. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607

Definition at line 236 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

uint32_t DFSDM_Filter_AwdParamTypeDef::LowBreakSignal

Break signal assigned to analog watchdog low threshold event. This parameter can be a values combination of DFSDM break signals

Definition at line 242 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

int32_t DFSDM_Filter_AwdParamTypeDef::LowThreshold

Low threshold for the analog watchdog. This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607

Definition at line 238 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dfsdm.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM channel output clock selection

Defines
DFSDM channel output clock selection
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC

Define Documentation

#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC

Source for ouput clock is audio clock

Definition at line 260 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U)

Source for ouput clock is system clock

Definition at line 259 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM channel input multiplexer

Defines
DFSDM channel input multiplexer
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1

Define Documentation

#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U)

Data are taken from external inputs

Definition at line 268 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1

Data are taken from internal register

Definition at line 269 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM channel input data packing

Defines
DFSDM channel input data packing
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0
#define | DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1

Define Documentation

#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1

Dual data packing mode

Definition at line 279 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0

Interleaved data packing mode

Definition at line 278 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U)

Standard data packing mode

Definition at line 277 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM channel input pins

Defines
DFSDM channel input pins
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL

Define Documentation

#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL

Input from pins on following channel

Definition at line 288 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U)

Input from pins on same channel

Definition at line 287 of file stm32l4xx_hal_dfsdm.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM channel serial interface type

Defines
DFSDM channel serial interface type
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0
#define | DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1
#define | DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP

Define Documentation

#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP

Manchester with falling edge

Definition at line 299 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1

Manchester with rising edge

Definition at line 298 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0

SPI with falling edge

Definition at line 297 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U)

SPI with rising edge

Definition at line 296 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM channel SPI clock selection

Defines
DFSDM channel SPI clock selection
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL

Define Documentation

#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U)

External SPI clock

Definition at line 307 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0

Internal SPI clock

Definition at line 308 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1

Internal SPI clock divided by 2, falling edge

Definition at line 309 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL

Internal SPI clock divided by 2, rising edge

Definition at line 310 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM channel analog watchdog filter order

Defines
DFSDM channel analog watchdog filter order
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0
#define | DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1
#define | DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD

Define Documentation

#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U)

FastSinc filter type

Definition at line 318 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0

Sinc 1 filter type

Definition at line 319 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1

Sinc 2 filter type

Definition at line 320 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD

Sinc 3 filter type

Definition at line 321 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM filter conversion trigger

Defines
DFSDM filter conversion trigger
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U)
#define | DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U)
#define | DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U)

Define Documentation

#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U)

External trigger (only for injected conversion)

Definition at line 331 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStop(), and HAL_DFSDM_FilterInit().

#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U)

Software trigger

Definition at line 329 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStart(), DFSDM_RegConvStop(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U)

Synchronous with DFSDM_FLT0

Definition at line 330 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_InjConvStart(), DFSDM_InjConvStop(), DFSDM_RegConvStop(), and HAL_DFSDM_FilterInit().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM filter external trigger

Defines
DFSDM filter external trigger
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U)
#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2
#define | DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2
#define | DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL

Define Documentation

#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2)

For DFSDM filter 0, 1, 2 and 3

Definition at line 348 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL

For DFSDM filter 0, 1, 2 and 3

Definition at line 349 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2

For DFSDM filter 3

Definition at line 345 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U)

For DFSDM filter 0, 1, 2 and 3

Definition at line 339 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0

For DFSDM filter 0, 1, 2 and 3

Definition at line 340 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)

For DFSDM filter 3

Definition at line 343 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2

For DFSDM filter 0, 1 and 2

Definition at line 344 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)

For DFSDM filter 0 and 1

Definition at line 346 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)

For DFSDM filter 2 and 3

Definition at line 347 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1

For DFSDM filter 0, 1, 2 and 3

Definition at line 341 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)

For DFSDM filter 0, 1 and 2

Definition at line 342 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM filter external trigger edge

Defines
DFSDM filter external trigger edge
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0
#define | DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1
#define | DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN

Define Documentation

#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN

External rising and falling edges

Definition at line 359 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1

External falling edge

Definition at line 358 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0

External rising edge

Definition at line 357 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM filter sinc order

Defines
DFSDM filter sinc order
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U)
#define | DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0
#define | DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1
#define | DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)
#define | DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2
#define | DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)

Define Documentation

#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U)

FastSinc filter type

Definition at line 367 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0

Sinc 1 filter type

Definition at line 368 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1

Sinc 2 filter type

Definition at line 369 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)

Sinc 3 filter type

Definition at line 370 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2

Sinc 4 filter type

Definition at line 371 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)

Sinc 5 filter type

Definition at line 372 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM filter analog watchdog data source

Defines
DFSDM filter analog watchdog data source
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U)
#define | DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL

Define Documentation

#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL

From analog watchdog channel

Definition at line 381 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U)

From digital filter

Definition at line 380 of file stm32l4xx_hal_dfsdm.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM filter error code

Defines
DFSDM filter error code
DFSDM Exported Constants

Defines

#define | DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U)
#define | DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U)
#define | DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U)
#define | DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U)

Define Documentation

#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U)

DMA error occurs

Definition at line 392 of file stm32l4xx_hal_dfsdm.h.

Referenced by DFSDM_DMAError().

#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U)

Overrun occurs during injected conversion

Definition at line 391 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterPollForInjConversion(), and HAL_DFSDM_IRQHandler().

#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 389 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U)

Overrun occurs during regular conversion

Definition at line 390 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterPollForRegConversion(), and HAL_DFSDM_IRQHandler().

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STM32L486xx HAL User Manual: DFSDM break signals

Defines
DFSDM break signals
DFSDM Exported Constants

Defines

#define | DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U)
#define | DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U)
#define | DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U)
#define | DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U)
#define | DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U)

Define Documentation

#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U)

Break signal 0

Definition at line 401 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U)

Break signal 1

Definition at line 402 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U)

Break signal 2

Definition at line 403 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U)

Break signal 3

Definition at line 404 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U)

No break signal

Definition at line 400 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM Channel Selection

Defines
DFSDM Channel Selection
DFSDM Exported Constants

Defines

#define | DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
#define | DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
#define | DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
#define | DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
#define | DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)
#define | DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
#define | DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
#define | DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)

Define Documentation

#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)

Definition at line 420 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)

Definition at line 421 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)

Definition at line 422 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)

Definition at line 423 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)

Definition at line 424 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)

Definition at line 425 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)

Definition at line 426 of file stm32l4xx_hal_dfsdm.h.

#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)

Definition at line 427 of file stm32l4xx_hal_dfsdm.h.

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STM32L486xx HAL User Manual: DFSDM Continuous Mode

Defines
DFSDM Continuous Mode
DFSDM Exported Constants

Defines

#define | DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U)
#define | DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U)

Define Documentation

#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U)

Conversion are not continuous

Definition at line 435 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DFSDM_IRQHandler().

#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U)

Conversion are continuous

Definition at line 436 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM analog watchdog threshold

Defines
DFSDM analog watchdog threshold
DFSDM Exported Constants

Defines

#define | DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U)
#define | DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U)

Define Documentation

#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U)

Analog watchdog high threshold

Definition at line 444 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_IRQHandler().

#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U)

Analog watchdog low threshold

Definition at line 445 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_IRQHandler().

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM Exported Macros

Defines
DFSDM Exported Macros
DFSDM

Defines

#define | __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
Reset DFSDM channel handle state.
#define | __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
Reset DFSDM filter handle state.

Define Documentation

#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)

Reset DFSDM channel handle state.

Parameters:
__HANDLE__,: DFSDM channel handle.
Return values:
None

Definition at line 464 of file stm32l4xx_hal_dfsdm.h.

#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)

Reset DFSDM filter handle state.

Parameters:
__HANDLE__,: DFSDM filter handle.
Return values:
None

Definition at line 470 of file stm32l4xx_hal_dfsdm.h.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM Private Macros

Defines
DFSDM Private Macros
DFSDM

Defines

#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)
#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
#define | IS_DFSDM_CHANNEL_INPUT(INPUT)
#define | IS_DFSDM_CHANNEL_DATA_PACKING(MODE)
#define | IS_DFSDM_CHANNEL_INPUT_PINS(PINS)
#define | IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)
#define | IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)
#define | IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)
#define | IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
#define | IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
#define | IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
#define | IS_DFSDM_FILTER_REG_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)
#define | IS_DFSDM_FILTER_SINC_ORDER(ORDER)
#define | IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
#define | IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
#define | IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)
#define | IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
#define | IS_DFSDM_REGULAR_CHANNEL(CHANNEL)
#define | IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
#define | IS_DFSDM_CONTINUOUS_MODE(MODE)

Define Documentation

#define IS_DFSDM_BREAK_SIGNALS ( VALUE ) ((VALUE) <= 0xFU)

Definition at line 674 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), and HAL_DFSDM_FilterAwdStart_IT().

#define IS_DFSDM_CHANNEL_DATA_PACKING ( MODE )
Value:
(((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))

Definition at line 623 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_FILTER_ORDER ( ORDER )
Value:
(((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))

Definition at line 636 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO ( RATIO ) ((1 <= (RATIO)) && ((RATIO) <= 32))

Definition at line 640 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_INPUT ( INPUT )
Value:
(((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))

Definition at line 621 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_INPUT_PINS ( PINS )
Value:
(((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))

Definition at line 626 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_OFFSET ( VALUE ) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

Definition at line 641 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit(), and HAL_DFSDM_ChannelModifyOffset().

#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK ( CLOCK )
Value:
(((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))

Definition at line 618 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER ( DIVIDER ) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))

Definition at line 620 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT ( VALUE ) ((VALUE) <= 0x1F)

Definition at line 642 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_SCD_THRESHOLD ( VALUE ) ((VALUE) <= 0xFF)

Definition at line 643 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelScdStart(), and HAL_DFSDM_ChannelScdStart_IT().

#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE ( MODE )
Value:
(((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))

Definition at line 628 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CHANNEL_SPI_CLOCK ( TYPE )
Value:
(((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))

Definition at line 632 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_ChannelInit().

#define IS_DFSDM_CONTINUOUS_MODE ( MODE )
Value:
(((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))

Definition at line 684 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

#define IS_DFSDM_FILTER_AWD_DATA_SOURCE ( DATA )
Value:
(((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))

Definition at line 671 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define IS_DFSDM_FILTER_AWD_THRESHOLD ( VALUE ) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

Definition at line 673 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT().

#define IS_DFSDM_FILTER_EXT_TRIG ( TRIG )
Value:
(((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))

Definition at line 649 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_EXT_TRIG_EDGE ( EDGE )
Value:
(((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))

Definition at line 660 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_INJ_TRIGGER ( TRIG )
Value:
(((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))

Definition at line 646 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO ( RATIO ) ((1 <= (RATIO)) && ((RATIO) <= 256))

Definition at line 670 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_OVS_RATIO ( RATIO ) ((1 <= (RATIO)) && ((RATIO) <= 1024))

Definition at line 669 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_REG_TRIGGER ( TRIG )
Value:
(((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))

Definition at line 644 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_FILTER_SINC_ORDER ( ORDER )
Value:
(((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))

Definition at line 663 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterInit().

#define IS_DFSDM_INJECTED_CHANNEL ( CHANNEL ) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))

Definition at line 683 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterConfigInjChannel(), and HAL_DFSDM_FilterExdStart().

#define IS_DFSDM_REGULAR_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == DFSDM_CHANNEL_0)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_3)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_4)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_5)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_6)  || \
                                                       ((CHANNEL) == DFSDM_CHANNEL_7))

Definition at line 675 of file stm32l4xx_hal_dfsdm.h.

Referenced by HAL_DFSDM_FilterConfigRegChannel().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Private Functions

Functions
DMA Private Functions
DMA

Functions

static void DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.

Function Documentation

static void DMA_SetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Sets the DMA Transfer parameter.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 893 of file stm32l4xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Channel source
    and destination addresses, incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.

Function Documentation

HAL_StatusTypeDef HAL_DMA_DeInit ( DMA_HandleTypeDef * hdma )

DeInitialize the DMA peripheral.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 265 of file stm32l4xx_hal_dma.c.

References __HAL_DMA_DISABLE, assert_param, __DMA_HandleTypeDef::ChannelIndex, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Init ( DMA_HandleTypeDef * hdma )

Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 161 of file stm32l4xx_hal_dma.c.

References assert_param, __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, DMA_MEMORY_TO_MEMORY, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_DMA_ALL_REQUEST, IS_DMA_DIRECTION, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, IS_DMA_PRIORITY, __DMA_HandleTypeDef::Lock, DMA_InitTypeDef::MemDataAlignment, DMA_InitTypeDef::MemInc, DMA_InitTypeDef::Mode, DMA_InitTypeDef::PeriphDataAlignment, DMA_InitTypeDef::PeriphInc, DMA_InitTypeDef::Priority, DMA_InitTypeDef::Request, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
DMA Exported Functions

Input and Output operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.

Detailed Description

Input and Output operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_DMA_Abort ( DMA_HandleTypeDef * hdma )

Abort the DMA Transfer.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 453 of file stm32l4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, and __DMA_HandleTypeDef::State.

Referenced by HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop_DMA(), HAL_DAC_Stop_DMA(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_IRDA_DMAStop(), HAL_QSPI_Abort(), HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SPI_DMAStop(), HAL_SWPMI_DMAStop(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_UART_DMAStop(), HAL_USART_DMAStop(), SD_DMA_RxCplt(), and SD_DMA_TxCplt().

HAL_StatusTypeDef HAL_DMA_Abort_IT ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer in Interrupt mode.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
Return values:
HAL status

Definition at line 490 of file stm32l4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_SAI_IRQHandler(), HAL_UART_IRQHandler(), HAL_USART_IRQHandler(), and I2C_ITError().

void HAL_DMA_IRQHandler ( DMA_HandleTypeDef * hdma )

Handle DMA interrupt request.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 636 of file stm32l4xx_hal_dma.c.

References __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_TE, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_PollForTransfer | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CompleteLevel,: Specifies the DMA level complete.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 535 of file stm32l4xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_ERROR_TE, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_FULL_TRANSFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, HAL_GetTick(), __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_RegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID,
 |  | void(*)(DMA_HandleTypeDef *_hdma) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CallbackID,: User Callback identifer a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
pCallback,: pointer to private callbacsk function which has pointer to a DMA_HandleTypeDef structure as parameter.
Return values:
HAL status

Definition at line 726 of file stm32l4xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Start | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 356 of file stm32l4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Start_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer with interrupt enabled.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 399 of file stm32l4xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __HAL_DMA_ENABLE, __HAL_DMA_ENABLE_IT, assert_param, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by CRYP_GCMCMAC_SetDMAConfig(), CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SD_ReadBlocks_DMA(), HAL_SD_WriteBlocks_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMasterTransmitCplt().

HAL_StatusTypeDef HAL_DMA_UnRegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID
 | ) |  |

UnRegister callbacks.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Stream.
CallbackID,: User Callback identifer a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
Return values:
HAL status

Definition at line 777 of file stm32l4xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_ALL_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DMA Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA hande state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA_GetError ( DMA_HandleTypeDef * hdma )

Return the DMA error code.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
DMA Error Code

Definition at line 867 of file stm32l4xx_hal_dma.c.

References __DMA_HandleTypeDef::ErrorCode.

HAL_DMA_StateTypeDef HAL_DMA_GetState ( DMA_HandleTypeDef * hdma )

Return the DMA hande state.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL state

Definition at line 855 of file stm32l4xx_hal_dma.c.

References __DMA_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Exported Types

Data Structures | Typedefs | Enumerations
DMA Exported Types
DMA

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00, HAL_DMA_STATE_READY = 0x01, HAL_DMA_STATE_BUSY = 0x02, HAL_DMA_STATE_TIMEOUT = 0x03 }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00, HAL_DMA_HALF_TRANSFER = 0x01 }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, HAL_DMA_XFER_ERROR_CB_ID = 0x02, HAL_DMA_XFER_ABORT_CB_ID = 0x03,
HAL_DMA_XFER_ALL_CB_ID = 0x04
}
HAL DMA Callback ID structure definition. More...

Typedef Documentation

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef

DMA handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA_CallbackIDTypeDef

HAL DMA Callback ID structure definition.

Enumerator:
HAL_DMA_XFER_CPLT_CB_ID

Full transfer

HAL_DMA_XFER_HALFCPLT_CB_ID

Half transfer

HAL_DMA_XFER_ERROR_CB_ID

Error

HAL_DMA_XFER_ABORT_CB_ID

Abort

HAL_DMA_XFER_ALL_CB_ID

All

Definition at line 120 of file stm32l4xx_hal_dma.h.

enum HAL_DMA_LevelCompleteTypeDef

HAL DMA Error Code structure definition.

Enumerator:
HAL_DMA_FULL_TRANSFER

Full transfer

HAL_DMA_HALF_TRANSFER

Half Transfer

Definition at line 110 of file stm32l4xx_hal_dma.h.

enum HAL_DMA_StateTypeDef

HAL DMA State structures definition.

Enumerator:
HAL_DMA_STATE_RESET

DMA not yet initialized or disabled

HAL_DMA_STATE_READY

DMA initialized and ready for use

HAL_DMA_STATE_BUSY

DMA process is ongoing

HAL_DMA_STATE_TIMEOUT

DMA timeout state

Definition at line 99 of file stm32l4xx_hal_dma.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_InitTypeDef Struct Reference
DMA Exported Types

DMA Configuration Structure definition. More...

#include <stm32l4xx_hal_dma.h>

Data Fields

uint32_t | Request
uint32_t | Direction
uint32_t | PeriphInc
uint32_t | MemInc
uint32_t | PeriphDataAlignment
uint32_t | MemDataAlignment
uint32_t | Mode
uint32_t | Priority

Detailed Description

DMA Configuration Structure definition.

Definition at line 66 of file stm32l4xx_hal_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA Data transfer direction

Definition at line 71 of file stm32l4xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Init(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

uint32_t DMA_InitTypeDef::MemDataAlignment

Specifies the Memory data width. This parameter can be a value of DMA Memory data size

Definition at line 84 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

uint32_t DMA_InitTypeDef::MemInc

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA Memory incremented mode

Definition at line 78 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Mode

Specifies the operation mode of the DMAy Channelx. This parameter can be a value of DMA mode

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel

Definition at line 87 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), and HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphDataAlignment

Specifies the Peripheral data width. This parameter can be a value of DMA Peripheral data size

Definition at line 81 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

uint32_t DMA_InitTypeDef::PeriphInc

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA Peripheral incremented mode

Definition at line 75 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Priority

Specifies the software priority for the DMAy Channelx. This parameter can be a value of DMA Priority level

Definition at line 92 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Request

Specifies the request selected for the specified channel. This parameter can be a value of DMA request

Definition at line 68 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dma.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: __DMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA_HandleTypeDef Struct Reference
DMA Exported Types

DMA handle Structure definition. More...

#include <stm32l4xx_hal_dma.h>

Data Fields

DMA_Channel_TypeDef * | Instance
DMA_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DMA_StateTypeDef | State
void * | Parent
void(* | XferCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferHalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferErrorCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferAbortCallback )(struct __DMA_HandleTypeDef *hdma)
__IO uint32_t | ErrorCode
DMA_TypeDef * | DmaBaseAddress
uint32_t | ChannelIndex

Detailed Description

DMA handle Structure definition.

Definition at line 133 of file stm32l4xx_hal_dma.h.

Field Documentation

uint32_t __DMA_HandleTypeDef::ChannelIndex

DMA Channel Index

Definition at line 157 of file stm32l4xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMA_TypeDef* __DMA_HandleTypeDef::DmaBaseAddress

DMA Channel Base Address

Definition at line 155 of file stm32l4xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

__IO uint32_t __DMA_HandleTypeDef::ErrorCode

DMA Error code

Definition at line 153 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetError(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), HAL_DMA_Start_IT(), and I2C_ITError().

DMA_InitTypeDef __DMA_HandleTypeDef::Init

DMA communication parameters

Definition at line 137 of file stm32l4xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_Init(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

DMA_Channel_TypeDef* __DMA_HandleTypeDef::Instance

Register base address

Definition at line 135 of file stm32l4xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SAI_DMARxCplt(), SAI_DMATxCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SWPMI_DMAReceiveCplt(), SWPMI_DMATransmitCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

HAL_LockTypeDef __DMA_HandleTypeDef::Lock

DMA locking object

Definition at line 139 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

void* __DMA_HandleTypeDef::Parent

Parent object state

Definition at line 143 of file stm32l4xx_hal_dma.h.

Referenced by I2C_DMAAbort(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), and USART_DMATxHalfCplt().

__IO HAL_DMA_StateTypeDef __DMA_HandleTypeDef::State

DMA transfer state

Definition at line 141 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetState(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_RegisterCallback(), HAL_DMA_Start(), HAL_DMA_Start_IT(), and HAL_DMA_UnRegisterCallback().

void(* __DMA_HandleTypeDef::XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer abort callback

Definition at line 151 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Abort_IT(), HAL_DMA_Init(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_IRQHandler(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_IRQHandler(), I2C_DMAAbort(), and I2C_ITError().

void(* __DMA_HandleTypeDef::XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete callback

Definition at line 145 of file stm32l4xx_hal_dma.h.

Referenced by CRYP_GCMCMAC_SetDMAConfig(), CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer error callback

Definition at line 149 of file stm32l4xx_hal_dma.h.

Referenced by CRYP_GCMCMAC_SetDMAConfig(), CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA Half transfer complete callback

Definition at line 147 of file stm32l4xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DAC_Start_DMA(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Transmit_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_dma.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Error Code

Defines
DMA Error Code
DMA Exported Constants

Defines

#define | HAL_DMA_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_DMA_ERROR_TE ((uint32_t)0x00000001)
#define | HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004)
#define | HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020)
#define | HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100)

Define Documentation

#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004)

no ongoing transfer

Definition at line 174 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 172 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100)

Not supported mode

Definition at line 176 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001)

Transfer error

Definition at line 173 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020)

Timeout error

Definition at line 175 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA request

Defines
DMA request
DMA Exported Constants

Defines

#define | DMA_REQUEST_0 ((uint32_t)0x00000000)
#define | DMA_REQUEST_1 ((uint32_t)0x00000001)
#define | DMA_REQUEST_2 ((uint32_t)0x00000002)
#define | DMA_REQUEST_3 ((uint32_t)0x00000003)
#define | DMA_REQUEST_4 ((uint32_t)0x00000004)
#define | DMA_REQUEST_5 ((uint32_t)0x00000005)
#define | DMA_REQUEST_6 ((uint32_t)0x00000006)
#define | DMA_REQUEST_7 ((uint32_t)0x00000007)

Define Documentation

#define DMA_REQUEST_0 ((uint32_t)0x00000000)

Definition at line 184 of file stm32l4xx_hal_dma.h.

#define DMA_REQUEST_1 ((uint32_t)0x00000001)

Definition at line 185 of file stm32l4xx_hal_dma.h.

#define DMA_REQUEST_2 ((uint32_t)0x00000002)

Definition at line 186 of file stm32l4xx_hal_dma.h.

#define DMA_REQUEST_3 ((uint32_t)0x00000003)

Definition at line 187 of file stm32l4xx_hal_dma.h.

#define DMA_REQUEST_4 ((uint32_t)0x00000004)

Definition at line 188 of file stm32l4xx_hal_dma.h.

#define DMA_REQUEST_5 ((uint32_t)0x00000005)

Definition at line 189 of file stm32l4xx_hal_dma.h.

#define DMA_REQUEST_6 ((uint32_t)0x00000006)

Definition at line 190 of file stm32l4xx_hal_dma.h.

#define DMA_REQUEST_7 ((uint32_t)0x00000007)

Definition at line 191 of file stm32l4xx_hal_dma.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Data transfer direction

Defines
DMA Data transfer direction
DMA Exported Constants

Defines

#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)

Define Documentation

#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)

Memory to memory direction

Definition at line 202 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)

Memory to peripheral direction

Definition at line 201 of file stm32l4xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_QSPI_Transmit_DMA(), HAL_SD_ReadBlocks_DMA(), and HAL_SD_WriteBlocks_DMA().

#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000)

Peripheral to memory direction

Definition at line 200 of file stm32l4xx_hal_dma.h.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_SD_ReadBlocks_DMA().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Peripheral incremented mode

Defines
DMA Peripheral incremented mode
DMA Exported Constants

Defines

#define | DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define DMA_PINC_DISABLE ((uint32_t)0x00000000)

Peripheral increment mode Disable

Definition at line 212 of file stm32l4xx_hal_dma.h.

#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)

Peripheral increment mode Enable

Definition at line 211 of file stm32l4xx_hal_dma.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Memory incremented mode

Defines
DMA Memory incremented mode
DMA Exported Constants

Defines

#define | DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define DMA_MINC_DISABLE ((uint32_t)0x00000000)

Memory increment mode Disable

Definition at line 221 of file stm32l4xx_hal_dma.h.

#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)

Memory increment mode Enable

Definition at line 220 of file stm32l4xx_hal_dma.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Peripheral data size

Defines
DMA Peripheral data size
DMA Exported Constants

Defines

#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)

Define Documentation

#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000)

Peripheral data alignment : Byte

Definition at line 229 of file stm32l4xx_hal_dma.h.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)

Peripheral data alignment : HalfWord

Definition at line 230 of file stm32l4xx_hal_dma.h.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)

Peripheral data alignment : Word

Definition at line 231 of file stm32l4xx_hal_dma.h.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Memory data size

Defines
DMA Memory data size
DMA Exported Constants

Defines

#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)

Define Documentation

#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000)

Memory data alignment : Byte

Definition at line 239 of file stm32l4xx_hal_dma.h.

#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)

Memory data alignment : HalfWord

Definition at line 240 of file stm32l4xx_hal_dma.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)

Memory data alignment : Word

Definition at line 241 of file stm32l4xx_hal_dma.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA mode

Defines
DMA mode
DMA Exported Constants

Defines

#define | DMA_NORMAL ((uint32_t)0x00000000)
#define | DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)

Define Documentation

#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)

Circular mode

Definition at line 250 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

#define DMA_NORMAL ((uint32_t)0x00000000)

Normal mode

Definition at line 249 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterRegularMsbStart_DMA(), and HAL_DFSDM_FilterRegularStart_DMA().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Priority level

Defines
DMA Priority level
DMA Exported Constants

Defines

#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)

Define Documentation

#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)

Priority level : High

Definition at line 260 of file stm32l4xx_hal_dma.h.

#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)

Priority level : Low

Definition at line 258 of file stm32l4xx_hal_dma.h.

#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)

Priority level : Medium

Definition at line 259 of file stm32l4xx_hal_dma.h.

#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)

Priority level : Very_High

Definition at line 261 of file stm32l4xx_hal_dma.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA interrupt enable definitions

Defines
DMA interrupt enable definitions
DMA Exported Constants

Defines

#define | DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)

Define Documentation

#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)

Definition at line 271 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)

Definition at line 270 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)

Definition at line 272 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA flag definitions

Defines
DMA flag definitions
DMA Exported Constants

Defines

#define | DMA_FLAG_GL1 ((uint32_t)0x00000001)
#define | DMA_FLAG_TC1 ((uint32_t)0x00000002)
#define | DMA_FLAG_HT1 ((uint32_t)0x00000004)
#define | DMA_FLAG_TE1 ((uint32_t)0x00000008)
#define | DMA_FLAG_GL2 ((uint32_t)0x00000010)
#define | DMA_FLAG_TC2 ((uint32_t)0x00000020)
#define | DMA_FLAG_HT2 ((uint32_t)0x00000040)
#define | DMA_FLAG_TE2 ((uint32_t)0x00000080)
#define | DMA_FLAG_GL3 ((uint32_t)0x00000100)
#define | DMA_FLAG_TC3 ((uint32_t)0x00000200)
#define | DMA_FLAG_HT3 ((uint32_t)0x00000400)
#define | DMA_FLAG_TE3 ((uint32_t)0x00000800)
#define | DMA_FLAG_GL4 ((uint32_t)0x00001000)
#define | DMA_FLAG_TC4 ((uint32_t)0x00002000)
#define | DMA_FLAG_HT4 ((uint32_t)0x00004000)
#define | DMA_FLAG_TE4 ((uint32_t)0x00008000)
#define | DMA_FLAG_GL5 ((uint32_t)0x00010000)
#define | DMA_FLAG_TC5 ((uint32_t)0x00020000)
#define | DMA_FLAG_HT5 ((uint32_t)0x00040000)
#define | DMA_FLAG_TE5 ((uint32_t)0x00080000)
#define | DMA_FLAG_GL6 ((uint32_t)0x00100000)
#define | DMA_FLAG_TC6 ((uint32_t)0x00200000)
#define | DMA_FLAG_HT6 ((uint32_t)0x00400000)
#define | DMA_FLAG_TE6 ((uint32_t)0x00800000)
#define | DMA_FLAG_GL7 ((uint32_t)0x01000000)
#define | DMA_FLAG_TC7 ((uint32_t)0x02000000)
#define | DMA_FLAG_HT7 ((uint32_t)0x04000000)
#define | DMA_FLAG_TE7 ((uint32_t)0x08000000)

Define Documentation

#define DMA_FLAG_GL1 ((uint32_t)0x00000001)

Definition at line 280 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_GL2 ((uint32_t)0x00000010)

Definition at line 284 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_GL3 ((uint32_t)0x00000100)

Definition at line 288 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_GL4 ((uint32_t)0x00001000)

Definition at line 292 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_GL5 ((uint32_t)0x00010000)

Definition at line 296 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_GL6 ((uint32_t)0x00100000)

Definition at line 300 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_GL7 ((uint32_t)0x01000000)

Definition at line 304 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_HT1 ((uint32_t)0x00000004)

Definition at line 282 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_HT2 ((uint32_t)0x00000040)

Definition at line 286 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_HT3 ((uint32_t)0x00000400)

Definition at line 290 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_HT4 ((uint32_t)0x00004000)

Definition at line 294 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_HT5 ((uint32_t)0x00040000)

Definition at line 298 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_HT6 ((uint32_t)0x00400000)

Definition at line 302 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_HT7 ((uint32_t)0x04000000)

Definition at line 306 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TC1 ((uint32_t)0x00000002)

Definition at line 281 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TC2 ((uint32_t)0x00000020)

Definition at line 285 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TC3 ((uint32_t)0x00000200)

Definition at line 289 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TC4 ((uint32_t)0x00002000)

Definition at line 293 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TC5 ((uint32_t)0x00020000)

Definition at line 297 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TC6 ((uint32_t)0x00200000)

Definition at line 301 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TC7 ((uint32_t)0x02000000)

Definition at line 305 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TE1 ((uint32_t)0x00000008)

Definition at line 283 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TE2 ((uint32_t)0x00000080)

Definition at line 287 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TE3 ((uint32_t)0x00000800)

Definition at line 291 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TE4 ((uint32_t)0x00008000)

Definition at line 295 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TE5 ((uint32_t)0x00080000)

Definition at line 299 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TE6 ((uint32_t)0x00800000)

Definition at line 303 of file stm32l4xx_hal_dma.h.

#define DMA_FLAG_TE7 ((uint32_t)0x08000000)

Definition at line 307 of file stm32l4xx_hal_dma.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Exported Macros

Defines
DMA Exported Macros
DMA

Defines

#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Channel pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enable the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disable the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Check whether the specified DMA Channel interrupt is enabled or not.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Return the number of remaining data units in the current DMA Channel transfer.

Define Documentation

#define __HAL_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
 (DMA2->IFCR |= (__FLAG__)) : (DMA1->IFCR |= (__FLAG__)))

Clear the DMA Channel pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx: Transfer complete flag
  • DMA_FLAG_HTx: Half transfer complete flag
  • DMA_FLAG_TEx: Transfer error flag
  • DMA_FLAG_GLx: Global interrupt flag Where x can be from 1 to 7 to select the DMA Channel x flag.
Return values:
None

Definition at line 452 of file stm32l4xx_hal_dma.h.

#define __HAL_DMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)

Disable the specified DMA Channel.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 339 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Start(), HAL_DMA_Start_IT(), and HAL_QSPI_IRQHandler().

#define __HAL_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))

Disable the specified DMA Channel interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 477 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define __HAL_DMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)

Enable the specified DMA Channel.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 332 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define __HAL_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))

Enable the specified DMA Channel interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 465 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Start_IT().

#define __HAL_DMA_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNDTR)

Return the number of remaining data units in the current DMA Channel transfer.

Parameters:
__HANDLE__,: DMA handle
Return values:
The number of remaining data units in the current DMA Channel transfer.

Definition at line 496 of file stm32l4xx_hal_dma.h.

#define __HAL_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))

Get the DMA Channel pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx: Transfer complete flag
  • DMA_FLAG_HTx: Half transfer complete flag
  • DMA_FLAG_TEx: Transfer error flag
  • DMA_FLAG_GLx: Global interrupt flag Where x can be from 1 to 7 to select the DMA Channel x flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 437 of file stm32l4xx_hal_dma.h.

#define __HAL_DMA_GET_GI_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
   DMA_ISR_GIF7)

Return the current DMA Channel Global interrupt flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer error flag index.

Definition at line 410 of file stm32l4xx_hal_dma.h.

#define __HAL_DMA_GET_HT_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
   DMA_FLAG_HT7)

Return the current DMA Channel half transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified half transfer complete flag index.

Definition at line 370 of file stm32l4xx_hal_dma.h.

#define __HAL_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))

Check whether the specified DMA Channel interrupt is enabled or not.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt source to check. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
The state of DMA_IT (SET or RESET).

Definition at line 489 of file stm32l4xx_hal_dma.h.

#define __HAL_DMA_GET_TC_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
   DMA_FLAG_TC7)

Return the current DMA Channel transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer complete flag index.

Definition at line 350 of file stm32l4xx_hal_dma.h.

#define __HAL_DMA_GET_TE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
   DMA_FLAG_TE7)

Return the current DMA Channel transfer error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer error flag index.

Definition at line 390 of file stm32l4xx_hal_dma.h.

#define __HAL_DMA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

Reset DMA handle state.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 325 of file stm32l4xx_hal_dma.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_ALL_REQUEST(REQUEST)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Define Documentation

#define IS_DMA_ALL_REQUEST ( REQUEST )
Value:
(((REQUEST) == DMA_REQUEST_0) || \
                                     ((REQUEST) == DMA_REQUEST_1) || \
                                     ((REQUEST) == DMA_REQUEST_2) || \
                                     ((REQUEST) == DMA_REQUEST_3) || \
                                     ((REQUEST) == DMA_REQUEST_4) || \
                                     ((REQUEST) == DMA_REQUEST_5) || \
                                     ((REQUEST) == DMA_REQUEST_6) || \
                                     ((REQUEST) == DMA_REQUEST_7))

Definition at line 566 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))

Definition at line 558 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define IS_DMA_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

Definition at line 554 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                       ((SIZE) == DMA_MDATAALIGN_WORD ))

Definition at line 579 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MINC_ENABLE)  || \
                                        ((STATE) == DMA_MINC_DISABLE))

Definition at line 563 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MODE ( MODE )
Value:
(((MODE) == DMA_NORMAL )  || \
                           ((MODE) == DMA_CIRCULAR))

Definition at line 583 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                           ((SIZE) == DMA_PDATAALIGN_WORD))

Definition at line 575 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PINC_ENABLE) || \
                                            ((STATE) == DMA_PINC_DISABLE))

Definition at line 560 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

Definition at line 586 of file stm32l4xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization Functions

Functions
Initialization Functions
FIREWALL Exported Functions

Initialization and Configuration Functions. More...

Functions

HAL_StatusTypeDef | HAL_FIREWALL_Config (FIREWALL_InitTypeDef *fw_init)
Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters.
void | HAL_FIREWALL_GetConfig (FIREWALL_InitTypeDef *fw_config)
Retrieve the Firewall configuration.
void | HAL_FIREWALL_EnableFirewall (void)
Enable FIREWALL.
void | HAL_FIREWALL_EnablePreArmFlag (void)
Enable FIREWALL pre arm.
void | HAL_FIREWALL_DisablePreArmFlag (void)
Disable FIREWALL pre arm.

Detailed Description

Initialization and Configuration Functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides the functions allowing to initialize the Firewall.
    Initialization is done by HAL_FIREWALL_Config():

      (+) Enable the Firewall clock thru __HAL_RCC_FIREWALL_CLK_ENABLE() macro.

      (+) Set the protected code segment address start and length.

      (+) Set the protected non-volatile and/or volatile data segments
          address starts and lengths if applicable.

      (+) Set the volatile data segment execution and sharing status.

      (+) Length must be set to 0 for an unprotected segment.

Function Documentation

HAL_StatusTypeDef HAL_FIREWALL_Config ( FIREWALL_InitTypeDef * fw_init )

Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters.

Parameters:
fw_init,: Firewall initialization structure
Note:
The API returns HAL_ERROR if the Firewall is already enabled.
Return values:
HAL status

Definition at line 121 of file stm32l4xx_hal_firewall.c.

References __HAL_FIREWALL_IS_ENABLED, __HAL_RCC_FIREWALL_CLK_ENABLE, assert_param, FIREWALL_InitTypeDef::CodeSegmentLength, FIREWALL_InitTypeDef::CodeSegmentStartAddress, IS_FIREWALL_CODE_SEGMENT_ADDRESS, IS_FIREWALL_CODE_SEGMENT_LENGTH, IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS, IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH, IS_FIREWALL_VOLATILEDATA_EXECUTE, IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS, IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH, IS_FIREWALL_VOLATILEDATA_SHARE, FIREWALL_InitTypeDef::NonVDataSegmentLength, FIREWALL_InitTypeDef::NonVDataSegmentStartAddress, FIREWALL_InitTypeDef::VDataSegmentLength, FIREWALL_InitTypeDef::VDataSegmentStartAddress, FIREWALL_InitTypeDef::VolatileDataExecution, and FIREWALL_InitTypeDef::VolatileDataShared.

void HAL_FIREWALL_DisablePreArmFlag ( void )

Disable FIREWALL pre arm.

Note:
When FPA bit is reset, any code executed outside the protected segment when the Firewall is opened will generate a system reset.
This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro but can't be executed inside a code area protected by the Firewall.
When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.
When the Firewall is enabled and NVDSL register is equal to 0 (that is, when the non volatile data segment is not defined), ** this API can be executed when the Firewall is closed ** when the Firewall is opened, user should resort to __HAL_FIREWALL_PREARM_DISABLE() macro instead
When the Firewall is enabled and NVDSL register is different from 0 (that is, when the non volatile data segment is defined) ** FW_CR register can be accessed only when the Firewall is opened: user should resort to __HAL_FIREWALL_PREARM_DISABLE() macro instead.
Return values:
None

Definition at line 285 of file stm32l4xx_hal_firewall.c.

void HAL_FIREWALL_EnableFirewall ( void )

Enable FIREWALL.

Note:
Firewall is enabled in clearing FWDIS bit of SYSCFG CFGR1 register. Once enabled, the Firewall cannot be disabled by software. Only a system reset can set again FWDIS bit.
Return values:
None

Definition at line 234 of file stm32l4xx_hal_firewall.c.

void HAL_FIREWALL_EnablePreArmFlag ( void )

Enable FIREWALL pre arm.

Note:
When FPA bit is set, any code executed outside the protected segment will close the Firewall.
This API provides the same service as __HAL_FIREWALL_PREARM_ENABLE() macro but can't be executed inside a code area protected by the Firewall.
When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.
When the Firewall is enabled and NVDSL register is equal to 0 (that is, when the non volatile data segment is not defined), ** this API can be executed when the Firewall is closed ** when the Firewall is opened, user should resort to __HAL_FIREWALL_PREARM_ENABLE() macro instead
When the Firewall is enabled and NVDSL register is different from 0 (that is, when the non volatile data segment is defined) ** FW_CR register can be accessed only when the Firewall is opened: user should resort to __HAL_FIREWALL_PREARM_ENABLE() macro instead.
Return values:
None

Definition at line 259 of file stm32l4xx_hal_firewall.c.

void HAL_FIREWALL_GetConfig ( FIREWALL_InitTypeDef * fw_config )

Retrieve the Firewall configuration.

Parameters:
fw_config,: Firewall configuration, type is same as initialization structure
Note:
This API can't be executed inside a code area protected by the Firewall when the Firewall is enabled
If NVDSL register is different from 0, that is, if the non volatile data segment is defined, this API can't be executed when the Firewall is enabled.
User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status
Return values:
None

Definition at line 197 of file stm32l4xx_hal_firewall.c.

References __HAL_RCC_FIREWALL_CLK_ENABLE, FIREWALL_InitTypeDef::CodeSegmentLength, FIREWALL_InitTypeDef::CodeSegmentStartAddress, FIREWALL_InitTypeDef::NonVDataSegmentLength, FIREWALL_InitTypeDef::NonVDataSegmentStartAddress, FIREWALL_InitTypeDef::VDataSegmentLength, FIREWALL_InitTypeDef::VDataSegmentStartAddress, FIREWALL_InitTypeDef::VolatileDataExecution, and FIREWALL_InitTypeDef::VolatileDataShared.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FIREWALL_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FIREWALL_InitTypeDef Struct Reference
FIREWALL Exported Types

FIREWALL Initialization Structure definition. More...

#include <stm32l4xx_hal_firewall.h>

Data Fields

uint32_t | CodeSegmentStartAddress
uint32_t | CodeSegmentLength
uint32_t | NonVDataSegmentStartAddress
uint32_t | NonVDataSegmentLength
uint32_t | VDataSegmentStartAddress
uint32_t | VDataSegmentLength
uint32_t | VolatileDataExecution
uint32_t | VolatileDataShared

Detailed Description

FIREWALL Initialization Structure definition.

Definition at line 65 of file stm32l4xx_hal_firewall.h.

Field Documentation

uint32_t FIREWALL_InitTypeDef::CodeSegmentLength

Protected code segment length in bytes. This value is 22-bit long, the 8 LSB bits are reserved and forced to 0 for the length to be a multiple of 256 bytes.

Definition at line 70 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config(), and HAL_FIREWALL_GetConfig().

uint32_t FIREWALL_InitTypeDef::CodeSegmentStartAddress

Protected code segment start address. This value is 24-bit long, the 8 LSB bits are reserved and forced to 0 in order to allow a 256-byte granularity.

Definition at line 67 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config(), and HAL_FIREWALL_GetConfig().

uint32_t FIREWALL_InitTypeDef::NonVDataSegmentLength

Protected non-volatile data segment length in bytes. This value is 22-bit long, the 8 LSB bits are reserved and forced to 0 for the length to be a multiple of 256 bytes.

Definition at line 76 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config(), and HAL_FIREWALL_GetConfig().

uint32_t FIREWALL_InitTypeDef::NonVDataSegmentStartAddress

Protected non-volatile data segment start address. This value is 24-bit long, the 8 LSB bits are reserved and forced to 0 in order to allow a 256-byte granularity.

Definition at line 73 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config(), and HAL_FIREWALL_GetConfig().

uint32_t FIREWALL_InitTypeDef::VDataSegmentLength

Protected volatile data segment length in bytes. This value is 17-bit long, the 6 LSB bits are reserved and forced to 0 for the length to be a multiple of 64 bytes.

Definition at line 82 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config(), and HAL_FIREWALL_GetConfig().

uint32_t FIREWALL_InitTypeDef::VDataSegmentStartAddress

Protected volatile data segment start address. This value is 17-bit long, the 6 LSB bits are reserved and forced to 0 in order to allow a 64-byte granularity.

Definition at line 79 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config(), and HAL_FIREWALL_GetConfig().

uint32_t FIREWALL_InitTypeDef::VolatileDataExecution

Set VDE bit specifying whether or not the volatile data segment can be executed. When VDS = 1 (set by parameter VolatileDataShared), VDE bit has no meaning. This parameter can be a value of FIREWALL volatile data segment execution status

Definition at line 85 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config(), and HAL_FIREWALL_GetConfig().

uint32_t FIREWALL_InitTypeDef::VolatileDataShared

Set VDS bit in specifying whether or not the volatile data segment can be shared with a non-protected application code. This parameter can be a value of FIREWALL volatile data segment share status

Definition at line 89 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config(), and HAL_FIREWALL_GetConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_firewall.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FIREWALL volatile data segment execution status

Defines
FIREWALL volatile data segment execution status
FIREWALL Exported Constants

Defines

#define | FIREWALL_VOLATILEDATA_NOT_EXECUTABLE ((uint32_t)0x0000)
#define | FIREWALL_VOLATILEDATA_EXECUTABLE ((uint32_t)FW_CR_VDE)

Define Documentation

#define FIREWALL_VOLATILEDATA_EXECUTABLE ((uint32_t)FW_CR_VDE)

Definition at line 110 of file stm32l4xx_hal_firewall.h.

#define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE ((uint32_t)0x0000)

Definition at line 109 of file stm32l4xx_hal_firewall.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FIREWALL volatile data segment share status

Defines
FIREWALL volatile data segment share status
FIREWALL Exported Constants

Defines

#define | FIREWALL_VOLATILEDATA_NOT_SHARED ((uint32_t)0x0000)
#define | FIREWALL_VOLATILEDATA_SHARED ((uint32_t)FW_CR_VDS)

Define Documentation

#define FIREWALL_VOLATILEDATA_NOT_SHARED ((uint32_t)0x0000)

Definition at line 118 of file stm32l4xx_hal_firewall.h.

#define FIREWALL_VOLATILEDATA_SHARED ((uint32_t)FW_CR_VDS)

Definition at line 119 of file stm32l4xx_hal_firewall.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FIREWALL pre arm status

Defines
FIREWALL pre arm status
FIREWALL Exported Constants

Defines

#define | FIREWALL_PRE_ARM_RESET ((uint32_t)0x0000)
#define | FIREWALL_PRE_ARM_SET ((uint32_t)FW_CR_FPA)

Define Documentation

#define FIREWALL_PRE_ARM_RESET ((uint32_t)0x0000)

Definition at line 127 of file stm32l4xx_hal_firewall.h.

#define FIREWALL_PRE_ARM_SET ((uint32_t)FW_CR_FPA)

Definition at line 128 of file stm32l4xx_hal_firewall.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FIREWALL Private Macros

Defines
FIREWALL Private Macros
FIREWALL

Defines

#define | IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
#define | IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
#define | IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
#define | IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
#define | IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= SRAM1_BASE) && ((ADDRESS) < (SRAM1_BASE + SRAM1_SIZE_MAX)))
#define | IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM1_BASE + SRAM1_SIZE_MAX))
#define | IS_FIREWALL_VOLATILEDATA_SHARE(SHARE)
#define | IS_FIREWALL_VOLATILEDATA_EXECUTE(EXECUTE)

Define Documentation

#define IS_FIREWALL_CODE_SEGMENT_ADDRESS ( ADDRESS ) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))

Definition at line 142 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config().

#define IS_FIREWALL_CODE_SEGMENT_LENGTH | ( | ADDRESS,
 |  | LENGTH
 | ) | (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))

Definition at line 143 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config().

#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS ( ADDRESS ) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))

Definition at line 145 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config().

#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH | ( | ADDRESS,
 |  | LENGTH
 | ) | (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))

Definition at line 146 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config().

#define IS_FIREWALL_VOLATILEDATA_EXECUTE ( EXECUTE )
Value:
(((EXECUTE) == FIREWALL_VOLATILEDATA_NOT_EXECUTABLE) || \
                                                   ((EXECUTE) == FIREWALL_VOLATILEDATA_EXECUTABLE))

Definition at line 155 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config().

#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS ( ADDRESS ) (((ADDRESS) >= SRAM1_BASE) && ((ADDRESS) < (SRAM1_BASE + SRAM1_SIZE_MAX)))

Definition at line 148 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config().

#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH | ( | ADDRESS,
 |  | LENGTH
 | ) | (((ADDRESS) + (LENGTH)) <= (SRAM1_BASE + SRAM1_SIZE_MAX))

Definition at line 149 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config().

#define IS_FIREWALL_VOLATILEDATA_SHARE ( SHARE )
Value:
(((SHARE) == FIREWALL_VOLATILEDATA_NOT_SHARED) || \
                                               ((SHARE) == FIREWALL_VOLATILEDATA_SHARED))

Definition at line 152 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FIREWALL Exported Macros

Defines
FIREWALL Exported Macros
FIREWALL

Defines

#define | __HAL_FIREWALL_IS_ENABLED() HAL_IS_BIT_CLR(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS)
Check whether the FIREWALL is enabled or not.
#define | __HAL_FIREWALL_PREARM_ENABLE()
Enable FIREWALL pre arm.
#define | __HAL_FIREWALL_PREARM_DISABLE()
Disable FIREWALL pre arm.
#define | __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE()
Enable volatile data sharing in setting VDS bit.
#define | __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE()
Disable volatile data sharing in resetting VDS bit.
#define | __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE()
Enable volatile data execution in setting VDE bit.
#define | __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE()
Disable volatile data execution in resetting VDE bit.
#define | __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FIREWALL->CR & FW_CR_VDS) == FW_CR_VDS)
Check whether or not the volatile data segment is shared.
#define | __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FIREWALL->CR & FW_CR_VDE) == FW_CR_VDE)
Check whether or not the volatile data segment is declared executable.
#define | __HAL_FIREWALL_GET_PREARM() ((FIREWALL->CR & FW_CR_FPA) == FW_CR_FPA)
Check whether or not the Firewall pre arm bit is set.

Define Documentation

#define __HAL_FIREWALL_GET_PREARM ( ) ((FIREWALL->CR & FW_CR_FPA) == FW_CR_FPA)

Check whether or not the Firewall pre arm bit is set.

Note:
This macro can be executed inside a code area protected by the Firewall.
This macro can be executed whatever the Firewall state (opened or closed) when NVDSL register is equal to 0. Otherwise (when NVDSL register is different from 0, that is, when the non volatile data segment is defined), the macro can be executed only when the Firewall is opened.
Return values:
FPA bit setting status (TRUE or FALSE).

Definition at line 325 of file stm32l4xx_hal_firewall.h.

#define __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION ( ) ((FIREWALL->CR & FW_CR_VDE) == FW_CR_VDE)

Check whether or not the volatile data segment is declared executable.

Note:
This macro can be executed inside a code area protected by the Firewall.
This macro can be executed whatever the Firewall state (opened or closed) when NVDSL register is equal to 0. Otherwise (when NVDSL register is different from 0, that is, when the non volatile data segment is defined), the macro can be executed only when the Firewall is opened.
Return values:
VDE bit setting status (TRUE or FALSE).

Definition at line 315 of file stm32l4xx_hal_firewall.h.

#define __HAL_FIREWALL_GET_VOLATILEDATA_SHARED ( ) ((FIREWALL->CR & FW_CR_VDS) == FW_CR_VDS)

Check whether or not the volatile data segment is shared.

Note:
This macro can be executed inside a code area protected by the Firewall.
This macro can be executed whatever the Firewall state (opened or closed) when NVDSL register is equal to 0. Otherwise (when NVDSL register is different from 0, that is, when the non volatile data segment is defined), the macro can be executed only when the Firewall is opened.
Return values:
VDS bit setting status (TRUE or FALSE).

Definition at line 305 of file stm32l4xx_hal_firewall.h.

#define __HAL_FIREWALL_IS_ENABLED ( ) HAL_IS_BIT_CLR(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS)

Check whether the FIREWALL is enabled or not.

Return values:
FIREWALL enabling status (TRUE or FALSE).

Definition at line 170 of file stm32l4xx_hal_firewall.h.

Referenced by HAL_FIREWALL_Config().

#define __HAL_FIREWALL_PREARM_DISABLE ( )
Value:
do {                                                              \
                  __IO uint32_t tmpreg;                                        \
                  CLEAR_BIT(FIREWALL->CR, FW_CR_FPA) ;                         \
                  /* Read bit back to ensure it is taken into account by IP */ \
                  /* (introduce proper delay inside macro execution) */        \
                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                 \
                  UNUSED(tmpreg);                                              \
                } while(0)

Disable FIREWALL pre arm.

Note:
When FPA bit is set, any code executed outside the protected segment closes the Firewall, otherwise, it generates a system reset.
This macro provides the same service as HAL_FIREWALL_DisablePreArmFlag() API but can be executed inside a code area protected by the Firewall.
This macro can be executed whatever the Firewall state (opened or closed) when NVDSL register is equal to 0. Otherwise (when NVDSL register is different from 0, that is, when the non volatile data segment is defined), the macro can be executed only when the Firewall is opened.

Definition at line 205 of file stm32l4xx_hal_firewall.h.

#define __HAL_FIREWALL_PREARM_ENABLE ( )
Value:
do {                                                              \
                  __IO uint32_t tmpreg;                                        \
                  SET_BIT(FIREWALL->CR, FW_CR_FPA) ;                           \
                  /* Read bit back to ensure it is taken into account by IP */ \
                  /* (introduce proper delay inside macro execution) */        \
                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                 \
                  UNUSED(tmpreg);                                              \
                } while(0)

Enable FIREWALL pre arm.

Note:
When FPA bit is set, any code executed outside the protected segment closes the Firewall, otherwise it generates a system reset.
This macro provides the same service as HAL_FIREWALL_EnablePreArmFlag() API but can be executed inside a code area protected by the Firewall.
This macro can be executed whatever the Firewall state (opened or closed) when NVDSL register is equal to 0. Otherwise (when NVDSL register is different from 0, that is, when the non volatile data segment is defined), the macro can be executed only when the Firewall is opened.

Definition at line 183 of file stm32l4xx_hal_firewall.h.

#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE ( )
Value:
do {                                                              \
                  __IO uint32_t tmpreg;                                        \
                  CLEAR_BIT(FIREWALL->CR, FW_CR_VDE) ;                         \
                  /* Read bit back to ensure it is taken into account by IP */ \
                  /* (introduce proper delay inside macro execution) */        \
                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                 \
                  UNUSED(tmpreg);                                              \
                } while(0)

Disable volatile data execution in resetting VDE bit.

Note:
VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be executed whatever the VDE bit value.
When VDE bit is reset (with VDS = 0), the volatile data segment cannot be executed.
This macro can be executed inside a code area protected by the Firewall.
This macro can be executed whatever the Firewall state (opened or closed) when NVDSL register is equal to 0. Otherwise (when NVDSL register is different from 0, that is, when the non volatile data segment is defined), the macro can be executed only when the Firewall is opened.

Definition at line 286 of file stm32l4xx_hal_firewall.h.

#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE ( )
Value:
do {                                                              \
                  __IO uint32_t tmpreg;                                        \
                  SET_BIT(FIREWALL->CR, FW_CR_VDE) ;                           \
                  /* Read bit back to ensure it is taken into account by IP */ \
                  /* (introduce proper delay inside macro execution) */        \
                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                 \
                  UNUSED(tmpreg);                                              \
                } while(0)

Enable volatile data execution in setting VDE bit.

Note:
VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be executed whatever the VDE bit value.
When VDE bit is set (with VDS = 0), the volatile data segment is executable. When the Firewall call is closed, a "call gate" entry procedure is required to open first the Firewall.
This macro can be executed inside a code area protected by the Firewall.
This macro can be executed whatever the Firewall state (opened or closed) when NVDSL register is equal to 0. Otherwise (when NVDSL register is different from 0, that is, when the non volatile data segment is defined), the macro can be executed only when the Firewall is opened.

Definition at line 266 of file stm32l4xx_hal_firewall.h.

#define __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE ( )
Value:
do {                                                              \
                  __IO uint32_t tmpreg;                                        \
                  CLEAR_BIT(FIREWALL->CR, FW_CR_VDS) ;                         \
                  /* Read bit back to ensure it is taken into account by IP */ \
                  /* (introduce proper delay inside macro execution) */        \
                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                 \
                  UNUSED(tmpreg);                                              \
                } while(0)

Disable volatile data sharing in resetting VDS bit.

Note:
When VDS bit is reset, the volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed. If it is accessed in such a condition, a system reset is generated by the Firewall.
This macro can be executed inside a code area protected by the Firewall.
This macro can be executed whatever the Firewall state (opened or closed) when NVDSL register is equal to 0. Otherwise (when NVDSL register is different from 0, that is, when the non volatile data segment is defined), the macro can be executed only when the Firewall is opened.

Definition at line 244 of file stm32l4xx_hal_firewall.h.

#define __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE ( )
Value:
do {                                                              \
                  __IO uint32_t tmpreg;                                        \
                  SET_BIT(FIREWALL->CR, FW_CR_VDS) ;                           \
                  /* Read bit back to ensure it is taken into account by IP */ \
                  /* (introduce proper delay inside macro execution) */        \
                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                 \
                  UNUSED(tmpreg);                                              \
                } while(0)

Enable volatile data sharing in setting VDS bit.

Note:
When VDS bit is set, the volatile data segment is shared with non-protected application code. It can be accessed whatever the Firewall state (opened or closed).
This macro can be executed inside a code area protected by the Firewall.
This macro can be executed whatever the Firewall state (opened or closed) when NVDSL register is equal to 0. Otherwise (when NVDSL register is different from 0, that is, when the non volatile data segment is defined), the macro can be executed only when the Firewall is opened.

Definition at line 224 of file stm32l4xx_hal_firewall.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH Private Variables

Variables
FLASH Private Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Variable Documentation

FLASH_ProcessTypeDef pFlash

Variable used for Program/Erase sectors under interruption.

Definition at line 131 of file stm32l4xx_hal_flash.c.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH Private Functions

Functions
FLASH Private Functions
FLASH

Functions

HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
void | FLASH_PageErase (uint32_t Page, uint32_t Banks)
Erase the specified FLASH memory page.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.
static void | FLASH_SetErrorCode (void)
Set the specific FLASH error flag.
static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program double-word (64-bit) at a specified address.
static void | FLASH_Program_Fast (uint32_t Address, uint32_t DataAddress)
Fast program a 32 row double-word (64-bit) at a specified address.

Function Documentation

void FLASH_FlushCaches ( void )

Flush the instruction and data caches.

Return values:
None

Definition at line 430 of file stm32l4xx_hal_flash_ex.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, __HAL_FLASH_DATA_CACHE_ENABLE, __HAL_FLASH_DATA_CACHE_RESET, __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_INSTRUCTION_CACHE_ENABLE, and __HAL_FLASH_INSTRUCTION_CACHE_RESET.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase().

void FLASH_PageErase | ( | uint32_t | Page,
 |  | uint32_t | Banks
 | ) |  |

Erase the specified FLASH memory page.

Parameters:
Page,: FLASH page to erase This parameter must be a value between 0 and (max number of pages in the bank - 1)
Banks,: Bank(s) where the page will be erased This parameter can be one or a combination of the following values:
  • FLASH_BANK_1: Page in bank 1 to be erased
  • FLASH_BANK_2: Page in bank 2 to be erased
Return values:
None

Definition at line 403 of file stm32l4xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, IS_FLASH_BANK_EXCLUSIVE, and IS_FLASH_PAGE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static void FLASH_Program_DoubleWord | ( | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  | [static]

Program double-word (64-bit) at a specified address.

Parameters:
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed.
Return values:
None

Definition at line 734 of file stm32l4xx_hal_flash.c.

References assert_param, and IS_FLASH_PROGRAM_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_Program_Fast | ( | uint32_t | Address,
 |  | uint32_t | DataAddress
 | ) |  | [static]

Fast program a 32 row double-word (64-bit) at a specified address.

Parameters:
Address,: specifies the address to be programmed.
DataAddress,: specifies the address where the data are stored.
Return values:
None

Definition at line 753 of file stm32l4xx_hal_flash.c.

References assert_param, and IS_FLASH_MAIN_MEM_ADDRESS.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_SetErrorCode ( void ) [static]

Set the specific FLASH error flag.

Return values:
None

Definition at line 659 of file stm32l4xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_ALL_ERRORS, FLASH_FLAG_ECCD, FLASH_FLAG_FASTERR, FLASH_FLAG_MISERR, FLASH_FLAG_OPERR, FLASH_FLAG_OPTVERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGSERR, FLASH_FLAG_PROGERR, FLASH_FLAG_RDERR, FLASH_FLAG_SIZERR, FLASH_FLAG_WRPERR, HAL_FLASH_ERROR_ECCD, HAL_FLASH_ERROR_FAST, HAL_FLASH_ERROR_MIS, HAL_FLASH_ERROR_OP, HAL_FLASH_ERROR_OPTV, HAL_FLASH_ERROR_PGA, HAL_FLASH_ERROR_PGS, HAL_FLASH_ERROR_PROG, HAL_FLASH_ERROR_RD, HAL_FLASH_ERROR_SIZ, and HAL_FLASH_ERROR_WRP.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout,: maximum flash operation timeout
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 608 of file stm32l4xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_FLAG_BSY, FLASH_FLAG_ECCD, FLASH_FLAG_EOP, FLASH_FLAG_FASTERR, FLASH_FLAG_MISERR, FLASH_FLAG_OPERR, FLASH_FLAG_OPTVERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGSERR, FLASH_FLAG_PROGERR, FLASH_FLAG_RDERR, FLASH_FLAG_SIZERR, FLASH_FLAG_WRPERR, FLASH_SetErrorCode(), and HAL_GetTick().

Referenced by FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRPConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), and HAL_FLASHEx_Erase().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Programming operation functions

Functions
Programming operation functions
FLASH Exported Functions

Programming operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Detailed Description

Programming operation functions.

 ===============================================================================
                  ##### Programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the FLASH
    program operations.

Function Documentation

void HAL_FLASH_EndOfOperationCallback ( uint32_t ReturnValue )

FLASH end of operation interrupt callback.

Parameters:
ReturnValue,: The value saved in this parameter depends on the ongoing procedure Mass Erase: Bank number which has been requested to erase Page Erase: Page which has been erased (if 0xFFFFFFFF, it means that all the selected pages have been erased) Program: Address which was selected for data program
Return values:
None

Definition at line 419 of file stm32l4xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

void HAL_FLASH_IRQHandler ( void )

Handle FLASH interrupt request.

Return values:
None

Definition at line 288 of file stm32l4xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_DISABLE_IT, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::Address, FLASH_ProcessTypeDef::Bank, FLASH_FLAG_ECCD, FLASH_FLAG_EOP, FLASH_FLAG_FASTERR, FLASH_FLAG_MISERR, FLASH_FLAG_OPERR, FLASH_FLAG_OPTVERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGSERR, FLASH_FLAG_PROGERR, FLASH_FLAG_RDERR, FLASH_FLAG_SIZERR, FLASH_FLAG_WRPERR, FLASH_FlushCaches(), FLASH_IT_EOP, FLASH_IT_OPERR, FLASH_PageErase(), FLASH_PROC_MASS_ERASE, FLASH_PROC_NONE, FLASH_PROC_PAGE_ERASE, FLASH_PROC_PROGRAM, FLASH_PROC_PROGRAM_LAST, FLASH_SetErrorCode(), HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), FLASH_ProcessTypeDef::NbPagesToErase, FLASH_ProcessTypeDef::Page, and FLASH_ProcessTypeDef::ProcedureOnGoing.

void HAL_FLASH_OperationErrorCallback ( uint32_t ReturnValue )

FLASH operation error interrupt callback.

Parameters:
ReturnValue,: The value saved in this parameter depends on the ongoing procedure Mass Erase: Bank number which has been requested to erase Page Erase: Page number which returned an error Program: Address which was selected for data program
Return values:
None

Definition at line 437 of file stm32l4xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program double word or fast program of a row at a specified address.

Parameters:
TypeProgram,: Indicate the way to program at a specified address. This parameter can be a value of FLASH Program Type
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed This parameter is the data for the double word program and the address where are stored the data for the row fast program
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 181 of file stm32l4xx_hal_flash.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_Program_DoubleWord(), FLASH_Program_Fast(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_TYPEPROGRAM_FAST, FLASH_TYPEPROGRAM_FAST_AND_LAST, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program double word or fast program of a row at a specified address with interrupt enabled.

Parameters:
TypeProgram,: Indicate the way to program at a specified address. This parameter can be a value of FLASH Program Type
Address,: specifies the address to be programmed.
Data,: specifies the data to be programmed This parameter is the data for the double word program and the address where are stored the data for the row fast program
Return values:
HAL Status

Definition at line 244 of file stm32l4xx_hal_flash.c.

References __HAL_FLASH_ENABLE_IT, FLASH_ProcessTypeDef::Address, assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_IT_EOP, FLASH_IT_OPERR, FLASH_PROC_PROGRAM, FLASH_PROC_PROGRAM_LAST, FLASH_Program_DoubleWord(), FLASH_Program_Fast(), FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_TYPEPROGRAM_FAST, FLASH_TYPEPROGRAM_FAST_AND_LAST, HAL_FLASH_ERROR_NONE, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FLASH Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Lock the FLASH control register access.

Return values:
HAL Status

Definition at line 490 of file stm32l4xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option byte loading.

Return values:
HAL Status

Definition at line 534 of file stm32l4xx_hal_flash.c.

References FLASH_TIMEOUT_VALUE, and FLASH_WaitForLastOperation().

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Bytes Registers access.

Return values:
HAL Status

Definition at line 522 of file stm32l4xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Bytes Registers access.

Return values:
HAL Status

Definition at line 502 of file stm32l4xx_hal_flash.c.

References FLASH_OPTKEY1, and FLASH_OPTKEY2.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control register access.

Return values:
HAL Status

Definition at line 470 of file stm32l4xx_hal_flash.c.

References FLASH_KEY1, and FLASH_KEY2.

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STM32L486xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
FLASH Exported Functions

Peripheral Errors functions. More...

Functions

uint32_t HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Detailed Description

Peripheral Errors functions.

 ===============================================================================
                ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time Errors of the FLASH peripheral.

Function Documentation

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
FLASH_ErrorCode,: The returned value can be:
  • HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
  • HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
  • HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
  • HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
  • HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
  • HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
  • HAL_FLASH_ERROR_NONE: No error set
  • HAL_FLASH_ERROR_OP: FLASH Operation error
  • HAL_FLASH_ERROR_PROG: FLASH Programming error
  • HAL_FLASH_ERROR_WRP: FLASH Write protection error
  • HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
  • HAL_FLASH_ERROR_SIZ: FLASH Size error
  • HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
  • HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
  • HAL_FLASH_ERROR_FAST: FLASH Fast programming error
  • HAL_FLASH_ERROR_RD: FLASH PCROP read error
  • HAL_FLASH_ERROR_OPTV: FLASH Option validity error
  • FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
  • HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected

Definition at line 584 of file stm32l4xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

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STM32L486xx HAL User Manual: FLASH Exported Types

Data Structures | Enumerations
FLASH Exported Types
FLASH

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0, FLASH_PROC_PAGE_ERASE, FLASH_PROC_MASS_ERASE, FLASH_PROC_PROGRAM,
FLASH_PROC_PROGRAM_LAST
}
FLASH Procedure structure definition. More...

Enumeration Type Documentation

enum FLASH_ProcedureTypeDef

FLASH Procedure structure definition.

Enumerator:
FLASH_PROC_NONE
FLASH_PROC_PAGE_ERASE
FLASH_PROC_MASS_ERASE
FLASH_PROC_PROGRAM
FLASH_PROC_PROGRAM_LAST

Definition at line 119 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH_EraseInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_EraseInitTypeDef Struct Reference
FLASH Exported Types

FLASH Erase structure definition. More...

#include <stm32l4xx_hal_flash.h>

Data Fields

uint32_t | TypeErase
uint32_t | Banks
uint32_t | Page
uint32_t | NbPages

Detailed Description

FLASH Erase structure definition.

Definition at line 65 of file stm32l4xx_hal_flash.h.

Field Documentation

uint32_t FLASH_EraseInitTypeDef::Banks

Select bank to erase. This parameter must be a value of FLASH Banks (FLASH_BANK_BOTH should be used only for mass erase)

Definition at line 69 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::NbPages

Number of pages to be erased. This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)

Definition at line 75 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::Page

Initial Flash page to erase when page erase is disabled This parameter must be a value between 0 and (max number of pages in the bank - 1) (eg : 255 for 1MB dual bank)

Definition at line 72 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::TypeErase

Mass erase or page erase. This parameter can be a value of FLASH Erase Type

Definition at line 67 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_flash.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH_OBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_OBProgramInitTypeDef Struct Reference
FLASH Exported Types

FLASH Option Bytes Program structure definition. More...

#include <stm32l4xx_hal_flash.h>

Data Fields

uint32_t | OptionType
uint32_t | WRPArea
uint32_t | WRPStartOffset
uint32_t | WRPEndOffset
uint32_t | RDPLevel
uint32_t | USERType
uint32_t | USERConfig
uint32_t | PCROPConfig
uint32_t | PCROPStartAddr
uint32_t | PCROPEndAddr

Detailed Description

FLASH Option Bytes Program structure definition.

Definition at line 82 of file stm32l4xx_hal_flash.h.

Field Documentation

uint32_t FLASH_OBProgramInitTypeDef::OptionType

Option byte to be configured. This parameter can be a combination of the values of FLASH Option Bytes Type

Definition at line 84 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPConfig

Configuration of the PCROP (used for OPTIONBYTE_PCROP). This parameter must be a combination of FLASH Banks (except FLASH_BANK_BOTH) and FLASH Option Bytes PCROP On RDP Level Type

Definition at line 106 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPEndAddr

PCROP End address (used for OPTIONBYTE_PCROP). This parameter must be a value between PCROP Start address and end of bank

Definition at line 112 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPStartAddr

PCROP Start address (used for OPTIONBYTE_PCROP). This parameter must be a value between begin and end of bank => Be careful of the bank swapping for the address

Definition at line 109 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::RDPLevel

Set the read protection level.. (used for OPTIONBYTE_RDP). This parameter can be a value of FLASH Option Bytes Read Protection

Definition at line 94 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERConfig

Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of FLASH Option Bytes User BOR Level, FLASH Option Bytes User Reset On Stop, FLASH Option Bytes User Reset On Standby, FLASH Option Bytes User Reset On Shutdown, FLASH Option Bytes User IWDG Type, FLASH Option Bytes User IWDG Mode On Stop, FLASH Option Bytes User IWDG Mode On Standby, FLASH Option Bytes User WWDG Type, FLASH Option Bytes User BFB2 Mode, FLASH Option Bytes User Dual-bank Type, FLASH Option Bytes User BOOT1 Type, FLASH Option Bytes User SRAM2 Parity Check Type and FLASH Option Bytes User SRAM2 Erase On Reset Type

Definition at line 98 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::USERType

User option byte(s) to be configured (used for OPTIONBYTE_USER). This parameter can be a combination of FLASH Option Bytes User Type

Definition at line 96 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPArea

Write protection area to be programmed (used for OPTIONBYTE_WRP). Only one WRP area could be programmed at the same time. This parameter can be value of FLASH WRP Area

Definition at line 86 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPEndOffset

Write protection end offset (used for OPTIONBYTE_WRP). This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1)

Definition at line 92 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPStartOffset

Write protection start offset (used for OPTIONBYTE_WRP). This parameter must be a value between 0 and (max number of pages in the bank - 1) (eg : 25 for 1MB dual bank)

Definition at line 89 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_flash.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH_ProcessTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_ProcessTypeDef Struct Reference
FLASH Exported Types

FLASH handle Structure definition. More...

#include <stm32l4xx_hal_flash.h>

Data Fields

HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode
__IO FLASH_ProcedureTypeDef | ProcedureOnGoing
__IO uint32_t | Address
__IO uint32_t | Bank
__IO uint32_t | Page
__IO uint32_t | NbPagesToErase

Detailed Description

FLASH handle Structure definition.

Definition at line 131 of file stm32l4xx_hal_flash.h.

Field Documentation

__IO uint32_t FLASH_ProcessTypeDef::Address

Definition at line 136 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASH_Program_IT().

__IO uint32_t FLASH_ProcessTypeDef::Bank

Definition at line 137 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::ErrorCode

Definition at line 134 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), HAL_FLASH_GetError(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

HAL_LockTypeDef FLASH_ProcessTypeDef::Lock

Definition at line 133 of file stm32l4xx_hal_flash.h.

__IO uint32_t FLASH_ProcessTypeDef::NbPagesToErase

Definition at line 139 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::Page

Definition at line 138 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

__IO FLASH_ProcedureTypeDef FLASH_ProcessTypeDef::ProcedureOnGoing

Definition at line 135 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_flash.h
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STM32L486xx HAL User Manual: FLASH Error

Defines
FLASH Error
FLASH Exported Constants

Defines

#define | HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_FLASH_ERROR_OP ((uint32_t)0x00000001)
#define | HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002)
#define | HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004)
#define | HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)
#define | HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010)
#define | HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020)
#define | HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040)
#define | HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080)
#define | HAL_FLASH_ERROR_RD ((uint32_t)0x00000100)
#define | HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200)
#define | HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400)

Define Documentation

#define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400)

Definition at line 165 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080)

Definition at line 162 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040)

Definition at line 161 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)

Definition at line 154 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

#define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001)

Definition at line 155 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200)

Definition at line 164 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)

Definition at line 158 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020)

Definition at line 160 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002)

Definition at line 156 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100)

Definition at line 163 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010)

Definition at line 159 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004)

Definition at line 157 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

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STM32L486xx HAL User Manual: FLASH Erase Type

Defines
FLASH Erase Type
FLASH Exported Constants

Defines

#define | FLASH_TYPEERASE_PAGES ((uint32_t)0x00)
#define | FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)

Define Documentation

#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)

Flash mass erase activation

Definition at line 177 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00)

Pages erase only

Definition at line 176 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Banks

Defines
FLASH Banks
FLASH Exported Constants

Defines

#define | FLASH_BANK_1 ((uint32_t)0x01)
#define | FLASH_BANK_2 ((uint32_t)0x02)
#define | FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2))

Define Documentation

#define FLASH_BANK_1 ((uint32_t)0x01)

Bank 1

Definition at line 185 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_MassErase(), FLASH_OB_GetPCROP(), FLASH_OB_PCROPConfig(), and FLASH_PageErase().

#define FLASH_BANK_2 ((uint32_t)0x02)

Bank 2

Definition at line 187 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_MassErase(), FLASH_OB_GetPCROP(), and FLASH_OB_PCROPConfig().

#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2))

Bank1 and Bank2

Definition at line 188 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetPCROP(), and FLASH_OB_PCROPConfig().

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STM32L486xx HAL User Manual: FLASH Program Type

Defines
FLASH Program Type
FLASH Exported Constants

Defines

#define | FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00)
#define | FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01)
#define | FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02)

Define Documentation

#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00)

Program a double-word (64-bit) at a specified address.

Definition at line 200 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01)

Fast program a 32 row double-word (64-bit) at a specified address. And another 32 row double-word (64-bit) will be programmed

Definition at line 201 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02)

Fast program a 32 row double-word (64-bit) at a specified address. And this is the last 32 row double-word (64-bit) programmed

Definition at line 203 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

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STM32L486xx HAL User Manual: FLASH Option Bytes Type

Defines
FLASH Option Bytes Type
FLASH Exported Constants

Defines

#define | OPTIONBYTE_WRP ((uint32_t)0x01)
#define | OPTIONBYTE_RDP ((uint32_t)0x02)
#define | OPTIONBYTE_USER ((uint32_t)0x04)
#define | OPTIONBYTE_PCROP ((uint32_t)0x08)

Define Documentation

#define OPTIONBYTE_PCROP ((uint32_t)0x08)

PCROP option byte configuration

Definition at line 215 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_RDP ((uint32_t)0x02)

RDP option byte configuration

Definition at line 213 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_USER ((uint32_t)0x04)

USER option byte configuration

Definition at line 214 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_WRP ((uint32_t)0x01)

WRP option byte configuration

Definition at line 212 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH WRP Area

Defines
FLASH WRP Area
FLASH Exported Constants

Defines

#define | OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00)
#define | OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01)
#define | OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02)
#define | OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04)

Define Documentation

#define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00)

Flash Bank 1 Area A

Definition at line 223 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), and FLASH_OB_WRPConfig().

#define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01)

Flash Bank 1 Area B

Definition at line 224 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), and FLASH_OB_WRPConfig().

#define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02)

Flash Bank 2 Area A

Definition at line 226 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), and FLASH_OB_WRPConfig().

#define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04)

Flash Bank 2 Area B

Definition at line 227 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), and FLASH_OB_WRPConfig().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH Option Bytes Read Protection

Defines
FLASH Option Bytes Read Protection
FLASH Exported Constants

Defines

#define | OB_RDP_LEVEL_0 ((uint32_t)0xAA)
#define | OB_RDP_LEVEL_1 ((uint32_t)0xBB)
#define | OB_RDP_LEVEL_2 ((uint32_t)0xCC)

Define Documentation

#define OB_RDP_LEVEL_0 ((uint32_t)0xAA)

Definition at line 236 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_1 ((uint32_t)0xBB)

Definition at line 237 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_2 ((uint32_t)0xCC)

Warning: When enabling read protection level 2 it's no more possible to go back to level 1 or 0

Definition at line 238 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

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STM32L486xx HAL User Manual: FLASH Option Bytes User Type

Defines
FLASH Option Bytes User Type
FLASH Exported Constants

Defines

#define | OB_USER_BOR_LEV ((uint32_t)0x0001)
#define | OB_USER_nRST_STOP ((uint32_t)0x0002)
#define | OB_USER_nRST_STDBY ((uint32_t)0x0004)
#define | OB_USER_IWDG_SW ((uint32_t)0x0008)
#define | OB_USER_IWDG_STOP ((uint32_t)0x0010)
#define | OB_USER_IWDG_STDBY ((uint32_t)0x0020)
#define | OB_USER_WWDG_SW ((uint32_t)0x0040)
#define | OB_USER_BFB2 ((uint32_t)0x0080)
#define | OB_USER_DUALBANK ((uint32_t)0x0100)
#define | OB_USER_nBOOT1 ((uint32_t)0x0200)
#define | OB_USER_SRAM2_PE ((uint32_t)0x0400)
#define | OB_USER_SRAM2_RST ((uint32_t)0x0800)
#define | OB_USER_nRST_SHDW ((uint32_t)0x1000)

Define Documentation

#define OB_USER_BFB2 ((uint32_t)0x0080)

Dual-bank boot

Definition at line 255 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_BOR_LEV ((uint32_t)0x0001)

BOR reset Level

Definition at line 247 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_DUALBANK ((uint32_t)0x0100)

Dual-Bank on 512KB or 256KB Flash memory devices

Definition at line 256 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG_STDBY ((uint32_t)0x0020)

Independent watchdog counter freeze in standby mode

Definition at line 252 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG_STOP ((uint32_t)0x0010)

Independent watchdog counter freeze in stop mode

Definition at line 251 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_IWDG_SW ((uint32_t)0x0008)

Independent watchdog selection

Definition at line 250 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_nBOOT1 ((uint32_t)0x0200)

Boot configuration

Definition at line 258 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_nRST_SHDW ((uint32_t)0x1000)

Reset generated when entering the shutdown mode

Definition at line 261 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_nRST_STDBY ((uint32_t)0x0004)

Reset generated when entering the standby mode

Definition at line 249 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_nRST_STOP ((uint32_t)0x0002)

Reset generated when entering the stop mode

Definition at line 248 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_SRAM2_PE ((uint32_t)0x0400)

SRAM2 parity check enable

Definition at line 259 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_SRAM2_RST ((uint32_t)0x0800)

SRAM2 Erase when system reset

Definition at line 260 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define OB_USER_WWDG_SW ((uint32_t)0x0040)

Window watchdog selection

Definition at line 253 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

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STM32L486xx HAL User Manual: FLASH Option Bytes User BOR Level

Defines
FLASH Option Bytes User BOR Level
FLASH Exported Constants

Defines

#define | OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0)
#define | OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1)
#define | OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2)
#define | OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3)
#define | OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4)

Define Documentation

#define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0)

Reset level threshold is around 1.7V

Definition at line 273 of file stm32l4xx_hal_flash.h.

#define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1)

Reset level threshold is around 2.0V

Definition at line 274 of file stm32l4xx_hal_flash.h.

#define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2)

Reset level threshold is around 2.2V

Definition at line 275 of file stm32l4xx_hal_flash.h.

#define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3)

Reset level threshold is around 2.5V

Definition at line 276 of file stm32l4xx_hal_flash.h.

#define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4)

Reset level threshold is around 2.8V

Definition at line 277 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes User Reset On Stop

Defines
FLASH Option Bytes User Reset On Stop
FLASH Exported Constants

Defines

#define | OB_STOP_RST ((uint32_t)0x0000)
#define | OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP)

Define Documentation

#define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP)

No reset generated when entering the stop mode

Definition at line 286 of file stm32l4xx_hal_flash.h.

#define OB_STOP_RST ((uint32_t)0x0000)

Reset generated when entering the stop mode

Definition at line 285 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes User Reset On Standby

Defines
FLASH Option Bytes User Reset On Standby
FLASH Exported Constants

Defines

#define | OB_STANDBY_RST ((uint32_t)0x0000)
#define | OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY)

Define Documentation

#define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY)

No reset generated when entering the standby mode

Definition at line 295 of file stm32l4xx_hal_flash.h.

#define OB_STANDBY_RST ((uint32_t)0x0000)

Reset generated when entering the standby mode

Definition at line 294 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes User Reset On Shutdown

Defines
FLASH Option Bytes User Reset On Shutdown
FLASH Exported Constants

Defines

#define | OB_SHUTDOWN_RST ((uint32_t)0x0000)
#define | OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW)

Define Documentation

#define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW)

No reset generated when entering the shutdown mode

Definition at line 304 of file stm32l4xx_hal_flash.h.

#define OB_SHUTDOWN_RST ((uint32_t)0x0000)

Reset generated when entering the shutdown mode

Definition at line 303 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes User IWDG Type

Defines
FLASH Option Bytes User IWDG Type
FLASH Exported Constants

Defines

#define | OB_IWDG_HW ((uint32_t)0x00000)
#define | OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW)

Define Documentation

#define OB_IWDG_HW ((uint32_t)0x00000)

Hardware independent watchdog

Definition at line 312 of file stm32l4xx_hal_flash.h.

#define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW)

Software independent watchdog

Definition at line 313 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes User IWDG Mode On Stop

Defines
FLASH Option Bytes User IWDG Mode On Stop
FLASH Exported Constants

Defines

#define | OB_IWDG_STOP_FREEZE ((uint32_t)0x00000)
#define | OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP)

Define Documentation

#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000)

Independent watchdog counter is frozen in Stop mode

Definition at line 321 of file stm32l4xx_hal_flash.h.

#define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP)

Independent watchdog counter is running in Stop mode

Definition at line 322 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes User IWDG Mode On Standby

Defines
FLASH Option Bytes User IWDG Mode On Standby
FLASH Exported Constants

Defines

#define | OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000)
#define | OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY)

Define Documentation

#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000)

Independent watchdog counter is frozen in Standby mode

Definition at line 330 of file stm32l4xx_hal_flash.h.

#define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY)

Independent watchdog counter is running in Standby mode

Definition at line 331 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes User WWDG Type

Defines
FLASH Option Bytes User WWDG Type
FLASH Exported Constants

Defines

#define | OB_WWDG_HW ((uint32_t)0x00000)
#define | OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW)

Define Documentation

#define OB_WWDG_HW ((uint32_t)0x00000)

Hardware window watchdog

Definition at line 339 of file stm32l4xx_hal_flash.h.

#define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW)

Software window watchdog

Definition at line 340 of file stm32l4xx_hal_flash.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH Option Bytes User BFB2 Mode

Defines
FLASH Option Bytes User BFB2 Mode
FLASH Exported Constants

Defines

#define | OB_BFB2_DISABLE ((uint32_t)0x000000)
#define | OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2)

Define Documentation

#define OB_BFB2_DISABLE ((uint32_t)0x000000)

Dual-bank boot disable

Definition at line 349 of file stm32l4xx_hal_flash.h.

#define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2)

Dual-bank boot enable

Definition at line 350 of file stm32l4xx_hal_flash.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH Option Bytes User Dual-bank Type

Defines
FLASH Option Bytes User Dual-bank Type
FLASH Exported Constants

Defines

#define | OB_DUALBANK_SINGLE ((uint32_t)0x000000)
#define | OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK)

Define Documentation

#define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK)

256 KB/512 KB Dual-bank Flash

Definition at line 359 of file stm32l4xx_hal_flash.h.

#define OB_DUALBANK_SINGLE ((uint32_t)0x000000)

256 KB/512 KB Single-bank Flash

Definition at line 358 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes User BOOT1 Type

Defines
FLASH Option Bytes User BOOT1 Type
FLASH Exported Constants

Defines

#define | OB_BOOT1_SRAM ((uint32_t)0x000000)
#define | OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1)

Define Documentation

#define OB_BOOT1_SRAM ((uint32_t)0x000000)

Embedded SRAM1 is selected as boot space (if BOOT0=1)

Definition at line 368 of file stm32l4xx_hal_flash.h.

#define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1)

System memory is selected as boot space (if BOOT0=1)

Definition at line 369 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes User SRAM2 Parity Check Type

Defines
FLASH Option Bytes User SRAM2 Parity Check Type
FLASH Exported Constants

Defines

#define | OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000)
#define | OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE)

Define Documentation

#define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE)

SRAM2 parity check disable

Definition at line 378 of file stm32l4xx_hal_flash.h.

#define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000)

SRAM2 parity check enable

Definition at line 377 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes User SRAM2 Erase On Reset Type

Defines
FLASH Option Bytes User SRAM2 Erase On Reset Type
FLASH Exported Constants

Defines

#define | OB_SRAM2_RST_ERASE ((uint32_t)0x0000000)
#define | OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST)

Define Documentation

#define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000)

SRAM2 erased when a system reset occurs

Definition at line 386 of file stm32l4xx_hal_flash.h.

#define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST)

SRAM2 is not erased when a system reset occurs

Definition at line 387 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Option Bytes PCROP On RDP Level Type

Defines
FLASH Option Bytes PCROP On RDP Level Type
FLASH Exported Constants

Defines

#define | OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000)
#define | OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP)

Define Documentation

#define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP)

PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase)

Definition at line 417 of file stm32l4xx_hal_flash.h.

#define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000)

PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0

Definition at line 415 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Constants

Defines

#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

Define Documentation

#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero wait state

Definition at line 426 of file stm32l4xx_hal_flash.h.

Referenced by RCC_SetFlashLatencyFromMSIRange().

#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One wait state

Definition at line 427 of file stm32l4xx_hal_flash.h.

Referenced by RCC_SetFlashLatencyFromMSIRange().

#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two wait states

Definition at line 428 of file stm32l4xx_hal_flash.h.

Referenced by RCC_SetFlashLatencyFromMSIRange().

#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three wait states

Definition at line 429 of file stm32l4xx_hal_flash.h.

Referenced by RCC_SetFlashLatencyFromMSIRange().

#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

FLASH Four wait states

Definition at line 430 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Keys

Defines
FLASH Keys
FLASH Exported Constants

Defines

#define | FLASH_KEY1 ((uint32_t)0x45670123U)
#define | FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
#define | FLASH_PDKEY1 ((uint32_t)0x04152637U)
#define | FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU)
#define | FLASH_OPTKEY1 ((uint32_t)0x08192A3BU)
#define | FLASH_OPTKEY2 ((uint32_t)0x4C5D6E7FU)

Define Documentation

#define FLASH_KEY1 ((uint32_t)0x45670123U)

Flash key1

Definition at line 438 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)

Flash key2: used with FLASH_KEY1 to unlock the FLASH registers access

Definition at line 439 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_OPTKEY1 ((uint32_t)0x08192A3BU)

Flash option byte key1

Definition at line 446 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define FLASH_OPTKEY2 ((uint32_t)0x4C5D6E7FU)

Flash option byte key2: used with FLASH_OPTKEY1 to allow option bytes operations

Definition at line 447 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define FLASH_PDKEY1 ((uint32_t)0x04152637U)

Flash power down key1

Definition at line 442 of file stm32l4xx_hal_flash.h.

#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU)

Flash power down key2: used with FLASH_PDKEY1 to unlock the RUN_PD bit in FLASH_ACR

Definition at line 443 of file stm32l4xx_hal_flash.h.

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STM32L486xx HAL User Manual: FLASH Flags Definition

Defines
FLASH Flags Definition
FLASH Exported Constants

Defines

#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPERR FLASH_SR_OPERR
#define | FLASH_FLAG_PROGERR FLASH_SR_PROGERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_SIZERR FLASH_SR_SIZERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_MISERR FLASH_SR_MISERR
#define | FLASH_FLAG_FASTERR FLASH_SR_FASTERR
#define | FLASH_FLAG_RDERR FLASH_SR_RDERR
#define | FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_ECCC FLASH_ECCR_ECCC
#define | FLASH_FLAG_ECCD FLASH_ECCR_ECCD
#define | FLASH_FLAG_ALL_ERRORS

Define Documentation

#define FLASH_FLAG_ALL_ERRORS
Value:
(FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
                                   FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)

Definition at line 474 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define FLASH_FLAG_BSY FLASH_SR_BSY

FLASH Busy flag

Definition at line 467 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC

FLASH ECC correction

Definition at line 471 of file stm32l4xx_hal_flash.h.

#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD

FLASH ECC detection

Definition at line 472 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_EOP FLASH_SR_EOP

FLASH End of operation flag

Definition at line 456 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR

FLASH Fast programming error flag

Definition at line 464 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_MISERR FLASH_SR_MISERR

FLASH Fast programming data miss error flag

Definition at line 463 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_OPERR FLASH_SR_OPERR

FLASH Operation error flag

Definition at line 457 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR

FLASH Option validity error flag

Definition at line 466 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR

FLASH Programming alignment error flag

Definition at line 460 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR

FLASH Programming sequence error flag

Definition at line 462 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR

FLASH Programming error flag

Definition at line 458 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_RDERR FLASH_SR_RDERR

FLASH PCROP read error flag

Definition at line 465 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR

FLASH Size error flag

Definition at line 461 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR

FLASH Write protection error flag

Definition at line 459 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH Interrupts Definition

Defines
FLASH Interrupts Definition
FLASH Exported Constants

FLASH Interrupt definition. More...

Defines

#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_OPERR FLASH_CR_ERRIE
#define | FLASH_IT_RDERR FLASH_CR_RDERRIE
#define | FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24)

Detailed Description

FLASH Interrupt definition.

Define Documentation

#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24)

ECC Correction Interrupt source

Definition at line 489 of file stm32l4xx_hal_flash.h.

#define FLASH_IT_EOP FLASH_CR_EOPIE

End of FLASH Operation Interrupt source

Definition at line 486 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_OPERR FLASH_CR_ERRIE

Error Interrupt source

Definition at line 487 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_RDERR FLASH_CR_RDERRIE

PCROP Read Error Interrupt source

Definition at line 488 of file stm32l4xx_hal_flash.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH Exported Macros

Defines
FLASH Exported Macros
FLASH

macros to control FLASH features More...

Defines

#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Enable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Disable the FLASH instruction cache.
#define | __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Enable the FLASH data cache.
#define | __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Disable the FLASH data cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_RESET()
Reset the FLASH instruction Cache.
#define | __HAL_FLASH_DATA_CACHE_RESET()
Reset the FLASH data Cache.
#define | __HAL_FLASH_POWER_DOWN_ENABLE()
Enable the FLASH power down during Low-power run mode.
#define | __HAL_FLASH_POWER_DOWN_DISABLE()
Disable the FLASH power down during Low-power run mode.
#define | __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Enable the FLASH power down during Low-Power sleep mode.
#define | __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Disable the FLASH power down during Low-Power sleep mode.

Detailed Description

macros to control FLASH features

Define Documentation

#define __HAL_FLASH_DATA_CACHE_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)

Disable the FLASH data cache.

Return values:
none

Definition at line 563 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_FlushCaches(), and HAL_Init().

#define __HAL_FLASH_DATA_CACHE_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)

Enable the FLASH data cache.

Return values:
none

Definition at line 557 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_DATA_CACHE_RESET ( )
Value:
do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
                                                   } while (0)

Reset the FLASH data Cache.

Note:
This function must be used only when the data Cache is disabled.
Return values:
None

Definition at line 579 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_GET_LATENCY ( ) READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)

Get the FLASH Latency.

Return values:
FLASH Latency This parameter can be one of the following values :
  • FLASH_LATENCY_0: FLASH Zero wait state
  • FLASH_LATENCY_1: FLASH One wait state
  • FLASH_LATENCY_2: FLASH Two wait states
  • FLASH_LATENCY_3: FLASH Three wait states
  • FLASH_LATENCY_4: FLASH Four wait states

Definition at line 527 of file stm32l4xx_hal_flash.h.

#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)

Disable the FLASH instruction cache.

Return values:
none

Definition at line 551 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_FlushCaches(), and HAL_Init().

#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)

Enable the FLASH instruction cache.

Return values:
none

Definition at line 545 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_INSTRUCTION_CACHE_RESET ( )
Value:
do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
                                                   } while (0)

Reset the FLASH instruction Cache.

Note:
This function must be used only when the Instruction Cache is disabled.
Return values:
None

Definition at line 570 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_POWER_DOWN_DISABLE ( )
Value:
do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
                                                   } while (0)

Disable the FLASH power down during Low-power run mode.

Note:
Writing this bit to 0 this bit, automatically the keys are loss and a new unlock sequence is necessary to re-write it to 1.

Definition at line 598 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_DisableRunPowerDown().

#define __HAL_FLASH_POWER_DOWN_ENABLE ( )
Value:
do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
                                                     SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);   \
                                                   } while (0)

Enable the FLASH power down during Low-power run mode.

Note:
Writing this bit to 0 this bit, automatically the keys are loss and a new unlock sequence is necessary to re-write it to 1.

Definition at line 588 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_EnableRunPowerDown().

#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)

Disable the FLASH prefetch buffer.

Return values:
None

Definition at line 539 of file stm32l4xx_hal_flash.h.

#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)

Enable the FLASH prefetch buffer.

Return values:
None

Definition at line 533 of file stm32l4xx_hal_flash.h.

Referenced by HAL_Init().

#define __HAL_FLASH_SET_LATENCY ( __LATENCY__ ) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))

Set the FLASH Latency.

Parameters:
__LATENCY__,: FLASH Latency This parameter can be one of the following values :
  • FLASH_LATENCY_0: FLASH Zero wait state
  • FLASH_LATENCY_1: FLASH One wait state
  • FLASH_LATENCY_2: FLASH Two wait states
  • FLASH_LATENCY_3: FLASH Three wait states
  • FLASH_LATENCY_4: FLASH Four wait states
Return values:
None

Definition at line 515 of file stm32l4xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig(), and RCC_SetFlashLatencyFromMSIRange().

#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)

Disable the FLASH power down during Low-Power sleep mode.

Return values:
none

Definition at line 613 of file stm32l4xx_hal_flash.h.

#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)

Enable the FLASH power down during Low-Power sleep mode.

Return values:
none

Definition at line 607 of file stm32l4xx_hal_flash.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH Interrupts Macros

Defines
FLASH Interrupts Macros
FLASH

macros to handle FLASH interrupts More...

Defines

#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
Check whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the FLASH's pending flags.

Detailed Description

macros to handle FLASH interrupts

Define Documentation

#define __HAL_FLASH_CLEAR_FLAG ( __FLAG__ )
Value:
do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
                                                     if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
                                                   } while(0)

Clear the FLASH's pending flags.

Parameters:
__FLAG__,: specifies the FLASH flags to clear. This parameter can be any combination of the following values:
  • FLASH_FLAG_EOP: FLASH End of Operation flag
  • FLASH_FLAG_OPERR: FLASH Operation error flag
  • FLASH_FLAG_PROGERR: FLASH Programming error flag
  • FLASH_FLAG_WRPERR: FLASH Write protection error flag
  • FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
  • FLASH_FLAG_SIZERR: FLASH Size error flag
  • FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
  • FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
  • FLASH_FLAG_FASTERR: FLASH Fast programming error flag
  • FLASH_FLAG_RDERR: FLASH PCROP read error flag
  • FLASH_FLAG_OPTVERR: FLASH Option validity error flag
  • FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
  • FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
  • FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
Return values:
None

Definition at line 697 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define __HAL_FLASH_DISABLE_IT ( __INTERRUPT__ )
Value:
do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
                                                     if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
                                                   } while(0)

Disable the specified FLASH interrupt.

Parameters:
__INTERRUPT__,: FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP: End of FLASH Operation Interrupt
  • FLASH_IT_OPERR: Error Interrupt
  • FLASH_IT_RDERR: PCROP Read Error Interrupt
  • FLASH_IT_ECCC: ECC Correction Interrupt
Return values:
none

Definition at line 648 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_ENABLE_IT ( __INTERRUPT__ )
Value:
do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
                                                     if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
                                                   } while(0)

Enable the specified FLASH interrupt.

Parameters:
__INTERRUPT__,: FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP: End of FLASH Operation Interrupt
  • FLASH_IT_OPERR: Error Interrupt
  • FLASH_IT_RDERR: PCROP Read Error Interrupt
  • FLASH_IT_ECCC: ECC Correction Interrupt
Return values:
none

Definition at line 634 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_GET_FLAG ( __FLAG__ )
Value:
(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \
                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))  : \
                                                 (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))

Check whether the specified FLASH flag is set or not.

Parameters:
__FLAG__,: specifies the FLASH flag to check. This parameter can be one of the following values:
  • FLASH_FLAG_EOP: FLASH End of Operation flag
  • FLASH_FLAG_OPERR: FLASH Operation error flag
  • FLASH_FLAG_PROGERR: FLASH Programming error flag
  • FLASH_FLAG_WRPERR: FLASH Write protection error flag
  • FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
  • FLASH_FLAG_SIZERR: FLASH Size error flag
  • FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
  • FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
  • FLASH_FLAG_FASTERR: FLASH Fast programming error flag
  • FLASH_FLAG_RDERR: FLASH PCROP read error flag
  • FLASH_FLAG_OPTVERR: FLASH Option validity error flag
  • FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
  • FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
  • FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
  • FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
Return values:
The new state of FLASH_FLAG (SET or RESET).

Definition at line 673 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASH

Defines

#define | FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
#define | FLASH_SIZE
#define | FLASH_BANK_SIZE (FLASH_SIZE >> 1)
#define | FLASH_PAGE_SIZE ((uint32_t)0x800)
#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */

Define Documentation

#define FLASH_BANK_SIZE (FLASH_SIZE >> 1)

Definition at line 765 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetPCROP(), and FLASH_OB_PCROPConfig().

#define FLASH_PAGE_SIZE ((uint32_t)0x800)

Definition at line 770 of file stm32l4xx_hal_flash.h.

#define FLASH_SIZE
Value:
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))

Definition at line 761 of file stm32l4xx_hal_flash.h.

#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)

Definition at line 759 of file stm32l4xx_hal_flash.h.

#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */

Definition at line 772 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRPConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), and HAL_FLASHEx_Erase().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH Private Macros

Defines
FLASH Private Macros
FLASH

Defines

#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_FLASH_BANK(BANK)
#define | IS_FLASH_BANK_EXCLUSIVE(BANK)
#define | IS_FLASH_TYPEPROGRAM(VALUE)
#define | IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)
#define | IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
#define | IS_FLASH_PAGE(PAGE)
#define | IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
#define | IS_OB_WRPAREA(VALUE)
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
#define | IS_OB_USER_BOR_LEVEL(LEVEL)
#define | IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
#define | IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
#define | IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
#define | IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
#define | IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
#define | IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
#define | IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
#define | IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
#define | IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
#define | IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
#define | IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
#define | IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
#define | IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
#define | IS_FLASH_LATENCY(LATENCY)

Define Documentation

#define IS_FLASH_BANK ( BANK )
Value:
(((BANK) == FLASH_BANK_1)  || \
                                            ((BANK) == FLASH_BANK_2)  || \
                                            ((BANK) == FLASH_BANK_BOTH))

Definition at line 786 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_MassErase().

#define IS_FLASH_BANK_EXCLUSIVE ( BANK )
Value:
(((BANK) == FLASH_BANK_1)  || \
                                            ((BANK) == FLASH_BANK_2))

Definition at line 790 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetPCROP(), FLASH_OB_PCROPConfig(), and FLASH_PageErase().

#define IS_FLASH_LATENCY ( LATENCY )
Value:
(((LATENCY) == FLASH_LATENCY_0) || \
                                            ((LATENCY) == FLASH_LATENCY_1) || \
                                            ((LATENCY) == FLASH_LATENCY_2) || \
                                            ((LATENCY) == FLASH_LATENCY_3) || \
                                            ((LATENCY) == FLASH_LATENCY_4))

Definition at line 879 of file stm32l4xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_FLASH_MAIN_MEM_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) >= FLASH_BASE)        && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
                                            ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
                                            ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
                                            ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \
                                            ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF))))))

Definition at line 802 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_PCROPConfig(), and FLASH_Program_Fast().

#define IS_FLASH_OTP_ADDRESS ( ADDRESS ) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))

Definition at line 808 of file stm32l4xx_hal_flash.h.

#define IS_FLASH_PAGE ( PAGE )
Value:
(((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
                                            ((PAGE) < 256)))))

Definition at line 813 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_WRPConfig(), and FLASH_PageErase().

#define IS_FLASH_PROGRAM_ADDRESS ( ADDRESS ) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))

Definition at line 810 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_Program_DoubleWord().

#define IS_FLASH_TYPEERASE ( VALUE )
Value:
(((VALUE) == FLASH_TYPEERASE_PAGES) || \
                                            ((VALUE) == FLASH_TYPEERASE_MASSERASE))

Definition at line 782 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_TYPEPROGRAM ( VALUE )
Value:
(((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))

Definition at line 798 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_OB_PCROP_RDP ( VALUE ) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))

Definition at line 877 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_PCROPConfig().

#define IS_OB_RDP_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_RDP_LEVEL_0)   ||\
                                            ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
                                            ((LEVEL) == OB_RDP_LEVEL_2)*/)

Definition at line 832 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_RDPConfig().

#define IS_OB_USER_BFB2 ( VALUE ) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))

Definition at line 860 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_BOOT1 ( VALUE ) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))

Definition at line 865 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_BOR_LEVEL ( LEVEL )
Value:
(((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
                                            ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
                                            ((LEVEL) == OB_BOR_LEVEL_4))

Definition at line 841 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_DUALBANK ( VALUE ) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))

Definition at line 862 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IWDG ( VALUE ) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))

Definition at line 851 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IWDG_STDBY ( VALUE ) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))

Definition at line 855 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_IWDG_STOP ( VALUE ) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))

Definition at line 853 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_SHUTDOWN ( VALUE ) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))

Definition at line 849 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_SRAM2_PARITY ( VALUE ) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))

Definition at line 867 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_SRAM2_RST ( VALUE ) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))

Definition at line 869 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_STANDBY ( VALUE ) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))

Definition at line 847 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_STOP ( VALUE ) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))

Definition at line 845 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_TYPE ( TYPE ) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))

Definition at line 836 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_USER_WWDG ( VALUE ) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))

Definition at line 857 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_WRPAREA ( VALUE )
Value:
(((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
                                            ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))

Definition at line 826 of file stm32l4xx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), and FLASH_OB_WRPConfig().

#define IS_OPTIONBYTE ( VALUE ) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))

Definition at line 823 of file stm32l4xx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASHEx Private Variables

Variables
FLASHEx Private Variables
FLASHEx

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Variable Documentation

FLASH_ProcessTypeDef pFlash

Variable used for Program/Erase sectors under interruption.

Definition at line 131 of file stm32l4xx_hal_flash.c.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASHEx Private Functions

Functions
FLASHEx Private Functions
FLASHEx

Functions

HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
void | FLASH_PageErase (uint32_t Page, uint32_t Banks)
Erase the specified FLASH memory page.
static void | FLASH_MassErase (uint32_t Banks)
Mass erase of FLASH memory.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.
static HAL_StatusTypeDef | FLASH_OB_WRPConfig (uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
Configure the write protection of the desired pages.
static HAL_StatusTypeDef | FLASH_OB_RDPConfig (uint32_t RDPLevel)
Set the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint32_t UserType, uint32_t UserConfig)
Program the FLASH User Option Byte.
static HAL_StatusTypeDef | FLASH_OB_PCROPConfig (uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
Configure the Proprietary code readout protection of the desired addresses.
static void | FLASH_OB_GetWRP (uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
Return the FLASH Write Protection Option Bytes value.
static uint32_t | FLASH_OB_GetRDP (void)
Return the FLASH Read Protection level.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static void | FLASH_OB_GetPCROP (uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr)
Return the FLASH Write Protection Option Bytes value.

Function Documentation

void FLASH_FlushCaches ( void )

Flush the instruction and data caches.

Return values:
None

Definition at line 430 of file stm32l4xx_hal_flash_ex.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, __HAL_FLASH_DATA_CACHE_ENABLE, __HAL_FLASH_DATA_CACHE_RESET, __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_INSTRUCTION_CACHE_ENABLE, and __HAL_FLASH_INSTRUCTION_CACHE_RESET.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase().

static void FLASH_MassErase ( uint32_t Banks ) [static]

Mass erase of FLASH memory.

Parameters:
Banks,: Banks to be erased This parameter can be one of the following values:
  • FLASH_BANK_1: Bank1 to be erased
  • FLASH_BANK_2: Bank2 to be erased
  • FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
Return values:
None

Definition at line 370 of file stm32l4xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, and IS_FLASH_BANK.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static void FLASH_OB_GetPCROP | ( | uint32_t * | PCROPConfig,
 |  | uint32_t * | PCROPStartAddr,
 |  | uint32_t * | PCROPEndAddr
 | ) |  | [static]

Return the FLASH Write Protection Option Bytes value.

Parameters:
PCROPConfig | [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option). This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
PCROPStartAddr | [out]: specifies the address where to copied the start address of the Proprietary code readout protection
PCROPEndAddr | [out]: specifies the address where to copied the end address of the Proprietary code readout protection
Return values:
None

Definition at line 974 of file stm32l4xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_BANK_BOTH, FLASH_BANK_SIZE, and IS_FLASH_BANK_EXCLUSIVE.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetRDP ( void ) [static]

Return the FLASH Read Protection level.

Return values:
FLASH ReadOut Protection Status: This return value can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection

Definition at line 926 of file stm32l4xx_hal_flash_ex.c.

References OB_RDP_LEVEL_0, OB_RDP_LEVEL_1, and OB_RDP_LEVEL_2.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetUser ( void ) [static]

Return the FLASH User Option Byte value.

Return values:
The FLASH User Option Bytes values: For STM32L47x/STM32L48x devices : BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). For STM32L43x/STM32L44x devices : BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27).

Definition at line 951 of file stm32l4xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetWRP | ( | uint32_t | WRPArea,
 |  | uint32_t * | WRPStartOffset,
 |  | uint32_t * | WRDPEndOffset
 | ) |  | [static]

Return the FLASH Write Protection Option Bytes value.

Parameters:
[in] WRPArea,: specifies the area to be returned. This parameter can be one of the following values:
  • OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
  • OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
  • OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices)
  • OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices)
[out] WRPStartOffset,: specifies the address where to copied the start page of the write protected area
[out] WRDPEndOffset,: specifies the address where to copied the end page of the write protected area
Return values:
None

Definition at line 888 of file stm32l4xx_hal_flash_ex.c.

References assert_param, IS_OB_WRPAREA, OB_WRPAREA_BANK1_AREAA, OB_WRPAREA_BANK1_AREAB, OB_WRPAREA_BANK2_AREAA, and OB_WRPAREA_BANK2_AREAB.

Referenced by HAL_FLASHEx_OBGetConfig().

static HAL_StatusTypeDef FLASH_OB_PCROPConfig | ( | uint32_t | PCROPConfig,
 |  | uint32_t | PCROPStartAddr,
 |  | uint32_t | PCROPEndAddr
 | ) |  | [static]

Configure the Proprietary code readout protection of the desired addresses.

Note:
To configure the PCROP options, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the PCROP options, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
PCROPConfig,: specifies the configuration (Bank to be configured and PCROP_RDP option). This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
PCROPStartAddr,: specifies the start address of the Proprietary code readout protection This parameter can be an address between begin and end of the bank
PCROPEndAddr,: specifies the end address of the Proprietary code readout protection This parameter can be an address between PCROPStartAddr and end of the bank
Return values:
HAL Status

Definition at line 799 of file stm32l4xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, FLASH_BANK_2, FLASH_BANK_BOTH, FLASH_BANK_SIZE, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_BANK_EXCLUSIVE, IS_FLASH_MAIN_MEM_ADDRESS, and IS_OB_PCROP_RDP.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_RDPConfig ( uint32_t RDPLevel ) [static]

Set the read protection level.

Note:
To configure the RDP level, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the RDP level, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
!!! Warning : When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 !!!
Parameters:
RDPLevel,: specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0: No protection
  • OB_RDP_LEVEL_1: Read protection of the memory
  • OB_RDP_LEVEL_2: Full chip protection
Return values:
HAL status

Definition at line 551 of file stm32l4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), and IS_OB_RDP_LEVEL.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_UserConfig | ( | uint32_t | UserType,
 |  | uint32_t | UserConfig
 | ) |  | [static]

Program the FLASH User Option Byte.

Note:
To configure the user option bytes, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the user option bytes, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
UserType,: The FLASH User Option Bytes to be modified
UserConfig,: The FLASH User Option Bytes values: BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
Return values:
HAL status

Definition at line 595 of file stm32l4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_OB_USER_BFB2, IS_OB_USER_BOOT1, IS_OB_USER_BOR_LEVEL, IS_OB_USER_DUALBANK, IS_OB_USER_IWDG, IS_OB_USER_IWDG_STDBY, IS_OB_USER_IWDG_STOP, IS_OB_USER_SHUTDOWN, IS_OB_USER_SRAM2_PARITY, IS_OB_USER_SRAM2_RST, IS_OB_USER_STANDBY, IS_OB_USER_STOP, IS_OB_USER_TYPE, IS_OB_USER_WWDG, OB_USER_BFB2, OB_USER_BOR_LEV, OB_USER_DUALBANK, OB_USER_IWDG_STDBY, OB_USER_IWDG_STOP, OB_USER_IWDG_SW, OB_USER_nBOOT1, OB_USER_nRST_SHDW, OB_USER_nRST_STDBY, OB_USER_nRST_STOP, OB_USER_SRAM2_PE, OB_USER_SRAM2_RST, and OB_USER_WWDG_SW.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_WRPConfig | ( | uint32_t | WRPArea,
 |  | uint32_t | WRPStartOffset,
 |  | uint32_t | WRDPEndOffset
 | ) |  | [static]

Configure the write protection of the desired pages.

Note:
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase Flash memory if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM or System flash, even if WRP is not activated.
To configure the WRP options, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the WRP options, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
WRPArea,: specifies the area to be configured. This parameter can be one of the following values:
  • OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
  • OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
  • OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices)
  • OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices)
WRPStartOffset,: specifies the start page of the write protected area This parameter can be page number between 0 and (max number of pages in the bank - 1)
WRDPEndOffset,: specifies the end page of the write protected area This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
Return values:
HAL Status

Definition at line 482 of file stm32l4xx_hal_flash_ex.c.

References assert_param, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), IS_FLASH_PAGE, IS_OB_WRPAREA, OB_WRPAREA_BANK1_AREAA, OB_WRPAREA_BANK1_AREAB, OB_WRPAREA_BANK2_AREAA, and OB_WRPAREA_BANK2_AREAB.

Referenced by HAL_FLASHEx_OBProgram().

void FLASH_PageErase | ( | uint32_t | Page,
 |  | uint32_t | Banks
 | ) |  |

Erase the specified FLASH memory page.

Parameters:
Page,: FLASH page to erase This parameter must be a value between 0 and (max number of pages in the bank - 1)
Banks,: Bank(s) where the page will be erased This parameter can be one or a combination of the following values:
  • FLASH_BANK_1: Page in bank 1 to be erased
  • FLASH_BANK_2: Page in bank 2 to be erased
Return values:
None

Definition at line 403 of file stm32l4xx_hal_flash_ex.c.

References assert_param, FLASH_BANK_1, IS_FLASH_BANK_EXCLUSIVE, and IS_FLASH_PAGE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout,: maximum flash operation timeout
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 608 of file stm32l4xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_FLAG_BSY, FLASH_FLAG_ECCD, FLASH_FLAG_EOP, FLASH_FLAG_FASTERR, FLASH_FLAG_MISERR, FLASH_FLAG_OPERR, FLASH_FLAG_OPTVERR, FLASH_FLAG_PGAERR, FLASH_FLAG_PGSERR, FLASH_FLAG_PROGERR, FLASH_FLAG_RDERR, FLASH_FLAG_SIZERR, FLASH_FLAG_WRPERR, FLASH_SetErrorCode(), and HAL_GetTick().

Referenced by FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRPConfig(), HAL_FLASH_OB_Launch(), HAL_FLASH_Program(), and HAL_FLASHEx_Erase().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended IO operation functions

Functions
Extended IO operation functions
FLASH Extended Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                ##### Extended programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the Extended FLASH
    programming operations Operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | PageError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory pages.

Parameters:
[in] pEraseInit,: pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] PageError : pointer to variable that contains the configuration information on faulty page in case of error (0xFFFFFFFF means that all the pages have been correctly erased)
Return values:
HAL Status

Definition at line 156 of file stm32l4xx_hal_flash_ex.c.

References assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_ProcessTypeDef::ErrorCode, FLASH_FlushCaches(), FLASH_MassErase(), FLASH_PageErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_EraseInitTypeDef::Page, and FLASH_EraseInitTypeDef::TypeErase.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.

Parameters:
pEraseInit,: pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL Status

Definition at line 231 of file stm32l4xx_hal_flash_ex.c.

References __HAL_FLASH_ENABLE_IT, assert_param, FLASH_ProcessTypeDef::Bank, FLASH_EraseInitTypeDef::Banks, FLASH_ProcessTypeDef::ErrorCode, FLASH_IT_EOP, FLASH_IT_OPERR, FLASH_MassErase(), FLASH_PageErase(), FLASH_PROC_MASS_ERASE, FLASH_PROC_PAGE_ERASE, FLASH_TYPEERASE_MASSERASE, HAL_FLASH_ERROR_NONE, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_ProcessTypeDef::NbPagesToErase, FLASH_EraseInitTypeDef::Page, FLASH_ProcessTypeDef::Page, FLASH_ProcessTypeDef::ProcedureOnGoing, and FLASH_EraseInitTypeDef::TypeErase.

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option bytes configuration.

Parameters:
pOBInit,: pointer to an FLASH_OBInitStruct structure that contains the configuration information. The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate which area is requested for the WRP and PCROP
Return values:
None

Definition at line 330 of file stm32l4xx_hal_flash_ex.c.

References FLASH_OB_GetPCROP(), FLASH_OB_GetRDP(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::PCROPEndAddr, FLASH_OBProgramInitTypeDef::PCROPStartAddr, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::WRPArea, FLASH_OBProgramInitTypeDef::WRPEndOffset, and FLASH_OBProgramInitTypeDef::WRPStartOffset.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program Option bytes.

Parameters:
pOBInit,: pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
HAL Status

Definition at line 275 of file stm32l4xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRPConfig(), HAL_FLASH_ERROR_NONE, IS_OPTIONBYTE, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::PCROPEndAddr, FLASH_OBProgramInitTypeDef::PCROPStartAddr, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::USERType, FLASH_OBProgramInitTypeDef::WRPArea, FLASH_OBProgramInitTypeDef::WRPEndOffset, and FLASH_OBProgramInitTypeDef::WRPStartOffset.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral features functions

Functions
Peripheral features functions
FLASH in RAM function Exported Functions

Data transfers functions. More...

Functions

__RAM_FUNC | HAL_FLASHEx_EnableRunPowerDown (void)
Enable the Power down in Run Mode.
__RAM_FUNC | HAL_FLASHEx_DisableRunPowerDown (void)
Disable the Power down in Run Mode.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### ramfunc functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions that should be executed from RAM.

Function Documentation

__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown ( void )

Disable the Power down in Run Mode.

Note:
This function should be called and executed from SRAM memory
Return values:
None

Definition at line 125 of file stm32l4xx_hal_flash_ramfunc.c.

References __HAL_FLASH_POWER_DOWN_DISABLE.

__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown ( void )

Enable the Power down in Run Mode.

Note:
This function should be called and executed from SRAM memory
Return values:
None

Definition at line 111 of file stm32l4xx_hal_flash_ramfunc.c.

References __HAL_FLASH_POWER_DOWN_ENABLE.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO Private Defines

Defines
GPIO Private Defines
GPIO

Defines

#define | GPIO_MODE ((uint32_t)0x00000003)
#define | ANALOG_MODE ((uint32_t)0x00000008)
#define | EXTI_MODE ((uint32_t)0x10000000)
#define | GPIO_MODE_IT ((uint32_t)0x00010000)
#define | GPIO_MODE_EVT ((uint32_t)0x00020000)
#define | RISING_EDGE ((uint32_t)0x00100000)
#define | FALLING_EDGE ((uint32_t)0x00200000)
#define | GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define | GPIO_NUMBER ((uint32_t)16)

Define Documentation

#define ANALOG_MODE ((uint32_t)0x00000008)

Definition at line 143 of file stm32l4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define EXTI_MODE ((uint32_t)0x10000000)

Definition at line 144 of file stm32l4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define FALLING_EDGE ((uint32_t)0x00200000)

Definition at line 148 of file stm32l4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE ((uint32_t)0x00000003)

Definition at line 142 of file stm32l4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_EVT ((uint32_t)0x00020000)

Definition at line 146 of file stm32l4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT ((uint32_t)0x00010000)

Definition at line 145 of file stm32l4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_NUMBER ((uint32_t)16)

Definition at line 151 of file stm32l4xx_hal_gpio.c.

#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)

Definition at line 149 of file stm32l4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define RISING_EDGE ((uint32_t)0x00100000)

Definition at line 147 of file stm32l4xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
#define | IS_GPIO_MODE(__MODE__)
#define | IS_GPIO_SPEED(__SPEED__)
#define | IS_GPIO_PULL(__PULL__)

Define Documentation

#define IS_GPIO_MODE ( __MODE__ )
Value:
(((__MODE__) == GPIO_MODE_INPUT)              ||\
                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
                                     ((__MODE__) == GPIO_MODE_ANALOG)             ||\
                                     ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL))

Definition at line 236 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_PIN ( __PIN__ ) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)

Definition at line 234 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define IS_GPIO_PIN_ACTION ( ACTION ) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

Definition at line 232 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_WritePin().

#define IS_GPIO_PULL ( __PULL__ )
Value:
(((__PULL__) == GPIO_NOPULL)   ||\
                                     ((__PULL__) == GPIO_PULLUP)   || \
                                     ((__PULL__) == GPIO_PULLDOWN))

Definition at line 255 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_SPEED ( __SPEED__ )
Value:
(((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 250 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
GPIO Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_DeInit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | GPIO_Pin
 | ) |  |

De-initialize the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 330 of file stm32l4xx_hal_gpio.c.

References assert_param, GPIO_GET_INDEX, and IS_GPIO_PIN.

void HAL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_Init
 | ) |  |

Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
GPIO_Init,: pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 191 of file stm32l4xx_hal_gpio.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, GPIO_InitTypeDef::Alternate, ANALOG_MODE, assert_param, EXTI_MODE, FALLING_EDGE, GPIO_GET_INDEX, GPIO_MODE, GPIO_MODE_AF_OD, GPIO_MODE_AF_PP, GPIO_MODE_ANALOG, GPIO_MODE_EVT, GPIO_MODE_IT, GPIO_MODE_OUTPUT_OD, GPIO_MODE_OUTPUT_PP, GPIO_OUTPUT_TYPE, IS_GPIO_AF, IS_GPIO_MODE, IS_GPIO_PIN, IS_GPIO_PULL, IS_GPIO_SPEED, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RISING_EDGE, and GPIO_InitTypeDef::Speed.

Referenced by HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
GPIO Exported Functions

GPIO Read, Write, Toggle, Lock and EXTI management functions. More...

Functions

GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO Read, Write, Toggle, Lock and EXTI management functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_EXTI_Callback ( uint16_t GPIO_Pin )

EXTI line detection callback.

Parameters:
GPIO_Pin,: Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 542 of file stm32l4xx_hal_gpio.c.

Referenced by HAL_GPIO_EXTI_IRQHandler().

void HAL_GPIO_EXTI_IRQHandler ( uint16_t GPIO_Pin )

Handle EXTI interrupt request.

Parameters:
GPIO_Pin,: Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 527 of file stm32l4xx_hal_gpio.c.

References __HAL_GPIO_EXTI_CLEAR_IT, __HAL_GPIO_EXTI_GET_IT, and HAL_GPIO_EXTI_Callback().

HAL_StatusTypeDef HAL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Lock GPIO Pins configuration registers.

Note:
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The configuration of the locked GPIO pins can no longer be modified until the next reset.
Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
GPIO_Pin,: specifies the port bits to be locked. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 493 of file stm32l4xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

GPIO_PinState HAL_GPIO_ReadPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Read the specified input port pin.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_PIN_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 418 of file stm32l4xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, GPIO_PIN_SET, and IS_GPIO_PIN.

void HAL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggle the specified GPIO pin.

Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
GPIO_Pin,: specifies the pin to be toggled.
Return values:
None

Definition at line 474 of file stm32l4xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

void HAL_GPIO_WritePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | GPIO_PinState | PinState
 | ) |  |

Set or clear the selected data port bit.

Note:
This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Parameters:
GPIOx,: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
PinState,: specifies the value to be written to the selected bit. This parameter can be one of the GPIO_PinState enum values:
  • GPIO_PIN_RESET: to clear the port pin
  • GPIO_PIN_SET: to set the port pin
Return values:
None

Definition at line 452 of file stm32l4xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, IS_GPIO_PIN, and IS_GPIO_PIN_ACTION.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO Exported Types

Data Structures | Enumerations
GPIO Exported Types
GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Enumeration Type Documentation

enum GPIO_PinState

GPIO Bit SET and Bit RESET enumeration.

Enumerator:
GPIO_PIN_RESET
GPIO_PIN_SET

Definition at line 86 of file stm32l4xx_hal_gpio.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GPIO_InitTypeDef Struct Reference
GPIO Exported Types

GPIO Init structure definition. More...

#include <stm32l4xx_hal_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Pull
uint32_t | Speed
uint32_t | Alternate

Detailed Description

GPIO Init structure definition.

Definition at line 65 of file stm32l4xx_hal_gpio.h.

Field Documentation

uint32_t GPIO_InitTypeDef::Alternate

Peripheral to be connected to the selected pins This parameter can be a value of GPIOEx Alternate function selection

Definition at line 79 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIO mode

Definition at line 70 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

uint32_t GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO pins

Definition at line 67 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

uint32_t GPIO_InitTypeDef::Pull

Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of GPIO pull

Definition at line 73 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

uint32_t GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIO speed

Definition at line 76 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_gpio.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO pins

Defines
GPIO pins
GPIO Exported Constants

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */

Define Documentation

#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */

Definition at line 102 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */

Definition at line 103 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */

Definition at line 112 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */

Definition at line 113 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */

Definition at line 114 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */

Definition at line 115 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */

Definition at line 116 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */

Definition at line 117 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */

Definition at line 104 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */

Definition at line 105 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */

Definition at line 106 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */

Definition at line 107 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */

Definition at line 108 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */

Definition at line 109 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */

Definition at line 110 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */

Definition at line 111 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */

Definition at line 118 of file stm32l4xx_hal_gpio.h.

#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */

Definition at line 120 of file stm32l4xx_hal_gpio.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO mode

Defines
GPIO mode
GPIO Exported Constants

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ. More...

Defines

#define | GPIO_MODE_INPUT ((uint32_t)0x00000000)
#define | GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001)
#define | GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011)
#define | GPIO_MODE_AF_PP ((uint32_t)0x00000002)
#define | GPIO_MODE_AF_OD ((uint32_t)0x00000012)
#define | GPIO_MODE_ANALOG ((uint32_t)0x00000003)
#define | GPIO_MODE_ANALOG_ADC_CONTROL ((uint32_t)0x0000000B)
#define | GPIO_MODE_IT_RISING ((uint32_t)0x10110000)
#define | GPIO_MODE_IT_FALLING ((uint32_t)0x10210000)
#define | GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000)
#define | GPIO_MODE_EVT_RISING ((uint32_t)0x10120000)
#define | GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000)
#define | GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000)

Detailed Description

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

  • X : GPIO mode or EXTI Mode
  • y : External IT or Event trigger detection
  • z : IO configuration on External IT or Event
  • Y : Output type (Push Pull or Open Drain)
  • Z : IO Direction mode (Input, Output, Alternate or Analog)

Define Documentation

#define GPIO_MODE_AF_OD ((uint32_t)0x00000012)

Alternate Function Open Drain Mode

Definition at line 139 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_AF_PP ((uint32_t)0x00000002)

Alternate Function Push Pull Mode

Definition at line 138 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

#define GPIO_MODE_ANALOG ((uint32_t)0x00000003)

Analog Mode

Definition at line 140 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCCEx_EnableLSCO().

#define GPIO_MODE_ANALOG_ADC_CONTROL ((uint32_t)0x0000000B)

Analog Mode for ADC conversion

Definition at line 141 of file stm32l4xx_hal_gpio.h.

#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000)

External Event Mode with Falling edge trigger detection

Definition at line 146 of file stm32l4xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000)

External Event Mode with Rising edge trigger detection

Definition at line 145 of file stm32l4xx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000)

External Event Mode with Rising/Falling edge trigger detection

Definition at line 147 of file stm32l4xx_hal_gpio.h.

#define GPIO_MODE_INPUT ((uint32_t)0x00000000)

Input Floating Mode

Definition at line 135 of file stm32l4xx_hal_gpio.h.

#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000)

External Interrupt Mode with Falling edge trigger detection

Definition at line 143 of file stm32l4xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000)

External Interrupt Mode with Rising edge trigger detection

Definition at line 142 of file stm32l4xx_hal_gpio.h.

#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 144 of file stm32l4xx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011)

Output Open Drain Mode

Definition at line 137 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001)

Output Push Pull Mode

Definition at line 136 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO speed

Defines
GPIO speed
GPIO Exported Constants

GPIO Output Maximum frequency. More...

Defines

#define | GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000)
#define | GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001)
#define | GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002)
#define | GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003)

Detailed Description

GPIO Output Maximum frequency.

Define Documentation

#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002)

range 25 MHz to 50 MHz, please refer to the product datasheet

Definition at line 158 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000)

range up to 5 MHz, please refer to the product datasheet

Definition at line 156 of file stm32l4xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001)

range 5 MHz to 25 MHz, please refer to the product datasheet

Definition at line 157 of file stm32l4xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003)

range 50 MHz to 80 MHz, please refer to the product datasheet

Definition at line 159 of file stm32l4xx_hal_gpio.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO pull

Defines
GPIO pull
GPIO Exported Constants

GPIO Pull-Up or Pull-Down Activation. More...

Defines

#define | GPIO_NOPULL ((uint32_t)0x00000000)
#define | GPIO_PULLUP ((uint32_t)0x00000001)
#define | GPIO_PULLDOWN ((uint32_t)0x00000002)

Detailed Description

GPIO Pull-Up or Pull-Down Activation.

Define Documentation

#define GPIO_NOPULL ((uint32_t)0x00000000)

No Pull-up or Pull-down activation

Definition at line 168 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig(), and HAL_RCCEx_EnableLSCO().

#define GPIO_PULLDOWN ((uint32_t)0x00000002)

Pull-down activation

Definition at line 170 of file stm32l4xx_hal_gpio.h.

#define GPIO_PULLUP ((uint32_t)0x00000001)

Pull-up activation

Definition at line 169 of file stm32l4xx_hal_gpio.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO Exported Macros

Defines
GPIO Exported Macros
GPIO

Defines

#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generate a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_GPIO_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI->PR1 = (__EXTI_LINE__))

Clear the EXTI's line pending flags.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines flags to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 198 of file stm32l4xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_IT ( __EXTI_LINE__ ) (EXTI->PR1 = (__EXTI_LINE__))

Clear the EXTI's line pending bits.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 214 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER1 |= (__EXTI_LINE__))

Generate a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
None

Definition at line 222 of file stm32l4xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI->PR1 & (__EXTI_LINE__))

Check whether the specified EXTI line flag is set or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line flag to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 190 of file stm32l4xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_IT ( __EXTI_LINE__ ) (EXTI->PR1 & (__EXTI_LINE__))

Check whether the specified EXTI line is asserted or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 206 of file stm32l4xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIOEx Alternate function selection

Defines
GPIOEx Alternate function selection
GPIOEx Exported Constants

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define | GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
#define | GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
#define | GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define | GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define | GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define | GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define | GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define | GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#define | GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
#define | GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define | GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
AF 12 selection.
#define | GPIO_AF12_SWPMI1 ((uint8_t)0xC) /* SWPMI1 Alternate Function mapping */
#define | GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
#define | GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
#define | GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
#define | GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
AF 13 selection.
#define | GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
#define | GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
AF 14 selection.
#define | GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define | GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define | GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
#define | GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
#define | GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)

Define Documentation

#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */

Definition at line 77 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */

Definition at line 74 of file stm32l4xx_hal_gpio_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */

AF 0 selection.

Definition at line 73 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */

Definition at line 75 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */

Definition at line 79 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */

AF 10 selection.

Definition at line 151 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */

Definition at line 153 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */

AF 11 selection.

Definition at line 159 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */

Definition at line 167 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */

Definition at line 168 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */

AF 12 selection.

Definition at line 165 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */

Definition at line 169 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF12_SWPMI1 ((uint8_t)0xC) /* SWPMI1 Alternate Function mapping */

Definition at line 166 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */

AF 13 selection.

Definition at line 174 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */

Definition at line 175 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */

Definition at line 177 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */

Definition at line 176 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */

Definition at line 186 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */

Definition at line 183 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */

Definition at line 184 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */

Definition at line 185 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */

AF 14 selection.

Definition at line 182 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */

Definition at line 187 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */

AF 15 selection.

Definition at line 192 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */

Definition at line 89 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */

Definition at line 88 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */

AF 1 selection.

Definition at line 84 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */

Definition at line 85 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */

Definition at line 86 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */

Definition at line 87 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */

AF 2 selection.

Definition at line 94 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */

Definition at line 95 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */

Definition at line 96 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */

Definition at line 97 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */

Definition at line 98 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */

Definition at line 105 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */

Definition at line 104 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */

AF 3 selection.

Definition at line 103 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */

AF 4 selection.

Definition at line 110 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */

Definition at line 111 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */

Definition at line 112 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */

AF 5 selection.

Definition at line 117 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */

Definition at line 118 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */

Definition at line 124 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */

AF 6 selection.

Definition at line 123 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */

AF 7 selection.

Definition at line 129 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */

Definition at line 130 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */

Definition at line 131 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */

Definition at line 138 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */

AF 8 selection.

Definition at line 136 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */

Definition at line 137 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */

AF 9 selection.

Definition at line 144 of file stm32l4xx_hal_gpio_ex.h.

#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */

Definition at line 145 of file stm32l4xx_hal_gpio_ex.h.

#define IS_GPIO_AF ( AF ) ((AF) <= (uint8_t)0x0F)

Definition at line 194 of file stm32l4xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIOEx_Get Port Index

Defines
GPIOEx_Get Port Index
GPIOEx Exported Macros

Defines

#define GPIO_GET_INDEX(__GPIOx__)

Define Documentation

#define GPIO_GET_INDEX ( __GPIOx__ )
Value:
(((__GPIOx__) == (GPIOA))? 0U :\
                                      ((__GPIOx__) == (GPIOB))? 1U :\
                                      ((__GPIOx__) == (GPIOC))? 2U :\
                                      ((__GPIOx__) == (GPIOD))? 3U :\
                                      ((__GPIOx__) == (GPIOE))? 4U :\
                                      ((__GPIOx__) == (GPIOF))? 5U :\
                                      ((__GPIOx__) == (GPIOG))? 6U : 7U)

Definition at line 350 of file stm32l4xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HCD Private Functions

Functions
HCD Private Functions
HCD

Functions

static void | HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel IN interrupt requests.
static void | HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel OUT interrupt requests.
static void | HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Rx Queue Level interrupt requests.
static void | HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Host Port interrupt requests.

Function Documentation

static void HCD_HC_IN_IRQHandler | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  | [static]

Handle Host Channel IN interrupt requests.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
none

Definition at line 809 of file stm32l4xx_hal_hcd.c.

References __HAL_HCD_CLEAR_HC_INT, __HAL_HCD_MASK_HALT_HC_INT, __HAL_HCD_UNMASK_HALT_HC_INT, HAL_HCD_HC_NotifyURBChange_Callback(), HCD_HandleTypeDef::hc, HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_HC_OUT_IRQHandler | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  | [static]

Handle Host Channel OUT interrupt requests.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
none

Definition at line 954 of file stm32l4xx_hal_hcd.c.

References __HAL_HCD_CLEAR_HC_INT, __HAL_HCD_MASK_HALT_HC_INT, __HAL_HCD_UNMASK_HALT_HC_INT, HAL_HCD_HC_NotifyURBChange_Callback(), HCD_HandleTypeDef::hc, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_Port_IRQHandler ( HCD_HandleTypeDef * hhcd ) [static]

Handle Host Port interrupt requests.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 1150 of file stm32l4xx_hal_hcd.c.

References HAL_HCD_Connect_Callback(), HCD_SPEED_FULL, HCD_SPEED_HIGH, HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

static void HCD_RXQLVL_IRQHandler ( HCD_HandleTypeDef * hhcd ) [static]

Handle Rx Queue Level interrupt requests.

Parameters:
hhcd,: HCD handle
Return values:
none

Definition at line 1097 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::hc, and HCD_HandleTypeDef::Instance.

Referenced by HAL_HCD_IRQHandler().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
HCD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the Host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a Host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a Host channel.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the Host driver.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
          ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_HCD_DeInit ( HCD_HandleTypeDef * hhcd )

DeInitialize the Host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 245 of file stm32l4xx_hal_hcd.c.

References __HAL_HCD_DISABLE, HAL_HCD_MspDeInit(), HAL_HCD_STATE_BUSY, HAL_HCD_STATE_RESET, and HCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_HCD_HC_Halt | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num
 | ) |  |

Halt a Host channel.

Parameters:
hhcd,: HCD handle
ch_num,: Channel number. This parameter can be a value from 1 to 15
Return values:
HAL status

Definition at line 229 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_HC_Init | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | epnum,
 |  | uint8_t | dev_address,
 |  | uint8_t | speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | mps
 | ) |  |

Initialize a Host channel.

Parameters:
hhcd,: HCD handle
ch_num,: Channel number. This parameter can be a value from 1 to 15
epnum,: Endpoint number. This parameter can be a value from 1 to 15
dev_address : Current device address This parameter can be a value from 0 to 255
speed,: Current device speed. This parameter can be one of these values: HCD_SPEED_HIGH: High speed mode, HCD_SPEED_FULL: Full speed mode, HCD_SPEED_LOW: Low speed mode
ep_type,: Endpoint Type. This parameter can be one of these values: EP_TYPE_CTRL: Control type, EP_TYPE_ISOC: Isochronous type, EP_TYPE_BULK: Bulk type, EP_TYPE_INTR: Interrupt type
mps,: Max Packet Size. This parameter can be a value from 0 to32K
Return values:
HAL status

Definition at line 190 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::hc, and HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Init ( HCD_HandleTypeDef * hhcd )

Initialize the Host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 127 of file stm32l4xx_hal_hcd.c.

References __HAL_HCD_DISABLE, assert_param, HAL_HCD_MspInit(), HAL_HCD_STATE_BUSY, HAL_HCD_STATE_READY, HAL_HCD_STATE_RESET, HCD_HandleTypeDef::Init, HCD_HandleTypeDef::Instance, HCD_HandleTypeDef::Lock, and HCD_HandleTypeDef::State.

void HAL_HCD_MspDeInit ( HCD_HandleTypeDef * hhcd )

DeInitialize the HCD MSP.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 285 of file stm32l4xx_hal_hcd.c.

Referenced by HAL_HCD_DeInit().

void HAL_HCD_MspInit ( HCD_HandleTypeDef * hhcd )

Initialize the HCD MSP.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 270 of file stm32l4xx_hal_hcd.c.

Referenced by HAL_HCD_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
HCD Exported Functions

HCD IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.

Detailed Description

HCD IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..] This subsection provides a set of functions allowing to manage the USB Host Data
    Transfer

Function Documentation

void HAL_HCD_Connect_Callback ( HCD_HandleTypeDef * hhcd )

Connection Event callback.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 579 of file stm32l4xx_hal_hcd.c.

Referenced by HCD_Port_IRQHandler().

void HAL_HCD_Disconnect_Callback ( HCD_HandleTypeDef * hhcd )

Disconnection Event callback.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 594 of file stm32l4xx_hal_hcd.c.

Referenced by HAL_HCD_IRQHandler().

void HAL_HCD_HC_NotifyURBChange_Callback | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum,
 |  | HCD_URBStateTypeDef | urb_state
 | ) |  |

Notify URB state change callback.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
urb_state,: This parameter can be one of these values: URB_IDLE/ URB_DONE/ URB_NOTREADY/ URB_NYET/ URB_ERROR/ URB_STALL/
Return values:
None

Definition at line 619 of file stm32l4xx_hal_hcd.c.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | ch_num,
 |  | uint8_t | direction,
 |  | uint8_t | ep_type,
 |  | uint8_t | token,
 |  | uint8_t * | pbuff,
 |  | uint16_t | length,
 |  | uint8_t | do_ping
 | ) |  |

Submit a new URB for processing.

Parameters:
hhcd,: HCD handle
ch_num,: Channel number. This parameter can be a value from 1 to 15
direction,: Channel number. This parameter can be one of these values: 0 : Output / 1 : Input
ep_type,: Endpoint Type. This parameter can be one of these values: EP_TYPE_CTRL: Control type/ EP_TYPE_ISOC: Isochronous type/ EP_TYPE_BULK: Bulk type/ EP_TYPE_INTR: Interrupt type/
token,: Endpoint Type. This parameter can be one of these values: 0: HC_PID_SETUP / 1: HC_PID_DATA1
pbuff,: pointer to URB data
length,: Length of URB data
do_ping,: activate do ping protocol (for high speed only). This parameter can be one of these values: 0 : do ping inactive / 1 : do ping active
Return values:
HAL status

Definition at line 337 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::hc, HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

void HAL_HCD_IRQHandler ( HCD_HandleTypeDef * hhcd )

Handle HCD interrupt request.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 461 of file stm32l4xx_hal_hcd.c.

References __HAL_HCD_CLEAR_FLAG, __HAL_HCD_GET_FLAG, __HAL_HCD_IS_INVALID_INTERRUPT, HAL_HCD_Disconnect_Callback(), HAL_HCD_SOF_Callback(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), HCD_Port_IRQHandler(), HCD_RXQLVL_IRQHandler(), HCD_HandleTypeDef::Init, and HCD_HandleTypeDef::Instance.

void HAL_HCD_SOF_Callback ( HCD_HandleTypeDef * hhcd )

SOF callback.

Parameters:
hhcd,: HCD handle
Return values:
None

Definition at line 564 of file stm32l4xx_hal_hcd.c.

Referenced by HAL_HCD_IRQHandler().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
HCD Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the Host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the Host driver.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the Host port.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the HCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_HCD_ResetPort ( HCD_HandleTypeDef * hhcd )

Reset the Host port.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 683 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Start ( HCD_HandleTypeDef * hhcd )

Start the Host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 655 of file stm32l4xx_hal_hcd.c.

References __HAL_HCD_ENABLE, and HCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HCD_Stop ( HCD_HandleTypeDef * hhcd )

Stop the Host driver.

Parameters:
hhcd,: HCD handle
Return values:
HAL status

Definition at line 670 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

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STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
HCD Exported Functions

Peripheral State functions. More...

Functions

HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last Host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_HCD_GetCurrentFrame ( HCD_HandleTypeDef * hhcd )

Return the current Host frame number.

Parameters:
hhcd,: HCD handle
Return values:
Current Host frame number

Definition at line 776 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

uint32_t HAL_HCD_GetCurrentSpeed ( HCD_HandleTypeDef * hhcd )

Return the Host enumeration speed.

Parameters:
hhcd,: HCD handle
Return values:
Enumeration speed

Definition at line 786 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::Instance.

HCD_StateTypeDef HAL_HCD_GetState ( HCD_HandleTypeDef * hhcd )

Return the HCD handle state.

Parameters:
hhcd,: HCD handle
Return values:
HAL state

Definition at line 712 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::State.

HCD_HCStateTypeDef HAL_HCD_HC_GetState | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return the Host Channel state.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
Host channel state This parameter can be one of these values: HC_IDLE/ HC_XFRC/ HC_HALTED/ HC_NYET/ HC_NAK/ HC_STALL/ HC_XACTERR/ HC_BBLERR/ HC_DATATGLERR

Definition at line 766 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::hc.

HCD_URBStateTypeDef HAL_HCD_HC_GetURBState | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return URB state for a channel.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
URB state. This parameter can be one of these values: URB_IDLE/ URB_DONE/ URB_NOTREADY/ URB_NYET/ URB_ERROR/ URB_STALL

Definition at line 731 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::hc.

uint32_t HAL_HCD_HC_GetXferCount | ( | HCD_HandleTypeDef * | hhcd,
 |  | uint8_t | chnum
 | ) |  |

Return the last Host transfer size.

Parameters:
hhcd,: HCD handle
chnum,: Channel number. This parameter can be a value from 1 to 15
Return values:
last transfer size in byte

Definition at line 744 of file stm32l4xx_hal_hcd.c.

References HCD_HandleTypeDef::hc.

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STM32L486xx HAL User Manual: HCD State Structure definition

Typedefs | Enumerations
HCD State Structure definition
HCD Exported Types

Typedefs

typedef USB_OTG_GlobalTypeDef | HCD_TypeDef
typedef USB_OTG_CfgTypeDef | HCD_InitTypeDef
typedef USB_OTG_HCTypeDef | HCD_HCTypeDef
typedef USB_OTG_URBStateTypeDef | HCD_URBStateTypeDef
typedef USB_OTG_HCStateTypeDef | HCD_HCStateTypeDef

Enumerations

enum HCD_StateTypeDef {
HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, HAL_HCD_STATE_ERROR = 0x02, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
}

Typedef Documentation

typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef

Definition at line 80 of file stm32l4xx_hal_hcd.h.

typedef USB_OTG_HCTypeDef HCD_HCTypeDef

Definition at line 78 of file stm32l4xx_hal_hcd.h.

typedef USB_OTG_CfgTypeDef HCD_InitTypeDef

Definition at line 77 of file stm32l4xx_hal_hcd.h.

typedef USB_OTG_GlobalTypeDef HCD_TypeDef

Definition at line 76 of file stm32l4xx_hal_hcd.h.

typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef

Definition at line 79 of file stm32l4xx_hal_hcd.h.

Enumeration Type Documentation

enum HCD_StateTypeDef
Enumerator:
HAL_HCD_STATE_RESET
HAL_HCD_STATE_READY
HAL_HCD_STATE_ERROR
HAL_HCD_STATE_BUSY
HAL_HCD_STATE_TIMEOUT

Definition at line 67 of file stm32l4xx_hal_hcd.h.

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STM32L486xx HAL User Manual: HCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HCD_HandleTypeDef Struct Reference
HCD Handle Structure definition

#include <stm32l4xx_hal_hcd.h>

Data Fields

HCD_TypeDef * Instance
HCD_InitTypeDef Init
HCD_HCTypeDef | hc [15]
HAL_LockTypeDef | Lock
__IO HCD_StateTypeDef | State
void * | pData

Detailed Description

Definition at line 88 of file stm32l4xx_hal_hcd.h.

Field Documentation

HCD_HCTypeDef HCD_HandleTypeDef::hc[15]

Host channels parameters

Definition at line 92 of file stm32l4xx_hal_hcd.h.

Referenced by HAL_HCD_HC_GetState(), HAL_HCD_HC_GetURBState(), HAL_HCD_HC_GetXferCount(), HAL_HCD_HC_Init(), HAL_HCD_HC_SubmitRequest(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), and HCD_RXQLVL_IRQHandler().

HCD_InitTypeDef HCD_HandleTypeDef::Init

HCD required parameters

Definition at line 91 of file stm32l4xx_hal_hcd.h.

Referenced by HAL_HCD_HC_SubmitRequest(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), HCD_HC_IN_IRQHandler(), and HCD_Port_IRQHandler().

HCD_TypeDef* HCD_HandleTypeDef::Instance

Register base address

Definition at line 90 of file stm32l4xx_hal_hcd.h.

Referenced by HAL_HCD_GetCurrentFrame(), HAL_HCD_GetCurrentSpeed(), HAL_HCD_HC_Halt(), HAL_HCD_HC_Init(), HAL_HCD_HC_SubmitRequest(), HAL_HCD_Init(), HAL_HCD_IRQHandler(), HAL_HCD_ResetPort(), HAL_HCD_Start(), HAL_HCD_Stop(), HCD_HC_IN_IRQHandler(), HCD_HC_OUT_IRQHandler(), HCD_Port_IRQHandler(), and HCD_RXQLVL_IRQHandler().

HAL_LockTypeDef HCD_HandleTypeDef::Lock

HCD peripheral status

Definition at line 93 of file stm32l4xx_hal_hcd.h.

Referenced by HAL_HCD_Init().

void* HCD_HandleTypeDef::pData

Pointer Stack Handler

Definition at line 95 of file stm32l4xx_hal_hcd.h.

__IO HCD_StateTypeDef HCD_HandleTypeDef::State

HCD communication state

Definition at line 94 of file stm32l4xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), HAL_HCD_GetState(), and HAL_HCD_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_hcd.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HCD Speed

Defines
HCD Speed
HCD Exported Constants

Defines

#define | HCD_SPEED_HIGH 0
#define | HCD_SPEED_LOW 2
#define | HCD_SPEED_FULL 3

Define Documentation

#define HCD_SPEED_FULL 3

Definition at line 116 of file stm32l4xx_hal_hcd.h.

Referenced by HCD_Port_IRQHandler().

#define HCD_SPEED_HIGH 0

Definition at line 114 of file stm32l4xx_hal_hcd.h.

Referenced by HCD_Port_IRQHandler().

#define HCD_SPEED_LOW 2

Definition at line 115 of file stm32l4xx_hal_hcd.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HCD PHY Module

Defines
HCD PHY Module
HCD Exported Constants

Defines

#define HCD_PHY_EMBEDDED 1

Define Documentation

#define HCD_PHY_EMBEDDED 1

Definition at line 124 of file stm32l4xx_hal_hcd.h.

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STM32L486xx HAL User Manual: HCD Exported Macros

Defines
HCD Exported Macros
HCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define | __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define | __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_HCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))

Definition at line 142 of file stm32l4xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_CLEAR_HC_INT | ( | chnum,
 |  | __INTERRUPT__
 | ) | (USBx_HC(chnum)->HCINT = (__INTERRUPT__))

Definition at line 145 of file stm32l4xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

#define __HAL_HCD_DISABLE ( __HANDLE__ ) USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 139 of file stm32l4xx_hal_hcd.h.

Referenced by HAL_HCD_DeInit(), and HAL_HCD_Init().

#define __HAL_HCD_ENABLE ( __HANDLE__ ) USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 138 of file stm32l4xx_hal_hcd.h.

Referenced by HAL_HCD_Start().

#define __HAL_HCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 141 of file stm32l4xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_IS_INVALID_INTERRUPT ( __HANDLE__ ) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)

Definition at line 143 of file stm32l4xx_hal_hcd.h.

Referenced by HAL_HCD_IRQHandler().

#define __HAL_HCD_MASK_ACK_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)

Definition at line 148 of file stm32l4xx_hal_hcd.h.

#define __HAL_HCD_MASK_HALT_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)

Definition at line 146 of file stm32l4xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

#define __HAL_HCD_UNMASK_ACK_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

Definition at line 149 of file stm32l4xx_hal_hcd.h.

#define __HAL_HCD_UNMASK_HALT_HC_INT ( chnum ) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)

Definition at line 147 of file stm32l4xx_hal_hcd.h.

Referenced by HCD_HC_IN_IRQHandler(), and HCD_HC_OUT_IRQHandler().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HCD Private Macros

HCD Private Macros
HCD
Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Private Define

Defines
I2C Private Define
I2C

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~HAL_I2C_STATE_READY)))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_XFER_TX_IT (0x00000001U)
#define | I2C_XFER_RX_IT (0x00000002U)
#define | I2C_XFER_LISTEN_IT (0x00000004U)
#define | I2C_XFER_ERROR_IT (0x00000011U)
#define | I2C_XFER_CPLT_IT (0x00000012U)
#define | I2C_XFER_RELOAD_IT (0x00000012U)

Define Documentation

#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 281 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), and I2C_ITMasterSequentialCplt().

#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 280 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITMasterSequentialCplt().

#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))

Memory Busy RX, combinaison of State LSB and Mode enum

Definition at line 285 of file stm32l4xx_hal_i2c.c.

#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))

Memory Busy TX, combinaison of State LSB and Mode enum

Definition at line 284 of file stm32l4xx_hal_i2c.c.

#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~HAL_I2C_STATE_READY)))

Mask State define, keep only RX and TX bits

Definition at line 278 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT().

#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))

Default Value

Definition at line 279 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), and I2C_ITSlaveCplt().

#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 283 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITSlaveSequentialCplt().

#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 282 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Sequential_Transmit_IT(), and I2C_ITSlaveSequentialCplt().

#define I2C_TIMEOUT_ADDR (10000U)

10 s

Definition at line 263 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_BUSY (25U)

25 ms

Definition at line 264 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), and HAL_I2C_Mem_Write().

#define I2C_TIMEOUT_DIR (25U)

25 ms

Definition at line 265 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_FLAG (25U)

25 ms

Definition at line 271 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define I2C_TIMEOUT_RXNE (25U)

25 ms

Definition at line 266 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_STOPF (25U)

25 ms

Definition at line 267 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_TC (25U)

25 ms

Definition at line 268 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_TCR (25U)

25 ms

Definition at line 269 of file stm32l4xx_hal_i2c.c.

#define I2C_TIMEOUT_TXIS (25U)

25 ms

Definition at line 270 of file stm32l4xx_hal_i2c.c.

#define I2C_XFER_CPLT_IT (0x00000012U)

Definition at line 294 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), and I2C_Master_ISR_DMA().

#define I2C_XFER_ERROR_IT (0x00000011U)

Definition at line 293 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_XFER_LISTEN_IT (0x00000004U)

Definition at line 291 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

#define I2C_XFER_RELOAD_IT (0x00000012U)

Definition at line 295 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Enable_IRQ().

#define I2C_XFER_RX_IT (0x00000002U)

Definition at line 290 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

#define I2C_XFER_TX_IT (0x00000001U)

Definition at line 289 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

#define MAX_NBYTE_SIZE 255U

Definition at line 273 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define SlaveAddr_MSK 0x06U

Definition at line 275 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define SlaveAddr_SHIFT 7U

Definition at line 274 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define TIMING_CLEAR_MASK (0xF0FFFFFFU)

I2C TIMING clear register Mask

Definition at line 262 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Private Functions

Functions
I2C Private Functions
I2C

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles Acknowledge failed detection during an I2C Communication.
static HAL_StatusTypeDef | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Function Documentation

static HAL_StatusTypeDef I2C_Disable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
HAL status

Definition at line 4746 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_STATE_LISTEN, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

static void I2C_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 4389 of file stm32l4xx_hal_i2c.c.

References HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_STATE_ABORT, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, __I2C_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __I2C_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by I2C_ITError().

static void I2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4372 of file stm32l4xx_hal_i2c.c.

References HAL_I2C_ERROR_DMA, I2C_ITError(), __I2C_HandleTypeDef::Instance, and __DMA_HandleTypeDef::Parent.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_DMAMasterReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4318 of file stm32l4xx_hal_i2c.c.

References HAL_DMA_Start_IT(), __I2C_HandleTypeDef::hdmarx, I2C_Enable_IRQ(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __DMA_HandleTypeDef::Parent, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), and HAL_I2C_Mem_Read_DMA().

static void I2C_DMAMasterTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4264 of file stm32l4xx_hal_i2c.c.

References HAL_DMA_Start_IT(), __I2C_HandleTypeDef::hdmatx, I2C_Enable_IRQ(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __DMA_HandleTypeDef::Parent, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Transmit_DMA(), and HAL_I2C_Mem_Write_DMA().

static void I2C_DMASlaveReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4360 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Slave_Receive_DMA().

static void I2C_DMASlaveTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 4306 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Slave_Transmit_DMA().

static HAL_StatusTypeDef I2C_Enable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
HAL status

Definition at line 4673 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_Master_ISR_DMA(), I2C_Slave_ISR_DMA(), I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::XferISR.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Master_ISR_DMA().

static void I2C_Flush_TXDR ( I2C_HandleTypeDef * hi2c ) [static]

I2C Tx data register flush process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 4243 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_FLAG_TXE, I2C_FLAG_TXIS, and __I2C_HandleTypeDef::Instance.

Referenced by I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_IsAcknowledgeFailed | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles Acknowledge failed detection during an I2C Communication.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4577 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

static void I2C_ITAddrCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Address complete process callback.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 3730 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::AddrEventCount, HAL_I2C_AddrCallback(), HAL_I2C_STATE_LISTEN, I2C_ADDRESSINGMODE_10BIT, I2C_Disable_IRQ(), I2C_FLAG_ADDR, I2C_GET_ADDR_MATCH, I2C_GET_DIR, I2C_GET_OWN_ADDRESS1, I2C_GET_OWN_ADDRESS2, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Init, SlaveAddr_MSK, SlaveAddr_SHIFT, and __I2C_HandleTypeDef::State.

Referenced by I2C_Slave_ISR_IT().

static void I2C_ITError | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ErrorCode
 | ) |  | [static]

I2C interrupts error process.

Parameters:
hi2c | I2C handle.
ErrorCode | Error code to handle.
Return values:
None

Definition at line 4141 of file stm32l4xx_hal_i2c.c.

References __DMA_HandleTypeDef::ErrorCode, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_DMAError(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITListenCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Listen complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 4097 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_ITSlaveCplt(), and I2C_Slave_ISR_IT().

static void I2C_ITMasterCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Master complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 3899 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_ITError(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITMasterSequentialCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Master sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 3810 of file stm32l4xx_hal_i2c.c.

References HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

Referenced by I2C_Master_ISR_IT().

static void I2C_ITSlaveCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Slave complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 3991 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_FLAG_ADDR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_GET_DMA_REMAIN_DATA, I2C_ITError(), I2C_ITListenCplt(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITSlaveSequentialCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Slave sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 3855 of file stm32l4xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_Disable_IRQ(), I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

Referenced by I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_Master_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 3460 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_Flush_TXDR(), I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_ITError(), I2C_ITMasterCplt(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_CPLT_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Master_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 3226 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, I2C_AUTOEND_MODE, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_RequestMemoryRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 3669 of file stm32l4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_TC, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

static HAL_StatusTypeDef I2C_RequestMemoryWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 3603 of file stm32l4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_Slave_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 3549 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_GET_DMA_REMAIN_DATA, I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_STOPI, and I2C_ITSlaveCplt().

Referenced by HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Slave_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 3347 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TXI, I2C_ITAddrCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSequentialCplt(), I2C_LAST_FRAME, I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), and I2C_ITError().

static void I2C_TransferConfig | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hi2c | I2C handle.
DevAddress | Specifies the slave address to be programmed.
Size | Specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_RELOAD_MODE Enable Reload mode .
  • I2C_AUTOEND_MODE Enable Automatic end mode.
  • I2C_SOFTEND_MODE Enable Software end mode.
Request New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_NO_STARTSTOP Don't Generate stop and start condition.
  • I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • I2C_GENERATE_START_READ Generate Restart for read request.
  • I2C_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 4643 of file stm32l4xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::Instance, IS_TRANSFER_MODE, and IS_TRANSFER_REQUEST.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Flag | Specifies the I2C flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4425 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, HAL_GetTick(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4525 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), and HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of STOP flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4491 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of TXIS flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4454 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_TXIS, I2C_IsAcknowledgeFailed(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2C_DeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C peripheral.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 487 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_DISABLE, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspDeInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_RESET, I2C_STATE_NONE, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Init ( I2C_HandleTypeDef * hi2c )

Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 402 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, I2C_InitTypeDef::AddressingMode, assert_param, I2C_InitTypeDef::DualAddressMode, __I2C_HandleTypeDef::ErrorCode, I2C_InitTypeDef::GeneralCallMode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, I2C_ADDRESSINGMODE_10BIT, I2C_ADDRESSINGMODE_7BIT, I2C_STATE_NONE, __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, IS_I2C_ADDRESSING_MODE, IS_I2C_DUAL_ADDRESS, IS_I2C_GENERAL_CALL, IS_I2C_NO_STRETCH, IS_I2C_OWN_ADDRESS1, IS_I2C_OWN_ADDRESS2, IS_I2C_OWN_ADDRESS2_MASK, __I2C_HandleTypeDef::Lock, __I2C_HandleTypeDef::Mode, I2C_InitTypeDef::NoStretchMode, I2C_InitTypeDef::OwnAddress1, I2C_InitTypeDef::OwnAddress2, I2C_InitTypeDef::OwnAddress2Masks, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, I2C_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_I2C_MspDeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 539 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit().

void HAL_I2C_MspInit ( I2C_HandleTypeDef * hi2c )

Initialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 523 of file stm32l4xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
I2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2C_DisableListen_IT ( I2C_HandleTypeDef * hi2c )

Disable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C
Return values:
HAL status

Definition at line 2850 of file stm32l4xx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MSK, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_EnableListen_IT ( I2C_HandleTypeDef * hi2c )

Enable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 2826 of file stm32l4xx_hal_i2c.c.

References HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_IsDeviceReady | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2436 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_TIMEOUT, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_GENERATE_START, I2C_WaitOnFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Abort_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master I2C IT or DMA process communication with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
Return values:
HAL status

Definition at line 2882 of file stm32l4xx_hal_i2c.c.

References HAL_I2C_MODE_MASTER, HAL_I2C_STATE_ABORT, I2C_AUTOEND_MODE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_GENERATE_STOP, I2C_TransferConfig(), I2C_XFER_CPLT_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 745 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1480 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1207 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_RX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 2627 of file stm32l4xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 2554 of file stm32l4xx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_SLAVE_BUSY_TX, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 622 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1373 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1139 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1871 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in non-blocking mode with DMA from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be read
Return values:
HAL status

Definition at line 2323 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in non-blocking mode with Interrupt from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2111 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1720 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with DMA to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2208 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_Master_ISR_DMA(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with Interrupt to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2013 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1008 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1651 of file stm32l4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1323 of file stm32l4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 2764 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 2698 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 868 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ADDRESSINGMODE_10BIT, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1585 of file stm32l4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1274 of file stm32l4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
I2C Exported Functions

Functions

void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.

Function Documentation

void HAL_I2C_AbortCpltCallback ( I2C_HandleTypeDef * hi2c )

I2C abort callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3143 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_AddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
TransferDirection,: Master request Transfer Direction (Write/Read), value of I2C Sequential Transfer Options
AddrMatchCode,: Address Match Code
Return values:
None

Definition at line 3061 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

void HAL_I2C_ER_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C error interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2951 of file stm32l4xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_OVR, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_OVR, I2C_IT_ERRI, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

void HAL_I2C_ErrorCallback ( I2C_HandleTypeDef * hi2c )

I2C error callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3127 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_EV_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C event interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2932 of file stm32l4xx_hal_i2c.c.

References __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferISR.

void HAL_I2C_ListenCpltCallback ( I2C_HandleTypeDef * hi2c )

Listen Complete callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3079 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITListenCplt(), and I2C_ITSlaveCplt().

void HAL_I2C_MasterRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3012 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt(), and I2C_ITMasterSequentialCplt().

void HAL_I2C_MasterTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 2996 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt(), and I2C_ITMasterSequentialCplt().

void HAL_I2C_MemRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3111 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt().

void HAL_I2C_MemTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3095 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITMasterCplt().

void HAL_I2C_SlaveRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3043 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

void HAL_I2C_SlaveTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3027 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State, Mode and Error functions

Functions
Peripheral State, Mode and Error functions
I2C Exported Functions

Peripheral State, Mode and Error functions. More...

Functions

HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Peripheral State, Mode and Error functions.

 ===============================================================================
            ##### Peripheral State, Mode and Error functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2C_GetError ( I2C_HandleTypeDef * hi2c )

Return the I2C error code.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
I2C Error Code

Definition at line 3201 of file stm32l4xx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode.

HAL_I2C_ModeTypeDef HAL_I2C_GetMode ( I2C_HandleTypeDef * hi2c )

Returns the I2C Master, Slave, Memory or no mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL mode

Definition at line 3190 of file stm32l4xx_hal_i2c.c.

References __I2C_HandleTypeDef::Mode.

HAL_I2C_StateTypeDef HAL_I2C_GetState ( I2C_HandleTypeDef * hi2c )

Return the I2C handle state.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL state

Definition at line 3178 of file stm32l4xx_hal_i2c.c.

References __I2C_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_InitTypeDef Struct Reference
I2C Configuration Structure definition

#include <stm32l4xx_hal_i2c.h>

Data Fields

uint32_t | Timing
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

Definition at line 66 of file stm32l4xx_hal_i2c.h.

Field Documentation

uint32_t I2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of I2C Addressing Mode

Definition at line 75 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

uint32_t I2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of I2C Dual Addressing Mode

Definition at line 78 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of I2C General Call Addressing Mode

Definition at line 87 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of I2C No-Stretch Mode

Definition at line 90 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 72 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 81 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2Masks

Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of I2C Own Address2 Masks

Definition at line 84 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::Timing

Specifies the I2C_TIMINGR_register value. This parameter calculated by referring to I2C initialization section in Reference manual

Definition at line 68 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_i2c.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HAL state structure definition

Enumerations
HAL state structure definition
I2C Exported Types

HAL State structure definition. More...

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}

Detailed Description

HAL State structure definition.

Note:
HAL I2C State value coding follow below described bitmap :
b7-b6 Error information
00 : No Error
01 : Abort (Abort user request on going)
10 : Timeout
11 : Error
b5 IP initilisation status
0 : Reset (IP not initialized)
1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
b4 (not used)
x : Should be set to 0
b3
0 : Ready or Busy (No Listen mode ongoing)
1 : Listen (IP in Address Listen Mode)
b2 Intrinsic process state
0 : Ready
1 : Busy (IP busy with some configuration or internal operations)
b1 Rx state
0 : Ready (no Rx operation ongoing)
1 : Busy (Rx operation ongoing)
b0 Tx state
0 : Ready (no Tx operation ongoing)
1 : Busy (Tx operation ongoing)

Enumeration Type Documentation

enum HAL_I2C_StateTypeDef
Enumerator:
HAL_I2C_STATE_RESET

Peripheral is not yet Initialized

HAL_I2C_STATE_READY

Peripheral Initialized and ready for use

HAL_I2C_STATE_BUSY

An internal process is ongoing

HAL_I2C_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2C_STATE_LISTEN

Address Listen Mode is ongoing

HAL_I2C_STATE_BUSY_TX_LISTEN

Address Listen Mode and Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX_LISTEN

Address Listen Mode and Data Reception process is ongoing

HAL_I2C_STATE_ABORT

Abort user request ongoing

HAL_I2C_STATE_TIMEOUT

Timeout state

HAL_I2C_STATE_ERROR

Error

Definition at line 126 of file stm32l4xx_hal_i2c.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HAL mode structure definition

Enumerations
HAL mode structure definition
I2C Exported Types

HAL Mode structure definition. More...

Enumerations

enum HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }

Detailed Description

HAL Mode structure definition.

Note:
HAL I2C Mode value coding follow below described bitmap :
b7 (not used)
x : Should be set to 0
b6
0 : None
1 : Memory (HAL I2C communication is in Memory Mode)
b5
0 : None
1 : Slave (HAL I2C communication is in Slave Mode)
b4
0 : None
1 : Master (HAL I2C communication is in Master Mode)
b3-b2-b1-b0 (not used)
xxxx : Should be set to 0000

Enumeration Type Documentation

enum HAL_I2C_ModeTypeDef
Enumerator:
HAL_I2C_MODE_NONE

No I2C communication on going

HAL_I2C_MODE_MASTER

I2C communication is in Master Mode

HAL_I2C_MODE_SLAVE

I2C communication is in Slave Mode

HAL_I2C_MODE_MEM

I2C communication is in Memory Mode

Definition at line 166 of file stm32l4xx_hal_i2c.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Error Code definition

Defines
I2C Error Code definition
I2C Exported Types

I2C Error Code definition. More...

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)

Detailed Description

I2C Error Code definition.

Define Documentation

#define HAL_I2C_ERROR_AF (0x00000004U)

ACKF error

Definition at line 186 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define HAL_I2C_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 185 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_BERR (0x00000001U)

BERR error

Definition at line 184 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 188 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_DMAError().

#define HAL_I2C_ERROR_NONE (0x00000000U)

No error

Definition at line 183 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_OVR (0x00000008U)

OVR error

Definition at line 187 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_SIZE (0x00000040U)

Size Management error

Definition at line 190 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define HAL_I2C_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 189 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C handle Structure definition

Data Structures | Typedefs
I2C handle Structure definition
I2C Exported Types

I2C handle Structure definition. More...

Data Structures

struct | __I2C_HandleTypeDef

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef

Detailed Description

I2C handle Structure definition.

Typedef Documentation

typedef struct __I2C_HandleTypeDef I2C_HandleTypeDef
Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: __I2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2C_HandleTypeDef Struct Reference
I2C handle Structure definition

#include <stm32l4xx_hal_i2c.h>

Data Fields

I2C_TypeDef * | Instance
I2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_StatusTypeDef(* | XferISR )(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_I2C_StateTypeDef | State
__IO HAL_I2C_ModeTypeDef | Mode
__IO uint32_t | ErrorCode
__IO uint32_t | AddrEventCount

Detailed Description

Definition at line 199 of file stm32l4xx_hal_i2c.h.

Field Documentation

__IO uint32_t __I2C_HandleTypeDef::AddrEventCount

I2C Address Event counter

Definition at line 230 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

__IO uint32_t __I2C_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 228 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetError(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmarx

I2C Rx DMA handle parameters

Definition at line 220 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Slave_Receive_DMA(), I2C_DMAAbort(), I2C_DMAMasterReceiveCplt(), and I2C_ITError().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmatx

I2C Tx DMA handle parameters

Definition at line 218 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAAbort(), I2C_DMAMasterTransmitCplt(), and I2C_ITError().

I2C_InitTypeDef __I2C_HandleTypeDef::Init

I2C communication parameters

Definition at line 203 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

I2C_TypeDef* __I2C_HandleTypeDef::Instance

I2C registers base address

Definition at line 201 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Flush_TXDR(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_IT(), and I2C_TransferConfig().

HAL_LockTypeDef __I2C_HandleTypeDef::Lock

I2C locking object

Definition at line 222 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

__IO HAL_I2C_ModeTypeDef __I2C_HandleTypeDef::Mode

I2C communication mode

Definition at line 226 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_GetMode(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSequentialCplt(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

uint8_t* __I2C_HandleTypeDef::pBuffPtr

Pointer to I2C transfer buffer

Definition at line 205 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

__IO uint32_t __I2C_HandleTypeDef::PreviousState

I2C communication Previous state

Definition at line 214 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_Init(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSequentialCplt().

__IO HAL_I2C_StateTypeDef __I2C_HandleTypeDef::State

I2C communication state

Definition at line 224 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_GetState(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_IsAcknowledgeFailed(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSequentialCplt(), I2C_Master_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

__IO uint16_t __I2C_HandleTypeDef::XferCount

I2C transfer counter

Definition at line 209 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

HAL_StatusTypeDef(* __I2C_HandleTypeDef::XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)

I2C transfer IRQ handler function pointer

Definition at line 216 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSequentialCplt(), and I2C_ITSlaveCplt().

__IO uint32_t __I2C_HandleTypeDef::XferOptions

I2C sequantial transfer options, this parameter can be a value of I2C Sequential Transfer Options

Definition at line 211 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

uint16_t __I2C_HandleTypeDef::XferSize

I2C transfer size

Definition at line 207 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_i2c.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Sequential Transfer Options

Defines
I2C Sequential Transfer Options
I2C Exported Constants

Defines

#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Define Documentation

#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 251 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 249 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 252 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 250 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Slave_ISR_IT().

#define I2C_NO_OPTION_FRAME (0xFFFF0000U)

Definition at line 248 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Addressing Mode

Defines
I2C Addressing Mode
I2C Exported Constants

Defines

#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 261 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 260 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Dual Addressing Mode

Defines
I2C Dual Addressing Mode
I2C Exported Constants

Defines

#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define I2C_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 269 of file stm32l4xx_hal_i2c.h.

#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 270 of file stm32l4xx_hal_i2c.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Own Address2 Masks

Defines
I2C Own Address2 Masks
I2C Exported Constants

Defines

#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define I2C_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 279 of file stm32l4xx_hal_i2c.h.

#define I2C_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 280 of file stm32l4xx_hal_i2c.h.

#define I2C_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 281 of file stm32l4xx_hal_i2c.h.

#define I2C_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 282 of file stm32l4xx_hal_i2c.h.

#define I2C_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 283 of file stm32l4xx_hal_i2c.h.

#define I2C_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 284 of file stm32l4xx_hal_i2c.h.

#define I2C_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 285 of file stm32l4xx_hal_i2c.h.

#define I2C_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 278 of file stm32l4xx_hal_i2c.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C General Call Addressing Mode

Defines
I2C General Call Addressing Mode
I2C Exported Constants

Defines

#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define I2C_GENERALCALL_DISABLE (0x00000000U)

Definition at line 293 of file stm32l4xx_hal_i2c.h.

#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 294 of file stm32l4xx_hal_i2c.h.

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STM32L486xx HAL User Manual: I2C No-Stretch Mode

Defines
I2C No-Stretch Mode
I2C Exported Constants

Defines

#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define I2C_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 302 of file stm32l4xx_hal_i2c.h.

#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 303 of file stm32l4xx_hal_i2c.h.

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STM32L486xx HAL User Manual: I2C Memory Address Size

Defines
I2C Memory Address Size
I2C Exported Constants

Defines

#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)

Define Documentation

#define I2C_MEMADD_SIZE_16BIT (0x00000002U)

Definition at line 312 of file stm32l4xx_hal_i2c.h.

#define I2C_MEMADD_SIZE_8BIT (0x00000001U)

Definition at line 311 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Transfer Direction

Defines
I2C Transfer Direction
I2C Exported Constants

Defines

#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)

Define Documentation

#define I2C_DIRECTION_RECEIVE (0x00000001U)

Definition at line 321 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Sequential_Transmit_IT().

#define I2C_DIRECTION_TRANSMIT (0x00000000U)

Definition at line 320 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Sequential_Receive_IT().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Reload End Mode

Defines
I2C Reload End Mode
I2C Exported Constants

Defines

#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)

Define Documentation

#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 330 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 329 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_SOFTEND_MODE (0x00000000U)

Definition at line 331 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Start or Stop Mode

Defines
I2C Start or Stop Mode
I2C Exported Constants

Defines

#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP I2C_CR2_STOP
#define | I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE I2C_CR2_START

Define Documentation

#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 341 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

#define I2C_GENERATE_START_WRITE I2C_CR2_START

Definition at line 342 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_GENERATE_STOP I2C_CR2_STOP

Definition at line 340 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT().

#define I2C_NO_STARTSTOP (0x00000000U)

Definition at line 339 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Interrupt configuration definition

Defines
I2C Interrupt configuration definition
I2C Exported Constants

I2C Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE

Detailed Description

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define I2C_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 357 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_ERRI I2C_CR1_ERRIE

Definition at line 353 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_IT_NACKI I2C_CR1_NACKIE

Definition at line 356 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_RXI I2C_CR1_RXIE

Definition at line 358 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

#define I2C_IT_STOPI I2C_CR1_STOPIE

Definition at line 355 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_TCI I2C_CR1_TCIE

Definition at line 354 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_IT_TXI I2C_CR1_TXIE

Definition at line 359 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Flag definition

Defines
I2C Flag definition
I2C Exported Constants

Defines

#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR

Define Documentation

#define I2C_FLAG_ADDR I2C_ISR_ADDR

Definition at line 370 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_ITAddrCplt(), I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_AF I2C_ISR_NACKF

Definition at line 371 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_IsAcknowledgeFailed(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_ALERT I2C_ISR_ALERT

Definition at line 380 of file stm32l4xx_hal_i2c.h.

#define I2C_FLAG_ARLO I2C_ISR_ARLO

Definition at line 376 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BERR I2C_ISR_BERR

Definition at line 375 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BUSY I2C_ISR_BUSY

Definition at line 381 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_DIR I2C_ISR_DIR

Definition at line 382 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_OVR I2C_ISR_OVR

Definition at line 377 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_PECERR I2C_ISR_PECERR

Definition at line 378 of file stm32l4xx_hal_i2c.h.

#define I2C_FLAG_RXNE I2C_ISR_RXNE

Definition at line 369 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Slave_Receive(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_STOPF I2C_ISR_STOPF

Definition at line 372 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnRXNEFlagUntilTimeout(), and I2C_WaitOnSTOPFlagUntilTimeout().

#define I2C_FLAG_TC I2C_ISR_TC

Definition at line 373 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Master_ISR_IT(), and I2C_RequestMemoryRead().

#define I2C_FLAG_TCR I2C_ISR_TCR

Definition at line 374 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 379 of file stm32l4xx_hal_i2c.h.

#define I2C_FLAG_TXE I2C_ISR_TXE

Definition at line 367 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR().

#define I2C_FLAG_TXIS I2C_ISR_TXIS

Definition at line 368 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Flush_TXDR(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Exported Macros

Defines
I2C Exported Macros
I2C

Defines

#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified I2C interrupt source is enabled or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.

Define Documentation

#define __HAL_I2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
                                                                                : ((__HANDLE__)->Instance->ICR = (__FLAG__)))

Clear the I2C pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 493 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_Flush_TXDR(), I2C_IsAcknowledgeFailed(), I2C_ITAddrCplt(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define __HAL_I2C_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 506 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 433 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), and I2C_Master_ISR_DMA().

#define __HAL_I2C_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 500 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 417 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Enable_IRQ().

#define __HAL_I2C_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge I2C peripheral in Slave mode.

Parameters:
__HANDLE__,: specifies the I2C Handle.
Return values:
None

Definition at line 512 of file stm32l4xx_hal_i2c.h.

#define __HAL_I2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Check whether the specified I2C flag is set or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_TXIS Transmit interrupt status
  • I2C_FLAG_RXNE Receive data register not empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_TC Transfer complete (master mode)
  • I2C_FLAG_TCR Transfer complete reload
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
  • I2C_FLAG_BUSY Bus busy
  • I2C_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 474 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), I2C_Flush_TXDR(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

#define __HAL_I2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified I2C interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the I2C interrupt source to check. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 449 of file stm32l4xx_hal_i2c.h.

#define __HAL_I2C_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)

Reset I2C handle state.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 401 of file stm32l4xx_hal_i2c.h.

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STM32L486xx HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
#define | I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)

Define Documentation

#define I2C_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 679 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady().

#define I2C_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)

Definition at line 667 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)

Definition at line 668 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), and I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS1 ( __HANDLE__ ) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)

Definition at line 670 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS2 ( __HANDLE__ ) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)

Definition at line 671 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 669 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_Master_ISR_IT().

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 677 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_MEM_ADD_MSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))

Definition at line 676 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 665 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define IS_I2C_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))

Definition at line 627 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

Definition at line 630 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
                                         ((CALL) == I2C_GENERALCALL_ENABLE))

Definition at line 642 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))

Definition at line 648 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))

Definition at line 645 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 673 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 674 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == I2C_OA2_NOMASK)  || \
                                         ((MASK) == I2C_OA2_MASK01) || \
                                         ((MASK) == I2C_OA2_MASK02) || \
                                         ((MASK) == I2C_OA2_MASK03) || \
                                         ((MASK) == I2C_OA2_MASK04) || \
                                         ((MASK) == I2C_OA2_MASK05) || \
                                         ((MASK) == I2C_OA2_MASK06) || \
                                         ((MASK) == I2C_OA2_MASK07))

Definition at line 633 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_FIRST_FRAME)          || \
                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
                                                   ((REQUEST) == I2C_LAST_FRAME))

Definition at line 660 of file stm32l4xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), and HAL_I2C_Slave_Sequential_Transmit_IT().

#define IS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == I2C_RELOAD_MODE)   || \
                                         ((MODE) == I2C_AUTOEND_MODE) || \
                                         ((MODE) == I2C_SOFTEND_MODE))

Definition at line 651 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

#define IS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_GENERATE_STOP)        || \
                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
                                         ((REQUEST) == I2C_NO_STARTSTOP))

Definition at line 655 of file stm32l4xx_hal_i2c.h.

Referenced by I2C_TransferConfig().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C

Modules | Defines
I2C
STM32L4xx_HAL_Driver

I2C HAL module driver. More...

Modules

I2C Private Define
I2C Private Functions
I2C Exported Functions
I2C Exported Types
I2C Exported Constants
I2C Exported Macros
I2C Private Constants
I2C Private Macros

Defines

#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)

Detailed Description

I2C HAL module driver.

Define Documentation

#define I2C_GET_DMA_REMAIN_DATA ( __HANDLE__ )
Value:
((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX)   ? \
                                            ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \
                                            ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR)))

Definition at line 301 of file stm32l4xx_hal_i2c.c.

Referenced by I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Extended Private Constants

I2C Extended Private Constants
Extended features functions
Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Extended Private Macros

Defines
I2C Extended Private Macros
Extended features functions

Defines

#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Define Documentation

#define IS_I2C_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))

Definition at line 124 of file stm32l4xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigAnalogFilter().

#define IS_I2C_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000F)

Definition at line 127 of file stm32l4xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigDigitalFilter().

#define IS_I2C_FASTMODEPLUS ( __CONFIG__ )
Value:
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6)    || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7)   || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8)   || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9)   || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))

Definition at line 135 of file stm32l4xx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Extended Private Functions

I2C Extended Private Functions
Extended features functions
Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended features functions

Modules | Functions
Extended features functions
I2C Extended Exported Functions

Extended features functions. More...

Modules

I2C Extended Private Constants
I2C Extended Private Macros
I2C Extended Private Functions

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from stop mode.
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Extended features functions.

 ===============================================================================
                      ##### Extended features functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Noise Filters
      (+) Configure Wake Up Feature

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure I2C Analog noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
AnalogFilter | New state of the Analog filter.
Return values:
HAL status

Definition at line 113 of file stm32l4xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_ANALOG_FILTER, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure I2C Digital noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
DigitalFilter | Coefficient of digital noise filter between 0x00 and 0x0F.
Return values:
HAL status

Definition at line 157 of file stm32l4xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_DIGITAL_FILTER, and __I2C_HandleTypeDef::State.

void HAL_I2CEx_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be disabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
Return values:
None

Definition at line 323 of file stm32l4xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp ( I2C_HandleTypeDef * hi2c )

Disable I2C wakeup from stop mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 248 of file stm32l4xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

void HAL_I2CEx_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be enabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C2 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C2 parameter.
For all I2C3 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
Return values:
None

Definition at line 296 of file stm32l4xx_hal_i2c_ex.c.

References __HAL_RCC_SYSCFG_CLK_ENABLE, assert_param, and IS_I2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp ( I2C_HandleTypeDef * hi2c )

Enable I2C wakeup from stop mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 208 of file stm32l4xx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Extended Analog Filter

Defines
I2C Extended Analog Filter
I2C Extended Exported Constants

Defines

#define | I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 68 of file stm32l4xx_hal_i2c_ex.h.

#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)

Definition at line 67 of file stm32l4xx_hal_i2c_ex.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Extended Fast Mode Plus

Defines
I2C Extended Fast Mode Plus
I2C Extended Exported Constants

Defines

#define | I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Define Documentation

#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 80 of file stm32l4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP

Enable Fast Mode Plus on I2C2 pins

Definition at line 81 of file stm32l4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable Fast Mode Plus on I2C3 pins

Definition at line 82 of file stm32l4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 76 of file stm32l4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 77 of file stm32l4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 78 of file stm32l4xx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 79 of file stm32l4xx_hal_i2c_ex.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Private Constants

Defines
IRDA Private Constants
IRDA

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000
#define | IRDA_CR1_FIELDS

Define Documentation

#define IRDA_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE \
                                   | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))

UART or USART CR1 fields of parameters set by IRDA_SetConfig API

Definition at line 161 of file stm32l4xx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IRDA_TEACK_REACK_TIMEOUT 1000

IRDA TX or RX enable acknowledge time-out value

Definition at line 160 of file stm32l4xx_hal_irda.c.

Referenced by IRDA_CheckIdleState().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
IRDA Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  in asynchronous IRDA mode.
  (+) For the asynchronous mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length
      (++) Parity: If the parity is enabled, then the MSB bit of the data written
           in the data register is transmitted but is changed by the parity bit.
      (++) Power mode
      (++) Prescaler setting
      (++) Receiver/transmitter modes

  [..]
  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
  (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible IRDA frame formats are listed in the following table.

Table 1. IRDA frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | IRDA frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA peripheral.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 303 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_DISABLE, assert_param, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspDeInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Init ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 250 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_DISABLE, __HAL_IRDA_ENABLE, assert_param, IRDA_HandleTypeDef::gState, HAL_IRDA_MspInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Instance, IRDA_CheckIdleState(), IRDA_SetConfig(), and IRDA_HandleTypeDef::Lock.

void HAL_IRDA_MspDeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA MSP.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 353 of file stm32l4xx_hal_irda.c.

Referenced by HAL_IRDA_DeInit().

void HAL_IRDA_MspInit ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA MSP.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 337 of file stm32l4xx_hal_irda.c.

Referenced by HAL_IRDA_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
IRDA Exported Functions

IRDA Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.

Detailed Description

IRDA Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the IRDA data transfers.

  [..]
    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
    While receiving data, transmission should be avoided as the data to be transmitted
    could be corrupted.

    (#) There are two modes of transfer:
        (++) Blocking mode: the communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode: the communication is performed using Interrupts
             or DMA, these API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode APIs are :
        (++) HAL_IRDA_Transmit()
        (++) HAL_IRDA_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_IRDA_Transmit_IT()
        (++) HAL_IRDA_Receive_IT()
        (++) HAL_IRDA_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_IRDA_Transmit_DMA()
        (++) HAL_IRDA_Receive_DMA()
        (++) HAL_IRDA_DMAPause()
        (++) HAL_IRDA_DMAResume()
        (++) HAL_IRDA_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
        (++) HAL_IRDA_TxHalfCpltCallback()
        (++) HAL_IRDA_TxCpltCallback()
        (++) HAL_IRDA_RxHalfCpltCallback()
        (++) HAL_IRDA_RxCpltCallback()
        (++) HAL_IRDA_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DMAPause ( IRDA_HandleTypeDef * hirda )

Pause the DMA Transfer.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 798 of file stm32l4xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAResume ( IRDA_HandleTypeDef * hirda )

Resume the DMA Transfer.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 826 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_OREFLAG, IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAStop ( IRDA_HandleTypeDef * hirda )

Stop the DMA Transfer.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 856 of file stm32l4xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

void HAL_IRDA_ErrorCallback ( IRDA_HandleTypeDef * hirda )

IRDA error callback.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1032 of file stm32l4xx_hal_irda.c.

Referenced by HAL_IRDA_IRQHandler(), and IRDA_DMAError().

void HAL_IRDA_IRQHandler ( IRDA_HandleTypeDef * hirda )

Handle IRDA interrupt request.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 893 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_IT, __HAL_IRDA_GET_IT, __HAL_IRDA_GET_IT_SOURCE, IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_FE, HAL_IRDA_ERROR_NE, HAL_IRDA_ERROR_NONE, HAL_IRDA_ERROR_ORE, HAL_IRDA_ERROR_PE, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_READY, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_EndTransmit_IT(), IRDA_IT_ERR, IRDA_IT_FE, IRDA_IT_NE, IRDA_IT_ORE, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_IT_TC, IRDA_IT_TXE, IRDA_Receive_IT(), IRDA_Transmit_IT(), and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Receive | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer.
Size,: Amount of data to be received.
Timeout,: Specify timeout value.
Return values:
HAL status

Definition at line 506 of file stm32l4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_MASK_COMPUTATION, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::RxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Receive_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer.
Size,: Amount of data to be received.
Note:
When the IRDA parity is enabled (PCE = 1) the received data contains the parity bit (MSB position).
Return values:
HAL status

Definition at line 741 of file stm32l4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Receive_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer.
Size,: Amount of data to be received.
Return values:
HAL status

Definition at line 624 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_MASK_COMPUTATION, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::RxXferSize.

void HAL_IRDA_RxCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Transfer completed callback.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1000 of file stm32l4xx_hal_irda.c.

Referenced by IRDA_DMAReceiveCplt(), and IRDA_Receive_IT().

void HAL_IRDA_RxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Half Transfer complete callback.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1016 of file stm32l4xx_hal_irda.c.

Referenced by IRDA_DMAReceiveHalfCplt().

HAL_StatusTypeDef HAL_IRDA_Transmit | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer.
Size,: Amount of data to be sent.
Timeout,: Specify timeout value.
Return values:
HAL status

Definition at line 433 of file stm32l4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Transmit_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: pointer to data buffer.
Size,: amount of data to be sent.
Return values:
HAL status

Definition at line 677 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_CLEAR_TCF, IRDA_DMAError(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Transmit_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer.
Size,: Amount of data to be sent.
Return values:
HAL status

Definition at line 581 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_IT_TXE, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, and IRDA_HandleTypeDef::TxXferSize.

void HAL_IRDA_TxCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Transfer completed callback.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 968 of file stm32l4xx_hal_irda.c.

Referenced by IRDA_DMATransmitCplt(), and IRDA_EndTransmit_IT().

void HAL_IRDA_TxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Half Transfer completed callback.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 984 of file stm32l4xx_hal_irda.c.

Referenced by IRDA_DMATransmitHalfCplt().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
IRDA Exported Functions

IRDA State and Errors functions. More...

Functions

HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of IrDA
    communication process and also return Peripheral Errors occurred during communication process
     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
         of the IRDA peripheral handle.
     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_IRDA_GetError ( IRDA_HandleTypeDef * hirda )

Return the IRDA handle error code.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
IRDA Error Code

Definition at line 1087 of file stm32l4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode.

HAL_IRDA_StateTypeDef HAL_IRDA_GetState ( IRDA_HandleTypeDef * hirda )

Return the IRDA handle state.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL state

Definition at line 1071 of file stm32l4xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, and IRDA_HandleTypeDef::RxState.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Private Functions

Functions
IRDA Private Functions
IRDA

Functions

static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.

Function Documentation

static HAL_StatusTypeDef IRDA_CheckIdleState ( IRDA_HandleTypeDef * hirda ) [static]

Check the IRDA Idle State.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1435 of file stm32l4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, IRDA_TEACK_REACK_TIMEOUT, IRDA_WaitOnFlagUntilTimeout(), and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Init().

static void IRDA_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication error callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1191 of file stm32l4xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_DMA, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Receive_DMA(), and HAL_IRDA_Transmit_DMA().

static void IRDA_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1152 of file stm32l4xx_hal_irda.c.

References HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Instance, IRDA_HandleTypeDef::Instance, IRDA_HandleTypeDef::RxState, and IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMAReceiveHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1178 of file stm32l4xx_hal_irda.c.

References HAL_IRDA_RxHalfCpltCallback().

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1110 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, HAL_IRDA_TxCpltCallback(), __DMA_HandleTypeDef::Instance, IRDA_HandleTypeDef::Instance, IRDA_IT_TC, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATransmitHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1139 of file stm32l4xx_hal_irda.c.

References HAL_IRDA_TxHalfCpltCallback().

Referenced by HAL_IRDA_Transmit_DMA().

static HAL_StatusTypeDef IRDA_EndTransmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1295 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), and IRDA_IT_TC.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_Receive_IT ( IRDA_HandleTypeDef * hirda ) [static]

Receive an amount of data in non-blocking mode.

Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Receive_IT().

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1317 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, __HAL_IRDA_SEND_REQ, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_PARITY_NONE, IRDA_RXDATA_FLUSH_REQUEST, IRDA_WORDLENGTH_9B, IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_SetConfig ( IRDA_HandleTypeDef * hirda ) [static]

Configure the IRDA peripheral.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1372 of file stm32l4xx_hal_irda.c.

References assert_param, IRDA_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_CLOCKSOURCE_HSI, IRDA_CLOCKSOURCE_LSE, IRDA_CLOCKSOURCE_PCLK1, IRDA_CLOCKSOURCE_PCLK2, IRDA_CLOCKSOURCE_SYSCLK, IRDA_CLOCKSOURCE_UNDEFINED, IRDA_CR1_FIELDS, IRDA_GETCLOCKSOURCE, IS_IRDA_BAUDRATE, IS_IRDA_PARITY, IS_IRDA_POWERMODE, IS_IRDA_PRESCALER, IS_IRDA_TX_RX_MODE, IS_IRDA_WORD_LENGTH, LSE_VALUE, IRDA_InitTypeDef::Mode, IRDA_InitTypeDef::Parity, IRDA_InitTypeDef::PowerMode, IRDA_InitTypeDef::Prescaler, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_Init().

static HAL_StatusTypeDef IRDA_Transmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Send an amount of data in non-blocking mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Transmit_IT().
Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1249 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, __HAL_IRDA_ENABLE_IT, IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_IT_TC, IRDA_IT_TXE, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle IRDA Communication Timeout.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Flag | Specifies the IRDA flag to check.
Status | the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1214 of file stm32l4xx_hal_irda.c.

References __HAL_IRDA_GET_FLAG, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), and IRDA_CheckIdleState().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Exported Types

Data Structures | Enumerations
IRDA Exported Types
IRDA

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00U, HAL_IRDA_STATE_READY = 0x20U, HAL_IRDA_STATE_BUSY = 0x24U, HAL_IRDA_STATE_BUSY_TX = 0x21U,
HAL_IRDA_STATE_BUSY_RX = 0x22U, HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, HAL_IRDA_STATE_TIMEOUT = 0xA0U, HAL_IRDA_STATE_ERROR = 0xE0U
}
HAL IRDA State structures definition. More...
enum HAL_IRDA_ErrorTypeDef {
HAL_IRDA_ERROR_NONE = 0x00, HAL_IRDA_ERROR_PE = 0x01, HAL_IRDA_ERROR_NE = 0x02, HAL_IRDA_ERROR_FE = 0x04,
HAL_IRDA_ERROR_ORE = 0x08, HAL_IRDA_ERROR_DMA = 0x10
}
HAL IRDA Error Code structure definition. More...
enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK1 = 0x00, IRDA_CLOCKSOURCE_PCLK2 = 0x01, IRDA_CLOCKSOURCE_HSI = 0x02, IRDA_CLOCKSOURCE_SYSCLK = 0x04,
IRDA_CLOCKSOURCE_LSE = 0x08, IRDA_CLOCKSOURCE_UNDEFINED = 0x10
}
IRDA clock sources definition. More...
enum IRDA_ControlTypeDef {
IRDA_BAUDRATE = 0x00, IRDA_PARITY = 0x01, IRDA_WORDLENGTH = 0x02, IRDA_MODE = 0x03,
IRDA_PRESCALER = 0x04, IRDA_POWERMODE = 0x05
}
IRDA Configuration enumeration values definition. More...

Enumeration Type Documentation

enum HAL_IRDA_ErrorTypeDef

HAL IRDA Error Code structure definition.

Enumerator:
HAL_IRDA_ERROR_NONE

No error

HAL_IRDA_ERROR_PE

Parity error

HAL_IRDA_ERROR_NE

Noise error

HAL_IRDA_ERROR_FE

frame error

HAL_IRDA_ERROR_ORE

Overrun error

HAL_IRDA_ERROR_DMA

DMA transfer error

Definition at line 155 of file stm32l4xx_hal_irda.h.

enum HAL_IRDA_StateTypeDef

HAL IRDA State structures definition.

Note:
HAL IRDA State value is a combination of 2 different substates: gState and RxState.
  • gState contains IRDA state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL IRDA Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_IRDA_STATE_RESET

Peripheral is not initialized Value is allowed for gState and RxState

HAL_IRDA_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_IRDA_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_IRDA_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_IRDA_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_IRDA_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_IRDA_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_IRDA_STATE_ERROR

Error Value is allowed for gState only

Definition at line 131 of file stm32l4xx_hal_irda.h.

enum IRDA_ClockSourceTypeDef

IRDA clock sources definition.

Enumerator:
IRDA_CLOCKSOURCE_PCLK1

PCLK1 clock source

IRDA_CLOCKSOURCE_PCLK2

PCLK2 clock source

IRDA_CLOCKSOURCE_HSI

HSI clock source

IRDA_CLOCKSOURCE_SYSCLK

SYSCLK clock source

IRDA_CLOCKSOURCE_LSE

LSE clock source

IRDA_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 168 of file stm32l4xx_hal_irda.h.

enum IRDA_ControlTypeDef

IRDA Configuration enumeration values definition.

Enumerator:
IRDA_BAUDRATE

IRDA Baud rate

IRDA_PARITY

IRDA frame parity

IRDA_WORDLENGTH

IRDA frame length

IRDA_MODE

IRDA communication mode

IRDA_PRESCALER

IRDA prescaling

IRDA_POWERMODE

IRDA power mode

Definition at line 221 of file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_InitTypeDef Struct Reference
IRDA Exported Types

IRDA Init Structure definition. More...

#include <stm32l4xx_hal_irda.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | Parity
uint32_t | Mode
uint8_t | Prescaler
uint16_t | PowerMode

Detailed Description

IRDA Init Structure definition.

Definition at line 65 of file stm32l4xx_hal_irda.h.

Field Documentation

uint32_t IRDA_InitTypeDef::BaudRate

This member configures the IRDA communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate)))

Definition at line 67 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of IRDA Transfer Mode

Definition at line 81 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of IRDA Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 74 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

uint16_t IRDA_InitTypeDef::PowerMode

Specifies the IRDA power mode. This parameter can be a value of IRDA Low Power

Definition at line 88 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint8_t IRDA_InitTypeDef::Prescaler

Specifies the Prescaler value for dividing the UART/USART source clock to achieve low-power frequency.

Note:
Prescaler value 0 is forbidden

Definition at line 84 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of IRDA Word Length

Definition at line 71 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_irda.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_HandleTypeDef Struct Reference
IRDA Exported Types

IRDA handle Structure definition. More...

#include <stm32l4xx_hal_irda.h>

Data Fields

USART_TypeDef * | Instance
IRDA_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_IRDA_StateTypeDef | gState
__IO HAL_IRDA_StateTypeDef | RxState
uint32_t | ErrorCode

Detailed Description

IRDA handle Structure definition.

Definition at line 181 of file stm32l4xx_hal_irda.h.

Field Documentation

uint32_t IRDA_HandleTypeDef::ErrorCode

IRDA Error code

Definition at line 214 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_GetError(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), and IRDA_DMAError().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::gState

IRDA state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 207 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_EndTransmit_IT(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmarx

IRDA Rx DMA Handle parameters

Definition at line 203 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAStop(), and HAL_IRDA_Receive_DMA().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmatx

IRDA Tx DMA Handle parameters

Definition at line 201 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAStop(), and HAL_IRDA_Transmit_DMA().

IRDA_InitTypeDef IRDA_HandleTypeDef::Init

IRDA communication parameters

Definition at line 185 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

USART_TypeDef* IRDA_HandleTypeDef::Instance

USART registers base address

Definition at line 183 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Init(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), IRDA_CheckIdleState(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), IRDA_Receive_IT(), IRDA_SetConfig(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

HAL_LockTypeDef IRDA_HandleTypeDef::Lock

Locking object

Definition at line 205 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint16_t IRDA_HandleTypeDef::Mask

USART RX RDR register mask

Definition at line 199 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and IRDA_Receive_IT().

uint8_t* IRDA_HandleTypeDef::pRxBuffPtr

Pointer to IRDA Rx transfer Buffer

Definition at line 193 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

uint8_t* IRDA_HandleTypeDef::pTxBuffPtr

Pointer to IRDA Tx transfer Buffer

Definition at line 187 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::RxState

IRDA state information related to Rx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 211 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

uint16_t IRDA_HandleTypeDef::RxXferCount

IRDA Rx Transfer Counter

Definition at line 197 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_IT(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), and IRDA_Receive_IT().

uint16_t IRDA_HandleTypeDef::RxXferSize

IRDA Rx Transfer size

Definition at line 195 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), and HAL_IRDA_Receive_IT().

uint16_t IRDA_HandleTypeDef::TxXferCount

Definition at line 191 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAError(), IRDA_DMATransmitCplt(), and IRDA_Transmit_IT().

uint16_t IRDA_HandleTypeDef::TxXferSize

IRDA Tx Transfer size

Definition at line 189 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_irda.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Word Length

Defines
IRDA Word Length
IRDA Exported Constants

Defines

#define | IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)

7-bit long frame

Definition at line 243 of file stm32l4xx_hal_irda.h.

#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)

8-bit long frame

Definition at line 244 of file stm32l4xx_hal_irda.h.

#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

9-bit long frame

Definition at line 245 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Parity

Defines
IRDA Parity
IRDA Exported Constants

Defines

#define | IRDA_PARITY_NONE ((uint32_t)0x00000000)
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Even parity

Definition at line 254 of file stm32l4xx_hal_irda.h.

#define IRDA_PARITY_NONE ((uint32_t)0x00000000)

No parity

Definition at line 253 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Odd parity

Definition at line 255 of file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Transfer Mode

Defines
IRDA Transfer Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)

RX mode

Definition at line 263 of file stm32l4xx_hal_irda.h.

#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)

TX mode

Definition at line 264 of file stm32l4xx_hal_irda.h.

#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

RX and TX mode

Definition at line 265 of file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Low Power

Defines
IRDA Low Power
IRDA Exported Constants

Defines

#define | IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)

Define Documentation

#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)

IRDA low power mode

Definition at line 274 of file stm32l4xx_hal_irda.h.

#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)

IRDA normal power mode

Definition at line 273 of file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA State

Defines
IRDA State
IRDA Exported Constants

Defines

#define | IRDA_STATE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Define Documentation

#define IRDA_STATE_DISABLE ((uint32_t)0x00000000)

IRDA disabled

Definition at line 282 of file stm32l4xx_hal_irda.h.

#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)

IRDA enabled

Definition at line 283 of file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Mode

Defines
IRDA Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)

Define Documentation

#define IRDA_MODE_DISABLE ((uint32_t)0x00000000)

Associated UART disabled in IRDA mode

Definition at line 291 of file stm32l4xx_hal_irda.h.

#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)

Associated UART enabled in IRDA mode

Definition at line 292 of file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA One Bit Sampling

Defines
IRDA One Bit Sampling
IRDA Exported Constants

Defines

#define | IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)

One-bit sampling disabled

Definition at line 300 of file stm32l4xx_hal_irda.h.

#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

One-bit sampling enabled

Definition at line 301 of file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA DMA Tx

Defines
IRDA DMA Tx
IRDA Exported Constants

Defines

#define | IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define | IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

Define Documentation

#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)

IRDA DMA TX disabled

Definition at line 309 of file stm32l4xx_hal_irda.h.

#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

IRDA DMA TX enabled

Definition at line 310 of file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA DMA Rx

Defines
IRDA DMA Rx
IRDA Exported Constants

Defines

#define | IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000)
#define | IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000)

IRDA DMA RX disabled

Definition at line 318 of file stm32l4xx_hal_irda.h.

#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

IRDA DMA RX enabled

Definition at line 319 of file stm32l4xx_hal_irda.h.

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STM32L486xx HAL User Manual: IRDA Request Parameters

Defines
IRDA Request Parameters
IRDA Exported Constants

Defines

#define | IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ)
#define | IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)
#define | IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)

Define Documentation

#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ)

Auto-Baud Rate Request

Definition at line 327 of file stm32l4xx_hal_irda.h.

#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 328 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 329 of file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Flags

Defines
IRDA Flags
IRDA Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | IRDA_FLAG_REACK ((uint32_t)0x00400000)
#define | IRDA_FLAG_TEACK ((uint32_t)0x00200000)
#define | IRDA_FLAG_BUSY ((uint32_t)0x00010000)
#define | IRDA_FLAG_ABRF ((uint32_t)0x00008000)
#define | IRDA_FLAG_ABRE ((uint32_t)0x00004000)
#define | IRDA_FLAG_TXE ((uint32_t)0x00000080)
#define | IRDA_FLAG_TC ((uint32_t)0x00000040)
#define | IRDA_FLAG_RXNE ((uint32_t)0x00000020)
#define | IRDA_FLAG_ORE ((uint32_t)0x00000008)
#define | IRDA_FLAG_NE ((uint32_t)0x00000004)
#define | IRDA_FLAG_FE ((uint32_t)0x00000002)
#define | IRDA_FLAG_PE ((uint32_t)0x00000001)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define IRDA_FLAG_ABRE ((uint32_t)0x00004000)

IRDA Auto baud rate error

Definition at line 343 of file stm32l4xx_hal_irda.h.

#define IRDA_FLAG_ABRF ((uint32_t)0x00008000)

IRDA Auto baud rate flag

Definition at line 342 of file stm32l4xx_hal_irda.h.

#define IRDA_FLAG_BUSY ((uint32_t)0x00010000)

IRDA Busy flag

Definition at line 341 of file stm32l4xx_hal_irda.h.

#define IRDA_FLAG_FE ((uint32_t)0x00000002)

IRDA Noise error

Definition at line 349 of file stm32l4xx_hal_irda.h.

#define IRDA_FLAG_NE ((uint32_t)0x00000004)

IRDA Noise error

Definition at line 348 of file stm32l4xx_hal_irda.h.

#define IRDA_FLAG_ORE ((uint32_t)0x00000008)

IRDA Overrun error

Definition at line 347 of file stm32l4xx_hal_irda.h.

#define IRDA_FLAG_PE ((uint32_t)0x00000001)

IRDA Parity error

Definition at line 350 of file stm32l4xx_hal_irda.h.

#define IRDA_FLAG_REACK ((uint32_t)0x00400000)

IRDA Receive enable acknowledge flag

Definition at line 339 of file stm32l4xx_hal_irda.h.

#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)

IRDA Read data register not empty

Definition at line 346 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive().

#define IRDA_FLAG_TC ((uint32_t)0x00000040)

IRDA Transmission complete

Definition at line 345 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

#define IRDA_FLAG_TEACK ((uint32_t)0x00200000)

IRDA Transmit enable acknowledge flag

Definition at line 340 of file stm32l4xx_hal_irda.h.

#define IRDA_FLAG_TXE ((uint32_t)0x00000080)

IRDA Transmit data register empty

Definition at line 344 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Interrupts Definition

Defines
IRDA Interrupts Definition
IRDA Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | IRDA_IT_PE ((uint16_t)0x0028)
#define | IRDA_IT_TXE ((uint16_t)0x0727)
#define | IRDA_IT_TC ((uint16_t)0x0626)
#define | IRDA_IT_RXNE ((uint16_t)0x0525)
#define | IRDA_IT_IDLE ((uint16_t)0x0424)
#define | IRDA_IT_ERR ((uint16_t)0x0060)
#define | IRDA_IT_ORE ((uint16_t)0x0300)
#define | IRDA_IT_NE ((uint16_t)0x0200)
#define | IRDA_IT_FE ((uint16_t)0x0100)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define IRDA_IT_ERR ((uint16_t)0x0060)

IRDA Error interruption

Definition at line 377 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

#define IRDA_IT_FE ((uint16_t)0x0100)

IRDA Frame error interruption

Definition at line 383 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_IT_IDLE ((uint16_t)0x0424)

IRDA Idle interruption

Definition at line 369 of file stm32l4xx_hal_irda.h.

#define IRDA_IT_NE ((uint16_t)0x0200)

IRDA Noise error interruption

Definition at line 382 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_IT_ORE ((uint16_t)0x0300)

IRDA Overrun error interruption

Definition at line 381 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_IT_PE ((uint16_t)0x0028)

IRDA Parity error interruption

Definition at line 365 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

#define IRDA_IT_RXNE ((uint16_t)0x0525)

IRDA Read data register not empty interruption

Definition at line 368 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

#define IRDA_IT_TC ((uint16_t)0x0626)

IRDA Transmission complete interruption

Definition at line 367 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_Transmit_IT().

#define IRDA_IT_TXE ((uint16_t)0x0727)

IRDA Transmit data register empty interruption

Definition at line 366 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Interruption Clear Flags

Defines
IRDA Interruption Clear Flags
IRDA Exported Constants

Defines

#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NCF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF

Define Documentation

#define IRDA_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 392 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 395 of file stm32l4xx_hal_irda.h.

#define IRDA_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 393 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 394 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 391 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define IRDA_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 396 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA interruptions flags mask

Defines
IRDA interruptions flags mask
IRDA Exported Constants

Defines

#define IRDA_IT_MASK ((uint16_t)0x001F)

Define Documentation

#define IRDA_IT_MASK ((uint16_t)0x001F)

IRDA Interruptions flags mask

Definition at line 404 of file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Exported Macros

Defines
IRDA Exported Macros
IRDA

Defines

#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.

Define Documentation

#define __HAL_IRDA_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)

Clear the IRDA FE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 463 of file stm32l4xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified IRDA pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • IRDA_CLEAR_PEF
  • IRDA_CLEAR_FEF
  • IRDA_CLEAR_NEF
  • IRDA_CLEAR_OREF
  • IRDA_CLEAR_TCF
  • IRDA_CLEAR_IDLEF
Return values:
None

Definition at line 450 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA().

#define __HAL_IRDA_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)

Clear the IRDA IDLE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 481 of file stm32l4xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified IRDA ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • IRDA_CLEAR_PEF Parity Error Clear Flag
  • IRDA_CLEAR_FEF Framing Error Clear Flag
  • IRDA_CLEAR_NEF Noise detected Clear Flag
  • IRDA_CLEAR_OREF OverRun Error Clear Flag
  • IRDA_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 581 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)

Clear the IRDA NE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 469 of file stm32l4xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)

Clear the IRDA ORE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 475 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume().

#define __HAL_IRDA_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)

Clear the IRDA PE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 456 of file stm32l4xx_hal_irda.h.

#define __HAL_IRDA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 618 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define __HAL_IRDA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

Disable the specified IRDA interrupt.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__INTERRUPT__,: specifies the IRDA interrupt source to disable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 532 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_EndTransmit_IT(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define __HAL_IRDA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 612 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define __HAL_IRDA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

Enable the specified IRDA interrupt.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__INTERRUPT__,: specifies the IRDA interrupt source to enable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 516 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit_IT(), IRDA_DMATransmitCplt(), and IRDA_Transmit_IT().

#define __HAL_IRDA_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                    \
         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
      } while(0)

Flush the IRDA DR register.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 432 of file stm32l4xx_hal_irda.h.

#define __HAL_IRDA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified IRDA flag is set or not.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • IRDA_FLAG_REACK Receive enable acknowledge flag
  • IRDA_FLAG_TEACK Transmit enable acknowledge flag
  • IRDA_FLAG_BUSY Busy flag
  • IRDA_FLAG_ABRF Auto Baud rate detection flag
  • IRDA_FLAG_ABRE Auto Baud rate detection error flag
  • IRDA_FLAG_TXE Transmit data register empty flag
  • IRDA_FLAG_TC Transmission Complete flag
  • IRDA_FLAG_RXNE Receive data register not empty flag
  • IRDA_FLAG_ORE OverRun Error flag
  • IRDA_FLAG_NE Noise Error flag
  • IRDA_FLAG_FE Framing Error flag
  • IRDA_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 501 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))

Check whether the specified IRDA interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__IT__,: specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ORE OverRun Error interrupt
  • IRDA_IT_NE Noise Error interrupt
  • IRDA_IT_FE Framing Error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 551 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))

Check whether the specified IRDA interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__IT__,: specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ERR Framing, overrun or noise error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 565 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the IRDA one bit sample method.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 606 of file stm32l4xx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the IRDA one bit sample method.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None

Definition at line 600 of file stm32l4xx_hal_irda.h.

#define __HAL_IRDA_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
                                                     } while(0)

Reset IRDA handle state.

Parameters:
__HANDLE__,: IRDA handle.
Return values:
None

Definition at line 423 of file stm32l4xx_hal_irda.h.

#define __HAL_IRDA_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific IRDA request flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__REQ__,: specifies the request flag to set This parameter can be one of the following values:
  • IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 594 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Private Macros

Defines
IRDA Private Macros
IRDA

Defines

#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Define Documentation

#define IRDA_MASK_COMPUTATION ( __HANDLE__ )

Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
Return values:
None,the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 634 of file stm32l4xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and HAL_IRDA_Receive_IT().

#define IS_IRDA_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 115201)

Ensure that IRDA Baud rate is less or equal to maximum value.

Parameters:
__BAUDRATE__,: specifies the IRDA Baudrate set by the user.
Return values:
True or False

Definition at line 675 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))

Ensure that IRDA DMA RX mode is valid.

Parameters:
__DMARX__,: IRDA DMA RX mode.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 753 of file stm32l4xx_hal_irda.h.

#define IS_IRDA_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))

Ensure that IRDA DMA TX mode is valid.

Parameters:
__DMATX__,: IRDA DMA TX mode.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 745 of file stm32l4xx_hal_irda.h.

#define IS_IRDA_MODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_MODE_DISABLE) || \
                                 ((__MODE__) == IRDA_MODE_ENABLE))

Ensure that IRDA associated UART/USART mode is valid.

Parameters:
__MODE__,: IRDA associated UART/USART mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 729 of file stm32l4xx_hal_irda.h.

#define IS_IRDA_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))

Ensure that IRDA sampling rate is valid.

Parameters:
__ONEBIT__,: IRDA sampling rate.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 737 of file stm32l4xx_hal_irda.h.

#define IS_IRDA_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == IRDA_PARITY_NONE) || \
                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
                                    ((__PARITY__) == IRDA_PARITY_ODD))

Ensure that IRDA frame parity is valid.

Parameters:
__PARITY__,: IRDA frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 697 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_POWERMODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))

Ensure that IRDA power mode is valid.

Parameters:
__MODE__,: IRDA power mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 713 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_PRESCALER ( __PRESCALER__ ) ((__PRESCALER__) > 0)

Ensure that IRDA prescaler value is strictly larger than 0.

Parameters:
__PRESCALER__,: specifies the IRDA prescaler value set by the user.
Return values:
True or False

Definition at line 681 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))

Ensure that IRDA request is valid.

Parameters:
__PARAM__,: IRDA request.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 761 of file stm32l4xx_hal_irda.h.

#define IS_IRDA_STATE ( __STATE__ )
Value:
(((__STATE__) == IRDA_STATE_DISABLE) || \
                                  ((__STATE__) == IRDA_STATE_ENABLE))

Ensure that IRDA state is valid.

Parameters:
__STATE__,: IRDA state mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 721 of file stm32l4xx_hal_irda.h.

#define IS_IRDA_TX_RX_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))

Ensure that IRDA communication mode is valid.

Parameters:
__MODE__,: IRDA communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 706 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))

Ensure that IRDA frame length is valid.

Parameters:
__LENGTH__,: IRDA frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 688 of file stm32l4xx_hal_irda.h.

Referenced by IRDA_SetConfig().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG Private Defines

Defines
IWDG Private Defines
IWDG

Defines

#define HAL_IWDG_DEFAULT_TIMEOUT 48u

Define Documentation

#define HAL_IWDG_DEFAULT_TIMEOUT 48u

Definition at line 132 of file stm32l4xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_InitTypeDef Struct Reference
IWDG Exported Types

IWDG Init structure definition. More...

#include <stm32l4xx_hal_iwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Reload
uint32_t | Window

Detailed Description

IWDG Init structure definition.

Definition at line 65 of file stm32l4xx_hal_iwdg.h.

Field Documentation

uint32_t IWDG_InitTypeDef::Prescaler

Select the prescaler of the IWDG. This parameter can be a value of IWDG Prescaler

Definition at line 67 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Reload

Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 70 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Window

Specifies the window value to be compared to the down-counter. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 73 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_iwdg.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_HandleTypeDef Struct Reference
IWDG Exported Types

IWDG Handle Structure definition. More...

#include <stm32l4xx_hal_iwdg.h>

Data Fields

IWDG_TypeDef * Instance
IWDG_InitTypeDef Init

Detailed Description

IWDG Handle Structure definition.

Definition at line 81 of file stm32l4xx_hal_iwdg.h.

Field Documentation

IWDG_InitTypeDef IWDG_HandleTypeDef::Init

IWDG required parameters

Definition at line 85 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

IWDG_TypeDef* IWDG_HandleTypeDef::Instance

Register base address

Definition at line 83 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_iwdg.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG Prescaler

Defines
IWDG Prescaler
IWDG Exported Constants

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

IWDG prescaler set to 128

Definition at line 106 of file stm32l4xx_hal_iwdg.h.

#define IWDG_PRESCALER_16 IWDG_PR_PR_1

IWDG prescaler set to 16

Definition at line 103 of file stm32l4xx_hal_iwdg.h.

#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

IWDG prescaler set to 256

Definition at line 107 of file stm32l4xx_hal_iwdg.h.

#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

IWDG prescaler set to 32

Definition at line 104 of file stm32l4xx_hal_iwdg.h.

#define IWDG_PRESCALER_4 0x00000000u

IWDG prescaler set to 4

Definition at line 101 of file stm32l4xx_hal_iwdg.h.

#define IWDG_PRESCALER_64 IWDG_PR_PR_2

IWDG prescaler set to 64

Definition at line 105 of file stm32l4xx_hal_iwdg.h.

#define IWDG_PRESCALER_8 IWDG_PR_PR_0

IWDG prescaler set to 8

Definition at line 102 of file stm32l4xx_hal_iwdg.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG Window option

Defines
IWDG Window option
IWDG Exported Constants

Defines

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Define Documentation

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Definition at line 115 of file stm32l4xx_hal_iwdg.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG Exported Macros

Defines
IWDG Exported Macros
IWDG

Defines

#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).

Define Documentation

#define __HAL_IWDG_RELOAD_COUNTER ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 142 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Refresh().

#define __HAL_IWDG_START ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

Enable the IWDG peripheral.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 134 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and Start functions

Functions
Initialization and Start functions
IWDG Exported Functions

Initialization and Start functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Detailed Description

Initialization and Start functions.

 ===============================================================================
          ##### Initialization and Start functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters in the
          IWDG_InitTypeDef of associated handle.
      (+) Manage Window option.
      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
          is reloaded in order to exit function with correct time base.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Init ( IWDG_HandleTypeDef * hiwdg )

Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Before exiting function, watchdog is refreshed in order to have correct time base.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 172 of file stm32l4xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER, __HAL_IWDG_START, assert_param, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, IWDG_HandleTypeDef::Init, IWDG_HandleTypeDef::Instance, IS_IWDG_PRESCALER, IS_IWDG_RELOAD, IS_IWDG_WINDOW, IWDG_ENABLE_WRITE_ACCESS, IWDG_InitTypeDef::Prescaler, IWDG_InitTypeDef::Reload, and IWDG_InitTypeDef::Window.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
IWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Refresh the IWDG.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Refresh ( IWDG_HandleTypeDef * hiwdg )

Refresh the IWDG.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 256 of file stm32l4xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

Define Documentation

#define IWDG_KEY_ENABLE 0x0000CCCCu

IWDG Peripheral Enable

Definition at line 184 of file stm32l4xx_hal_iwdg.h.

#define IWDG_KEY_RELOAD 0x0000AAAAu

IWDG Key Register BitMask.

IWDG Reload Counter Enable

Definition at line 183 of file stm32l4xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

IWDG KR Write Access Disable

Definition at line 186 of file stm32l4xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u

IWDG KR Write Access Enable

Definition at line 185 of file stm32l4xx_hal_iwdg.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG Private Macros

Defines
IWDG Private Macros
IWDG

Defines

#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Define Documentation

#define IS_IWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == IWDG_PRESCALER_4)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
                                               ((__PRESCALER__) == IWDG_PRESCALER_256))

Check IWDG prescaler value.

Parameters:
__PRESCALER__ IWDG prescaler value
Return values:
None

Definition at line 216 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_RELOAD ( __RELOAD__ ) ((__RELOAD__) <= IWDG_RLR_RL)

Check IWDG reload value.

Parameters:
__RELOAD__ IWDG reload value
Return values:
None

Definition at line 229 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_WINDOW ( __WINDOW__ ) ((__WINDOW__) <= IWDG_WINR_WIN)

Check IWDG window value.

Parameters:
__WINDOW__ IWDG window value
Return values:
None

Definition at line 236 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IWDG_DISABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 209 of file stm32l4xx_hal_iwdg.h.

#define IWDG_ENABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 202 of file stm32l4xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LCD Private Defines

Defines
LCD Private Defines
LCD

Defines

#define LCD_TIMEOUT_VALUE 1000

Define Documentation

#define LCD_TIMEOUT_VALUE 1000

Definition at line 122 of file stm32l4xx_hal_lcd.c.

Referenced by HAL_LCD_Clear(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), HAL_LCD_Write(), and LCD_WaitForSynchro().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization/de-initialization methods

Functions
Initialization/de-initialization methods
LCD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LCD_Init (LCD_HandleTypeDef *hlcd)
Initialize the LCD peripheral according to the specified parameters in the LCD_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_LCD_DeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD peripheral.
__weak void | HAL_LCD_MspDeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD MSP.
__weak void | HAL_LCD_MspInit (LCD_HandleTypeDef *hlcd)
Initialize the LCD MSP.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]

Function Documentation

HAL_StatusTypeDef HAL_LCD_DeInit ( LCD_HandleTypeDef * hlcd )

DeInitialize the LCD peripheral.

Parameters:
hlcd,: LCD handle
Return values:
HAL status

Definition at line 276 of file stm32l4xx_hal_lcd.c.

References assert_param, LCD_HandleTypeDef::ErrorCode, HAL_LCD_ERROR_NONE, HAL_LCD_MspDeInit(), HAL_LCD_STATE_BUSY, HAL_LCD_STATE_RESET, LCD_HandleTypeDef::Instance, and LCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LCD_Init ( LCD_HandleTypeDef * hlcd )

Initialize the LCD peripheral according to the specified parameters in the LCD_InitStruct and initialize the associated handle.

Note:
This function can be used only when the LCD is disabled.
Parameters:
hlcd,: LCD handle
Return values:
None

< Wait Until the LCD Booster is ready

Definition at line 157 of file stm32l4xx_hal_lcd.c.

References __HAL_LCD_DISABLE, __HAL_LCD_ENABLE, __HAL_LCD_GET_FLAG, assert_param, LCD_InitTypeDef::Bias, LCD_InitTypeDef::BlinkFrequency, LCD_InitTypeDef::BlinkMode, LCD_InitTypeDef::Contrast, LCD_InitTypeDef::DeadTime, LCD_InitTypeDef::Divider, LCD_InitTypeDef::Duty, LCD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_LCD_ERROR_ENS, HAL_LCD_ERROR_NONE, HAL_LCD_ERROR_RDY, HAL_LCD_MspInit(), HAL_LCD_STATE_BUSY, HAL_LCD_STATE_READY, HAL_LCD_STATE_RESET, LCD_InitTypeDef::HighDrive, LCD_HandleTypeDef::Init, LCD_HandleTypeDef::Instance, IS_LCD_BIAS, IS_LCD_BLINK_FREQUENCY, IS_LCD_BLINK_MODE, IS_LCD_CONTRAST, IS_LCD_DEAD_TIME, IS_LCD_DIVIDER, IS_LCD_DUTY, IS_LCD_HIGH_DRIVE, IS_LCD_MUX_SEGMENT, IS_LCD_PRESCALER, IS_LCD_PULSE_ON_DURATION, IS_LCD_VOLTAGE_SOURCE, LCD_FLAG_ENS, LCD_FLAG_RDY, LCD_RAM_REGISTER0, LCD_RAM_REGISTER15, LCD_TIMEOUT_VALUE, LCD_WaitForSynchro(), LCD_HandleTypeDef::Lock, LCD_InitTypeDef::MuxSegment, LCD_InitTypeDef::Prescaler, LCD_InitTypeDef::PulseOnDuration, LCD_HandleTypeDef::State, and LCD_InitTypeDef::VoltageSource.

void HAL_LCD_MspDeInit ( LCD_HandleTypeDef * hlcd )

DeInitialize the LCD MSP.

Parameters:
hlcd,: LCD handle
Return values:
None

Definition at line 306 of file stm32l4xx_hal_lcd.c.

Referenced by HAL_LCD_DeInit().

void HAL_LCD_MspInit ( LCD_HandleTypeDef * hlcd )

Initialize the LCD MSP.

Parameters:
hlcd,: LCD handle
Return values:
None

Definition at line 321 of file stm32l4xx_hal_lcd.c.

Referenced by HAL_LCD_Init().

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STM32L486xx HAL User Manual: IO operation methods

Functions
IO operation methods
LCD Exported Functions

LCD RAM functions. More...

Functions

HAL_StatusTypeDef | HAL_LCD_Write (LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
Write a word in the specific LCD RAM.
HAL_StatusTypeDef | HAL_LCD_Clear (LCD_HandleTypeDef *hlcd)
Clear the LCD RAM registers.
HAL_StatusTypeDef | HAL_LCD_UpdateDisplayRequest (LCD_HandleTypeDef *hlcd)
Enable the Update Display Request.

Detailed Description

LCD RAM functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..] Using its double buffer memory the LCD controller ensures the coherency of the
 displayed information without having to use interrupts to control LCD_RAM
 modification.
 The application software can access the first buffer level (LCD_RAM) through
 the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API,
 it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API.
 This UDR flag (update display request) requests the updated information to be
 moved into the second buffer level (LCD_DISPLAY).
 This operation is done synchronously with the frame (at the beginning of the
 next frame), until the update is completed, the LCD_RAM is write protected and
 the UDR flag stays high.
 Once the update is completed another flag (UDD - Update Display Done) is set and
 generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
 The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one
 even frame.
 The update will not occur (UDR = 1 and UDD = 0) until the display is
 enabled (LCDEN = 1).

Function Documentation

HAL_StatusTypeDef HAL_LCD_Clear ( LCD_HandleTypeDef * hlcd )

Clear the LCD RAM registers.

Parameters:
hlcd,: LCD handle
Return values:
None

< Wait Until the LCD is ready

Definition at line 438 of file stm32l4xx_hal_lcd.c.

References __HAL_LCD_GET_FLAG, LCD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_LCD_ERROR_UDR, HAL_LCD_STATE_BUSY, HAL_LCD_STATE_READY, HAL_LCD_UpdateDisplayRequest(), LCD_HandleTypeDef::Instance, LCD_FLAG_UDR, LCD_RAM_REGISTER0, LCD_RAM_REGISTER15, LCD_TIMEOUT_VALUE, and LCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest ( LCD_HandleTypeDef * hlcd )

Enable the Update Display Request.

Parameters:
hlcd,: LCD handle
Note:
Each time software modifies the LCD_RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit stays set until the end of the update and during this time the LCD_RAM is write protected.
When the display is disabled, the update is performed for all LCD_DISPLAY locations. When the display is enabled, the update is performed only for locations for which commons are active (depending on DUTY). For example if DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
Return values:
None

< Wait Until the LCD display is done

Definition at line 497 of file stm32l4xx_hal_lcd.c.

References __HAL_LCD_CLEAR_FLAG, __HAL_LCD_GET_FLAG, LCD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_LCD_ERROR_UDD, HAL_LCD_STATE_READY, LCD_HandleTypeDef::Instance, LCD_FLAG_UDD, LCD_TIMEOUT_VALUE, and LCD_HandleTypeDef::State.

Referenced by HAL_LCD_Clear().

HAL_StatusTypeDef HAL_LCD_Write | ( | LCD_HandleTypeDef * | hlcd,
 |  | uint32_t | RAMRegisterIndex,
 |  | uint32_t | RAMRegisterMask,
 |  | uint32_t | Data
 | ) |  |

Write a word in the specific LCD RAM.

Parameters:
hlcd,: LCD handle
RAMRegisterIndex,: specifies the LCD RAM Register. This parameter can be one of the following values:
  • LCD_RAM_REGISTER0: LCD RAM Register 0
  • LCD_RAM_REGISTER1: LCD RAM Register 1
  • LCD_RAM_REGISTER2: LCD RAM Register 2
  • LCD_RAM_REGISTER3: LCD RAM Register 3
  • LCD_RAM_REGISTER4: LCD RAM Register 4
  • LCD_RAM_REGISTER5: LCD RAM Register 5
  • LCD_RAM_REGISTER6: LCD RAM Register 6
  • LCD_RAM_REGISTER7: LCD RAM Register 7
  • LCD_RAM_REGISTER8: LCD RAM Register 8
  • LCD_RAM_REGISTER9: LCD RAM Register 9
  • LCD_RAM_REGISTER10: LCD RAM Register 10
  • LCD_RAM_REGISTER11: LCD RAM Register 11
  • LCD_RAM_REGISTER12: LCD RAM Register 12
  • LCD_RAM_REGISTER13: LCD RAM Register 13
  • LCD_RAM_REGISTER14: LCD RAM Register 14
  • LCD_RAM_REGISTER15: LCD RAM Register 15
RAMRegisterMask,: specifies the LCD RAM Register Data Mask.
Data,: specifies LCD Data Value to be written.
Return values:
None

< Wait Until the LCD is ready

Definition at line 389 of file stm32l4xx_hal_lcd.c.

References __HAL_LCD_GET_FLAG, assert_param, LCD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_LCD_ERROR_UDR, HAL_LCD_STATE_BUSY, HAL_LCD_STATE_READY, LCD_HandleTypeDef::Instance, IS_LCD_RAM_REGISTER, LCD_FLAG_UDR, LCD_TIMEOUT_VALUE, and LCD_HandleTypeDef::State.

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STM32L486xx HAL User Manual: Peripheral State methods

Functions
Peripheral State methods
LCD Exported Functions

LCD State functions. More...

Functions

HAL_LCD_StateTypeDef | HAL_LCD_GetState (LCD_HandleTypeDef *hlcd)
Return the LCD handle state.
uint32_t | HAL_LCD_GetError (LCD_HandleTypeDef *hlcd)
Return the LCD error code.

Detailed Description

LCD State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
     This subsection provides a set of functions allowing to control the LCD:
      (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State.
      (+) HAL_LCD_GetError() API to return the LCD error code.

Function Documentation

uint32_t HAL_LCD_GetError ( LCD_HandleTypeDef * hlcd )

Return the LCD error code.

Parameters:
hlcd,: LCD handle
Return values:
LCD Error Code

Definition at line 567 of file stm32l4xx_hal_lcd.c.

References LCD_HandleTypeDef::ErrorCode.

HAL_LCD_StateTypeDef HAL_LCD_GetState ( LCD_HandleTypeDef * hlcd )

Return the LCD handle state.

Parameters:
hlcd,: LCD handle
Return values:
HAL state

Definition at line 556 of file stm32l4xx_hal_lcd.c.

References LCD_HandleTypeDef::State.

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STM32L486xx HAL User Manual: LCD Private Functions

Functions
LCD Private Functions
LCD

Functions

HAL_StatusTypeDef LCD_WaitForSynchro (LCD_HandleTypeDef *hlcd)
Wait until the LCD FCR register is synchronized in the LCDCLK domain.

Function Documentation

HAL_StatusTypeDef LCD_WaitForSynchro ( LCD_HandleTypeDef * hlcd )

Wait until the LCD FCR register is synchronized in the LCDCLK domain.

This function must be called after any write operation to LCD_FCR register.

Return values:
None

Definition at line 589 of file stm32l4xx_hal_lcd.c.

References __HAL_LCD_GET_FLAG, LCD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_LCD_ERROR_FCRSF, LCD_FLAG_FCRSF, and LCD_TIMEOUT_VALUE.

Referenced by HAL_LCD_Init().

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STM32L486xx HAL User Manual: LCD Exported Types

Data Structures | Enumerations
LCD Exported Types
LCD

Data Structures

struct | LCD_InitTypeDef
LCD Init structure definition. More...
struct | LCD_HandleTypeDef
UART handle Structure definition. More...

Enumerations

enum HAL_LCD_StateTypeDef {
HAL_LCD_STATE_RESET = 0x00, HAL_LCD_STATE_READY = 0x01, HAL_LCD_STATE_BUSY = 0x02, HAL_LCD_STATE_TIMEOUT = 0x03,
HAL_LCD_STATE_ERROR = 0x04
}
HAL LCD State structures definition. More...

Enumeration Type Documentation

enum HAL_LCD_StateTypeDef

HAL LCD State structures definition.

Enumerator:
HAL_LCD_STATE_RESET

Peripheral is not yet Initialized

HAL_LCD_STATE_READY

Peripheral Initialized and ready for use

HAL_LCD_STATE_BUSY

an internal process is ongoing

HAL_LCD_STATE_TIMEOUT

Timeout state

HAL_LCD_STATE_ERROR

Error

Definition at line 99 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LCD_InitTypeDef Struct Reference
LCD Exported Types

LCD Init structure definition. More...

#include <stm32l4xx_hal_lcd.h>

Data Fields

uint32_t | Prescaler
uint32_t | Divider
uint32_t | Duty
uint32_t | Bias
uint32_t | VoltageSource
uint32_t | Contrast
uint32_t | DeadTime
uint32_t | PulseOnDuration
uint32_t | HighDrive
uint32_t | BlinkMode
uint32_t | BlinkFrequency
uint32_t | MuxSegment

Detailed Description

LCD Init structure definition.

Definition at line 68 of file stm32l4xx_hal_lcd.h.

Field Documentation

uint32_t LCD_InitTypeDef::Bias

Configures the LCD Bias. This parameter can be one value of LCD Bias

Definition at line 76 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::BlinkFrequency

Configures the LCD Blink frequency. This parameter can be one value of LCD Blink Frequency

Definition at line 90 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::BlinkMode

Configures the LCD Blink Mode. This parameter can be one value of LCD Blink Mode

Definition at line 88 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::Contrast

Configures the LCD Contrast. This parameter can be one value of LCD Contrast

Definition at line 80 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::DeadTime

Configures the LCD Dead Time. This parameter can be one value of LCD Dead Time

Definition at line 82 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::Divider

Configures the LCD Divider. This parameter can be one value of LCD Divider

Definition at line 72 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::Duty

Configures the LCD Duty. This parameter can be one value of LCD Duty

Definition at line 74 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::HighDrive

Enable or disable the low resistance divider. This parameter can be one value of LCD High Drive

Definition at line 86 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::MuxSegment

Enable or disable mux segment. This parameter can be one value of LCD Mux Segment

Definition at line 92 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::Prescaler

Configures the LCD Prescaler. This parameter can be one value of LCD Prescaler

Definition at line 70 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::PulseOnDuration

Configures the LCD Pulse On Duration. This parameter can be one value of LCD Pulse On Duration

Definition at line 84 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::VoltageSource

Selects the LCD Voltage source. This parameter can be one value of LCD Voltage Source

Definition at line 78 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_lcd.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LCD_HandleTypeDef Struct Reference
LCD Exported Types

UART handle Structure definition. More...

#include <stm32l4xx_hal_lcd.h>

Data Fields

LCD_TypeDef * | Instance
LCD_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_LCD_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

UART handle Structure definition.

Definition at line 111 of file stm32l4xx_hal_lcd.h.

Field Documentation

__IO uint32_t LCD_HandleTypeDef::ErrorCode

Definition at line 121 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), HAL_LCD_DeInit(), HAL_LCD_GetError(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), HAL_LCD_Write(), and LCD_WaitForSynchro().

LCD_InitTypeDef LCD_HandleTypeDef::Init

Definition at line 115 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

LCD_TypeDef* LCD_HandleTypeDef::Instance

Definition at line 113 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), HAL_LCD_DeInit(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), and HAL_LCD_Write().

HAL_LockTypeDef LCD_HandleTypeDef::Lock

Definition at line 117 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

__IO HAL_LCD_StateTypeDef LCD_HandleTypeDef::State

Definition at line 119 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), HAL_LCD_DeInit(), HAL_LCD_GetState(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), and HAL_LCD_Write().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_lcd.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LCD Error Code

Defines
LCD Error Code
LCD Exported Constants

Defines

#define | HAL_LCD_ERROR_NONE ((uint32_t)0x00)
#define | HAL_LCD_ERROR_FCRSF ((uint32_t)0x01)
#define | HAL_LCD_ERROR_UDR ((uint32_t)0x02)
#define | HAL_LCD_ERROR_UDD ((uint32_t)0x04)
#define | HAL_LCD_ERROR_ENS ((uint32_t)0x08)
#define | HAL_LCD_ERROR_RDY ((uint32_t)0x10)

Define Documentation

#define HAL_LCD_ERROR_ENS ((uint32_t)0x08)

LCD enabled status flag timeout error

Definition at line 140 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01)

Synchro flag timeout error

Definition at line 137 of file stm32l4xx_hal_lcd.h.

Referenced by LCD_WaitForSynchro().

#define HAL_LCD_ERROR_NONE ((uint32_t)0x00)

No error

Definition at line 136 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_DeInit(), and HAL_LCD_Init().

#define HAL_LCD_ERROR_RDY ((uint32_t)0x10)

LCD Booster ready timeout error

Definition at line 141 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define HAL_LCD_ERROR_UDD ((uint32_t)0x04)

Update display done flag timeout error

Definition at line 139 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_UpdateDisplayRequest().

#define HAL_LCD_ERROR_UDR ((uint32_t)0x02)

Update display request flag timeout error

Definition at line 138 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), and HAL_LCD_Write().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LCD Prescaler

Defines
LCD Prescaler
LCD Exported Constants

Defines

#define | LCD_PRESCALER_1 ((uint32_t)0x00000000)
#define | LCD_PRESCALER_2 ((uint32_t)0x00400000)
#define | LCD_PRESCALER_4 ((uint32_t)0x00800000)
#define | LCD_PRESCALER_8 ((uint32_t)0x00C00000)
#define | LCD_PRESCALER_16 ((uint32_t)0x01000000)
#define | LCD_PRESCALER_32 ((uint32_t)0x01400000)
#define | LCD_PRESCALER_64 ((uint32_t)0x01800000)
#define | LCD_PRESCALER_128 ((uint32_t)0x01C00000)
#define | LCD_PRESCALER_256 ((uint32_t)0x02000000)
#define | LCD_PRESCALER_512 ((uint32_t)0x02400000)
#define | LCD_PRESCALER_1024 ((uint32_t)0x02800000)
#define | LCD_PRESCALER_2048 ((uint32_t)0x02C00000)
#define | LCD_PRESCALER_4096 ((uint32_t)0x03000000)
#define | LCD_PRESCALER_8192 ((uint32_t)0x03400000)
#define | LCD_PRESCALER_16384 ((uint32_t)0x03800000)
#define | LCD_PRESCALER_32768 ((uint32_t)0x03C00000)

Define Documentation

#define LCD_PRESCALER_1 ((uint32_t)0x00000000)

CLKPS = LCDCLK

Definition at line 149 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_1024 ((uint32_t)0x02800000)

CLKPS = LCDCLK/1024

Definition at line 159 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_128 ((uint32_t)0x01C00000)

CLKPS = LCDCLK/128

Definition at line 156 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_16 ((uint32_t)0x01000000)

CLKPS = LCDCLK/16

Definition at line 153 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_16384 ((uint32_t)0x03800000)

CLKPS = LCDCLK/16384

Definition at line 163 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_2 ((uint32_t)0x00400000)

CLKPS = LCDCLK/2

Definition at line 150 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_2048 ((uint32_t)0x02C00000)

CLKPS = LCDCLK/2048

Definition at line 160 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_256 ((uint32_t)0x02000000)

CLKPS = LCDCLK/256

Definition at line 157 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_32 ((uint32_t)0x01400000)

CLKPS = LCDCLK/32

Definition at line 154 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_32768 ((uint32_t)0x03C00000)

CLKPS = LCDCLK/32768

Definition at line 164 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_4 ((uint32_t)0x00800000)

CLKPS = LCDCLK/4

Definition at line 151 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_4096 ((uint32_t)0x03000000)

CLKPS = LCDCLK/4096

Definition at line 161 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_512 ((uint32_t)0x02400000)

CLKPS = LCDCLK/512

Definition at line 158 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_64 ((uint32_t)0x01800000)

CLKPS = LCDCLK/64

Definition at line 155 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_8 ((uint32_t)0x00C00000)

CLKPS = LCDCLK/8

Definition at line 152 of file stm32l4xx_hal_lcd.h.

#define LCD_PRESCALER_8192 ((uint32_t)0x03400000)

CLKPS = LCDCLK/8192

Definition at line 162 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Divider

Defines
LCD Divider
LCD Exported Constants

Defines

#define | LCD_DIVIDER_16 ((uint32_t)0x00000000)
#define | LCD_DIVIDER_17 ((uint32_t)0x00040000)
#define | LCD_DIVIDER_18 ((uint32_t)0x00080000)
#define | LCD_DIVIDER_19 ((uint32_t)0x000C0000)
#define | LCD_DIVIDER_20 ((uint32_t)0x00100000)
#define | LCD_DIVIDER_21 ((uint32_t)0x00140000)
#define | LCD_DIVIDER_22 ((uint32_t)0x00180000)
#define | LCD_DIVIDER_23 ((uint32_t)0x001C0000)
#define | LCD_DIVIDER_24 ((uint32_t)0x00200000)
#define | LCD_DIVIDER_25 ((uint32_t)0x00240000)
#define | LCD_DIVIDER_26 ((uint32_t)0x00280000)
#define | LCD_DIVIDER_27 ((uint32_t)0x002C0000)
#define | LCD_DIVIDER_28 ((uint32_t)0x00300000)
#define | LCD_DIVIDER_29 ((uint32_t)0x00340000)
#define | LCD_DIVIDER_30 ((uint32_t)0x00380000)
#define | LCD_DIVIDER_31 ((uint32_t)0x003C0000)

Define Documentation

#define LCD_DIVIDER_16 ((uint32_t)0x00000000)

LCD frequency = CLKPS/16

Definition at line 172 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_17 ((uint32_t)0x00040000)

LCD frequency = CLKPS/17

Definition at line 173 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_18 ((uint32_t)0x00080000)

LCD frequency = CLKPS/18

Definition at line 174 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_19 ((uint32_t)0x000C0000)

LCD frequency = CLKPS/19

Definition at line 175 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_20 ((uint32_t)0x00100000)

LCD frequency = CLKPS/20

Definition at line 176 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_21 ((uint32_t)0x00140000)

LCD frequency = CLKPS/21

Definition at line 177 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_22 ((uint32_t)0x00180000)

LCD frequency = CLKPS/22

Definition at line 178 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_23 ((uint32_t)0x001C0000)

LCD frequency = CLKPS/23

Definition at line 179 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_24 ((uint32_t)0x00200000)

LCD frequency = CLKPS/24

Definition at line 180 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_25 ((uint32_t)0x00240000)

LCD frequency = CLKPS/25

Definition at line 181 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_26 ((uint32_t)0x00280000)

LCD frequency = CLKPS/26

Definition at line 182 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_27 ((uint32_t)0x002C0000)

LCD frequency = CLKPS/27

Definition at line 183 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_28 ((uint32_t)0x00300000)

LCD frequency = CLKPS/28

Definition at line 184 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_29 ((uint32_t)0x00340000)

LCD frequency = CLKPS/29

Definition at line 185 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_30 ((uint32_t)0x00380000)

LCD frequency = CLKPS/30

Definition at line 186 of file stm32l4xx_hal_lcd.h.

#define LCD_DIVIDER_31 ((uint32_t)0x003C0000)

LCD frequency = CLKPS/31

Definition at line 187 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Duty

Defines
LCD Duty
LCD Exported Constants

Defines

#define | LCD_DUTY_STATIC ((uint32_t)0x00000000)
#define | LCD_DUTY_1_2 (LCD_CR_DUTY_0)
#define | LCD_DUTY_1_3 (LCD_CR_DUTY_1)
#define | LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0))
#define | LCD_DUTY_1_8 (LCD_CR_DUTY_2)

Define Documentation

#define LCD_DUTY_1_2 (LCD_CR_DUTY_0)

1/2 duty

Definition at line 197 of file stm32l4xx_hal_lcd.h.

#define LCD_DUTY_1_3 (LCD_CR_DUTY_1)

1/3 duty

Definition at line 198 of file stm32l4xx_hal_lcd.h.

#define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0))

1/4 duty

Definition at line 199 of file stm32l4xx_hal_lcd.h.

#define LCD_DUTY_1_8 (LCD_CR_DUTY_2)

1/8 duty

Definition at line 200 of file stm32l4xx_hal_lcd.h.

#define LCD_DUTY_STATIC ((uint32_t)0x00000000)

Static duty

Definition at line 196 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Bias

Defines
LCD Bias
LCD Exported Constants

Defines

#define | LCD_BIAS_1_4 ((uint32_t)0x00000000)
#define | LCD_BIAS_1_2 LCD_CR_BIAS_0
#define | LCD_BIAS_1_3 LCD_CR_BIAS_1

Define Documentation

#define LCD_BIAS_1_2 LCD_CR_BIAS_0

1/2 Bias

Definition at line 210 of file stm32l4xx_hal_lcd.h.

#define LCD_BIAS_1_3 LCD_CR_BIAS_1

1/3 Bias

Definition at line 211 of file stm32l4xx_hal_lcd.h.

#define LCD_BIAS_1_4 ((uint32_t)0x00000000)

1/4 Bias

Definition at line 209 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Voltage Source

Defines
LCD Voltage Source
LCD Exported Constants

Defines

#define | LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000)
#define | LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL

Define Documentation

#define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL

External voltage source for the LCD

Definition at line 220 of file stm32l4xx_hal_lcd.h.

#define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000)

Internal voltage source for the LCD

Definition at line 219 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Interrupts

Defines
LCD Interrupts
LCD Exported Constants

Defines

#define | LCD_IT_SOF LCD_FCR_SOFIE
#define | LCD_IT_UDD LCD_FCR_UDDIE

Define Documentation

#define LCD_IT_SOF LCD_FCR_SOFIE

Definition at line 228 of file stm32l4xx_hal_lcd.h.

#define LCD_IT_UDD LCD_FCR_UDDIE

Definition at line 229 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Pulse On Duration

Defines
LCD Pulse On Duration
LCD Exported Constants

Defines

#define | LCD_PULSEONDURATION_0 ((uint32_t)0x00000000)
#define | LCD_PULSEONDURATION_1 (LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_2 (LCD_FCR_PON_1)
#define | LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_4 (LCD_FCR_PON_2)
#define | LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1)
#define | LCD_PULSEONDURATION_7 (LCD_FCR_PON)

Define Documentation

#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000)

Pulse ON duration = 0 pulse

Definition at line 237 of file stm32l4xx_hal_lcd.h.

#define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0)

Pulse ON duration = 1/CK_PS

Definition at line 238 of file stm32l4xx_hal_lcd.h.

#define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1)

Pulse ON duration = 2/CK_PS

Definition at line 239 of file stm32l4xx_hal_lcd.h.

#define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0)

Pulse ON duration = 3/CK_PS

Definition at line 240 of file stm32l4xx_hal_lcd.h.

#define LCD_PULSEONDURATION_4 (LCD_FCR_PON_2)

Pulse ON duration = 4/CK_PS

Definition at line 241 of file stm32l4xx_hal_lcd.h.

#define LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0)

Pulse ON duration = 5/CK_PS

Definition at line 242 of file stm32l4xx_hal_lcd.h.

#define LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1)

Pulse ON duration = 6/CK_PS

Definition at line 243 of file stm32l4xx_hal_lcd.h.

#define LCD_PULSEONDURATION_7 (LCD_FCR_PON)

Pulse ON duration = 7/CK_PS

Definition at line 244 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Dead Time

Defines
LCD Dead Time
LCD Exported Constants

Defines

#define | LCD_DEADTIME_0 ((uint32_t)0x00000000)
#define | LCD_DEADTIME_1 (LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_2 (LCD_FCR_DEAD_1)
#define | LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_4 (LCD_FCR_DEAD_2)
#define | LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1)
#define | LCD_DEADTIME_7 (LCD_FCR_DEAD)

Define Documentation

#define LCD_DEADTIME_0 ((uint32_t)0x00000000)

No dead Time

Definition at line 253 of file stm32l4xx_hal_lcd.h.

#define LCD_DEADTIME_1 (LCD_FCR_DEAD_0)

One Phase between different couple of Frame

Definition at line 254 of file stm32l4xx_hal_lcd.h.

#define LCD_DEADTIME_2 (LCD_FCR_DEAD_1)

Two Phase between different couple of Frame

Definition at line 255 of file stm32l4xx_hal_lcd.h.

#define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0)

Three Phase between different couple of Frame

Definition at line 256 of file stm32l4xx_hal_lcd.h.

#define LCD_DEADTIME_4 (LCD_FCR_DEAD_2)

Four Phase between different couple of Frame

Definition at line 257 of file stm32l4xx_hal_lcd.h.

#define LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0)

Five Phase between different couple of Frame

Definition at line 258 of file stm32l4xx_hal_lcd.h.

#define LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1)

Six Phase between different couple of Frame

Definition at line 259 of file stm32l4xx_hal_lcd.h.

#define LCD_DEADTIME_7 (LCD_FCR_DEAD)

Seven Phase between different couple of Frame

Definition at line 260 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Blink Mode

Defines
LCD Blink Mode
LCD Exported Constants

Defines

#define | LCD_BLINKMODE_OFF ((uint32_t)0x00000000)
#define | LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0)
#define | LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1)
#define | LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK)

Define Documentation

#define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK)

Blink enabled on all SEG and all COM (all pixels)

Definition at line 272 of file stm32l4xx_hal_lcd.h.

#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000)

Blink disabled

Definition at line 268 of file stm32l4xx_hal_lcd.h.

#define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1)

Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty)

Definition at line 270 of file stm32l4xx_hal_lcd.h.

#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0)

Blink enabled on SEG[0], COM[0] (1 pixel)

Definition at line 269 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Blink Frequency

Defines
LCD Blink Frequency
LCD Exported Constants

Defines

#define | LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000)
#define | LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1)
#define | LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2)
#define | LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)
#define | LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF)

Define Documentation

#define LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF)

The Blink frequency = fLCD/1024

Definition at line 287 of file stm32l4xx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2)

The Blink frequency = fLCD/128

Definition at line 284 of file stm32l4xx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0)

The Blink frequency = fLCD/16

Definition at line 281 of file stm32l4xx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)

The Blink frequency = fLCD/256

Definition at line 285 of file stm32l4xx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1)

The Blink frequency = fLCD/32

Definition at line 282 of file stm32l4xx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)

The Blink frequency = fLCD/512

Definition at line 286 of file stm32l4xx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0)

The Blink frequency = fLCD/64

Definition at line 283 of file stm32l4xx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000)

The Blink frequency = fLCD/8

Definition at line 280 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Contrast

Defines
LCD Contrast
LCD Exported Constants

Defines

#define | LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000)
#define | LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1)
#define | LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2)
#define | LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1)
#define | LCD_CONTRASTLEVEL_7 (LCD_FCR_CC)

Define Documentation

#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000)

Maximum Voltage = 2.60V

Definition at line 295 of file stm32l4xx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0)

Maximum Voltage = 2.73V

Definition at line 296 of file stm32l4xx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1)

Maximum Voltage = 2.86V

Definition at line 297 of file stm32l4xx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0)

Maximum Voltage = 2.99V

Definition at line 298 of file stm32l4xx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2)

Maximum Voltage = 3.12V

Definition at line 299 of file stm32l4xx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0)

Maximum Voltage = 3.26V

Definition at line 300 of file stm32l4xx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1)

Maximum Voltage = 3.40V

Definition at line 301 of file stm32l4xx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_7 (LCD_FCR_CC)

Maximum Voltage = 3.55V

Definition at line 302 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD RAMRegister

Defines
LCD RAMRegister
LCD Exported Constants

Defines

#define | LCD_RAM_REGISTER0 ((uint32_t)0x00000000)
#define | LCD_RAM_REGISTER1 ((uint32_t)0x00000001)
#define | LCD_RAM_REGISTER2 ((uint32_t)0x00000002)
#define | LCD_RAM_REGISTER3 ((uint32_t)0x00000003)
#define | LCD_RAM_REGISTER4 ((uint32_t)0x00000004)
#define | LCD_RAM_REGISTER5 ((uint32_t)0x00000005)
#define | LCD_RAM_REGISTER6 ((uint32_t)0x00000006)
#define | LCD_RAM_REGISTER7 ((uint32_t)0x00000007)
#define | LCD_RAM_REGISTER8 ((uint32_t)0x00000008)
#define | LCD_RAM_REGISTER9 ((uint32_t)0x00000009)
#define | LCD_RAM_REGISTER10 ((uint32_t)0x0000000A)
#define | LCD_RAM_REGISTER11 ((uint32_t)0x0000000B)
#define | LCD_RAM_REGISTER12 ((uint32_t)0x0000000C)
#define | LCD_RAM_REGISTER13 ((uint32_t)0x0000000D)
#define | LCD_RAM_REGISTER14 ((uint32_t)0x0000000E)
#define | LCD_RAM_REGISTER15 ((uint32_t)0x0000000F)

Define Documentation

#define LCD_RAM_REGISTER0 ((uint32_t)0x00000000)

LCD RAM Register 0

Definition at line 310 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), and HAL_LCD_Init().

#define LCD_RAM_REGISTER1 ((uint32_t)0x00000001)

LCD RAM Register 1

Definition at line 311 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER10 ((uint32_t)0x0000000A)

LCD RAM Register 10

Definition at line 320 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER11 ((uint32_t)0x0000000B)

LCD RAM Register 11

Definition at line 321 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER12 ((uint32_t)0x0000000C)

LCD RAM Register 12

Definition at line 322 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER13 ((uint32_t)0x0000000D)

LCD RAM Register 13

Definition at line 323 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER14 ((uint32_t)0x0000000E)

LCD RAM Register 14

Definition at line 324 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER15 ((uint32_t)0x0000000F)

LCD RAM Register 15

Definition at line 325 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), and HAL_LCD_Init().

#define LCD_RAM_REGISTER2 ((uint32_t)0x00000002)

LCD RAM Register 2

Definition at line 312 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER3 ((uint32_t)0x00000003)

LCD RAM Register 3

Definition at line 313 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER4 ((uint32_t)0x00000004)

LCD RAM Register 4

Definition at line 314 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER5 ((uint32_t)0x00000005)

LCD RAM Register 5

Definition at line 315 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER6 ((uint32_t)0x00000006)

LCD RAM Register 6

Definition at line 316 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER7 ((uint32_t)0x00000007)

LCD RAM Register 7

Definition at line 317 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER8 ((uint32_t)0x00000008)

LCD RAM Register 8

Definition at line 318 of file stm32l4xx_hal_lcd.h.

#define LCD_RAM_REGISTER9 ((uint32_t)0x00000009)

LCD RAM Register 9

Definition at line 319 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD High Drive

Defines
LCD High Drive
LCD Exported Constants

Defines

#define | LCD_HIGHDRIVE_DISABLE ((uint32_t)0x00000000)
#define | LCD_HIGHDRIVE_ENABLE (LCD_FCR_HD)

Define Documentation

#define LCD_HIGHDRIVE_DISABLE ((uint32_t)0x00000000)

High drive disabled

Definition at line 334 of file stm32l4xx_hal_lcd.h.

#define LCD_HIGHDRIVE_ENABLE (LCD_FCR_HD)

High drive enabled

Definition at line 335 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Mux Segment

Defines
LCD Mux Segment
LCD Exported Constants

Defines

#define | LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000)
#define | LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG)

Define Documentation

#define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000)

SEG pin multiplexing disabled

Definition at line 344 of file stm32l4xx_hal_lcd.h.

#define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG)

SEG[31:28] are multiplexed with SEG[43:40]

Definition at line 345 of file stm32l4xx_hal_lcd.h.

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STM32L486xx HAL User Manual: LCD Flags Definition

Defines
LCD Flags Definition
LCD Exported Constants

Defines

#define | LCD_FLAG_ENS LCD_SR_ENS
#define | LCD_FLAG_SOF LCD_SR_SOF
#define | LCD_FLAG_UDR LCD_SR_UDR
#define | LCD_FLAG_UDD LCD_SR_UDD
#define | LCD_FLAG_RDY LCD_SR_RDY
#define | LCD_FLAG_FCRSF LCD_SR_FCRSR

Define Documentation

#define LCD_FLAG_ENS LCD_SR_ENS

LCD enabled status

Definition at line 353 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define LCD_FLAG_FCRSF LCD_SR_FCRSR

LCD Frame Control Register Synchronization flag

Definition at line 358 of file stm32l4xx_hal_lcd.h.

Referenced by LCD_WaitForSynchro().

#define LCD_FLAG_RDY LCD_SR_RDY

Ready flag

Definition at line 357 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define LCD_FLAG_SOF LCD_SR_SOF

Start of frame flag

Definition at line 354 of file stm32l4xx_hal_lcd.h.

#define LCD_FLAG_UDD LCD_SR_UDD

Update display done

Definition at line 356 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_UpdateDisplayRequest().

#define LCD_FLAG_UDR LCD_SR_UDR

Update display request

Definition at line 355 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), and HAL_LCD_Write().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LCD Exported Macros

Defines
LCD Exported Macros
LCD

Defines

#define | __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
Reset LCD handle state.
#define | __HAL_LCD_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
Enable the LCD peripheral.
#define | __HAL_LCD_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
Disable the LCD peripheral.
#define | __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)
Enable the low resistance divider.
#define | __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)
Disable the low resistance divider.
#define | __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
Enable the voltage output buffer for higher driving capability.
#define | __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
Disable the voltage output buffer for higher driving capability.
#define | __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)
Configure the LCD pulse on duration.
#define | __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)
Configure the LCD dead time.
#define | __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)
Configure the LCD contrast.
#define | __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)
Configure the LCD Blink mode and Blink frequency.
#define | __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified LCD interrupt.
#define | __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified LCD interrupt.
#define | __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
Check whether the specified LCD interrupt source is enabled or not.
#define | __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified LCD flag is set or not.
#define | __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))
Clear the specified LCD pending flag.

Define Documentation

#define __HAL_LCD_BLINK_CONFIG | ( | __HANDLE__,
 |  | __BLINKMODE__,
 |  | __BLINKFREQUENCY__
 | ) |
Value:
do {                                                                    \
                MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
                LCD_WaitForSynchro(__HANDLE__);                                       \
              } while(0)

Configure the LCD Blink mode and Blink frequency.

Parameters:
__HANDLE__,: specifies the LCD Handle.
__BLINKMODE__,: specifies the LCD blink mode. This parameter can be one of the following values:
  • LCD_BLINKMODE_OFF: Blink disabled
  • LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
  • LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty)
  • LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM (all pixels)
__BLINKFREQUENCY__,: specifies the LCD blink frequency.
  • LCD_BLINKFREQUENCY_DIV8: The Blink frequency = fLcd/8
  • LCD_BLINKFREQUENCY_DIV16: The Blink frequency = fLcd/16
  • LCD_BLINKFREQUENCY_DIV32: The Blink frequency = fLcd/32
  • LCD_BLINKFREQUENCY_DIV64: The Blink frequency = fLcd/64
  • LCD_BLINKFREQUENCY_DIV128: The Blink frequency = fLcd/128
  • LCD_BLINKFREQUENCY_DIV256: The Blink frequency = fLcd/256
  • LCD_BLINKFREQUENCY_DIV512: The Blink frequency = fLcd/512
  • LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
Return values:
None

Definition at line 513 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))

Clear the specified LCD pending flag.

Parameters:
__HANDLE__,: specifies the LCD Handle.
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • LCD_FLAG_SOF: Start of Frame Interrupt
  • LCD_FLAG_UDD: Update Display Done Interrupt
Return values:
None

Definition at line 590 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_UpdateDisplayRequest().

#define __HAL_LCD_CONTRAST_CONFIG | ( | __HANDLE__,
 |  | __CONTRAST__
 | ) |
Value:
do {                                                                    \
                MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__));  \
                LCD_WaitForSynchro(__HANDLE__);                                       \
              } while(0)

Configure the LCD contrast.

Parameters:
__HANDLE__,: specifies the LCD Handle.
__CONTRAST__,: specifies the LCD Contrast. This parameter can be one of the following values:
  • LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
  • LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
  • LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
  • LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
  • LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
  • LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
  • LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
  • LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
Return values:
None

Definition at line 485 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_DEADTIME_CONFIG | ( | __HANDLE__,
 |  | __DEADTIME__
 | ) |
Value:
do {                                                                     \
                    MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
                    LCD_WaitForSynchro(__HANDLE__);                                        \
                  } while(0)

Configure the LCD dead time.

Parameters:
__HANDLE__,: specifies the LCD Handle.
__DEADTIME__,: specifies the LCD dead time. This parameter can be one of the following values:
  • LCD_DEADTIME_0: No dead Time
  • LCD_DEADTIME_1: One Phase between different couple of Frame
  • LCD_DEADTIME_2: Two Phase between different couple of Frame
  • LCD_DEADTIME_3: Three Phase between different couple of Frame
  • LCD_DEADTIME_4: Four Phase between different couple of Frame
  • LCD_DEADTIME_5: Five Phase between different couple of Frame
  • LCD_DEADTIME_6: Six Phase between different couple of Frame
  • LCD_DEADTIME_7: Seven Phase between different couple of Frame
Return values:
None

Definition at line 464 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)

Disable the LCD peripheral.

Parameters:
__HANDLE__,: specifies the LCD Handle.
Return values:
None

Definition at line 388 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define __HAL_LCD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
do {                                                       \
                    CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
                    LCD_WaitForSynchro(__HANDLE__);                          \
                  } while(0)

Disable the specified LCD interrupt.

Parameters:
__HANDLE__,: specifies the LCD Handle.
__INTERRUPT__,: specifies the LCD interrupt source to be disabled. This parameter can be one of the following values:
  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt
Return values:
None

Definition at line 541 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)

Enable the LCD peripheral.

Parameters:
__HANDLE__,: specifies the LCD Handle.
Return values:
None

Definition at line 382 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define __HAL_LCD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
do {                                                      \
                    SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__));  \
                    LCD_WaitForSynchro(__HANDLE__);                         \
                  } while(0)

Enable the specified LCD interrupt.

Parameters:
__HANDLE__,: specifies the LCD Handle.
__INTERRUPT__,: specifies the LCD interrupt source to be enabled. This parameter can be one of the following values:
  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt
Return values:
None

Definition at line 527 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified LCD flag is set or not.

Parameters:
__HANDLE__,: specifies the LCD Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
Note:
The ENS bit is set immediately when the LCDEN bit in the LCD_CR goes from 0 to 1. On deactivation it reflects the real status of LCD so it becomes 0 at the end of the last displayed frame.
  • LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at the beginning of a new frame, at the same time as the display data is updated.
  • LCD_FLAG_UDR: Update Display Request flag.
  • LCD_FLAG_UDD: Update Display Done flag.
  • LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status of the step-up converter.
  • LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. This flag is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 580 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), HAL_LCD_Write(), and LCD_WaitForSynchro().

#define __HAL_LCD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) | (((__HANDLE__)->Instance->FCR) & (__IT__))

Check whether the specified LCD interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the LCD Handle.
__IT__,: specifies the LCD interrupt source to check. This parameter can be one of the following values:
  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt.
Note:
If the device is in STOP mode (PCLK not provided) UDD will not generate an interrupt even if UDDIE = 1. If the display is not enabled the UDD interrupt will never occur.
Return values:
The state of __IT__ (TRUE or FALSE).

Definition at line 558 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_HIGHDRIVER_DISABLE ( __HANDLE__ )
Value:
do {                                                  \
                    CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
                    LCD_WaitForSynchro(__HANDLE__);                     \
                  } while(0)

Disable the low resistance divider.

Parameters:
__HANDLE__,: specifies the LCD Handle.
Return values:
None

Definition at line 409 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_HIGHDRIVER_ENABLE ( __HANDLE__ )
Value:
do {                                                \
                    SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
                    LCD_WaitForSynchro(__HANDLE__);                   \
                  } while(0)

Enable the low resistance divider.

Parameters:
__HANDLE__,: specifies the LCD Handle.
Note:
Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This function is useful in this case if some additional power consumption can be tolerated.
When this mode is enabled, the PulseOn Duration (PON) have to be programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
Return values:
None

Definition at line 399 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_PULSEONDURATION_CONFIG | ( | __HANDLE__,
 |  | __DURATION__
 | ) |
Value:
do {                                                                    \
                    MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
                    LCD_WaitForSynchro(__HANDLE__);                                       \
                  } while(0)

Configure the LCD pulse on duration.

Parameters:
__HANDLE__,: specifies the LCD Handle.
__DURATION__,: specifies the LCD pulse on duration in terms of CK_PS (prescaled LCD clock period) pulses. This parameter can be one of the following values:
  • LCD_PULSEONDURATION_0: 0 pulse
  • LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
  • LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
  • LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
  • LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
  • LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
  • LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
  • LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
Return values:
None

Definition at line 443 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_LCD_STATE_RESET)

Reset LCD handle state.

Parameters:
__HANDLE__,: specifies the LCD Handle.
Return values:
None

Definition at line 376 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_VOLTAGE_BUFFER_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)

Disable the voltage output buffer for higher driving capability.

Parameters:
__HANDLE__,: specifies the LCD Handle.
Return values:
None

Definition at line 425 of file stm32l4xx_hal_lcd.h.

#define __HAL_LCD_VOLTAGE_BUFFER_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)

Enable the voltage output buffer for higher driving capability.

Parameters:
__HANDLE__,: specifies the LCD Handle.
Return values:
None

Definition at line 419 of file stm32l4xx_hal_lcd.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LCD Private Macros

Defines
LCD Private Macros
LCD

Defines

#define | IS_LCD_PRESCALER(__PRESCALER__)
#define | IS_LCD_DIVIDER(__DIVIDER__)
#define | IS_LCD_DUTY(__DUTY__)
#define | IS_LCD_BIAS(__BIAS__)
#define | IS_LCD_VOLTAGE_SOURCE(SOURCE)
#define | IS_LCD_PULSE_ON_DURATION(__DURATION__)
#define | IS_LCD_DEAD_TIME(__TIME__)
#define | IS_LCD_BLINK_MODE(__MODE__)
#define | IS_LCD_BLINK_FREQUENCY(__FREQUENCY__)
#define | IS_LCD_CONTRAST(__CONTRAST__)
#define | IS_LCD_RAM_REGISTER(__REGISTER__)
#define | IS_LCD_HIGH_DRIVE(__VALUE__)
#define | IS_LCD_MUX_SEGMENT(__VALUE__)

Define Documentation

#define IS_LCD_BIAS ( __BIAS__ )
Value:
(((__BIAS__) == LCD_BIAS_1_4) || \
                               ((__BIAS__) == LCD_BIAS_1_2) || \
                               ((__BIAS__) == LCD_BIAS_1_3))

Definition at line 686 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_BLINK_FREQUENCY ( __FREQUENCY__ )
Value:
(((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8)   || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16)  || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32)  || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64)  || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))

Definition at line 717 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_BLINK_MODE ( __MODE__ )
Value:
(((__MODE__) == LCD_BLINKMODE_OFF)            || \
                                     ((__MODE__) == LCD_BLINKMODE_SEG0_COM0)      || \
                                     ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM)    || \
                                     ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))

Definition at line 712 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_CONTRAST ( __CONTRAST__ )
Value:
(((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))

Definition at line 726 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_DEAD_TIME ( __TIME__ )
Value:
(((__TIME__) == LCD_DEADTIME_0) || \
                                    ((__TIME__) == LCD_DEADTIME_1) || \
                                    ((__TIME__) == LCD_DEADTIME_2) || \
                                    ((__TIME__) == LCD_DEADTIME_3) || \
                                    ((__TIME__) == LCD_DEADTIME_4) || \
                                    ((__TIME__) == LCD_DEADTIME_5) || \
                                    ((__TIME__) == LCD_DEADTIME_6) || \
                                    ((__TIME__) == LCD_DEADTIME_7))

Definition at line 703 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_DIVIDER ( __DIVIDER__ )
Value:
(((__DIVIDER__) == LCD_DIVIDER_16) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_17) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_18) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_19) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_20) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_21) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_22) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_23) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_24) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_25) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_26) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_27) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_28) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_29) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_30) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_31))

Definition at line 663 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_DUTY ( __DUTY__ )
Value:
(((__DUTY__) == LCD_DUTY_STATIC)  || \
                               ((__DUTY__) == LCD_DUTY_1_2)     || \
                               ((__DUTY__) == LCD_DUTY_1_3)     || \
                               ((__DUTY__) == LCD_DUTY_1_4)     || \
                               ((__DUTY__) == LCD_DUTY_1_8))

Definition at line 680 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_HIGH_DRIVE ( __VALUE__ )
Value:
(((__VALUE__) == LCD_HIGHDRIVE_DISABLE) || \
                                      ((__VALUE__) == LCD_HIGHDRIVE_ENABLE))

Definition at line 752 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_MUX_SEGMENT ( __VALUE__ )
Value:
(((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
                                       ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))

Definition at line 755 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == LCD_PRESCALER_1)     || \
                                         ((__PRESCALER__) == LCD_PRESCALER_2)     || \
                                         ((__PRESCALER__) == LCD_PRESCALER_4)     || \
                                         ((__PRESCALER__) == LCD_PRESCALER_8)     || \
                                         ((__PRESCALER__) == LCD_PRESCALER_16)    || \
                                         ((__PRESCALER__) == LCD_PRESCALER_32)    || \
                                         ((__PRESCALER__) == LCD_PRESCALER_64)    || \
                                         ((__PRESCALER__) == LCD_PRESCALER_128)   || \
                                         ((__PRESCALER__) == LCD_PRESCALER_256)   || \
                                         ((__PRESCALER__) == LCD_PRESCALER_512)   || \
                                         ((__PRESCALER__) == LCD_PRESCALER_1024)  || \
                                         ((__PRESCALER__) == LCD_PRESCALER_2048)  || \
                                         ((__PRESCALER__) == LCD_PRESCALER_4096)  || \
                                         ((__PRESCALER__) == LCD_PRESCALER_8192)  || \
                                         ((__PRESCALER__) == LCD_PRESCALER_16384) || \
                                         ((__PRESCALER__) == LCD_PRESCALER_32768))

Definition at line 646 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_PULSE_ON_DURATION ( __DURATION__ )
Value:
(((__DURATION__) == LCD_PULSEONDURATION_0) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_1) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_2) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_3) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_4) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_5) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_6) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_7))

Definition at line 694 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_RAM_REGISTER ( __REGISTER__ )
Value:
(((__REGISTER__) == LCD_RAM_REGISTER0)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER1)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER2)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER3)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER4)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER5)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER6)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER7)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER8)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER9)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER10) || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER11) || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER12) || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER13) || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER14) || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER15))

Definition at line 735 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Write().

#define IS_LCD_VOLTAGE_SOURCE ( SOURCE )
Value:
(((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
                                       ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))

Definition at line 690 of file stm32l4xx_hal_lcd.h.

Referenced by HAL_LCD_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
LPTIM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the LPTIM according to the specified parameters in the
          LPTIM_InitTypeDef and initialize the associated handle.
      (+) DeInitialize the LPTIM peripheral.
      (+) Initialize the LPTIM MSP.
      (+) DeInitialize the LPTIM MSP.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize the LPTIM peripheral.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 287 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 174 of file stm32l4xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, LPTIM_HandleTypeDef::Init, LPTIM_InitTypeDef::Input1Source, LPTIM_InitTypeDef::Input2Source, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_INPUT1_SOURCE, IS_LPTIM_INPUT2_SOURCE, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

__weak void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 334 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit().

__weak void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 319 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_Init().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Start-Stop operation functions

Functions
LPTIM Start-Stop operation functions
LPTIM Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.

Detailed Description

Start-Stop operation functions.

  ==============================================================================
                ##### LPTIM Start Stop operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start the PWM mode.
      (+) Stop the PWM mode.
      (+) Start the One pulse mode.
      (+) Stop the One pulse mode.
      (+) Start the Set once mode.
      (+) Stop the Set once mode.
      (+) Start the Encoder mode.
      (+) Stop the Encoder mode.
      (+) Start the Timeout mode.
      (+) Stop the Timeout mode.
      (+) Start the Counter mode.
      (+) Stop the Counter mode.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1210 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1274 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1249 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1319 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 879 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 966 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 938 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1032 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 549 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 613 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 586 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 669 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 383 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 447 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 420 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 503 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM in Set once mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 715 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 779 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 752 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 835 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1070 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function in interrupt mode.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1139 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1107 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1179 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Read operation functions

Functions
LPTIM Read operation functions
LPTIM Exported Functions

Read operation functions. More...

Functions

uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.

Detailed Description

Read operation functions.

  ==============================================================================
                  ##### LPTIM Read operation functions #####
  ==============================================================================
[..]  This section provides LPTIM Reading functions.
      (+) Read the counter value.
      (+) Read the period (Auto-reload) value.
      (+) Read the pulse (Compare)value.

Function Documentation

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

Return the current Autoreload (Period) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Autoreload value.

Definition at line 1380 of file stm32l4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

Return the current Compare (Pulse) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Compare value.

Definition at line 1393 of file stm32l4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

Return the current counter value.

Parameters:
hlptim,: LPTIM handle
Return values:
Counter value.

Definition at line 1367 of file stm32l4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM IRQ handler and callbacks

Functions
LPTIM IRQ handler and callbacks
LPTIM Exported Functions

LPTIM IRQ handler. More...

Functions

void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.

Detailed Description

LPTIM IRQ handler.

  ==============================================================================
                      ##### LPTIM IRQ handler and callbacks  #####
  ==============================================================================
[..]  This section provides LPTIM IRQ handler and callback functions called within
      the IRQ handler.

Function Documentation

__weak void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1540 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1585 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1525 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1570 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1615 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

__weak void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1600 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

Handle LPTIM interrupt request.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 1426 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, and LPTIM_IT_UP.

__weak void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1555 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
LPTIM Exported Functions

Peripheral State functions. More...

Functions

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Return the LPTIM handle state.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL state

Definition at line 1648 of file stm32l4xx_hal_lptim.c.

References LPTIM_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Exported Functions

Modules | Functions
LPTIM Exported Functions
LPTIM

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

LPTIM Start-Stop operation functions

Start-Stop operation functions.

LPTIM Read operation functions

Read operation functions.

LPTIM IRQ handler and callbacks

LPTIM IRQ handler.

Peripheral State functions

Peripheral State functions.

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.

Function Documentation

void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1540 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1585 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1525 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1570 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1210 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1274 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1249 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1319 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize the LPTIM peripheral.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 287 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, and LPTIM_HandleTypeDef::State.

void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1615 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1600 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 879 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 966 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 938 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1032 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and LPTIM_HandleTypeDef::State.

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Return the LPTIM handle state.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL state

Definition at line 1648 of file stm32l4xx_hal_lptim.c.

References LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.

Parameters:
hlptim,: LPTIM handle
Return values:
HAL status

Definition at line 174 of file stm32l4xx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, LPTIM_HandleTypeDef::Init, LPTIM_InitTypeDef::Input1Source, LPTIM_InitTypeDef::Input2Source, LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_INPUT1_SOURCE, IS_LPTIM_INPUT2_SOURCE, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

Handle LPTIM interrupt request.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 1426 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, and LPTIM_IT_UP.

void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 334 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit().

void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM MSP.

Parameters:
hlptim,: LPTIM handle
Return values:
None

Definition at line 319 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_Init().

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 549 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 613 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 586 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 669 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 383 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 447 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 420 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 503 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

Return the current Autoreload (Period) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Autoreload value.

Definition at line 1380 of file stm32l4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

Return the current Compare (Pulse) value.

Parameters:
hlptim,: LPTIM handle
Return values:
Compare value.

Definition at line 1393 of file stm32l4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

Return the current counter value.

Parameters:
hlptim,: LPTIM handle
Return values:
Counter value.

Definition at line 1367 of file stm32l4xx_hal_lptim.c.

References assert_param, and LPTIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM in Set once mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 715 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | : Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 779 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 752 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 835 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Init, LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1070 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function in interrupt mode.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | : LPTIM handle
Period | : Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | : Specifies the TimeOut value to rest the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1139 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1107 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, and LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function in interrupt mode.

Parameters:
hlptim : LPTIM handle
Return values:
HAL status

Definition at line 1179 of file stm32l4xx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and LPTIM_HandleTypeDef::State.

void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non-blocking mode.

Parameters:
hlptim : LPTIM handle
Return values:
None

Definition at line 1555 of file stm32l4xx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Exported Types

Data Structures | Typedefs | Enumerations
LPTIM Exported Types
LPTIM

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Typedefs

typedef enum
__HAL_LPTIM_StateTypeDef 		HAL_LPTIM_StateTypeDef
HAL LPTIM State structure definition.

Enumerations

enum __HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00, HAL_LPTIM_STATE_READY = 0x01, HAL_LPTIM_STATE_BUSY = 0x02, HAL_LPTIM_STATE_TIMEOUT = 0x03,
HAL_LPTIM_STATE_ERROR = 0x04
}
HAL LPTIM State structure definition. More...

Typedef Documentation

typedef enum __HAL_LPTIM_StateTypeDef HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumeration Type Documentation

enum __HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumerator:
HAL_LPTIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_LPTIM_STATE_READY

Peripheral Initialized and ready for use

HAL_LPTIM_STATE_BUSY

An internal process is ongoing

HAL_LPTIM_STATE_TIMEOUT

Timeout state

HAL_LPTIM_STATE_ERROR

Internal Process is ongoing

Definition at line 145 of file stm32l4xx_hal_lptim.h.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32l4xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | Prescaler

Detailed Description

LPTIM Clock configuration definition.

Definition at line 65 of file stm32l4xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ClockConfigTypeDef::Prescaler

Specifies the counter clock Prescaler. This parameter can be a value of LPTIM Clock Prescaler

Definition at line 70 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ClockConfigTypeDef::Source

Selects the clock source. This parameter can be a value of LPTIM Clock Source

Definition at line 67 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_lptim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM_ULPClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ULPClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32l4xx_hal_lptim.h>

Data Fields

uint32_t | Polarity
uint32_t | SampleTime

Detailed Description

LPTIM Clock configuration definition.

Definition at line 78 of file stm32l4xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ULPClockConfigTypeDef::Polarity

Selects the polarity of the active edge for the counter unit if the ULPTIM input is selected. Note: This parameter is used only when Ultra low power clock source is used. Note: If the polarity is configured on 'both edges', an auxiliary clock (one of the Low power oscillator) must be active. This parameter can be a value of LPTIM Clock Polarity

Definition at line 80 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ULPClockConfigTypeDef::SampleTime

Selects the clock sampling time to configure the clock glitch filter. Note: This parameter is used only when Ultra low power clock source is used. This parameter can be a value of LPTIM Clock Sample Time

Definition at line 87 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_lptim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM_TriggerConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_TriggerConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Trigger configuration definition. More...

#include <stm32l4xx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | ActiveEdge
uint32_t | SampleTime

Detailed Description

LPTIM Trigger configuration definition.

Definition at line 96 of file stm32l4xx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_TriggerConfigTypeDef::ActiveEdge

Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM External Trigger Polarity

Definition at line 101 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::SampleTime

Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM Trigger Sample Time

Definition at line 105 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::Source

Selects the Trigger source. This parameter can be a value of LPTIM Trigger Source

Definition at line 98 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_lptim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_InitTypeDef Struct Reference
LPTIM Exported Types

LPTIM Initialization Structure definition. More...

#include <stm32l4xx_hal_lptim.h>

Data Fields

LPTIM_ClockConfigTypeDef Clock
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock
LPTIM_TriggerConfigTypeDef Trigger
uint32_t | OutputPolarity
uint32_t | UpdateMode
uint32_t | CounterSource
uint32_t | Input1Source
uint32_t | Input2Source

Detailed Description

LPTIM Initialization Structure definition.

Definition at line 113 of file stm32l4xx_hal_lptim.h.

Field Documentation

LPTIM_ClockConfigTypeDef LPTIM_InitTypeDef::Clock

Specifies the clock parameters

Definition at line 115 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::CounterSource

Specifies whether the counter is incremented each internal event or each external event. This parameter can be a value of LPTIM Counter Source

Definition at line 128 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input1Source

Specifies source selected for input1 (GPIO or comparator output). This parameter can be a value of LPTIM Input1 Source

Definition at line 132 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input2Source

Specifies source selected for input2 (GPIO or comparator output). Note: This parameter is used only for encoder feature so is used only for LPTIM1 instance. This parameter can be a value of LPTIM Input2 Source

Definition at line 135 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::OutputPolarity

Specifies the Output polarity. This parameter can be a value of LPTIM Output Polarity

Definition at line 121 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

LPTIM_TriggerConfigTypeDef LPTIM_InitTypeDef::Trigger

Specifies the Trigger parameters

Definition at line 119 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_ULPClockConfigTypeDef LPTIM_InitTypeDef::UltraLowPowerClock

Specifies the Ultra Low Power clock parameters

Definition at line 117 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::UpdateMode

Specifies whether the update of the autoreload and the compare values is done immediately or after the end of current period. This parameter can be a value of LPTIM Updating Mode

Definition at line 124 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_lptim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_HandleTypeDef Struct Reference
LPTIM Exported Types

LPTIM handle Structure definition. More...

#include <stm32l4xx_hal_lptim.h>

Data Fields

LPTIM_TypeDef * | Instance
LPTIM_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_LPTIM_StateTypeDef | State

Detailed Description

LPTIM handle Structure definition.

Definition at line 157 of file stm32l4xx_hal_lptim.h.

Field Documentation

LPTIM_InitTypeDef LPTIM_HandleTypeDef::Init

LPTIM required parameters

Definition at line 161 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_TypeDef* LPTIM_HandleTypeDef::Instance

Register base address

Definition at line 159 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

HAL_LockTypeDef LPTIM_HandleTypeDef::Lock

LPTIM locking object

Definition at line 165 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

__IO HAL_LPTIM_StateTypeDef LPTIM_HandleTypeDef::State

LPTIM peripheral state

Definition at line 167 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_GetState(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

HAL_StatusTypeDef LPTIM_HandleTypeDef::Status

LPTIM peripheral status

Definition at line 163 of file stm32l4xx_hal_lptim.h.

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_lptim.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Clock Source

Defines
LPTIM Clock Source
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Define Documentation

#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)

Definition at line 183 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Definition at line 184 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

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STM32L486xx HAL User Manual: LPTIM Clock Prescaler

Defines
LPTIM Clock Prescaler
LPTIM Exported Constants

Defines

#define | LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)

Define Documentation

#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)

Definition at line 192 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)

Definition at line 199 of file stm32l4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Definition at line 196 of file stm32l4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Definition at line 193 of file stm32l4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))

Definition at line 197 of file stm32l4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Definition at line 194 of file stm32l4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))

Definition at line 198 of file stm32l4xx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))

Definition at line 195 of file stm32l4xx_hal_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Output Polarity

Defines
LPTIM Output Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)
#define | LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)

Define Documentation

#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)

Definition at line 208 of file stm32l4xx_hal_lptim.h.

#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)

Definition at line 209 of file stm32l4xx_hal_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Clock Sample Time

Defines
LPTIM Clock Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Define Documentation

#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0

Definition at line 218 of file stm32l4xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1

Definition at line 219 of file stm32l4xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Definition at line 220 of file stm32l4xx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)

Definition at line 217 of file stm32l4xx_hal_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Clock Polarity

Defines
LPTIM Clock Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0

Definition at line 229 of file stm32l4xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)

Definition at line 228 of file stm32l4xx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Definition at line 230 of file stm32l4xx_hal_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Trigger Source

Defines
LPTIM Trigger Source
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)
#define | LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)
#define | LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL

Define Documentation

#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)

Definition at line 239 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)

Definition at line 240 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1

Definition at line 241 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)

Definition at line 242 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2

Definition at line 243 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 244 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 245 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL

Definition at line 246 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)

Definition at line 238 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

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STM32L486xx HAL User Manual: LPTIM External Trigger Polarity

Defines
LPTIM External Trigger Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1

Definition at line 255 of file stm32l4xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0

Definition at line 254 of file stm32l4xx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Definition at line 256 of file stm32l4xx_hal_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Trigger Sample Time

Defines
LPTIM Trigger Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Define Documentation

#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0

Definition at line 265 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1

Definition at line 266 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Definition at line 267 of file stm32l4xx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)

Definition at line 264 of file stm32l4xx_hal_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Updating Mode

Defines
LPTIM Updating Mode
LPTIM Exported Constants

Defines

#define | LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Definition at line 277 of file stm32l4xx_hal_lptim.h.

#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)

Definition at line 276 of file stm32l4xx_hal_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Counter Source

Defines
LPTIM Counter Source
LPTIM Exported Constants

Defines

#define | LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Definition at line 287 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)

Definition at line 286 of file stm32l4xx_hal_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Input1 Source

Defines
LPTIM Input1 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT1SOURCE_GPIO ((uint32_t)0x00000000)
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0
#define | LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1
#define | LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR

Define Documentation

#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0

For LPTIM1 and LPTIM2

Definition at line 297 of file stm32l4xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR

For LPTIM2

Definition at line 299 of file stm32l4xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1

For LPTIM2

Definition at line 298 of file stm32l4xx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_GPIO ((uint32_t)0x00000000)

For LPTIM1 and LPTIM2

Definition at line 296 of file stm32l4xx_hal_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Input2 Source

Defines
LPTIM Input2 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT2SOURCE_GPIO ((uint32_t)0x00000000)
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1

Define Documentation

#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1

For LPTIM1

Definition at line 309 of file stm32l4xx_hal_lptim.h.

#define LPTIM_INPUT2SOURCE_GPIO ((uint32_t)0x00000000)

For LPTIM1

Definition at line 308 of file stm32l4xx_hal_lptim.h.

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STM32L486xx HAL User Manual: LPTIM Flags Definition

Defines
LPTIM Flags Definition
LPTIM Exported Constants

Defines

#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Define Documentation

#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM

Definition at line 323 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK

Definition at line 320 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Definition at line 324 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK

Definition at line 321 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN

Definition at line 318 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG

Definition at line 322 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_UP LPTIM_ISR_UP

Definition at line 319 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

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STM32L486xx HAL User Manual: LPTIM Interrupts Definition

Defines
LPTIM Interrupts Definition
LPTIM Exported Constants

Defines

#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Define Documentation

#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE

Definition at line 338 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE

Definition at line 335 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Definition at line 339 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE

Definition at line 336 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE

Definition at line 333 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE

Definition at line 337 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_UP LPTIM_IER_UPIE

Definition at line 334 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

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STM32L486xx HAL User Manual: LPTIM Exported Macros

Defines
LPTIM Exported Macros
LPTIM

Defines

#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous or in single mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified LPTIM interrupt source is enabled or not.

Define Documentation

#define __HAL_LPTIM_AUTORELOAD_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->ARR = (__VALUE__))

Write the passed parameter in the Autoreload register.

Parameters:
__HANDLE__,: LPTIM handle
__VALUE__,: Autoreload value
Return values:
None

Definition at line 388 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified LPTIM flag.

Parameters:
__HANDLE__,: LPTIM handle.
__FLAG__,: LPTIM flag to clear. This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
None

Definition at line 428 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_COMPARE_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->CMP = (__VALUE__))

Write the passed parameter in the Compare register.

Parameters:
__HANDLE__,: LPTIM handle
__VALUE__,: Compare value
Return values:
None

Definition at line 396 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))

Disable the LPTIM peripheral.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 371 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified LPTIM interrupt.

Parameters:
__HANDLE__,: LPTIM handle.
__INTERRUPT__,: LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None

Definition at line 460 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))

Enable the LPTIM peripheral.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 364 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified LPTIM interrupt.

Parameters:
__HANDLE__,: LPTIM handle.
__INTERRUPT__,: LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None

Definition at line 444 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))

Check whether the specified LPTIM flag is set or not.

Parameters:
__HANDLE__,: LPTIM handle
__FLAG__,: LPTIM flag to check This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
The state of the specified flag (SET or RESET).

Definition at line 412 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified LPTIM interrupt source is enabled or not.

Parameters:
__HANDLE__,: LPTIM handle.
__INTERRUPT__,: LPTIM interrupt to check. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
Interrupt status.

Definition at line 477 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)

Reset LPTIM handle state.

Parameters:
__HANDLE__,: LPTIM handle
Return values:
None

Definition at line 357 of file stm32l4xx_hal_lptim.h.

#define __HAL_LPTIM_START_CONTINUOUS ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)

Start the LPTIM peripheral in Continuous or in single mode.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 378 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_START_SINGLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)

Definition at line 379 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_SetOnce_Start(), and HAL_LPTIM_SetOnce_Start_IT().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Private Types

LPTIM Private Types
LPTIM
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Private Variables

LPTIM Private Variables
LPTIM
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Private Constants

LPTIM Private Constants
LPTIM
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
#define | IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFF)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Define Documentation

#define IS_LPTIM_AUTORELOAD ( __AUTORELOAD__ ) ((__AUTORELOAD__) <= 0x0000FFFF)

Definition at line 653 of file stm32l4xx_hal_lptim.h.

#define IS_LPTIM_CLOCK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))

Definition at line 624 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))

Definition at line 605 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALERDIV1 ( __PRESCALER__ ) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)

Definition at line 614 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define IS_LPTIM_CLOCK_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))

Definition at line 619 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))

Definition at line 601 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_COMPARE ( __COMPARE__ ) ((__COMPARE__) <= 0x0000FFFF)

Definition at line 655 of file stm32l4xx_hal_lptim.h.

#define IS_LPTIM_COUNTER_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))

Definition at line 650 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_EXT_TRG_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))

Definition at line 638 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT1_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
((((__INSTANCE__) == LPTIM1) &&                       \
     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))        \
     ||                                                   \
     (((__INSTANCE__) == LPTIM2) &&                       \
     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||       \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||       \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))

Definition at line 661 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT2_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
(((__INSTANCE__) == LPTIM1) &&                       \
     (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))

Definition at line 672 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))

Definition at line 616 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_PERIOD ( __PERIOD__ ) ((__PERIOD__) <= 0x0000FFFF)

Definition at line 657 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_PULSE ( __PULSE__ ) ((__PULSE__) <= 0x0000FFFF)

Definition at line 659 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_TRG_SOURCE ( __TRIG__ )
Value:
(((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))

Definition at line 628 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_TRIG_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))

Definition at line 642 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_UPDATE_MODE ( __MODE__ )
Value:
(((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))

Definition at line 647 of file stm32l4xx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Private Functions

LPTIM Private Functions
LPTIM
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NAND Private Constants

Defines
NAND Private Constants
NAND

Defines

#define | NAND_DEVICE FMC_BANK3
#define | NAND_WRITE_TIMEOUT ((uint32_t)1000)
#define | CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define | ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
#define | NAND_CMD_AREA_A ((uint8_t)0x00)
#define | NAND_CMD_AREA_B ((uint8_t)0x01)
#define | NAND_CMD_AREA_C ((uint8_t)0x50)
#define | NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define | NAND_CMD_READID ((uint8_t)0x90)
#define | NAND_CMD_STATUS ((uint8_t)0x70)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define | NAND_CMD_RESET ((uint8_t)0xFF)
#define | NAND_VALID_ADDRESS ((uint32_t)0x00000100)
#define | NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
#define | NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
#define | NAND_BUSY ((uint32_t)0x00000000)
#define | NAND_ERROR ((uint32_t)0x00000001)
#define | NAND_READY ((uint32_t)0x00000040)

Define Documentation

#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */

Definition at line 67 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */

Definition at line 66 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Read_Status(), HAL_NAND_Reset(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define NAND_BUSY ((uint32_t)0x00000000)

Definition at line 87 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_CMD_AREA_A ((uint8_t)0x00)

Definition at line 69 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page(), and HAL_NAND_Write_Page().

#define NAND_CMD_AREA_B ((uint8_t)0x01)

Definition at line 70 of file stm32l4xx_hal_nand.h.

#define NAND_CMD_AREA_C ((uint8_t)0x50)

Definition at line 71 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea(), and HAL_NAND_Write_SpareArea().

#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)

Definition at line 72 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page(), and HAL_NAND_Read_SpareArea().

#define NAND_CMD_ERASE0 ((uint8_t)0x60)

Definition at line 76 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block().

#define NAND_CMD_ERASE1 ((uint8_t)0xD0)

Definition at line 77 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block().

#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)

Definition at line 80 of file stm32l4xx_hal_nand.h.

#define NAND_CMD_READID ((uint8_t)0x90)

Definition at line 78 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

#define NAND_CMD_RESET ((uint8_t)0xFF)

Definition at line 81 of file stm32l4xx_hal_nand.h.

#define NAND_CMD_STATUS ((uint8_t)0x70)

Definition at line 79 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_CMD_WRITE0 ((uint8_t)0x80)

Definition at line 74 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)

Definition at line 75 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define NAND_DEVICE FMC_BANK3

Definition at line 63 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Read_Status(), HAL_NAND_Reset(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define NAND_ERROR ((uint32_t)0x00000001)

Definition at line 88 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_Status().

#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)

Definition at line 85 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), and NAND_AddressIncrement().

#define NAND_READY ((uint32_t)0x00000040)

Definition at line 89 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_Status(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)

Definition at line 86 of file stm32l4xx_hal_nand.h.

#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)

Definition at line 84 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), HAL_NAND_Write_SpareArea(), and NAND_AddressIncrement().

#define NAND_WRITE_TIMEOUT ((uint32_t)1000)

Definition at line 64 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NAND Private Macros

Defines
NAND Private Macros
NAND

Defines

#define | ARRAY_ADDRESS(__ADDRESS__, __HANDLE__)
NAND memory address computation.
#define | ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
NAND memory address cycling.
#define | ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define | ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define | ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */

Define Documentation

#define ADDR_1ST_CYCLE ( __ADDRESS__ ) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */

NAND memory address cycling.

Parameters:
__ADDRESS__,: NAND memory address.
Return values:
NAND address cycling value.

Definition at line 113 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define ADDR_2ND_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */

Definition at line 114 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define ADDR_3RD_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */

Definition at line 115 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define ADDR_4TH_CYCLE ( __ADDRESS__ ) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */

Definition at line 116 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

#define ARRAY_ADDRESS | ( | __ADDRESS__,
 |  | __HANDLE__
 | ) |
Value:
(((__ADDRESS__)->Page) + \
                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))

NAND memory address computation.

Parameters:
__ADDRESS__,: NAND memory address.
__HANDLE__,: NAND handle.
Return values:
NAND Raw address value

Definition at line 105 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NAND Private Functions

Functions
NAND Private Functions
NAND

Functions

static uint32_t NAND_AddressIncrement (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *Address)
Increment the NAND memory address.

Function Documentation

static uint32_t NAND_AddressIncrement | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | Address
 | ) |  | [static]

Increment the NAND memory address.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Address,: address to be incremented.
Return values:
The new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

Definition at line 1088 of file stm32l4xx_hal_nand.c.

References NAND_AddressTypeDef::Block, NAND_InfoTypeDef::BlockNbr, NAND_InfoTypeDef::BlockSize, NAND_HandleTypeDef::Info, NAND_INVALID_ADDRESS, NAND_VALID_ADDRESS, NAND_AddressTypeDef::Page, NAND_AddressTypeDef::Zone, and NAND_InfoTypeDef::ZoneSize.

Referenced by HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
NAND Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
Initialize the NAND MSP.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
DeInitialize the NAND MSP.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
            ##### NAND Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the NAND memory

Function Documentation

HAL_StatusTypeDef HAL_NAND_DeInit ( NAND_HandleTypeDef * hnand )

Perform NAND memory De-Initialization sequence.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 200 of file stm32l4xx_hal_nand.c.

References HAL_NAND_MspDeInit(), HAL_NAND_STATE_RESET, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Init | ( | NAND_HandleTypeDef * | hnand,
 |  | FMC_NAND_PCC_TimingTypeDef * | ComSpace_Timing,
 |  | FMC_NAND_PCC_TimingTypeDef * | AttSpace_Timing
 | ) |  |

Perform NAND memory Initialization sequence.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
ComSpace_Timing,: pointer to Common space timing structure
AttSpace_Timing,: pointer to Attribute space timing structure
Return values:
HAL status

Definition at line 159 of file stm32l4xx_hal_nand.c.

References HAL_NAND_MspInit(), HAL_NAND_STATE_READY, HAL_NAND_STATE_RESET, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, NAND_HandleTypeDef::Lock, and NAND_HandleTypeDef::State.

void HAL_NAND_IRQHandler ( NAND_HandleTypeDef * hnand )

This function handles NAND device interrupt request.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 256 of file stm32l4xx_hal_nand.c.

References HAL_NAND_ITCallback(), NAND_HandleTypeDef::Init, and NAND_HandleTypeDef::Instance.

void HAL_NAND_ITCallback ( NAND_HandleTypeDef * hnand )

NAND interrupt feature callback.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 305 of file stm32l4xx_hal_nand.c.

Referenced by HAL_NAND_IRQHandler().

void HAL_NAND_MspDeInit ( NAND_HandleTypeDef * hnand )

DeInitialize the NAND MSP.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 239 of file stm32l4xx_hal_nand.c.

Referenced by HAL_NAND_DeInit().

void HAL_NAND_MspInit ( NAND_HandleTypeDef * hnand )

Initialize the NAND MSP.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
None

Definition at line 223 of file stm32l4xx_hal_nand.c.

Referenced by HAL_NAND_Init().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output functions

Functions
Input and Output functions
NAND Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_Read_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Write_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory.
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory.
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                    ##### NAND Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the NAND
    memory

Function Documentation

uint32_t HAL_NAND_Address_Inc | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress
 | ) |  |

Increment the NAND memory address.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress,: pointer to NAND address structure
Return values:
The new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

Definition at line 906 of file stm32l4xx_hal_nand.c.

References NAND_AddressTypeDef::Block, NAND_InfoTypeDef::BlockNbr, NAND_InfoTypeDef::BlockSize, NAND_HandleTypeDef::Info, NAND_INVALID_ADDRESS, NAND_VALID_ADDRESS, NAND_AddressTypeDef::Page, NAND_AddressTypeDef::Zone, and NAND_InfoTypeDef::ZoneSize.

HAL_StatusTypeDef HAL_NAND_Erase_Block | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress
 | ) |  |

NAND memory Block erase.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress,: pointer to NAND address structure
Return values:
HAL status

Definition at line 802 of file stm32l4xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_InfoTypeDef::BlockNbr, CMD_AREA, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Info, NAND_CMD_ERASE0, NAND_CMD_ERASE1, NAND_DEVICE, NAND_READY, NAND_WRITE_TIMEOUT, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Read_ID | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_IDTypeDef * | pNAND_ID
 | ) |  |

Read the NAND memory electronic signature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pNAND_ID,: NAND ID structure
Return values:
HAL status

Definition at line 341 of file stm32l4xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, CMD_AREA, NAND_IDTypeDef::Device_Id, NAND_IDTypeDef::Fourth_Id, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_IDTypeDef::Maker_Id, NAND_CMD_READID, NAND_DEVICE, NAND_HandleTypeDef::State, and NAND_IDTypeDef::Third_Id.

HAL_StatusTypeDef HAL_NAND_Read_Page | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumPageToRead
 | ) |  |

Read Page(s) from NAND memory block.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress,: pointer to NAND address structure
pBuffer,: pointer to destination read buffer
NumPageToRead,: number of pages to read from block
Return values:
HAL status

Definition at line 431 of file stm32l4xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_AddressTypeDef::Block, NAND_InfoTypeDef::BlockNbr, CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Info, NAND_AddressIncrement(), NAND_CMD_AREA_A, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_VALID_ADDRESS, NAND_AddressTypeDef::Page, NAND_InfoTypeDef::PageSize, NAND_HandleTypeDef::State, and NAND_AddressTypeDef::Zone.

HAL_StatusTypeDef HAL_NAND_Read_SpareArea | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumSpareAreaToRead
 | ) |  |

Read Spare area(s) from NAND memory.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress,: pointer to NAND address structure
pBuffer,: pointer to source buffer to write
NumSpareAreaToRead,: Number of spare area to read
Return values:
HAL status

Definition at line 618 of file stm32l4xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_AddressTypeDef::Block, NAND_InfoTypeDef::BlockNbr, CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Info, NAND_AddressIncrement(), NAND_CMD_AREA_C, NAND_CMD_AREA_TRUE1, NAND_DEVICE, NAND_VALID_ADDRESS, NAND_AddressTypeDef::Page, NAND_InfoTypeDef::SpareAreaSize, NAND_HandleTypeDef::State, and NAND_AddressTypeDef::Zone.

uint32_t HAL_NAND_Read_Status ( NAND_HandleTypeDef * hnand )

NAND memory read status.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
NAND status

Definition at line 867 of file stm32l4xx_hal_nand.c.

References CMD_AREA, NAND_BUSY, NAND_CMD_STATUS, NAND_DEVICE, NAND_ERROR, and NAND_READY.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

HAL_StatusTypeDef HAL_NAND_Reset ( NAND_HandleTypeDef * hnand )

NAND memory reset.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 389 of file stm32l4xx_hal_nand.c.

References CMD_AREA, HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_DEVICE, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_Write_Page | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumPageToWrite
 | ) |  |

Write Page(s) to NAND memory block.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress,: pointer to NAND address structure
pBuffer,: pointer to source buffer to write
NumPageToWrite,: number of pages to write to block
Return values:
HAL status

Definition at line 518 of file stm32l4xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_AddressTypeDef::Block, NAND_InfoTypeDef::BlockNbr, CMD_AREA, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Info, NAND_AddressIncrement(), NAND_CMD_AREA_A, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_VALID_ADDRESS, NAND_WRITE_TIMEOUT, NAND_AddressTypeDef::Page, NAND_InfoTypeDef::PageSize, NAND_HandleTypeDef::State, and NAND_AddressTypeDef::Zone.

HAL_StatusTypeDef HAL_NAND_Write_SpareArea | ( | NAND_HandleTypeDef * | hnand,
 |  | NAND_AddressTypeDef * | pAddress,
 |  | uint8_t * | pBuffer,
 |  | uint32_t | NumSpareAreaTowrite
 | ) |  |

Write Spare area(s) to NAND memory.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddress,: pointer to NAND address structure
pBuffer,: pointer to source buffer to write
NumSpareAreaTowrite,: number of spare areas to write to block
Return values:
HAL status

Definition at line 704 of file stm32l4xx_hal_nand.c.

References ADDR_1ST_CYCLE, ADDR_2ND_CYCLE, ADDR_3RD_CYCLE, ADDR_4TH_CYCLE, ADDR_AREA, ARRAY_ADDRESS, NAND_AddressTypeDef::Block, NAND_InfoTypeDef::BlockNbr, CMD_AREA, HAL_GetTick(), HAL_NAND_Read_Status(), HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Info, NAND_AddressIncrement(), NAND_CMD_AREA_C, NAND_CMD_WRITE0, NAND_CMD_WRITE_TRUE1, NAND_DEVICE, NAND_READY, NAND_VALID_ADDRESS, NAND_WRITE_TIMEOUT, NAND_AddressTypeDef::Page, NAND_InfoTypeDef::SpareAreaSize, NAND_HandleTypeDef::State, and NAND_AddressTypeDef::Zone.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
NAND Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enable dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disable dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disable dynamically NAND ECC feature.

Detailed Description

management functions

  ==============================================================================
                         ##### NAND Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the NAND interface.

Function Documentation

HAL_StatusTypeDef HAL_NAND_ECC_Disable ( NAND_HandleTypeDef * hnand )

Disable dynamically NAND ECC feature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 985 of file stm32l4xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_ECC_Enable ( NAND_HandleTypeDef * hnand )

Enable dynamically NAND ECC feature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL status

Definition at line 959 of file stm32l4xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NAND_GetECC | ( | NAND_HandleTypeDef * | hnand,
 |  | uint32_t * | ECCval,
 |  | uint32_t | Timeout
 | ) |  |

Disable dynamically NAND ECC feature.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
ECCval,: pointer to ECC value
Timeout,: maximum timeout to wait
Return values:
HAL status

Definition at line 1013 of file stm32l4xx_hal_nand.c.

References HAL_NAND_STATE_BUSY, HAL_NAND_STATE_READY, NAND_HandleTypeDef::Init, NAND_HandleTypeDef::Instance, and NAND_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
NAND Exported Functions

Peripheral State functions. More...

Functions

HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
Return the NAND handle state.
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.

Detailed Description

Peripheral State functions.

  ==============================================================================
                         ##### NAND State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the NAND controller
    and the data flow.

Function Documentation

HAL_NAND_StateTypeDef HAL_NAND_GetState ( NAND_HandleTypeDef * hnand )

Return the NAND handle state.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
HAL state

Definition at line 1061 of file stm32l4xx_hal_nand.c.

References NAND_HandleTypeDef::State.

uint32_t HAL_NAND_Read_Status ( NAND_HandleTypeDef * hnand )

NAND memory read status.

Parameters:
hnand,: pointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values:
NAND status

Definition at line 867 of file stm32l4xx_hal_nand.c.

References CMD_AREA, NAND_BUSY, NAND_CMD_STATUS, NAND_DEVICE, NAND_ERROR, and NAND_READY.

Referenced by HAL_NAND_Erase_Block(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NAND Exported Types

Data Structures | Enumerations
NAND Exported Types
NAND

Data Structures

struct | NAND_IDTypeDef
NAND Memory electronic signature Structure definition. More...
struct | NAND_AddressTypeDef
NAND Memory address Structure definition. More...
struct | NAND_InfoTypeDef
NAND Memory info Structure definition. More...
struct | NAND_HandleTypeDef
NAND handle Structure definition. More...

Enumerations

enum | HAL_NAND_StateTypeDef { HAL_NAND_STATE_RESET = 0x00, HAL_NAND_STATE_READY = 0x01, HAL_NAND_STATE_BUSY = 0x02, HAL_NAND_STATE_ERROR = 0x03 }
HAL NAND State structures definition. More...

Enumeration Type Documentation

enum HAL_NAND_StateTypeDef

HAL NAND State structures definition.

Enumerator:
HAL_NAND_STATE_RESET

NAND not yet initialized or disabled

HAL_NAND_STATE_READY

NAND initialized and ready for use

HAL_NAND_STATE_BUSY

NAND internal process is ongoing

HAL_NAND_STATE_ERROR

NAND error state

Definition at line 131 of file stm32l4xx_hal_nand.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NAND_IDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_IDTypeDef Struct Reference
NAND Exported Types

NAND Memory electronic signature Structure definition. More...

#include <stm32l4xx_hal_nand.h>

Data Fields

uint8_t | Maker_Id
uint8_t | Device_Id
uint8_t | Third_Id
uint8_t | Fourth_Id

Detailed Description

NAND Memory electronic signature Structure definition.

Definition at line 142 of file stm32l4xx_hal_nand.h.

Field Documentation

uint8_t NAND_IDTypeDef::Device_Id

Definition at line 148 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Fourth_Id

Definition at line 152 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Maker_Id

Definition at line 146 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

uint8_t NAND_IDTypeDef::Third_Id

Definition at line 150 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_ID().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_nand.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NAND_AddressTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_AddressTypeDef Struct Reference
NAND Exported Types

NAND Memory address Structure definition. More...

#include <stm32l4xx_hal_nand.h>

Data Fields

uint16_t | Page
uint16_t | Zone
uint16_t | Block

Detailed Description

NAND Memory address Structure definition.

Definition at line 158 of file stm32l4xx_hal_nand.h.

Field Documentation

uint16_t NAND_AddressTypeDef::Block

NAND memory Block address

Definition at line 164 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), HAL_NAND_Write_SpareArea(), and NAND_AddressIncrement().

uint16_t NAND_AddressTypeDef::Page

NAND memory Page address

Definition at line 160 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), HAL_NAND_Write_SpareArea(), and NAND_AddressIncrement().

uint16_t NAND_AddressTypeDef::Zone

NAND memory Zone address

Definition at line 162 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), HAL_NAND_Write_SpareArea(), and NAND_AddressIncrement().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_nand.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NAND_InfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_InfoTypeDef Struct Reference
NAND Exported Types

NAND Memory info Structure definition. More...

#include <stm32l4xx_hal_nand.h>

Data Fields

uint32_t | PageSize
uint32_t | SpareAreaSize
uint32_t | BlockSize
uint32_t | BlockNbr
uint32_t | ZoneSize

Detailed Description

NAND Memory info Structure definition.

Definition at line 171 of file stm32l4xx_hal_nand.h.

Field Documentation

uint32_t NAND_InfoTypeDef::BlockNbr

NAND memory number of blocks

Definition at line 179 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_Erase_Block(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), HAL_NAND_Write_SpareArea(), and NAND_AddressIncrement().

uint32_t NAND_InfoTypeDef::BlockSize

NAND memory block size number of pages

Definition at line 177 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), and NAND_AddressIncrement().

uint32_t NAND_InfoTypeDef::PageSize

NAND memory page (without spare area) size measured in K. bytes

Definition at line 173 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_Page(), and HAL_NAND_Write_Page().

uint32_t NAND_InfoTypeDef::SpareAreaSize

NAND memory spare area size measured in K. bytes

Definition at line 175 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Read_SpareArea(), and HAL_NAND_Write_SpareArea().

uint32_t NAND_InfoTypeDef::ZoneSize

NAND memory zone size measured in number of blocks

Definition at line 181 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), and NAND_AddressIncrement().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_nand.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NAND_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NAND_HandleTypeDef Struct Reference
NAND Exported Types

NAND handle Structure definition. More...

#include <stm32l4xx_hal_nand.h>

Data Fields

FMC_NAND_TypeDef * | Instance
FMC_NAND_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_NAND_StateTypeDef | State
NAND_InfoTypeDef Info

Detailed Description

NAND handle Structure definition.

Definition at line 187 of file stm32l4xx_hal_nand.h.

Field Documentation

NAND_InfoTypeDef NAND_HandleTypeDef::Info

NAND characteristic information structure

Definition at line 197 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Address_Inc(), HAL_NAND_Erase_Block(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page(), HAL_NAND_Write_SpareArea(), and NAND_AddressIncrement().

FMC_NAND_InitTypeDef NAND_HandleTypeDef::Init

NAND device control configuration parameters

Definition at line 191 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_GetECC(), HAL_NAND_Init(), and HAL_NAND_IRQHandler().

FMC_NAND_TypeDef* NAND_HandleTypeDef::Instance

Register base address

Definition at line 189 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_GetECC(), HAL_NAND_Init(), and HAL_NAND_IRQHandler().

HAL_LockTypeDef NAND_HandleTypeDef::Lock

NAND locking object

Definition at line 193 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_Init().

__IO HAL_NAND_StateTypeDef NAND_HandleTypeDef::State

NAND device access state

Definition at line 195 of file stm32l4xx_hal_nand.h.

Referenced by HAL_NAND_DeInit(), HAL_NAND_ECC_Disable(), HAL_NAND_ECC_Enable(), HAL_NAND_Erase_Block(), HAL_NAND_GetECC(), HAL_NAND_GetState(), HAL_NAND_Init(), HAL_NAND_Read_ID(), HAL_NAND_Read_Page(), HAL_NAND_Read_SpareArea(), HAL_NAND_Reset(), HAL_NAND_Write_Page(), and HAL_NAND_Write_SpareArea().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_nand.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NAND Exported Macros

Defines
NAND Exported Macros
NAND

Defines

#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
Reset NAND handle state.

Define Documentation

#define __HAL_NAND_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)

Reset NAND handle state.

Parameters:
__HANDLE__,: specifies the NAND handle.
Return values:
None

Definition at line 214 of file stm32l4xx_hal_nand.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NOR Private Constants

Defines
NOR Private Constants
NOR

Defines

#define | NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define | NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
#define | NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define | NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define | NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define | NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define | NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define | NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define | NOR_CMD_DATA_CFI (uint16_t)0x0098
#define | NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define | NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define | NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define | NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define | NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
#define | MC_ADDRESS ((uint16_t)0x0000)
#define | DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define | DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define | DEVICE_CODE3_ADDR ((uint16_t)0x000F)
#define | CFI1_ADDRESS ((uint16_t)0x10)
#define | CFI2_ADDRESS ((uint16_t)0x11)
#define | CFI3_ADDRESS ((uint16_t)0x12)
#define | CFI4_ADDRESS ((uint16_t)0x13)
#define | NOR_MEMORY_8B ((uint8_t)0x0)
#define | NOR_MEMORY_16B ((uint8_t)0x1)
#define | NOR_MEMORY_ADRESS1 FMC_BANK1_1
#define | NOR_MEMORY_ADRESS2 FMC_BANK1_2
#define | NOR_MEMORY_ADRESS3 FMC_BANK1_3
#define | NOR_MEMORY_ADRESS4 FMC_BANK1_4

Define Documentation

#define CFI1_ADDRESS ((uint16_t)0x10)

Definition at line 71 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI2_ADDRESS ((uint16_t)0x11)

Definition at line 72 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI3_ADDRESS ((uint16_t)0x12)

Definition at line 73 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define CFI4_ADDRESS ((uint16_t)0x13)

Definition at line 74 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)

Definition at line 66 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)

Definition at line 67 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)

Definition at line 68 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define MC_ADDRESS ((uint16_t)0x0000)

Definition at line 65 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA

Definition at line 112 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555

Definition at line 107 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055

Definition at line 108 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Read_CFI().

#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555

Definition at line 111 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA

Definition at line 109 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555

Definition at line 113 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Chip().

#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555

Definition at line 110 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), and HAL_NOR_Read_ID().

#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090

Definition at line 119 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Read_ID().

#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30

Definition at line 129 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block().

#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25

Definition at line 127 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_ProgramBuffer().

#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29

Definition at line 128 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_ProgramBuffer().

#define NOR_CMD_DATA_CFI (uint16_t)0x0098

Definition at line 125 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Read_CFI().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055

Definition at line 123 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA

Definition at line 122 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080

Definition at line 121 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), and HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010

Definition at line 124 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Chip().

#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA

Definition at line 117 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0

Definition at line 120 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Program().

#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0

Definition at line 116 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Read(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_CMD_DATA_SECOND (uint16_t)0x0055

Definition at line 118 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020

Definition at line 132 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Definition at line 133 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

#define NOR_MEMORY_16B ((uint8_t)0x1)

Definition at line 78 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Init().

#define NOR_MEMORY_8B ((uint8_t)0x0)

Definition at line 77 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Init().

#define NOR_MEMORY_ADRESS1 FMC_BANK1_1

Definition at line 81 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS2 FMC_BANK1_2

Definition at line 82 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS3 FMC_BANK1_3

Definition at line 83 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

#define NOR_MEMORY_ADRESS4 FMC_BANK1_4

Definition at line 84 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NOR Private Macros

Defines
NOR Private Macros
NOR

Defines

#define | NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)
NOR memory address shifting.
#define | NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
NOR memory write data to specified address.

Define Documentation

#define NOR_ADDR_SHIFT | ( | __NOR_ADDRESS,
 |  | __NOR_MEMORY_WIDTH_,
 |  | __ADDRESS__
 | ) |
Value:
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
              ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))

NOR memory address shifting.

Parameters:
__NOR_ADDRESS,: NOR base address
__NOR_MEMORY_WIDTH_,: NOR memory width
__ADDRESS__,: NOR memory address
Return values:
NOR shifted address value

Definition at line 101 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

#define NOR_WRITE | ( | __ADDRESS__,
 |  | __DATA__
 | ) | (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))

NOR memory write data to specified address.

Parameters:
__ADDRESS__,: NOR memory address
__DATA__,: Data to write
Return values:
None

Definition at line 112 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), and HAL_NOR_ReturnToReadMode().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NOR Private Variables

Variables
NOR Private Variables
NOR

Variables

static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B

Variable Documentation

uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B [static]

Definition at line 154 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), and HAL_NOR_ReadBuffer().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
NOR Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
Initialize the NOR MSP.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
DeInitialize the NOR MSP.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### NOR Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize
    the NOR memory

Function Documentation

HAL_StatusTypeDef HAL_NOR_DeInit ( NOR_HandleTypeDef * hnor )

Perform NOR memory De-Initialization sequence.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 240 of file stm32l4xx_hal_nor.c.

References NOR_HandleTypeDef::Extended, HAL_NOR_MspDeInit(), HAL_NOR_STATE_RESET, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_Init | ( | NOR_HandleTypeDef * | hnor,
 |  | FMC_NORSRAM_TimingTypeDef * | Timing,
 |  | FMC_NORSRAM_TimingTypeDef * | ExtTiming
 | ) |  |

Perform the NOR memory Initialization sequence.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Timing,: pointer to NOR control timing structure
ExtTiming,: pointer to NOR extended mode timing structure
Return values:
HAL status

Definition at line 189 of file stm32l4xx_hal_nor.c.

References NOR_HandleTypeDef::Extended, HAL_NOR_MspInit(), HAL_NOR_STATE_READY, HAL_NOR_STATE_RESET, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, NOR_HandleTypeDef::Lock, NOR_MEMORY_16B, NOR_MEMORY_8B, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

void HAL_NOR_MspDeInit ( NOR_HandleTypeDef * hnor )

DeInitialize the NOR MSP.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
None

Definition at line 279 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_DeInit().

void HAL_NOR_MspInit ( NOR_HandleTypeDef * hnor )

Initialize the NOR MSP.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
None

Definition at line 263 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_Init().

void HAL_NOR_MspWait | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Timeout
 | ) |  |

NOR MSP Wait for Ready/Busy signal.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Timeout,: Maximum timeout value
Return values:
None

Definition at line 296 of file stm32l4xx_hal_nor.c.

Referenced by HAL_NOR_GetStatus().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output functions

Functions
Input and Output functions
NOR Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Return the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Read a block of data from the FMC NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Write a half-word buffer to the FMC NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                ##### NOR Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the NOR memory

Function Documentation

HAL_StatusTypeDef HAL_NOR_Erase_Block | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | BlockAddress,
 |  | uint32_t | Address
 | ) |  |

Erase the specified block of the NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
BlockAddress : Block to erase address
Address,: Device address
Return values:
HAL status

Definition at line 712 of file stm32l4xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIFTH, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_FOURTH, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_BLOCK_ERASE, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Erase_Chip | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Address
 | ) |  |

Erase the entire NOR chip.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Address : Device address
Return values:
HAL status

Definition at line 771 of file stm32l4xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIFTH, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_FOURTH, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_SIXTH, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH, NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD, NOR_CMD_DATA_CHIP_ERASE, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Program | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pData
 | ) |  |

Program data to NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pAddress,: Device address
pData : pointer to the data to write
Return values:
HAL status

Definition at line 501 of file stm32l4xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_PROGRAM, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_ProgramBuffer | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | uwAddress,
 |  | uint16_t * | pData,
 |  | uint32_t | uwBufferSize
 | ) |  |

Write a half-word buffer to the FMC NOR memory.

This function must be used only with S29GL128P NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
uwAddress,: NOR memory internal address from which the data
Note:
Some NOR memory need Address aligned to xx bytes (can be aligned to 64 bytes boundary for example).
Parameters:
pData,: pointer to source data buffer.
uwBufferSize,: number of Half words to write.
Note:
The maximum buffer size allowed is NOR memory dependent (can be 64 Bytes max for example).
Return values:
HAL status

Definition at line 632 of file stm32l4xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_DATA_BUFFER_AND_PROG, NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Read | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pData
 | ) |  |

Read data from NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pAddress,: pointer to Device address
pData : pointer to read data
Return values:
HAL status

Definition at line 442 of file stm32l4xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_READ_RESET, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Read_CFI | ( | NOR_HandleTypeDef * | hnor,
 |  | NOR_CFITypeDef * | pNOR_CFI
 | ) |  |

Read NOR flash CFI IDs.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pNOR_CFI : pointer to NOR CFI IDs structure
Return values:
HAL status

Definition at line 832 of file stm32l4xx_hal_nor.c.

References CFI1_ADDRESS, CFI2_ADDRESS, CFI3_ADDRESS, CFI4_ADDRESS, NOR_CFITypeDef::CFI_1, NOR_CFITypeDef::CFI_2, NOR_CFITypeDef::CFI_3, NOR_CFITypeDef::CFI_4, HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST_CFI, NOR_CMD_DATA_CFI, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_Read_ID | ( | NOR_HandleTypeDef * | hnor,
 |  | NOR_IDTypeDef * | pNOR_ID
 | ) |  |

Read NOR flash IDs.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pNOR_ID : pointer to NOR ID structure
Return values:
HAL status

Definition at line 332 of file stm32l4xx_hal_nor.c.

References NOR_IDTypeDef::Device_Code1, DEVICE_CODE1_ADDR, NOR_IDTypeDef::Device_Code2, DEVICE_CODE2_ADDR, NOR_IDTypeDef::Device_Code3, DEVICE_CODE3_ADDR, HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_IDTypeDef::Manufacturer_Code, MC_ADDRESS, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_ADDRESS_THIRD, NOR_CMD_DATA_AUTO_SELECT, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_ReadBuffer | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | uwAddress,
 |  | uint16_t * | pData,
 |  | uint32_t | uwBufferSize
 | ) |  |

Read a block of data from the FMC NOR memory.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
uwAddress,: NOR memory internal address to read from.
pData,: pointer to the buffer that receives the data read from the NOR memory.
uwBufferSize : number of Half word to read.
Return values:
HAL status

Definition at line 562 of file stm32l4xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_ADDR_SHIFT, NOR_CMD_ADDRESS_FIRST, NOR_CMD_ADDRESS_SECOND, NOR_CMD_DATA_FIRST, NOR_CMD_DATA_READ_RESET, NOR_CMD_DATA_SECOND, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, NOR_HandleTypeDef::State, and uwNORMemoryDataWidth.

HAL_StatusTypeDef HAL_NOR_ReturnToReadMode ( NOR_HandleTypeDef * hnor )

Return the NOR memory to Read mode.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 392 of file stm32l4xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_CMD_DATA_READ_RESET, NOR_MEMORY_ADRESS1, NOR_MEMORY_ADRESS2, NOR_MEMORY_ADRESS3, NOR_MEMORY_ADRESS4, NOR_WRITE, and NOR_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
NOR Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enable dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disable dynamically NOR write operation.

Detailed Description

management functions

  ==============================================================================
                        ##### NOR Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the NOR interface.

Function Documentation

HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable ( NOR_HandleTypeDef * hnor )

Disable dynamically NOR write operation.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 932 of file stm32l4xx_hal_nor.c.

References HAL_NOR_STATE_BUSY, HAL_NOR_STATE_PROTECTED, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, and NOR_HandleTypeDef::State.

HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable ( NOR_HandleTypeDef * hnor )

Enable dynamically NOR write operation.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
HAL status

Definition at line 909 of file stm32l4xx_hal_nor.c.

References HAL_NOR_STATE_READY, NOR_HandleTypeDef::Init, NOR_HandleTypeDef::Instance, and NOR_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
NOR Exported Functions

Peripheral State functions. More...

Functions

HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
Return the NOR controller handle state.
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Return the NOR operation status.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### NOR State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the NOR controller
    and the data flow.

Function Documentation

HAL_NOR_StateTypeDef HAL_NOR_GetState ( NOR_HandleTypeDef * hnor )

Return the NOR controller handle state.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Return values:
NOR controller state

Definition at line 977 of file stm32l4xx_hal_nor.c.

References NOR_HandleTypeDef::State.

HAL_NOR_StatusTypeDef HAL_NOR_GetStatus | ( | NOR_HandleTypeDef * | hnor,
 |  | uint32_t | Address,
 |  | uint32_t | Timeout
 | ) |  |

Return the NOR operation status.

Parameters:
hnor,: pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Address,: Device address
Timeout,: NOR programming Timeout
Return values:
NOR_Status,: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR or HAL_NOR_STATUS_TIMEOUT

Definition at line 992 of file stm32l4xx_hal_nor.c.

References HAL_GetTick(), HAL_NOR_MspWait(), HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_TIMEOUT, NOR_MASK_STATUS_DQ5, and NOR_MASK_STATUS_DQ6.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NOR Exported Types

Data Structures | Enumerations
NOR Exported Types
NOR

Data Structures

struct | NOR_IDTypeDef
FMC NOR ID typedef. More...
struct | NOR_CFITypeDef
FMC NOR CFI typedef. More...
struct | NOR_HandleTypeDef
NOR handle Structure definition. More...

Enumerations

enum HAL_NOR_StateTypeDef {
HAL_NOR_STATE_RESET = 0x00, HAL_NOR_STATE_READY = 0x01, HAL_NOR_STATE_BUSY = 0x02, HAL_NOR_STATE_ERROR = 0x03,
HAL_NOR_STATE_PROTECTED = 0x04
}
HAL SRAM State structures definition. More...
enum | HAL_NOR_StatusTypeDef { HAL_NOR_STATUS_SUCCESS = 0, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT }
FMC NOR Status typedef. More...

Enumeration Type Documentation

enum HAL_NOR_StateTypeDef

HAL SRAM State structures definition.

Enumerator:
HAL_NOR_STATE_RESET

NOR not yet initialized or disabled

HAL_NOR_STATE_READY

NOR initialized and ready for use

HAL_NOR_STATE_BUSY

NOR internal processing is ongoing

HAL_NOR_STATE_ERROR

NOR error state

HAL_NOR_STATE_PROTECTED

NOR NORSRAM device write protected

Definition at line 126 of file stm32l4xx_hal_nor.h.

enum HAL_NOR_StatusTypeDef

FMC NOR Status typedef.

Enumerator:
HAL_NOR_STATUS_SUCCESS
HAL_NOR_STATUS_ONGOING
HAL_NOR_STATUS_ERROR
HAL_NOR_STATUS_TIMEOUT

Definition at line 138 of file stm32l4xx_hal_nor.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NOR_IDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_IDTypeDef Struct Reference
NOR Exported Types

FMC NOR ID typedef. More...

#include <stm32l4xx_hal_nor.h>

Data Fields

uint16_t | Manufacturer_Code
uint16_t | Device_Code1
uint16_t | Device_Code2
uint16_t | Device_Code3

Detailed Description

FMC NOR ID typedef.

Definition at line 149 of file stm32l4xx_hal_nor.h.

Field Documentation

uint16_t NOR_IDTypeDef::Device_Code1

Definition at line 153 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Device_Code2

Definition at line 155 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Device_Code3

Defines the device's codes used to identify the memory. These codes can be accessed by performing read operations with specific control signals and addresses set.They can also be accessed by issuing an Auto Select command.

Definition at line 157 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

uint16_t NOR_IDTypeDef::Manufacturer_Code

Defines the device's manufacturer code used to identify the memory

Definition at line 151 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_ID().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_nor.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NOR_CFITypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_CFITypeDef Struct Reference
NOR Exported Types

FMC NOR CFI typedef. More...

#include <stm32l4xx_hal_nor.h>

Data Fields

uint16_t | CFI_1
uint16_t | CFI_2
uint16_t | CFI_3
uint16_t | CFI_4

Detailed Description

FMC NOR CFI typedef.

Definition at line 166 of file stm32l4xx_hal_nor.h.

Field Documentation

uint16_t NOR_CFITypeDef::CFI_1

Definition at line 168 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_2

Definition at line 170 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_3

Definition at line 172 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

uint16_t NOR_CFITypeDef::CFI_4

Defines the information stored in the memory's Common flash interface which contains a description of various electrical and timing parameters, density information and functions supported by the memory.

Definition at line 174 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Read_CFI().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_nor.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NOR_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
NOR_HandleTypeDef Struct Reference
NOR Exported Types

NOR handle Structure definition. More...

#include <stm32l4xx_hal_nor.h>

Data Fields

FMC_NORSRAM_TypeDef * | Instance
FMC_NORSRAM_EXTENDED_TypeDef * | Extended
FMC_NORSRAM_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_NOR_StateTypeDef | State

Detailed Description

NOR handle Structure definition.

Definition at line 182 of file stm32l4xx_hal_nor.h.

Field Documentation

FMC_NORSRAM_EXTENDED_TypeDef* NOR_HandleTypeDef::Extended

Extended mode register base address

Definition at line 186 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), and HAL_NOR_Init().

FMC_NORSRAM_InitTypeDef NOR_HandleTypeDef::Init

NOR device control configuration parameters

Definition at line 188 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), HAL_NOR_ReturnToReadMode(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

FMC_NORSRAM_TypeDef* NOR_HandleTypeDef::Instance

Register base address

Definition at line 184 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Init(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

HAL_LockTypeDef NOR_HandleTypeDef::Lock

NOR locking object

Definition at line 190 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_Init().

__IO HAL_NOR_StateTypeDef NOR_HandleTypeDef::State

NOR device access state

Definition at line 192 of file stm32l4xx_hal_nor.h.

Referenced by HAL_NOR_DeInit(), HAL_NOR_Erase_Block(), HAL_NOR_Erase_Chip(), HAL_NOR_GetState(), HAL_NOR_Init(), HAL_NOR_Program(), HAL_NOR_ProgramBuffer(), HAL_NOR_Read(), HAL_NOR_Read_CFI(), HAL_NOR_Read_ID(), HAL_NOR_ReadBuffer(), HAL_NOR_ReturnToReadMode(), HAL_NOR_WriteOperation_Disable(), and HAL_NOR_WriteOperation_Enable().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_nor.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NOR Exported Macros

Defines
NOR Exported Macros
NOR

Defines

#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
Reset NOR handle state.

Define Documentation

#define __HAL_NOR_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)

Reset NOR handle state.

Parameters:
__HANDLE__,: NOR handle
Return values:
None

Definition at line 210 of file stm32l4xx_hal_nor.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
OPAMP Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initializes the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_DeInit ( OPAMP_HandleTypeDef * hopamp )

DeInitialize the OPAMP peripheral.

Note:
Deinitialization can be performed if the OPAMP configuration is locked. (the lock is SW in L4)
Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 424 of file stm32l4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_MspDeInit(), HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Instance, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE, and OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Init ( OPAMP_HandleTypeDef * hopamp )

Initializes the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.

Note:
If the selected opamp is locked, initialization can't be performed. To unlock the configuration, perform a system reset.
Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 281 of file stm32l4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_MspInit(), HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Init, OPAMP_HandleTypeDef::Instance, OPAMP_InitTypeDef::InvertingInput, IS_OPAMP_FUNCTIONAL_NORMALMODE, IS_OPAMP_INVERTING_INPUT_PGA, IS_OPAMP_INVERTING_INPUT_STANDALONE, IS_OPAMP_NONINVERTING_INPUT, IS_OPAMP_PGA_GAIN, IS_OPAMP_POWER_SUPPLY_RANGE, IS_OPAMP_POWERMODE, IS_OPAMP_TRIMMING, IS_OPAMP_TRIMMINGVALUE, OPAMP_HandleTypeDef::Lock, OPAMP_InitTypeDef::Mode, OPAMP_InitTypeDef::NonInvertingInput, OPAMP_CSR_INIT_MASK_FOLLOWER, OPAMP_CSR_INIT_MASK_PGA, OPAMP_CSR_INIT_MASK_STANDALONE, OPAMP_FOLLOWER_MODE, OPAMP_INPUT_NONINVERTING, OPAMP_PGA_MODE, OPAMP_POWERMODE_LOWPOWER, OPAMP_POWERMODE_NORMAL, OPAMP_STANDALONE_MODE, OPAMP_TRIMMING_USER, OPAMP_InitTypeDef::PgaGain, OPAMP_InitTypeDef::PowerMode, OPAMP_InitTypeDef::PowerSupplyRange, OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueNLowPower, OPAMP_InitTypeDef::TrimmingValueP, OPAMP_InitTypeDef::TrimmingValuePLowPower, and OPAMP_InitTypeDef::UserTrimming.

void HAL_OPAMP_MspDeInit ( OPAMP_HandleTypeDef * hopamp )

DeInitialize OPAMP MSP.

Parameters:
hopamp,: OPAMP handle
Return values:
None

Definition at line 479 of file stm32l4xx_hal_opamp.c.

Referenced by HAL_OPAMP_DeInit().

void HAL_OPAMP_MspInit ( OPAMP_HandleTypeDef * hopamp )

Initialize the OPAMP MSP.

Parameters:
hopamp,: OPAMP handle
Return values:
None

Definition at line 464 of file stm32l4xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
OPAMP Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.

Detailed Description

IO operation functions.

 ===============================================================================
                        ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the OPAMP
    start, stop and calibration actions.

Function Documentation

HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate ( OPAMP_HandleTypeDef * hopamp )

Run the self calibration of one OPAMP.

Note:
Calibration is performed in the mode specified in OPAMP init structure (mode normal or low-power). To perform calibration for both modes, repeat this function twice after OPAMP init structure accordingly updated.
Calibration runs about 10 ms.
Parameters:
hopamp handle
Return values:
Updated | offset trimming values (PMOS & NMOS), user trimming is enabled
HAL | status

Definition at line 600 of file stm32l4xx_hal_opamp.c.

References assert_param, HAL_Delay(), HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_READY, OPAMP_HandleTypeDef::Init, OPAMP_HandleTypeDef::Instance, IS_OPAMP_POWERMODE, OPAMP_INPUT_NONINVERTING, OPAMP_POWERMODE_LOWPOWER, OPAMP_POWERMODE_NORMAL, OPAMP_STANDALONE_MODE, OPAMP_TRIMMING_DELAY, OPAMP_TRIMMING_USER, OPAMP_InitTypeDef::PowerMode, OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueNLowPower, OPAMP_InitTypeDef::TrimmingValueP, OPAMP_InitTypeDef::TrimmingValuePLowPower, and OPAMP_InitTypeDef::UserTrimming.

HAL_StatusTypeDef HAL_OPAMP_Start ( OPAMP_HandleTypeDef * hopamp )

Start the OPAMP.

Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 515 of file stm32l4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_READY, OPAMP_HandleTypeDef::Instance, and OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Stop ( OPAMP_HandleTypeDef * hopamp )

Stop the OPAMP.

Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 553 of file stm32l4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, OPAMP_HandleTypeDef::Instance, and OPAMP_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
OPAMP Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected OPAMP configuration.
HAL_OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the OPAMP data
    transfers.

Function Documentation

HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset | ( | OPAMP_HandleTypeDef * | hopamp,
 |  | uint32_t | trimmingoffset
 | ) |  |

Return the OPAMP factory trimming value.

Note:
On STM32L4 OPAMP, user can retrieve factory trimming if OPAMP has never been set to user trimming before. Therefore, this function must be called when OPAMP init parameter "UserTrimming" is set to trimming factory, and before OPAMP calibration (function "HAL_OPAMP_SelfCalibrate()"). Otherwise, factory trimming value cannot be retrieved and error status is returned.
Parameters:
hopamp | : OPAMP handle
trimmingoffset | : Trimming offset (P or N) This parameter must be a value of OPAMP Factory Trimming
Note:
Calibration parameter retrieved is corresponding to the mode specified in OPAMP init structure (mode normal or low-power). To retrieve calibration parameters for both modes, repeat this function after OPAMP init structure accordingly updated.
Return values:
Trimming value (P or N): range: 0->31 or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available

Definition at line 875 of file stm32l4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Init, OPAMP_HandleTypeDef::Instance, IS_OPAMP_FACTORYTRIMMING, IS_OPAMP_POWERMODE, OPAMP_FACTORYTRIMMING_DUMMY, OPAMP_FACTORYTRIMMING_P, OPAMP_INPUT_NONINVERTING, OPAMP_POWERMODE_NORMAL, OPAMP_InitTypeDef::PowerMode, and OPAMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_OPAMP_Lock ( OPAMP_HandleTypeDef * hopamp )

Lock the selected OPAMP configuration.

Note:
On STM32L4, HAL OPAMP lock is software lock only (in contrast of hardware lock available on some other STM32 devices).
Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 825 of file stm32l4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Instance, and OPAMP_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
OPAMP Exported Functions

Peripheral State functions. More...

Functions

HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState ( OPAMP_HandleTypeDef * hopamp )

Return the OPAMP handle state.

Parameters:
hopamp : OPAMP handle
Return values:
HAL state

Definition at line 958 of file stm32l4xx_hal_opamp.c.

References assert_param, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Instance, and OPAMP_HandleTypeDef::State.

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STM32L486xx HAL User Manual: OPAMP Exported Types

Data Structures | Typedefs | Enumerations
OPAMP Exported Types
OPAMP

Data Structures

struct | OPAMP_InitTypeDef
OPAMP Init structure definition. More...
struct | OPAMP_HandleTypeDef
OPAMP Handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_OPAMP_TrimmingValueTypeDef
HAl_OPAMP_TrimmingValueTypeDef definition.

Enumerations

enum HAL_OPAMP_StateTypeDef {
HAL_OPAMP_STATE_RESET = 0x00000000, HAL_OPAMP_STATE_READY = 0x00000001, HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, HAL_OPAMP_STATE_BUSY = 0x00000004,
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005
}
HAL State structures definition. More...

Typedef Documentation

typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef

HAl_OPAMP_TrimmingValueTypeDef definition.

Definition at line 154 of file stm32l4xx_hal_opamp.h.

Enumeration Type Documentation

enum HAL_OPAMP_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_OPAMP_STATE_RESET

OPAMP is not yet Initialized

HAL_OPAMP_STATE_READY

OPAMP is initialized and ready for use

HAL_OPAMP_STATE_CALIBBUSY

OPAMP is enabled in auto calibration mode

HAL_OPAMP_STATE_BUSY

OPAMP is enabled and running in normal mode

HAL_OPAMP_STATE_BUSYLOCKED

OPAMP is locked only system reset allows reconfiguring the opamp.

Definition at line 124 of file stm32l4xx_hal_opamp.h.

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STM32L486xx HAL User Manual: OPAMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OPAMP_InitTypeDef Struct Reference
OPAMP Exported Types

OPAMP Init structure definition. More...

#include <stm32l4xx_hal_opamp.h>

Data Fields

uint32_t | PowerSupplyRange
uint32_t | PowerMode
uint32_t | Mode
uint32_t | InvertingInput
uint32_t | NonInvertingInput
uint32_t | PgaGain
uint32_t | UserTrimming
uint32_t | TrimmingValueP
uint32_t | TrimmingValueN
uint32_t | TrimmingValuePLowPower
uint32_t | TrimmingValueNLowPower

Detailed Description

OPAMP Init structure definition.

Definition at line 67 of file stm32l4xx_hal_opamp.h.

Field Documentation

uint32_t OPAMP_InitTypeDef::InvertingInput

Specifies the inverting input in Standalone & PGA modes

  • In Standalone mode: i.e. when mode is OPAMP_STANDALONE_MODE & PGA mode: i.e. when mode is OPAMP_PGA_MODE This parameter must be a value of OPAMP Inverting Input
  • In Follower mode i.e. when mode is OPAMP_FOLLOWER_MODE This parameter is Not Applicable

Definition at line 80 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::Mode

Specifies the OPAMP mode This parameter must be a value of OPAMP Mode mode is either Standalone, - Follower or PGA

Definition at line 76 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::NonInvertingInput

Specifies the non inverting input of the opamp: This parameter must be a value of OPAMP Non Inverting Input

Definition at line 87 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PgaGain

Specifies the gain in PGA mode i.e. when mode is OPAMP_PGA_MODE. This parameter must be a value of OPAMP Pga Gain (2, 4, 8 or 16 )

Definition at line 90 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::PowerMode

Specifies the power mode Normal or Low-Power. This parameter must be a value of OPAMP PowerMode

Definition at line 73 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::PowerSupplyRange

Specifies the power supply range: above or under 2.4V. This parameter must be a value of OPAMP PowerSupplyRange Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances.

Definition at line 69 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

uint32_t OPAMP_InitTypeDef::TrimmingValueN

Specifies the offset trimming value (NMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value

Definition at line 103 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValueNLowPower

Specifies the offset trimming value (NMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value

Definition at line 113 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValueP

Specifies the offset trimming value (PMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value

Definition at line 98 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::TrimmingValuePLowPower

Specifies the offset trimming value (PMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value

Definition at line 108 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

uint32_t OPAMP_InitTypeDef::UserTrimming

Specifies the trimming mode This parameter must be a value of OPAMP User Trimming UserTrimming is either factory or user trimming.

Definition at line 94 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_opamp.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
OPAMP_HandleTypeDef Struct Reference
OPAMP Exported Types

OPAMP Handle Structure definition. More...

#include <stm32l4xx_hal_opamp.h>

Data Fields

OPAMP_TypeDef * | Instance
OPAMP_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_OPAMP_StateTypeDef | State

Detailed Description

OPAMP Handle Structure definition.

Definition at line 140 of file stm32l4xx_hal_opamp.h.

Field Documentation

OPAMP_InitTypeDef OPAMP_HandleTypeDef::Init

OPAMP required parameters

Definition at line 143 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

OPAMP_TypeDef* OPAMP_HandleTypeDef::Instance

OPAMP instance's registers base address

Definition at line 142 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMPEx_SelfCalibrateAll(), and HAL_OPAMPEx_Unlock().

HAL_LockTypeDef OPAMP_HandleTypeDef::Lock

Locking object

Definition at line 145 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

__IO HAL_OPAMP_StateTypeDef OPAMP_HandleTypeDef::State

OPAMP communication state

Definition at line 146 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMPEx_SelfCalibrateAll(), and HAL_OPAMPEx_Unlock().

HAL_StatusTypeDef OPAMP_HandleTypeDef::Status

OPAMP peripheral status

Definition at line 144 of file stm32l4xx_hal_opamp.h.

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_opamp.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP Mode

Defines
OPAMP Mode
OPAMP Exported Constants

Defines

#define | OPAMP_STANDALONE_MODE ((uint32_t)0x00000000)
#define | OPAMP_PGA_MODE OPAMP_CSR_OPAMODE_1
#define | OPAMP_FOLLOWER_MODE OPAMP_CSR_OPAMODE

Define Documentation

#define OPAMP_FOLLOWER_MODE OPAMP_CSR_OPAMODE

follower mode

Definition at line 171 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define OPAMP_PGA_MODE OPAMP_CSR_OPAMODE_1

PGA mode

Definition at line 170 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000)

standalone mode

Definition at line 169 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

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STM32L486xx HAL User Manual: OPAMP Non Inverting Input

Defines
OPAMP Non Inverting Input
OPAMP Exported Constants

Defines

#define | OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000)
#define | OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL

Define Documentation

#define OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL

OPAMP non-inverting input connected internally to DAC channel

Definition at line 182 of file stm32l4xx_hal_opamp.h.

#define OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000)

OPAMP non-inverting input connected to dedicated IO pin

Definition at line 181 of file stm32l4xx_hal_opamp.h.

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STM32L486xx HAL User Manual: OPAMP Inverting Input

Defines
OPAMP Inverting Input
OPAMP Exported Constants

Defines

#define | OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000)
#define | OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0
#define | OPAMP_INVERTINGINPUT_CONNECT_NO OPAMP_CSR_VMSEL_1

Define Documentation

#define OPAMP_INVERTINGINPUT_CONNECT_NO OPAMP_CSR_VMSEL_1

OPAMP inverting input not connected externally (PGA mode only)

Definition at line 194 of file stm32l4xx_hal_opamp.h.

#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000)

OPAMP inverting input connected to dedicated IO pin low-leakage

Definition at line 192 of file stm32l4xx_hal_opamp.h.

#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0

OPAMP inverting input connected to alternative IO pin available on some device packages

Definition at line 193 of file stm32l4xx_hal_opamp.h.

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STM32L486xx HAL User Manual: OPAMP Pga Gain

Defines
OPAMP Pga Gain
OPAMP Exported Constants

Defines

#define | OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000)
#define | OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0
#define | OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1
#define | OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)

Define Documentation

#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)

PGA gain = 16

Definition at line 207 of file stm32l4xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000)

PGA gain = 2

Definition at line 204 of file stm32l4xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0

PGA gain = 4

Definition at line 205 of file stm32l4xx_hal_opamp.h.

#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1

PGA gain = 8

Definition at line 206 of file stm32l4xx_hal_opamp.h.

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STM32L486xx HAL User Manual: OPAMP PowerMode

Defines
OPAMP PowerMode
OPAMP Exported Constants

Defines

#define | OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000)
#define | OPAMP_POWERMODE_LOWPOWER OPAMP_CSR_OPALPM

Define Documentation

#define OPAMP_POWERMODE_LOWPOWER OPAMP_CSR_OPALPM

Definition at line 217 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000)

Definition at line 216 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP PowerSupplyRange

Defines
OPAMP PowerSupplyRange
OPAMP Exported Constants

Defines

#define | OPAMP_POWERSUPPLY_LOW ((uint32_t)0x00000000)
#define | OPAMP_POWERSUPPLY_HIGH OPAMP1_CSR_OPARANGE

Define Documentation

#define OPAMP_POWERSUPPLY_HIGH OPAMP1_CSR_OPARANGE

Power supply range high (VDDA higher than 2.4V)

Definition at line 227 of file stm32l4xx_hal_opamp.h.

#define OPAMP_POWERSUPPLY_LOW ((uint32_t)0x00000000)

Power supply range low (VDDA lower than 2.4V)

Definition at line 226 of file stm32l4xx_hal_opamp.h.

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STM32L486xx HAL User Manual: OPAMP User Trimming

Defines
OPAMP User Trimming
OPAMP Exported Constants

Defines

#define | OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000)
#define | OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM
#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | IS_OPAMP_TRIMMING(TRIMMING)

Define Documentation

#define IS_OPAMP_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
                                     ((TRIMMING) == OPAMP_TRIMMING_USER))

Definition at line 337 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_TRIMMING ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
                                     ((TRIMMING) == OPAMP_TRIMMING_USER))

Definition at line 337 of file stm32l4xx_hal_opamp.h.

#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000)

Factory trimming

Definition at line 236 of file stm32l4xx_hal_opamp.h.

#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM

User trimming

Definition at line 237 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

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STM32L486xx HAL User Manual: OPAMP Factory Trimming

Defines
OPAMP Factory Trimming
OPAMP Exported Constants

Defines

#define | OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF)
#define | OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000)
#define | OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001)

Define Documentation

#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF)

Dummy value if trimming value could not be retrieved

Definition at line 248 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000)

Offset trimming N

Definition at line 250 of file stm32l4xx_hal_opamp.h.

#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001)

Offset trimming P

Definition at line 251 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

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STM32L486xx HAL User Manual: OPAMP Private Constants

Defines
OPAMP Private Constants
OPAMP

OPAMP Private constants and defines. More...

Defines

#define | OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
#define | OPAMP_CSR_RESET_BITS
#define | OPAMP_CSR_INIT_MASK_PGA
#define | OPAMP_CSR_INIT_MASK_FOLLOWER
#define | OPAMP_CSR_INIT_MASK_STANDALONE
#define | OPAMP_INPUT_NONINVERTING ((uint32_t) 8)
#define | OPAMP_TRIMMING_DELAY ((uint32_t) 1)

Detailed Description

OPAMP Private constants and defines.

Define Documentation

#define OPAMP_CSR_INIT_MASK_FOLLOWER
Value:
(OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_VPSEL \
                                    | OPAMP_CSR_USERTRIM)

Definition at line 242 of file stm32l4xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

#define OPAMP_CSR_INIT_MASK_PGA
Value:
(OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_PGGAIN \
                               | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL | OPAMP_CSR_USERTRIM)

Definition at line 239 of file stm32l4xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

#define OPAMP_CSR_INIT_MASK_STANDALONE
Value:
(OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_VPSEL \
                                      | OPAMP_CSR_VMSEL | OPAMP_CSR_USERTRIM)

Definition at line 245 of file stm32l4xx_hal_opamp.c.

Referenced by HAL_OPAMP_Init().

#define OPAMP_CSR_RESET_BITS
Value:
(OPAMP_CSR_OPAMPxEN | OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE \
                               | OPAMP_CSR_PGGAIN | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL \
                               | OPAMP_CSR_CALON | OPAMP_CSR_USERTRIM)

Definition at line 234 of file stm32l4xx_hal_opamp.c.

Referenced by HAL_OPAMP_DeInit().

#define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)

Definition at line 232 of file stm32l4xx_hal_opamp.c.

Referenced by HAL_OPAMP_DeInit().

#define OPAMP_INPUT_NONINVERTING ((uint32_t) 8)

Non inverting input

Definition at line 268 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define OPAMP_TRIMMING_DELAY ((uint32_t) 1)

Definition at line 274 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

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STM32L486xx HAL User Manual: OPAMP Exported Macros

Defines
OPAMP Exported Macros
OPAMP

Defines

#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
Reset OPAMP handle state.

Define Documentation

#define __HAL_OPAMP_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)

Reset OPAMP handle state.

Parameters:
__HANDLE__,: OPAMP handle.
Return values:
None

Definition at line 289 of file stm32l4xx_hal_opamp.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP Private Macros

Defines
OPAMP Private Macros
OPAMP

Defines

#define | IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT)
#define | IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT)
#define | IS_OPAMP_NONINVERTING_INPUT(INPUT)
#define | IS_OPAMP_INVERTING_INPUT_PGA(INPUT)
#define | IS_OPAMP_PGA_GAIN(GAIN)
#define | IS_OPAMP_POWERMODE(TRIMMING)
#define | IS_OPAMP_POWER_SUPPLY_RANGE(RANGE)
#define | IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_OPAMP_FACTORYTRIMMING(TRIMMING)

Define Documentation

#define IS_OPAMP_FACTORYTRIMMING ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
                                             ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))

Definition at line 343 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset().

#define IS_OPAMP_FUNCTIONAL_NORMALMODE ( INPUT )
Value:
(((INPUT) == OPAMP_STANDALONE_MODE) || \
                                               ((INPUT) == OPAMP_PGA_MODE) || \
                                               ((INPUT) == OPAMP_FOLLOWER_MODE))

Definition at line 301 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_INVERTING_INPUT_PGA ( INPUT )
Value:
(((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
                                             ((INPUT) == OPAMP_INVERTINGINPUT_IO1)|| \
                                             ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO))

Definition at line 317 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_INVERTING_INPUT_STANDALONE ( INPUT )
Value:
(((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
                                                    ((INPUT) == OPAMP_INVERTINGINPUT_IO1))

Definition at line 306 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_NONINVERTING_INPUT ( INPUT )
Value:
(((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))

Definition at line 313 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_PGA_GAIN ( GAIN )
Value:
(((GAIN) == OPAMP_PGA_GAIN_2) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_4) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_8) || \
                                 ((GAIN) == OPAMP_PGA_GAIN_16))

Definition at line 326 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_POWER_SUPPLY_RANGE ( RANGE )
Value:
(((RANGE) == OPAMP_POWERSUPPLY_LOW) || \
                                            ((RANGE) == OPAMP_POWERSUPPLY_HIGH)  )

Definition at line 334 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

#define IS_OPAMP_POWERMODE ( TRIMMING )
Value:
(((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
                                      ((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) )

Definition at line 331 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_SelfCalibrate(), and HAL_OPAMPEx_SelfCalibrateAll().

#define IS_OPAMP_TRIMMINGVALUE ( TRIMMINGVALUE ) ((TRIMMINGVALUE) <= 0x1F)

Definition at line 341 of file stm32l4xx_hal_opamp.h.

Referenced by HAL_OPAMP_Init().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD Private Macros

Defines
PCD Private Macros
PCD

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Define Documentation

#define PCD_MAX | ( | a,
 |  | b
 | ) | (((a) > (b)) ? (a) : (b))

Definition at line 100 of file stm32l4xx_hal_pcd.c.

#define PCD_MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Definition at line 99 of file stm32l4xx_hal_pcd.c.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD Private Functions

Functions
PCD Private Functions
PCD

Functions

static HAL_StatusTypeDef PCD_WriteEmptyTxFifo (PCD_HandleTypeDef *hpcd, uint32_t epnum)
Check FIFO for the next packet to be loaded.

Function Documentation

static HAL_StatusTypeDef PCD_WriteEmptyTxFifo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint32_t | epnum
 | ) |  | [static]

Check FIFO for the next packet to be loaded.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
HAL status

Definition at line 1360 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, and PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_IRQHandler().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PCD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_PCD_DeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes the PCD peripheral.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 228 of file stm32l4xx_hal_pcd.c.

References HAL_PCD_MspDeInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_RESET, HAL_PCD_Stop(), and PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_Init ( PCD_HandleTypeDef * hpcd )

Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 143 of file stm32l4xx_hal_pcd.c.

References __HAL_PCD_DISABLE, assert_param, HAL_PCD_MspInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCDEx_ActivateBCD(), HAL_PCDEx_ActivateLPM(), PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, PCD_HandleTypeDef::Lock, PCD_HandleTypeDef::OUT_ep, PCD_HandleTypeDef::State, and PCD_HandleTypeDef::USB_Address.

void HAL_PCD_MspDeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes PCD MSP.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 269 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_MspInit ( PCD_HandleTypeDef * hpcd )

Initializes the PCD MSP.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 254 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_Init().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
PCD Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB OTG Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB OTG Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
Handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PCD data
    transfers.

Function Documentation

void HAL_PCD_ConnectCallback ( PCD_HandleTypeDef * hpcd )

Connection event callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 975 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_DataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data IN stage callback.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 851 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_DataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data OUT stage callback.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 834 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_DisconnectCallback ( PCD_HandleTypeDef * hpcd )

Disconnection event callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 990 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_IRQHandler ( PCD_HandleTypeDef * hpcd )

Handles PCD interrupt request.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 332 of file stm32l4xx_hal_pcd.c.

References __HAL_PCD_CLEAR_FLAG, __HAL_PCD_GET_FLAG, __HAL_PCD_IS_INVALID_INTERRUPT, PCD_HandleTypeDef::BESL, HAL_PCD_ConnectCallback(), HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_DisconnectCallback(), HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetupStageCallback(), HAL_PCD_SOFCallback(), HAL_PCD_SuspendCallback(), HAL_PCDEx_LPM_Callback(), HAL_RCC_GetHCLKFreq(), PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, LPM_L0, LPM_L1, PCD_HandleTypeDef::LPM_State, PCD_HandleTypeDef::OUT_ep, PCD_LPM_L0_ACTIVE, PCD_LPM_L1_ACTIVE, PCD_WriteEmptyTxFifo(), and PCD_HandleTypeDef::Setup.

void HAL_PCD_ISOINIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO IN callback.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 959 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ISOOUTIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO OUT callback.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 942 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ResetCallback ( PCD_HandleTypeDef * hpcd )

USB Reset callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 896 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ResumeCallback ( PCD_HandleTypeDef * hpcd )

Resume event callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 926 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_SetupStageCallback ( PCD_HandleTypeDef * hpcd )

Setup stage callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 866 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_SOFCallback ( PCD_HandleTypeDef * hpcd )

USB Start Of Frame callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 881 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

HAL_StatusTypeDef HAL_PCD_Start ( PCD_HandleTypeDef * hpcd )

Start The USB OTG Device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 303 of file stm32l4xx_hal_pcd.c.

References __HAL_PCD_ENABLE, and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_Stop ( PCD_HandleTypeDef * hpcd )

Stop The USB OTG Device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 317 of file stm32l4xx_hal_pcd.c.

References __HAL_PCD_DISABLE, and PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_SuspendCallback ( PCD_HandleTypeDef * hpcd )

Suspend event callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 911 of file stm32l4xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

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STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCD Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

Activate remote wakeup signalling.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1299 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

De-activate remote wakeup signalling.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1309 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevConnect ( PCD_HandleTypeDef * hpcd )

Connect the USB device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1024 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevDisconnect ( PCD_HandleTypeDef * hpcd )

Disconnect the USB device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1037 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_EP_Close | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Deactivate an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1100 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_ClrStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Clear a STALL condition over in an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1246 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Flush | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Flush an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1276 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

uint16_t HAL_PCD_EP_GetRxCount | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Get Received Data Size.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
Data Size

Definition at line 1165 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Open | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint16_t | ep_mps,
 |  | uint8_t | ep_type
 | ) |  |

Open and configure an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
ep_mps,: endpoint max packet size
ep_type,: endpoint type
Return values:
HAL status

Definition at line 1067 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Receive an amount of data.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
pBuf,: pointer to the reception buffer
len,: amount of data to be received
Return values:
HAL status

Definition at line 1131 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_SetStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Set a STALL condition over an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1212 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, PCD_HandleTypeDef::OUT_ep, and PCD_HandleTypeDef::Setup.

HAL_StatusTypeDef HAL_PCD_EP_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Send an amount of data.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
pBuf,: pointer to the transmission buffer
len,: amount of data to be sent
Return values:
HAL status

Definition at line 1177 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_SetAddress | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | address
 | ) |  |

Set the USB Device address.

Parameters:
hpcd,: PCD handle
address,: new device address
Return values:
HAL status

Definition at line 1051 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::USB_Address.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
PCD Exported Functions

Peripheral State functions. More...

Functions

PCD_StateTypeDef HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

PCD_StateTypeDef HAL_PCD_GetState ( PCD_HandleTypeDef * hpcd )

Return the PCD handle state.

Parameters:
hpcd,: PCD handle
Return values:
HAL state

Definition at line 1337 of file stm32l4xx_hal_pcd.c.

References PCD_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD Exported Types

Data Structures | Typedefs | Enumerations
PCD Exported Types
PCD

Data Structures

struct | PCD_HandleTypeDef
PCD Handle Structure definition. More...

Typedefs

typedef USB_OTG_GlobalTypeDef | PCD_TypeDef
typedef USB_OTG_CfgTypeDef | PCD_InitTypeDef
typedef USB_OTG_EPTypeDef | PCD_EPTypeDef

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }

Typedef Documentation

typedef USB_OTG_EPTypeDef PCD_EPTypeDef

Definition at line 113 of file stm32l4xx_hal_pcd.h.

typedef USB_OTG_CfgTypeDef PCD_InitTypeDef

Definition at line 112 of file stm32l4xx_hal_pcd.h.

typedef USB_OTG_GlobalTypeDef PCD_TypeDef

Definition at line 111 of file stm32l4xx_hal_pcd.h.

Enumeration Type Documentation

enum PCD_LPM_StateTypeDef
Enumerator:
LPM_L0
LPM_L1
LPM_L2
LPM_L3

Definition at line 80 of file stm32l4xx_hal_pcd.h.

enum PCD_StateTypeDef

PCD State structure definition.

Enumerator:
HAL_PCD_STATE_RESET
HAL_PCD_STATE_READY
HAL_PCD_STATE_ERROR
HAL_PCD_STATE_BUSY
HAL_PCD_STATE_TIMEOUT

Definition at line 70 of file stm32l4xx_hal_pcd.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PCD_HandleTypeDef Struct Reference
PCD Exported Types

PCD Handle Structure definition. More...

#include <stm32l4xx_hal_pcd.h>

Data Fields

PCD_TypeDef * Instance
PCD_InitTypeDef Init
__IO uint8_t | USB_Address
PCD_EPTypeDef | IN_ep [15]
PCD_EPTypeDef | OUT_ep [15]
HAL_LockTypeDef | Lock
__IO PCD_StateTypeDef | State
uint32_t | Setup [12]
PCD_LPM_StateTypeDef LPM_State
uint32_t | BESL
uint32_t | lpm_active
uint32_t | battery_charging_active
void * | pData

Detailed Description

PCD Handle Structure definition.

Definition at line 125 of file stm32l4xx_hal_pcd.h.

Field Documentation

uint32_t PCD_HandleTypeDef::battery_charging_active

Enable or disable Battery charging. This parameter can be set to ENABLE or DISABLE

Definition at line 142 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateBCD(), and HAL_PCDEx_DeActivateBCD().

uint32_t PCD_HandleTypeDef::BESL

Definition at line 136 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

PCD_EPTypeDef PCD_HandleTypeDef::IN_ep[15]

IN endpoint parameters

Definition at line 130 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), and PCD_WriteEmptyTxFifo().

PCD_InitTypeDef PCD_HandleTypeDef::Init

PCD required parameters

Definition at line 128 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), and PCD_WriteEmptyTxFifo().

PCD_TypeDef* PCD_HandleTypeDef::Instance

Register base address

Definition at line 127 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_ActivateRemoteWakeup(), HAL_PCD_DeActivateRemoteWakeup(), HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Flush(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_SetAddress(), HAL_PCD_Start(), HAL_PCD_Stop(), HAL_PCDEx_ActivateBCD(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_BCD_VBUSDetect(), HAL_PCDEx_DeActivateBCD(), HAL_PCDEx_DeActivateLPM(), HAL_PCDEx_SetRxFiFo(), HAL_PCDEx_SetTxFiFo(), and PCD_WriteEmptyTxFifo().

HAL_LockTypeDef PCD_HandleTypeDef::Lock

PCD peripheral status

Definition at line 132 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

uint32_t PCD_HandleTypeDef::lpm_active

Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE

Definition at line 139 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateLPM(), and HAL_PCDEx_DeActivateLPM().

PCD_LPM_StateTypeDef PCD_HandleTypeDef::LPM_State

LPM State

Definition at line 135 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler(), and HAL_PCDEx_ActivateLPM().

PCD_EPTypeDef PCD_HandleTypeDef::OUT_ep[15]

OUT endpoint parameters

Definition at line 131 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_GetRxCount(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_Init(), and HAL_PCD_IRQHandler().

void* PCD_HandleTypeDef::pData

Pointer to upper stack Handler

Definition at line 144 of file stm32l4xx_hal_pcd.h.

uint32_t PCD_HandleTypeDef::Setup[12]

Setup packet buffer

Definition at line 134 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_EP_SetStall(), and HAL_PCD_IRQHandler().

__IO PCD_StateTypeDef PCD_HandleTypeDef::State

PCD communication state

Definition at line 133 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_GetState(), and HAL_PCD_Init().

__IO uint8_t PCD_HandleTypeDef::USB_Address

USB Address: not used by USB OTG FS

Definition at line 129 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), and HAL_PCD_SetAddress().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_pcd.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD Speed

Defines
PCD Speed
PCD Exported Constants

Defines

#define PCD_SPEED_FULL 1

Define Documentation

#define PCD_SPEED_FULL 1

Definition at line 163 of file stm32l4xx_hal_pcd.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD PHY Module

Defines
PCD PHY Module
PCD Exported Constants

Defines

#define PCD_PHY_EMBEDDED 1

Define Documentation

#define PCD_PHY_EMBEDDED 1

Definition at line 171 of file stm32l4xx_hal_pcd.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Turnaround Timeout Value

Defines
Turnaround Timeout Value
PCD Exported Constants

Defines

#define USBD_FS_TRDT_VALUE 5

Define Documentation

#define USBD_FS_TRDT_VALUE 5

Definition at line 180 of file stm32l4xx_hal_pcd.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD Exported Macros

Defines
PCD Exported Macros
PCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define | __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
#define | __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define | __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_PCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))

Definition at line 200 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_DISABLE ( __HANDLE__ ) USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 197 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), and HAL_PCD_Stop().

#define __HAL_PCD_ENABLE ( __HANDLE__ ) USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 196 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_Start().

#define __HAL_PCD_GATE_PHYCLOCK ( __HANDLE__ ) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK

Definition at line 207 of file stm32l4xx_hal_pcd.h.

#define __HAL_PCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 199 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_IS_INVALID_INTERRUPT ( __HANDLE__ ) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)

Definition at line 201 of file stm32l4xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_IS_PHY_SUSPENDED ( __HANDLE__ ) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)

Definition at line 209 of file stm32l4xx_hal_pcd.h.

#define __HAL_PCD_UNGATE_PHYCLOCK ( __HANDLE__ )
Value:
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
                                                          ~(USB_OTG_PCGCCTL_STOPCLK)

Definition at line 204 of file stm32l4xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG ( ) EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE

Definition at line 214 of file stm32l4xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT ( ) EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 212 of file stm32l4xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE ( )
Value:
do {\
                                                             EXTI->FTSR1 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                             EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                           } while(0)

Definition at line 221 of file stm32l4xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT ( ) EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE

Definition at line 211 of file stm32l4xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE ( )
Value:
do {\
                                                             EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                             EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
                                                           } while(0)

Definition at line 216 of file stm32l4xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {\
                                                                   EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                                   EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
                                                                   EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
                                                                   EXTI->FTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
                                                                  } while(0)

Definition at line 226 of file stm32l4xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 233 of file stm32l4xx_hal_pcd.h.

#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG ( ) EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE)

Definition at line 213 of file stm32l4xx_hal_pcd.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USB EXTI line interrupt

Defines
USB EXTI line interrupt
PCD Private Constants

Defines

#define | USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define | USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define | USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00020000)

Define Documentation

#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)

Definition at line 357 of file stm32l4xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00020000)

External interrupt line 17 Connected to the USB EXTI Line

Definition at line 360 of file stm32l4xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)

Definition at line 356 of file stm32l4xx_hal_pcd.h.

#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)

Definition at line 358 of file stm32l4xx_hal_pcd.h.

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STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCDEx Exported Functions

PCDEx control functions. More...

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCDEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Update FIFO configuration

Function Documentation

HAL_StatusTypeDef HAL_PCDEx_ActivateBCD ( PCD_HandleTypeDef * hpcd )

Activate BatteryCharging feature.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 251 of file stm32l4xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::battery_charging_active, and PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_Init().

HAL_StatusTypeDef HAL_PCDEx_ActivateLPM ( PCD_HandleTypeDef * hpcd )

Activate LPM feature.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 147 of file stm32l4xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance, PCD_HandleTypeDef::lpm_active, LPM_L0, and PCD_HandleTypeDef::LPM_State.

Referenced by HAL_PCD_Init().

void HAL_PCDEx_BCD_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_BCD_MsgTypeDef | msg
 | ) |  |

Send BatteryCharging message to user layer callback.

Parameters:
hpcd,: PCD handle
msg,: LPM message
Return values:
HAL status

Definition at line 489 of file stm32l4xx_hal_pcd_ex.c.

Referenced by HAL_PCDEx_BCD_VBUSDetect().

void HAL_PCDEx_BCD_VBUSDetect ( PCD_HandleTypeDef * hpcd )

Handle BatteryCharging Process.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 180 of file stm32l4xx_hal_pcd_ex.c.

References HAL_Delay(), HAL_GetTick(), HAL_PCDEx_BCD_Callback(), PCD_HandleTypeDef::Instance, PCD_BCD_CHARGING_DOWNSTREAM_PORT, PCD_BCD_CONTACT_DETECTION, PCD_BCD_DEDICATED_CHARGING_PORT, PCD_BCD_DISCOVERY_COMPLETED, PCD_BCD_ERROR, and PCD_BCD_STD_DOWNSTREAM_PORT.

HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD ( PCD_HandleTypeDef * hpcd )

Deactivate BatteryCharging feature.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 266 of file stm32l4xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::battery_charging_active, and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM ( PCD_HandleTypeDef * hpcd )

Deactivate LPM feature.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 164 of file stm32l4xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::lpm_active.

void HAL_PCDEx_LPM_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_LPM_MsgTypeDef | msg
 | ) |  |

Send LPM message to user layer callback.

Parameters:
hpcd,: PCD handle
msg,: LPM message
Return values:
HAL status

Definition at line 472 of file stm32l4xx_hal_pcd_ex.c.

Referenced by HAL_PCD_IRQHandler().

HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint16_t | size
 | ) |  |

Set Rx FIFO.

Parameters:
hpcd,: PCD handle
size,: Size of Rx fifo
Return values:
HAL status

Definition at line 135 of file stm32l4xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | fifo,
 |  | uint16_t | size
 | ) |  |

Set Tx FIFO.

Parameters:
hpcd,: PCD handle
fifo,: The number of Tx fifo
size,: Fifo size
Return values:
HAL status

Definition at line 93 of file stm32l4xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::Instance.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCDEx

Modules | Enumerations
PCDEx
STM32L4xx_HAL_Driver

PCD Extended HAL module driver. More...

Modules

PCDEx Exported Functions

Enumerations

enum PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}

Detailed Description

PCD Extended HAL module driver.

Enumeration Type Documentation

enum PCD_BCD_MsgTypeDef
Enumerator:
PCD_BCD_ERROR
PCD_BCD_CONTACT_DETECTION
PCD_BCD_STD_DOWNSTREAM_PORT
PCD_BCD_CHARGING_DOWNSTREAM_PORT
PCD_BCD_DEDICATED_CHARGING_PORT
PCD_BCD_DISCOVERY_COMPLETED

Definition at line 68 of file stm32l4xx_hal_pcd_ex.h.

enum PCD_LPM_MsgTypeDef
Enumerator:
PCD_LPM_L0_ACTIVE
PCD_LPM_L1_ACTIVE

Definition at line 62 of file stm32l4xx_hal_pcd_ex.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR PVD Mode Mask

Defines
PWR PVD Mode Mask
PWR Private Defines

Defines

#define | PVD_MODE_IT ((uint32_t)0x00010000)
#define | PVD_MODE_EVT ((uint32_t)0x00020000)
#define | PVD_RISING_EDGE ((uint32_t)0x00000001)
#define | PVD_FALLING_EDGE ((uint32_t)0x00000002)

Define Documentation

#define PVD_FALLING_EDGE ((uint32_t)0x00000002)

Mask for falling edge set as PVD trigger

Definition at line 70 of file stm32l4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_EVT ((uint32_t)0x00020000)

Mask for event yielded by PVD threshold crossing

Definition at line 68 of file stm32l4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_IT ((uint32_t)0x00010000)

Mask for interruption yielded by PVD threshold crossing

Definition at line 67 of file stm32l4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_EDGE ((uint32_t)0x00000001)

Mask for rising edge set as PVD trigger

Definition at line 69 of file stm32l4xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PWR Exported Functions

Initialization and de-initialization functions. More...

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers).

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]

Function Documentation

void HAL_PWR_DeInit ( void )

Deinitialize the HAL PWR peripheral registers to their default reset values.

Return values:
None

Definition at line 105 of file stm32l4xx_hal_pwr.c.

References __HAL_RCC_PWR_FORCE_RESET, and __HAL_RCC_PWR_RELEASE_RESET.

void HAL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain (RTC registers, RTC backup data registers).

Return values:
None

Definition at line 133 of file stm32l4xx_hal_pwr.c.

Referenced by HAL_RCCEx_DisableLSCO(), and HAL_RCCEx_EnableLSCO().

void HAL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain (RTC registers, RTC backup data registers).

Note:
After reset, the backup domain is protected against possible unwanted write accesses.
RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. In order to set or modify the RTC clock, the backup domain access must be disabled.
LSEON bit that switches on and off the LSE crystal belongs as well to the back-up domain.
Return values:
None

Definition at line 123 of file stm32l4xx_hal_pwr.c.

Referenced by HAL_RCCEx_DisableLSCO(), and HAL_RCCEx_EnableLSCO().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PWR Exported Functions

Low Power modes configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector (PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Power Voltage Detector (PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Power Voltage Detector (PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX M4 SEVONPEND bit.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

Low Power modes configuration functions.

 ===============================================================================
                 ##### Peripheral Control functions #####
 ===============================================================================

     [..]
     *** PVD configuration ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).

      (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line16 and can generate an interrupt if enabled. This is done through
          __HAL_PVD_EXTI_ENABLE_IT() macro.
      (+) The PVD is stopped in Standby mode.

    *** WakeUp pin configuration ***
    ================================
    [..]
      (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
          The polarity of these pins can be set to configure event detection on high
          level (rising edge) or low level (falling edge).

    *** Low Power modes configuration ***
    =====================================
    [..]
      The devices feature 8 low-power modes:
      (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
      (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
      (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
      (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
      (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
      (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.

   *** Low-power run mode ***
   ==========================
    [..]
      (+) Entry: (from main run mode)
        (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.

      (+) Exit:
        (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
             then can the system clock frequency be increased above 2 MHz.

   *** Sleep mode / Low-power sleep mode ***
   =========================================
    [..]
      (+) Entry:
          The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
          in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
          (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
          In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction

      (+) WFI Exit:
        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
             controller (NVIC) or any wake-up event.

      (+) WFE Exit:
        (++) Any wake-up event such as an EXTI line configured in event mode.

         [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
             the MCU is in Low-power Run mode.

   *** Stop 0, Stop 1 and Stop 2 modes ***
   ===============================
    [..]
      (+) Entry:
          The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
          (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
          (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
      (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
          (++) PWR_MAINREGULATOR_ON
          (++) PWR_LOWPOWERREGULATOR_ON
      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction

      (+) WFI Exit:
          (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
          (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
               when programmed in wakeup mode.
      (+) WFE Exit:
          (++) Any EXTI Line (Internal or External) configured in Event mode.

       [..]
          When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
          depending on the LPR bit setting.
          When exiting Stop 2 mode, the MCU is in Run mode.

   *** Standby mode ***
   ====================
     [..]
      The Standby mode offers two options:
      (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
        SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
        and Standby circuitry.
      (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
        SRAM and register contents are lost except for the RTC registers, RTC backup registers
        and Standby circuitry.

      (++) Entry:
          (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
                SRAM1 and register contents are lost except for registers in the Backup domain and
                Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
                To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
                to set RRS bit.

      (++) Exit:
          (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
                external reset in NRST pin, IWDG reset.

      [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.

    *** Shutdown mode ***
   ======================
     [..]
      In Shutdown mode,
        voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
        SRAM and registers contents are lost except for backup domain registers.

      (+) Entry:
          The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.

      (+) Exit:
          (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
               external reset in NRST pin.

         [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.

   *** Auto-wakeup (AWU) from low-power mode ***
   =============================================
    [..]
      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
      Wakeup event, a tamper event or a time-stamp event, without depending on
      an external interrupt (Auto-wakeup mode).

      (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes

        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.

        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
             is necessary to configure the RTC to detect the tamper or time stamp event using the
             HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.

        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.

Function Documentation

HAL_StatusTypeDef HAL_PWR_ConfigPVD ( PWR_PVDTypeDef * sConfigPVD )

Configure the voltage threshold detected by the Power Voltage Detector (PVD).

Parameters:
sConfigPVD,: pointer to a PWR_PVDTypeDef structure that contains the PVD configuration information.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage thresholds corresponding to each detection level.
Return values:
None

Definition at line 330 of file stm32l4xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_DISABLE_EVENT, __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_DISABLE_IT, __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_EVENT, __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_IT, __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVD_LEVEL, IS_PWR_PVD_MODE, PWR_PVDTypeDef::Mode, PVD_FALLING_EDGE, PVD_MODE_EVT, PVD_MODE_IT, PVD_RISING_EDGE, and PWR_PVDTypeDef::PVDLevel.

void HAL_PWR_DisablePVD ( void )

Disable the Power Voltage Detector (PVD).

Return values:
None

Definition at line 385 of file stm32l4xx_hal_pwr.c.

void HAL_PWR_DisableSEVOnPend ( void )

Disable CORTEX M4 SEVONPEND bit.

Note:
Clear SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 638 of file stm32l4xx_hal_pwr.c.

void HAL_PWR_DisableSleepOnExit ( void )

Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.

Note:
Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over.
Return values:
None

Definition at line 611 of file stm32l4xx_hal_pwr.c.

void HAL_PWR_DisableWakeUpPin ( uint32_t WakeUpPinx )

Disable the WakeUp PINx functionality.

Parameters:
WakeUpPinx,: Specifies the Power Wake-Up pin to disable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
Return values:
None

Definition at line 431 of file stm32l4xx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnablePVD ( void )

Enable the Power Voltage Detector (PVD).

Return values:
None

Definition at line 376 of file stm32l4xx_hal_pwr.c.

void HAL_PWR_EnableSEVOnPend ( void )

Enable CORTEX M4 SEVONPEND bit.

Note:
Set SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 625 of file stm32l4xx_hal_pwr.c.

void HAL_PWR_EnableSleepOnExit ( void )

Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.

Note:
Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over. Setting this bit is useful when the processor is expected to run only on interruptions handling.
Return values:
None

Definition at line 598 of file stm32l4xx_hal_pwr.c.

void HAL_PWR_EnableWakeUpPin ( uint32_t WakeUpPinPolarity )

Enable the WakeUp PINx functionality.

Parameters:
WakeUpPinPolarity,: Specifies which Wake-Up pin to enable. This parameter can be one of the following legacy values which set the default polarity i.e. detection on high level (rising edge):
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
or one of the following value where the user can explicitly specify the enabled pin and the chosen polarity:
  • PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
  • PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
  • PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
  • PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
  • PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
Note:
PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
Return values:
None

Definition at line 410 of file stm32l4xx_hal_pwr.c.

References assert_param, IS_PWR_WAKEUP_PIN, and PWR_WUP_POLARITY_SHIFT.

void HAL_PWR_EnterSLEEPMode | ( | uint32_t | Regulator,
 |  | uint8_t | SLEEPEntry
 | ) |  |

Enter Sleep or Low-power Sleep mode.

Note:
In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
Parameters:
Regulator,: Specifies the regulator state in Sleep/Low-power Sleep mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
  • PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
Note:
Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register. Additionally, the clock frequency must be reduced below 2 MHz. Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must be done before calling HAL_PWR_EnterSLEEPMode() API.
When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
Parameters:
SLEEPEntry,: Specifies if Sleep mode is entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
  • PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
Note:
When WFI entry is used, tick interrupt have to be disabled if not desired as the interrupt wake up source.
Return values:
None

Definition at line 463 of file stm32l4xx_hal_pwr.c.

References assert_param, HAL_PWREx_DisableLowPowerRunMode(), HAL_PWREx_EnableLowPowerRunMode(), IS_PWR_REGULATOR, IS_PWR_SLEEP_ENTRY, PWR_MAINREGULATOR_ON, and PWR_SLEEPENTRY_WFI.

void HAL_PWR_EnterSTANDBYMode ( void )

Enter Standby mode.

Note:
In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched off. The voltage regulator is disabled, except when SRAM2 content is preserved in which case the regulator is in low-power mode. SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API to set RRS bit. The BOR is available.
The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the same. These states are effective in Standby mode only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
Return values:
None

Definition at line 572 of file stm32l4xx_hal_pwr.c.

void HAL_PWR_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enter Stop mode.

Note:
This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running on devices where only "Stop mode" is mentioned with main or low power regulator ON.
In Stop mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available. The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set; the MSI oscillator is selected if STOPWUCK is cleared.
When the voltage regulator operates in low power mode (Stop 1), an additional startup delay is incurred when waking up. By keeping the internal regulator ON during Stop mode (Stop 0), the consumption is higher although the startup time is reduced.
Parameters:
Regulator,: Specifies the regulator state in Stop mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
  • PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
STOPEntry,: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
  • PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
Return values:
None

Definition at line 539 of file stm32l4xx_hal_pwr.c.

References assert_param, HAL_PWREx_EnterSTOP0Mode(), HAL_PWREx_EnterSTOP1Mode(), IS_PWR_REGULATOR, and PWR_LOWPOWERREGULATOR_ON.

void HAL_PWR_PVDCallback ( void )

PWR PVD interrupt callback.

Return values:
None

Definition at line 652 of file stm32l4xx_hal_pwr.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR_PVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVDTypeDef Struct Reference
PWR Exported Types

PWR PVD configuration structure definition. More...

#include <stm32l4xx_hal_pwr.h>

Data Fields

uint32_t | PVDLevel
uint32_t | Mode

Detailed Description

PWR PVD configuration structure definition.

Definition at line 66 of file stm32l4xx_hal_pwr.h.

Field Documentation

uint32_t PWR_PVDTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVD interrupt and event mode.

Definition at line 71 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

uint32_t PWR_PVDTypeDef::PVDLevel

PVDLevel: Specifies the PVD detection level. This parameter can be a value of Programmable Voltage Detection levels.

Definition at line 68 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_pwr.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Programmable Voltage Detection levels

Defines
Programmable Voltage Detection levels
PWR Exported Constants

Defines

#define | PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6
#define | PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7

Define Documentation

#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0

PVD threshold around 2.0 V

Definition at line 90 of file stm32l4xx_hal_pwr.h.

#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1

PVD threshold around 2.2 V

Definition at line 91 of file stm32l4xx_hal_pwr.h.

#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2

PVD threshold around 2.4 V

Definition at line 92 of file stm32l4xx_hal_pwr.h.

#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3

PVD threshold around 2.5 V

Definition at line 93 of file stm32l4xx_hal_pwr.h.

#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4

PVD threshold around 2.6 V

Definition at line 94 of file stm32l4xx_hal_pwr.h.

#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5

PVD threshold around 2.8 V

Definition at line 95 of file stm32l4xx_hal_pwr.h.

#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6

PVD threshold around 2.9 V

Definition at line 96 of file stm32l4xx_hal_pwr.h.

#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7

External input analog voltage (compared internally to VREFINT)

Definition at line 97 of file stm32l4xx_hal_pwr.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR PVD interrupt and event mode

Defines
PWR PVD interrupt and event mode
PWR Exported Constants

Defines

#define | PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000)
#define | PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001)
#define | PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002)
#define | PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)
#define | PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001)
#define | PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)

Define Documentation

#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002)

Event Mode with Falling edge trigger detection

Definition at line 110 of file stm32l4xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001)

Event Mode with Rising edge trigger detection

Definition at line 109 of file stm32l4xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)

Event Mode with Rising/Falling edge trigger detection

Definition at line 111 of file stm32l4xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002)

External Interrupt Mode with Falling edge trigger detection

Definition at line 107 of file stm32l4xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001)

External Interrupt Mode with Rising edge trigger detection

Definition at line 106 of file stm32l4xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 108 of file stm32l4xx_hal_pwr.h.

#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000)

Basic mode is used

Definition at line 105 of file stm32l4xx_hal_pwr.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR regulator mode

Defines
PWR regulator mode
PWR Exported Constants

Defines

#define | PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR

Define Documentation

#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR

Regulator in low-power mode

Definition at line 123 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)

Regulator in main mode

Definition at line 122 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR SLEEP mode entry

Defines
PWR SLEEP mode entry
PWR Exported Constants

Defines

#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

Define Documentation

#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

Wait For Event instruction to enter Sleep mode

Definition at line 132 of file stm32l4xx_hal_pwr.h.

#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)

Wait For Interruption instruction to enter Sleep mode

Definition at line 131 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR STOP mode entry

Defines
PWR STOP mode entry
PWR Exported Constants

Defines

#define | PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02)

Define Documentation

#define PWR_STOPENTRY_WFE ((uint8_t)0x02)

Wait For Event instruction to enter Stop mode

Definition at line 141 of file stm32l4xx_hal_pwr.h.

#define PWR_STOPENTRY_WFI ((uint8_t)0x01)

Wait For Interruption instruction to enter Stop mode

Definition at line 140 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSTOP0Mode(), HAL_PWREx_EnterSTOP1Mode(), and HAL_PWREx_EnterSTOP2Mode().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR PVD external interrupt line

Defines
PWR PVD external interrupt line
PWR Exported Constants

Defines

#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000)

Define Documentation

#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000)

External interrupt line 16 Connected to the PVD EXTI Line

Definition at line 150 of file stm32l4xx_hal_pwr.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR PVD event line

Defines
PWR PVD event line
PWR Exported Constants

Defines

#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000)

Define Documentation

#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000)

Event line 16 Connected to the PVD Event Line

Definition at line 158 of file stm32l4xx_hal_pwr.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Exported Macros

Defines
PWR Exported Macros
PWR

Defines

#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check whether or not a specific PWR flag is set.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__)
Clear a specific PWR flag.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Enable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Disable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
Check whether or not the PVD EXTI interrupt flag is set.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI interrupt flag.

Define Documentation

#define __HAL_PWR_CLEAR_FLAG ( __FLAG__ )
Value:
( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
                                         (PWR->SCR  = (__FLAG__)) :\
                                         (PWR->SCR = (1U << ((__FLAG__) & 31U))) )

Clear a specific PWR flag.

Parameters:
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event was received from the WKUP pin 1.
  • PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event was received from the WKUP pin 2.
  • PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event was received from the WKUP pin 3.
  • PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event was received from the WKUP pin 4.
  • PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event was received from the WKUP pin 5.
  • PWR_FLAG_WU Encompasses all five Wake Up Flags.
  • PWR_FLAG_SB Standby Flag. Indicates that the system entered Standby mode.
Return values:
None

Definition at line 232 of file stm32l4xx_hal_pwr.h.

#define __HAL_PWR_GET_FLAG ( __FLAG__ )
Value:
( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\
                                      (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
                                      (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )

Check whether or not a specific PWR flag is set.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event was received from the WKUP pin 1.
  • PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event was received from the WKUP pin 2.
  • PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event was received from the WKUP pin 3.
  • PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event was received from the WKUP pin 4.
  • PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event was received from the WKUP pin 5.
  • PWR_FLAG_SB StandBy Flag. Indicates that the system entered StandBy mode.
  • PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on the internal wakeup line.
  • PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the low-power regulator is ready.
  • PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the regulator is ready in main mode or is in low-power mode.
  • PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready in the selected voltage range or is still changing to the required voltage level.
  • PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is below or above the selected PVD threshold.
  • PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is is below or above PVM1 threshold (applicable when USB feature is supported).
  • PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
  • PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is is below or above PVM3 threshold.
  • PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is is below or above PVM4 threshold.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 210 of file stm32l4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)

Clear the PVD EXTI interrupt flag.

Return values:
None

Definition at line 321 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)

Disable the PVD Event Line.

Return values:
None

Definition at line 257 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 282 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Line.

Return values:
None

Definition at line 245 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 269 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 299 of file stm32l4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)

Enable the PVD Event Line.

Return values:
None

Definition at line 251 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 275 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Line.

Return values:
None

Definition at line 239 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 263 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                   \
    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

Enable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 289 of file stm32l4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 309 of file stm32l4xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GET_FLAG ( ) (EXTI->PR1 & PWR_EXTI_LINE_PVD)

Check whether or not the PVD EXTI interrupt flag is set.

Return values:
EXTI PVD Line Status.

Definition at line 315 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Private Macros

Defines
PWR Private Macros
PWR

Defines

#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))

Definition at line 333 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_PVD_MODE ( MODE )
Value:
(((MODE) == PWR_PVD_MODE_NORMAL)              ||\
                                ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
                                ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\
                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\
                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\
                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))

Definition at line 338 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                          ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

Definition at line 346 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode(), and HAL_PWR_EnterSTOPMode().

#define IS_PWR_SLEEP_ENTRY ( ENTRY ) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))

Definition at line 349 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

#define IS_PWR_STOP_ENTRY ( ENTRY ) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )

Definition at line 351 of file stm32l4xx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSTOP0Mode(), HAL_PWREx_EnterSTOP1Mode(), and HAL_PWREx_EnterSTOP2Mode().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR PVM Mode Mask

Defines
PWR PVM Mode Mask
PWR Extended Private Defines

Defines

#define | PVM_MODE_IT ((uint32_t)0x00010000)
#define | PVM_MODE_EVT ((uint32_t)0x00020000)
#define | PVM_RISING_EDGE ((uint32_t)0x00000001)
#define | PVM_FALLING_EDGE ((uint32_t)0x00000002)

Define Documentation

#define PVM_FALLING_EDGE ((uint32_t)0x00000002)

Mask for falling edge set as PVM trigger

Definition at line 76 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_MODE_EVT ((uint32_t)0x00020000)

Mask for event yielded by PVM threshold crossing

Definition at line 74 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_MODE_IT ((uint32_t)0x00010000)

Mask for interruption yielded by PVM threshold crossing

Definition at line 73 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_RISING_EDGE ((uint32_t)0x00000001)

Mask for rising edge set as PVM trigger

Definition at line 75 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ConfigPVM().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Extended Flag Setting Time Out Value

Defines
PWR Extended Flag Setting Time Out Value
PWR Extended Private Defines

Defines

#define PWR_FLAG_SETTING_DELAY_US 50

Define Documentation

#define PWR_FLAG_SETTING_DELAY_US 50

Time out value for REGLPF and VOSF flags setting

Definition at line 84 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_PWREx_DisableLowPowerRunMode().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
PWR Extended Exported Functions

Extended Peripheral Control functions. More...

Functions

uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnableVddUSB (void)
Enable VDDUSB supply.
void | HAL_PWREx_DisableVddUSB (void)
Disable VDDUSB supply.
void | HAL_PWREx_EnableVddIO2 (void)
Enable VDDIO2 supply.
void | HAL_PWREx_DisableVddIO2 (void)
Disable VDDIO2 supply.
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_EnableSRAM2ContentRetention (void)
Enable SRAM2 content retention in Standby mode.
void | HAL_PWREx_DisableSRAM2ContentRetention (void)
Disable SRAM2 content retention in Standby mode.
void | HAL_PWREx_EnablePVM1 (void)
Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_DisablePVM1 (void)
Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_EnablePVM2 (void)
Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
void | HAL_PWREx_DisablePVM2 (void)
Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
void | HAL_PWREx_EnablePVM3 (void)
Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
void | HAL_PWREx_DisablePVM3 (void)
Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
void | HAL_PWREx_EnablePVM4 (void)
Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
void | HAL_PWREx_DisablePVM4 (void)
Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSTOP0Mode (uint8_t STOPEntry)
Enter Stop 0 mode.
void | HAL_PWREx_EnterSTOP1Mode (uint8_t STOPEntry)
Enter Stop 1 mode.
void | HAL_PWREx_EnterSTOP2Mode (uint8_t STOPEntry)
Enter Stop 2 mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD/PVMx interrupt request.
__weak void | HAL_PWREx_PVM1Callback (void)
PWR PVM1 interrupt callback.
__weak void | HAL_PWREx_PVM2Callback (void)
PWR PVM2 interrupt callback.
__weak void | HAL_PWREx_PVM3Callback (void)
PWR PVM3 interrupt callback.
__weak void | HAL_PWREx_PVM4Callback (void)
PWR PVM4 interrupt callback.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extended Peripheral Initialization and de-initialization functions #####
 ===============================================================================
    [..]

Function Documentation

HAL_StatusTypeDef HAL_PWREx_ConfigPVM ( PWR_PVMTypeDef * sConfigPVM )

Configure the Peripheral Voltage Monitoring (PVM).

Parameters:
sConfigPVM,: pointer to a PWR_PVMTypeDef structure that contains the PVM configuration information.
Note:
The API configures a single PVM according to the information contained in the input structure. To configure several PVMs, the API must be singly called for each PVM used.
Refer to the electrical characteristics of your device datasheet for more details about the voltage thresholds corresponding to each detection level and to each monitored supply.
Return values:
HAL status

Definition at line 699 of file stm32l4xx_hal_pwr_ex.c.

References __HAL_PWR_PVM1_EXTI_DISABLE_EVENT, __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM1_EXTI_DISABLE_IT, __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM1_EXTI_ENABLE_EVENT, __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM1_EXTI_ENABLE_IT, __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE, __HAL_PWR_PVM2_EXTI_DISABLE_EVENT, __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM2_EXTI_DISABLE_IT, __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM2_EXTI_ENABLE_EVENT, __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM2_EXTI_ENABLE_IT, __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE, __HAL_PWR_PVM3_EXTI_DISABLE_EVENT, __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM3_EXTI_DISABLE_IT, __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM3_EXTI_ENABLE_EVENT, __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM3_EXTI_ENABLE_IT, __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE, __HAL_PWR_PVM4_EXTI_DISABLE_EVENT, __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM4_EXTI_DISABLE_IT, __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM4_EXTI_ENABLE_EVENT, __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM4_EXTI_ENABLE_IT, __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVM_MODE, IS_PWR_PVM_TYPE, PWR_PVMTypeDef::Mode, PVM_FALLING_EDGE, PVM_MODE_EVT, PVM_MODE_IT, PVM_RISING_EDGE, PWR_PVMTypeDef::PVMType, PWR_PVM_1, PWR_PVM_2, PWR_PVM_3, and PWR_PVM_4.

HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling ( uint32_t VoltageScaling )

Configure the main internal regulator output voltage.

Parameters:
VoltageScaling,: specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 80 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 26 MHz.
Note:
When moving from Range 1 to Range 2, the system frequency must be decreased to a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. When moving from Range 2 to Range 1, the system frequency can be increased to a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
When moving from Range 2 to Range 1, the API waits for VOSF flag to be cleared before returning the status. If the flag is not cleared within 50 microseconds, HAL_TIMEOUT status is reported.
Return values:
HAL Status

Definition at line 151 of file stm32l4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_VOLTAGE_SCALING_RANGE, PWR_FLAG_SETTING_DELAY_US, PWR_REGULATOR_VOLTAGE_SCALE1, and PWR_REGULATOR_VOLTAGE_SCALE2.

void HAL_PWREx_DisableBatteryCharging ( void )

Disable battery charging.

Return values:
None

Definition at line 216 of file stm32l4xx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-down state in Standby and Shutdown modes.

Note:
Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O in pull-down state in Standby and Shutdown modes.
Even if a PDy bit to reset is reserved, the other PDy bits entered as input parameter at the same time are reset.
Parameters:
GPIO,: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H to select the GPIO peripheral.
GPIONumber,: Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less I/O pins are available) or the logical OR of several of them to reset several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 506 of file stm32l4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_13, PWR_GPIO_BIT_15, PWR_GPIO_BIT_4, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_F, PWR_GPIO_G, PWR_GPIO_H, and PWR_PORTH_AVAILABLE_PINS.

HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-up state in Standby mode and Shutdown modes.

Note:
Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O in pull-up state in Standby and Shutdown modes.
Even if a PUy bit to reset is reserved, the other PUy bits entered as input parameter at the same time are reset.
Parameters:
GPIO,: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H to select the GPIO peripheral.
GPIONumber,: Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less I/O pins are available) or the logical OR of several of them to reset several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 375 of file stm32l4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_14, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_F, PWR_GPIO_G, PWR_GPIO_H, and PWR_PORTH_AVAILABLE_PINS.

void HAL_PWREx_DisableInternalWakeUpLine ( void )

Disable Internal Wake-up Line.

Return values:
None

Definition at line 281 of file stm32l4xx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode ( void )

Exit Low-power Run mode.

Note:
Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode returns HAL_TIMEOUT status). The system clock frequency can then be increased above 2 MHz.
Return values:
HAL Status

Definition at line 875 of file stm32l4xx_hal_pwr_ex.c.

References PWR_FLAG_SETTING_DELAY_US.

Referenced by HAL_PWR_EnterSLEEPMode().

void HAL_PWREx_DisablePullUpPullDownConfig ( void )

Disable pull-up and pull-down configuration.

Note:
When APC bit is cleared, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
Return values:
None

Definition at line 572 of file stm32l4xx_hal_pwr_ex.c.

void HAL_PWREx_DisablePVM1 ( void )

Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.

Return values:
None

Definition at line 619 of file stm32l4xx_hal_pwr_ex.c.

References PWR_PVM_1.

void HAL_PWREx_DisablePVM2 ( void )

Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.

Return values:
None

Definition at line 640 of file stm32l4xx_hal_pwr_ex.c.

References PWR_PVM_2.

void HAL_PWREx_DisablePVM3 ( void )

Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.

Return values:
None

Definition at line 660 of file stm32l4xx_hal_pwr_ex.c.

References PWR_PVM_3.

void HAL_PWREx_DisablePVM4 ( void )

Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.

Return values:
None

Definition at line 679 of file stm32l4xx_hal_pwr_ex.c.

References PWR_PVM_4.

void HAL_PWREx_DisableSRAM2ContentRetention ( void )

Disable SRAM2 content retention in Standby mode.

Note:
When RRS bit is reset, SRAM2 is powered off in Standby mode and its content is lost.
Return values:
None

Definition at line 597 of file stm32l4xx_hal_pwr_ex.c.

void HAL_PWREx_DisableVddIO2 ( void )

Disable VDDIO2 supply.

Return values:
None

Definition at line 260 of file stm32l4xx_hal_pwr_ex.c.

void HAL_PWREx_DisableVddUSB ( void )

Disable VDDUSB supply.

Return values:
None

Definition at line 238 of file stm32l4xx_hal_pwr_ex.c.

void HAL_PWREx_EnableBatteryCharging ( uint32_t ResistorSelection )

Enable battery charging.

When VDD is present, charge the external battery on VBAT thru an internal resistor.

Parameters:
ResistorSelection,: specifies the resistor impedance. This parameter can be one of the following values:
  • PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
Return values:
None

Definition at line 200 of file stm32l4xx_hal_pwr_ex.c.

References assert_param, and IS_PWR_BATTERY_RESISTOR_SELECT.

HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-down state in Standby and Shutdown modes.

Note:
Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in pull-down state in Standby and Shutdown modes.
This state is effective in Standby and Shutdown modes only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
The configuration is lost when exiting the Shutdown mode due to the power-on reset, maintained when exiting the Standby mode.
To avoid any conflict at Standby and Shutdown modes exits, the corresponding PUy bit of PWR_PUCRx register is cleared unless it is reserved.
Even if a PDy bit to set is reserved, the other PDy bits entered as input parameter at the same time are set.
Parameters:
GPIO,: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H to select the GPIO peripheral.
GPIONumber,: Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less I/O pins are available) or the logical OR of several of them to set several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 440 of file stm32l4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_13, PWR_GPIO_BIT_14, PWR_GPIO_BIT_15, PWR_GPIO_BIT_4, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_F, PWR_GPIO_G, PWR_GPIO_H, and PWR_PORTH_AVAILABLE_PINS.

HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-up state in Standby and Shutdown modes.

Note:
Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in pull-up state in Standby and Shutdown modes.
This state is effective in Standby and Shutdown modes only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
The configuration is lost when exiting the Shutdown mode due to the power-on reset, maintained when exiting the Standby mode.
To avoid any conflict at Standby and Shutdown modes exits, the corresponding PDy bit of PWR_PDCRx register is cleared unless it is reserved.
Even if a PUy bit to set is reserved, the other PUy bits entered as input parameter at the same time are set.
Parameters:
GPIO,: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H to select the GPIO peripheral.
GPIONumber,: Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less I/O pins are available) or the logical OR of several of them to set several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 309 of file stm32l4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_BIT_13, PWR_GPIO_BIT_14, PWR_GPIO_BIT_15, PWR_GPIO_BIT_4, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_F, PWR_GPIO_G, PWR_GPIO_H, and PWR_PORTH_AVAILABLE_PINS.

void HAL_PWREx_EnableInternalWakeUpLine ( void )

Enable Internal Wake-up Line.

Return values:
None

Definition at line 271 of file stm32l4xx_hal_pwr_ex.c.

void HAL_PWREx_EnableLowPowerRunMode ( void )

Enter Low-power Run mode.

Note:
In Low-power Run mode, all I/O pins keep the same state as in Run mode.
When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. Additionally, the clock frequency must be reduced below 2 MHz. Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
Return values:
None

Definition at line 860 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWR_EnterSLEEPMode().

void HAL_PWREx_EnablePullUpPullDownConfig ( void )

Enable pull-up and pull-down configuration.

Note:
When APC bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict when setting PUy or PDy bit.
Return values:
None

Definition at line 560 of file stm32l4xx_hal_pwr_ex.c.

void HAL_PWREx_EnablePVM1 ( void )

Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.

Return values:
None

Definition at line 610 of file stm32l4xx_hal_pwr_ex.c.

References PWR_PVM_1.

void HAL_PWREx_EnablePVM2 ( void )

Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.

Return values:
None

Definition at line 631 of file stm32l4xx_hal_pwr_ex.c.

References PWR_PVM_2.

void HAL_PWREx_EnablePVM3 ( void )

Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.

Return values:
None

Definition at line 651 of file stm32l4xx_hal_pwr_ex.c.

References PWR_PVM_3.

void HAL_PWREx_EnablePVM4 ( void )

Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.

Return values:
None

Definition at line 670 of file stm32l4xx_hal_pwr_ex.c.

References PWR_PVM_4.

void HAL_PWREx_EnableSRAM2ContentRetention ( void )

Enable SRAM2 content retention in Standby mode.

Note:
When RRS bit is set, SRAM2 is powered by the low-power regulator in Standby mode and its content is kept.
Return values:
None

Definition at line 585 of file stm32l4xx_hal_pwr_ex.c.

void HAL_PWREx_EnableVddIO2 ( void )

Enable VDDIO2 supply.

Note:
Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
Return values:
None

Definition at line 250 of file stm32l4xx_hal_pwr_ex.c.

void HAL_PWREx_EnableVddUSB ( void )

Enable VDDUSB supply.

Note:
Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
Return values:
None

Definition at line 228 of file stm32l4xx_hal_pwr_ex.c.

void HAL_PWREx_EnterSHUTDOWNMode ( void )

Enter Shutdown mode.

Note:
In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched off. The voltage regulator is disabled and Vcore domain is powered off. SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. The BOR is not available.
The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
Return values:
None

Definition at line 1064 of file stm32l4xx_hal_pwr_ex.c.

void HAL_PWREx_EnterSTOP0Mode ( uint8_t STOPEntry )

Enter Stop 0 mode.

Note:
In Stop 0 mode, main and low voltage regulators are ON.
In Stop 0 mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available.
When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set; the MSI oscillator is selected if STOPWUCK is cleared.
By keeping the internal regulator ON during Stop 0 mode, the consumption is higher although the startup time is reduced.
Parameters:
STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
Return values:
None

Definition at line 919 of file stm32l4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

Referenced by HAL_PWR_EnterSTOPMode().

void HAL_PWREx_EnterSTOP1Mode ( uint8_t STOPEntry )

Enter Stop 1 mode.

Note:
In Stop 1 mode, only low power voltage regulator is ON.
In Stop 1 mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available.
When exiting Stop 1 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set; the MSI oscillator is selected if STOPWUCK is cleared.
Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
Parameters:
STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
Return values:
None

Definition at line 970 of file stm32l4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

Referenced by HAL_PWR_EnterSTOPMode().

void HAL_PWREx_EnterSTOP2Mode ( uint8_t STOPEntry )

Enter Stop 2 mode.

Note:
In Stop 2 mode, only low power voltage regulator is ON.
In Stop 2 mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available. The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. Otherwise, Stop 1 mode is entered.
When exiting Stop 2 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set; the MSI oscillator is selected if STOPWUCK is cleared.
Parameters:
STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
Return values:
None

Definition at line 1022 of file stm32l4xx_hal_pwr_ex.c.

References assert_param, IS_PWR_STOP_ENTRY, and PWR_STOPENTRY_WFI.

uint32_t HAL_PWREx_GetVoltageRange ( void )

Return Voltage Scaling Range.

Return values:
VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)

Definition at line 124 of file stm32l4xx_hal_pwr_ex.c.

Referenced by RCC_SetFlashLatencyFromMSIRange().

void HAL_PWREx_PVD_PVM_IRQHandler ( void )

This function handles the PWR PVD/PVMx interrupt request.

Note:
This API should be called under the PVD_PVM_IRQHandler().
Return values:
None

Definition at line 1089 of file stm32l4xx_hal_pwr_ex.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, __HAL_PWR_PVM1_EXTI_CLEAR_FLAG, __HAL_PWR_PVM1_EXTI_GET_FLAG, __HAL_PWR_PVM2_EXTI_CLEAR_FLAG, __HAL_PWR_PVM2_EXTI_GET_FLAG, __HAL_PWR_PVM3_EXTI_CLEAR_FLAG, __HAL_PWR_PVM3_EXTI_GET_FLAG, __HAL_PWR_PVM4_EXTI_CLEAR_FLAG, __HAL_PWR_PVM4_EXTI_GET_FLAG, HAL_PWR_PVDCallback(), HAL_PWREx_PVM1Callback(), HAL_PWREx_PVM2Callback(), HAL_PWREx_PVM3Callback(), and HAL_PWREx_PVM4Callback().

void HAL_PWREx_PVM1Callback ( void )

PWR PVM1 interrupt callback.

Return values:
None

Definition at line 1145 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

void HAL_PWREx_PVM2Callback ( void )

PWR PVM2 interrupt callback.

Return values:
None

Definition at line 1158 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

void HAL_PWREx_PVM3Callback ( void )

PWR PVM3 interrupt callback.

Return values:
None

Definition at line 1170 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

void HAL_PWREx_PVM4Callback ( void )

PWR PVM4 interrupt callback.

Return values:
None

Definition at line 1181 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR_PVMTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVMTypeDef Struct Reference
PWR Extended Exported Types

PWR PVM configuration structure definition. More...

#include <stm32l4xx_hal_pwr_ex.h>

Data Fields

uint32_t | PVMType
uint32_t | Mode

Detailed Description

PWR PVM configuration structure definition.

Definition at line 68 of file stm32l4xx_hal_pwr_ex.h.

Field Documentation

uint32_t PWR_PVMTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVM interrupt and event mode.

Definition at line 79 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

uint32_t PWR_PVMTypeDef::PVMType

PVMType: Specifies which voltage is monitored and against which threshold. This parameter can be a value of Peripheral Voltage Monitoring type.

  • PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
  • PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
  • PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
  • PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V.

Definition at line 70 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_pwr_ex.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants

Defines
Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
PWR Extended Exported Constants

Defines

#define PWR_WUP_POLARITY_SHIFT 0x05

Define Documentation

#define PWR_WUP_POLARITY_SHIFT 0x05

Internal constant used to retrieve wakeup pin polariry

Definition at line 96 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWR_EnableWakeUpPin().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR wake-up pins

Defines
PWR wake-up pins
PWR Extended Exported Constants

Defines

#define | PWR_WAKEUP_PIN1 PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2 PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3 PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4 PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5 PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)
#define | PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)
#define | PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)
#define | PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)
#define | PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)

Define Documentation

#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1

Wakeup pin 1 (with high level polarity)

Definition at line 105 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1

Wakeup pin 1 (with high level polarity)

Definition at line 110 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)

Wakeup pin 1 (with low level polarity)

Definition at line 115 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2

Wakeup pin 2 (with high level polarity)

Definition at line 106 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2

Wakeup pin 2 (with high level polarity)

Definition at line 111 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)

Wakeup pin 2 (with low level polarity)

Definition at line 116 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3

Wakeup pin 3 (with high level polarity)

Definition at line 107 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3

Wakeup pin 3 (with high level polarity)

Definition at line 112 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)

Wakeup pin 3 (with low level polarity)

Definition at line 117 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4

Wakeup pin 4 (with high level polarity)

Definition at line 108 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4

Wakeup pin 4 (with high level polarity)

Definition at line 113 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)

Wakeup pin 4 (with low level polarity)

Definition at line 118 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5

Wakeup pin 5 (with high level polarity)

Definition at line 109 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5

Wakeup pin 5 (with high level polarity)

Definition at line 114 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)

Wakeup pin 5 (with low level polarity)

Definition at line 119 of file stm32l4xx_hal_pwr_ex.h.

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STM32L486xx HAL User Manual: Peripheral Voltage Monitoring type

Defines
Peripheral Voltage Monitoring type
PWR Extended Exported Constants

Defines

#define | PWR_PVM_1 PWR_CR2_PVME1
#define | PWR_PVM_2 PWR_CR2_PVME2
#define | PWR_PVM_3 PWR_CR2_PVME3
#define | PWR_PVM_4 PWR_CR2_PVME4

Define Documentation

#define PWR_PVM_1 PWR_CR2_PVME1

Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported)

Definition at line 129 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVM1(), and HAL_PWREx_EnablePVM1().

#define PWR_PVM_2 PWR_CR2_PVME2

Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device)

Definition at line 132 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVM2(), and HAL_PWREx_EnablePVM2().

#define PWR_PVM_3 PWR_CR2_PVME3

Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V

Definition at line 134 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVM3(), and HAL_PWREx_EnablePVM3().

#define PWR_PVM_4 PWR_CR2_PVME4

Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V

Definition at line 135 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVM4(), and HAL_PWREx_EnablePVM4().

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STM32L486xx HAL User Manual: PWR PVM interrupt and event mode

Defines
PWR PVM interrupt and event mode
PWR Extended Exported Constants

Defines

#define | PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000)
#define | PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001)
#define | PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002)
#define | PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)
#define | PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001)
#define | PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002)
#define | PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)

Define Documentation

#define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002)

Event Mode with Falling edge trigger detection

Definition at line 148 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001)

Event Mode with Rising edge trigger detection

Definition at line 147 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)

Event Mode with Rising/Falling edge trigger detection

Definition at line 149 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002)

External Interrupt Mode with Falling edge trigger detection

Definition at line 145 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001)

External Interrupt Mode with Rising edge trigger detection

Definition at line 144 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 146 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000)

basic mode is used

Definition at line 143 of file stm32l4xx_hal_pwr_ex.h.

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STM32L486xx HAL User Manual: PWR Regulator voltage scale

Defines
PWR Regulator voltage scale
PWR Extended Exported Constants

Defines

#define | PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0
#define | PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Define Documentation

#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0

Voltage scaling range 1

Definition at line 159 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), and RCC_SetFlashLatencyFromMSIRange().

#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Voltage scaling range 2

Definition at line 160 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

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STM32L486xx HAL User Manual: PWR battery charging resistor selection

Defines
PWR battery charging resistor selection
PWR Extended Exported Constants

Defines

#define | PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000)
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS

Define Documentation

#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS

VBAT charging through a 1.5 kOhms resistor

Definition at line 170 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000)

VBAT charging through a 5 kOhms resistor

Definition at line 169 of file stm32l4xx_hal_pwr_ex.h.

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STM32L486xx HAL User Manual: PWR battery charging

Defines
PWR battery charging
PWR Extended Exported Constants

Defines

#define | PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000)
#define | PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE

Define Documentation

#define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000)

Definition at line 178 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE

Definition at line 179 of file stm32l4xx_hal_pwr_ex.h.

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STM32L486xx HAL User Manual: GPIO bit number for I/O setting in standby/shutdown mode

Defines
GPIO bit number for I/O setting in standby/shutdown mode
PWR Extended Exported Constants

Defines

#define | PWR_GPIO_BIT_0 PWR_PUCRA_PA0
#define | PWR_GPIO_BIT_1 PWR_PUCRA_PA1
#define | PWR_GPIO_BIT_2 PWR_PUCRA_PA2
#define | PWR_GPIO_BIT_3 PWR_PUCRA_PA3
#define | PWR_GPIO_BIT_4 PWR_PUCRA_PA4
#define | PWR_GPIO_BIT_5 PWR_PUCRA_PA5
#define | PWR_GPIO_BIT_6 PWR_PUCRA_PA6
#define | PWR_GPIO_BIT_7 PWR_PUCRA_PA7
#define | PWR_GPIO_BIT_8 PWR_PUCRA_PA8
#define | PWR_GPIO_BIT_9 PWR_PUCRA_PA9
#define | PWR_GPIO_BIT_10 PWR_PUCRA_PA10
#define | PWR_GPIO_BIT_11 PWR_PUCRA_PA11
#define | PWR_GPIO_BIT_12 PWR_PUCRA_PA12
#define | PWR_GPIO_BIT_13 PWR_PUCRA_PA13
#define | PWR_GPIO_BIT_14 PWR_PDCRA_PA14
#define | PWR_GPIO_BIT_15 PWR_PUCRA_PA15

Define Documentation

#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0

GPIO port I/O pin 0

Definition at line 187 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1

GPIO port I/O pin 1

Definition at line 188 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10

GPIO port I/O pin 10

Definition at line 197 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11

GPIO port I/O pin 11

Definition at line 198 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12

GPIO port I/O pin 12

Definition at line 199 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13

GPIO port I/O pin 13

Definition at line 200 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_14 PWR_PDCRA_PA14

GPIO port I/O pin 14

Definition at line 201 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_15 PWR_PUCRA_PA15

GPIO port I/O pin 15

Definition at line 202 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2

GPIO port I/O pin 2

Definition at line 189 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3

GPIO port I/O pin 3

Definition at line 190 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4

GPIO port I/O pin 4

Definition at line 191 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5

GPIO port I/O pin 5

Definition at line 192 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6

GPIO port I/O pin 6

Definition at line 193 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7

GPIO port I/O pin 7

Definition at line 194 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8

GPIO port I/O pin 8

Definition at line 195 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9

GPIO port I/O pin 9

Definition at line 196 of file stm32l4xx_hal_pwr_ex.h.

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STM32L486xx HAL User Manual: GPIO port

Defines
GPIO port
PWR Extended Exported Constants

Defines

#define | PWR_GPIO_A 0x00000000
#define | PWR_GPIO_B 0x00000001
#define | PWR_GPIO_C 0x00000002
#define | PWR_GPIO_D 0x00000003
#define | PWR_GPIO_E 0x00000004
#define | PWR_GPIO_F 0x00000005
#define | PWR_GPIO_G 0x00000006
#define | PWR_GPIO_H 0x00000007

Define Documentation

#define PWR_GPIO_A 0x00000000

GPIO port A

Definition at line 210 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_B 0x00000001

GPIO port B

Definition at line 211 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_C 0x00000002

GPIO port C

Definition at line 212 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_D 0x00000003

GPIO port D

Definition at line 215 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_E 0x00000004

GPIO port E

Definition at line 216 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_F 0x00000005

GPIO port F

Definition at line 219 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_G 0x00000006

GPIO port G

Definition at line 220 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_H 0x00000007

GPIO port H

Definition at line 222 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

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STM32L486xx HAL User Manual: PWR PVM external interrupts lines

Defines
PWR PVM external interrupts lines
PWR Extended Exported Constants

Defines

#define | PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008)
#define | PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010)
#define | PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020)
#define | PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040)

Define Documentation

#define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008)

External interrupt line 35 Connected to the PVM1 EXTI Line

Definition at line 231 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010)

External interrupt line 36 Connected to the PVM2 EXTI Line

Definition at line 234 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020)

External interrupt line 37 Connected to the PVM3 EXTI Line

Definition at line 236 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040)

External interrupt line 38 Connected to the PVM4 EXTI Line

Definition at line 237 of file stm32l4xx_hal_pwr_ex.h.

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STM32L486xx HAL User Manual: PWR PVM event lines

Defines
PWR PVM event lines
PWR Extended Exported Constants

Defines

#define | PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)
#define | PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)
#define | PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)
#define | PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)

Define Documentation

#define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)

Event line 35 Connected to the PVM1 EXTI Line

Definition at line 246 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)

Event line 36 Connected to the PVM2 EXTI Line

Definition at line 249 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)

Event line 37 Connected to the PVM3 EXTI Line

Definition at line 251 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)

Event line 38 Connected to the PVM4 EXTI Line

Definition at line 252 of file stm32l4xx_hal_pwr_ex.h.

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STM32L486xx HAL User Manual: PWR Status Flags

Defines
PWR Status Flags
PWR Extended Exported Constants

Elements values convention: 0000 0000 0XXY YYYYb. More...

Defines

#define | PWR_FLAG_WUF1 ((uint32_t)0x0020)
#define | PWR_FLAG_WUF2 ((uint32_t)0x0021)
#define | PWR_FLAG_WUF3 ((uint32_t)0x0022)
#define | PWR_FLAG_WUF4 ((uint32_t)0x0023)
#define | PWR_FLAG_WUF5 ((uint32_t)0x0024)
#define | PWR_FLAG_WU PWR_SR1_WUF
#define | PWR_FLAG_SB ((uint32_t)0x0028)
#define | PWR_FLAG_WUFI ((uint32_t)0x002F)
#define | PWR_FLAG_REGLPS ((uint32_t)0x0048)
#define | PWR_FLAG_REGLPF ((uint32_t)0x0049)
#define | PWR_FLAG_VOSF ((uint32_t)0x004A)
#define | PWR_FLAG_PVDO ((uint32_t)0x004B)
#define | PWR_FLAG_PVMO1 ((uint32_t)0x004C)
#define | PWR_FLAG_PVMO2 ((uint32_t)0x004D)
#define | PWR_FLAG_PVMO3 ((uint32_t)0x004E)
#define | PWR_FLAG_PVMO4 ((uint32_t)0x004F)

Detailed Description

Elements values convention: 0000 0000 0XXY YYYYb.

  • Y YYYY : Flag position in the XX register (5 bits)
  • XX : Status register (2 bits)
    • 01: SR1 register
    • 10: SR2 register The only exception is PWR_FLAG_WU, encompassing all wake-up flags and set to PWR_SR1_WUF.

Define Documentation

#define PWR_FLAG_PVDO ((uint32_t)0x004B)

Power Voltage Detector output flag

Definition at line 279 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_PVMO1 ((uint32_t)0x004C)

Power Voltage Monitoring 1 output flag

Definition at line 281 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_PVMO2 ((uint32_t)0x004D)

Power Voltage Monitoring 2 output flag

Definition at line 284 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_PVMO3 ((uint32_t)0x004E)

Power Voltage Monitoring 3 output flag

Definition at line 286 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_PVMO4 ((uint32_t)0x004F)

Power Voltage Monitoring 4 output flag

Definition at line 287 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_REGLPF ((uint32_t)0x0049)

Low-power regulator flag

Definition at line 277 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_REGLPS ((uint32_t)0x0048)

Low-power regulator start flag

Definition at line 276 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_SB ((uint32_t)0x0028)

Standby flag

Definition at line 273 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_VOSF ((uint32_t)0x004A)

Voltage scaling flag

Definition at line 278 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_WU PWR_SR1_WUF

Encompass wakeup event on all wakeup pins

Definition at line 272 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUF1 ((uint32_t)0x0020)

Wakeup event on wakeup pin 1

Definition at line 267 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUF2 ((uint32_t)0x0021)

Wakeup event on wakeup pin 2

Definition at line 268 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUF3 ((uint32_t)0x0022)

Wakeup event on wakeup pin 3

Definition at line 269 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUF4 ((uint32_t)0x0023)

Wakeup event on wakeup pin 4

Definition at line 270 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUF5 ((uint32_t)0x0024)

Wakeup event on wakeup pin 5

Definition at line 271 of file stm32l4xx_hal_pwr_ex.h.

#define PWR_FLAG_WUFI ((uint32_t)0x002F)

Wakeup on internal wakeup line

Definition at line 274 of file stm32l4xx_hal_pwr_ex.h.

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STM32L486xx HAL User Manual: PWR Extended Exported Macros

Defines
PWR Extended Exported Macros
PWREx

Defines

#define | __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
Enable the PVM1 Event Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
Disable the PVM1 Event Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM1 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
Check whether the specified PVM1 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
Clear the PVM1 EXTI flag.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Line.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Line.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
Enable the PVM2 Event Line.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
Disable the PVM2 Event Line.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM2 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
Check whether the specified PVM2 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
Clear the PVM2 EXTI flag.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
Enable the PVM3 Event Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
Disable the PVM3 Event Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM3 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
Check whether the specified PVM3 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
Clear the PVM3 EXTI flag.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Line.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Line.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
Enable the PVM4 Event Line.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
Disable the PVM4 Event Line.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM4 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
Check whether or not the specified PVM4 EXTI interrupt flag is set.
#define | __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
Clear the PVM4 EXTI flag.
#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
Configure the main internal regulator output voltage.

Define Documentation

#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)

Clear the PVM1 EXTI flag.

Return values:
None

Definition at line 388 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)

Disable the PVM1 Event Line.

Return values:
None

Definition at line 324 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)

Disable the PVM1 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 349 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)

Disable the PVM1 Extended Interrupt Line.

Return values:
None

Definition at line 312 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)

Disable the PVM1 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 336 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
    __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVM1 Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 366 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)

Enable the PVM1 Event Line.

Return values:
None

Definition at line 318 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)

Enable the PVM1 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 342 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)

Enable the PVM1 Extended Interrupt Line.

Return values:
None

Definition at line 306 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)

Enable the PVM1 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 330 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

PVM1 EXTI line configuration: set rising & falling edge trigger.

Return values:
None

Definition at line 356 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 376 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTI_GET_FLAG ( ) (EXTI->PR2 & PWR_EXTI_LINE_PVM1)

Check whether the specified PVM1 EXTI interrupt flag is set or not.

Return values:
EXTI PVM1 Line Status.

Definition at line 382 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)

Clear the PVM2 EXTI flag.

Return values:
None

Definition at line 480 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)

Disable the PVM2 Event Line.

Return values:
None

Definition at line 416 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)

Disable the PVM2 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 441 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)

Disable the PVM2 Extended Interrupt Line.

Return values:
None

Definition at line 404 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)

Disable the PVM2 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 428 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
    __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVM2 Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 458 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)

Enable the PVM2 Event Line.

Return values:
None

Definition at line 410 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)

Enable the PVM2 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 434 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)

Enable the PVM2 Extended Interrupt Line.

Return values:
None

Definition at line 398 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)

Enable the PVM2 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 422 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

PVM2 EXTI line configuration: set rising & falling edge trigger.

Return values:
None

Definition at line 448 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 468 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM2_EXTI_GET_FLAG ( ) (EXTI->PR2 & PWR_EXTI_LINE_PVM2)

Check whether the specified PVM2 EXTI interrupt flag is set or not.

Return values:
EXTI PVM2 Line Status.

Definition at line 474 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)

Clear the PVM3 EXTI flag.

Return values:
None

Definition at line 571 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)

Disable the PVM3 Event Line.

Return values:
None

Definition at line 507 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)

Disable the PVM3 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 532 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)

Disable the PVM3 Extended Interrupt Line.

Return values:
None

Definition at line 495 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)

Disable the PVM3 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 519 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
    __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVM3 Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 549 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)

Enable the PVM3 Event Line.

Return values:
None

Definition at line 501 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)

Enable the PVM3 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 525 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)

Enable the PVM3 Extended Interrupt Line.

Return values:
None

Definition at line 489 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)

Enable the PVM3 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 513 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

PVM3 EXTI line configuration: set rising & falling edge trigger.

Return values:
None

Definition at line 539 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 559 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTI_GET_FLAG ( ) (EXTI->PR2 & PWR_EXTI_LINE_PVM3)

Check whether the specified PVM3 EXTI interrupt flag is set or not.

Return values:
EXTI PVM3 Line Status.

Definition at line 565 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)

Clear the PVM4 EXTI flag.

Return values:
None

Definition at line 662 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)

Disable the PVM4 Event Line.

Return values:
None

Definition at line 598 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)

Disable the PVM4 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 623 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)

Disable the PVM4 Extended Interrupt Line.

Return values:
None

Definition at line 586 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)

Disable the PVM4 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 610 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
    __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVM4 Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 640 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)

Enable the PVM4 Event Line.

Return values:
None

Definition at line 592 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)

Enable the PVM4 Extended Interrupt Falling Trigger.

Return values:
None

Definition at line 616 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)

Enable the PVM4 Extended Interrupt Line.

Return values:
None

Definition at line 580 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)

Enable the PVM4 Extended Interrupt Rising Trigger.

Return values:
None

Definition at line 604 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

PVM4 EXTI line configuration: set rising & falling edge trigger.

Return values:
None

Definition at line 630 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 650 of file stm32l4xx_hal_pwr_ex.h.

#define __HAL_PWR_PVM4_EXTI_GET_FLAG ( ) (EXTI->PR2 & PWR_EXTI_LINE_PVM4)

Check whether or not the specified PVM4 EXTI interrupt flag is set.

Return values:
EXTI PVM4 Line Status.

Definition at line 656 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_VOLTAGESCALING_CONFIG ( __REGULATOR__ )
Value:
do {                                                     \
                                                            __IO uint32_t tmpreg;                               \
                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
                                                            /* Delay after an RCC peripheral clock enabling */  \
                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
                                                            UNUSED(tmpreg);                                     \
                                                          } while(0)

Configure the main internal regulator output voltage.

Parameters:
__REGULATOR__,: specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 80 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 26 MHz.
Note:
This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check whether or not VOSF flag is cleared when moving from range 2 to range 1. User may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
Return values:
None

Definition at line 681 of file stm32l4xx_hal_pwr_ex.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Extended Private Macros

Defines
PWR Extended Private Macros
PWREx

Defines

#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_PVM_TYPE(TYPE)
#define | IS_PWR_PVM_MODE(MODE)
#define | IS_PWR_VOLTAGE_SCALING_RANGE(RANGE)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)
#define | IS_PWR_BATTERY_CHARGING(CHARGING)
#define | IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
#define | IS_PWR_GPIO(GPIO)

Define Documentation

#define IS_PWR_BATTERY_CHARGING ( CHARGING )
Value:
(((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))

Definition at line 748 of file stm32l4xx_hal_pwr_ex.h.

#define IS_PWR_BATTERY_RESISTOR_SELECT ( RESISTOR )
Value:
(((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))

Definition at line 745 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableBatteryCharging().

#define IS_PWR_GPIO ( GPIO )
Value:
(((GPIO) == PWR_GPIO_A) ||\
                           ((GPIO) == PWR_GPIO_B) ||\
                           ((GPIO) == PWR_GPIO_C) ||\
                           ((GPIO) == PWR_GPIO_D) ||\
                           ((GPIO) == PWR_GPIO_E) ||\
                           ((GPIO) == PWR_GPIO_F) ||\
                           ((GPIO) == PWR_GPIO_G) ||\
                           ((GPIO) == PWR_GPIO_H))

Definition at line 755 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define IS_PWR_GPIO_BIT_NUMBER ( BIT_NUMBER ) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)

Definition at line 751 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define IS_PWR_PVM_MODE ( MODE )
Value:
(((MODE) == PWR_PVM_MODE_NORMAL)              ||\
                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))

Definition at line 734 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define IS_PWR_PVM_TYPE ( TYPE )
Value:
(((TYPE) == PWR_PVM_1) ||\
                               ((TYPE) == PWR_PVM_2) ||\
                               ((TYPE) == PWR_PVM_3) ||\
                               ((TYPE) == PWR_PVM_4))

Definition at line 715 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define IS_PWR_VOLTAGE_SCALING_RANGE ( RANGE )
Value:
(((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))

Definition at line 742 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define IS_PWR_WAKEUP_PIN ( PIN )
Value:
(((PIN) == PWR_WAKEUP_PIN1) || \
                                ((PIN) == PWR_WAKEUP_PIN2) || \
                                ((PIN) == PWR_WAKEUP_PIN3) || \
                                ((PIN) == PWR_WAKEUP_PIN4) || \
                                ((PIN) == PWR_WAKEUP_PIN5) || \
                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN5_LOW))

Definition at line 698 of file stm32l4xx_hal_pwr_ex.h.

Referenced by HAL_PWR_DisableWakeUpPin(), and HAL_PWR_EnableWakeUpPin().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWREx

Modules | Defines
PWREx
STM32L4xx_HAL_Driver

PWR Extended HAL module driver. More...

Modules

PWR Extended Private Defines
PWR Extended Exported Functions
PWR Extended Exported Types
PWR Extended Exported Constants
PWR Extended Exported Macros
PWR Extended Private Macros

Defines

#define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1)

Detailed Description

PWR Extended HAL module driver.

Define Documentation

#define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1)

Definition at line 61 of file stm32l4xx_hal_pwr_ex.c.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Private Constants

Defines
QSPI Private Constants
QSPI

Defines

#define | QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)
#define | QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)
#define | QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)
#define | QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)

Define Documentation

#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)

Automatic polling mode

Definition at line 189 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)

Indirect read mode

Definition at line 188 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)

Indirect write mode

Definition at line 187 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)

Memory-mapped mode

Definition at line 190 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Private Macros

Defines
QSPI Private Macros
QSPI

Defines

#define | IS_QSPI_FUNCTIONAL_MODE(MODE)
#define | IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
#define | IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16))
#define | IS_QSPI_SSHIFT(SSHIFT)
#define | IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
#define | IS_QSPI_CS_HIGH_TIME(CSHTIME)
#define | IS_QSPI_CLOCK_MODE(CLKMODE)
#define | IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
#define | IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)
#define | IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)
#define | IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
#define | IS_QSPI_INSTRUCTION_MODE(MODE)
#define | IS_QSPI_ADDRESS_MODE(MODE)
#define | IS_QSPI_ALTERNATE_BYTES_MODE(MODE)
#define | IS_QSPI_DATA_MODE(MODE)
#define | IS_QSPI_DDR_MODE(DDR_MODE)
#define | IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
#define | IS_QSPI_SIOO_MODE(SIOO_MODE)
#define | IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define | IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
#define | IS_QSPI_MATCH_MODE(MODE)
#define | IS_QSPI_AUTOMATIC_STOP(APMS)
#define | IS_QSPI_TIMEOUT_ACTIVATION(TCEN)
#define | IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)

Define Documentation

#define IS_QSPI_ADDRESS_MODE ( MODE )
Value:
(((MODE) == QSPI_ADDRESS_NONE)    || \
                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \
                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \
                                            ((MODE) == QSPI_ADDRESS_4_LINES))

Definition at line 635 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ADDRESS_SIZE ( ADDR_SIZE )
Value:
(((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))

Definition at line 618 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ALTERNATE_BYTES_MODE ( MODE )
Value:
(((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))

Definition at line 640 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ALTERNATE_BYTES_SIZE ( SIZE )
Value:
(((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))

Definition at line 623 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_AUTOMATIC_STOP ( APMS )
Value:
(((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))

Definition at line 670 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_CLOCK_MODE ( CLKMODE )
Value:
(((CLKMODE) == QSPI_CLOCK_MODE_0) || \
                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))

Definition at line 605 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_CLOCK_PRESCALER ( PRESCALER ) ((PRESCALER) <= 0xFF)

Definition at line 587 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_CS_HIGH_TIME ( CSHTIME )
Value:
(((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))

Definition at line 596 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_DATA_MODE ( MODE )
Value:
(((MODE) == QSPI_DATA_NONE)    || \
                                            ((MODE) == QSPI_DATA_1_LINE)  || \
                                            ((MODE) == QSPI_DATA_2_LINES) || \
                                            ((MODE) == QSPI_DATA_4_LINES))

Definition at line 645 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DDR_HHC ( DDR_HHC ) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))

Definition at line 657 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DDR_MODE ( DDR_MODE )
Value:
(((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))

Definition at line 650 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DUMMY_CYCLES ( DCY ) ((DCY) <= 31)

Definition at line 628 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_FIFO_THRESHOLD ( THR ) (((THR) > 0) && ((THR) <= 16))

Definition at line 589 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_FLASH_SIZE ( FSIZE ) (((FSIZE) <= 31))

Definition at line 594 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_FUNCTIONAL_MODE ( MODE )
Value:
(((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))

Definition at line 199 of file stm32l4xx_hal_qspi.c.

Referenced by QSPI_Config().

#define IS_QSPI_INSTRUCTION ( INSTRUCTION ) ((INSTRUCTION) <= 0xFF)

Definition at line 616 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_INSTRUCTION_MODE ( MODE )
Value:
(((MODE) == QSPI_INSTRUCTION_NONE)    || \
                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))

Definition at line 630 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_INTERVAL ( INTERVAL ) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)

Definition at line 663 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_MATCH_MODE ( MODE )
Value:
(((MODE) == QSPI_MATCH_MODE_AND) || \
                                            ((MODE) == QSPI_MATCH_MODE_OR))

Definition at line 667 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_SIOO_MODE ( SIOO_MODE )
Value:
(((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))

Definition at line 660 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_SSHIFT ( SSHIFT )
Value:
(((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))

Definition at line 591 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_STATUS_BYTES_SIZE ( SIZE ) (((SIZE) >= 1) && ((SIZE) <= 4))

Definition at line 665 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_TIMEOUT_ACTIVATION ( TCEN )
Value:
(((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))

Definition at line 673 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

#define IS_QSPI_TIMEOUT_PERIOD ( PERIOD ) ((PERIOD) <= 0xFFFF)

Definition at line 676 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
QSPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
__weak void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
__weak void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Initialize the QuadSPI.
      (+) De-initialize the QuadSPI.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_DeInit ( QSPI_HandleTypeDef * hqspi )

De-Initialize the QSPI peripheral.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 337 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_DISABLE, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspDeInit(), HAL_QSPI_STATE_RESET, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Init ( QSPI_HandleTypeDef * hqspi )

Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 247 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_ENABLE, assert_param, QSPI_InitTypeDef::ChipSelectHighTime, QSPI_InitTypeDef::ClockMode, QSPI_InitTypeDef::ClockPrescaler, QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, QSPI_InitTypeDef::FlashSize, HAL_GetTick(), HAL_QPSI_TIMEOUT_DEFAULT_VALUE, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspInit(), HAL_QSPI_SetTimeout(), HAL_QSPI_STATE_READY, HAL_QSPI_STATE_RESET, QSPI_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, IS_QSPI_CLOCK_MODE, IS_QSPI_CLOCK_PRESCALER, IS_QSPI_CS_HIGH_TIME, IS_QSPI_FIFO_THRESHOLD, IS_QSPI_FLASH_SIZE, IS_QSPI_SSHIFT, QSPI_HandleTypeDef::Lock, QSPI_FLAG_BUSY, QSPI_WaitFlagStateUntilTimeout(), QSPI_InitTypeDef::SampleShifting, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

__weak void HAL_QSPI_MspDeInit ( QSPI_HandleTypeDef * hqspi )

DeInitialize the QSPI MSP.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 386 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_DeInit().

__weak void HAL_QSPI_MspInit ( QSPI_HandleTypeDef * hqspi )

Initialize the QSPI MSP.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 371 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_Init().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
QSPI Exported Functions

QSPI Transmit/Receive functions. More...

Functions

void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
__weak void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
__weak void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
__weak void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
__weak void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
__weak void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
__weak void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
__weak void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
__weak void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
__weak void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.

Detailed Description

QSPI Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Handle the interrupts.
      (+) Handle the command sequence.
      (+) Transmit data in blocking, interrupt or DMA mode.
      (+) Receive data in blocking, interrupt or DMA mode.
      (+) Manage the auto-polling functional mode.
      (+) Manage the memory-mapped functional mode.

Function Documentation

__weak void HAL_QSPI_AbortCpltCallback ( QSPI_HandleTypeDef * hqspi )

Abort completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1715 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_AutoPolling | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg,
 |  | uint32_t | Timeout
 | ) |  |

Configure the QSPI Automatic Polling Mode in blocking mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the polling configuration information.
Timeout : Timeout duration
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1410 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_AUTOMATIC_STOP_ENABLE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, and QSPI_AutoPollingTypeDef::StatusBytesSize.

HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg
 | ) |  |

Configure the QSPI Automatic Polling Mode in non-blocking mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the polling configuration information.
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1510 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_AutoPollingTypeDef::AutomaticStop, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_AUTOMATIC_STOP, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_IT_SM, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, QSPI_AutoPollingTypeDef::StatusBytesSize, and QSPI_HandleTypeDef::Timeout.

__weak void HAL_QSPI_CmdCpltCallback ( QSPI_HandleTypeDef * hqspi )

Command completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1730 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_Command | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | uint32_t | Timeout
 | ) |  |

Set the command configuration.

Parameters:
hqspi,: QSPI handle
cmd | : structure that contains the command configuration information
Timeout | : Timeout duration
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 653 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Command_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd
 | ) |  |

Set the command configuration in interrupt mode.

Parameters:
hqspi,: QSPI handle
cmd : structure that contains the command configuration information
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 742 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_IT_TC, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

__weak void HAL_QSPI_ErrorCallback ( QSPI_HandleTypeDef * hqspi )

Transfer Error callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1700 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_DMAAbortCplt().

__weak void HAL_QSPI_FifoThresholdCallback ( QSPI_HandleTypeDef * hqspi )

FIFO Threshold callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1805 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_IRQHandler ( QSPI_HandleTypeDef * hqspi )

Handle QSPI interrupt request.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 425 of file stm32l4xx_hal_qspi.c.

References __HAL_DMA_DISABLE, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_GET_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_QSPI_Abort_IT(), HAL_QSPI_AbortCpltCallback(), HAL_QSPI_CmdCpltCallback(), HAL_QSPI_ERROR_NONE, HAL_QSPI_ERROR_TRANSFER, HAL_QSPI_ErrorCallback(), HAL_QSPI_FifoThresholdCallback(), HAL_QSPI_RxCpltCallback(), HAL_QSPI_STATE_ABORT, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, HAL_QSPI_StatusMatchCallback(), HAL_QSPI_TimeOutCallback(), HAL_QSPI_TxCpltCallback(), QSPI_HandleTypeDef::hdma, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAAbortCplt(), QSPI_FLAG_FT, QSPI_FLAG_SM, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FLAG_TO, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_QSPI_MemoryMapped | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_MemoryMappedTypeDef * | cfg
 | ) |  |

Configure the Memory Mapped mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the memory mapped configuration information.
Note:
This function is used only in Memory mapped Mode
Return values:
HAL status

Definition at line 1614 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_MEM_MAPPED, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_TIMEOUT_ACTIVATION, IS_QSPI_TIMEOUT_PERIOD, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_TO, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED, QSPI_INSTRUCTION_NONE, QSPI_IT_TO, QSPI_TIMEOUT_COUNTER_ENABLE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::Timeout, QSPI_MemoryMappedTypeDef::TimeOutActivation, and QSPI_MemoryMappedTypeDef::TimeOutPeriod.

HAL_StatusTypeDef HAL_QSPI_Receive | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Timeout : Timeout duration
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 928 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_Abort(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Receive_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer.
Note:
This function is used only in Indirect Read Mode
If DMA peripheral access is configured as halfword, the number of data and the fifo threshold should be aligned on halfword
If DMA peripheral access is configured as word, the number of data and the fifo threshold should be aligned on word
Return values:
HAL status

Definition at line 1276 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, DMA_InitTypeDef::Direction, DMA_PDATAALIGN_BYTE, DMA_PDATAALIGN_HALFWORD, DMA_PDATAALIGN_WORD, DMA_PERIPH_TO_MEMORY, QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, HAL_DMA_Start_IT(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hdma, QSPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, DMA_InitTypeDef::PeriphDataAlignment, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_DMAError(), QSPI_DMARxCplt(), QSPI_DMARxHalfCplt(), QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_TE, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, QSPI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_QSPI_Receive_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1076 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, and QSPI_HandleTypeDef::State.

__weak void HAL_QSPI_RxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1745 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

__weak void HAL_QSPI_RxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Half Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1775 of file stm32l4xx_hal_qspi.c.

Referenced by QSPI_DMARxHalfCplt().

__weak void HAL_QSPI_StatusMatchCallback ( QSPI_HandleTypeDef * hqspi )

Status Match callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1820 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

__weak void HAL_QSPI_TimeOutCallback ( QSPI_HandleTypeDef * hqspi )

Timeout callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1835 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_Transmit | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Timeout : Timeout duration
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 842 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_Abort(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and QSPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_QSPI_Transmit_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with DMA.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Write Mode
If DMA peripheral access is configured as halfword, the number of data and the fifo threshold should be aligned on halfword
If DMA peripheral access is configured as word, the number of data and the fifo threshold should be aligned on word
Return values:
HAL status

Definition at line 1144 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, DMA_PDATAALIGN_BYTE, DMA_PDATAALIGN_HALFWORD, DMA_PDATAALIGN_WORD, QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, HAL_DMA_Start_IT(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hdma, QSPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, DMA_InitTypeDef::PeriphDataAlignment, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAError(), QSPI_DMATxCplt(), QSPI_DMATxHalfCplt(), QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_TE, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, QSPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_QSPI_Transmit_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with interrupt.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 1016 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and QSPI_HandleTypeDef::TxXferSize.

__weak void HAL_QSPI_TxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1760 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

__weak void HAL_QSPI_TxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Half Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1790 of file stm32l4xx_hal_qspi.c.

Referenced by QSPI_DMATxHalfCplt().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control and State functions

Functions
Peripheral Control and State functions
QSPI Exported Functions

QSPI control and State functions. More...

Functions

HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.

Detailed Description

QSPI control and State functions.

 ===============================================================================
                  ##### Peripheral Control and State functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Check in run-time the state of the driver.
      (+) Check the error code set during last operation.
      (+) Abort any operation.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_Abort ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 1893 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_GetTick(), HAL_QSPI_ERROR_DMA, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hdma, QSPI_HandleTypeDef::Instance, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_Receive(), and HAL_QSPI_Transmit().

HAL_StatusTypeDef HAL_QSPI_Abort_IT ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission (non-blocking function)

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 1946 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_ENABLE_IT, HAL_DMA_Abort_IT(), HAL_QSPI_STATE_ABORT, QSPI_HandleTypeDef::hdma, QSPI_HandleTypeDef::Instance, QSPI_DMAAbortCplt(), QSPI_FLAG_TC, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, QSPI_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_DMAError().

uint32_t HAL_QSPI_GetError ( QSPI_HandleTypeDef * hqspi )

Return the QSPI error code.

Parameters:
hqspi,: QSPI handle
Return values:
QSPI Error Code

Definition at line 1883 of file stm32l4xx_hal_qspi.c.

References QSPI_HandleTypeDef::ErrorCode.

uint32_t HAL_QSPI_GetFifoThreshold ( QSPI_HandleTypeDef * hqspi )

Get QSPI Fifo threshold.

Parameters:
hqspi,: QSPI handle.
Return values:
Fifo threshold (value between 1 and 16)

Definition at line 2033 of file stm32l4xx_hal_qspi.c.

References QSPI_HandleTypeDef::Instance.

HAL_QSPI_StateTypeDef HAL_QSPI_GetState ( QSPI_HandleTypeDef * hqspi )

Return the QSPI handle state.

Parameters:
hqspi,: QSPI handle
Return values:
HAL state

Definition at line 1872 of file stm32l4xx_hal_qspi.c.

References QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Threshold
 | ) |  |

Set QSPI Fifo threshold.

Parameters:
hqspi,: QSPI handle.
Threshold,: Threshold of the Fifo (value between 1 and 16).
Return values:
HAL status

Definition at line 2001 of file stm32l4xx_hal_qspi.c.

References QSPI_InitTypeDef::FifoThreshold, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, and QSPI_HandleTypeDef::State.

void HAL_QSPI_SetTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Timeout
 | ) |  |

Set QSPI timeout.

Parameters:
hqspi,: QSPI handle.
Timeout,: Timeout for the QSPI memory access.
Return values:
None

Definition at line 1991 of file stm32l4xx_hal_qspi.c.

References QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_Init().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Exported Functions

Modules | Functions
QSPI Exported Functions
QSPI

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

QSPI Transmit/Receive functions.

Peripheral Control and State functions

QSPI control and State functions.

Functions

HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.
void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.
HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.
static void | QSPI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process complete callback.
static void | QSPI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process complete callback.
static void | QSPI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process half complete callback.
static void | QSPI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process half complete callback.
static void | QSPI_DMAError (DMA_HandleTypeDef *hdma)
DMA QSPI communication error callback.
static void | QSPI_DMAAbortCplt (DMA_HandleTypeDef *hdma)
DMA QSPI abort complete callback.
static HAL_StatusTypeDef | QSPI_WaitFlagStateUntilTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
Wait for a flag state until timeout.
static void | QSPI_Config (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
Configure the communication registers.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_Abort ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 1893 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_GetTick(), HAL_QSPI_ERROR_DMA, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hdma, QSPI_HandleTypeDef::Instance, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_Receive(), and HAL_QSPI_Transmit().

HAL_StatusTypeDef HAL_QSPI_Abort_IT ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission (non-blocking function)

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 1946 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_ENABLE_IT, HAL_DMA_Abort_IT(), HAL_QSPI_STATE_ABORT, QSPI_HandleTypeDef::hdma, QSPI_HandleTypeDef::Instance, QSPI_DMAAbortCplt(), QSPI_FLAG_TC, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, QSPI_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_DMAError().

void HAL_QSPI_AbortCpltCallback ( QSPI_HandleTypeDef * hqspi )

Abort completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1715 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_AutoPolling | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg,
 |  | uint32_t | Timeout
 | ) |  |

Configure the QSPI Automatic Polling Mode in blocking mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the polling configuration information.
Timeout : Timeout duration
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1410 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_AUTOMATIC_STOP_ENABLE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, and QSPI_AutoPollingTypeDef::StatusBytesSize.

HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg
 | ) |  |

Configure the QSPI Automatic Polling Mode in non-blocking mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the polling configuration information.
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1510 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_AutoPollingTypeDef::AutomaticStop, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_AUTOMATIC_STOP, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_IT_SM, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, QSPI_AutoPollingTypeDef::StatusBytesSize, and QSPI_HandleTypeDef::Timeout.

void HAL_QSPI_CmdCpltCallback ( QSPI_HandleTypeDef * hqspi )

Command completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1730 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_Command | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | uint32_t | Timeout
 | ) |  |

Set the command configuration.

Parameters:
hqspi,: QSPI handle
cmd | : structure that contains the command configuration information
Timeout | : Timeout duration
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 653 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Command_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd
 | ) |  |

Set the command configuration in interrupt mode.

Parameters:
hqspi,: QSPI handle
cmd : structure that contains the command configuration information
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 742 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_IT_TC, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

HAL_StatusTypeDef HAL_QSPI_DeInit ( QSPI_HandleTypeDef * hqspi )

De-Initialize the QSPI peripheral.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 337 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_DISABLE, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspDeInit(), HAL_QSPI_STATE_RESET, and QSPI_HandleTypeDef::State.

void HAL_QSPI_ErrorCallback ( QSPI_HandleTypeDef * hqspi )

Transfer Error callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1700 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_DMAAbortCplt().

void HAL_QSPI_FifoThresholdCallback ( QSPI_HandleTypeDef * hqspi )

FIFO Threshold callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1805 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

uint32_t HAL_QSPI_GetError ( QSPI_HandleTypeDef * hqspi )

Return the QSPI error code.

Parameters:
hqspi,: QSPI handle
Return values:
QSPI Error Code

Definition at line 1883 of file stm32l4xx_hal_qspi.c.

References QSPI_HandleTypeDef::ErrorCode.

uint32_t HAL_QSPI_GetFifoThreshold ( QSPI_HandleTypeDef * hqspi )

Get QSPI Fifo threshold.

Parameters:
hqspi,: QSPI handle.
Return values:
Fifo threshold (value between 1 and 16)

Definition at line 2033 of file stm32l4xx_hal_qspi.c.

References QSPI_HandleTypeDef::Instance.

HAL_QSPI_StateTypeDef HAL_QSPI_GetState ( QSPI_HandleTypeDef * hqspi )

Return the QSPI handle state.

Parameters:
hqspi,: QSPI handle
Return values:
HAL state

Definition at line 1872 of file stm32l4xx_hal_qspi.c.

References QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Init ( QSPI_HandleTypeDef * hqspi )

Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.

Parameters:
hqspi,: QSPI handle
Return values:
HAL status

Definition at line 247 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_ENABLE, assert_param, QSPI_InitTypeDef::ChipSelectHighTime, QSPI_InitTypeDef::ClockMode, QSPI_InitTypeDef::ClockPrescaler, QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, QSPI_InitTypeDef::FlashSize, HAL_GetTick(), HAL_QPSI_TIMEOUT_DEFAULT_VALUE, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspInit(), HAL_QSPI_SetTimeout(), HAL_QSPI_STATE_READY, HAL_QSPI_STATE_RESET, QSPI_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, IS_QSPI_CLOCK_MODE, IS_QSPI_CLOCK_PRESCALER, IS_QSPI_CS_HIGH_TIME, IS_QSPI_FIFO_THRESHOLD, IS_QSPI_FLASH_SIZE, IS_QSPI_SSHIFT, QSPI_HandleTypeDef::Lock, QSPI_FLAG_BUSY, QSPI_WaitFlagStateUntilTimeout(), QSPI_InitTypeDef::SampleShifting, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::Timeout.

void HAL_QSPI_IRQHandler ( QSPI_HandleTypeDef * hqspi )

Handle QSPI interrupt request.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 425 of file stm32l4xx_hal_qspi.c.

References __HAL_DMA_DISABLE, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_GET_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_QSPI_Abort_IT(), HAL_QSPI_AbortCpltCallback(), HAL_QSPI_CmdCpltCallback(), HAL_QSPI_ERROR_NONE, HAL_QSPI_ERROR_TRANSFER, HAL_QSPI_ErrorCallback(), HAL_QSPI_FifoThresholdCallback(), HAL_QSPI_RxCpltCallback(), HAL_QSPI_STATE_ABORT, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, HAL_QSPI_StatusMatchCallback(), HAL_QSPI_TimeOutCallback(), HAL_QSPI_TxCpltCallback(), QSPI_HandleTypeDef::hdma, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAAbortCplt(), QSPI_FLAG_FT, QSPI_FLAG_SM, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FLAG_TO, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_QSPI_MemoryMapped | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_MemoryMappedTypeDef * | cfg
 | ) |  |

Configure the Memory Mapped mode.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information.
cfg,: structure that contains the memory mapped configuration information.
Note:
This function is used only in Memory mapped Mode
Return values:
HAL status

Definition at line 1614 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_MEM_MAPPED, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_HHC, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_TIMEOUT_ACTIVATION, IS_QSPI_TIMEOUT_PERIOD, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_TO, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED, QSPI_INSTRUCTION_NONE, QSPI_IT_TO, QSPI_TIMEOUT_COUNTER_ENABLE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::Timeout, QSPI_MemoryMappedTypeDef::TimeOutActivation, and QSPI_MemoryMappedTypeDef::TimeOutPeriod.

void HAL_QSPI_MspDeInit ( QSPI_HandleTypeDef * hqspi )

DeInitialize the QSPI MSP.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 386 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_DeInit().

void HAL_QSPI_MspInit ( QSPI_HandleTypeDef * hqspi )

Initialize the QSPI MSP.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 371 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_Init().

HAL_StatusTypeDef HAL_QSPI_Receive | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Timeout : Timeout duration
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 928 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_Abort(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, and QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Receive_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer.
Note:
This function is used only in Indirect Read Mode
If DMA peripheral access is configured as halfword, the number of data and the fifo threshold should be aligned on halfword
If DMA peripheral access is configured as word, the number of data and the fifo threshold should be aligned on word
Return values:
HAL status

Definition at line 1276 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, DMA_InitTypeDef::Direction, DMA_PDATAALIGN_BYTE, DMA_PDATAALIGN_HALFWORD, DMA_PDATAALIGN_WORD, DMA_PERIPH_TO_MEMORY, QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, HAL_DMA_Start_IT(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hdma, QSPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, DMA_InitTypeDef::PeriphDataAlignment, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_DMAError(), QSPI_DMARxCplt(), QSPI_DMARxHalfCplt(), QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_TE, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, QSPI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_QSPI_Receive_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1076 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::RxXferSize, and QSPI_HandleTypeDef::State.

void HAL_QSPI_RxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1745 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_RxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Half Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1775 of file stm32l4xx_hal_qspi.c.

Referenced by QSPI_DMARxHalfCplt().

HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Threshold
 | ) |  |

Set QSPI Fifo threshold.

Parameters:
hqspi,: QSPI handle.
Threshold,: Threshold of the Fifo (value between 1 and 16).
Return values:
HAL status

Definition at line 2001 of file stm32l4xx_hal_qspi.c.

References QSPI_InitTypeDef::FifoThreshold, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, and QSPI_HandleTypeDef::State.

void HAL_QSPI_SetTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Timeout
 | ) |  |

Set QSPI timeout.

Parameters:
hqspi,: QSPI handle.
Timeout,: Timeout for the QSPI memory access.
Return values:
None

Definition at line 1991 of file stm32l4xx_hal_qspi.c.

References QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_Init().

void HAL_QSPI_StatusMatchCallback ( QSPI_HandleTypeDef * hqspi )

Status Match callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1820 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_TimeOutCallback ( QSPI_HandleTypeDef * hqspi )

Timeout callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1835 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

HAL_StatusTypeDef HAL_QSPI_Transmit | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Timeout : Timeout duration
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 842 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_Abort(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_WaitFlagStateUntilTimeout(), QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and QSPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_QSPI_Transmit_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with DMA.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Write Mode
If DMA peripheral access is configured as halfword, the number of data and the fifo threshold should be aligned on halfword
If DMA peripheral access is configured as word, the number of data and the fifo threshold should be aligned on word
Return values:
HAL status

Definition at line 1144 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, DMA_PDATAALIGN_BYTE, DMA_PDATAALIGN_HALFWORD, DMA_PDATAALIGN_WORD, QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, HAL_DMA_Start_IT(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::hdma, QSPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, QSPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, DMA_InitTypeDef::PeriphDataAlignment, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAError(), QSPI_DMATxCplt(), QSPI_DMATxHalfCplt(), QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_TE, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, QSPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_QSPI_Transmit_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with interrupt.

Parameters:
hqspi,: QSPI handle
pData,: pointer to data buffer
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 1016 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, QSPI_HandleTypeDef::State, QSPI_HandleTypeDef::TxXferCount, and QSPI_HandleTypeDef::TxXferSize.

void HAL_QSPI_TxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1760 of file stm32l4xx_hal_qspi.c.

Referenced by HAL_QSPI_IRQHandler().

void HAL_QSPI_TxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Half Transfer completed callback.

Parameters:
hqspi,: QSPI handle
Return values:
None

Definition at line 1790 of file stm32l4xx_hal_qspi.c.

Referenced by QSPI_DMATxHalfCplt().

static void QSPI_Config | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | uint32_t | FunctionalMode
 | ) |  | [static]

Configure the communication registers.

Parameters:
hqspi,: QSPI handle
cmd,: structure that contains the command configuration information
FunctionalMode,: functional mode to configured This parameter can be one of the following values:
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
Return values:
None

Definition at line 2190 of file stm32l4xx_hal_qspi.c.

References QSPI_CommandTypeDef::Address, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytes, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrHoldHalfCycle, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_FUNCTIONAL_MODE, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_DATA_NONE, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED, QSPI_INSTRUCTION_NONE, and QSPI_CommandTypeDef::SIOOMode.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

static void QSPI_DMAAbortCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI abort complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2119 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, HAL_QSPI_ErrorCallback(), HAL_QSPI_STATE_ABORT, HAL_QSPI_STATE_READY, QSPI_HandleTypeDef::Instance, QSPI_FLAG_TC, QSPI_IT_TC, QSPI_HandleTypeDef::RxXferCount, QSPI_HandleTypeDef::State, and QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Abort_IT(), and HAL_QSPI_IRQHandler().

static void QSPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2099 of file stm32l4xx_hal_qspi.c.

References QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_Abort_IT(), HAL_QSPI_ERROR_DMA, QSPI_HandleTypeDef::Instance, QSPI_HandleTypeDef::RxXferCount, and QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

static void QSPI_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2047 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_ENABLE_IT, QSPI_IT_TC, and QSPI_HandleTypeDef::RxXferCount.

Referenced by HAL_QSPI_Receive_DMA().

static void QSPI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI receive process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 2075 of file stm32l4xx_hal_qspi.c.

References HAL_QSPI_RxHalfCpltCallback().

Referenced by HAL_QSPI_Receive_DMA().

static void QSPI_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2061 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_ENABLE_IT, QSPI_IT_TC, and QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Transmit_DMA().

static void QSPI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI transmit process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 2087 of file stm32l4xx_hal_qspi.c.

References HAL_QSPI_TxHalfCpltCallback().

Referenced by HAL_QSPI_Transmit_DMA().

static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Flag,
 |  | FlagStatus | State,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Wait for a flag state until timeout.

Parameters:
hqspi,: QSPI handle
Flag,: Flag checked
State,: Value of the flag expected
Timeout,: Duration of the timeout
Tickstart Tick start value
Return values:
HAL status

Definition at line 2157 of file stm32l4xx_hal_qspi.c.

References __HAL_QSPI_GET_FLAG, QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_TIMEOUT, HAL_QSPI_STATE_ERROR, and QSPI_HandleTypeDef::State.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), and HAL_QSPI_Transmit().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Exported Types

Data Structures | Enumerations
QSPI Exported Types
QSPI

Data Structures

struct | QSPI_InitTypeDef
QSPI Init structure definition. More...
struct | QSPI_HandleTypeDef
QSPI Handle Structure definition. More...
struct | QSPI_CommandTypeDef
QSPI Command structure definition. More...
struct | QSPI_AutoPollingTypeDef
QSPI Auto Polling mode configuration structure definition. More...
struct | QSPI_MemoryMappedTypeDef
QSPI Memory Mapped mode configuration structure definition. More...

Enumerations

enum HAL_QSPI_StateTypeDef {
HAL_QSPI_STATE_RESET = 0x00, HAL_QSPI_STATE_READY = 0x01, HAL_QSPI_STATE_BUSY = 0x02, HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12,
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, HAL_QSPI_STATE_ABORT = 0x08,
HAL_QSPI_STATE_ERROR = 0x04
}
HAL QSPI State structures definition. More...

Enumeration Type Documentation

enum HAL_QSPI_StateTypeDef

HAL QSPI State structures definition.

Enumerator:
HAL_QSPI_STATE_RESET

Peripheral not initialized

HAL_QSPI_STATE_READY

Peripheral initialized and ready for use

HAL_QSPI_STATE_BUSY

Peripheral in indirect mode and busy

HAL_QSPI_STATE_BUSY_INDIRECT_TX

Peripheral in indirect mode with transmission ongoing

HAL_QSPI_STATE_BUSY_INDIRECT_RX

Peripheral in indirect mode with reception ongoing

HAL_QSPI_STATE_BUSY_AUTO_POLLING

Peripheral in auto polling mode ongoing

HAL_QSPI_STATE_BUSY_MEM_MAPPED

Peripheral in memory mapped mode ongoing

HAL_QSPI_STATE_ABORT

Peripheral with abort request ongoing

HAL_QSPI_STATE_ERROR

Peripheral in error

Definition at line 95 of file stm32l4xx_hal_qspi.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_InitTypeDef Struct Reference
QSPI Exported Types

QSPI Init structure definition. More...

#include <stm32l4xx_hal_qspi.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | FifoThreshold
uint32_t | SampleShifting
uint32_t | FlashSize
uint32_t | ChipSelectHighTime
uint32_t | ClockMode

Detailed Description

QSPI Init structure definition.

Definition at line 65 of file stm32l4xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_InitTypeDef::ChipSelectHighTime

Definition at line 79 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::ClockMode

Definition at line 82 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::ClockPrescaler

Definition at line 67 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::FifoThreshold

Definition at line 69 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_Receive_DMA(), HAL_QSPI_SetFifoThreshold(), and HAL_QSPI_Transmit_DMA().

uint32_t QSPI_InitTypeDef::FlashSize

Definition at line 74 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::SampleShifting

Definition at line 71 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_qspi.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_HandleTypeDef Struct Reference
QSPI Exported Types

QSPI Handle Structure definition. More...

#include <stm32l4xx_hal_qspi.h>

Data Fields

QUADSPI_TypeDef * | Instance
QSPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
__IO uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
__IO uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdma
__IO HAL_LockTypeDef | Lock
__IO HAL_QSPI_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | Timeout

Detailed Description

QSPI Handle Structure definition.

Definition at line 111 of file stm32l4xx_hal_qspi.h.

Field Documentation

__IO uint32_t QSPI_HandleTypeDef::ErrorCode

Definition at line 124 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_GetError(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAError(), and QSPI_WaitFlagStateUntilTimeout().

DMA_HandleTypeDef* QSPI_HandleTypeDef::hdma

Definition at line 121 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

QSPI_InitTypeDef QSPI_HandleTypeDef::Init

Definition at line 114 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_Receive_DMA(), HAL_QSPI_SetFifoThreshold(), and HAL_QSPI_Transmit_DMA().

QUADSPI_TypeDef* QSPI_HandleTypeDef::Instance

Definition at line 113 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_GetFifoThreshold(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_SetFifoThreshold(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_Config(), QSPI_DMAAbortCplt(), and QSPI_DMAError().

__IO HAL_LockTypeDef QSPI_HandleTypeDef::Lock

Definition at line 122 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint8_t* QSPI_HandleTypeDef::pRxBuffPtr

Definition at line 118 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

uint8_t* QSPI_HandleTypeDef::pTxBuffPtr

Definition at line 115 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

__IO uint16_t QSPI_HandleTypeDef::RxXferCount

Definition at line 120 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), QSPI_DMAAbortCplt(), QSPI_DMAError(), and QSPI_DMARxCplt().

__IO uint16_t QSPI_HandleTypeDef::RxXferSize

Definition at line 119 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

__IO HAL_QSPI_StateTypeDef QSPI_HandleTypeDef::State

Definition at line 123 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_GetState(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_SetFifoThreshold(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), and QSPI_WaitFlagStateUntilTimeout().

uint32_t QSPI_HandleTypeDef::Timeout

Definition at line 125 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), and HAL_QSPI_SetTimeout().

__IO uint16_t QSPI_HandleTypeDef::TxXferCount

Definition at line 117 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), QSPI_DMAError(), and QSPI_DMATxCplt().

__IO uint16_t QSPI_HandleTypeDef::TxXferSize

Definition at line 116 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_qspi.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI_CommandTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_CommandTypeDef Struct Reference
QSPI Exported Types

QSPI Command structure definition. More...

#include <stm32l4xx_hal_qspi.h>

Data Fields

uint32_t | Instruction
uint32_t | Address
uint32_t | AlternateBytes
uint32_t | AddressSize
uint32_t | AlternateBytesSize
uint32_t | DummyCycles
uint32_t | InstructionMode
uint32_t | AddressMode
uint32_t | AlternateByteMode
uint32_t | DataMode
uint32_t | NbData
uint32_t | DdrMode
uint32_t | DdrHoldHalfCycle
uint32_t | SIOOMode

Detailed Description

QSPI Command structure definition.

Definition at line 131 of file stm32l4xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_CommandTypeDef::Address

Definition at line 135 of file stm32l4xx_hal_qspi.h.

Referenced by QSPI_Config().

uint32_t QSPI_CommandTypeDef::AddressMode

Definition at line 147 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AddressSize

Definition at line 139 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateByteMode

Definition at line 149 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateBytes

Definition at line 137 of file stm32l4xx_hal_qspi.h.

Referenced by QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateBytesSize

Definition at line 141 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DataMode

Definition at line 151 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DdrHoldHalfCycle

Definition at line 158 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DdrMode

Definition at line 156 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DummyCycles

Definition at line 143 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::Instruction

Definition at line 133 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::InstructionMode

Definition at line 145 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::NbData

Definition at line 153 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::SIOOMode

Definition at line 161 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_qspi.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI_AutoPollingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_AutoPollingTypeDef Struct Reference
QSPI Exported Types

QSPI Auto Polling mode configuration structure definition. More...

#include <stm32l4xx_hal_qspi.h>

Data Fields

uint32_t | Match
uint32_t | Mask
uint32_t | Interval
uint32_t | StatusBytesSize
uint32_t | MatchMode
uint32_t | AutomaticStop

Detailed Description

QSPI Auto Polling mode configuration structure definition.

Definition at line 168 of file stm32l4xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_AutoPollingTypeDef::AutomaticStop

Definition at line 180 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Interval

Definition at line 174 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Mask

Definition at line 172 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Match

Definition at line 170 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::MatchMode

Definition at line 178 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::StatusBytesSize

Definition at line 176 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_qspi.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI_MemoryMappedTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_MemoryMappedTypeDef Struct Reference
QSPI Exported Types

QSPI Memory Mapped mode configuration structure definition. More...

#include <stm32l4xx_hal_qspi.h>

Data Fields

uint32_t | TimeOutPeriod
uint32_t | TimeOutActivation

Detailed Description

QSPI Memory Mapped mode configuration structure definition.

Definition at line 187 of file stm32l4xx_hal_qspi.h.

Field Documentation

uint32_t QSPI_MemoryMappedTypeDef::TimeOutActivation

Definition at line 191 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

uint32_t QSPI_MemoryMappedTypeDef::TimeOutPeriod

Definition at line 189 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_qspi.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Error Code

Defines
QSPI Error Code
QSPI Exported Constants

Defines

#define | HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)
#define | HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002)
#define | HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004)
#define | HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008)

Define Documentation

#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004)

DMA transfer error

Definition at line 210 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), and QSPI_DMAError().

#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008)

Invalid parameters error

Definition at line 211 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 207 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)

Timeout error

Definition at line 208 of file stm32l4xx_hal_qspi.h.

Referenced by QSPI_WaitFlagStateUntilTimeout().

#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002)

Transfer error

Definition at line 209 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Sample Shifting

Defines
QSPI Sample Shifting
QSPI Exported Constants

Defines

#define | QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000)
#define | QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)

Define Documentation

#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)

1/2 clock cycle shift to sample data

Definition at line 220 of file stm32l4xx_hal_qspi.h.

#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000)

No clock cycle shift to sample data

Definition at line 219 of file stm32l4xx_hal_qspi.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI ChipSelect High Time

Defines
QSPI ChipSelect High Time
QSPI Exported Constants

Defines

#define | QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000)
#define | QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
#define | QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)

Define Documentation

#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000)

nCS stay high for at least 1 clock cycle between commands

Definition at line 228 of file stm32l4xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)

nCS stay high for at least 2 clock cycles between commands

Definition at line 229 of file stm32l4xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)

nCS stay high for at least 3 clock cycles between commands

Definition at line 230 of file stm32l4xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)

nCS stay high for at least 4 clock cycles between commands

Definition at line 231 of file stm32l4xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)

nCS stay high for at least 5 clock cycles between commands

Definition at line 232 of file stm32l4xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)

nCS stay high for at least 6 clock cycles between commands

Definition at line 233 of file stm32l4xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)

nCS stay high for at least 7 clock cycles between commands

Definition at line 234 of file stm32l4xx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)

nCS stay high for at least 8 clock cycles between commands

Definition at line 235 of file stm32l4xx_hal_qspi.h.

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STM32L486xx HAL User Manual: QSPI Clock Mode

Defines
QSPI Clock Mode
QSPI Exported Constants

Defines

#define | QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000)
#define | QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)

Define Documentation

#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000)

Clk stays low while nCS is released

Definition at line 243 of file stm32l4xx_hal_qspi.h.

#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)

Clk goes high while nCS is released

Definition at line 244 of file stm32l4xx_hal_qspi.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Address Size

Defines
QSPI Address Size
QSPI Exported Constants

Defines

#define | QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
#define | QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
#define | QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)

Define Documentation

#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)

16-bit address

Definition at line 273 of file stm32l4xx_hal_qspi.h.

#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)

24-bit address

Definition at line 274 of file stm32l4xx_hal_qspi.h.

#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)

32-bit address

Definition at line 275 of file stm32l4xx_hal_qspi.h.

#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000)

8-bit address

Definition at line 272 of file stm32l4xx_hal_qspi.h.

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STM32L486xx HAL User Manual: QSPI Alternate Bytes Size

Defines
QSPI Alternate Bytes Size
QSPI Exported Constants

Defines

#define | QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
#define | QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
#define | QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)

Define Documentation

#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)

16-bit alternate bytes

Definition at line 284 of file stm32l4xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)

24-bit alternate bytes

Definition at line 285 of file stm32l4xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)

32-bit alternate bytes

Definition at line 286 of file stm32l4xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000)

8-bit alternate bytes

Definition at line 283 of file stm32l4xx_hal_qspi.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Instruction Mode

Defines
QSPI Instruction Mode
QSPI Exported Constants

Defines

#define | QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000)
#define | QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
#define | QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
#define | QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)

Define Documentation

#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)

Instruction on a single line

Definition at line 295 of file stm32l4xx_hal_qspi.h.

#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)

Instruction on two lines

Definition at line 296 of file stm32l4xx_hal_qspi.h.

#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)

Instruction on four lines

Definition at line 297 of file stm32l4xx_hal_qspi.h.

#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000)

No instruction

Definition at line 294 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Address Mode

Defines
QSPI Address Mode
QSPI Exported Constants

Defines

#define | QSPI_ADDRESS_NONE ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
#define | QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
#define | QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)

Define Documentation

#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)

Address on a single line

Definition at line 306 of file stm32l4xx_hal_qspi.h.

#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)

Address on two lines

Definition at line 307 of file stm32l4xx_hal_qspi.h.

#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)

Address on four lines

Definition at line 308 of file stm32l4xx_hal_qspi.h.

#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000)

No address

Definition at line 305 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Alternate Bytes Mode

Defines
QSPI Alternate Bytes Mode
QSPI Exported Constants

Defines

#define | QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
#define | QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
#define | QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)

Define Documentation

#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)

Alternate bytes on a single line

Definition at line 317 of file stm32l4xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)

Alternate bytes on two lines

Definition at line 318 of file stm32l4xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)

Alternate bytes on four lines

Definition at line 319 of file stm32l4xx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000)

No alternate bytes

Definition at line 316 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Data Mode

Defines
QSPI Data Mode
QSPI Exported Constants

Defines

#define | QSPI_DATA_NONE ((uint32_t)0X00000000)
#define | QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
#define | QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
#define | QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)

Define Documentation

#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)

Data on a single line

Definition at line 328 of file stm32l4xx_hal_qspi.h.

#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)

Data on two lines

Definition at line 329 of file stm32l4xx_hal_qspi.h.

#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)

Data on four lines

Definition at line 330 of file stm32l4xx_hal_qspi.h.

#define QSPI_DATA_NONE ((uint32_t)0X00000000)

No data

Definition at line 327 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and QSPI_Config().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI DDR Mode

Defines
QSPI DDR Mode
QSPI Exported Constants

Defines

#define | QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000)
#define | QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)

Define Documentation

#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000)

Double data rate mode disabled

Definition at line 338 of file stm32l4xx_hal_qspi.h.

#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)

Double data rate mode enabled

Definition at line 339 of file stm32l4xx_hal_qspi.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI DDR Data Output Delay

Defines
QSPI DDR Data Output Delay
QSPI Exported Constants

Defines

#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000)

Define Documentation

#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000)

Delay the data output using analog delay in DDR mode

Definition at line 347 of file stm32l4xx_hal_qspi.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Send Instruction Mode

Defines
QSPI Send Instruction Mode
QSPI Exported Constants

Defines

#define | QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000)
#define | QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)

Define Documentation

#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000)

Send instruction on every transaction

Definition at line 358 of file stm32l4xx_hal_qspi.h.

#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)

Send instruction only for the first command

Definition at line 359 of file stm32l4xx_hal_qspi.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Match Mode

Defines
QSPI Match Mode
QSPI Exported Constants

Defines

#define | QSPI_MATCH_MODE_AND ((uint32_t)0x00000000)
#define | QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)

Define Documentation

#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000)

AND match mode between unmasked bits

Definition at line 367 of file stm32l4xx_hal_qspi.h.

#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)

OR match mode between unmasked bits

Definition at line 368 of file stm32l4xx_hal_qspi.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Automatic Stop

Defines
QSPI Automatic Stop
QSPI Exported Constants

Defines

#define | QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000)
#define | QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)

Define Documentation

#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000)

AutoPolling stops only with abort or QSPI disabling

Definition at line 376 of file stm32l4xx_hal_qspi.h.

#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)

AutoPolling stops as soon as there is a match

Definition at line 377 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Timeout Activation

Defines
QSPI Timeout Activation
QSPI Exported Constants

Defines

#define | QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000)
#define | QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)

Define Documentation

#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000)

Timeout counter disabled, nCS remains active

Definition at line 385 of file stm32l4xx_hal_qspi.h.

#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)

Timeout counter enabled, nCS released when timeout expires

Definition at line 386 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Flags

Defines
QSPI Flags
QSPI Exported Constants

Defines

#define | QSPI_FLAG_BUSY QUADSPI_SR_BUSY
#define | QSPI_FLAG_TO QUADSPI_SR_TOF
#define | QSPI_FLAG_SM QUADSPI_SR_SMF
#define | QSPI_FLAG_FT QUADSPI_SR_FTF
#define | QSPI_FLAG_TC QUADSPI_SR_TCF
#define | QSPI_FLAG_TE QUADSPI_SR_TEF

Define Documentation

#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY

Busy flag: operation is ongoing

Definition at line 394 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), and HAL_QSPI_MemoryMapped().

#define QSPI_FLAG_FT QUADSPI_SR_FTF

Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete

Definition at line 397 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), and HAL_QSPI_Transmit().

#define QSPI_FLAG_SM QUADSPI_SR_SMF

Status match flag: received data matches in autopolling mode

Definition at line 396 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), and HAL_QSPI_IRQHandler().

#define QSPI_FLAG_TC QUADSPI_SR_TCF

Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted

Definition at line 398 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), and QSPI_DMAAbortCplt().

#define QSPI_FLAG_TE QUADSPI_SR_TEF

Transfer error flag: invalid address is being accessed

Definition at line 399 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define QSPI_FLAG_TO QUADSPI_SR_TOF

Timeout flag: timeout occurs in memory-mapped mode

Definition at line 395 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), and HAL_QSPI_MemoryMapped().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Interrupts

Defines
QSPI Interrupts
QSPI Exported Constants

Defines

#define | QSPI_IT_TO QUADSPI_CR_TOIE
#define | QSPI_IT_SM QUADSPI_CR_SMIE
#define | QSPI_IT_FT QUADSPI_CR_FTIE
#define | QSPI_IT_TC QUADSPI_CR_TCIE
#define | QSPI_IT_TE QUADSPI_CR_TEIE

Define Documentation

#define QSPI_IT_FT QUADSPI_CR_FTIE

Interrupt on the fifo threshold flag

Definition at line 409 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_IT(), and HAL_QSPI_Transmit_IT().

#define QSPI_IT_SM QUADSPI_CR_SMIE

Interrupt on the status match flag

Definition at line 408 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling_IT(), and HAL_QSPI_IRQHandler().

#define QSPI_IT_TC QUADSPI_CR_TCIE

Interrupt on the transfer complete flag

Definition at line 410 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

#define QSPI_IT_TE QUADSPI_CR_TEIE

Interrupt on the transfer error flag

Definition at line 411 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define QSPI_IT_TO QUADSPI_CR_TOIE

Interrupt on the timeout flag

Definition at line 407 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), and HAL_QSPI_MemoryMapped().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Timeout definition

Defines
QSPI Timeout definition
QSPI Exported Constants

QSPI Timeout definition. More...

Defines

#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */

Detailed Description

QSPI Timeout definition.

Define Documentation

#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */

Definition at line 420 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Exported Macros

Defines
QSPI Exported Macros
QSPI

Defines

#define | __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
Reset QSPI handle state.
#define | __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Enable the QSPI peripheral.
#define | __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Disable the QSPI peripheral.
#define | __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Enable the specified QSPI interrupt.
#define | __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Disable the specified QSPI interrupt.
#define | __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified QSPI interrupt source is enabled or not.
#define | __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
Check whether the selected QSPI flag is set or not.
#define | __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Clears the specified QSPI's flag status.

Define Documentation

#define __HAL_QSPI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))

Clears the specified QSPI's flag status.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__FLAG__,: specifies the QSPI clear register flag that needs to be set This parameter can be one of the following values:
  • QSPI_FLAG_TO: QSPI Timeout flag
  • QSPI_FLAG_SM: QSPI Status match flag
  • QSPI_FLAG_TC: QSPI Transfer complete flag
  • QSPI_FLAG_TE: QSPI Transfer error flag
Return values:
None

Definition at line 516 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), and QSPI_DMAAbortCplt().

#define __HAL_QSPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

Disable the QSPI peripheral.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
Return values:
None

Definition at line 449 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_DeInit().

#define __HAL_QSPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

Disable the specified QSPI interrupt.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__INTERRUPT__,: specifies the QSPI interrupt source to disable. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Timeout interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
None

Definition at line 476 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), and HAL_QSPI_IRQHandler().

#define __HAL_QSPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

Enable the QSPI peripheral.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
Return values:
None

Definition at line 443 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define __HAL_QSPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

Enable the specified QSPI interrupt.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__INTERRUPT__,: specifies the QSPI interrupt source to enable. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Timeout interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
None

Definition at line 462 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

#define __HAL_QSPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)

Check whether the selected QSPI flag is set or not.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__FLAG__,: specifies the QSPI flag to check. This parameter can be one of the following values:
  • QSPI_FLAG_BUSY: QSPI Busy flag
  • QSPI_FLAG_TO: QSPI Timeout flag
  • QSPI_FLAG_SM: QSPI Status match flag
  • QSPI_FLAG_FT: QSPI FIFO threshold flag
  • QSPI_FLAG_TC: QSPI Transfer complete flag
  • QSPI_FLAG_TE: QSPI Transfer error flag
Return values:
None

Definition at line 504 of file stm32l4xx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_WaitFlagStateUntilTimeout().

#define __HAL_QSPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified QSPI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the QSPI Handle.
__INTERRUPT__,: specifies the QSPI interrupt source to check. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Timeout interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 489 of file stm32l4xx_hal_qspi.h.

#define __HAL_QSPI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)

Reset QSPI handle state.

Parameters:
__HANDLE__,: QSPI handle.
Return values:
None

Definition at line 437 of file stm32l4xx_hal_qspi.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Private Constants

Defines
RCC Private Constants
RCC

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | MSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
#define | CR_REG_INDEX ((uint32_t)1U)
#define | BDCR_REG_INDEX ((uint32_t)2U)
#define | CSR_REG_INDEX ((uint32_t)3U)
#define | RCC_FLAG_MASK ((uint32_t)0x1FU)

Define Documentation

#define BDCR_REG_INDEX ((uint32_t)2U)

Definition at line 3682 of file stm32l4xx_hal_rcc.h.

#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */

Definition at line 95 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_ClockConfig().

#define CR_REG_INDEX ((uint32_t)1U)

Definition at line 3681 of file stm32l4xx_hal_rcc.h.

#define CSR_REG_INDEX ((uint32_t)3U)

Definition at line 3683 of file stm32l4xx_hal_rcc.h.

#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

Definition at line 89 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */

Definition at line 93 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */

Definition at line 90 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */

Definition at line 92 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define MSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */

Definition at line 91 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */

Definition at line 94 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define RCC_FLAG_MASK ((uint32_t)0x1FU)

Definition at line 3688 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31U)
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
#define | IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
#define | IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define | IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
#define | IS_RCC_PLLQ_VALUE(__VALUE__)
#define | IS_RCC_PLLR_VALUE(__VALUE__)
#define | IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__)
#define | IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__)
#define | IS_RCC_MSI_CLOCK_RANGE(__RANGE__)
#define | IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__)
#define | IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_HCLK(__HCLK__)
#define | IS_RCC_PCLK(__PCLK__)
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define | IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
#define | IS_RCC_MCO1SOURCE(__SOURCE__)
#define | IS_RCC_MCODIV(__DIV__)
#define | IS_RCC_LSE_DRIVE(__DRIVE__)
#define | IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__)

Define Documentation

#define __MCO1_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 104 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_CLOCKTYPE ( __CLK__ ) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))

Definition at line 3788 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HCLK ( __HCLK__ )
Value:
(((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
                               ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \
                               ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \
                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV512))

Definition at line 3795 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HSE ( __HSE__ )
Value:
(((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
                              ((__HSE__) == RCC_HSE_BYPASS))

Definition at line 3715 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI ( __HSI__ ) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))

Definition at line 3721 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI_CALIBRATION_VALUE ( __VALUE__ ) ((__VALUE__) <= (uint32_t)31U)

Definition at line 3723 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE ( __LSE__ )
Value:
(((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
                              ((__LSE__) == RCC_LSE_BYPASS))

Definition at line 3718 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE_DRIVE ( __DRIVE__ )
Value:
(((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_HIGH))

Definition at line 3837 of file stm32l4xx_hal_rcc.h.

#define IS_RCC_LSI ( __LSI__ ) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))

Definition at line 3725 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO ( __MCOX__ ) ((__MCOX__) == RCC_MCO1)

Definition at line 3810 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO1SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE))

Definition at line 3823 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCODIV ( __DIV__ )
Value:
(((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
                                ((__DIV__) == RCC_MCODIV_16))

Definition at line 3833 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MSI ( __MSI__ ) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))

Definition at line 3727 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MSI_CLOCK_RANGE ( __RANGE__ )
Value:
(((__RANGE__) == RCC_MSIRANGE_0)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_1)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_2)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_3)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_4)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_5)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_6)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_7)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_8)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_9)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_10) || \
                                           ((__RANGE__) == RCC_MSIRANGE_11))

Definition at line 3770 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MSI_STANDBY_CLOCK_RANGE ( __RANGE__ )
Value:
(((__RANGE__) == RCC_MSIRANGE_4)  || \
                                                   ((__RANGE__) == RCC_MSIRANGE_5)  || \
                                                   ((__RANGE__) == RCC_MSIRANGE_6)  || \
                                                   ((__RANGE__) == RCC_MSIRANGE_7))

Definition at line 3783 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_StandbyMSIRangeConfig().

#define IS_RCC_MSICALIBRATION_VALUE ( __VALUE__ ) ((__VALUE__) <= (uint32_t)255U)

Definition at line 3729 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_OSCILLATORTYPE ( __OSCILLATOR__ )
Value:
(((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))

Definition at line 3707 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PCLK ( __PCLK__ )
Value:
(((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
                               ((__PCLK__) == RCC_HCLK_DIV16))

Definition at line 3801 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PLL ( __PLL__ )
Value:
(((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
                             ((__PLL__) == RCC_PLL_ON))

Definition at line 3735 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLM_VALUE ( __VALUE__ ) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))

Definition at line 3743 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLN_VALUE ( __VALUE__ ) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))

Definition at line 3745 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLP_VALUE ( __VALUE__ ) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))

Definition at line 3750 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLQ_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))

Definition at line 3753 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLR_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
                                      ((__VALUE__) == 6U) || ((__VALUE__) == 8U))

Definition at line 3756 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLSAI1CLOCKOUT_VALUE ( __VALUE__ )
Value:
(((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK)  || \
                                                  (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK)  || \
                                                  (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
                                                 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))

Definition at line 3759 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define IS_RCC_PLLSAI2CLOCKOUT_VALUE ( __VALUE__ )
Value:
(((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK)  || \
                                                  (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
                                                 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))

Definition at line 3765 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define IS_RCC_PLLSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_MSI)  || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))

Definition at line 3738 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_RTCCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)    || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)    || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))

Definition at line 3805 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_STOP_WAKEUPCLOCK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
                                             ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))

Definition at line 3842 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_WakeUpStopCLKConfig().

#define IS_RCC_SYSCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))

Definition at line 3790 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define MCO1_GPIO_PORT GPIOA

Definition at line 105 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_PIN GPIO_PIN_8

Definition at line 106 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define RCC_PLL_OSCSOURCE_CONFIG ( __HAL_RCC_PLLSOURCE__ ) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))

Definition at line 108 of file stm32l4xx_hal_rcc.c.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Private Variables

RCC Private Variables
RCC
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Private Functions

Functions
RCC Private Functions
RCC

Functions

static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange (uint32_t msirange)
Update number of Flash wait states in line with MSI range and current voltage range.

Function Documentation

static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange ( uint32_t msirange ) [static]

Update number of Flash wait states in line with MSI range and current voltage range.

Parameters:
msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
Return values:
HAL status

Definition at line 1442 of file stm32l4xx_hal_rcc.c.

References __HAL_FLASH_SET_LATENCY, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_ENABLED, FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3, HAL_PWREx_GetVoltageRange(), PWR_REGULATOR_VOLTAGE_SCALE1, RCC_MSIRANGE_10, RCC_MSIRANGE_7, and RCC_MSIRANGE_8.

Referenced by HAL_RCC_OscConfig().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RCC Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
           ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to configure the internal and external oscillators
      (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
       and APB2).

    [..] Internal/external clock and PLL configuration
         (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
             the PLL as System clock source.

         (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
             It can be used to generate the clock for the USB OTG FS (48 MHz).
             The number of flash wait states is automatically adjusted when MSI range is updated with
             HAL_RCC_OscConfig() and the MSI is used as System clock source.

         (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
             clock source.

         (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
             through the PLL as System clock source. Can be used also optionally as RTC clock source.

         (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.

         (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
           (++) The first output is used to generate the high speed system clock (up to 80MHz).
           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
           (++) The third output is used to generate an accurate clock to achieve
                high-quality audio performance on SAI interface.

         (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
           (++) The first output is used to generate SAR ADC1 clock.
           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
           (++) The Third output is used to generate an accurate clock to achieve
                high-quality audio performance on SAI interface.

         (+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks:
           (++) The first output is used to generate SAR ADC2 clock.
           (++) The second  output is used to generate an accurate clock to achieve
                high-quality audio performance on SAI interface.

         (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
            (HSE used directly or through PLL as System clock source), the System clock
             is automatically switched to HSI and an interrupt is generated if enabled.
             The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
             exception vector.

         (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
             main PLL clock (through a configurable prescaler) on PA8 pin.

    [..] System, AHB and APB busses clocks configuration
         (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
             HSE and main PLL.
             The AHB clock (HCLK) is derived from System clock through configurable
             prescaler and used to clock the CPU, memory and peripherals mapped
             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
             from AHB clock through configurable prescalers and used to clock
             the peripherals mapped on these busses. You can use
             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:

           (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or
                from an external clock mapped on the SAI_CKIN pin.
                You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
                divided by 2 to 31.
                You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
                to configure this clock.
           (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
                to work correctly, while the SDMMC1 and RNG peripherals require a frequency
                equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1
                through PLLQ divider. You have to enable the peripheral clock and use
                HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
           (+@) IWDG clock which is always the LSI clock.

         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.
             The clock source frequency should be adapted depending on the device voltage range
             as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.

Table 1. HCLK clock frequency. +-------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |-------------------------------------| | | voltage range 1 | voltage range 2 | | | 1.2 V | 1.0 V | |-----------------|------------------|------------------| |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 | |-----------------|------------------|------------------| |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 | |-----------------|------------------|------------------| |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 | |-----------------|------------------|------------------| |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 | |-----------------|------------------|------------------| |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 | +-------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t | FLatency
 | ) |  |

Initialize the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:
RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency FLASH Latency This parameter can be one of the following values:
  • FLASH_LATENCY_0 FLASH 0 Latency cycle
  • FLASH_LATENCY_1 FLASH 1 Latency cycle
  • FLASH_LATENCY_2 FLASH 2 Latency cycle
  • FLASH_LATENCY_3 FLASH 3 Latency cycle
  • FLASH_LATENCY_4 FLASH 4 Latency cycle
Note:
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this function
The MSI is used by default as system clock source after startup from Reset, wake-up from STANDBY mode. After restart from Reset, the MSI frequency is set to its default value 4 MHz.
The HSI can be selected as system clock source after from STOP modes or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source is ready.
You can use HAL_RCC_GetClockConfig() function to know which clock is currently used as system clock source.
Depending on the device voltage range, the software has to set correctly HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "Initialization/de-initialization functions")
Return values:
None

Definition at line 849 of file stm32l4xx_hal_rcc.c.

References __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_SYSCLK_SOURCE, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_InitTick(), HAL_RCC_GetSysClockFreq(), IS_FLASH_LATENCY, IS_RCC_CLOCKTYPE, IS_RCC_HCLK, IS_RCC_PCLK, IS_RCC_SYSCLKSOURCE, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_MSI, RCC_SYSCLKSOURCE_PLLCLK, RCC_ClkInitTypeDef::SYSCLKSource, and TICK_INT_PRIORITY.

void HAL_RCC_DeInit ( void )

Reset the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • MSI ON and used as system clock source
  • HSE, HSI, PLL, PLLSAI1 and PLLISAI2 OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO1 OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
None

Definition at line 261 of file stm32l4xx_hal_rcc.c.

References MSI_VALUE, and RCC_MSIRANGE_6.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Return values:
HAL status

Definition at line 326 of file stm32l4xx_hal_rcc.c.

References __HAL_RCC_GET_MSI_RANGE, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_DISABLE, __HAL_RCC_HSI_ENABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI_DISABLE, __HAL_RCC_LSI_ENABLE, __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_MSI_DISABLE, __HAL_RCC_MSI_ENABLE, __HAL_RCC_MSI_RANGE_CONFIG, __HAL_RCC_PLL_CONFIG, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PLLCLKOUT_DISABLE, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, assert_param, HAL_GetTick(), HAL_InitTick(), HAL_RCC_GetSysClockFreq(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEState, HSI48_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSI48State, HSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, IS_RCC_HSE, IS_RCC_HSI, IS_RCC_HSI_CALIBRATION_VALUE, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_MSI, IS_RCC_MSI_CLOCK_RANGE, IS_RCC_MSICALIBRATION_VALUE, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLLM_VALUE, IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLR_VALUE, IS_RCC_PLLSOURCE, RCC_OscInitTypeDef::LSEState, LSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSIState, MSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::MSICalibrationValue, RCC_OscInitTypeDef::MSIClockRange, RCC_OscInitTypeDef::MSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_DBP_TIMEOUT_VALUE, RCC_HSE_OFF, RCC_HSI48_OFF, RCC_HSI_OFF, RCC_LSE_OFF, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_MSI_OFF, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_OSCILLATORTYPE_MSI, RCC_PLL_48M1CLK, RCC_PLL_NONE, RCC_PLL_ON, RCC_PLL_SAI3CLK, RCC_PLL_SYSCLK, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_PLLSOURCE_NONE, RCC_SetFlashLatencyFromMSIRange(), and TICK_INT_PRIORITY.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCC Exported Functions

RCC clocks control functions. More...

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO pin(PA8).
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Return the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC clocks control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to:

    (+) Ouput clock to MCO pin.
    (+) Retrieve current clock frequencies.
    (+) Enable the Clock Security System.

Function Documentation

void HAL_RCC_CSSCallback ( void )

RCC Clock Security System interrupt callback.

Return values:
none

Definition at line 1417 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_EnableCSS ( void )

Enable the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
The Clock Security System can only be cleared by reset.
Return values:
None

Definition at line 1390 of file stm32l4xx_hal_rcc.c.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct | pointer to an RCC_ClkInitTypeDef structure that will be configured.
pFLatency | Pointer on the Flash Latency.
Return values:
None

Definition at line 1355 of file stm32l4xx_hal_rcc.c.

References RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, RCC_ClkInitTypeDef::ClockType, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Return the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
Return values:
HCLK frequency in Hz

Definition at line 1192 of file stm32l4xx_hal_rcc.c.

Referenced by HAL_PCD_IRQHandler(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configure the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1228 of file stm32l4xx_hal_rcc.c.

References assert_param, RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSI48State, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::MSICalibrationValue, RCC_OscInitTypeDef::MSIClockRange, RCC_OscInitTypeDef::MSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI48_OFF, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_MSI_OFF, RCC_MSI_ON, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSI, RCC_OSCILLATORTYPE_MSI, RCC_PLL_OFF, RCC_PLL_ON, RCC_PLLP_DIV17, and RCC_PLLP_DIV7.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Return the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency in Hz

Definition at line 1203 of file stm32l4xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Return the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK2 frequency in Hz

Definition at line 1215 of file stm32l4xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Return the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is MSI, function returns values based on MSI Value as defined by the MSI range.
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
(*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 1113 of file stm32l4xx_hal_rcc.c.

References __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_GET_SYSCLK_SOURCE, HSE_VALUE, HSI_VALUE, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, and RCC_PLLSOURCE_MSI.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Select the clock source to output on MCO pin(PA8).

Note:
PA8 should be configured in alternate function mode.
Parameters:
RCC_MCOx specifies the output direction for the clock source. For STM32L4xx family this parameter can have only one value:
  • RCC_MCO1 Clock source to output on MCO1 pin(PA8).
RCC_MCOSource specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
  • RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
  • RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
  • RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
  • RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
  • RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
RCC_MCODiv specifies the MCO prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 no division applied to MCO clock
  • RCC_MCODIV_2 division by 2 applied to MCO clock
  • RCC_MCODIV_4 division by 4 applied to MCO clock
  • RCC_MCODIV_8 division by 8 applied to MCO clock
  • RCC_MCODIV_16 division by 16 applied to MCO clock
Return values:
None

Definition at line 1058 of file stm32l4xx_hal_rcc.c.

References __MCO1_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_MCO, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCODIV, MCO1_GPIO_PORT, MCO1_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

Handle the RCC Clock Security System interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1400 of file stm32l4xx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CSSCallback(), and RCC_IT_CSS.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLInitTypeDef Struct Reference
RCC Exported Types

RCC PLL configuration structure definition. More...

#include <stm32l4xx_hal_rcc.h>

Data Fields

uint32_t | PLLState
uint32_t | PLLSource
uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLP
uint32_t | PLLQ
uint32_t | PLLR

Detailed Description

RCC PLL configuration structure definition.

Definition at line 65 of file stm32l4xx_hal_rcc.h.

Field Documentation

uint32_t RCC_PLLInitTypeDef::PLLM

PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 8

Definition at line 73 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLN

PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 86

Definition at line 76 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLP

PLLP: Division factor for SAI clock. This parameter must be a value of PLLP Clock Divider

Definition at line 79 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLQ

PLLQ: Division factor for SDMMC1, RNG and USB clocks. This parameter must be a value of PLLQ Clock Divider

Definition at line 82 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLR

PLLR: Division for the main system clock. User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ. This parameter must be a value of PLLR Clock Divider

Definition at line 85 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLSource

RCC_PLLSource: PLL entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 70 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLState

The new state of the PLL. This parameter can be a value of PLL Config

Definition at line 67 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rcc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC_OscInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_OscInitTypeDef Struct Reference
RCC Exported Types

RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition. More...

#include <stm32l4xx_hal_rcc.h>

Data Fields

uint32_t | OscillatorType
uint32_t | HSEState
uint32_t | LSEState
uint32_t | HSIState
uint32_t | HSICalibrationValue
uint32_t | LSIState
uint32_t | MSIState
uint32_t | MSICalibrationValue
uint32_t | MSIClockRange
uint32_t | HSI48State
RCC_PLLInitTypeDef PLL

Detailed Description

RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition.

Definition at line 94 of file stm32l4xx_hal_rcc.h.

Field Documentation

uint32_t RCC_OscInitTypeDef::HSEState

The new state of the HSE. This parameter can be a value of HSE Config

Definition at line 99 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSI48State

The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). This parameter can be a value of HSI48 Config

Definition at line 124 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSICalibrationValue

The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L47x/STM32L48x devices. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on STM32L43x/STM32L44x/STM32L49x/STM32L4Ax/ devices

Definition at line 108 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIState

The new state of the HSI. This parameter can be a value of HSI Config

Definition at line 105 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSEState

The new state of the LSE. This parameter can be a value of LSE Config

Definition at line 102 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSIState

The new state of the LSI. This parameter can be a value of LSI Config

Definition at line 112 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::MSICalibrationValue

The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 118 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::MSIClockRange

The MSI frequency range. This parameter can be a value of MSI Clock Range

Definition at line 121 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::MSIState

The new state of the MSI. This parameter can be a value of MSI Config

Definition at line 115 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::OscillatorType

The oscillators to be configured. This parameter can be a value of Oscillator Type

Definition at line 96 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL

Main PLL structure parameters

Definition at line 127 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rcc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_ClkInitTypeDef Struct Reference
RCC Exported Types

RCC System, AHB and APB busses clock configuration structure definition. More...

#include <stm32l4xx_hal_rcc.h>

Data Fields

uint32_t | ClockType
uint32_t | SYSCLKSource
uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

RCC System, AHB and APB busses clock configuration structure definition.

Definition at line 134 of file stm32l4xx_hal_rcc.h.

Field Documentation

uint32_t RCC_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB Clock Source

Definition at line 142 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1 APB2 Clock Source

Definition at line 145 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1 APB2 Clock Source

Definition at line 148 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::ClockType

The clock to be configured. This parameter can be a value of System Clock Type

Definition at line 136 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKSource

The clock source used as system clock (SYSCLK). This parameter can be a value of System Clock Source

Definition at line 139 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rcc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Timeout Values

Defines
Timeout Values
RCC Exported Constants

Defines

#define | RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Define Documentation

#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */

Definition at line 165 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Definition at line 166 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Oscillator Type

Defines
Oscillator Type
RCC Exported Constants

Defines

#define | RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
#define | RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
#define | RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
#define | RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
#define | RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
#define | RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U)

Define Documentation

#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)

HSE to configure

Definition at line 175 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)

HSI to configure

Definition at line 176 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)

LSE to configure

Definition at line 177 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)

LSI to configure

Definition at line 178 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U)

MSI to configure

Definition at line 179 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)

Oscillator configuration unchanged

Definition at line 174 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: HSE Config

Defines
HSE Config
RCC Exported Constants

Defines

#define | RCC_HSE_OFF ((uint32_t)0x00000000U)
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

Define Documentation

#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

External clock source for HSE clock

Definition at line 192 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_OFF ((uint32_t)0x00000000U)

HSE clock deactivation

Definition at line 190 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSE_ON RCC_CR_HSEON

HSE clock activation

Definition at line 191 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LSE Config

Defines
LSE Config
RCC Exported Constants

Defines

#define | RCC_LSE_OFF ((uint32_t)0x00000000U)
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Define Documentation

#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

External clock source for LSE clock

Definition at line 202 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_OFF ((uint32_t)0x00000000U)

LSE clock deactivation

Definition at line 200 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSE_ON RCC_BDCR_LSEON

LSE clock activation

Definition at line 201 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HSI Config

Defines
HSI Config
RCC Exported Constants

Defines

#define | RCC_HSI_OFF ((uint32_t)0x00000000U)
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT ((uint32_t)16)

Define Documentation

#define RCC_HSI_OFF ((uint32_t)0x00000000U)

HSI clock deactivation

Definition at line 210 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI_ON RCC_CR_HSION

HSI clock activation

Definition at line 211 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)16)

Default HSI calibration trimming value

Definition at line 213 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: LSI Config

Defines
LSI Config
RCC Exported Constants

Defines

#define | RCC_LSI_OFF ((uint32_t)0x00000000U)
#define | RCC_LSI_ON RCC_CSR_LSION

Define Documentation

#define RCC_LSI_OFF ((uint32_t)0x00000000U)

LSI clock deactivation

Definition at line 221 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSI_ON RCC_CSR_LSION

LSI clock activation

Definition at line 222 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MSI Config

Defines
MSI Config
RCC Exported Constants

Defines

#define | RCC_MSI_OFF ((uint32_t)0x00000000U)
#define | RCC_MSI_ON RCC_CR_MSION
#define | RCC_MSICALIBRATION_DEFAULT ((uint32_t)0)

Define Documentation

#define RCC_MSI_OFF ((uint32_t)0x00000000U)

MSI clock deactivation

Definition at line 230 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_MSI_ON RCC_CR_MSION

MSI clock activation

Definition at line 231 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0)

Default MSI calibration trimming value

Definition at line 233 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HSI48 Config

Defines
HSI48 Config
RCC Exported Constants

Defines

#define RCC_HSI48_OFF ((uint32_t)0x00000000U)

Define Documentation

#define RCC_HSI48_OFF ((uint32_t)0x00000000U)

HSI48 clock deactivation

Definition at line 251 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PLL Config

Defines
PLL Config
RCC Exported Constants

Defines

#define | RCC_PLL_NONE ((uint32_t)0x00000000U)
#define | RCC_PLL_OFF ((uint32_t)0x00000001U)
#define | RCC_PLL_ON ((uint32_t)0x00000002U)

Define Documentation

#define RCC_PLL_NONE ((uint32_t)0x00000000U)

PLL configuration unchanged

Definition at line 260 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_OFF ((uint32_t)0x00000001U)

PLL deactivation

Definition at line 261 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_PLL_ON ((uint32_t)0x00000002U)

PLL activation

Definition at line 262 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PLLP Clock Divider

Defines
PLLP Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLP_DIV7 ((uint32_t)0x00000007U)
#define | RCC_PLLP_DIV17 ((uint32_t)0x00000011U)

Define Documentation

#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U)

PLLP division factor = 17

Definition at line 303 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U)

PLLP division factor = 7

Definition at line 302 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PLLQ Clock Divider

Defines
PLLQ Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLQ_DIV2 ((uint32_t)0x00000002U)
#define | RCC_PLLQ_DIV4 ((uint32_t)0x00000004U)
#define | RCC_PLLQ_DIV6 ((uint32_t)0x00000006U)
#define | RCC_PLLQ_DIV8 ((uint32_t)0x00000008U)

Define Documentation

#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U)

PLLQ division factor = 2

Definition at line 312 of file stm32l4xx_hal_rcc.h.

#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U)

PLLQ division factor = 4

Definition at line 313 of file stm32l4xx_hal_rcc.h.

#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U)

PLLQ division factor = 6

Definition at line 314 of file stm32l4xx_hal_rcc.h.

#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U)

PLLQ division factor = 8

Definition at line 315 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: PLLR Clock Divider

Defines
PLLR Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLR_DIV2 ((uint32_t)0x00000002U)
#define | RCC_PLLR_DIV4 ((uint32_t)0x00000004U)
#define | RCC_PLLR_DIV6 ((uint32_t)0x00000006U)
#define | RCC_PLLR_DIV8 ((uint32_t)0x00000008U)

Define Documentation

#define RCC_PLLR_DIV2 ((uint32_t)0x00000002U)

PLLR division factor = 2

Definition at line 323 of file stm32l4xx_hal_rcc.h.

#define RCC_PLLR_DIV4 ((uint32_t)0x00000004U)

PLLR division factor = 4

Definition at line 324 of file stm32l4xx_hal_rcc.h.

#define RCC_PLLR_DIV6 ((uint32_t)0x00000006U)

PLLR division factor = 6

Definition at line 325 of file stm32l4xx_hal_rcc.h.

#define RCC_PLLR_DIV8 ((uint32_t)0x00000008U)

PLLR division factor = 8

Definition at line 326 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: PLL Clock Source

Defines
PLL Clock Source
RCC Exported Constants

Defines

#define | RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U)
#define | RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI
#define | RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

Define Documentation

#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

HSE clock selected as PLL entry clock source

Definition at line 337 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), RCCEx_PLLSAI1_Config(), and RCCEx_PLLSAI2_Config().

#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI

HSI clock selected as PLL entry clock source

Definition at line 336 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), RCCEx_PLLSAI1_Config(), and RCCEx_PLLSAI2_Config().

#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI

MSI clock selected as PLL entry clock source

Definition at line 335 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), RCCEx_PLLSAI1_Config(), and RCCEx_PLLSAI2_Config().

#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U)

No clock selected as PLL entry clock source

Definition at line 334 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisablePLLSAI1(), HAL_RCCEx_DisablePLLSAI2(), RCCEx_PLLSAI1_Config(), and RCCEx_PLLSAI2_Config().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PLL Clock Output

Defines
PLL Clock Output
RCC Exported Constants

Defines

#define | RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN
#define | RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN
#define | RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN

Define Documentation

#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN

PLL48M1CLK selection from main PLL

Definition at line 350 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN

PLLSAI3CLK selection from main PLL (for devices with PLLSAI2)

Definition at line 346 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN

PLLCLK selection from main PLL

Definition at line 351 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PLLSAI1 Clock Output

Defines
PLLSAI1 Clock Output
RCC Exported Constants

Defines

#define | RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN
#define | RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN
#define | RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN

Define Documentation

#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN

PLL48M2CLK selection from PLLSAI1

Definition at line 360 of file stm32l4xx_hal_rcc.h.

#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN

PLLADC1CLK selection from PLLSAI1

Definition at line 361 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN

PLLSAI1CLK selection from PLLSAI1

Definition at line 359 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: PLLSAI2 Clock Output

Defines
PLLSAI2 Clock Output
RCC Exported Constants

Defines

#define | RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN
#define | RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN

Define Documentation

#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN

PLLADC2CLK selection from PLLSAI2

Definition at line 372 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN

PLLSAI2CLK selection from PLLSAI2

Definition at line 371 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: MSI Clock Range

Defines
MSI Clock Range
RCC Exported Constants

Defines

#define | RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0
#define | RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1
#define | RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2
#define | RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3
#define | RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4
#define | RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5
#define | RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6
#define | RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7
#define | RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8
#define | RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9
#define | RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10
#define | RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11

Define Documentation

#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0

MSI = 100 KHz

Definition at line 382 of file stm32l4xx_hal_rcc.h.

#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1

MSI = 200 KHz

Definition at line 383 of file stm32l4xx_hal_rcc.h.

#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10

MSI = 32 MHz

Definition at line 392 of file stm32l4xx_hal_rcc.h.

Referenced by RCC_SetFlashLatencyFromMSIRange().

#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11

MSI = 48 MHz

Definition at line 393 of file stm32l4xx_hal_rcc.h.

#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2

MSI = 400 KHz

Definition at line 384 of file stm32l4xx_hal_rcc.h.

#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3

MSI = 800 KHz

Definition at line 385 of file stm32l4xx_hal_rcc.h.

#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4

MSI = 1 MHz

Definition at line 386 of file stm32l4xx_hal_rcc.h.

#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5

MSI = 2 MHz

Definition at line 387 of file stm32l4xx_hal_rcc.h.

#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6

MSI = 4 MHz

Definition at line 388 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_DeInit().

#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7

MSI = 8 MHz

Definition at line 389 of file stm32l4xx_hal_rcc.h.

Referenced by RCC_SetFlashLatencyFromMSIRange().

#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8

MSI = 16 MHz

Definition at line 390 of file stm32l4xx_hal_rcc.h.

Referenced by RCC_SetFlashLatencyFromMSIRange().

#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9

MSI = 24 MHz

Definition at line 391 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: System Clock Type

Defines
System Clock Type
RCC Exported Constants

Defines

#define | RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
#define | RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
#define | RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
#define | RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)

Define Documentation

#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)

HCLK to configure

Definition at line 402 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)

PCLK1 to configure

Definition at line 403 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)

PCLK2 to configure

Definition at line 404 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)

SYSCLK to configure

Definition at line 401 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

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STM32L486xx HAL User Manual: System Clock Source

Defines
System Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

HSE selection as system clock

Definition at line 414 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

HSI selection as system clock

Definition at line 413 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI

MSI selection as system clock

Definition at line 412 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

PLL selection as system clock

Definition at line 415 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

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STM32L486xx HAL User Manual: System Clock Source Status

Defines
System Clock Source Status
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI
#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 425 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 424 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI

MSI used as system clock

Definition at line 423 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

PLL used as system clock

Definition at line 426 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: AHB Clock Source

Defines
AHB Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

Define Documentation

#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1

SYSCLK not divided

Definition at line 434 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128

SYSCLK divided by 128

Definition at line 440 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16

SYSCLK divided by 16

Definition at line 438 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2

SYSCLK divided by 2

Definition at line 435 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256

SYSCLK divided by 256

Definition at line 441 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4

SYSCLK divided by 4

Definition at line 436 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

SYSCLK divided by 512

Definition at line 442 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64

SYSCLK divided by 64

Definition at line 439 of file stm32l4xx_hal_rcc.h.

#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8

SYSCLK divided by 8

Definition at line 437 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: APB1 APB2 Clock Source

Defines
APB1 APB2 Clock Source
RCC Exported Constants

Defines

#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

Define Documentation

#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1

HCLK not divided

Definition at line 450 of file stm32l4xx_hal_rcc.h.

#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

HCLK divided by 16

Definition at line 454 of file stm32l4xx_hal_rcc.h.

#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2

HCLK divided by 2

Definition at line 451 of file stm32l4xx_hal_rcc.h.

#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4

HCLK divided by 4

Definition at line 452 of file stm32l4xx_hal_rcc.h.

#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8

HCLK divided by 8

Definition at line 453 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: RTC Clock Source

Defines
RTC Clock Source
RCC Exported Constants

Defines

#define | RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U)
#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

Define Documentation

#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

HSE oscillator clock divided by 32 used as RTC clock

Definition at line 465 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0

LSE oscillator clock used as RTC clock

Definition at line 463 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1

LSI oscillator clock used as RTC clock

Definition at line 464 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U)

No clock used as RTC clock

Definition at line 462 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32L486xx HAL User Manual: MCO Index

Defines
MCO Index
RCC Exported Constants

Defines

#define | RCC_MCO1 ((uint32_t)0x00000000U)
#define | RCC_MCO RCC_MCO1

Define Documentation

#define RCC_MCO RCC_MCO1

MCO1 to be compliant with other families with 2 MCOs

Definition at line 474 of file stm32l4xx_hal_rcc.h.

#define RCC_MCO1 ((uint32_t)0x00000000U)

Definition at line 473 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: MCO1 Clock Source

Defines
MCO1 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U)
#define | RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1
#define | RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

Define Documentation

#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2

HSE selection as MCO1 source

Definition at line 486 of file stm32l4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)

HSI selection as MCO1 source

Definition at line 485 of file stm32l4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSE selection as MCO1 source

Definition at line 489 of file stm32l4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSI selection as MCO1 source

Definition at line 488 of file stm32l4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1

MSI selection as MCO1 source

Definition at line 484 of file stm32l4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U)

MCO1 output disabled, no clock on MCO1

Definition at line 482 of file stm32l4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)

PLLCLK selection as MCO1 source

Definition at line 487 of file stm32l4xx_hal_rcc.h.

#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0

SYSCLK selection as MCO1 source

Definition at line 483 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: MCO1 Clock Prescaler

Defines
MCO1 Clock Prescaler
RCC Exported Constants

Defines

#define | RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1
#define | RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2
#define | RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4
#define | RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8
#define | RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16

Define Documentation

#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1

MCO not divided

Definition at line 500 of file stm32l4xx_hal_rcc.h.

#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16

MCO divided by 16

Definition at line 504 of file stm32l4xx_hal_rcc.h.

#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2

MCO divided by 2

Definition at line 501 of file stm32l4xx_hal_rcc.h.

#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4

MCO divided by 4

Definition at line 502 of file stm32l4xx_hal_rcc.h.

#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8

MCO divided by 8

Definition at line 503 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: Interrupts

Defines
Interrupts
RCC Exported Constants

Defines

#define | RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
#define | RCC_IT_LSERDY RCC_CIFR_LSERDYF
#define | RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
#define | RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
#define | RCC_IT_HSERDY RCC_CIFR_HSERDYF
#define | RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
#define | RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF
#define | RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF
#define | RCC_IT_CSS RCC_CIFR_CSSF
#define | RCC_IT_LSECSS RCC_CIFR_LSECSSF

Define Documentation

#define RCC_IT_CSS RCC_CIFR_CSSF

Clock Security System Interrupt flag

Definition at line 522 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_IT_HSERDY RCC_CIFR_HSERDYF

HSE Ready Interrupt flag

Definition at line 516 of file stm32l4xx_hal_rcc.h.

#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF

HSI16 Ready Interrupt flag

Definition at line 515 of file stm32l4xx_hal_rcc.h.

#define RCC_IT_LSECSS RCC_CIFR_LSECSSF

LSE Clock Security System Interrupt flag

Definition at line 523 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS(), HAL_RCCEx_EnableLSECSS_IT(), and HAL_RCCEx_LSECSS_IRQHandler().

#define RCC_IT_LSERDY RCC_CIFR_LSERDYF

LSE Ready Interrupt flag

Definition at line 513 of file stm32l4xx_hal_rcc.h.

#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF

LSI Ready Interrupt flag

Definition at line 512 of file stm32l4xx_hal_rcc.h.

#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF

MSI Ready Interrupt flag

Definition at line 514 of file stm32l4xx_hal_rcc.h.

#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF

PLL Ready Interrupt flag

Definition at line 517 of file stm32l4xx_hal_rcc.h.

#define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF

PLLSAI1 Ready Interrupt flag

Definition at line 518 of file stm32l4xx_hal_rcc.h.

#define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF

PLLSAI2 Ready Interrupt flag

Definition at line 520 of file stm32l4xx_hal_rcc.h.

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STM32L486xx HAL User Manual: Flags

Defines
Flags
RCC Exported Constants

Elements values convention: XXXYYYYYb. More...

Defines

#define | RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY)))
#define | RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY)))
#define | RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY)))
#define | RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY)))
#define | RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY)))
#define | RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY)))
#define | RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY)))
#define | RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD)))
#define | RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))
#define | RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF)))
#define | RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF)))
#define | RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))
#define | RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))
#define | RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF)))
#define | RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))
#define | RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF)))
#define | RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF)))
#define | RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF)))

Detailed Description

Elements values convention: XXXYYYYYb.

  • YYYYY : Flag position in the register
  • XXX : Register index
    • 001: CR register
    • 010: BDCR register
    • 011: CSR register
    • 100: CRRCR register

Define Documentation

#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF)))

BOR reset flag

Definition at line 561 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF)))

Firewall reset flag

Definition at line 558 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY)))

HSE Ready flag

Definition at line 544 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY)))

HSI Ready flag

Definition at line 543 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF)))

Independent Watchdog reset flag

Definition at line 563 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF)))

Low-Power reset flag

Definition at line 565 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD)))

LSE Clock Security System Interrupt flag

Definition at line 553 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY)))

LSE Ready flag

Definition at line 552 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))

LSI Ready flag

Definition at line 556 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY)))

MSI Ready flag

Definition at line 542 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))

Option Byte Loader reset flag

Definition at line 559 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))

PIN reset flag

Definition at line 560 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY)))

PLL Ready flag

Definition at line 545 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY)))

PLLSAI1 Ready flag

Definition at line 546 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY)))

PLLSAI2 Ready flag

Definition at line 548 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF)))

Remove reset flag

Definition at line 557 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))

Software Reset flag

Definition at line 562 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF)))

Window watchdog reset flag

Definition at line 564 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LSE Drive Config

Defines
LSE Drive Config
RCC Exported Constants

Defines

#define | RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

LSE high drive capability

Definition at line 581 of file stm32l4xx_hal_rcc.h.

#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)

LSE low drive capability

Definition at line 578 of file stm32l4xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

LSE medium high drive capability

Definition at line 580 of file stm32l4xx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

LSE medium low drive capability

Definition at line 579 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Wake-Up from STOP Clock

Defines
Wake-Up from STOP Clock
RCC Exported Constants

Defines

#define | RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U)
#define | RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK

Define Documentation

#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK

HSI selection after wake-up from STOP

Definition at line 590 of file stm32l4xx_hal_rcc.h.

#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U)

MSI selection after wake-up from STOP

Definition at line 589 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB1 Peripheral Clock Enable Disable

Defines
AHB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Defines

#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_FLASH_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_TSC_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
#define | __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
#define | __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
#define | __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
#define | __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)

Detailed Description

Enable or disable the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRC_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)

Definition at line 660 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 637 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)

Definition at line 654 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 613 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)

Definition at line 656 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 621 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)

Definition at line 658 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 629 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TSC_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)

Definition at line 662 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TSC_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 645 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB2 Peripheral Clock Enable Disable

Defines
AHB2 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB2 peripheral clock. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOG_CLK_ENABLE()
#define | __HAL_RCC_GPIOH_CLK_ENABLE()
#define | __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
#define | __HAL_RCC_ADC_CLK_ENABLE()
#define | __HAL_RCC_AES_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
#define | __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
#define | __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
#define | __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
#define | __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
#define | __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
#define | __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
#define | __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)

Detailed Description

Enable or disable the AHB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)

Definition at line 813 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_ADC_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 758 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AES_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);

Definition at line 816 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AES_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 767 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)

Definition at line 785 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 676 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)

Definition at line 787 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 684 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)

Definition at line 789 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 692 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)

Definition at line 792 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 701 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)

Definition at line 796 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 711 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)

Definition at line 800 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 721 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)

Definition at line 804 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 731 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)

Definition at line 807 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 740 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)

Definition at line 819 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 776 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);

Definition at line 810 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 749 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB3 Peripheral Clock Enable Disable

Defines
AHB3 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB3 peripheral clock. More...

Defines

#define | __HAL_RCC_FMC_CLK_ENABLE()
#define | __HAL_RCC_QSPI_CLK_ENABLE()
#define | __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
#define | __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)

Detailed Description

Enable or disable the AHB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_FMC_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)

Definition at line 855 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 834 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_QSPI_CLK_DISABLE ( ) CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)

Definition at line 859 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_QSPI_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 844 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB1 Peripheral Clock Enable Disable

Defines
APB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_TIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_LCD_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_UART4_CLK_ENABLE()
#define | __HAL_RCC_UART5_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_CAN1_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_DAC1_CLK_ENABLE()
#define | __HAL_RCC_OPAMP_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_LPUART1_CLK_ENABLE()
#define | __HAL_RCC_SWPMI1_CLK_ENABLE()
#define | __HAL_RCC_LPTIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
#define | __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
#define | __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
#define | __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
#define | __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
#define | __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
#define | __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
#define | __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
#define | __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
#define | __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
#define | __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
#define | __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
#define | __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
#define | __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
#define | __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
#define | __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
#define | __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
#define | __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
#define | __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
#define | __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
#define | __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)

Detailed Description

Enable or disable the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CAN1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)

Definition at line 1181 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_CAN1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1048 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)

Definition at line 1189 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1074 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)

Definition at line 1169 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1012 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)

Definition at line 1172 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1021 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)

Definition at line 1175 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1030 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LCD_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);

Definition at line 1142 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LCD_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 929 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)

Definition at line 1193 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1090 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)

Definition at line 1199 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1114 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)

Definition at line 1195 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1098 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)

Definition at line 1191 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1082 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)

Definition at line 1187 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), HAL_RCCEx_PeriphCLKConfig(), and RCC_SetFlashLatencyFromMSIRange().

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1066 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), HAL_RCCEx_PeriphCLKConfig(), and RCC_SetFlashLatencyFromMSIRange().

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)

Definition at line 1150 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 957 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)

Definition at line 1153 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 966 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)

Definition at line 1197 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1106 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)

Definition at line 1123 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 874 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)

Definition at line 1126 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 883 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)

Definition at line 1130 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 893 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)

Definition at line 1134 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 903 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)

Definition at line 1137 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 912 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)

Definition at line 1139 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 920 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)

Definition at line 1162 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 993 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)

Definition at line 1166 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1003 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)

Definition at line 1155 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 974 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)

Definition at line 1158 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 983 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 948 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB2 Peripheral Clock Enable Disable

Defines
APB2 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_FIREWALL_CLK_ENABLE()
#define | __HAL_RCC_SDMMC1_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_TIM8_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_SAI1_CLK_ENABLE()
#define | __HAL_RCC_SAI2_CLK_ENABLE()
#define | __HAL_RCC_DFSDM1_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
#define | __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
#define | __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
#define | __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
#define | __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
#define | __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
#define | __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
#define | __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
#define | __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
#define | __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
#define | __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
#define | __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)

Detailed Description

Enable or disable the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DFSDM1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)

Definition at line 1360 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1319 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FIREWALL_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1221 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_FIREWALL_Config(), and HAL_FIREWALL_GetConfig().

#define __HAL_RCC_SAI1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)

Definition at line 1353 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1300 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)

Definition at line 1356 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1309 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)

Definition at line 1332 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1230 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)

Definition at line 1337 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1247 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)

Definition at line 1329 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1213 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_COMP_Init(), HAL_GPIO_Init(), HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

#define __HAL_RCC_TIM15_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)

Definition at line 1345 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1274 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)

Definition at line 1347 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1282 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)

Definition at line 1350 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1291 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)

Definition at line 1335 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1239 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)

Definition at line 1340 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1256 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( ) CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)

Definition at line 1343 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
                                                 __IO uint32_t tmpreg; \
                                                 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
                                                 /* Delay after an RCC peripheral clock enabling */ \
                                                 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
                                                 UNUSED(tmpreg); \
                                               } while(0)

Definition at line 1265 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB1 Peripheral Clock Enabled or Disabled Status

Defines
AHB1 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB1 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
#define | __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
#define | __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
#define | __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
#define | __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)

Detailed Description

Check whether the AHB1 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)

Definition at line 1392 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)

Definition at line 1381 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)

Definition at line 1386 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)

Definition at line 1375 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)

Definition at line 1388 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)

Definition at line 1377 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)

Definition at line 1390 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)

Definition at line 1379 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TSC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)

Definition at line 1394 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TSC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)

Definition at line 1383 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB2 Peripheral Clock Enabled or Disabled Status

Defines
AHB2 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB2 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
#define | __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
#define | __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
#define | __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
#define | __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)

Detailed Description

Check whether the AHB2 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)

Definition at line 1473 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_ADC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)

Definition at line 1436 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AES_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)

Definition at line 1476 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AES_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)

Definition at line 1439 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)

Definition at line 1445 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)

Definition at line 1408 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)

Definition at line 1447 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)

Definition at line 1410 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)

Definition at line 1449 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)

Definition at line 1412 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)

Definition at line 1452 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)

Definition at line 1415 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)

Definition at line 1456 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)

Definition at line 1419 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)

Definition at line 1460 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)

Definition at line 1423 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)

Definition at line 1464 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)

Definition at line 1427 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)

Definition at line 1467 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)

Definition at line 1430 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)

Definition at line 1479 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)

Definition at line 1442 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)

Definition at line 1470 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)

Definition at line 1433 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB3 Peripheral Clock Enabled or Disabled Status

Defines
AHB3 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB3 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
#define | __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
#define | __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
#define | __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)

Detailed Description

Check whether the AHB3 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_FMC_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)

Definition at line 1502 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FMC_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)

Definition at line 1494 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_QSPI_IS_CLK_DISABLED ( ) (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)

Definition at line 1506 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_QSPI_IS_CLK_ENABLED ( ) (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)

Definition at line 1498 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB1 Peripheral Clock Enabled or Disabled Status

Defines
APB1 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the APB1 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
#define | __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
#define | __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
#define | __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
#define | __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
#define | __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
#define | __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
#define | __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
#define | __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
#define | __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
#define | __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
#define | __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
#define | __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
#define | __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
#define | __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)

Detailed Description

Check whether the APB1 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CAN1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)

Definition at line 1662 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_CAN1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)

Definition at line 1581 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)

Definition at line 1670 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)

Definition at line 1589 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)

Definition at line 1650 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)

Definition at line 1569 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)

Definition at line 1653 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)

Definition at line 1572 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)

Definition at line 1656 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)

Definition at line 1575 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LCD_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)

Definition at line 1621 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LCD_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)

Definition at line 1540 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)

Definition at line 1674 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)

Definition at line 1593 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)

Definition at line 1680 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)

Definition at line 1599 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)

Definition at line 1676 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)

Definition at line 1595 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)

Definition at line 1672 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)

Definition at line 1591 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)

Definition at line 1668 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PWR_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)

Definition at line 1587 of file stm32l4xx_hal_rcc.h.

Referenced by RCC_SetFlashLatencyFromMSIRange().

#define __HAL_RCC_SPI2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)

Definition at line 1631 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)

Definition at line 1550 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)

Definition at line 1634 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)

Definition at line 1553 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)

Definition at line 1678 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)

Definition at line 1597 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)

Definition at line 1602 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)

Definition at line 1521 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)

Definition at line 1605 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)

Definition at line 1524 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)

Definition at line 1609 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)

Definition at line 1528 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)

Definition at line 1613 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)

Definition at line 1532 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)

Definition at line 1616 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)

Definition at line 1535 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)

Definition at line 1618 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)

Definition at line 1537 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)

Definition at line 1643 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)

Definition at line 1562 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART5_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)

Definition at line 1647 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART5_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)

Definition at line 1566 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)

Definition at line 1636 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)

Definition at line 1555 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)

Definition at line 1639 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)

Definition at line 1558 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)

Definition at line 1628 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)

Definition at line 1547 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB2 Peripheral Clock Enabled or Disabled Status

Defines
APB2 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the APB2 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
#define | __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
#define | __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
#define | __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
#define | __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
#define | __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
#define | __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
#define | __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
#define | __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
#define | __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)

Detailed Description

Check whether the APB2 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)

Definition at line 1762 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)

Definition at line 1727 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)

Definition at line 1696 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)

Definition at line 1755 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)

Definition at line 1720 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI2_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)

Definition at line 1758 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI2_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)

Definition at line 1723 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)

Definition at line 1734 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)

Definition at line 1699 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)

Definition at line 1739 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)

Definition at line 1704 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)

Definition at line 1731 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)

Definition at line 1694 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)

Definition at line 1747 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)

Definition at line 1712 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)

Definition at line 1749 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)

Definition at line 1714 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)

Definition at line 1752 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)

Definition at line 1717 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)

Definition at line 1737 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)

Definition at line 1702 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)

Definition at line 1742 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)

Definition at line 1707 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_DISABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)

Definition at line 1745 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_ENABLED ( ) (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)

Definition at line 1710 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB1 Peripheral Force Release Reset

Defines
AHB1 Peripheral Force Release Reset
RCC Exported Macros

Force or release AHB1 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
#define | __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
#define | __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
#define | __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
#define | __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
#define | __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
#define | __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
#define | __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
#define | __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
#define | __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
#define | __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)

Detailed Description

Force or release AHB1 peripheral reset.

Define Documentation

#define __HAL_RCC_AHB1_FORCE_RESET ( ) WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)

Definition at line 1773 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB1_RELEASE_RESET ( ) WRITE_REG(RCC->AHB1RSTR, 0x00000000U)

Definition at line 1786 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_CRC_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)

Definition at line 1781 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_CRC_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)

Definition at line 1794 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)

Definition at line 1775 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)

Definition at line 1788 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)

Definition at line 1777 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)

Definition at line 1790 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)

Definition at line 1779 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)

Definition at line 1792 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TSC_FORCE_RESET ( ) SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)

Definition at line 1783 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TSC_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)

Definition at line 1796 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB2 Peripheral Force Release Reset

Defines
AHB2 Peripheral Force Release Reset
RCC Exported Macros

Force or release AHB2 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
#define | __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
#define | __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
#define | __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
#define | __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
#define | __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
#define | __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
#define | __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
#define | __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
#define | __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)

Detailed Description

Force or release AHB2 peripheral reset.

Define Documentation

#define __HAL_RCC_ADC_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)

Definition at line 1836 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_ADC_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)

Definition at line 1875 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AES_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)

Definition at line 1839 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AES_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)

Definition at line 1878 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AHB2_FORCE_RESET ( ) WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)

Definition at line 1806 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB2_RELEASE_RESET ( ) WRITE_REG(RCC->AHB2RSTR, 0x00000000U)

Definition at line 1845 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_GPIOA_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)

Definition at line 1808 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)

Definition at line 1847 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)

Definition at line 1810 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)

Definition at line 1849 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)

Definition at line 1812 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)

Definition at line 1851 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)

Definition at line 1815 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)

Definition at line 1854 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)

Definition at line 1819 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)

Definition at line 1858 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)

Definition at line 1823 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)

Definition at line 1862 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)

Definition at line 1827 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)

Definition at line 1866 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)

Definition at line 1830 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)

Definition at line 1869 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RNG_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)

Definition at line 1842 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RNG_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)

Definition at line 1881 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USB_OTG_FS_FORCE_RESET ( ) SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)

Definition at line 1833 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)

Definition at line 1872 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB3 Peripheral Force Release Reset

Defines
AHB3 Peripheral Force Release Reset
RCC Exported Macros

Force or release AHB3 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
#define | __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
#define | __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
#define | __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
#define | __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)

Detailed Description

Force or release AHB3 peripheral reset.

Define Documentation

#define __HAL_RCC_AHB3_FORCE_RESET ( ) WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)

Definition at line 1891 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB3_RELEASE_RESET ( ) WRITE_REG(RCC->AHB3RSTR, 0x00000000U)

Definition at line 1902 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_FMC_FORCE_RESET ( ) SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)

Definition at line 1894 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FMC_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)

Definition at line 1905 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_QSPI_FORCE_RESET ( ) SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)

Definition at line 1898 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_QSPI_RELEASE_RESET ( ) CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)

Definition at line 1909 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB1 Peripheral Force Release Reset

Defines
APB1 Peripheral Force Release Reset
RCC Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
#define | __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
#define | __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
#define | __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
#define | __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
#define | __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
#define | __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
#define | __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
#define | __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
#define | __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
#define | __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
#define | __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
#define | __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
#define | __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
#define | __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
#define | __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
#define | __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
#define | __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
#define | __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
#define | __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
#define | __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
#define | __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
#define | __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
#define | __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
#define | __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
#define | __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
#define | __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
#define | __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
#define | __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
#define | __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
#define | __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
#define | __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
#define | __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
#define | __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
#define | __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
#define | __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_APB1_FORCE_RESET ( ) WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)

Definition at line 1920 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1_RELEASE_RESET ( ) WRITE_REG(RCC->APB1RSTR1, 0x00000000U)

Definition at line 1997 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_CAN1_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)

Definition at line 1976 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_CAN1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)

Definition at line 2053 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)

Definition at line 1984 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)

Definition at line 2061 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)

Definition at line 1964 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)

Definition at line 2041 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)

Definition at line 1967 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)

Definition at line 2044 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)

Definition at line 1970 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)

Definition at line 2047 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LCD_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)

Definition at line 1941 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LCD_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)

Definition at line 2018 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)

Definition at line 1988 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)

Definition at line 2065 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)

Definition at line 1994 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)

Definition at line 2071 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)

Definition at line 1990 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)

Definition at line 2067 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)

Definition at line 1986 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)

Definition at line 2063 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PWR_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)

Definition at line 1982 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_PWR_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)

Definition at line 2059 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_SPI2_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)

Definition at line 1945 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)

Definition at line 2022 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)

Definition at line 1948 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)

Definition at line 2025 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)

Definition at line 1992 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)

Definition at line 2069 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)

Definition at line 1922 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)

Definition at line 1999 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)

Definition at line 1925 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)

Definition at line 2002 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)

Definition at line 1929 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)

Definition at line 2006 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)

Definition at line 1933 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)

Definition at line 2010 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)

Definition at line 1936 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)

Definition at line 2013 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)

Definition at line 1938 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)

Definition at line 2015 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART4_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)

Definition at line 1957 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART4_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)

Definition at line 2034 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART5_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)

Definition at line 1961 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART5_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)

Definition at line 2038 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART2_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)

Definition at line 1950 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)

Definition at line 2027 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART3_FORCE_RESET ( ) SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)

Definition at line 1953 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART3_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)

Definition at line 2030 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB2 Peripheral Force Release Reset

Defines
APB2 Peripheral Force Release Reset
RCC Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
#define | __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
#define | __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
#define | __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
#define | __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_APB2_FORCE_RESET ( ) WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)

Definition at line 2081 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_RELEASE_RESET ( ) WRITE_REG(RCC->APB2RSTR, 0x00000000U)

Definition at line 2118 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_DFSDM1_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)

Definition at line 2114 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)

Definition at line 2151 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)

Definition at line 2107 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)

Definition at line 2144 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI2_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)

Definition at line 2110 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI2_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)

Definition at line 2147 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)

Definition at line 2086 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)

Definition at line 2123 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)

Definition at line 2091 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)

Definition at line 2128 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)

Definition at line 2083 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)

Definition at line 2120 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)

Definition at line 2099 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)

Definition at line 2136 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)

Definition at line 2101 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)

Definition at line 2138 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)

Definition at line 2104 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)

Definition at line 2141 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)

Definition at line 2089 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)

Definition at line 2126 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)

Definition at line 2094 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)

Definition at line 2131 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART1_FORCE_RESET ( ) SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)

Definition at line 2097 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART1_RELEASE_RESET ( ) CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)

Definition at line 2134 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB1 Peripheral Clock Sleep Enable Disable

Defines
AHB1 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
#define | __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
#define | __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)

Detailed Description

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)

Definition at line 2188 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)

Definition at line 2175 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)

Definition at line 2180 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)

Definition at line 2167 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)

Definition at line 2182 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)

Definition at line 2169 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)

Definition at line 2184 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)

Definition at line 2171 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)

Definition at line 2186 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)

Definition at line 2173 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)

Definition at line 2190 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)

Definition at line 2177 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB2 Peripheral Clock Sleep Enable Disable

Defines
AHB2 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
#define | __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
#define | __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
#define | __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
#define | __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
#define | __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
#define | __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)

Detailed Description

Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)

Definition at line 2274 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)

Definition at line 2235 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AES_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)

Definition at line 2277 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AES_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)

Definition at line 2238 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)

Definition at line 2244 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)

Definition at line 2205 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)

Definition at line 2246 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)

Definition at line 2207 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)

Definition at line 2248 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)

Definition at line 2209 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)

Definition at line 2251 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)

Definition at line 2212 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)

Definition at line 2255 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)

Definition at line 2216 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)

Definition at line 2259 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)

Definition at line 2220 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)

Definition at line 2263 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)

Definition at line 2224 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)

Definition at line 2266 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)

Definition at line 2227 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)

Definition at line 2280 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)

Definition at line 2241 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)

Definition at line 2268 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)

Definition at line 2229 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)

Definition at line 2271 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)

Definition at line 2232 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB3 Peripheral Clock Sleep Enable Disable

Defines
AHB3 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
#define | __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
#define | __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
#define | __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)

Detailed Description

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)

Definition at line 2309 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)

Definition at line 2300 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)

Definition at line 2305 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)

Definition at line 2296 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB1 Peripheral Clock Sleep Enable Disable

Defines
APB1 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
#define | __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
#define | __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
#define | __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
#define | __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)

Detailed Description

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)

Definition at line 2466 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)

Definition at line 2385 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)

Definition at line 2474 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)

Definition at line 2393 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)

Definition at line 2454 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)

Definition at line 2373 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)

Definition at line 2457 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)

Definition at line 2376 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)

Definition at line 2460 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)

Definition at line 2379 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)

Definition at line 2425 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)

Definition at line 2344 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)

Definition at line 2478 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)

Definition at line 2397 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)

Definition at line 2484 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)

Definition at line 2403 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)

Definition at line 2480 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)

Definition at line 2399 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)

Definition at line 2476 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)

Definition at line 2395 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)

Definition at line 2472 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)

Definition at line 2391 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)

Definition at line 2435 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)

Definition at line 2354 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)

Definition at line 2438 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)

Definition at line 2357 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)

Definition at line 2482 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)

Definition at line 2401 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)

Definition at line 2406 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)

Definition at line 2325 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)

Definition at line 2409 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)

Definition at line 2328 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)

Definition at line 2413 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)

Definition at line 2332 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)

Definition at line 2417 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)

Definition at line 2336 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)

Definition at line 2420 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)

Definition at line 2339 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)

Definition at line 2422 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)

Definition at line 2341 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)

Definition at line 2447 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)

Definition at line 2366 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)

Definition at line 2451 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)

Definition at line 2370 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)

Definition at line 2440 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)

Definition at line 2359 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)

Definition at line 2443 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)

Definition at line 2362 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)

Definition at line 2432 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)

Definition at line 2351 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB2 Peripheral Clock Sleep Enable Disable

Defines
APB2 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)

Detailed Description

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)

Definition at line 2565 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)

Definition at line 2530 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)

Definition at line 2558 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)

Definition at line 2523 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)

Definition at line 2561 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)

Definition at line 2526 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)

Definition at line 2537 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)

Definition at line 2502 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)

Definition at line 2542 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)

Definition at line 2507 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)

Definition at line 2534 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)

Definition at line 2499 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)

Definition at line 2550 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)

Definition at line 2515 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)

Definition at line 2552 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)

Definition at line 2517 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)

Definition at line 2555 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)

Definition at line 2520 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)

Definition at line 2540 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)

Definition at line 2505 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)

Definition at line 2545 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)

Definition at line 2510 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE ( ) CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)

Definition at line 2548 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE ( ) SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)

Definition at line 2513 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB1 Peripheral Clock Sleep Enabled or Disabled Status

Defines
AHB1 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
#define | __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
#define | __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)

Detailed Description

Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)

Definition at line 2602 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)

Definition at line 2589 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)

Definition at line 2594 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)

Definition at line 2581 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)

Definition at line 2596 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)

Definition at line 2583 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)

Definition at line 2598 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)

Definition at line 2585 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)

Definition at line 2600 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)

Definition at line 2587 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)

Definition at line 2604 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)

Definition at line 2591 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB2 Peripheral Clock Sleep Enabled or Disabled Status

Defines
AHB2 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
#define | __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
#define | __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)

Detailed Description

Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)

Definition at line 2688 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)

Definition at line 2649 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)

Definition at line 2691 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)

Definition at line 2652 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)

Definition at line 2658 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)

Definition at line 2619 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)

Definition at line 2660 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)

Definition at line 2621 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)

Definition at line 2662 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)

Definition at line 2623 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)

Definition at line 2665 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)

Definition at line 2626 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)

Definition at line 2669 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)

Definition at line 2630 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)

Definition at line 2673 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)

Definition at line 2634 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)

Definition at line 2677 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)

Definition at line 2638 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)

Definition at line 2680 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)

Definition at line 2641 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)

Definition at line 2694 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)

Definition at line 2655 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)

Definition at line 2682 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)

Definition at line 2643 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)

Definition at line 2685 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)

Definition at line 2646 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: AHB3 Peripheral Clock Sleep Enabled or Disabled Status

Defines
AHB3 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
#define | __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)

Detailed Description

Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)

Definition at line 2722 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)

Definition at line 2714 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)

Definition at line 2718 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)

Definition at line 2710 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB1 Peripheral Clock Sleep Enabled or Disabled Status

Defines
APB1 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
#define | __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
#define | __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
#define | __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
#define | __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
#define | __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
#define | __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
#define | __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)

Detailed Description

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)

Definition at line 2879 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)

Definition at line 2798 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)

Definition at line 2887 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)

Definition at line 2806 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)

Definition at line 2867 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)

Definition at line 2786 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)

Definition at line 2870 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)

Definition at line 2789 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)

Definition at line 2873 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)

Definition at line 2792 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)

Definition at line 2838 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)

Definition at line 2757 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)

Definition at line 2891 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)

Definition at line 2810 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)

Definition at line 2897 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)

Definition at line 2816 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)

Definition at line 2893 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)

Definition at line 2812 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)

Definition at line 2889 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)

Definition at line 2808 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)

Definition at line 2885 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)

Definition at line 2804 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)

Definition at line 2848 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)

Definition at line 2767 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)

Definition at line 2851 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)

Definition at line 2770 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)

Definition at line 2895 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)

Definition at line 2814 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)

Definition at line 2819 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)

Definition at line 2738 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)

Definition at line 2822 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)

Definition at line 2741 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)

Definition at line 2826 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)

Definition at line 2745 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)

Definition at line 2830 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)

Definition at line 2749 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)

Definition at line 2833 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)

Definition at line 2752 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)

Definition at line 2835 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)

Definition at line 2754 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)

Definition at line 2860 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)

Definition at line 2779 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)

Definition at line 2864 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)

Definition at line 2783 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)

Definition at line 2853 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)

Definition at line 2772 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)

Definition at line 2856 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)

Definition at line 2775 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)

Definition at line 2845 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)

Definition at line 2764 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: APB2 Peripheral Clock Sleep Enabled or Disabled Status

Defines
APB2 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
#define | __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
#define | __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)

Detailed Description

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)

Definition at line 2978 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)

Definition at line 2943 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)

Definition at line 2971 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)

Definition at line 2936 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)

Definition at line 2974 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)

Definition at line 2939 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)

Definition at line 2950 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)

Definition at line 2915 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)

Definition at line 2955 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)

Definition at line 2920 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)

Definition at line 2947 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)

Definition at line 2912 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)

Definition at line 2963 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)

Definition at line 2928 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)

Definition at line 2965 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)

Definition at line 2930 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)

Definition at line 2968 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)

Definition at line 2933 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)

Definition at line 2953 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)

Definition at line 2918 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)

Definition at line 2958 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)

Definition at line 2923 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)

Definition at line 2961 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)

Definition at line 2926 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Backup Domain Reset

Defines
RCC Backup Domain Reset
RCC Exported Macros

Defines

#define | __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Define Documentation

#define __HAL_RCC_BACKUPRESET_FORCE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Macros to force or release the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
The BKPSRAM is not affected by this reset.
Return values:
None

Definition at line 2995 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BACKUPRESET_RELEASE ( ) CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Definition at line 2997 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC RTC Clock Configuration

Defines
RCC RTC Clock Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Define Documentation

#define __HAL_RCC_RTC_DISABLE ( ) CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Definition at line 3017 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_RTC_ENABLE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Macros to enable or disable the RTC clock.

Note:
As the RTC is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the RTC (to be done once after reset).
These macros must be used after the RTC clock source was selected.
Return values:
None

Definition at line 3015 of file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCC Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the RCC interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check whether the selected RCC flag is set or not.

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CLEAR_IT ( __INTERRUPT__ ) (RCC->CICR = (__INTERRUPT__))

Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.

Parameters:
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_MSIRDY MSI ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
  • RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
  • RCC_IT_CSS HSE Clock security system interrupt
  • RCC_IT_LSECSS LSE Clock security system interrupt
Return values:
None

Definition at line 3598 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler(), and HAL_RCCEx_LSECSS_IRQHandler().

#define __HAL_RCC_CLEAR_RESET_FLAGS ( ) (RCC->CSR |= RCC_CSR_RMVF)

Set RMVF bit to clear the reset flags.

The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.

Return values:
None

Definition at line 3625 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))

Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).

Parameters:
__INTERRUPT__,: specifies the RCC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_MSIRDY HSI ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
  • RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
  • RCC_IT_LSECSS LSE Clock security system interrupt
Return values:
None

Definition at line 3577 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS().

#define __HAL_RCC_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(RCC->CIER, (__INTERRUPT__))

Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).

Parameters:
__INTERRUPT__,: specifies the RCC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_MSIRDY HSI ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
  • RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
  • RCC_IT_LSECSS LSE Clock security system interrupt
Return values:
None

Definition at line 3557 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_GET_FLAG ( __FLAG__ )
Value:
(((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                    \
                                        ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                  \
                                        ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) &    \
                                          ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
                                            ? 1U : 0U)

Check whether the selected RCC flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_MSIRDY MSI oscillator clock ready
  • RCC_FLAG_HSIRDY HSI oscillator clock ready
  • RCC_FLAG_HSERDY HSE oscillator clock ready
  • RCC_FLAG_PLLRDY Main PLL clock ready
  • RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready
  • RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2
  • RCC_FLAG_LSERDY LSE oscillator clock ready
  • RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
  • RCC_FLAG_LSIRDY LSI oscillator clock ready
  • RCC_FLAG_BORRST BOR reset
  • RCC_FLAG_OBLRST OBLRST reset
  • RCC_FLAG_PINRST Pin reset
  • RCC_FLAG_FWRST FIREWALL reset
  • RCC_FLAG_RMVF Remove reset Flag
  • RCC_FLAG_SFTRST Software reset
  • RCC_FLAG_IWDGRST Independent Watchdog reset
  • RCC_FLAG_WWDGRST Window Watchdog reset
  • RCC_FLAG_LPWRRST Low Power reset
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 3661 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_GET_IT ( __INTERRUPT__ ) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the RCC interrupt has occurred or not.

Parameters:
__INTERRUPT__,: specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_MSIRDY MSI ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY Main PLL ready interrupt
  • RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
  • RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
  • RCC_IT_CSS HSE Clock security system interrupt
  • RCC_IT_LSECSS LSE Clock security system interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 3618 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler(), and HAL_RCCEx_LSECSS_IRQHandler().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Exported Macros

Modules | Defines
RCC Exported Macros
RCC

Modules

AHB1 Peripheral Clock Enable Disable

Enable or disable the AHB1 peripheral clock.

AHB2 Peripheral Clock Enable Disable

Enable or disable the AHB2 peripheral clock.

AHB3 Peripheral Clock Enable Disable

Enable or disable the AHB3 peripheral clock.

APB1 Peripheral Clock Enable Disable

Enable or disable the APB1 peripheral clock.

APB2 Peripheral Clock Enable Disable

Enable or disable the APB2 peripheral clock.

AHB1 Peripheral Clock Enabled or Disabled Status

Check whether the AHB1 peripheral clock is enabled or not.

AHB2 Peripheral Clock Enabled or Disabled Status

Check whether the AHB2 peripheral clock is enabled or not.

AHB3 Peripheral Clock Enabled or Disabled Status

Check whether the AHB3 peripheral clock is enabled or not.

APB1 Peripheral Clock Enabled or Disabled Status

Check whether the APB1 peripheral clock is enabled or not.

APB2 Peripheral Clock Enabled or Disabled Status

Check whether the APB2 peripheral clock is enabled or not.

AHB1 Peripheral Force Release Reset

Force or release AHB1 peripheral reset.

AHB2 Peripheral Force Release Reset

Force or release AHB2 peripheral reset.

AHB3 Peripheral Force Release Reset

Force or release AHB3 peripheral reset.

APB1 Peripheral Force Release Reset

Force or release APB1 peripheral reset.

APB2 Peripheral Force Release Reset

Force or release APB2 peripheral reset.

AHB1 Peripheral Clock Sleep Enable Disable

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

AHB2 Peripheral Clock Sleep Enable Disable

Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

AHB3 Peripheral Clock Sleep Enable Disable

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

APB1 Peripheral Clock Sleep Enable Disable

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

APB2 Peripheral Clock Sleep Enable Disable

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

AHB1 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

AHB2 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

AHB3 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.

APB1 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

APB2 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

RCC Backup Domain Reset
RCC RTC Clock Configuration
Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

Defines

#define | __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
#define | __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
#define | __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
#define | __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define | __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
Macros to enable or disable the Internal Multi Speed oscillator (MSI).
#define | __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
#define | __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
#define | __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__)
Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode.
#define | __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
#define | __HAL_RCC_GET_MSI_RANGE()
Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode.
#define | __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Macro to get the RTC clock source.
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
Macro to configure the PLL source division factor M.
#define | __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
#define | __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
Macro to configure the wake up from stop clock.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the MCO clock.

Define Documentation

#define __HAL_RCC_GET_MSI_RANGE ( )
Value:
((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ?             \
                   (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) :            \
                   (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))

Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode.

Return values:
MSI clock range. This parameter must be one of the following values:
  • RCC_MSIRANGE_0 MSI clock is around 100 KHz
  • RCC_MSIRANGE_1 MSI clock is around 200 KHz
  • RCC_MSIRANGE_2 MSI clock is around 400 KHz
  • RCC_MSIRANGE_3 MSI clock is around 800 KHz
  • RCC_MSIRANGE_4 MSI clock is around 1 MHz
  • RCC_MSIRANGE_5 MSI clock is around 2MHz
  • RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset)
  • RCC_MSIRANGE_7 MSI clock is around 8 MHz
  • RCC_MSIRANGE_8 MSI clock is around 16 MHz
  • RCC_MSIRANGE_9 MSI clock is around 24 MHz
  • RCC_MSIRANGE_10 MSI clock is around 32 MHz
  • RCC_MSIRANGE_11 MSI clock is around 48 MHz

Definition at line 3174 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))

Macro to get the oscillator used as PLL clock source.

Return values:
The oscillator used as PLL clock source. The returned value can be one of the following:
  • RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

Definition at line 3424 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), RCCEx_PLLSAI1_Config(), and RCCEx_PLLSAI2_Config().

#define __HAL_RCC_GET_PLLCLKOUT_CONFIG ( __PLLCLOCKOUT__ ) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)

Parameters:
__PLLCLOCKOUT__,: specifies the output PLL clock to be checked. This parameter can be one of the following values:
  • RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case.
  • RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
  • RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
Return values:
SET / RESET

Definition at line 3455 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_RTC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))

Macro to get the RTC clock source.

Return values:
The returned value can be one of the following:
  • RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected

Definition at line 3321 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))

Macro to get the clock source used as system clock.

Return values:
The clock source used as system clock. The returned value can be one of the following:
  • RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.

Definition at line 3478 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define __HAL_RCC_HSE_CONFIG ( __STATE__ )
Value:
do {                                     \
                      if((__STATE__) == RCC_HSE_ON)          \
                      {                                      \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \
                      }                                      \
                      else if((__STATE__) == RCC_HSE_BYPASS) \
                      {                                      \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);      \
                      }                                      \
                      else                                   \
                      {                                      \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
                      }                                      \
                    } while(0)

Macro to configure the External High Speed oscillator (HSE).

Note:
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
__STATE__,: specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON Turn ON the HSE oscillator.
  • RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
Return values:
None

Definition at line 3215 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( __HSICALIBRATIONVALUE__ ) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))

Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
__HSICALIBRATIONVALUE__,: specifies the calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between 0 and 31.
Return values:
None

Definition at line 3051 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSION)

Definition at line 3041 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSION)

Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).

Note:
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source. This parameter can be: ENABLE or DISABLE.
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
Return values:
None

Definition at line 3039 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)

Definition at line 3063 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSIASFS)

Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.

Note:
The enable of this function has not effect on the HSION bit. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 3061 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)

Definition at line 3076 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSIKERON)

Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

Note:
Keeping the HSI ON in STOP mode allows to avoid slowing down the communication speed because of the HSI startup time.
The enable of this function has not effect on the HSION bit. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 3074 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LSE_CONFIG ( __STATE__ )
Value:
do {                                       \
                      if((__STATE__) == RCC_LSE_ON)            \
                      {                                        \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                      }                                        \
                      else if((__STATE__) == RCC_LSE_BYPASS)   \
                      {                                        \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
                      }                                        \
                      else                                     \
                      {                                        \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
                      }                                        \
                    } while(0)

Macro to configure the External Low Speed oscillator (LSE).

Note:
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
__STATE__,: specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON Turn ON the LSE oscillator.
  • RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
Return values:
None

Definition at line 3253 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSEDRIVE_CONFIG ( __LSEDRIVE__ ) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))

Macro to configure the External Low Speed oscillator (LSE) drive capability.

Note:
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
Parameters:
__LSEDRIVE__,: specifies the new state of the LSE drive capability. This parameter can be one of the following values:
  • RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
  • RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
  • RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
  • RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
Return values:
None

Definition at line 3494 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_LSI_DISABLE ( ) CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)

Definition at line 3190 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI_ENABLE ( ) SET_BIT(RCC->CSR, RCC_CSR_LSION)

Macros to enable or disable the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.
Return values:
None

Definition at line 3188 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MCO1_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

Macro to configure the MCO clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK MCO output disabled
  • RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
  • RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
  • RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
  • RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
  • RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 MCO clock source is divided by 1
  • RCC_MCODIV_2 MCO clock source is divided by 2
  • RCC_MCODIV_4 MCO clock source is divided by 4
  • RCC_MCODIV_8 MCO clock source is divided by 8
  • RCC_MCODIV_16 MCO clock source is divided by 16

Definition at line 3531 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST ( __MSICALIBRATIONVALUE__ ) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)

Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal MSI RC. Refer to the Application Note AN3300 for more details on how to calibrate the MSI.
Parameters:
__MSICALIBRATIONVALUE__,: specifies the calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). This parameter must be a number between 0 and 255.
Return values:
None

Definition at line 3109 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_MSION)

Definition at line 3097 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_MSION)

Macros to enable or disable the Internal Multi Speed oscillator (MSI).

Note:
The MSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
MSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the MSI.
After enabling the MSI, the application software should wait on MSIRDY flag to be set indicating that MSI clock is stable and can be used as system clock source.
When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator clock cycles.
Return values:
None

Definition at line 3095 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_RANGE_CONFIG ( __MSIRANGEVALUE__ )
Value:
do {                                                         \
                    SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);                         \
                    MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
                  } while(0)

Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode.

Note:
After restart from Reset , the MSI clock is around 4 MHz. After stop the startup clock can be MSI (at any of its possible frequencies, the one that was used before entering stop mode) or HSI. After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1).
The MSI clock range after reset can be modified on the fly.
Parameters:
__MSIRANGEVALUE__,: specifies the MSI clock range. This parameter must be one of the following values:
  • RCC_MSIRANGE_0 MSI clock is around 100 KHz
  • RCC_MSIRANGE_1 MSI clock is around 200 KHz
  • RCC_MSIRANGE_2 MSI clock is around 400 KHz
  • RCC_MSIRANGE_3 MSI clock is around 800 KHz
  • RCC_MSIRANGE_4 MSI clock is around 1 MHz
  • RCC_MSIRANGE_5 MSI clock is around 2MHz
  • RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset)
  • RCC_MSIRANGE_7 MSI clock is around 8 MHz
  • RCC_MSIRANGE_8 MSI clock is around 16 MHz
  • RCC_MSIRANGE_9 MSI clock is around 24 MHz
  • RCC_MSIRANGE_10 MSI clock is around 32 MHz
  • RCC_MSIRANGE_11 MSI clock is around 48 MHz
Return values:
None

Definition at line 3138 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG ( __MSIRANGEVALUE__ ) MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)

Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).

Parameters:
__MSIRANGEVALUE__,: specifies the MSI clock range. This parameter must be one of the following values:
  • RCC_MSIRANGE_4 MSI clock is around 1 MHz
  • RCC_MSIRANGE_5 MSI clock is around 2MHz
  • RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset)
  • RCC_MSIRANGE_7 MSI clock is around 8 MHz
Return values:
None

Definition at line 3155 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_StandbyMSIRangeConfig().

#define __HAL_RCC_PLL_CONFIG | ( | __PLLSOURCE__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__,
 |  | __PLLQ__,
 |  | __PLLR__
 | ) |
Value:
(RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \
                   (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))

Macro to configure the main PLL clock source, multiplication and division factors.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLSOURCE__,: specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
  • RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Note:
This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
Parameters:
__PLLM__,: specifies the division factor for PLL VCO input clock. This parameter must be a number between 1 and 8.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 4 to 16 MHz. It is recommended to select a frequency of 16 MHz to limit PLL jitter.
Parameters:
__PLLN__,: specifies the multiplication factor for PLL VCO output clock. This parameter must be a number between 8 and 86.
Note:
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz.
Parameters:
__PLLP__,: specifies the division factor for SAI clock. This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x else (2 to 31).
__PLLQ__,: specifies the division factor for OTG FS, SDMMC1 and RNG clocks. This parameter must be in the range (2, 4, 6 or 8).
Note:
If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work correctly.
Parameters:
__PLLR__,: specifies the division factor for the main system clock.
Note:
You have to set the PLLR parameter correctly to not exceed 80MHZ. This parameter must be in the range (2, 4, 6 or 8).
Return values:
None

Definition at line 3410 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLLON)

Definition at line 3333 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLLON)

Macros to enable or disable the main PLL.

Note:
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL can not be disabled if it is used as system clock source
The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Return values:
None

Definition at line 3331 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_PLLM_CONFIG ( __PLLM__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)

Macro to configure the PLL source division factor M.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLM__,: specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 1 and Max_Data = 8.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 4 to 16 MHz. It is recommended to select a frequency of 16 MHz to limit PLL jitter.
Return values:
None

Definition at line 3360 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG ( __PLLSOURCE__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))

Macro to configure the PLL clock source.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLSOURCE__,: specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
  • RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Note:
This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
Return values:
None

Definition at line 3347 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_PLLCLKOUT_DISABLE ( __PLLCLOCKOUT__ ) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Definition at line 3442 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLLCLKOUT_ENABLE ( __PLLCLOCKOUT__ ) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)

Note:
Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot be stopped if used as System Clock.
Parameters:
__PLLCLOCKOUT__,: specifies the PLL clock to be output. This parameter can be one or a combination of the following values:
  • RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case.
  • RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
  • RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
Return values:
None

Definition at line 3440 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_CONFIG ( __RTC_CLKSOURCE__ ) MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))

Macros to configure the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it cannot be changed unless the Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by a Power On Reset (POR).
Parameters:
__RTC_CLKSOURCE__,: specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
Return values:
None

Definition at line 3310 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SYSCLK_CONFIG ( __SYSCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters:
__SYSCLKSOURCE__,: specifies the system clock source. This parameter can be one of the following values:
  • RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Return values:
None

Definition at line 3467 of file stm32l4xx_hal_rcc.h.

#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG ( __STOPWUCLK__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))

Macro to configure the wake up from stop clock.

Parameters:
__STOPWUCLK__,: specifies the clock source used after wake up from stop. This parameter can be one of the following values:
  • RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
  • RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
Return values:
None

Definition at line 3505 of file stm32l4xx_hal_rcc.h.

Referenced by HAL_RCCEx_WakeUpStopCLKConfig().

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCCEx Private Constants

Defines
RCCEx Private Constants
RCCEx

Defines

#define | PLLSAI1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | PLLSAI2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | DIVIDER_P_UPDATE 0U
#define | DIVIDER_Q_UPDATE 1U
#define | DIVIDER_R_UPDATE 2U
#define | __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | LSCO_GPIO_PORT GPIOA
#define | LSCO_PIN GPIO_PIN_2

Define Documentation

#define __LSCO_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 71 of file stm32l4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO().

#define DIVIDER_P_UPDATE 0U

Definition at line 67 of file stm32l4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_PeriphCLKConfig(), RCCEx_PLLSAI1_Config(), and RCCEx_PLLSAI2_Config().

#define DIVIDER_Q_UPDATE 1U

Definition at line 68 of file stm32l4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

#define DIVIDER_R_UPDATE 2U

Definition at line 69 of file stm32l4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define LSCO_GPIO_PORT GPIOA

Definition at line 72 of file stm32l4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO().

#define LSCO_PIN GPIO_PIN_2

Definition at line 73 of file stm32l4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO().

#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */

Definition at line 65 of file stm32l4xx_hal_rcc_ex.c.

#define PLLSAI1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */

Definition at line 63 of file stm32l4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_DisablePLLSAI1(), HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define PLLSAI2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */

Definition at line 64 of file stm32l4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_DisablePLLSAI2(), HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCCEx Private Functions

Functions
RCCEx Private Functions
RCCEx

Functions

static HAL_StatusTypeDef | RCCEx_PLLSAI1_Config (RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s).
static HAL_StatusTypeDef | RCCEx_PLLSAI2_Config (RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s).

Function Documentation

static HAL_StatusTypeDef RCCEx_PLLSAI1_Config | ( | RCC_PLLSAI1InitTypeDef * | PllSai1,
 |  | uint32_t | Divider
 | ) |  | [static]

Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s).

Parameters:
PllSai1 | pointer to an RCC_PLLSAI1InitTypeDef structure that contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s)
Divider | divider parameter to be updated
Note:
PLLSAI1 is temporary disable to apply new parameters
Return values:
HAL status

Definition at line 2383 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_PLLSAI1_DISABLE, __HAL_RCC_PLLSAI1_ENABLE, __HAL_RCC_PLLSAI1CLKOUT_ENABLE, assert_param, DIVIDER_P_UPDATE, DIVIDER_Q_UPDATE, HAL_GetTick(), IS_RCC_PLLSAI1CLOCKOUT_VALUE, IS_RCC_PLLSAI1M_VALUE, IS_RCC_PLLSAI1N_VALUE, IS_RCC_PLLSAI1P_VALUE, IS_RCC_PLLSAI1Q_VALUE, IS_RCC_PLLSAI1R_VALUE, IS_RCC_PLLSAI1SOURCE, PLLSAI1_TIMEOUT_VALUE, RCC_PLLSAI1InitTypeDef::PLLSAI1ClockOut, RCC_PLLSAI1InitTypeDef::PLLSAI1M, RCC_PLLSAI1InitTypeDef::PLLSAI1N, RCC_PLLSAI1InitTypeDef::PLLSAI1P, RCC_PLLSAI1InitTypeDef::PLLSAI1Q, RCC_PLLSAI1InitTypeDef::PLLSAI1R, RCC_PLLSAI1InitTypeDef::PLLSAI1Source, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_PLLSOURCE_MSI, and RCC_PLLSOURCE_NONE.

Referenced by HAL_RCCEx_PeriphCLKConfig().

static HAL_StatusTypeDef RCCEx_PLLSAI2_Config | ( | RCC_PLLSAI2InitTypeDef * | PllSai2,
 |  | uint32_t | Divider
 | ) |  | [static]

Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s).

Parameters:
PllSai2 | pointer to an RCC_PLLSAI2InitTypeDef structure that contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s)
Divider | divider parameter to be updated
Note:
PLLSAI2 is temporary disable to apply new parameters
Return values:
HAL status

Definition at line 2538 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_PLLSAI2_DISABLE, __HAL_RCC_PLLSAI2_ENABLE, __HAL_RCC_PLLSAI2CLKOUT_ENABLE, assert_param, DIVIDER_P_UPDATE, HAL_GetTick(), IS_RCC_PLLSAI2CLOCKOUT_VALUE, IS_RCC_PLLSAI2M_VALUE, IS_RCC_PLLSAI2N_VALUE, IS_RCC_PLLSAI2P_VALUE, IS_RCC_PLLSAI2R_VALUE, IS_RCC_PLLSAI2SOURCE, PLLSAI2_TIMEOUT_VALUE, RCC_PLLSAI2InitTypeDef::PLLSAI2ClockOut, RCC_PLLSAI2InitTypeDef::PLLSAI2M, RCC_PLLSAI2InitTypeDef::PLLSAI2N, RCC_PLLSAI2InitTypeDef::PLLSAI2P, RCC_PLLSAI2InitTypeDef::PLLSAI2R, RCC_PLLSAI2InitTypeDef::PLLSAI2Source, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_PLLSOURCE_MSI, and RCC_PLLSOURCE_NONE.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RCCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLLSAIs.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) are set to their reset values.

Function Documentation

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that returns the configuration information for the Extended Peripherals clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, LPUART, USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG).
Return values:
None

Definition at line 643 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC_SOURCE, __HAL_RCC_GET_DFSDM1_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C2_SOURCE, __HAL_RCC_GET_I2C3_SOURCE, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPTIM2_SOURCE, __HAL_RCC_GET_LPUART1_SOURCE, __HAL_RCC_GET_RNG_SOURCE, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_SAI1_SOURCE, __HAL_RCC_GET_SAI2_SOURCE, __HAL_RCC_GET_SDMMC1_SOURCE, __HAL_RCC_GET_SWPMI1_SOURCE, __HAL_RCC_GET_UART4_SOURCE, __HAL_RCC_GET_UART5_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USART2_SOURCE, __HAL_RCC_GET_USART3_SOURCE, __HAL_RCC_GET_USB_SOURCE, RCC_PeriphCLKInitTypeDef::AdcClockSelection, RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::I2c3ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PeriphCLKInitTypeDef::PLLSAI1, RCC_PLLSAI1InitTypeDef::PLLSAI1M, RCC_PLLSAI1InitTypeDef::PLLSAI1N, RCC_PLLSAI1InitTypeDef::PLLSAI1P, RCC_PLLSAI1InitTypeDef::PLLSAI1Q, RCC_PLLSAI1InitTypeDef::PLLSAI1R, RCC_PLLSAI1InitTypeDef::PLLSAI1Source, RCC_PeriphCLKInitTypeDef::PLLSAI2, RCC_PLLSAI2InitTypeDef::PLLSAI2M, RCC_PLLSAI2InitTypeDef::PLLSAI2N, RCC_PLLSAI2InitTypeDef::PLLSAI2P, RCC_PLLSAI2InitTypeDef::PLLSAI2R, RCC_PLLSAI2InitTypeDef::PLLSAI2Source, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_DFSDM1, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2, RCC_PERIPHCLK_SWPMI1, RCC_PERIPHCLK_UART4, RCC_PERIPHCLK_UART5, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::Sai2ClockSelection, RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection, RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection, RCC_PeriphCLKInitTypeDef::Uart4ClockSelection, RCC_PeriphCLKInitTypeDef::Uart5ClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

uint32_t HAL_RCCEx_GetPeriphCLKFreq ( uint32_t PeriphClk )

Return the peripheral clock frequency for peripherals with clock source from PLLSAIs.

Note:
Return 0 if peripheral clock identifier not managed by this API
Parameters:
PeriphClk Peripheral clock identifier This parameter can be one of the following values:
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_ADC ADC peripheral clock
  • RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM)
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
  • RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
  • RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
  • RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
  • RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
  • RCC_PERIPHCLK_RNG RNG peripheral clock
  • RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
  • RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2)
  • RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock
  • RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_USART2 USART1 peripheral clock
  • RCC_PERIPHCLK_USART3 USART1 peripheral clock
  • RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4)
  • RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5)
  • RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
Return values:
Frequency in Hz

Definition at line 820 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC_SOURCE, __HAL_RCC_GET_DFSDM1_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C2_SOURCE, __HAL_RCC_GET_I2C3_SOURCE, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPTIM2_SOURCE, __HAL_RCC_GET_LPUART1_SOURCE, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_GET_PLLCLKOUT_CONFIG, __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG, __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_SAI1_SOURCE, __HAL_RCC_GET_SAI2_SOURCE, __HAL_RCC_GET_SWPMI1_SOURCE, __HAL_RCC_GET_UART4_SOURCE, __HAL_RCC_GET_UART5_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USART2_SOURCE, __HAL_RCC_GET_USART3_SOURCE, assert_param, EXTERNAL_SAI1_CLOCK_VALUE, EXTERNAL_SAI2_CLOCK_VALUE, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSE_VALUE, HSI48_VALUE, HSI_VALUE, IS_RCC_PERIPHCLOCK, LSE_VALUE, LSI_VALUE, RCC_ADCCLKSOURCE_PLLSAI1, RCC_ADCCLKSOURCE_PLLSAI2, RCC_ADCCLKSOURCE_SYSCLK, RCC_DFSDM1CLKSOURCE_PCLK, RCC_I2C1CLKSOURCE_HSI, RCC_I2C1CLKSOURCE_PCLK1, RCC_I2C1CLKSOURCE_SYSCLK, RCC_I2C2CLKSOURCE_HSI, RCC_I2C2CLKSOURCE_PCLK1, RCC_I2C2CLKSOURCE_SYSCLK, RCC_I2C3CLKSOURCE_HSI, RCC_I2C3CLKSOURCE_PCLK1, RCC_I2C3CLKSOURCE_SYSCLK, RCC_LPTIM1CLKSOURCE_HSI, RCC_LPTIM1CLKSOURCE_LSE, RCC_LPTIM1CLKSOURCE_LSI, RCC_LPTIM1CLKSOURCE_PCLK, RCC_LPTIM2CLKSOURCE_HSI, RCC_LPTIM2CLKSOURCE_LSE, RCC_LPTIM2CLKSOURCE_LSI, RCC_LPTIM2CLKSOURCE_PCLK, RCC_LPUART1CLKSOURCE_HSI, RCC_LPUART1CLKSOURCE_LSE, RCC_LPUART1CLKSOURCE_PCLK1, RCC_LPUART1CLKSOURCE_SYSCLK, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_DFSDM1, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2, RCC_PERIPHCLK_SDMMC1, RCC_PERIPHCLK_SWPMI1, RCC_PERIPHCLK_UART4, RCC_PERIPHCLK_UART5, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PLL_SAI3CLK, RCC_PLLSAI1_ADC1CLK, RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI2_ADC2CLK, RCC_PLLSAI2_SAI2CLK, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_PLLSOURCE_MSI, RCC_RTCCLKSOURCE_HSE_DIV32, RCC_RTCCLKSOURCE_LSE, RCC_RTCCLKSOURCE_LSI, RCC_SAI1CLKSOURCE_PIN, RCC_SAI1CLKSOURCE_PLL, RCC_SAI1CLKSOURCE_PLLSAI1, RCC_SAI1CLKSOURCE_PLLSAI2, RCC_SAI2CLKSOURCE_PIN, RCC_SAI2CLKSOURCE_PLL, RCC_SAI2CLKSOURCE_PLLSAI2, RCC_SWPMI1CLKSOURCE_HSI, RCC_SWPMI1CLKSOURCE_PCLK, RCC_UART4CLKSOURCE_HSI, RCC_UART4CLKSOURCE_LSE, RCC_UART4CLKSOURCE_PCLK1, RCC_UART4CLKSOURCE_SYSCLK, RCC_UART5CLKSOURCE_HSI, RCC_UART5CLKSOURCE_LSE, RCC_UART5CLKSOURCE_PCLK1, RCC_UART5CLKSOURCE_SYSCLK, RCC_USART1CLKSOURCE_HSI, RCC_USART1CLKSOURCE_LSE, RCC_USART1CLKSOURCE_PCLK2, RCC_USART1CLKSOURCE_SYSCLK, RCC_USART2CLKSOURCE_HSI, RCC_USART2CLKSOURCE_LSE, RCC_USART2CLKSOURCE_PCLK1, RCC_USART2CLKSOURCE_SYSCLK, RCC_USART3CLKSOURCE_HSI, RCC_USART3CLKSOURCE_LSE, RCC_USART3CLKSOURCE_PCLK1, and RCC_USART3CLKSOURCE_SYSCLK.

Referenced by HAL_SAI_Init().

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters:
PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that contains a field PeriphClockSelection which can be a combination of the following values:
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_ADC ADC peripheral clock
  • RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1)
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
  • RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
  • RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
  • RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
  • RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
  • RCC_PERIPHCLK_RNG RNG peripheral clock
  • RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
  • RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2)
  • RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock
  • RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1)
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_USART2 USART1 peripheral clock
  • RCC_PERIPHCLK_USART3 USART1 peripheral clock
  • RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4)
  • RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5)
  • RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
Note:
Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source: in this case the access to Backup domain is enabled.
Return values:
HAL status

Definition at line 163 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_ADC_CONFIG, __HAL_RCC_BACKUPRESET_FORCE, __HAL_RCC_BACKUPRESET_RELEASE, __HAL_RCC_DFSDM1_CONFIG, __HAL_RCC_I2C1_CONFIG, __HAL_RCC_I2C2_CONFIG, __HAL_RCC_I2C3_CONFIG, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_LPTIM2_CONFIG, __HAL_RCC_LPUART1_CONFIG, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, __HAL_RCC_RNG_CONFIG, __HAL_RCC_RTC_CONFIG, __HAL_RCC_SAI1_CONFIG, __HAL_RCC_SAI2_CONFIG, __HAL_RCC_SDMMC1_CONFIG, __HAL_RCC_SWPMI1_CONFIG, __HAL_RCC_UART4_CONFIG, __HAL_RCC_UART5_CONFIG, __HAL_RCC_USART1_CONFIG, __HAL_RCC_USART2_CONFIG, __HAL_RCC_USART3_CONFIG, __HAL_RCC_USB_CONFIG, RCC_PeriphCLKInitTypeDef::AdcClockSelection, assert_param, RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection, DIVIDER_P_UPDATE, DIVIDER_Q_UPDATE, DIVIDER_R_UPDATE, HAL_GetTick(), RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c2ClockSelection, RCC_PeriphCLKInitTypeDef::I2c3ClockSelection, IS_RCC_ADCCLKSOURCE, IS_RCC_DFSDM1CLKSOURCE, IS_RCC_I2C1CLKSOURCE, IS_RCC_I2C2CLKSOURCE, IS_RCC_I2C3CLKSOURCE, IS_RCC_LPTIM1CLK, IS_RCC_LPTIM2CLK, IS_RCC_LPUART1CLKSOURCE, IS_RCC_PERIPHCLOCK, IS_RCC_RNGCLKSOURCE, IS_RCC_RTCCLKSOURCE, IS_RCC_SAI1CLK, IS_RCC_SAI2CLK, IS_RCC_SDMMC1CLKSOURCE, IS_RCC_SWPMI1CLKSOURCE, IS_RCC_UART4CLKSOURCE, IS_RCC_UART5CLKSOURCE, IS_RCC_USART1CLKSOURCE, IS_RCC_USART2CLKSOURCE, IS_RCC_USART3CLKSOURCE, IS_RCC_USBCLKSOURCE, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PeriphCLKInitTypeDef::PLLSAI1, RCC_PeriphCLKInitTypeDef::PLLSAI2, RCC_ADCCLKSOURCE_PLLSAI1, RCC_ADCCLKSOURCE_PLLSAI2, RCC_DBP_TIMEOUT_VALUE, RCC_LSE_TIMEOUT_VALUE, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_DFSDM1, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C2, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2, RCC_PERIPHCLK_SDMMC1, RCC_PERIPHCLK_SWPMI1, RCC_PERIPHCLK_UART4, RCC_PERIPHCLK_UART5, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_USART3, RCC_PERIPHCLK_USB, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK, RCC_RNGCLKSOURCE_PLL, RCC_RNGCLKSOURCE_PLLSAI1, RCC_RTCCLKSOURCE_NO_CLK, RCC_SAI1CLKSOURCE_PIN, RCC_SAI1CLKSOURCE_PLL, RCC_SAI1CLKSOURCE_PLLSAI1, RCC_SAI1CLKSOURCE_PLLSAI2, RCC_SAI2CLKSOURCE_PIN, RCC_SAI2CLKSOURCE_PLL, RCC_SAI2CLKSOURCE_PLLSAI1, RCC_SAI2CLKSOURCE_PLLSAI2, RCC_SDMMC1CLKSOURCE_PLL, RCC_SDMMC1CLKSOURCE_PLLSAI1, RCC_USBCLKSOURCE_PLL, RCC_USBCLKSOURCE_PLLSAI1, RCCEx_PLLSAI1_Config(), RCCEx_PLLSAI2_Config(), RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::Sai2ClockSelection, RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection, RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection, RCC_PeriphCLKInitTypeDef::Uart4ClockSelection, RCC_PeriphCLKInitTypeDef::Uart5ClockSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, RCC_PeriphCLKInitTypeDef::Usart2ClockSelection, RCC_PeriphCLKInitTypeDef::Usart3ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Clock management functions

Functions
Extended Clock management functions
RCCEx Exported Functions

Extended Clock management functions. More...

Functions

HAL_StatusTypeDef | HAL_RCCEx_EnablePLLSAI1 (RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
Enable PLLSAI1.
HAL_StatusTypeDef | HAL_RCCEx_DisablePLLSAI1 (void)
Disable PLLSAI1.
HAL_StatusTypeDef | HAL_RCCEx_EnablePLLSAI2 (RCC_PLLSAI2InitTypeDef *PLLSAI2Init)
Enable PLLSAI2.
HAL_StatusTypeDef | HAL_RCCEx_DisablePLLSAI2 (void)
Disable PLLISAI2.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_StandbyMSIRangeConfig (uint32_t MSIRange)
Configure the MSI range after standby mode.
void | HAL_RCCEx_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCCEx_EnableLSECSS_IT (void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
void | HAL_RCCEx_LSECSS_IRQHandler (void)
Handle the RCC LSE Clock Security System interrupt request.
__weak void | HAL_RCCEx_LSECSS_Callback (void)
RCCEx LSE Clock Security System interrupt callback.
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.
void | HAL_RCCEx_EnableMSIPLLMode (void)
Enable the PLL-mode of the MSI.
void | HAL_RCCEx_DisableMSIPLLMode (void)
Disable the PLL-mode of the MSI.

Detailed Description

Extended Clock management functions.

 ===============================================================================
                ##### Extended clock management functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the
    activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS,
    Low speed clock output and clock after wake-up from STOP mode.

Function Documentation

void HAL_RCCEx_DisableLSCO ( void )

Disable the Low Speed clock output.

Return values:
None

Definition at line 1950 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, HAL_PWR_DisableBkUpAccess(), and HAL_PWR_EnableBkUpAccess().

void HAL_RCCEx_DisableLSECSS ( void )

Disable the LSE Clock Security System.

Note:
LSE Clock Security System can only be disabled after a LSE failure detection.
Return values:
None

Definition at line 1841 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_DISABLE_IT, and RCC_IT_LSECSS.

void HAL_RCCEx_DisableMSIPLLMode ( void )

Disable the PLL-mode of the MSI.

Note:
PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
Return values:
None

Definition at line 1998 of file stm32l4xx_hal_rcc_ex.c.

HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1 ( void )

Disable PLLSAI1.

Return values:
HAL status

Definition at line 1644 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_PLLSAI1_DISABLE, __HAL_RCC_PLLSAI1CLKOUT_DISABLE, HAL_GetTick(), PLLSAI1_TIMEOUT_VALUE, and RCC_PLLSOURCE_NONE.

HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2 ( void )

Disable PLLISAI2.

Return values:
HAL status

Definition at line 1751 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_PLLSAI2_DISABLE, __HAL_RCC_PLLSAI2CLKOUT_DISABLE, HAL_GetTick(), PLLSAI2_TIMEOUT_VALUE, and RCC_PLLSOURCE_NONE.

void HAL_RCCEx_EnableLSCO ( uint32_t LSCOSource )

Select the Low Speed clock source to output on LSCO pin (PA2).

Parameters:
LSCOSource specifies the Low Speed clock source to output. This parameter can be one of the following values:
  • RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
  • RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
Return values:
None

Definition at line 1903 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, __LSCO_CLK_ENABLE, assert_param, GPIO_MODE_ANALOG, GPIO_NOPULL, GPIO_SPEED_FREQ_HIGH, HAL_GPIO_Init(), HAL_PWR_DisableBkUpAccess(), HAL_PWR_EnableBkUpAccess(), IS_RCC_LSCOSOURCE, LSCO_GPIO_PORT, LSCO_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, and GPIO_InitTypeDef::Speed.

void HAL_RCCEx_EnableLSECSS ( void )

Enable the LSE Clock Security System.

Note:
Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC clock with HAL_RCCEx_PeriphCLKConfig().
Return values:
None

Definition at line 1831 of file stm32l4xx_hal_rcc_ex.c.

void HAL_RCCEx_EnableLSECSS_IT ( void )

Enable the LSE Clock Security System Interrupt & corresponding EXTI line.

Note:
LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
Return values:
None

Definition at line 1854 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_ENABLE_IT, __HAL_RCC_LSECSS_EXTI_ENABLE_IT, __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE, and RCC_IT_LSECSS.

void HAL_RCCEx_EnableMSIPLLMode ( void )

Enable the PLL-mode of the MSI.

Note:
Prior to enable the PLL-mode of the MSI for automatic hardware calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
Return values:
None

Definition at line 1988 of file stm32l4xx_hal_rcc_ex.c.

HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1 ( RCC_PLLSAI1InitTypeDef * PLLSAI1Init )

Enable PLLSAI1.

Parameters:
PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that contains the configuration information for the PLLSAI1
Return values:
HAL status

Definition at line 1582 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_PLLSAI1_CONFIG, __HAL_RCC_PLLSAI1_DISABLE, __HAL_RCC_PLLSAI1_ENABLE, __HAL_RCC_PLLSAI1CLKOUT_ENABLE, assert_param, HAL_GetTick(), IS_RCC_PLLSAI1CLOCKOUT_VALUE, IS_RCC_PLLSAI1M_VALUE, IS_RCC_PLLSAI1N_VALUE, IS_RCC_PLLSAI1P_VALUE, IS_RCC_PLLSAI1Q_VALUE, IS_RCC_PLLSAI1R_VALUE, IS_RCC_PLLSAI1SOURCE, PLLSAI1_TIMEOUT_VALUE, RCC_PLLSAI1InitTypeDef::PLLSAI1ClockOut, RCC_PLLSAI1InitTypeDef::PLLSAI1M, RCC_PLLSAI1InitTypeDef::PLLSAI1N, RCC_PLLSAI1InitTypeDef::PLLSAI1P, RCC_PLLSAI1InitTypeDef::PLLSAI1Q, RCC_PLLSAI1InitTypeDef::PLLSAI1R, and RCC_PLLSAI1InitTypeDef::PLLSAI1Source.

HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2 ( RCC_PLLSAI2InitTypeDef * PLLSAI2Init )

Enable PLLSAI2.

Parameters:
PLLSAI2Init pointer to an RCC_PLLSAI2InitTypeDef structure that contains the configuration information for the PLLSAI2
Return values:
HAL status

Definition at line 1690 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_PLLSAI2_CONFIG, __HAL_RCC_PLLSAI2_DISABLE, __HAL_RCC_PLLSAI2_ENABLE, __HAL_RCC_PLLSAI2CLKOUT_ENABLE, assert_param, HAL_GetTick(), IS_RCC_PLLSAI2CLOCKOUT_VALUE, IS_RCC_PLLSAI2M_VALUE, IS_RCC_PLLSAI2N_VALUE, IS_RCC_PLLSAI2P_VALUE, IS_RCC_PLLSAI2R_VALUE, IS_RCC_PLLSAI2SOURCE, PLLSAI2_TIMEOUT_VALUE, RCC_PLLSAI2InitTypeDef::PLLSAI2ClockOut, RCC_PLLSAI2InitTypeDef::PLLSAI2M, RCC_PLLSAI2InitTypeDef::PLLSAI2N, RCC_PLLSAI2InitTypeDef::PLLSAI2P, RCC_PLLSAI2InitTypeDef::PLLSAI2R, and RCC_PLLSAI2InitTypeDef::PLLSAI2Source.

void HAL_RCCEx_LSECSS_Callback ( void )

RCCEx LSE Clock Security System interrupt callback.

Return values:
none

Definition at line 1888 of file stm32l4xx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_LSECSS_IRQHandler().

void HAL_RCCEx_LSECSS_IRQHandler ( void )

Handle the RCC LSE Clock Security System interrupt request.

Return values:
None

Definition at line 1871 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCCEx_LSECSS_Callback(), and RCC_IT_LSECSS.

void HAL_RCCEx_StandbyMSIRangeConfig ( uint32_t MSIRange )

Configure the MSI range after standby mode.

Note:
After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
Parameters:
MSIRange MSI range This parameter can be one of the following values:
  • RCC_MSIRANGE_4 Range 4 around 1 MHz
  • RCC_MSIRANGE_5 Range 5 around 2 MHz
  • RCC_MSIRANGE_6 Range 6 around 4 MHz (reset value)
  • RCC_MSIRANGE_7 Range 7 around 8 MHz
Return values:
None

Definition at line 1817 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_MSI_STANDBY_RANGE_CONFIG, assert_param, and IS_RCC_MSI_STANDBY_CLOCK_RANGE.

void HAL_RCCEx_WakeUpStopCLKConfig ( uint32_t WakeUpClk )

Configure the oscillator clock source for wakeup from Stop and CSS backup clock.

Parameters:
WakeUpClk Wakeup clock This parameter can be one of the following values:
  • RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection
  • RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
Note:
This function shall not be called after the Clock Security System on HSE has been enabled.
Return values:
None

Definition at line 1799 of file stm32l4xx_hal_rcc_ex.c.

References __HAL_RCC_WAKEUPSTOP_CLK_CONFIG, assert_param, and IS_RCC_STOP_WAKEUPCLOCK.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC_PLLSAI1InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLSAI1InitTypeDef Struct Reference
RCCEx Exported Types

PLLSAI1 Clock structure definition. More...

#include <stm32l4xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLLSAI1Source
uint32_t | PLLSAI1M
uint32_t | PLLSAI1N
uint32_t | PLLSAI1P
uint32_t | PLLSAI1Q
uint32_t | PLLSAI1R
uint32_t | PLLSAI1ClockOut

Detailed Description

PLLSAI1 Clock structure definition.

Definition at line 66 of file stm32l4xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1ClockOut

PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. This parameter must be a value of PLLSAI1 Clock Output

Definition at line 87 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1M

PLLSAI1M: specifies the division factor for PLLSAI1 input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 8

Definition at line 72 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1N

PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between 8 and 86 or 127 depending on devices.

Definition at line 75 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1P

PLLSAI1P: specifies the division factor for SAI clock. This parameter must be a value of PLLP Clock Divider

Definition at line 78 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1Q

PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. This parameter must be a value of PLLQ Clock Divider

Definition at line 81 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1R

PLLSAI1R: specifies the division factor for ADC clock. This parameter must be a value of PLLR Clock Divider

Definition at line 84 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1Source

PLLSAI1Source: PLLSAI1 entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 69 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_Config().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rcc_ex.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC_PLLSAI2InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLSAI2InitTypeDef Struct Reference
RCCEx Exported Types

PLLSAI2 Clock structure definition. More...

#include <stm32l4xx_hal_rcc_ex.h>

Data Fields

uint32_t | PLLSAI2Source
uint32_t | PLLSAI2M
uint32_t | PLLSAI2N
uint32_t | PLLSAI2P
uint32_t | PLLSAI2R
uint32_t | PLLSAI2ClockOut

Detailed Description

PLLSAI2 Clock structure definition.

Definition at line 96 of file stm32l4xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PLLSAI2InitTypeDef::PLLSAI2ClockOut

PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. This parameter must be a value of PLLSAI2 Clock Output

Definition at line 114 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

uint32_t RCC_PLLSAI2InitTypeDef::PLLSAI2M

PLLSAI2M: specifies the division factor for PLLSAI2 input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 8

Definition at line 102 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI2_Config().

uint32_t RCC_PLLSAI2InitTypeDef::PLLSAI2N

PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. This parameter must be a number between 8 and 86 or 127 depending on devices.

Definition at line 105 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI2_Config().

uint32_t RCC_PLLSAI2InitTypeDef::PLLSAI2P

PLLSAI2P: specifies the division factor for SAI clock. This parameter must be a value of PLLP Clock Divider

Definition at line 108 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI2_Config().

uint32_t RCC_PLLSAI2InitTypeDef::PLLSAI2R

PLLSAI2R: specifies the division factor for ADC clock. This parameter must be a value of PLLR Clock Divider

Definition at line 111 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI2_Config().

uint32_t RCC_PLLSAI2InitTypeDef::PLLSAI2Source

PLLSAI2Source: PLLSAI2 entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 99 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI2_Config().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rcc_ex.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC_PeriphCLKInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PeriphCLKInitTypeDef Struct Reference
RCCEx Exported Types

RCC extended clocks structure definition. More...

#include <stm32l4xx_hal_rcc_ex.h>

Data Fields

uint32_t | PeriphClockSelection
RCC_PLLSAI1InitTypeDef PLLSAI1
RCC_PLLSAI2InitTypeDef PLLSAI2
uint32_t | Usart1ClockSelection
uint32_t | Usart2ClockSelection
uint32_t | Usart3ClockSelection
uint32_t | Uart4ClockSelection
uint32_t | Uart5ClockSelection
uint32_t | Lpuart1ClockSelection
uint32_t | I2c1ClockSelection
uint32_t | I2c2ClockSelection
uint32_t | I2c3ClockSelection
uint32_t | Lptim1ClockSelection
uint32_t | Lptim2ClockSelection
uint32_t | Sai1ClockSelection
uint32_t | Sai2ClockSelection
uint32_t | UsbClockSelection
uint32_t | Sdmmc1ClockSelection
uint32_t | RngClockSelection
uint32_t | AdcClockSelection
uint32_t | Swpmi1ClockSelection
uint32_t | Dfsdm1ClockSelection
uint32_t | RTCClockSelection

Detailed Description

RCC extended clocks structure definition.

Definition at line 123 of file stm32l4xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PeriphCLKInitTypeDef::AdcClockSelection

Specifies ADC interface clock source. This parameter can be a value of ADC Clock Source

Definition at line 214 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection

Specifies DFSDM1 clock source. This parameter can be a value of DFSDM1 Clock Source

Definition at line 226 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c1ClockSelection

Specifies I2C1 clock source. This parameter can be a value of I2C1 Clock Source

Definition at line 168 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c2ClockSelection

Specifies I2C2 clock source. This parameter can be a value of I2C2 Clock Source

Definition at line 173 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c3ClockSelection

Specifies I2C3 clock source. This parameter can be a value of I2C3 Clock Source

Definition at line 178 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection

Specifies LPTIM1 clock source. This parameter can be a value of LPTIM1 Clock Source

Definition at line 181 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection

Specifies LPTIM2 clock source. This parameter can be a value of LPTIM2 Clock Source

Definition at line 184 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection

Specifies LPUART1 clock source. This parameter can be a value of LPUART1 Clock Source

Definition at line 165 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PeriphClockSelection

The Extended Clock to be configured. This parameter can be a value of Periph Clock Selection

Definition at line 125 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

RCC_PLLSAI1InitTypeDef RCC_PeriphCLKInitTypeDef::PLLSAI1

PLLSAI1 structure parameters. This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC

Definition at line 128 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

RCC_PLLSAI2InitTypeDef RCC_PeriphCLKInitTypeDef::PLLSAI2

PLLSAI2 structure parameters. This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC

Definition at line 133 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RngClockSelection

Specifies RNG clock source (warning: same source for USB and SDMMC1). This parameter can be a value of RNG Clock Source

Definition at line 211 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RTCClockSelection

Specifies RTC clock source. This parameter can be a value of RTC Clock Source

Definition at line 231 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai1ClockSelection

Specifies SAI1 clock source. This parameter can be a value of SAI1 Clock Source

Definition at line 187 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai2ClockSelection

Specifies SAI2 clock source. This parameter can be a value of SAI2 Clock Source

Definition at line 192 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection

Specifies SDMMC1 clock source (warning: same source for USB and RNG). This parameter can be a value of SDMMC1 Clock Source

Definition at line 206 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection

Specifies SWPMI1 clock source. This parameter can be a value of SWPMI1 Clock Source

Definition at line 219 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Uart4ClockSelection

Specifies UART4 clock source. This parameter can be a value of UART4 Clock Source

Definition at line 153 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Uart5ClockSelection

Specifies UART5 clock source. This parameter can be a value of UART5 Clock Source

Definition at line 160 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart1ClockSelection

Specifies USART1 clock source. This parameter can be a value of USART1 Clock Source

Definition at line 138 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart2ClockSelection

Specifies USART2 clock source. This parameter can be a value of USART2 Clock Source

Definition at line 141 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart3ClockSelection

Specifies USART3 clock source. This parameter can be a value of USART3 Clock Source

Definition at line 146 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::UsbClockSelection

Specifies USB clock source (warning: same source for SDMMC1 and RNG). This parameter can be a value of USB Clock Source

Definition at line 199 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rcc_ex.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Low Speed Clock Source

Defines
Low Speed Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U
#define | RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL

Define Documentation

#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL

LSE selection for low speed clock output

Definition at line 299 of file stm32l4xx_hal_rcc_ex.h.

#define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U

LSI selection for low speed clock output

Definition at line 298 of file stm32l4xx_hal_rcc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Periph Clock Selection

Defines
Periph Clock Selection
RCCEx Exported Constants

Defines

#define | RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
#define | RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
#define | RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U)
#define | RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U)
#define | RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U)
#define | RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U)
#define | RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U)
#define | RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U)
#define | RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
#define | RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U)
#define | RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U)
#define | RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U)
#define | RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U)
#define | RCC_PERIPHCLK_USB ((uint32_t)0x00002000U)
#define | RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U)
#define | RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U)
#define | RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U)
#define | RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U)
#define | RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U)
#define | RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U)

Define Documentation

#define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U)

Definition at line 333 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U)

Definition at line 336 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U)

Definition at line 319 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U)

Definition at line 321 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)

Definition at line 323 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U)

Definition at line 324 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U)

Definition at line 325 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U)

Definition at line 318 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U)

Definition at line 339 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U)

Definition at line 338 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U)

Definition at line 326 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U)

Definition at line 328 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U)

Definition at line 341 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U)

Definition at line 334 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U)

Definition at line 313 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U)

Definition at line 316 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)

Definition at line 307 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)

Definition at line 308 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U)

Definition at line 310 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USB ((uint32_t)0x00002000U)

Definition at line 331 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

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STM32L486xx HAL User Manual: USART1 Clock Source

Defines
USART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
#define | RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define | RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define | RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)

Define Documentation

#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1

Definition at line 353 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)

Definition at line 354 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)

Definition at line 351 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0

Definition at line 352 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: USART2 Clock Source

Defines
USART2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define | RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define | RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)

Define Documentation

#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1

Definition at line 364 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)

Definition at line 365 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)

Definition at line 362 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0

Definition at line 363 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: USART3 Clock Source

Defines
USART3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
#define | RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
#define | RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)

Define Documentation

#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1

Definition at line 376 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)

Definition at line 377 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)

Definition at line 374 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0

Definition at line 375 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: UART4 Clock Source

Defines
UART4 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
#define | RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
#define | RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)

Define Documentation

#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1

Definition at line 389 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)

Definition at line 390 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)

Definition at line 387 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0

Definition at line 388 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: UART5 Clock Source

Defines
UART5 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
#define | RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
#define | RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)

Define Documentation

#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1

Definition at line 402 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)

Definition at line 403 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)

Definition at line 400 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0

Definition at line 401 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: LPUART1 Clock Source

Defines
LPUART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)

Define Documentation

#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1

Definition at line 414 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)

Definition at line 415 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)

Definition at line 412 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0

Definition at line 413 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: I2C1 Clock Source

Defines
I2C1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define | RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1

Define Documentation

#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1

Definition at line 425 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)

Definition at line 423 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0

Definition at line 424 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: I2C2 Clock Source

Defines
I2C2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
#define | RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1

Define Documentation

#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1

Definition at line 436 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)

Definition at line 434 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0

Definition at line 435 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: I2C3 Clock Source

Defines
I2C3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
#define | RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1

Define Documentation

#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1

Definition at line 447 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)

Definition at line 445 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0

Definition at line 446 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: SAI1 Clock Source

Defines
SAI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
#define | RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
#define | RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
#define | RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL

Define Documentation

#define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL

Definition at line 460 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1

Definition at line 459 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)

Definition at line 455 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0

Definition at line 457 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

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STM32L486xx HAL User Manual: SAI2 Clock Source

Defines
SAI2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
#define | RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
#define | RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
#define | RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL

Define Documentation

#define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL

Definition at line 472 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1

Definition at line 471 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)

Definition at line 469 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0

Definition at line 470 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

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STM32L486xx HAL User Manual: LPTIM1 Clock Source

Defines
LPTIM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL

Define Documentation

#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1

Definition at line 483 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL

Definition at line 484 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0

Definition at line 482 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)

Definition at line 481 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: LPTIM2 Clock Source

Defines
LPTIM2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM2CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define | RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
#define | RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
#define | RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL

Define Documentation

#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1

Definition at line 494 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL

Definition at line 495 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0

Definition at line 493 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_LPTIM2CLKSOURCE_PCLK ((uint32_t)0x00000000U)

Definition at line 492 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: SDMMC1 Clock Source

Defines
SDMMC1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U)
#define | RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define | RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL

Define Documentation

#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL

Definition at line 511 of file stm32l4xx_hal_rcc_ex.h.

#define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U)

Definition at line 507 of file stm32l4xx_hal_rcc_ex.h.

#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

Definition at line 510 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0

Definition at line 509 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32L486xx HAL User Manual: RNG Clock Source

Defines
RNG Clock Source
RCCEx Exported Constants

Defines

#define | RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U)
#define | RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define | RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL

Define Documentation

#define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL

Definition at line 527 of file stm32l4xx_hal_rcc_ex.h.

#define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U)

Definition at line 523 of file stm32l4xx_hal_rcc_ex.h.

#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

Definition at line 526 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0

Definition at line 525 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32L486xx HAL User Manual: USB Clock Source

Defines
USB Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U)
#define | RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define | RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL

Define Documentation

#define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL

Definition at line 543 of file stm32l4xx_hal_rcc_ex.h.

#define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U)

Definition at line 539 of file stm32l4xx_hal_rcc_ex.h.

#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

Definition at line 542 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0

Definition at line 541 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32L486xx HAL User Manual: ADC Clock Source

Defines
ADC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U)
#define | RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
#define | RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
#define | RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL

Define Documentation

#define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U)

Definition at line 552 of file stm32l4xx_hal_rcc_ex.h.

#define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0

Definition at line 553 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1

Definition at line 555 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL

Definition at line 557 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32L486xx HAL User Manual: SWPMI1 Clock Source

Defines
SWPMI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SWPMI1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define | RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL

Define Documentation

#define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL

Definition at line 567 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_SWPMI1CLKSOURCE_PCLK ((uint32_t)0x00000000U)

Definition at line 566 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM1 Clock Source

Defines
DFSDM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define | RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL

Define Documentation

#define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)

Definition at line 577 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL

Definition at line 578 of file stm32l4xx_hal_rcc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC LSE CSS external interrupt line

Defines
RCC LSE CSS external interrupt line
RCCEx Exported Constants

Defines

#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19

Define Documentation

#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19

External interrupt line 19 connected to the LSE CSS EXTI Line

Definition at line 587 of file stm32l4xx_hal_rcc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCCEx Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
Enable PLLSAI1RDY interrupt.
#define | __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
Disable PLLSAI1RDY interrupt.
#define | __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
Clear the PLLSAI1RDY interrupt pending bit.
#define | __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
Check whether PLLSAI1RDY interrupt has occurred or not.
#define | __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
Check whether the PLLSAI1RDY flag is set or not.
#define | __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
Enable PLLSAI2RDY interrupt.
#define | __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
Disable PLLSAI2RDY interrupt.
#define | __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
Clear the PLLSAI2RDY interrupt pending bit.
#define | __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
Check whether the PLLSAI2RDY interrupt has occurred or not.
#define | __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
Check whether the PLLSAI2RDY flag is set or not.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Event Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Event Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
#define | __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
Clear the RCC LSE CSS EXTI flag.
#define | __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
Generate a Software interrupt on the RCC LSE CSS EXTI line.

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG ( ) WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)

Clear the RCC LSE CSS EXTI flag.

Return values:
None.

Definition at line 1653 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Event Line.

Return values:
None.

Definition at line 1594 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 1608 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Line.

Return values:
None

Definition at line 1582 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 1621 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                       \
    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

Return values:
None.

Definition at line 1637 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Event Line.

Return values:
None.

Definition at line 1588 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 1601 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Line.

Return values:
None

Definition at line 1576 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 1615 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                      \
    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

Return values:
None.

Definition at line 1627 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)

Generate a Software interrupt on the RCC LSE CSS EXTI line.

Return values:
None.

Definition at line 1659 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_GET_FLAG ( ) (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)

Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.

Return values:
EXTI RCC LSE CSS Line Status.

Definition at line 1647 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_CLEAR_IT ( ) WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)

Clear the PLLSAI1RDY interrupt pending bit.

Return values:
None

Definition at line 1530 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_DISABLE_IT ( ) CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)

Disable PLLSAI1RDY interrupt.

Return values:
None

Definition at line 1525 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_ENABLE_IT ( ) SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)

Enable PLLSAI1RDY interrupt.

Return values:
None

Definition at line 1520 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_GET_FLAG ( ) (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))

Check whether the PLLSAI1RDY flag is set or not.

Return values:
TRUE or FALSE.

Definition at line 1540 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE ( ) (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)

Check whether PLLSAI1RDY interrupt has occurred or not.

Return values:
TRUE or FALSE.

Definition at line 1535 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2_CLEAR_IT ( ) WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)

Clear the PLLSAI2RDY interrupt pending bit.

Return values:
None

Definition at line 1557 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2_DISABLE_IT ( ) CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)

Disable PLLSAI2RDY interrupt.

Return values:
None

Definition at line 1552 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2_ENABLE_IT ( ) SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)

Enable PLLSAI2RDY interrupt.

Return values:
None

Definition at line 1547 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2_GET_FLAG ( ) (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))

Check whether the PLLSAI2RDY flag is set or not.

Return values:
TRUE or FALSE.

Definition at line 1567 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2_GET_IT_SOURCE ( ) (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)

Check whether the PLLSAI2RDY interrupt has occurred or not.

Return values:
TRUE or FALSE.

Definition at line 1562 of file stm32l4xx_hal_rcc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCCEx Exported Macros

Modules | Defines
RCCEx Exported Macros
RCCEx

Modules

Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

Defines

#define | __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__)
Macro to configure the PLLSAI1 clock multiplication and division factors.
#define | __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
Macro to configure the PLLSAI1 clock multiplication factor N.
#define | __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
Macro to configure the PLLSAI1 clock division factor P.
#define | __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
Macro to configure the PLLSAI1 clock division factor Q.
#define | __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
Macro to configure the PLLSAI1 clock division factor R.
#define | __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
Macros to enable or disable the PLLSAI1.
#define | __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
#define | __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
#define | __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
#define | __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
#define | __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__)
Macro to configure the PLLSAI2 clock multiplication and division factors.
#define | __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
Macro to configure the PLLSAI2 clock multiplication factor N.
#define | __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
Macro to configure the PLLSAI2 clock division factor P.
#define | __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
Macro to configure the PLLSAI2 clock division factor R.
#define | __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
Macros to enable or disable the PLLSAI2.
#define | __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
#define | __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
#define | __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
#define | __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
#define | __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
Macro to configure the SAI1 clock source.
#define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
Macro to get the SAI1 clock source.
#define | __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
Macro to configure the SAI2 clock source.
#define | __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
Macro to get the SAI2 clock source.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
Macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
Macro to get the I2C2 clock source.
#define | __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
Macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
Macro to get the I2C3 clock source.
#define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
Macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
Macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
Macro to get the USART3 clock source.
#define | __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
Macro to configure the UART4 clock (UART4CLK).
#define | __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
Macro to get the UART4 clock source.
#define | __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
Macro to configure the UART5 clock (UART5CLK).
#define | __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
Macro to get the UART5 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
Macro to configure the LPUART1 clock (LPUART1CLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
Macro to get the LPUART1 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
Macro to get the LPTIM1 clock source.
#define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
Macro to configure the LPTIM2 clock (LPTIM2CLK).
#define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
Macro to get the LPTIM2 clock source.
#define | __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
Macro to configure the SDMMC1 clock.
#define | __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Macro to get the SDMMC1 clock.
#define | __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
Macro to configure the RNG clock.
#define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Macro to get the RNG clock.
#define | __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Macro to get the USB clock source.
#define | __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
Macro to configure the ADC interface clock.
#define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
Macro to get the ADC clock source.
#define | __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
Macro to configure the SWPMI1 clock.
#define | __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
Macro to get the SWPMI1 clock source.
#define | __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
Macro to configure the DFSDM1 clock.
#define | __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))
Macro to get the DFSDM1 clock source.

Define Documentation

#define __HAL_RCC_ADC_CONFIG ( __ADC_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))

Macro to configure the ADC interface clock.

Parameters:
__ADC_CLKSOURCE__ specifies the ADC digital interface clock source. This parameter can be one of the following values:
  • RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
  • RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
Return values:
None

Definition at line 1456 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_DFSDM1_CONFIG ( __DFSDM1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))

Macro to configure the DFSDM1 clock.

Parameters:
__DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. This parameter can be one of the following values:
  • RCC_DFSDM1CLKSOURCE_PCLK PCLK Clock selected as DFSDM1 clock
  • RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
Return values:
None

Definition at line 1499 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_ADC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))

Macro to get the ADC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
  • RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock

Definition at line 1468 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_DFSDM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))

Macro to get the DFSDM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_DFSDM1CLKSOURCE_PCLK PCLK Clock selected as DFSDM1 clock
  • RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock

Definition at line 1507 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2C1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))

Macro to get the I2C1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock

Definition at line 1091 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2C2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))

Macro to get the I2C2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock

Definition at line 1113 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2C3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))

Macro to get the I2C3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock

Definition at line 1135 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_LPTIM1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))

Macro to get the LPTIM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPUART1 clock
  • RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
  • RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
  • RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 1301 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_LPTIM2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))

Macro to get the LPTIM2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_PCLK PCLK selected as LPUART1 clock
  • RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock
  • RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock
  • RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 1323 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_LPUART1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))

Macro to get the LPUART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 1279 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG ( __PLLSAI1_CLOCKOUT__ ) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))

Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).

Parameters:
__PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. This parameter can be one of the following values:
  • RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case.
  • RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
  • RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
Return values:
SET / RESET

Definition at line 878 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG ( __PLLSAI2_CLOCKOUT__ ) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))

Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).

Parameters:
__PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. This parameter can be one of the following values:
  • RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case.
  • RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
Return values:
SET / RESET

Definition at line 1005 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_RNG_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))

Macro to get the RNG clock.

Return values:
The clock source can be one of the following values:
  • RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
  • RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
  • RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock

Definition at line 1405 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SAI1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))

Macro to get the SAI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
  • RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
  • RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
  • RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
Note:
Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 clock source when PLLs are disabled for devices without PLLSAI2.

Definition at line 1043 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))

Macro to get the SAI2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
  • RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
  • RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
  • RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)

Definition at line 1069 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SDMMC1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))

Macro to get the SDMMC1 clock.

Return values:
The clock source can be one of the following values:
  • RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
  • RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
  • RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
  • RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock

Definition at line 1369 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SWPMI1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))

Macro to get the SWPMI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SWPMI1CLKSOURCE_PCLK PCLK Clock selected as SWPMI1 clock
  • RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock

Definition at line 1487 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_UART4_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))

Macro to get the UART4 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock

Definition at line 1229 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_UART5_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))

Macro to get the UART5 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock

Definition at line 1255 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART1_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))

Macro to get the USART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock

Definition at line 1157 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART2_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))

Macro to get the USART2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock

Definition at line 1179 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART3_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))

Macro to get the USART3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock

Definition at line 1203 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USB_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))

Macro to get the USB clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
  • RCC_USBCLKSOURCE_MSI MSI selected as USB clock
  • RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
  • RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock

Definition at line 1441 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_I2C1_CONFIG ( __I2C1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))

Macro to configure the I2C1 clock (I2C1CLK).

Parameters:
__I2C1_CLKSOURCE__ specifies the I2C1 clock source. This parameter can be one of the following values:
  • RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
Return values:
None

Definition at line 1082 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C2_CONFIG ( __I2C2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))

Macro to configure the I2C2 clock (I2C2CLK).

Parameters:
__I2C2_CLKSOURCE__ specifies the I2C2 clock source. This parameter can be one of the following values:
  • RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
Return values:
None

Definition at line 1104 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C3_CONFIG ( __I2C3_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))

Macro to configure the I2C3 clock (I2C3CLK).

Parameters:
__I2C3_CLKSOURCE__ specifies the I2C3 clock source. This parameter can be one of the following values:
  • RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
Return values:
None

Definition at line 1126 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM1_CONFIG ( __LPTIM1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))

Macro to configure the LPTIM1 clock (LPTIM1CLK).

Parameters:
__LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. This parameter can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
Return values:
None

Definition at line 1291 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM2_CONFIG ( __LPTIM2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))

Macro to configure the LPTIM2 clock (LPTIM2CLK).

Parameters:
__LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. This parameter can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_PCLK PCLK selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
Return values:
None

Definition at line 1313 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPUART1_CONFIG ( __LPUART1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))

Macro to configure the LPUART1 clock (LPUART1CLK).

Parameters:
__LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. This parameter can be one of the following values:
  • RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
Return values:
None

Definition at line 1269 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI1_CONFIG | ( | __PLLSAI1N__,
 |  | __PLLSAI1P__,
 |  | __PLLSAI1Q__,
 |  | __PLLSAI1R__
 | ) |
Value:
WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
                   (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
                   ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
                   ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))

Macro to configure the PLLSAI1 clock multiplication and division factors.

Note:
This function must be used only when the PLLSAI1 is disabled.
PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between 8 and 86.
Note:
You have to set the PLLSAI1N parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz. PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
Parameters:
__PLLSAI1P__ | specifies the division factor for SAI clock. This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx else (2 to 31). SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
__PLLSAI1Q__ | specifies the division factor for USB/RNG/SDMMC1 clock. This parameter must be in the range (2, 4, 6 or 8). USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
__PLLSAI1R__ | specifies the division factor for SAR ADC clock. This parameter must be in the range (2, 4, 6 or 8). ADC clock frequency = f(PLLSAI1) / PLLSAI1R
Return values:
None

Definition at line 758 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1().

#define __HAL_RCC_PLLSAI1_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)

Definition at line 847 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI1(), HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define __HAL_RCC_PLLSAI1_DIVP_CONFIG ( __PLLSAI1P__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))

Macro to configure the PLLSAI1 clock division factor P.

Note:
This function must be used only when the PLLSAI1 is disabled.
PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLSAI1P__ specifies the division factor for SAI clock. This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx else (2 to 31). Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
Return values:
None

Definition at line 804 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG ( __PLLSAI1Q__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))

Macro to configure the PLLSAI1 clock division factor Q.

Note:
This function must be used only when the PLLSAI1 is disabled.
PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. This parameter must be in the range (2, 4, 6 or 8). Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
Return values:
None

Definition at line 821 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_DIVR_CONFIG ( __PLLSAI1R__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))

Macro to configure the PLLSAI1 clock division factor R.

Note:
This function must be used only when the PLLSAI1 is disabled.
PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLSAI1R__ specifies the division factor for ADC clock. This parameter must be in the range (2, 4, 6 or 8) Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
Return values:
None

Definition at line 836 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)

Macros to enable or disable the PLLSAI1.

Note:
The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
Return values:
None

Definition at line 845 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define __HAL_RCC_PLLSAI1_MULN_CONFIG ( __PLLSAI1N__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))

Macro to configure the PLLSAI1 clock multiplication factor N.

Note:
This function must be used only when the PLLSAI1 is disabled.
PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between 8 and 86.
Note:
You have to set the PLLSAI1N parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz. Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
Return values:
None

Definition at line 781 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE ( __PLLSAI1_CLOCKOUT__ ) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))

Definition at line 865 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI1().

#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE ( __PLLSAI1_CLOCKOUT__ ) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))

Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).

Note:
Enabling and disabling those clocks can be done without the need to stop the PLL. This is mainly used to save Power.
Parameters:
__PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. This parameter can be one or a combination of the following values:
  • RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case.
  • RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
  • RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
Return values:
None

Definition at line 863 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define __HAL_RCC_PLLSAI2_CONFIG | ( | __PLLSAI2N__,
 |  | __PLLSAI2P__,
 |  | __PLLSAI2R__
 | ) |
Value:
WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
                    (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
                    ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))

Macro to configure the PLLSAI2 clock multiplication and division factors.

Note:
This function must be used only when the PLLSAI2 is disabled.
PLLSAI2 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. This parameter must be a number between 8 and 86.
Note:
You have to set the PLLSAI2N parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz.
Parameters:
__PLLSAI2P__ | specifies the division factor for SAI clock. This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx else (2 to 31). SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
__PLLSAI2R__ | specifies the division factor for SAR ADC clock. This parameter must be in the range (2, 4, 6 or 8).
Return values:
None

Definition at line 914 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2().

#define __HAL_RCC_PLLSAI2_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)

Definition at line 978 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI2(), HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define __HAL_RCC_PLLSAI2_DIVP_CONFIG ( __PLLSAI2P__ ) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))

Macro to configure the PLLSAI2 clock division factor P.

Note:
This function must be used only when the PLLSAI2 is disabled.
PLLSAI2 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLSAI2P__ specifies the division factor. This parameter must be a number in the range (7 or 17). Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
Return values:
None

Definition at line 952 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2_DIVR_CONFIG ( __PLLSAI2R__ ) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))

Macro to configure the PLLSAI2 clock division factor R.

Note:
This function must be used only when the PLLSAI2 is disabled.
PLLSAI2 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLSAI2R__ specifies the division factor. This parameter must be in the range (2, 4, 6 or 8). Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
Return values:
None

Definition at line 967 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)

Macros to enable or disable the PLLSAI2.

Note:
The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
Return values:
None

Definition at line 976 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define __HAL_RCC_PLLSAI2_MULN_CONFIG ( __PLLSAI2N__ ) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))

Macro to configure the PLLSAI2 clock multiplication factor N.

Note:
This function must be used only when the PLLSAI2 is disabled.
PLLSAI2 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. This parameter must be a number between 8 and 86.
Note:
You have to set the PLLSAI2N parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz. PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
Return values:
None

Definition at line 937 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE ( __PLLSAI2_CLOCKOUT__ ) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))

Definition at line 994 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI2().

#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE ( __PLLSAI2_CLOCKOUT__ ) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))

Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).

Note:
Enabling and disabling those clocks can be done without the need to stop the PLL. This is mainly used to save Power.
Parameters:
__PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. This parameter can be one or a combination of the following values:
  • RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case.
  • RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
Return values:
None

Definition at line 992 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define __HAL_RCC_RNG_CONFIG ( __RNG_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))

Macro to configure the RNG clock.

Note:
USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Parameters:
__RNG_CLKSOURCE__ specifies the RNG clock source. This parameter can be one of the following values:
  • RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
  • RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
  • RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
Return values:
None

Definition at line 1390 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI1_CONFIG ( __SAI1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))

Macro to configure the SAI1 clock source.

Parameters:
__SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived from the PLLSAI1, system PLL or external clock (through a dedicated pin). This parameter can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
  • RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
  • RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
  • RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
Return values:
None

Definition at line 1027 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI2_CONFIG ( __SAI2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))

Macro to configure the SAI2 clock source.

Parameters:
__SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived from the PLLSAI2, system PLL or external clock (through a dedicated pin). This parameter can be one of the following values:
  • RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
  • RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
  • RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
  • RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
Return values:
None

Definition at line 1059 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SDMMC1_CONFIG ( __SDMMC1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))

Macro to configure the SDMMC1 clock.

Note:
USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Parameters:
__SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. This parameter can be one of the following values:
  • RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
  • RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
  • RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
  • RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
Return values:
None

Definition at line 1352 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SWPMI1_CONFIG ( __SWPMI1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))

Macro to configure the SWPMI1 clock.

Parameters:
__SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source. This parameter can be one of the following values:
  • RCC_SWPMI1CLKSOURCE_PCLK PCLK Clock selected as SWPMI1 clock
  • RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
Return values:
None

Definition at line 1479 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART4_CONFIG ( __UART4_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))

Macro to configure the UART4 clock (UART4CLK).

Parameters:
__UART4_CLKSOURCE__ specifies the UART4 clock source. This parameter can be one of the following values:
  • RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
Return values:
None

Definition at line 1219 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART5_CONFIG ( __UART5_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))

Macro to configure the UART5 clock (UART5CLK).

Parameters:
__UART5_CLKSOURCE__ specifies the UART5 clock source. This parameter can be one of the following values:
  • RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
Return values:
None

Definition at line 1245 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART1_CONFIG ( __USART1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))

Macro to configure the USART1 clock (USART1CLK).

Parameters:
__USART1_CLKSOURCE__ specifies the USART1 clock source. This parameter can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock
Return values:
None

Definition at line 1147 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART2_CONFIG ( __USART2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))

Macro to configure the USART2 clock (USART2CLK).

Parameters:
__USART2_CLKSOURCE__ specifies the USART2 clock source. This parameter can be one of the following values:
  • RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
Return values:
None

Definition at line 1169 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART3_CONFIG ( __USART3_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))

Macro to configure the USART3 clock (USART3CLK).

Parameters:
__USART3_CLKSOURCE__ specifies the USART3 clock source. This parameter can be one of the following values:
  • RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
Return values:
None

Definition at line 1193 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USB_CONFIG ( __USB_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))

Macro to configure the USB clock (USBCLK).

Note:
USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
Parameters:
__USB_CLKSOURCE__ specifies the USB clock source. This parameter can be one of the following values:
  • RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
  • RCC_USBCLKSOURCE_MSI MSI selected as USB clock
  • RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
  • RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
Return values:
None

Definition at line 1426 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCCEx_Private_Macros

Defines
RCCEx_Private_Macros
RCCEx

Defines

#define | IS_RCC_LSCOSOURCE(__SOURCE__)
#define | IS_RCC_PERIPHCLOCK(__SELECTION__)
#define | IS_RCC_USART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART2CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART3CLKSOURCE(__SOURCE__)
#define | IS_RCC_UART4CLKSOURCE(__SOURCE__)
#define | IS_RCC_UART5CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPUART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C2CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C3CLKSOURCE(__SOURCE__)
#define | IS_RCC_SAI1CLK(__SOURCE__)
#define | IS_RCC_SAI2CLK(__SOURCE__)
#define | IS_RCC_LPTIM1CLK(__SOURCE__)
#define | IS_RCC_LPTIM2CLK(__SOURCE__)
#define | IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)
#define | IS_RCC_RNGCLKSOURCE(__SOURCE__)
#define | IS_RCC_USBCLKSOURCE(__SOURCE__)
#define | IS_RCC_ADCCLKSOURCE(__SOURCE__)
#define | IS_RCC_SWPMI1CLKSOURCE(__SOURCE__)
#define | IS_RCC_DFSDM1CLKSOURCE(__SOURCE__)
#define | IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
#define | IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
#define | IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define | IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
#define | IS_RCC_PLLSAI1Q_VALUE(__VALUE__)
#define | IS_RCC_PLLSAI1R_VALUE(__VALUE__)
#define | IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
#define | IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
#define | IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define | IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
#define | IS_RCC_PLLSAI2R_VALUE(__VALUE__)

Define Documentation

#define IS_RCC_ADCCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \
                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))

Definition at line 2179 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_DFSDM1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK) || \
                ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))

Definition at line 2204 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
                ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))

Definition at line 2061 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C2CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
                ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))

Definition at line 2068 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C3CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
                ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))

Definition at line 2075 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM1CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) || \
                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)  || \
                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)  || \
                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))

Definition at line 2107 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM2CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) || \
                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)  || \
                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)  || \
                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))

Definition at line 2113 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPUART1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))

Definition at line 2055 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LSCOSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
                                       ((__SOURCE__) == RCC_LSCOSOURCE_LSE))

Definition at line 1905 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSCO().

#define IS_RCC_PERIPHCLOCK ( __SELECTION__ )
Value:
((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
                (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \
                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))

Definition at line 1989 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLSAI1M_VALUE ( __VALUE__ ) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))

Definition at line 2212 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define IS_RCC_PLLSAI1N_VALUE ( __VALUE__ ) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))

Definition at line 2214 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define IS_RCC_PLLSAI1P_VALUE ( __VALUE__ ) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))

Definition at line 2219 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define IS_RCC_PLLSAI1Q_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))

Definition at line 2222 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define IS_RCC_PLLSAI1R_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))

Definition at line 2225 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define IS_RCC_PLLSAI1SOURCE ( __VALUE__ ) IS_RCC_PLLSOURCE(__VALUE__)

Definition at line 2210 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define IS_RCC_PLLSAI2M_VALUE ( __VALUE__ ) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))

Definition at line 2232 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define IS_RCC_PLLSAI2N_VALUE ( __VALUE__ ) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))

Definition at line 2234 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define IS_RCC_PLLSAI2P_VALUE ( __VALUE__ ) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))

Definition at line 2239 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define IS_RCC_PLLSAI2R_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
                                            ((__VALUE__) == 6U) || ((__VALUE__) == 8U))

Definition at line 2242 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define IS_RCC_PLLSAI2SOURCE ( __VALUE__ ) IS_RCC_PLLSOURCE(__VALUE__)

Definition at line 2230 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define IS_RCC_RNGCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RNGCLKSOURCE_NONE)    || \
                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))

Definition at line 2149 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SAI1CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))

Definition at line 2082 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SAI2CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))

Definition at line 2099 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SDMMC1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE)    || \
                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))

Definition at line 2130 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SWPMI1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) || \
                ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))

Definition at line 2196 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_UART4CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1)  || \
                ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))

Definition at line 2037 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_UART5CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1)  || \
                ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))

Definition at line 2047 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
                ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))

Definition at line 2013 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART2CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
                ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))

Definition at line 2019 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USART3CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
                ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))

Definition at line 2027 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USBCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USBCLKSOURCE_NONE)    || \
                ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))

Definition at line 2168 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG_Private_Constants

Defines
RNG_Private_Constants
RNG

Defines

#define RNG_TIMEOUT_VALUE 2

Define Documentation

#define RNG_TIMEOUT_VALUE 2

Definition at line 80 of file stm32l4xx_hal_rng.c.

Referenced by HAL_RNG_GenerateRandomNumber().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG Exported Types

Data Structures | Enumerations
RNG Exported Types
RNG

Data Structures

struct RNG_HandleTypeDef
RNG Handle Structure definition. More...

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00, HAL_RNG_STATE_READY = 0x01, HAL_RNG_STATE_BUSY = 0x02, HAL_RNG_STATE_TIMEOUT = 0x03,
HAL_RNG_STATE_ERROR = 0x04
}
RNG HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_RNG_StateTypeDef

RNG HAL State Structure definition.

Enumerator:
HAL_RNG_STATE_RESET

RNG not yet initialized or disabled

HAL_RNG_STATE_READY

RNG initialized and ready for use

HAL_RNG_STATE_BUSY

RNG internal process is ongoing

HAL_RNG_STATE_TIMEOUT

RNG timeout state

HAL_RNG_STATE_ERROR

RNG error state

Definition at line 65 of file stm32l4xx_hal_rng.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RNG_HandleTypeDef Struct Reference
RNG Exported Types

RNG Handle Structure definition. More...

#include <stm32l4xx_hal_rng.h>

Data Fields

RNG_TypeDef * | Instance
HAL_LockTypeDef | Lock
__IO HAL_RNG_StateTypeDef | State
uint32_t | RandomNumber

Detailed Description

RNG Handle Structure definition.

Definition at line 78 of file stm32l4xx_hal_rng.h.

Field Documentation

RNG_TypeDef* RNG_HandleTypeDef::Instance

Register base address

Definition at line 80 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GetRandomNumber_IT(), HAL_RNG_Init(), and HAL_RNG_IRQHandler().

HAL_LockTypeDef RNG_HandleTypeDef::Lock

RNG locking object

Definition at line 82 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_Init().

uint32_t RNG_HandleTypeDef::RandomNumber

Last Generated RNG Data

Definition at line 86 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), HAL_RNG_GetRandomNumber(), HAL_RNG_IRQHandler(), and HAL_RNG_ReadLastRandomNumber().

__IO HAL_RNG_StateTypeDef RNG_HandleTypeDef::State

RNG communication state

Definition at line 84 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetRandomNumber_IT(), HAL_RNG_GetState(), HAL_RNG_Init(), and HAL_RNG_IRQHandler().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rng.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG Interrupts Definition

Defines
RNG Interrupts Definition
RNG Exported Constants

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS

Define Documentation

#define RNG_IT_CEI RNG_SR_CEIS

Clock error interrupt

Definition at line 103 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_DRDY RNG_SR_DRDY

Data Ready interrupt

Definition at line 102 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_SEI RNG_SR_SEIS

Seed error interrupt

Definition at line 104 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG Flags Definition

Defines
RNG Flags Definition
RNG Exported Constants

Defines

#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS

Define Documentation

#define RNG_FLAG_CECS RNG_SR_CECS

Clock error current status

Definition at line 113 of file stm32l4xx_hal_rng.h.

#define RNG_FLAG_DRDY RNG_SR_DRDY

Data ready

Definition at line 112 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define RNG_FLAG_SECS RNG_SR_SECS

Seed error current status

Definition at line 114 of file stm32l4xx_hal_rng.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG Exported Macros

Defines
RNG Exported Macros
RNG

Defines

#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enable the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disable the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified RNG flag is set or not.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clear the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enable the RNG interrupt.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disable the RNG interrupt.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.

Define Documentation

#define __HAL_RNG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | /* dummy macro */

Clear the selected RNG flag status.

Parameters:
__HANDLE__,: RNG handle
__FLAG__,: RNG flag to clear
Note:
WARNING: This is a dummy macro for HAL code alignment, flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
Return values:
None

Definition at line 169 of file stm32l4xx_hal_rng.h.

#define __HAL_RNG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))

Clear the RNG interrupt status flags.

Parameters:
__HANDLE__,: RNG Handle
__INTERRUPT__,: specifies the RNG interrupt status flag to clear. This parameter can be one of the following values:
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Note:
RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
Return values:
None

Definition at line 209 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)

Disable the RNG peripheral.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 146 of file stm32l4xx_hal_rng.h.

#define __HAL_RNG_DISABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)

Disable the RNG interrupt.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 185 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)

Enable the RNG peripheral.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 139 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define __HAL_RNG_ENABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)

Enable the RNG interrupt.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 178 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber_IT(), and HAL_RNG_GetRandomNumber_IT().

#define __HAL_RNG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified RNG flag is set or not.

Parameters:
__HANDLE__,: RNG Handle
__FLAG__,: RNG flag This parameter can be one of the following values:
  • RNG_FLAG_DRDY: Data ready
  • RNG_FLAG_CECS: Clock error current status
  • RNG_FLAG_SECS: Seed error current status
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 158 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define __HAL_RNG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified RNG interrupt has occurred or not.

Parameters:
__HANDLE__,: RNG Handle
__INTERRUPT__,: specifies the RNG interrupt status flag to check. This parameter can be one of the following values:
  • RNG_IT_DRDY: Data ready interrupt
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 197 of file stm32l4xx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)

Reset RNG handle state.

Parameters:
__HANDLE__,: RNG Handle
Return values:
None

Definition at line 132 of file stm32l4xx_hal_rng.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RNG Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initialize the RNG peripheral and initialize the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitialize the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initialize the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitialize the RNG MSP.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
          ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the RNG according to the specified parameters
          in the RNG_InitTypeDef and create the associated handle
      (+) DeInitialize the RNG peripheral
      (+) Initialize the RNG MSP (MCU Specific Package)
      (+) DeInitialize the RNG MSP

Function Documentation

HAL_StatusTypeDef HAL_RNG_DeInit ( RNG_HandleTypeDef * hrng )

DeInitialize the RNG peripheral.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
HAL status

Definition at line 159 of file stm32l4xx_hal_rng.c.

References HAL_RNG_MspDeInit(), HAL_RNG_STATE_RESET, RNG_HandleTypeDef::Instance, and RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_Init ( RNG_HandleTypeDef * hrng )

Initialize the RNG peripheral and initialize the associated handle.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
HAL status

Definition at line 118 of file stm32l4xx_hal_rng.c.

References __HAL_RNG_ENABLE, assert_param, HAL_RNG_MspInit(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, RNG_HandleTypeDef::Instance, RNG_HandleTypeDef::Lock, and RNG_HandleTypeDef::State.

void HAL_RNG_MspDeInit ( RNG_HandleTypeDef * hrng )

DeInitialize the RNG MSP.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
None

Definition at line 205 of file stm32l4xx_hal_rng.c.

Referenced by HAL_RNG_DeInit().

void HAL_RNG_MspInit ( RNG_HandleTypeDef * hrng )

Initialize the RNG MSP.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
None

Definition at line 190 of file stm32l4xx_hal_rng.c.

Referenced by HAL_RNG_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RNG Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generate a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generate a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handle RNG interrupt request.
uint32_t | HAL_RNG_GetRandomNumber (RNG_HandleTypeDef *hrng)
Return generated random number in polling mode (Obsolete).
uint32_t | HAL_RNG_GetRandomNumber_IT (RNG_HandleTypeDef *hrng)
Return a 32-bit random number with interrupt enabled (Obsolete).
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callback.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the 32 bit Random number
      (+) Get the 32 bit Random number with interrupt enabled
      (+) Handle RNG interrupt request

Function Documentation

void HAL_RNG_ErrorCallback ( RNG_HandleTypeDef * hrng )

RNG error callback.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
None

Definition at line 462 of file stm32l4xx_hal_rng.c.

Referenced by HAL_RNG_IRQHandler().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t * | random32bit
 | ) |  |

Generate a 32-bit random number.

Note:
Each time the random number data is read the RNG_FLAG_DRDY flag is automatically cleared.
Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
random32bit,: pointer to generated random number variable if successful.
Return values:
HAL status

Definition at line 244 of file stm32l4xx_hal_rng.c.

References __HAL_RNG_GET_FLAG, HAL_GetTick(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, RNG_HandleTypeDef::Instance, RNG_HandleTypeDef::RandomNumber, RNG_FLAG_DRDY, RNG_TIMEOUT_VALUE, and RNG_HandleTypeDef::State.

Referenced by HAL_RNG_GetRandomNumber().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Generate a 32-bit random number in interrupt mode.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
HAL status

Definition at line 297 of file stm32l4xx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, and RNG_HandleTypeDef::State.

uint32_t HAL_RNG_GetRandomNumber ( RNG_HandleTypeDef * hrng )

Return generated random number in polling mode (Obsolete).

Note:
Use HAL_RNG_GenerateRandomNumber() API instead.
Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
random value

Definition at line 389 of file stm32l4xx_hal_rng.c.

References HAL_RNG_GenerateRandomNumber(), and RNG_HandleTypeDef::RandomNumber.

uint32_t HAL_RNG_GetRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Return a 32-bit random number with interrupt enabled (Obsolete).

Note:
Use HAL_RNG_GenerateRandomNumber_IT() API instead.
Parameters:
hrng,: RNG handle
Return values:
32-bit random number

Definition at line 408 of file stm32l4xx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, HAL_RNG_STATE_BUSY, RNG_HandleTypeDef::Instance, and RNG_HandleTypeDef::State.

void HAL_RNG_IRQHandler ( RNG_HandleTypeDef * hrng )

Handle RNG interrupt request.

Note:
In the case of a clock error, the RNG is no more able to generate random numbers because the PLL48CLK clock is not correct. User has to check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used.
In the case of a seed error, the generation of random numbers is interrupted as long as the SECS bit is '1'. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. In this case, it is recommended to clear the SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable the RNG peripheral to reinitialize and restart the RNG.
User-written HAL_RNG_ErrorCallback() API is called once whether SEIS or CEIS are set.
Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
None

Definition at line 347 of file stm32l4xx_hal_rng.c.

References __HAL_RNG_CLEAR_IT, __HAL_RNG_DISABLE_IT, __HAL_RNG_GET_IT, HAL_RNG_ErrorCallback(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, RNG_HandleTypeDef::Instance, RNG_HandleTypeDef::RandomNumber, RNG_IT_CEI, RNG_IT_DRDY, RNG_IT_SEI, and RNG_HandleTypeDef::State.

uint32_t HAL_RNG_ReadLastRandomNumber ( RNG_HandleTypeDef * hrng )

Read latest generated random number.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
random value

Definition at line 435 of file stm32l4xx_hal_rng.c.

References RNG_HandleTypeDef::RandomNumber.

void HAL_RNG_ReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t | random32bit
 | ) |  |

Data Ready callback in non-blocking mode.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
random32bit,: generated random value
Return values:
None

Definition at line 446 of file stm32l4xx_hal_rng.c.

Referenced by HAL_RNG_IRQHandler().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RNG Exported Functions

Peripheral State functions. More...

Functions

HAL_RNG_StateTypeDef HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Return the RNG handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_RNG_StateTypeDef HAL_RNG_GetState ( RNG_HandleTypeDef * hrng )

Return the RNG handle state.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
HAL state

Definition at line 495 of file stm32l4xx_hal_rng.c.

References RNG_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..] This section provide functions allowing to initialize and configure the
         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
         RTC registers Write protection, enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
             It is split into 2 programmable prescalers to minimize power consumption.
             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
             (++) When both prescalers are used, it is recommended to configure the
                 asynchronous prescaler to a high value to minimize power consumption.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by writing a key into the Write Protection register, RTC_WPR.
         (#) To configure the RTC Calendar, user application should enter
             initialization mode. In this mode, the calendar counter is stopped
             and its value can be updated. When the initialization sequence is
             complete, the calendar restarts counting after 4 RTCCLK cycles.
         (#) To read the calendar through the shadow registers after Calendar
             initialization, calendar update or after wakeup from low power modes
             the software must first clear the RSF flag. The software must then
             wait until it is set again before reading the calendar, which means
             that the calendar registers have been correctly copied into the
             RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function
             implements the above software sequence (RSF clear and RSF check).

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC peripheral.

Parameters:
hrtc,: RTC handle
Note:
This function doesn't reset the RTC Backup Data registers.
Return values:
HAL status

Definition at line 263 of file stm32l4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_RESET, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 186 of file stm32l4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_InitTypeDef::AsynchPrediv, HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, RTC_InitTypeDef::HourFormat, RTC_HandleTypeDef::Init, RTC_HandleTypeDef::Instance, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, IS_RTC_OUTPUT_REMAP, IS_RTC_OUTPUT_TYPE, IS_RTC_SYNCH_PREDIV, RTC_HandleTypeDef::Lock, RTC_InitTypeDef::OutPut, RTC_InitTypeDef::OutPutPolarity, RTC_InitTypeDef::OutPutRemap, RTC_InitTypeDef::OutPutType, RTC_EnterInitMode(), RTC_HandleTypeDef::State, and RTC_InitTypeDef::SynchPrediv.

void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC MSP.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 381 of file stm32l4xx_hal_rtc.c.

Referenced by HAL_RTC_DeInit().

void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initialize the RTC MSP.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 366 of file stm32l4xx_hal_rtc.c.

Referenced by HAL_RTC_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Time and Date functions

Functions
RTC Time and Date functions
RTC Exported Functions

RTC Time and Date functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.

Detailed Description

RTC Time and Date functions.

 ===============================================================================
                 ##### RTC Time and Date functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Time and Date features

Function Documentation

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Get RTC current date.

Parameters:
hrtc,: RTC handle
sDate,: Pointer to Date structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read.
Return values:
HAL status

Definition at line 709 of file stm32l4xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Get RTC current time.

Parameters:
hrtc,: RTC handle
sTime,: Pointer to Time structure with Hours, Minutes and Seconds fields returned with input format (BIN or BCD), also SubSeconds field returning the RTC_SSR register content and SecondFraction field the Synchronous pre-scaler factor to be used for second fraction ratio computation.
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds value in second fraction ratio with time unit following generic formula: Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read to ensure consistency between the time and date values.
Return values:
HAL status

Definition at line 554 of file stm32l4xx_hal_rtc.c.

References assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::SecondFraction, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Set RTC current date.

Parameters:
hrtc,: RTC handle
sDate,: Pointer to date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 598 of file stm32l4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_DateTypeDef::Date, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Set RTC current time.

Parameters:
hrtc,: RTC handle
sTime,: Pointer to Time structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 419 of file stm32l4xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TimeTypeDef::DayLightSaving, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_DAYLIGHT_SAVING, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, IS_RTC_STORE_OPERATION, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::StoreOperation, and RTC_TimeTypeDef::TimeFormat.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Alarm functions

Functions
RTC Alarm functions
RTC Exported Functions

RTC Alarm functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.

Detailed Description

RTC Alarm functions.

 ===============================================================================
                 ##### RTC Alarm functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Alarm feature

Function Documentation

void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 1319 of file stm32l4xx_hal_rtc.c.

Referenced by HAL_RTC_AlarmIRQHandler().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Alarm interrupt request.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 1277 of file stm32l4xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_EXTI_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARM_GET_IT_SOURCE, HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, HAL_RTCEx_AlarmBEventCallback(), RTC_FLAG_ALRAF, RTC_FLAG_ALRBF, RTC_IT_ALRA, RTC_IT_ALRB, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactivate the specified RTC Alarm.

Parameters:
hrtc,: RTC handle
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Return values:
HAL status

Definition at line 1132 of file stm32l4xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, IS_RTC_ALARM, RTC_ALARM_A, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Get the RTC Alarm value and masks.

Parameters:
hrtc,: RTC handle
sAlarm,: Pointer to Date structure
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1226 of file stm32l4xx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARM_B, RTC_ALARMMASK_ALL, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle AlarmA Polling request.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1335 of file stm32l4xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRAF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm.

Parameters:
hrtc,: RTC handle
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 763 of file stm32l4xx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm with Interrupt.

Parameters:
hrtc,: RTC handle
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the HAL_RTC_DeactivateAlarm()).
The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
Return values:
HAL status

Definition at line 947 of file stm32l4xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAF, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RTC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1394 of file stm32l4xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_SetSynchroShift().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RTC Exported Functions

Peripheral State functions. More...

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

Return the RTC handle state.

Parameters:
hrtc,: RTC handle
Return values:
HAL state

Definition at line 1438 of file stm32l4xx_hal_rtc.c.

References RTC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Private functions

Functions
RTC Private functions
RTC

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Function Documentation

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Convert from 2 digit BCD to Binary.

Parameters:
Value,: BCD value to be converted
Return values:
Converted word

Definition at line 1510 of file stm32l4xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Convert a 2 digit decimal to BCD format.

Parameters:
Value,: Byte to be converted
Return values:
Converted byte

Definition at line 1492 of file stm32l4xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

Enter the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1462 of file stm32l4xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_INIT_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Exported Types

Data Structures | Enumerations
RTC Exported Types
RTC

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_HandleTypeDef
Time Handle Structure definition. More...

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00, HAL_RTC_STATE_READY = 0x01, HAL_RTC_STATE_BUSY = 0x02, HAL_RTC_STATE_TIMEOUT = 0x03,
HAL_RTC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_RTCStateTypeDef

HAL State structures definition.

Enumerator:
HAL_RTC_STATE_RESET

RTC not yet initialized or disabled

HAL_RTC_STATE_READY

RTC initialized and ready for use

HAL_RTC_STATE_BUSY

RTC process is ongoing

HAL_RTC_STATE_TIMEOUT

RTC timeout state

HAL_RTC_STATE_ERROR

RTC error state

Definition at line 64 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InitTypeDef Struct Reference
RTC Exported Types

RTC Configuration Structure definition. More...

#include <stm32l4xx_hal_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrediv
uint32_t | SynchPrediv
uint32_t | OutPut
uint32_t | OutPutRemap
uint32_t | OutPutPolarity
uint32_t | OutPutType

Detailed Description

RTC Configuration Structure definition.

Definition at line 77 of file stm32l4xx_hal_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

Definition at line 82 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::HourFormat

Specifies the RTC Hour Format. This parameter can be a value of RTC Hour Formats

Definition at line 79 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPut

Specifies which signal will be routed to the RTC output. This parameter can be a value of RTC Output Selection Definitions

Definition at line 88 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPolarity

Specifies the polarity of the output signal. This parameter can be a value of RTC Output Polarity Definitions

Definition at line 94 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutRemap

Specifies the remap for RTC output. This parameter can be a value of RTC Output ALARM OUT Remap

Definition at line 91 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutType

Specifies the RTC Output Pin mode. This parameter can be a value of RTC Output Type ALARM OUT

Definition at line 97 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::SynchPrediv

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

Definition at line 85 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rtc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TimeTypeDef Struct Reference
RTC Exported Types

RTC Time structure definition. More...

#include <stm32l4xx_hal_rtc.h>

Data Fields

uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds
uint8_t | TimeFormat
uint32_t | SubSeconds
uint32_t | SecondFraction
uint32_t | DayLightSaving
uint32_t | StoreOperation

Detailed Description

RTC Time structure definition.

Definition at line 104 of file stm32l4xx_hal_rtc.h.

Field Documentation

uint32_t RTC_TimeTypeDef::DayLightSaving

Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of RTC DayLight Saving Definitions

Definition at line 129 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Hours

Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected

Definition at line 106 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 110 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::SecondFraction

Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function

Definition at line 123 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime().

uint8_t RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 113 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::StoreOperation

Specifies RTC_StoreOperation value to be written in the BCK bit in CR register to store the operation. This parameter can be a value of RTC Store Operation Definitions

Definition at line 132 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint32_t RTC_TimeTypeDef::SubSeconds

Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity

Definition at line 119 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of RTC AM PM Definitions

Definition at line 116 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rtc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_DateTypeDef Struct Reference
RTC Exported Types

RTC Date structure definition. More...

#include <stm32l4xx_hal_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Date
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 140 of file stm32l4xx_hal_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::Date

Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 148 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC Month Date Definitions

Definition at line 145 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of RTC WeekDay Definitions

Definition at line 142 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

Definition at line 151 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rtc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_AlarmTypeDef Struct Reference
RTC Exported Types

RTC Alarm structure definition. More...

#include <stm32l4xx_hal_rtc.h>

Data Fields

RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmSubSecondMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay
uint32_t | Alarm

Detailed Description

RTC Alarm structure definition.

Definition at line 159 of file stm32l4xx_hal_rtc.h.

Field Documentation

uint32_t RTC_AlarmTypeDef::Alarm

Specifies the alarm . This parameter can be a value of RTC Alarms Definitions

Definition at line 176 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint8_t RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC WeekDay Definitions

Definition at line 172 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC Alarm Date WeekDay Definitions

Definition at line 169 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of RTC Alarm Mask Definitions

Definition at line 163 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmSubSecondMask

Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of RTC Alarm Sub Seconds Masks Definitions

Definition at line 166 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

RTC_TimeTypeDef RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members

Definition at line 161 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rtc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_HandleTypeDef Struct Reference
RTC Exported Types

Time Handle Structure definition. More...

#include <stm32l4xx_hal_rtc.h>

Data Fields

RTC_TypeDef * | Instance
RTC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RTCStateTypeDef | State

Detailed Description

Time Handle Structure definition.

Definition at line 183 of file stm32l4xx_hal_rtc.h.

Field Documentation

RTC_InitTypeDef RTC_HandleTypeDef::Init

RTC required parameters

Definition at line 187 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

RTC_TypeDef* RTC_HandleTypeDef::Instance

Register base address

Definition at line 185 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_GetWakeUpTimer(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

HAL_LockTypeDef RTC_HandleTypeDef::Lock

RTC locking object

Definition at line 189 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

__IO HAL_RTCStateTypeDef RTC_HandleTypeDef::State

Time communication state

Definition at line 191 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetState(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperTimeStampIRQHandler(), and HAL_RTCEx_WakeUpTimerIRQHandler().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rtc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Hour Formats

Defines
RTC Hour Formats
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define | RTC_HOURFORMAT_12 ((uint32_t)0x00000040)

Define Documentation

#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)

Definition at line 208 of file stm32l4xx_hal_rtc.h.

#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)

Definition at line 207 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Output Polarity Definitions

Defines
RTC Output Polarity Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define | RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)

Define Documentation

#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)

Definition at line 216 of file stm32l4xx_hal_rtc.h.

#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)

Definition at line 217 of file stm32l4xx_hal_rtc.h.

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STM32L486xx HAL User Manual: RTC Output Type ALARM OUT

Defines
RTC Output Type ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define | RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)

Define Documentation

#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)

Definition at line 225 of file stm32l4xx_hal_rtc.h.

#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)

Definition at line 226 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Output ALARM OUT Remap

Defines
RTC Output ALARM OUT Remap
RTC Exported Constants

Defines

#define | RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000)
#define | RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)

Define Documentation

#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000)

Definition at line 234 of file stm32l4xx_hal_rtc.h.

#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)

Definition at line 235 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC AM PM Definitions

Defines
RTC AM PM Definitions
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40)

Define Documentation

#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)

Definition at line 243 of file stm32l4xx_hal_rtc.h.

#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)

Definition at line 244 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC DayLight Saving Definitions

Defines
RTC DayLight Saving Definitions
RTC Exported Constants

Defines

#define | RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define | RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define | RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)

Define Documentation

#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)

Definition at line 253 of file stm32l4xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)

Definition at line 254 of file stm32l4xx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)

Definition at line 252 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Store Operation Definitions

Defines
RTC Store Operation Definitions
RTC Exported Constants

Defines

#define | RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define | RTC_STOREOPERATION_SET ((uint32_t)0x00040000)

Define Documentation

#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)

Definition at line 262 of file stm32l4xx_hal_rtc.h.

#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)

Definition at line 263 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Input Parameter Format Definitions

Defines
RTC Input Parameter Format Definitions
RTC Exported Constants

Defines

#define | RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define | RTC_FORMAT_BCD ((uint32_t)0x000000001)

Define Documentation

#define RTC_FORMAT_BCD ((uint32_t)0x000000001)

Definition at line 272 of file stm32l4xx_hal_rtc.h.

#define RTC_FORMAT_BIN ((uint32_t)0x000000000)

Definition at line 271 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Month Date Definitions

Defines
RTC Month Date Definitions
RTC Exported Constants

Defines

#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)

Define Documentation

#define RTC_MONTH_APRIL ((uint8_t)0x04)

Definition at line 285 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_AUGUST ((uint8_t)0x08)

Definition at line 289 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_DECEMBER ((uint8_t)0x12)

Definition at line 293 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)

Definition at line 283 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_JANUARY ((uint8_t)0x01)

Definition at line 282 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_JULY ((uint8_t)0x07)

Definition at line 288 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_JUNE ((uint8_t)0x06)

Definition at line 287 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_MARCH ((uint8_t)0x03)

Definition at line 284 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_MAY ((uint8_t)0x05)

Definition at line 286 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)

Definition at line 292 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_OCTOBER ((uint8_t)0x10)

Definition at line 291 of file stm32l4xx_hal_rtc.h.

#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)

Definition at line 290 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC WeekDay Definitions

Defines
RTC WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)

Define Documentation

#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)

Definition at line 305 of file stm32l4xx_hal_rtc.h.

#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)

Definition at line 301 of file stm32l4xx_hal_rtc.h.

#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)

Definition at line 306 of file stm32l4xx_hal_rtc.h.

#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)

Definition at line 307 of file stm32l4xx_hal_rtc.h.

#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)

Definition at line 304 of file stm32l4xx_hal_rtc.h.

#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)

Definition at line 302 of file stm32l4xx_hal_rtc.h.

#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)

Definition at line 303 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Alarm Date WeekDay Definitions

Defines
RTC Alarm Date WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)

Define Documentation

#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)

Definition at line 315 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)

Definition at line 316 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Alarm Mask Definitions

Defines
RTC Alarm Mask Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL ((uint32_t)0x80808080)

Define Documentation

#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)

Definition at line 330 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Definition at line 326 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3

Definition at line 327 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2

Definition at line 328 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)

Definition at line 325 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1

Definition at line 329 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Alarms Definitions

Defines
RTC Alarms Definitions
RTC Exported Constants

Defines

#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE

Define Documentation

#define RTC_ALARM_A RTC_CR_ALRAE

Definition at line 338 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARM_B RTC_CR_ALRBE

Definition at line 339 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Alarm Sub Seconds Masks Definitions

Defines
RTC Alarm Sub Seconds Masks Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000)
#define | RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000)
#define | RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000)

Define Documentation

#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000)

All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm

Definition at line 347 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000)

SS[14:0] are compared and must match to activate alarm.

Definition at line 378 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000)

SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared

Definition at line 376 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000)

SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared.

Definition at line 350 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000)

SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared

Definition at line 368 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000)

SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared

Definition at line 370 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000)

SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared

Definition at line 372 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000)

SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared

Definition at line 374 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000)

SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared

Definition at line 352 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000)

SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared

Definition at line 354 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000)

SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared

Definition at line 356 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000)

SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared

Definition at line 358 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000)

SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared

Definition at line 360 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000)

SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared

Definition at line 362 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000)

SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared

Definition at line 364 of file stm32l4xx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000)

SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared

Definition at line 366 of file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Interrupts Definitions

Defines
RTC Interrupts Definitions
RTC Exported Constants

Defines

#define | RTC_IT_TS ((uint32_t)RTC_CR_TSIE)
#define | RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)
#define | RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
#define | RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
#define | RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE)
#define | RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
#define | RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)
#define | RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)

Define Documentation

#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)

Enable Alarm A Interrupt

Definition at line 389 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)

Enable Alarm B Interrupt

Definition at line 390 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE)

Enable all Tamper Interrupt

Definition at line 391 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)

Enable Tamper 1 Interrupt

Definition at line 392 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)

Enable Tamper 2 Interrupt

Definition at line 393 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)

Enable Tamper 3 Interrupt

Definition at line 394 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE)

Enable Timestamp Interrupt

Definition at line 387 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)

Enable Wakeup timer Interrupt

Definition at line 388 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Flags Definitions

Defines
RTC Flags Definitions
RTC Exported Constants

Defines

#define | RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
#define | RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
#define | RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
#define | RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
#define | RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define | RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#define | RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
#define | RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define | RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define | RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
#define | RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
#define | RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
#define | RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
#define | RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
#define | RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
#define | RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
#define | RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)

Define Documentation

#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)

Definition at line 411 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)

Definition at line 418 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)

Definition at line 410 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)

Definition at line 417 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)

Definition at line 412 of file stm32l4xx_hal_rtc.h.

#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)

Definition at line 414 of file stm32l4xx_hal_rtc.h.

#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)

Definition at line 408 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp().

#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)

Definition at line 402 of file stm32l4xx_hal_rtc.h.

#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)

Definition at line 413 of file stm32l4xx_hal_rtc.h.

#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)

Definition at line 415 of file stm32l4xx_hal_rtc.h.

#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)

Definition at line 405 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)

Definition at line 404 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper2Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)

Definition at line 403 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)

Definition at line 407 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)

Definition at line 406 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent().

#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)

Definition at line 409 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)

Definition at line 416 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Exported Macros

Defines
RTC Exported Macros
RTC

Defines

#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt is enabled or not.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.

Define Documentation

#define __HAL_RTC_ALARM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Alarm's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
Return values:
None

Definition at line 543 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC Alarm interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 508 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), and HAL_RTC_SetAlarm().

#define __HAL_RTC_ALARM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC Alarm interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 497 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG ( ) (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)

Clear the RTC Alarm associated Exti line flag.

Return values:
None

Definition at line 632 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable event on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 578 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 590 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 566 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 602 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                             __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
                                                             __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
                                                           } while(0)

Disable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 617 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable event on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 572 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 584 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 560 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 596 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                             __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
                                                             __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
                                                           } while(0)

Enable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None

Definition at line 608 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)

Generate a Software interrupt on RTC Alarm associated Exti line.

Return values:
None

Definition at line 638 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GET_FLAG ( ) (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)

Check whether the RTC Alarm associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 626 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC Alarm's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to check. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
  • RTC_FLAG_ALRAWF
  • RTC_FLAG_ALRBWF
Return values:
None

Definition at line 532 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)

Check whether the specified RTC Alarm interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 519 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Alarm interrupt is enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 554 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))

Disable the RTC ALARMA peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 472 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))

Enable the RTC ALARMA peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 465 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))

Disable the RTC ALARMB peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 486 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))

Enable the RTC ALARMB peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 479 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)

Reset RTC handle state.

Parameters:
__HANDLE__,: RTC handle.
Return values:
None

Definition at line 436 of file stm32l4xx_hal_rtc.h.

#define __HAL_RTC_WRITEPROTECTION_DISABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xCA;   \
                            (__HANDLE__)->Instance->WPR = 0x53;   \
                          } while(0)

Disable the write protection for RTC registers.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 443 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WRITEPROTECTION_ENABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xFF;   \
                          } while(0)

Enable the write protection for RTC registers.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 454 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define | RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define | RTC_TIMEOUT_VALUE 1000
#define | RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00040000)

Define Documentation

#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)

Definition at line 722 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00040000)

External interrupt line 18 Connected to the RTC Alarm event

Definition at line 728 of file stm32l4xx_hal_rtc.h.

#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)

Definition at line 723 of file stm32l4xx_hal_rtc.h.

Referenced by RTC_EnterInitMode().

#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)

Definition at line 724 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro().

#define RTC_TIMEOUT_VALUE 1000

Definition at line 726 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)

Definition at line 721 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Private macros to check input parameters

Defines
RTC Private macros to check input parameters
RTC Private Macros

Defines

#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
#define | IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)

Define Documentation

#define IS_RTC_ALARM ( ALARM ) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))

Definition at line 795 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_DATE ( DATE ) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))

Definition at line 780 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_SEL ( SEL )
Value:
(((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))

Definition at line 790 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 782 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_MASK ( MASK ) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)

Definition at line 793 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_MASK ( MASK )
Value:
(((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))

Definition at line 799 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_VALUE ( VALUE ) ((VALUE) <= (uint32_t)0x00007FFF)

Definition at line 797 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ASYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (uint32_t)0x7F)

Definition at line 816 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_DATE ( DATE ) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))

Definition at line 770 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_DAYLIGHT_SAVING ( SAVE )
Value:
(((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))

Definition at line 757 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_FORMAT ( FORMAT ) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))

Definition at line 764 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

#define IS_RTC_HOUR12 ( HOUR ) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))

Definition at line 820 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR24 ( HOUR ) ((HOUR) <= (uint32_t)23)

Definition at line 822 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_HOURFORMAT_12) || \
                                        ((FORMAT) == RTC_HOURFORMAT_24))

Definition at line 743 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_HOURFORMAT12 ( PM ) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))

Definition at line 755 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MINUTES ( MINUTES ) ((MINUTES) <= (uint32_t)59)

Definition at line 824 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MONTH ( MONTH ) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))

Definition at line 768 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_OUTPUT_POL ( POL )
Value:
(((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
                                ((POL) == RTC_OUTPUT_POLARITY_LOW))

Definition at line 746 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_REMAP ( REMAP )
Value:
(((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
                                      ((REMAP) == RTC_OUTPUT_REMAP_POS1))

Definition at line 752 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_TYPE ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))

Definition at line 749 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SECONDS ( SECONDS ) ((SECONDS) <= (uint32_t)59)

Definition at line 826 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_STORE_OPERATION ( OPERATION )
Value:
(((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                           ((OPERATION) == RTC_STOREOPERATION_SET))

Definition at line 761 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_SYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (uint32_t)0x7FFF)

Definition at line 818 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 772 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_YEAR ( YEAR ) ((YEAR) <= (uint32_t)99)

Definition at line 766 of file stm32l4xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC TimeStamp and Tamper functions

Functions
RTC TimeStamp and Tamper functions
RTCEx Exported Functions

RTC TimeStamp and Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 3 Polling.

Detailed Description

RTC TimeStamp and Tamper functions.

 ===============================================================================
                 ##### RTC TimeStamp and Tamper functions #####
 ===============================================================================

 [..] This section provide functions allowing to configure TimeStamp feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate Internal TimeStamp.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 381 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivate Tamper.

Parameters:
hrtc,: RTC handle
Tamper,: Selected tamper pin. This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
Return values:
HAL status

Definition at line 656 of file stm32l4xx_hal_rtc_ex.c.

References assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, RTC_IT_TAMP, RTC_IT_TAMP1, RTC_IT_TAMP2, RTC_IT_TAMP3, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate TimeStamp.

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 311 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_DISABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_IT_TS, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTimeStamp,
 |  | RTC_DateTypeDef * | sTimeStampDate,
 |  | uint32_t | Format
 | ) |  |

Get the RTC TimeStamp value.

Parameters:
hrtc,: RTC handle
sTimeStamp,: Pointer to Time structure
sTimeStampDate,: Pointer to Date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 416 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, assert_param, RTC_DateTypeDef::Date, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FLAG_ITSF, RTC_FLAG_TSF, RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, RTC_TimeTypeDef::TimeFormat, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper 1 Polling.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 880 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP1F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper 2 Polling.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 913 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP2F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper 3 Polling.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 946 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP3F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle TimeStamp polling request.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 840 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TSF, RTC_FLAG_TSOVF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Set Internal TimeStamp.

Note:
This API must be called before enabling the internal TimeStamp feature.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 350 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper.

Note:
By calling this API we disable the tamper interrupt for all tampers.
Parameters:
hrtc,: RTC handle
sTamper,: Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 468 of file stm32l4xx_hal_rtc_ex.c.

References assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPCR_MASK, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper with interrupt.

Note:
By calling this API we force the tamper interrupt for all tampers.
Parameters:
hrtc,: RTC handle
sTamper,: Pointer to RTC Tamper.
Return values:
HAL status

Definition at line 559 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE, assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_TamperTypeDef::Interrupt, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_INTERRUPT, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPCR_MASK, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc,: RTC handle
TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin,: specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 205 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp with Interrupt.

Parameters:
hrtc,: RTC handle
Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
TimeStampEdge,: Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin,: Specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 261 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_TIMESTAMP_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, RTC_IT_TS, and RTC_HandleTypeDef::State.

void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 791 of file stm32l4xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 2 callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 807 of file stm32l4xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 3 callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 823 of file stm32l4xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_TamperTimeStampIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle TimeStamp interrupt request.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 701 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, __HAL_RTC_TAMPER_GET_IT_SOURCE, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, __HAL_RTC_TIMESTAMP_GET_IT_SOURCE, HAL_RTC_STATE_READY, HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), RTC_FLAG_TAMP1F, RTC_FLAG_TAMP2F, RTC_FLAG_TAMP3F, RTC_FLAG_TSF, RTC_IT_TAMP, RTC_IT_TAMP1, RTC_IT_TAMP2, RTC_IT_TAMP3, RTC_IT_TS, and RTC_HandleTypeDef::State.

void HAL_RTCEx_TimeStampEventCallback ( RTC_HandleTypeDef * hrtc )

TimeStamp callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 775 of file stm32l4xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Wake-up functions

Functions
RTC Wake-up functions
RTCEx Exported Functions

RTC Wake-up functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.

Detailed Description

RTC Wake-up functions.

 ===============================================================================
                        ##### RTC Wake-up functions #####
 ===============================================================================

 [..] This section provide functions allowing to configure Wake-up feature

Function Documentation

uint32_t HAL_RTCEx_DeactivateWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Deactivate wake up timer counter.

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1184 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_DISABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

uint32_t HAL_RTCEx_GetWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Get wake up timer counter.

Parameters:
hrtc,: RTC handle
Return values:
Counter value

Definition at line 1236 of file stm32l4xx_hal_rtc_ex.c.

References RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Wake Up Timer Polling.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1288 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer.

Parameters:
hrtc,: RTC handle
WakeUpCounter,: Wake up counter
WakeUpClock,: Wake up clock
Return values:
HAL status

Definition at line 998 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTWF, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer with interrupt.

Parameters:
hrtc,: RTC handle
WakeUpCounter,: Wake up counter
WakeUpClock,: Wake up clock
Return values:
HAL status

Definition at line 1088 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

void HAL_RTCEx_WakeUpTimerEventCallback ( RTC_HandleTypeDef * hrtc )

Wake Up Timer callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 1272 of file stm32l4xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_RTCEx_WakeUpTimerIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Wake Up Timer interrupt request.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 1247 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_RTC_STATE_READY, HAL_RTCEx_WakeUpTimerEventCallback(), RTC_FLAG_WUTF, and RTC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RTCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Read data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extended Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Write a data in a specified RTC Backup data register
      (+) Read a data in a specified RTC Backup data register
      (+) Set the Coarse calibration parameters.
      (+) Deactivate the Coarse calibration parameters
      (+) Set the Smooth calibration parameters.
      (+) Configure the Synchronization Shift Control Settings.
      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Enable the RTC reference clock detection.
      (+) Disable the RTC reference clock detection.
      (+) Enable the Bypass Shadow feature.
      (+) Disable the Bypass Shadow feature.

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Read data from the specified RTC Backup data Register.

Parameters:
hrtc,: RTC handle
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Return values:
Read value

Definition at line 1376 of file stm32l4xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Write a data in a specified RTC Backup data register.

Parameters:
hrtc,: RTC handle
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Data,: Data to be written in the specified RTC Backup data register.
Return values:
None

Definition at line 1354 of file stm32l4xx_hal_rtc_ex.c.

References assert_param, RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut ( RTC_HandleTypeDef * hrtc )

Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1608 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock ( RTC_HandleTypeDef * hrtc )

Disable the RTC reference clock detection.

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1686 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow ( RTC_HandleTypeDef * hrtc )

Disable the Bypass Shadow feature.

Parameters:
hrtc,: RTC handle
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1769 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow ( RTC_HandleTypeDef * hrtc )

Enable the Bypass Shadow feature.

Parameters:
hrtc,: RTC handle
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1737 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibOutput
 | ) |  |

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc,: RTC handle
CalibOutput : Select the Calibration output Selection . This parameter can be one of the following values:
  • RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
  • RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
Return values:
HAL status

Definition at line 1570 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_CALIB_OUTPUT, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetRefClock ( RTC_HandleTypeDef * hrtc )

Enable the RTC reference clock detection.

Parameters:
hrtc,: RTC handle
Return values:
HAL status

Definition at line 1637 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmoothCalibMinusPulsesValue
 | ) |  |

Set the Smooth calibration parameters.

Parameters:
hrtc,: RTC handle
SmoothCalibPeriod,: Select the Smooth Calibration Period. This parameter can be can be one of the following values :
  • RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
  • RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
  • RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
SmoothCalibPlusPulses,: Select to Set or reset the CALP bit. This parameter can be one of the following values:
  • RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
SmoothCalibMinusPulsesValue,: Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Note:
To deactivate the smooth calibration, the field SmoothCalibPlusPulses must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field SmoothCalibMinusPulsesValue must be equal to 0.
Return values:
HAL status

Definition at line 1409 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_HandleTypeDef::Instance, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | ShiftAdd1S,
 |  | uint32_t | ShiftSubFS
 | ) |  |

Configure the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register.
Parameters:
hrtc,: RTC handle
ShiftAdd1S,: Select to add or not 1 second to the time calendar. This parameter can be one of the following values :
  • RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
  • RTC_SHIFTADD1S_RESET: No effect.
ShiftSubFS,: Select the number of Second Fractions to substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
HAL status

Definition at line 1477 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RTC_TIMEOUT_VALUE, and RTC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended features functions

Functions
Extended features functions
RTCEx Exported Functions

Extended features functions. More...

Functions

__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) RTC Alarm B callback
      (+) RTC Poll for Alarm B request

Function Documentation

void HAL_RTCEx_AlarmBEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm B callback.

Parameters:
hrtc,: RTC handle
Return values:
None

Definition at line 1818 of file stm32l4xx_hal_rtc_ex.c.

Referenced by HAL_RTC_AlarmIRQHandler().

HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Alarm B Polling request.

Parameters:
hrtc,: RTC handle
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1834 of file stm32l4xx_hal_rtc_ex.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRBF, and RTC_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC_TamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TamperTypeDef Struct Reference
RTCEx Exported Types

RTC Tamper structure definition. More...

#include <stm32l4xx_hal_rtc_ex.h>

Data Fields

uint32_t | Tamper
uint32_t | Interrupt
uint32_t | Trigger
uint32_t | NoErase
uint32_t | MaskFlag
uint32_t | Filter
uint32_t | SamplingFrequency
uint32_t | PrechargeDuration
uint32_t | TamperPullUp
uint32_t | TimeStampOnTamperDetection

Detailed Description

RTC Tamper structure definition.

Definition at line 64 of file stm32l4xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_TamperTypeDef::Filter

Specifies the RTC Filter Tamper. This parameter can be a value of RTC Tamper Filter Definitions

Definition at line 81 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Interrupt

Specifies the Tamper Interrupt. This parameter can be a value of RTC Tamper Interrupts Definitions

Definition at line 69 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::MaskFlag

Specifies the Tamper Flag masking. This parameter can be a value of RTC Tamper Mask Flag Definitions

Definition at line 78 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::NoErase

Specifies the Tamper no erase mode. This parameter can be a value of RTC Tamper EraseBackUp Definitions

Definition at line 75 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::PrechargeDuration

Specifies the Precharge Duration . This parameter can be a value of RTC Tamper Pin Precharge Duration Definitions

Definition at line 87 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::SamplingFrequency

Specifies the sampling frequency. This parameter can be a value of RTC Tamper Sampling Frequencies Definitions

Definition at line 84 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Tamper

Specifies the Tamper Pin. This parameter can be a value of RTC Tamper Pins Definitions

Definition at line 66 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TamperPullUp

Specifies the Tamper PullUp . This parameter can be a value of RTC Tamper Pull Up Definitions

Definition at line 90 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTC Tamper TimeStamp On Tamper Detection Definitions

Definition at line 93 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Trigger

Specifies the Tamper Trigger. This parameter can be a value of RTC Tamper Triggers Definitions

Definition at line 72 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_rtc_ex.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Output Selection Definitions

Defines
RTC Output Selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define | RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
#define | RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
#define | RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)

Define Documentation

#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)

Definition at line 110 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)

Definition at line 111 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)

Definition at line 109 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)

Definition at line 112 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Backup Registers Definitions

Defines
RTC Backup Registers Definitions
RTCEx Exported Constants

Defines

#define | RTC_BKP_DR0 ((uint32_t)0x00000000)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000A)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000B)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000C)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000D)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000E)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000F)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013)
#define | RTC_BKP_DR20 ((uint32_t)0x00000014)
#define | RTC_BKP_DR21 ((uint32_t)0x00000015)
#define | RTC_BKP_DR22 ((uint32_t)0x00000016)
#define | RTC_BKP_DR23 ((uint32_t)0x00000017)
#define | RTC_BKP_DR24 ((uint32_t)0x00000018)
#define | RTC_BKP_DR25 ((uint32_t)0x00000019)
#define | RTC_BKP_DR26 ((uint32_t)0x0000001A)
#define | RTC_BKP_DR27 ((uint32_t)0x0000001B)
#define | RTC_BKP_DR28 ((uint32_t)0x0000001C)
#define | RTC_BKP_DR29 ((uint32_t)0x0000001D)
#define | RTC_BKP_DR30 ((uint32_t)0x0000001E)
#define | RTC_BKP_DR31 ((uint32_t)0x0000001F)

Define Documentation

#define RTC_BKP_DR0 ((uint32_t)0x00000000)

Definition at line 120 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR1 ((uint32_t)0x00000001)

Definition at line 121 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR10 ((uint32_t)0x0000000A)

Definition at line 130 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR11 ((uint32_t)0x0000000B)

Definition at line 131 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR12 ((uint32_t)0x0000000C)

Definition at line 132 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR13 ((uint32_t)0x0000000D)

Definition at line 133 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR14 ((uint32_t)0x0000000E)

Definition at line 134 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR15 ((uint32_t)0x0000000F)

Definition at line 135 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR16 ((uint32_t)0x00000010)

Definition at line 136 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR17 ((uint32_t)0x00000011)

Definition at line 137 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR18 ((uint32_t)0x00000012)

Definition at line 138 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR19 ((uint32_t)0x00000013)

Definition at line 139 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR2 ((uint32_t)0x00000002)

Definition at line 122 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR20 ((uint32_t)0x00000014)

Definition at line 140 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR21 ((uint32_t)0x00000015)

Definition at line 141 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR22 ((uint32_t)0x00000016)

Definition at line 142 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR23 ((uint32_t)0x00000017)

Definition at line 143 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR24 ((uint32_t)0x00000018)

Definition at line 144 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR25 ((uint32_t)0x00000019)

Definition at line 145 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR26 ((uint32_t)0x0000001A)

Definition at line 146 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR27 ((uint32_t)0x0000001B)

Definition at line 147 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR28 ((uint32_t)0x0000001C)

Definition at line 148 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR29 ((uint32_t)0x0000001D)

Definition at line 149 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR3 ((uint32_t)0x00000003)

Definition at line 123 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR30 ((uint32_t)0x0000001E)

Definition at line 150 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR31 ((uint32_t)0x0000001F)

Definition at line 151 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR4 ((uint32_t)0x00000004)

Definition at line 124 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR5 ((uint32_t)0x00000005)

Definition at line 125 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR6 ((uint32_t)0x00000006)

Definition at line 126 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR7 ((uint32_t)0x00000007)

Definition at line 127 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR8 ((uint32_t)0x00000008)

Definition at line 128 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_BKP_DR9 ((uint32_t)0x00000009)

Definition at line 129 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC TimeStamp Edges Definitions

Defines
RTC TimeStamp Edges Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define | RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)

Define Documentation

#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)

Definition at line 160 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)

Definition at line 159 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC TimeStamp Pins Selection

Defines
RTC TimeStamp Pins Selection
RTCEx Exported Constants

Defines

#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)

Define Documentation

#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)

Definition at line 168 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Tamper Pins Definitions

Defines
RTC Tamper Pins Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

Define Documentation

#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E

Definition at line 177 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E

Definition at line 179 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

Definition at line 181 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Tamper Interrupts Definitions

Defines
RTC Tamper Interrupts Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE
#define | RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
#define | RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE
#define | RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE

Define Documentation

#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE

Definition at line 197 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE

Definition at line 191 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE

Definition at line 193 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE

Definition at line 195 of file stm32l4xx_hal_rtc_ex.h.

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STM32L486xx HAL User Manual: RTC Tamper Triggers Definitions

Defines
RTC Tamper Triggers Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
#define | RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Define Documentation

#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)

Definition at line 206 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Definition at line 208 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE

Definition at line 207 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)

Definition at line 205 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Tamper EraseBackUp Definitions

Defines
RTC Tamper EraseBackUp Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)

Define Documentation

#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)

Definition at line 217 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)

Definition at line 216 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Tamper Mask Flag Definitions

Defines
RTC Tamper Mask Flag Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)

Define Documentation

#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)

Definition at line 225 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)

Definition at line 226 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Tamper Filter Definitions

Defines
RTC Tamper Filter Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800)
#define | RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000)
#define | RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800)

Define Documentation

#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800)

Tamper is activated after 2 consecutive samples at the active level

Definition at line 236 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000)

Tamper is activated after 4 consecutive samples at the active level

Definition at line 238 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800)

Tamper is activated after 8 consecutive samples at the active level.

Definition at line 240 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000)

Tamper filter is disabled

Definition at line 234 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Tamper Sampling Frequencies Definitions

Defines
RTC Tamper Sampling Frequencies Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700)

Define Documentation

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 259 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 251 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 257 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 263 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 249 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 255 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 261 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 253 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Tamper Pin Precharge Duration Definitions

Defines
RTC Tamper Pin Precharge Duration Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)

Define Documentation

#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 272 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 274 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 276 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 278 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Tamper TimeStamp On Tamper Detection Definitions

Defines
RTC Tamper TimeStamp On Tamper Detection Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS)
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)

TimeStamp on Tamper Detection event is not saved

Definition at line 288 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS)

TimeStamp on Tamper Detection event saved

Definition at line 287 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Tamper Pull Up Definitions

Defines
RTC Tamper Pull Up Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)

Define Documentation

#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)

TimeStamp on Tamper Detection event is not saved

Definition at line 297 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000)

TimeStamp on Tamper Detection event saved

Definition at line 296 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Wakeup Timer Definitions

Defines
RTC Wakeup Timer Definitions
RTCEx Exported Constants

Defines

#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)

Define Documentation

#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)

Definition at line 309 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)

Definition at line 310 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)

Definition at line 305 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)

Definition at line 308 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)

Definition at line 307 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)

Definition at line 306 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Smooth Calib Period Definitions

Defines
RTC Smooth Calib Period Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000)
#define | RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000)
#define | RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000)

Define Documentation

#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000)

If RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK seconds

Definition at line 320 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000)

If RTCCLK = 32768 Hz, Smooth calibration period is 32s, else 2exp20 RTCCLK seconds

Definition at line 318 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000)

If RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK seconds

Definition at line 322 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Smooth Calib Plus Pulses Definitions

Defines
RTC Smooth Calib Plus Pulses Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000)
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000)

Define Documentation

#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000)

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]

Definition at line 334 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000)

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8

Definition at line 331 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Calib Output Selection Definitions

Defines
RTC Calib Output Selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
#define | RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)

Define Documentation

#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)

Definition at line 344 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)

Definition at line 343 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Add 1 Second Parameter Definitions

Defines
RTC Add 1 Second Parameter Definitions
RTCEx Exported Constants

Defines

#define | RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
#define | RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)

Define Documentation

#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)

Definition at line 352 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)

Definition at line 353 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTCEx Exported Macros

Defines
RTCEx Exported Macros
RTCEx

Defines

#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Wake Up timer interrupt is enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Tamper interrupt is enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Time Stamp interrupt is enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Internal Time Stamp's flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Internal Time Stamp's pending flags.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC shift operation's flag status.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Define Documentation

#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))

Disable the calibration output.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 691 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateCalibrationOutPut().

#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))

Enable the RTC calibration output.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 684 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))

Disable the clock reference detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 705 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateRefClock().

#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))

Enable the clock reference detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 698 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetRefClock().

#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Internal Time Stamp's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Internal Time Stamp Flag source to clear. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 677 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))

Disable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 657 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))

Enable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 650 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC Internal Time Stamp's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Internal Time Stamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 667 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_SHIFT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC shift operation's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC shift operation Flag is pending or not. This parameter can be:
  • RTC_FLAG_SHPF
Return values:
None

Definition at line 715 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))

Disable the RTC Tamper1 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 455 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))

Enable the RTC Tamper1 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 448 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))

Disable the RTC Tamper2 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 470 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))

Enable the RTC Tamper2 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 463 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))

Disable the RTC Tamper3 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 485 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))

Enable the RTC Tamper3 input detection.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 478 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Tamper's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag sources to clear. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 flag
  • RTC_FLAG_TAMP2F: Tamper2 flag
  • RTC_FLAG_TAMP3F: Tamper3 flag
Return values:
None

Definition at line 567 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))

Disable the RTC Tamper interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 512 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))

Enable the RTC Tamper interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 499 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC Tamper's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag is pending or not. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 flag
  • RTC_FLAG_TAMP2F: Tamper2 flag
  • RTC_FLAG_TAMP3F: Tamper3 flag
Return values:
None

Definition at line 555 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
                                                                      ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
                                                                      (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))

Check whether the specified RTC Tamper interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt to check. This parameter can be:
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 525 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Tamper interrupt is enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt source to check. This parameter can be:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt
Return values:
None

Definition at line 543 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG ( ) (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Clear the RTC Tamper and Timestamp associated Exti line flag.

Return values:
None

Definition at line 879 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 824 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 836 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 812 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 848 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
                                                                       } while(0)

Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

This parameter can be:

Return values:
None

Definition at line 864 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable event on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 818 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 830 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 806 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 842 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
                                                                      } while(0)

Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 854 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None

Definition at line 885 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG ( ) (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 873 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Time Stamp's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 643 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))

Disable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 581 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt source to be disabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 601 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp().

#define __HAL_RTC_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))

Enable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 574 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt source to be enabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 591 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC TimeStamp's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC TimeStamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 632 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)

Check whether the specified RTC TimeStamp interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC TimeStamp interrupt source to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 611 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Time Stamp interrupt is enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Time Stamp interrupt source to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 621 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Wake Up timer's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC WakeUpTimer Flag to clear. This parameter can be:
  • RTC_FLAG_WUTF
Return values:
None

Definition at line 440 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))

Disable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 379 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to be disabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 399 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer().

#define __HAL_RTC_WAKEUPTIMER_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))

Enable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 372 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to be enabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 389 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG ( ) (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the RTC WakeUp Timer associated Exti line flag.

Return values:
None

Definition at line 794 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 739 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 751 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 727 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 763 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
                                                                  } while(0)

Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

This parameter can be:

Return values:
None

Definition at line 779 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 733 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 745 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 721 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 757 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
                                                                 } while(0)

Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 769 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 800 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG ( ) (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.

Return values:
Line Status.

Definition at line 788 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)

Get the selected RTC WakeUpTimer's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC WakeUpTimer Flag is pending or not. This parameter can be:
  • RTC_FLAG_WUTF
  • RTC_FLAG_WUTWF
Return values:
None

Definition at line 430 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)

Check whether the specified RTC WakeUpTimer interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC WakeUpTimer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 409 of file stm32l4xx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the specified RTC Wake Up timer interrupt is enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Wake Up timer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 419 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTCEx Private Constants

Defines
RTCEx Private Constants
RTCEx

Defines

#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000)
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000)

Define Documentation

#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000)

External interrupt line 19 Connected to the RTC Tamper and Time Stamp events

Definition at line 986 of file stm32l4xx_hal_rtc_ex.h.

#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000)

External interrupt line 20 Connected to the RTC Wakeup event

Definition at line 987 of file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Private macros to check input parameters

Defines
Private macros to check input parameters
RTCEx Private Macros

Defines

#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
#define | IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != (uint32_t)RESET))
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TAMPER_ERASE_MODE(MODE)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(STATE)
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_PULLUP_STATE(STATE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Define Documentation

#define IS_RTC_BKP ( BKP ) ((BKP) < (uint32_t) RTC_BKP_NUMBER)

Definition at line 1007 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_BKUPRead(), and HAL_RTCEx_BKUPWrite().

#define IS_RTC_CALIB_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))

Definition at line 1077 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define IS_RTC_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_OUTPUT_DISABLE) || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))

Definition at line 1002 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SHIFT_ADD1S ( SEL )
Value:
(((SEL) == RTC_SHIFTADD1S_RESET) || \
                                 ((SEL) == RTC_SHIFTADD1S_SET))

Definition at line 1072 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SHIFT_SUBFS ( FS ) ((FS) <= 0x00007FFF)

Definition at line 1075 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SMOOTH_CALIB_MINUS ( VALUE ) ((VALUE) <= 0x000001FF)

Definition at line 1070 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PERIOD ( PERIOD )
Value:
(((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))

Definition at line 1063 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PLUS ( PLUS )
Value:
(((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))

Definition at line 1067 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_TAMPER ( TAMPER ) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))

Definition at line 1012 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_ERASE_MODE ( MODE )
Value:
(((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
                                                    ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))

Definition at line 1023 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_FILTER ( FILTER )
Value:
(((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))

Definition at line 1029 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_INTERRUPT ( INTERRUPT ) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != (uint32_t)RESET))

Definition at line 1014 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_MASKFLAG_STATE ( STATE )
Value:
(((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
                                                    ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))

Definition at line 1026 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PRECHARGE_DURATION ( DURATION )
Value:
(((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
                                                   ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))

Definition at line 1043 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PULLUP_STATE ( STATE )
Value:
(((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
                                           ((STATE) == RTC_TAMPER_PULLUP_DISABLE))

Definition at line 1051 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_SAMPLING_FREQ ( FREQ )
Value:
(((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
                                          ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))

Definition at line 1034 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION ( DETECTION )
Value:
(((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 1048 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))

Definition at line 1018 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TIMESTAMP_PIN ( PIN ) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))

Definition at line 1016 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define IS_RTC_WAKEUP_CLOCK ( CLOCK )
Value:
(((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))

Definition at line 1054 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_RTC_WAKEUP_COUNTER ( COUNTER ) ((COUNTER) <= 0xFFFF)

Definition at line 1061 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_TIMESTAMP_EDGE ( EDGE )
Value:
(((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))

Definition at line 1009 of file stm32l4xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTCEx

Modules | Defines
RTCEx
STM32L4xx_HAL_Driver

RTC Extended HAL module driver. More...

Modules

RTCEx Exported Functions
RTCEx Exported Types
RTCEx Exported Constants
RTCEx Exported Macros
RTCEx Private Constants
RTCEx Private Macros

Defines

#define RTC_TAMPCR_MASK

Detailed Description

RTC Extended HAL module driver.

Define Documentation

#define RTC_TAMPCR_MASK
Value:
((uint32_t)RTC_TAMPCR_TAMPTS    |\
                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
                                       (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
                                       (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)

Definition at line 138 of file stm32l4xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Private Typedefs

Enumerations
SAI Private Typedefs
SAI

Enumerations

enum SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Enumeration Type Documentation

enum SAI_ModeTypedef
Enumerator:
SAI_MODE_DMA
SAI_MODE_IT

Definition at line 187 of file stm32l4xx_hal_sai.c.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Private Constants

Defines
SAI Private Constants
SAI

Defines

#define | SAI_FIFO_SIZE 8
#define | SAI_DEFAULT_TIMEOUT 4
#define | SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)

Define Documentation

#define SAI_DEFAULT_TIMEOUT 4

Definition at line 201 of file stm32l4xx_hal_sai.c.

Referenced by SAI_Disable().

#define SAI_FIFO_SIZE 8

Definition at line 200 of file stm32l4xx_hal_sai.c.

#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)

Definition at line 202 of file stm32l4xx_hal_sai.c.

Referenced by HAL_SAI_EnableRxMuteMode().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Private Functions

Functions
SAI Private Functions
SAI

Private functions. More...

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (SAI_HandleTypeDef *hsai, uint32_t mode)
Return the interrupt flag to set according the SAI setup.
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
Disable the SAI and wait for the disabling.
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8-Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
static void | SAI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA SAI Abort callback.

Detailed Description

Private functions.

Function Documentation

static HAL_StatusTypeDef SAI_Disable ( SAI_HandleTypeDef * hsai ) [static]

Disable the SAI and wait for the disabling.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1882 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_DISABLE, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_TIMEOUT, __SAI_HandleTypeDef::Instance, and SAI_DEFAULT_TIMEOUT.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DMAStop(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Transmit(), SAI_DMAAbort(), and SAI_DMAError().

static void SAI_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI Abort callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2163 of file stm32l4xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, SAI_Disable(), __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_IRQHandler().

static void SAI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2134 of file stm32l4xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_DMA, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, SAI_Disable(), __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA(), and HAL_SAI_Transmit_DMA().

static void SAI_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2099 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __DMA_HandleTypeDef::Instance, __SAI_HandleTypeDef::Instance, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2122 of file stm32l4xx_hal_sai.c.

References HAL_SAI_RxHalfCpltCallback().

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2061 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __SAI_HandleTypeDef::Instance, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2086 of file stm32l4xx_hal_sai.c.

References HAL_SAI_TxHalfCpltCallback().

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_FillFifo ( SAI_HandleTypeDef * hsai ) [static]

Fill the fifo.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1819 of file stm32l4xx_hal_sai.c.

References SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FIFOSTATUS_FULL, SAI_NOCOMPANDING, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit(), and HAL_SAI_Transmit_IT().

static HAL_StatusTypeDef SAI_InitI2S | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol,: one of the supported protocol.
datasize,: one of the supported datasize SAI protocol data size the configuration information for SAI module.
nbslot,: number of slot minimum value is 2 and max is 16. the value must be a multiple of 2.
Return values:
HAL status

Definition at line 1659 of file stm32l4xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_ACTIVE_LOW, SAI_FS_BEFOREFIRSTBIT, SAI_FS_CHANNEL_IDENTIFICATION, SAI_FS_FIRSTBIT, SAI_I2S_LSBJUSTIFIED, SAI_I2S_MSBJUSTIFIED, SAI_I2S_STANDARD, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static HAL_StatusTypeDef SAI_InitPCM | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol,: one of the supported protocol
datasize,: one of the supported datasize SAI protocol data size
nbslot,: number of slot minimum value is 1 and the max is 16.
Return values:
HAL status

Definition at line 1752 of file stm32l4xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_BEFOREFIRSTBIT, SAI_FS_STARTFRAME, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PCM_LONG, SAI_PCM_SHORT, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static uint32_t SAI_InterruptFlag | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | mode
 | ) |  | [static]

Return the interrupt flag to set according the SAI setup.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
mode,: SAI_MODE_DMA or SAI_MODE_IT
Return values:
the list of the IT flag to enable

Definition at line 1849 of file stm32l4xx_hal_sai.c.

References SAI_InitTypeDef::AudioMode, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_AC97_PROTOCOL, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, SAI_MODE_IT, SAI_MODEMASTER_RX, SAI_MODESLAVE_RX, and SAI_MODESLAVE_TX.

Referenced by HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

static void SAI_Receive_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 16-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2008 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 32-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2034 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode 8-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1982 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Transmit_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1932 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1957 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode 8-Bit transfer.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1908 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SAI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
             ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]  This subsection provides a set of functions allowing to initialize and
        de-initialize the SAIx peripheral:

      (+) User must implement HAL_SAI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SAI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode (Master/slave TX/RX)
        (++) Protocol
        (++) Data Size
        (++) MCLK Output
        (++) Audio frequency
        (++) FIFO Threshold
        (++) Frame Config
        (++) Slot Config

      (+) Call the function HAL_SAI_DeInit() to restore the default configuration
          of the selected SAI peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SAI_DeInit ( SAI_HandleTypeDef * hsai )

DeInitialize the SAI peripheral.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 540 of file stm32l4xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_MspDeInit(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_Init ( SAI_HandleTypeDef * hsai )

Initialize the SAI according to the specified parameters.

in the SAI_InitTypeDef structure and initialize the associated handle.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 325 of file stm32l4xx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, assert_param, SAI_InitTypeDef::AudioFrequency, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, SAI_InitTypeDef::FIFOThreshold, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, HAL_RCCEx_GetPeriphCLKFreq(), HAL_SAI_ERROR_NONE, HAL_SAI_MspInit(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, IS_SAI_AUDIO_FREQUENCY, IS_SAI_BLOCK_ACTIVE_FRAME, IS_SAI_BLOCK_CLOCK_STROBING, IS_SAI_BLOCK_COMPANDING_MODE, IS_SAI_BLOCK_DATASIZE, IS_SAI_BLOCK_FIFO_THRESHOLD, IS_SAI_BLOCK_FIRST_BIT, IS_SAI_BLOCK_FIRSTBIT_OFFSET, IS_SAI_BLOCK_FRAME_LENGTH, IS_SAI_BLOCK_FS_DEFINITION, IS_SAI_BLOCK_FS_OFFSET, IS_SAI_BLOCK_FS_POLARITY, IS_SAI_BLOCK_MODE, IS_SAI_BLOCK_NODIVIDER, IS_SAI_BLOCK_OUTPUT_DRIVE, IS_SAI_BLOCK_PROTOCOL, IS_SAI_BLOCK_SLOT_NUMBER, IS_SAI_BLOCK_SLOT_SIZE, IS_SAI_BLOCK_SYNCEXT, IS_SAI_BLOCK_SYNCHRO, IS_SAI_BLOCK_TRISTATE_MANAGEMENT, IS_SAI_MONO_STEREO_MODE, IS_SAI_SLOT_ACTIVE, __SAI_HandleTypeDef::Lock, SAI_InitTypeDef::Mckdiv, SAI_InitTypeDef::MonoStereoMode, SAI_InitTypeDef::NoDivider, SAI_InitTypeDef::OutputDrive, SAI_InitTypeDef::Protocol, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SAI2, SAI_ASYNCHRONOUS, SAI_AUDIO_FREQUENCY_MCKDIV, SAI_CLOCKSTROBING_RISINGEDGE, SAI_Disable(), SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_SYNCEXT_DISABLE, SAI_SYNCEXT_OUTBLOCKA_ENABLE, SAI_SYNCEXT_OUTBLOCKB_ENABLE, SAI_SYNCHRONOUS, SAI_SYNCHRONOUS_EXT_SAI1, SAI_SYNCHRONOUS_EXT_SAI2, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, SAI_SlotInitTypeDef::SlotSize, __SAI_HandleTypeDef::State, SAI_InitTypeDef::Synchro, SAI_InitTypeDef::SynchroExt, and SAI_InitTypeDef::TriState.

Referenced by HAL_SAI_InitProtocol().

HAL_StatusTypeDef HAL_SAI_InitProtocol | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  |

Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol,: one of the supported protocol SAI Supported protocol
datasize,: one of the supported datasize SAI protocol data size the configuration information for SAI module.
nbslot,: Number of slot.
Return values:
HAL status

Definition at line 286 of file stm32l4xx_hal_sai.c.

References assert_param, HAL_SAI_Init(), IS_SAI_PROTOCOL_DATASIZE, IS_SAI_SUPPORTED_PROTOCOL, SAI_I2S_LSBJUSTIFIED, SAI_I2S_MSBJUSTIFIED, SAI_I2S_STANDARD, SAI_InitI2S(), SAI_InitPCM(), SAI_PCM_LONG, and SAI_PCM_SHORT.

void HAL_SAI_MspDeInit ( SAI_HandleTypeDef * hsai )

DeInitialize the SAI MSP.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 597 of file stm32l4xx_hal_sai.c.

Referenced by HAL_SAI_DeInit().

void HAL_SAI_MspInit ( SAI_HandleTypeDef * hsai )

Initialize the SAI MSP.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 581 of file stm32l4xx_hal_sai.c.

Referenced by HAL_SAI_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
SAI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SAI data
    transfers.

    (+) There are two modes of transfer:
      (++) Blocking mode : The communication is performed in the polling mode.
           The status of all data processing is returned by the same function
           after finishing transfer.
      (++) No-Blocking mode : The communication is performed using Interrupts
           or DMA. These functions return the status of the transfer startup.
           The end of the data processing will be indicated through the
           dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.

    (+) Blocking mode functions are :
      (++) HAL_SAI_Transmit()
      (++) HAL_SAI_Receive()
      (++) HAL_SAI_TransmitReceive()

    (+) Non Blocking mode functions with Interrupt are :
      (++) HAL_SAI_Transmit_IT()
      (++) HAL_SAI_Receive_IT()
      (++) HAL_SAI_TransmitReceive_IT()

    (+) Non Blocking mode functions with DMA are :
      (++) HAL_SAI_Transmit_DMA()
      (++) HAL_SAI_Receive_DMA()
      (++) HAL_SAI_TransmitReceive_DMA()

    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
      (++) HAL_SAI_TxCpltCallback()
      (++) HAL_SAI_RxCpltCallback()
      (++) HAL_SAI_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SAI_Abort ( SAI_HandleTypeDef * hsai )

Abort the current transfer and disable the SAI.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1071 of file stm32l4xx_hal_sai.c.

References HAL_DMA_Abort(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

Referenced by HAL_SAI_IRQHandler().

HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the Rx mute detection.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1324 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the Tx mute mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1283 of file stm32l4xx_hal_sai.c.

References HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DMAPause ( SAI_HandleTypeDef * hsai )

Pause the audio stream playing from the Media.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 982 of file stm32l4xx_hal_sai.c.

References __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAResume ( SAI_HandleTypeDef * hsai )

Resume the audio stream playing from the Media.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1002 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_ENABLE, and __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAStop ( SAI_HandleTypeDef * hsai )

Stop the audio stream playing from the Media.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1029 of file stm32l4xx_hal_sai.c.

References HAL_DMA_Abort(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | SAIcallback | callback,
 |  | uint16_t | counter
 | ) |  |

Enable the Rx mute detection.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
callback,: function called when the mute is detected.
counter,: number a data before mute detection max 63.
Return values:
HAL status

Definition at line 1301 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_ENABLE_IT, assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_COUNTER, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, SAI_xCR2_MUTECNT_OFFSET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | uint16_t | val
 | ) |  |

Enable the Tx mute mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
val,: value sent during the mute SAI Block Mute Value
Return values:
HAL status

Definition at line 1264 of file stm32l4xx_hal_sai.c.

References assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_VALUE, and __SAI_HandleTypeDef::State.

void HAL_SAI_ErrorCallback ( SAI_HandleTypeDef * hsai )

SAI error callback.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1583 of file stm32l4xx_hal_sai.c.

Referenced by HAL_SAI_IRQHandler(), SAI_DMAAbort(), and SAI_DMAError().

void HAL_SAI_IRQHandler ( SAI_HandleTypeDef * hsai )

Handle SAI interrupt request.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1343 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SAI_Abort(), HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_CNREADY, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_OVR, HAL_SAI_ERROR_UDR, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::mutecallback, SAI_DMAAbort(), SAI_FLAG_AFSDET, SAI_FLAG_CNRDY, SAI_FLAG_LFSDET, SAI_FLAG_MUTEDET, SAI_FLAG_OVRUDR, SAI_FLAG_WCKCFG, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_MUTEDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, and __SAI_HandleTypeDef::XferCount.

HAL_StatusTypeDef HAL_SAI_Receive | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 765 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_Disable(), SAI_FIFOSTATUS_EMPTY, SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 1195 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMARxCplt(), SAI_DMARxHalfCplt(), SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 924 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_RxCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer completed callback.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1551 of file stm32l4xx_hal_sai.c.

Referenced by SAI_DMARxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

void HAL_SAI_RxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer half completed callback.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1567 of file stm32l4xx_hal_sai.c.

Referenced by SAI_DMARxHalfCplt().

HAL_StatusTypeDef HAL_SAI_Transmit | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 665 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_Disable(), SAI_FIFOSTATUS_FULL, SAI_FillFifo(), SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 1126 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMATxCplt(), SAI_DMATxHalfCplt(), SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 862 of file stm32l4xx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FillFifo(), SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), SAI_Transmit_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_TxCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer completed callback.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1519 of file stm32l4xx_hal_sai.c.

Referenced by SAI_DMATxCplt(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void HAL_SAI_TxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer Half completed callback.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1535 of file stm32l4xx_hal_sai.c.

Referenced by SAI_DMATxHalfCplt().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SAI Exported Functions

Peripheral State functions. More...

Functions

HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Peripheral State functions.

  ===============================================================================
                ##### Peripheral State and Errors functions #####
  ===============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SAI_GetError ( SAI_HandleTypeDef * hsai )

Return the SAI error code.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for the specified SAI Block.
Return values:
SAI Error Code

Definition at line 1630 of file stm32l4xx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode.

HAL_SAI_StateTypeDef HAL_SAI_GetState ( SAI_HandleTypeDef * hsai )

Return the SAI handle state.

Parameters:
hsai,: pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL state

Definition at line 1619 of file stm32l4xx_hal_sai.c.

References __SAI_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_InitTypeDef Struct Reference
SAI Init Structure definition

#include <stm32l4xx_hal_sai.h>

Data Fields

uint32_t | AudioMode
uint32_t | Synchro
uint32_t | SynchroExt
uint32_t | OutputDrive
uint32_t | NoDivider
uint32_t | FIFOThreshold
uint32_t | AudioFrequency
uint32_t | Mckdiv
uint32_t | MonoStereoMode
uint32_t | CompandingMode
uint32_t | TriState
uint32_t | Protocol
uint32_t | DataSize
uint32_t | FirstBit
uint32_t | ClockStrobing

Detailed Description

Definition at line 83 of file stm32l4xx_hal_sai.h.

Field Documentation

uint32_t SAI_InitTypeDef::AudioFrequency

Specifies the audio frequency sampling. This parameter can be a value of SAI Audio Frequency

Definition at line 114 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::AudioMode

Specifies the SAI Block audio Mode. This parameter can be a value of SAI Block Mode

Definition at line 85 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::ClockStrobing

Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of SAI Block Clock Strobing

Definition at line 142 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::CompandingMode

Specifies the companding mode type. This parameter can be a value of SAI Block Companding Mode

Definition at line 124 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

uint32_t SAI_InitTypeDef::DataSize

Specifies the SAI Block data size. This parameter can be a value of SAI Block Data Size

Definition at line 136 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::FIFOThreshold

Specifies SAI Block FIFO threshold. This parameter can be a value of SAI Block Fifo Threshold

Definition at line 111 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SAI Block MSB LSB transmission

Definition at line 139 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::Mckdiv

Specifies the master clock divider, the parameter will be used if for AudioFrequency the user choice This parameter must be a number between Min_Data = 0 and Max_Data = 15

Definition at line 117 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MonoStereoMode

Specifies if the mono or stereo mode is selected. This parameter can be a value of SAI Mono Stereo Mode

Definition at line 121 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::NoDivider

Specifies whether master clock will be divided or not. This parameter can be a value of SAI Block NoDivider

Note:
: If bit NODIV in the SAI_xCR1 register is cleared, the frame length should be aligned to a number equal to a power of 2, from 8 to 256. If bit NODIV in the SAI_xCR1 register is set, the frame length can take any of the values without constraint since the input clock of the audio block should be equal to the bit clock. There is no MCLK_x clock which can be output.

Definition at line 102 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::OutputDrive

Specifies when SAI Block outputs are driven. This parameter can be a value of SAI Block Output Drive

Note:
this value has to be set before enabling the audio block but after the audio block configuration.

Definition at line 97 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::Protocol

Specifies the SAI Block protocol. This parameter can be a value of SAI Block Protocol

Definition at line 133 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::Synchro

Specifies SAI Block synchronization This parameter can be a value of SAI Block Synchronization

Definition at line 88 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::SynchroExt

Specifies SAI external output synchronization, this setup is common for BlockA and BlockB This parameter can be a value of SAI External synchronisation

Note:
: If both audio blocks of same SAI are used, this parameter has to be set to the same value for each audio block

Definition at line 91 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::TriState

Specifies the companding mode type. This parameter can be a value of SAI TRIState Management

Definition at line 127 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_sai.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI_FrameInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_FrameInitTypeDef Struct Reference
SAI Frame Structure definition

#include <stm32l4xx_hal_sai.h>

Data Fields

uint32_t | FrameLength
uint32_t | ActiveFrameLength
uint32_t | FSDefinition
uint32_t | FSPolarity
uint32_t | FSOffset

Detailed Description

Definition at line 153 of file stm32l4xx_hal_sai.h.

Field Documentation

uint32_t SAI_FrameInitTypeDef::ActiveFrameLength

Specifies the Frame synchronization active level length. This Parameter specifies the length in number of bit clock (SCK + 1) of the active level of FS signal in audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 162 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FrameLength

Specifies the Frame length, the number of SCK clocks for each audio frame. This parameter must be a number between Min_Data = 8 and Max_Data = 256.

Note:
: If master clock MCLK_x pin is declared as an output, the frame length should be aligned to a number equal to power of 2 in order to keep in an audio frame, an integer number of MCLK pulses by bit Clock.

Definition at line 156 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSDefinition

Specifies the Frame synchronization definition. This parameter can be a value of SAI Block FS Definition

Definition at line 167 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSOffset

Specifies the Frame synchronization Offset. This parameter can be a value of SAI Block FS Offset

Definition at line 173 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSPolarity

Specifies the Frame synchronization Polarity. This parameter can be a value of SAI Block FS Polarity

Definition at line 170 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_sai.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI_SlotInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_SlotInitTypeDef Struct Reference
SAI Slot Structure definition

#include <stm32l4xx_hal_sai.h>

Data Fields

uint32_t | FirstBitOffset
uint32_t | SlotSize
uint32_t | SlotNumber
uint32_t | SlotActive

Detailed Description

Definition at line 185 of file stm32l4xx_hal_sai.h.

Field Documentation

uint32_t SAI_SlotInitTypeDef::FirstBitOffset

Specifies the position of first data transfer bit in the slot. This parameter must be a number between Min_Data = 0 and Max_Data = 24

Definition at line 187 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotActive

Specifies the slots in audio frame that will be activated. This parameter can be a value of SAI Block Slot Active

Definition at line 196 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotNumber

Specifies the number of slot in the audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 16

Definition at line 193 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotSize

Specifies the Slot Size. This parameter can be a value of SAI Block Slot Size

Definition at line 190 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_sai.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Handle Structure definition

Data Structures | Typedefs
SAI Handle Structure definition
SAI Exported Types

SAI handle Structure definition. More...

Data Structures

struct | __SAI_HandleTypeDef

Typedefs

typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef

Detailed Description

SAI handle Structure definition.

Typedef Documentation

typedef struct __SAI_HandleTypeDef SAI_HandleTypeDef
Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: __SAI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SAI_HandleTypeDef Struct Reference
SAI Handle Structure definition

#include <stm32l4xx_hal_sai.h>

Data Fields

SAI_Block_TypeDef * | Instance
SAI_InitTypeDef Init
SAI_FrameInitTypeDef FrameInit
SAI_SlotInitTypeDef SlotInit
uint8_t * | pBuffPtr
uint16_t | XferSize
uint16_t | XferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
SAIcallback mutecallback
void(* | InterruptServiceRoutine )(struct __SAI_HandleTypeDef *hsai)
HAL_LockTypeDef | Lock
__IO HAL_SAI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

Definition at line 207 of file stm32l4xx_hal_sai.h.

Field Documentation

__IO uint32_t __SAI_HandleTypeDef::ErrorCode

SAI Error code

Definition at line 235 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_GetError(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_Disable(), SAI_DMAAbort(), and SAI_DMAError().

SAI_FrameInitTypeDef __SAI_HandleTypeDef::FrameInit

SAI Frame configuration parameters

Definition at line 213 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmarx

SAI Rx DMA handle parameters

Definition at line 225 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), and HAL_SAI_Receive_DMA().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmatx

SAI Tx DMA handle parameters

Definition at line 223 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), and HAL_SAI_Transmit_DMA().

SAI_InitTypeDef __SAI_HandleTypeDef::Init

SAI communication parameters

Definition at line 211 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

SAI_Block_TypeDef* __SAI_HandleTypeDef::Instance

SAI Blockx registers base address

Definition at line 209 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAPause(), HAL_SAI_DMAResume(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_Disable(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai)

Definition at line 229 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive_IT(), and HAL_SAI_Transmit_IT().

HAL_LockTypeDef __SAI_HandleTypeDef::Lock

SAI locking object

Definition at line 231 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

SAIcallback __SAI_HandleTypeDef::mutecallback

SAI mute callback

Definition at line 227 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

uint8_t* __SAI_HandleTypeDef::pBuffPtr

Pointer to SAI transfer Buffer

Definition at line 217 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

SAI_SlotInitTypeDef __SAI_HandleTypeDef::SlotInit

SAI Slot configuration parameters

Definition at line 215 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

__IO HAL_SAI_StateTypeDef __SAI_HandleTypeDef::State

SAI communication state

Definition at line 233 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableRxMuteMode(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_GetState(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

uint16_t __SAI_HandleTypeDef::XferCount

SAI transfer counter

Definition at line 221 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

uint16_t __SAI_HandleTypeDef::XferSize

SAI transfer size

Definition at line 219 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_sai.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Exported Types

Modules | Typedefs | Enumerations
SAI Exported Types
SAI

Modules

SAI Init Structure definition

SAI Init Structure definition.

SAI Frame Structure definition

SAI Frame Init structure definition.

SAI Slot Structure definition

SAI Block Slot Init Structure definition.

SAI Handle Structure definition

SAI handle Structure definition.

Typedefs

typedef void(* SAIcallback )(void)
SAI Callback prototype.

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00U, HAL_SAI_STATE_READY = 0x01U, HAL_SAI_STATE_BUSY = 0x02U, HAL_SAI_STATE_BUSY_TX = 0x12U,
HAL_SAI_STATE_BUSY_RX = 0x22U
}
HAL State structures definition. More...

Typedef Documentation

typedef void(* SAIcallback)(void)

SAI Callback prototype.

Definition at line 77 of file stm32l4xx_hal_sai.h.

Enumeration Type Documentation

enum HAL_SAI_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SAI_STATE_RESET

SAI not yet initialized or disabled

HAL_SAI_STATE_READY

SAI initialized and ready for use

HAL_SAI_STATE_BUSY

SAI internal process is ongoing

HAL_SAI_STATE_BUSY_TX

Data transmission process is ongoing

HAL_SAI_STATE_BUSY_RX

Data reception process is ongoing

Definition at line 65 of file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Error Code

Defines
SAI Error Code
SAI Exported Constants

Defines

#define | HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U)
#define | HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U)
#define | HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U)
#define | HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U)
#define | HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)
#define | HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U)
#define | HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)
#define | HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U)

Define Documentation

#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U)

Anticipated Frame synchronisation detection

Definition at line 257 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)

codec not ready

Definition at line 259 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U)

DMA error

Definition at line 262 of file stm32l4xx_hal_sai.h.

Referenced by SAI_DMAError().

#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U)

Late Frame synchronisation detection

Definition at line 258 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 254 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U)

Overrun Error

Definition at line 255 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)

Timeout error

Definition at line 261 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Transmit(), and SAI_Disable().

#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U)

Underrun error

Definition at line 256 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U)

Wrong clock configuration

Definition at line 260 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_DMAAbort().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI External synchronisation

Defines
SAI External synchronisation
SAI Exported Constants

Defines

#define | SAI_SYNCEXT_DISABLE 0
#define | SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
#define | SAI_SYNCEXT_OUTBLOCKB_ENABLE 2

Define Documentation

#define SAI_SYNCEXT_DISABLE 0

Definition at line 270 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1

Definition at line 271 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2

Definition at line 272 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Supported protocol

Defines
SAI Supported protocol
SAI Exported Constants

Defines

#define | SAI_I2S_STANDARD 0
#define | SAI_I2S_MSBJUSTIFIED 1
#define | SAI_I2S_LSBJUSTIFIED 2
#define | SAI_PCM_LONG 3
#define | SAI_PCM_SHORT 4

Define Documentation

#define SAI_I2S_LSBJUSTIFIED 2

Definition at line 282 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_I2S_MSBJUSTIFIED 1

Definition at line 281 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_I2S_STANDARD 0

Definition at line 280 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_PCM_LONG 3

Definition at line 283 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitPCM().

#define SAI_PCM_SHORT 4

Definition at line 284 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitPCM().

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STM32L486xx HAL User Manual: SAI protocol data size

Defines
SAI protocol data size
SAI Exported Constants

Defines

#define | SAI_PROTOCOL_DATASIZE_16BIT 0
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
#define | SAI_PROTOCOL_DATASIZE_24BIT 2
#define | SAI_PROTOCOL_DATASIZE_32BIT 3

Define Documentation

#define SAI_PROTOCOL_DATASIZE_16BIT 0

Definition at line 292 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1

Definition at line 293 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_24BIT 2

Definition at line 294 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_32BIT 3

Definition at line 295 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Audio Frequency

Defines
SAI Audio Frequency
SAI Exported Constants

Defines

#define | SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U)
#define | SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U)
#define | SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U)
#define | SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U)
#define | SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U)
#define | SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U)
#define | SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U)
#define | SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U)
#define | SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U)
#define | SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U)

Define Documentation

#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U)

Definition at line 310 of file stm32l4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U)

Definition at line 309 of file stm32l4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U)

Definition at line 303 of file stm32l4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U)

Definition at line 308 of file stm32l4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U)

Definition at line 307 of file stm32l4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U)

Definition at line 306 of file stm32l4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U)

Definition at line 305 of file stm32l4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U)

Definition at line 311 of file stm32l4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U)

Definition at line 304 of file stm32l4xx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U)

Definition at line 312 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Mode

Defines
SAI Block Mode
SAI Exported Constants

Defines

#define | SAI_MODEMASTER_TX ((uint32_t)0x00000000U)
#define | SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
#define | SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
#define | SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))

Define Documentation

#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)

Definition at line 321 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U)

Definition at line 320 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))

Definition at line 323 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)

Definition at line 322 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Protocol

Defines
SAI Block Protocol
SAI Exported Constants

Defines

#define | SAI_FREE_PROTOCOL ((uint32_t)0x00000000U)
#define | SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
#define | SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)

Define Documentation

#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)

Definition at line 334 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U)

Definition at line 332 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)

Definition at line 333 of file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Data Size

Defines
SAI Block Data Size
SAI Exported Constants

Defines

#define | SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
#define | SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
#define | SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
#define | SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))

Define Documentation

#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))

Definition at line 343 of file stm32l4xx_hal_sai.h.

#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)

Definition at line 344 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))

Definition at line 345 of file stm32l4xx_hal_sai.h.

#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))

Definition at line 346 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))

Definition at line 347 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)

Definition at line 342 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block MSB LSB transmission

Defines
SAI Block MSB LSB transmission
SAI Exported Constants

Defines

#define | SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
#define | SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)

Define Documentation

#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)

Definition at line 356 of file stm32l4xx_hal_sai.h.

#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U)

Definition at line 355 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Clock Strobing

Defines
SAI Block Clock Strobing
SAI Exported Constants

Defines

#define | SAI_CLOCKSTROBING_FALLINGEDGE 0
#define | SAI_CLOCKSTROBING_RISINGEDGE 1

Define Documentation

#define SAI_CLOCKSTROBING_FALLINGEDGE 0

Definition at line 364 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_CLOCKSTROBING_RISINGEDGE 1

Definition at line 365 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Synchronization

Defines
SAI Block Synchronization
SAI Exported Constants

Defines

#define | SAI_ASYNCHRONOUS 0
#define | SAI_SYNCHRONOUS 1
#define | SAI_SYNCHRONOUS_EXT_SAI1 2
#define | SAI_SYNCHRONOUS_EXT_SAI2 3

Define Documentation

#define SAI_ASYNCHRONOUS 0

Asynchronous

Definition at line 373 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS 1

Synchronous with other block of same SAI

Definition at line 374 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS_EXT_SAI1 2

Synchronous with other SAI, SAI1

Definition at line 375 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS_EXT_SAI2 3

Synchronous with other SAI, SAI2

Definition at line 376 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Output Drive

Defines
SAI Block Output Drive
SAI Exported Constants

Defines

#define | SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U)
#define | SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)

Define Documentation

#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U)

Definition at line 384 of file stm32l4xx_hal_sai.h.

#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)

Definition at line 385 of file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block NoDivider

Defines
SAI Block NoDivider
SAI Exported Constants

Defines

#define | SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U)
#define | SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)

Define Documentation

#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)

Definition at line 394 of file stm32l4xx_hal_sai.h.

#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U)

Definition at line 393 of file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block FS Definition

Defines
SAI Block FS Definition
SAI Exported Constants

Defines

#define | SAI_FS_STARTFRAME ((uint32_t)0x00000000U)
#define | SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)

Define Documentation

#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)

Definition at line 404 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S().

#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U)

Definition at line 403 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitPCM().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block FS Polarity

Defines
SAI Block FS Polarity
SAI Exported Constants

Defines

#define | SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U)
#define | SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)

Define Documentation

#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)

Definition at line 413 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U)

Definition at line 412 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block FS Offset

Defines
SAI Block FS Offset
SAI Exported Constants

Defines

#define | SAI_FS_FIRSTBIT ((uint32_t)0x00000000U)
#define | SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)

Define Documentation

#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)

Definition at line 422 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U)

Definition at line 421 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Slot Size

Defines
SAI Block Slot Size
SAI Exported Constants

Defines

#define | SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)
#define | SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
#define | SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)

Define Documentation

#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)

Definition at line 432 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)

Definition at line 433 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)

Definition at line 431 of file stm32l4xx_hal_sai.h.

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STM32L486xx HAL User Manual: SAI Block Slot Active

Defines
SAI Block Slot Active
SAI Exported Constants

Defines

#define | SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U)
#define | SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U)
#define | SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U)
#define | SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U)
#define | SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U)
#define | SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U)
#define | SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U)
#define | SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U)
#define | SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U)
#define | SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U)
#define | SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U)
#define | SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U)
#define | SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U)
#define | SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U)
#define | SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U)
#define | SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U)
#define | SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U)
#define | SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU)

Define Documentation

#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U)

Definition at line 441 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U)

Definition at line 442 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U)

Definition at line 443 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U)

Definition at line 452 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U)

Definition at line 453 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U)

Definition at line 454 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U)

Definition at line 455 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U)

Definition at line 456 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U)

Definition at line 457 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U)

Definition at line 444 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U)

Definition at line 445 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U)

Definition at line 446 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U)

Definition at line 447 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U)

Definition at line 448 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U)

Definition at line 449 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U)

Definition at line 450 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U)

Definition at line 451 of file stm32l4xx_hal_sai.h.

#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU)

Definition at line 458 of file stm32l4xx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Mono Stereo Mode

Defines
SAI Mono Stereo Mode
SAI Exported Constants

Defines

#define | SAI_STEREOMODE ((uint32_t)0x00000000U)
#define | SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)

Define Documentation

#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)

Definition at line 467 of file stm32l4xx_hal_sai.h.

#define SAI_STEREOMODE ((uint32_t)0x00000000U)

Definition at line 466 of file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI TRIState Management

Defines
SAI TRIState Management
SAI Exported Constants

Defines

#define | SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U)
#define | SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)

Define Documentation

#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U)

Definition at line 475 of file stm32l4xx_hal_sai.h.

#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)

Definition at line 476 of file stm32l4xx_hal_sai.h.

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STM32L486xx HAL User Manual: SAI Block Fifo Threshold

Defines
SAI Block Fifo Threshold
SAI Exported Constants

Defines

#define | SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U)
#define | SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))
#define | SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))
#define | SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
#define | SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))

Define Documentation

#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))

Definition at line 485 of file stm32l4xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))

Definition at line 487 of file stm32l4xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U)

Definition at line 484 of file stm32l4xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))

Definition at line 488 of file stm32l4xx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))

Definition at line 486 of file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Companding Mode

Defines
SAI Block Companding Mode
SAI Exported Constants

Defines

#define | SAI_NOCOMPANDING ((uint32_t)0x00000000U)
#define | SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))
#define | SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
#define | SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
#define | SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))

Define Documentation

#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))

Definition at line 498 of file stm32l4xx_hal_sai.h.

#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))

Definition at line 500 of file stm32l4xx_hal_sai.h.

#define SAI_NOCOMPANDING ((uint32_t)0x00000000U)

Definition at line 496 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))

Definition at line 497 of file stm32l4xx_hal_sai.h.

#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))

Definition at line 499 of file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Mute Value

Defines
SAI Block Mute Value
SAI Exported Constants

Defines

#define | SAI_ZERO_VALUE ((uint32_t)0x00000000U)
#define | SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)

Define Documentation

#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)

Definition at line 509 of file stm32l4xx_hal_sai.h.

#define SAI_ZERO_VALUE ((uint32_t)0x00000000U)

Definition at line 508 of file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Interrupts Definition

Defines
SAI Block Interrupts Definition
SAI Exported Constants

Defines

#define | SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
#define | SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
#define | SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
#define | SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
#define | SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
#define | SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
#define | SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)

Define Documentation

#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)

Definition at line 522 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)

Definition at line 521 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)

Definition at line 520 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)

Definition at line 523 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)

Definition at line 518 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)

Definition at line 517 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)

Definition at line 519 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Block Flags Definition

Defines
SAI Block Flags Definition
SAI Exported Constants

Defines

#define | SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
#define | SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
#define | SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
#define | SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
#define | SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
#define | SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
#define | SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)

Define Documentation

#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)

Definition at line 536 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)

Definition at line 535 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)

Definition at line 534 of file stm32l4xx_hal_sai.h.

#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)

Definition at line 537 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)

Definition at line 532 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)

Definition at line 531 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)

Definition at line 533 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

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STM32L486xx HAL User Manual: SAI Block Fifo Status Level

Defines
SAI Block Fifo Status Level
SAI Exported Constants

Defines

#define | SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U)
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U)
#define | SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U)
#define | SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U)
#define | SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U)
#define | SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U)

Define Documentation

#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U)

Definition at line 547 of file stm32l4xx_hal_sai.h.

#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U)

Definition at line 549 of file stm32l4xx_hal_sai.h.

#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U)

Definition at line 545 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Receive().

#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U)

Definition at line 550 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Transmit(), and SAI_FillFifo().

#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U)

Definition at line 548 of file stm32l4xx_hal_sai.h.

#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U)

Definition at line 546 of file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI Exported Macros

Defines
SAI Exported Macros
SAI

macros to handle interrupts and specific configurations More...

Defines

#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SAI interrupt source is enabled or not.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)

Detailed Description

macros to handle interrupts and specific configurations

Define Documentation

#define __HAL_SAI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CLRFR = (__FLAG__))

Clear the specified SAI pending flag.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • SAI_FLAG_OVRUDR: Clear Overrun underrun
  • SAI_FLAG_MUTEDET: Clear Mute detection
  • SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
  • SAI_FLAG_FREQ: Clear FIFO request
  • SAI_FLAG_CNRDY: Clear Codec not ready
  • SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
  • SAI_FLAG_LFSDET: Clear Late frame synchronization detection
Return values:
None

Definition at line 632 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define __HAL_SAI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)

Definition at line 635 of file stm32l4xx_hal_sai.h.

Referenced by SAI_Disable().

#define __HAL_SAI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))

Definition at line 586 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

#define __HAL_SAI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)

Definition at line 634 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_DMAResume(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

Enable or disable the specified SAI interrupts.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
None

Definition at line 585 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SAI flag is set or not.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SAI_FLAG_OVRUDR: Overrun underrun flag.
  • SAI_FLAG_MUTEDET: Mute detection flag.
  • SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
  • SAI_FLAG_FREQ: FIFO request flag.
  • SAI_FLAG_CNRDY: Codec not ready flag.
  • SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
  • SAI_FLAG_LFSDET: Late frame synchronization detection flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 616 of file stm32l4xx_hal_sai.h.

#define __HAL_SAI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SAI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SAI Handle.
__INTERRUPT__,: specifies the SAI interrupt source to check. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 601 of file stm32l4xx_hal_sai.h.

#define __HAL_SAI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)

Reset SAI handle state.

Parameters:
__HANDLE__,: specifies the SAI Handle.
Return values:
None

Definition at line 570 of file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SAI_Private_Macros

Defines
SAI_Private_Macros
SAI

Defines

#define | IS_SAI_BLOCK_SYNCEXT(STATE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))

Define Documentation

#define IS_SAI_AUDIO_FREQUENCY ( AUDIO )
Value:
(((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))

Definition at line 735 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_ACTIVE_FRAME ( LENGTH ) ((1 <= (LENGTH)) && ((LENGTH) <= 128))

Definition at line 820 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_CLOCK_STROBING ( CLOCK )
Value:
(((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))

Definition at line 760 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_COMPANDING_MODE ( MODE )
Value:
(((MODE) == SAI_NOCOMPANDING)         || \
                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))

Definition at line 779 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_DATASIZE_8)  || \
                                         ((DATASIZE) == SAI_DATASIZE_10) || \
                                         ((DATASIZE) == SAI_DATASIZE_16) || \
                                         ((DATASIZE) == SAI_DATASIZE_20) || \
                                         ((DATASIZE) == SAI_DATASIZE_24) || \
                                         ((DATASIZE) == SAI_DATASIZE_32))

Definition at line 750 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))

Definition at line 785 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRST_BIT ( BIT )
Value:
(((BIT) == SAI_FIRSTBIT_MSB) || \
                                     ((BIT) == SAI_FIRSTBIT_LSB))

Definition at line 757 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRSTBIT_OFFSET ( OFFSET ) ((OFFSET) <= 24)

Definition at line 805 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FRAME_LENGTH ( LENGTH ) ((8 <= (LENGTH)) && ((LENGTH) <= 256))

Definition at line 818 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_DEFINITION ( DEFINITION )
Value:
(((DEFINITION) == SAI_FS_STARTFRAME) || \
                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))

Definition at line 813 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_OFFSET ( OFFSET )
Value:
(((OFFSET) == SAI_FS_FIRSTBIT) || \
                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))

Definition at line 807 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_POLARITY ( POLARITY )
Value:
(((POLARITY) == SAI_FS_ACTIVE_LOW) || \
                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))

Definition at line 810 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MASTER_DIVIDER ( DIVIDER ) ((DIVIDER) <= 15)

Definition at line 816 of file stm32l4xx_hal_sai.h.

#define IS_SAI_BLOCK_MODE ( MODE )
Value:
(((MODE) == SAI_MODEMASTER_TX) || \
                                  ((MODE) == SAI_MODEMASTER_RX) || \
                                  ((MODE) == SAI_MODESLAVE_TX)  || \
                                  ((MODE) == SAI_MODESLAVE_RX))

Definition at line 741 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MUTE_COUNTER ( COUNTER ) ((COUNTER) <= 63)

Definition at line 774 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode().

#define IS_SAI_BLOCK_MUTE_VALUE ( VALUE )
Value:
(((VALUE) == SAI_ZERO_VALUE)     || \
                                           ((VALUE) == SAI_LAST_SENT_VALUE))

Definition at line 776 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_EnableTxMuteMode().

#define IS_SAI_BLOCK_NODIVIDER ( NODIVIDER )
Value:
(((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))

Definition at line 771 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_OUTPUT_DRIVE ( DRIVE )
Value:
(((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))

Definition at line 768 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))

Definition at line 746 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_NUMBER ( NUMBER ) ((1 <= (NUMBER)) && ((NUMBER) <= 16))

Definition at line 799 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_SIZE ( SIZE )
Value:
(((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
                                      ((SIZE) == SAI_SLOTSIZE_32B))

Definition at line 801 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCEXT ( STATE )
Value:
(((STATE) == SAI_SYNCEXT_DISABLE) ||\
                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))

Definition at line 720 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCHRO ( SYNCHRO )
Value:
(((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))

Definition at line 763 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT ( STATE )
Value:
(((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
                                                 ((STATE) == SAI_OUTPUT_RELEASED))

Definition at line 791 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_MONO_STEREO_MODE ( MODE )
Value:
(((MODE) == SAI_MONOMODE) ||\
                                       ((MODE) == SAI_STEREOMODE))

Definition at line 794 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_PROTOCOL_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))

Definition at line 730 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define IS_SAI_SLOT_ACTIVE ( ACTIVE ) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)

Definition at line 797 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_SUPPORTED_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_I2S_STANDARD)     ||\
                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\
                                               ((PROTOCOL) == SAI_PCM_SHORT))

Definition at line 724 of file stm32l4xx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Private Constants

Defines
SMARTCARD Private Constants
SMARTCARD

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))

Define Documentation

#define SMARTCARD_TEACK_REACK_TIMEOUT 1000

SMARTCARD TX or RX enable acknowledge time-out value

Definition at line 154 of file stm32l4xx_hal_smartcard.c.

Referenced by SMARTCARD_CheckIdleState().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))

USART CR1 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 156 of file stm32l4xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))

SMARTCARD clock-related USART CR2 fields of parameters

Definition at line 158 of file stm32l4xx_hal_smartcard.c.

#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))

USART CR2 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 159 of file stm32l4xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))

USART CR3 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 160 of file stm32l4xx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMARTCARD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.

Detailed Description

Initialization and Configuration functions.

  ===============================================================================
              ##### Initialization and Configuration functions #####
  ===============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  associated to the SmartCard.
  (+) These parameters can be configured:
      (++) Baud Rate
      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
      (++) Receiver/transmitter modes
      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
      (++) Prescaler value
      (++) Guard bit time
      (++) NACK enabling or disabling on transmission error

  (+) The following advanced features can be configured as well:
      (++) TX and/or RX pin level inversion
      (++) data logical level inversion
      (++) RX and TX pins swap
      (++) RX overrun detection disabling
      (++) DMA disabling on RX error
      (++) MSB first on communication line
      (++) Time out enabling (and if activated, timeout value)
      (++) Block length
      (++) Auto-retry counter
  [..]
  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
  (details for the procedures are available in reference manual).

The USART frame format is given in the following table:

Table 1. USART frame format. +---------------------------------------------------------------+ | M1M0 bits | PCE bit | USART frame | |-----------------------|---------------------------------------| | 01 | 1 | | SB | 8 bit data | PB | STB | | +---------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_DeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD peripheral.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 308 of file stm32l4xx_hal_smartcard.c.

References assert_param, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_SMARTCARD_Init ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 246 of file stm32l4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::Lock, SMARTCARD_ADVFEATURE_NO_INIT, SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_SetConfig(), and SMARTCARD_TRANSMISSION_COMPLETION_SETTING.

void HAL_SMARTCARD_MspDeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD MSP.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 365 of file stm32l4xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_DeInit().

void HAL_SMARTCARD_MspInit ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD MSP.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 349 of file stm32l4xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
SMARTCARD Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.

  [..]
    Smartcard is a single wire half duplex communication protocol.
    The Smartcard interface is designed to support asynchronous protocol Smartcards as
    defined in the ISO 7816-3 standard. The USART should be configured as:
    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.

  [..]
    (+) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode: The communication is performed using Interrupts
             or DMA, the relevant API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
        (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
             error is detected.

    (+) Blocking mode APIs are :
        (++) HAL_SMARTCARD_Transmit()
        (++) HAL_SMARTCARD_Receive()

    (+) Non Blocking mode APIs with Interrupt are :
        (++) HAL_SMARTCARD_Transmit_IT()
        (++) HAL_SMARTCARD_Receive_IT()
        (++) HAL_SMARTCARD_IRQHandler()

    (+) Non Blocking mode functions with DMA are :
        (++) HAL_SMARTCARD_Transmit_DMA()
        (++) HAL_SMARTCARD_Receive_DMA()

    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_SMARTCARD_TxCpltCallback()
        (++) HAL_SMARTCARD_RxCpltCallback()
        (++) HAL_SMARTCARD_ErrorCallback()

Function Documentation

void HAL_SMARTCARD_ErrorCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD error callback.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 934 of file stm32l4xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

void HAL_SMARTCARD_IRQHandler ( SMARTCARD_HandleTypeDef * hsmartcard )

Handle SMARTCARD interrupt requests.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 807 of file stm32l4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_IT, __HAL_SMARTCARD_GET_IT, __HAL_SMARTCARD_GET_IT_SOURCE, SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_FE, HAL_SMARTCARD_ERROR_NE, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_ERROR_ORE, HAL_SMARTCARD_ERROR_PE, HAL_SMARTCARD_ERROR_RTO, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_EndTransmit_IT(), SMARTCARD_IT_EOB, SMARTCARD_IT_ERR, SMARTCARD_IT_FE, SMARTCARD_IT_NE, SMARTCARD_IT_ORE, SMARTCARD_IT_PE, SMARTCARD_IT_RTO, SMARTCARD_IT_RXNE, SMARTCARD_IT_TXE, SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), and SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication.

HAL_StatusTypeDef HAL_SMARTCARD_Receive | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData,: pointer to data buffer.
Size,: amount of data to be received.
Timeout : Timeout duration.
Return values:
HAL status

Definition at line 523 of file stm32l4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FLAG_RXNE, and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData,: pointer to data buffer.
Size,: amount of data to be received.
Note:
The SMARTCARD-associated USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
Return values:
HAL status

Definition at line 755 of file stm32l4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData,: pointer to data buffer.
Size,: amount of data to be received.
Return values:
HAL status

Definition at line 636 of file stm32l4xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_IT_ERR, SMARTCARD_IT_PE, and SMARTCARD_IT_RXNE.

void HAL_SMARTCARD_RxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Rx Transfer completed callback.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 918 of file stm32l4xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMAReceiveCplt(), and SMARTCARD_Receive_IT().

HAL_StatusTypeDef HAL_SMARTCARD_Transmit | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData,: pointer to data buffer.
Size,: amount of data to be sent.
Timeout : Timeout duration.
Return values:
HAL status

Definition at line 442 of file stm32l4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_FLAG_TXE, SMARTCARD_MODE_TX_RX, SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_TRANSMISSION_COMPLETION_FLAG, SMARTCARD_WaitOnFlagUntilTimeout(), SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData,: pointer to data buffer.
Size,: amount of data to be sent.
Return values:
HAL status

Definition at line 684 of file stm32l4xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_CLEAR_TCF, SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_HandleTypeDef::TxXferCount, SMARTCARD_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData,: pointer to data buffer.
Size,: amount of data to be sent.
Return values:
HAL status

Definition at line 580 of file stm32l4xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_IT_ERR, SMARTCARD_IT_TXE, SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

void HAL_SMARTCARD_TxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Tx Transfer completed callback.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 902 of file stm32l4xx_hal_smartcard.c.

Referenced by SMARTCARD_EndTransmit_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMARTCARD Exported Functions

SMARTCARD State and Errors functions. More...

Functions

HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of SmartCard
    handle and also return Peripheral Errors occurred during communication process
     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
         of the SMARTCARD peripheral.
     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_SMARTCARD_GetError ( SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle error code.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle Error Code

Definition at line 989 of file stm32l4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode.

HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState ( SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle state.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle state

Definition at line 974 of file stm32l4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, and SMARTCARD_HandleTypeDef::RxState.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Private Functions

Functions
SMARTCARD Private Functions
SMARTCARD

Functions

static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.

Function Documentation

static void SMARTCARD_AdvFeatureConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral advanced features.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1325 of file stm32l4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_AdvFeatureInitTypeDef::DataInvert, SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_ADVFEATURE_DATAINV, IS_SMARTCARD_ADVFEATURE_DMAONRXERROR, IS_SMARTCARD_ADVFEATURE_INIT, IS_SMARTCARD_ADVFEATURE_MSBFIRST, IS_SMARTCARD_ADVFEATURE_RXINV, IS_SMARTCARD_ADVFEATURE_SWAP, IS_SMARTCARD_ADVFEATURE_TXINV, IS_SMARTCARD_OVERRUN, SMARTCARD_AdvFeatureInitTypeDef::MSBFirst, SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable, SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert, SMARTCARD_ADVFEATURE_DATAINVERT_INIT, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT, SMARTCARD_ADVFEATURE_MSBFIRST_INIT, SMARTCARD_ADVFEATURE_RXINVERT_INIT, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT, SMARTCARD_ADVFEATURE_SWAP_INIT, SMARTCARD_ADVFEATURE_TXINVERT_INIT, SMARTCARD_AdvFeatureInitTypeDef::Swap, and SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_CheckIdleState ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Check the SMARTCARD Idle State.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 1387 of file stm32l4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_TEACK_REACK_TIMEOUT, and SMARTCARD_WaitOnFlagUntilTimeout().

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication error callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1210 of file stm32l4xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD receive process complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1189 of file stm32l4xx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, and SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA().

static void SMARTCARD_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD transmit process complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1170 of file stm32l4xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_DMA().

static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 1050 of file stm32l4xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_TxCpltCallback(), SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_IT_ERR, SMARTCARD_MODE_TX_RX, and SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_Receive_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module. Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
Return values:
HAL status

Definition at line 1091 of file stm32l4xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_IT_ERR, SMARTCARD_IT_PE, and SMARTCARD_IT_RXNE.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_SetConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1227 of file stm32l4xx_hal_smartcard.c.

References assert_param, SMARTCARD_InitTypeDef::AutoRetryCount, SMARTCARD_InitTypeDef::BaudRate, SMARTCARD_InitTypeDef::BlockLength, SMARTCARD_InitTypeDef::CLKLastBit, SMARTCARD_InitTypeDef::CLKPhase, SMARTCARD_InitTypeDef::CLKPolarity, SMARTCARD_InitTypeDef::GuardTime, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_AUTORETRY_COUNT, IS_SMARTCARD_BAUDRATE, IS_SMARTCARD_LASTBIT, IS_SMARTCARD_MODE, IS_SMARTCARD_NACK, IS_SMARTCARD_ONE_BIT_SAMPLE, IS_SMARTCARD_PARITY, IS_SMARTCARD_PHASE, IS_SMARTCARD_POLARITY, IS_SMARTCARD_STOPBITS, IS_SMARTCARD_TIMEOUT, IS_SMARTCARD_TIMEOUT_VALUE, IS_SMARTCARD_WORD_LENGTH, LSE_VALUE, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, SMARTCARD_InitTypeDef::OneBitSampling, SMARTCARD_InitTypeDef::Parity, SMARTCARD_InitTypeDef::Prescaler, SMARTCARD_CLOCKSOURCE_HSI, SMARTCARD_CLOCKSOURCE_LSE, SMARTCARD_CLOCKSOURCE_PCLK1, SMARTCARD_CLOCKSOURCE_PCLK2, SMARTCARD_CLOCKSOURCE_SYSCLK, SMARTCARD_CLOCKSOURCE_UNDEFINED, SMARTCARD_CR3_SCARCNT_LSB_POS, SMARTCARD_GETCLOCKSOURCE, SMARTCARD_GTPR_GT_LSB_POS, SMARTCARD_RTOR_BLEN_LSB_POS, SMARTCARD_TIMEOUT_ENABLE, SMARTCARD_InitTypeDef::StopBits, SMARTCARD_InitTypeDef::TimeOutEnable, SMARTCARD_InitTypeDef::TimeOutValue, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_CR3_FIELDS, and SMARTCARD_InitTypeDef::WordLength.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_Transmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module. Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
Return values:
HAL status

Definition at line 1014 of file stm32l4xx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, __HAL_SMARTCARD_ENABLE_IT, SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_IT_TXE, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMARTCARD Communication Timeout.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Flag | Specifies the SMARTCARD flag to check.
Status | The new Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1137 of file stm32l4xx_hal_smartcard.c.

References __HAL_SMARTCARD_GET_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), and SMARTCARD_CheckIdleState().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Exported Types

Data Structures | Enumerations
SMARTCARD Exported Types
SMARTCARD

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00U, HAL_SMARTCARD_STATE_READY = 0x20U, HAL_SMARTCARD_STATE_BUSY = 0x24U, HAL_SMARTCARD_STATE_BUSY_TX = 0x21U,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, HAL_SMARTCARD_STATE_ERROR = 0xE0U
}
HAL SMARTCARD State structures definition. More...
enum HAL_SMARTCARD_ErrorTypeDef {
HAL_SMARTCARD_ERROR_NONE = 0x00, HAL_SMARTCARD_ERROR_PE = 0x01, HAL_SMARTCARD_ERROR_NE = 0x02, HAL_SMARTCARD_ERROR_FE = 0x04,
HAL_SMARTCARD_ERROR_ORE = 0x08, HAL_SMARTCARD_ERROR_DMA = 0x10, HAL_SMARTCARD_ERROR_RTO = 0x20
}
HAL SMARTCARD Error Code structure definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, SMARTCARD_CLOCKSOURCE_HSI = 0x02, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04,
SMARTCARD_CLOCKSOURCE_LSE = 0x08, SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10
}
SMARTCARD clock sources. More...

Enumeration Type Documentation

enum HAL_SMARTCARD_ErrorTypeDef

HAL SMARTCARD Error Code structure definition.

Enumerator:
HAL_SMARTCARD_ERROR_NONE

No error

HAL_SMARTCARD_ERROR_PE

Parity error

HAL_SMARTCARD_ERROR_NE

Noise error

HAL_SMARTCARD_ERROR_FE

frame error

HAL_SMARTCARD_ERROR_ORE

Overrun error

HAL_SMARTCARD_ERROR_DMA

DMA transfer error

HAL_SMARTCARD_ERROR_RTO

Receiver TimeOut error

Definition at line 224 of file stm32l4xx_hal_smartcard.h.

enum HAL_SMARTCARD_StateTypeDef

HAL SMARTCARD State structures definition.

Note:
HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
  • gState contains SMARTCARD state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_SMARTCARD_STATE_RESET

Peripheral is not initialized Value is allowed for gState and RxState

HAL_SMARTCARD_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_SMARTCARD_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_SMARTCARD_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_SMARTCARD_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_SMARTCARD_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_SMARTCARD_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_SMARTCARD_STATE_ERROR

Error Value is allowed for gState only

Definition at line 200 of file stm32l4xx_hal_smartcard.h.

enum SMARTCARD_ClockSourceTypeDef

SMARTCARD clock sources.

Enumerator:
SMARTCARD_CLOCKSOURCE_PCLK1

PCLK1 clock source

SMARTCARD_CLOCKSOURCE_PCLK2

PCLK2 clock source

SMARTCARD_CLOCKSOURCE_HSI

HSI clock source

SMARTCARD_CLOCKSOURCE_SYSCLK

SYSCLK clock source

SMARTCARD_CLOCKSOURCE_LSE

LSE clock source

SMARTCARD_CLOCKSOURCE_UNDEFINED

undefined clock source

Definition at line 278 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_InitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD Init Structure definition. More...

#include <stm32l4xx_hal_smartcard.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint16_t | Parity
uint16_t | Mode
uint16_t | CLKPolarity
uint16_t | CLKPhase
uint16_t | CLKLastBit
uint16_t | OneBitSampling
uint8_t | Prescaler
uint8_t | GuardTime
uint16_t | NACKEnable
uint32_t | TimeOutEnable
uint32_t | TimeOutValue
uint8_t | BlockLength
uint8_t | AutoRetryCount

Detailed Description

SMARTCARD Init Structure definition.

Definition at line 65 of file stm32l4xx_hal_smartcard.h.

Field Documentation

uint8_t SMARTCARD_InitTypeDef::AutoRetryCount

Specifies the SmartCard auto-retry count (number of retries in receive and transmit mode). When set to 0, retransmission is disabled. Otherwise, its maximum value is 7 (before signalling an error)

Definition at line 118 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::BaudRate

Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate)))

Definition at line 67 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::BlockLength

Specifies the SmartCard Block Length in T=1 Reception mode. This parameter can be any value from 0x0 to 0xFF

Definition at line 115 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of SMARTCARD Last Bit

Definition at line 92 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SMARTCARD Clock Phase

Definition at line 89 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of SMARTCARD Clock Polarity

Definition at line 86 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::GuardTime

Specifies the SmartCard Guard Time applied after stop bits.

Definition at line 102 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of SMARTCARD Transfer Mode

Definition at line 83 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::NACKEnable

Specifies whether the SmartCard NACK transmission is enabled in case of parity error. This parameter can be a value of SMARTCARD NACK Enable

Definition at line 104 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of SMARTCARD One Bit Sampling Method.

Definition at line 96 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of SMARTCARD Parity

Note:
The parity is enabled by default (PCE is forced to 1). Since the WordLength is forced to 8 bits + parity, M is forced to 1 and the parity bit is the 9th bit.

Definition at line 77 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::Prescaler

Specifies the SmartCard Prescaler.

Definition at line 100 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::StopBits

Specifies the number of stop bits. This parameter can be a value of SMARTCARD Number of Stop Bits.

Definition at line 74 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutEnable

Specifies whether the receiver timeout is enabled. This parameter can be a value of SMARTCARD Timeout Enable

Definition at line 108 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutValue

Specifies the receiver time out value in number of baud blocks: it is used to implement the Character Wait Time (CWT) and Block Wait Time (BWT). It is coded over 24 bits.

Definition at line 111 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter SMARTCARD Word Length can only be set to 9 (8 data + 1 parity bits).

Definition at line 71 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_smartcard.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_AdvFeatureInitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD advanced features initalization structure definition. More...

#include <stm32l4xx_hal_smartcard.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | MSBFirst
uint16_t | TxCompletionIndication

Detailed Description

SMARTCARD advanced features initalization structure definition.

Definition at line 128 of file stm32l4xx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced SMARTCARD features is initialized. Several advanced features may be initialized at the same time. This parameter can be a value of SMARTCARD advanced feature initialization type

Definition at line 130 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of SMARTCARD advanced feature Binary Data inversion

Definition at line 140 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of SMARTCARD advanced feature DMA Disable on Rx Error

Definition at line 150 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of SMARTCARD advanced feature MSB first

Definition at line 153 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of SMARTCARD advanced feature Overrun Disable

Definition at line 147 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature RX pin active level inversion

Definition at line 137 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of SMARTCARD advanced feature RX TX pins swap

Definition at line 144 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint16_t SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication

Specifies which transmission completion indication is used: before (when relevant flag is available) or once guard time period has elapsed. This parameter can be a value of SMARTCARD Transmission Completion Indication.

Definition at line 156 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_Transmit_IT().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature TX pin active level inversion

Definition at line 134 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_smartcard.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_HandleTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD handle Structure definition. More...

#include <stm32l4xx_hal_smartcard.h>

Data Fields

USART_TypeDef * | Instance
SMARTCARD_InitTypeDef Init
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SMARTCARD_StateTypeDef | gState
__IO HAL_SMARTCARD_StateTypeDef | RxState
uint32_t | ErrorCode

Detailed Description

SMARTCARD handle Structure definition.

Definition at line 238 of file stm32l4xx_hal_smartcard.h.

Field Documentation

SMARTCARD_AdvFeatureInitTypeDef SMARTCARD_HandleTypeDef::AdvancedInit

SmartCard advanced features initialization parameters

Definition at line 244 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_Transmit_IT().

uint32_t SMARTCARD_HandleTypeDef::ErrorCode

SmartCard Error code

Definition at line 271 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetError(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_CheckIdleState(), and SMARTCARD_DMAError().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::gState

SmartCard state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 264 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_EndTransmit_IT(), SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmarx

SmartCard Rx DMA Handle parameters

Definition at line 260 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmatx

SmartCard Tx DMA Handle parameters

Definition at line 258 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA().

SMARTCARD_InitTypeDef SMARTCARD_HandleTypeDef::Init

SmartCard communication parameters

Definition at line 242 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

USART_TypeDef* SMARTCARD_HandleTypeDef::Instance

USART registers base address

Definition at line 240 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_BlockLength_Config(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), SMARTCARD_Receive_IT(), SMARTCARD_SetConfig(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_LockTypeDef SMARTCARD_HandleTypeDef::Lock

Locking object

Definition at line 262 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

uint8_t* SMARTCARD_HandleTypeDef::pRxBuffPtr

Pointer to SmartCard Rx transfer Buffer

Definition at line 252 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), and SMARTCARD_Receive_IT().

uint8_t* SMARTCARD_HandleTypeDef::pTxBuffPtr

Pointer to SmartCard Tx transfer Buffer

Definition at line 246 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Transmit_IT().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::RxState

SmartCard state information related to Rx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 268 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_EndTransmit_IT(), SMARTCARD_Receive_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

uint16_t SMARTCARD_HandleTypeDef::RxXferCount

SmartCard Rx Transfer Counter

Definition at line 256 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), and SMARTCARD_Receive_IT().

uint16_t SMARTCARD_HandleTypeDef::RxXferSize

SmartCard Rx Transfer size

Definition at line 254 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Receive_IT().

uint16_t SMARTCARD_HandleTypeDef::TxXferCount

SmartCard Tx Transfer Counter

Definition at line 250 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), and SMARTCARD_Transmit_IT().

uint16_t SMARTCARD_HandleTypeDef::TxXferSize

SmartCard Tx Transfer size

Definition at line 248 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_smartcard.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Word Length

Defines
SMARTCARD Word Length
SMARTCARD Exported Constants

Defines

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

SMARTCARD frame length

Definition at line 300 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Number of Stop Bits

Defines
SMARTCARD Number of Stop Bits
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Define Documentation

#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)

SMARTCARD frame with 0.5 stop bit

Definition at line 308 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

SMARTCARD frame with 1.5 stop bits

Definition at line 309 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Parity

Defines
SMARTCARD Parity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

SMARTCARD frame even parity

Definition at line 317 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

SMARTCARD frame odd parity

Definition at line 318 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Transfer Mode

Defines
SMARTCARD Transfer Mode
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)

SMARTCARD RX mode

Definition at line 326 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)

SMARTCARD TX mode

Definition at line 327 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

SMARTCARD RX and TX mode

Definition at line 328 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), and SMARTCARD_EndTransmit_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Clock Polarity

Defines
SMARTCARD Clock Polarity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

SMARTCARD frame high polarity

Definition at line 337 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)

SMARTCARD frame low polarity

Definition at line 336 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Clock Phase

Defines
SMARTCARD Clock Phase
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)

SMARTCARD frame phase on first clock transition

Definition at line 345 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

SMARTCARD frame phase on second clock transition

Definition at line 346 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Last Bit

Defines
SMARTCARD Last Bit
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)

SMARTCARD frame last data bit clock pulse not output to SCLK pin

Definition at line 354 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

SMARTCARD frame last data bit clock pulse output to SCLK pin

Definition at line 355 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD One Bit Sampling Method

Defines
SMARTCARD One Bit Sampling Method
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)

SMARTCARD frame one-bit sample disabled

Definition at line 363 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

SMARTCARD frame one-bit sample enabled

Definition at line 364 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD NACK Enable

Defines
SMARTCARD NACK Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)

SMARTCARD NACK transmission enabled

Definition at line 374 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)

SMARTCARD NACK transmission disabled

Definition at line 373 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Timeout Enable

Defines
SMARTCARD Timeout Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

Define Documentation

#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)

SMARTCARD receiver timeout disabled

Definition at line 382 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

SMARTCARD receiver timeout enabled

Definition at line 383 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD advanced feature TX pin active level inversion

Defines
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)

TX pin active level inversion disable

Definition at line 391 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

TX pin active level inversion enable

Definition at line 392 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD advanced feature RX pin active level inversion

Defines
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)

RX pin active level inversion disable

Definition at line 400 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

RX pin active level inversion enable

Definition at line 401 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD advanced feature Binary Data inversion

Defines
SMARTCARD advanced feature Binary Data inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)

Binary data inversion disable

Definition at line 409 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Binary data inversion enable

Definition at line 410 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD advanced feature RX TX pins swap

Defines
SMARTCARD advanced feature RX TX pins swap
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

Define Documentation

#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)

TX/RX pins swap disable

Definition at line 418 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

TX/RX pins swap enable

Definition at line 419 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD advanced feature Overrun Disable

Defines
SMARTCARD advanced feature Overrun Disable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

Define Documentation

#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

RX overrun disable

Definition at line 428 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)

RX overrun enable

Definition at line 427 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD advanced feature DMA Disable on Rx Error

Defines
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

Define Documentation

#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

DMA disable on Reception Error

Definition at line 437 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)

DMA enable on Reception Error

Definition at line 436 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD advanced feature MSB first

Defines
SMARTCARD advanced feature MSB first
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Define Documentation

#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)

Most significant bit sent/received first disable

Definition at line 445 of file stm32l4xx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Most significant bit sent/received first enable

Definition at line 446 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Request Parameters

Defines
SMARTCARD Request Parameters
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)
#define | SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)

Define Documentation

#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)

Receive data flush request

Definition at line 454 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)

Transmit data flush request

Definition at line 455 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD auto retry counter LSB position in CR3 register

Defines
SMARTCARD auto retry counter LSB position in CR3 register
SMARTCARD Exported Constants

Defines

#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)

Define Documentation

#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)

SMARTCARD auto retry counter LSB position in CR3 register

Definition at line 463 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD guard time value LSB position in GTPR register

Defines
SMARTCARD guard time value LSB position in GTPR register
SMARTCARD Exported Constants

Defines

#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)

Define Documentation

#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)

SMARTCARD guard time value LSB position in GTPR register

Definition at line 471 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD block length LSB position in RTOR register

Defines
SMARTCARD block length LSB position in RTOR register
SMARTCARD Exported Constants

Defines

#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)

Define Documentation

#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)

SMARTCARD block length LSB position in RTOR register

Definition at line 479 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_BlockLength_Config(), and SMARTCARD_SetConfig().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD interruptions flags mask

Defines
SMARTCARD interruptions flags mask
SMARTCARD Exported Constants

Defines

#define SMARTCARD_IT_MASK ((uint16_t)0x001F)

Define Documentation

#define SMARTCARD_IT_MASK ((uint16_t)0x001F)

SMARTCARD interruptions flags mask

Definition at line 487 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Exported Macros

Defines
SMARTCARD Exported Macros
SMARTCARD

Defines

#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.

Define Documentation

#define __HAL_SMARTCARD_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)

Clear the SMARTCARD FE pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 550 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified SMARTCARD pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
Return values:
None

Definition at line 537 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA().

#define __HAL_SMARTCARD_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)

Clear the SMARTCARD IDLE pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 568 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))

Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
Return values:
None

Definition at line 699 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)

Clear the SMARTCARD NE pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 556 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)

Clear the SMARTCARD ORE pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 562 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)

Clear the SMARTCARD PE pending flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 543 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 734 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Disable the specified SmartCard interrupt.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__INTERRUPT__,: specifies the SMARTCARD interrupt to disable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
Return values:
None

Definition at line 633 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_EndTransmit_IT(), SMARTCARD_Receive_IT(), and SMARTCARD_Transmit_IT().

#define __HAL_SMARTCARD_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 728 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Enable the specified SmartCard interrupt.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__INTERRUPT__,: specifies the SMARTCARD interrupt to enable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
Return values:
None

Definition at line 612 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMATransmitCplt(), and SMARTCARD_Transmit_IT().

#define __HAL_SMARTCARD_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                              \
      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
      } while(0)

Flush the Smartcard Data registers.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 514 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SMARTCARD_FLAG_REACK Receive enable acknowledge flag
  • SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
  • SMARTCARD_FLAG_BUSY Busy flag
  • SMARTCARD_FLAG_EOBF End of block flag
  • SMARTCARD_FLAG_RTOF Receiver timeout flag
  • SMARTCARD_FLAG_TXE Transmit data register empty flag
  • SMARTCARD_FLAG_TC Transmission complete flag
  • SMARTCARD_FLAG_RXNE Receive data register not empty flag
  • SMARTCARD_FLAG_IDLE Idle line detection flag
  • SMARTCARD_FLAG_ORE Overrun error flag
  • SMARTCARD_FLAG_NE Noise error flag
  • SMARTCARD_FLAG_FE Framing error flag
  • SMARTCARD_FLAG_PE Parity error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 592 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))

Check whether the specified SmartCard interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__IT__,: specifies the SMARTCARD interrupt to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_ORE Overrun error interrupt
  • SMARTCARD_IT_NE Noise error interrupt
  • SMARTCARD_IT_FE Framing error interrupt
  • SMARTCARD_IT_PE Parity error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 657 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
                                                           (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
                                                           (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))

Check whether the specified SmartCard interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__IT__,: specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_ERR Framing, overrun or noise error interrupt
  • SMARTCARD_IT_PE Parity error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 676 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 722 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Return values:
None

Definition at line 716 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                       \
                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
                                                          } while(0)

Reset SMARTCARD handle states.

Parameters:
__HANDLE__,: SMARTCARD handle.
Return values:
None

Definition at line 505 of file stm32l4xx_hal_smartcard.h.

#define __HAL_SMARTCARD_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific SMARTCARD request flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__REQ__,: specifies the request flag to set This parameter can be one of the following values:
  • SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
  • SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 710 of file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Private Macros

Defines
SMARTCARD Private Macros
SMARTCARD

Defines

#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 5000001)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Define Documentation

#define IS_SMARTCARD_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))

Ensure that SMARTCARD frame data inversion setting is valid.

Parameters:
__DATAINV__,: SMARTCARD frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 885 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__,: SMARTCARD DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 909 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))

Ensure that SMARTCARD advanced features initialization is valid.

Parameters:
__INIT__,: SMARTCARD advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 855 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that SMARTCARD frame MSB first setting is valid.

Parameters:
__MSBFIRST__,: SMARTCARD frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 917 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))

Ensure that SMARTCARD frame RX inversion setting is valid.

Parameters:
__RXINV__,: SMARTCARD frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 877 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))

Ensure that SMARTCARD frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__,: SMARTCARD frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 893 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))

Ensure that SMARTCARD frame TX inversion setting is valid.

Parameters:
__TXINV__,: SMARTCARD frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 869 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_AUTORETRY_COUNT ( __COUNT__ ) ((__COUNT__) <= 0x7)

Check the SMARTCARD autoretry counter value.

Note:
The maximum number of retransmissions is 0x7.
Parameters:
__COUNT__,: number of retransmissions.
Return values:
Test result (TRUE or FALSE)

Definition at line 772 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 5000001)

Check the Baud rate range.

Note:
The maximum Baud Rate is derived from the maximum clock on L4 (80 MHz) divided by the oversampling used on the SMARTCARD (i.e. 16).
Parameters:
__BAUDRATE__,: Baud rate set by the configuration function.
Return values:
Test result (TRUE or FALSE)

Definition at line 751 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BLOCKLENGTH ( __LENGTH__ ) ((__LENGTH__) <= 0xFF)

Check the block length range.

Note:
The maximum SMARTCARD block length is 0xFF.
Parameters:
__LENGTH__,: block length.
Return values:
Test result (TRUE or FALSE)

Definition at line 758 of file stm32l4xx_hal_smartcard.h.

#define IS_SMARTCARD_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))

Ensure that SMARTCARD frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__,: SMARTCARD frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 823 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_MODE ( __MODE__ ) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))

Ensure that SMARTCARD communication mode is valid.

Parameters:
__MODE__,: SMARTCARD communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 802 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_NACK ( __NACK__ )
Value:
(((__NACK__) == SMARTCARD_NACK_ENABLE) || \
                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))

Ensure that SMARTCARD NACK transmission setting is valid.

Parameters:
__NACK__,: SMARTCARD NACK transmission setting.
Return values:
SET (__NACK__ is valid) or RESET (__NACK__ is invalid)

Definition at line 839 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))

Ensure that SMARTCARD frame sampling is valid.

Parameters:
__ONEBIT__,: SMARTCARD frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 831 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))

Ensure that SMARTCARD frame overrun setting is valid.

Parameters:
__OVERRUN__,: SMARTCARD frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 901 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))

Ensure that SMARTCARD frame parity is valid.

Parameters:
__PARITY__,: SMARTCARD frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 794 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PHASE ( __CPHA__ ) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))

Ensure that SMARTCARD frame phase is valid.

Parameters:
__CPHA__,: SMARTCARD frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 816 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_POLARITY ( __CPOL__ ) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))

Ensure that SMARTCARD frame polarity is valid.

Parameters:
__CPOL__,: SMARTCARD frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 809 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))

Ensure that SMARTCARD request parameter is valid.

Parameters:
__PARAM__,: SMARTCARD request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 925 of file stm32l4xx_hal_smartcard.h.

#define IS_SMARTCARD_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))

Ensure that SMARTCARD frame number of stop bits is valid.

Parameters:
__STOPBITS__,: SMARTCARD frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 786 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))

Ensure that SMARTCARD receiver timeout setting is valid.

Parameters:
__TIMEOUT__,: SMARTCARD receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 847 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFF)

Check the receiver timeout value.

Note:
The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__,: receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 765 of file stm32l4xx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

#define IS_SMARTCARD_WORD_LENGTH ( __LENGTH__ ) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)

Ensure that SMARTCARD frame length is valid.

Parameters:
__LENGTH__,: SMARTCARD frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 779 of file stm32l4xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
SMARTCARD Extended Exported Functions

Extended control functions. More...

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Extended control functions.

  ===============================================================================
                      ##### Peripheral Control functions #####
  ===============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the SMARTCARD.
     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature

Function Documentation

void HAL_SMARTCARDEx_BlockLength_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t | BlockLength
 | ) |  |

Update on the fly the SMARTCARD block length in RTOR register.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
BlockLength,: SMARTCARD block length (8-bit long at most)
Return values:
None

Definition at line 107 of file stm32l4xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_RTOR_BLEN_LSB_POS.

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 164 of file stm32l4xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 132 of file stm32l4xx_hal_smartcard_ex.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and SMARTCARD_HandleTypeDef::Instance.

void HAL_SMARTCARDEx_TimeOut_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | TimeOutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
hsmartcard,: Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
TimeOutValue,: receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 120 of file stm32l4xx_hal_smartcard_ex.c.

References assert_param, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TIMEOUT_VALUE, and SMARTCARD_InitTypeDef::TimeOutValue.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Extended Private Macros

Defines
SMARTCARD Extended Private Macros
SMARTCARDEx

Defines

#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC)
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
Ensure that SMARTCARD frame transmission completion used flag is valid.

Define Documentation

#define IS_SMARTCARD_TRANSMISSION_COMPLETION ( __TXCOMPLETE__ ) ((__TXCOMPLETE__) == SMARTCARD_TC)

Ensure that SMARTCARD frame transmission completion used flag is valid.

Parameters:
__TXCOMPLETE__,: SMARTCARD frame transmission completion used flag.
Return values:
SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)

Definition at line 346 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the SMARTCARD clock source.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
__CLOCKSOURCE__,: output variable.
Return values:
the SMARTCARD clocking source, written in __CLOCKSOURCE__.

Definition at line 231 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_SetConfig().

#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG ( __HANDLE__ ) (SMARTCARD_FLAG_TC)

Return the transmission completion flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Note:
Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is reported.
Return values:
Transmission completion flag

Definition at line 333 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING ( __HANDLE__ )
Value:
do {                                                            \
    (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
  } while(0)

Set the Transmission Completion flag.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle.
Note:
If TCBGT (Transmission Complete Before Guard Time) flag is not available or if AdvancedInit.TxCompletionIndication is not already filled, the latter is forced to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
Return values:
None

Definition at line 307 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Transmission Completion Indication

Defines
SMARTCARD Transmission Completion Indication
SMARTCARD Extended Exported Constants

Defines

#define SMARTCARD_TC SMARTCARD_IT_TC

Define Documentation

#define SMARTCARD_TC SMARTCARD_IT_TC

SMARTCARD transmission complete (flag raised when guard time has elapsed)

Definition at line 70 of file stm32l4xx_hal_smartcard_ex.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD advanced feature initialization type

Defines
SMARTCARD advanced feature initialization type
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
#define | SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)

Binary data inversion

Definition at line 81 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)

DMA disable on Reception Error

Definition at line 84 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)

Most significant bit sent/received first

Definition at line 85 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)

No advanced feature initialization

Definition at line 78 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)

RX pin active level inversion

Definition at line 80 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)

RX overrun disable

Definition at line 83 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)

TX/RX pins swap

Definition at line 82 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)

TX pin active level inversion

Definition at line 79 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Flags

Defines
SMARTCARD Flags
SMARTCARD Extended Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY

SMARTCARD busy flag

Definition at line 106 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF

SMARTCARD end of block flag

Definition at line 107 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_FE USART_ISR_FE

SMARTCARD frame error

Definition at line 115 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE

SMARTCARD idle line detection

Definition at line 112 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_NE USART_ISR_NE

SMARTCARD noise error

Definition at line 114 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_ORE USART_ISR_ORE

SMARTCARD overrun error

Definition at line 113 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_PE USART_ISR_PE

SMARTCARD parity error

Definition at line 116 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_REACK USART_ISR_REACK

SMARTCARD receive enable acknowledge flag

Definition at line 104 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF

SMARTCARD receiver timeout flag

Definition at line 108 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE

SMARTCARD read data register not empty

Definition at line 111 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Receive().

#define SMARTCARD_FLAG_TC USART_ISR_TC

SMARTCARD transmission complete

Definition at line 110 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK

SMARTCARD transmit enable acknowledge flag

Definition at line 105 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXE USART_ISR_TXE

SMARTCARD transmit data register empty

Definition at line 109 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Interrupts Definition

Defines
SMARTCARD Interrupts Definition
SMARTCARD Extended Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | SMARTCARD_IT_PE ((uint16_t)0x0028)
#define | SMARTCARD_IT_TXE ((uint16_t)0x0727)
#define | SMARTCARD_IT_TC ((uint16_t)0x0626)
#define | SMARTCARD_IT_RXNE ((uint16_t)0x0525)
#define | SMARTCARD_IT_IDLE ((uint16_t)0x0424)
#define | SMARTCARD_IT_ERR ((uint16_t)0x0060)
#define | SMARTCARD_IT_ORE ((uint16_t)0x0300)
#define | SMARTCARD_IT_NE ((uint16_t)0x0200)
#define | SMARTCARD_IT_FE ((uint16_t)0x0100)
#define | SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
#define | SMARTCARD_IT_RTO ((uint16_t)0x0B3A)

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5 bits)
  • XX : Interrupt source register (2 bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5 bits)

Define Documentation

#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B)

SMARTCARD end of block interruption

Definition at line 142 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_IT_ERR ((uint16_t)0x0060)

SMARTCARD error interruption

Definition at line 137 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_Receive_IT().

#define SMARTCARD_IT_FE ((uint16_t)0x0100)

SMARTCARD frame error interruption

Definition at line 140 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_IT_IDLE ((uint16_t)0x0424)

SMARTCARD idle line detection interruption

Definition at line 135 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_NE ((uint16_t)0x0200)

SMARTCARD noise error interruption

Definition at line 139 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_IT_ORE ((uint16_t)0x0300)

SMARTCARD overrun error interruption

Definition at line 138 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_IT_PE ((uint16_t)0x0028)

SMARTCARD parity error interruption

Definition at line 131 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), and SMARTCARD_Receive_IT().

#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A)

SMARTCARD receiver timeout interruption

Definition at line 143 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)

SMARTCARD read data register not empty interruption

Definition at line 134 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), and SMARTCARD_Receive_IT().

#define SMARTCARD_IT_TC ((uint16_t)0x0626)

SMARTCARD transmission complete interruption

Definition at line 133 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXE ((uint16_t)0x0727)

SMARTCARD transmit data register empty interruption

Definition at line 132 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Transmit_IT().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMARTCARD Interruption Clear Flags

Defines
SMARTCARD Interruption Clear Flags
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NCF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

Define Documentation

#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

SMARTCARD end of block clear flag

Definition at line 165 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_FEF USART_ICR_FECF

SMARTCARD framing error clear flag

Definition at line 156 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF

SMARTCARD idle line detected clear flag

Definition at line 159 of file stm32l4xx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_NEF USART_ICR_NCF

SMARTCARD noise detected clear flag

Definition at line 157 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF

SMARTCARD overrun error clear flag

Definition at line 158 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_PEF USART_ICR_PECF

SMARTCARD parity error clear flag

Definition at line 155 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF

SMARTCARD receiver time out clear flag

Definition at line 164 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF

SMARTCARD transmission complete clear flag

Definition at line 160 of file stm32l4xx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit_DMA().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS Private Constants

Defines
SMBUS Private Constants
SMBUS

Defines

#define | TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */
#define | HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
#define | HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
#define | MAX_NBYTE_SIZE 255

Define Documentation

#define HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */

Definition at line 147 of file stm32l4xx_hal_smbus.c.

#define HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */

Definition at line 148 of file stm32l4xx_hal_smbus.c.

#define HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */

Definition at line 149 of file stm32l4xx_hal_smbus.c.

#define HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */

Definition at line 150 of file stm32l4xx_hal_smbus.c.

#define HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */

Definition at line 151 of file stm32l4xx_hal_smbus.c.

#define HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */

Definition at line 152 of file stm32l4xx_hal_smbus.c.

#define HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */

Definition at line 153 of file stm32l4xx_hal_smbus.c.

#define HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */

Definition at line 154 of file stm32l4xx_hal_smbus.c.

#define MAX_NBYTE_SIZE 255

Definition at line 155 of file stm32l4xx_hal_smbus.c.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */

Definition at line 146 of file stm32l4xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMBUS Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SMBUSx peripheral:

      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).

      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Bus Timeout
        (++) Analog Filer mode
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode
        (++) Packet Error Check mode
        (++) Peripheral mode

      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
          of the selected SMBUSx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS peripheral.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 329 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_MspDeInit(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_RESET, SMBUS_HandleTypeDef::Instance, SMBUS_HandleTypeDef::PreviousState, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Init ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 227 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, SMBUS_InitTypeDef::AddressingMode, SMBUS_InitTypeDef::AnalogFilter, assert_param, SMBUS_InitTypeDef::DualAddressMode, SMBUS_HandleTypeDef::ErrorCode, SMBUS_InitTypeDef::GeneralCallMode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_MspInit(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, SMBUS_HandleTypeDef::Init, SMBUS_HandleTypeDef::Instance, IS_SMBUS_ADDRESSING_MODE, IS_SMBUS_ANALOG_FILTER, IS_SMBUS_DUAL_ADDRESS, IS_SMBUS_GENERAL_CALL, IS_SMBUS_NO_STRETCH, IS_SMBUS_OWN_ADDRESS1, IS_SMBUS_OWN_ADDRESS2, IS_SMBUS_OWN_ADDRESS2_MASK, IS_SMBUS_PEC, IS_SMBUS_PERIPHERAL_MODE, SMBUS_HandleTypeDef::Lock, SMBUS_InitTypeDef::NoStretchMode, SMBUS_InitTypeDef::OwnAddress1, SMBUS_InitTypeDef::OwnAddress2, SMBUS_InitTypeDef::OwnAddress2Masks, SMBUS_InitTypeDef::PacketErrorCheckMode, SMBUS_InitTypeDef::PeripheralMode, SMBUS_HandleTypeDef::PreviousState, SMBUS_ADDRESSINGMODE_10BIT, SMBUS_ADDRESSINGMODE_7BIT, SMBUS_PEC_ENABLE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP, SMBUS_InitTypeDef::SMBusTimeout, SMBUS_HandleTypeDef::State, SMBUS_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_SMBUS_MspDeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS MSP.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 380 of file stm32l4xx_hal_smbus.c.

Referenced by HAL_SMBUS_DeInit().

void HAL_SMBUS_MspInit ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS MSP.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 364 of file stm32l4xx_hal_smbus.c.

Referenced by HAL_SMBUS_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Blocking mode Polling

Functions
Blocking mode Polling
Input and Output operation functions

Functions

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
Trials,: Number of trials
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 920 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_TIMEOUT, SMBUS_HandleTypeDef::Init, SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and SMBUS_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Non-Blocking mode Interrupt

Functions
Non-Blocking mode Interrupt
Input and Output operation functions

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 899 of file stm32l4xx_hal_smbus.c.

References SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 856 of file stm32l4xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 880 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 840 of file stm32l4xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
Return values:
HAL status

Definition at line 614 of file stm32l4xx_hal_smbus.c.

References SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 535 of file stm32l4xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 447 of file stm32l4xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 766 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 675 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
SMBUS Exported Functions | Input and Output operation functions

Functions

void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.

Function Documentation

void HAL_SMBUS_AddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
TransferDirection,: Master request Transfer Direction (Write/Read)
AddrMatchCode,: Address Match Code
Return values:
None

Definition at line 1244 of file stm32l4xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

void HAL_SMBUS_ER_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS error interrupt request.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1096 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, __HAL_SMBUS_GET_IT_SOURCE, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ERROR_ALERT, HAL_SMBUS_ERROR_ARLO, HAL_SMBUS_ERROR_BERR, HAL_SMBUS_ERROR_BUSTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ERROR_OVR, HAL_SMBUS_ERROR_PECERR, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::PreviousState, SMBUS_FLAG_ALERT, SMBUS_FLAG_ARLO, SMBUS_FLAG_BERR, SMBUS_FLAG_OVR, SMBUS_FLAG_PECERR, SMBUS_FLAG_TIMEOUT, SMBUS_IT_ERRI, and SMBUS_HandleTypeDef::State.

void HAL_SMBUS_ErrorCallback ( SMBUS_HandleTypeDef * hsmbus )

SMBUS error callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1278 of file stm32l4xx_hal_smbus.c.

Referenced by HAL_SMBUS_ER_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

void HAL_SMBUS_EV_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS event interrupt request.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1041 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_GET_IT_SOURCE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_CHECK_FLAG, SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_ISR_REG, SMBUS_IT_ADDRI, SMBUS_IT_NACKI, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TXI, SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_HandleTypeDef::State.

void HAL_SMBUS_ListenCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Listen Complete callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1262 of file stm32l4xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

void HAL_SMBUS_MasterRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Rx Transfer completed callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1195 of file stm32l4xx_hal_smbus.c.

Referenced by SMBUS_Master_ISR().

void HAL_SMBUS_MasterTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Tx Transfer completed callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1179 of file stm32l4xx_hal_smbus.c.

Referenced by SMBUS_Master_ISR().

void HAL_SMBUS_SlaveRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Rx Transfer completed callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1226 of file stm32l4xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

void HAL_SMBUS_SlaveTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Tx Transfer completed callback.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1210 of file stm32l4xx_hal_smbus.c.

Referenced by SMBUS_Slave_ISR().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMBUS Exported Functions | Input and Output operation functions

Peripheral State and Errors functions. More...

Functions

uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SMBUS_GetError ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS error code.

Parameters:
hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
SMBUS Error Code

Definition at line 1325 of file stm32l4xx_hal_smbus.c.

References SMBUS_HandleTypeDef::ErrorCode.

uint32_t HAL_SMBUS_GetState ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS handle state.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL state

Definition at line 1313 of file stm32l4xx_hal_smbus.c.

References SMBUS_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output operation functions

Modules | Functions
Input and Output operation functions
SMBUS Exported Functions

Data transfers functions. More...

Modules

Blocking mode Polling
Non-Blocking mode Interrupt
IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SMBUS data
    transfers.

    (#) Blocking mode function to check if device is ready for usage is :
        (++) HAL_SMBUS_IsDeviceReady()

    (#) There is only one mode of transfer:
       (++) No-Blocking mode : The communication is performed using Interrupts.
            These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated SMBUS IRQ when using Interrupt mode.

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_SMBUS_Master_Transmit_IT()
        (++) HAL_SMBUS_Master_Receive_IT()
        (++) HAL_SMBUS_Slave_Transmit_IT()
        (++) HAL_SMBUS_Slave_Receive_IT()
        (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
        (++) HAL_SMBUS_DisableListen_IT()
        (++) HAL_SMBUS_EnableAlert_IT()
        (++) HAL_SMBUS_DisableAlert_IT()

    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
        (++) HAL_SMBUS_MasterTxCpltCallback()
        (++) HAL_SMBUS_MasterRxCpltCallback()
        (++) HAL_SMBUS_SlaveTxCpltCallback()
        (++) HAL_SMBUS_SlaveRxCpltCallback()
        (++) HAL_SMBUS_AddrCallback()
        (++) HAL_SMBUS_ListenCpltCallback()
        (++) HAL_SMBUS_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 899 of file stm32l4xx_hal_smbus.c.

References SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 856 of file stm32l4xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 880 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 840 of file stm32l4xx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
Trials,: Number of trials
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 920 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_TIMEOUT, SMBUS_HandleTypeDef::Init, SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
Return values:
HAL status

Definition at line 614 of file stm32l4xx_hal_smbus.c.

References SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 535 of file stm32l4xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress,: Target device address
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 447 of file stm32l4xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 766 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
XferOptions,: Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 675 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMBUS_InitTypeDef Struct Reference
SMBUS Configuration Structure definition

#include <stm32l4xx_hal_smbus.h>

Data Fields

uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode
uint32_t | PacketErrorCheckMode
uint32_t | PeripheralMode
uint32_t | SMBusTimeout

Detailed Description

Definition at line 66 of file stm32l4xx_hal_smbus.h.

Field Documentation

uint32_t SMBUS_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode for master is selected. This parameter can be a value of SMBUS addressing mode

Definition at line 77 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

uint32_t SMBUS_InitTypeDef::AnalogFilter

Specifies if Analog Filter is enable or not. This parameter can be a value of SMBUS Analog Filter

Definition at line 71 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of SMBUS dual addressing mode

Definition at line 80 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of SMBUS general call addressing mode.

Definition at line 89 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of SMBUS nostretch mode

Definition at line 92 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 74 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 83 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2Masks

Specifies the acknoledge mask address second device own address if dual addressing mode is selected This parameter can be a value of SMBUS own address2 masks.

Definition at line 86 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PacketErrorCheckMode

Specifies if Packet Error Check mode is selected. This parameter can be a value of SMBUS packet error check mode

Definition at line 95 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PeripheralMode

Specifies which mode of Periphal is selected. This parameter can be a value of SMBUS peripheral mode

Definition at line 98 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::SMBusTimeout

Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. (Enable bits and different timeout values) This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 101 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::Timing

Specifies the SMBUS_TIMINGR_register value. This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 68 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_smbus.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HAL state definition

Defines
HAL state definition
SMBUS Exported Types

HAL State definition. More...

Defines

#define | HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000)
#define | HAL_SMBUS_STATE_READY ((uint32_t)0x00000001)
#define | HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042)
#define | HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003)
#define | HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004)
#define | HAL_SMBUS_STATE_LISTEN ((uint32_t)0x00000008)

Detailed Description

HAL State definition.

Define Documentation

#define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002)

SMBUS internal process is ongoing

Definition at line 116 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

#define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004)

Reception process is ongoing

Definition at line 122 of file stm32l4xx_hal_smbus.h.

#define HAL_SMBUS_STATE_LISTEN ((uint32_t)0x00000008)

Address Listen Mode is ongoing

Definition at line 123 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022)

Master Data Reception process is ongoing

Definition at line 118 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012)

Master Data Transmission process is ongoing

Definition at line 117 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001)

SMBUS initialized and ready for use

Definition at line 115 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000)

SMBUS not yet initialized or disabled

Definition at line 114 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), and HAL_SMBUS_Init().

#define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042)

Slave Data Reception process is ongoing

Definition at line 120 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032)

Slave Data Transmission process is ongoing

Definition at line 119 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003)

Timeout state

Definition at line 121 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS Error Code definition

Defines
SMBUS Error Code definition
SMBUS Exported Types

SMBUS Error Code definition. More...

Defines

#define | HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001)
#define | HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002)
#define | HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004)
#define | HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008)
#define | HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020)
#define | HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040)
#define | HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080)

Detailed Description

SMBUS Error Code definition.

Define Documentation

#define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004)

ACKF error

Definition at line 135 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040)

Alert error

Definition at line 139 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002)

ARLO error

Definition at line 134 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001)

BERR error

Definition at line 133 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020)

Bus Timeout error

Definition at line 138 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010)

Timeout error

Definition at line 137 of file stm32l4xx_hal_smbus.h.

#define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 132 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008)

OVR error

Definition at line 136 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080)

PEC error

Definition at line 140 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

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STM32L486xx HAL User Manual: SMBUS_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMBUS_HandleTypeDef Struct Reference
SMBUS handle Structure definition

#include <stm32l4xx_hal_smbus.h>

Data Fields

I2C_TypeDef * | Instance
SMBUS_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode

Detailed Description

Definition at line 149 of file stm32l4xx_hal_smbus.h.

Field Documentation

__IO uint32_t SMBUS_HandleTypeDef::ErrorCode

SMBUS Error code

Definition at line 169 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_GetError(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

SMBUS_InitTypeDef SMBUS_HandleTypeDef::Init

SMBUS communication parameters

Definition at line 153 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

I2C_TypeDef* SMBUS_HandleTypeDef::Instance

SMBUS registers base address

Definition at line 151 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_TransferConfig().

HAL_LockTypeDef SMBUS_HandleTypeDef::Lock

SMBUS locking object

Definition at line 165 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint8_t* SMBUS_HandleTypeDef::pBuffPtr

Pointer to SMBUS transfer buffer

Definition at line 155 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t SMBUS_HandleTypeDef::PreviousState

SMBUS communication Previous state

Definition at line 163 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

__IO uint32_t SMBUS_HandleTypeDef::State

SMBUS communication state

Definition at line 167 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_GetState(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

__IO uint16_t SMBUS_HandleTypeDef::XferCount

SMBUS transfer counter

Definition at line 159 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t SMBUS_HandleTypeDef::XferOptions

SMBUS transfer options

Definition at line 161 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

uint16_t SMBUS_HandleTypeDef::XferSize

SMBUS transfer size

Definition at line 157 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_smbus.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS Analog Filter

Defines
SMBUS Analog Filter
SMBUS Exported Constants

Defines

#define | SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 189 of file stm32l4xx_hal_smbus.h.

#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)

Definition at line 188 of file stm32l4xx_hal_smbus.h.

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STM32L486xx HAL User Manual: SMBUS addressing mode

Defines
SMBUS addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
#define | SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)

Define Documentation

#define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)

Definition at line 198 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)

Definition at line 197 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS dual addressing mode

Defines
SMBUS dual addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000)

Definition at line 207 of file stm32l4xx_hal_smbus.h.

#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 208 of file stm32l4xx_hal_smbus.h.

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STM32L486xx HAL User Manual: SMBUS own address2 masks

Defines
SMBUS own address2 masks
SMBUS Exported Constants

Defines

#define | SMBUS_OA2_NOMASK ((uint8_t)0x00)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07)

Define Documentation

#define SMBUS_OA2_MASK01 ((uint8_t)0x01)

Definition at line 218 of file stm32l4xx_hal_smbus.h.

#define SMBUS_OA2_MASK02 ((uint8_t)0x02)

Definition at line 219 of file stm32l4xx_hal_smbus.h.

#define SMBUS_OA2_MASK03 ((uint8_t)0x03)

Definition at line 220 of file stm32l4xx_hal_smbus.h.

#define SMBUS_OA2_MASK04 ((uint8_t)0x04)

Definition at line 221 of file stm32l4xx_hal_smbus.h.

#define SMBUS_OA2_MASK05 ((uint8_t)0x05)

Definition at line 222 of file stm32l4xx_hal_smbus.h.

#define SMBUS_OA2_MASK06 ((uint8_t)0x06)

Definition at line 223 of file stm32l4xx_hal_smbus.h.

#define SMBUS_OA2_MASK07 ((uint8_t)0x07)

Definition at line 224 of file stm32l4xx_hal_smbus.h.

#define SMBUS_OA2_NOMASK ((uint8_t)0x00)

Definition at line 217 of file stm32l4xx_hal_smbus.h.

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STM32L486xx HAL User Manual: SMBUS general call addressing mode

Defines
SMBUS general call addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000)

Definition at line 233 of file stm32l4xx_hal_smbus.h.

#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 234 of file stm32l4xx_hal_smbus.h.

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STM32L486xx HAL User Manual: SMBUS nostretch mode

Defines
SMBUS nostretch mode
SMBUS Exported Constants

Defines

#define | SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000)

Definition at line 242 of file stm32l4xx_hal_smbus.h.

#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 243 of file stm32l4xx_hal_smbus.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS packet error check mode

Defines
SMBUS packet error check mode
SMBUS Exported Constants

Defines

#define | SMBUS_PEC_DISABLE ((uint32_t)0x00000000)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN

Define Documentation

#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000)

Definition at line 251 of file stm32l4xx_hal_smbus.h.

#define SMBUS_PEC_ENABLE I2C_CR1_PECEN

Definition at line 252 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS peripheral mode

Defines
SMBUS peripheral mode
SMBUS Exported Constants

Defines

#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN)

Define Documentation

#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)

Definition at line 260 of file stm32l4xx_hal_smbus.h.

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000)

Definition at line 261 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN)

Definition at line 262 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS ReloadEndMode definition

Defines
SMBUS ReloadEndMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_SOFTEND_MODE ((uint32_t)0x00000000)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Define Documentation

#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 273 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 272 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Definition at line 274 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000)

Definition at line 271 of file stm32l4xx_hal_smbus.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS StartStopMode definition

Defines
SMBUS StartStopMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_NO_STARTSTOP ((uint32_t)0x00000000)
#define | SMBUS_GENERATE_STOP I2C_CR2_STOP
#define | SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE I2C_CR2_START

Define Documentation

#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 285 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT().

#define SMBUS_GENERATE_START_WRITE I2C_CR2_START

Definition at line 286 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT().

#define SMBUS_GENERATE_STOP I2C_CR2_STOP

Definition at line 284 of file stm32l4xx_hal_smbus.h.

#define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000)

Definition at line 283 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS XferOptions definition

Defines
SMBUS XferOptions definition
SMBUS Exported Constants

Defines

#define | SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE))
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Define Documentation

#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 297 of file stm32l4xx_hal_smbus.h.

#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 299 of file stm32l4xx_hal_smbus.h.

#define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE))

Definition at line 295 of file stm32l4xx_hal_smbus.h.

#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 298 of file stm32l4xx_hal_smbus.h.

#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 300 of file stm32l4xx_hal_smbus.h.

#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))

Definition at line 296 of file stm32l4xx_hal_smbus.h.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS Interrupt configuration definition

Defines
SMBUS Interrupt configuration definition
SMBUS Exported Constants

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define | SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Detailed Description

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Definition at line 321 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 315 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)

Definition at line 320 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_ERRI I2C_CR1_ERRIE

Definition at line 311 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_NACKI I2C_CR1_NACKIE

Definition at line 314 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)

Definition at line 319 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_RXI I2C_CR1_RXIE

Definition at line 316 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_STOPI I2C_CR1_STOPIE

Definition at line 313 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TCI I2C_CR1_TCIE

Definition at line 312 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)

Definition at line 318 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_TXI I2C_CR1_TXIE

Definition at line 317 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS Flag definition

Defines
SMBUS Flag definition
SMBUS Exported Constants

Flag definition Elements values convention: 0xXXXXYYYY. More...

Defines

#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR

Detailed Description

Flag definition Elements values convention: 0xXXXXYYYY.

  • XXXXXXXX : Flag mask

Define Documentation

#define SMBUS_FLAG_ADDR I2C_ISR_ADDR

Definition at line 336 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_AF I2C_ISR_NACKF

Definition at line 337 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_ALERT I2C_ISR_ALERT

Definition at line 346 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), and HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_ARLO I2C_ISR_ARLO

Definition at line 342 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_BERR I2C_ISR_BERR

Definition at line 341 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_BUSY I2C_ISR_BUSY

Definition at line 347 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_FLAG_DIR I2C_ISR_DIR

Definition at line 348 of file stm32l4xx_hal_smbus.h.

#define SMBUS_FLAG_OVR I2C_ISR_OVR

Definition at line 343 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_PECERR I2C_ISR_PECERR

Definition at line 344 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_RXNE I2C_ISR_RXNE

Definition at line 335 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_STOPF I2C_ISR_STOPF

Definition at line 338 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TC I2C_ISR_TC

Definition at line 339 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), and SMBUS_Master_ISR().

#define SMBUS_FLAG_TCR I2C_ISR_TCR

Definition at line 340 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 345 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler().

#define SMBUS_FLAG_TXE I2C_ISR_TXE

Definition at line 333 of file stm32l4xx_hal_smbus.h.

#define SMBUS_FLAG_TXIS I2C_ISR_TXIS

Definition at line 334 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS Exported Macros

Defines
SMBUS Exported Macros
SMBUS

Defines

#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Define Documentation

#define __HAL_SMBUS_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • SMBUS_FLAG_ADDR: Address matched (slave mode)
  • SMBUS_FLAG_AF: NACK received flag
  • SMBUS_FLAG_STOPF: STOP detection flag
  • SMBUS_FLAG_BERR: Bus error
  • SMBUS_FLAG_ARLO: Arbitration lost
  • SMBUS_FLAG_OVR: Overrun/Underrun
  • SMBUS_FLAG_PECERR: PEC error in reception
  • SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT: SMBus alert
Return values:
None

Definition at line 458 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified SMBUS peripheral.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
Return values:
None

Definition at line 470 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified SMBUS interrupts.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
__INTERRUPT__,: specifies the interrupt source to disable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI: Errors interrupt enable
  • SMBUS_IT_TCI: Transfer complete interrupt enable
  • SMBUS_IT_STOPI: STOP detection interrupt enable
  • SMBUS_IT_NACKI: NACK received interrupt enable
  • SMBUS_IT_ADDRI: Address match interrupt enable
  • SMBUS_IT_RXI: RX interrupt enable
  • SMBUS_IT_TXI: TX interrupt enable
Return values:
None

Definition at line 398 of file stm32l4xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified SMBUS peripheral.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
Return values:
None

Definition at line 464 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified SMBUS interrupts.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
__INTERRUPT__,: specifies the interrupt source to enable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI: Errors interrupt enable
  • SMBUS_IT_TCI: Transfer complete interrupt enable
  • SMBUS_IT_STOPI: STOP detection interrupt enable
  • SMBUS_IT_NACKI: NACK received interrupt enable
  • SMBUS_IT_ADDRI: Address match interrupt enable
  • SMBUS_IT_RXI: RX interrupt enable
  • SMBUS_IT_TXI: TX interrupt enable
Return values:
None

Definition at line 382 of file stm32l4xx_hal_smbus.h.

Referenced by SMBUS_Enable_IRQ().

#define __HAL_SMBUS_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
Return values:
None

Definition at line 476 of file stm32l4xx_hal_smbus.h.

#define __HAL_SMBUS_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))

Definition at line 440 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define __HAL_SMBUS_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SMBUS interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
__INTERRUPT__,: specifies the SMBUS interrupt source to check. This parameter can be one of the following values:
  • SMBUS_IT_ERRI: Errors interrupt enable
  • SMBUS_IT_TCI: Transfer complete interrupt enable
  • SMBUS_IT_STOPI: STOP detection interrupt enable
  • SMBUS_IT_NACKI: NACK received interrupt enable
  • SMBUS_IT_ADDRI: Address match interrupt enable
  • SMBUS_IT_RXI: RX interrupt enable
  • SMBUS_IT_TXI: TX interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 414 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_ER_IRQHandler(), and HAL_SMBUS_EV_IRQHandler().

#define __HAL_SMBUS_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)

Reset SMBUS handle state.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
Return values:
None

Definition at line 366 of file stm32l4xx_hal_smbus.h.

#define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF)

Check whether the specified SMBUS flag is set or not.

Parameters:
__HANDLE__,: specifies the SMBUS Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SMBUS_FLAG_TXE: Transmit data register empty
  • SMBUS_FLAG_TXIS: Transmit interrupt status
  • SMBUS_FLAG_RXNE: Receive data register not empty
  • SMBUS_FLAG_ADDR: Address matched (slave mode)
  • SMBUS_FLAG_AF: NACK received flag
  • SMBUS_FLAG_STOPF: STOP detection flag
  • SMBUS_FLAG_TC: Transfer complete (master mode)
  • SMBUS_FLAG_TCR: Transfer complete reload
  • SMBUS_FLAG_BERR: Bus error
  • SMBUS_FLAG_ARLO: Arbitration lost
  • SMBUS_FLAG_OVR: Overrun/Underrun
  • SMBUS_FLAG_PECERR: PEC error in reception
  • SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT: SMBus alert
  • SMBUS_FLAG_BUSY: Bus busy
  • SMBUS_FLAG_DIR: Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 439 of file stm32l4xx_hal_smbus.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS Private Macros

Defines
SMBUS Private Macros
SMBUS

Defines

#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define | SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)

Define Documentation

#define IS_SMBUS_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))

Definition at line 493 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))

Definition at line 490 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))

Definition at line 496 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_GENERAL_CALL ( CALL )
Value:
(((CALL) == SMBUS_GENERALCALL_DISABLE) || \
                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))

Definition at line 508 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))

Definition at line 511 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= (uint32_t)0x000003FF)

Definition at line 558 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FF)

Definition at line 559 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == SMBUS_OA2_NOMASK)    || \
                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
                                                         ((MASK) == SMBUS_OA2_MASK07))

Definition at line 499 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PEC ( PEC )
Value:
(((PEC) == SMBUS_PEC_DISABLE) || \
                                                          ((PEC) == SMBUS_PEC_ENABLE))

Definition at line 514 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PERIPHERAL_MODE ( MODE )
Value:
(((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))

Definition at line 517 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == SMBUS_RELOAD_MODE)                           || \
                                                          ((MODE) == SMBUS_AUTOEND_MODE)                         || \
                                                          ((MODE) == SMBUS_SOFTEND_MODE)                         || \
                                                          ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))

Definition at line 521 of file stm32l4xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_FIRST_FRAME)                        || \
                                                          ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
                                                          ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))

Definition at line 536 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define IS_SMBUS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_GENERATE_STOP)              || \
                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))

Definition at line 530 of file stm32l4xx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define SMBUS_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) | ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))

Definition at line 556 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define SMBUS_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                                  (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 546 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)

Definition at line 549 of file stm32l4xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_ALERT_ENABLED ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)

Definition at line 553 of file stm32l4xx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ().

#define SMBUS_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)

Definition at line 550 of file stm32l4xx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_ISR_REG ( __HANDLE__ ) ((__HANDLE__)->Instance->ISR)

Definition at line 555 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define SMBUS_GET_PEC_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)

Definition at line 552 of file stm32l4xx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 551 of file stm32l4xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR().

#define SMBUS_RESET_CR1 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))

Definition at line 543 of file stm32l4xx_hal_smbus.h.

#define SMBUS_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 544 of file stm32l4xx_hal_smbus.h.

Referenced by SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SMBUS Private Functions

Functions
SMBUS Private Functions
SMBUS

Data transfers Private functions. More...

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static HAL_StatusTypeDef | SMBUS_Enable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Disable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Master_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_TransferConfig (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Detailed Description

Data transfers Private functions.

Function Documentation

static HAL_StatusTypeDef SMBUS_Disable_IRQ | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hsmbus | : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | : Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 1792 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_DISABLE_IT, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_GET_ALERT_ENABLED, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, SMBUS_IT_TXI, and SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static HAL_StatusTypeDef SMBUS_Enable_IRQ | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hsmbus | : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | : Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 1750 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_ENABLE_IT, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, and SMBUS_IT_TXI.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static HAL_StatusTypeDef SMBUS_Master_ISR ( SMBUS_HandleTypeDef * hsmbus ) [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1349 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __HAL_SMBUS_GET_FLAG, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::Instance, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Disable_IRQ(), SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_PEC_MODE, SMBUS_GET_STOP_MODE, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static HAL_StatusTypeDef SMBUS_Slave_ISR ( SMBUS_HandleTypeDef * hsmbus ) [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1546 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE_IT, __HAL_SMBUS_GET_FLAG, SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, SMBUS_HandleTypeDef::Instance, MAX_NBYTE_SIZE, SMBUS_HandleTypeDef::pBuffPtr, SMBUS_HandleTypeDef::PreviousState, SMBUS_Disable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_ADDR_MATCH, SMBUS_GET_DIR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), SMBUS_HandleTypeDef::State, SMBUS_HandleTypeDef::XferCount, SMBUS_HandleTypeDef::XferOptions, and SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static void SMBUS_TransferConfig | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hsmbus,: SMBUS handle.
DevAddress,: specifies the slave address to be programmed.
Size,: specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode,: new state of the SMBUS START condition generation. This parameter can be one or a combination of the following values:
  • SMBUS_NO_MODE: No specific mode enabled.
  • SMBUS_RELOAD_MODE: Enable Reload mode.
  • SMBUS_AUTOEND_MODE: Enable Automatic end mode.
  • SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
Request,: new state of the SMBUS START condition generation. This parameter can be one of the following values:
  • SMBUS_NO_STARTSTOP: Don't Generate stop and start condition.
  • SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
  • SMBUS_GENERATE_START_READ: Generate Restart for read request.
  • SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
Return values:
None

Definition at line 1936 of file stm32l4xx_hal_smbus.c.

References assert_param, SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_MODE, and IS_SMBUS_TRANSFER_REQUEST.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMBUS Communication Timeout.

Parameters:
hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Flag,: specifies the SMBUS flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1868 of file stm32l4xx_hal_smbus.c.

References __HAL_SMBUS_GET_FLAG, HAL_GetTick(), HAL_SMBUS_STATE_READY, SMBUS_HandleTypeDef::PreviousState, and SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_IsDeviceReady().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_DEFAULT_TIMEOUT 50

Define Documentation

#define SPI_DEFAULT_TIMEOUT 50

Definition at line 105 of file stm32l4xx_hal_spi.c.

Referenced by SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Private Functions

Functions
SPI Private Functions
SPI

Private functions. More...

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout)
Handle the check of the RXTX or TX transaction complete.

Detailed Description

Private functions.

Function Documentation

static void SPI_2linesRxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2254 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_16BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2285 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), and SPI_IT_RXNE.

Referenced by SPI_2linesRxISR_16BIT().

static void SPI_2linesRxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2142 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_8BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_RXNE, SPI_RXFIFO_THRESHOLD, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2189 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by SPI_2linesRxISR_8BIT().

static void SPI_2linesTxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2303 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2215 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_CloseRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2688 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, SPI_DEFAULT_TIMEOUT, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::State.

Referenced by SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), and SPI_RxISR_8BITCRC().

static void SPI_CloseRxTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RXTX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2640 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, and __SPI_HandleTypeDef::State.

Referenced by SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), and SPI_2linesTxISR_8BIT().

static void SPI_CloseTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the TX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2726 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_IT_ERR, SPI_IT_TXE, and __SPI_HandleTypeDef::State.

Referenced by SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

static void SPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication error callback.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2124 of file stm32l4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_DMA, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2098 of file stm32l4xx_hal_spi.c.

References HAL_SPI_RxHalfCpltCallback().

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit process complete callback.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2085 of file stm32l4xx_hal_spi.c.

References HAL_SPI_TxHalfCpltCallback().

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit receive process complete callback.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2111 of file stm32l4xx_hal_spi.c.

References HAL_SPI_TxRxHalfCpltCallback().

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1944 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1905 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit receive process complete callback.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2018 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_8BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_FRLVL_QUARTER_FULL, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_DMA().

static HAL_StatusTypeDef SPI_EndRxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle the check of the RX transaction complete.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Timeout : Timeout duration
Return values:
None

Definition at line 2585 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_MODE_MASTER, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Receive(), SPI_CloseRx_ISR(), and SPI_DMAReceiveCplt().

static HAL_StatusTypeDef SPI_EndRxTxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle the check of the RXTX or TX transaction complete.

Parameters:
hspi,: SPI handle
Timeout : Timeout duration

Definition at line 2617 of file stm32l4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, SPI_FLAG_BSY, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

static void SPI_RxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the 16-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2399 of file stm32l4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_16BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2380 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRx_ISR(), SPI_IT_ERR, and SPI_IT_RXNE.

Referenced by SPI_RxISR_16BIT().

static void SPI_RxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the receive 8-bit in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2352 of file stm32l4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_8BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 8-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2333 of file stm32l4xx_hal_spi.c.

References __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, and SPI_CloseRx_ISR().

Referenced by SPI_RxISR_8BIT().

static void SPI_TxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 16-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2451 of file stm32l4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static void SPI_TxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 8-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2428 of file stm32l4xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Fifo,
 |  | uint32_t | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SPI FIFO Communication Timeout.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Fifo | : Fifo to check
State | : Fifo state to check
Timeout | : Timeout duration
Return values:
HAL status

Definition at line 2529 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FRLVL_EMPTY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Flag,
 |  | uint32_t | State,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SPI Communication Timeout.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Flag | : SPI flag to check
State | : flag state to check
Timeout | : Timeout duration
Return values:
HAL status

Definition at line 2478 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_DMAReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
DeInitialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
DeInitialize the SPI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SPIx peripheral:

      (+) User must implement HAL_SPI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SPI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Direction
        (++) Data Size
        (++) Clock Polarity and Phase
        (++) NSS Management
        (++) BaudRate Prescaler
        (++) FirstBit
        (++) TIMode
        (++) CRC Calculation
        (++) CRC Polynomial if CRC enabled
        (++) CRC Length, used only with Data8 and Data16
        (++) FIFO reception threshold

      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
          of the selected SPIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DeInit ( SPI_HandleTypeDef * hspi )

DeInitialize the SPI peripheral.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 298 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_MspDeInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPI_Init ( SPI_HandleTypeDef * hspi )

Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 194 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, SPI_InitTypeDef::BaudRatePrescaler, SPI_InitTypeDef::CLKPhase, SPI_InitTypeDef::CLKPolarity, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::CRCPolynomial, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FirstBit, HAL_SPI_ERROR_NONE, HAL_SPI_MspInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_CALCULATION, IS_SPI_CRC_LENGTH, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, IS_SPI_NSSP, IS_SPI_TIMODE, __SPI_HandleTypeDef::Lock, SPI_InitTypeDef::Mode, SPI_InitTypeDef::NSS, SPI_InitTypeDef::NSSPMode, SPI_CRC_LENGTH_16BIT, SPI_CRC_LENGTH_8BIT, SPI_CRC_LENGTH_DATASIZE, SPI_CRCCALCULATION_DISABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_RXFIFO_THRESHOLD_HF, SPI_RXFIFO_THRESHOLD_QF, __SPI_HandleTypeDef::State, and SPI_InitTypeDef::TIMode.

void HAL_SPI_MspDeInit ( SPI_HandleTypeDef * hspi )

DeInitialize the SPI MSP.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 346 of file stm32l4xx_hal_spi.c.

Referenced by HAL_SPI_DeInit().

void HAL_SPI_MspInit ( SPI_HandleTypeDef * hspi )

Initialize the SPI MSP.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 330 of file stm32l4xx_hal_spi.c.

Referenced by HAL_SPI_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SPI
    data transfers.

    [..] The SPI supports master and slave mode :

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These APIs return the HAL status.
           The end of the data processing will be indicated through the
           dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected

    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
        exist for 1Line (simplex) and 2Lines (full duplex) modes.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DMAPause ( SPI_HandleTypeDef * hspi )

Pause the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1599 of file stm32l4xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAResume ( SPI_HandleTypeDef * hspi )

Resume the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1619 of file stm32l4xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAStop ( SPI_HandleTypeDef * hspi )

Stop the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1639 of file stm32l4xx_hal_spi.c.

References HAL_DMA_Abort(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

void HAL_SPI_ErrorCallback ( SPI_HandleTypeDef * hspi )

SPI error callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1830 of file stm32l4xx_hal_spi.c.

Referenced by HAL_SPI_IRQHandler(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_IRQHandler ( SPI_HandleTypeDef * hspi )

Handle SPI interrupt request.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
None

Definition at line 1670 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FRE, HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_OVR, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, SPI_FLAG_FRE, SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxISR.

HAL_StatusTypeDef HAL_SPI_Receive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 549 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Receive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Note:
When the CRC feature is enabled the pData Length must be Size + 1.
Parameters:
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1349 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_ENABLE, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_DMA(), __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAReceiveCplt(), SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Receive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1054 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_IT(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

void HAL_SPI_RxCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1750 of file stm32l4xx_hal_spi.c.

Referenced by SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void HAL_SPI_RxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1798 of file stm32l4xx_hal_spi.c.

Referenced by SPI_DMAHalfReceiveCplt().

HAL_StatusTypeDef HAL_SPI_Transmit | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 402 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FLAG_TXE, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Transmit_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1254 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, DMA_InitTypeDef::MemDataAlignment, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DMAError(), SPI_DMAHalfTransmitCplt(), SPI_DMATransmitCplt(), SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Transmit_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 977 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_IT_TXE, SPI_RESET_CRC, SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_TransmitReceive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size,: amount of data to be sent and received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 760 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Note:
When the CRC feature is enabled the pRxData Length must be Size + 1
Parameters:
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1456 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAHalfTransmitReceiveCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size,: amount of data to be sent and received
Return values:
HAL status

Definition at line 1156 of file stm32l4xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive_IT().

void HAL_SPI_TxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1734 of file stm32l4xx_hal_spi.c.

Referenced by SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void HAL_SPI_TxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1782 of file stm32l4xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitCplt().

void HAL_SPI_TxRxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1766 of file stm32l4xx_hal_spi.c.

Referenced by SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_TxRxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Half Transfer callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 1814 of file stm32l4xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitReceiveCplt().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPI Exported Functions

SPI control functions. More...

Functions

HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI control functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SPI.
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication

Function Documentation

uint32_t HAL_SPI_GetError ( SPI_HandleTypeDef * hspi )

Return the SPI error code.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI error code in bitmap format

Definition at line 1880 of file stm32l4xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode.

HAL_SPI_StateTypeDef HAL_SPI_GetState ( SPI_HandleTypeDef * hspi )

Return the SPI handle state.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI state

Definition at line 1868 of file stm32l4xx_hal_spi.c.

References __SPI_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Exported Types

Data Structures | Typedefs | Enumerations
SPI Exported Types
SPI

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00, HAL_SPI_STATE_READY = 0x01, HAL_SPI_STATE_BUSY = 0x02, HAL_SPI_STATE_BUSY_TX = 0x03,
HAL_SPI_STATE_BUSY_RX = 0x04, HAL_SPI_STATE_BUSY_TX_RX = 0x05, HAL_SPI_STATE_ERROR = 0x06
}
HAL State structures definition. More...

Typedef Documentation

typedef struct __SPI_HandleTypeDef SPI_HandleTypeDef

SPI handle Structure definition.

Enumeration Type Documentation

enum HAL_SPI_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SPI_STATE_RESET

Peripheral not Initialized

HAL_SPI_STATE_READY

Peripheral Initialized and ready for use

HAL_SPI_STATE_BUSY

an internal process is ongoing

HAL_SPI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SPI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SPI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SPI_STATE_ERROR

SPI error state

Definition at line 119 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPI_InitTypeDef Struct Reference
SPI Exported Types

SPI Configuration Structure definition. More...

#include <stm32l4xx_hal_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Direction
uint32_t | DataSize
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | NSS
uint32_t | BaudRatePrescaler
uint32_t | FirstBit
uint32_t | TIMode
uint32_t | CRCCalculation
uint32_t | CRCPolynomial
uint32_t | CRCLength
uint32_t | NSSPMode

Detailed Description

SPI Configuration Structure definition.

Definition at line 65 of file stm32l4xx_hal_spi.h.

Field Documentation

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 86 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 79 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 76 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 98 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::CRCLength

Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size This parameter can be a value of SPI CRC Length

Definition at line 104 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0 and Max_Data = 65535

Definition at line 101 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 73 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI bidirectional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 70 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB transmission

Definition at line 92 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 67 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select management

Definition at line 82 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::NSSPMode

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of SPI NSS Pulse Mode This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored)..

Definition at line 108 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not . This parameter can be a value of SPI TI mode

Definition at line 95 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_spi.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: __SPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPI_HandleTypeDef Struct Reference
SPI Exported Types

SPI handle Structure definition. More...

#include <stm32l4xx_hal_spi.h>

Data Fields

SPI_TypeDef * | Instance
SPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
uint32_t | CRCSize
void(* | RxISR )(struct __SPI_HandleTypeDef *hspi)
void(* | TxISR )(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SPI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SPI handle Structure definition.

Definition at line 133 of file stm32l4xx_hal_spi.h.

Field Documentation

uint32_t __SPI_HandleTypeDef::CRCSize

SPI CRC size used for the transfer

Definition at line 151 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BITCRC(), and SPI_RxISR_8BITCRC().

__IO uint32_t __SPI_HandleTypeDef::ErrorCode

SPI Error code

Definition at line 165 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_GetError(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmarx

SPI Rx DMA Handle parameters

Definition at line 159 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_DMAStop(), HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmatx

SPI Tx DMA Handle parameters

Definition at line 157 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_DMAStop(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

SPI_InitTypeDef __SPI_HandleTypeDef::Init

SPI communication parameters

Definition at line 137 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

SPI_TypeDef* __SPI_HandleTypeDef::Instance

SPI registers base address

Definition at line 135 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_FlushRxFifo(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), SPI_RxISR_8BITCRC(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

HAL_LockTypeDef __SPI_HandleTypeDef::Lock

Locking object

Definition at line 161 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint8_t* __SPI_HandleTypeDef::pRxBuffPtr

Pointer to SPI Rx transfer Buffer

Definition at line 145 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint8_t* __SPI_HandleTypeDef::pTxBuffPtr

Pointer to SPI Tx transfer Buffer

Definition at line 139 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

void(* __SPI_HandleTypeDef::RxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Rx IRQ handler

Definition at line 153 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferCount

SPI Rx Transfer Counter

Definition at line 149 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferSize

SPI Rx Transfer size

Definition at line 147 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO HAL_SPI_StateTypeDef __SPI_HandleTypeDef::State

SPI communication state

Definition at line 163 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetState(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

void(* __SPI_HandleTypeDef::TxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Tx IRQ handler

Definition at line 155 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

uint16_t __SPI_HandleTypeDef::TxXferCount

SPI Tx Transfer Counter

Definition at line 143 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

uint16_t __SPI_HandleTypeDef::TxXferSize

SPI Tx Transfer size

Definition at line 141 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_spi.h
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Error Code

Defines
SPI Error Code
SPI Exported Constants

Defines

#define | HAL_SPI_ERROR_NONE (uint32_t)0x00000000
#define | HAL_SPI_ERROR_MODF (uint32_t)0x00000001
#define | HAL_SPI_ERROR_CRC (uint32_t)0x00000002
#define | HAL_SPI_ERROR_OVR (uint32_t)0x00000004
#define | HAL_SPI_ERROR_FRE (uint32_t)0x00000008
#define | HAL_SPI_ERROR_DMA (uint32_t)0x00000010
#define | HAL_SPI_ERROR_FLAG (uint32_t)0x00000020
#define | HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040

Define Documentation

#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002

CRC error

Definition at line 184 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010

DMA transfer error

Definition at line 187 of file stm32l4xx_hal_spi.h.

Referenced by SPI_DMAError().

#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020

Error on BSY/TXE/FTLVL/FRLVL Flag

Definition at line 188 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008

FRE error

Definition at line 186 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001

MODF error

Definition at line 183 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000

No error

Definition at line 182 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004

OVR error

Definition at line 185 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040

Unknown error

Definition at line 189 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Mode

Defines
SPI Mode
SPI Exported Constants

Defines

#define | SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Define Documentation

#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Definition at line 199 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_MODE_SLAVE ((uint32_t)0x00000000)

Definition at line 198 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Direction Mode

Defines
SPI Direction Mode
SPI Exported Constants

Defines

#define | SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Define Documentation

#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Definition at line 209 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)

Definition at line 207 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY

Definition at line 208 of file stm32l4xx_hal_spi.h.

Referenced by SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Data Size

Defines
SPI Data Size
SPI Exported Constants

Defines

#define | SPI_DATASIZE_4BIT ((uint32_t)0x0300)
#define | SPI_DATASIZE_5BIT ((uint32_t)0x0400)
#define | SPI_DATASIZE_6BIT ((uint32_t)0x0500)
#define | SPI_DATASIZE_7BIT ((uint32_t)0x0600)
#define | SPI_DATASIZE_8BIT ((uint32_t)0x0700)
#define | SPI_DATASIZE_9BIT ((uint32_t)0x0800)
#define | SPI_DATASIZE_10BIT ((uint32_t)0x0900)
#define | SPI_DATASIZE_11BIT ((uint32_t)0x0A00)
#define | SPI_DATASIZE_12BIT ((uint32_t)0x0B00)
#define | SPI_DATASIZE_13BIT ((uint32_t)0x0C00)
#define | SPI_DATASIZE_14BIT ((uint32_t)0x0D00)
#define | SPI_DATASIZE_15BIT ((uint32_t)0x0E00)
#define | SPI_DATASIZE_16BIT ((uint32_t)0x0F00)

Define Documentation

#define SPI_DATASIZE_10BIT ((uint32_t)0x0900)

Definition at line 223 of file stm32l4xx_hal_spi.h.

#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00)

Definition at line 224 of file stm32l4xx_hal_spi.h.

#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00)

Definition at line 225 of file stm32l4xx_hal_spi.h.

#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00)

Definition at line 226 of file stm32l4xx_hal_spi.h.

#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00)

Definition at line 227 of file stm32l4xx_hal_spi.h.

#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00)

Definition at line 228 of file stm32l4xx_hal_spi.h.

#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00)

Definition at line 229 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), and HAL_SPI_TransmitReceive().

#define SPI_DATASIZE_4BIT ((uint32_t)0x0300)

Definition at line 217 of file stm32l4xx_hal_spi.h.

#define SPI_DATASIZE_5BIT ((uint32_t)0x0400)

Definition at line 218 of file stm32l4xx_hal_spi.h.

#define SPI_DATASIZE_6BIT ((uint32_t)0x0500)

Definition at line 219 of file stm32l4xx_hal_spi.h.

#define SPI_DATASIZE_7BIT ((uint32_t)0x0600)

Definition at line 220 of file stm32l4xx_hal_spi.h.

#define SPI_DATASIZE_8BIT ((uint32_t)0x0700)

Definition at line 221 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_DATASIZE_9BIT ((uint32_t)0x0800)

Definition at line 222 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Clock Polarity

Defines
SPI Clock Polarity
SPI Exported Constants

Defines

#define | SPI_POLARITY_LOW ((uint32_t)0x00000000)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL

Define Documentation

#define SPI_POLARITY_HIGH SPI_CR1_CPOL

Definition at line 238 of file stm32l4xx_hal_spi.h.

#define SPI_POLARITY_LOW ((uint32_t)0x00000000)

Definition at line 237 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Clock Phase

Defines
SPI Clock Phase
SPI Exported Constants

Defines

#define | SPI_PHASE_1EDGE ((uint32_t)0x00000000)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA

Define Documentation

#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)

Definition at line 246 of file stm32l4xx_hal_spi.h.

#define SPI_PHASE_2EDGE SPI_CR1_CPHA

Definition at line 247 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Slave Select management

Defines
SPI Slave Select management
SPI Exported Constants

Defines

#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
#define | SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)

Define Documentation

#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)

Definition at line 256 of file stm32l4xx_hal_spi.h.

#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)

Definition at line 257 of file stm32l4xx_hal_spi.h.

#define SPI_NSS_SOFT SPI_CR1_SSM

Definition at line 255 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI NSS Pulse Mode

Defines
SPI NSS Pulse Mode
SPI Exported Constants

Defines

#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)

Define Documentation

#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)

Definition at line 266 of file stm32l4xx_hal_spi.h.

#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP

Definition at line 265 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI BaudRate Prescaler

Defines
SPI BaudRate Prescaler
SPI Exported Constants

Defines

#define | SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
#define | SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
#define | SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
#define | SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
#define | SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
#define | SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
#define | SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
#define | SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)

Define Documentation

#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)

Definition at line 280 of file stm32l4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)

Definition at line 277 of file stm32l4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)

Definition at line 274 of file stm32l4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)

Definition at line 281 of file stm32l4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)

Definition at line 278 of file stm32l4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)

Definition at line 275 of file stm32l4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)

Definition at line 279 of file stm32l4xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)

Definition at line 276 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI MSB LSB transmission

Defines
SPI MSB LSB transmission
SPI Exported Constants

Defines

#define | SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Define Documentation

#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Definition at line 290 of file stm32l4xx_hal_spi.h.

#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)

Definition at line 289 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI TI mode

Defines
SPI TI mode
SPI Exported Constants

Defines

#define | SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF

Define Documentation

#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)

Definition at line 298 of file stm32l4xx_hal_spi.h.

#define SPI_TIMODE_ENABLE SPI_CR2_FRF

Definition at line 299 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI CRC Calculation

Defines
SPI CRC Calculation
SPI Exported Constants

Defines

#define | SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Define Documentation

#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)

Definition at line 307 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Definition at line 308 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI CRC Length

Defines
SPI CRC Length
SPI Exported Constants

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit. More...

Defines

#define | SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)
#define | SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)
#define | SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)

Detailed Description

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

Define Documentation

#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)

Definition at line 322 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), and SPI_DMAReceiveCplt().

#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)

Definition at line 321 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init(), and SPI_DMATransmitReceiveCplt().

#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)

Definition at line 320 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI FIFO Reception Threshold

Defines
SPI FIFO Reception Threshold
SPI Exported Constants

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/2(16-bits). More...

Defines

#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)

Detailed Description

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/2(16-bits).

SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO level is greater or equal to 1/4(8 bits).

Define Documentation

#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH

Definition at line 335 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), and SPI_2linesRxISR_8BIT().

#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)

Definition at line 337 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH

Definition at line 336 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Interrupt configuration definition

Defines
SPI Interrupt configuration definition
SPI Exported Constants

SPI Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE

Detailed Description

SPI Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define SPI_IT_ERR SPI_CR2_ERRIE

Definition at line 351 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_RXNE SPI_CR2_RXNEIE

Definition at line 350 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_TXE SPI_CR2_TXEIE

Definition at line 349 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Flag definition

Defines
SPI Flag definition
SPI Exported Constants

Flag definition Elements values convention: 0xXXXXYYYY. More...

Defines

#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */

Detailed Description

Flag definition Elements values convention: 0xXXXXYYYY.

  • XXXX : Flag register Index
  • YYYY : Flag mask

Define Documentation

#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */

Definition at line 366 of file stm32l4xx_hal_spi.h.

Referenced by SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */

Definition at line 367 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */

Definition at line 370 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */

Definition at line 372 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPIEx_FlushRxFifo(), SPI_DMATransmitReceiveCplt(), and SPI_EndRxTransaction().

#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */

Definition at line 371 of file stm32l4xx_hal_spi.h.

Referenced by SPI_EndRxTxTransaction().

#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */

Definition at line 368 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */

Definition at line 369 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */

Definition at line 364 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), and SPI_DMAReceiveCplt().

#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */

Definition at line 365 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Transmission FIFO Status Level

Defines
SPI Transmission FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FTLVL_EMPTY ((uint32_t)0x0000)
#define | SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
#define | SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
#define | SPI_FTLVL_FULL ((uint32_t)0x1800)

Define Documentation

#define SPI_FTLVL_EMPTY ((uint32_t)0x0000)

Definition at line 380 of file stm32l4xx_hal_spi.h.

Referenced by SPI_EndRxTxTransaction().

#define SPI_FTLVL_FULL ((uint32_t)0x1800)

Definition at line 383 of file stm32l4xx_hal_spi.h.

#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)

Definition at line 382 of file stm32l4xx_hal_spi.h.

#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)

Definition at line 381 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Reception FIFO Status Level

Defines
SPI Reception FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FRLVL_EMPTY ((uint32_t)0x0000)
#define | SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
#define | SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
#define | SPI_FRLVL_FULL ((uint32_t)0x0600)

Define Documentation

#define SPI_FRLVL_EMPTY ((uint32_t)0x0000)

Definition at line 392 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPIEx_FlushRxFifo(), SPI_EndRxTransaction(), and SPI_WaitFifoStateUntilTimeout().

#define SPI_FRLVL_FULL ((uint32_t)0x0600)

Definition at line 395 of file stm32l4xx_hal_spi.h.

#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)

Definition at line 394 of file stm32l4xx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)

Definition at line 393 of file stm32l4xx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Exported Macros

Defines
SPI Exported Macros
SPI

Defines

#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
Disable the SPI peripheral.

Define Documentation

#define __HAL_SPI_CLEAR_CRCERRFLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))

Clear the SPI CRCERR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 463 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_CLEAR_FREFLAG ( __HANDLE__ )
Value:
do{                                              \
     __IO uint32_t tmpreg;                          \
     tmpreg = (__HANDLE__)->Instance->SR;           \
     UNUSED(tmpreg);                                \
   } while(0)

Clear the SPI FRE pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 499 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_MODFFLAG ( __HANDLE__ )
Value:
do{                                              \
     __IO uint32_t tmpreg;                          \
     tmpreg = (__HANDLE__)->Instance->SR;           \
     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
     UNUSED(tmpreg);                                \
   } while(0)

Clear the SPI MODF pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 471 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{                                              \
     __IO uint32_t tmpreg;                          \
     tmpreg = (__HANDLE__)->Instance->DR;           \
     tmpreg = (__HANDLE__)->Instance->SR;           \
     UNUSED(tmpreg);                                \
   } while(0)

Clear the SPI OVR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 485 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

#define __HAL_SPI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))

Disable the SPI peripheral.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 518 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_Init(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))

Definition at line 426 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)

Enable the SPI peripheral.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 511 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))

Enable or disable the specified SPI interrupts.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 425 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SPI flag is set or not.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
  • SPI_FLAG_FRE: Frame format error flag
  • SPI_FLAG_FTLVL: SPI fifo transmission level
  • SPI_FLAG_FRLVL: SPI fifo reception level
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 456 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__,: specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 438 of file stm32l4xx_hal_spi.h.

#define __HAL_SPI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)

Reset SPI handle state.

Parameters:
__HANDLE__,: SPI handle.
Return values:
None

Definition at line 413 of file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSSP(NSSP)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_LENGTH(LENGTH)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

Definition at line 590 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPHA ( CPHA )
Value:
(((CPHA) == SPI_PHASE_1EDGE) || \
                           ((CPHA) == SPI_PHASE_2EDGE))

Definition at line 580 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPOL ( CPOL )
Value:
(((CPOL) == SPI_POLARITY_LOW) || \
                           ((CPOL) == SPI_POLARITY_HIGH))

Definition at line 577 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_CALCULATION ( CALCULATION )
Value:
(((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))

Definition at line 605 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_LENGTH ( LENGTH )
Value:
(((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT))

Definition at line 608 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_POLYNOMIAL ( POLYNOMIAL ) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))

Definition at line 612 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SPI_DATASIZE_16BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
                                   ((DATASIZE) == SPI_DATASIZE_4BIT))

Definition at line 563 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES) || \
                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
                                  ((MODE) == SPI_DIRECTION_1LINE))

Definition at line 554 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION_2LINES ( MODE ) ((MODE) == SPI_DIRECTION_2LINES)

Definition at line 558 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES)|| \
                                                 ((MODE) == SPI_DIRECTION_1LINE))

Definition at line 560 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define IS_SPI_FIRST_BIT ( BIT )
Value:
(((BIT) == SPI_FIRSTBIT_MSB) || \
                               ((BIT) == SPI_FIRSTBIT_LSB))

Definition at line 599 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_MODE ( MODE )
Value:
(((MODE) == SPI_MODE_SLAVE) || \
                           ((MODE) == SPI_MODE_MASTER))

Definition at line 551 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSS ( NSS )
Value:
(((NSS) == SPI_NSS_SOFT) || \
                         ((NSS) == SPI_NSS_HARD_INPUT) || \
                         ((NSS) == SPI_NSS_HARD_OUTPUT))

Definition at line 583 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSSP ( NSSP )
Value:
(((NSSP) == SPI_NSS_PULSE_ENABLE) || \
                           ((NSSP) == SPI_NSS_PULSE_DISABLE))

Definition at line 587 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_TIMODE ( MODE )
Value:
(((MODE) == SPI_TIMODE_DISABLE) || \
                             ((MODE) == SPI_TIMODE_ENABLE))

Definition at line 602 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_1LINE_RX ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))

Set the SPI receive-only mode.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 541 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define SPI_1LINE_TX ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)

Set the SPI transmit-only mode.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 534 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define SPI_RESET_CRC ( __HANDLE__ )
Value:
do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)

Reset the CRC calculation of the SPI.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 548 of file stm32l4xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SPIEx Private Constants

Defines
SPIEx Private Constants
SPIEx

Defines

#define SPI_FIFO_SIZE 4

Define Documentation

#define SPI_FIFO_SIZE 4

Definition at line 60 of file stm32l4xx_hal_spi_ex.c.

Referenced by HAL_SPIEx_FlushRxFifo().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPIEx Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of extended functions to manage the SPI
    data transfers.

    (#) Rx data flush function:
        (++) HAL_SPIEx_FlushRxFifo()

Function Documentation

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo ( SPI_HandleTypeDef * hspi )

Flush the RX fifo.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 98 of file stm32l4xx_hal_spi_ex.c.

References __SPI_HandleTypeDef::Instance, SPI_FIFO_SIZE, SPI_FLAG_FRLVL, and SPI_FRLVL_EMPTY.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SRAM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Perform the SRAM device de-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
Initialize the SRAM MSP.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
DeInitialize the SRAM MSP.
__weak void | HAL_SRAM_DMA_XferCpltCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
__weak void | HAL_SRAM_DMA_XferErrorCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete error callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
           ##### SRAM Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to initialize/de-initialize
          the SRAM memory.

Function Documentation

HAL_StatusTypeDef HAL_SRAM_DeInit ( SRAM_HandleTypeDef * hsram )

Perform the SRAM device de-initialization sequence.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 180 of file stm32l4xx_hal_sram.c.

References SRAM_HandleTypeDef::Extended, HAL_SRAM_MspDeInit(), HAL_SRAM_STATE_RESET, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, and SRAM_HandleTypeDef::State.

void HAL_SRAM_DMA_XferCpltCallback ( DMA_HandleTypeDef * hdma )

DMA transfer complete callback.

Parameters:
hdma,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 234 of file stm32l4xx_hal_sram.c.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

void HAL_SRAM_DMA_XferErrorCallback ( DMA_HandleTypeDef * hdma )

DMA transfer complete error callback.

Parameters:
hdma,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 250 of file stm32l4xx_hal_sram.c.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

HAL_StatusTypeDef HAL_SRAM_Init | ( | SRAM_HandleTypeDef * | hsram,
 |  | FMC_NORSRAM_TimingTypeDef * | Timing,
 |  | FMC_NORSRAM_TimingTypeDef * | ExtTiming
 | ) |  |

Perform the SRAM device initialization sequence.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Timing,: Pointer to SRAM control timing structure
ExtTiming,: Pointer to SRAM extended mode timing structure
Return values:
HAL status

Definition at line 142 of file stm32l4xx_hal_sram.c.

References SRAM_HandleTypeDef::Extended, HAL_SRAM_MspInit(), HAL_SRAM_STATE_RESET, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, SRAM_HandleTypeDef::Lock, and SRAM_HandleTypeDef::State.

void HAL_SRAM_MspDeInit ( SRAM_HandleTypeDef * hsram )

DeInitialize the SRAM MSP.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 218 of file stm32l4xx_hal_sram.c.

Referenced by HAL_SRAM_DeInit().

void HAL_SRAM_MspInit ( SRAM_HandleTypeDef * hsram )

Initialize the SRAM MSP.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
None

Definition at line 202 of file stm32l4xx_hal_sram.c.

Referenced by HAL_SRAM_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input Output and memory control functions

Functions
Input Output and memory control functions
SRAM Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Read 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Write 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Read 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Write 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Read 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Write 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Read a Word data buffer from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Write a Word data buffer to SRAM memory using DMA transfer.

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                  ##### SRAM Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the SRAM memory

Function Documentation

HAL_StatusTypeDef HAL_SRAM_Read_16b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Read 16-bit buffer from SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 365 of file stm32l4xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_32b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Read 32-bit buffer from SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 443 of file stm32l4xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_8b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Read 8-bit buffer from SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 287 of file stm32l4xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Read_DMA | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pDstBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Read a Word data buffer from the SRAM memory using DMA transfer.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to read start address
pDstBuffer,: Pointer to destination buffer
BufferSize,: Size of the buffer to read from memory
Return values:
HAL status

Definition at line 517 of file stm32l4xx_hal_sram.c.

References HAL_DMA_Start_IT(), HAL_SRAM_DMA_XferCpltCallback(), HAL_SRAM_DMA_XferErrorCallback(), HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_READY, SRAM_HandleTypeDef::hdma, SRAM_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SRAM_Write_16b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint16_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Write 16-bit buffer to SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 401 of file stm32l4xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_32b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Write 32-bit buffer to SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 477 of file stm32l4xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_8b | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint8_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Write 8-bit buffer to SRAM memory.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 323 of file stm32l4xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_Write_DMA | ( | SRAM_HandleTypeDef * | hsram,
 |  | uint32_t * | pAddress,
 |  | uint32_t * | pSrcBuffer,
 |  | uint32_t | BufferSize
 | ) |  |

Write a Word data buffer to SRAM memory using DMA transfer.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
pAddress,: Pointer to write start address
pSrcBuffer,: Pointer to source buffer to write
BufferSize,: Size of the buffer to write to memory
Return values:
HAL status

Definition at line 550 of file stm32l4xx_hal_sram.c.

References HAL_DMA_Start_IT(), HAL_SRAM_DMA_XferCpltCallback(), HAL_SRAM_DMA_XferErrorCallback(), HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, HAL_SRAM_STATE_READY, SRAM_HandleTypeDef::hdma, SRAM_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Control functions

Functions
Control functions
SRAM Exported Functions

Control functions. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enable dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disable dynamically SRAM write operation.

Detailed Description

Control functions.

  ==============================================================================
                        ##### SRAM Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control dynamically
    the SRAM interface.

Function Documentation

HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable ( SRAM_HandleTypeDef * hsram )

Disable dynamically SRAM write operation.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 628 of file stm32l4xx_hal_sram.c.

References HAL_SRAM_STATE_BUSY, HAL_SRAM_STATE_PROTECTED, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, and SRAM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable ( SRAM_HandleTypeDef * hsram )

Enable dynamically SRAM write operation.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL status

Definition at line 605 of file stm32l4xx_hal_sram.c.

References HAL_SRAM_STATE_READY, SRAM_HandleTypeDef::Init, SRAM_HandleTypeDef::Instance, and SRAM_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SRAM Exported Functions

Peripheral State functions. More...

Functions

HAL_SRAM_StateTypeDef HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Return the SRAM controller handle state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### SRAM State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the SRAM controller
    and the data flow.

Function Documentation

HAL_SRAM_StateTypeDef HAL_SRAM_GetState ( SRAM_HandleTypeDef * hsram )

Return the SRAM controller handle state.

Parameters:
hsram,: pointer to a SRAM_HandleTypeDef structure that contains the configuration information for SRAM module.
Return values:
HAL state

Definition at line 673 of file stm32l4xx_hal_sram.c.

References SRAM_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SRAM Exported Types

Data Structures | Enumerations
SRAM Exported Types
SRAM

Data Structures

struct SRAM_HandleTypeDef
SRAM handle Structure definition. More...

Enumerations

enum HAL_SRAM_StateTypeDef {
HAL_SRAM_STATE_RESET = 0x00, HAL_SRAM_STATE_READY = 0x01, HAL_SRAM_STATE_BUSY = 0x02, HAL_SRAM_STATE_ERROR = 0x03,
HAL_SRAM_STATE_PROTECTED = 0x04
}
HAL SRAM State structures definition. More...

Enumeration Type Documentation

enum HAL_SRAM_StateTypeDef

HAL SRAM State structures definition.

Enumerator:
HAL_SRAM_STATE_RESET

SRAM not yet initialized or disabled

HAL_SRAM_STATE_READY

SRAM initialized and ready for use

HAL_SRAM_STATE_BUSY

SRAM internal process is ongoing

HAL_SRAM_STATE_ERROR

SRAM error state

HAL_SRAM_STATE_PROTECTED

SRAM peripheral NORSRAM device write protected

Definition at line 67 of file stm32l4xx_hal_sram.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SRAM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SRAM_HandleTypeDef Struct Reference
SRAM Exported Types

SRAM handle Structure definition. More...

#include <stm32l4xx_hal_sram.h>

Data Fields

FMC_NORSRAM_TypeDef * | Instance
FMC_NORSRAM_EXTENDED_TypeDef * | Extended
FMC_NORSRAM_InitTypeDef | Init
HAL_LockTypeDef | Lock
__IO HAL_SRAM_StateTypeDef | State
DMA_HandleTypeDef * hdma

Detailed Description

SRAM handle Structure definition.

Definition at line 80 of file stm32l4xx_hal_sram.h.

Field Documentation

FMC_NORSRAM_EXTENDED_TypeDef* SRAM_HandleTypeDef::Extended

Extended mode register base address

Definition at line 84 of file stm32l4xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), and HAL_SRAM_Init().

DMA_HandleTypeDef* SRAM_HandleTypeDef::hdma

Pointer DMA handler

Definition at line 92 of file stm32l4xx_hal_sram.h.

Referenced by HAL_SRAM_Read_DMA(), and HAL_SRAM_Write_DMA().

FMC_NORSRAM_InitTypeDef SRAM_HandleTypeDef::Init

SRAM device control configuration parameters

Definition at line 86 of file stm32l4xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_Init(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

FMC_NORSRAM_TypeDef* SRAM_HandleTypeDef::Instance

Register base address

Definition at line 82 of file stm32l4xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_Init(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

HAL_LockTypeDef SRAM_HandleTypeDef::Lock

SRAM locking object

Definition at line 88 of file stm32l4xx_hal_sram.h.

Referenced by HAL_SRAM_Init().

__IO HAL_SRAM_StateTypeDef SRAM_HandleTypeDef::State

SRAM device access state

Definition at line 90 of file stm32l4xx_hal_sram.h.

Referenced by HAL_SRAM_DeInit(), HAL_SRAM_GetState(), HAL_SRAM_Init(), HAL_SRAM_Read_16b(), HAL_SRAM_Read_32b(), HAL_SRAM_Read_8b(), HAL_SRAM_Read_DMA(), HAL_SRAM_Write_16b(), HAL_SRAM_Write_32b(), HAL_SRAM_Write_8b(), HAL_SRAM_Write_DMA(), HAL_SRAM_WriteOperation_Disable(), and HAL_SRAM_WriteOperation_Enable().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_sram.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SRAM Exported Macros

Defines
SRAM Exported Macros
SRAM

Defines

#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
Reset SRAM handle state.

Define Documentation

#define __HAL_SRAM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)

Reset SRAM handle state.

Parameters:
__HANDLE__,: SRAM handle
Return values:
None

Definition at line 111 of file stm32l4xx_hal_sram.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization/de-initialization methods

Functions
Initialization/de-initialization methods
SWPMI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
__weak void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
__weak void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the SWPMI peripheral.
      (+) De-initialize the SWPMI peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SWPMI_DeInit ( SWPMI_HandleTypeDef * hswpmi )

De-initialize the SWPMI peripheral.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 219 of file stm32l4xx_hal_swpmi.c.

References assert_param, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_MspDeInit(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_RESET, SWPMI_HandleTypeDef::Instance, and SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_Init ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 145 of file stm32l4xx_hal_swpmi.c.

References assert_param, SWPMI_InitTypeDef::BitRate, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_MspInit(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_READY, HAL_SWPMI_STATE_RESET, SWPMI_HandleTypeDef::Init, SWPMI_HandleTypeDef::Instance, IS_SWPMI_BITRATE_VALUE, IS_SWPMI_RX_BUFFERING_MODE, IS_SWPMI_TX_BUFFERING_MODE, IS_SWPMI_VOLTAGE_CLASS, SWPMI_HandleTypeDef::Lock, SWPMI_InitTypeDef::RxBufferingMode, SWPMI_HandleTypeDef::State, SWPMI_VOLTAGE_CLASS_B, SWPMI_InitTypeDef::TxBufferingMode, and SWPMI_InitTypeDef::VoltageClass.

__weak void HAL_SWPMI_MspDeInit ( SWPMI_HandleTypeDef * hswpmi )

DeInitialize the SWPMI MSP.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 272 of file stm32l4xx_hal_swpmi.c.

Referenced by HAL_SWPMI_DeInit().

__weak void HAL_SWPMI_MspInit ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI MSP.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 257 of file stm32l4xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation methods

Functions
IO operation methods
SWPMI Exported Functions

SWPMI Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.

Detailed Description

SWPMI Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation methods #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SWPMI
     data transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) Non-Blocking mode: The communication is performed using Interrupts
           or DMA. The end of the data processing will be indicated through the
           dedicated SWPMI Interrupt handler (HAL_SWPMI_IRQHandler()) when using Interrupt mode or
           the selected DMA channel interrupt handler when using DMA mode.
           The HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or receive process.
           The HAL_SWPMI_ErrorCallback() user callback will be executed when a communication error is detected.

    (#) Blocking mode API's are:
        (++) HAL_SWPMI_Transmit()
        (++) HAL_SWPMI_Receive()

    (#) Non-Blocking mode API's with Interrupt are:
        (++) HAL_SWPMI_Transmit_IT()
        (++) HAL_SWPMI_Receive_IT()
        (++) HAL_SWPMI_IRQHandler()

    (#) Non-Blocking mode API's with DMA are:
        (++) HAL_SWPMI_Transmit_DMA()
        (++) HAL_SWPMI_Receive_DMA()
        (++) HAL_SWPMI_DMAPause()
        (++) HAL_SWPMI_DMAResume()
        (++) HAL_SWPMI_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
        (++) HAL_SWPMI_TxHalfCpltCallback()
        (++) HAL_SWPMI_TxCpltCallback()
        (++) HAL_SWPMI_RxHalfCpltCallback()
        (++) HAL_SWPMI_RxCpltCallback()
        (++) HAL_SWPMI_ErrorCallback()

    (#) The capability to launch the above IO operations in loopback mode for
        user application verification:
        (++) HAL_SWPMI_EnableLoopback()
        (++) HAL_SWPMI_DisableLoopback()

Function Documentation

HAL_StatusTypeDef HAL_SWPMI_DisableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Disable the Loopback mode.

Parameters:
hswpmi,: SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 882 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SWPMI_DMAStop ( SWPMI_HandleTypeDef * hswpmi )

Stop all DMA transfers.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL_OK

Definition at line 815 of file stm32l4xx_hal_swpmi.c.

References HAL_DMA_Abort(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmarx, SWPMI_HandleTypeDef::hdmatx, SWPMI_HandleTypeDef::Instance, and SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_EnableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Enable the Loopback mode.

Parameters:
hswpmi,: SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 852 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SWPMI_Receive | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 451 of file stm32l4xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, and SWPMI_IT_SRIE.

HAL_StatusTypeDef HAL_SWPMI_Receive_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 746 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmarx, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pRxBuffPtr, SWPMI_HandleTypeDef::RxXferSize, SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), SWPMI_DMARxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Receive_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 613 of file stm32l4xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pRxBuffPtr, SWPMI_HandleTypeDef::RxXferCount, SWPMI_HandleTypeDef::RxXferSize, SWPMI_HandleTypeDef::State, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, and SWPMI_IT_RXOVRIE.

HAL_StatusTypeDef HAL_SWPMI_Transmit | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 350 of file stm32l4xx_hal_swpmi.c.

References __HAL_SWPMI_CLEAR_FLAG, __HAL_SWPMI_DISABLE_IT, HAL_GetTick(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, and SWPMI_WaitOnFlagSetUntilTimeout().

HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 674 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmatx, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pTxBuffPtr, SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMATransmitCplt(), SWPMI_DMATxHalfCplt(), SWPMI_HandleTypeDef::TxXferCount, SWPMI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Transmit_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 548 of file stm32l4xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pTxBuffPtr, SWPMI_HandleTypeDef::State, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, SWPMI_HandleTypeDef::TxXferCount, and SWPMI_HandleTypeDef::TxXferSize.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI IRQ handler and callbacks

Functions
SWPMI IRQ handler and callbacks
SWPMI Exported Functions

SWPMI IRQ handler. More...

Functions

void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
__weak void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
__weak void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
__weak void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
__weak void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
__weak void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.

Detailed Description

SWPMI IRQ handler.

  ==============================================================================
                      ##### SWPMI IRQ handler and callbacks  #####
  ==============================================================================
[..]  This section provides SWPMI IRQ handler and callback functions called within
      the IRQ handler.

Function Documentation

__weak void HAL_SWPMI_ErrorCallback ( SWPMI_HandleTypeDef * hswpmi )

SWPMI error callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1072 of file stm32l4xx_hal_swpmi.c.

Referenced by HAL_SWPMI_IRQHandler(), SWPMI_DMAError(), and SWPMI_DMATransmitCplt().

void HAL_SWPMI_IRQHandler ( SWPMI_HandleTypeDef * hswpmi )

Handle SWPMI interrupt request.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 929 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_CRC, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_ERROR_OVR, HAL_SWPMI_ERROR_UDR, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_FLAG_RXBERF, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_FLAG_RXOVRF, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, SWPMI_Receive_IT(), and SWPMI_Transmit_IT().

__weak void HAL_SWPMI_RxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1042 of file stm32l4xx_hal_swpmi.c.

Referenced by SWPMI_DMAReceiveCplt(), and SWPMI_Receive_IT().

__weak void HAL_SWPMI_RxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Half Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1057 of file stm32l4xx_hal_swpmi.c.

Referenced by SWPMI_DMARxHalfCplt().

__weak void HAL_SWPMI_TxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1012 of file stm32l4xx_hal_swpmi.c.

Referenced by SWPMI_DMATransmitCplt(), and SWPMI_EndTransmit_IT().

__weak void HAL_SWPMI_TxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Half Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1027 of file stm32l4xx_hal_swpmi.c.

Referenced by SWPMI_DMATxHalfCplt().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control methods

Functions
Peripheral Control methods
SWPMI Exported Functions

SWPMI control functions. More...

Functions

HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Detailed Description

SWPMI control functions.

 ===============================================================================
                      ##### Peripheral Control methods #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SWPMI.
     (+) HAL_SWPMI_GetState() API is helpful to check in run-time the state of the SWPMI peripheral
     (+) HAL_SWPMI_GetError() API is helpful to check in run-time the error state of the SWPMI peripheral

Function Documentation

uint32_t HAL_SWPMI_GetError ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI error code.

Parameters:
hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for the specified SWPMI.
Return values:
SWPMI Error Code

Definition at line 1118 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode.

HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI handle state.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL state

Definition at line 1106 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Exported Functions

Modules | Functions
SWPMI Exported Functions
SWPMI

Modules

Initialization/de-initialization methods

Initialization and Configuration functions.

IO operation methods

SWPMI Transmit/Receive functions.

SWPMI IRQ handler and callbacks

SWPMI IRQ handler.

Peripheral Control methods

SWPMI control functions.

Functions

HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.
HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.
void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.
HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Function Documentation

HAL_StatusTypeDef HAL_SWPMI_DeInit ( SWPMI_HandleTypeDef * hswpmi )

De-initialize the SWPMI peripheral.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 219 of file stm32l4xx_hal_swpmi.c.

References assert_param, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_MspDeInit(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_RESET, SWPMI_HandleTypeDef::Instance, and SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_DisableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Disable the Loopback mode.

Parameters:
hswpmi,: SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 882 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SWPMI_DMAStop ( SWPMI_HandleTypeDef * hswpmi )

Stop all DMA transfers.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL_OK

Definition at line 815 of file stm32l4xx_hal_swpmi.c.

References HAL_DMA_Abort(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmarx, SWPMI_HandleTypeDef::hdmatx, SWPMI_HandleTypeDef::Instance, and SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_EnableLoopback ( SWPMI_HandleTypeDef * hswpmi )

Enable the Loopback mode.

Parameters:
hswpmi,: SWPMI handle
Note:
Loopback mode is to be used only for test purposes
Return values:
HAL_OK / HAL_BUSY

Definition at line 852 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::Instance.

void HAL_SWPMI_ErrorCallback ( SWPMI_HandleTypeDef * hswpmi )

SWPMI error callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1072 of file stm32l4xx_hal_swpmi.c.

Referenced by HAL_SWPMI_IRQHandler(), SWPMI_DMAError(), and SWPMI_DMATransmitCplt().

uint32_t HAL_SWPMI_GetError ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI error code.

Parameters:
hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for the specified SWPMI.
Return values:
SWPMI Error Code

Definition at line 1118 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode.

HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState ( SWPMI_HandleTypeDef * hswpmi )

Return the SWPMI handle state.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL state

Definition at line 1106 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SWPMI_Init ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 145 of file stm32l4xx_hal_swpmi.c.

References assert_param, SWPMI_InitTypeDef::BitRate, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_MspInit(), HAL_SWPMI_STATE_BUSY, HAL_SWPMI_STATE_READY, HAL_SWPMI_STATE_RESET, SWPMI_HandleTypeDef::Init, SWPMI_HandleTypeDef::Instance, IS_SWPMI_BITRATE_VALUE, IS_SWPMI_RX_BUFFERING_MODE, IS_SWPMI_TX_BUFFERING_MODE, IS_SWPMI_VOLTAGE_CLASS, SWPMI_HandleTypeDef::Lock, SWPMI_InitTypeDef::RxBufferingMode, SWPMI_HandleTypeDef::State, SWPMI_VOLTAGE_CLASS_B, SWPMI_InitTypeDef::TxBufferingMode, and SWPMI_InitTypeDef::VoltageClass.

void HAL_SWPMI_IRQHandler ( SWPMI_HandleTypeDef * hswpmi )

Handle SWPMI interrupt request.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 929 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_CRC, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_ERROR_OVR, HAL_SWPMI_ERROR_UDR, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_FLAG_RXBERF, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_FLAG_RXOVRF, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, SWPMI_Receive_IT(), and SWPMI_Transmit_IT().

void HAL_SWPMI_MspDeInit ( SWPMI_HandleTypeDef * hswpmi )

DeInitialize the SWPMI MSP.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 272 of file stm32l4xx_hal_swpmi.c.

Referenced by HAL_SWPMI_DeInit().

void HAL_SWPMI_MspInit ( SWPMI_HandleTypeDef * hswpmi )

Initialize the SWPMI MSP.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 257 of file stm32l4xx_hal_swpmi.c.

Referenced by HAL_SWPMI_Init().

HAL_StatusTypeDef HAL_SWPMI_Receive | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 451 of file stm32l4xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_RXBFF, SWPMI_FLAG_RXNE, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, SWPMI_IT_RXOVRIE, and SWPMI_IT_SRIE.

HAL_StatusTypeDef HAL_SWPMI_Receive_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 746 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmarx, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pRxBuffPtr, SWPMI_HandleTypeDef::RxXferSize, SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), SWPMI_DMARxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Receive_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 613 of file stm32l4xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pRxBuffPtr, SWPMI_HandleTypeDef::RxXferCount, SWPMI_HandleTypeDef::RxXferSize, SWPMI_HandleTypeDef::State, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, and SWPMI_IT_RXOVRIE.

void HAL_SWPMI_RxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1042 of file stm32l4xx_hal_swpmi.c.

Referenced by SWPMI_DMAReceiveCplt(), and SWPMI_Receive_IT().

void HAL_SWPMI_RxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Rx Half Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1057 of file stm32l4xx_hal_swpmi.c.

Referenced by SWPMI_DMARxHalfCplt().

HAL_StatusTypeDef HAL_SWPMI_Transmit | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 350 of file stm32l4xx_hal_swpmi.c.

References __HAL_SWPMI_CLEAR_FLAG, __HAL_SWPMI_DISABLE_IT, HAL_GetTick(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_TCF, SWPMI_FLAG_TXBEF, SWPMI_FLAG_TXE, SWPMI_FLAG_TXUNRF, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, and SWPMI_WaitOnFlagSetUntilTimeout().

HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA interrupt.

Parameters:
hswpmi,: SWPMI handle
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 674 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::hdmatx, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pTxBuffPtr, SWPMI_HandleTypeDef::State, SWPMI_DMAError(), SWPMI_DMATransmitCplt(), SWPMI_DMATxHalfCplt(), SWPMI_HandleTypeDef::TxXferCount, SWPMI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SWPMI_Transmit_IT | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with interrupt.

Parameters:
hswpmi,: pointer to a SWPMI_HandleTypeDef structure that contains the configuration information for SWPMI module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 548 of file stm32l4xx_hal_swpmi.c.

References __HAL_SWPMI_ENABLE_IT, SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_NONE, HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pTxBuffPtr, SWPMI_HandleTypeDef::State, SWPMI_IT_TCIE, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, SWPMI_IT_TXUNRIE, SWPMI_HandleTypeDef::TxXferCount, and SWPMI_HandleTypeDef::TxXferSize.

void HAL_SWPMI_TxCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1012 of file stm32l4xx_hal_swpmi.c.

Referenced by SWPMI_DMATransmitCplt(), and SWPMI_EndTransmit_IT().

void HAL_SWPMI_TxHalfCpltCallback ( SWPMI_HandleTypeDef * hswpmi )

Tx Half Transfer completed callback.

Parameters:
hswpmi,: SWPMI handle
Return values:
None

Definition at line 1027 of file stm32l4xx_hal_swpmi.c.

Referenced by SWPMI_DMATxHalfCplt().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Private Functions

Functions
SWPMI Private Functions
SWPMI

Functions

static HAL_StatusTypeDef | SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi)
Transmit an amount of data in interrupt mode.
static HAL_StatusTypeDef | SWPMI_EndTransmit_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi)
Receive an amount of data in interrupt mode.
static HAL_StatusTypeDef | SWPMI_EndReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up reception in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_EndTransmitReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission and reception in non-blocking mode.
static void | SWPMI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process complete callback.
static void | SWPMI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process half complete callback.
static void | SWPMI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process complete callback.
static void | SWPMI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process half complete callback.
static void | SWPMI_DMAError (DMA_HandleTypeDef *hdma)
DMA SWPMI communication error callback.
static HAL_StatusTypeDef | SWPMI_WaitOnFlagSetUntilTimeout (SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
Handle SWPMI Communication Timeout.

Function Documentation

static void SWPMI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1388 of file stm32l4xx_hal_swpmi.c.

References SWPMI_HandleTypeDef::ErrorCode, HAL_SWPMI_ERROR_DMA, HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::RxXferCount, SWPMI_HandleTypeDef::State, and SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_Receive_DMA(), and HAL_SWPMI_Transmit_DMA().

static void SWPMI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1345 of file stm32l4xx_hal_swpmi.c.

References HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, SWPMI_HandleTypeDef::RxXferCount, and SWPMI_HandleTypeDef::State.

Referenced by HAL_SWPMI_Receive_DMA().

static void SWPMI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI receive process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1376 of file stm32l4xx_hal_swpmi.c.

References HAL_SWPMI_RxHalfCpltCallback().

Referenced by HAL_SWPMI_Receive_DMA().

static void SWPMI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1281 of file stm32l4xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_ErrorCallback(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, HAL_SWPMI_TxCpltCallback(), SWPMI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_TXBEF, SWPMI_TIMEOUT_VALUE, SWPMI_WaitOnFlagSetUntilTimeout(), and SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_Transmit_DMA().

static void SWPMI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SWPMI transmit process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 1332 of file stm32l4xx_hal_swpmi.c.

References HAL_SWPMI_TxHalfCpltCallback().

Referenced by HAL_SWPMI_Transmit_DMA().

static HAL_StatusTypeDef SWPMI_EndReceive_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Wraps up reception in non-blocking mode.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL | status
HAL | status

Definition at line 1230 of file stm32l4xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_RXBFF, SWPMI_IT_RIE, SWPMI_IT_RXBERIE, SWPMI_IT_RXBFIE, and SWPMI_IT_RXOVRIE.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_EndTransmit_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL | status
HAL | status

Definition at line 1174 of file stm32l4xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, HAL_SWPMI_TxCpltCallback(), SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_TXBEF, SWPMI_IT_TIE, SWPMI_IT_TXBEIE, and SWPMI_IT_TXUNRIE.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Wraps up transmission and reception in non-blocking mode.

Parameters:
hswpmi,: SWPMI handle
Return values:
HAL | status
HAL | status

Definition at line 1256 of file stm32l4xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::State, SWPMI_FLAG_TCF, and SWPMI_IT_TCIE.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_Receive_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Receive an amount of data in interrupt mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT()
Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 1202 of file stm32l4xx_hal_swpmi.c.

References HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_STATE_BUSY_RX, HAL_SWPMI_STATE_BUSY_TX_RX, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pRxBuffPtr, SWPMI_HandleTypeDef::RxXferCount, and SWPMI_HandleTypeDef::State.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_Transmit_IT ( SWPMI_HandleTypeDef * hswpmi ) [static]

Transmit an amount of data in interrupt mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT()
Parameters:
hswpmi,: SWPMI handle
Return values:
HAL status

Definition at line 1143 of file stm32l4xx_hal_swpmi.c.

References HAL_SWPMI_STATE_BUSY_TX, HAL_SWPMI_STATE_BUSY_TX_RX, SWPMI_HandleTypeDef::Instance, SWPMI_HandleTypeDef::pTxBuffPtr, SWPMI_HandleTypeDef::State, SWPMI_IT_TIE, SWPMI_IT_TXUNRIE, and SWPMI_HandleTypeDef::TxXferCount.

Referenced by HAL_SWPMI_IRQHandler().

static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout | ( | SWPMI_HandleTypeDef * | hswpmi,
 |  | uint32_t | Flag,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SWPMI Communication Timeout.

Parameters:
hswpmi,: SWPMI handle
Flag,: specifies the SWPMI flag to check.
Tickstart | Tick start value
Timeout | timeout duration.
Return values:
HAL status

Definition at line 1409 of file stm32l4xx_hal_swpmi.c.

References HAL_GetTick(), HAL_SWPMI_STATE_READY, SWPMI_HandleTypeDef::Instance, and SWPMI_HandleTypeDef::State.

Referenced by HAL_SWPMI_Transmit(), and SWPMI_DMATransmitCplt().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Exported Types

Data Structures | Enumerations
SWPMI Exported Types
SWPMI

Data Structures

struct | SWPMI_InitTypeDef
SWPMI Init Structure definition. More...
struct | SWPMI_HandleTypeDef
SWPMI handle Structure definition. More...

Enumerations

enum HAL_SWPMI_StateTypeDef {
HAL_SWPMI_STATE_RESET = 0x00, HAL_SWPMI_STATE_READY = 0x01, HAL_SWPMI_STATE_BUSY = 0x02, HAL_SWPMI_STATE_BUSY_TX = 0x12,
HAL_SWPMI_STATE_BUSY_RX = 0x22, HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, HAL_SWPMI_STATE_TIMEOUT = 0x03, HAL_SWPMI_STATE_ERROR = 0x04
}
HAL SWPMI State structures definition. More...

Enumeration Type Documentation

enum HAL_SWPMI_StateTypeDef

HAL SWPMI State structures definition.

Enumerator:
HAL_SWPMI_STATE_RESET

Peripheral Reset state

HAL_SWPMI_STATE_READY

Peripheral Initialized and ready for use

HAL_SWPMI_STATE_BUSY

an internal process is ongoing

HAL_SWPMI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SWPMI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SWPMI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SWPMI_STATE_TIMEOUT

Timeout state

HAL_SWPMI_STATE_ERROR

Error

Definition at line 88 of file stm32l4xx_hal_swpmi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SWPMI_InitTypeDef Struct Reference
SWPMI Exported Types

SWPMI Init Structure definition. More...

#include <stm32l4xx_hal_swpmi.h>

Data Fields

uint32_t | VoltageClass
uint32_t | BitRate
uint32_t | TxBufferingMode
uint32_t | RxBufferingMode

Detailed Description

SWPMI Init Structure definition.

Definition at line 65 of file stm32l4xx_hal_swpmi.h.

Field Documentation

uint32_t SWPMI_InitTypeDef::BitRate

Specifies the SWPMI Bitrate. This parameter must be a number between 0 and 63. The Bitrate is computed using the following formula: SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)

Definition at line 70 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t SWPMI_InitTypeDef::RxBufferingMode

Specifies the reception buffering mode. This parameter can be a value of SWPMI Rx Buffering Mode

Definition at line 79 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t SWPMI_InitTypeDef::TxBufferingMode

Specifies the transmission buffering mode. This parameter can be a value of SWPMI Tx Buffering Mode

Definition at line 76 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t SWPMI_InitTypeDef::VoltageClass

Specifies the SWP Voltage Class. This parameter can be a value of SWPMI Voltage Class

Definition at line 67 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_swpmi.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SWPMI_HandleTypeDef Struct Reference
SWPMI Exported Types

SWPMI handle Structure definition. More...

#include <stm32l4xx_hal_swpmi.h>

Data Fields

SWPMI_TypeDef * | Instance
SWPMI_InitTypeDef Init
uint32_t * | pTxBuffPtr
uint32_t | TxXferSize
uint32_t | TxXferCount
uint32_t * | pRxBuffPtr
uint32_t | RxXferSize
uint32_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SWPMI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SWPMI handle Structure definition.

Definition at line 103 of file stm32l4xx_hal_swpmi.h.

Field Documentation

__IO uint32_t SWPMI_HandleTypeDef::ErrorCode

Definition at line 129 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_GetError(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), and SWPMI_DMAError().

DMA_HandleTypeDef* SWPMI_HandleTypeDef::hdmarx

Definition at line 123 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DMAStop(), and HAL_SWPMI_Receive_DMA().

DMA_HandleTypeDef* SWPMI_HandleTypeDef::hdmatx

Definition at line 121 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DMAStop(), and HAL_SWPMI_Transmit_DMA().

SWPMI_InitTypeDef SWPMI_HandleTypeDef::Init

Definition at line 107 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

SWPMI_TypeDef* SWPMI_HandleTypeDef::Instance

Definition at line 105 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_DisableLoopback(), HAL_SWPMI_DMAStop(), HAL_SWPMI_EnableLoopback(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), SWPMI_DMAReceiveCplt(), SWPMI_DMATransmitCplt(), SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_Receive_IT(), SWPMI_Transmit_IT(), and SWPMI_WaitOnFlagSetUntilTimeout().

HAL_LockTypeDef SWPMI_HandleTypeDef::Lock

Definition at line 125 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

uint32_t* SWPMI_HandleTypeDef::pRxBuffPtr

Definition at line 115 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), and SWPMI_Receive_IT().

uint32_t* SWPMI_HandleTypeDef::pTxBuffPtr

Definition at line 109 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), and SWPMI_Transmit_IT().

uint32_t SWPMI_HandleTypeDef::RxXferCount

Definition at line 119 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_IT(), SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), and SWPMI_Receive_IT().

uint32_t SWPMI_HandleTypeDef::RxXferSize

Definition at line 117 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_DMA(), and HAL_SWPMI_Receive_IT().

__IO HAL_SWPMI_StateTypeDef SWPMI_HandleTypeDef::State

Definition at line 127 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_DMAStop(), HAL_SWPMI_GetState(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), SWPMI_DMAError(), SWPMI_DMAReceiveCplt(), SWPMI_DMATransmitCplt(), SWPMI_EndReceive_IT(), SWPMI_EndTransmit_IT(), SWPMI_EndTransmitReceive_IT(), SWPMI_Receive_IT(), SWPMI_Transmit_IT(), and SWPMI_WaitOnFlagSetUntilTimeout().

uint32_t SWPMI_HandleTypeDef::TxXferCount

Definition at line 113 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit_DMA(), HAL_SWPMI_Transmit_IT(), SWPMI_DMAError(), SWPMI_DMATransmitCplt(), and SWPMI_Transmit_IT().

uint32_t SWPMI_HandleTypeDef::TxXferSize

Definition at line 111 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit_DMA(), and HAL_SWPMI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_swpmi.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Error Code Bitmap

Defines
SWPMI Error Code Bitmap
SWPMI Exported Constants

Defines

#define | HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004)
#define | HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008)
#define | HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C)
#define | HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010)

Define Documentation

#define HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004)

frame error

Definition at line 147 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010)

DMA transfer error

Definition at line 150 of file stm32l4xx_hal_swpmi.h.

Referenced by SWPMI_DMAError().

#define HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000)

No error

Definition at line 146 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_DeInit(), HAL_SWPMI_Init(), HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive_DMA(), HAL_SWPMI_Receive_IT(), HAL_SWPMI_Transmit_DMA(), and HAL_SWPMI_Transmit_IT().

#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008)

Overrun error

Definition at line 148 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C)

Underrun error

Definition at line 149 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Voltage Class

Defines
SWPMI Voltage Class
SWPMI Exported Constants

Defines

#define | SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define | SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS

Define Documentation

#define SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS

Definition at line 159 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)

Definition at line 158 of file stm32l4xx_hal_swpmi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Tx Buffering Mode

Defines
SWPMI Tx Buffering Mode
SWPMI Exported Constants

Defines

#define | SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE

Define Documentation

#define SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE

Definition at line 169 of file stm32l4xx_hal_swpmi.h.

#define SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 167 of file stm32l4xx_hal_swpmi.h.

#define SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 168 of file stm32l4xx_hal_swpmi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Rx Buffering Mode

Defines
SWPMI Rx Buffering Mode
SWPMI Exported Constants

Defines

#define | SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE

Define Documentation

#define SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE

Definition at line 179 of file stm32l4xx_hal_swpmi.h.

#define SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 177 of file stm32l4xx_hal_swpmi.h.

#define SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)

Definition at line 178 of file stm32l4xx_hal_swpmi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Status Flags

Defines
SWPMI Status Flags
SWPMI Exported Constants

Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF
#define | SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF
#define | SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF
#define | SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF
#define | SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF
#define | SWPMI_FLAG_RXNE SWPMI_ISR_RXNE
#define | SWPMI_FLAG_TXE SWPMI_ISR_TXE
#define | SWPMI_FLAG_TCF SWPMI_ISR_TCF
#define | SWPMI_FLAG_SRF SWPMI_ISR_SRF
#define | SWPMI_FLAG_SUSP SWPMI_ISR_SUSP
#define | SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF

Detailed Description

Elements values convention: 0xXXXXXXXX.

  • 0xXXXXXXXX : Flag mask in the ISR register

Define Documentation

#define SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF

Definition at line 199 of file stm32l4xx_hal_swpmi.h.

#define SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF

Definition at line 191 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF

Definition at line 189 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), and SWPMI_EndReceive_IT().

#define SWPMI_FLAG_RXNE SWPMI_ISR_RXNE

Definition at line 194 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Receive().

#define SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF

Definition at line 192 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler().

#define SWPMI_FLAG_SRF SWPMI_ISR_SRF

Definition at line 197 of file stm32l4xx_hal_swpmi.h.

#define SWPMI_FLAG_SUSP SWPMI_ISR_SUSP

Definition at line 198 of file stm32l4xx_hal_swpmi.h.

#define SWPMI_FLAG_TCF SWPMI_ISR_TCF

Definition at line 196 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), and SWPMI_EndTransmitReceive_IT().

#define SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF

Definition at line 190 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), SWPMI_DMATransmitCplt(), and SWPMI_EndTransmit_IT().

#define SWPMI_FLAG_TXE SWPMI_ISR_TXE

Definition at line 195 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Transmit().

#define SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF

Definition at line 193 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), and HAL_SWPMI_Transmit().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Interrupts Definition

Defines
SWPMI Interrupts Definition
SWPMI Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | SWPMI_IT_SRIE SWPMI_IER_SRIE
#define | SWPMI_IT_TCIE SWPMI_IER_TCIE
#define | SWPMI_IT_TIE SWPMI_IER_TIE
#define | SWPMI_IT_RIE SWPMI_IER_RIE
#define | SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE
#define | SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE
#define | SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE
#define | SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE
#define | SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the IER register

Define Documentation

#define SWPMI_IT_RIE SWPMI_IER_RIE

Definition at line 212 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE

Definition at line 215 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE

Definition at line 217 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE

Definition at line 214 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Receive(), HAL_SWPMI_Receive_IT(), and SWPMI_EndReceive_IT().

#define SWPMI_IT_SRIE SWPMI_IER_SRIE

Definition at line 209 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive().

#define SWPMI_IT_TCIE SWPMI_IER_TCIE

Definition at line 210 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_IT(), and SWPMI_EndTransmitReceive_IT().

#define SWPMI_IT_TIE SWPMI_IER_TIE

Definition at line 211 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_IT(), SWPMI_EndTransmit_IT(), and SWPMI_Transmit_IT().

#define SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE

Definition at line 216 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_IT(), and SWPMI_EndTransmit_IT().

#define SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE

Definition at line 213 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_IRQHandler(), HAL_SWPMI_Transmit(), HAL_SWPMI_Transmit_IT(), SWPMI_EndTransmit_IT(), and SWPMI_Transmit_IT().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Exported Macros

Defines
SWPMI Exported Macros
SWPMI

Defines

#define | __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
Reset SWPMI handle state.
#define | __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Enable the SWPMI peripheral.
#define | __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Disable the SWPMI peripheral.
#define | __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified SWPMI flag is set or not.
#define | __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
Clear the specified SWPMI ISR flag.
#define | __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Enable the specified SWPMI interrupt.
#define | __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Disable the specified SWPMI interrupt.
#define | __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
Check whether the specified SWPMI interrupt has occurred or not.
#define | __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
Check whether the specified SWPMI interrupt source is enabled or not.

Define Documentation

#define __HAL_SWPMI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))

Clear the specified SWPMI ISR flag.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • SWPMI_FLAG_RXBFF : Receive buffer full flag.
  • SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
  • SWPMI_FLAG_RXBERF : Receive CRC error flag.
  • SWPMI_FLAG_RXOVRF : Receive overrun error flag.
  • SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
  • SWPMI_FLAG_TCF : Transfer complete flag.
  • SWPMI_FLAG_SRF : Slave resume flag.
Return values:
None

Definition at line 283 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit().

#define __HAL_SWPMI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)

Disable the SWPMI peripheral.

Parameters:
__HANDLE__,: SWPMI handle
Return values:
None

Definition at line 249 of file stm32l4xx_hal_swpmi.h.

#define __HAL_SWPMI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))

Disable the specified SWPMI interrupt.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__INTERRUPT__,: specifies the SWPMI interrupt source to disable. This parameter can be one of the following values:
  • SWPMI_IT_SRIE : Slave resume interrupt.
  • SWPMI_IT_TCIE : Transmit complete interrupt.
  • SWPMI_IT_TIE : Transmit interrupt.
  • SWPMI_IT_RIE : Receive interrupt.
  • SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
  • SWPMI_IT_RXBEIE : Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE : Receive buffer full interrupt.
Return values:
None

Definition at line 317 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Transmit().

#define __HAL_SWPMI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)

Enable the SWPMI peripheral.

Parameters:
__HANDLE__,: SWPMI handle
Return values:
None

Definition at line 242 of file stm32l4xx_hal_swpmi.h.

#define __HAL_SWPMI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))

Enable the specified SWPMI interrupt.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__INTERRUPT__,: specifies the SWPMI interrupt source to enable. This parameter can be one of the following values:
  • SWPMI_IT_SRIE : Slave resume interrupt.
  • SWPMI_IT_TCIE : Transmit complete interrupt.
  • SWPMI_IT_TIE : Transmit interrupt.
  • SWPMI_IT_RIE : Receive interrupt.
  • SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
  • SWPMI_IT_RXBEIE : Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE : Receive buffer full interrupt.
Return values:
None

Definition at line 300 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Receive_IT(), and HAL_SWPMI_Transmit_IT().

#define __HAL_SWPMI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))

Check whether the specified SWPMI flag is set or not.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SWPMI_FLAG_RXBFF : Receive buffer full flag.
  • SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
  • SWPMI_FLAG_RXBERF : Receive CRC error flag.
  • SWPMI_FLAG_RXOVRF : Receive overrun error flag.
  • SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
  • SWPMI_FLAG_RXNE : Receive data register not empty.
  • SWPMI_FLAG_TXE : Transmit data register empty.
  • SWPMI_FLAG_TCF : Transfer complete flag.
  • SWPMI_FLAG_SRF : Slave resume flag.
  • SWPMI_FLAG_SUSP : SUSPEND flag.
  • SWPMI_FLAG_DEACTF : DEACTIVATED flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 268 of file stm32l4xx_hal_swpmi.h.

#define __HAL_SWPMI_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))

Check whether the specified SWPMI interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__IT__,: specifies the SWPMI interrupt to check. This parameter can be one of the following values:
  • SWPMI_IT_SRIE : Slave resume interrupt.
  • SWPMI_IT_TCIE : Transmit complete interrupt.
  • SWPMI_IT_TIE : Transmit interrupt.
  • SWPMI_IT_RIE : Receive interrupt.
  • SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
  • SWPMI_IT_RXBERIE : Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE : Receive buffer full interrupt.
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 334 of file stm32l4xx_hal_swpmi.h.

#define __HAL_SWPMI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) | ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)

Check whether the specified SWPMI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
__IT__,: specifies the SWPMI interrupt source to check. This parameter can be one of the following values:
  • SWPMI_IT_SRIE : Slave resume interrupt.
  • SWPMI_IT_TCIE : Transmit complete interrupt.
  • SWPMI_IT_TIE : Transmit interrupt.
  • SWPMI_IT_RIE : Receive interrupt.
  • SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
  • SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
  • SWPMI_IT_RXBERIE : Receive CRC error interrupt.
  • SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
  • SWPMI_IT_RXBFIE : Receive buffer full interrupt.
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 351 of file stm32l4xx_hal_swpmi.h.

#define __HAL_SWPMI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)

Reset SWPMI handle state.

Parameters:
__HANDLE__,: specifies the SWPMI Handle.
Return values:
None

Definition at line 235 of file stm32l4xx_hal_swpmi.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Private Types

SWPMI Private Types
SWPMI
Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Private Variables

SWPMI Private Variables
SWPMI
Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Private Constants

Defines
SWPMI Private Constants
SWPMI

Defines

#define SWPMI_TIMEOUT_VALUE ((uint32_t) 22000)

Define Documentation

#define SWPMI_TIMEOUT_VALUE ((uint32_t) 22000)

Definition at line 98 of file stm32l4xx_hal_swpmi.c.

Referenced by SWPMI_DMATransmitCplt().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SWPMI Private Macros

Defines
SWPMI Private Macros
SWPMI

Defines

#define | IS_SWPMI_VOLTAGE_CLASS(__CLASS__)
#define | IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
#define | IS_SWPMI_TX_BUFFERING_MODE(__MODE__)
#define | IS_SWPMI_RX_BUFFERING_MODE(__MODE__)

Define Documentation

#define IS_SWPMI_BITRATE_VALUE ( __VALUE__ ) (((__VALUE__) <= 63))

Definition at line 428 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define IS_SWPMI_RX_BUFFERING_MODE ( __MODE__ )
Value:
(((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
                                              ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))

Definition at line 435 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define IS_SWPMI_TX_BUFFERING_MODE ( __MODE__ )
Value:
(((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
                                              ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))

Definition at line 431 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

#define IS_SWPMI_VOLTAGE_CLASS ( __CLASS__ )
Value:
(((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
                                              ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))

Definition at line 425 of file stm32l4xx_hal_swpmi.h.

Referenced by HAL_SWPMI_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Time Base functions

Functions
Time Base functions
TIM Exported Functions

Time Base functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.

Detailed Description

Time Base functions.

  ==============================================================================
              ##### Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM base.
    (+) De-initialize the TIM base.
    (+) Start the Time Base.
    (+) Stop the Time Base.
    (+) Start the Time Base and enable interrupt.
    (+) Stop the Time Base and disable interrupt.
    (+) Start the Time Base and enable DMA transfer.
    (+) Stop the Time Base and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Base_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM Base peripheral.

Parameters:
htim,: TIM Base handle
Return values:
HAL status

Definition at line 237 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Base_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Parameters:
htim,: TIM Base handle
Return values:
HAL status

Definition at line 198 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_Base_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Base_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM Base MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 279 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_Base_DeInit().

void HAL_TIM_Base_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Base MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 264 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_Base_Init().

HAL_StatusTypeDef HAL_TIM_Base_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 295 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Base generation in DMA mode.

Parameters:
htim : TIM handle
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to peripheral.
Return values:
HAL status

Definition at line 382 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, TIM_DMA_UPDATE, TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Base_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation in interrupt mode.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 341 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 318 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in DMA mode.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 426 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in interrupt mode.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 361 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Time Output Compare functions

Functions
Time Output Compare functions
TIM Exported Functions

Time Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.

Detailed Description

Time Output Compare functions.

  ==============================================================================
                  ##### Time Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the Time Output Compare.
    (+) Stop the Time Output Compare.
    (+) Start the Time Output Compare and enable interrupt.
    (+) Stop the Time Output Compare and disable interrupt.
    (+) Start the Time Output Compare and enable DMA transfer.
    (+) Stop the Time Output Compare and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OC_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM peripheral.

Parameters:
htim,: TIM Output Compare handle
Return values:
HAL status

Definition at line 514 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Parameters:
htim,: TIM Output Compare handle
Return values:
HAL status

Definition at line 475 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM Output Compare MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 556 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_OC_DeInit().

void HAL_TIM_OC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 541 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_OC_Init().

HAL_StatusTypeDef HAL_TIM_OC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 579 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 785 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_OC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim : TIM OC handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 647 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 613 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 904 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 715 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Time PWM functions

Functions
Time PWM functions
TIM Exported Functions

Time PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.

Detailed Description

Time PWM functions.

  ==============================================================================
                          ##### Time PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM OPWM.
    (+) De-initialize the TIM PWM.
    (+) Start the Time PWM.
    (+) Stop the Time PWM.
    (+) Start the Time PWM and enable interrupt.
    (+) Stop the Time PWM and disable interrupt.
    (+) Start the Time PWM and enable DMA transfer.
    (+) Stop the Time PWM and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_PWM_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM peripheral.

Parameters:
htim,: TIM handle
Return values:
HAL status

Definition at line 1032 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_PWM_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_PWM_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Parameters:
htim,: TIM handle
Return values:
HAL status

Definition at line 993 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_PWM_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_PWM_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM PWM MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 1074 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_PWM_DeInit().

void HAL_TIM_PWM_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 1059 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_PWM_Init().

HAL_StatusTypeDef HAL_TIM_PWM_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation.

Parameters:
htim : TIM handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 1097 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode.

Parameters:
htim : TIM handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1300 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_PWM_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters:
htim : TIM handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1166 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation.

Parameters:
htim : TIM handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 1131 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode.

Parameters:
htim : TIM handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1417 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters:
htim : TIM handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1232 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Time Input Capture functions

Functions
Time Input Capture functions
TIM Exported Functions

Time Input Capture functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM INput Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.

Detailed Description

Time Input Capture functions.

  ==============================================================================
              ##### Time Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the Time Input Capture.
   (+) Stop the Time Input Capture.
   (+) Start the Time Input Capture and enable interrupt.
   (+) Stop the Time Input Capture and disable interrupt.
   (+) Start the Time Input Capture and enable DMA transfer.
   (+) Stop the Time Input Capture and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_IC_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM peripheral.

Parameters:
htim,: TIM Input Capture handle
Return values:
HAL status

Definition at line 1545 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_IC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Parameters:
htim,: TIM Input Capture handle
Return values:
HAL status

Definition at line 1506 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_IC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_IC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM Input Capture MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 1587 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IC_DeInit().

void HAL_TIM_IC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM INput Capture MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 1572 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IC_Init().

HAL_StatusTypeDef HAL_TIM_IC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement.

Parameters:
htim : TIM Input Capture handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1608 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Input Capture measurement on in DMA mode.

Parameters:
htim : TIM Input Capture handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The destination Buffer address.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 1781 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_IC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement in interrupt mode.

Parameters:
htim : TIM Input Capture handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1660 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement.

Parameters:
htim : TIM handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1634 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement on in DMA mode.

Parameters:
htim : TIM Input Capture handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1894 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in interrupt mode.

Parameters:
htim : TIM handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1719 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Time One Pulse functions

Functions
Time One Pulse functions
TIM Exported Functions

Time One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.

Detailed Description

Time One Pulse functions.

  ==============================================================================
                        ##### Time One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse.
    (+) De-initialize the TIM One Pulse.
    (+) Start the Time One Pulse.
    (+) Stop the Time One Pulse.
    (+) Start the Time One Pulse and enable interrupt.
    (+) Stop the Time One Pulse and disable interrupt.
    (+) Start the Time One Pulse and enable DMA transfer.
    (+) Stop the Time One Pulse and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM One Pulse.

Parameters:
htim,: TIM One Pulse handle
Return values:
HAL status

Definition at line 2027 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OnePulse_Init | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OnePulseMode
 | ) |  |

Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Parameters:
htim,: TIM OnePulse handle
OnePulseMode,: Select the One pulse mode. This parameter can be one of the following values:
  • TIM_OPMODE_SINGLE: Only one pulse will be generated.
  • TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
Return values:
HAL status

Definition at line 1981 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OnePulse_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_OPM_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OnePulse_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM One Pulse MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 2069 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_DeInit().

void HAL_TIM_OnePulse_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM One Pulse MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 2054 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_Init().

HAL_StatusTypeDef HAL_TIM_OnePulse_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2088 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2160 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channels to be disable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2124 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2202 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Time Encoder functions

Functions
Time Encoder functions
TIM Exported Functions

Time Encoder functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.

Detailed Description

Time Encoder functions.

  ==============================================================================
                          ##### Time Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder.
    (+) Start the Time Encoder.
    (+) Stop the Time Encoder.
    (+) Start the Time Encoder and enable interrupt.
    (+) Stop the Time Encoder and disable interrupt.
    (+) Start the Time Encoder and enable DMA transfer.
    (+) Stop the Time Encoder and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Encoder_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM Encoder interface.

Parameters:
htim,: TIM Encoder handle
Return values:
HAL status

Definition at line 2355 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Encoder_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_Encoder_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Encoder Interface and initialize the associated handle.

Parameters:
htim,: TIM Encoder Interface handle
sConfig,: TIM Encoder Interface configuration structure
Return values:
HAL status

Definition at line 2265 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_Encoder_InitTypeDef::EncoderMode, HAL_TIM_Encoder_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_Encoder_InitTypeDef::IC1Filter, TIM_Encoder_InitTypeDef::IC1Polarity, TIM_Encoder_InitTypeDef::IC1Prescaler, TIM_Encoder_InitTypeDef::IC1Selection, TIM_Encoder_InitTypeDef::IC2Filter, TIM_Encoder_InitTypeDef::IC2Polarity, TIM_Encoder_InitTypeDef::IC2Prescaler, TIM_Encoder_InitTypeDef::IC2Selection, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_ENCODER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Encoder_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM Encoder Interface MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 2397 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_DeInit().

void HAL_TIM_Encoder_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Encoder Interface MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 2382 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_Init().

HAL_StatusTypeDef HAL_TIM_Encoder_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2417 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData1,
 |  | uint32_t * | pData2,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Encoder Interface in DMA mode.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
pData1,: The destination Buffer address for IC1.
pData2,: The destination Buffer address for IC2.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2611 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_ALL, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface in interrupt mode.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2507 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2461 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in DMA mode.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2728 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_DMA_CC1, and TIM_DMA_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in interrupt mode.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2557 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM IRQ handler management

Functions
TIM IRQ handler management
TIM Exported Functions

IRQ handler management. More...

Functions

void HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.

Detailed Description

IRQ handler management.

  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides Timer IRQ handler function.

Function Documentation

void HAL_TIM_IRQHandler ( TIM_HandleTypeDef * htim )

This function handles TIM interrupts requests.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 2790 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_CLEAR_IT, __HAL_TIM_GET_FLAG, __HAL_TIM_GET_IT_SOURCE, TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_TriggerCallback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutationCallback(), TIM_HandleTypeDef::Instance, TIM_FLAG_BREAK, TIM_FLAG_CC1, TIM_FLAG_CC2, TIM_FLAG_CC3, TIM_FLAG_CC4, TIM_FLAG_COM, TIM_FLAG_TRIGGER, TIM_FLAG_UPDATE, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_COM, TIM_IT_TRIGGER, and TIM_IT_UPDATE.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
TIM Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
      (+) Configure External Clock source.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master and the Slave synchronization.
      (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigClockSource | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClockConfigTypeDef * | sClockSourceConfig
 | ) |  |

Configures the clock source to be used.

Parameters:
htim,: TIM handle
sClockSourceConfig,: pointer to a TIM_ClockConfigTypeDef structure that contains the clock source information for the TIM peripheral.
Return values:
HAL status

Definition at line 4062 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_ClockConfigTypeDef::ClockFilter, TIM_ClockConfigTypeDef::ClockPolarity, TIM_ClockConfigTypeDef::ClockPrescaler, TIM_ClockConfigTypeDef::ClockSource, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKFILTER, IS_TIM_CLOCKPOLARITY, IS_TIM_CLOCKPRESCALER, IS_TIM_CLOCKSOURCE, TIM_HandleTypeDef::State, TIM_CLOCKSOURCE_ETRMODE1, TIM_CLOCKSOURCE_ETRMODE2, TIM_CLOCKSOURCE_INTERNAL, TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ITR1, TIM_CLOCKSOURCE_ITR2, TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_TI1, TIM_CLOCKSOURCE_TI1ED, TIM_CLOCKSOURCE_TI2, TIM_ETR_SetConfig(), TIM_ITRx_SetConfig(), TIM_SLAVEMODE_EXTERNAL1, TIM_TI1_ConfigInputStage(), and TIM_TI2_ConfigInputStage().

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim,: TIM handle
sClearInputConfig,: pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
  • TIM_Channel_4: TIM Channel 4
  • TIM_Channel_5: TIM Channel 5
  • TIM_Channel_6: TIM Channel 6
Return values:
None

Definition at line 3901 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, TIM_HandleTypeDef::Instance, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_CLEARINPUTSOURCE_ETR, TIM_CLEARINPUTSOURCE_NONE, TIM_CLEARINPUTSOURCE_OCREFCLR, and TIM_ETR_SetConfig().

HAL_StatusTypeDef HAL_TIM_ConfigTI1Input | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TI1_Selection
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters:
htim,: TIM handle.
TI1_Selection,: Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  • TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values:
HAL status

Definition at line 4242 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, and IS_TIM_TI1SELECTION.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim,: TIM handle
BurstBaseAddress,: TIM Base address from when the DMA will starts the Data read This parameters can be on of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc,: TIM DMA Request sources This parameters can be on of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer,: The Buffer address.
BurstLength,: DMA Burst length. This parameter can be one value between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
Return values:
HAL status

Definition at line 3659 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMACaptureCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stop the DMA burst reading.

Parameters:
htim,: TIM handle
BurstRequestSrc,: TIM DMA Request sources to disable.
Return values:
HAL status

Definition at line 3791 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.

Parameters:
htim,: TIM handle
BurstBaseAddress,: TIM Base address from when the DMA will starts the Data write This parameters can be on of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc,: TIM DMA Request sources This parameters can be on of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer,: The Buffer address.
BurstLength,: DMA Burst length. This parameter can be one value between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
Return values:
HAL status

Definition at line 3436 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMADelayPulseCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stops the TIM DMA Burst mode.

Parameters:
htim,: TIM handle
BurstRequestSrc,: TIM DMA Request sources to disable
Return values:
HAL status

Definition at line 3567 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_GenerateEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | EventSource
 | ) |  |

Generate a software event.

Parameters:
htim,: TIM handle
EventSource,: specifies the event source. This parameter can be one of the following values:
  • TIM_EVENTSOURCE_UPDATE: Timer update Event source
  • TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  • TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  • TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  • TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  • TIM_EVENTSOURCE_COM: Timer COM event source
  • TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  • TIM_EVENTSOURCE_BREAK: Timer Break event source
  • TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
Return values:
None

Definition at line 3862 of file stm32l4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_EVENT_SOURCE, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_IC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.

Parameters:
htim,: TIM IC handle
sConfig,: TIM Input Capture configuration structure
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3055 of file stm32l4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_IC_InitTypeDef::ICFilter, TIM_IC_InitTypeDef::ICPolarity, TIM_IC_InitTypeDef::ICPrescaler, TIM_IC_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TI3_SetConfig(), and TIM_TI4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim,: TIM Output Compare handle
sConfig,: TIM Output Compare configuration structure
Channel : TIM Channels to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 2955 of file stm32l4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OnePulse_InitTypeDef * | sConfig,
 |  | uint32_t | OutputChannel,
 |  | uint32_t | InputChannel
 | ) |  |

Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.

Parameters:
htim,: TIM One Pulse handle
sConfig,: TIM One Pulse configuration structure
OutputChannel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
InputChannel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 3299 of file stm32l4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_OnePulse_InitTypeDef::ICFilter, TIM_OnePulse_InitTypeDef::ICPolarity, TIM_OnePulse_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_OPM_CHANNELS, TIM_OC_InitTypeDef::OCIdleState, TIM_OnePulse_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OnePulse_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OnePulse_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OnePulse_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OnePulse_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_OnePulse_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_SLAVEMODE_TRIGGER, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TS_TI1FP1, and TIM_TS_TI2FP2.

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim,: TIM PWM handle
sConfig,: TIM PWM configuration structure
Channel : TIM Channels to be configured This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 3154 of file stm32l4xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t HAL_TIM_ReadCapturedValue | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters:
htim,: TIM handle.
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
Captured value

Definition at line 4347 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode.

Parameters:
htim,: TIM handle.
sSlaveConfig,: pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4274 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode in interrupt mode.

Parameters:
htim,: TIM handle.
sSlaveConfig,: pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4309 of file stm32l4xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Callbacks functions

Functions
TIM Callbacks functions
TIM Exported Functions

TIM Callbacks functions. More...

Functions

__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.

Detailed Description

TIM Callbacks functions.

  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) Timer Period elapsed callback
   (+) Timer Output Compare callback
   (+) Timer Input capture callback
   (+) Timer Trigger callback
   (+) Timer Error callback

Function Documentation

void HAL_TIM_ErrorCallback ( TIM_HandleTypeDef * htim )

Timer error callback in non-blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 4508 of file stm32l4xx_hal_tim.c.

Referenced by TIM_DMAError().

void HAL_TIM_IC_CaptureCallback ( TIM_HandleTypeDef * htim )

Input Capture callback in non-blocking mode.

Parameters:
htim : TIM IC handle
Return values:
None

Definition at line 4463 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMACaptureCplt().

void HAL_TIM_OC_DelayElapsedCallback ( TIM_HandleTypeDef * htim )

Output Compare callback in non-blocking mode.

Parameters:
htim : TIM OC handle
Return values:
None

Definition at line 4449 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIM_PeriodElapsedCallback ( TIM_HandleTypeDef * htim )

Period elapsed callback in non-blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 4434 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMAPeriodElapsedCplt().

void HAL_TIM_PWM_PulseFinishedCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished callback in non-blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 4478 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMADelayPulseCplt().

void HAL_TIM_TriggerCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection callback in non-blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 4493 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMATriggerCplt().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
TIM Exported Functions

Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIM_Base_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Base handle state.

Parameters:
htim,: TIM Base handle
Return values:
HAL state

Definition at line 4542 of file stm32l4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode handle state.

Parameters:
htim,: TIM Encoder handle
Return values:
HAL state

Definition at line 4592 of file stm32l4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_IC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Input Capture handle state.

Parameters:
htim,: TIM IC handle
Return values:
HAL state

Definition at line 4572 of file stm32l4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM OC handle state.

Parameters:
htim,: TIM Ouput Compare handle
Return values:
HAL state

Definition at line 4552 of file stm32l4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState ( TIM_HandleTypeDef * htim )

Return the TIM One Pulse Mode handle state.

Parameters:
htim,: TIM OPM handle
Return values:
HAL state

Definition at line 4582 of file stm32l4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState ( TIM_HandleTypeDef * htim )

Return the TIM PWM handle state.

Parameters:
htim,: TIM handle
Return values:
HAL state

Definition at line 4562 of file stm32l4xx_hal_tim.c.

References TIM_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Exported Functions

Modules | Functions
TIM Exported Functions
TIM

Modules

Time Base functions

Time Base functions.

Time Output Compare functions

Time Output Compare functions.

Time PWM functions

Time PWM functions.

Time Input Capture functions

Time Input Capture functions.

Time One Pulse functions

Time One Pulse functions.

Time Encoder functions

Time Encoder functions.

TIM IRQ handler management

IRQ handler management.

Peripheral Control functions

Peripheral Control functions.

TIM Callbacks functions

TIM Callbacks functions.

Peripheral State functions

Peripheral State functions.

Functions

void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 4 configuration.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Ouput Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Ouput Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
Selects the Input Trigger source.

Function Documentation

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx,: TIM peripheral
Structure,: TIM Base configuration structure
Return values:
None

Definition at line 4714 of file stm32l4xx_hal_tim.c.

References TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
ChannelState,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
Return values:
None

Definition at line 5610 of file stm32l4xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

void TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4652 of file stm32l4xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4620 of file stm32l4xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4606 of file stm32l4xx_hal_tim.c.

References HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse complete callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4685 of file stm32l4xx_hal_tim.c.

References HAL_TIM_PeriodElapsedCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4699 of file stm32l4xx_hal_tim.c.

References HAL_TIM_STATE_READY, HAL_TIM_TriggerCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx to select the TIM peripheral
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 5580 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), and TIM_SlaveTimer_SetConfig().

static void TIM_ITRx_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | InputTriggerSource
 | ) |  | [static]

Selects the Input Trigger source.

Parameters:
TIMx to select the TIM peripheral
InputTriggerSource,: The Input Trigger source. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
Return values:
None

Definition at line 5550 of file stm32l4xx_hal_tim.c.

References TIM_SLAVEMODE_EXTERNAL1.

Referenced by HAL_TIM_ConfigClockSource().

static void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Time Ouput Compare 1 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The ouput configuration structure
Return values:
None

Definition at line 4759 of file stm32l4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_1.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Ouput Compare 2 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The ouput configuration structure
Return values:
None

Definition at line 4833 of file stm32l4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_2.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Time Ouput Compare 3 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The ouput configuration structure
Return values:
None

Definition at line 4909 of file stm32l4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_3.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Time Ouput Compare 4 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The ouput configuration structure
Return values:
None

Definition at line 4983 of file stm32l4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC5_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Ouput Compare 5 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The ouput configuration structure
Return values:
None

Definition at line 5041 of file stm32l4xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC6_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Ouput Compare 6 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The ouput configuration structure
Return values:
None

Definition at line 5094 of file stm32l4xx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_TI1_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI1.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5333 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5286 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_TI2_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI2.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5416 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

static void TIM_TI2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5376 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIM_OnePulse_ConfigChannel().

static void TIM_TI3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 5459 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

static void TIM_TI4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 5507 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Exported Types

Data Structures | Enumerations
TIM Exported Types
TIM

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00, HAL_TIM_STATE_READY = 0x01, HAL_TIM_STATE_BUSY = 0x02, HAL_TIM_STATE_TIMEOUT = 0x03,
HAL_TIM_STATE_ERROR = 0x04
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00
}
HAL Active channel structures definition. More...

Enumeration Type Documentation

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator:
HAL_TIM_ACTIVE_CHANNEL_1

The active channel is 1

HAL_TIM_ACTIVE_CHANNEL_2

The active channel is 2

HAL_TIM_ACTIVE_CHANNEL_3

The active channel is 3

HAL_TIM_ACTIVE_CHANNEL_4

The active channel is 4

HAL_TIM_ACTIVE_CHANNEL_5

The active channel is 5

HAL_TIM_ACTIVE_CHANNEL_6

The active channel is 6

HAL_TIM_ACTIVE_CHANNEL_CLEARED

All active channels cleared

Definition at line 320 of file stm32l4xx_hal_tim.h.

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_TIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_TIM_STATE_READY

Peripheral Initialized and ready for use

HAL_TIM_STATE_BUSY

An internal process is ongoing

HAL_TIM_STATE_TIMEOUT

Timeout state

HAL_TIM_STATE_ERROR

Reception process is ongoing

Definition at line 308 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_Base_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Base_InitTypeDef Struct Reference
TIM Exported Types

TIM Time base Configuration Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

uint32_t | Prescaler
uint32_t | CounterMode
uint32_t | Period
uint32_t | ClockDivision
uint32_t | RepetitionCounter

Detailed Description

TIM Time base Configuration Structure definition.

Definition at line 65 of file stm32l4xx_hal_tim.h.

Field Documentation

uint32_t TIM_Base_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of TIM Clock Division

Definition at line 77 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of TIM Counter Mode

Definition at line 70 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 73 of file stm32l4xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 67 of file stm32l4xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
    Note:
    This parameter is valid only for TIM1 and TIM8.

Definition at line 80 of file stm32l4xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OC_InitTypeDef Struct Reference
TIM Exported Types

TIM Output Compare Configuration Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCFastMode
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare Configuration Structure definition.

Definition at line 93 of file stm32l4xx_hal_tim.h.

Field Documentation

uint32_t TIM_OC_InitTypeDef::OCFastMode

Specifies the Fast mode state. This parameter can be a value of TIM Output Fast State

Note:
This parameter is valid only in PWM1 and PWM2 mode.

Definition at line 108 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

uint32_t TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 113 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 95 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 117 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 104 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 101 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 98 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_OnePulse_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OnePulse_InitTypeDef Struct Reference
TIM Exported Types

TIM One Pulse Mode Configuration Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState
uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICFilter

Detailed Description

TIM One Pulse Mode Configuration Structure definition.

Definition at line 125 of file stm32l4xx_hal_tim.h.

Field Documentation

uint32_t TIM_OnePulse_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 154 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 148 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 151 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 140 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 127 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 144 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 136 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 133 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 130 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_IC_InitTypeDef Struct Reference
TIM Exported Types

TIM Input Capture Configuration Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture Configuration Structure definition.

Definition at line 162 of file stm32l4xx_hal_tim.h.

Field Documentation

uint32_t TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 173 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 164 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 170 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 167 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_Encoder_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Encoder_InitTypeDef Struct Reference
TIM Exported Types

TIM Encoder Configuration Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1Selection
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2Selection
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder Configuration Structure definition.

Definition at line 180 of file stm32l4xx_hal_tim.h.

Field Documentation

uint32_t TIM_Encoder_InitTypeDef::EncoderMode

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Mode

Definition at line 182 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 194 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 185 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 191 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 188 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 206 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 197 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 203 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 200 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClockConfigTypeDef Struct Reference
TIM Exported Types

Clock Configuration Handle Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

uint32_t | ClockSource
uint32_t | ClockPolarity
uint32_t | ClockPrescaler
uint32_t | ClockFilter

Detailed Description

Clock Configuration Handle Structure definition.

Definition at line 214 of file stm32l4xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClockConfigTypeDef::ClockFilter

TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 222 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPolarity

TIM clock polarity This parameter can be a value of TIM Clock Polarity

Definition at line 218 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPrescaler

TIM clock prescaler This parameter can be a value of TIM Clock Prescaler

Definition at line 220 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockSource

TIM clock sources This parameter can be a value of TIM Clock Source

Definition at line 216 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_ClearInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClearInputConfigTypeDef Struct Reference
TIM Exported Types

Clear Input Configuration Handle Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

uint32_t | ClearInputState
uint32_t | ClearInputSource
uint32_t | ClearInputPolarity
uint32_t | ClearInputPrescaler
uint32_t | ClearInputFilter

Detailed Description

Clear Input Configuration Handle Structure definition.

Definition at line 229 of file stm32l4xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClearInputConfigTypeDef::ClearInputFilter

TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 239 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPolarity

TIM Clear Input polarity This parameter can be a value of TIM Clear Input Polarity

Definition at line 235 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPrescaler

TIM Clear Input prescaler This parameter can be a value of TIM Clear Input Prescaler

Definition at line 237 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputSource

TIM clear Input sources This parameter can be a value of TIM Clear Input Source

Definition at line 233 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputState

TIM clear Input state This parameter can be ENABLE or DISABLE

Definition at line 231 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_MasterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_MasterConfigTypeDef Struct Reference
TIM Exported Types

TIM Master configuration Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

uint32_t | MasterOutputTrigger
uint32_t | MasterOutputTrigger2
uint32_t | MasterSlaveMode

Detailed Description

TIM Master configuration Structure definition.

Note:
Advanced timers provide TRGO2 internal line which is redirected to the ADC

Definition at line 248 of file stm32l4xx_hal_tim.h.

Field Documentation

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger

Trigger output (TRGO) selection This parameter can be a value of TIM Master Mode Selection

Definition at line 249 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger2

Trigger output2 (TRGO2) selection This parameter can be a value of TIM Master Mode Selection 2 (TRGO2)

Definition at line 251 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterSlaveMode

Master/slave mode selection This parameter can be a value of TIM Master/Slave Mode

Definition at line 253 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_SlaveConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_SlaveConfigTypeDef Struct Reference
TIM Exported Types

TIM Slave configuration Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

uint32_t | SlaveMode
uint32_t | InputTrigger
uint32_t | TriggerPolarity
uint32_t | TriggerPrescaler
uint32_t | TriggerFilter

Detailed Description

TIM Slave configuration Structure definition.

Definition at line 260 of file stm32l4xx_hal_tim.h.

Field Documentation

uint32_t TIM_SlaveConfigTypeDef::InputTrigger

Input Trigger source This parameter can be a value of TIM Trigger Selection

Definition at line 263 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::SlaveMode

Slave mode selection This parameter can be a value of TIM Slave mode

Definition at line 261 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerFilter

Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 269 of file stm32l4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPolarity

Input Trigger polarity This parameter can be a value of TIM Trigger Polarity

Definition at line 265 of file stm32l4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPrescaler

Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler

Definition at line 267 of file stm32l4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_BreakDeadTimeConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_BreakDeadTimeConfigTypeDef Struct Reference
TIM Exported Types

TIM Break input(s) and Dead time configuration Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

uint32_t | OffStateRunMode
uint32_t | OffStateIDLEMode
uint32_t | LockLevel
uint32_t | DeadTime
uint32_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | AutomaticOutput

Detailed Description

TIM Break input(s) and Dead time configuration Structure definition.

Note:
2 break inputs can be configured (BKIN and BKIN2) with configurable filter and polarity.

Definition at line 279 of file stm32l4xx_hal_tim.h.

Field Documentation

uint32_t TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput

TIM Automatic Output Enable state This parameter can be a value of TIM Automatic Output Enable

Definition at line 301 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Filter

TIM break2 input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 299 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Polarity

TIM Break2 input polarity This parameter can be a value of TIM Break Input 2 Polarity

Definition at line 297 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2State

TIM Break2 State This parameter can be a value of TIM Break input 2 Enable

Definition at line 295 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakFilter

Specifies the break input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 293 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakPolarity

TIM Break input polarity This parameter can be a value of TIM Break Input Polarity

Definition at line 291 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakState

TIM Break State This parameter can be a value of TIM Break Input Enable

Definition at line 289 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::DeadTime

TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 287 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::LockLevel

TIM Lock level This parameter can be a value of TIM Lock level

Definition at line 285 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode

TIM off state in IDLE mode This parameter can be a value of TIM OSSI OffState Selection for Idle mode state

Definition at line 283 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode

TIM off state in run mode This parameter can be a value of TIM OSSR OffState Selection for Run mode state

Definition at line 281 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HandleTypeDef Struct Reference
TIM Exported Types

TIM Time Base Handle Structure definition. More...

#include <stm32l4xx_hal_tim.h>

Data Fields

TIM_TypeDef * | Instance
TIM_Base_InitTypeDef Init
HAL_TIM_ActiveChannel Channel
DMA_HandleTypeDef * | hdma [7]
HAL_LockTypeDef | Lock
__IO HAL_TIM_StateTypeDef | State

Detailed Description

TIM Time Base Handle Structure definition.

Definition at line 334 of file stm32l4xx_hal_tim.h.

Field Documentation

HAL_TIM_ActiveChannel TIM_HandleTypeDef::Channel

Active channel

Definition at line 338 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

DMA_HandleTypeDef* TIM_HandleTypeDef::hdma[7]

DMA Handlers array This array is accessed by a TIM DMA Handle Index

Definition at line 339 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

TIM_Base_InitTypeDef TIM_HandleTypeDef::Init

TIM Time Base required parameters

Definition at line 337 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

TIM_TypeDef* TIM_HandleTypeDef::Instance

Register base address

Definition at line 336 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), and TIM_SlaveTimer_SetConfig().

HAL_LockTypeDef TIM_HandleTypeDef::Lock

Locking object

Definition at line 341 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

__IO HAL_TIM_StateTypeDef TIM_HandleTypeDef::State

TIM operation state

Definition at line 342 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_GetState(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_ConfigClockSource(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_GetState(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_GetState(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_GetState(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_GetState(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_GetState(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_GetState(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_RemapConfig(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), and TIMEx_DMACommutationCplt().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Clear Input Source

Defines
TIM Clear Input Source
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
#define | TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
#define | TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)

Define Documentation

#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)

Definition at line 358 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)

Definition at line 360 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)

Definition at line 359 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM DMA Base Address

Defines
TIM DMA Base Address
TIM Exported Constants

Defines

#define | TIM_DMABASE_CR1 (0x00000000)
#define | TIM_DMABASE_CR2 (0x00000001)
#define | TIM_DMABASE_SMCR (0x00000002)
#define | TIM_DMABASE_DIER (0x00000003)
#define | TIM_DMABASE_SR (0x00000004)
#define | TIM_DMABASE_EGR (0x00000005)
#define | TIM_DMABASE_CCMR1 (0x00000006)
#define | TIM_DMABASE_CCMR2 (0x00000007)
#define | TIM_DMABASE_CCER (0x00000008)
#define | TIM_DMABASE_CNT (0x00000009)
#define | TIM_DMABASE_PSC (0x0000000A)
#define | TIM_DMABASE_ARR (0x0000000B)
#define | TIM_DMABASE_RCR (0x0000000C)
#define | TIM_DMABASE_CCR1 (0x0000000D)
#define | TIM_DMABASE_CCR2 (0x0000000E)
#define | TIM_DMABASE_CCR3 (0x0000000F)
#define | TIM_DMABASE_CCR4 (0x00000010)
#define | TIM_DMABASE_BDTR (0x00000011)
#define | TIM_DMABASE_DCR (0x00000012)
#define | TIM_DMABASE_DMAR (0x00000013)
#define | TIM_DMABASE_OR1 (0x00000014)
#define | TIM_DMABASE_CCMR3 (0x00000015)
#define | TIM_DMABASE_CCR5 (0x00000016)
#define | TIM_DMABASE_CCR6 (0x00000017)
#define | TIM_DMABASE_OR2 (0x00000018)
#define | TIM_DMABASE_OR3 (0x00000019)

Define Documentation

#define TIM_DMABASE_ARR (0x0000000B)

Definition at line 379 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_BDTR (0x00000011)

Definition at line 385 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CCER (0x00000008)

Definition at line 376 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CCMR1 (0x00000006)

Definition at line 374 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CCMR2 (0x00000007)

Definition at line 375 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CCMR3 (0x00000015)

Definition at line 389 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CCR1 (0x0000000D)

Definition at line 381 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CCR2 (0x0000000E)

Definition at line 382 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CCR3 (0x0000000F)

Definition at line 383 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CCR4 (0x00000010)

Definition at line 384 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CCR5 (0x00000016)

Definition at line 390 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CCR6 (0x00000017)

Definition at line 391 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CNT (0x00000009)

Definition at line 377 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CR1 (0x00000000)

Definition at line 368 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_CR2 (0x00000001)

Definition at line 369 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_DCR (0x00000012)

Definition at line 386 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_DIER (0x00000003)

Definition at line 371 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_DMAR (0x00000013)

Definition at line 387 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_EGR (0x00000005)

Definition at line 373 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_OR1 (0x00000014)

Definition at line 388 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_OR2 (0x00000018)

Definition at line 392 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_OR3 (0x00000019)

Definition at line 393 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_PSC (0x0000000A)

Definition at line 378 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_RCR (0x0000000C)

Definition at line 380 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_SMCR (0x00000002)

Definition at line 370 of file stm32l4xx_hal_tim.h.

#define TIM_DMABASE_SR (0x00000004)

Definition at line 372 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Extended Event Source

Defines
TIM Extended Event Source
TIM Exported Constants

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

Define Documentation

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

A break event is generated

Definition at line 408 of file stm32l4xx_hal_tim.h.

#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

A break 2 event is generated

Definition at line 409 of file stm32l4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

A capture/compare event is generated on channel 1

Definition at line 402 of file stm32l4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

A capture/compare event is generated on channel 2

Definition at line 403 of file stm32l4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

A capture/compare event is generated on channel 3

Definition at line 404 of file stm32l4xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

A capture/compare event is generated on channel 4

Definition at line 405 of file stm32l4xx_hal_tim.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

A commutation event is generated

Definition at line 406 of file stm32l4xx_hal_tim.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

A trigger event is generated

Definition at line 407 of file stm32l4xx_hal_tim.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Reinitialize the counter and generates an update of the registers

Definition at line 401 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Input Channel polarity

Defines
TIM Input Channel polarity
TIM Exported Constants

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000)
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Polarity for TIx source

Definition at line 419 of file stm32l4xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)

Polarity for TIx source

Definition at line 418 of file stm32l4xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000)

Polarity for TIx source

Definition at line 417 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM ETR Polarity

Defines
TIM ETR Polarity
TIM Exported Constants

Defines

#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000)

Define Documentation

#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)

Polarity for ETR source

Definition at line 427 of file stm32l4xx_hal_tim.h.

#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000)

Polarity for ETR source

Definition at line 428 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM ETR Prescaler

Defines
TIM ETR Prescaler
TIM Exported Constants

Defines

#define | TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000)
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

Define Documentation

#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000)

No prescaler is used

Definition at line 436 of file stm32l4xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)

ETR input source is divided by 2

Definition at line 437 of file stm32l4xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)

ETR input source is divided by 4

Definition at line 438 of file stm32l4xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

ETR input source is divided by 8

Definition at line 439 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Counter Mode

Defines
TIM Counter Mode
TIM Exported Constants

Defines

#define | TIM_COUNTERMODE_UP ((uint32_t)0x0000)
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Define Documentation

#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0

Definition at line 449 of file stm32l4xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1

Definition at line 450 of file stm32l4xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Definition at line 451 of file stm32l4xx_hal_tim.h.

#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Definition at line 448 of file stm32l4xx_hal_tim.h.

#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)

Definition at line 447 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Clock Division

Defines
TIM Clock Division
TIM Exported Constants

Defines

#define | TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Define Documentation

#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)

Definition at line 459 of file stm32l4xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)

Definition at line 460 of file stm32l4xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Definition at line 461 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Output Compare State

Defines
TIM Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
#define | TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)

Define Documentation

#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)

Definition at line 469 of file stm32l4xx_hal_tim.h.

#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)

Definition at line 470 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Output Fast State

Defines
TIM Output Fast State
TIM Exported Constants

Defines

#define | TIM_OCFAST_DISABLE ((uint32_t)0x0000)
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Define Documentation

#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)

Definition at line 478 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Definition at line 479 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Complementary Output Compare State

Defines
TIM Complementary Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
#define | TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)

Define Documentation

#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)

Definition at line 487 of file stm32l4xx_hal_tim.h.

#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)

Definition at line 488 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Output Compare Polarity

Defines
TIM Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Define Documentation

#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)

Definition at line 496 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Definition at line 497 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Complementary Output Compare Polarity

Defines
TIM Complementary Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Define Documentation

#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)

Definition at line 505 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Definition at line 506 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Output Compare Idle State

Defines
TIM Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)

Define Documentation

#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)

Definition at line 515 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)

Definition at line 514 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Complementary Output Compare Idle State

Defines
TIM Complementary Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)

Define Documentation

#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)

Definition at line 524 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)

Definition at line 523 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Input Capture Polarity

Defines
TIM Input Capture Polarity
TIM Exported Constants

Defines

#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Definition at line 534 of file stm32l4xx_hal_tim.h.

#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Definition at line 533 of file stm32l4xx_hal_tim.h.

#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Definition at line 532 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Input Capture Selection

Defines
TIM Input Capture Selection
TIM Exported Constants

Defines

#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

Define Documentation

#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 542 of file stm32l4xx_hal_tim.h.

#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively

Definition at line 544 of file stm32l4xx_hal_tim.h.

#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC

Definition at line 546 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Input Capture Prescaler

Defines
TIM Input Capture Prescaler
TIM Exported Constants

Defines

#define | TIM_ICPSC_DIV1 ((uint32_t)0x0000)
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Define Documentation

#define TIM_ICPSC_DIV1 ((uint32_t)0x0000)

Capture performed each time an edge is detected on the capture input

Definition at line 554 of file stm32l4xx_hal_tim.h.

#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)

Capture performed once every 2 events

Definition at line 555 of file stm32l4xx_hal_tim.h.

#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)

Capture performed once every 4 events

Definition at line 556 of file stm32l4xx_hal_tim.h.

#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Capture performed once every 8 events

Definition at line 557 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM One Pulse Mode

Defines
TIM One Pulse Mode
TIM Exported Constants

Defines

#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)

Define Documentation

#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)

Definition at line 566 of file stm32l4xx_hal_tim.h.

#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)

Definition at line 565 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Encoder Mode

Defines
TIM Encoder Mode
TIM Exported Constants

Defines

#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)

Definition at line 574 of file stm32l4xx_hal_tim.h.

#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Definition at line 576 of file stm32l4xx_hal_tim.h.

#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)

Definition at line 575 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM interrupt Definition

Defines
TIM interrupt Definition
TIM Exported Constants

Defines

#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)

Define Documentation

#define TIM_IT_BREAK (TIM_DIER_BIE)

Definition at line 591 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC1 (TIM_DIER_CC1IE)

Definition at line 585 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC2 (TIM_DIER_CC2IE)

Definition at line 586 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC3 (TIM_DIER_CC3IE)

Definition at line 587 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC4 (TIM_DIER_CC4IE)

Definition at line 588 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_COM (TIM_DIER_COMIE)

Definition at line 589 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), and HAL_TIMEx_ConfigCommutationEvent_IT().

#define TIM_IT_TRIGGER (TIM_DIER_TIE)

Definition at line 590 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_IT_UPDATE (TIM_DIER_UIE)

Definition at line 584 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop_IT(), and HAL_TIM_IRQHandler().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Commutation Source

Defines
TIM Commutation Source
TIM Exported Constants

Defines

#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)

Define Documentation

#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)

Definition at line 600 of file stm32l4xx_hal_tim.h.

#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)

Definition at line 599 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM DMA Sources

Defines
TIM DMA Sources
TIM Exported Constants

Defines

#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)

Define Documentation

#define TIM_DMA_CC1 (TIM_DIER_CC1DE)

Definition at line 609 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC2 (TIM_DIER_CC2DE)

Definition at line 610 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC3 (TIM_DIER_CC3DE)

Definition at line 611 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC4 (TIM_DIER_CC4DE)

Definition at line 612 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_COM (TIM_DIER_COMDE)

Definition at line 613 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

#define TIM_DMA_TRIGGER (TIM_DIER_TDE)

Definition at line 614 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_DMA_UPDATE (TIM_DIER_UDE)

Definition at line 608 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Flag Definition

Defines
TIM Flag Definition
TIM Exported Constants

Defines

#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_CC5 (TIM_SR_CC5IF)
#define | TIM_FLAG_CC6 (TIM_SR_CC6IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_BREAK2 (TIM_SR_B2IF)
#define | TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Define Documentation

#define TIM_FLAG_BREAK (TIM_SR_BIF)

Definition at line 631 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_BREAK2 (TIM_SR_B2IF)

Definition at line 632 of file stm32l4xx_hal_tim.h.

#define TIM_FLAG_CC1 (TIM_SR_CC1IF)

Definition at line 623 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)

Definition at line 634 of file stm32l4xx_hal_tim.h.

#define TIM_FLAG_CC2 (TIM_SR_CC2IF)

Definition at line 624 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)

Definition at line 635 of file stm32l4xx_hal_tim.h.

#define TIM_FLAG_CC3 (TIM_SR_CC3IF)

Definition at line 625 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)

Definition at line 636 of file stm32l4xx_hal_tim.h.

#define TIM_FLAG_CC4 (TIM_SR_CC4IF)

Definition at line 626 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Definition at line 637 of file stm32l4xx_hal_tim.h.

#define TIM_FLAG_CC5 (TIM_SR_CC5IF)

Definition at line 627 of file stm32l4xx_hal_tim.h.

#define TIM_FLAG_CC6 (TIM_SR_CC6IF)

Definition at line 628 of file stm32l4xx_hal_tim.h.

#define TIM_FLAG_COM (TIM_SR_COMIF)

Definition at line 629 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)

Definition at line 633 of file stm32l4xx_hal_tim.h.

#define TIM_FLAG_TRIGGER (TIM_SR_TIF)

Definition at line 630 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_UPDATE (TIM_SR_UIF)

Definition at line 622 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Channel

Defines
TIM Channel
TIM Exported Constants

Defines

#define | TIM_CHANNEL_1 ((uint32_t)0x0000)
#define | TIM_CHANNEL_2 ((uint32_t)0x0004)
#define | TIM_CHANNEL_3 ((uint32_t)0x0008)
#define | TIM_CHANNEL_4 ((uint32_t)0x000C)
#define | TIM_CHANNEL_5 ((uint32_t)0x0010)
#define | TIM_CHANNEL_6 ((uint32_t)0x0014)
#define | TIM_CHANNEL_ALL ((uint32_t)0x003C)

Define Documentation

#define TIM_CHANNEL_1 ((uint32_t)0x0000)

Definition at line 645 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC1_SetConfig().

#define TIM_CHANNEL_2 ((uint32_t)0x0004)

Definition at line 646 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC2_SetConfig().

#define TIM_CHANNEL_3 ((uint32_t)0x0008)

Definition at line 647 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC3_SetConfig().

#define TIM_CHANNEL_4 ((uint32_t)0x000C)

Definition at line 648 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_5 ((uint32_t)0x0010)

Definition at line 649 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_6 ((uint32_t)0x0014)

Definition at line 650 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_ALL ((uint32_t)0x003C)

Definition at line 651 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_DMA().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Clock Source

Defines
TIM Clock Source
TIM Exported Constants

Defines

#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)

Define Documentation

#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)

Definition at line 668 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)

Definition at line 659 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)

Definition at line 660 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)

Definition at line 661 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)

Definition at line 662 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)

Definition at line 663 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Definition at line 664 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)

Definition at line 666 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)

Definition at line 665 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Definition at line 667 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Clock Polarity

Defines
TIM Clock Polarity
TIM Exported Constants

Defines

#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIx clock sources

Definition at line 680 of file stm32l4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIx clock sources

Definition at line 679 of file stm32l4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx clock sources

Definition at line 676 of file stm32l4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx clock sources

Definition at line 677 of file stm32l4xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIx clock sources

Definition at line 678 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Clock Prescaler

Defines
TIM Clock Prescaler
TIM Exported Constants

Defines

#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 688 of file stm32l4xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Clock: Capture performed once every 2 events.

Definition at line 689 of file stm32l4xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Clock: Capture performed once every 4 events.

Definition at line 690 of file stm32l4xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Clock: Capture performed once every 8 events.

Definition at line 691 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Clear Input Polarity

Defines
TIM Clear Input Polarity
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 699 of file stm32l4xx_hal_tim.h.

#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 700 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Clear Input Prescaler

Defines
TIM Clear Input Prescaler
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 708 of file stm32l4xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 709 of file stm32l4xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 710 of file stm32l4xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 711 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM OSSR OffState Selection for Run mode state

Defines
TIM OSSR OffState Selection for Run mode state
TIM Exported Constants

Defines

#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_OSSR_DISABLE ((uint32_t)0x0000)

Definition at line 720 of file stm32l4xx_hal_tim.h.

#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)

Definition at line 719 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM OSSI OffState Selection for Idle mode state

Defines
TIM OSSI OffState Selection for Idle mode state
TIM Exported Constants

Defines

#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_OSSI_DISABLE ((uint32_t)0x0000)

Definition at line 729 of file stm32l4xx_hal_tim.h.

#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)

Definition at line 728 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Lock level

Defines
TIM Lock level
TIM Exported Constants

Defines

#define | TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Define Documentation

#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)

Definition at line 737 of file stm32l4xx_hal_tim.h.

#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)

Definition at line 738 of file stm32l4xx_hal_tim.h.

#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Definition at line 739 of file stm32l4xx_hal_tim.h.

#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)

Definition at line 736 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Break Input Enable

Defines
TIM Break Input Enable
TIM Exported Constants

Defines

#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_BREAK_DISABLE ((uint32_t)0x0000)

Definition at line 748 of file stm32l4xx_hal_tim.h.

#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)

Definition at line 747 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Break Input Polarity

Defines
TIM Break Input Polarity
TIM Exported Constants

Defines

#define | TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Define Documentation

#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Definition at line 757 of file stm32l4xx_hal_tim.h.

#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)

Definition at line 756 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Break input 2 Enable

Defines
TIM Break input 2 Enable
TIM Exported Constants

Defines

#define | TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
#define | TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)

Define Documentation

#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)

Definition at line 765 of file stm32l4xx_hal_tim.h.

#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)

Definition at line 766 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Break Input 2 Polarity

Defines
TIM Break Input 2 Polarity
TIM Exported Constants

Defines

#define | TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
#define | TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)

Define Documentation

#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)

Definition at line 775 of file stm32l4xx_hal_tim.h.

#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)

Definition at line 774 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Automatic Output Enable

Defines
TIM Automatic Output Enable
TIM Exported Constants

Defines

#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)

Definition at line 784 of file stm32l4xx_hal_tim.h.

#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)

Definition at line 783 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: Group Channel 5 and Channel 1, 2 or 3

Defines
Group Channel 5 and Channel 1, 2 or 3
TIM Exported Constants

Defines

#define | TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define | TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define | TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define | TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */

Define Documentation

#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */

Definition at line 792 of file stm32l4xx_hal_tim.h.

#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */

Definition at line 793 of file stm32l4xx_hal_tim.h.

#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */

Definition at line 794 of file stm32l4xx_hal_tim.h.

#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */

Definition at line 795 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Master Mode Selection

Defines
TIM Master Mode Selection
TIM Exported Constants

Defines

#define | TIM_TRGO_RESET ((uint32_t)0x0000)
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Define Documentation

#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)

Definition at line 804 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 806 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)

Definition at line 807 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))

Definition at line 808 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))

Definition at line 809 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 810 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO_RESET ((uint32_t)0x0000)

Definition at line 803 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)

Definition at line 805 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Master Mode Selection 2 (TRGO2)

Defines
TIM Master Mode Selection 2 (TRGO2)
TIM Exported Constants

Defines

#define | TIM_TRGO2_RESET ((uint32_t)0x00000000)
#define | TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
#define | TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
#define | TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Define Documentation

#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))

Definition at line 819 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 821 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))

Definition at line 822 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))

Definition at line 823 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))

Definition at line 824 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 825 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))

Definition at line 831 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))

Definition at line 830 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))

Definition at line 828 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))

Definition at line 826 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 833 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))

Definition at line 832 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))

Definition at line 827 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))

Definition at line 829 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_RESET ((uint32_t)0x00000000)

Definition at line 818 of file stm32l4xx_hal_tim.h.

#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))

Definition at line 820 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Master/Slave Mode

Defines
TIM Master/Slave Mode
TIM Exported Constants

Defines

#define | TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
#define | TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)

Definition at line 842 of file stm32l4xx_hal_tim.h.

#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)

Definition at line 841 of file stm32l4xx_hal_tim.h.

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STM32L486xx HAL User Manual: TIM Slave mode

Defines
TIM Slave mode
TIM Exported Constants

Defines

#define | TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
#define | TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
#define | TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
#define | TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))

Define Documentation

#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))

Definition at line 855 of file stm32l4xx_hal_tim.h.

#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)

Definition at line 850 of file stm32l4xx_hal_tim.h.

#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))

Definition at line 854 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_ITRx_SetConfig().

#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))

Definition at line 852 of file stm32l4xx_hal_tim.h.

#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))

Definition at line 851 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))

Definition at line 853 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

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STM32L486xx HAL User Manual: TIM Output Compare and PWM Modes

Defines
TIM Output Compare and PWM Modes
TIM Exported Constants

Defines

#define | TIM_OCMODE_TIMING ((uint32_t)0x0000)
#define | TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Define Documentation

#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)

Definition at line 864 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Definition at line 876 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Definition at line 877 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Definition at line 874 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Definition at line 875 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

Definition at line 869 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)

Definition at line 870 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)

Definition at line 865 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

Definition at line 867 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Definition at line 868 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)

Definition at line 872 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Definition at line 873 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_TIMING ((uint32_t)0x0000)

Definition at line 863 of file stm32l4xx_hal_tim.h.

#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Definition at line 866 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Exported Constants

Defines

#define | TIM_TS_ITR0 ((uint32_t)0x0000)
#define | TIM_TS_ITR1 ((uint32_t)0x0010)
#define | TIM_TS_ITR2 ((uint32_t)0x0020)
#define | TIM_TS_ITR3 ((uint32_t)0x0030)
#define | TIM_TS_TI1F_ED ((uint32_t)0x0040)
#define | TIM_TS_TI1FP1 ((uint32_t)0x0050)
#define | TIM_TS_TI2FP2 ((uint32_t)0x0060)
#define | TIM_TS_ETRF ((uint32_t)0x0070)
#define | TIM_TS_NONE ((uint32_t)0xFFFF)

Define Documentation

#define TIM_TS_ETRF ((uint32_t)0x0070)

Definition at line 892 of file stm32l4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR0 ((uint32_t)0x0000)

Definition at line 885 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR1 ((uint32_t)0x0010)

Definition at line 886 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR2 ((uint32_t)0x0020)

Definition at line 887 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR3 ((uint32_t)0x0030)

Definition at line 888 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_NONE ((uint32_t)0xFFFF)

Definition at line 893 of file stm32l4xx_hal_tim.h.

#define TIM_TS_TI1F_ED ((uint32_t)0x0040)

Definition at line 889 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI1FP1 ((uint32_t)0x0050)

Definition at line 890 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI2FP2 ((uint32_t)0x0060)

Definition at line 891 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Trigger Polarity

Defines
TIM Trigger Polarity
TIM Exported Constants

Defines

#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 905 of file stm32l4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 904 of file stm32l4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx trigger sources

Definition at line 901 of file stm32l4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx trigger sources

Definition at line 902 of file stm32l4xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 903 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Trigger Prescaler

Defines
TIM Trigger Prescaler
TIM Exported Constants

Defines

#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 913 of file stm32l4xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Trigger: Capture performed once every 2 events.

Definition at line 914 of file stm32l4xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Trigger: Capture performed once every 4 events.

Definition at line 915 of file stm32l4xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Trigger: Capture performed once every 8 events.

Definition at line 916 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM TI1 Input Selection

Defines
TIM TI1 Input Selection
TIM Exported Constants

Defines

#define | TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Define Documentation

#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)

Definition at line 924 of file stm32l4xx_hal_tim.h.

#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Definition at line 925 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM DMA Burst Length

Defines
TIM DMA Burst Length
TIM Exported Constants

Defines

#define | TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
#define | TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
#define | TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
#define | TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
#define | TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
#define | TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
#define | TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
#define | TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
#define | TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
#define | TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
#define | TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
#define | TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
#define | TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
#define | TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
#define | TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
#define | TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
#define | TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
#define | TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)

Define Documentation

#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)

Definition at line 942 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)

Definition at line 943 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)

Definition at line 944 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)

Definition at line 945 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)

Definition at line 946 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)

Definition at line 947 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)

Definition at line 948 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)

Definition at line 949 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)

Definition at line 950 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)

Definition at line 933 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)

Definition at line 934 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)

Definition at line 935 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)

Definition at line 936 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)

Definition at line 937 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)

Definition at line 938 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)

Definition at line 939 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)

Definition at line 940 of file stm32l4xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)

Definition at line 941 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM DMA Handle Index

Defines
TIM DMA Handle Index
TIM Exported Constants

Defines

#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x1)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x2)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x3)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x4)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x6)

Define Documentation

#define TIM_DMA_ID_CC1 ((uint16_t) 0x1)

Index of the DMA handle used for Capture/Compare 1 DMA requests

Definition at line 959 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC2 ((uint16_t) 0x2)

Index of the DMA handle used for Capture/Compare 2 DMA requests

Definition at line 960 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC3 ((uint16_t) 0x3)

Index of the DMA handle used for Capture/Compare 3 DMA requests

Definition at line 961 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC4 ((uint16_t) 0x4)

Index of the DMA handle used for Capture/Compare 4 DMA requests

Definition at line 962 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5)

Index of the DMA handle used for Commutation DMA requests

Definition at line 963 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6)

Index of the DMA handle used for Trigger DMA requests

Definition at line 964 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0)

Index of the DMA handle used for Update DMA requests

Definition at line 958 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Capture/Compare Channel State

Defines
TIM Capture/Compare Channel State
TIM Exported Constants

Defines

#define | TIM_CCx_ENABLE ((uint32_t)0x0001)
#define | TIM_CCx_DISABLE ((uint32_t)0x0000)
#define | TIM_CCxN_ENABLE ((uint32_t)0x0004)
#define | TIM_CCxN_DISABLE ((uint32_t)0x0000)

Define Documentation

#define TIM_CCx_DISABLE ((uint32_t)0x0000)

Definition at line 973 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

#define TIM_CCx_ENABLE ((uint32_t)0x0001)

Definition at line 972 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), and HAL_TIMEx_HallSensor_Start_IT().

#define TIM_CCxN_DISABLE ((uint32_t)0x0000)

Definition at line 975 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CCxN_ENABLE ((uint32_t)0x0004)

Definition at line 974 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Break System

Defines
TIM Break System
TIM Exported Constants

Defines

#define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define | TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL
#define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Define Documentation

#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17

Definition at line 983 of file stm32l4xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17

Definition at line 986 of file stm32l4xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 984 of file stm32l4xx_hal_tim.h.

#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL

Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17

Definition at line 985 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Exported Macros

Defines
TIM Exported Macros
TIM

Defines

#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.

Define Documentation

#define __HAL_TIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the specified TIM interrupt flag.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__FLAG__,: specifies the TIM interrupt flag to clear. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 5 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1165 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

Clear the TIM interrupt pending bits.

Parameters:
__HANDLE__,: TIM handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1198 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
                            { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
                            { \
                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
                            } \
                          } \
                        } while(0)

Disable the TIM peripheral.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 1026 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

Disable the specified DMA request.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__DMA__,: specifies the TIM DMA request to disable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
  • TIM_DMA_BREAK: Break DMA request
Return values:
None

Definition at line 1117 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define __HAL_TIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

Disable the specified TIM interrupt.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__INTERRUPT__,: specifies the TIM interrupt source to disable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1085 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

Enable the TIM peripheral.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 1012 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER |= (__DMA__))

Enable the specified DMA request.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__DMA__,: specifies the TIM DMA request to enable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
  • TIM_DMA_BREAK: Break DMA request
Return values:
None

Definition at line 1101 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define __HAL_TIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

Enable the specified TIM interrupt.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__INTERRUPT__,: specifies the TIM interrupt source to enable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1068 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start_IT(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_GET_AUTORELOAD ( __HANDLE__ ) ((__HANDLE__)->Instance->ARR)

Get the TIM Autoreload Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 1251 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_GET_CLOCKDIVISION ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

Get the TIM Clock Division value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 1276 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_GET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
 ((__HANDLE__)->Instance->CCR6))

Get the TIM Capture Compare Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channel associated with the capture compare register This parameter can be one of the following values:
  • TIM_CHANNEL_1: get capture/compare 1 register value
  • TIM_CHANNEL_2: get capture/compare 2 register value
  • TIM_CHANNEL_3: get capture/compare 3 register value
  • TIM_CHANNEL_4: get capture/compare 4 register value
  • TIM_CHANNEL_5: get capture/compare 5 register value
  • TIM_CHANNEL_6: get capture/compare 6 register value
Return values:
None

Definition at line 1354 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNT)

Get the TIM Counter Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 1231 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

Check whether the specified TIM interrupt flag is set or not.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__FLAG__,: specifies the TIM interrupt flag to check. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 5 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1141 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_GET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)

Get the TIM Input Capture prescaler on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: get input capture 1 prescaler value
  • TIM_CHANNEL_2: get input capture 2 prescaler value
  • TIM_CHANNEL_3: get input capture 3 prescaler value
  • TIM_CHANNEL_4: get input capture 4 prescaler value
Return values:
None

Definition at line 1313 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified TIM interrupt source is enabled or not.

Parameters:
__HANDLE__,: TIM handle
__INTERRUPT__,: specifies the TIM interrupt source to check. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
The state of TIM_IT (SET or RESET).

Definition at line 1182 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_IS_TIM_COUNTING_DOWN ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))

Indicates whether or not the TIM Counter is used as downcounter.

Parameters:
__HANDLE__,: TIM handle.
Return values:
False (Counter used as upcounter) or True (Counter used as downcounter)
Note:
This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.

Definition at line 1207 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_MOE_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
                          { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
                            { \
                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
                            } \
                            } \
                        } while(0)

Disable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled

Definition at line 1043 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_MOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

Enable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 1019 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)

Reset TIM handle state.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 1005 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_SET_AUTORELOAD | ( | __HANDLE__,
 |  | __AUTORELOAD__
 | ) |
Value:
do{                                                    \
                              (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
                              (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
                          } while(0)

Set the TIM Autoreload Register value on runtime without calling another time any Init function.

Parameters:
__HANDLE__,: TIM handle.
__AUTORELOAD__,: specifies the Counter register new value.
Return values:
None

Definition at line 1240 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
do{                                                                     \
          TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
          TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
        }while(0)

Set the TIM Capture x input polarity on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__POLARITY__,: Polarity for TIx source
  • TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  • TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Return values:
None

Definition at line 1402 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_SET_CLOCKDIVISION | ( | __HANDLE__,
 |  | __CKD__
 | ) |
Value:
do{                                                    \
                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
                          } while(0)

Set the TIM Clock Division value on runtime without calling another time any Init function.

Parameters:
__HANDLE__,: TIM handle.
__CKD__,: specifies the clock division value. This parameter can be one of the following value:
  • TIM_CLOCKDIVISION_DIV1
  • TIM_CLOCKDIVISION_DIV2
  • TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 1264 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_SET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __COMPARE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))

Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
__COMPARE__,: specifies the Capture Compare register new value.
Return values:
None

Definition at line 1333 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->CNT = (__COUNTER__))

Set the TIM Counter Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
__COUNTER__,: specifies the Counter register new value.
Return values:
None

Definition at line 1224 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_SET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
do{                                                    \
                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
                          } while(0)

Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__ICPSC__,: specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1296 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_SET_PRESCALER | ( | __HANDLE__,
 |  | __PRESC__
 | ) | ((__HANDLE__)->Instance->PSC = (__PRESC__))

Set the TIM Prescaler on runtime.

Parameters:
__HANDLE__,: TIM handle.
__PRESC__,: specifies the Prescaler new value.
Return values:
None

Definition at line 1216 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_URS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))

Reset the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__,: TIM handle.
Note:
When the USR bit of the TIMx_CR1 register is reset, any of the following events generate an update interrupt or DMA request (if enabled): _ Counter overflow underflow _ Setting the UG bit _ Update generation through the slave mode controller
Return values:
None

Definition at line 1384 of file stm32l4xx_hal_tim.h.

#define __HAL_TIM_URS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))

Set the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__,: TIM handle.
Note:
When the USR bit of the TIMx_CR1 register is set, only counter overflow/underflow generates an update interrupt or DMA request (if enabled)
Return values:
None

Definition at line 1370 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Define Documentation

#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

Definition at line 1419 of file stm32l4xx_hal_tim.h.

#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Definition at line 1420 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))

Definition at line 1587 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK2_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))

Definition at line 1584 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK2_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK2_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK2_DISABLE))

Definition at line 1581 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_FILTER ( __BRKFILTER__ ) ((__BRKFILTER__) <= 0xF)

Definition at line 1572 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))

Definition at line 1578 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK_DISABLE))

Definition at line 1575 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_SYSTEM ( __CONFIG__ )
Value:
(((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                 || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                 || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)  || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))

Definition at line 1700 of file stm32l4xx_hal_tim.h.

#define IS_TIM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))

Definition at line 1511 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and TIM_CCxChannelCmd().

#define IS_TIM_CLEARINPUT_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xF)

Definition at line 1558 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

Definition at line 1550 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))

Definition at line 1553 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_SOURCE ( __MODE__ )
Value:
(((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))

Definition at line 1431 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLOCKDIVISION_DIV ( __DIV__ )
Value:
(((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))

Definition at line 1470 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_CLOCKFILTER ( ICFILTER ) ((ICFILTER) <= 0xF)

Definition at line 1548 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))

Definition at line 1537 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))

Definition at line 1543 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKSOURCE ( __CLOCK__ )
Value:
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))

Definition at line 1526 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_COMPLEMENTARY_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_3))

Definition at line 1522 of file stm32l4xx_hal_tim.h.

#define IS_TIM_COUNTER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_COUNTERMODE_UP)              || \
                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))

Definition at line 1464 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_DEADTIME ( __DEADTIME__ ) ((__DEADTIME__) <= 0xFF)

Definition at line 1698 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_DMA_BASE ( __BASE__ )
Value:
(((__BASE__) == TIM_DMABASE_CR1)   || \
                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
                                   ((__BASE__) == TIM_DMABASE_SR)    || \
                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
                                   ((__BASE__) == TIM_DMABASE_OR1)   || \
                                   ((__BASE__) == TIM_DMABASE_OR2)   || \
                                   ((__BASE__) == TIM_DMABASE_OR3))

Definition at line 1435 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))

Definition at line 1677 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))

Definition at line 1509 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define IS_TIM_ENCODER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_ENCODERMODE_TI1) || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI12))

Definition at line 1505 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_EVENT_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))

Definition at line 1461 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_GenerateEvent().

#define IS_TIM_FAST_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCFAST_DISABLE) || \
                                            ((__STATE__) == TIM_OCFAST_ENABLE))

Definition at line 1474 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_GROUPCH5 ( __OCREF__ ) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))

Definition at line 1590 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_GroupChannel5().

#define IS_TIM_IC_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xF)

Definition at line 1696 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

Definition at line 1489 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_ICPSC_DIV1) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))

Definition at line 1497 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))

Definition at line 1493 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_IC_ConfigChannel().

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
                                                               ((__SELECTION__) == TIM_TS_NONE))

Definition at line 1654 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), and HAL_TIMEx_ConfigCommutationEvent_IT().

#define IS_TIM_LOCK_LEVEL ( __LEVEL__ )
Value:
(((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))

Definition at line 1567 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_MSM_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))

Definition at line 1619 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_OC_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_TIMING)             || \
                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))

Definition at line 1636 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel().

#define IS_TIM_OC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))

Definition at line 1477 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_OCIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))

Definition at line 1483 of file stm32l4xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OCN_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))

Definition at line 1480 of file stm32l4xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OCNIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCNIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))

Definition at line 1486 of file stm32l4xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OPM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2))

Definition at line 1519 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

#define IS_TIM_OPM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OPMODE_SINGLE) || \
                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))

Definition at line 1502 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init().

#define IS_TIM_OSSI_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSI_ENABLE) || \
                                            ((__STATE__) == TIM_OSSI_DISABLE))

Definition at line 1564 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OSSR_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSR_ENABLE) || \
                                            ((__STATE__) == TIM_OSSR_DISABLE))

Definition at line 1561 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_PWM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_PWM1)               || \
                                         ((__MODE__) == TIM_OCMODE_PWM2)               || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))

Definition at line 1629 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_SLAVE_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

Definition at line 1622 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TI1SELECTION ( __TI1SELECTION__ )
Value:
(((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

Definition at line 1674 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_ConfigTI1Input().

#define IS_TIM_TRGO2_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO2_RESET)                        || \
                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))

Definition at line 1601 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRGO_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO_RESET)  || \
                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC4REF))

Definition at line 1592 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRIGGER_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
                                                 ((__SELECTION__) == TIM_TS_ETRF))

Definition at line 1645 of file stm32l4xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TRIGGERFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xF)

Definition at line 1672 of file stm32l4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

Definition at line 1661 of file stm32l4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))

Definition at line 1667 of file stm32l4xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_RESET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))

Definition at line 1723 of file stm32l4xx_hal_tim.h.

#define TIM_RESET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))

Definition at line 1711 of file stm32l4xx_hal_tim.h.

#define TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))

Definition at line 1717 of file stm32l4xx_hal_tim.h.

#define TIM_SET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))

Definition at line 1705 of file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Functions

void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 2 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Function Documentation

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx,: TIM peripheral
Structure,: TIM Base configuration structure
Return values:
None

Definition at line 4714 of file stm32l4xx_hal_tim.c.

References TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
ChannelState,: specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
Return values:
None

Definition at line 5610 of file stm32l4xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

void TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4652 of file stm32l4xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4620 of file stm32l4xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4606 of file stm32l4xx_hal_tim.c.

References HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx to select the TIM peripheral
TIM_ExtTRGPrescaler,: The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
TIM_ExtTRGPolarity,: The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
ExtTRGFilter,: External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 5580 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), and TIM_SlaveTimer_SetConfig().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Ouput Compare 2 configuration.

Parameters:
TIMx to select the TIM peripheral
OC_Config,: The ouput configuration structure
Return values:
None

Definition at line 4833 of file stm32l4xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_2.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPolarity_Rising
  • TIM_ICPolarity_Falling
  • TIM_ICPolarity_BothEdge
TIM_ICSelection,: specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter,: Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5286 of file stm32l4xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM

Modules | Functions
TIM
STM32L4xx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Exported Functions
TIM Exported Types
TIM Exported Constants
TIM Exported Macros
TIM Private Constants
TIM Private Macros
TIM Private Functions

Functions

static void TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)

Detailed Description

TIM HAL module driver.

Function Documentation

static void TIM_SlaveTimer_SetConfig | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  | [static]

Definition at line 5142 of file stm32l4xx_hal_tim.c.

References assert_param, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_ETR_SetConfig(), TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Timer Hall Sensor functions

Functions
Extended Timer Hall Sensor functions
TIM Extended Exported Functions

Timer Hall Sensor functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.

Detailed Description

Timer Hall Sensor functions.

  ==============================================================================
                      ##### Timer Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit ( TIM_HandleTypeDef * htim )

DeInitialize the TIM Hall Sensor interface.

Parameters:
htim,: TIM Hall Sensor handle
Return values:
HAL status

Definition at line 235 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspDeInit(), TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_HallSensor_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Hall Sensor Interface and initialize the associated handle.

Parameters:
htim,: TIM Encoder Interface handle
sConfig,: TIM Hall Sensor configuration structure
Return values:
HAL status

Definition at line 157 of file stm32l4xx_hal_tim_ex.c.

References assert_param, TIM_Base_InitTypeDef::ClockDivision, TIM_HallSensor_InitTypeDef::Commutation_Delay, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspInit(), TIM_HallSensor_InitTypeDef::IC1Filter, TIM_HallSensor_InitTypeDef::IC1Polarity, TIM_HallSensor_InitTypeDef::IC1Prescaler, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, TIM_HandleTypeDef::Lock, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_ICSELECTION_TRC, TIM_OC2_SetConfig(), TIM_OCFAST_DISABLE, TIM_OCIDLESTATE_RESET, TIM_OCMODE_PWM2, TIM_OCNIDLESTATE_RESET, TIM_OCNPOLARITY_HIGH, TIM_OCPOLARITY_HIGH, TIM_SLAVEMODE_RESET, TIM_TI1_SetConfig(), TIM_TRGO_OC2REF, and TIM_TS_TI1F_ED.

void HAL_TIMEx_HallSensor_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitialize TIM Hall Sensor MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 277 of file stm32l4xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_DeInit().

void HAL_TIMEx_HallSensor_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Hall Sensor MSP.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 262 of file stm32l4xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_Init().

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface.

Parameters:
htim : TIM Hall Sensor handle
Return values:
HAL status

Definition at line 292 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim : TIM Hall Sensor handle
pData,: The destination Buffer address.
Length,: The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 384 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_DMA_CC1, TIM_DMA_ID_CC1, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim : TIM Hall Sensor handle
Return values:
HAL status

Definition at line 334 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Hall sensor Interface.

Parameters:
htim : TIM Hall Sensor handle
Return values:
HAL status

Definition at line 313 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 431 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_DMA_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 358 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Timer Complementary Output Compare functions

Functions
Extended Timer Complementary Output Compare functions
TIM Extended Exported Functions

Timer Complementary Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary Output Compare functions.

  ==============================================================================
              ##### Timer Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare/PWM.
    (+) Stop the Complementary Output Compare/PWM.
    (+) Start the Complementary Output Compare/PWM and enable interrupts.
    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OCN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation on the complementary output.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 487 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 689 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM OC handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 547 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 517 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 804 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 614 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Timer Complementary PWM functions

Functions
Extended Timer Complementary PWM functions
TIM Extended Exported Functions

Timer Complementary PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary PWM functions.

  ==============================================================================
                 ##### Timer Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.
    (+) Start the Complementary Input Capture measurement.
    (+) Stop the Complementary Input Capture.
    (+) Start the Complementary Input Capture and enable interrupts.
    (+) Stop the Complementary Input Capture and disable interrupts.
    (+) Start the Complementary Input Capture and enable DMA transfers.
    (+) Stop the Complementary Input Capture and disable DMA transfers.
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 904 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData,: The source Buffer address.
Length,: The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1106 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 963 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 933 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1221 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1030 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Timer Complementary One Pulse functions

Functions
Extended Timer Complementary One Pulse functions
TIM Extended Exported Functions

Timer Complementary One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Detailed Description

Timer Complementary One Pulse functions.

  ==============================================================================
                ##### Timer Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation on the complementary output.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1308 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1362 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation on the complementary output.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1333 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1393 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
TIM Extended Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Configure the commutation event in case of use of the Hall sensor interface.
      (+) Configure Output channels for OC and PWM mode.

      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master synchronization.
      (+) Configure timer remapping capabilities.
      (+) Enable or disable channel grouping

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_BreakDeadTimeConfigTypeDef * | sBreakDeadTimeConfig
 | ) |  |

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

Parameters:
htim,: TIM handle
sBreakDeadTimeConfig,: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Return values:
HAL status

Definition at line 1671 of file stm32l4xx_hal_tim_ex.c.

References assert_param, TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput, BDTR_BK2F_SHIFT, BDTR_BKF_SHIFT, TIM_BreakDeadTimeConfigTypeDef::Break2Filter, TIM_BreakDeadTimeConfigTypeDef::Break2Polarity, TIM_BreakDeadTimeConfigTypeDef::Break2State, TIM_BreakDeadTimeConfigTypeDef::BreakFilter, TIM_BreakDeadTimeConfigTypeDef::BreakPolarity, TIM_BreakDeadTimeConfigTypeDef::BreakState, TIM_BreakDeadTimeConfigTypeDef::DeadTime, TIM_HandleTypeDef::Instance, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK2_POLARITY, IS_TIM_BREAK2_STATE, IS_TIM_BREAK_FILTER, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_DEADTIME, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BreakDeadTimeConfigTypeDef::LockLevel, TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode, and TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode.

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BreakInput,
 |  | TIMEx_BreakInputConfigTypeDef * | sBreakInputConfig
 | ) |  |

Configures the break input source.

Parameters:
htim,: TIM handle.
BreakInput,: Break input to configure This parameter can be one of the following values:
  • TIM_BREAKINPUT_BRK: Timer break input
  • TIM_BREAKINPUT_BRK2: Timer break 2 input
sBreakInputConfig,: Break input source configuration
Return values:
HAL status

Definition at line 1753 of file stm32l4xx_hal_tim_ex.c.

References assert_param, TIMEx_BreakInputConfigTypeDef::Enable, TIM_HandleTypeDef::Instance, IS_TIM_BREAKINPUT, IS_TIM_BREAKINPUTSOURCE, IS_TIM_BREAKINPUTSOURCE_POLARITY, IS_TIM_BREAKINPUTSOURCE_STATE, TIMEx_BreakInputConfigTypeDef::Polarity, TIMEx_BreakInputConfigTypeDef::Source, TIM_BREAKINPUT_BRK, TIM_BREAKINPUT_BRK2, TIM_BREAKINPUTSOURCE_BKIN, TIM_BREAKINPUTSOURCE_COMP1, TIM_BREAKINPUTSOURCE_COMP2, and TIM_BREAKINPUTSOURCE_DFSDM1.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim,: TIM handle
InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource : the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1464 of file stm32l4xx_hal_tim_ex.c.

References assert_param, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with DMA.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
The user should configure the DMA in his own software, in This function only the COMDE bit is set
Parameters:
htim,: TIM handle
InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource : the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1566 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_DMA, assert_param, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_DMA_ID_COMMUTATION, TIM_DMAError(), TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with interrupt.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim,: TIM handle
InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource : the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1513 of file stm32l4xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_GroupChannel5 | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channels
 | ) |  |

Group channel 5 and channel 1, 2 or 3.

Parameters:
htim,: TIM handle.
Channels,: specifies the reference signal(s) the OC5REF is combined with. This parameter can be any combination of the following values: TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
Return values:
HAL status

Definition at line 2094 of file stm32l4xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_GROUPCH5, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_MasterConfigTypeDef * | sMasterConfig
 | ) |  |

Configures the TIM in master mode.

Parameters:
htim,: TIM handle.
sMasterConfig,: pointer to a TIM_MasterConfigTypeDef structure that contains the selected trigger output (TRGO) and the Master/Slave mode.
Return values:
HAL status

Definition at line 1610 of file stm32l4xx_hal_tim_ex.c.

References assert_param, TIM_HandleTypeDef::Instance, IS_TIM_MSM_STATE, IS_TIM_TRGO2_SOURCE, IS_TIM_TRGO_SOURCE, TIM_MasterConfigTypeDef::MasterOutputTrigger, TIM_MasterConfigTypeDef::MasterOutputTrigger2, and TIM_MasterConfigTypeDef::MasterSlaveMode.

HAL_StatusTypeDef HAL_TIMEx_RemapConfig | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Remap
 | ) |  |

Configures the TIMx Remapping input capabilities.

Parameters:
htim,: TIM handle.
Remap,: specifies the TIM remapping source.

For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):

field1 can have the following values:

  • TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
  • TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
  • TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
  • TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3

field2 can have the following values:

  • TIM_TIM1_ETR_ADC3_NONE: TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)
  • TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
  • TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
  • TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3

field3 can have the following values:

  • TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
  • TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output

field4 can have the following values:

  • TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
  • TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
    Note:
    When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
    field1 can have the following values:
  • TIM_TIM2_ITR1_TIM8_TRGO: TIM2_ITR1 is connected to TIM8_TRGO
  • TIM_TIM2_ITR1_OTG_FS_SOF: TIM2_ITR1 is connected to OTG_FS SOF

field2 can have the following values:

  • TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
  • TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
  • TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
  • TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output

field3 can have the following values:

  • TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
  • TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
  • TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
  • TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output For TIM3, the parameter is a combination 2 fields(field1 | field2):

field1 can have the following values:

  • TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
  • TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
  • TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
  • TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output

field2 can have the following values:

  • TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO
  • TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output

For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):

field1 can have the following values:

  • TIM_TIM8_ETR_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)
  • TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
  • TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
  • TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3

field2 can have the following values:

  • TIM_TIM8_ETR_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)
  • TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
  • TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
  • TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3

field3 can have the following values:

  • TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
  • TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output

field4 can have the following values:

  • TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output
  • TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output
    Note:
    When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant
    For TIM15, the parameter is a combination of 3 fields (field1 | field2):

field1 can have the following values:

  • TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
  • TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE

field2 can have the following values:

  • TIM_TIM15_ENCODERMODE_NONE: No redirection
  • TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
  • TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
  • TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
  • TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
  • TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
  • TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
  • TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt

For TIM17, the parameter can have the following values:

  • TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
  • TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock)
  • TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
  • TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
Return values:
HAL status

Definition at line 2044 of file stm32l4xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_REMAP, TIM_HandleTypeDef::State, and TIMx_ETRSEL_MASK.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Callbacks functions

Functions
Extended Callbacks functions
TIM Extended Exported Functions

Extended Callbacks functions. More...

Functions

__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.

Detailed Description

Extended Callbacks functions.

  ==============================================================================
                    ##### Extended Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extended TIM callback functions:
    (+) Timer Commutation callback
    (+) Timer Break callback

Function Documentation

void HAL_TIMEx_BreakCallback ( TIM_HandleTypeDef * htim )

Hall Break detection callback in non-blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 2158 of file stm32l4xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIMEx_CommutationCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed callback in non-blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 2143 of file stm32l4xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), and TIMEx_DMACommutationCplt().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Peripheral State functions

Functions
Extended Peripheral State functions
TIM Extended Exported Functions

Extended Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.

Detailed Description

Extended Peripheral State functions.

  ==============================================================================
                ##### Extended Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Hall Sensor interface handle state.

Parameters:
htim,: TIM Hall Sensor handle
Return values:
HAL state

Definition at line 2192 of file stm32l4xx_hal_tim_ex.c.

References TIM_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Extended Exported Functions

Modules | Functions
TIM Extended Exported Functions
TIMEx

Modules

Extended Timer Hall Sensor functions

Timer Hall Sensor functions.

Extended Timer Complementary Output Compare functions

Timer Complementary Output Compare functions.

Extended Timer Complementary PWM functions

Timer Complementary PWM functions.

Extended Timer Complementary One Pulse functions

Timer Complementary One Pulse functions.

Extended Peripheral Control functions

Peripheral Control functions.

Extended Callbacks functions

Extended Callbacks functions.

Extended Peripheral State functions

Extended Peripheral State functions.

Functions

void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.

Function Documentation

static void TIM_CCxNChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelNState
 | ) |  | [static]

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx to select the TIM peripheral
Channel,: specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
ChannelNState,: specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
Return values:
None

Definition at line 2227 of file stm32l4xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 2206 of file stm32l4xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM_HallSensor_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HallSensor_InitTypeDef Struct Reference
TIM Extended Exported Types

TIM Hall sensor Configuration Structure definition. More...

#include <stm32l4xx_hal_tim_ex.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | Commutation_Delay

Detailed Description

TIM Hall sensor Configuration Structure definition.

Definition at line 66 of file stm32l4xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_HallSensor_InitTypeDef::Commutation_Delay

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 78 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 75 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 69 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 72 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim_ex.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIMEx_BreakInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIMEx_BreakInputConfigTypeDef Struct Reference
TIM Extended Exported Types

TIM Break/Break2 input configuration. More...

#include <stm32l4xx_hal_tim_ex.h>

Data Fields

uint32_t | Source
uint32_t | Enable
uint32_t | Polarity

Detailed Description

TIM Break/Break2 input configuration.

Definition at line 85 of file stm32l4xx_hal_tim_ex.h.

Field Documentation

uint32_t TIMEx_BreakInputConfigTypeDef::Enable

Specifies whether or not the break input source is enabled. This parameter can be a value of TIM Extended Break input source enabling

Definition at line 88 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Polarity

Specifies the break input source polarity. This parameter can be a value of TIM Extended Break input polarity Not relevant when analog watchdog output of the DFSDM1 used as break input source

Definition at line 90 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Source

Specifies the source of the timer break input. This parameter can be a value of TIM Extended Break input source

Definition at line 86 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tim_ex.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Extended Remapping

Defines
TIM Extended Remapping
TIM Extended Exported Constants

Defines

#define | TIM_TIM1_ETR_ADC1_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define | TIM_TIM1_ETR_ADC1_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | TIM_TIM1_ETR_ADC1_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | TIM_TIM1_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define | TIM_TIM1_ETR_ADC3_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM1_ETR_ADC3_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */
#define | TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */
#define | TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */
#define | TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */
#define | TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */
#define | TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */
#define | TIM_TIM2_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM2_ETR is connected to GPIO */
#define | TIM_TIM2_ETR_LSE (TIM2_OR1_ETR1_RMP) /* !< TIM2_ETR is connected to LSE */
#define | TIM_TIM2_ETR_COMP1 (TIM2_OR2_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 output */
#define | TIM_TIM2_ETR_COMP2 (TIM2_OR2_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 output */
#define | TIM_TIM2_TI4_GPIO ((uint32_t)(0x00000000)) /* !< TIM2 TI4 is connected to GPIO */
#define | TIM_TIM2_TI4_COMP1 (TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to COMP1 output */
#define | TIM_TIM2_TI4_COMP2 (TIM2_OR1_TI4_RMP_1) /* !< TIM2 TI4 is connected to COMP2 output */
#define | TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
#define | TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */
#define | TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */
#define | TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */
#define | TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
#define | TIM_TIM3_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM3_ETR is connected to GPIO */
#define | TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */
#define | TIM_TIM8_ETR_ADC2_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define | TIM_TIM8_ETR_ADC2_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define | TIM_TIM8_ETR_ADC2_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define | TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define | TIM_TIM8_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define | TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */
#define | TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */
#define | TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */
#define | TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */
#define | TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */
#define | TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */
#define | TIM_TIM15_ENCODERMODE_NONE ((uint32_t)(0x00000000)) /* !< No redirection */
#define | TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#define | TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#define | TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#define | TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */
#define | TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */
#define | TIM_TIM16_TI1_LSE (TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to LSE */
#define | TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
#define | TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */
#define | TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */
#define | TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */
#define | TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */

Define Documentation

#define TIM_TIM15_ENCODERMODE_NONE ((uint32_t)(0x00000000)) /* !< No redirection */

Definition at line 162 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */

Definition at line 163 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */

Definition at line 165 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */

Definition at line 166 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */

Definition at line 160 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */

Definition at line 161 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */

Definition at line 168 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_LSE (TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to LSE */

Definition at line 170 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */

Definition at line 169 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */

Definition at line 171 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */

Definition at line 178 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */

Definition at line 180 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */

Definition at line 181 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */

Definition at line 179 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */

Definition at line 109 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD2 */

Definition at line 110 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */

Definition at line 111 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/

Definition at line 108 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD1 */

Definition at line 114 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1) /* !< TIM1_ETR is connected to ADC3 AWD2 */

Definition at line 115 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */

Definition at line 116 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/

Definition at line 113 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */

Definition at line 120 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */

Definition at line 121 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */

Definition at line 119 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */

Definition at line 118 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP1 (TIM2_OR2_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 output */

Definition at line 132 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP2 (TIM2_OR2_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 output */

Definition at line 133 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM2_ETR is connected to GPIO */

Definition at line 130 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM2_ETR_LSE (TIM2_OR1_ETR1_RMP) /* !< TIM2_ETR is connected to LSE */

Definition at line 131 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */

Definition at line 124 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */

Definition at line 123 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP1 (TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to COMP1 output */

Definition at line 135 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */

Definition at line 137 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP2 (TIM2_OR1_TI4_RMP_1) /* !< TIM2 TI4 is connected to COMP2 output */

Definition at line 136 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM2_TI4_GPIO ((uint32_t)(0x00000000)) /* !< TIM2 TI4 is connected to GPIO */

Definition at line 134 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */

Definition at line 144 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM3_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM3_ETR is connected to GPIO */

Definition at line 143 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */

Definition at line 140 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */

Definition at line 142 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */

Definition at line 141 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */

Definition at line 139 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */

Definition at line 148 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1) /* !< TIM8_ETR is connected to ADC2 AWD2 */

Definition at line 149 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */

Definition at line 150 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC2_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/

Definition at line 147 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */

Definition at line 152 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */

Definition at line 153 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */

Definition at line 154 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/

Definition at line 151 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */

Definition at line 157 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */

Definition at line 158 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */

Definition at line 156 of file stm32l4xx_hal_tim_ex.h.

#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */

Definition at line 155 of file stm32l4xx_hal_tim_ex.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Extended Break input

Defines
TIM Extended Break input
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */
#define | TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */

Define Documentation

#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */

Definition at line 190 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */

Definition at line 191 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Extended Break input source

Defines
TIM Extended Break input source
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */
#define | TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */

Define Documentation

#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */

Definition at line 199 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */

Definition at line 200 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */

Definition at line 201 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */

Definition at line 203 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Extended Break input source enabling

Defines
TIM Extended Break input source enabling
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
#define | TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */

Define Documentation

#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */

Definition at line 212 of file stm32l4xx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */

Definition at line 213 of file stm32l4xx_hal_tim_ex.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Extended Break input polarity

Defines
TIM Extended Break input polarity
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */

Define Documentation

#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */

Definition at line 222 of file stm32l4xx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */

Definition at line 221 of file stm32l4xx_hal_tim_ex.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Extended Exported Macros

TIM Extended Exported Macros
TIMEx
Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Extended Private Macros

Defines
TIM Extended Private Macros
TIMEx

Defines

#define | IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)

Define Documentation

#define IS_TIM_BREAKINPUT ( __BREAKINPUT__ )
Value:
(((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))

Definition at line 248 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))

Definition at line 252 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))

Definition at line 265 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))

Definition at line 262 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_REMAP ( __REMAP__ ) (((__REMAP__) <= (uint32_t)0x0001C01F))

Definition at line 246 of file stm32l4xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_RemapConfig().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIMEx Private Functions

Functions
TIMEx Private Functions
TIMEx

Functions

void TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Function Documentation

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 2206 of file stm32l4xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIMEx

Modules | Defines
TIMEx
STM32L4xx_HAL_Driver

TIM Extended HAL module driver. More...

Modules

TIM Extended Exported Functions
TIM Extended Exported Types
TIM Extended Exported Constants
TIM Extended Exported Macros
TIM Extended Private Macros
TIMEx Private Functions

Defines

#define | BDTR_BKF_SHIFT (16)
#define | BDTR_BK2F_SHIFT (20)
#define | TIMx_ETRSEL_MASK ((uint32_t)0x0001C000)

Detailed Description

TIM Extended HAL module driver.

Define Documentation

#define BDTR_BK2F_SHIFT (20)

Definition at line 115 of file stm32l4xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define BDTR_BKF_SHIFT (16)

Definition at line 114 of file stm32l4xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define TIMx_ETRSEL_MASK ((uint32_t)0x0001C000)

Definition at line 116 of file stm32l4xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_RemapConfig().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_TSC_Init (TSC_HandleTypeDef *htsc)
Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_TSC_DeInit (TSC_HandleTypeDef *htsc)
Deinitialize the TSC peripheral registers to their default reset values.
__weak void | HAL_TSC_MspInit (TSC_HandleTypeDef *htsc)
Initialize the TSC MSP.
__weak void | HAL_TSC_MspDeInit (TSC_HandleTypeDef *htsc)
DeInitialize the TSC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the TSC.
      (+) De-initialize the TSC.

Function Documentation

HAL_StatusTypeDef HAL_TSC_DeInit ( TSC_HandleTypeDef * htsc )

Deinitialize the TSC peripheral registers to their default reset values.

Parameters:
htsc,: TSC handle
Return values:
HAL status

Definition at line 298 of file stm32l4xx_hal_tsc.c.

References assert_param, HAL_TSC_MspDeInit(), HAL_TSC_STATE_BUSY, HAL_TSC_STATE_RESET, TSC_HandleTypeDef::Instance, and TSC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TSC_Init ( TSC_HandleTypeDef * htsc )

Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.

Parameters:
htsc,: TSC handle
Return values:
HAL status

Definition at line 210 of file stm32l4xx_hal_tsc.c.

References TSC_InitTypeDef::AcquisitionMode, assert_param, TSC_InitTypeDef::ChannelIOs, TSC_InitTypeDef::CTPulseHighLength, TSC_InitTypeDef::CTPulseLowLength, HAL_TSC_MspInit(), HAL_TSC_STATE_BUSY, HAL_TSC_STATE_READY, HAL_TSC_STATE_RESET, TSC_HandleTypeDef::Init, TSC_HandleTypeDef::Instance, TSC_InitTypeDef::IODefaultMode, IS_TSC_ACQ_MODE, IS_TSC_CTPH, IS_TSC_CTPL, IS_TSC_IODEF, IS_TSC_MCE_IT, IS_TSC_MCV, IS_TSC_PG_PRESC, IS_TSC_SS, IS_TSC_SS_PRESC, IS_TSC_SSD, IS_TSC_SYNC_POL, TSC_HandleTypeDef::Lock, TSC_InitTypeDef::MaxCountInterrupt, TSC_InitTypeDef::MaxCountValue, TSC_InitTypeDef::PulseGeneratorPrescaler, TSC_InitTypeDef::SamplingIOs, TSC_InitTypeDef::ShieldIOs, TSC_InitTypeDef::SpreadSpectrum, TSC_InitTypeDef::SpreadSpectrumDeviation, TSC_InitTypeDef::SpreadSpectrumPrescaler, TSC_HandleTypeDef::State, TSC_InitTypeDef::SynchroPinPolarity, TSC_extract_groups(), TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IT_EOA, and TSC_IT_MCE.

void HAL_TSC_MspDeInit ( TSC_HandleTypeDef * htsc )

DeInitialize the TSC MSP.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 347 of file stm32l4xx_hal_tsc.c.

Referenced by HAL_TSC_DeInit().

void HAL_TSC_MspInit ( TSC_HandleTypeDef * htsc )

Initialize the TSC MSP.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 331 of file stm32l4xx_hal_tsc.c.

Referenced by HAL_TSC_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
Exported Functions

Input and Output operation functions. More...

Functions

HAL_StatusTypeDef | HAL_TSC_Start (TSC_HandleTypeDef *htsc)
Start the acquisition.
HAL_StatusTypeDef | HAL_TSC_Start_IT (TSC_HandleTypeDef *htsc)
Start the acquisition in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_Stop (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in polling mode.
HAL_StatusTypeDef | HAL_TSC_Stop_IT (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_PollForAcquisition (TSC_HandleTypeDef *htsc)
Start acquisition and wait until completion.
TSC_GroupStatusTypeDef | HAL_TSC_GroupGetStatus (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition status for a group.
uint32_t | HAL_TSC_GroupGetValue (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition measure for a group.

Detailed Description

Input and Output operation functions.

 ===============================================================================
             ##### IO Operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start acquisition in polling mode.
      (+) Start acquisition in interrupt mode.
      (+) Stop conversion in polling mode.
      (+) Stop conversion in interrupt mode.
      (+) Poll for acquisition completed.
      (+) Get group acquisition status.
      (+) Get group acquisition value.

Function Documentation

TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus | ( | TSC_HandleTypeDef * | htsc,
 |  | uint32_t | gx_index
 | ) |  |

Get the acquisition status for a group.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
gx_index,: Index of the group
Return values:
Group status

Definition at line 581 of file stm32l4xx_hal_tsc.c.

References __HAL_TSC_GET_GROUP_STATUS, assert_param, TSC_HandleTypeDef::Instance, and IS_TSC_GROUP_INDEX.

uint32_t HAL_TSC_GroupGetValue | ( | TSC_HandleTypeDef * | htsc,
 |  | uint32_t | gx_index
 | ) |  |

Get the acquisition measure for a group.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
gx_index,: Index of the group
Return values:
Acquisition measure

Definition at line 598 of file stm32l4xx_hal_tsc.c.

References assert_param, TSC_HandleTypeDef::Instance, and IS_TSC_GROUP_INDEX.

HAL_StatusTypeDef HAL_TSC_PollForAcquisition ( TSC_HandleTypeDef * htsc )

Start acquisition and wait until completion.

Note:
There is no need of a timeout parameter as the max count error is already managed by the TSC peripheral.
Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL state

Definition at line 554 of file stm32l4xx_hal_tsc.c.

References assert_param, HAL_TSC_GetState(), HAL_TSC_STATE_BUSY, and TSC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TSC_Start ( TSC_HandleTypeDef * htsc )

Start the acquisition.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status

Definition at line 386 of file stm32l4xx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_DISABLE_IT, __HAL_TSC_SET_IODEF_INFLOAT, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_START_ACQ, assert_param, HAL_TSC_STATE_BUSY, TSC_HandleTypeDef::Init, TSC_HandleTypeDef::Instance, TSC_InitTypeDef::IODefaultMode, TSC_HandleTypeDef::State, TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IODEF_OUT_PP_LOW, TSC_IT_EOA, and TSC_IT_MCE.

HAL_StatusTypeDef HAL_TSC_Start_IT ( TSC_HandleTypeDef * htsc )

Start the acquisition in interrupt mode.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status.

Definition at line 429 of file stm32l4xx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_DISABLE_IT, __HAL_TSC_ENABLE_IT, __HAL_TSC_SET_IODEF_INFLOAT, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_START_ACQ, assert_param, HAL_TSC_STATE_BUSY, TSC_HandleTypeDef::Init, TSC_HandleTypeDef::Instance, TSC_InitTypeDef::IODefaultMode, IS_TSC_MCE_IT, TSC_InitTypeDef::MaxCountInterrupt, TSC_HandleTypeDef::State, TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IODEF_OUT_PP_LOW, TSC_IT_EOA, and TSC_IT_MCE.

HAL_StatusTypeDef HAL_TSC_Stop ( TSC_HandleTypeDef * htsc )

Stop the acquisition previously launched in polling mode.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status

Definition at line 483 of file stm32l4xx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_STOP_ACQ, assert_param, HAL_TSC_STATE_READY, TSC_HandleTypeDef::Instance, TSC_HandleTypeDef::State, TSC_FLAG_EOA, and TSC_FLAG_MCE.

HAL_StatusTypeDef HAL_TSC_Stop_IT ( TSC_HandleTypeDef * htsc )

Stop the acquisition previously launched in interrupt mode.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status

Definition at line 516 of file stm32l4xx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_DISABLE_IT, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_STOP_ACQ, assert_param, HAL_TSC_STATE_READY, TSC_HandleTypeDef::Instance, TSC_HandleTypeDef::State, TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IT_EOA, and TSC_IT_MCE.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TSC_IOConfig (TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
Configure TSC IOs.
HAL_StatusTypeDef | HAL_TSC_IODischarge (TSC_HandleTypeDef *htsc, uint32_t choice)
Discharge TSC IOs.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure TSC IOs
      (+) Discharge TSC IOs

Function Documentation

HAL_StatusTypeDef HAL_TSC_IOConfig | ( | TSC_HandleTypeDef * | htsc,
 |  | TSC_IOConfigTypeDef * | config
 | ) |  |

Configure TSC IOs.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
config,: pointer to the configuration structure.
Return values:
HAL status

Definition at line 633 of file stm32l4xx_hal_tsc.c.

References __HAL_TSC_STOP_ACQ, assert_param, TSC_IOConfigTypeDef::ChannelIOs, TSC_HandleTypeDef::Instance, TSC_IOConfigTypeDef::SamplingIOs, TSC_IOConfigTypeDef::ShieldIOs, and TSC_extract_groups().

HAL_StatusTypeDef HAL_TSC_IODischarge | ( | TSC_HandleTypeDef * | htsc,
 |  | uint32_t | choice
 | ) |  |

Discharge TSC IOs.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
choice,: enable or disable
Return values:
HAL status

Definition at line 670 of file stm32l4xx_hal_tsc.c.

References __HAL_TSC_SET_IODEF_INFLOAT, __HAL_TSC_SET_IODEF_OUTPPLOW, assert_param, and TSC_HandleTypeDef::Instance.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_TSC_StateTypeDef HAL_TSC_GetState (TSC_HandleTypeDef *htsc)
Return the TSC handle state.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get TSC state.

Function Documentation

HAL_TSC_StateTypeDef HAL_TSC_GetState ( TSC_HandleTypeDef * htsc )

Return the TSC handle state.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL state

Definition at line 719 of file stm32l4xx_hal_tsc.c.

References __HAL_TSC_GET_FLAG, assert_param, HAL_TSC_STATE_BUSY, HAL_TSC_STATE_ERROR, HAL_TSC_STATE_READY, TSC_HandleTypeDef::Instance, TSC_HandleTypeDef::State, TSC_FLAG_EOA, and TSC_FLAG_MCE.

Referenced by HAL_TSC_PollForAcquisition().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
Exported Functions

Functions

void | HAL_TSC_IRQHandler (TSC_HandleTypeDef *htsc)
Handle TSC interrupt request.
__weak void | HAL_TSC_ConvCpltCallback (TSC_HandleTypeDef *htsc)
Acquisition completed callback in non-blocking mode.
__weak void | HAL_TSC_ErrorCallback (TSC_HandleTypeDef *htsc)
Error callback in non-blocking mode.

Function Documentation

void HAL_TSC_ConvCpltCallback ( TSC_HandleTypeDef * htsc )

Acquisition completed callback in non-blocking mode.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 798 of file stm32l4xx_hal_tsc.c.

Referenced by HAL_TSC_IRQHandler().

void HAL_TSC_ErrorCallback ( TSC_HandleTypeDef * htsc )

Error callback in non-blocking mode.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 814 of file stm32l4xx_hal_tsc.c.

Referenced by HAL_TSC_IRQHandler().

void HAL_TSC_IRQHandler ( TSC_HandleTypeDef * htsc )

Handle TSC interrupt request.

Parameters:
htsc,: pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 761 of file stm32l4xx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_GET_FLAG, assert_param, HAL_TSC_ConvCpltCallback(), HAL_TSC_ErrorCallback(), HAL_TSC_STATE_ERROR, HAL_TSC_STATE_READY, TSC_HandleTypeDef::Instance, TSC_HandleTypeDef::State, TSC_FLAG_EOA, and TSC_FLAG_MCE.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Private Functions

Functions
Private Functions
TSC

Functions

static uint32_t TSC_extract_groups (uint32_t iomask)
Utility function used to set the acquired groups mask.

Function Documentation

static uint32_t TSC_extract_groups ( uint32_t iomask ) [static]

Utility function used to set the acquired groups mask.

Parameters:
iomask,: Channels IOs mask
Return values:
Acquired groups mask

Definition at line 842 of file stm32l4xx_hal_tsc.c.

References TSC_NB_OF_GROUPS.

Referenced by HAL_TSC_Init(), and HAL_TSC_IOConfig().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TSC Exported Types

Data Structures | Enumerations
TSC Exported Types
TSC

Data Structures

struct | TSC_InitTypeDef
TSC init structure definition. More...
struct | TSC_IOConfigTypeDef
TSC IOs configuration structure definition. More...
struct | TSC_HandleTypeDef
TSC handle Structure definition. More...

Enumerations

enum | HAL_TSC_StateTypeDef { HAL_TSC_STATE_RESET = 0x00, HAL_TSC_STATE_READY = 0x01, HAL_TSC_STATE_BUSY = 0x02, HAL_TSC_STATE_ERROR = 0x03 }
TSC state structure definition. More...
enum | TSC_GroupStatusTypeDef { TSC_GROUP_ONGOING = 0x00, TSC_GROUP_COMPLETED = 0x01 }
TSC group status structure definition. More...

Enumeration Type Documentation

enum HAL_TSC_StateTypeDef

TSC state structure definition.

Enumerator:
HAL_TSC_STATE_RESET

TSC registers have their reset value

HAL_TSC_STATE_READY

TSC registers are initialized or acquisition is completed with success

HAL_TSC_STATE_BUSY

TSC initialization or acquisition is on-going

HAL_TSC_STATE_ERROR

Acquisition is completed with max count error

Definition at line 65 of file stm32l4xx_hal_tsc.h.

enum TSC_GroupStatusTypeDef

TSC group status structure definition.

Enumerator:
TSC_GROUP_ONGOING

Acquisition on group is on-going or not started

TSC_GROUP_COMPLETED

Acquisition on group is completed with success (no max count error)

Definition at line 76 of file stm32l4xx_hal_tsc.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TSC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TSC_InitTypeDef Struct Reference
TSC Exported Types

TSC init structure definition. More...

#include <stm32l4xx_hal_tsc.h>

Data Fields

uint32_t | CTPulseHighLength
uint32_t | CTPulseLowLength
uint32_t | SpreadSpectrum
uint32_t | SpreadSpectrumDeviation
uint32_t | SpreadSpectrumPrescaler
uint32_t | PulseGeneratorPrescaler
uint32_t | MaxCountValue
uint32_t | IODefaultMode
uint32_t | SynchroPinPolarity
uint32_t | AcquisitionMode
uint32_t | MaxCountInterrupt
uint32_t | ChannelIOs
uint32_t | ShieldIOs
uint32_t | SamplingIOs

Detailed Description

TSC init structure definition.

Definition at line 85 of file stm32l4xx_hal_tsc.h.

Field Documentation

uint32_t TSC_InitTypeDef::AcquisitionMode

Acquisition mode This parameter can be a value of Acquisition Mode

Definition at line 105 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::ChannelIOs

Channel IOs mask

Definition at line 109 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::CTPulseHighLength

Charge-transfer high pulse length This parameter can be a value of CTPulse High Length

Definition at line 87 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::CTPulseLowLength

Charge-transfer low pulse length This parameter can be a value of CTPulse Low Length

Definition at line 89 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::IODefaultMode

IO default mode This parameter can be a value of IO Default Mode

Definition at line 101 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), and HAL_TSC_Start_IT().

uint32_t TSC_InitTypeDef::MaxCountInterrupt

Max count interrupt activation This parameter can be set to ENABLE or DISABLE.

Definition at line 107 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), and HAL_TSC_Start_IT().

uint32_t TSC_InitTypeDef::MaxCountValue

Max count value This parameter can be a value of Max Count Value

Definition at line 99 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::PulseGeneratorPrescaler

Pulse generator prescaler This parameter can be a value of Pulse Generator Prescaler

Definition at line 97 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SamplingIOs

Sampling IOs mask

Definition at line 111 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::ShieldIOs

Shield IOs mask

Definition at line 110 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SpreadSpectrum

Spread spectrum activation This parameter can be a value of CTPulse Low Length

Definition at line 91 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SpreadSpectrumDeviation

Spread spectrum deviation This parameter must be a number between Min_Data = 0 and Max_Data = 127

Definition at line 93 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SpreadSpectrumPrescaler

Spread spectrum prescaler This parameter can be a value of Spread Spectrum Prescaler

Definition at line 95 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SynchroPinPolarity

Synchro pin polarity This parameter can be a value of Synchro Pin Polarity

Definition at line 103 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tsc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TSC_IOConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TSC_IOConfigTypeDef Struct Reference
TSC Exported Types

TSC IOs configuration structure definition. More...

#include <stm32l4xx_hal_tsc.h>

Data Fields

uint32_t | ChannelIOs
uint32_t | ShieldIOs
uint32_t | SamplingIOs

Detailed Description

TSC IOs configuration structure definition.

Definition at line 117 of file stm32l4xx_hal_tsc.h.

Field Documentation

uint32_t TSC_IOConfigTypeDef::ChannelIOs

Channel IOs mask

Definition at line 119 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig().

uint32_t TSC_IOConfigTypeDef::SamplingIOs

Sampling IOs mask

Definition at line 121 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig().

uint32_t TSC_IOConfigTypeDef::ShieldIOs

Shield IOs mask

Definition at line 120 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tsc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TSC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TSC_HandleTypeDef Struct Reference
TSC Exported Types

TSC handle Structure definition. More...

#include <stm32l4xx_hal_tsc.h>

Data Fields

TSC_TypeDef * | Instance
TSC_InitTypeDef Init
__IO HAL_TSC_StateTypeDef | State
HAL_LockTypeDef | Lock

Detailed Description

TSC handle Structure definition.

Definition at line 127 of file stm32l4xx_hal_tsc.h.

Field Documentation

TSC_InitTypeDef TSC_HandleTypeDef::Init

Initialization parameters

Definition at line 130 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), and HAL_TSC_Start_IT().

TSC_TypeDef* TSC_HandleTypeDef::Instance

Register base address

Definition at line 129 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_DeInit(), HAL_TSC_GetState(), HAL_TSC_GroupGetStatus(), HAL_TSC_GroupGetValue(), HAL_TSC_Init(), HAL_TSC_IOConfig(), HAL_TSC_IODischarge(), HAL_TSC_IRQHandler(), HAL_TSC_PollForAcquisition(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

HAL_LockTypeDef TSC_HandleTypeDef::Lock

Lock feature

Definition at line 132 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

__IO HAL_TSC_StateTypeDef TSC_HandleTypeDef::State

Peripheral state

Definition at line 131 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_DeInit(), HAL_TSC_GetState(), HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_tsc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CTPulse High Length

Defines
CTPulse High Length
TSC Exported Constants

Defines

#define | TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28))
#define | TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28))
#define | TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28))
#define | TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28))
#define | TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28))
#define | TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28))
#define | TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28))
#define | TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28))
#define | TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28))
#define | TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
#define | TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
#define | TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
#define | TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
#define | TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
#define | TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
#define | TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))

Define Documentation

#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))

Definition at line 156 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))

Definition at line 157 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))

Definition at line 158 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))

Definition at line 159 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))

Definition at line 160 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))

Definition at line 161 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))

Definition at line 162 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28))

Definition at line 147 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28))

Definition at line 148 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28))

Definition at line 149 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28))

Definition at line 150 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28))

Definition at line 151 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28))

Definition at line 152 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28))

Definition at line 153 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28))

Definition at line 154 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28))

Definition at line 155 of file stm32l4xx_hal_tsc.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CTPulse Low Length

Defines
CTPulse Low Length
TSC Exported Constants

Defines

#define | TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24))
#define | TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24))
#define | TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24))
#define | TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24))
#define | TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24))
#define | TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24))
#define | TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24))
#define | TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24))
#define | TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24))
#define | TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
#define | TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
#define | TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
#define | TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
#define | TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
#define | TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
#define | TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))

Define Documentation

#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))

Definition at line 179 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))

Definition at line 180 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))

Definition at line 181 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))

Definition at line 182 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))

Definition at line 183 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))

Definition at line 184 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))

Definition at line 185 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24))

Definition at line 170 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24))

Definition at line 171 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24))

Definition at line 172 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24))

Definition at line 173 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24))

Definition at line 174 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24))

Definition at line 175 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24))

Definition at line 176 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24))

Definition at line 177 of file stm32l4xx_hal_tsc.h.

#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24))

Definition at line 178 of file stm32l4xx_hal_tsc.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Spread Spectrum Prescaler

Defines
Spread Spectrum Prescaler
TSC Exported Constants

Defines

#define | TSC_SS_PRESC_DIV1 ((uint32_t)0)
#define | TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)

Define Documentation

#define TSC_SS_PRESC_DIV1 ((uint32_t)0)

Definition at line 193 of file stm32l4xx_hal_tsc.h.

#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)

Definition at line 194 of file stm32l4xx_hal_tsc.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Pulse Generator Prescaler

Defines
Pulse Generator Prescaler
TSC Exported Constants

Defines

#define | TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))
#define | TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))
#define | TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12))
#define | TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12))
#define | TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12))
#define | TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))
#define | TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))
#define | TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))

Define Documentation

#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))

Definition at line 202 of file stm32l4xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))

Definition at line 209 of file stm32l4xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12))

Definition at line 206 of file stm32l4xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))

Definition at line 203 of file stm32l4xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))

Definition at line 207 of file stm32l4xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12))

Definition at line 204 of file stm32l4xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))

Definition at line 208 of file stm32l4xx_hal_tsc.h.

#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12))

Definition at line 205 of file stm32l4xx_hal_tsc.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Max Count Value

Defines
Max Count Value
TSC Exported Constants

Defines

#define | TSC_MCV_255 ((uint32_t)(0 << 5))
#define | TSC_MCV_511 ((uint32_t)(1 << 5))
#define | TSC_MCV_1023 ((uint32_t)(2 << 5))
#define | TSC_MCV_2047 ((uint32_t)(3 << 5))
#define | TSC_MCV_4095 ((uint32_t)(4 << 5))
#define | TSC_MCV_8191 ((uint32_t)(5 << 5))
#define | TSC_MCV_16383 ((uint32_t)(6 << 5))

Define Documentation

#define TSC_MCV_1023 ((uint32_t)(2 << 5))

Definition at line 219 of file stm32l4xx_hal_tsc.h.

#define TSC_MCV_16383 ((uint32_t)(6 << 5))

Definition at line 223 of file stm32l4xx_hal_tsc.h.

#define TSC_MCV_2047 ((uint32_t)(3 << 5))

Definition at line 220 of file stm32l4xx_hal_tsc.h.

#define TSC_MCV_255 ((uint32_t)(0 << 5))

Definition at line 217 of file stm32l4xx_hal_tsc.h.

#define TSC_MCV_4095 ((uint32_t)(4 << 5))

Definition at line 221 of file stm32l4xx_hal_tsc.h.

#define TSC_MCV_511 ((uint32_t)(1 << 5))

Definition at line 218 of file stm32l4xx_hal_tsc.h.

#define TSC_MCV_8191 ((uint32_t)(5 << 5))

Definition at line 222 of file stm32l4xx_hal_tsc.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO Default Mode

Defines
IO Default Mode
TSC Exported Constants

Defines

#define | TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
#define | TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)

Define Documentation

#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)

Definition at line 232 of file stm32l4xx_hal_tsc.h.

#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)

Definition at line 231 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Start(), and HAL_TSC_Start_IT().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Synchro Pin Polarity

Defines
Synchro Pin Polarity
TSC Exported Constants

Defines

#define | TSC_SYNC_POLARITY_FALLING ((uint32_t)0)
#define | TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)

Define Documentation

#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0)

Definition at line 240 of file stm32l4xx_hal_tsc.h.

#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)

Definition at line 241 of file stm32l4xx_hal_tsc.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Acquisition Mode

Defines
Acquisition Mode
TSC Exported Constants

Defines

#define | TSC_ACQ_MODE_NORMAL ((uint32_t)0)
#define | TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)

Define Documentation

#define TSC_ACQ_MODE_NORMAL ((uint32_t)0)

Definition at line 249 of file stm32l4xx_hal_tsc.h.

#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)

Definition at line 250 of file stm32l4xx_hal_tsc.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO Mode

Defines
IO Mode
TSC Exported Constants

Defines

#define | TSC_IOMODE_UNUSED ((uint32_t)0)
#define | TSC_IOMODE_CHANNEL ((uint32_t)1)
#define | TSC_IOMODE_SHIELD ((uint32_t)2)
#define | TSC_IOMODE_SAMPLING ((uint32_t)3)

Define Documentation

#define TSC_IOMODE_CHANNEL ((uint32_t)1)

Definition at line 259 of file stm32l4xx_hal_tsc.h.

#define TSC_IOMODE_SAMPLING ((uint32_t)3)

Definition at line 261 of file stm32l4xx_hal_tsc.h.

#define TSC_IOMODE_SHIELD ((uint32_t)2)

Definition at line 260 of file stm32l4xx_hal_tsc.h.

#define TSC_IOMODE_UNUSED ((uint32_t)0)

Definition at line 258 of file stm32l4xx_hal_tsc.h.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Interrupts definition

Defines
Interrupts definition
TSC Exported Constants

Defines

#define | TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
#define | TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)

Define Documentation

#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)

Definition at line 269 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), HAL_TSC_Start_IT(), and HAL_TSC_Stop_IT().

#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)

Definition at line 270 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), HAL_TSC_Start_IT(), and HAL_TSC_Stop_IT().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Flags definition

Defines
Flags definition
TSC Exported Constants

Defines

#define | TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
#define | TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)

Define Documentation

#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)

Definition at line 278 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_GetState(), HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)

Definition at line 279 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_GetState(), HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Group definition

Defines
Group definition
TSC Exported Constants

Defines

#define | TSC_NB_OF_GROUPS (8)
#define | TSC_GROUP1 ((uint32_t)0x00000001)
#define | TSC_GROUP2 ((uint32_t)0x00000002)
#define | TSC_GROUP3 ((uint32_t)0x00000004)
#define | TSC_GROUP4 ((uint32_t)0x00000008)
#define | TSC_GROUP5 ((uint32_t)0x00000010)
#define | TSC_GROUP6 ((uint32_t)0x00000020)
#define | TSC_GROUP7 ((uint32_t)0x00000040)
#define | TSC_GROUP8 ((uint32_t)0x00000080)
#define | TSC_ALL_GROUPS ((uint32_t)0x000000FF)
#define | TSC_GROUP1_IDX ((uint32_t)0)
#define | TSC_GROUP2_IDX ((uint32_t)1)
#define | TSC_GROUP3_IDX ((uint32_t)2)
#define | TSC_GROUP4_IDX ((uint32_t)3)
#define | TSC_GROUP5_IDX ((uint32_t)4)
#define | TSC_GROUP6_IDX ((uint32_t)5)
#define | TSC_GROUP7_IDX ((uint32_t)6)
#define | TSC_GROUP8_IDX ((uint32_t)7)
#define | TSC_GROUP1_IO1 ((uint32_t)0x00000001)
#define | TSC_GROUP1_IO2 ((uint32_t)0x00000002)
#define | TSC_GROUP1_IO3 ((uint32_t)0x00000004)
#define | TSC_GROUP1_IO4 ((uint32_t)0x00000008)
#define | TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
#define | TSC_GROUP2_IO1 ((uint32_t)0x00000010)
#define | TSC_GROUP2_IO2 ((uint32_t)0x00000020)
#define | TSC_GROUP2_IO3 ((uint32_t)0x00000040)
#define | TSC_GROUP2_IO4 ((uint32_t)0x00000080)
#define | TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
#define | TSC_GROUP3_IO1 ((uint32_t)0x00000100)
#define | TSC_GROUP3_IO2 ((uint32_t)0x00000200)
#define | TSC_GROUP3_IO3 ((uint32_t)0x00000400)
#define | TSC_GROUP3_IO4 ((uint32_t)0x00000800)
#define | TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
#define | TSC_GROUP4_IO1 ((uint32_t)0x00001000)
#define | TSC_GROUP4_IO2 ((uint32_t)0x00002000)
#define | TSC_GROUP4_IO3 ((uint32_t)0x00004000)
#define | TSC_GROUP4_IO4 ((uint32_t)0x00008000)
#define | TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
#define | TSC_GROUP5_IO1 ((uint32_t)0x00010000)
#define | TSC_GROUP5_IO2 ((uint32_t)0x00020000)
#define | TSC_GROUP5_IO3 ((uint32_t)0x00040000)
#define | TSC_GROUP5_IO4 ((uint32_t)0x00080000)
#define | TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
#define | TSC_GROUP6_IO1 ((uint32_t)0x00100000)
#define | TSC_GROUP6_IO2 ((uint32_t)0x00200000)
#define | TSC_GROUP6_IO3 ((uint32_t)0x00400000)
#define | TSC_GROUP6_IO4 ((uint32_t)0x00800000)
#define | TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
#define | TSC_GROUP7_IO1 ((uint32_t)0x01000000)
#define | TSC_GROUP7_IO2 ((uint32_t)0x02000000)
#define | TSC_GROUP7_IO3 ((uint32_t)0x04000000)
#define | TSC_GROUP7_IO4 ((uint32_t)0x08000000)
#define | TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
#define | TSC_GROUP8_IO1 ((uint32_t)0x10000000)
#define | TSC_GROUP8_IO2 ((uint32_t)0x20000000)
#define | TSC_GROUP8_IO3 ((uint32_t)0x40000000)
#define | TSC_GROUP8_IO4 ((uint32_t)0x80000000)
#define | TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)
#define | TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)

Define Documentation

#define TSC_ALL_GROUPS ((uint32_t)0x000000FF)

Definition at line 297 of file stm32l4xx_hal_tsc.h.

#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)

Definition at line 356 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP1 ((uint32_t)0x00000001)

Definition at line 289 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)

Definition at line 312 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP1_IDX ((uint32_t)0)

Definition at line 299 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP1_IO1 ((uint32_t)0x00000001)

Definition at line 308 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP1_IO2 ((uint32_t)0x00000002)

Definition at line 309 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP1_IO3 ((uint32_t)0x00000004)

Definition at line 310 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP1_IO4 ((uint32_t)0x00000008)

Definition at line 311 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP2 ((uint32_t)0x00000002)

Definition at line 290 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)

Definition at line 318 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP2_IDX ((uint32_t)1)

Definition at line 300 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP2_IO1 ((uint32_t)0x00000010)

Definition at line 314 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP2_IO2 ((uint32_t)0x00000020)

Definition at line 315 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP2_IO3 ((uint32_t)0x00000040)

Definition at line 316 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP2_IO4 ((uint32_t)0x00000080)

Definition at line 317 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP3 ((uint32_t)0x00000004)

Definition at line 291 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)

Definition at line 324 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP3_IDX ((uint32_t)2)

Definition at line 301 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP3_IO1 ((uint32_t)0x00000100)

Definition at line 320 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP3_IO2 ((uint32_t)0x00000200)

Definition at line 321 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP3_IO3 ((uint32_t)0x00000400)

Definition at line 322 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP3_IO4 ((uint32_t)0x00000800)

Definition at line 323 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP4 ((uint32_t)0x00000008)

Definition at line 292 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)

Definition at line 330 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP4_IDX ((uint32_t)3)

Definition at line 302 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP4_IO1 ((uint32_t)0x00001000)

Definition at line 326 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP4_IO2 ((uint32_t)0x00002000)

Definition at line 327 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP4_IO3 ((uint32_t)0x00004000)

Definition at line 328 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP4_IO4 ((uint32_t)0x00008000)

Definition at line 329 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP5 ((uint32_t)0x00000010)

Definition at line 293 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)

Definition at line 336 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP5_IDX ((uint32_t)4)

Definition at line 303 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP5_IO1 ((uint32_t)0x00010000)

Definition at line 332 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP5_IO2 ((uint32_t)0x00020000)

Definition at line 333 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP5_IO3 ((uint32_t)0x00040000)

Definition at line 334 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP5_IO4 ((uint32_t)0x00080000)

Definition at line 335 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP6 ((uint32_t)0x00000020)

Definition at line 294 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)

Definition at line 342 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP6_IDX ((uint32_t)5)

Definition at line 304 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP6_IO1 ((uint32_t)0x00100000)

Definition at line 338 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP6_IO2 ((uint32_t)0x00200000)

Definition at line 339 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP6_IO3 ((uint32_t)0x00400000)

Definition at line 340 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP6_IO4 ((uint32_t)0x00800000)

Definition at line 341 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP7 ((uint32_t)0x00000040)

Definition at line 295 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)

Definition at line 348 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP7_IDX ((uint32_t)6)

Definition at line 305 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP7_IO1 ((uint32_t)0x01000000)

Definition at line 344 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP7_IO2 ((uint32_t)0x02000000)

Definition at line 345 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP7_IO3 ((uint32_t)0x04000000)

Definition at line 346 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP7_IO4 ((uint32_t)0x08000000)

Definition at line 347 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP8 ((uint32_t)0x00000080)

Definition at line 296 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)

Definition at line 354 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP8_IDX ((uint32_t)7)

Definition at line 306 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP8_IO1 ((uint32_t)0x10000000)

Definition at line 350 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP8_IO2 ((uint32_t)0x20000000)

Definition at line 351 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP8_IO3 ((uint32_t)0x40000000)

Definition at line 352 of file stm32l4xx_hal_tsc.h.

#define TSC_GROUP8_IO4 ((uint32_t)0x80000000)

Definition at line 353 of file stm32l4xx_hal_tsc.h.

#define TSC_NB_OF_GROUPS (8)

Definition at line 287 of file stm32l4xx_hal_tsc.h.

Referenced by TSC_extract_groups().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TSC Exported Macros

Defines
TSC Exported Macros
TSC

Defines

#define | __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
Reset TSC handle state.
#define | __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
Enable the TSC peripheral.
#define | __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
Disable the TSC peripheral.
#define | __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
Start acquisition.
#define | __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
Stop acquisition.
#define | __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
Set IO default mode to output push-pull low.
#define | __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
Set IO default mode to input floating.
#define | __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
Set synchronization polarity to falling edge.
#define | __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
Set synchronization polarity to rising edge and high level.
#define | __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable TSC interrupt.
#define | __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
Disable TSC interrupt.
#define | __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified TSC interrupt source is enabled or not.
#define | __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified TSC flag is set or not.
#define | __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the TSC's pending flag.
#define | __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
Enable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Open analog switch on a group of IOs.
#define | __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
Close analog switch on a group of IOs.
#define | __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
Enable a group of IOs in channel mode.
#define | __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable a group of channel IOs.
#define | __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
Enable a group of IOs in sampling mode.
#define | __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable a group of sampling IOs.
#define | __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
Enable acquisition groups.
#define | __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
Disable acquisition groups.
#define | __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
Gets acquisition group status.

Define Documentation

#define __HAL_TSC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the TSC's pending flag.

Parameters:
__HANDLE__,: TSC handle
__FLAG__,: TSC flag
Return values:
None

Definition at line 470 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

#define __HAL_TSC_CLOSE_ANALOG_SWITCH | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))

Close analog switch on a group of IOs.

Parameters:
__HANDLE__,: TSC handle
__GX_IOY_MASK__,: IOs mask
Return values:
None

Definition at line 502 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))

Disable the TSC peripheral.

Parameters:
__HANDLE__,: TSC handle
Return values:
None

Definition at line 389 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_DISABLE_CHANNEL | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))

Disable a group of channel IOs.

Parameters:
__HANDLE__,: TSC handle
__GX_IOY_MASK__,: IOs mask
Return values:
None

Definition at line 518 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_DISABLE_GROUP | ( | __HANDLE__,
 |  | __GX_MASK__
 | ) | ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))

Disable acquisition groups.

Parameters:
__HANDLE__,: TSC handle
__GX_MASK__,: Groups mask
Return values:
None

Definition at line 550 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_DISABLE_HYSTERESIS | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))

Disable schmitt trigger hysteresis on a group of IOs.

Parameters:
__HANDLE__,: TSC handle
__GX_IOY_MASK__,: IOs mask
Return values:
None

Definition at line 486 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))

Disable TSC interrupt.

Parameters:
__HANDLE__,: TSC handle
__INTERRUPT__,: TSC interrupt
Return values:
None

Definition at line 447 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Start(), HAL_TSC_Start_IT(), and HAL_TSC_Stop_IT().

#define __HAL_TSC_DISABLE_SAMPLING | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))

Disable a group of sampling IOs.

Parameters:
__HANDLE__,: TSC handle
__GX_IOY_MASK__,: IOs mask
Return values:
None

Definition at line 534 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)

Enable the TSC peripheral.

Parameters:
__HANDLE__,: TSC handle
Return values:
None

Definition at line 382 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_ENABLE_CHANNEL | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))

Enable a group of IOs in channel mode.

Parameters:
__HANDLE__,: TSC handle
__GX_IOY_MASK__,: IOs mask
Return values:
None

Definition at line 510 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_ENABLE_GROUP | ( | __HANDLE__,
 |  | __GX_MASK__
 | ) | ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))

Enable acquisition groups.

Parameters:
__HANDLE__,: TSC handle
__GX_MASK__,: Groups mask
Return values:
None

Definition at line 542 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_ENABLE_HYSTERESIS | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))

Enable schmitt trigger hysteresis on a group of IOs.

Parameters:
__HANDLE__,: TSC handle
__GX_IOY_MASK__,: IOs mask
Return values:
None

Definition at line 478 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable TSC interrupt.

Parameters:
__HANDLE__,: TSC handle
__INTERRUPT__,: TSC interrupt
Return values:
None

Definition at line 439 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Start_IT().

#define __HAL_TSC_ENABLE_SAMPLING | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))

Enable a group of IOs in sampling mode.

Parameters:
__HANDLE__,: TSC handle
__GX_IOY_MASK__,: IOs mask
Return values:
None

Definition at line 526 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Check whether the specified TSC flag is set or not.

Parameters:
__HANDLE__,: TSC handle
__FLAG__,: TSC flag
Return values:
SET or RESET

Definition at line 462 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_GetState(), and HAL_TSC_IRQHandler().

#define __HAL_TSC_GET_GROUP_STATUS | ( | __HANDLE__,
 |  | __GX_INDEX__
 | ) | ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)

Gets acquisition group status.

Parameters:
__HANDLE__,: TSC Handle
__GX_INDEX__,: Group index
Return values:
SET or RESET

Definition at line 557 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_GroupGetStatus().

#define __HAL_TSC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified TSC interrupt source is enabled or not.

Parameters:
__HANDLE__,: TSC Handle
__INTERRUPT__,: TSC interrupt
Return values:
SET or RESET

Definition at line 454 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_OPEN_ANALOG_SWITCH | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))

Open analog switch on a group of IOs.

Parameters:
__HANDLE__,: TSC handle
__GX_IOY_MASK__,: IOs mask
Return values:
None

Definition at line 494 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)

Reset TSC handle state.

Parameters:
__HANDLE__,: TSC handle
Return values:
None

Definition at line 375 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_SET_IODEF_INFLOAT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)

Set IO default mode to input floating.

Parameters:
__HANDLE__,: TSC handle
Return values:
None

Definition at line 417 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_IODischarge(), HAL_TSC_Start(), and HAL_TSC_Start_IT().

#define __HAL_TSC_SET_IODEF_OUTPPLOW ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))

Set IO default mode to output push-pull low.

Parameters:
__HANDLE__,: TSC handle
Return values:
None

Definition at line 410 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_IODischarge(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

#define __HAL_TSC_SET_SYNC_POL_FALL ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))

Set synchronization polarity to falling edge.

Parameters:
__HANDLE__,: TSC handle
Return values:
None

Definition at line 424 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)

Set synchronization polarity to rising edge and high level.

Parameters:
__HANDLE__,: TSC handle
Return values:
None

Definition at line 431 of file stm32l4xx_hal_tsc.h.

#define __HAL_TSC_START_ACQ ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_START)

Start acquisition.

Parameters:
__HANDLE__,: TSC handle
Return values:
None

Definition at line 396 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Start(), and HAL_TSC_Start_IT().

#define __HAL_TSC_STOP_ACQ ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))

Stop acquisition.

Parameters:
__HANDLE__,: TSC handle
Return values:
None

Definition at line 403 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TSC Private Macros

Defines
TSC Private Macros
TSC

Defines

#define | IS_TSC_CTPH(VAL)
#define | IS_TSC_CTPL(VAL)
#define | IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
#define | IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
#define | IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
#define | IS_TSC_PG_PRESC(VAL)
#define | IS_TSC_MCV(VAL)
#define | IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
#define | IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
#define | IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
#define | IS_TSC_IOMODE(VAL)
#define | IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
#define | IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))

Define Documentation

#define IS_TSC_ACQ_MODE ( VAL ) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))

Definition at line 631 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_CTPH ( VAL )
Value:
(((VAL) == TSC_CTPH_1CYCLE) || \
                          ((VAL) == TSC_CTPH_2CYCLES) || \
                          ((VAL) == TSC_CTPH_3CYCLES) || \
                          ((VAL) == TSC_CTPH_4CYCLES) || \
                          ((VAL) == TSC_CTPH_5CYCLES) || \
                          ((VAL) == TSC_CTPH_6CYCLES) || \
                          ((VAL) == TSC_CTPH_7CYCLES) || \
                          ((VAL) == TSC_CTPH_8CYCLES) || \
                          ((VAL) == TSC_CTPH_9CYCLES) || \
                          ((VAL) == TSC_CTPH_10CYCLES) || \
                          ((VAL) == TSC_CTPH_11CYCLES) || \
                          ((VAL) == TSC_CTPH_12CYCLES) || \
                          ((VAL) == TSC_CTPH_13CYCLES) || \
                          ((VAL) == TSC_CTPH_14CYCLES) || \
                          ((VAL) == TSC_CTPH_15CYCLES) || \
                          ((VAL) == TSC_CTPH_16CYCLES))

Definition at line 570 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_CTPL ( VAL )
Value:
(((VAL) == TSC_CTPL_1CYCLE) || \
                          ((VAL) == TSC_CTPL_2CYCLES) || \
                          ((VAL) == TSC_CTPL_3CYCLES) || \
                          ((VAL) == TSC_CTPL_4CYCLES) || \
                          ((VAL) == TSC_CTPL_5CYCLES) || \
                          ((VAL) == TSC_CTPL_6CYCLES) || \
                          ((VAL) == TSC_CTPL_7CYCLES) || \
                          ((VAL) == TSC_CTPL_8CYCLES) || \
                          ((VAL) == TSC_CTPL_9CYCLES) || \
                          ((VAL) == TSC_CTPL_10CYCLES) || \
                          ((VAL) == TSC_CTPL_11CYCLES) || \
                          ((VAL) == TSC_CTPL_12CYCLES) || \
                          ((VAL) == TSC_CTPL_13CYCLES) || \
                          ((VAL) == TSC_CTPL_14CYCLES) || \
                          ((VAL) == TSC_CTPL_15CYCLES) || \
                          ((VAL) == TSC_CTPL_16CYCLES))

Definition at line 587 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_GROUP_INDEX ( VAL ) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))

Definition at line 640 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_GroupGetStatus(), and HAL_TSC_GroupGetValue().

#define IS_TSC_IODEF ( VAL ) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))

Definition at line 627 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_IOMODE ( VAL )
Value:
(((VAL) == TSC_IOMODE_UNUSED) || \
                            ((VAL) == TSC_IOMODE_CHANNEL) || \
                            ((VAL) == TSC_IOMODE_SHIELD) || \
                            ((VAL) == TSC_IOMODE_SAMPLING))

Definition at line 633 of file stm32l4xx_hal_tsc.h.

#define IS_TSC_MCE_IT ( VAL ) (((VAL) == DISABLE) || ((VAL) == ENABLE))

Definition at line 638 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init(), and HAL_TSC_Start_IT().

#define IS_TSC_MCV ( VAL )
Value:
(((VAL) == TSC_MCV_255) || \
                         ((VAL) == TSC_MCV_511) || \
                         ((VAL) == TSC_MCV_1023) || \
                         ((VAL) == TSC_MCV_2047) || \
                         ((VAL) == TSC_MCV_4095) || \
                         ((VAL) == TSC_MCV_8191) || \
                         ((VAL) == TSC_MCV_16383))

Definition at line 619 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_PG_PRESC ( VAL )
Value:
(((VAL) == TSC_PG_PRESC_DIV1) || \
                              ((VAL) == TSC_PG_PRESC_DIV2) || \
                              ((VAL) == TSC_PG_PRESC_DIV4) || \
                              ((VAL) == TSC_PG_PRESC_DIV8) || \
                              ((VAL) == TSC_PG_PRESC_DIV16) || \
                              ((VAL) == TSC_PG_PRESC_DIV32) || \
                              ((VAL) == TSC_PG_PRESC_DIV64) || \
                              ((VAL) == TSC_PG_PRESC_DIV128))

Definition at line 610 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SS ( VAL ) (((VAL) == DISABLE) || ((VAL) == ENABLE))

Definition at line 604 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SS_PRESC ( VAL ) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))

Definition at line 608 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SSD ( VAL ) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))

Definition at line 606 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SYNC_POL ( VAL ) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))

Definition at line 629 of file stm32l4xx_hal_tsc.h.

Referenced by HAL_TSC_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Private Constants

Defines
UART Private Constants
UART

Defines

#define | UART_CR1_FIELDS
#define | UART_LPUART_BRR_MIN ((uint32_t)0x00000300) /* LPUART BRR minimum authorized value */
#define | UART_LPUART_BRR_MAX ((uint32_t)0x000FFFFF) /* LPUART BRR maximum authorized value */

Define Documentation

#define UART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))

UART or USART CR1 fields of parameters set by UART_SetConfig API

Definition at line 121 of file stm32l4xx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_LPUART_BRR_MAX ((uint32_t)0x000FFFFF) /* LPUART BRR maximum authorized value */

Definition at line 125 of file stm32l4xx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_LPUART_BRR_MIN ((uint32_t)0x00000300) /* LPUART BRR minimum authorized value */

Definition at line 124 of file stm32l4xx_hal_uart.c.

Referenced by UART_SetConfig().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
    and UART multiprocessor mode configuration procedures (details for the procedures
    are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_Init ( UART_HandleTypeDef * huart )

Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 286 of file stm32l4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), and UART_SetConfig().

HAL_StatusTypeDef HAL_LIN_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | BreakDetectLength
 | ) |  |

Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .

Parameters:
huart,: UART handle.
BreakDetectLength,: specifies the LIN break detection length. This parameter can be one of the following values:
  • UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
  • UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
Return values:
HAL status

Definition at line 349 of file stm32l4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_LIN_BREAK_DETECT_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_OVERSAMPLING_8, UART_SetConfig(), UART_WORDLENGTH_8B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_MultiProcessor_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t | Address,
 |  | uint32_t | WakeUpMethod
 | ) |  |

Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart,: UART handle.
Address,: UART node address (4-, 6-, 7- or 8-bit long).
WakeUpMethod,: specifies the UART wakeup method. This parameter can be one of the following values:
  • UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
  • UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
Note:
If the user resorts to idle line detection wake up, the Address parameter is useless and ignored by the initialization function.
If the user resorts to address mark wake up, the address length detection is configured by default to 4 bits only. For the UART to be able to manage 6-, 7- or 8-bit long addresses detection, the API HAL_MultiProcessorEx_AddressLength_Set() must be called after HAL_MultiProcessor_Init().
Return values:
HAL status

Definition at line 436 of file stm32l4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, IS_UART_WAKEUPMETHOD, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR2_ADDRESS_LSB_POS, UART_SetConfig(), and UART_WAKEUPMETHOD_ADDRESSMARK.

HAL_StatusTypeDef HAL_UART_DeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART peripheral.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 500 of file stm32l4xx_hal_uart.c.

References __HAL_UART_DISABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspDeInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_Init ( UART_HandleTypeDef * huart )

Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 223 of file stm32l4xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_HWCONTROL_NONE, and UART_SetConfig().

void HAL_UART_MspDeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART MSP.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 553 of file stm32l4xx_hal_uart.c.

Referenced by HAL_UART_DeInit().

void HAL_UART_MspInit ( UART_HandleTypeDef * huart )

Initialize the UART MSP.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 538 of file stm32l4xx_hal_uart.c.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
UART Exported Functions

UART Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.

Detailed Description

UART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the UART asynchronous
    and Half duplex data transfers.

    (#) There are two mode of transfer:
       (+) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (+) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (+) HAL_UART_Transmit()
        (+) HAL_UART_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (+) HAL_UART_Transmit_IT()
        (+) HAL_UART_Receive_IT()
        (+) HAL_UART_IRQHandler()

    (#) No-Blocking mode API's with DMA are :
        (+) HAL_UART_Transmit_DMA()
        (+) HAL_UART_Receive_DMA()
        (+) HAL_UART_DMAPause()
        (+) HAL_UART_DMAResume()
        (+) HAL_UART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
        (+) HAL_UART_TxHalfCpltCallback()
        (+) HAL_UART_TxCpltCallback()
        (+) HAL_UART_RxHalfCpltCallback()
        (+) HAL_UART_RxCpltCallback()
        (+) HAL_UART_ErrorCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.

    -@- In the Half duplex communication, it is forbidden to run the transmit
        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.

Function Documentation

HAL_StatusTypeDef HAL_UART_DMAPause ( UART_HandleTypeDef * huart )

Pause the DMA Transfer.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 997 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAResume ( UART_HandleTypeDef * huart )

Resume the DMA Transfer.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1030 of file stm32l4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, and UART_CLEAR_OREF.

HAL_StatusTypeDef HAL_UART_DMAStop ( UART_HandleTypeDef * huart )

Stop the DMA Transfer.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1064 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_EndRxTransfer(), and UART_EndTxTransfer().

void HAL_UART_ErrorCallback ( UART_HandleTypeDef * huart )

UART error callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1322 of file stm32l4xx_hal_uart.c.

Referenced by HAL_UART_IRQHandler(), UART_DMAAbortOnError(), and UART_DMAError().

void HAL_UART_IRQHandler ( UART_HandleTypeDef * huart )

Handle UART interrupt request.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1111 of file stm32l4xx_hal_uart.c.

References __HAL_UART_CLEAR_IT, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_ORE, HAL_UART_ERROR_PE, HAL_UART_ErrorCallback(), HAL_UART_STATE_READY, HAL_UARTEx_WakeupCallback(), UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_CLEAR_WUF, UART_DMAAbortOnError(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_Receive_IT(), UART_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Receive | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
huart,: UART handle.
pData,: pointer to data buffer.
Size,: amount of data to be received.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 707 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, UART_FLAG_RXNE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
huart,: UART handle.
pData,: pointer to data buffer.
Size,: amount of data to be received.
Note:
When the UART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
Return values:
HAL status

Definition at line 934 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferSize, UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Parameters:
huart,: UART handle.
pData,: pointer to data buffer.
Size,: amount of data to be received.
Return values:
HAL status

Definition at line 819 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, and UART_MASK_COMPUTATION.

void HAL_UART_RxCpltCallback ( UART_HandleTypeDef * huart )

Rx Transfer completed callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1292 of file stm32l4xx_hal_uart.c.

Referenced by UART_DMAReceiveCplt(), and UART_Receive_IT().

void HAL_UART_RxHalfCpltCallback ( UART_HandleTypeDef * huart )

Rx Half Transfer completed callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1307 of file stm32l4xx_hal_uart.c.

Referenced by UART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_UART_Transmit | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
huart,: UART handle.
pData,: Pointer to data buffer.
Size,: Amount of data to be sent.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 638 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_FLAG_TC, UART_FLAG_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Transmit_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
huart,: UART handle.
pData,: pointer to data buffer.
Size,: amount of data to be sent.
Return values:
HAL status

Definition at line 869 of file stm32l4xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_CLEAR_TCF, UART_DMAError(), UART_DMATransmitCplt(), UART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Transmit_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
huart,: UART handle.
pData,: pointer to data buffer.
Size,: amount of data to be sent.
Return values:
HAL status

Definition at line 778 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, and UART_HandleTypeDef::TxXferSize.

void HAL_UART_TxCpltCallback ( UART_HandleTypeDef * huart )

Tx Transfer completed callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1262 of file stm32l4xx_hal_uart.c.

Referenced by UART_DMATransmitCplt(), and UART_EndTransmit_IT().

void HAL_UART_TxHalfCpltCallback ( UART_HandleTypeDef * huart )

Tx Half Transfer completed callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1277 of file stm32l4xx_hal_uart.c.

Referenced by UART_DMATxHalfCplt().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UART Exported Functions

UART control functions. More...

Functions

HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.

Detailed Description

UART control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the UART.
     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
     (+) UART_SetConfig() API configures the UART peripheral
     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
     (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters
     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
     (+) HAL_LIN_SendBreak() API transmits the break characters

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver ( UART_HandleTypeDef * huart )

Enable the UART receiver and disable the UART transmitter.

Parameters:
huart,: UART handle.
Return values:
HAL status.

Definition at line 1442 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter ( UART_HandleTypeDef * huart )

Enable the UART transmitter and disable the UART receiver.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1418 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LIN_SendBreak ( UART_HandleTypeDef * huart )

Transmit break characters.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1466 of file stm32l4xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_SENDBREAK_REQUEST.

HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode ( UART_HandleTypeDef * huart )

Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1387 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode ( UART_HandleTypeDef * huart )

Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1366 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_CheckIdleState().

void HAL_MultiProcessor_EnterMuteMode ( UART_HandleTypeDef * huart )

Enter UART mute mode (means UART actually enters mute mode).

Note:
To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1408 of file stm32l4xx_hal_uart.c.

References __HAL_UART_SEND_REQ, and UART_MUTE_MODE_REQUEST.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
UART Exported Functions

UART Peripheral State functions. More...

Functions

HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.

Detailed Description

UART Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the UART handle state.
      (+) Return the UART handle error code

Function Documentation

uint32_t HAL_UART_GetError ( UART_HandleTypeDef * huart )

Return the UART handle error code.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 1529 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( UART_HandleTypeDef * huart )

Return the UART handle state.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
HAL state

Definition at line 1514 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::gState, and UART_HandleTypeDef::RxState.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Private Functions

Functions
UART Private Functions
UART

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when call by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Send an amount of data in interrupt mode.
static HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.

Function Documentation

void UART_AdvFeatureConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral advanced features.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1741 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_AdvFeatureInitTypeDef::AutoBaudRateEnable, UART_AdvFeatureInitTypeDef::AutoBaudRateMode, UART_AdvFeatureInitTypeDef::DataInvert, UART_AdvFeatureInitTypeDef::DMADisableonRxError, UART_HandleTypeDef::Instance, IS_UART_ADVFEATURE_AUTOBAUDRATE, IS_UART_ADVFEATURE_AUTOBAUDRATEMODE, IS_UART_ADVFEATURE_DATAINV, IS_UART_ADVFEATURE_DMAONRXERROR, IS_UART_ADVFEATURE_INIT, IS_UART_ADVFEATURE_MSBFIRST, IS_UART_ADVFEATURE_RXINV, IS_UART_ADVFEATURE_SWAP, IS_UART_ADVFEATURE_TXINV, IS_UART_OVERRUN, UART_AdvFeatureInitTypeDef::MSBFirst, UART_AdvFeatureInitTypeDef::OverrunDisable, UART_AdvFeatureInitTypeDef::RxPinLevelInvert, UART_AdvFeatureInitTypeDef::Swap, UART_AdvFeatureInitTypeDef::TxPinLevelInvert, UART_ADVFEATURE_AUTOBAUDRATE_ENABLE, UART_ADVFEATURE_AUTOBAUDRATE_INIT, UART_ADVFEATURE_DATAINVERT_INIT, UART_ADVFEATURE_DMADISABLEONERROR_INIT, UART_ADVFEATURE_MSBFIRST_INIT, UART_ADVFEATURE_RXINVERT_INIT, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT, UART_ADVFEATURE_SWAP_INIT, and UART_ADVFEATURE_TXINVERT_INIT.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_CheckIdleState ( UART_HandleTypeDef * huart )

Check the UART Idle State.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1815 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, and UART_WaitOnFlagUntilTimeout().

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication abort callback, when call by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 2041 of file stm32l4xx_hal_uart.c.

References HAL_UART_ErrorCallback(), UART_HandleTypeDef::RxXferCount, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_IRQHandler().

static void UART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication error callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 2011 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_DMA, HAL_UART_ErrorCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_EndRxTransfer(), and UART_EndTxTransfer().

Referenced by HAL_UART_Receive_DMA(), and HAL_UART_Transmit_DMA().

static void UART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process complete callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 1970 of file stm32l4xx_hal_uart.c.

References HAL_UART_RxCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Instance, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, and UART_HandleTypeDef::RxXferCount.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process half complete callback.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 1999 of file stm32l4xx_hal_uart.c.

References HAL_UART_RxHalfCpltCallback().

Referenced by HAL_UART_Receive_DMA().

static void UART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process complete callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 1929 of file stm32l4xx_hal_uart.c.

References HAL_UART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process half complete callback.

Parameters:
hdma : DMA handle.
Return values:
None

Definition at line 1958 of file stm32l4xx_hal_uart.c.

References HAL_UART_TxHalfCpltCallback().

Referenced by HAL_UART_Transmit_DMA().

static void UART_EndRxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1913 of file stm32l4xx_hal_uart.c.

References HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

Referenced by HAL_UART_DMAStop(), HAL_UART_IRQHandler(), and UART_DMAError().

static HAL_StatusTypeDef UART_EndTransmit_IT ( UART_HandleTypeDef * huart ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2106 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_READY, HAL_UART_TxCpltCallback(), and UART_HandleTypeDef::Instance.

Referenced by HAL_UART_IRQHandler().

static void UART_EndTxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 1898 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

Referenced by HAL_UART_DMAStop(), and UART_DMAError().

static HAL_StatusTypeDef UART_Receive_IT ( UART_HandleTypeDef * huart ) [static]

Receive an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 2127 of file stm32l4xx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_PARITY_NONE, UART_RXDATA_FLUSH_REQUEST, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

HAL_StatusTypeDef UART_SetConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 1550 of file stm32l4xx_hal_uart.c.

References assert_param, UART_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_LPUART_STOPBITS, IS_UART_BAUDRATE, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_MODE, IS_UART_ONE_BIT_SAMPLE, IS_UART_OVERSAMPLING, IS_UART_PARITY, IS_UART_STOPBITS, IS_UART_WORD_LENGTH, LSE_VALUE, UART_InitTypeDef::Mode, UART_InitTypeDef::OneBitSampling, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, UART_InitTypeDef::StopBits, UART_CLOCKSOURCE_HSI, UART_CLOCKSOURCE_LSE, UART_CLOCKSOURCE_PCLK1, UART_CLOCKSOURCE_PCLK2, UART_CLOCKSOURCE_SYSCLK, UART_CLOCKSOURCE_UNDEFINED, UART_CR1_FIELDS, UART_DIV_LPUART, UART_DIV_SAMPLING16, UART_DIV_SAMPLING8, UART_GETCLOCKSOURCE, UART_INSTANCE_LOWPOWER, UART_LPUART_BRR_MAX, UART_LPUART_BRR_MIN, UART_OVERSAMPLING_8, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static HAL_StatusTypeDef UART_Transmit_IT ( UART_HandleTypeDef * huart ) [static]

Send an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 2057 of file stm32l4xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_PARITY_NONE, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  |

Handle UART Communication Timeout.

Parameters:
huart,: UART handle.
Flag | Specifies the UART flag to check
Status | Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1865 of file stm32l4xx_hal_uart.c.

References __HAL_UART_GET_FLAG, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Exported Types

Data Structures | Enumerations
UART Exported Types
UART

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initalization structure definition. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00U, HAL_UART_STATE_READY = 0x20U, HAL_UART_STATE_BUSY = 0x24U, HAL_UART_STATE_BUSY_TX = 0x21U,
HAL_UART_STATE_BUSY_RX = 0x22U, HAL_UART_STATE_BUSY_TX_RX = 0x23U, HAL_UART_STATE_TIMEOUT = 0xA0U, HAL_UART_STATE_ERROR = 0xE0U
}
HAL UART State structures definition. More...
enum HAL_UART_ErrorTypeDef {
HAL_UART_ERROR_NONE = 0x00, HAL_UART_ERROR_PE = 0x01, HAL_UART_ERROR_NE = 0x02, HAL_UART_ERROR_FE = 0x04,
HAL_UART_ERROR_ORE = 0x08, HAL_UART_ERROR_DMA = 0x10
}
HAL UART Error Code structure definition. More...
enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00, UART_CLOCKSOURCE_PCLK2 = 0x01, UART_CLOCKSOURCE_HSI = 0x02, UART_CLOCKSOURCE_SYSCLK = 0x04,
UART_CLOCKSOURCE_LSE = 0x08, UART_CLOCKSOURCE_UNDEFINED = 0x10
}
UART clock sources definition. More...

Enumeration Type Documentation

enum HAL_UART_ErrorTypeDef

HAL UART Error Code structure definition.

Enumerator:
HAL_UART_ERROR_NONE

No error

HAL_UART_ERROR_PE

Parity error

HAL_UART_ERROR_NE

Noise error

HAL_UART_ERROR_FE

frame error

HAL_UART_ERROR_ORE

Overrun error

HAL_UART_ERROR_DMA

DMA transfer error

Definition at line 208 of file stm32l4xx_hal_uart.h.

enum HAL_UART_StateTypeDef

HAL UART State structures definition.

Note:
HAL UART State value is a combination of 2 different substates: gState and RxState.
  • gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_UART_STATE_RESET

Peripheral is not initialized Value is allowed for gState and RxState

HAL_UART_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_UART_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_UART_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_UART_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_UART_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_UART_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_UART_STATE_ERROR

Error Value is allowed for gState only

Definition at line 184 of file stm32l4xx_hal_uart.h.

enum UART_ClockSourceTypeDef

UART clock sources definition.

Enumerator:
UART_CLOCKSOURCE_PCLK1

PCLK1 clock source

UART_CLOCKSOURCE_PCLK2

PCLK2 clock source

UART_CLOCKSOURCE_HSI

HSI clock source

UART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

UART_CLOCKSOURCE_LSE

LSE clock source

UART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 221 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_InitTypeDef Struct Reference
UART Exported Types

UART Init Structure definition. More...

#include <stm32l4xx_hal_uart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | HwFlowCtl
uint32_t | OverSampling
uint32_t | OneBitSampling

Detailed Description

UART Init Structure definition.

Definition at line 65 of file stm32l4xx_hal_uart.h.

Field Documentation

uint32_t UART_InitTypeDef::BaudRate

This member configures the UART communication baud rate. The baud rate register is computed using the following formula:

  • If oversampling is 16 or in LIN mode, Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
  • If oversampling is 8, Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1

Definition at line 67 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::HwFlowCtl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of UART Hardware Flow Control.

Definition at line 92 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of UART Transfer Mode.

Definition at line 89 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of UART One Bit Sampling Method.

Definition at line 99 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). This parameter can be a value of UART Over Sampling.

Definition at line 96 of file stm32l4xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of UART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 82 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

uint32_t UART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of UART Number of Stop Bits.

Definition at line 79 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of UART Word Length.

Definition at line 76 of file stm32l4xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_uart.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_AdvFeatureInitTypeDef Struct Reference
UART Exported Types

UART Advanced Features initalization structure definition. More...

#include <stm32l4xx_hal_uart.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | AutoBaudRateEnable
uint32_t | AutoBaudRateMode
uint32_t | MSBFirst

Detailed Description

UART Advanced Features initalization structure definition.

Definition at line 107 of file stm32l4xx_hal_uart.h.

Field Documentation

uint32_t UART_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . This parameter can be a value of UART Advanced Feature Initialization Type.

Definition at line 109 of file stm32l4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateEnable

Specifies whether auto Baud rate detection is enabled. This parameter can be a value of UART Advanced Feature Auto BaudRate Enable

Definition at line 132 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateMode

If auto Baud rate detection is enabled, specifies how the rate detection is carried out. This parameter can be a value of UART Advanced Feature AutoBaud Rate Mode.

Definition at line 135 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of UART Advanced Feature Binary Data Inversion.

Definition at line 119 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of UART Advanced Feature DMA Disable On Rx Error.

Definition at line 129 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of UART Advanced Feature MSB First.

Definition at line 139 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of UART Advanced Feature Overrun Disable.

Definition at line 126 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of UART Advanced Feature RX Pin Active Level Inversion.

Definition at line 116 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of UART Advanced Feature RX TX Pins Swap.

Definition at line 123 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of UART Advanced Feature TX Pin Active Level Inversion.

Definition at line 113 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_uart.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_HandleTypeDef Struct Reference
UART Exported Types

UART handle Structure definition. More...

#include <stm32l4xx_hal_uart.h>

Data Fields

USART_TypeDef * | Instance
UART_InitTypeDef Init
UART_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_UART_StateTypeDef | gState
__IO HAL_UART_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

UART handle Structure definition.

Definition at line 234 of file stm32l4xx_hal_uart.h.

Field Documentation

UART_AdvFeatureInitTypeDef UART_HandleTypeDef::AdvancedInit

UART Advanced Features initialization parameters

Definition at line 240 of file stm32l4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

__IO uint32_t UART_HandleTypeDef::ErrorCode

UART Error code

Definition at line 269 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UART_GetError(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_CheckIdleState(), and UART_DMAError().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::gState

UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 262 of file stm32l4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAError(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmarx

UART Rx DMA Handle parameters

Definition at line 258 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_DMAStop(), HAL_UART_IRQHandler(), and HAL_UART_Receive_DMA().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmatx

UART Tx DMA Handle parameters

Definition at line 256 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_DMAStop(), and HAL_UART_Transmit_DMA().

UART_InitTypeDef UART_HandleTypeDef::Init

UART communication parameters

Definition at line 238 of file stm32l4xx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

USART_TypeDef* UART_HandleTypeDef::Instance

UART registers base address

Definition at line 236 of file stm32l4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_Receive_IT(), UART_SetConfig(), UART_Transmit_IT(), UART_WaitOnFlagUntilTimeout(), and UARTEx_Wakeup_AddressConfig().

HAL_LockTypeDef UART_HandleTypeDef::Lock

Locking object

Definition at line 260 of file stm32l4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

uint16_t UART_HandleTypeDef::Mask

UART Rx RDR register mask

Definition at line 254 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), and UART_Receive_IT().

uint8_t* UART_HandleTypeDef::pRxBuffPtr

Pointer to UART Rx transfer Buffer

Definition at line 248 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), and UART_Receive_IT().

uint8_t* UART_HandleTypeDef::pTxBuffPtr

Pointer to UART Tx transfer Buffer

Definition at line 242 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), and UART_Transmit_IT().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::RxState

UART state information related to Rx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 266 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_EndRxTransfer(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

uint16_t UART_HandleTypeDef::RxXferCount

UART Rx Transfer Counter

Definition at line 252 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), and UART_Receive_IT().

uint16_t UART_HandleTypeDef::RxXferSize

UART Rx Transfer size

Definition at line 250 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_DMA(), and HAL_UART_Receive_IT().

uint16_t UART_HandleTypeDef::TxXferCount

UART Tx Transfer Counter

Definition at line 246 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMATransmitCplt(), and UART_Transmit_IT().

uint16_t UART_HandleTypeDef::TxXferSize

UART Tx Transfer size

Definition at line 244 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_uart.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Number of Stop Bits

Defines
UART Number of Stop Bits
UART Exported Constants

Defines

#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 ((uint32_t)0x00000000)
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define UART_STOPBITS_0_5 USART_CR2_STOP_0

UART frame with 0.5 stop bit

Definition at line 285 of file stm32l4xx_hal_uart.h.

#define UART_STOPBITS_1 ((uint32_t)0x00000000)

UART frame with 1 stop bit

Definition at line 286 of file stm32l4xx_hal_uart.h.

#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

UART frame with 1.5 stop bits

Definition at line 287 of file stm32l4xx_hal_uart.h.

#define UART_STOPBITS_2 USART_CR2_STOP_1

UART frame with 2 stop bits

Definition at line 288 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Parity

Defines
UART Parity
UART Exported Constants

Defines

#define | UART_PARITY_NONE ((uint32_t)0x00000000)
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Even parity

Definition at line 297 of file stm32l4xx_hal_uart.h.

#define UART_PARITY_NONE ((uint32_t)0x00000000)

No parity

Definition at line 296 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Odd parity

Definition at line 298 of file stm32l4xx_hal_uart.h.

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STM32L486xx HAL User Manual: UART Hardware Flow Control

Defines
UART Hardware Flow Control
UART Exported Constants

Defines

#define | UART_HWCONTROL_NONE ((uint32_t)0x00000000)
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Define Documentation

#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)

Clear To Send

Definition at line 308 of file stm32l4xx_hal_uart.h.

#define UART_HWCONTROL_NONE ((uint32_t)0x00000000)

No hardware control

Definition at line 306 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)

Request To Send

Definition at line 307 of file stm32l4xx_hal_uart.h.

#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Request and Clear To Send

Definition at line 309 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Transfer Mode

Defines
UART Transfer Mode
UART Exported Constants

Defines

#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define UART_MODE_RX ((uint32_t)USART_CR1_RE)

RX mode

Definition at line 317 of file stm32l4xx_hal_uart.h.

#define UART_MODE_TX ((uint32_t)USART_CR1_TE)

TX mode

Definition at line 318 of file stm32l4xx_hal_uart.h.

#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

RX and TX mode

Definition at line 319 of file stm32l4xx_hal_uart.h.

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STM32L486xx HAL User Manual: UART State

Defines
UART State
UART Exported Constants

Defines

#define | UART_STATE_DISABLE ((uint32_t)0x00000000)
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Define Documentation

#define UART_STATE_DISABLE ((uint32_t)0x00000000)

UART disabled

Definition at line 327 of file stm32l4xx_hal_uart.h.

#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

UART enabled

Definition at line 328 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Over Sampling

Defines
UART Over Sampling
UART Exported Constants

Defines

#define | UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
#define | UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Define Documentation

#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)

Oversampling by 16

Definition at line 336 of file stm32l4xx_hal_uart.h.

#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Oversampling by 8

Definition at line 337 of file stm32l4xx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART One Bit Sampling Method

Defines
UART One Bit Sampling Method
UART Exported Constants

Defines

#define | UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

Define Documentation

#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)

One-bit sampling disable

Definition at line 345 of file stm32l4xx_hal_uart.h.

#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)

One-bit sampling enable

Definition at line 346 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Advanced Feature AutoBaud Rate Mode

Defines
UART Advanced Feature AutoBaud Rate Mode
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)

Auto Baud rate detection on 0x55 frame detection

Definition at line 357 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)

Auto Baud rate detection on 0x7F frame detection

Definition at line 356 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)

Auto Baud rate detection on falling edge

Definition at line 355 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000)

Auto Baud rate detection on start bit

Definition at line 354 of file stm32l4xx_hal_uart.h.

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STM32L486xx HAL User Manual: UART Receiver TimeOut

Defines
UART Receiver TimeOut
UART Exported Constants

Defines

#define | UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000)
#define | UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

Define Documentation

#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000)

UART receiver timeout disable

Definition at line 365 of file stm32l4xx_hal_uart.h.

#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)

UART receiver timeout enable

Definition at line 366 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Local Interconnection Network mode

Defines
UART Local Interconnection Network mode
UART Exported Constants

Defines

#define | UART_LIN_DISABLE ((uint32_t)0x00000000)
#define | UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)

Define Documentation

#define UART_LIN_DISABLE ((uint32_t)0x00000000)

Local Interconnect Network disable

Definition at line 374 of file stm32l4xx_hal_uart.h.

#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)

Local Interconnect Network enable

Definition at line 375 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART LIN Break Detection

Defines
UART LIN Break Detection
UART Exported Constants

Defines

#define | UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)

Define Documentation

#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)

LIN 10-bit break detection length

Definition at line 383 of file stm32l4xx_hal_uart.h.

#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)

LIN 11-bit break detection length

Definition at line 384 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART DMA Tx

Defines
UART DMA Tx
UART Exported Constants

Defines

#define | UART_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define | UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

Define Documentation

#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000)

UART DMA TX disabled

Definition at line 392 of file stm32l4xx_hal_uart.h.

#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)

UART DMA TX enabled

Definition at line 393 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART DMA Rx

Defines
UART DMA Rx
UART Exported Constants

Defines

#define | UART_DMA_RX_DISABLE ((uint32_t)0x00000000)
#define | UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000)

UART DMA RX disabled

Definition at line 401 of file stm32l4xx_hal_uart.h.

#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)

UART DMA RX enabled

Definition at line 402 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Half Duplex Selection

Defines
UART Half Duplex Selection
UART Exported Constants

Defines

#define | UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000)
#define | UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)

Define Documentation

#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000)

UART half-duplex disabled

Definition at line 410 of file stm32l4xx_hal_uart.h.

#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)

UART half-duplex enabled

Definition at line 411 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART WakeUp Methods

Defines
UART WakeUp Methods
UART Exported Constants

Defines

#define | UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)

Define Documentation

#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)

UART wake-up on address mark

Definition at line 420 of file stm32l4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)

UART wake-up on idle line

Definition at line 419 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Request Parameters

Defines
UART Request Parameters
UART Exported Constants

Defines

#define | UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)
#define | UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)
#define | UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)
#define | UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)

Auto-Baud Rate Request

Definition at line 428 of file stm32l4xx_hal_uart.h.

#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)

Mute Mode Request

Definition at line 430 of file stm32l4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode().

#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 431 of file stm32l4xx_hal_uart.h.

Referenced by UART_Receive_IT().

#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)

Send Break Request

Definition at line 429 of file stm32l4xx_hal_uart.h.

Referenced by HAL_LIN_SendBreak().

#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 432 of file stm32l4xx_hal_uart.h.

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STM32L486xx HAL User Manual: UART Advanced Feature Initialization Type

Defines
UART Advanced Feature Initialization Type
UART Exported Constants

Defines

#define | UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
#define | UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
#define | UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
#define | UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040)
#define | UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040)

Auto Baud rate detection initialization

Definition at line 447 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)

Binary data inversion

Definition at line 443 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)

DMA disable on Reception Error

Definition at line 446 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)

Most significant bit sent/received first

Definition at line 448 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)

No advanced feature initialization

Definition at line 440 of file stm32l4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)

RX pin active level inversion

Definition at line 442 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)

RX overrun disable

Definition at line 445 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)

TX/RX pins swap

Definition at line 444 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)

TX pin active level inversion

Definition at line 441 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

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STM32L486xx HAL User Manual: UART Advanced Feature TX Pin Active Level Inversion

Defines
UART Advanced Feature TX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

Define Documentation

#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)

TX pin active level inversion disable

Definition at line 456 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)

TX pin active level inversion enable

Definition at line 457 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Advanced Feature RX Pin Active Level Inversion

Defines
UART Advanced Feature RX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

Define Documentation

#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)

RX pin active level inversion disable

Definition at line 465 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)

RX pin active level inversion enable

Definition at line 466 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Advanced Feature Binary Data Inversion

Defines
UART Advanced Feature Binary Data Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Define Documentation

#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)

Binary data inversion disable

Definition at line 474 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)

Binary data inversion enable

Definition at line 475 of file stm32l4xx_hal_uart.h.

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STM32L486xx HAL User Manual: UART Advanced Feature RX TX Pins Swap

Defines
UART Advanced Feature RX TX Pins Swap
UART Exported Constants

Defines

#define | UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

Define Documentation

#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)

TX/RX pins swap disable

Definition at line 483 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)

TX/RX pins swap enable

Definition at line 484 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Advanced Feature Overrun Disable

Defines
UART Advanced Feature Overrun Disable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

Define Documentation

#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)

RX overrun disable

Definition at line 493 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)

RX overrun enable

Definition at line 492 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Advanced Feature Auto BaudRate Enable

Defines
UART Advanced Feature Auto BaudRate Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000)

RX Auto Baud rate detection enable

Definition at line 501 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)

RX Auto Baud rate detection disable

Definition at line 502 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Advanced Feature DMA Disable On Rx Error

Defines
UART Advanced Feature DMA Disable On Rx Error
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

Define Documentation

#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)

DMA disable on Reception Error

Definition at line 511 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)

DMA enable on Reception Error

Definition at line 510 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Advanced Feature MSB First

Defines
UART Advanced Feature MSB First
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Define Documentation

#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)

Most significant bit sent/received first disable

Definition at line 519 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)

Most significant bit sent/received first enable

Definition at line 520 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Advanced Feature Stop Mode Enable

Defines
UART Advanced Feature Stop Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)

Define Documentation

#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000)

UART stop mode disable

Definition at line 528 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)

UART stop mode enable

Definition at line 529 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Advanced Feature Mute Mode Enable

Defines
UART Advanced Feature Mute Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)

Define Documentation

#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000)

UART mute mode disable

Definition at line 537 of file stm32l4xx_hal_uart.h.

#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)

UART mute mode enable

Definition at line 538 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Address-matching LSB Position In CR2 Register

Defines
UART Address-matching LSB Position In CR2 Register
UART Exported Constants

Defines

#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24)

Define Documentation

#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24)

UART address-matching LSB position in CR2 register

Definition at line 546 of file stm32l4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init(), and UARTEx_Wakeup_AddressConfig().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART WakeUp From Stop Selection

Defines
UART WakeUp From Stop Selection
UART Exported Constants

Defines

#define | UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000)
#define | UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)
#define | UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)

Define Documentation

#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000)

UART wake-up on address

Definition at line 554 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)

UART wake-up on receive data register not empty

Definition at line 556 of file stm32l4xx_hal_uart.h.

#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)

UART wake-up on start bit

Definition at line 555 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART DriverEnable Polarity

Defines
UART DriverEnable Polarity
UART Exported Constants

Defines

#define | UART_DE_POLARITY_HIGH ((uint32_t)0x00000000)
#define | UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)

Define Documentation

#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000)

Driver enable signal is active high

Definition at line 564 of file stm32l4xx_hal_uart.h.

#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)

Driver enable signal is active low

Definition at line 565 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Driver Enable Assertion Time LSB Position In CR1 Register

Defines
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21)

Define Documentation

#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21)

UART Driver Enable assertion time LSB position in CR1 register

Definition at line 573 of file stm32l4xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Driver Enable DeAssertion Time LSB Position In CR1 Register

Defines
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16)

Define Documentation

#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16)

UART Driver Enable de-assertion time LSB position in CR1 register

Definition at line 581 of file stm32l4xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Interruptions Flag Mask

Defines
UART Interruptions Flag Mask
UART Exported Constants

Defines

#define UART_IT_MASK ((uint32_t)0x001F)

Define Documentation

#define UART_IT_MASK ((uint32_t)0x001F)

UART interruptions flags mask

Definition at line 589 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART polling-based communications time-out value

Defines
UART polling-based communications time-out value
UART Exported Constants

Defines

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF

Define Documentation

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF

UART polling-based communications time-out value

Definition at line 597 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Status Flags

Defines
UART Status Flags
UART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | UART_FLAG_REACK ((uint32_t)0x00400000)
#define | UART_FLAG_TEACK ((uint32_t)0x00200000)
#define | UART_FLAG_WUF ((uint32_t)0x00100000)
#define | UART_FLAG_RWU ((uint32_t)0x00080000)
#define | UART_FLAG_SBKF ((uint32_t)0x00040000)
#define | UART_FLAG_CMF ((uint32_t)0x00020000)
#define | UART_FLAG_BUSY ((uint32_t)0x00010000)
#define | UART_FLAG_ABRF ((uint32_t)0x00008000)
#define | UART_FLAG_ABRE ((uint32_t)0x00004000)
#define | UART_FLAG_EOBF ((uint32_t)0x00001000)
#define | UART_FLAG_RTOF ((uint32_t)0x00000800)
#define | UART_FLAG_CTS ((uint32_t)0x00000400)
#define | UART_FLAG_CTSIF ((uint32_t)0x00000200)
#define | UART_FLAG_LBDF ((uint32_t)0x00000100)
#define | UART_FLAG_TXE ((uint32_t)0x00000080)
#define | UART_FLAG_TC ((uint32_t)0x00000040)
#define | UART_FLAG_RXNE ((uint32_t)0x00000020)
#define | UART_FLAG_IDLE ((uint32_t)0x00000010)
#define | UART_FLAG_ORE ((uint32_t)0x00000008)
#define | UART_FLAG_NE ((uint32_t)0x00000004)
#define | UART_FLAG_FE ((uint32_t)0x00000002)
#define | UART_FLAG_PE ((uint32_t)0x00000001)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define UART_FLAG_ABRE ((uint32_t)0x00004000)

UART uto Baud rate error

Definition at line 615 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_ABRF ((uint32_t)0x00008000)

UART auto Baud rate flag

Definition at line 614 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_BUSY ((uint32_t)0x00010000)

UART busy flag

Definition at line 613 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_CMF ((uint32_t)0x00020000)

UART character match flag

Definition at line 612 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_CTS ((uint32_t)0x00000400)

UART clear to send flag

Definition at line 618 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_CTSIF ((uint32_t)0x00000200)

UART clear to send interrupt flag

Definition at line 619 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_EOBF ((uint32_t)0x00001000)

UART end of block flag

Definition at line 616 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_FE ((uint32_t)0x00000002)

UART frame error

Definition at line 627 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_IDLE ((uint32_t)0x00000010)

UART idle flag

Definition at line 624 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_LBDF ((uint32_t)0x00000100)

UART LIN break detection flag

Definition at line 620 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_NE ((uint32_t)0x00000004)

UART noise error

Definition at line 626 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_ORE ((uint32_t)0x00000008)

UART overrun error

Definition at line 625 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_PE ((uint32_t)0x00000001)

UART parity error

Definition at line 628 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_REACK ((uint32_t)0x00400000)

UART receive enable acknowledge flag

Definition at line 607 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_RTOF ((uint32_t)0x00000800)

UART receiver timeout flag

Definition at line 617 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_RWU ((uint32_t)0x00080000)

UART receiver wake-up from mute mode flag

Definition at line 610 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_RXNE ((uint32_t)0x00000020)

UART read data register not empty

Definition at line 623 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Receive().

#define UART_FLAG_SBKF ((uint32_t)0x00040000)

UART send break flag

Definition at line 611 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_TC ((uint32_t)0x00000040)

UART transmission complete

Definition at line 622 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_TEACK ((uint32_t)0x00200000)

UART transmit enable acknowledge flag

Definition at line 608 of file stm32l4xx_hal_uart.h.

#define UART_FLAG_TXE ((uint32_t)0x00000080)

UART transmit data register empty

Definition at line 621 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_WUF ((uint32_t)0x00100000)

UART wake-up from stop mode flag

Definition at line 609 of file stm32l4xx_hal_uart.h.

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STM32L486xx HAL User Manual: UART Interrupts Definition

Defines
UART Interrupts Definition
UART Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | UART_IT_PE ((uint32_t)0x0028)
#define | UART_IT_TXE ((uint32_t)0x0727)
#define | UART_IT_TC ((uint32_t)0x0626)
#define | UART_IT_RXNE ((uint32_t)0x0525)
#define | UART_IT_IDLE ((uint32_t)0x0424)
#define | UART_IT_LBD ((uint32_t)0x0846)
#define | UART_IT_CTS ((uint32_t)0x096A)
#define | UART_IT_CM ((uint32_t)0x112E)
#define | UART_IT_WUF ((uint32_t)0x1476)
#define | UART_IT_ERR ((uint32_t)0x0060)
#define | UART_IT_ORE ((uint32_t)0x0300)
#define | UART_IT_NE ((uint32_t)0x0200)
#define | UART_IT_FE ((uint32_t)0x0100)

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5bits)

Define Documentation

#define UART_IT_CM ((uint32_t)0x112E)

UART character match interruption

Definition at line 650 of file stm32l4xx_hal_uart.h.

#define UART_IT_CTS ((uint32_t)0x096A)

UART CTS interruption

Definition at line 649 of file stm32l4xx_hal_uart.h.

#define UART_IT_ERR ((uint32_t)0x0060)

UART error interruption

Definition at line 659 of file stm32l4xx_hal_uart.h.

#define UART_IT_FE ((uint32_t)0x0100)

UART frame error interruption

Definition at line 665 of file stm32l4xx_hal_uart.h.

#define UART_IT_IDLE ((uint32_t)0x0424)

UART idle interruption

Definition at line 647 of file stm32l4xx_hal_uart.h.

#define UART_IT_LBD ((uint32_t)0x0846)

UART LIN break detection interruption

Definition at line 648 of file stm32l4xx_hal_uart.h.

#define UART_IT_NE ((uint32_t)0x0200)

UART noise error interruption

Definition at line 664 of file stm32l4xx_hal_uart.h.

#define UART_IT_ORE ((uint32_t)0x0300)

UART overrun error interruption

Definition at line 663 of file stm32l4xx_hal_uart.h.

#define UART_IT_PE ((uint32_t)0x0028)

UART parity error interruption

Definition at line 643 of file stm32l4xx_hal_uart.h.

#define UART_IT_RXNE ((uint32_t)0x0525)

UART read data register not empty interruption

Definition at line 646 of file stm32l4xx_hal_uart.h.

#define UART_IT_TC ((uint32_t)0x0626)

UART transmission complete interruption

Definition at line 645 of file stm32l4xx_hal_uart.h.

#define UART_IT_TXE ((uint32_t)0x0727)

UART transmit data register empty interruption

Definition at line 644 of file stm32l4xx_hal_uart.h.

#define UART_IT_WUF ((uint32_t)0x1476)

UART wake-up from stop mode interruption

Definition at line 651 of file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Interruption Clear Flags

Defines
UART Interruption Clear Flags
UART Exported Constants

Defines

#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NCF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | UART_CLEAR_EOBF USART_ICR_EOBCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF

Define Documentation

#define UART_CLEAR_CMF USART_ICR_CMCF

Character Match Clear Flag

Definition at line 683 of file stm32l4xx_hal_uart.h.

#define UART_CLEAR_CTSF USART_ICR_CTSCF

CTS Interrupt Clear Flag

Definition at line 680 of file stm32l4xx_hal_uart.h.

#define UART_CLEAR_EOBF USART_ICR_EOBCF

End Of Block Clear Flag

Definition at line 682 of file stm32l4xx_hal_uart.h.

#define UART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 674 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 677 of file stm32l4xx_hal_uart.h.

#define UART_CLEAR_LBDF USART_ICR_LBDCF

LIN Break Detection Clear Flag

Definition at line 679 of file stm32l4xx_hal_uart.h.

#define UART_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 675 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_CLEAR_OREF USART_ICR_ORECF

Overrun Error Clear Flag

Definition at line 676 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_DMAResume(), and HAL_UART_IRQHandler().

#define UART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 673 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define UART_CLEAR_RTOF USART_ICR_RTOCF

Receiver Time Out Clear Flag

Definition at line 681 of file stm32l4xx_hal_uart.h.

#define UART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 678 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA().

#define UART_CLEAR_WUF USART_ICR_WUCF

Wake Up from stop mode Clear Flag

Definition at line 684 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Exported Macros

Defines
UART Exported Macros
UART

Defines

#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.

Define Documentation

#define __HAL_UART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)

Clear the UART FE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 747 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified UART pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_RTOF Receiver Time Out Clear Flag
  • UART_CLEAR_EOBF End Of Block Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 735 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_DMAResume(), and HAL_UART_Transmit_DMA().

#define __HAL_UART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)

Clear the UART IDLE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 765 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified UART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 893 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define __HAL_UART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)

Clear the UART NE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 753 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)

Clear the UART ORE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 759 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)

Clear the UART PE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 741 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 930 of file stm32l4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Disable the specified UART interrupt.

Parameters:
__HANDLE__,: specifies the UART Handle.
__INTERRUPT__,: specifies the UART interrupt source to disable. This parameter can be one of the following values:
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
None

Definition at line 833 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 924 of file stm32l4xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Enable the specified UART interrupt.

Parameters:
__HANDLE__,: specifies the UART Handle.
__INTERRUPT__,: specifies the UART interrupt source to enable. This parameter can be one of the following values:
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
None

Definition at line 812 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                \
      SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
      SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
    }  while(0)

Flush the UART Data registers.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 711 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified UART flag is set or not.

Parameters:
__HANDLE__,: specifies the UART Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • UART_FLAG_REACK Receive enable acknowledge flag
  • UART_FLAG_TEACK Transmit enable acknowledge flag
  • UART_FLAG_WUF Wake up from stop mode flag
  • UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
  • UART_FLAG_SBKF Send Break flag
  • UART_FLAG_CMF Character match flag
  • UART_FLAG_BUSY Busy flag
  • UART_FLAG_ABRF Auto Baud rate detection flag
  • UART_FLAG_ABRE Auto Baud rate detection error flag
  • UART_FLAG_EOBF End of block flag
  • UART_FLAG_RTOF Receiver timeout flag
  • UART_FLAG_CTS CTS Change flag
  • UART_FLAG_LBDF LIN Break detection flag
  • UART_FLAG_TXE Transmit data register empty flag
  • UART_FLAG_TC Transmission Complete flag
  • UART_FLAG_RXNE Receive data register not empty flag
  • UART_FLAG_IDLE Idle Line detection flag
  • UART_FLAG_ORE Overrun Error flag
  • UART_FLAG_NE Noise Error flag
  • UART_FLAG_FE Framing Error flag
  • UART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 794 of file stm32l4xx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))

Check whether the specified UART interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the UART Handle.
__IT__,: specifies the UART interrupt to check. This parameter can be one of the following values:
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_ORE Overrun Error interrupt
  • UART_IT_NE Noise Error interrupt
  • UART_IT_FE Framing Error interrupt
  • UART_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 855 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))

Check whether the specified UART interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the UART Handle.
__IT__,: specifies the UART interrupt source to check. This parameter can be one of the following values:
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
  • UART_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 873 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_DISABLE ( __HANDLE__ )
Value:
do{                                                       \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
  } while(0)

Disable CTS flow control.

Note:
This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 962 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_ENABLE ( __HANDLE__ )
Value:
do{                                                      \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
  } while(0)

Enable CTS flow control.

Note:
This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 944 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_DISABLE ( __HANDLE__ )
Value:
do{                                                      \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
  } while(0)

Disable RTS flow control.

Note:
This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 998 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_ENABLE ( __HANDLE__ )
Value:
do{                                                     \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
  } while(0)

Enable RTS flow control.

Note:
This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 980 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the UART one bit sample method.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 918 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the UART one bit sample method.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None

Definition at line 912 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
                                                     } while(0)

Reset UART handle states.

Parameters:
__HANDLE__,: UART handle.
Return values:
None

Definition at line 703 of file stm32l4xx_hal_uart.h.

#define __HAL_UART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))

Set a specific UART request flag.

Parameters:
__HANDLE__,: specifies the UART Handle.
__REQ__,: specifies the request flag to set This parameter can be one of the following values:
  • UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • UART_SENDBREAK_REQUEST Send Break Request
  • UART_MUTE_MODE_REQUEST Mute Mode Request
  • UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 906 of file stm32l4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode(), and UART_Receive_IT().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Private Macros

Defines
UART Private Macros
UART

Defines

#define | UART_DIV_LPUART(__PCLK__, __BAUD__) ((((uint64_t)(__PCLK__)*256) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.

Define Documentation

#define IS_LPUART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_1) || \
                                          ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that LPUART frame number of stop bits is valid.

Parameters:
__STOPBITS__,: LPUART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1074 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATE ( __AUTOBAUDRATE__ )
Value:
(((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))

Ensure that UART auto Baud rate state is valid.

Parameters:
__AUTOBAUDRATE__,: UART auto Baud rate state.
Return values:
SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)

Definition at line 1265 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE ( __MODE__ )
Value:
(((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))

Ensure that UART auto Baud rate detection mode is valid.

Parameters:
__MODE__,: UART auto Baud rate detection mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1133 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))

Ensure that UART frame data inversion setting is valid.

Parameters:
__DATAINV__,: UART frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1241 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that UART DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__,: UART DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1273 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
                                                            UART_ADVFEATURE_SWAP_INIT              | \
                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
                                                            UART_ADVFEATURE_MSBFIRST_INIT))

Ensure that UART advanced features initialization is valid.

Parameters:
__INIT__,: UART advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 1210 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that UART frame MSB first setting is valid.

Parameters:
__MSBFIRST__,: UART frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1281 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))

Ensure that UART frame RX inversion setting is valid.

Parameters:
__RXINV__,: UART frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 1233 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_STOPMODE ( __STOPMODE__ )
Value:
(((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))

Ensure that UART stop mode state is valid.

Parameters:
__STOPMODE__,: UART stop mode state.
Return values:
SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)

Definition at line 1289 of file stm32l4xx_hal_uart.h.

#define IS_UART_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))

Ensure that UART frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__,: UART frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1249 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))

Ensure that UART frame TX inversion setting is valid.

Parameters:
__TXINV__,: UART frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 1225 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1F)

Check UART assertion time.

Parameters:
__TIME__,: 5-bit value assertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1051 of file stm32l4xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 10000001)

Check UART Baud rate.

Parameters:
__BAUDRATE__,: Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 1045 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_DE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))

Ensure that UART driver enable polarity is valid.

Parameters:
__POLARITY__,: UART driver enable polarity.
Return values:
SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)

Definition at line 1314 of file stm32l4xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DEASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1F)

Check UART deassertion time.

Parameters:
__TIME__,: 5-bit value deassertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1057 of file stm32l4xx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == UART_DMA_RX_DISABLE) || \
                                       ((__DMARX__) == UART_DMA_RX_ENABLE))

Ensure that UART DMA RX state is valid.

Parameters:
__DMARX__,: UART DMA RX state.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 1175 of file stm32l4xx_hal_uart.h.

#define IS_UART_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == UART_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == UART_DMA_TX_ENABLE))

Ensure that UART DMA TX state is valid.

Parameters:
__DMATX__,: UART DMA TX state.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 1167 of file stm32l4xx_hal_uart.h.

#define IS_UART_HALF_DUPLEX ( __HDSEL__ )
Value:
(((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))

Ensure that UART half-duplex state is valid.

Parameters:
__HDSEL__,: UART half-duplex state.
Return values:
SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)

Definition at line 1183 of file stm32l4xx_hal_uart.h.

#define IS_UART_HARDWARE_FLOW_CONTROL ( __CONTROL__ )
Value:
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
                                    ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
                                    ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
                                    ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))

Ensure that UART hardware flow control is valid.

Parameters:
__CONTROL__,: UART hardware flow control.
Return values:
SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)

Definition at line 1091 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_LIN ( __LIN__ )
Value:
(((__LIN__) == UART_LIN_DISABLE) || \
                                     ((__LIN__) == UART_LIN_ENABLE))

Ensure that UART LIN state is valid.

Parameters:
__LIN__,: UART LIN state.
Return values:
SET (__LIN__ is valid) or RESET (__LIN__ is invalid)

Definition at line 1151 of file stm32l4xx_hal_uart.h.

#define IS_UART_LIN_BREAK_DETECT_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))

Ensure that UART LIN break detection length is valid.

Parameters:
__LENGTH__,: UART LIN break detection length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 1159 of file stm32l4xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))

Ensure that UART communication mode is valid.

Parameters:
__MODE__,: UART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1102 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_MUTE_MODE ( __MUTE__ )
Value:
(((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))

Ensure that UART mute mode state is valid.

Parameters:
__MUTE__,: UART mute mode state.
Return values:
SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)

Definition at line 1297 of file stm32l4xx_hal_uart.h.

#define IS_UART_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))

Ensure that UART frame sampling is valid.

Parameters:
__ONEBIT__,: UART frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 1125 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))

Ensure that UART frame overrun setting is valid.

Parameters:
__OVERRUN__,: UART frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1257 of file stm32l4xx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == UART_OVERSAMPLING_16) || \
                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))

Ensure that UART oversampling is valid.

Parameters:
__SAMPLING__,: UART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 1117 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == UART_PARITY_NONE) || \
                                    ((__PARITY__) == UART_PARITY_EVEN) || \
                                    ((__PARITY__) == UART_PARITY_ODD))

Ensure that UART frame parity is valid.

Parameters:
__PARITY__,: UART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 1082 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_RECEIVER_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
                                               ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))

Ensure that UART receiver timeout setting is valid.

Parameters:
__TIMEOUT__,: UART receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 1143 of file stm32l4xx_hal_uart.h.

#define IS_UART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))

Ensure that UART request parameter is valid.

Parameters:
__PARAM__,: UART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1199 of file stm32l4xx_hal_uart.h.

#define IS_UART_STATE ( __STATE__ )
Value:
(((__STATE__) == UART_STATE_DISABLE) || \
                                  ((__STATE__) == UART_STATE_ENABLE))

Ensure that UART state is valid.

Parameters:
__STATE__,: UART state.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 1109 of file stm32l4xx_hal_uart.h.

#define IS_UART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_0_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that UART frame number of stop bits is valid.

Parameters:
__STOPBITS__,: UART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) UART_STOPBITS_1_5

Definition at line 1064 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_WAKEUP_SELECTION ( __WAKE__ )
Value:
(((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))

Ensure that UART wake-up selection is valid.

Parameters:
__WAKE__,: UART wake-up selection.
Return values:
SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)

Definition at line 1305 of file stm32l4xx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define IS_UART_WAKEUPMETHOD ( __WAKEUP__ )
Value:
(((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))

Ensure that UART wake-up method is valid.

Parameters:
__WAKEUP__,: UART wake-up method .
Return values:
SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)

Definition at line 1191 of file stm32l4xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_DIV_LPUART | ( | __PCLK__,
 |  | __BAUD__
 | ) | ((((uint64_t)(__PCLK__)*256) + ((__BAUD__)/2)) / (__BAUD__))

BRR division operation to set BRR register with LPUART.

Parameters:
__PCLK__,: LPUART clock.
__BAUD__,: Baud rate set by the user.
Return values:
Division result

Definition at line 1017 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__
 | ) | (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__,: UART clock.
__BAUD__,: Baud rate set by the user.
Return values:
Division result

Definition at line 1031 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__
 | ) | ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__,: UART clock.
__BAUD__,: Baud rate set by the user.
Return values:
Division result

Definition at line 1024 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_INSTANCE_LOWPOWER ( __HANDLE__ ) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )

Check whether or not UART instance is Low Power UART.

Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
SET (instance is LPUART) or RESET (instance isn't LPUART)

Definition at line 1037 of file stm32l4xx_hal_uart.h.

Referenced by UART_SetConfig().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UARTEx Private Functions

Functions
UARTEx Private Functions
UARTEx

Functions

static void UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Function Documentation

static void UARTEx_Wakeup_AddressConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  | [static]

Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Parameters:
huart,: UART handle.
WakeUpSelection,: UART wake up from stop mode parameters.
Return values:
None

Definition at line 441 of file stm32l4xx_hal_uart_ex.c.

References UART_WakeUpTypeDef::Address, UART_WakeUpTypeDef::AddressLength, assert_param, UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CR2_ADDRESS_LSB_POS.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UARTEx Exported Functions

Extended Initialization and Configuration Functions. More...

Functions

HAL_StatusTypeDef HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Detailed Description

Extended Initialization and Configuration Functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
     procedures (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_RS485Ex_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Polarity,
 |  | uint32_t | AssertionTime,
 |  | uint32_t | DeassertionTime
 | ) |  |

Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart,: UART handle.
Polarity,: select the driver enable polarity. This parameter can be one of the following values:
  • UART_DE_POLARITY_HIGH DE signal is active high
  • UART_DE_POLARITY_LOW DE signal is active low
AssertionTime,: Driver Enable assertion time: 5-bit value defining the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate)
DeassertionTime,: Driver Enable deassertion time: 5-bit value defining the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate).
Return values:
HAL status

Definition at line 166 of file stm32l4xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, IS_UART_ASSERTIONTIME, IS_UART_DE_POLARITY, IS_UART_DEASSERTIONTIME, UART_HandleTypeDef::Lock, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR1_DEAT_ADDRESS_LSB_POS, UART_CR1_DEDT_ADDRESS_LSB_POS, and UART_SetConfig().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides the following functions:
     (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
     (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
         detection length to more than 4 bits for multiprocessor address mark wake up.
     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
         trigger: address match, Start Bit detection or RXNE bit status.
     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
     (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt

Function Documentation

HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | AddressLength
 | ) |  |

By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).

Note:
Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
Parameters:
huart,: UART handle.
AddressLength,: this parameter can be one of the following values:
  • UART_ADDRESS_DETECT_4B 4-bit long address
  • UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
Return values:
HAL status

Definition at line 274 of file stm32l4xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_UARTEx_DisableStopMode ( UART_HandleTypeDef * huart )

Disable UART Stop Mode.

Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 390 of file stm32l4xx_hal_uart_ex.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_EnableStopMode ( UART_HandleTypeDef * huart )

Enable UART Stop Mode.

Note:
The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
Parameters:
huart,: UART handle.
Return values:
HAL status

Definition at line 367 of file stm32l4xx_hal_uart_ex.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  |

Set Wakeup from Stop mode interrupt flag selection.

Parameters:
huart,: UART handle.
WakeUpSelection,: address match, Start Bit detection or RXNE bit status. This parameter can be one of the following values:
  • UART_WAKEUP_ON_ADDRESS
  • UART_WAKEUP_ON_STARTBIT
  • UART_WAKEUP_ON_READDATA_NONEMPTY
Return values:
HAL status

Definition at line 311 of file stm32l4xx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, UART_HandleTypeDef::Instance, IS_UART_WAKEUP_SELECTION, UART_WaitOnFlagUntilTimeout(), UART_WAKEUP_ON_ADDRESS, UARTEx_Wakeup_AddressConfig(), and UART_WakeUpTypeDef::WakeUpEvent.

void HAL_UARTEx_WakeupCallback ( UART_HandleTypeDef * huart )

UART wakeup from Stop mode callback.

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 413 of file stm32l4xx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART_WakeUpTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_WakeUpTypeDef Struct Reference
UARTEx Exported Types

UART wake up from stop mode parameters. More...

#include <stm32l4xx_hal_uart_ex.h>

Data Fields

uint32_t | WakeUpEvent
uint16_t | AddressLength
uint8_t | Address

Detailed Description

UART wake up from stop mode parameters.

Definition at line 65 of file stm32l4xx_hal_uart_ex.h.

Field Documentation

uint8_t UART_WakeUpTypeDef::Address

UART/USART node address (7-bit long max).

Definition at line 75 of file stm32l4xx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint16_t UART_WakeUpTypeDef::AddressLength

Specifies whether the address is 4 or 7-bit long. This parameter can be a value of UART Extended WakeUp Address Length.

Definition at line 72 of file stm32l4xx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint32_t UART_WakeUpTypeDef::WakeUpEvent

Specifies which event will activat the Wakeup from Stop mode flag (WUF). This parameter can be a value of UART WakeUp From Stop Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up.

Definition at line 67 of file stm32l4xx_hal_uart_ex.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_uart_ex.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Word Length

Defines
UART Word Length
UARTEx Exported Constants

Defines

#define | UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | UART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)

7-bit long UART frame

Definition at line 90 of file stm32l4xx_hal_uart_ex.h.

#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)

8-bit long UART frame

Definition at line 91 of file stm32l4xx_hal_uart_ex.h.

Referenced by HAL_LIN_Init().

#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

9-bit long UART frame

Definition at line 92 of file stm32l4xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Extended WakeUp Address Length

Defines
UART Extended WakeUp Address Length
UARTEx Exported Constants

Defines

#define | UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000)
#define | UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)

Define Documentation

#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000)

4-bit long wake-up address

Definition at line 100 of file stm32l4xx_hal_uart_ex.h.

#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)

7-bit long wake-up address

Definition at line 101 of file stm32l4xx_hal_uart_ex.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UARTEx Private Macros

Defines
UARTEx Private Macros
UARTEx

Defines

#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.

Define Documentation

#define IS_UART_ADDRESSLENGTH_DETECT ( __ADDRESS__ )
Value:
(((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))

Ensure that UART wake-up address length is valid.

Parameters:
__ADDRESS__,: UART wake-up address length.
Return values:
SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)

Definition at line 506 of file stm32l4xx_hal_uart_ex.h.

Referenced by HAL_MultiProcessorEx_AddressLength_Set(), and UARTEx_Wakeup_AddressConfig().

#define IS_UART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_9B))

Ensure that UART frame length is valid.

Parameters:
__LENGTH__,: UART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 497 of file stm32l4xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the UART clock source.

Parameters:
__HANDLE__,: specifies the UART Handle.
__CLOCKSOURCE__,: output variable.
Return values:
UART clocking source, written in __CLOCKSOURCE__.

Definition at line 159 of file stm32l4xx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_MASK_COMPUTATION ( __HANDLE__ )

Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__,: specifies the UART Handle.
Return values:
None,the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 454 of file stm32l4xx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), and HAL_UART_Receive_IT().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000)
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS

Define Documentation

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))

USART CR1 fields of parameters set by USART_SetConfig API

Definition at line 110 of file stm32l4xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR2_FIELDS
Value:
((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
                                              USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))

USART CR2 fields of parameters set by USART_SetConfig API

Definition at line 112 of file stm32l4xx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_DUMMY_DATA ((uint16_t) 0xFFFF)

USART transmitted dummy data

Definition at line 108 of file stm32l4xx_hal_usart.c.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), and USART_Receive_IT().

#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000)

USART TX or RX enable acknowledge time-out value

Definition at line 109 of file stm32l4xx_hal_usart.c.

Referenced by USART_CheckIdleState().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USART
    in asynchronous and in synchronous modes.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) USART polarity
        (++) USART phase
        (++) USART LastBit
        (++) Receiver/transmitter modes

    [..]
    The HAL_USART_Init() function follows the USART  synchronous configuration
    procedure (details for the procedure are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible USART formats are listed in the following table.

Table 1. USART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | USART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_USART_DeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART peripheral.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 254 of file stm32l4xx_hal_usart.c.

References assert_param, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspDeInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_Init ( USART_HandleTypeDef * husart )

Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 205 of file stm32l4xx_hal_usart.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_MspInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Lock, USART_HandleTypeDef::State, USART_CheckIdleState(), and USART_SetConfig().

void HAL_USART_MspDeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART MSP.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 303 of file stm32l4xx_hal_usart.c.

Referenced by HAL_USART_DeInit().

void HAL_USART_MspInit ( USART_HandleTypeDef * husart )

Initialize the USART MSP.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 288 of file stm32l4xx_hal_usart.c.

Referenced by HAL_USART_Init().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
USART Exported Functions

USART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.

Detailed Description

USART Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART synchronous
    data transfers.

    [..] The USART supports master mode only: it cannot receive or send data related to an input
         clock (SCLK is always an output).

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (++) HAL_USART_Transmit()in simplex mode
        (++) HAL_USART_Receive() in full duplex receive only
        (++) HAL_USART_TransmitReceive() in full duplex mode

    (#) Non-Blocking mode API's with Interrupt are :
        (++) HAL_USART_Transmit_IT()in simplex mode
        (++) HAL_USART_Receive_IT() in full duplex receive only
        (++) HAL_USART_TransmitReceive_IT()in full duplex mode
        (++) HAL_USART_IRQHandler()

    (#) No-Blocking mode API's  with DMA are :
        (++) HAL_USART_Transmit_DMA()in simplex mode
        (++) HAL_USART_Receive_DMA() in full duplex receive only
        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
        (++) HAL_USART_DMAPause()
        (++) HAL_USART_DMAResume()
        (++) HAL_USART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (++) HAL_USART_TxCpltCallback()
        (++) HAL_USART_RxCpltCallback()
        (++) HAL_USART_TxHalfCpltCallback()
        (++) HAL_USART_RxHalfCpltCallback()
        (++) HAL_USART_ErrorCallback()
        (++) HAL_USART_TxRxCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
           and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_USART_DMAPause ( USART_HandleTypeDef * husart )

Pause the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1016 of file stm32l4xx_hal_usart.c.

References HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_DMAResume ( USART_HandleTypeDef * husart )

Resume the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1057 of file stm32l4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, and USART_CLEAR_OREF.

HAL_StatusTypeDef HAL_USART_DMAStop ( USART_HandleTypeDef * husart )

Stop the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1095 of file stm32l4xx_hal_usart.c.

References HAL_DMA_Abort(), HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, and USART_EndTransfer().

void HAL_USART_ErrorCallback ( USART_HandleTypeDef * husart )

USART error callback.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1377 of file stm32l4xx_hal_usart.c.

Referenced by HAL_USART_IRQHandler(), USART_DMAAbortOnError(), and USART_DMAError().

void HAL_USART_IRQHandler ( USART_HandleTypeDef * husart )

Handle USART interrupt request.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1130 of file stm32l4xx_hal_usart.c.

References __HAL_USART_CLEAR_IT, USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_ERROR_FE, HAL_USART_ERROR_NE, HAL_USART_ERROR_NONE, HAL_USART_ERROR_ORE, HAL_USART_ERROR_PE, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_DMAAbortOnError(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Receive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
Parameters:
husart | USART handle.
pRxData | Pointer to data buffer.
Size | Amount of data to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 464 of file stm32l4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FLAG_RXNE, USART_FLAG_TC, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Receive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
husart | USART handle.
pRxData | pointer to data buffer.
Size | amount of data to be received.
Note:
When the USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
The USART DMA transmit channel must be configured in order to generate the clock for the slave.
Return values:
HAL status

Definition at line 856 of file stm32l4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Receive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in blocking mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
Parameters:
husart | USART handle.
pRxData | pointer to data buffer.
Size | amount of data to be received.
Return values:
HAL status

Definition at line 687 of file stm32l4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_MASK_COMPUTATION, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_RxCpltCallback ( USART_HandleTypeDef * husart )

Rx Transfer completed callback.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1332 of file stm32l4xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_Receive_IT().

void HAL_USART_RxHalfCpltCallback ( USART_HandleTypeDef * husart )

Rx Half Transfer completed callback.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1347 of file stm32l4xx_hal_usart.c.

Referenced by USART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_USART_Transmit | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Simplex send an amount of data in blocking mode.

Parameters:
husart | USART handle.
pTxData | Pointer to data buffer.
Size | Amount of data to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 392 of file stm32l4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_TC, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Transmit_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
husart | USART handle.
pTxData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 795 of file stm32l4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Transmit_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Parameters:
husart | USART handle.
pTxData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 640 of file stm32l4xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, and USART_IT_TXE.

HAL_StatusTypeDef HAL_USART_TransmitReceive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Send and Receive an amount of data in blocking mode.

Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer.
pRxData | pointer to RX data buffer.
Size | amount of data to be sent (same amount to be received).
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 549 of file stm32l4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_RXNE, USART_FLAG_TC, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Transmit Receive an amount of data in non-blocking mode.

Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer.
pRxData | pointer to RX data buffer.
Size | amount of data to be received/sent.
Note:
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
Return values:
HAL status

Definition at line 936 of file stm32l4xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_TransmitReceive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Send and Receive an amount of data in interrupt mode.

Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer.
pRxData | pointer to RX data buffer.
Size | amount of data to be sent (same amount to be received).
Return values:
HAL status

Definition at line 743 of file stm32l4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, and USART_MASK_COMPUTATION.

void HAL_USART_TxCpltCallback ( USART_HandleTypeDef * husart )

Tx Transfer completed callback.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1302 of file stm32l4xx_hal_usart.c.

Referenced by USART_DMATransmitCplt(), and USART_EndTransmit_IT().

void HAL_USART_TxHalfCpltCallback ( USART_HandleTypeDef * husart )

Tx Half Transfer completed callback.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1317 of file stm32l4xx_hal_usart.c.

Referenced by USART_DMATxHalfCplt().

void HAL_USART_TxRxCpltCallback ( USART_HandleTypeDef * husart )

Tx/Rx Transfers completed callback for the non-blocking process.

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1362 of file stm32l4xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_TransmitReceive_IT().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
USART Exported Functions

USART Peripheral State and Error functions. More...

Functions

HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART Peripheral State and Error functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the USART handle state
      (+) Return the USART handle error code

Function Documentation

uint32_t HAL_USART_GetError ( USART_HandleTypeDef * husart )

Return the USART error code.

Parameters:
husart : pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle Error Code

Definition at line 1425 of file stm32l4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode.

HAL_USART_StateTypeDef HAL_USART_GetState ( USART_HandleTypeDef * husart )

Return the USART handle state.

Parameters:
husart : pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle state

Definition at line 1414 of file stm32l4xx_hal_usart.c.

References USART_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Private Functions

Functions
USART Private Functions
USART

Functions

static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Function Documentation

static HAL_StatusTypeDef USART_CheckIdleState ( USART_HandleTypeDef * husart ) [static]

Check the USART Idle State.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 1723 of file stm32l4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_TEACK_REACK_TIMEOUT, and USART_WaitOnFlagUntilTimeout().

Referenced by HAL_USART_Init().

static void USART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1593 of file stm32l4xx_hal_usart.c.

References HAL_USART_ErrorCallback(), __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, and USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_IRQHandler().

static void USART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication error callback.

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 1573 of file stm32l4xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_DMA, HAL_USART_ErrorCallback(), HAL_USART_STATE_READY, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and USART_EndTransfer().

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1509 of file stm32l4xx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __DMA_HandleTypeDef::Instance, USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::RxXferCount, and USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1561 of file stm32l4xx_hal_usart.c.

References HAL_USART_RxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1463 of file stm32l4xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and USART_IT_TC.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1497 of file stm32l4xx_hal_usart.c.

References HAL_USART_TxHalfCpltCallback(), and __DMA_HandleTypeDef::Parent.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_EndTransfer ( USART_HandleTypeDef * husart ) [static]

End ongoing transfer on USART peripheral (following error detection or Transfer completion).

Parameters:
husart USART handle.
Return values:
None

Definition at line 1447 of file stm32l4xx_hal_usart.c.

References HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

Referenced by HAL_USART_DMAStop(), HAL_USART_IRQHandler(), and USART_DMAError().

static HAL_StatusTypeDef USART_EndTransmit_IT ( USART_HandleTypeDef * husart ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
husart Pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1820 of file stm32l4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, HAL_USART_STATE_READY, HAL_USART_TxCpltCallback(), USART_HandleTypeDef::State, USART_IT_ERR, and USART_IT_TC.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_Receive_IT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
Parameters:
husart USART handle
Return values:
HAL status

Definition at line 1844 of file stm32l4xx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_SetConfig ( USART_HandleTypeDef * husart ) [static]

Configure the USART peripheral.

Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 1642 of file stm32l4xx_hal_usart.c.

References assert_param, USART_InitTypeDef::BaudRate, USART_InitTypeDef::CLKLastBit, USART_InitTypeDef::CLKPhase, USART_InitTypeDef::CLKPolarity, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, IS_USART_BAUDRATE, IS_USART_LASTBIT, IS_USART_MODE, IS_USART_PARITY, IS_USART_PHASE, IS_USART_POLARITY, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, LSE_VALUE, USART_InitTypeDef::Mode, USART_InitTypeDef::Parity, USART_InitTypeDef::StopBits, USART_CLOCK_ENABLE, USART_CLOCKSOURCE_HSI, USART_CLOCKSOURCE_LSE, USART_CLOCKSOURCE_PCLK1, USART_CLOCKSOURCE_PCLK2, USART_CLOCKSOURCE_SYSCLK, USART_CLOCKSOURCE_UNDEFINED, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_GETCLOCKSOURCE, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_Init().

static HAL_StatusTypeDef USART_Transmit_IT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1771 of file stm32l4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_IT_TC, USART_IT_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_TransmitReceive_IT ( USART_HandleTypeDef * husart ) [static]

Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_TransmitReceive_IT().
Parameters:
husart,: USART handle.
Return values:
HAL status

Definition at line 1896 of file stm32l4xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_FLAG_RXNE, USART_FLAG_TXE, USART_IT_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle USART Communication Timeout.

Parameters:
husart | USART handle.
Flag | Specifies the USART flag to check.
Status | the Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | timeout duration.
Return values:
HAL status

Definition at line 1611 of file stm32l4xx_hal_usart.c.

References __HAL_USART_GET_FLAG, HAL_GetTick(), HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_CheckIdleState().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Exported Types

Data Structures | Enumerations
USART Exported Types
USART

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00, HAL_USART_STATE_READY = 0x01, HAL_USART_STATE_BUSY = 0x02, HAL_USART_STATE_BUSY_TX = 0x12,
HAL_USART_STATE_BUSY_RX = 0x22, HAL_USART_STATE_BUSY_TX_RX = 0x32, HAL_USART_STATE_TIMEOUT = 0x03, HAL_USART_STATE_ERROR = 0x04
}
HAL USART State structures definition. More...
enum HAL_USART_ErrorTypeDef {
HAL_USART_ERROR_NONE = 0x00, HAL_USART_ERROR_PE = 0x01, HAL_USART_ERROR_NE = 0x02, HAL_USART_ERROR_FE = 0x04,
HAL_USART_ERROR_ORE = 0x08, HAL_USART_ERROR_DMA = 0x10
}
HAL USART Error Code structure definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK1 = 0x00, USART_CLOCKSOURCE_PCLK2 = 0x01, USART_CLOCKSOURCE_HSI = 0x02, USART_CLOCKSOURCE_SYSCLK = 0x04,
USART_CLOCKSOURCE_LSE = 0x08, USART_CLOCKSOURCE_UNDEFINED = 0x10
}
USART clock sources definitions. More...

Enumeration Type Documentation

enum HAL_USART_ErrorTypeDef

HAL USART Error Code structure definition.

Enumerator:
HAL_USART_ERROR_NONE

No error

HAL_USART_ERROR_PE

Parity error

HAL_USART_ERROR_NE

Noise error

HAL_USART_ERROR_FE

frame error

HAL_USART_ERROR_ORE

Overrun error

HAL_USART_ERROR_DMA

DMA transfer error

Definition at line 116 of file stm32l4xx_hal_usart.h.

enum HAL_USART_StateTypeDef

HAL USART State structures definition.

Enumerator:
HAL_USART_STATE_RESET

Peripheral is not initialized

HAL_USART_STATE_READY

Peripheral Initialized and ready for use

HAL_USART_STATE_BUSY

an internal process is ongoing

HAL_USART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_USART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_USART_STATE_BUSY_TX_RX

Data Transmission Reception process is ongoing

HAL_USART_STATE_TIMEOUT

Timeout state

HAL_USART_STATE_ERROR

Error

Definition at line 101 of file stm32l4xx_hal_usart.h.

enum USART_ClockSourceTypeDef

USART clock sources definitions.

Enumerator:
USART_CLOCKSOURCE_PCLK1

PCLK1 clock source

USART_CLOCKSOURCE_PCLK2

PCLK2 clock source

USART_CLOCKSOURCE_HSI

HSI clock source

USART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

USART_CLOCKSOURCE_LSE

LSE clock source

USART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 129 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_InitTypeDef Struct Reference
USART Exported Types

USART Init Structure definition. More...

#include <stm32l4xx_hal_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit

Detailed Description

USART Init Structure definition.

Definition at line 65 of file stm32l4xx_hal_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::BaudRate

This member configures the Usart communication baud rate. The baud rate is computed using the following formula: Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))).

Definition at line 67 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART Last Bit.

Definition at line 93 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART Clock Phase.

Definition at line 90 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of USART Clock Polarity.

Definition at line 87 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART Mode.

Definition at line 84 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of USART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 77 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint32_t USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART Number of Stop Bits.

Definition at line 74 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USARTEx Word Length.

Definition at line 71 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_usart.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_HandleTypeDef Struct Reference
USART Exported Types

USART handle Structure definition. More...

#include <stm32l4xx_hal_usart.h>

Data Fields

USART_TypeDef * | Instance
USART_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_USART_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

USART handle Structure definition.

Definition at line 143 of file stm32l4xx_hal_usart.h.

Field Documentation

__IO uint32_t USART_HandleTypeDef::ErrorCode

USART Error code

Definition at line 171 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_GetError(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), and USART_DMAError().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmarx

USART Rx DMA Handle parameters

Definition at line 165 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmatx

USART Tx DMA Handle parameters

Definition at line 163 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

USART_InitTypeDef USART_HandleTypeDef::Init

USART communication parameters

Definition at line 147 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

USART_TypeDef* USART_HandleTypeDef::Instance

USART registers base address

Definition at line 145 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndTransfer(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

HAL_LockTypeDef USART_HandleTypeDef::Lock

Locking object

Definition at line 167 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Init().

uint16_t USART_HandleTypeDef::Mask

USART Rx RDR register mask

Definition at line 161 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint8_t* USART_HandleTypeDef::pRxBuffPtr

Pointer to USART Rx transfer Buffer

Definition at line 155 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint8_t* USART_HandleTypeDef::pTxBuffPtr

Pointer to USART Tx transfer Buffer

Definition at line 149 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::RxXferCount

USART Rx Transfer Counter

Definition at line 159 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::RxXferSize

USART Rx Transfer size

Definition at line 157 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

__IO HAL_USART_StateTypeDef USART_HandleTypeDef::State

USART communication state

Definition at line 169 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_GetState(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

uint16_t USART_HandleTypeDef::TxXferCount

USART Tx Transfer Counter

Definition at line 153 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMATransmitCplt(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::TxXferSize

USART Tx Transfer size

Definition at line 151 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_usart.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Number of Stop Bits

Defines
USART Number of Stop Bits
USART Exported Constants

Defines

#define | USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | USART_STOPBITS_1 ((uint32_t)0x00000000)
#define | USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define USART_STOPBITS_0_5 USART_CR2_STOP_0

USART frame with 0.5 stop bit

Definition at line 187 of file stm32l4xx_hal_usart.h.

#define USART_STOPBITS_1 ((uint32_t)0x00000000)

USART frame with 1 stop bit

Definition at line 188 of file stm32l4xx_hal_usart.h.

#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

USART frame with 1.5 stop bits

Definition at line 189 of file stm32l4xx_hal_usart.h.

#define USART_STOPBITS_2 USART_CR2_STOP_1

USART frame with 2 stop bits

Definition at line 190 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Parity

Defines
USART Parity
USART Exported Constants

Defines

#define | USART_PARITY_NONE ((uint32_t)0x00000000)
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Even parity

Definition at line 199 of file stm32l4xx_hal_usart.h.

#define USART_PARITY_NONE ((uint32_t)0x00000000)

No parity

Definition at line 198 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Odd parity

Definition at line 200 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Mode

Defines
USART Mode
USART Exported Constants

Defines

#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define USART_MODE_RX ((uint32_t)USART_CR1_RE)

RX mode

Definition at line 208 of file stm32l4xx_hal_usart.h.

#define USART_MODE_TX ((uint32_t)USART_CR1_TE)

TX mode

Definition at line 209 of file stm32l4xx_hal_usart.h.

#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

RX and TX mode

Definition at line 210 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Over Sampling

Defines
USART Over Sampling
USART Exported Constants

Defines

#define | USART_OVERSAMPLING_16 ((uint32_t)0x00000000)
#define | USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Define Documentation

#define USART_OVERSAMPLING_16 ((uint32_t)0x00000000)

Oversampling by 16

Definition at line 218 of file stm32l4xx_hal_usart.h.

#define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)

Oversampling by 8

Definition at line 219 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Clock

Defines
USART Clock
USART Exported Constants

Defines

#define | USART_CLOCK_DISABLE ((uint32_t)0x00000000)
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

Define Documentation

#define USART_CLOCK_DISABLE ((uint32_t)0x00000000)

USART clock disable

Definition at line 227 of file stm32l4xx_hal_usart.h.

#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

USART clock enable

Definition at line 228 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Clock Polarity

Defines
USART Clock Polarity
USART Exported Constants

Defines

#define | USART_POLARITY_LOW ((uint32_t)0x00000000)
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Driver enable signal is active low

Definition at line 237 of file stm32l4xx_hal_usart.h.

#define USART_POLARITY_LOW ((uint32_t)0x00000000)

Driver enable signal is active high

Definition at line 236 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Clock Phase

Defines
USART Clock Phase
USART Exported Constants

Defines

#define | USART_PHASE_1EDGE ((uint32_t)0x00000000)
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define USART_PHASE_1EDGE ((uint32_t)0x00000000)

USART frame phase on first clock transition

Definition at line 245 of file stm32l4xx_hal_usart.h.

#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

USART frame phase on second clock transition

Definition at line 246 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Last Bit

Defines
USART Last Bit
USART Exported Constants

Defines

#define | USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000)

USART frame last data bit clock pulse not output to SCLK pin

Definition at line 254 of file stm32l4xx_hal_usart.h.

#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

USART frame last data bit clock pulse output to SCLK pin

Definition at line 255 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Request Parameters

Defines
USART Request Parameters
USART Exported Constants

Defines

#define | USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Define Documentation

#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)

Receive Data flush Request

Definition at line 263 of file stm32l4xx_hal_usart.h.

#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)

Transmit data flush Request

Definition at line 264 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Flags

Defines
USART Flags
USART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | USART_FLAG_REACK ((uint32_t)0x00400000)
#define | USART_FLAG_TEACK ((uint32_t)0x00200000)
#define | USART_FLAG_BUSY ((uint32_t)0x00010000)
#define | USART_FLAG_CTS ((uint32_t)0x00000400)
#define | USART_FLAG_CTSIF ((uint32_t)0x00000200)
#define | USART_FLAG_LBDF ((uint32_t)0x00000100)
#define | USART_FLAG_TXE ((uint32_t)0x00000080)
#define | USART_FLAG_TC ((uint32_t)0x00000040)
#define | USART_FLAG_RXNE ((uint32_t)0x00000020)
#define | USART_FLAG_IDLE ((uint32_t)0x00000010)
#define | USART_FLAG_ORE ((uint32_t)0x00000008)
#define | USART_FLAG_NE ((uint32_t)0x00000004)
#define | USART_FLAG_FE ((uint32_t)0x00000002)
#define | USART_FLAG_PE ((uint32_t)0x00000001)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define USART_FLAG_BUSY ((uint32_t)0x00010000)

USART busy flag

Definition at line 276 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_CTS ((uint32_t)0x00000400)

USART clear to send flag

Definition at line 277 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_CTSIF ((uint32_t)0x00000200)

USART clear to send interrupt flag

Definition at line 278 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_FE ((uint32_t)0x00000002)

USART frame error

Definition at line 286 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_IDLE ((uint32_t)0x00000010)

USART idle flag

Definition at line 283 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_LBDF ((uint32_t)0x00000100)

USART LIN break detection flag

Definition at line 279 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_NE ((uint32_t)0x00000004)

USART noise error

Definition at line 285 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_ORE ((uint32_t)0x00000008)

USART overrun error

Definition at line 284 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_PE ((uint32_t)0x00000001)

USART parity error

Definition at line 287 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_REACK ((uint32_t)0x00400000)

USART receive enable acknowledge flag

Definition at line 274 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_RXNE ((uint32_t)0x00000020)

USART read data register not empty

Definition at line 282 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), and USART_TransmitReceive_IT().

#define USART_FLAG_TC ((uint32_t)0x00000040)

USART transmission complete

Definition at line 281 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), and HAL_USART_TransmitReceive().

#define USART_FLAG_TEACK ((uint32_t)0x00200000)

USART transmit enable acknowledge flag

Definition at line 275 of file stm32l4xx_hal_usart.h.

#define USART_FLAG_TXE ((uint32_t)0x00000080)

USART transmit data register empty

Definition at line 280 of file stm32l4xx_hal_usart.h.

Referenced by USART_TransmitReceive_IT().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Interrupts Definition

Defines
USART Interrupts Definition
USART Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | USART_IT_PE ((uint16_t)0x0028)
#define | USART_IT_TXE ((uint16_t)0x0727)
#define | USART_IT_TC ((uint16_t)0x0626)
#define | USART_IT_RXNE ((uint16_t)0x0525)
#define | USART_IT_IDLE ((uint16_t)0x0424)
#define | USART_IT_ERR ((uint16_t)0x0060)
#define | USART_IT_ORE ((uint16_t)0x0300)
#define | USART_IT_NE ((uint16_t)0x0200)
#define | USART_IT_FE ((uint16_t)0x0100)

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define USART_IT_ERR ((uint16_t)0x0060)

USART error interruption

Definition at line 308 of file stm32l4xx_hal_usart.h.

Referenced by USART_EndTransmit_IT().

#define USART_IT_FE ((uint16_t)0x0100)

USART frame error interruption

Definition at line 311 of file stm32l4xx_hal_usart.h.

#define USART_IT_IDLE ((uint16_t)0x0424)

USART idle interruption

Definition at line 307 of file stm32l4xx_hal_usart.h.

#define USART_IT_NE ((uint16_t)0x0200)

USART noise error interruption

Definition at line 310 of file stm32l4xx_hal_usart.h.

#define USART_IT_ORE ((uint16_t)0x0300)

USART overrun error interruption

Definition at line 309 of file stm32l4xx_hal_usart.h.

#define USART_IT_PE ((uint16_t)0x0028)

USART parity error interruption

Definition at line 303 of file stm32l4xx_hal_usart.h.

#define USART_IT_RXNE ((uint16_t)0x0525)

USART read data register not empty interruption

Definition at line 306 of file stm32l4xx_hal_usart.h.

#define USART_IT_TC ((uint16_t)0x0626)

USART transmission complete interruption

Definition at line 305 of file stm32l4xx_hal_usart.h.

Referenced by USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_Transmit_IT().

#define USART_IT_TXE ((uint16_t)0x0727)

USART transmit data register empty interruption

Definition at line 304 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Interruption Clear Flags

Defines
USART Interruption Clear Flags
USART Exported Constants

Defines

#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NCF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF

Define Documentation

#define USART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 320 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 323 of file stm32l4xx_hal_usart.h.

#define USART_CLEAR_NEF USART_ICR_NCF

Noise detected Clear Flag

Definition at line 321 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 322 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_DMAResume(), and HAL_USART_IRQHandler().

#define USART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 319 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define USART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 324 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Interruption Flags Mask

Defines
USART Interruption Flags Mask
USART Exported Constants

Defines

#define USART_IT_MASK ((uint16_t)0x001F)

Define Documentation

#define USART_IT_MASK ((uint16_t)0x001F)

USART interruptions flags mask

Definition at line 332 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Exported Macros

Defines
USART Exported Macros
USART

Defines

#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.

Define Documentation

#define __HAL_USART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)

Clear the USART FE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 396 of file stm32l4xx_hal_usart.h.

#define __HAL_USART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified USART pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • USART_CLEAR_PEF
  • USART_CLEAR_FEF
  • USART_CLEAR_NEF
  • USART_CLEAR_OREF
  • USART_CLEAR_IDLEF
  • USART_CLEAR_TCF
Return values:
None

Definition at line 384 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_DMAResume(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define __HAL_USART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)

Clear the USART IDLE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 414 of file stm32l4xx_hal_usart.h.

#define __HAL_USART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified USART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
__IT_CLEAR__,: specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • USART_CLEAR_PEF Parity Error Clear Flag
  • USART_CLEAR_FEF Framing Error Clear Flag
  • USART_CLEAR_NEF Noise detected Clear Flag
  • USART_CLEAR_OREF OverRun Error Clear Flag
  • USART_CLEAR_IDLEF IDLE line detected Clear Flag
  • USART_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 497 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)

Clear the USART NE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 402 of file stm32l4xx_hal_usart.h.

#define __HAL_USART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)

Clear the USART ORE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 408 of file stm32l4xx_hal_usart.h.

#define __HAL_USART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)

Clear the USART PE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 390 of file stm32l4xx_hal_usart.h.

#define __HAL_USART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable USART.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 532 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Init().

#define __HAL_USART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Disable the specified USART interrupt.

Parameters:
__HANDLE__,: specifies the USART Handle.
__INTERRUPT__,: specifies the USART interrupt source to disable. This parameter can be one of the following values:
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 444 of file stm32l4xx_hal_usart.h.

Referenced by USART_EndTransmit_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

#define __HAL_USART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable USART.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 526 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Init().

#define __HAL_USART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Enable the specified USART interrupt.

Parameters:
__HANDLE__,: specifies the USART Handle.
__INTERRUPT__,: specifies the USART interrupt source to enable. This parameter can be one of the following values:
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 428 of file stm32l4xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_DMATransmitCplt(), and USART_Transmit_IT().

#define __HAL_USART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified USART flag is set or not.

Parameters:
__HANDLE__,: specifies the USART Handle
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • USART_FLAG_REACK Receive enable acknowledge flag
  • USART_FLAG_TEACK Transmit enable acknowledge flag
  • USART_FLAG_BUSY Busy flag
  • USART_FLAG_CTS CTS Change flag
  • USART_FLAG_TXE Transmit data register empty flag
  • USART_FLAG_TC Transmission Complete flag
  • USART_FLAG_RXNE Receive data register not empty flag
  • USART_FLAG_IDLE Idle Line detection flag
  • USART_FLAG_ORE OverRun Error flag
  • USART_FLAG_NE Noise Error flag
  • USART_FLAG_FE Framing Error flag
  • USART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 370 of file stm32l4xx_hal_usart.h.

Referenced by USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_GET_IT | ( | __HANDLE__,
 |  | __IT__
 | ) | ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))

Check whether the specified USART interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the USART Handle.
__IT__,: specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 463 of file stm32l4xx_hal_usart.h.

#define __HAL_USART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
                                                   (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
                                                   (((uint16_t)(__IT__)) & USART_IT_MASK)))

Check whether the specified USART interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the USART Handle.
__IT__,: specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 479 of file stm32l4xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the USART one bit sample method.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 520 of file stm32l4xx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the USART one bit sample method.

Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None

Definition at line 514 of file stm32l4xx_hal_usart.h.

#define __HAL_USART_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_USART_STATE_RESET)

Reset USART handle state.

Parameters:
__HANDLE__,: USART handle.
Return values:
None

Definition at line 350 of file stm32l4xx_hal_usart.h.

#define __HAL_USART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (__REQ__))

Set a specific USART request flag.

Parameters:
__HANDLE__,: specifies the USART Handle.
__REQ__,: specifies the request flag to set. This parameter can be one of the following values:
  • USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 508 of file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
Ensure that USART communication mode is valid.
#define | IS_USART_OVERSAMPLING(__SAMPLING__)
Ensure that USART oversampling is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.

Define Documentation

#define IS_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 10000001)

Check USART Baud rate.

Parameters:
__BAUDRATE__,: Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz) divided by the smallest oversampling used on the USART (i.e. 8).
Return values:
Test result (TRUE or FALSE).

Definition at line 549 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == USART_CLOCK_DISABLE) || \
                                   ((__CLOCK__) == USART_CLOCK_ENABLE))

Ensure that USART clock state is valid.

Parameters:
__CLOCK__,: USART clock state.
Return values:
SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)

Definition at line 590 of file stm32l4xx_hal_usart.h.

#define IS_USART_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))

Ensure that USART frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__,: USART frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 612 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_MODE ( __MODE__ ) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))

Ensure that USART communication mode is valid.

Parameters:
__MODE__,: USART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 575 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == USART_OVERSAMPLING_16) || \
                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))

Ensure that USART oversampling is valid.

Parameters:
__SAMPLING__,: USART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 582 of file stm32l4xx_hal_usart.h.

#define IS_USART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == USART_PARITY_NONE) || \
                                     ((__PARITY__) == USART_PARITY_EVEN) || \
                                     ((__PARITY__) == USART_PARITY_ODD))

Ensure that USART frame parity is valid.

Parameters:
__PARITY__,: USART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 566 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PHASE ( __CPHA__ ) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))

Ensure that USART frame phase is valid.

Parameters:
__CPHA__,: USART frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 605 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_POLARITY ( __CPOL__ ) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))

Ensure that USART frame polarity is valid.

Parameters:
__CPOL__,: USART frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 598 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))

Ensure that USART request parameter is valid.

Parameters:
__PARAM__,: USART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 620 of file stm32l4xx_hal_usart.h.

#define IS_USART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == USART_STOPBITS_0_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_2))

Ensure that USART frame number of stop bits is valid.

Parameters:
__STOPBITS__,: USART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 556 of file stm32l4xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
WWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
          ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Initialize and start the WWDG according to the specified parameters
          in the WWDG_InitTypeDef of associated handle.
      (+) Initialize the WWDG MSP.

Function Documentation

HAL_StatusTypeDef HAL_WWDG_Init ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG according to the specified.

parameters in the WWDG_InitTypeDef of associated handle.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 174 of file stm32l4xx_hal_wwdg.c.

References assert_param, WWDG_InitTypeDef::Counter, WWDG_InitTypeDef::EWIMode, HAL_WWDG_MspInit(), WWDG_HandleTypeDef::Init, WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, IS_WWDG_EWI_MODE, IS_WWDG_PRESCALER, IS_WWDG_WINDOW, WWDG_InitTypeDef::Prescaler, and WWDG_InitTypeDef::Window.

void HAL_WWDG_MspInit ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG MSP.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Note:
When rewriting this function in user file, mechanism may be added to avoid multiple initialize when HAL_WWDG_Init function is called again to change parameters.
Return values:
None

Definition at line 212 of file stm32l4xx_hal_wwdg.c.

Referenced by HAL_WWDG_Init().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IO operation functions

Functions
IO operation functions
WWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

IO operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Refresh the WWDG.
    (+) Handle WWDG interrupt request and associated function callback.

Function Documentation

void HAL_WWDG_EarlyWakeupCallback ( WWDG_HandleTypeDef * hwwdg )

WWDG Early Wakeup callback.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 295 of file stm32l4xx_hal_wwdg.c.

Referenced by HAL_WWDG_IRQHandler().

void HAL_WWDG_IRQHandler ( WWDG_HandleTypeDef * hwwdg )

Handle WWDG interrupt request.

Note:
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by calling HAL_WWDG_Init function with EWIMode set to WWDG_EWI_ENABLE. When the downcounter reaches the value 0x40, and EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 271 of file stm32l4xx_hal_wwdg.c.

References __HAL_WWDG_CLEAR_FLAG, __HAL_WWDG_GET_FLAG, __HAL_WWDG_GET_IT_SOURCE, HAL_WWDG_EarlyWakeupCallback(), WWDG_FLAG_EWIF, and WWDG_IT_EWI.

HAL_StatusTypeDef HAL_WWDG_Refresh ( WWDG_HandleTypeDef * hwwdg )

Refresh the WWDG.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 248 of file stm32l4xx_hal_wwdg.c.

References WWDG_InitTypeDef::Counter, WWDG_HandleTypeDef::Init, and WWDG_HandleTypeDef::Instance.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_InitTypeDef Struct Reference
WWDG Exported Types

WWDG Init structure definition. More...

#include <stm32l4xx_hal_wwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Window
uint32_t | Counter
uint32_t | EWIMode

Detailed Description

WWDG Init structure definition.

Definition at line 66 of file stm32l4xx_hal_wwdg.h.

Field Documentation

uint32_t WWDG_InitTypeDef::Counter

Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 74 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

uint32_t WWDG_InitTypeDef::EWIMode

Specifies if WWDG Early Wakeup Interupt is enable or not. This parameter can be a value of WWDG Early Wakeup Interrupt Mode

Definition at line 77 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Prescaler

Specifies the prescaler value of the WWDG. This parameter can be a value of WWDG Prescaler

Definition at line 68 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Window

Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 71 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_wwdg.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_HandleTypeDef Struct Reference
WWDG Exported Types

WWDG handle Structure definition. More...

#include <stm32l4xx_hal_wwdg.h>

Data Fields

WWDG_TypeDef * Instance
WWDG_InitTypeDef Init

Detailed Description

WWDG handle Structure definition.

Definition at line 85 of file stm32l4xx_hal_wwdg.h.

Field Documentation

WWDG_InitTypeDef WWDG_HandleTypeDef::Init

WWDG required parameters

Definition at line 89 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

WWDG_TypeDef* WWDG_HandleTypeDef::Instance

Register base address

Definition at line 87 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

The documentation for this struct was generated from the following file:
  • stm32l4xx_hal_wwdg.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Interrupt definition

Defines
WWDG Interrupt definition
WWDG Exported Constants

Defines

#define WWDG_IT_EWI WWDG_CFR_EWI

Define Documentation

#define WWDG_IT_EWI WWDG_CFR_EWI

Early wakeup interrupt

Definition at line 105 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Flag definition

Defines
WWDG Flag definition
WWDG Exported Constants

WWDG Flag definition. More...

Defines

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Detailed Description

WWDG Flag definition.

Define Documentation

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Early wakeup interrupt flag

Definition at line 114 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Prescaler

Defines
WWDG Prescaler
WWDG Exported Constants

Defines

#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 WWDG_CFR_WDGTB

Define Documentation

#define WWDG_PRESCALER_1 0x00000000u

WWDG counter clock = (PCLK1/4096)/1

Definition at line 122 of file stm32l4xx_hal_wwdg.h.

#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 123 of file stm32l4xx_hal_wwdg.h.

#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 124 of file stm32l4xx_hal_wwdg.h.

#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB

WWDG counter clock = (PCLK1/4096)/8

Definition at line 125 of file stm32l4xx_hal_wwdg.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Early Wakeup Interrupt Mode

Defines
WWDG Early Wakeup Interrupt Mode
WWDG Exported Constants

Defines

#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI

Define Documentation

#define WWDG_EWI_DISABLE 0x00000000u

EWI Disable

Definition at line 133 of file stm32l4xx_hal_wwdg.h.

#define WWDG_EWI_ENABLE WWDG_CFR_EWI

EWI Enable

Definition at line 134 of file stm32l4xx_hal_wwdg.h.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Private Macros

Defines
WWDG Private Macros
WWDG

Defines

#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)

Define Documentation

#define IS_WWDG_COUNTER ( __COUNTER__ ) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))

Definition at line 155 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_EWI_MODE ( __MODE__ )
Value:
(((__MODE__) == WWDG_EWI_ENABLE) || \
                                             ((__MODE__) == WWDG_EWI_DISABLE))

Definition at line 157 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == WWDG_PRESCALER_1) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_2) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_4) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_8))

Definition at line 148 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_WINDOW ( __WINDOW__ ) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))

Definition at line 153 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Exported Macros

Defines
WWDG Exported Macros
WWDG

Defines

#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified WWDG interrupt source is enabled or not.

Define Documentation

#define __HAL_WWDG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the WWDG's pending flags.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
None

Definition at line 225 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

Clear the WWDG interrupt pending bits.

bits to clear the selected interrupt pending bits.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag

Definition at line 205 of file stm32l4xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

Enable the WWDG peripheral.

Parameters:
__HANDLE__ WWDG handle
Return values:
None

Definition at line 175 of file stm32l4xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

Enable the WWDG early wakeup interrupt.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__ specifies the interrupt to enable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 186 of file stm32l4xx_hal_wwdg.h.

#define __HAL_WWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified WWDG flag is set or not.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 215 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

Check whether the selected WWDG interrupt has occurred or not.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the it to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt IT
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 196 of file stm32l4xx_hal_wwdg.h.

#define __HAL_WWDG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified WWDG interrupt source is enabled or not.

Parameters:
__HANDLE__ WWDG Handle.
__INTERRUPT__ specifies the WWDG interrupt source to check. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early Wakeup Interrupt
Return values:
state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 234 of file stm32l4xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDAEx Private Macros

Defines
IRDAEx Private Macros
IRDAEx

Defines

#define IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.

Define Documentation

#define IRDA_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the IRDA clock source.

Parameters:
__HANDLE__,: specifies the IRDA Handle.
__CLOCKSOURCE__,: output variable.
Return values:
IRDA clocking source, written in __CLOCKSOURCE__.

Definition at line 74 of file stm32l4xx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Extended Input and Output operation functions

Functions
Extended Input and Output operation functions
OPAMPEx Exported Functions

Functions

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
Run the self calibration of the 2 OPAMPs in parallel.

Function Documentation

HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll | ( | OPAMP_HandleTypeDef * | hopamp1,
 |  | OPAMP_HandleTypeDef * | hopamp2
 | ) |  |

Run the self calibration of the 2 OPAMPs in parallel.

Note:
Trimming values (PMOS & NMOS) are updated and user trimming is enabled is calibration is successful.
Calibration is performed in the mode specified in OPAMP init structure (mode normal or low-power). To perform calibration for both modes, repeat this function twice after OPAMP init structure accordingly updated.
Calibration runs about 10 ms (5 dichotomy steps, repeated for P and N transistors: 10 steps with 1 ms for each step).
Parameters:
hopamp1 | handle
hopamp2 | handle
Return values:
HAL status

Definition at line 105 of file stm32l4xx_hal_opamp_ex.c.

References assert_param, HAL_Delay(), HAL_OPAMP_STATE_BUSYLOCKED, HAL_OPAMP_STATE_READY, OPAMP_HandleTypeDef::Init, OPAMP_HandleTypeDef::Instance, IS_OPAMP_POWERMODE, OPAMP_INPUT_NONINVERTING, OPAMP_POWERMODE_LOWPOWER, OPAMP_POWERMODE_NORMAL, OPAMP_STANDALONE_MODE, OPAMP_TRIMMING_DELAY, OPAMP_TRIMMING_USER, OPAMP_InitTypeDef::PowerMode, OPAMP_HandleTypeDef::State, OPAMP_InitTypeDef::TrimmingValueN, OPAMP_InitTypeDef::TrimmingValueNLowPower, OPAMP_InitTypeDef::TrimmingValueP, OPAMP_InitTypeDef::TrimmingValuePLowPower, and OPAMP_InitTypeDef::UserTrimming.

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
OPAMPEx Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_OPAMPEx_Unlock (OPAMP_HandleTypeDef *hopamp)
Unlock the selected OPAMP configuration.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]
      (+) OPAMP unlock.

Function Documentation

HAL_StatusTypeDef HAL_OPAMPEx_Unlock ( OPAMP_HandleTypeDef * hopamp )

Unlock the selected OPAMP configuration.

Note:
This function must be called only when OPAMP is in state "locked".
Parameters:
hopamp,: OPAMP handle
Return values:
HAL status

Definition at line 413 of file stm32l4xx_hal_opamp_ex.c.

References assert_param, HAL_OPAMP_STATE_BUSY, HAL_OPAMP_STATE_CALIBBUSY, HAL_OPAMP_STATE_READY, HAL_OPAMP_STATE_RESET, OPAMP_HandleTypeDef::Instance, and OPAMP_HandleTypeDef::State.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SD_Private_Defines

Defines
SD_Private_Defines
SD

Defines

#define | DATA_BLOCK_SIZE ((uint32_t)(9 << 4))
SDMMC Data block size.
#define | SDMMC_STATIC_FLAGS
SDMMC Static flags, Timeout, FIFO Address.
#define | SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000)
#define | SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)
Mask for errors Card Status R1 (OCR Register)
#define | SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)
#define | SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)
#define | SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)
#define | SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)
#define | SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)
#define | SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)
#define | SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)
#define | SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)
#define | SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)
#define | SD_OCR_CC_ERROR ((uint32_t)0x00100000)
#define | SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
#define | SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
#define | SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
#define | SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
#define | SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
#define | SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
#define | SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
#define | SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)
#define | SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)
#define | SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)
Masks for R6 Response.
#define | SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)
#define | SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)
#define | SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)
#define | SD_HIGH_CAPACITY ((uint32_t)0x40000000)
#define | SD_STD_CAPACITY ((uint32_t)0x00000000)
#define | SD_CHECK_PATTERN ((uint32_t)0x000001AA)
#define | SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
#define | SD_ALLZERO ((uint32_t)0x00000000)
#define | SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)
#define | SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)
#define | SD_CARD_LOCKED ((uint32_t)0x02000000)
#define | SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)
#define | SD_0TO7BITS ((uint32_t)0x000000FF)
#define | SD_8TO15BITS ((uint32_t)0x0000FF00)
#define | SD_16TO23BITS ((uint32_t)0x00FF0000)
#define | SD_24TO31BITS ((uint32_t)0xFF000000)
#define | SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)
#define | SD_HALFFIFO ((uint32_t)0x00000008)
#define | SD_HALFFIFOBYTES ((uint32_t)0x00000020)
#define | SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)
Command Class Supported.
#define | SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)
#define | SD_CCCC_ERASE ((uint32_t)0x00000020)
#define | SD_SDMMC_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
Following commands are SD Card Specific commands.

Define Documentation

#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4))

SDMMC Data block size.

Definition at line 205 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_ReadBlocks().

#define SD_0TO7BITS ((uint32_t)0x000000FF)

Definition at line 260 of file stm32l4xx_hal_sd.c.

Referenced by SD_FindSCR().

#define SD_16TO23BITS ((uint32_t)0x00FF0000)

Definition at line 262 of file stm32l4xx_hal_sd.c.

Referenced by SD_FindSCR().

#define SD_24TO31BITS ((uint32_t)0xFF000000)

Definition at line 263 of file stm32l4xx_hal_sd.c.

Referenced by SD_FindSCR().

#define SD_8TO15BITS ((uint32_t)0x0000FF00)

Definition at line 261 of file stm32l4xx_hal_sd.c.

Referenced by SD_FindSCR().

#define SD_ALLZERO ((uint32_t)0x00000000)

Definition at line 253 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_HighSpeed(), SD_CmdResp1Error(), SD_CmdResp6Error(), SD_IsCardProgramming(), SD_WideBus_Disable(), and SD_WideBus_Enable().

#define SD_CARD_LOCKED ((uint32_t)0x02000000)

Definition at line 257 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_Erase(), HAL_SD_SendSDStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

#define SD_CCCC_ERASE ((uint32_t)0x00000020)

Definition at line 274 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_Erase().

#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)

Command Class Supported.

Definition at line 272 of file stm32l4xx_hal_sd.c.

#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)

Definition at line 273 of file stm32l4xx_hal_sd.c.

#define SD_CHECK_PATTERN ((uint32_t)0x000001AA)

Definition at line 250 of file stm32l4xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)

Definition at line 259 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_Erase(), HAL_SD_HighSpeed(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_SendSDStatus(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), and SD_FindSCR().

#define SD_HALFFIFO ((uint32_t)0x00000008)

Definition at line 266 of file stm32l4xx_hal_sd.c.

#define SD_HALFFIFOBYTES ((uint32_t)0x00000020)

Definition at line 267 of file stm32l4xx_hal_sd.c.

#define SD_HIGH_CAPACITY ((uint32_t)0x40000000)

Definition at line 248 of file stm32l4xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)

Definition at line 264 of file stm32l4xx_hal_sd.c.

#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)

Definition at line 252 of file stm32l4xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)

Definition at line 220 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)

Mask for errors Card Status R1 (OCR Register)

Definition at line 219 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)

Definition at line 237 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)

Definition at line 223 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)

Definition at line 221 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)

Definition at line 235 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)

Definition at line 228 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_CC_ERROR ((uint32_t)0x00100000)

Definition at line 229 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)

Definition at line 233 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)

Definition at line 226 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)

Definition at line 236 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)

Definition at line 222 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)

Definition at line 238 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)

Definition at line 230 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)

Definition at line 227 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)

Definition at line 225 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)

Definition at line 231 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)

Definition at line 232 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)

Definition at line 234 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)

Definition at line 224 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp1Error(), and SD_IsCardProgramming().

#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)

Definition at line 245 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp6Error().

#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)

Masks for R6 Response.

Definition at line 243 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp6Error().

#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)

Definition at line 244 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdResp6Error().

#define SD_SDMMC_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)

Following commands are SD Card Specific commands.

SDMMC_APP_CMD should be sent before sending these commands.

Definition at line 280 of file stm32l4xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)

Definition at line 256 of file stm32l4xx_hal_sd.c.

Referenced by SD_WideBus_Disable().

#define SD_STD_CAPACITY ((uint32_t)0x00000000)

Definition at line 249 of file stm32l4xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)

Definition at line 247 of file stm32l4xx_hal_sd.c.

Referenced by SD_PowerON().

#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)

Definition at line 255 of file stm32l4xx_hal_sd.c.

Referenced by SD_WideBus_Enable().

#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000)

Definition at line 214 of file stm32l4xx_hal_sd.c.

Referenced by SD_CmdError(), and SD_CmdResp7Error().

#define SDMMC_STATIC_FLAGS
Value:
((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
                                                    SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\
                                                    SDMMC_FLAG_CMDREND  | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\
                                                    SDMMC_FLAG_DBCKEND))

SDMMC Static flags, Timeout, FIFO Address.

Definition at line 209 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_CheckReadOperation(), HAL_SD_CheckWriteOperation(), HAL_SD_HighSpeed(), HAL_SD_ReadBlocks(), HAL_SD_SendSDStatus(), HAL_SD_WriteBlocks(), SD_CmdError(), SD_CmdResp1Error(), SD_CmdResp2Error(), SD_CmdResp3Error(), SD_CmdResp6Error(), SD_FindSCR(), and SD_IsCardProgramming().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SD_Private_Functions_Prototypes

SD_Private_Functions_Prototypes
SD
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SD_Exported_Functions_Group1

Functions
SD_Exported_Functions_Group1
SD_Exported_Functions

Initialization and de-initialization functions. More...

Functions

HAL_SD_ErrorTypedef | HAL_SD_Init (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
Initializes the SD card according to the specified parameters in the SD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.

Detailed Description

Initialization and de-initialization functions.

  ==============================================================================
          ##### Initialization and de-initialization functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to initialize/de-initialize the SD
    card device to be ready for use.

Function Documentation

HAL_StatusTypeDef HAL_SD_DeInit ( SD_HandleTypeDef * hsd )

De-Initializes the SD card.

Parameters:
hsd,: SD handle
Return values:
HAL status

Definition at line 397 of file stm32l4xx_hal_sd.c.

References HAL_SD_MspDeInit(), and SD_PowerOFF().

HAL_SD_ErrorTypedef HAL_SD_Init | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardInfoTypedef * | SDCardInfo
 | ) |  |

Initializes the SD card according to the specified parameters in the SD_HandleTypeDef and initialize the associated handle.

Parameters:
hsd,: SD handle
SDCardInfo,: HAL_SD_CardInfoTypedef structure for SD card information
Return values:
HAL SD error state

Definition at line 342 of file stm32l4xx_hal_sd.c.

References HAL_SD_Get_CardInfo(), HAL_SD_MspInit(), SD_Initialize_Cards(), SD_PowerON(), and SD_Select_Deselect().

__weak void HAL_SD_MspDeInit ( SD_HandleTypeDef * hsd )

De-Initialize SD MSP.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 430 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_DeInit().

__weak void HAL_SD_MspInit ( SD_HandleTypeDef * hsd )

Initializes the SD MSP.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 415 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_Init().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SD_Exported_Functions_Group2

Functions
SD_Exported_Functions_Group2
SD_Exported_Functions

Data transfer functions. More...

Functions

HAL_SD_ErrorTypedef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Allows to write block(s) to a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_CheckReadOperation (SD_HandleTypeDef *hsd, uint32_t Timeout)
This function waits until the SD DMA data read transfer is finished.
HAL_SD_ErrorTypedef | HAL_SD_CheckWriteOperation (SD_HandleTypeDef *hsd, uint32_t Timeout)
This function waits until the SD DMA data write transfer is finished.
HAL_SD_ErrorTypedef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
Erases the specified memory area of the given SD card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
__weak void | HAL_SD_XferCpltCallback (SD_HandleTypeDef *hsd)
SD end of transfer callback.
__weak void | HAL_SD_XferErrorCallback (SD_HandleTypeDef *hsd)
SD Transfer Error callback.
__weak void | HAL_SD_DMA_RxCpltCallback (DMA_HandleTypeDef *hdma)
SD Transfer complete Rx callback in non-blocking mode.
__weak void | HAL_SD_DMA_RxErrorCallback (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Rx error callback.
__weak void | HAL_SD_DMA_TxCpltCallback (DMA_HandleTypeDef *hdma)
SD Transfer complete Tx callback in non-blocking mode.
__weak void | HAL_SD_DMA_TxErrorCallback (DMA_HandleTypeDef *hdma)
SD DMA transfer complete error Tx callback.

Detailed Description

Data transfer functions.

  ==============================================================================
                        ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the data
    transfer from/to SD card.

Function Documentation

HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | Timeout
 | ) |  |

This function waits until the SD DMA data read transfer is finished.

This API should be called after HAL_SD_ReadBlocks_DMA() function to insure that all data sent by the card is already transferred by the DMA controller.

Parameters:
hsd,: SD handle
Timeout,: Timeout duration
Return values:
SD Card error state

Definition at line 1095 of file stm32l4xx_hal_sd.c.

References HAL_SD_StopTransfer(), and SDMMC_STATIC_FLAGS.

HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | Timeout
 | ) |  |

This function waits until the SD DMA data write transfer is finished.

This API should be called after HAL_SD_WriteBlocks_DMA() function to insure that all data sent by the card is already transferred by the DMA controller.

Parameters:
hsd,: SD handle
Timeout,: Timeout duration
Return values:
SD Card error state

Definition at line 1155 of file stm32l4xx_hal_sd.c.

References HAL_SD_GetStatus(), HAL_SD_StopTransfer(), and SDMMC_STATIC_FLAGS.

__weak void HAL_SD_DMA_RxCpltCallback ( DMA_HandleTypeDef * hdma )

SD Transfer complete Rx callback in non-blocking mode.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1418 of file stm32l4xx_hal_sd.c.

Referenced by SD_DMA_RxCplt().

__weak void HAL_SD_DMA_RxErrorCallback ( DMA_HandleTypeDef * hdma )

SD DMA transfer complete Rx error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1434 of file stm32l4xx_hal_sd.c.

Referenced by SD_DMA_RxError().

__weak void HAL_SD_DMA_TxCpltCallback ( DMA_HandleTypeDef * hdma )

SD Transfer complete Tx callback in non-blocking mode.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1450 of file stm32l4xx_hal_sd.c.

Referenced by SD_DMA_TxCplt().

__weak void HAL_SD_DMA_TxErrorCallback ( DMA_HandleTypeDef * hdma )

SD DMA transfer complete error Tx callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1466 of file stm32l4xx_hal_sd.c.

Referenced by SD_DMA_TxError().

HAL_SD_ErrorTypedef HAL_SD_Erase | ( | SD_HandleTypeDef * | hsd,
 |  | uint64_t | startaddr,
 |  | uint64_t | endaddr
 | ) |  |

Erases the specified memory area of the given SD card.

Parameters:
hsd,: SD handle
startaddr,: Start byte address
endaddr,: End byte address
Return values:
SD Card error state

Definition at line 1218 of file stm32l4xx_hal_sd.c.

References SD_CARD_LOCKED, SD_CCCC_ERASE, SD_CmdResp1Error(), SD_DATATIMEOUT, and SD_IsCardProgramming().

void HAL_SD_IRQHandler ( SD_HandleTypeDef * hsd )

This function handles SD card interrupt request.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 1322 of file stm32l4xx_hal_sd.c.

References HAL_SD_XferCpltCallback(), and HAL_SD_XferErrorCallback().

HAL_SD_ErrorTypedef HAL_SD_ReadBlocks | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pReadBuffer,
 |  | uint64_t | ReadAddr,
 |  | uint32_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by polling mode.

Parameters:
hsd,: SD handle
pReadBuffer,: pointer to the buffer that will contain the received data
ReadAddr,: Address from where data is to be read
BlockSize,: SD card Data block size
Note:
BlockSize must be 512 bytes.
Parameters:
NumberOfBlocks,: Number of SD blocks to read
Return values:
SD Card error state

Definition at line 470 of file stm32l4xx_hal_sd.c.

References DATA_BLOCK_SIZE, HAL_SD_StopTransfer(), SD_CmdResp1Error(), SD_DATATIMEOUT, and SDMMC_STATIC_FLAGS.

HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pReadBuffer,
 |  | uint64_t | ReadAddr,
 |  | uint32_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Reads block(s) from a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by the function HAL_SD_CheckReadOperation() to check the completion of the read process
Parameters:
hsd,: SD handle
pReadBuffer,: Pointer to the buffer that will contain the received data
ReadAddr,: Address from where data is to be read
BlockSize,: SD card Data block size
Note:
BlockSize must be 512 bytes.
Parameters:
NumberOfBlocks,: Number of blocks to read.
Return values:
SD Card error state

Definition at line 856 of file stm32l4xx_hal_sd.c.

References DMA_MEMORY_TO_PERIPH, DMA_PERIPH_TO_MEMORY, HAL_DMA_Start_IT(), SD_CmdResp1Error(), SD_DATATIMEOUT, SD_DMA_RxCplt(), and SD_DMA_RxError().

HAL_SD_ErrorTypedef HAL_SD_WriteBlocks | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pWriteBuffer,
 |  | uint64_t | WriteAddr,
 |  | uint32_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Allows to write block(s) to a specified address in a card.

The Data transfer is managed by polling mode.

Parameters:
hsd,: SD handle
pWriteBuffer,: pointer to the buffer that will contain the data to transmit
WriteAddr,: Address from where data is to be written
BlockSize,: SD card Data block size
Note:
BlockSize must be 512 bytes.
Parameters:
NumberOfBlocks,: Number of SD blocks to write
Return values:
SD Card error state

Definition at line 646 of file stm32l4xx_hal_sd.c.

References HAL_SD_StopTransfer(), SD_CmdResp1Error(), SD_DATATIMEOUT, SD_IsCardProgramming(), and SDMMC_STATIC_FLAGS.

HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pWriteBuffer,
 |  | uint64_t | WriteAddr,
 |  | uint32_t | BlockSize,
 |  | uint32_t | NumberOfBlocks
 | ) |  |

Writes block(s) to a specified address in a card.

The Data transfer is managed by DMA mode.

Note:
This API should be followed by the function HAL_SD_CheckWriteOperation() to check the completion of the write process (by SD current status polling).
Parameters:
hsd,: SD handle
pWriteBuffer,: pointer to the buffer that will contain the data to transmit
WriteAddr,: Address from where data is to be read
BlockSize,: the SD card Data block size
Note:
BlockSize must be 512 bytes.
Parameters:
NumberOfBlocks,: Number of blocks to write
Return values:
SD Card error state

Definition at line 976 of file stm32l4xx_hal_sd.c.

References DMA_MEMORY_TO_PERIPH, HAL_DMA_Start_IT(), SD_CmdResp1Error(), SD_DATATIMEOUT, SD_DMA_TxCplt(), and SD_DMA_TxError().

__weak void HAL_SD_XferCpltCallback ( SD_HandleTypeDef * hsd )

SD end of transfer callback.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 1387 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

__weak void HAL_SD_XferErrorCallback ( SD_HandleTypeDef * hsd )

SD Transfer Error callback.

Parameters:
hsd,: SD handle
Return values:
None

Definition at line 1402 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_IRQHandler().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SD_Exported_Functions_Group3

Functions
SD_Exported_Functions_Group3
SD_Exported_Functions

management functions More...

Functions

HAL_SD_ErrorTypedef | HAL_SD_Get_CardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
Returns information about specific card.
HAL_SD_ErrorTypedef | HAL_SD_WideBusOperation_Config (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_SD_ErrorTypedef | HAL_SD_StopTransfer (SD_HandleTypeDef *hsd)
Aborts an ongoing data transfer.
HAL_SD_ErrorTypedef | HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to High Speed mode.

Detailed Description

management functions

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control the SD card
    operations.

Function Documentation

HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardInfoTypedef * | pCardInfo
 | ) |  |

Returns information about specific card.

Parameters:
hsd,: SD handle
pCardInfo,: Pointer to a HAL_SD_CardInfoTypedef structure that contains all SD cardinformation
Return values:
SD Card error state

< Reserved

Definition at line 1502 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_Init().

HAL_SD_ErrorTypedef HAL_SD_HighSpeed ( SD_HandleTypeDef * hsd )

Switches the SD card to High Speed mode.

This API must be used after "Transfer State"

Note:
This operation should be followed by the configuration of PLL to have SDMMCCK clock between 67 and 75 MHz
Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 1799 of file stm32l4xx_hal_sd.c.

References SD_ALLZERO, SD_CmdResp1Error(), SD_DATATIMEOUT, SD_FindSCR(), and SDMMC_STATIC_FLAGS.

HAL_SD_ErrorTypedef HAL_SD_StopTransfer ( SD_HandleTypeDef * hsd )

Aborts an ongoing data transfer.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 1772 of file stm32l4xx_hal_sd.c.

References SD_CmdResp1Error().

Referenced by HAL_SD_CheckReadOperation(), HAL_SD_CheckWriteOperation(), HAL_SD_ReadBlocks(), and HAL_SD_WriteBlocks().

HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t | WideMode
 | ) |  |

Enables wide bus operation for the requested card if supported by card.

Parameters:
hsd,: SD handle
WideMode,: Specifies the SD card wide bus mode This parameter can be one of the following values:
  • SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
  • SDMMC_BUS_WIDE_4B: 4-bit data transfer
  • SDMMC_BUS_WIDE_1B: 1-bit data transfer
Return values:
SD Card error state

Definition at line 1718 of file stm32l4xx_hal_sd.c.

References SD_WideBus_Disable(), and SD_WideBus_Enable().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SD_Exported_Functions_Group4

Functions
SD_Exported_Functions_Group4
SD_Exported_Functions

Peripheral State functions. More...

Functions

HAL_SD_ErrorTypedef | HAL_SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
Returns the current SD card's status.
HAL_SD_TransferStateTypedef | HAL_SD_GetStatus (SD_HandleTypeDef *hsd)
Gets the current sd card data status.
HAL_SD_ErrorTypedef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
Gets the SD card status.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in runtime the status of the peripheral
    and the data flow.

Function Documentation

HAL_SD_ErrorTypedef HAL_SD_GetCardStatus | ( | SD_HandleTypeDef * | hsd,
 |  | HAL_SD_CardStatusTypedef * | pCardStatus
 | ) |  |

Gets the SD card status.

Parameters:
hsd,: SD handle
pCardStatus,: Pointer to the HAL_SD_CardStatusTypedef structure that will contain the SD card status information
Return values:
SD Card error state

Definition at line 2111 of file stm32l4xx_hal_sd.c.

References HAL_SD_SendSDStatus().

HAL_SD_TransferStateTypedef HAL_SD_GetStatus ( SD_HandleTypeDef * hsd )

Gets the current sd card data status.

Parameters:
hsd,: SD handle
Return values:
Data Transfer state

Definition at line 2082 of file stm32l4xx_hal_sd.c.

References SD_GetState().

Referenced by HAL_SD_CheckWriteOperation().

HAL_SD_ErrorTypedef HAL_SD_SendSDStatus | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pSDstatus
 | ) |  |

Returns the current SD card's status.

Parameters:
hsd,: SD handle
pSDstatus,: Pointer to the buffer that will contain the SD card status SD Status register)
Return values:
SD Card error state

Definition at line 1954 of file stm32l4xx_hal_sd.c.

References SD_CARD_LOCKED, SD_CmdResp1Error(), SD_DATATIMEOUT, and SDMMC_STATIC_FLAGS.

Referenced by HAL_SD_GetCardStatus().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: SD_Private_Functions

Functions
SD_Private_Functions
SD

Functions

static void | SD_DMA_RxCplt (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Rx callback.
static void | SD_DMA_RxError (DMA_HandleTypeDef *hdma)
SD DMA transfer Error Rx callback.
static void | SD_DMA_TxCplt (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Tx callback.
static void | SD_DMA_TxError (DMA_HandleTypeDef *hdma)
SD DMA transfer Error Tx callback.
static HAL_SD_CardStateTypedef | SD_GetState (SD_HandleTypeDef *hsd)
Returns the SD current state.
static HAL_SD_ErrorTypedef | SD_Initialize_Cards (SD_HandleTypeDef *hsd)
Initializes all cards or single card as the case may be Card(s) come into standby state.
static HAL_SD_ErrorTypedef | SD_Select_Deselect (SD_HandleTypeDef *hsd, uint64_t addr)
Selects or Deselects the corresponding card.
static HAL_SD_ErrorTypedef | SD_PowerON (SD_HandleTypeDef *hsd)
Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.
static HAL_SD_ErrorTypedef | SD_PowerOFF (SD_HandleTypeDef *hsd)
Turns the SDMMC output signals off.
static HAL_SD_ErrorTypedef | SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
Returns the current card's status.
static HAL_SD_ErrorTypedef | SD_CmdError (SD_HandleTypeDef *hsd)
Checks for error conditions for CMD0.
static HAL_SD_ErrorTypedef | SD_CmdResp7Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R7 response.
static HAL_SD_ErrorTypedef | SD_CmdResp1Error (SD_HandleTypeDef *hsd, uint8_t SD_CMD)
Checks for error conditions for R1 response.
static HAL_SD_ErrorTypedef | SD_CmdResp3Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R3 (OCR) response.
static HAL_SD_ErrorTypedef | SD_CmdResp2Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R2 (CID or CSD) response.
static HAL_SD_ErrorTypedef | SD_CmdResp6Error (SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
Checks for error conditions for R6 (RCA) response.
static HAL_SD_ErrorTypedef | SD_WideBus_Enable (SD_HandleTypeDef *hsd)
Enables the SDMMC wide bus mode.
static HAL_SD_ErrorTypedef | SD_WideBus_Disable (SD_HandleTypeDef *hsd)
Disables the SDMMC wide bus mode.
static HAL_SD_ErrorTypedef | SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR)
Finds the SD card SCR register value.
static HAL_SD_ErrorTypedef | SD_IsCardProgramming (SD_HandleTypeDef *hsd, uint8_t *pStatus)
Checks if the SD card is in programming state.

Function Documentation

static HAL_SD_ErrorTypedef SD_CmdError ( SD_HandleTypeDef * hsd ) [static]

Checks for error conditions for CMD0.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2618 of file stm32l4xx_hal_sd.c.

References SDMMC_CMD0TIMEOUT, and SDMMC_STATIC_FLAGS.

Referenced by SD_PowerON().

static HAL_SD_ErrorTypedef SD_CmdResp1Error | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t | SD_CMD
 | ) |  | [static]

Checks for error conditions for R1 response.

Parameters:
hsd,: SD handle
SD_CMD,: The sent command index
Return values:
SD Card error state

Definition at line 2694 of file stm32l4xx_hal_sd.c.

References SD_ALLZERO, SD_OCR_ADDR_MISALIGNED, SD_OCR_ADDR_OUT_OF_RANGE, SD_OCR_AKE_SEQ_ERROR, SD_OCR_BAD_ERASE_PARAM, SD_OCR_BLOCK_LEN_ERR, SD_OCR_CARD_ECC_DISABLED, SD_OCR_CARD_ECC_FAILED, SD_OCR_CC_ERROR, SD_OCR_CID_CSD_OVERWRITE, SD_OCR_COM_CRC_FAILED, SD_OCR_ERASE_RESET, SD_OCR_ERASE_SEQ_ERR, SD_OCR_ERRORBITS, SD_OCR_GENERAL_UNKNOWN_ERROR, SD_OCR_ILLEGAL_CMD, SD_OCR_LOCK_UNLOCK_FAILED, SD_OCR_STREAM_READ_UNDERRUN, SD_OCR_STREAM_WRITE_OVERRUN, SD_OCR_WP_ERASE_SKIP, SD_OCR_WRITE_PROT_VIOLATION, and SDMMC_STATIC_FLAGS.

Referenced by HAL_SD_Erase(), HAL_SD_HighSpeed(), HAL_SD_ReadBlocks(), HAL_SD_ReadBlocks_DMA(), HAL_SD_SendSDStatus(), HAL_SD_StopTransfer(), HAL_SD_WriteBlocks(), HAL_SD_WriteBlocks_DMA(), SD_FindSCR(), SD_PowerON(), SD_Select_Deselect(), SD_SendStatus(), SD_WideBus_Disable(), and SD_WideBus_Enable().

static HAL_SD_ErrorTypedef SD_CmdResp2Error ( SD_HandleTypeDef * hsd ) [static]

Checks for error conditions for R2 (CID or CSD) response.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2870 of file stm32l4xx_hal_sd.c.

References SDMMC_STATIC_FLAGS.

Referenced by SD_Initialize_Cards().

static HAL_SD_ErrorTypedef SD_CmdResp3Error ( SD_HandleTypeDef * hsd ) [static]

Checks for error conditions for R3 (OCR) response.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2842 of file stm32l4xx_hal_sd.c.

References SDMMC_STATIC_FLAGS.

Referenced by SD_PowerON().

static HAL_SD_ErrorTypedef SD_CmdResp6Error | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t | SD_CMD,
 |  | uint16_t * | pRCA
 | ) |  | [static]

Checks for error conditions for R6 (RCA) response.

Parameters:
hsd,: SD handle
SD_CMD,: The sent command index
pRCA,: Pointer to the variable that will contain the SD card relative address RCA
Return values:
SD Card error state

Definition at line 2913 of file stm32l4xx_hal_sd.c.

References SD_ALLZERO, SD_R6_COM_CRC_FAILED, SD_R6_GENERAL_UNKNOWN_ERROR, SD_R6_ILLEGAL_CMD, and SDMMC_STATIC_FLAGS.

Referenced by SD_Initialize_Cards().

static HAL_SD_ErrorTypedef SD_CmdResp7Error ( SD_HandleTypeDef * hsd ) [static]

Checks for error conditions for R7 response.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2650 of file stm32l4xx_hal_sd.c.

References SDMMC_CMD0TIMEOUT.

Referenced by SD_PowerON().

static void SD_DMA_RxCplt ( DMA_HandleTypeDef * hdma ) [static]

SD DMA transfer complete Rx callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2206 of file stm32l4xx_hal_sd.c.

References HAL_DMA_Abort(), and HAL_SD_DMA_RxCpltCallback().

Referenced by HAL_SD_ReadBlocks_DMA().

static void SD_DMA_RxError ( DMA_HandleTypeDef * hdma ) [static]

SD DMA transfer Error Rx callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2231 of file stm32l4xx_hal_sd.c.

References HAL_SD_DMA_RxErrorCallback().

Referenced by HAL_SD_ReadBlocks_DMA().

static void SD_DMA_TxCplt ( DMA_HandleTypeDef * hdma ) [static]

SD DMA transfer complete Tx callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2245 of file stm32l4xx_hal_sd.c.

References HAL_DMA_Abort(), and HAL_SD_DMA_TxCpltCallback().

Referenced by HAL_SD_WriteBlocks_DMA().

static void SD_DMA_TxError ( DMA_HandleTypeDef * hdma ) [static]

SD DMA transfer Error Tx callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2270 of file stm32l4xx_hal_sd.c.

References HAL_SD_DMA_TxErrorCallback().

Referenced by HAL_SD_WriteBlocks_DMA().

static HAL_SD_ErrorTypedef SD_FindSCR | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pSCR
 | ) |  | [static]

Finds the SD card SCR register value.

Parameters:
hsd,: SD handle
pSCR,: pointer to the buffer that will contain the SCR value
Return values:
SD Card error state

Definition at line 3127 of file stm32l4xx_hal_sd.c.

References SD_0TO7BITS, SD_16TO23BITS, SD_24TO31BITS, SD_8TO15BITS, SD_CmdResp1Error(), SD_DATATIMEOUT, and SDMMC_STATIC_FLAGS.

Referenced by HAL_SD_HighSpeed(), SD_WideBus_Disable(), and SD_WideBus_Enable().

static HAL_SD_CardStateTypedef SD_GetState ( SD_HandleTypeDef * hsd ) [static]

Returns the SD current state.

Parameters:
hsd,: SD handle
Return values:
SD card current state

Definition at line 2283 of file stm32l4xx_hal_sd.c.

References SD_SendStatus().

Referenced by HAL_SD_GetStatus().

static HAL_SD_ErrorTypedef SD_Initialize_Cards ( SD_HandleTypeDef * hsd ) [static]

Initializes all cards or single card as the case may be Card(s) come into standby state.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2303 of file stm32l4xx_hal_sd.c.

References SD_CmdResp2Error(), and SD_CmdResp6Error().

Referenced by HAL_SD_Init().

static HAL_SD_ErrorTypedef SD_IsCardProgramming | ( | SD_HandleTypeDef * | hsd,
 |  | uint8_t * | pStatus
 | ) |  | [static]

Checks if the SD card is in programming state.

Parameters:
hsd,: SD handle
pStatus,: pointer to the variable that will contain the SD card state
Return values:
SD Card error state

Definition at line 3241 of file stm32l4xx_hal_sd.c.

References SD_ALLZERO, SD_OCR_ADDR_MISALIGNED, SD_OCR_ADDR_OUT_OF_RANGE, SD_OCR_AKE_SEQ_ERROR, SD_OCR_BAD_ERASE_PARAM, SD_OCR_BLOCK_LEN_ERR, SD_OCR_CARD_ECC_DISABLED, SD_OCR_CARD_ECC_FAILED, SD_OCR_CC_ERROR, SD_OCR_CID_CSD_OVERWRITE, SD_OCR_COM_CRC_FAILED, SD_OCR_ERASE_RESET, SD_OCR_ERASE_SEQ_ERR, SD_OCR_ERRORBITS, SD_OCR_GENERAL_UNKNOWN_ERROR, SD_OCR_ILLEGAL_CMD, SD_OCR_LOCK_UNLOCK_FAILED, SD_OCR_STREAM_READ_UNDERRUN, SD_OCR_STREAM_WRITE_OVERRUN, SD_OCR_WP_ERASE_SKIP, SD_OCR_WRITE_PROT_VIOLATION, and SDMMC_STATIC_FLAGS.

Referenced by HAL_SD_Erase(), and HAL_SD_WriteBlocks().

static HAL_SD_ErrorTypedef SD_PowerOFF ( SD_HandleTypeDef * hsd ) [static]

Turns the SDMMC output signals off.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2562 of file stm32l4xx_hal_sd.c.

Referenced by HAL_SD_DeInit().

static HAL_SD_ErrorTypedef SD_PowerON ( SD_HandleTypeDef * hsd ) [static]

Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2421 of file stm32l4xx_hal_sd.c.

References HAL_Delay(), SD_CHECK_PATTERN, SD_CmdError(), SD_CmdResp1Error(), SD_CmdResp3Error(), SD_CmdResp7Error(), SD_HIGH_CAPACITY, SD_MAX_VOLT_TRIAL, SD_SDMMC_SEND_IF_COND, SD_STD_CAPACITY, and SD_VOLTAGE_WINDOW_SD.

Referenced by HAL_SD_Init().

static HAL_SD_ErrorTypedef SD_Select_Deselect | ( | SD_HandleTypeDef * | hsd,
 |  | uint64_t | addr
 | ) |  | [static]

Selects or Deselects the corresponding card.

Parameters:
hsd,: SD handle
addr,: Address of the card to be selected
Return values:
SD Card error state

Definition at line 2395 of file stm32l4xx_hal_sd.c.

References SD_CmdResp1Error().

Referenced by HAL_SD_Init().

static HAL_SD_ErrorTypedef SD_SendStatus | ( | SD_HandleTypeDef * | hsd,
 |  | uint32_t * | pCardStatus
 | ) |  | [static]

Returns the current card's status.

Parameters:
hsd,: SD handle
pCardStatus,: pointer to the buffer that will contain the SD card status (Card Status register)
Return values:
SD Card error state

Definition at line 2579 of file stm32l4xx_hal_sd.c.

References SD_CmdResp1Error().

Referenced by SD_GetState().

static HAL_SD_ErrorTypedef SD_WideBus_Disable ( SD_HandleTypeDef * hsd ) [static]

Disables the SDMMC wide bus mode.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 3056 of file stm32l4xx_hal_sd.c.

References SD_ALLZERO, SD_CARD_LOCKED, SD_CmdResp1Error(), SD_FindSCR(), and SD_SINGLE_BUS_SUPPORT.

Referenced by HAL_SD_WideBusOperation_Config().

static HAL_SD_ErrorTypedef SD_WideBus_Enable ( SD_HandleTypeDef * hsd ) [static]

Enables the SDMMC wide bus mode.

Parameters:
hsd,: SD handle
Return values:
SD Card error state

Definition at line 2987 of file stm32l4xx_hal_sd.c.

References SD_ALLZERO, SD_CARD_LOCKED, SD_CmdResp1Error(), SD_FindSCR(), and SD_WIDE_BUS_SUPPORT.

Referenced by HAL_SD_WideBusOperation_Config().

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USARTEx Word Length

Defines
USARTEx Word Length
USARTEx Exported Constants

Defines

#define | USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | USART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)

7-bit long USART frame

Definition at line 66 of file stm32l4xx_hal_usart_ex.h.

#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)

8-bit long USART frame

Definition at line 67 of file stm32l4xx_hal_usart_ex.h.

#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

9-bit long USART frame

Definition at line 68 of file stm32l4xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USARTEx Private Macros

Defines
USARTEx Private Macros
USARTEx

Defines

#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.

Define Documentation

#define IS_USART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == USART_WORDLENGTH_7B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_9B))

Ensure that USART frame length is valid.

Parameters:
__LENGTH__,: USART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 256 of file stm32l4xx_hal_usart_ex.h.

Referenced by USART_SetConfig().

#define USART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the USART clock source.

Parameters:
__HANDLE__,: specifies the USART Handle.
__CLOCKSOURCE__,: output variable.
Return values:
the USART clocking source, written in __CLOCKSOURCE__.

Definition at line 136 of file stm32l4xx_hal_usart_ex.h.

Referenced by USART_SetConfig().

#define USART_MASK_COMPUTATION ( __HANDLE__ )

Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__,: specifies the USART Handle.
Return values:
None,the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 213 of file stm32l4xx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • ABOM : CAN_InitTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • AcquisitionMode : TSC_InitTypeDef
  • Activation : DFSDM_Channel_OutputClockTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • Address : FLASH_ProcessTypeDef , QSPI_CommandTypeDef , UART_WakeUpTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddressMode : QSPI_CommandTypeDef
  • AddressSize : QSPI_CommandTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • Alternate : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • AlternateByteMode : QSPI_CommandTypeDef
  • AlternateBytes : QSPI_CommandTypeDef
  • AlternateBytesSize : QSPI_CommandTypeDef
  • AnalogFilter : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef
  • AutomaticStop : QSPI_AutoPollingTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
  • Awd : DFSDM_Channel_InitTypeDef
  • AWUM : CAN_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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  • x
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • Bank : FLASH_ProcessTypeDef
  • BankNumber : CAN_FilterConfTypeDef
  • Banks : FLASH_EraseInitTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • battery_charging_active : PCD_HandleTypeDef
  • BaudRate : UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , IRDA_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BESL : PCD_HandleTypeDef
  • Bias : LCD_InitTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BitRate : SWPMI_InitTypeDef
  • BitRatePrescaler : LL_SWPMI_InitTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlinkFrequency : LCD_InitTypeDef
  • BlinkMode : LCD_InitTypeDef
  • Block : NAND_AddressTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BlockNbr : NAND_InfoTypeDef
  • BlockSize : NAND_InfoTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef
  • Break2Polarity : TIM_BreakDeadTimeConfigTypeDef
  • Break2State : TIM_BreakDeadTimeConfigTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef
  • BreakPolarity : TIM_BreakDeadTimeConfigTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef
  • BS1 : CAN_InitTypeDef
  • BS2 : CAN_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • CFI_1 : NOR_CFITypeDef
  • CFI_2 : NOR_CFITypeDef
  • CFI_3 : NOR_CFITypeDef
  • CFI_4 : NOR_CFITypeDef
  • ChainingMode : CRYP_InitTypeDef
  • Channel : DFSDM_Filter_AwdParamTypeDef , TIM_HandleTypeDef , ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef
  • ChannelCount : ADC_InjectionConfigTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ChannelIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • ChipSelectHighTime : QSPI_InitTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockMode : QSPI_InitTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : ADC_InitTypeDef , QSPI_InitTypeDef , TIM_ClockConfigTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , LL_LPTIM_InitTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CodeSegmentLength : FIREWALL_InitTypeDef
  • CodeSegmentStartAddress : FIREWALL_InitTypeDef
  • CommonClock : LL_ADC_CommonInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CompandingMode : SAI_InitTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • ContextQueue : ADC_InjectionConfigTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • Contrast : LCD_InitTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCLength : SPI_InitTypeDef , CRC_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CrypInCount : CRYP_HandleTypeDef
  • CrypOutCount : CRYP_HandleTypeDef
  • CTPulseHighLength : TSC_InitTypeDef
  • CTPulseLowLength : TSC_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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  • x
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • DAC_ConnectOnChipPeripheral : DAC_ChannelConfTypeDef
  • DAC_HoldTime : DAC_SampleAndHoldConfTypeDef
  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_RefreshTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SampleAndHold : DAC_ChannelConfTypeDef
  • DAC_SampleAndHoldConfig : DAC_ChannelConfTypeDef
  • DAC_SampleTime : DAC_SampleAndHoldConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAC_TrimmingValue : DAC_ChannelConfTypeDef
  • DAC_UserTrimming : DAC_ChannelConfTypeDef
  • Data : CanTxMsgTypeDef , CanRxMsgTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DataInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DataMode : QSPI_CommandTypeDef
  • DataPacking : DFSDM_Channel_InputTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • DataSource : DFSDM_Filter_AwdParamTypeDef
  • DataType : CRYP_InitTypeDef
  • DataWidth : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DdrHoldHalfCycle : QSPI_CommandTypeDef
  • DdrMode : QSPI_CommandTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef , LCD_InitTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • Device_Code1 : NOR_IDTypeDef
  • Device_Code2 : NOR_IDTypeDef
  • Device_Code3 : NOR_IDTypeDef
  • Device_Id : NAND_IDTypeDef
  • Dfsdm1ClockSelection : RCC_PeriphCLKInitTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : LL_DMA_InitTypeDef , DMA_InitTypeDef , SPI_InitTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • Divider : LCD_InitTypeDef , DFSDM_Channel_OutputClockTypeDef
  • DLC : CanTxMsgTypeDef , CanRxMsgTypeDef
  • DMA_Handle : ADC_HandleTypeDef
  • DMA_Handle1 : DAC_HandleTypeDef
  • DMA_Handle2 : DAC_HandleTypeDef
  • DMAAccessMode : ADC_MultiModeTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DmaMode : DFSDM_Filter_RegularParamTypeDef , DFSDM_Filter_InjectedParamTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • DualAddressMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • DummyCycles : QSPI_CommandTypeDef
  • Duty : LCD_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • a
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  • x
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • Enable : MPU_Region_InitTypeDef , TIMEx_BreakInputConfigTypeDef
  • EncoderMode : LL_TIM_ENCODER_InitTypeDef , TIM_Encoder_InitTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ErrorCode : CRYP_HandleTypeDef , QSPI_HandleTypeDef , __SAI_HandleTypeDef , DAC_HandleTypeDef , SMARTCARD_HandleTypeDef , SMBUS_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , SWPMI_HandleTypeDef , __DMA_HandleTypeDef , UART_HandleTypeDef , ADC_HandleTypeDef , FLASH_ProcessTypeDef , __I2C_HandleTypeDef , CAN_HandleTypeDef , IRDA_HandleTypeDef , LCD_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • Extended : SRAM_HandleTypeDef , NOR_HandleTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
  • ExtId : CanTxMsgTypeDef , CanRxMsgTypeDef
  • ExtTrigger : DFSDM_Filter_InjectedParamTypeDef
  • ExtTriggerEdge : DFSDM_Filter_InjectedParamTypeDef , DFSDM_Filter_HandleTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • t
  • u
  • v
  • w
  • x
  • y
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • FastMode : DFSDM_Filter_RegularParamTypeDef
  • FIFONumber : CanRxMsgTypeDef
  • FIFOThreshold : SAI_InitTypeDef
  • FifoThreshold : QSPI_InitTypeDef
  • Filter : RTC_TamperTypeDef
  • FilterActivation : CAN_FilterConfTypeDef
  • FilterFIFOAssignment : CAN_FilterConfTypeDef
  • FilterIdHigh : CAN_FilterConfTypeDef
  • FilterIdLow : CAN_FilterConfTypeDef
  • FilterMaskIdHigh : CAN_FilterConfTypeDef
  • FilterMaskIdLow : CAN_FilterConfTypeDef
  • FilterMode : CAN_FilterConfTypeDef
  • FilterNumber : CAN_FilterConfTypeDef
  • FilterOrder : DFSDM_Channel_AwdTypeDef
  • FilterParam : DFSDM_Filter_InitTypeDef
  • FilterScale : CAN_FilterConfTypeDef
  • FirstBit : SAI_InitTypeDef , SPI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FlashSize : QSPI_InitTypeDef
  • FMI : CanRxMsgTypeDef
  • Fourth_Id : NAND_IDTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
  • FunctionalMode : LL_OPAMP_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GCMCMACPhase : CRYP_InitTypeDef
  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • gState : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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  • x
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • HardwareFlowControl : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • hc : HCD_HandleTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : QSPI_HandleTypeDef , SRAM_HandleTypeDef , TIM_HandleTypeDef
  • hdmain : CRYP_HandleTypeDef
  • hdmaInj : DFSDM_Filter_HandleTypeDef
  • hdmaout : CRYP_HandleTypeDef
  • hdmaReg : DFSDM_Filter_HandleTypeDef
  • hdmarx : __SPI_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , __I2C_HandleTypeDef , IRDA_HandleTypeDef , __SAI_HandleTypeDef , SMARTCARD_HandleTypeDef
  • hdmatx : __I2C_HandleTypeDef , IRDA_HandleTypeDef , __SAI_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef
  • Header : CRYP_InitTypeDef
  • HeaderSize : CRYP_InitTypeDef
  • HighBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • HighDrive : LCD_InitTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef , DFSDM_Filter_AwdParamTypeDef
  • HourFormat : LL_RTC_InitTypeDef , RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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  • u
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  • x
  • y
  • z
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c3ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPolarity : LL_TIM_IC_InitTypeDef , TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IDE : CanTxMsgTypeDef , CanRxMsgTypeDef
  • IN_ep : PCD_HandleTypeDef
  • Info : NAND_HandleTypeDef
  • Init : __SPI_HandleTypeDef , SRAM_HandleTypeDef , SWPMI_HandleTypeDef , TIM_HandleTypeDef , TSC_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , ADC_HandleTypeDef , CAN_HandleTypeDef , COMP_HandleTypeDef , CRC_HandleTypeDef , CRYP_HandleTypeDef , DFSDM_Channel_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __DMA_HandleTypeDef , HCD_HandleTypeDef , __I2C_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , LCD_HandleTypeDef , LPTIM_HandleTypeDef , NAND_HandleTypeDef , NOR_HandleTypeDef , OPAMP_HandleTypeDef , PCD_HandleTypeDef , QSPI_HandleTypeDef , RTC_HandleTypeDef , __SAI_HandleTypeDef , SMARTCARD_HandleTypeDef , SMBUS_HandleTypeDef
  • InitValue : CRC_InitTypeDef
  • InjConvRemaining : DFSDM_Filter_HandleTypeDef
  • InjecOversampling : ADC_InjectionConfTypeDef
  • InjecOversamplingMode : ADC_InjectionConfTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedChannelsNbr : DFSDM_Filter_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedOffsetNumber : ADC_InjectionConfTypeDef
  • InjectedParam : DFSDM_Filter_InitTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedScanMode : DFSDM_Filter_HandleTypeDef
  • InjectedSingleDiff : ADC_InjectionConfTypeDef
  • InjectedTrigger : DFSDM_Filter_HandleTypeDef
  • InjectionConfig : ADC_HandleTypeDef
  • Input : DFSDM_Channel_InitTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputInverting : LL_OPAMP_InitTypeDef
  • InputMinus : LL_COMP_InitTypeDef
  • InputNonInverting : LL_OPAMP_InitTypeDef
  • InputPlus : LL_COMP_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : __SAI_HandleTypeDef , SMBUS_HandleTypeDef , CAN_HandleTypeDef , DFSDM_Channel_HandleTypeDef , TSC_HandleTypeDef , TIM_HandleTypeDef , OPAMP_HandleTypeDef , DFSDM_Filter_HandleTypeDef , COMP_HandleTypeDef , DAC_HandleTypeDef , CRC_HandleTypeDef , __I2C_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef , HCD_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef , NOR_HandleTypeDef , USART_HandleTypeDef , __DMA_HandleTypeDef , CRYP_HandleTypeDef , WWDG_HandleTypeDef , PCD_HandleTypeDef , RTC_HandleTypeDef , LPTIM_HandleTypeDef , NAND_HandleTypeDef , RNG_HandleTypeDef , SRAM_HandleTypeDef , ADC_HandleTypeDef , IWDG_HandleTypeDef , LCD_HandleTypeDef , IRDA_HandleTypeDef
  • Instruction : QSPI_CommandTypeDef
  • InstructionMode : QSPI_CommandTypeDef
  • Interrupt : RTC_TamperTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • Interval : QSPI_AutoPollingTypeDef
  • IntOversampling : DFSDM_Filter_FilterParamTypeDef
  • InvertingInput : COMP_InitTypeDef , OPAMP_InitTypeDef
  • IODefaultMode : TSC_InitTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- k -

  • KeySize : CRYP_InitTypeDef
  • KeyWriteFlag : CRYP_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • Line_32_63 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • Lock : CRC_HandleTypeDef , LCD_HandleTypeDef , TSC_HandleTypeDef , UART_HandleTypeDef , LPTIM_HandleTypeDef , USART_HandleTypeDef , CRYP_HandleTypeDef , NAND_HandleTypeDef , NOR_HandleTypeDef , ADC_HandleTypeDef , DAC_HandleTypeDef , OPAMP_HandleTypeDef , PCD_HandleTypeDef , TIM_HandleTypeDef , SWPMI_HandleTypeDef , SRAM_HandleTypeDef , __SPI_HandleTypeDef , SMBUS_HandleTypeDef , SMARTCARD_HandleTypeDef , __SAI_HandleTypeDef , __DMA_HandleTypeDef , QSPI_HandleTypeDef , RNG_HandleTypeDef , CAN_HandleTypeDef , FLASH_ProcessTypeDef , RTC_HandleTypeDef , HCD_HandleTypeDef , COMP_HandleTypeDef , __I2C_HandleTypeDef , IRDA_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef
  • LowBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowPowerMode : LL_ADC_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef , DFSDM_Filter_AwdParamTypeDef
  • lpm_active : PCD_HandleTypeDef
  • LPM_State : PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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  • x
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • Maker_Id : NAND_IDTypeDef
  • Manufacturer_Code : NOR_IDTypeDef
  • Mask : QSPI_AutoPollingTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef , USART_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • Match : QSPI_AutoPollingTypeDef
  • MatchMode : QSPI_AutoPollingTypeDef
  • MaxCountInterrupt : TSC_InitTypeDef
  • MaxCountValue : TSC_InitTypeDef
  • Mckdiv : SAI_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • Minutes : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Mode : PWR_PVMTypeDef , SMARTCARD_InitTypeDef , PWR_PVDTypeDef , SPI_InitTypeDef , LL_GPIO_InitTypeDef , USART_InitTypeDef , GPIO_InitTypeDef , LL_EXTI_InitTypeDef , UART_InitTypeDef , LL_DMA_InitTypeDef , LL_SPI_InitTypeDef , ADC_MultiModeTypeDef , CAN_InitTypeDef , COMP_InitTypeDef , DMA_InitTypeDef , __I2C_HandleTypeDef , IRDA_InitTypeDef , OPAMP_InitTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : LL_RTC_DateTypeDef , RTC_DateTypeDef
  • MSBFirst : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • MSICalibrationValue : RCC_OscInitTypeDef
  • MSIClockRange : RCC_OscInitTypeDef
  • MSIState : RCC_OscInitTypeDef
  • MultiDMATransfer : LL_ADC_CommonInitTypeDef
  • Multimode : LL_ADC_CommonInitTypeDef
  • Multiplexer : DFSDM_Channel_InputTypeDef
  • MultiTwoSamplingDelay : LL_ADC_CommonInitTypeDef
  • mutecallback : __SAI_HandleTypeDef
  • MuxSegment : LCD_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NART : CAN_InitTypeDef
  • NbData : LL_DMA_InitTypeDef , QSPI_CommandTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbPagesToErase : FLASH_ProcessTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef
  • NonInvertingInput : COMP_InitTypeDef , OPAMP_InitTypeDef
  • NonVDataSegmentLength : FIREWALL_InitTypeDef
  • NonVDataSegmentStartAddress : FIREWALL_InitTypeDef
  • NoStretchMode : SMBUS_InitTypeDef , I2C_InitTypeDef
  • NSS : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • Offset : ADC_ChannelConfTypeDef , DFSDM_Channel_InitTypeDef
  • OffsetNumber : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OperatingMode : CRYP_InitTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OUT_ep : PCD_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputBlankingSource : LL_COMP_InitTypeDef
  • OutputBuffer : LL_DAC_InitTypeDef
  • OutputClock : DFSDM_Channel_InitTypeDef
  • OutputConnection : LL_DAC_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputMode : LL_DAC_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef , LL_COMP_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • Overrun : ADC_InitTypeDef , LL_ADC_REG_InitTypeDef
  • OverrunDisable : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • OverSampling : LL_USART_InitTypeDef
  • Oversampling : ADC_InitTypeDef , DFSDM_Filter_FilterParamTypeDef
  • OverSampling : UART_InitTypeDef
  • Oversampling : DFSDM_Channel_AwdTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OversamplingStopReset : ADC_OversamplingTypeDef
  • OwnAddress1 : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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  • x
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • Page : FLASH_EraseInitTypeDef , NAND_AddressTypeDef , FLASH_ProcessTypeDef
  • PageSize : NAND_InfoTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_USART_InitTypeDef , IRDA_InitTypeDef
  • pBuffPtr : __I2C_HandleTypeDef , __SAI_HandleTypeDef , SMBUS_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • PCROPEndAddr : FLASH_OBProgramInitTypeDef
  • PCROPStartAddr : FLASH_OBProgramInitTypeDef
  • pCrypInBuffPtr : CRYP_HandleTypeDef
  • pCrypOutBuffPtr : CRYP_HandleTypeDef
  • pData : HCD_HandleTypeDef , PCD_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • PeriphRequest : LL_DMA_InitTypeDef
  • PgaGain : OPAMP_InitTypeDef
  • Phase : CRYP_HandleTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • pInitVect : CRYP_InitTypeDef
  • Pins : DFSDM_Channel_InputTypeDef
  • pKey : CRYP_InitTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLM : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLSAI1 : RCC_PeriphCLKInitTypeDef
  • PLLSAI1ClockOut : RCC_PLLSAI1InitTypeDef
  • PLLSAI1M : RCC_PLLSAI1InitTypeDef
  • PLLSAI1N : RCC_PLLSAI1InitTypeDef
  • PLLSAI1P : RCC_PLLSAI1InitTypeDef
  • PLLSAI1Q : RCC_PLLSAI1InitTypeDef
  • PLLSAI1R : RCC_PLLSAI1InitTypeDef
  • PLLSAI1Source : RCC_PLLSAI1InitTypeDef
  • PLLSAI2 : RCC_PeriphCLKInitTypeDef
  • PLLSAI2ClockOut : RCC_PLLSAI2InitTypeDef
  • PLLSAI2M : RCC_PLLSAI2InitTypeDef
  • PLLSAI2N : RCC_PLLSAI2InitTypeDef
  • PLLSAI2P : RCC_PLLSAI2InitTypeDef
  • PLLSAI2R : RCC_PLLSAI2InitTypeDef
  • PLLSAI2Source : RCC_PLLSAI2InitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • Polarity : LPTIM_ULPClockConfigTypeDef , TIMEx_BreakInputConfigTypeDef , LL_LPTIM_InitTypeDef
  • PowerMode : IRDA_InitTypeDef , OPAMP_InitTypeDef , LL_COMP_InitTypeDef , LL_OPAMP_InitTypeDef
  • PowerSupplyRange : OPAMP_InitTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prescaler : WWDG_InitTypeDef , IWDG_InitTypeDef , LL_LPTIM_InitTypeDef , CAN_InitTypeDef , TIM_Base_InitTypeDef , LCD_InitTypeDef , LPTIM_ClockConfigTypeDef , SMARTCARD_InitTypeDef , IRDA_InitTypeDef , LL_TIM_InitTypeDef
  • PreviousState : SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • Priority : LL_DMA_InitTypeDef , DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • Protocol : SAI_InitTypeDef
  • pRxBuffPtr : SMARTCARD_HandleTypeDef , USART_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef , SWPMI_HandleTypeDef
  • pRxMsg : CAN_HandleTypeDef
  • pTxBuffPtr : __SPI_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , QSPI_HandleTypeDef , IRDA_HandleTypeDef , SWPMI_HandleTypeDef , USART_HandleTypeDef
  • pTxMsg : CAN_HandleTypeDef
  • Pull : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Pulse : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • PulseGeneratorPrescaler : TSC_InitTypeDef
  • PulseOnDuration : LCD_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
  • PVMType : PWR_PVMTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- q -

  • QueueInjectedContext : ADC_InjectionConfTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RandomNumber : RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_InjOversamplingTypeDef , ADC_OversamplingTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • RegularContMode : DFSDM_Filter_HandleTypeDef
  • RegularParam : DFSDM_Filter_InitTypeDef
  • RegularTrigger : DFSDM_Filter_HandleTypeDef
  • Reload : IWDG_InitTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • Request : DMA_InitTypeDef
  • Resolution : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • RFLM : CAN_InitTypeDef
  • RightBitShift : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef , DFSDM_Channel_InitTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RTR : CanTxMsgTypeDef , CanRxMsgTypeDef
  • RxBufferingMode : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • RxISR : __SPI_HandleTypeDef
  • RxPinLevelInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • RxState : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • RxXferCount : SWPMI_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef
  • RxXferSize : USART_HandleTypeDef , SWPMI_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , IRDA_HandleTypeDef , UART_HandleTypeDef , QSPI_HandleTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai2ClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleShifting : QSPI_InitTypeDef
  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingIOs : TSC_IOConfigTypeDef , TSC_InitTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • ScanMode : DFSDM_Filter_InjectedParamTypeDef
  • Sdmmc1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Selection : DFSDM_Channel_OutputClockTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SerialInterface : DFSDM_Channel_InitTypeDef
  • Setup : PCD_HandleTypeDef
  • ShieldIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • SincOrder : DFSDM_Filter_FilterParamTypeDef
  • SingleDiff : ADC_ChannelConfTypeDef
  • SIOOMode : QSPI_CommandTypeDef
  • Size : MPU_Region_InitTypeDef
  • SJW : CAN_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , TIMEx_BreakInputConfigTypeDef
  • SpareAreaSize : NAND_InfoTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • SpiClock : DFSDM_Channel_SerialInterfaceTypeDef
  • SpreadSpectrum : TSC_InitTypeDef
  • SpreadSpectrumDeviation : TSC_InitTypeDef
  • SpreadSpectrumPrescaler : TSC_InitTypeDef
  • State : RNG_HandleTypeDef , RTC_HandleTypeDef , DAC_HandleTypeDef , __SAI_HandleTypeDef , SMBUS_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , PCD_HandleTypeDef , TSC_HandleTypeDef , QSPI_HandleTypeDef , HCD_HandleTypeDef , NAND_HandleTypeDef , ADC_HandleTypeDef , CAN_HandleTypeDef , USART_HandleTypeDef , COMP_HandleTypeDef , CRC_HandleTypeDef , CRYP_HandleTypeDef , DFSDM_Channel_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __DMA_HandleTypeDef , SRAM_HandleTypeDef , TIM_HandleTypeDef , OPAMP_HandleTypeDef , __I2C_HandleTypeDef , LCD_HandleTypeDef , LPTIM_HandleTypeDef , NOR_HandleTypeDef
  • Status : OPAMP_HandleTypeDef , LPTIM_HandleTypeDef
  • StatusBytesSize : QSPI_AutoPollingTypeDef
  • StdId : CanTxMsgTypeDef , CanRxMsgTypeDef
  • StopBits : USART_InitTypeDef , LL_USART_InitTypeDef , LL_LPUART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SuspendRequest : CRYP_HandleTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • Swpmi1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SynchroPinPolarity : TSC_InitTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • Tamper : RTC_TamperTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • Third_Id : NAND_IDTypeDef
  • TimeFormat : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Timeout : QSPI_HandleTypeDef
  • TimeOutActivation : QSPI_MemoryMappedTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeOutPeriod : QSPI_MemoryMappedTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TransferDirection : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : DFSDM_Filter_RegularParamTypeDef , DFSDM_Filter_InjectedParamTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_DAC_InitTypeDef , LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • TrimmingValueN : OPAMP_InitTypeDef
  • TrimmingValueNLowPower : OPAMP_InitTypeDef
  • TrimmingValueP : OPAMP_InitTypeDef
  • TrimmingValuePLowPower : OPAMP_InitTypeDef
  • TriState : SAI_InitTypeDef
  • TTCM : CAN_InitTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxBufferingMode : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TXFP : CAN_InitTypeDef
  • TxISR : __SPI_HandleTypeDef
  • TxPinLevelInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • TxXferCount : IRDA_HandleTypeDef , SWPMI_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef
  • TxXferSize : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , QSPI_HandleTypeDef , SWPMI_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef
  • Type : DFSDM_Channel_SerialInterfaceTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • Uart4ClockSelection : RCC_PeriphCLKInitTypeDef
  • Uart5ClockSelection : RCC_PeriphCLKInitTypeDef
  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
  • UserTrimming : OPAMP_InitTypeDef
  • USERType : FLASH_OBProgramInitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- v -

  • VDataSegmentLength : FIREWALL_InitTypeDef
  • VDataSegmentStartAddress : FIREWALL_InitTypeDef
  • VolatileDataExecution : FIREWALL_InitTypeDef
  • VolatileDataShared : FIREWALL_InitTypeDef
  • VoltageClass : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • VoltageSource : LCD_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WakeUpEvent : UART_WakeUpTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WaveAutoGeneration : LL_DAC_InitTypeDef
  • WaveAutoGenerationConfig : LL_DAC_InitTypeDef
  • Waveform : LL_LPTIM_InitTypeDef
  • WeekDay : LL_RTC_DateTypeDef , RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WordLength : USART_InitTypeDef , UART_InitTypeDef , SMARTCARD_InitTypeDef , IRDA_InitTypeDef
  • WRPArea : FLASH_OBProgramInitTypeDef
  • WRPEndOffset : FLASH_OBProgramInitTypeDef
  • WRPStartOffset : FLASH_OBProgramInitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : __I2C_HandleTypeDef , SMBUS_HandleTypeDef , __SAI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferOptions : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • XferSize : __SAI_HandleTypeDef , SMBUS_HandleTypeDef , __I2C_HandleTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- z -

  • Zone : NAND_AddressTypeDef
  • ZoneSize : NAND_InfoTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- a -

  • ABOM : CAN_InitTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • AcquisitionMode : TSC_InitTypeDef
  • Activation : DFSDM_Channel_OutputClockTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • Address : FLASH_ProcessTypeDef , QSPI_CommandTypeDef , UART_WakeUpTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddressMode : QSPI_CommandTypeDef
  • AddressSize : QSPI_CommandTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmDateWeekDay : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • Alternate : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • AlternateByteMode : QSPI_CommandTypeDef
  • AlternateBytes : QSPI_CommandTypeDef
  • AlternateBytesSize : QSPI_CommandTypeDef
  • AnalogFilter : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef
  • AutomaticStop : QSPI_AutoPollingTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
  • Awd : DFSDM_Channel_InitTypeDef
  • AWUM : CAN_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- b -

  • Bank : FLASH_ProcessTypeDef
  • BankNumber : CAN_FilterConfTypeDef
  • Banks : FLASH_EraseInitTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • battery_charging_active : PCD_HandleTypeDef
  • BaudRate : UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , IRDA_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BESL : PCD_HandleTypeDef
  • Bias : LCD_InitTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BitRate : SWPMI_InitTypeDef
  • BitRatePrescaler : LL_SWPMI_InitTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlinkFrequency : LCD_InitTypeDef
  • BlinkMode : LCD_InitTypeDef
  • Block : NAND_AddressTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • BlockNbr : NAND_InfoTypeDef
  • BlockSize : NAND_InfoTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef
  • Break2Polarity : TIM_BreakDeadTimeConfigTypeDef
  • Break2State : TIM_BreakDeadTimeConfigTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef
  • BreakPolarity : TIM_BreakDeadTimeConfigTypeDef
  • BreakState : TIM_BreakDeadTimeConfigTypeDef
  • BS1 : CAN_InitTypeDef
  • BS2 : CAN_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • a
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- c -

  • CFI_1 : NOR_CFITypeDef
  • CFI_2 : NOR_CFITypeDef
  • CFI_3 : NOR_CFITypeDef
  • CFI_4 : NOR_CFITypeDef
  • ChainingMode : CRYP_InitTypeDef
  • Channel : DFSDM_Filter_AwdParamTypeDef , TIM_HandleTypeDef , ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef
  • ChannelCount : ADC_InjectionConfigTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ChannelIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • ChipSelectHighTime : QSPI_InitTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockMode : QSPI_InitTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : ADC_InitTypeDef , QSPI_InitTypeDef , TIM_ClockConfigTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , LL_LPTIM_InitTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CodeSegmentLength : FIREWALL_InitTypeDef
  • CodeSegmentStartAddress : FIREWALL_InitTypeDef
  • CommonClock : LL_ADC_CommonInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CompandingMode : SAI_InitTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • ContextQueue : ADC_InjectionConfigTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • Contrast : LCD_InitTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCLength : SPI_InitTypeDef , CRC_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CrypInCount : CRYP_HandleTypeDef
  • CrypOutCount : CRYP_HandleTypeDef
  • CTPulseHighLength : TSC_InitTypeDef
  • CTPulseLowLength : TSC_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- d -

  • DAC_ConnectOnChipPeripheral : DAC_ChannelConfTypeDef
  • DAC_HoldTime : DAC_SampleAndHoldConfTypeDef
  • DAC_OutputBuffer : DAC_ChannelConfTypeDef
  • DAC_RefreshTime : DAC_SampleAndHoldConfTypeDef
  • DAC_SampleAndHold : DAC_ChannelConfTypeDef
  • DAC_SampleAndHoldConfig : DAC_ChannelConfTypeDef
  • DAC_SampleTime : DAC_SampleAndHoldConfTypeDef
  • DAC_Trigger : DAC_ChannelConfTypeDef
  • DAC_TrimmingValue : DAC_ChannelConfTypeDef
  • DAC_UserTrimming : DAC_ChannelConfTypeDef
  • Data : CanTxMsgTypeDef , CanRxMsgTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DataInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DataMode : QSPI_CommandTypeDef
  • DataPacking : DFSDM_Channel_InputTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • DataSource : DFSDM_Filter_AwdParamTypeDef
  • DataType : CRYP_InitTypeDef
  • DataWidth : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DdrHoldHalfCycle : QSPI_CommandTypeDef
  • DdrMode : QSPI_CommandTypeDef
  • DeadTime : TIM_BreakDeadTimeConfigTypeDef , LCD_InitTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • Device_Code1 : NOR_IDTypeDef
  • Device_Code2 : NOR_IDTypeDef
  • Device_Code3 : NOR_IDTypeDef
  • Device_Id : NAND_IDTypeDef
  • Dfsdm1ClockSelection : RCC_PeriphCLKInitTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : LL_DMA_InitTypeDef , DMA_InitTypeDef , SPI_InitTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • Divider : LCD_InitTypeDef , DFSDM_Channel_OutputClockTypeDef
  • DLC : CanTxMsgTypeDef , CanRxMsgTypeDef
  • DMA_Handle : ADC_HandleTypeDef
  • DMA_Handle1 : DAC_HandleTypeDef
  • DMA_Handle2 : DAC_HandleTypeDef
  • DMAAccessMode : ADC_MultiModeTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DMADisableonRxError : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • DmaMode : DFSDM_Filter_RegularParamTypeDef , DFSDM_Filter_InjectedParamTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • DualAddressMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • DummyCycles : QSPI_CommandTypeDef
  • Duty : LCD_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- e -

  • Enable : MPU_Region_InitTypeDef , TIMEx_BreakInputConfigTypeDef
  • EncoderMode : LL_TIM_ENCODER_InitTypeDef , TIM_Encoder_InitTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ErrorCode : CRYP_HandleTypeDef , QSPI_HandleTypeDef , __SAI_HandleTypeDef , DAC_HandleTypeDef , SMARTCARD_HandleTypeDef , SMBUS_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , SWPMI_HandleTypeDef , __DMA_HandleTypeDef , UART_HandleTypeDef , ADC_HandleTypeDef , FLASH_ProcessTypeDef , __I2C_HandleTypeDef , CAN_HandleTypeDef , IRDA_HandleTypeDef , LCD_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • Extended : SRAM_HandleTypeDef , NOR_HandleTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
  • ExtId : CanTxMsgTypeDef , CanRxMsgTypeDef
  • ExtTrigger : DFSDM_Filter_InjectedParamTypeDef
  • ExtTriggerEdge : DFSDM_Filter_InjectedParamTypeDef , DFSDM_Filter_HandleTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
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  • d
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  • f
  • g
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- f -

  • FastMode : DFSDM_Filter_RegularParamTypeDef
  • FIFONumber : CanRxMsgTypeDef
  • FIFOThreshold : SAI_InitTypeDef
  • FifoThreshold : QSPI_InitTypeDef
  • Filter : RTC_TamperTypeDef
  • FilterActivation : CAN_FilterConfTypeDef
  • FilterFIFOAssignment : CAN_FilterConfTypeDef
  • FilterIdHigh : CAN_FilterConfTypeDef
  • FilterIdLow : CAN_FilterConfTypeDef
  • FilterMaskIdHigh : CAN_FilterConfTypeDef
  • FilterMaskIdLow : CAN_FilterConfTypeDef
  • FilterMode : CAN_FilterConfTypeDef
  • FilterNumber : CAN_FilterConfTypeDef
  • FilterOrder : DFSDM_Channel_AwdTypeDef
  • FilterParam : DFSDM_Filter_InitTypeDef
  • FilterScale : CAN_FilterConfTypeDef
  • FirstBit : SAI_InitTypeDef , SPI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FlashSize : QSPI_InitTypeDef
  • FMI : CanRxMsgTypeDef
  • Fourth_Id : NAND_IDTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
  • FunctionalMode : LL_OPAMP_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- g -

  • GCMCMACPhase : CRYP_InitTypeDef
  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • gState : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- h -

  • HardwareFlowControl : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • hc : HCD_HandleTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : QSPI_HandleTypeDef , SRAM_HandleTypeDef , TIM_HandleTypeDef
  • hdmain : CRYP_HandleTypeDef
  • hdmaInj : DFSDM_Filter_HandleTypeDef
  • hdmaout : CRYP_HandleTypeDef
  • hdmaReg : DFSDM_Filter_HandleTypeDef
  • hdmarx : __SPI_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , __I2C_HandleTypeDef , IRDA_HandleTypeDef , __SAI_HandleTypeDef , SMARTCARD_HandleTypeDef
  • hdmatx : __I2C_HandleTypeDef , IRDA_HandleTypeDef , __SAI_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef
  • Header : CRYP_InitTypeDef
  • HeaderSize : CRYP_InitTypeDef
  • HighBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • HighDrive : LCD_InitTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef , DFSDM_Filter_AwdParamTypeDef
  • HourFormat : LL_RTC_InitTypeDef , RTC_InitTypeDef
  • Hours : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c2ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c3ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPolarity : LL_TIM_IC_InitTypeDef , TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IDE : CanTxMsgTypeDef , CanRxMsgTypeDef
  • IN_ep : PCD_HandleTypeDef
  • Info : NAND_HandleTypeDef
  • Init : __SPI_HandleTypeDef , SRAM_HandleTypeDef , SWPMI_HandleTypeDef , TIM_HandleTypeDef , TSC_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , ADC_HandleTypeDef , CAN_HandleTypeDef , COMP_HandleTypeDef , CRC_HandleTypeDef , CRYP_HandleTypeDef , DFSDM_Channel_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __DMA_HandleTypeDef , HCD_HandleTypeDef , __I2C_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , LCD_HandleTypeDef , LPTIM_HandleTypeDef , NAND_HandleTypeDef , NOR_HandleTypeDef , OPAMP_HandleTypeDef , PCD_HandleTypeDef , QSPI_HandleTypeDef , RTC_HandleTypeDef , __SAI_HandleTypeDef , SMARTCARD_HandleTypeDef , SMBUS_HandleTypeDef
  • InitValue : CRC_InitTypeDef
  • InjConvRemaining : DFSDM_Filter_HandleTypeDef
  • InjecOversampling : ADC_InjectionConfTypeDef
  • InjecOversamplingMode : ADC_InjectionConfTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedChannelsNbr : DFSDM_Filter_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedOffsetNumber : ADC_InjectionConfTypeDef
  • InjectedParam : DFSDM_Filter_InitTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedScanMode : DFSDM_Filter_HandleTypeDef
  • InjectedSingleDiff : ADC_InjectionConfTypeDef
  • InjectedTrigger : DFSDM_Filter_HandleTypeDef
  • InjectionConfig : ADC_HandleTypeDef
  • Input : DFSDM_Channel_InitTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputInverting : LL_OPAMP_InitTypeDef
  • InputMinus : LL_COMP_InitTypeDef
  • InputNonInverting : LL_OPAMP_InitTypeDef
  • InputPlus : LL_COMP_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : __SAI_HandleTypeDef , SMBUS_HandleTypeDef , CAN_HandleTypeDef , DFSDM_Channel_HandleTypeDef , TSC_HandleTypeDef , TIM_HandleTypeDef , OPAMP_HandleTypeDef , DFSDM_Filter_HandleTypeDef , COMP_HandleTypeDef , DAC_HandleTypeDef , CRC_HandleTypeDef , __I2C_HandleTypeDef , SWPMI_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef , HCD_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef , NOR_HandleTypeDef , USART_HandleTypeDef , __DMA_HandleTypeDef , CRYP_HandleTypeDef , WWDG_HandleTypeDef , PCD_HandleTypeDef , RTC_HandleTypeDef , LPTIM_HandleTypeDef , NAND_HandleTypeDef , RNG_HandleTypeDef , SRAM_HandleTypeDef , ADC_HandleTypeDef , IWDG_HandleTypeDef , LCD_HandleTypeDef , IRDA_HandleTypeDef
  • Instruction : QSPI_CommandTypeDef
  • InstructionMode : QSPI_CommandTypeDef
  • Interrupt : RTC_TamperTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • Interval : QSPI_AutoPollingTypeDef
  • IntOversampling : DFSDM_Filter_FilterParamTypeDef
  • InvertingInput : COMP_InitTypeDef , OPAMP_InitTypeDef
  • IODefaultMode : TSC_InitTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- k -

  • KeySize : CRYP_InitTypeDef
  • KeyWriteFlag : CRYP_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • Line_32_63 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • Lock : CRC_HandleTypeDef , LCD_HandleTypeDef , TSC_HandleTypeDef , UART_HandleTypeDef , LPTIM_HandleTypeDef , USART_HandleTypeDef , CRYP_HandleTypeDef , NAND_HandleTypeDef , NOR_HandleTypeDef , ADC_HandleTypeDef , DAC_HandleTypeDef , OPAMP_HandleTypeDef , PCD_HandleTypeDef , TIM_HandleTypeDef , SWPMI_HandleTypeDef , SRAM_HandleTypeDef , __SPI_HandleTypeDef , SMBUS_HandleTypeDef , SMARTCARD_HandleTypeDef , __SAI_HandleTypeDef , __DMA_HandleTypeDef , QSPI_HandleTypeDef , RNG_HandleTypeDef , CAN_HandleTypeDef , FLASH_ProcessTypeDef , RTC_HandleTypeDef , HCD_HandleTypeDef , COMP_HandleTypeDef , __I2C_HandleTypeDef , IRDA_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef
  • LowBreakSignal : DFSDM_Filter_AwdParamTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowPowerMode : LL_ADC_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef , DFSDM_Filter_AwdParamTypeDef
  • lpm_active : PCD_HandleTypeDef
  • LPM_State : PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- m -

  • Maker_Id : NAND_IDTypeDef
  • Manufacturer_Code : NOR_IDTypeDef
  • Mask : QSPI_AutoPollingTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef , USART_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • Match : QSPI_AutoPollingTypeDef
  • MatchMode : QSPI_AutoPollingTypeDef
  • MaxCountInterrupt : TSC_InitTypeDef
  • MaxCountValue : TSC_InitTypeDef
  • Mckdiv : SAI_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • Minutes : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Mode : PWR_PVMTypeDef , SMARTCARD_InitTypeDef , PWR_PVDTypeDef , SPI_InitTypeDef , LL_GPIO_InitTypeDef , USART_InitTypeDef , GPIO_InitTypeDef , LL_EXTI_InitTypeDef , UART_InitTypeDef , LL_DMA_InitTypeDef , LL_SPI_InitTypeDef , ADC_MultiModeTypeDef , CAN_InitTypeDef , COMP_InitTypeDef , DMA_InitTypeDef , __I2C_HandleTypeDef , IRDA_InitTypeDef , OPAMP_InitTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : LL_RTC_DateTypeDef , RTC_DateTypeDef
  • MSBFirst : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • MSICalibrationValue : RCC_OscInitTypeDef
  • MSIClockRange : RCC_OscInitTypeDef
  • MSIState : RCC_OscInitTypeDef
  • MultiDMATransfer : LL_ADC_CommonInitTypeDef
  • Multimode : LL_ADC_CommonInitTypeDef
  • Multiplexer : DFSDM_Channel_InputTypeDef
  • MultiTwoSamplingDelay : LL_ADC_CommonInitTypeDef
  • mutecallback : __SAI_HandleTypeDef
  • MuxSegment : LCD_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NART : CAN_InitTypeDef
  • NbData : LL_DMA_InitTypeDef , QSPI_CommandTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbPagesToErase : FLASH_ProcessTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef
  • NonInvertingInput : COMP_InitTypeDef , OPAMP_InitTypeDef
  • NonVDataSegmentLength : FIREWALL_InitTypeDef
  • NonVDataSegmentStartAddress : FIREWALL_InitTypeDef
  • NoStretchMode : SMBUS_InitTypeDef , I2C_InitTypeDef
  • NSS : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- o -

  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • Offset : ADC_ChannelConfTypeDef , DFSDM_Channel_InitTypeDef
  • OffsetNumber : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OperatingMode : CRYP_InitTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OUT_ep : PCD_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputBlankingSource : LL_COMP_InitTypeDef
  • OutputBuffer : LL_DAC_InitTypeDef
  • OutputClock : DFSDM_Channel_InitTypeDef
  • OutputConnection : LL_DAC_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputMode : LL_DAC_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef , LL_COMP_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • Overrun : ADC_InitTypeDef , LL_ADC_REG_InitTypeDef
  • OverrunDisable : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • OverSampling : LL_USART_InitTypeDef
  • Oversampling : ADC_InitTypeDef , DFSDM_Filter_FilterParamTypeDef
  • OverSampling : UART_InitTypeDef
  • Oversampling : DFSDM_Channel_AwdTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OversamplingStopReset : ADC_OversamplingTypeDef
  • OwnAddress1 : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- p -

  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • Page : FLASH_EraseInitTypeDef , NAND_AddressTypeDef , FLASH_ProcessTypeDef
  • PageSize : NAND_InfoTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_USART_InitTypeDef , IRDA_InitTypeDef
  • pBuffPtr : __I2C_HandleTypeDef , __SAI_HandleTypeDef , SMBUS_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • PCROPEndAddr : FLASH_OBProgramInitTypeDef
  • PCROPStartAddr : FLASH_OBProgramInitTypeDef
  • pCrypInBuffPtr : CRYP_HandleTypeDef
  • pCrypOutBuffPtr : CRYP_HandleTypeDef
  • pData : HCD_HandleTypeDef , PCD_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • PeriphRequest : LL_DMA_InitTypeDef
  • PgaGain : OPAMP_InitTypeDef
  • Phase : CRYP_HandleTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • pInitVect : CRYP_InitTypeDef
  • Pins : DFSDM_Channel_InputTypeDef
  • pKey : CRYP_InitTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLM : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef
  • PLLQ : RCC_PLLInitTypeDef
  • PLLR : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLSAI1 : RCC_PeriphCLKInitTypeDef
  • PLLSAI1ClockOut : RCC_PLLSAI1InitTypeDef
  • PLLSAI1M : RCC_PLLSAI1InitTypeDef
  • PLLSAI1N : RCC_PLLSAI1InitTypeDef
  • PLLSAI1P : RCC_PLLSAI1InitTypeDef
  • PLLSAI1Q : RCC_PLLSAI1InitTypeDef
  • PLLSAI1R : RCC_PLLSAI1InitTypeDef
  • PLLSAI1Source : RCC_PLLSAI1InitTypeDef
  • PLLSAI2 : RCC_PeriphCLKInitTypeDef
  • PLLSAI2ClockOut : RCC_PLLSAI2InitTypeDef
  • PLLSAI2M : RCC_PLLSAI2InitTypeDef
  • PLLSAI2N : RCC_PLLSAI2InitTypeDef
  • PLLSAI2P : RCC_PLLSAI2InitTypeDef
  • PLLSAI2R : RCC_PLLSAI2InitTypeDef
  • PLLSAI2Source : RCC_PLLSAI2InitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • Polarity : LPTIM_ULPClockConfigTypeDef , TIMEx_BreakInputConfigTypeDef , LL_LPTIM_InitTypeDef
  • PowerMode : IRDA_InitTypeDef , OPAMP_InitTypeDef , LL_COMP_InitTypeDef , LL_OPAMP_InitTypeDef
  • PowerSupplyRange : OPAMP_InitTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prescaler : WWDG_InitTypeDef , IWDG_InitTypeDef , LL_LPTIM_InitTypeDef , CAN_InitTypeDef , TIM_Base_InitTypeDef , LCD_InitTypeDef , LPTIM_ClockConfigTypeDef , SMARTCARD_InitTypeDef , IRDA_InitTypeDef , LL_TIM_InitTypeDef
  • PreviousState : SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • Priority : LL_DMA_InitTypeDef , DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • Protocol : SAI_InitTypeDef
  • pRxBuffPtr : SMARTCARD_HandleTypeDef , USART_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef , SWPMI_HandleTypeDef
  • pRxMsg : CAN_HandleTypeDef
  • pTxBuffPtr : __SPI_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , QSPI_HandleTypeDef , IRDA_HandleTypeDef , SWPMI_HandleTypeDef , USART_HandleTypeDef
  • pTxMsg : CAN_HandleTypeDef
  • Pull : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Pulse : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • PulseGeneratorPrescaler : TSC_InitTypeDef
  • PulseOnDuration : LCD_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
  • PVMType : PWR_PVMTypeDef
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STM32L486xx HAL User Manual: Data Fields - Variables

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  • QueueInjectedContext : ADC_InjectionConfTypeDef
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  • RandomNumber : RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_InjOversamplingTypeDef , ADC_OversamplingTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • RegularContMode : DFSDM_Filter_HandleTypeDef
  • RegularParam : DFSDM_Filter_InitTypeDef
  • RegularTrigger : DFSDM_Filter_HandleTypeDef
  • Reload : IWDG_InitTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • Request : DMA_InitTypeDef
  • Resolution : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • RFLM : CAN_InitTypeDef
  • RightBitShift : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef , DFSDM_Channel_InitTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RTR : CanTxMsgTypeDef , CanRxMsgTypeDef
  • RxBufferingMode : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • RxISR : __SPI_HandleTypeDef
  • RxPinLevelInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • RxState : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • RxXferCount : SWPMI_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef
  • RxXferSize : USART_HandleTypeDef , SWPMI_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , IRDA_HandleTypeDef , UART_HandleTypeDef , QSPI_HandleTypeDef
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STM32L486xx HAL User Manual: Data Fields - Variables

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  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Sai2ClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleShifting : QSPI_InitTypeDef
  • SampleTime : LPTIM_ULPClockConfigTypeDef , LPTIM_TriggerConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingIOs : TSC_IOConfigTypeDef , TSC_InitTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • ScanMode : DFSDM_Filter_InjectedParamTypeDef
  • Sdmmc1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Selection : DFSDM_Channel_OutputClockTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SerialInterface : DFSDM_Channel_InitTypeDef
  • Setup : PCD_HandleTypeDef
  • ShieldIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • SincOrder : DFSDM_Filter_FilterParamTypeDef
  • SingleDiff : ADC_ChannelConfTypeDef
  • SIOOMode : QSPI_CommandTypeDef
  • Size : MPU_Region_InitTypeDef
  • SJW : CAN_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , TIMEx_BreakInputConfigTypeDef
  • SpareAreaSize : NAND_InfoTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • SpiClock : DFSDM_Channel_SerialInterfaceTypeDef
  • SpreadSpectrum : TSC_InitTypeDef
  • SpreadSpectrumDeviation : TSC_InitTypeDef
  • SpreadSpectrumPrescaler : TSC_InitTypeDef
  • State : RNG_HandleTypeDef , RTC_HandleTypeDef , DAC_HandleTypeDef , __SAI_HandleTypeDef , SMBUS_HandleTypeDef , __SPI_HandleTypeDef , SWPMI_HandleTypeDef , PCD_HandleTypeDef , TSC_HandleTypeDef , QSPI_HandleTypeDef , HCD_HandleTypeDef , NAND_HandleTypeDef , ADC_HandleTypeDef , CAN_HandleTypeDef , USART_HandleTypeDef , COMP_HandleTypeDef , CRC_HandleTypeDef , CRYP_HandleTypeDef , DFSDM_Channel_HandleTypeDef , DFSDM_Filter_HandleTypeDef , __DMA_HandleTypeDef , SRAM_HandleTypeDef , TIM_HandleTypeDef , OPAMP_HandleTypeDef , __I2C_HandleTypeDef , LCD_HandleTypeDef , LPTIM_HandleTypeDef , NOR_HandleTypeDef
  • Status : OPAMP_HandleTypeDef , LPTIM_HandleTypeDef
  • StatusBytesSize : QSPI_AutoPollingTypeDef
  • StdId : CanTxMsgTypeDef , CanRxMsgTypeDef
  • StopBits : USART_InitTypeDef , LL_USART_InitTypeDef , LL_LPUART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SuspendRequest : CRYP_HandleTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • Swpmi1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SynchroPinPolarity : TSC_InitTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
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STM32L486xx HAL User Manual: Data Fields - Variables

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  • Tamper : RTC_TamperTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • Third_Id : NAND_IDTypeDef
  • TimeFormat : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Timeout : QSPI_HandleTypeDef
  • TimeOutActivation : QSPI_MemoryMappedTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeOutPeriod : QSPI_MemoryMappedTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TransferDirection : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : DFSDM_Filter_RegularParamTypeDef , DFSDM_Filter_InjectedParamTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_DAC_InitTypeDef , LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • TrimmingValueN : OPAMP_InitTypeDef
  • TrimmingValueNLowPower : OPAMP_InitTypeDef
  • TrimmingValueP : OPAMP_InitTypeDef
  • TrimmingValuePLowPower : OPAMP_InitTypeDef
  • TriState : SAI_InitTypeDef
  • TTCM : CAN_InitTypeDef
  • TwoSamplingDelay : ADC_MultiModeTypeDef
  • TxBufferingMode : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TXFP : CAN_InitTypeDef
  • TxISR : __SPI_HandleTypeDef
  • TxPinLevelInvert : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • TxXferCount : IRDA_HandleTypeDef , SWPMI_HandleTypeDef , QSPI_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef
  • TxXferSize : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef , QSPI_HandleTypeDef , SWPMI_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef
  • Type : DFSDM_Channel_SerialInterfaceTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
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STM32L486xx HAL User Manual: Data Fields - Variables

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  • Uart4ClockSelection : RCC_PeriphCLKInitTypeDef
  • Uart5ClockSelection : RCC_PeriphCLKInitTypeDef
  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Usart3ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
  • UserTrimming : OPAMP_InitTypeDef
  • USERType : FLASH_OBProgramInitTypeDef
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  • VDataSegmentLength : FIREWALL_InitTypeDef
  • VDataSegmentStartAddress : FIREWALL_InitTypeDef
  • VolatileDataExecution : FIREWALL_InitTypeDef
  • VolatileDataShared : FIREWALL_InitTypeDef
  • VoltageClass : SWPMI_InitTypeDef , LL_SWPMI_InitTypeDef
  • VoltageSource : LCD_InitTypeDef
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STM32L486xx HAL User Manual: Data Fields - Variables

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  • WakeUpEvent : UART_WakeUpTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WaveAutoGeneration : LL_DAC_InitTypeDef
  • WaveAutoGenerationConfig : LL_DAC_InitTypeDef
  • Waveform : LL_LPTIM_InitTypeDef
  • WeekDay : LL_RTC_DateTypeDef , RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WordLength : USART_InitTypeDef , UART_InitTypeDef , SMARTCARD_InitTypeDef , IRDA_InitTypeDef
  • WRPArea : FLASH_OBProgramInitTypeDef
  • WRPEndOffset : FLASH_OBProgramInitTypeDef
  • WRPStartOffset : FLASH_OBProgramInitTypeDef
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STM32L486xx HAL User Manual: Data Fields - Variables

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  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : __I2C_HandleTypeDef , SMBUS_HandleTypeDef , __SAI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferOptions : __I2C_HandleTypeDef , SMBUS_HandleTypeDef
  • XferSize : __SAI_HandleTypeDef , SMBUS_HandleTypeDef , __I2C_HandleTypeDef
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  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
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  • Zone : NAND_AddressTypeDef
  • ZoneSize : NAND_InfoTypeDef
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STM32L486xx HAL User Manual: stm32l4xx_hal_conf.h File Reference

  • File List
  • Globals
Defines
stm32l4xx_hal_conf.h File Reference

HAL configuration template file. This file should be copied to the application folder and renamed to stm32l4xx_hal_conf.h. More...

#include "stm32l4xx_hal_rcc.h"
#include "stm32l4xx_hal_gpio.h"
#include "stm32l4xx_hal_dma.h"
#include "stm32l4xx_hal_dfsdm.h"
#include "stm32l4xx_hal_cortex.h"
#include "stm32l4xx_hal_adc.h"
#include "stm32l4xx_hal_can.h"
#include "stm32l4xx_hal_comp.h"
#include "stm32l4xx_hal_crc.h"
#include "stm32l4xx_hal_cryp.h"
#include "stm32l4xx_hal_dac.h"
#include "stm32l4xx_hal_firewall.h"
#include "stm32l4xx_hal_flash.h"
#include "stm32l4xx_hal_sram.h"
#include "stm32l4xx_hal_nor.h"
#include "stm32l4xx_hal_nand.h"
#include "stm32l4xx_hal_i2c.h"
#include "stm32l4xx_hal_iwdg.h"
#include "stm32l4xx_hal_lcd.h"
#include "stm32l4xx_hal_lptim.h"
#include "stm32l4xx_hal_opamp.h"
#include "stm32l4xx_hal_pwr.h"
#include "stm32l4xx_hal_qspi.h"
#include "stm32l4xx_hal_rng.h"
#include "stm32l4xx_hal_rtc.h"
#include "stm32l4xx_hal_sai.h"
#include "stm32l4xx_hal_sd.h"
#include "stm32l4xx_hal_smbus.h"
#include "stm32l4xx_hal_spi.h"
#include "stm32l4xx_hal_swpmi.h"
#include "stm32l4xx_hal_tim.h"
#include "stm32l4xx_hal_tsc.h"
#include "stm32l4xx_hal_uart.h"
#include "stm32l4xx_hal_usart.h"
#include "stm32l4xx_hal_irda.h"
#include "stm32l4xx_hal_smartcard.h"
#include "stm32l4xx_hal_wwdg.h"
#include "stm32l4xx_hal_pcd.h"
#include "stm32l4xx_hal_hcd.h"

Go to the source code of this file.

Defines

#define | HAL_MODULE_ENABLED
This is the list of modules to be used in the HAL driver.
#define | HAL_ADC_MODULE_ENABLED
#define | HAL_CAN_MODULE_ENABLED
#define | HAL_COMP_MODULE_ENABLED
#define | HAL_CORTEX_MODULE_ENABLED
#define | HAL_CRC_MODULE_ENABLED
#define | HAL_CRYP_MODULE_ENABLED
#define | HAL_DAC_MODULE_ENABLED
#define | HAL_DFSDM_MODULE_ENABLED
#define | HAL_DMA_MODULE_ENABLED
#define | HAL_FIREWALL_MODULE_ENABLED
#define | HAL_FLASH_MODULE_ENABLED
#define | HAL_HCD_MODULE_ENABLED
#define | HAL_NAND_MODULE_ENABLED
#define | HAL_NOR_MODULE_ENABLED
#define | HAL_SRAM_MODULE_ENABLED
#define | HAL_GPIO_MODULE_ENABLED
#define | HAL_I2C_MODULE_ENABLED
#define | HAL_IRDA_MODULE_ENABLED
#define | HAL_IWDG_MODULE_ENABLED
#define | HAL_LCD_MODULE_ENABLED
#define | HAL_LPTIM_MODULE_ENABLED
#define | HAL_OPAMP_MODULE_ENABLED
#define | HAL_PCD_MODULE_ENABLED
#define | HAL_PWR_MODULE_ENABLED
#define | HAL_QSPI_MODULE_ENABLED
#define | HAL_RCC_MODULE_ENABLED
#define | HAL_RNG_MODULE_ENABLED
#define | HAL_RTC_MODULE_ENABLED
#define | HAL_SAI_MODULE_ENABLED
#define | HAL_SD_MODULE_ENABLED
#define | HAL_SMARTCARD_MODULE_ENABLED
#define | HAL_SMBUS_MODULE_ENABLED
#define | HAL_SPI_MODULE_ENABLED
#define | HAL_SWPMI_MODULE_ENABLED
#define | HAL_TIM_MODULE_ENABLED
#define | HAL_TSC_MODULE_ENABLED
#define | HAL_UART_MODULE_ENABLED
#define | HAL_USART_MODULE_ENABLED
#define | HAL_WWDG_MODULE_ENABLED
#define | HSE_VALUE ((uint32_t)8000000U)
Adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSE_STARTUP_TIMEOUT ((uint32_t)100U)
#define | MSI_VALUE ((uint32_t)4000000U)
Internal Multiple Speed oscillator (MSI) default value.
#define | HSI_VALUE ((uint32_t)16000000U)
Internal High Speed oscillator (HSI) value.
#define | HSI48_VALUE ((uint32_t)48000000U)
Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
#define | LSI_VALUE ((uint32_t)32000U)
Internal Low Speed oscillator (LSI) value.
#define | LSE_VALUE ((uint32_t)32768U)
External Low Speed oscillator (LSE) value.
#define | LSE_STARTUP_TIMEOUT ((uint32_t)5000U)
#define | EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)48000U)
External clock source for SAI1 peripheral This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source frequency.
#define | EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U)
External clock source for SAI2 peripheral This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source frequency.
#define | VDD_VALUE ((uint32_t)3300U)
This is the HAL system configuration section.
#define | TICK_INT_PRIORITY ((uint32_t)0x0FU)
#define | USE_RTOS 0
#define | PREFETCH_ENABLE 0
#define | INSTRUCTION_CACHE_ENABLE 1
#define | DATA_CACHE_ENABLE 1
#define | assert_param(expr) ((void)0U)
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Detailed Description

HAL configuration template file. This file should be copied to the application folder and renamed to stm32l4xx_hal_conf.h.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Include module's header file

Definition at line 374 of file stm32l4xx_hal_conf.h.

Referenced by ADC_ConversionStop(), FLASH_MassErase(), FLASH_OB_GetPCROP(), FLASH_OB_GetWRP(), FLASH_OB_PCROPConfig(), FLASH_OB_RDPConfig(), FLASH_OB_UserConfig(), FLASH_OB_WRPConfig(), FLASH_PageErase(), FLASH_Program_DoubleWord(), FLASH_Program_Fast(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_ADCEx_RegularMultiModeStop_DMA(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), HAL_ADCEx_RegularStop_IT(), HAL_CAN_ConfigFilter(), HAL_CAN_DeInit(), HAL_CAN_Init(), HAL_CAN_Receive(), HAL_CAN_Receive_IT(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), HAL_COMP_DeInit(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Stop(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), HAL_CRCEx_Polynomial_Set(), HAL_CRYP_Init(), HAL_DAC_ConfigChannel(), HAL_DAC_DeInit(), HAL_DAC_GetValue(), HAL_DAC_Init(), HAL_DAC_SetValue(), HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop(), HAL_DAC_Stop_DMA(), HAL_DACEx_DualSetValue(), HAL_DACEx_GetTrimOffset(), HAL_DACEx_NoiseWaveGenerate(), HAL_DACEx_SelfCalibrate(), HAL_DACEx_SetUserTrimming(), HAL_DACEx_TriangleWaveGenerate(), HAL_DFSDM_ChannelCkabStart(), HAL_DFSDM_ChannelCkabStart_IT(), HAL_DFSDM_ChannelCkabStop(), HAL_DFSDM_ChannelCkabStop_IT(), HAL_DFSDM_ChannelDeInit(), HAL_DFSDM_ChannelInit(), HAL_DFSDM_ChannelModifyOffset(), HAL_DFSDM_ChannelPollForCkab(), HAL_DFSDM_ChannelPollForScd(), HAL_DFSDM_ChannelScdStart(), HAL_DFSDM_ChannelScdStart_IT(), HAL_DFSDM_ChannelScdStop(), HAL_DFSDM_ChannelScdStop_IT(), HAL_DFSDM_FilterAwdStart_IT(), HAL_DFSDM_FilterAwdStop_IT(), HAL_DFSDM_FilterConfigInjChannel(), HAL_DFSDM_FilterConfigRegChannel(), HAL_DFSDM_FilterDeInit(), HAL_DFSDM_FilterExdStart(), HAL_DFSDM_FilterExdStop(), HAL_DFSDM_FilterGetConvTimeValue(), HAL_DFSDM_FilterGetExdMaxValue(), HAL_DFSDM_FilterGetExdMinValue(), HAL_DFSDM_FilterGetInjectedValue(), HAL_DFSDM_FilterGetRegularValue(), HAL_DFSDM_FilterInit(), HAL_DFSDM_FilterInjectedMsbStart_DMA(), HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_DMA(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStop(), HAL_DFSDM_FilterInjectedStop_DMA(), HAL_DFSDM_FilterInjectedStop_IT(), HAL_DFSDM_FilterPollForInjConversion(), HAL_DFSDM_FilterPollForRegConversion(), HAL_DFSDM_FilterRegularMsbStart_DMA(), HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_DMA(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStop(), HAL_DFSDM_FilterRegularStop_DMA(), HAL_DFSDM_FilterRegularStop_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_FIREWALL_Config(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_OBProgram(), HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), HAL_GPIO_WritePin(), HAL_HalfDuplex_Init(), HAL_HCD_Init(), HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableFastModePlus(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableFastModePlus(), HAL_I2CEx_EnableWakeUp(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IWDG_Init(), HAL_LCD_DeInit(), HAL_LCD_Init(), HAL_LCD_Write(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_MPU_ConfigRegion(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetPriority(), HAL_NVIC_SetPriority(), HAL_NVIC_SetPriorityGrouping(), HAL_OPAMP_DeInit(), HAL_OPAMP_GetState(), HAL_OPAMP_GetTrimOffset(), HAL_OPAMP_Init(), HAL_OPAMP_Lock(), HAL_OPAMP_SelfCalibrate(), HAL_OPAMP_Start(), HAL_OPAMP_Stop(), HAL_OPAMPEx_SelfCalibrateAll(), HAL_OPAMPEx_Unlock(), HAL_PCD_Init(), HAL_PWR_ConfigPVD(), HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_PWREx_ConfigPVM(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableBatteryCharging(), HAL_PWREx_EnableGPIOPullDown(), HAL_PWREx_EnableGPIOPullUp(), HAL_PWREx_EnterSTOP0Mode(), HAL_PWREx_EnterSTOP1Mode(), HAL_PWREx_EnterSTOP2Mode(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_RCC_ClockConfig(), HAL_RCC_GetClockConfig(), HAL_RCC_GetOscConfig(), HAL_RCC_MCOConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_EnableLSCO(), HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_EnablePLLSAI2(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), HAL_RCCEx_StandbyMSIRangeConfig(), HAL_RCCEx_WakeUpStopCLKConfig(), HAL_RNG_Init(), HAL_RS485Ex_Init(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_InitProtocol(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_TimeOut_Config(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SWPMI_DeInit(), HAL_SWPMI_Init(), HAL_SYSCFG_VREFBUF_HighImpedanceConfig(), HAL_SYSCFG_VREFBUF_TrimmingConfig(), HAL_SYSCFG_VREFBUF_VoltageScalingConfig(), HAL_SYSTICK_CLKSourceConfig(), HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), HAL_TSC_DeInit(), HAL_TSC_GetState(), HAL_TSC_GroupGetStatus(), HAL_TSC_GroupGetValue(), HAL_TSC_Init(), HAL_TSC_IOConfig(), HAL_TSC_IODischarge(), HAL_TSC_IRQHandler(), HAL_TSC_PollForAcquisition(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), HAL_TSC_Stop_IT(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_WWDG_Init(), I2C_TransferConfig(), IRDA_SetConfig(), QSPI_Config(), RCCEx_PLLSAI1_Config(), RCCEx_PLLSAI2_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_SetConfig(), SMBUS_TransferConfig(), TIM_CCxChannelCmd(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_SlaveTimer_SetConfig(), UART_AdvFeatureConfig(), UART_SetConfig(), UARTEx_Wakeup_AddressConfig(), and USART_SetConfig().

#define DATA_CACHE_ENABLE 1

Definition at line 190 of file stm32l4xx_hal_conf.h.

#define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)48000U)

External clock source for SAI1 peripheral This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source frequency.

Value of the SAI1 External clock source in Hz

Definition at line 166 of file stm32l4xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U)

External clock source for SAI2 peripheral This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source frequency.

Value of the SAI2 External clock source in Hz

Definition at line 175 of file stm32l4xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define HAL_ADC_MODULE_ENABLED

Definition at line 56 of file stm32l4xx_hal_conf.h.

#define HAL_CAN_MODULE_ENABLED

Definition at line 57 of file stm32l4xx_hal_conf.h.

#define HAL_COMP_MODULE_ENABLED

Definition at line 58 of file stm32l4xx_hal_conf.h.

#define HAL_CORTEX_MODULE_ENABLED

Definition at line 59 of file stm32l4xx_hal_conf.h.

#define HAL_CRC_MODULE_ENABLED

Definition at line 60 of file stm32l4xx_hal_conf.h.

#define HAL_CRYP_MODULE_ENABLED

Definition at line 61 of file stm32l4xx_hal_conf.h.

#define HAL_DAC_MODULE_ENABLED

Definition at line 62 of file stm32l4xx_hal_conf.h.

#define HAL_DFSDM_MODULE_ENABLED

Definition at line 63 of file stm32l4xx_hal_conf.h.

#define HAL_DMA_MODULE_ENABLED

Definition at line 64 of file stm32l4xx_hal_conf.h.

#define HAL_FIREWALL_MODULE_ENABLED

Definition at line 65 of file stm32l4xx_hal_conf.h.

#define HAL_FLASH_MODULE_ENABLED

Definition at line 66 of file stm32l4xx_hal_conf.h.

#define HAL_GPIO_MODULE_ENABLED

Definition at line 71 of file stm32l4xx_hal_conf.h.

#define HAL_HCD_MODULE_ENABLED

Definition at line 67 of file stm32l4xx_hal_conf.h.

#define HAL_I2C_MODULE_ENABLED

Definition at line 72 of file stm32l4xx_hal_conf.h.

#define HAL_IRDA_MODULE_ENABLED

Definition at line 73 of file stm32l4xx_hal_conf.h.

#define HAL_IWDG_MODULE_ENABLED

Definition at line 74 of file stm32l4xx_hal_conf.h.

#define HAL_LCD_MODULE_ENABLED

Definition at line 75 of file stm32l4xx_hal_conf.h.

#define HAL_LPTIM_MODULE_ENABLED

Definition at line 76 of file stm32l4xx_hal_conf.h.

#define HAL_MODULE_ENABLED

This is the list of modules to be used in the HAL driver.

Definition at line 55 of file stm32l4xx_hal_conf.h.

#define HAL_NAND_MODULE_ENABLED

Definition at line 68 of file stm32l4xx_hal_conf.h.

#define HAL_NOR_MODULE_ENABLED

Definition at line 69 of file stm32l4xx_hal_conf.h.

#define HAL_OPAMP_MODULE_ENABLED

Definition at line 77 of file stm32l4xx_hal_conf.h.

#define HAL_PCD_MODULE_ENABLED

Definition at line 78 of file stm32l4xx_hal_conf.h.

#define HAL_PWR_MODULE_ENABLED

Definition at line 79 of file stm32l4xx_hal_conf.h.

#define HAL_QSPI_MODULE_ENABLED

Definition at line 80 of file stm32l4xx_hal_conf.h.

#define HAL_RCC_MODULE_ENABLED

Definition at line 81 of file stm32l4xx_hal_conf.h.

#define HAL_RNG_MODULE_ENABLED

Definition at line 82 of file stm32l4xx_hal_conf.h.

#define HAL_RTC_MODULE_ENABLED

Definition at line 83 of file stm32l4xx_hal_conf.h.

#define HAL_SAI_MODULE_ENABLED

Definition at line 84 of file stm32l4xx_hal_conf.h.

#define HAL_SD_MODULE_ENABLED

Definition at line 85 of file stm32l4xx_hal_conf.h.

#define HAL_SMARTCARD_MODULE_ENABLED

Definition at line 86 of file stm32l4xx_hal_conf.h.

#define HAL_SMBUS_MODULE_ENABLED

Definition at line 87 of file stm32l4xx_hal_conf.h.

#define HAL_SPI_MODULE_ENABLED

Definition at line 88 of file stm32l4xx_hal_conf.h.

#define HAL_SRAM_MODULE_ENABLED

Definition at line 70 of file stm32l4xx_hal_conf.h.

#define HAL_SWPMI_MODULE_ENABLED

Definition at line 89 of file stm32l4xx_hal_conf.h.

#define HAL_TIM_MODULE_ENABLED

Definition at line 90 of file stm32l4xx_hal_conf.h.

#define HAL_TSC_MODULE_ENABLED

Definition at line 91 of file stm32l4xx_hal_conf.h.

#define HAL_UART_MODULE_ENABLED

Definition at line 92 of file stm32l4xx_hal_conf.h.

#define HAL_USART_MODULE_ENABLED

Definition at line 93 of file stm32l4xx_hal_conf.h.

#define HAL_WWDG_MODULE_ENABLED

Definition at line 94 of file stm32l4xx_hal_conf.h.

#define HSE_STARTUP_TIMEOUT ((uint32_t)100U)

Time out for HSE start up, in ms

Definition at line 108 of file stm32l4xx_hal_conf.h.

#define HSE_VALUE ((uint32_t)8000000U)

Adjust the value of External High Speed oscillator (HSE) used in your application.

This value is used by the RCC HAL module to compute the system frequency (when HSE is used as system clock source, directly or through the PLL). Value of the External oscillator in Hz

Definition at line 104 of file stm32l4xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().

#define HSI48_VALUE ((uint32_t)48000000U)

Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.

This internal oscillator is mainly dedicated to provide a high precision clock to the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. When the CRS is not used, the HSI48 RC oscillator runs on it default frequency which is subject to manufacturing process variations. Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.

Definition at line 136 of file stm32l4xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define HSI_VALUE ((uint32_t)16000000U)

Internal High Speed oscillator (HSI) value.

This value is used by the RCC HAL module to compute the system frequency (when HSI is used as system clock source, directly or through the PLL). Value of the Internal oscillator in Hz

Definition at line 125 of file stm32l4xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSWPMIClockFreq(), LL_RCC_GetUARTClockFreq(), LL_RCC_GetUSARTClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), RCC_PLLSAI2_GetFreqDomain_SAI(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define INSTRUCTION_CACHE_ENABLE 1

Definition at line 189 of file stm32l4xx_hal_conf.h.

#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U)

Time out for LSE start up, in ms

Definition at line 157 of file stm32l4xx_hal_conf.h.

#define LSE_VALUE ((uint32_t)32768U)

External Low Speed oscillator (LSE) value.

< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. This value is used by the UART, RTC HAL module to compute the system frequency Value of the External oscillator in Hz

Definition at line 153 of file stm32l4xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetUARTClockFreq(), LL_RCC_GetUSARTClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define LSI_VALUE ((uint32_t)32000U)

Internal Low Speed oscillator (LSI) value.

LSI Typical Value in Hz

Definition at line 144 of file stm32l4xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPTIMClockFreq().

#define MSI_VALUE ((uint32_t)4000000U)

Internal Multiple Speed oscillator (MSI) default value.

This value is the default MSI range value after Reset. Value of the Internal oscillator in Hz

Definition at line 116 of file stm32l4xx_hal_conf.h.

Referenced by HAL_RCC_DeInit().

#define PREFETCH_ENABLE 0

Definition at line 188 of file stm32l4xx_hal_conf.h.

#define TICK_INT_PRIORITY ((uint32_t)0x0FU)

tick interrupt priority

Definition at line 186 of file stm32l4xx_hal_conf.h.

Referenced by HAL_Init(), HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define USE_RTOS 0

Definition at line 187 of file stm32l4xx_hal_conf.h.

#define VDD_VALUE ((uint32_t)3300U)

This is the HAL system configuration section.

Value of VDD in mv

Definition at line 185 of file stm32l4xx_hal_conf.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sd.h File Reference

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stm32l4xx_hal_sd.h File Reference

Header file of SD HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of SD HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_sd.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_adc.c File Reference

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Defines | Functions
stm32l4xx_ll_adc.c File Reference

ADC LL module driver. More...

#include "stm32l4xx_ll_adc.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
#define | ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
#define | ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
#define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__)
#define | IS_LL_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_LOW_POWER(__LOW_POWER__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)
#define | IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)
#define | IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)
#define | IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

ADC LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_adc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_CommonDeInit(), LL_ADC_CommonInit(), LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_comp.c File Reference

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Defines | Functions
stm32l4xx_ll_comp.c File Reference

COMP LL module driver. More...

#include "stm32l4xx_ll_comp.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_COMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

COMP LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_comp.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32l4xx_ll_comp.c.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_crc.c File Reference

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stm32l4xx_ll_crc.c File Reference

CRC LL module driver. More...

#include "stm32l4xx_ll_crc.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

CRC LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_crc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32l4xx_ll_crc.c.

Referenced by LL_CRC_DeInit().

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_crs.c File Reference

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stm32l4xx_ll_crs.c File Reference
#include "stm32l4xx_ll_crs.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_crs.h File Reference

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stm32l4xx_ll_crs.h File Reference

CRS LL module driver. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Detailed Description

CRS LL module driver.

Header file of CRS LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_crs.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_dac.c File Reference

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Defines | Functions
stm32l4xx_ll_dac.c File Reference

DAC LL module driver. More...

#include "stm32l4xx_ll_dac.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)
#define | IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)
#define | IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__)
#define | IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)
#define | IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)
#define | IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)

Functions

ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC instance.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Detailed Description

DAC LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_dac.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32l4xx_ll_dac.c.

Referenced by LL_DAC_DeInit(), and LL_DAC_Init().

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_dma.c File Reference

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Defines | Functions
stm32l4xx_ll_dma.c File Reference

DMA LL module driver. More...

#include "stm32l4xx_ll_dma.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU)
#define | IS_LL_DMA_PERIPHREQUEST(__VALUE__)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Functions

uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Detailed Description

DMA LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_dma.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32l4xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_exti.c File Reference

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Defines | Functions
stm32l4xx_ll_exti.c File Reference

EXTI LL module driver. More...

#include "stm32l4xx_ll_exti.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Functions

uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

EXTI LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_exti.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 44 of file stm32l4xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_gpio.c File Reference

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Defines | Functions
stm32l4xx_ll_gpio.c File Reference

GPIO LL module driver. More...

#include "stm32l4xx_ll_gpio.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

GPIO LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_gpio.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32l4xx_ll_gpio.c.

Referenced by LL_GPIO_DeInit(), and LL_GPIO_Init().

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_i2c.c File Reference

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Defines | Functions
stm32l4xx_ll_i2c.c File Reference

I2C LL module driver. More...

#include "stm32l4xx_ll_i2c.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= (uint32_t)0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Functions

uint32_t | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
uint32_t | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

I2C LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_i2c.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32l4xx_ll_i2c.c.

Referenced by LL_I2C_DeInit(), and LL_I2C_Init().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_lptim.c File Reference

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  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_ll_lptim.c File Reference

LPTIM LL module driver. More...

#include "stm32l4xx_ll_lptim.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LPTIM_CLOCK_SOURCE(__VALUE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__VALUE__)
#define | IS_LPTIM_WAVEFORM(__VALUE__)
#define | IS_LPTIM_OUTPUT_POLARITY(__VALUE__)

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.

Detailed Description

LPTIM LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_lptim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32l4xx_ll_lptim.c.

Referenced by LL_LPTIM_DeInit(), and LL_LPTIM_Init().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_lpuart.c File Reference

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Defines | Functions
stm32l4xx_ll_lpuart.c File Reference

LPUART LL module driver. More...

#include "stm32l4xx_ll_lpuart.h"
#include "stm32l4xx_ll_rcc.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 26000000U) && ((__BAUDRATE__) >= 8U))
#define | IS_LL_LPUART_DIRECTION(__VALUE__)
#define | IS_LL_LPUART_PARITY(__VALUE__)
#define | IS_LL_LPUART_DATAWIDTH(__VALUE__)
#define | IS_LL_LPUART_STOPBITS(__VALUE__)
#define | IS_LL_LPUART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_LPUART_DeInit (USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Detailed Description

LPUART LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_lpuart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32l4xx_ll_lpuart.c.

Referenced by LL_LPUART_DeInit(), and LL_LPUART_Init().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_opamp.c File Reference

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Defines | Functions
stm32l4xx_ll_opamp.c File Reference

OPAMP LL module driver. More...

#include "stm32l4xx_ll_opamp.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)
#define | IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__)
#define | IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__)

Functions

ErrorStatus | LL_OPAMP_DeInit (OPAMP_TypeDef *OPAMPx)
De-initialize registers of the selected OPAMP instance to their default reset values.
ErrorStatus | LL_OPAMP_Init (OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Initialize some features of OPAMP instance.
void | LL_OPAMP_StructInit (LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Set each LL_OPAMP_InitTypeDef field to default value.

Detailed Description

OPAMP LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_opamp.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32l4xx_ll_opamp.c.

Referenced by LL_OPAMP_DeInit(), and LL_OPAMP_Init().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rcc.c File Reference

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Defines | Functions
stm32l4xx_ll_rcc.c File Reference

RCC LL module driver. More...

#include "stm32l4xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_UART_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
#define | IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
#define | IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))
#define | IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))

Functions

uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock frequency used for system domain.
uint32_t | RCC_PLL_GetFreqDomain_SAI (void)
Return PLL clock frequency used for SAI domain.
uint32_t | RCC_PLL_GetFreqDomain_48M (void)
Return PLL clock frequency used for 48 MHz domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_SAI (void)
Return PLLSAI1 clock frequency used for SAI domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_48M (void)
Return PLLSAI1 clock frequency used for 48Mhz domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_ADC (void)
Return PLLSAI1 clock frequency used for ADC domain.
uint32_t | RCC_PLLSAI2_GetFreqDomain_SAI (void)
Return PLLSAI2 clock frequency used for SAI domain.
uint32_t | RCC_PLLSAI2_GetFreqDomain_ADC (void)
Return PLLSAI2 clock frequency used for ADC domain.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetUARTClockFreq (uint32_t UARTxSource)
Return UARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetSDMMCClockFreq (uint32_t SDMMCxSource)
Return SDMMCx clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetSWPMIClockFreq (uint32_t SWPMIxSource)
Return SWPMIx clock frequency.
uint32_t | LL_RCC_GetDFSDMClockFreq (uint32_t DFSDMxSource)
Return DFSDMx clock frequency.

Detailed Description

RCC LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_rcc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 44 of file stm32l4xx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetDFSDMClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetSWPMIClockFreq(), LL_RCC_GetUARTClockFreq(), LL_RCC_GetUSARTClockFreq(), and LL_RCC_GetUSBClockFreq().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rng.c File Reference

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Defines | Functions
stm32l4xx_ll_rng.c File Reference

RNG LL module driver. More...

#include "stm32l4xx_ll_rng.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).

Detailed Description

RNG LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_rng.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32l4xx_ll_rng.c.

Referenced by LL_RNG_DeInit().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rtc.c File Reference

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Defines | Functions
stm32l4xx_ll_rtc.c File Reference

RTC LL module driver. More...

#include "stm32l4xx_ll_rtc.h"
#include "stm32l4xx_ll_cortex.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU)
#define | RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU)
#define | RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
#define | IS_LL_RTC_MONTH(__VALUE__)
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

RTC LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_rtc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32l4xx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_EnterInitMode(), LL_RTC_ExitInitMode(), LL_RTC_Init(), LL_RTC_TIME_Init(), and LL_RTC_WaitForSynchro().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_spi.c File Reference

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Defines | Functions
stm32l4xx_ll_spi.c File Reference

SPI LL module driver. More...

#include "stm32l4xx_ll_spi.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | SPI_CR1_CLEAR_MASK
#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Detailed Description

SPI LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_spi.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32l4xx_ll_spi.c.

Referenced by LL_SPI_DeInit(), and LL_SPI_Init().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_swpmi.c File Reference

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Defines | Functions
stm32l4xx_ll_swpmi.c File Reference

SWPMI LL module driver. More...

#include "stm32l4xx_ll_swpmi.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
#define | IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__)
#define | IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__)
#define | IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__)

Functions

ErrorStatus | LL_SWPMI_DeInit (SWPMI_TypeDef *SWPMIx)
De-initialize the SWPMI peripheral registers to their default reset values.
ErrorStatus | LL_SWPMI_Init (SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
void | LL_SWPMI_StructInit (LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Set each LL_SWPMI_InitTypeDef field to default value.

Detailed Description

SWPMI LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_swpmi.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32l4xx_ll_swpmi.c.

Referenced by LL_SWPMI_DeInit(), and LL_SWPMI_Init().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_tim.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Defines | Functions
stm32l4xx_ll_tim.c File Reference

TIM LL module driver. More...

#include "stm32l4xx_ll_tim.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | OC5Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 5.
static ErrorStatus | OC6Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 6.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.

Detailed Description

TIM LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_tim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32l4xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_DeInit(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_usart.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Defines | Functions
stm32l4xx_ll_usart.c File Reference

USART LL module driver. More...

#include "stm32l4xx_ll_usart.h"
#include "stm32l4xx_ll_rcc.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Detailed Description

USART LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_usart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32l4xx_ll_usart.c.

Referenced by LL_USART_ClockInit(), LL_USART_DeInit(), and LL_USART_Init().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_utils.c File Reference

  • File List
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  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Defines | Functions
stm32l4xx_ll_utils.c File Reference

UTILS LL module driver. More...

#include "stm32l4xx_ll_utils.h"
#include "stm32l4xx_ll_rcc.h"
#include "stm32l4xx_ll_system.h"
#include "stm32l4xx_ll_pwr.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | UTILS_MAX_FREQUENCY_SCALE1 ((uint32_t)80000000)
#define | UTILS_MAX_FREQUENCY_SCALE2 ((uint32_t)26000000)
#define | UTILS_PLLVCO_INPUT_MIN ((uint32_t)4000000)
#define | UTILS_PLLVCO_INPUT_MAX ((uint32_t)16000000)
#define | UTILS_PLLVCO_OUTPUT_MIN ((uint32_t)64000000)
#define | UTILS_PLLVCO_OUTPUT_MAX ((uint32_t)344000000)
#define | UTILS_HSE_FREQUENCY_MIN ((uint32_t)4000000)
#define | UTILS_HSE_FREQUENCY_MAX ((uint32_t)48000000)
#define | UTILS_SCALE1_LATENCY1_FREQ ((uint32_t)16000000)
#define | UTILS_SCALE1_LATENCY2_FREQ ((uint32_t)32000000)
#define | UTILS_SCALE1_LATENCY3_FREQ ((uint32_t)48000000)
#define | UTILS_SCALE1_LATENCY4_FREQ ((uint32_t)64000000)
#define | UTILS_SCALE2_LATENCY1_FREQ ((uint32_t)6000000)
#define | UTILS_SCALE2_LATENCY2_FREQ ((uint32_t)12000000)
#define | UTILS_SCALE2_LATENCY3_FREQ ((uint32_t)18000000)
#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
#define | IS_LL_UTILS_PLLR_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_SetFlashLatency (uint32_t HCLK_Frequency)
Update number of Flash wait states in line with new frequency and current voltage range.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_MSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with MSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

UTILS LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_utils.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32l4xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_GetPLLOutputFrequency().

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __ADC_MASK_SHIFT : stm32l4xx_ll_adc.h
  • __ADC_PTR_REG_OFFSET : stm32l4xx_ll_adc.h
  • __DAC_MASK_SHIFT : stm32l4xx_ll_dac.h
  • __DAC_PTR_REG_OFFSET : stm32l4xx_ll_dac.h
  • __HAL_ADC_CLEAR_FLAG : stm32l4xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32l4xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32l4xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32l4xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32l4xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32l4xx_hal_adc.h
  • __HAL_CAN_CANCEL_TRANSMIT : stm32l4xx_hal_can.h
  • __HAL_CAN_CLEAR_FLAG : stm32l4xx_hal_can.h
  • __HAL_CAN_DBG_FREEZE : stm32l4xx_hal_can.h
  • __HAL_CAN_DISABLE_IT : stm32l4xx_hal_can.h
  • __HAL_CAN_ENABLE_IT : stm32l4xx_hal_can.h
  • __HAL_CAN_FIFO_RELEASE : stm32l4xx_hal_can.h
  • __HAL_CAN_GET_FLAG : stm32l4xx_hal_can.h
  • __HAL_CAN_GET_IT_SOURCE : stm32l4xx_hal_can.h
  • __HAL_CAN_MSG_PENDING : stm32l4xx_hal_can.h
  • __HAL_CAN_RESET_HANDLE_STATE : stm32l4xx_hal_can.h
  • __HAL_CAN_TRANSMIT_STATUS : stm32l4xx_hal_can.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32l4xx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32l4xx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32l4xx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32l4xx_hal_comp.h
  • __HAL_COMP_LOCK : stm32l4xx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32l4xx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32l4xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32l4xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32l4xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32l4xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32l4xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32l4xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32l4xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32l4xx_hal_crc.h
  • __HAL_CRYP_CLEAR_FLAG : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_CLEAR_IT : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_DISABLE : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_DISABLE_IT : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_ENABLE : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_ENABLE_IT : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_GET_FLAG : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_GET_IT : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_GET_IT_SOURCE : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_RESET_HANDLE_STATE : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_SET_CHAININGMODE : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_SET_OPERATINGMODE : stm32l4xx_hal_cryp.h
  • __HAL_DAC_CLEAR_FLAG : stm32l4xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32l4xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32l4xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32l4xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32l4xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32l4xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32l4xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32l4xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_CAN1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM2 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM2 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM15 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM16 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM17 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM5 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM8 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32l4xx_hal.h
  • __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE : stm32l4xx_hal_dfsdm.h
  • __HAL_DFSDM_FILTER_RESET_HANDLE_STATE : stm32l4xx_hal_dfsdm.h
  • __HAL_DMA_CLEAR_FLAG : stm32l4xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32l4xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32l4xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32l4xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32l4xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32l4xx_hal_dma.h
  • __HAL_FIREWALL_GET_PREARM : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_GET_VOLATILEDATA_SHARED : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_IS_ENABLED : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_PREARM_DISABLE : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_PREARM_ENABLE : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE : stm32l4xx_hal_firewall.h
  • __HAL_FLASH_CLEAR_FLAG : stm32l4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_DISABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_ENABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_RESET : stm32l4xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32l4xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32l4xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32l4xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32l4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_DISABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_ENABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_RESET : stm32l4xx_hal_flash.h
  • __HAL_FLASH_POWER_DOWN_DISABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_POWER_DOWN_ENABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32l4xx_hal_flash.h
  • __HAL_FLASH_SLEEP_POWERDOWN_DISABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_SLEEP_POWERDOWN_ENABLE : stm32l4xx_hal_flash.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32l4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32l4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32l4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32l4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32l4xx_hal_gpio.h
  • __HAL_HCD_CLEAR_FLAG : stm32l4xx_hal_hcd.h
  • __HAL_HCD_CLEAR_HC_INT : stm32l4xx_hal_hcd.h
  • __HAL_HCD_DISABLE : stm32l4xx_hal_hcd.h
  • __HAL_HCD_ENABLE : stm32l4xx_hal_hcd.h
  • __HAL_HCD_GET_FLAG : stm32l4xx_hal_hcd.h
  • __HAL_HCD_IS_INVALID_INTERRUPT : stm32l4xx_hal_hcd.h
  • __HAL_HCD_MASK_ACK_HC_INT : stm32l4xx_hal_hcd.h
  • __HAL_HCD_MASK_HALT_HC_INT : stm32l4xx_hal_hcd.h
  • __HAL_HCD_UNMASK_ACK_HC_INT : stm32l4xx_hal_hcd.h
  • __HAL_HCD_UNMASK_HALT_HC_INT : stm32l4xx_hal_hcd.h
  • __HAL_I2C_CLEAR_FLAG : stm32l4xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32l4xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32l4xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32l4xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32l4xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32l4xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32l4xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32l4xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32l4xx_hal_i2c.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32l4xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32l4xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32l4xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32l4xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32l4xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32l4xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32l4xx_hal_iwdg.h
  • __HAL_LCD_BLINK_CONFIG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_CLEAR_FLAG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_CONTRAST_CONFIG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_DEADTIME_CONFIG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_DISABLE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_DISABLE_IT : stm32l4xx_hal_lcd.h
  • __HAL_LCD_ENABLE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_ENABLE_IT : stm32l4xx_hal_lcd.h
  • __HAL_LCD_GET_FLAG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_GET_IT_SOURCE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_HIGHDRIVER_DISABLE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_HIGHDRIVER_ENABLE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_PULSEONDURATION_CONFIG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_RESET_HANDLE_STATE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_VOLTAGE_BUFFER_DISABLE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_VOLTAGE_BUFFER_ENABLE : stm32l4xx_hal_lcd.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_StateTypeDef : stm32l4xx_hal_lptim.h
  • __HAL_NAND_RESET_HANDLE_STATE : stm32l4xx_hal_nand.h
  • __HAL_NOR_RESET_HANDLE_STATE : stm32l4xx_hal_nor.h
  • __HAL_OPAMP_RESET_HANDLE_STATE : stm32l4xx_hal_opamp.h
  • __HAL_PCD_CLEAR_FLAG : stm32l4xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32l4xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32l4xx_hal_pcd.h
  • __HAL_PCD_GATE_PHYCLOCK : stm32l4xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32l4xx_hal_pcd.h
  • __HAL_PCD_IS_INVALID_INTERRUPT : stm32l4xx_hal_pcd.h
  • __HAL_PCD_IS_PHY_SUSPENDED : stm32l4xx_hal_pcd.h
  • __HAL_PCD_UNGATE_PHYCLOCK : stm32l4xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32l4xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVM1_EXTI_CLEAR_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GENERATE_SWIT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GET_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_CLEAR_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_GENERATE_SWIT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_GET_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_CLEAR_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GENERATE_SWIT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GET_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_CLEAR_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_GENERATE_SWIT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_GET_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32l4xx_hal_pwr_ex.h
  • __HAL_QSPI_CLEAR_FLAG : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_DISABLE : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_DISABLE_IT : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_ENABLE : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_ENABLE_IT : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_GET_FLAG : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_GET_IT_SOURCE : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_RESET_HANDLE_STATE : stm32l4xx_hal_qspi.h
  • __HAL_RCC_ADC_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_ADC_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_DFSDM1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FIREWALL_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FIREWALL_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_DFSDM1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM2_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_MSI_RANGE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_PLLCLKOUT_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI2_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SDMMC1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SWPMI1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_UART4_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART5_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSIAUTOMATIC_START_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSIAUTOMATIC_START_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GET_FLAG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MSI_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MSI_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MSI_RANGE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MSI_STANDBY_RANGE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLLSAI1_CLEAR_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DISABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DISABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVP_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVQ_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVR_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_ENABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_ENABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_GET_FLAG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_GET_IT_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_MULN_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1CLKOUT_DISABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1CLKOUT_ENABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_CLEAR_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_DISABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_DISABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_DIVP_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_DIVR_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_ENABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_ENABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_GET_FLAG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_GET_IT_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_MULN_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2CLKOUT_DISABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2CLKOUT_ENABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_SWPMI1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WAKEUPSTOP_CLK_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32l4xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32l4xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32l4xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32l4xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32l4xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32l4xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32l4xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32l4xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32l4xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32l4xx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32l4xx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32l4xx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32l4xx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32l4xx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32l4xx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32l4xx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32l4xx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32l4xx_hal_sai.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32l4xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32l4xx_hal_smbus.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32l4xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32l4xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32l4xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32l4xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32l4xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32l4xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32l4xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32l4xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32l4xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32l4xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32l4xx_hal_spi.h
  • __HAL_SRAM_RESET_HANDLE_STATE : stm32l4xx_hal_sram.h
  • __HAL_SWPMI_CLEAR_FLAG : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE_IT : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE_IT : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_GET_FLAG : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT_SOURCE : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_RESET_HANDLE_STATE : stm32l4xx_hal_swpmi.h
  • __HAL_SYSCFG_BREAK_ECC_LOCK : stm32l4xx_hal.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32l4xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32l4xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK : stm32l4xx_hal.h
  • __HAL_SYSCFG_CLEAR_FLAG : stm32l4xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32l4xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32l4xx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_DISABLE : stm32l4xx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_ENABLE : stm32l4xx_hal.h
  • __HAL_SYSCFG_GET_BOOT_MODE : stm32l4xx_hal.h
  • __HAL_SYSCFG_GET_FLAG : stm32l4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32l4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FMC : stm32l4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_QUADSPI : stm32l4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32l4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32l4xx_hal.h
  • __HAL_SYSCFG_SRAM2_ERASE : stm32l4xx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_ENABLE : stm32l4xx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_UNLOCK : stm32l4xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32l4xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32l4xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32l4xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32l4xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32l4xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32l4xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32l4xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32l4xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32l4xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32l4xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32l4xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32l4xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32l4xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32l4xx_hal_tim.h
  • __HAL_TSC_CLEAR_FLAG : stm32l4xx_hal_tsc.h
  • __HAL_TSC_CLOSE_ANALOG_SWITCH : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE_CHANNEL : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE_GROUP : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE_HYSTERESIS : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE_IT : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE_SAMPLING : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE_CHANNEL : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE_GROUP : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE_HYSTERESIS : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE_IT : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE_SAMPLING : stm32l4xx_hal_tsc.h
  • __HAL_TSC_GET_FLAG : stm32l4xx_hal_tsc.h
  • __HAL_TSC_GET_GROUP_STATUS : stm32l4xx_hal_tsc.h
  • __HAL_TSC_GET_IT_SOURCE : stm32l4xx_hal_tsc.h
  • __HAL_TSC_OPEN_ANALOG_SWITCH : stm32l4xx_hal_tsc.h
  • __HAL_TSC_RESET_HANDLE_STATE : stm32l4xx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_INFLOAT : stm32l4xx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_OUTPPLOW : stm32l4xx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_FALL : stm32l4xx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_RISE_HIGH : stm32l4xx_hal_tsc.h
  • __HAL_TSC_START_ACQ : stm32l4xx_hal_tsc.h
  • __HAL_TSC_STOP_ACQ : stm32l4xx_hal_tsc.h
  • __HAL_UART_CLEAR_FEFLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32l4xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32l4xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32l4xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32l4xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32l4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32l4xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32l4xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32l4xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32l4xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32l4xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32l4xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32l4xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32l4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32l4xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32l4xx_hal_usart.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG : stm32l4xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32l4xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32l4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32l4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32l4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW : stm32l4xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32l4xx_ll_adc.h
  • __LL_ADC_CALC_DATA_VOLTAGE : stm32l4xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32l4xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32l4xx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32l4xx_ll_adc.h
  • __LL_ADC_CALIB_FACTOR_SINGLE_DIFF : stm32l4xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32l4xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32l4xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32l4xx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32l4xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32l4xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32l4xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32l4xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32l4xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32l4xx_ll_adc.h
  • __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32l4xx_ll_adc.h
  • __LL_COMP_COMMON_INSTANCE : stm32l4xx_ll_comp.h
  • __LL_DAC_CALC_VOLTAGE_TO_DATA : stm32l4xx_ll_dac.h
  • __LL_DAC_CHANNEL_TO_DECIMAL_NB : stm32l4xx_ll_dac.h
  • __LL_DAC_DECIMAL_NB_TO_CHANNEL : stm32l4xx_ll_dac.h
  • __LL_DAC_DIGITAL_SCALE : stm32l4xx_ll_dac.h
  • __LL_DMA_GET_CHANNEL : stm32l4xx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32l4xx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32l4xx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32l4xx_ll_i2c.h
  • __LL_LPUART_DIV : stm32l4xx_ll_lpuart.h
  • __LL_OPAMP_COMMON_INSTANCE : stm32l4xx_ll_opamp.h
  • __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE : stm32l4xx_ll_opamp.h
  • __LL_RCC_CALC_HCLK_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_MSI_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK2_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_48M_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_SAI_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_48M_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_ADC_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_SAI_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI2_ADC_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI2_SAI_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32l4xx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32l4xx_ll_rtc.h
  • __LL_SWPMI_CALC_BITRATE_PRESCALER : stm32l4xx_ll_swpmi.h
  • __LL_TIM_CALC_ARR : stm32l4xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32l4xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32l4xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32l4xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32l4xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32l4xx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32l4xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32l4xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32l4xx_ll_usart.h
  • __LSCO_CLK_ENABLE : stm32l4xx_hal_rcc_ex.c
  • __MCO1_CLK_ENABLE : stm32l4xx_hal_rcc.c
  • __OPAMP_PTR_REG_OFFSET : stm32l4xx_ll_opamp.h
  • __STM32L4xx_HAL_VERSION : stm32l4xx_hal.c
  • __STM32L4xx_HAL_VERSION_MAIN : stm32l4xx_hal.c
  • __STM32L4xx_HAL_VERSION_RC : stm32l4xx_hal.c
  • __STM32L4xx_HAL_VERSION_SUB1 : stm32l4xx_hal.c
  • __STM32L4xx_HAL_VERSION_SUB2 : stm32l4xx_hal.c
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • a_dfsdm1ChannelHandle : stm32l4xx_hal_dfsdm.c
  • ADC_ANALOGWATCHDOG_1 : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_2 : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_3 : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_NONE : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32l4xx_hal_adc_ex.h
  • ADC_ANY_OTHER_ENABLED : stm32l4xx_hal_adc_ex.h
  • ADC_AWD1_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32l4xx_hal_adc_ex.h
  • ADC_AWD23THRESHOLD_SHIFT_RESOLUTION : stm32l4xx_hal_adc_ex.h
  • ADC_AWD2_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_AWD3_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_AWD_CR12_REGOFFSETGAP_MASK : stm32l4xx_ll_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_VAL : stm32l4xx_ll_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32l4xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_CR23_CHANNEL_MASK : stm32l4xx_ll_adc.h
  • ADC_AWD_CR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_CR3_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32l4xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_AWD_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_AWD_TR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_TR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_TR3_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_BATTERY_VOLTAGE_INSTANCE : stm32l4xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_GET : stm32l4xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_SET : stm32l4xx_hal_adc_ex.h
  • ADC_CALIBRATION_TIMEOUT : stm32l4xx_hal_adc_ex.c
  • ADC_CCR_MULTI_DMACONTREQ : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR2_FIELDS : stm32l4xx_hal_adc.c
  • ADC_CFGR2_INJ_FIELDS : stm32l4xx_hal_adc_ex.c
  • ADC_CFGR_AUTOWAIT : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_AWD1EN_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CFGR_AWD1SGL_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CFGR_CONTINUOUS : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_DFSDM : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_DISCONTINUOUS_NUM : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_DMACONTREQ : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS_1 : stm32l4xx_hal_adc.c
  • ADC_CFGR_FIELDS_2 : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_CONTEXT_QUEUE : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_DISCCONTINUOUS : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_JAWD1EN_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CFGR_REG_DISCONTINUOUS : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_RES_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CFGR_SET_AWD1CH : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_SET_AWD23CR : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_WD_FIELDS : stm32l4xx_hal_adc.c
  • ADC_CHANNEL_0 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_0_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_10_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_11_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_12_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_13_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_14_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_15_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_16_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_17_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_18 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_18_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_18_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_18_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_1_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_2_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_3_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_4_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_5_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_6_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_7_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_8_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_9_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_BITFIELD_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_2 : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_VBAT : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32l4xx_hal_adc.h
  • ADC_CLEAR_COMMON_CONTROL_REGISTER : stm32l4xx_hal_adc_ex.h
  • ADC_CLEAR_ERRORCODE : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_RATIO_VS_CPU_HIGHEST : stm32l4xx_ll_adc.c
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32l4xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV1 : stm32l4xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV2 : stm32l4xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV4 : stm32l4xx_hal_adc.h
  • ADC_COMMON_REGISTER : stm32l4xx_hal_adc_ex.h
  • ADC_CONVERSION_TIME_MAX_CPU_CYCLES : stm32l4xx_hal_adc.c
  • ADC_ConversionStop() : stm32l4xx_hal_adc.c
  • ADC_CR_BITS_PROPERTY_RS : stm32l4xx_ll_adc.h
  • ADC_DATAALIGN_LEFT : stm32l4xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32l4xx_hal_adc.h
  • ADC_DIFFERENTIAL_ENDED : stm32l4xx_hal_adc_ex.h
  • ADC_DIFSEL_CHANNEL : stm32l4xx_hal_adc_ex.h
  • ADC_Disable() : stm32l4xx_hal_adc.c
  • ADC_DISABLE : stm32l4xx_hal_adc_ex.h
  • ADC_DISABLE_TIMEOUT : stm32l4xx_hal_adc.c
  • ADC_DISABLING_CONDITIONS : stm32l4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_12_10_BITS : stm32l4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_8_6_BITS : stm32l4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_DISABLED : stm32l4xx_hal_adc_ex.h
  • ADC_DMAConvCplt() : stm32l4xx_hal_adc.c
  • ADC_DMAError() : stm32l4xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32l4xx_hal_adc.c
  • ADC_DUALMODE_ALTERTRIG : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGINTERL_INJECSIMULT : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32l4xx_hal_adc_ex.h
  • ADC_Enable() : stm32l4xx_hal_adc.c
  • ADC_ENABLE : stm32l4xx_hal_adc_ex.h
  • ADC_ENABLE_TIMEOUT : stm32l4xx_hal_adc.c
  • ADC_ENABLING_CONDITIONS : stm32l4xx_hal_adc_ex.h
  • ADC_EOC_SEQ_CONV : stm32l4xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32l4xx_hal_adc.h
  • ADC_EOC_SINGLE_SEQ_CONV : stm32l4xx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T15_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC1 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC2 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC3 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_CC4 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_CC4 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T6_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO2 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T15_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC4 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO2 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC1 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC3 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC4 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T6_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_CC4 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO2 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_ALL : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_AWD1 : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_AWD2 : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_AWD3 : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_EOC : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_EOS : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_EOSMP : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_JEOC : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_JEOS : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_JQOVF : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_OVR : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_POSTCONV_ALL : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_RDY : stm32l4xx_hal_adc_ex.h
  • ADC_GET_RESOLUTION : stm32l4xx_hal_adc.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE : stm32l4xx_hal_adc_ex.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE : stm32l4xx_hal_adc_ex.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_INJ_RANK_1_JSQR_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_RANK_2_JSQR_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_RANK_3_JSQR_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_RANK_4_JSQR_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32l4xx_ll_adc.h
  • ADC_INJ_TRIG_EDGE_MASK : stm32l4xx_ll_adc.h
  • ADC_INJ_TRIG_EXT_EDGE_DEFAULT : stm32l4xx_ll_adc.h
  • ADC_INJ_TRIG_EXTEN_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_TRIG_SOURCE_MASK : stm32l4xx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32l4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32l4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32l4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32l4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32l4xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32l4xx_hal_adc_ex.h
  • ADC_INSTANCE_IS_ENABLED : stm32l4xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_INJECTED : stm32l4xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR : stm32l4xx_hal_adc.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED : stm32l4xx_hal_adc_ex.h
  • ADC_IS_DUAL_CONVERSION_ENABLE : stm32l4xx_hal_adc_ex.h
  • ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE : stm32l4xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32l4xx_hal_adc.h
  • ADC_IS_INDEPENDENT : stm32l4xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32l4xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32l4xx_hal_adc.h
  • ADC_IT_AWD : stm32l4xx_hal_adc_ex.h
  • ADC_IT_AWD1 : stm32l4xx_hal_adc_ex.h
  • ADC_IT_AWD2 : stm32l4xx_hal_adc_ex.h
  • ADC_IT_AWD3 : stm32l4xx_hal_adc_ex.h
  • ADC_IT_EOC : stm32l4xx_hal_adc_ex.h
  • ADC_IT_EOS : stm32l4xx_hal_adc_ex.h
  • ADC_IT_EOSMP : stm32l4xx_hal_adc_ex.h
  • ADC_IT_JEOC : stm32l4xx_hal_adc_ex.h
  • ADC_IT_JEOS : stm32l4xx_hal_adc_ex.h
  • ADC_IT_JQOVF : stm32l4xx_hal_adc_ex.h
  • ADC_IT_OVR : stm32l4xx_hal_adc_ex.h
  • ADC_IT_RDY : stm32l4xx_hal_adc_ex.h
  • ADC_JDR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_JQOVF_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_JSQR_FIELDS : stm32l4xx_hal_adc_ex.c
  • ADC_JSQR_RK : stm32l4xx_hal_adc_ex.h
  • ADC_MASTER_REGISTER : stm32l4xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32l4xx_hal_adc_ex.h
  • ADC_MULTI_SLAVE : stm32l4xx_hal_adc_ex.h
  • ADC_MULTIMODE_DMA_ENABLED : stm32l4xx_hal_adc_ex.h
  • ADC_NONMULTIMODE_OR_MULTIMODEMASTER : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_1 : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_2 : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_3 : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_4 : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_NONE : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_SHIFT_RESOLUTION : stm32l4xx_hal_adc_ex.h
  • ADC_OFR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_OFR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_OFR3_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_OFR4_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_OFR_CHANNEL : stm32l4xx_hal_adc_ex.h
  • ADC_OFR_FIELDS : stm32l4xx_hal_adc.c
  • ADC_OFRx_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_OVERSAMPLING_RATIO_128 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_16 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_2 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_256 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_32 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_4 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_64 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_8 : stm32l4xx_hal_adc_ex.h
  • ADC_OVR_DATA_OVERWRITTEN : stm32l4xx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32l4xx_hal_adc.h
  • ADC_OVR_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32l4xx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_REG_TRIG_EDGE_MASK : stm32l4xx_ll_adc.h
  • ADC_REG_TRIG_EXT_EDGE_DEFAULT : stm32l4xx_ll_adc.h
  • ADC_REG_TRIG_EXTEN_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_TRIG_EXTSEL_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_TRIG_SOURCE_MASK : stm32l4xx_ll_adc.h
  • ADC_REGOVERSAMPLING_CONTINUED_MODE : stm32l4xx_hal_adc_ex.h
  • ADC_REGOVERSAMPLING_RESUMED_MODE : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_GROUP : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_10 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_11 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_12 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_13 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_14 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_15 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_16 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_2 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_3 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_4 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_5 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_6 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_7 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_8 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_9 : stm32l4xx_hal_adc_ex.h
  • ADC_RESOLUTION_10B : stm32l4xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32l4xx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32l4xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32l4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_2 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_3 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_4 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_5 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_6 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_7 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_8 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_NONE : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_12CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_247CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_24CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_2CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_47CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_640CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_6CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_92CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SCAN_DISABLE : stm32l4xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32l4xx_hal_adc.h
  • ADC_SINGLE_ENDED : stm32l4xx_hal_adc_ex.h
  • ADC_SINGLEDIFF_CALIB_FACTOR_MASK : stm32l4xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_START_MASK : stm32l4xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_MASK : stm32l4xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK : stm32l4xx_ll_adc.h
  • ADC_SMPR1 : stm32l4xx_hal_adc_ex.h
  • ADC_SMPR1_FIELDS : stm32l4xx_hal_adc_ex.h
  • ADC_SMPR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SMPR1_SETTING : stm32l4xx_hal_adc_ex.h
  • ADC_SMPR2 : stm32l4xx_hal_adc_ex.h
  • ADC_SMPR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SMPR2_SETTING : stm32l4xx_hal_adc_ex.h
  • ADC_SOFTWARE_START : stm32l4xx_hal_adc.h
  • ADC_SQR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SQR1_RK : stm32l4xx_hal_adc_ex.h
  • ADC_SQR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SQR2_RK : stm32l4xx_hal_adc_ex.h
  • ADC_SQR3_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SQR3_RK : stm32l4xx_hal_adc_ex.h
  • ADC_SQR4_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SQR4_RK : stm32l4xx_hal_adc_ex.h
  • ADC_STAB_DELAY_US : stm32l4xx_hal_adc.c
  • ADC_STATE_CLR_SET : stm32l4xx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32l4xx_hal_adc.h
  • ADC_TEMPERATURE_SENSOR_INSTANCE : stm32l4xx_hal_adc_ex.h
  • ADC_TEMPSENSOR_DELAY_US : stm32l4xx_hal_adc.h
  • ADC_TIMEOUT_DISABLE_CPU_CYCLES : stm32l4xx_ll_adc.c
  • ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES : stm32l4xx_ll_adc.c
  • ADC_TR1_HT1_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32l4xx_hal_adc_ex.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32l4xx_hal_adc_ex.h
  • ADC_TRX_HIGHTHRESHOLD : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_10CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_11CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_12CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_1CYCLE : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_2CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_3CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_4CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_VREFINT_INSTANCE : stm32l4xx_hal_adc_ex.h
  • ADDR_1ST_CYCLE : stm32l4xx_hal_nand.h
  • ADDR_2ND_CYCLE : stm32l4xx_hal_nand.h
  • ADDR_3RD_CYCLE : stm32l4xx_hal_nand.h
  • ADDR_4TH_CYCLE : stm32l4xx_hal_nand.h
  • ADDR_AREA : stm32l4xx_hal_nand.h
  • ANALOG_MODE : stm32l4xx_hal_gpio.c
  • aRCC_APBAHBPrescTable : stm32l4xx_ll_rcc.h
  • ARRAY_ADDRESS : stm32l4xx_hal_nand.h
  • assert_param : stm32l4xx_ll_rng.c , stm32l4xx_ll_dac.c , stm32l4xx_ll_lpuart.c , stm32l4xx_ll_rcc.c , stm32l4xx_ll_crc.c , stm32l4xx_ll_lptim.c , stm32l4xx_ll_comp.c , stm32l4xx_ll_i2c.c , stm32l4xx_ll_spi.c , stm32l4xx_ll_utils.c , stm32l4xx_hal_conf.h , stm32l4xx_ll_swpmi.c , stm32l4xx_ll_usart.c , stm32l4xx_ll_tim.c , stm32l4xx_ll_exti.c , stm32l4xx_ll_dma.c , stm32l4xx_ll_opamp.c , stm32l4xx_ll_rtc.c , stm32l4xx_ll_gpio.c , stm32l4xx_ll_adc.c
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BDCR_REG_INDEX : stm32l4xx_hal_rcc.h
  • BDTR_BK2F_SHIFT : stm32l4xx_hal_tim_ex.c
  • BDTR_BKF_SHIFT : stm32l4xx_hal_tim_ex.c
  • BRER_BitNumber : stm32l4xx_hal.c
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
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  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CAN_BS1_10TQ : stm32l4xx_hal_can.h
  • CAN_BS1_11TQ : stm32l4xx_hal_can.h
  • CAN_BS1_12TQ : stm32l4xx_hal_can.h
  • CAN_BS1_13TQ : stm32l4xx_hal_can.h
  • CAN_BS1_14TQ : stm32l4xx_hal_can.h
  • CAN_BS1_15TQ : stm32l4xx_hal_can.h
  • CAN_BS1_16TQ : stm32l4xx_hal_can.h
  • CAN_BS1_1TQ : stm32l4xx_hal_can.h
  • CAN_BS1_2TQ : stm32l4xx_hal_can.h
  • CAN_BS1_3TQ : stm32l4xx_hal_can.h
  • CAN_BS1_4TQ : stm32l4xx_hal_can.h
  • CAN_BS1_5TQ : stm32l4xx_hal_can.h
  • CAN_BS1_6TQ : stm32l4xx_hal_can.h
  • CAN_BS1_7TQ : stm32l4xx_hal_can.h
  • CAN_BS1_8TQ : stm32l4xx_hal_can.h
  • CAN_BS1_9TQ : stm32l4xx_hal_can.h
  • CAN_BS2_1TQ : stm32l4xx_hal_can.h
  • CAN_BS2_2TQ : stm32l4xx_hal_can.h
  • CAN_BS2_3TQ : stm32l4xx_hal_can.h
  • CAN_BS2_4TQ : stm32l4xx_hal_can.h
  • CAN_BS2_5TQ : stm32l4xx_hal_can.h
  • CAN_BS2_6TQ : stm32l4xx_hal_can.h
  • CAN_BS2_7TQ : stm32l4xx_hal_can.h
  • CAN_BS2_8TQ : stm32l4xx_hal_can.h
  • CAN_FIFO0 : stm32l4xx_hal_can.h
  • CAN_FIFO1 : stm32l4xx_hal_can.h
  • CAN_FILTER_FIFO0 : stm32l4xx_hal_can.h
  • CAN_FILTER_FIFO1 : stm32l4xx_hal_can.h
  • CAN_FILTERMODE_IDLIST : stm32l4xx_hal_can.h
  • CAN_FILTERMODE_IDMASK : stm32l4xx_hal_can.h
  • CAN_FILTERSCALE_16BIT : stm32l4xx_hal_can.h
  • CAN_FILTERSCALE_32BIT : stm32l4xx_hal_can.h
  • CAN_FLAG_BOF : stm32l4xx_hal_can.h
  • CAN_FLAG_EPV : stm32l4xx_hal_can.h
  • CAN_FLAG_EWG : stm32l4xx_hal_can.h
  • CAN_FLAG_FF0 : stm32l4xx_hal_can.h
  • CAN_FLAG_FF1 : stm32l4xx_hal_can.h
  • CAN_FLAG_FOV0 : stm32l4xx_hal_can.h
  • CAN_FLAG_FOV1 : stm32l4xx_hal_can.h
  • CAN_FLAG_MASK : stm32l4xx_hal_can.h
  • CAN_FLAG_RQCP0 : stm32l4xx_hal_can.h
  • CAN_FLAG_RQCP1 : stm32l4xx_hal_can.h
  • CAN_FLAG_RQCP2 : stm32l4xx_hal_can.h
  • CAN_FLAG_SLAK : stm32l4xx_hal_can.h
  • CAN_FLAG_SLAKI : stm32l4xx_hal_can.h
  • CAN_FLAG_TME0 : stm32l4xx_hal_can.h
  • CAN_FLAG_TME1 : stm32l4xx_hal_can.h
  • CAN_FLAG_TME2 : stm32l4xx_hal_can.h
  • CAN_FLAG_TXOK0 : stm32l4xx_hal_can.h
  • CAN_FLAG_TXOK1 : stm32l4xx_hal_can.h
  • CAN_FLAG_TXOK2 : stm32l4xx_hal_can.h
  • CAN_FLAG_WKU : stm32l4xx_hal_can.h
  • CAN_ID_EXT : stm32l4xx_hal_can.h
  • CAN_ID_STD : stm32l4xx_hal_can.h
  • CAN_INITSTATUS_FAILED : stm32l4xx_hal_can.h
  • CAN_INITSTATUS_SUCCESS : stm32l4xx_hal_can.h
  • CAN_IT_BOF : stm32l4xx_hal_can.h
  • CAN_IT_EPV : stm32l4xx_hal_can.h
  • CAN_IT_ERR : stm32l4xx_hal_can.h
  • CAN_IT_EWG : stm32l4xx_hal_can.h
  • CAN_IT_FF0 : stm32l4xx_hal_can.h
  • CAN_IT_FF1 : stm32l4xx_hal_can.h
  • CAN_IT_FMP0 : stm32l4xx_hal_can.h
  • CAN_IT_FMP1 : stm32l4xx_hal_can.h
  • CAN_IT_FOV0 : stm32l4xx_hal_can.h
  • CAN_IT_FOV1 : stm32l4xx_hal_can.h
  • CAN_IT_LEC : stm32l4xx_hal_can.h
  • CAN_IT_SLK : stm32l4xx_hal_can.h
  • CAN_IT_TME : stm32l4xx_hal_can.h
  • CAN_IT_WKU : stm32l4xx_hal_can.h
  • CAN_MODE_LOOPBACK : stm32l4xx_hal_can.h
  • CAN_MODE_NORMAL : stm32l4xx_hal_can.h
  • CAN_MODE_SILENT : stm32l4xx_hal_can.h
  • CAN_MODE_SILENT_LOOPBACK : stm32l4xx_hal_can.h
  • CAN_Receive_IT() : stm32l4xx_hal_can.c
  • CAN_RTR_DATA : stm32l4xx_hal_can.h
  • CAN_RTR_REMOTE : stm32l4xx_hal_can.h
  • CAN_SJW_1TQ : stm32l4xx_hal_can.h
  • CAN_SJW_2TQ : stm32l4xx_hal_can.h
  • CAN_SJW_3TQ : stm32l4xx_hal_can.h
  • CAN_SJW_4TQ : stm32l4xx_hal_can.h
  • CAN_TIMEOUT_VALUE : stm32l4xx_hal_can.c
  • CAN_Transmit_IT() : stm32l4xx_hal_can.c
  • CAN_TXMAILBOX_0 : stm32l4xx_hal_can.h
  • CAN_TXMAILBOX_1 : stm32l4xx_hal_can.h
  • CAN_TXMAILBOX_2 : stm32l4xx_hal_can.h
  • CAN_TXSTATUS_NOMAILBOX : stm32l4xx_hal_can.h
  • CFI1_ADDRESS : stm32l4xx_hal_nor.h
  • CFI2_ADDRESS : stm32l4xx_hal_nor.h
  • CFI3_ADDRESS : stm32l4xx_hal_nor.h
  • CFI4_ADDRESS : stm32l4xx_hal_nor.h
  • CHANNEL_OFFSET_TAB : stm32l4xx_ll_dma.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • CMD_AREA : stm32l4xx_hal_nand.h
  • COMP_BLANKINGSRC_NONE : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC1_COMP2 : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP1 : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3_COMP1 : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP1 : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC4_COMP2 : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP2 : stm32l4xx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32l4xx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32l4xx_hal_comp.c
  • COMP_EXTI_EVENT : stm32l4xx_hal_comp.h
  • COMP_EXTI_FALLING : stm32l4xx_hal_comp.h
  • COMP_EXTI_IT : stm32l4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32l4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32l4xx_hal_comp.h
  • COMP_EXTI_RISING : stm32l4xx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32l4xx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32l4xx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32l4xx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32l4xx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH1 : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH2 : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32l4xx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32l4xx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32l4xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32l4xx_hal_comp.c
  • COMP_OUTPUT_LEVEL_HIGH : stm32l4xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32l4xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32l4xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32l4xx_hal_comp.h
  • COMP_POWERMODE_HIGHSPEED : stm32l4xx_hal_comp.h
  • COMP_POWERMODE_MEDIUMSPEED : stm32l4xx_hal_comp.h
  • COMP_POWERMODE_ULTRALOWPOWER : stm32l4xx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32l4xx_hal_comp.h
  • COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32l4xx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32l4xx_hal_comp.h
  • CR_REG_INDEX : stm32l4xx_hal_rcc.h
  • CRC_Handle_16() : stm32l4xx_hal_crc.c
  • CRC_Handle_8() : stm32l4xx_hal_crc.c
  • CRC_INPUTDATA_FORMAT_BYTES : stm32l4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32l4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32l4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32l4xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32l4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32l4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32l4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32l4xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32l4xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32l4xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32l4xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32l4xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32l4xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32l4xx_hal_crc.h
  • CRYP_AES_Auth_IT() : stm32l4xx_hal_cryp_ex.c
  • CRYP_AES_DISABLE : stm32l4xx_hal_cryp.h
  • CRYP_AES_ENABLE : stm32l4xx_hal_cryp.h
  • CRYP_AES_IT() : stm32l4xx_hal_cryp.c
  • CRYP_ALGOMODE_DECRYPT : stm32l4xx_hal_cryp.h
  • CRYP_ALGOMODE_ENCRYPT : stm32l4xx_hal_cryp.h
  • CRYP_ALGOMODE_KEYDERIVATION : stm32l4xx_hal_cryp.h
  • CRYP_ALGOMODE_KEYDERIVATION_DECRYPT : stm32l4xx_hal_cryp.h
  • CRYP_ALGOMODE_TAG_GENERATION : stm32l4xx_hal_cryp.h
  • CRYP_BUSY_TIMEOUTVALUE : stm32l4xx_hal_cryp_ex.c
  • CRYP_CCF_CLEAR : stm32l4xx_hal_cryp.h
  • CRYP_CCF_TIMEOUTVALUE : stm32l4xx_hal_cryp_ex.c
  • CRYP_CHAINMODE_AES_CBC : stm32l4xx_hal_cryp.h
  • CRYP_CHAINMODE_AES_CMAC : stm32l4xx_hal_cryp.h
  • CRYP_CHAINMODE_AES_CTR : stm32l4xx_hal_cryp.h
  • CRYP_CHAINMODE_AES_ECB : stm32l4xx_hal_cryp.h
  • CRYP_CHAINMODE_AES_GCM_GMAC : stm32l4xx_hal_cryp.h
  • CRYP_DATATYPE_16B : stm32l4xx_hal_cryp.h
  • CRYP_DATATYPE_1B : stm32l4xx_hal_cryp.h
  • CRYP_DATATYPE_32B : stm32l4xx_hal_cryp.h
  • CRYP_DATATYPE_8B : stm32l4xx_hal_cryp.h
  • CRYP_DMAError() : stm32l4xx_hal_cryp_ex.c
  • CRYP_DMAIN_DISABLE : stm32l4xx_hal_cryp.h
  • CRYP_DMAIN_ENABLE : stm32l4xx_hal_cryp.h
  • CRYP_DMAInCplt() : stm32l4xx_hal_cryp_ex.c
  • CRYP_DMAOUT_DISABLE : stm32l4xx_hal_cryp.h
  • CRYP_DMAOUT_ENABLE : stm32l4xx_hal_cryp.h
  • CRYP_DMAOutCplt() : stm32l4xx_hal_cryp_ex.c
  • CRYP_ERR_CLEAR : stm32l4xx_hal_cryp.h
  • CRYP_FLAG_BUSY : stm32l4xx_hal_cryp.h
  • CRYP_FLAG_CCF : stm32l4xx_hal_cryp.h
  • CRYP_FLAG_RDERR : stm32l4xx_hal_cryp.h
  • CRYP_FLAG_WRERR : stm32l4xx_hal_cryp.h
  • CRYP_GCM_INIT_PHASE : stm32l4xx_hal_cryp.h
  • CRYP_GCM_PAYLOAD_PHASE : stm32l4xx_hal_cryp.h
  • CRYP_GCMCMAC_DMAError() : stm32l4xx_hal_cryp_ex.c
  • CRYP_GCMCMAC_DMAInCplt() : stm32l4xx_hal_cryp_ex.c
  • CRYP_GCMCMAC_DMAOutCplt() : stm32l4xx_hal_cryp_ex.c
  • CRYP_GCMCMAC_FINAL_PHASE : stm32l4xx_hal_cryp.h
  • CRYP_GCMCMAC_HEADER_PHASE : stm32l4xx_hal_cryp.h
  • CRYP_GCMCMAC_SetDMAConfig() : stm32l4xx_hal_cryp_ex.c
  • CRYP_IT_CCF : stm32l4xx_hal_cryp.h
  • CRYP_IT_CCFIE : stm32l4xx_hal_cryp.h
  • CRYP_IT_ERRIE : stm32l4xx_hal_cryp.h
  • CRYP_IT_RDERR : stm32l4xx_hal_cryp.h
  • CRYP_IT_WRERR : stm32l4xx_hal_cryp.h
  • CRYP_KEY_WRITE_DISABLE : stm32l4xx_hal_cryp.h
  • CRYP_KEY_WRITE_ENABLE : stm32l4xx_hal_cryp.h
  • CRYP_KEYSIZE_128B : stm32l4xx_hal_cryp.h
  • CRYP_KEYSIZE_256B : stm32l4xx_hal_cryp.h
  • CRYP_Padding() : stm32l4xx_hal_cryp_ex.c
  • CRYP_POLLING_OFF : stm32l4xx_hal_cryp_ex.c
  • CRYP_POLLING_ON : stm32l4xx_hal_cryp_ex.c
  • CRYP_ProcessData() : stm32l4xx_hal_cryp_ex.c
  • CRYP_ReadKey() : stm32l4xx_hal_cryp_ex.c
  • CRYP_SetDMAConfig() : stm32l4xx_hal_cryp_ex.c
  • CRYP_SetInitVector() : stm32l4xx_hal_cryp.c
  • CRYP_SetKey() : stm32l4xx_hal_cryp.c
  • CRYP_WaitOnBusyFlagReset() : stm32l4xx_hal_cryp_ex.c
  • CRYP_WaitOnCCFlag() : stm32l4xx_hal_cryp_ex.c
  • CSR_REG_INDEX : stm32l4xx_hal_rcc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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  • Variables
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  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC_ALIGN_12B_L : stm32l4xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32l4xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32l4xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32l4xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32l4xx_hal_dac.h
  • DAC_CHIPCONNECT_DISABLE : stm32l4xx_hal_dac.h
  • DAC_CHIPCONNECT_ENABLE : stm32l4xx_hal_dac.h
  • DAC_CR_CH1_BITOFFSET : stm32l4xx_ll_dac.h
  • DAC_CR_CH2_BITOFFSET : stm32l4xx_ll_dac.h
  • DAC_CR_CHX_BITOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_DHR12LD_DACC2DHR_BITOFFSET_POS : stm32l4xx_ll_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32l4xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32l4xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32l4xx_hal_dac.h
  • DAC_DHR12RD_DACC2DHR_BITOFFSET_POS : stm32l4xx_ll_dac.h
  • DAC_DHR8RD_DACC2DHR_BITOFFSET_POS : stm32l4xx_ll_dac.h
  • DAC_DIGITAL_SCALE_12BITS : stm32l4xx_ll_dac.h
  • DAC_DMAConvCpltCh1() : stm32l4xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32l4xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32l4xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32l4xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32l4xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32l4xx_hal_dac_ex.c
  • DAC_FLAG_DMAUDR1 : stm32l4xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32l4xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32l4xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32l4xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32l4xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32l4xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32l4xx_hal_dac.h
  • DAC_REG_DHR12L1_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR12L2_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_REG_DHR12R1_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR12R2_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_REG_DHR8R1_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR8R2_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_REG_DHRX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_REG_DOR1_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DOR2_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_REG_SHSR1_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_SHSR2_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_SAMPLEANDHOLD_DISABLE : stm32l4xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_ENABLE : stm32l4xx_hal_dac.h
  • DAC_SWTR_CH1 : stm32l4xx_ll_dac.h
  • DAC_SWTR_CH2 : stm32l4xx_ll_dac.h
  • DAC_SWTR_CHX_MASK : stm32l4xx_ll_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T5_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIMMING_FACTORY : stm32l4xx_hal_dac.h
  • DAC_TRIMMING_USER : stm32l4xx_hal_dac.h
  • DATA_BLOCK_SIZE : stm32l4xx_hal_sd.c
  • DATA_CACHE_ENABLE : stm32l4xx_hal_conf.h
  • DBGMCU_REVID_POSITION : stm32l4xx_ll_system.h
  • DEFAULT_CRC32_POLY : stm32l4xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32l4xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32l4xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32l4xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32l4xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32l4xx_hal_crc.h
  • DEVICE_CODE1_ADDR : stm32l4xx_hal_nor.h
  • DEVICE_CODE2_ADDR : stm32l4xx_hal_nor.h
  • DEVICE_CODE3_ADDR : stm32l4xx_hal_nor.h
  • DFSDM1_CHANNEL_NUMBER : stm32l4xx_hal_dfsdm.c
  • DFSDM_AWD_HIGH_THRESHOLD : stm32l4xx_hal_dfsdm.h
  • DFSDM_AWD_LOW_THRESHOLD : stm32l4xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_0 : stm32l4xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_1 : stm32l4xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_2 : stm32l4xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_3 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_0 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_1 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_2 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_3 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_4 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_5 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_6 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_7 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_DUAL_MODE : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_EXTERNAL_INPUTS : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FASTSINC_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERLEAVED_MODE : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERNAL_REGISTER : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_FALLING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_RISING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SAME_CHANNEL_PINS : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC1_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC2_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC3_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_FALLING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_RISING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_STANDARD_MODE : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHAWSCDR_BKSCD_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_CHAWSCDR_FOSR_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_CHCFGR1_CLK_DIV_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_CHCFGR2_DTRBS_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_CHCFGR2_OFFSET_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_CKAB_TIMEOUT : stm32l4xx_hal_dfsdm.c
  • DFSDM_CONTINUOUS_CONV_OFF : stm32l4xx_hal_dfsdm.h
  • DFSDM_CONTINUOUS_CONV_ON : stm32l4xx_hal_dfsdm.h
  • DFSDM_DMAError() : stm32l4xx_hal_dfsdm.c
  • DFSDM_DMAInjectedConvCplt() : stm32l4xx_hal_dfsdm.c
  • DFSDM_DMAInjectedHalfConvCplt() : stm32l4xx_hal_dfsdm.c
  • DFSDM_DMARegularConvCplt() : stm32l4xx_hal_dfsdm.c
  • DFSDM_DMARegularHalfConvCplt() : stm32l4xx_hal_dfsdm.c
  • DFSDM_FILTER_AWD_CHANNEL_DATA : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_AWD_FILTER_DATA : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_DMA : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_INJECTED_OVERRUN : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_NONE : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_REGULAR_OVERRUN : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_BOTH_EDGES : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI11 : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI15 : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_FALLING_EDGE : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_RISING_EDGE : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM16_OC1 : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM3_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM4_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM6_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM7_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIGGER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_FASTSINC_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC1_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC2_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC3_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC4_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC5_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SW_TRIGGER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SYNC_TRIGGER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FLTAWHTR_THRESHOLD_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTAWLTR_THRESHOLD_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTAWSR_HIGH_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTCNVTIMR_DATA_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTCR1_MSB_RCH_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTCR2_AWDCH_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTCR2_EXCH_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTEXMAX_DATA_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTEXMIN_DATA_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTFCR_FOSR_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTICR_CLRCKABF_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTICR_CLRSCDF_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTISR_CKABF_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTISR_SCDF_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTJDATAR_DATA_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTRDATAR_DATA_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_GetChannelFromInstance() : stm32l4xx_hal_dfsdm.c
  • DFSDM_GetInjChannelsNbr() : stm32l4xx_hal_dfsdm.c
  • DFSDM_InjConvStart() : stm32l4xx_hal_dfsdm.c
  • DFSDM_InjConvStop() : stm32l4xx_hal_dfsdm.c
  • DFSDM_LSB_MASK : stm32l4xx_hal_dfsdm.c
  • DFSDM_MSB_MASK : stm32l4xx_hal_dfsdm.c
  • DFSDM_NO_BREAK_SIGNAL : stm32l4xx_hal_dfsdm.h
  • DFSDM_RegConvStart() : stm32l4xx_hal_dfsdm.c
  • DFSDM_RegConvStop() : stm32l4xx_hal_dfsdm.c
  • DIVIDER_P_UPDATE : stm32l4xx_hal_rcc_ex.c
  • DIVIDER_Q_UPDATE : stm32l4xx_hal_rcc_ex.c
  • DIVIDER_R_UPDATE : stm32l4xx_hal_rcc_ex.c
  • DMA_CIRCULAR : stm32l4xx_hal_dma.h
  • DMA_CSELR_OFFSET : stm32l4xx_ll_dma.h
  • DMA_FLAG_GL1 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL2 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL3 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL4 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL5 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL6 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL7 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT1 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT2 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT3 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT4 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT5 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT6 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT7 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC1 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC2 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC3 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC4 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC5 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC6 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC7 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE1 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE2 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE3 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE4 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE5 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE6 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE7 : stm32l4xx_hal_dma.h
  • DMA_HandleTypeDef : stm32l4xx_hal_dma.h
  • DMA_IT_HT : stm32l4xx_hal_dma.h
  • DMA_IT_TC : stm32l4xx_hal_dma.h
  • DMA_IT_TE : stm32l4xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32l4xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32l4xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32l4xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32l4xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32l4xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32l4xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32l4xx_hal_dma.h
  • DMA_NORMAL : stm32l4xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32l4xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32l4xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32l4xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32l4xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32l4xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32l4xx_hal_dma.h
  • DMA_POSITION_CSELR_CXS : stm32l4xx_ll_dma.h
  • DMA_PRIORITY_HIGH : stm32l4xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32l4xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32l4xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32l4xx_hal_dma.h
  • DMA_REQUEST_0 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_1 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_2 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_3 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_4 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_5 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_6 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_7 : stm32l4xx_hal_dma.h
  • DMA_SetConfig() : stm32l4xx_hal_dma.c
  • DT_DELAY_1 : stm32l4xx_ll_tim.h
  • DT_DELAY_2 : stm32l4xx_ll_tim.h
  • DT_DELAY_3 : stm32l4xx_ll_tim.h
  • DT_DELAY_4 : stm32l4xx_ll_tim.h
  • DT_RANGE_1 : stm32l4xx_ll_tim.h
  • DT_RANGE_2 : stm32l4xx_ll_tim.h
  • DT_RANGE_3 : stm32l4xx_ll_tim.h
  • DT_RANGE_4 : stm32l4xx_ll_tim.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • EXTERNAL_SAI1_CLOCK_VALUE : stm32l4xx_hal_conf.h
  • EXTERNAL_SAI2_CLOCK_VALUE : stm32l4xx_hal_conf.h
  • EXTI_MODE : stm32l4xx_hal_gpio.c
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • a
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  • f
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALLING_EDGE : stm32l4xx_hal_gpio.c
  • FB_MODE_BB : stm32l4xx_hal.c
  • FB_MODE_BitNumber : stm32l4xx_hal.c
  • FIREWALL_PRE_ARM_RESET : stm32l4xx_hal_firewall.h
  • FIREWALL_PRE_ARM_SET : stm32l4xx_hal_firewall.h
  • FIREWALL_VOLATILEDATA_EXECUTABLE : stm32l4xx_hal_firewall.h
  • FIREWALL_VOLATILEDATA_NOT_EXECUTABLE : stm32l4xx_hal_firewall.h
  • FIREWALL_VOLATILEDATA_NOT_SHARED : stm32l4xx_hal_firewall.h
  • FIREWALL_VOLATILEDATA_SHARED : stm32l4xx_hal_firewall.h
  • FLASH_BANK_1 : stm32l4xx_hal_flash.h
  • FLASH_BANK_2 : stm32l4xx_hal_flash.h
  • FLASH_BANK_BOTH : stm32l4xx_hal_flash.h
  • FLASH_BANK_SIZE : stm32l4xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS : stm32l4xx_hal_flash.h
  • FLASH_FLAG_BSY : stm32l4xx_hal_flash.h
  • FLASH_FLAG_ECCC : stm32l4xx_hal_flash.h
  • FLASH_FLAG_ECCD : stm32l4xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32l4xx_hal_flash.h
  • FLASH_FLAG_FASTERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_MISERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_OPTVERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_PROGERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_RDERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_SIZERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32l4xx_hal_flash.h
  • FLASH_FlushCaches() : stm32l4xx_hal_flash.c , stm32l4xx_hal_flash_ex.c
  • FLASH_IT_ECCC : stm32l4xx_hal_flash.h
  • FLASH_IT_EOP : stm32l4xx_hal_flash.h
  • FLASH_IT_OPERR : stm32l4xx_hal_flash.h
  • FLASH_IT_RDERR : stm32l4xx_hal_flash.h
  • FLASH_KEY1 : stm32l4xx_hal_flash.h
  • FLASH_KEY2 : stm32l4xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32l4xx_hal_flash.h
  • FLASH_LATENCY_1 : stm32l4xx_hal_flash.h
  • FLASH_LATENCY_2 : stm32l4xx_hal_flash.h
  • FLASH_LATENCY_3 : stm32l4xx_hal_flash.h
  • FLASH_LATENCY_4 : stm32l4xx_hal_flash.h
  • FLASH_MassErase() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_PCROPConfig() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_RDPConfig() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_WRPConfig() : stm32l4xx_hal_flash_ex.c
  • FLASH_OPTKEY1 : stm32l4xx_hal_flash.h
  • FLASH_OPTKEY2 : stm32l4xx_hal_flash.h
  • FLASH_PAGE_SIZE : stm32l4xx_hal_flash.h
  • FLASH_PageErase() : stm32l4xx_hal_flash_ex.c , stm32l4xx_hal_flash.c
  • FLASH_PDKEY1 : stm32l4xx_ll_system.h , stm32l4xx_hal_flash.h
  • FLASH_PDKEY2 : stm32l4xx_ll_system.h , stm32l4xx_hal_flash.h
  • FLASH_PROC_MASS_ERASE : stm32l4xx_hal_flash.h
  • FLASH_PROC_NONE : stm32l4xx_hal_flash.h
  • FLASH_PROC_PAGE_ERASE : stm32l4xx_hal_flash.h
  • FLASH_PROC_PROGRAM : stm32l4xx_hal_flash.h
  • FLASH_PROC_PROGRAM_LAST : stm32l4xx_hal_flash.h
  • FLASH_ProcedureTypeDef : stm32l4xx_hal_flash.h
  • FLASH_Program_DoubleWord() : stm32l4xx_hal_flash.c
  • FLASH_Program_Fast() : stm32l4xx_hal_flash.c
  • FLASH_SetErrorCode() : stm32l4xx_hal_flash.c
  • FLASH_SIZE : stm32l4xx_hal_flash.h
  • FLASH_SIZE_DATA_REGISTER : stm32l4xx_hal_flash.h
  • FLASH_TIMEOUT_VALUE : stm32l4xx_hal_flash.h
  • FLASH_TYPEERASE_MASSERASE : stm32l4xx_hal_flash.h
  • FLASH_TYPEERASE_PAGES : stm32l4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32l4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST : stm32l4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST_AND_LAST : stm32l4xx_hal_flash.h
  • FLASH_WaitForLastOperation() : stm32l4xx_hal_flash.c , stm32l4xx_hal_flash_ex.c
  • FLASHSIZE_BASE_ADDRESS : stm32l4xx_ll_utils.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • Defines
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GPIO_AF0_LCDBIAS : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF0_MCO : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF10_OTG_FS : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF10_QUADSPI : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF11_LCD : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF12_COMP1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF12_COMP2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF12_FMC : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF12_SDMMC1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF12_SWPMI1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF13_SAI1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF13_SAI2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF13_TIM8_COMP1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF13_TIM8_COMP2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_LPTIM2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM15 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM16 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM17 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM8_COMP1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_IR : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM5 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM8 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM1_COMP1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM1_COMP2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM8 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF6_DFSDM1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF8_LPUART1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF8_UART4 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF8_UART5 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF9_CAN1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF9_TSC : stm32l4xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32l4xx_hal_gpio_ex.h
  • GPIO_MODE : stm32l4xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32l4xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32l4xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32l4xx_hal_gpio.h
  • GPIO_MODE_ANALOG_ADC_CONTROL : stm32l4xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32l4xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32l4xx_hal_gpio.h
  • GPIO_MODE_IT : stm32l4xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32l4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32l4xx_hal_gpio.h
  • GPIO_NOPULL : stm32l4xx_hal_gpio.h
  • GPIO_NUMBER : stm32l4xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32l4xx_hal_gpio.c
  • GPIO_PIN_0 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_1 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_10 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_11 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_12 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_13 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_14 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_15 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_2 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_3 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_4 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_5 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_6 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_7 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_8 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_9 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_All : stm32l4xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32l4xx_hal_gpio.h
  • GPIO_PIN_RESET : stm32l4xx_hal_gpio.h
  • GPIO_PIN_SET : stm32l4xx_hal_gpio.h
  • GPIO_PinState : stm32l4xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32l4xx_hal_gpio.h
  • GPIO_PULLUP : stm32l4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32l4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32l4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32l4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32l4xx_hal_gpio.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32l4xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32l4xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32l4xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32l4xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32l4xx_hal_adc.c
  • HAL_ADC_ERROR_DMA : stm32l4xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32l4xx_hal_adc.h
  • HAL_ADC_ERROR_JQOVF : stm32l4xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32l4xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32l4xx_hal_adc.h
  • HAL_ADC_ErrorCallback() : stm32l4xx_hal_adc.c
  • HAL_ADC_GetError() : stm32l4xx_hal_adc.c
  • HAL_ADC_GetState() : stm32l4xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32l4xx_hal_adc.c
  • HAL_ADC_Init() : stm32l4xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32l4xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32l4xx_hal_adc.c
  • HAL_ADC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_ADC_MspDeInit() : stm32l4xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32l4xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32l4xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32l4xx_hal_adc.c
  • HAL_ADC_Start() : stm32l4xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32l4xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32l4xx_hal_adc.c
  • HAL_ADC_STATE_AWD1 : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32l4xx_hal_adc.h
  • HAL_ADC_Stop() : stm32l4xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32l4xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32l4xx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_DisableInjectedQueue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_EnableInjectedQueue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_EndOfSamplingCallback() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_EnterADCDeepPowerDownMode() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedQueueOverflowCallback() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularMultiModeStop_DMA() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_DMA() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_IT() : stm32l4xx_hal_adc_ex.c
  • HAL_CAN_ConfigFilter() : stm32l4xx_hal_can.c
  • HAL_CAN_DeInit() : stm32l4xx_hal_can.c
  • HAL_CAN_ERROR_ACK : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_BD : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_BOF : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_BR : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_CRC : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_EPV : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_EWG : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_FOR : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_NONE : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_STF : stm32l4xx_hal_can.h
  • HAL_CAN_ErrorCallback() : stm32l4xx_hal_can.c
  • HAL_CAN_GetError() : stm32l4xx_hal_can.c
  • HAL_CAN_GetState() : stm32l4xx_hal_can.c
  • HAL_CAN_Init() : stm32l4xx_hal_can.c
  • HAL_CAN_IRQHandler() : stm32l4xx_hal_can.c
  • HAL_CAN_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_CAN_MspDeInit() : stm32l4xx_hal_can.c
  • HAL_CAN_MspInit() : stm32l4xx_hal_can.c
  • HAL_CAN_Receive() : stm32l4xx_hal_can.c
  • HAL_CAN_Receive_IT() : stm32l4xx_hal_can.c
  • HAL_CAN_RxCpltCallback() : stm32l4xx_hal_can.c
  • HAL_CAN_Sleep() : stm32l4xx_hal_can.c
  • HAL_CAN_STATE_BUSY : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_ERROR : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_READY : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_RESET : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_TIMEOUT : stm32l4xx_hal_can.h
  • HAL_CAN_StateTypeDef : stm32l4xx_hal_can.h
  • HAL_CAN_Transmit() : stm32l4xx_hal_can.c
  • HAL_CAN_Transmit_IT() : stm32l4xx_hal_can.c
  • HAL_CAN_TxCpltCallback() : stm32l4xx_hal_can.c
  • HAL_CAN_WakeUp() : stm32l4xx_hal_can.c
  • HAL_COMP_DeInit() : stm32l4xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32l4xx_hal_comp.c
  • HAL_COMP_GetState() : stm32l4xx_hal_comp.c
  • HAL_COMP_Init() : stm32l4xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32l4xx_hal_comp.c
  • HAL_COMP_Lock() : stm32l4xx_hal_comp.c
  • HAL_COMP_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_COMP_MspDeInit() : stm32l4xx_hal_comp.c
  • HAL_COMP_MspInit() : stm32l4xx_hal_comp.c
  • HAL_COMP_Start() : stm32l4xx_hal_comp.c
  • HAL_COMP_STATE_BUSY : stm32l4xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32l4xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32l4xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32l4xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32l4xx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32l4xx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32l4xx_hal_comp.h
  • HAL_COMP_Stop() : stm32l4xx_hal_comp.c
  • HAL_COMP_TriggerCallback() : stm32l4xx_hal_comp.c
  • HAL_CORTEX_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_CRC_Accumulate() : stm32l4xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32l4xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32l4xx_hal_crc.c
  • HAL_CRC_GetState() : stm32l4xx_hal_crc.c
  • HAL_CRC_Init() : stm32l4xx_hal_crc.c
  • HAL_CRC_Input_Data_Reverse : stm32l4xx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32l4xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32l4xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32l4xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32l4xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_CRC_MspDeInit() : stm32l4xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32l4xx_hal_crc.c
  • HAL_CRC_Output_Data_Reverse : stm32l4xx_hal_crc.h
  • HAL_CRC_STATE_BUSY : stm32l4xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32l4xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32l4xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32l4xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32l4xx_hal_crc.h
  • HAL_CRC_StateTypeDef : stm32l4xx_hal_crc.h
  • HAL_CRCEx_Input_Data_Reverse() : stm32l4xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32l4xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32l4xx_hal_crc_ex.c
  • HAL_CRYP_AESCBC_Decrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCBC_Decrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCBC_Decrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCBC_Encrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCBC_Encrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCBC_Encrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Decrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Decrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Decrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Encrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Encrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Encrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Decrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Decrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Decrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Encrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Encrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Encrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_BUSY_ERROR : stm32l4xx_hal_cryp.h
  • HAL_CRYP_DeInit() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_DMA_ERROR : stm32l4xx_hal_cryp.h
  • HAL_CRYP_ERROR_NONE : stm32l4xx_hal_cryp.h
  • HAL_CRYP_ErrorCallback() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_GetError() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_GetState() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_InCpltCallback() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_Init() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_IRQHandler() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_CRYP_MspDeInit() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_MspInit() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_OutCpltCallback() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_PHASE_FINAL_OVER : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_HEADER_OVER : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_HEADER_SUSPENDED : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_INIT_OVER : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_NOT_USED : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_PAYLOAD_OVER : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_PAYLOAD_SUSPENDED : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_PROCESS : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_READY : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_START : stm32l4xx_hal_cryp.h
  • HAL_CRYP_READ_ERROR : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_BUSY : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_ERROR : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_READY : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_RESET : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_SUSPENDED : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_TIMEOUT : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATETypeDef : stm32l4xx_hal_cryp.h
  • HAL_CRYP_SUSPEND : stm32l4xx_hal_cryp.h
  • HAL_CRYP_SUSPEND_NONE : stm32l4xx_hal_cryp.h
  • HAL_CRYP_WRITE_ERROR : stm32l4xx_hal_cryp.h
  • HAL_CRYPEx_AES() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_AES_Auth() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_AES_Auth_DMA() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_AES_Auth_IT() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_AES_DMA() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_AES_IT() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_ComputationCpltCallback() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_ProcessSuspend() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Read_ControlRegister() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Read_IVRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Read_KeyRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Read_SuspendRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Write_ControlRegister() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Write_IVRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Write_KeyRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Write_SuspendRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_DAC_ConfigChannel() : stm32l4xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32l4xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32l4xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32l4xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32l4xx_hal_dac.c
  • HAL_DAC_ERROR_DMA : stm32l4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32l4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32l4xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32l4xx_hal_dac.h
  • HAL_DAC_ERROR_TIMEOUT : stm32l4xx_hal_dac.h
  • HAL_DAC_ErrorCallbackCh1() : stm32l4xx_hal_dac.c
  • HAL_DAC_GetError() : stm32l4xx_hal_dac.c
  • HAL_DAC_GetState() : stm32l4xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32l4xx_hal_dac.c
  • HAL_DAC_Init() : stm32l4xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32l4xx_hal_dac.c
  • HAL_DAC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_DAC_MspDeInit() : stm32l4xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32l4xx_hal_dac.c
  • HAL_DAC_SetValue() : stm32l4xx_hal_dac.c
  • HAL_DAC_Start() : stm32l4xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32l4xx_hal_dac.c
  • HAL_DAC_STATE_BUSY : stm32l4xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32l4xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32l4xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32l4xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32l4xx_hal_dac.h
  • HAL_DAC_StateTypeDef : stm32l4xx_hal_dac.h
  • HAL_DAC_Stop() : stm32l4xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32l4xx_hal_dac.c
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_DualSetValue() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_GetTrimOffset() : stm32l4xx_hal_dac_ex.c , stm32l4xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_SelfCalibrate() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_SetUserTrimming() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_TriangleWaveGenerate() : stm32l4xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32l4xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32l4xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32l4xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32l4xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32l4xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32l4xx_hal.c
  • HAL_DeInit() : stm32l4xx_hal.c
  • HAL_Delay() : stm32l4xx_hal.c
  • HAL_DFSDM_CHANNEL_STATE_ERROR : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_READY : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_RESET : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_Channel_StateTypeDef : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_ChannelCkabCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelDeInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetAwdValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetState() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelModifyOffset() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspDeInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForCkab() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForScd() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FILTER_STATE_ERROR : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_INJ : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_READY : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG_INJ : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_RESET : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_Filter_StateTypeDef : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FilterAwdCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStart_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStop_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigInjChannel() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigRegChannel() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterDeInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterErrorCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStart() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStop() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetConvTimeValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetError() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMaxValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMinValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetInjectedValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetRegularValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetState() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvCpltCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvHalfCpltCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedMsbStart_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspDeInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForInjConversion() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForRegConversion() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvCpltCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvHalfCpltCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularMsbStart_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_IRQHandler() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_DMA_Abort() : stm32l4xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32l4xx_hal_dma.c
  • HAL_DMA_CallbackIDTypeDef : stm32l4xx_hal_dma.h
  • HAL_DMA_DeInit() : stm32l4xx_hal_dma.c
  • HAL_DMA_ERROR_NO_XFER : stm32l4xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32l4xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32l4xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32l4xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32l4xx_hal_dma.h
  • HAL_DMA_FULL_TRANSFER : stm32l4xx_hal_dma.h
  • HAL_DMA_GetError() : stm32l4xx_hal_dma.c
  • HAL_DMA_GetState() : stm32l4xx_hal_dma.c
  • HAL_DMA_HALF_TRANSFER : stm32l4xx_hal_dma.h
  • HAL_DMA_Init() : stm32l4xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32l4xx_hal_dma.c
  • HAL_DMA_LevelCompleteTypeDef : stm32l4xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_DMA_PollForTransfer() : stm32l4xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32l4xx_hal_dma.c
  • HAL_DMA_Start() : stm32l4xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32l4xx_hal_dma.c
  • HAL_DMA_STATE_BUSY : stm32l4xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32l4xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32l4xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32l4xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32l4xx_hal_dma.h
  • HAL_DMA_UnRegisterCallback() : stm32l4xx_hal_dma.c
  • HAL_DMA_XFER_ABORT_CB_ID : stm32l4xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32l4xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32l4xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32l4xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32l4xx_hal_dma.h
  • HAL_FIREWALL_Config() : stm32l4xx_hal_firewall.c
  • HAL_FIREWALL_DisablePreArmFlag() : stm32l4xx_hal_firewall.c
  • HAL_FIREWALL_EnableFirewall() : stm32l4xx_hal_firewall.c
  • HAL_FIREWALL_EnablePreArmFlag() : stm32l4xx_hal_firewall.c
  • HAL_FIREWALL_GetConfig() : stm32l4xx_hal_firewall.c
  • HAL_FIREWALL_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_FLASH_EndOfOperationCallback() : stm32l4xx_hal_flash.c
  • HAL_FLASH_ERROR_ECCD : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_FAST : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_MIS : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_OP : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_OPTV : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_RD : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_SIZ : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32l4xx_hal_flash.h
  • HAL_FLASH_GetError() : stm32l4xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32l4xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32l4xx_hal_flash.c
  • HAL_FLASH_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_FLASH_OB_Launch() : stm32l4xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32l4xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32l4xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32l4xx_hal_flash.c
  • HAL_FLASH_Program() : stm32l4xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32l4xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32l4xx_hal_flash.c
  • HAL_FLASHEx_DisableRunPowerDown() : stm32l4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_EnableRunPowerDown() : stm32l4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_Erase() : stm32l4xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32l4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32l4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32l4xx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32l4xx_hal.c
  • HAL_GetHalVersion() : stm32l4xx_hal.c
  • HAL_GetREVID() : stm32l4xx_hal.c
  • HAL_GetTick() : stm32l4xx_hal.c
  • HAL_GPIO_DeInit() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_GPIO_ReadPin() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32l4xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32l4xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32l4xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32l4xx_hal_uart.c
  • HAL_HCD_Connect_Callback() : stm32l4xx_hal_hcd.c
  • HAL_HCD_DeInit() : stm32l4xx_hal_hcd.c
  • HAL_HCD_Disconnect_Callback() : stm32l4xx_hal_hcd.c
  • HAL_HCD_GetCurrentFrame() : stm32l4xx_hal_hcd.c
  • HAL_HCD_GetCurrentSpeed() : stm32l4xx_hal_hcd.c
  • HAL_HCD_GetState() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_GetState() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_GetURBState() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_GetXferCount() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_Halt() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_Init() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_NotifyURBChange_Callback() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_SubmitRequest() : stm32l4xx_hal_hcd.c
  • HAL_HCD_Init() : stm32l4xx_hal_hcd.c
  • HAL_HCD_IRQHandler() : stm32l4xx_hal_hcd.c
  • HAL_HCD_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_HCD_MspDeInit() : stm32l4xx_hal_hcd.c
  • HAL_HCD_MspInit() : stm32l4xx_hal_hcd.c
  • HAL_HCD_ResetPort() : stm32l4xx_hal_hcd.c
  • HAL_HCD_SOF_Callback() : stm32l4xx_hal_hcd.c
  • HAL_HCD_Start() : stm32l4xx_hal_hcd.c
  • HAL_HCD_STATE_BUSY : stm32l4xx_hal_hcd.h
  • HAL_HCD_STATE_ERROR : stm32l4xx_hal_hcd.h
  • HAL_HCD_STATE_READY : stm32l4xx_hal_hcd.h
  • HAL_HCD_STATE_RESET : stm32l4xx_hal_hcd.h
  • HAL_HCD_STATE_TIMEOUT : stm32l4xx_hal_hcd.h
  • HAL_HCD_Stop() : stm32l4xx_hal_hcd.c
  • HAL_I2C_AbortCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32l4xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32l4xx_hal_i2c.c
  • HAL_I2C_ERROR_AF : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32l4xx_hal_i2c.h
  • HAL_I2C_ErrorCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32l4xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32l4xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32l4xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Init() : stm32l4xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32l4xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Receive_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Transmit_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MODE_MASTER : stm32l4xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32l4xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32l4xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32l4xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32l4xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_I2C_MspDeInit() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Receive_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Transmit_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_STATE_ABORT : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32l4xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32l4xx_hal_i2c.h
  • HAL_I2CEx_ConfigAnalogFilter() : stm32l4xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32l4xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32l4xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32l4xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32l4xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32l4xx_hal_i2c_ex.c
  • HAL_IncTick() : stm32l4xx_hal.c
  • HAL_Init() : stm32l4xx_hal.c
  • HAL_InitTick() : stm32l4xx_hal.c
  • HAL_IRDA_DeInit() : stm32l4xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32l4xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32l4xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32l4xx_hal_irda.c
  • HAL_IRDA_ERROR_DMA : stm32l4xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32l4xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32l4xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32l4xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32l4xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32l4xx_hal_irda.h
  • HAL_IRDA_ErrorCallback() : stm32l4xx_hal_irda.c
  • HAL_IRDA_ErrorTypeDef : stm32l4xx_hal_irda.h
  • HAL_IRDA_GetError() : stm32l4xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Init() : stm32l4xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32l4xx_hal_irda.c
  • HAL_IRDA_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_IRDA_MspDeInit() : stm32l4xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32l4xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32l4xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32l4xx_hal_irda.c
  • HAL_IRDA_STATE_BUSY : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32l4xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32l4xx_hal_irda.h
  • HAL_IRDA_Transmit() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32l4xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32l4xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32l4xx_hal_irda.c
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32l4xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32l4xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_IWDG_Refresh() : stm32l4xx_hal_iwdg.c
  • HAL_LCD_Clear() : stm32l4xx_hal_lcd.c
  • HAL_LCD_DeInit() : stm32l4xx_hal_lcd.c
  • HAL_LCD_ERROR_ENS : stm32l4xx_hal_lcd.h
  • HAL_LCD_ERROR_FCRSF : stm32l4xx_hal_lcd.h
  • HAL_LCD_ERROR_NONE : stm32l4xx_hal_lcd.h
  • HAL_LCD_ERROR_RDY : stm32l4xx_hal_lcd.h
  • HAL_LCD_ERROR_UDD : stm32l4xx_hal_lcd.h
  • HAL_LCD_ERROR_UDR : stm32l4xx_hal_lcd.h
  • HAL_LCD_GetError() : stm32l4xx_hal_lcd.c
  • HAL_LCD_GetState() : stm32l4xx_hal_lcd.c
  • HAL_LCD_Init() : stm32l4xx_hal_lcd.c
  • HAL_LCD_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_LCD_MspDeInit() : stm32l4xx_hal_lcd.c
  • HAL_LCD_MspInit() : stm32l4xx_hal_lcd.c
  • HAL_LCD_STATE_BUSY : stm32l4xx_hal_lcd.h
  • HAL_LCD_STATE_ERROR : stm32l4xx_hal_lcd.h
  • HAL_LCD_STATE_READY : stm32l4xx_hal_lcd.h
  • HAL_LCD_STATE_RESET : stm32l4xx_hal_lcd.h
  • HAL_LCD_STATE_TIMEOUT : stm32l4xx_hal_lcd.h
  • HAL_LCD_StateTypeDef : stm32l4xx_hal_lcd.h
  • HAL_LCD_UpdateDisplayRequest() : stm32l4xx_hal_lcd.c
  • HAL_LCD_Write() : stm32l4xx_hal_lcd.c
  • HAL_LIN_Init() : stm32l4xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32l4xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_CompareWriteCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_DeInit() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_DirectionUpCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_GetState() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Init() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_IRQHandler() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_LPTIM_MspDeInit() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_ReadAutoReload() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_ReadCompare() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_ReadCounter() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_STATE_BUSY : stm32l4xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32l4xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32l4xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32l4xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32l4xx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32l4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_MPU_ConfigRegion() : stm32l4xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32l4xx_hal_cortex.h
  • HAL_MPU_Enable() : stm32l4xx_hal_cortex.h
  • HAL_MspDeInit() : stm32l4xx_hal.c
  • HAL_MspInit() : stm32l4xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32l4xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32l4xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32l4xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32l4xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32l4xx_hal_uart_ex.c
  • HAL_NAND_Address_Inc() : stm32l4xx_hal_nand.c
  • HAL_NAND_DeInit() : stm32l4xx_hal_nand.c
  • HAL_NAND_ECC_Disable() : stm32l4xx_hal_nand.c
  • HAL_NAND_ECC_Enable() : stm32l4xx_hal_nand.c
  • HAL_NAND_Erase_Block() : stm32l4xx_hal_nand.c
  • HAL_NAND_GetECC() : stm32l4xx_hal_nand.c
  • HAL_NAND_GetState() : stm32l4xx_hal_nand.c
  • HAL_NAND_Init() : stm32l4xx_hal_nand.c
  • HAL_NAND_IRQHandler() : stm32l4xx_hal_nand.c
  • HAL_NAND_ITCallback() : stm32l4xx_hal_nand.c
  • HAL_NAND_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_NAND_MspDeInit() : stm32l4xx_hal_nand.c
  • HAL_NAND_MspInit() : stm32l4xx_hal_nand.c
  • HAL_NAND_Read_ID() : stm32l4xx_hal_nand.c
  • HAL_NAND_Read_Page() : stm32l4xx_hal_nand.c
  • HAL_NAND_Read_SpareArea() : stm32l4xx_hal_nand.c
  • HAL_NAND_Read_Status() : stm32l4xx_hal_nand.c , stm32l4xx_hal_nand.h
  • HAL_NAND_Reset() : stm32l4xx_hal_nand.c
  • HAL_NAND_STATE_BUSY : stm32l4xx_hal_nand.h
  • HAL_NAND_STATE_ERROR : stm32l4xx_hal_nand.h
  • HAL_NAND_STATE_READY : stm32l4xx_hal_nand.h
  • HAL_NAND_STATE_RESET : stm32l4xx_hal_nand.h
  • HAL_NAND_StateTypeDef : stm32l4xx_hal_nand.h
  • HAL_NAND_Write_Page() : stm32l4xx_hal_nand.c
  • HAL_NAND_Write_SpareArea() : stm32l4xx_hal_nand.c
  • HAL_NOR_DeInit() : stm32l4xx_hal_nor.c
  • HAL_NOR_Erase_Block() : stm32l4xx_hal_nor.c
  • HAL_NOR_Erase_Chip() : stm32l4xx_hal_nor.c
  • HAL_NOR_GetState() : stm32l4xx_hal_nor.c
  • HAL_NOR_GetStatus() : stm32l4xx_hal_nor.c
  • HAL_NOR_Init() : stm32l4xx_hal_nor.c
  • HAL_NOR_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_NOR_MspDeInit() : stm32l4xx_hal_nor.c
  • HAL_NOR_MspInit() : stm32l4xx_hal_nor.c
  • HAL_NOR_MspWait() : stm32l4xx_hal_nor.c
  • HAL_NOR_Program() : stm32l4xx_hal_nor.c
  • HAL_NOR_ProgramBuffer() : stm32l4xx_hal_nor.c
  • HAL_NOR_Read() : stm32l4xx_hal_nor.c
  • HAL_NOR_Read_CFI() : stm32l4xx_hal_nor.c
  • HAL_NOR_Read_ID() : stm32l4xx_hal_nor.c
  • HAL_NOR_ReadBuffer() : stm32l4xx_hal_nor.c
  • HAL_NOR_ReturnToReadMode() : stm32l4xx_hal_nor.c
  • HAL_NOR_STATE_BUSY : stm32l4xx_hal_nor.h
  • HAL_NOR_STATE_ERROR : stm32l4xx_hal_nor.h
  • HAL_NOR_STATE_PROTECTED : stm32l4xx_hal_nor.h
  • HAL_NOR_STATE_READY : stm32l4xx_hal_nor.h
  • HAL_NOR_STATE_RESET : stm32l4xx_hal_nor.h
  • HAL_NOR_StateTypeDef : stm32l4xx_hal_nor.h
  • HAL_NOR_STATUS_ERROR : stm32l4xx_hal_nor.h
  • HAL_NOR_STATUS_ONGOING : stm32l4xx_hal_nor.h
  • HAL_NOR_STATUS_SUCCESS : stm32l4xx_hal_nor.h
  • HAL_NOR_STATUS_TIMEOUT : stm32l4xx_hal_nor.h
  • HAL_NOR_StatusTypeDef : stm32l4xx_hal_nor.h
  • HAL_NOR_WriteOperation_Disable() : stm32l4xx_hal_nor.c
  • HAL_NOR_WriteOperation_Enable() : stm32l4xx_hal_nor.c
  • HAL_NVIC_ClearPendingIRQ() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32l4xx_hal_cortex.c
  • HAL_OPAMP_DeInit() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_GetState() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_GetTrimOffset() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_Init() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_Lock() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_OPAMP_MspDeInit() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_MspInit() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_SelfCalibrate() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_Start() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_STATE_BUSY : stm32l4xx_hal_opamp.h
  • HAL_OPAMP_STATE_BUSYLOCKED : stm32l4xx_hal_opamp.h
  • HAL_OPAMP_STATE_CALIBBUSY : stm32l4xx_hal_opamp.h
  • HAL_OPAMP_STATE_READY : stm32l4xx_hal_opamp.h
  • HAL_OPAMP_STATE_RESET : stm32l4xx_hal_opamp.h
  • HAL_OPAMP_StateTypeDef : stm32l4xx_hal_opamp.h
  • HAL_OPAMP_Stop() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_TrimmingValueTypeDef : stm32l4xx_hal_opamp.h
  • HAL_OPAMPEx_SelfCalibrateAll() : stm32l4xx_hal_opamp_ex.c , stm32l4xx_hal_opamp_ex.h
  • HAL_OPAMPEx_Unlock() : stm32l4xx_hal_opamp_ex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32l4xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32l4xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32l4xx_hal_pcd.c
  • HAL_PCD_Init() : stm32l4xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32l4xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_PCD_MspDeInit() : stm32l4xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32l4xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32l4xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_Start() : stm32l4xx_hal_pcd.c
  • HAL_PCD_STATE_BUSY : stm32l4xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32l4xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32l4xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32l4xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32l4xx_hal_pcd.h
  • HAL_PCD_Stop() : stm32l4xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_SetRxFiFo() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_SetTxFiFo() : stm32l4xx_hal_pcd_ex.c
  • HAL_PhaseTypeDef : stm32l4xx_hal_cryp.h
  • HAL_PWR_ConfigPVD() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32l4xx_hal_pwr.c
  • HAL_PWR_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_PWR_PVDCallback() : stm32l4xx_hal_pwr.c
  • HAL_PWREx_ConfigPVM() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullDown() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullUp() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableInternalWakeUpLine() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowPowerRunMode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePullUpPullDownConfig() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM1() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM2() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM3() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM4() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableSRAM2ContentRetention() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableVddIO2() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableVddUSB() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullDown() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullUp() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableInternalWakeUpLine() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowPowerRunMode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePullUpPullDownConfig() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM1() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM2() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM3() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM4() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableSRAM2ContentRetention() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableVddIO2() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableVddUSB() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSHUTDOWNMode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP0Mode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP1Mode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP2Mode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_IRQHandler() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM1Callback() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM2Callback() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM3Callback() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM4Callback() : stm32l4xx_hal_pwr_ex.c
  • HAL_QPSI_TIMEOUT_DEFAULT_VALUE : stm32l4xx_hal_qspi.h
  • HAL_QSPI_Abort() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Abort_IT() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_AbortCpltCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_AutoPolling() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_AutoPolling_IT() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_CmdCpltCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Command() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Command_IT() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_DeInit() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_ERROR_DMA : stm32l4xx_hal_qspi.h
  • HAL_QSPI_ERROR_INVALID_PARAM : stm32l4xx_hal_qspi.h
  • HAL_QSPI_ERROR_NONE : stm32l4xx_hal_qspi.h
  • HAL_QSPI_ERROR_TIMEOUT : stm32l4xx_hal_qspi.h
  • HAL_QSPI_ERROR_TRANSFER : stm32l4xx_hal_qspi.h
  • HAL_QSPI_ErrorCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_FifoThresholdCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_GetError() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_GetFifoThreshold() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_GetState() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_Init() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_IRQHandler() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_MemoryMapped() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_QSPI_MspDeInit() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_MspInit() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Receive() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Receive_DMA() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Receive_IT() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_RxCpltCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_RxHalfCpltCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_SetFifoThreshold() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_SetTimeout() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_ABORT : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_AUTO_POLLING : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_RX : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_TX : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_MEM_MAPPED : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_ERROR : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_READY : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_RESET : stm32l4xx_hal_qspi.h
  • HAL_QSPI_StateTypeDef : stm32l4xx_hal_qspi.h
  • HAL_QSPI_StatusMatchCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_TimeOutCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Transmit() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Transmit_DMA() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Transmit_IT() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_TxCpltCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_TxHalfCpltCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_RCC_ClockConfig() : stm32l4xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32l4xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32l4xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32l4xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32l4xx_hal_rcc.c
  • HAL_RCC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_RCC_NMI_IRQHandler() : stm32l4xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32l4xx_hal_rcc.c
  • HAL_RCCEx_DisableLSCO() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSECSS() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableMSIPLLMode() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisablePLLSAI1() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisablePLLSAI2() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSCO() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS_IT() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableMSIPLLMode() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnablePLLSAI1() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnablePLLSAI2() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_Callback() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_IRQHandler() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_StandbyMSIRangeConfig() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_WakeUpStopCLKConfig() : stm32l4xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32l4xx_hal.c
  • HAL_RNG_DeInit() : stm32l4xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32l4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32l4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32l4xx_hal_rng.c
  • HAL_RNG_GetRandomNumber() : stm32l4xx_hal_rng.c
  • HAL_RNG_GetRandomNumber_IT() : stm32l4xx_hal_rng.c
  • HAL_RNG_GetState() : stm32l4xx_hal_rng.c
  • HAL_RNG_Init() : stm32l4xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32l4xx_hal_rng.c
  • HAL_RNG_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_RNG_MspDeInit() : stm32l4xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32l4xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32l4xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32l4xx_hal_rng.c
  • HAL_RNG_STATE_BUSY : stm32l4xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32l4xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32l4xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32l4xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32l4xx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32l4xx_hal_rng.h
  • HAL_RS485Ex_Init() : stm32l4xx_hal_uart_ex.c
  • HAL_RTC_AlarmAEventCallback() : stm32l4xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32l4xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32l4xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32l4xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32l4xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32l4xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32l4xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32l4xx_hal_rtc.c
  • HAL_RTC_Init() : stm32l4xx_hal_rtc.c
  • HAL_RTC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_RTC_MspDeInit() : stm32l4xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32l4xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32l4xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32l4xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32l4xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32l4xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32l4xx_hal_rtc.c
  • HAL_RTC_STATE_BUSY : stm32l4xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32l4xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32l4xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32l4xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32l4xx_hal_rtc.h
  • HAL_RTC_WaitForSynchro() : stm32l4xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCStateTypeDef : stm32l4xx_hal_rtc.h
  • HAL_SAI_Abort() : stm32l4xx_hal_sai.c
  • HAL_SAI_DeInit() : stm32l4xx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32l4xx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32l4xx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32l4xx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32l4xx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32l4xx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32l4xx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32l4xx_hal_sai.c
  • HAL_SAI_ERROR_AFSDET : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_DMA : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32l4xx_hal_sai.h
  • HAL_SAI_ErrorCallback() : stm32l4xx_hal_sai.c
  • HAL_SAI_GetError() : stm32l4xx_hal_sai.c
  • HAL_SAI_GetState() : stm32l4xx_hal_sai.c
  • HAL_SAI_Init() : stm32l4xx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32l4xx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32l4xx_hal_sai.c
  • HAL_SAI_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SAI_MspDeInit() : stm32l4xx_hal_sai.c
  • HAL_SAI_MspInit() : stm32l4xx_hal_sai.c
  • HAL_SAI_Receive() : stm32l4xx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32l4xx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32l4xx_hal_sai.c
  • HAL_SAI_RxCpltCallback() : stm32l4xx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32l4xx_hal_sai.c
  • HAL_SAI_STATE_BUSY : stm32l4xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32l4xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32l4xx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32l4xx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32l4xx_hal_sai.h
  • HAL_SAI_StateTypeDef : stm32l4xx_hal_sai.h
  • HAL_SAI_Transmit() : stm32l4xx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32l4xx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32l4xx_hal_sai.c
  • HAL_SAI_TxCpltCallback() : stm32l4xx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32l4xx_hal_sai.c
  • HAL_SD_CheckReadOperation() : stm32l4xx_hal_sd.c
  • HAL_SD_CheckWriteOperation() : stm32l4xx_hal_sd.c
  • HAL_SD_DeInit() : stm32l4xx_hal_sd.c
  • HAL_SD_DMA_RxCpltCallback() : stm32l4xx_hal_sd.c
  • HAL_SD_DMA_RxErrorCallback() : stm32l4xx_hal_sd.c
  • HAL_SD_DMA_TxCpltCallback() : stm32l4xx_hal_sd.c
  • HAL_SD_DMA_TxErrorCallback() : stm32l4xx_hal_sd.c
  • HAL_SD_Erase() : stm32l4xx_hal_sd.c
  • HAL_SD_Get_CardInfo() : stm32l4xx_hal_sd.c
  • HAL_SD_GetCardStatus() : stm32l4xx_hal_sd.c
  • HAL_SD_GetStatus() : stm32l4xx_hal_sd.c
  • HAL_SD_HighSpeed() : stm32l4xx_hal_sd.c
  • HAL_SD_Init() : stm32l4xx_hal_sd.c
  • HAL_SD_IRQHandler() : stm32l4xx_hal_sd.c
  • HAL_SD_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SD_MspDeInit() : stm32l4xx_hal_sd.c
  • HAL_SD_MspInit() : stm32l4xx_hal_sd.c
  • HAL_SD_ReadBlocks() : stm32l4xx_hal_sd.c
  • HAL_SD_ReadBlocks_DMA() : stm32l4xx_hal_sd.c
  • HAL_SD_SendSDStatus() : stm32l4xx_hal_sd.c
  • HAL_SD_StopTransfer() : stm32l4xx_hal_sd.c
  • HAL_SD_WideBusOperation_Config() : stm32l4xx_hal_sd.c
  • HAL_SD_WriteBlocks() : stm32l4xx_hal_sd.c
  • HAL_SD_WriteBlocks_DMA() : stm32l4xx_hal_sd.c
  • HAL_SD_XferCpltCallback() : stm32l4xx_hal_sd.c
  • HAL_SD_XferErrorCallback() : stm32l4xx_hal_sd.c
  • HAL_SMARTCARD_DeInit() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_ERROR_DMA : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ErrorCallback() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorTypeDef : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_GetError() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SMARTCARD_MspDeInit() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_STATE_BUSY : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_Transmit() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32l4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32l4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32l4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32l4xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_DisableListen_IT() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_EnableAlert_IT() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_EnableListen_IT() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_ER_IRQHandler() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_ERROR_ACKF : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ErrorCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_ListenCpltCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_Master_Receive_IT() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_Master_Transmit_IT() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_MasterRxCpltCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SMBUS_MspDeInit() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_MspInit() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32l4xx_hal_smbus.c , stm32l4xx_hal_smbus.h
  • HAL_SMBUS_Slave_Transmit_IT() : stm32l4xx_hal_smbus.c , stm32l4xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_STATE_BUSY : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32l4xx_hal_smbus.h
  • HAL_SPI_DeInit() : stm32l4xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32l4xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32l4xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32l4xx_hal_spi.c
  • HAL_SPI_ERROR_CRC : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_UNKNOW : stm32l4xx_hal_spi.h
  • HAL_SPI_ErrorCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_GetError() : stm32l4xx_hal_spi.c
  • HAL_SPI_GetState() : stm32l4xx_hal_spi.c
  • HAL_SPI_Init() : stm32l4xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32l4xx_hal_spi.c
  • HAL_SPI_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SPI_MspDeInit() : stm32l4xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32l4xx_hal_spi.c
  • HAL_SPI_Receive() : stm32l4xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32l4xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32l4xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_STATE_BUSY : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32l4xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32l4xx_hal_spi.h
  • HAL_SPI_Transmit() : stm32l4xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32l4xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32l4xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32l4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32l4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32l4xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPIEx_FlushRxFifo() : stm32l4xx_hal_spi_ex.c
  • HAL_SRAM_DeInit() : stm32l4xx_hal_sram.c
  • HAL_SRAM_DMA_XferCpltCallback() : stm32l4xx_hal_sram.c
  • HAL_SRAM_DMA_XferErrorCallback() : stm32l4xx_hal_sram.c
  • HAL_SRAM_GetState() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Init() : stm32l4xx_hal_sram.c
  • HAL_SRAM_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SRAM_MspDeInit() : stm32l4xx_hal_sram.c
  • HAL_SRAM_MspInit() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Read_16b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Read_32b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Read_8b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Read_DMA() : stm32l4xx_hal_sram.c
  • HAL_SRAM_STATE_BUSY : stm32l4xx_hal_sram.h
  • HAL_SRAM_STATE_ERROR : stm32l4xx_hal_sram.h
  • HAL_SRAM_STATE_PROTECTED : stm32l4xx_hal_sram.h
  • HAL_SRAM_STATE_READY : stm32l4xx_hal_sram.h
  • HAL_SRAM_STATE_RESET : stm32l4xx_hal_sram.h
  • HAL_SRAM_StateTypeDef : stm32l4xx_hal_sram.h
  • HAL_SRAM_Write_16b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Write_32b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Write_8b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Write_DMA() : stm32l4xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Disable() : stm32l4xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Enable() : stm32l4xx_hal_sram.c
  • HAL_SuspendTick() : stm32l4xx_hal.c
  • HAL_SuspendTypeDef : stm32l4xx_hal_cryp.h
  • HAL_SWPMI_DeInit() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_DisableLoopback() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_DMAStop() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_EnableLoopback() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_CRC : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_DMA : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_NONE : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_OVR : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_UDR : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ErrorCallback() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_GetError() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_GetState() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_Init() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_IRQHandler() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SWPMI_MspDeInit() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_MspInit() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_Receive() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_Receive_DMA() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_Receive_IT() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_RxCpltCallback() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_RxHalfCpltCallback() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_STATE_BUSY : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_RX : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX_RX : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_ERROR : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_READY : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_RESET : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_TIMEOUT : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_StateTypeDef : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_Transmit() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_Transmit_DMA() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_Transmit_IT() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_TxCpltCallback() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_TxHalfCpltCallback() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SYSCFG_DisableIOAnalogSwitchBooster() : stm32l4xx_hal.c
  • HAL_SYSCFG_DisableMemorySwappingBank() : stm32l4xx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32l4xx_hal.c
  • HAL_SYSCFG_EnableIOAnalogSwitchBooster() : stm32l4xx_hal.c
  • HAL_SYSCFG_EnableMemorySwappingBank() : stm32l4xx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32l4xx_hal.c
  • HAL_SYSCFG_SRAM2Erase() : stm32l4xx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32l4xx_hal.c
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32l4xx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32l4xx_hal.c
  • HAL_SYSTICK_Callback() : stm32l4xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32l4xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32l4xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32l4xx_hal_cortex.c
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32l4xx_hal_tim.h
  • HAL_TIM_ActiveChannel : stm32l4xx_hal_tim.h
  • HAL_TIM_Base_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32l4xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32l4xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32l4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32l4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32l4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32l4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32l4xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32l4xx_hal_tim.c
  • HAL_TIM_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_TIM_OC_ConfigChannel() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32l4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32l4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_STATE_BUSY : stm32l4xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32l4xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32l4xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32l4xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32l4xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32l4xx_hal_tim.h
  • HAL_TIM_TriggerCallback() : stm32l4xx_hal_tim.c
  • HAL_TIMEOUT_ADDR : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_DIR : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_RXNE : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32l4xx_hal_smbus.c
  • HAL_TIMEx_BreakCallback() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32l4xx_hal_tim_ex.c
  • HAL_TSC_ConvCpltCallback() : stm32l4xx_hal_tsc.c
  • HAL_TSC_DeInit() : stm32l4xx_hal_tsc.c
  • HAL_TSC_ErrorCallback() : stm32l4xx_hal_tsc.c
  • HAL_TSC_GetState() : stm32l4xx_hal_tsc.c
  • HAL_TSC_GroupGetStatus() : stm32l4xx_hal_tsc.c
  • HAL_TSC_GroupGetValue() : stm32l4xx_hal_tsc.c
  • HAL_TSC_Init() : stm32l4xx_hal_tsc.c
  • HAL_TSC_IOConfig() : stm32l4xx_hal_tsc.c
  • HAL_TSC_IODischarge() : stm32l4xx_hal_tsc.c
  • HAL_TSC_IRQHandler() : stm32l4xx_hal_tsc.c
  • HAL_TSC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_TSC_MspDeInit() : stm32l4xx_hal_tsc.c
  • HAL_TSC_MspInit() : stm32l4xx_hal_tsc.c
  • HAL_TSC_PollForAcquisition() : stm32l4xx_hal_tsc.c
  • HAL_TSC_Start() : stm32l4xx_hal_tsc.c
  • HAL_TSC_Start_IT() : stm32l4xx_hal_tsc.c
  • HAL_TSC_STATE_BUSY : stm32l4xx_hal_tsc.h
  • HAL_TSC_STATE_ERROR : stm32l4xx_hal_tsc.h
  • HAL_TSC_STATE_READY : stm32l4xx_hal_tsc.h
  • HAL_TSC_STATE_RESET : stm32l4xx_hal_tsc.h
  • HAL_TSC_StateTypeDef : stm32l4xx_hal_tsc.h
  • HAL_TSC_Stop() : stm32l4xx_hal_tsc.c
  • HAL_TSC_Stop_IT() : stm32l4xx_hal_tsc.c
  • HAL_UART_DeInit() : stm32l4xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32l4xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32l4xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32l4xx_hal_uart.c
  • HAL_UART_ERROR_DMA : stm32l4xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32l4xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32l4xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32l4xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32l4xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32l4xx_hal_uart.h
  • HAL_UART_ErrorCallback() : stm32l4xx_hal_uart.c
  • HAL_UART_ErrorTypeDef : stm32l4xx_hal_uart.h
  • HAL_UART_GetError() : stm32l4xx_hal_uart.c
  • HAL_UART_GetState() : stm32l4xx_hal_uart.c
  • HAL_UART_Init() : stm32l4xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32l4xx_hal_uart.c
  • HAL_UART_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_UART_MspDeInit() : stm32l4xx_hal_uart.c
  • HAL_UART_MspInit() : stm32l4xx_hal_uart.c
  • HAL_UART_Receive() : stm32l4xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32l4xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32l4xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32l4xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32l4xx_hal_uart.c
  • HAL_UART_STATE_BUSY : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32l4xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32l4xx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32l4xx_hal_uart.h
  • HAL_UART_Transmit() : stm32l4xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32l4xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32l4xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32l4xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32l4xx_hal_uart.c
  • HAL_UARTEx_DisableStopMode() : stm32l4xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32l4xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32l4xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32l4xx_hal_uart_ex.c
  • HAL_USART_DeInit() : stm32l4xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32l4xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32l4xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32l4xx_hal_usart.c
  • HAL_USART_ERROR_DMA : stm32l4xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32l4xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32l4xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32l4xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32l4xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32l4xx_hal_usart.h
  • HAL_USART_ErrorCallback() : stm32l4xx_hal_usart.c
  • HAL_USART_ErrorTypeDef : stm32l4xx_hal_usart.h
  • HAL_USART_GetError() : stm32l4xx_hal_usart.c
  • HAL_USART_GetState() : stm32l4xx_hal_usart.c
  • HAL_USART_Init() : stm32l4xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32l4xx_hal_usart.c
  • HAL_USART_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_USART_MspDeInit() : stm32l4xx_hal_usart.c
  • HAL_USART_MspInit() : stm32l4xx_hal_usart.c
  • HAL_USART_Receive() : stm32l4xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32l4xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32l4xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32l4xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32l4xx_hal_usart.c
  • HAL_USART_STATE_BUSY : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32l4xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32l4xx_hal_usart.h
  • HAL_USART_Transmit() : stm32l4xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32l4xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32l4xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32l4xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32l4xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32l4xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32l4xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32l4xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32l4xx_hal_usart.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32l4xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32l4xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32l4xx_hal_wwdg.c
  • HAL_WWDG_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_WWDG_MspInit() : stm32l4xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32l4xx_hal_wwdg.c
  • HCD_HC_IN_IRQHandler() : stm32l4xx_hal_hcd.c
  • HCD_HC_OUT_IRQHandler() : stm32l4xx_hal_hcd.c
  • HCD_HCStateTypeDef : stm32l4xx_hal_hcd.h
  • HCD_HCTypeDef : stm32l4xx_hal_hcd.h
  • HCD_InitTypeDef : stm32l4xx_hal_hcd.h
  • HCD_PHY_EMBEDDED : stm32l4xx_hal_hcd.h
  • HCD_Port_IRQHandler() : stm32l4xx_hal_hcd.c
  • HCD_RXQLVL_IRQHandler() : stm32l4xx_hal_hcd.c
  • HCD_SPEED_FULL : stm32l4xx_hal_hcd.h
  • HCD_SPEED_HIGH : stm32l4xx_hal_hcd.h
  • HCD_SPEED_LOW : stm32l4xx_hal_hcd.h
  • HCD_StateTypeDef : stm32l4xx_hal_hcd.h
  • HCD_TypeDef : stm32l4xx_hal_hcd.h
  • HCD_URBStateTypeDef : stm32l4xx_hal_hcd.h
  • HSE_STARTUP_TIMEOUT : stm32l4xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • HSE_VALUE : stm32l4xx_ll_rcc.h , stm32l4xx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • HSI48_VALUE : stm32l4xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • HSI_VALUE : stm32l4xx_hal_conf.h , stm32l4xx_ll_rcc.h
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32l4xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32l4xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32l4xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32l4xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32l4xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32l4xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32l4xx_hal_i2c.h
  • I2C_Disable_IRQ() : stm32l4xx_hal_i2c.c
  • I2C_DMAAbort() : stm32l4xx_hal_i2c.c
  • I2C_DMAError() : stm32l4xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32l4xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32l4xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32l4xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32l4xx_hal_i2c.c
  • I2C_DUALADDRESS_DISABLE : stm32l4xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32l4xx_hal_i2c.h
  • I2C_Enable_IRQ() : stm32l4xx_hal_i2c.c
  • I2C_FASTMODEPLUS_I2C1 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32l4xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32l4xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32l4xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_AF : stm32l4xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32l4xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32l4xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32l4xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32l4xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32l4xx_hal_i2c.h
  • I2C_FLAG_TC : stm32l4xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32l4xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32l4xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32l4xx_hal_i2c.h
  • I2C_Flush_TXDR() : stm32l4xx_hal_i2c.c
  • I2C_GENERALCALL_DISABLE : stm32l4xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32l4xx_hal_i2c.h
  • I2C_GENERATE_START : stm32l4xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32l4xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32l4xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32l4xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32l4xx_hal_i2c.h
  • I2C_GET_DIR : stm32l4xx_hal_i2c.h
  • I2C_GET_DMA_REMAIN_DATA : stm32l4xx_hal_i2c.c
  • I2C_GET_OWN_ADDRESS1 : stm32l4xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32l4xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32l4xx_hal_i2c.h
  • I2C_HandleTypeDef : stm32l4xx_hal_i2c.h
  • I2C_IsAcknowledgeFailed() : stm32l4xx_hal_i2c.c
  • I2C_IT_ADDRI : stm32l4xx_hal_i2c.h
  • I2C_IT_ERRI : stm32l4xx_hal_i2c.h
  • I2C_IT_NACKI : stm32l4xx_hal_i2c.h
  • I2C_IT_RXI : stm32l4xx_hal_i2c.h
  • I2C_IT_STOPI : stm32l4xx_hal_i2c.h
  • I2C_IT_TCI : stm32l4xx_hal_i2c.h
  • I2C_IT_TXI : stm32l4xx_hal_i2c.h
  • I2C_ITAddrCplt() : stm32l4xx_hal_i2c.c
  • I2C_ITError() : stm32l4xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32l4xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32l4xx_hal_i2c.c
  • I2C_ITMasterSequentialCplt() : stm32l4xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32l4xx_hal_i2c.c
  • I2C_ITSlaveSequentialCplt() : stm32l4xx_hal_i2c.c
  • I2C_LAST_FRAME : stm32l4xx_hal_i2c.h
  • I2C_Master_ISR_DMA() : stm32l4xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32l4xx_hal_i2c.c
  • I2C_MEM_ADD_LSB : stm32l4xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32l4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32l4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32l4xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32l4xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32l4xx_hal_i2c.h
  • I2C_NO_STARTSTOP : stm32l4xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32l4xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32l4xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32l4xx_hal_i2c.h
  • I2C_POSITION_CR1_DNF : stm32l4xx_ll_i2c.h
  • I2C_POSITION_CR2_NBYTES : stm32l4xx_ll_i2c.h
  • I2C_POSITION_ISR_ADDCODE : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMEOUTR_TIMEOUTB : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMINGR_PRESC : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMINGR_SCLDEL : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMINGR_SCLH : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMINGR_SCLL : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMINGR_SDADEL : stm32l4xx_ll_i2c.h
  • I2C_RELOAD_MODE : stm32l4xx_hal_i2c.h
  • I2C_RequestMemoryRead() : stm32l4xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32l4xx_hal_i2c.c
  • I2C_RESET_CR2 : stm32l4xx_hal_i2c.h
  • I2C_Slave_ISR_DMA() : stm32l4xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32l4xx_hal_i2c.c
  • I2C_SOFTEND_MODE : stm32l4xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32l4xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32l4xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32l4xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32l4xx_hal_i2c.c
  • I2C_STATE_MSK : stm32l4xx_hal_i2c.c
  • I2C_STATE_NONE : stm32l4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32l4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32l4xx_hal_i2c.c
  • I2C_TransferConfig() : stm32l4xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32l4xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32l4xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32l4xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32l4xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32l4xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32l4xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32l4xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32l4xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32l4xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32l4xx_hal_i2c.c
  • IC1Config() : stm32l4xx_ll_tim.c
  • IC2Config() : stm32l4xx_ll_tim.c
  • IC3Config() : stm32l4xx_ll_tim.c
  • IC4Config() : stm32l4xx_ll_tim.c
  • INSTRUCTION_CACHE_ENABLE : stm32l4xx_hal_conf.h
  • IRDA_AUTOBAUD_REQUEST : stm32l4xx_hal_irda.h
  • IRDA_BAUDRATE : stm32l4xx_hal_irda.h
  • IRDA_CheckIdleState() : stm32l4xx_hal_irda.c
  • IRDA_CLEAR_FEF : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK1 : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK2 : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32l4xx_hal_irda.h
  • IRDA_ClockSourceTypeDef : stm32l4xx_hal_irda.h
  • IRDA_ControlTypeDef : stm32l4xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32l4xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32l4xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32l4xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32l4xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32l4xx_hal_irda.h
  • IRDA_DMAError() : stm32l4xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32l4xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32l4xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32l4xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32l4xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32l4xx_hal_irda.c
  • IRDA_FLAG_ABRE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32l4xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32l4xx_hal_irda.h
  • IRDA_FLAG_FE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_NE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_PE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32l4xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_TC : stm32l4xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32l4xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32l4xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32l4xx_hal_irda_ex.h
  • IRDA_IT_ERR : stm32l4xx_hal_irda.h
  • IRDA_IT_FE : stm32l4xx_hal_irda.h
  • IRDA_IT_IDLE : stm32l4xx_hal_irda.h
  • IRDA_IT_MASK : stm32l4xx_hal_irda.h
  • IRDA_IT_NE : stm32l4xx_hal_irda.h
  • IRDA_IT_ORE : stm32l4xx_hal_irda.h
  • IRDA_IT_PE : stm32l4xx_hal_irda.h
  • IRDA_IT_RXNE : stm32l4xx_hal_irda.h
  • IRDA_IT_TC : stm32l4xx_hal_irda.h
  • IRDA_IT_TXE : stm32l4xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32l4xx_hal_irda.h
  • IRDA_MODE : stm32l4xx_hal_irda.h
  • IRDA_MODE_DISABLE : stm32l4xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32l4xx_hal_irda.h
  • IRDA_MODE_RX : stm32l4xx_hal_irda.h
  • IRDA_MODE_TX : stm32l4xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32l4xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_irda.h
  • IRDA_PARITY : stm32l4xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32l4xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32l4xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32l4xx_hal_irda.h
  • IRDA_POWERMODE : stm32l4xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32l4xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32l4xx_hal_irda.h
  • IRDA_PRESCALER : stm32l4xx_hal_irda.h
  • IRDA_Receive_IT() : stm32l4xx_hal_irda.c
  • IRDA_RXDATA_FLUSH_REQUEST : stm32l4xx_hal_irda.h
  • IRDA_SetConfig() : stm32l4xx_hal_irda.c
  • IRDA_STATE_DISABLE : stm32l4xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32l4xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32l4xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32l4xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32l4xx_hal_irda.h
  • IRDA_WaitOnFlagUntilTimeout() : stm32l4xx_hal_irda.c
  • IRDA_WORDLENGTH : stm32l4xx_hal_irda.h
  • IRDA_WORDLENGTH_7B : stm32l4xx_hal_irda.h
  • IRDA_WORDLENGTH_8B : stm32l4xx_hal_irda.h
  • IRDA_WORDLENGTH_9B : stm32l4xx_hal_irda.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32l4xx_hal_adc_ex.h
  • IS_ADC_CALFACT : stm32l4xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32l4xx_hal_adc_ex.h
  • IS_ADC_CLOCKPRESCALER : stm32l4xx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32l4xx_hal_adc_ex.h
  • IS_ADC_DATA_ALIGN : stm32l4xx_hal_adc.h
  • IS_ADC_DFSDMCFG_MODE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_DIFF_CHANNEL : stm32l4xx_hal_adc_ex.h
  • IS_ADC_DMA_ACCESS_MULTIMODE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_EOC_SELECTION : stm32l4xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32l4xx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32l4xx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32l4xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32l4xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32l4xx_hal_adc_ex.h
  • IS_ADC_MULTIMODE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_OFFSET_NUMBER : stm32l4xx_hal_adc_ex.h
  • IS_ADC_OVERRUN : stm32l4xx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32l4xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32l4xx_hal_adc.h
  • IS_ADC_REGOVERSAMPLING_MODE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32l4xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32l4xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32l4xx_hal_adc_ex.h
  • IS_ADC_RESOLUTION : stm32l4xx_hal_adc.h
  • IS_ADC_RESOLUTION_8_6_BITS : stm32l4xx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32l4xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32l4xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32l4xx_hal_adc_ex.h
  • IS_ADC_SCAN_MODE : stm32l4xx_hal_adc.h
  • IS_ADC_SINGLE_DIFFERENTIAL : stm32l4xx_hal_adc_ex.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32l4xx_hal_adc_ex.h
  • IS_CAN_BANKNUMBER : stm32l4xx_hal_can.h
  • IS_CAN_BS1 : stm32l4xx_hal_can.h
  • IS_CAN_BS2 : stm32l4xx_hal_can.h
  • IS_CAN_DLC : stm32l4xx_hal_can.h
  • IS_CAN_EXTID : stm32l4xx_hal_can.h
  • IS_CAN_FIFO : stm32l4xx_hal_can.h
  • IS_CAN_FILTER_FIFO : stm32l4xx_hal_can.h
  • IS_CAN_FILTER_MODE : stm32l4xx_hal_can.h
  • IS_CAN_FILTER_NUMBER : stm32l4xx_hal_can.h
  • IS_CAN_FILTER_SCALE : stm32l4xx_hal_can.h
  • IS_CAN_IDTYPE : stm32l4xx_hal_can.h
  • IS_CAN_MODE : stm32l4xx_hal_can.h
  • IS_CAN_PRESCALER : stm32l4xx_hal_can.h
  • IS_CAN_RTR : stm32l4xx_hal_can.h
  • IS_CAN_SJW : stm32l4xx_hal_can.h
  • IS_CAN_STDID : stm32l4xx_hal_can.h
  • IS_CAN_TRANSMITMAILBOX : stm32l4xx_hal_can.h
  • IS_COMP_BLANKINGSRC_INSTANCE : stm32l4xx_hal_comp.h
  • IS_COMP_BLANKINGSRCE : stm32l4xx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32l4xx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32l4xx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32l4xx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32l4xx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32l4xx_hal_comp.h
  • IS_COMP_POWERMODE : stm32l4xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32l4xx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32l4xx_hal_comp.h
  • IS_CRC_INPUTDATA_FORMAT : stm32l4xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32l4xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32l4xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32l4xx_hal_crc.h
  • IS_CRYP_AES : stm32l4xx_hal_cryp.h
  • IS_CRYP_ALGOMODE : stm32l4xx_hal_cryp.h
  • IS_CRYP_CHAINMODE : stm32l4xx_hal_cryp.h
  • IS_CRYP_DATATYPE : stm32l4xx_hal_cryp.h
  • IS_CRYP_DMAIN : stm32l4xx_hal_cryp.h
  • IS_CRYP_DMAOUT : stm32l4xx_hal_cryp.h
  • IS_CRYP_GCMCMAC_PHASE : stm32l4xx_hal_cryp.h
  • IS_CRYP_KEYSIZE : stm32l4xx_hal_cryp.h
  • IS_CRYP_WRITE : stm32l4xx_hal_cryp.h
  • IS_DAC_ALIGN : stm32l4xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32l4xx_hal_dac.h
  • IS_DAC_CHIP_CONNECTION : stm32l4xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32l4xx_hal_dac.h
  • IS_DAC_HOLDTIME : stm32l4xx_hal_dac_ex.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32l4xx_hal_dac_ex.h
  • IS_DAC_NEWTRIMMINGVALUE : stm32l4xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32l4xx_hal_dac.h
  • IS_DAC_REFRESHTIME : stm32l4xx_hal_dac.h
  • IS_DAC_SAMPLEANDHOLD : stm32l4xx_hal_dac_ex.h
  • IS_DAC_SAMPLETIME : stm32l4xx_hal_dac_ex.h
  • IS_DAC_TRIGGER : stm32l4xx_hal_dac_ex.h
  • IS_DAC_TRIMMING : stm32l4xx_hal_dac_ex.h
  • IS_DAC_TRIMMINGVALUE : stm32l4xx_hal_dac_ex.h
  • IS_DEFAULT_INIT_VALUE : stm32l4xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32l4xx_hal_crc.h
  • IS_DFSDM_BREAK_SIGNALS : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_DATA_PACKING : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_ORDER : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_OVS_RATIO : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT_PINS : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OFFSET : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SCD_THRESHOLD : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SPI_CLOCK : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CONTINUOUS_MODE : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_DATA_SOURCE : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_THRESHOLD : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG_EDGE : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INJ_TRIGGER : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_OVS_RATIO : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_REG_TRIGGER : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_SINC_ORDER : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_INJECTED_CHANNEL : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_REGULAR_CHANNEL : stm32l4xx_hal_dfsdm.h
  • IS_DMA_ALL_REQUEST : stm32l4xx_hal_dma.h
  • IS_DMA_BUFFER_SIZE : stm32l4xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32l4xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32l4xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32l4xx_hal_dma.h
  • IS_DMA_MODE : stm32l4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32l4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32l4xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32l4xx_hal_dma.h
  • IS_FIREWALL_CODE_SEGMENT_ADDRESS : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_CODE_SEGMENT_LENGTH : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_VOLATILEDATA_EXECUTE : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_VOLATILEDATA_SHARE : stm32l4xx_hal_firewall.h
  • IS_FLASH_BANK : stm32l4xx_hal_flash.h
  • IS_FLASH_BANK_EXCLUSIVE : stm32l4xx_hal_flash.h
  • IS_FLASH_LATENCY : stm32l4xx_hal_flash.h
  • IS_FLASH_MAIN_MEM_ADDRESS : stm32l4xx_hal_flash.h
  • IS_FLASH_OTP_ADDRESS : stm32l4xx_hal_flash.h
  • IS_FLASH_PAGE : stm32l4xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32l4xx_hal_flash.h
  • IS_FLASH_TYPEERASE : stm32l4xx_hal_flash.h
  • IS_FLASH_TYPEPROGRAM : stm32l4xx_hal_flash.h
  • IS_GPIO_AF : stm32l4xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32l4xx_hal_gpio.h
  • IS_GPIO_PIN : stm32l4xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32l4xx_hal_gpio.h
  • IS_GPIO_PULL : stm32l4xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32l4xx_hal_gpio.h
  • IS_I2C_ADDRESSING_MODE : stm32l4xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32l4xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32l4xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32l4xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32l4xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32l4xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32l4xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32l4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32l4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32l4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32l4xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32l4xx_hal_i2c.h
  • IS_IRDA_BAUDRATE : stm32l4xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32l4xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32l4xx_hal_irda.h
  • IS_IRDA_MODE : stm32l4xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32l4xx_hal_irda.h
  • IS_IRDA_PARITY : stm32l4xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32l4xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32l4xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32l4xx_hal_irda.h
  • IS_IRDA_STATE : stm32l4xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32l4xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32l4xx_hal_irda.h
  • IS_IWDG_PRESCALER : stm32l4xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32l4xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32l4xx_hal_iwdg.h
  • IS_LCD_BIAS : stm32l4xx_hal_lcd.h
  • IS_LCD_BLINK_FREQUENCY : stm32l4xx_hal_lcd.h
  • IS_LCD_BLINK_MODE : stm32l4xx_hal_lcd.h
  • IS_LCD_CONTRAST : stm32l4xx_hal_lcd.h
  • IS_LCD_DEAD_TIME : stm32l4xx_hal_lcd.h
  • IS_LCD_DIVIDER : stm32l4xx_hal_lcd.h
  • IS_LCD_DUTY : stm32l4xx_hal_lcd.h
  • IS_LCD_HIGH_DRIVE : stm32l4xx_hal_lcd.h
  • IS_LCD_MUX_SEGMENT : stm32l4xx_hal_lcd.h
  • IS_LCD_PRESCALER : stm32l4xx_hal_lcd.h
  • IS_LCD_PULSE_ON_DURATION : stm32l4xx_hal_lcd.h
  • IS_LCD_RAM_REGISTER : stm32l4xx_hal_lcd.h
  • IS_LCD_VOLTAGE_SOURCE : stm32l4xx_hal_lcd.h
  • IS_LL_ADC_COMMON_CLOCK : stm32l4xx_ll_adc.c
  • IS_LL_ADC_DATA_ALIGN : stm32l4xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32l4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32l4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_EXT_EDGE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_LOW_POWER : stm32l4xx_ll_adc.c
  • IS_LL_ADC_MULTI_DMA_TRANSFER : stm32l4xx_ll_adc.c
  • IS_LL_ADC_MULTI_MASTER_SLAVE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_MULTI_MODE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_MULTI_TWOSMP_DELAY : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_OVR_DATA_BEHAVIOR : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_RESOLUTION : stm32l4xx_ll_adc.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32l4xx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32l4xx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32l4xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_BLANKING_SOURCE : stm32l4xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32l4xx_ll_comp.c
  • IS_LL_COMP_POWER_MODE : stm32l4xx_ll_comp.c
  • IS_LL_DAC_CHANNEL : stm32l4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_BUFFER : stm32l4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_CONNECTION : stm32l4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_MODE : stm32l4xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE : stm32l4xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_CONFIG : stm32l4xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_MODE : stm32l4xx_ll_dac.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32l4xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32l4xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_PERIPHREQUEST : stm32l4xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32l4xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32l4xx_ll_exti.c
  • IS_LL_EXTI_LINE_32_63 : stm32l4xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32l4xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32l4xx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32l4xx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32l4xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32l4xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32l4xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32l4xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32l4xx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32l4xx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32l4xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32l4xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32l4xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32l4xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32l4xx_ll_i2c.c
  • IS_LL_LPUART_BAUDRATE : stm32l4xx_ll_lpuart.c
  • IS_LL_LPUART_DATAWIDTH : stm32l4xx_ll_lpuart.c
  • IS_LL_LPUART_DIRECTION : stm32l4xx_ll_lpuart.c
  • IS_LL_LPUART_HWCONTROL : stm32l4xx_ll_lpuart.c
  • IS_LL_LPUART_PARITY : stm32l4xx_ll_lpuart.c
  • IS_LL_LPUART_STOPBITS : stm32l4xx_ll_lpuart.c
  • IS_LL_OPAMP_FUNCTIONAL_MODE : stm32l4xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_INVERTING : stm32l4xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_NONINVERTING : stm32l4xx_ll_opamp.c
  • IS_LL_OPAMP_POWER_MODE : stm32l4xx_ll_opamp.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_DFSDM_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_LPTIM_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_LPUART_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_RNG_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_SAI_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_SDMMC_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_SWPMI_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_UART_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32l4xx_ll_rtc.c
  • IS_LL_SPI_BAUDRATE : stm32l4xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32l4xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32l4xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32l4xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32l4xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32l4xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32l4xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32l4xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32l4xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32l4xx_ll_spi.c
  • IS_LL_SWPMI_BITRATE_VALUE : stm32l4xx_ll_swpmi.c
  • IS_LL_SWPMI_SW_BUFFER_RX : stm32l4xx_ll_swpmi.c
  • IS_LL_SWPMI_SW_BUFFER_TX : stm32l4xx_ll_swpmi.c
  • IS_LL_SWPMI_VOLTAGE_CLASS : stm32l4xx_ll_swpmi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32l4xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32l4xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32l4xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32l4xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32l4xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32l4xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32l4xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32l4xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32l4xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32l4xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32l4xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32l4xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32l4xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32l4xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32l4xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32l4xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32l4xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32l4xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32l4xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32l4xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32l4xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32l4xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32l4xx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLLM_VALUE : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLLN_VALUE : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLLR_VALUE : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_INPUT : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_OUTPUT : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32l4xx_ll_utils.c
  • IS_LPTIM_AUTORELOAD : stm32l4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32l4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32l4xx_hal_lptim.h , stm32l4xx_ll_lptim.c
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32l4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32l4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32l4xx_hal_lptim.h , stm32l4xx_ll_lptim.c
  • IS_LPTIM_COMPARE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32l4xx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32l4xx_hal_lptim.h , stm32l4xx_ll_lptim.c
  • IS_LPTIM_PERIOD : stm32l4xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32l4xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_WAVEFORM : stm32l4xx_ll_lptim.c
  • IS_LPUART_STOPBITS : stm32l4xx_hal_uart.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32l4xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32l4xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32l4xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32l4xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32l4xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32l4xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32l4xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32l4xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32l4xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32l4xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32l4xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32l4xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32l4xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32l4xx_hal_cortex.h
  • IS_OB_PCROP_RDP : stm32l4xx_hal_flash.h
  • IS_OB_RDP_LEVEL : stm32l4xx_hal_flash.h
  • IS_OB_USER_BFB2 : stm32l4xx_hal_flash.h
  • IS_OB_USER_BOOT1 : stm32l4xx_hal_flash.h
  • IS_OB_USER_BOR_LEVEL : stm32l4xx_hal_flash.h
  • IS_OB_USER_DUALBANK : stm32l4xx_hal_flash.h
  • IS_OB_USER_IWDG : stm32l4xx_hal_flash.h
  • IS_OB_USER_IWDG_STDBY : stm32l4xx_hal_flash.h
  • IS_OB_USER_IWDG_STOP : stm32l4xx_hal_flash.h
  • IS_OB_USER_SHUTDOWN : stm32l4xx_hal_flash.h
  • IS_OB_USER_SRAM2_PARITY : stm32l4xx_hal_flash.h
  • IS_OB_USER_SRAM2_RST : stm32l4xx_hal_flash.h
  • IS_OB_USER_STANDBY : stm32l4xx_hal_flash.h
  • IS_OB_USER_STOP : stm32l4xx_hal_flash.h
  • IS_OB_USER_TYPE : stm32l4xx_hal_flash.h
  • IS_OB_USER_WWDG : stm32l4xx_hal_flash.h
  • IS_OB_WRPAREA : stm32l4xx_hal_flash.h
  • IS_OPAMP_FACTORYTRIMMING : stm32l4xx_hal_opamp.h
  • IS_OPAMP_FUNCTIONAL_NORMALMODE : stm32l4xx_hal_opamp.h
  • IS_OPAMP_INVERTING_INPUT_PGA : stm32l4xx_hal_opamp.h
  • IS_OPAMP_INVERTING_INPUT_STANDALONE : stm32l4xx_hal_opamp.h
  • IS_OPAMP_NONINVERTING_INPUT : stm32l4xx_hal_opamp.h
  • IS_OPAMP_PGA_GAIN : stm32l4xx_hal_opamp.h
  • IS_OPAMP_POWER_SUPPLY_RANGE : stm32l4xx_hal_opamp.h
  • IS_OPAMP_POWERMODE : stm32l4xx_hal_opamp.h
  • IS_OPAMP_TRIMMING : stm32l4xx_hal_opamp.h
  • IS_OPAMP_TRIMMINGVALUE : stm32l4xx_hal_opamp.h
  • IS_OPTIONBYTE : stm32l4xx_hal_flash.h
  • IS_PWR_BATTERY_CHARGING : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_GPIO : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_GPIO_BIT_NUMBER : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32l4xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32l4xx_hal_pwr.h
  • IS_PWR_PVM_MODE : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_PVM_TYPE : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_REGULATOR : stm32l4xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32l4xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32l4xx_hal_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32l4xx_hal_pwr_ex.h
  • IS_QSPI_ADDRESS_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_ADDRESS_SIZE : stm32l4xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_SIZE : stm32l4xx_hal_qspi.h
  • IS_QSPI_AUTOMATIC_STOP : stm32l4xx_hal_qspi.h
  • IS_QSPI_CLOCK_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_CLOCK_PRESCALER : stm32l4xx_hal_qspi.h
  • IS_QSPI_CS_HIGH_TIME : stm32l4xx_hal_qspi.h
  • IS_QSPI_DATA_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_DDR_HHC : stm32l4xx_hal_qspi.h
  • IS_QSPI_DDR_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_DUMMY_CYCLES : stm32l4xx_hal_qspi.h
  • IS_QSPI_FIFO_THRESHOLD : stm32l4xx_hal_qspi.h
  • IS_QSPI_FLASH_SIZE : stm32l4xx_hal_qspi.h
  • IS_QSPI_FUNCTIONAL_MODE : stm32l4xx_hal_qspi.c
  • IS_QSPI_INSTRUCTION : stm32l4xx_hal_qspi.h
  • IS_QSPI_INSTRUCTION_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_INTERVAL : stm32l4xx_hal_qspi.h
  • IS_QSPI_MATCH_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_SIOO_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_SSHIFT : stm32l4xx_hal_qspi.h
  • IS_QSPI_STATUS_BYTES_SIZE : stm32l4xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_ACTIVATION : stm32l4xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_PERIOD : stm32l4xx_hal_qspi.h
  • IS_RCC_ADCCLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32l4xx_hal_rcc.h
  • IS_RCC_DFSDM1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32l4xx_hal_rcc.h
  • IS_RCC_HSE : stm32l4xx_hal_rcc.h
  • IS_RCC_HSI : stm32l4xx_hal_rcc.h
  • IS_RCC_HSI_CALIBRATION_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLK : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_LPTIM2CLK : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_LSCOSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32l4xx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32l4xx_hal_rcc.h
  • IS_RCC_LSI : stm32l4xx_hal_rcc.h
  • IS_RCC_MCO : stm32l4xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32l4xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32l4xx_hal_rcc.h
  • IS_RCC_MSI : stm32l4xx_hal_rcc.h
  • IS_RCC_MSI_CLOCK_RANGE : stm32l4xx_hal_rcc.h
  • IS_RCC_MSI_STANDBY_CLOCK_RANGE : stm32l4xx_hal_rcc.h
  • IS_RCC_MSICALIBRATION_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32l4xx_hal_rcc.h
  • IS_RCC_PCLK : stm32l4xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLM_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLSAI1CLOCKOUT_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLSAI1M_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1N_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1P_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1Q_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1R_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1SOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI2CLOCKOUT_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLSAI2M_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI2N_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI2P_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI2R_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI2SOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSOURCE : stm32l4xx_hal_rcc.h
  • IS_RCC_RNGCLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32l4xx_hal_rcc.h
  • IS_RCC_SAI1CLK : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_SAI2CLK : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_SDMMC1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_STOP_WAKEUPCLOCK : stm32l4xx_hal_rcc.h
  • IS_RCC_SWPMI1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_SYSCLKSOURCE : stm32l4xx_hal_rcc.h
  • IS_RCC_UART4CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_UART5CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RTC_ALARM : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32l4xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32l4xx_hal_rtc.h
  • IS_RTC_BKP : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32l4xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32l4xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32l4xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32l4xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32l4xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32l4xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32l4xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32l4xx_hal_rtc.h
  • IS_RTC_MONTH : stm32l4xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_OUTPUT_POL : stm32l4xx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32l4xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32l4xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32l4xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32l4xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32l4xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_INTERRUPT : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32l4xx_hal_rtc.h
  • IS_RTC_YEAR : stm32l4xx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32l4xx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32l4xx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32l4xx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32l4xx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32l4xx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32l4xx_hal_smartcard_ex.h
  • IS_SMARTCARD_WORD_LENGTH : stm32l4xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32l4xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32l4xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32l4xx_hal_smbus.h
  • IS_SMBUS_GENERAL_CALL : stm32l4xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32l4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32l4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32l4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32l4xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32l4xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32l4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32l4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32l4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32l4xx_hal_smbus.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32l4xx_hal_spi.h
  • IS_SPI_CPHA : stm32l4xx_hal_spi.h
  • IS_SPI_CPOL : stm32l4xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32l4xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32l4xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32l4xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32l4xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32l4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32l4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32l4xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32l4xx_hal_spi.h
  • IS_SPI_MODE : stm32l4xx_hal_spi.h
  • IS_SPI_NSS : stm32l4xx_hal_spi.h
  • IS_SPI_NSSP : stm32l4xx_hal_spi.h
  • IS_SPI_TIMODE : stm32l4xx_hal_spi.h
  • IS_SWPMI_BITRATE_VALUE : stm32l4xx_hal_swpmi.h
  • IS_SWPMI_RX_BUFFERING_MODE : stm32l4xx_hal_swpmi.h
  • IS_SWPMI_TX_BUFFERING_MODE : stm32l4xx_hal_swpmi.h
  • IS_SWPMI_VOLTAGE_CLASS : stm32l4xx_hal_swpmi.h
  • IS_SYSCFG_BREAK_CONFIG : stm32l4xx_hal.h
  • IS_SYSCFG_FASTMODEPLUS : stm32l4xx_hal.h
  • IS_SYSCFG_FPU_INTERRUPT : stm32l4xx_hal.h
  • IS_SYSCFG_SRAM2WRP_PAGE : stm32l4xx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32l4xx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32l4xx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32l4xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32l4xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32l4xx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32l4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32l4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32l4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32l4xx_hal_tim_ex.h
  • IS_TIM_CHANNELS : stm32l4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32l4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32l4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32l4xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32l4xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32l4xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32l4xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32l4xx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32l4xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32l4xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32l4xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32l4xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32l4xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32l4xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32l4xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32l4xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32l4xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_REMAP : stm32l4xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32l4xx_hal_tim.h
  • IS_TIM_TRGO2_SOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32l4xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32l4xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32l4xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32l4xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32l4xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32l4xx_hal_i2c.h
  • IS_TSC_ACQ_MODE : stm32l4xx_hal_tsc.h
  • IS_TSC_CTPH : stm32l4xx_hal_tsc.h
  • IS_TSC_CTPL : stm32l4xx_hal_tsc.h
  • IS_TSC_GROUP_INDEX : stm32l4xx_hal_tsc.h
  • IS_TSC_IODEF : stm32l4xx_hal_tsc.h
  • IS_TSC_IOMODE : stm32l4xx_hal_tsc.h
  • IS_TSC_MCE_IT : stm32l4xx_hal_tsc.h
  • IS_TSC_MCV : stm32l4xx_hal_tsc.h
  • IS_TSC_PG_PRESC : stm32l4xx_hal_tsc.h
  • IS_TSC_SS : stm32l4xx_hal_tsc.h
  • IS_TSC_SS_PRESC : stm32l4xx_hal_tsc.h
  • IS_TSC_SSD : stm32l4xx_hal_tsc.h
  • IS_TSC_SYNC_POL : stm32l4xx_hal_tsc.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32l4xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32l4xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32l4xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32l4xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32l4xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32l4xx_hal_uart.h
  • IS_UART_DMA_RX : stm32l4xx_hal_uart.h
  • IS_UART_DMA_TX : stm32l4xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32l4xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32l4xx_hal_uart.h
  • IS_UART_LIN : stm32l4xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32l4xx_hal_uart.h
  • IS_UART_MODE : stm32l4xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32l4xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32l4xx_hal_uart.h
  • IS_UART_OVERRUN : stm32l4xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32l4xx_hal_uart.h
  • IS_UART_PARITY : stm32l4xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32l4xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32l4xx_hal_uart.h
  • IS_UART_STATE : stm32l4xx_hal_uart.h
  • IS_UART_STOPBITS : stm32l4xx_hal_uart.h
  • IS_UART_WAKEUP_SELECTION : stm32l4xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32l4xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32l4xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32l4xx_hal_usart.h
  • IS_USART_CLOCK : stm32l4xx_hal_usart.h
  • IS_USART_LASTBIT : stm32l4xx_hal_usart.h
  • IS_USART_MODE : stm32l4xx_hal_usart.h
  • IS_USART_OVERSAMPLING : stm32l4xx_hal_usart.h
  • IS_USART_PARITY : stm32l4xx_hal_usart.h
  • IS_USART_PHASE : stm32l4xx_hal_usart.h
  • IS_USART_POLARITY : stm32l4xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32l4xx_hal_usart.h
  • IS_USART_STOPBITS : stm32l4xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32l4xx_hal_usart_ex.h
  • IS_WWDG_COUNTER : stm32l4xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32l4xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32l4xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32l4xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32l4xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32l4xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32l4xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32l4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32l4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32l4xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32l4xx_hal_iwdg.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LCD_BIAS_1_2 : stm32l4xx_hal_lcd.h
  • LCD_BIAS_1_3 : stm32l4xx_hal_lcd.h
  • LCD_BIAS_1_4 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV1024 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV128 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV16 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV256 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV32 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV512 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV64 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV8 : stm32l4xx_hal_lcd.h
  • LCD_BLINKMODE_ALLSEG_ALLCOM : stm32l4xx_hal_lcd.h
  • LCD_BLINKMODE_OFF : stm32l4xx_hal_lcd.h
  • LCD_BLINKMODE_SEG0_ALLCOM : stm32l4xx_hal_lcd.h
  • LCD_BLINKMODE_SEG0_COM0 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_0 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_1 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_2 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_3 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_4 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_5 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_6 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_7 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_0 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_1 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_2 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_3 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_4 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_5 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_6 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_7 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_16 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_17 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_18 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_19 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_20 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_21 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_22 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_23 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_24 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_25 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_26 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_27 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_28 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_29 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_30 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_31 : stm32l4xx_hal_lcd.h
  • LCD_DUTY_1_2 : stm32l4xx_hal_lcd.h
  • LCD_DUTY_1_3 : stm32l4xx_hal_lcd.h
  • LCD_DUTY_1_4 : stm32l4xx_hal_lcd.h
  • LCD_DUTY_1_8 : stm32l4xx_hal_lcd.h
  • LCD_DUTY_STATIC : stm32l4xx_hal_lcd.h
  • LCD_FLAG_ENS : stm32l4xx_hal_lcd.h
  • LCD_FLAG_FCRSF : stm32l4xx_hal_lcd.h
  • LCD_FLAG_RDY : stm32l4xx_hal_lcd.h
  • LCD_FLAG_SOF : stm32l4xx_hal_lcd.h
  • LCD_FLAG_UDD : stm32l4xx_hal_lcd.h
  • LCD_FLAG_UDR : stm32l4xx_hal_lcd.h
  • LCD_HIGHDRIVE_DISABLE : stm32l4xx_hal_lcd.h
  • LCD_HIGHDRIVE_ENABLE : stm32l4xx_hal_lcd.h
  • LCD_IT_SOF : stm32l4xx_hal_lcd.h
  • LCD_IT_UDD : stm32l4xx_hal_lcd.h
  • LCD_MUXSEGMENT_DISABLE : stm32l4xx_hal_lcd.h
  • LCD_MUXSEGMENT_ENABLE : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_1 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_1024 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_128 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_16 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_16384 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_2 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_2048 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_256 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_32 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_32768 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_4 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_4096 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_512 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_64 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_8 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_8192 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_0 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_1 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_2 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_3 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_4 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_5 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_6 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_7 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER0 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER1 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER10 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER11 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER12 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER13 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER14 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER15 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER2 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER3 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER4 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER5 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER6 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER7 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER8 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER9 : stm32l4xx_hal_lcd.h
  • LCD_TIMEOUT_VALUE : stm32l4xx_hal_lcd.c
  • LCD_VOLTAGESOURCE_EXTERNAL : stm32l4xx_hal_lcd.h
  • LCD_VOLTAGESOURCE_INTERNAL : stm32l4xx_hal_lcd.h
  • LCD_WaitForSynchro() : stm32l4xx_hal_lcd.c
  • LL_ADC_AWD1 : stm32l4xx_ll_adc.h
  • LL_ADC_AWD2 : stm32l4xx_ll_adc.h
  • LL_ADC_AWD3 : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW : stm32l4xx_ll_adc.h
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_18 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_VBAT : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV1 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV10 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV12 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV128 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV16 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV2 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV256 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV32 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV4 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV6 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV64 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV8 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4 : stm32l4xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32l4xx_ll_adc.c
  • LL_ADC_CommonInit() : stm32l4xx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32l4xx_ll_adc.c
  • LL_ADC_ConfigAnalogWDThresholds() : stm32l4xx_ll_adc.h
  • LL_ADC_ConfigOverSamplingRatioShift() : stm32l4xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_LEFT : stm32l4xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32l4xx_ll_adc.h
  • LL_ADC_DeInit() : stm32l4xx_ll_adc.c
  • LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_DELAY_INTERNAL_REGUL_STAB_US : stm32l4xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32l4xx_ll_adc.h
  • LL_ADC_DELAY_VREFINT_STAB_US : stm32l4xx_ll_adc.h
  • LL_ADC_DIFFERENTIAL_ENDED : stm32l4xx_ll_adc.h
  • LL_ADC_Disable() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableDeepPowerDown() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableInternalRegulator() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32l4xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32l4xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI : stm32l4xx_ll_adc.h
  • LL_ADC_Enable() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableDeepPowerDown() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableInternalRegulator() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2 : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3 : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOC : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOC_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOC_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOS_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOS_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_OVR : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_OVR_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_OVR_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32l4xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32l4xx_ll_adc.h
  • LL_ADC_GetCalibrationFactor() : stm32l4xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32l4xx_ll_adc.h
  • LL_ADC_GetChannelSingleDiff() : stm32l4xx_ll_adc.h
  • LL_ADC_GetCommonClock() : stm32l4xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32l4xx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32l4xx_ll_adc.h
  • LL_ADC_GetLowPowerMode() : stm32l4xx_ll_adc.h
  • LL_ADC_GetMultiDMATransfer() : stm32l4xx_ll_adc.h
  • LL_ADC_GetMultimode() : stm32l4xx_ll_adc.h
  • LL_ADC_GetMultiTwoSamplingDelay() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOffsetChannel() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOffsetLevel() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOffsetState() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOverSamplingDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOverSamplingRatio() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOverSamplingScope() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOverSamplingShift() : stm32l4xx_ll_adc.h
  • LL_ADC_GetResolution() : stm32l4xx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32l4xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32l4xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32l4xx_ll_adc.h
  • LL_ADC_Init() : stm32l4xx_ll_adc.c
  • LL_ADC_INJ_ConfigQueueContext() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetQueueMode() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerEdge() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32l4xx_ll_adc.c
  • LL_ADC_INJ_IsConversionOngoing() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_IsStopConversionOngoing() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData10() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData6() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData8() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetQueueMode() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerEdge() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetTrigSource() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_StartConversion() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_StopConversion() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32l4xx_ll_adc.c
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_FALLING : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CC4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CC1 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CC1 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CC3 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CC4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_CC4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SW_START : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32l4xx_ll_adc.h
  • LL_ADC_IsDeepPowerDownEnabled() : stm32l4xx_ll_adc.h
  • LL_ADC_IsDisableOngoing() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_IsInternalRegulatorEnabled() : stm32l4xx_ll_adc.h
  • LL_ADC_IT_ADRDY : stm32l4xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32l4xx_ll_adc.h
  • LL_ADC_IT_AWD2 : stm32l4xx_ll_adc.h
  • LL_ADC_IT_AWD3 : stm32l4xx_ll_adc.h
  • LL_ADC_IT_EOC : stm32l4xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32l4xx_ll_adc.h
  • LL_ADC_IT_EOSMP : stm32l4xx_ll_adc.h
  • LL_ADC_IT_JEOC : stm32l4xx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32l4xx_ll_adc.h
  • LL_ADC_IT_JQOVF : stm32l4xx_ll_adc.h
  • LL_ADC_IT_OVR : stm32l4xx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT : stm32l4xx_ll_adc.h
  • LL_ADC_LP_MODE_NONE : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_ALTERN : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_SIMULT : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTERL : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIMULT : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_INDEPENDENT : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_MASTER : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_MASTER_SLAVE : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_EACH_ADC : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_SLAVE : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_1 : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_2 : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_3 : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_4 : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_ENABLE : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_1 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_2 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_3 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_4 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_5 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_6 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_7 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_8 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_NONE : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJECTED : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_RESUMED : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_128 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_16 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_2 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_256 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_32 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_4 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_64 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_8 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_REG_CONT : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_REG_DISCONT : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_NONE : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_1 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_2 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_3 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_4 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_5 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_6 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_7 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_8 : stm32l4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32l4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32l4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VBAT : stm32l4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32l4xx_ll_adc.h
  • LL_ADC_ReadReg : stm32l4xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32l4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_LIMITED : stm32l4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32l4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetOverrun() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetTriggerEdge() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32l4xx_ll_adc.c
  • LL_ADC_REG_IsConversionOngoing() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_IsStopConversionOngoing() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN : stm32l4xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_PRESERVED : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData10() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData6() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData8() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadMultiConversionData32() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetOverrun() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetTriggerEdge() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetTrigSource() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_StopConversion() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32l4xx_ll_adc.c
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_FALLING : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CC1 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CC2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CC3 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CC2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_CC4 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CC4 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_SW_START : stm32l4xx_ll_adc.h
  • LL_ADC_RESOLUTION_10B : stm32l4xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32l4xx_ll_adc.h
  • LL_ADC_RESOLUTION_6B : stm32l4xx_ll_adc.h
  • LL_ADC_RESOLUTION_8B : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_12CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_247CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_24CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_2CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_47CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_640CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_6CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_92CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SetAnalogWDMonitChannels() : stm32l4xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32l4xx_ll_adc.h
  • LL_ADC_SetCalibrationFactor() : stm32l4xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32l4xx_ll_adc.h
  • LL_ADC_SetChannelSingleDiff() : stm32l4xx_ll_adc.h
  • LL_ADC_SetCommonClock() : stm32l4xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32l4xx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32l4xx_ll_adc.h
  • LL_ADC_SetLowPowerMode() : stm32l4xx_ll_adc.h
  • LL_ADC_SetMultiDMATransfer() : stm32l4xx_ll_adc.h
  • LL_ADC_SetMultimode() : stm32l4xx_ll_adc.h
  • LL_ADC_SetMultiTwoSamplingDelay() : stm32l4xx_ll_adc.h
  • LL_ADC_SetOffset() : stm32l4xx_ll_adc.h
  • LL_ADC_SetOffsetState() : stm32l4xx_ll_adc.h
  • LL_ADC_SetOverSamplingDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_SetOverSamplingScope() : stm32l4xx_ll_adc.h
  • LL_ADC_SetResolution() : stm32l4xx_ll_adc.h
  • LL_ADC_SINGLE_ENDED : stm32l4xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32l4xx_ll_adc.h
  • LL_ADC_StructInit() : stm32l4xx_ll_adc.c
  • LL_ADC_WriteReg : stm32l4xx_ll_adc.h
  • LL_AHB1_GRP1_DisableClock() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FLASH : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM1 : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_TSC : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClock() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClock() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_ForceReset() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ADC : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_AES : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOA : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOB : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOC : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOD : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOE : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOF : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOG : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOH : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_OTGFS : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_RNG : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_SRAM2 : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClock() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClock() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_ForceReset() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_FMC : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_QSPI : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CAN1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DAC1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C3 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LCD : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_OPAMP : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_PWR : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI3 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM5 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM6 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM7 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART4 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART5 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_DisableClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_EnableClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_ForceReset() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_LPTIM2 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_LPUART1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_SWPMI1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_DFSDM1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_FW : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI2 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SDMMC1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SYSCFG : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM15 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM8 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_COMP_BLANKINGSRC_NONE : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC1 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC4 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 : stm32l4xx_ll_comp.h
  • LL_COMP_ConfigInputs() : stm32l4xx_ll_comp.h
  • LL_COMP_DeInit() : stm32l4xx_ll_comp.c
  • LL_COMP_DELAY_STARTUP_US : stm32l4xx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32l4xx_ll_comp.h
  • LL_COMP_Disable() : stm32l4xx_ll_comp.h
  • LL_COMP_Enable() : stm32l4xx_ll_comp.h
  • LL_COMP_GetCommonWindowMode() : stm32l4xx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32l4xx_ll_comp.h
  • LL_COMP_GetInputInverting() : stm32l4xx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32l4xx_ll_comp.h
  • LL_COMP_GetInputNonInverting() : stm32l4xx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32l4xx_ll_comp.h
  • LL_COMP_GetOutputBlankingSource() : stm32l4xx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32l4xx_ll_comp.h
  • LL_COMP_GetPowerMode() : stm32l4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32l4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32l4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32l4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32l4xx_ll_comp.h
  • LL_COMP_Init() : stm32l4xx_ll_comp.c
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH1 : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH2 : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO2 : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_1_2VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_1_4VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_3_4VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_DAC1 : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_DAC2 : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_IO1 : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_IO2 : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_IsEnabled() : stm32l4xx_ll_comp.h
  • LL_COMP_IsLocked() : stm32l4xx_ll_comp.h
  • LL_COMP_Lock() : stm32l4xx_ll_comp.h
  • LL_COMP_NONINVERTINGINPUT_IO1 : stm32l4xx_ll_comp.h
  • LL_COMP_NONINVERTINGINPUT_IO2 : stm32l4xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32l4xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32l4xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32l4xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32l4xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32l4xx_ll_comp.h
  • LL_COMP_POWERMODE_HIGHSPEED : stm32l4xx_ll_comp.h
  • LL_COMP_POWERMODE_MEDIUMSPEED : stm32l4xx_ll_comp.h
  • LL_COMP_POWERMODE_ULTRALOWPOWER : stm32l4xx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32l4xx_ll_comp.h
  • LL_COMP_ReadReg : stm32l4xx_ll_comp.h
  • LL_COMP_SetCommonWindowMode() : stm32l4xx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32l4xx_ll_comp.h
  • LL_COMP_SetInputInverting() : stm32l4xx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32l4xx_ll_comp.h
  • LL_COMP_SetInputNonInverting() : stm32l4xx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32l4xx_ll_comp.h
  • LL_COMP_SetOutputBlankingSource() : stm32l4xx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32l4xx_ll_comp.h
  • LL_COMP_SetPowerMode() : stm32l4xx_ll_comp.h
  • LL_COMP_StructInit() : stm32l4xx_ll_comp.c
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32l4xx_ll_comp.h
  • LL_COMP_WINDOWMODE_DISABLE : stm32l4xx_ll_comp.h
  • LL_COMP_WINDOWMODE_ENABLE : stm32l4xx_ll_comp.h
  • LL_COMP_WriteReg : stm32l4xx_ll_comp.h
  • LL_CPUID_GetConstant() : stm32l4xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32l4xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32l4xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32l4xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32l4xx_ll_cortex.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32l4xx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32l4xx_ll_crc.h
  • LL_CRC_DeInit() : stm32l4xx_ll_crc.c
  • LL_CRC_FeedData16() : stm32l4xx_ll_crc.h
  • LL_CRC_FeedData32() : stm32l4xx_ll_crc.h
  • LL_CRC_FeedData8() : stm32l4xx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32l4xx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32l4xx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32l4xx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32l4xx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32l4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32l4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32l4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32l4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32l4xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32l4xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32l4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32l4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32l4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32l4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32l4xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32l4xx_ll_crc.h
  • LL_CRC_ReadData16() : stm32l4xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32l4xx_ll_crc.h
  • LL_CRC_ReadData7() : stm32l4xx_ll_crc.h
  • LL_CRC_ReadData8() : stm32l4xx_ll_crc.h
  • LL_CRC_ReadReg : stm32l4xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32l4xx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32l4xx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32l4xx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32l4xx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32l4xx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32l4xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32l4xx_ll_crc.h
  • LL_CRC_WriteReg : stm32l4xx_ll_crc.h
  • LL_DAC_CHANNEL_1 : stm32l4xx_ll_dac.h
  • LL_DAC_CHANNEL_2 : stm32l4xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR1() : stm32l4xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR2() : stm32l4xx_ll_dac.h
  • LL_DAC_ConfigOutput() : stm32l4xx_ll_dac.h
  • LL_DAC_CONNECT_GPIO : stm32l4xx_ll_dac.h
  • LL_DAC_CONNECT_INTERNAL : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertData12LeftAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertData12RightAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertData8RightAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertDualData12LeftAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertDualData12RightAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertDualData8RightAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_DeInit() : stm32l4xx_ll_dac.c
  • LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US : stm32l4xx_ll_dac.h
  • LL_DAC_DELAY_VOLTAGE_SETTLING_US : stm32l4xx_ll_dac.h
  • LL_DAC_Disable() : stm32l4xx_ll_dac.h
  • LL_DAC_DisableDMAReq() : stm32l4xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR1() : stm32l4xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR2() : stm32l4xx_ll_dac.h
  • LL_DAC_DisableTrigger() : stm32l4xx_ll_dac.h
  • LL_DAC_DMA_GetRegAddr() : stm32l4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED : stm32l4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED : stm32l4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED : stm32l4xx_ll_dac.h
  • LL_DAC_Enable() : stm32l4xx_ll_dac.h
  • LL_DAC_EnableDMAReq() : stm32l4xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR1() : stm32l4xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR2() : stm32l4xx_ll_dac.h
  • LL_DAC_EnableTrigger() : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_BWST1 : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_BWST2 : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_CAL1 : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_CAL2 : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR1 : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR2 : stm32l4xx_ll_dac.h
  • LL_DAC_GetMode() : stm32l4xx_ll_dac.h
  • LL_DAC_GetOutputBuffer() : stm32l4xx_ll_dac.h
  • LL_DAC_GetOutputConnection() : stm32l4xx_ll_dac.h
  • LL_DAC_GetOutputMode() : stm32l4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldHoldTime() : stm32l4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldRefreshTime() : stm32l4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldSampleTime() : stm32l4xx_ll_dac.h
  • LL_DAC_GetTriggerSource() : stm32l4xx_ll_dac.h
  • LL_DAC_GetTrimmingValue() : stm32l4xx_ll_dac.h
  • LL_DAC_GetWaveAutoGeneration() : stm32l4xx_ll_dac.h
  • LL_DAC_GetWaveMode() : stm32l4xx_ll_dac.h
  • LL_DAC_GetWaveNoiseLFSR() : stm32l4xx_ll_dac.h
  • LL_DAC_GetWaveTriangleAmplitude() : stm32l4xx_ll_dac.h
  • LL_DAC_Init() : stm32l4xx_ll_dac.c
  • LL_DAC_IsActiveFlag_BWST1() : stm32l4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_BWST2() : stm32l4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL1() : stm32l4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL2() : stm32l4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR1() : stm32l4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR2() : stm32l4xx_ll_dac.h
  • LL_DAC_IsDMAReqEnabled() : stm32l4xx_ll_dac.h
  • LL_DAC_IsEnabled() : stm32l4xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR1() : stm32l4xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR2() : stm32l4xx_ll_dac.h
  • LL_DAC_IsTriggerEnabled() : stm32l4xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE1 : stm32l4xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE2 : stm32l4xx_ll_dac.h
  • LL_DAC_MODE_CALIBRATION : stm32l4xx_ll_dac.h
  • LL_DAC_MODE_NORMAL_OPERATION : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_DISABLE : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_ENABLE : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_GPIO : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_INTERNAL : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_NORMAL : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD : stm32l4xx_ll_dac.h
  • LL_DAC_ReadReg : stm32l4xx_ll_dac.h
  • LL_DAC_RESOLUTION_12B : stm32l4xx_ll_dac.h
  • LL_DAC_RESOLUTION_8B : stm32l4xx_ll_dac.h
  • LL_DAC_RetrieveOutputData() : stm32l4xx_ll_dac.h
  • LL_DAC_SetMode() : stm32l4xx_ll_dac.h
  • LL_DAC_SetOutputBuffer() : stm32l4xx_ll_dac.h
  • LL_DAC_SetOutputConnection() : stm32l4xx_ll_dac.h
  • LL_DAC_SetOutputMode() : stm32l4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldHoldTime() : stm32l4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldRefreshTime() : stm32l4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldSampleTime() : stm32l4xx_ll_dac.h
  • LL_DAC_SetTriggerSource() : stm32l4xx_ll_dac.h
  • LL_DAC_SetTrimmingValue() : stm32l4xx_ll_dac.h
  • LL_DAC_SetWaveAutoGeneration() : stm32l4xx_ll_dac.h
  • LL_DAC_SetWaveMode() : stm32l4xx_ll_dac.h
  • LL_DAC_SetWaveNoiseLFSR() : stm32l4xx_ll_dac.h
  • LL_DAC_SetWaveTriangleAmplitude() : stm32l4xx_ll_dac.h
  • LL_DAC_StructInit() : stm32l4xx_ll_dac.c
  • LL_DAC_TRIANGLE_AMPLITUDE_1 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1023 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_127 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_15 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_2047 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_255 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_3 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_31 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_4095 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_511 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_63 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_7 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE9 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM2_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM4_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM5_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM6_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM7_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM8_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_SOFTWARE : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_EXT_IT9 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_SOFTWARE : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM2_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM4_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM5_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM6_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM7_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM8_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TrigSWConversion() : stm32l4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE : stm32l4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NONE : stm32l4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE : stm32l4xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_NOISE : stm32l4xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_NONE : stm32l4xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_TRIANGLE : stm32l4xx_ll_dac.h
  • LL_DAC_WriteReg : stm32l4xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_CAN_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_FreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_LPTIM2_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_UnFreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_DisableDBGSleepMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_EnableDBGSleepMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32l4xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32l4xx_ll_system.h
  • LL_DBGMCU_GetTracePinAssignment() : stm32l4xx_ll_system.h
  • LL_DBGMCU_SetTracePinAssignment() : stm32l4xx_ll_system.h
  • LL_DBGMCU_TRACE_ASYNCH : stm32l4xx_ll_system.h
  • LL_DBGMCU_TRACE_NONE : stm32l4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE1 : stm32l4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE2 : stm32l4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE4 : stm32l4xx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32l4xx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32l4xx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_7 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI1() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI7() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32l4xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32l4xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32l4xx_ll_dma.h
  • LL_DMA_DeInit() : stm32l4xx_ll_dma.c
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32l4xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32l4xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32l4xx_ll_dma.h
  • LL_DMA_DisableChannel() : stm32l4xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32l4xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32l4xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32l4xx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32l4xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32l4xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32l4xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32l4xx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32l4xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32l4xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32l4xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32l4xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32l4xx_ll_dma.h
  • LL_DMA_GetMode() : stm32l4xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32l4xx_ll_dma.h
  • LL_DMA_GetPeriphRequest() : stm32l4xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_Init() : stm32l4xx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI7() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32l4xx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32l4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32l4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32l4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32l4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32l4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32l4xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32l4xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32l4xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32l4xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32l4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32l4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32l4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32l4xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32l4xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32l4xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32l4xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32l4xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32l4xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32l4xx_ll_dma.h
  • LL_DMA_ReadReg : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_0 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_1 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_2 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_3 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_4 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_5 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_6 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_7 : stm32l4xx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32l4xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32l4xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32l4xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32l4xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32l4xx_ll_dma.h
  • LL_DMA_SetMode() : stm32l4xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32l4xx_ll_dma.h
  • LL_DMA_SetPeriphRequest() : stm32l4xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32l4xx_ll_dma.h
  • LL_DMA_StructInit() : stm32l4xx_ll_dma.c
  • LL_DMA_WriteReg : stm32l4xx_ll_dma.h
  • LL_EXTI_ClearFlag_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_ClearFlag_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32l4xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableEvent_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableIT_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableEvent_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableIT_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_GenerateSWI_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_Init() : stm32l4xx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsActiveFlag_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_0 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_26 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_27 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_29 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_30 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_31 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_32 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_33 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_34 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_35 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_36 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_37 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_38 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_39 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_ALL_32_63 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32l4xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32l4xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32l4xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32l4xx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_ReadFlag_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32l4xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32l4xx_ll_exti.c
  • LL_EXTI_TRIGGER_FALLING : stm32l4xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32l4xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32l4xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32l4xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32l4xx_ll_exti.h
  • LL_FLASH_DisableDataCache() : stm32l4xx_ll_system.h
  • LL_FLASH_DisableDataCacheReset() : stm32l4xx_ll_system.h
  • LL_FLASH_DisableInstCache() : stm32l4xx_ll_system.h
  • LL_FLASH_DisableInstCacheReset() : stm32l4xx_ll_system.h
  • LL_FLASH_DisablePrefetch() : stm32l4xx_ll_system.h
  • LL_FLASH_DisableRunPowerDown() : stm32l4xx_ll_system.h
  • LL_FLASH_DisableSleepPowerDown() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableDataCache() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableDataCacheReset() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableInstCache() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableInstCacheReset() : stm32l4xx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableRunPowerDown() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableSleepPowerDown() : stm32l4xx_ll_system.h
  • LL_FLASH_GetLatency() : stm32l4xx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32l4xx_ll_system.h
  • LL_FLASH_LATENCY_0 : stm32l4xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32l4xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32l4xx_ll_system.h
  • LL_FLASH_LATENCY_3 : stm32l4xx_ll_system.h
  • LL_FLASH_LATENCY_4 : stm32l4xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32l4xx_ll_system.h
  • LL_GetFlashSize() : stm32l4xx_ll_utils.h
  • LL_GetPackageType() : stm32l4xx_ll_utils.h
  • LL_GetUID_Word0() : stm32l4xx_ll_utils.h
  • LL_GetUID_Word1() : stm32l4xx_ll_utils.h
  • LL_GetUID_Word2() : stm32l4xx_ll_utils.h
  • LL_GPIO_AF_0 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_11 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_12 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_13 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_14 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_15 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32l4xx_ll_gpio.h
  • LL_GPIO_DeInit() : stm32l4xx_ll_gpio.c
  • LL_GPIO_DisablePinAnalogControl() : stm32l4xx_ll_gpio.h
  • LL_GPIO_EnablePinAnalogControl() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetAFPin_0_7() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32l4xx_ll_gpio.h
  • LL_GPIO_Init() : stm32l4xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32l4xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32l4xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32l4xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32l4xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32l4xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32l4xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32l4xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32l4xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32l4xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32l4xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32l4xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32l4xx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32l4xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32l4xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32l4xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32l4xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32l4xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_FAST : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_VERY_HIGH : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_HIGH : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_LOW : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_MEDIUM : stm32l4xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32l4xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32l4xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32l4xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32l4xx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32l4xx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32l4xx_ll_cortex.h
  • LL_HANDLER_FAULT_BUS : stm32l4xx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32l4xx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32l4xx_ll_cortex.h
  • LL_I2C_ACK : stm32l4xx_ll_i2c.h
  • LL_I2C_AcknowledgeNextData() : stm32l4xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32l4xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32l4xx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32l4xx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32l4xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32l4xx_ll_i2c.c
  • LL_I2C_DIRECTION_READ : stm32l4xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32l4xx_ll_i2c.h
  • LL_I2C_Disable() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32l4xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32l4xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32l4xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32l4xx_ll_i2c.h
  • LL_I2C_Enable() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32l4xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32l4xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32l4xx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32l4xx_ll_i2c.h
  • LL_I2C_Init() : stm32l4xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32l4xx_ll_i2c.h
  • LL_I2C_NACK : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32l4xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32l4xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32l4xx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32l4xx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32l4xx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32l4xx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32l4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32l4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32l4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32l4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32l4xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32l4xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32l4xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32l4xx_ll_i2c.h
  • LL_Init1msTick() : stm32l4xx_ll_utils.c
  • LL_InitTick() : stm32l4xx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_KEY_ENABLE : stm32l4xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32l4xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32l4xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32l4xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32l4xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32l4xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32l4xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32l4xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32l4xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32l4xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32l4xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32l4xx_ll_cortex.h
  • LL_LPTIM_ClearFLAG_ARRM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_ARROK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFLAG_CMPM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPOK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_DOWN() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_EXTTRIG() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_UP() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_4 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_8 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_NONE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_EXTERNAL : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_INTERNAL : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ConfigClock() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ConfigOutput() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ConfigTrigger() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_EXTERNAL : stm32l4xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_INTERNAL : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DeInit() : stm32l4xx_ll_lptim.c
  • LL_LPTIM_Disable() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableEncoderMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARRM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARROK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPOK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_DOWN() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_EXTTRIG() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_UP() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableTimeout() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_Enable() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableEncoderMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARRM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARROK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPOK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_DOWN() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_EXTTRIG() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_UP() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableTimeout() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetAutoReload() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetClockFilter() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetClockPolarity() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetClockSource() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetCompare() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetCounter() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetCounterMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetEncoderMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetPolarity() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetPrescaler() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerFilter() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerPolarity() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerSource() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetUpdateMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetWaveform() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_ARRMIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_ARROKIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_CMPMIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_CMPOKIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_DOWNIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_EXTTRIGIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_UPIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_Init() : stm32l4xx_ll_lptim.c
  • LL_LPTIM_INPUT1_SRC_COMP1 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_GPIO : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_GPIO : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARRM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARROK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPOK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_DOWN() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_EXTTRIG() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_UP() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabled() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledEncoderMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARRM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARROK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPOK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_DOWN() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_EXTTRIG() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_UP() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledTimeout() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_ARRM : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_ARROK : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPM : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPOK : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_DOWN : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_EXTTRIG : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_UP : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_ONESHOT : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV1 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV128 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV16 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV32 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV4 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV64 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV8 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ReadReg : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetAutoReload() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetClockSource() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetCompare() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetCounterMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetEncoderMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetInput1Src() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetInput2Src() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetPolarity() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetPrescaler() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetUpdateMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetWaveform() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_StartCounter() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_StructInit() : stm32l4xx_ll_lptim.c
  • LL_LPTIM_TRIG_FILTER_2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_4 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_8 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_NONE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP1 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_GPIO : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TrigSw() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD : stm32l4xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_WriteReg : stm32l4xx_ll_lptim.h
  • LL_LPUART_ADDRESS_DETECT_4B : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ADDRESS_DETECT_7B : stm32l4xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_NEGATIVE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_POSITIVE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_BITORDER_LSBFIRST : stm32l4xx_ll_lpuart.h
  • LL_LPUART_BITORDER_MSBFIRST : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_CM() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_FE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_IDLE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_nCTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_NE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_ORE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_PE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TC() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_WKUP() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ConfigCharacter() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ConfigNodeAddress() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_CMIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_IDLEIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_PEIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_RXNEIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_TCIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_TXEIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR3_CTSIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR3_EIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR3_WUFIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_7B : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_8B : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_9B : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_HIGH : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_LOW : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DeInit() : stm32l4xx_ll_lpuart.c
  • LL_LPUART_DIRECTION_NONE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_RX : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX_RX : stm32l4xx_ll_lpuart.h
  • LL_LPUART_Disable() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableCTSHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDEMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionRx() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionTx() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDMADeactOnRxErr() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_RX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_TX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableHalfDuplex() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableInStopMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CM() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_ERROR() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_IDLE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_PE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TC() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_WKUP() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableMuteMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableOverrunDetect() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableRTSHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DMA_GetRegAddr() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_RECEIVE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_TRANSMIT : stm32l4xx_ll_lpuart.h
  • LL_LPUART_Enable() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableCTSHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDEMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionRx() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionTx() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDMADeactOnRxErr() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_RX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_TX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableHalfDuplex() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableInStopMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CM() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_ERROR() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_IDLE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_PE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TC() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_WKUP() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableMuteMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableOverrunDetect() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableRTSHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetBaudRate() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetBinaryDataLogic() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetDataWidth() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetDEAssertionTime() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetDEDeassertionTime() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetDESignalPolarity() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddress() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddressLen() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetParity() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetRXPinLevel() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetStopBitsLength() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetTransferBitOrder() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetTransferDirection() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetTXPinLevel() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetTXRXSwap() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetWakeUpMethod() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetWKUPType() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_CTS : stm32l4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_NONE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS : stm32l4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS_CTS : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_CMCF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_CTSCF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_FECF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_IDLECF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_NCF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_ORECF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_PECF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_TCCF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_WUCF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_Init() : stm32l4xx_ll_lpuart.c
  • LL_LPUART_IsActiveFlag_BUSY() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CM() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_FE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_IDLE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_nCTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_NE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_ORE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_PE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_REACK() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RWU() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_SBK() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TC() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TEACK() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_WKUP() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabled() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDEMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMADeactOnRxErr() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_RX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_TX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledHalfDuplex() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledInStopMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CM() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_ERROR() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_IDLE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_PE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TC() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_WKUP() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledMuteMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledOverrunDetect() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_BUSY : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_CMF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_CTS : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_CTSIF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_FE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_IDLE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_NE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_ORE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_PE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_REACK : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_RWU : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_RXNE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_SBKF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_TC : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_TEACK : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_TXE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_WUF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_PARITY_EVEN : stm32l4xx_ll_lpuart.h
  • LL_LPUART_PARITY_NONE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_PARITY_ODD : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ReadReg : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ReceiveData8() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ReceiveData9() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_RequestBreakSending() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_RequestEnterMuteMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_RequestRxDataFlush() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_INVERTED : stm32l4xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_STANDARD : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetBaudRate() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetBinaryDataLogic() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetDataWidth() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetDEAssertionTime() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetDEDeassertionTime() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetDESignalPolarity() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetParity() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetRXPinLevel() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetStopBitsLength() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetTransferBitOrder() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetTransferDirection() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetTXPinLevel() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetTXRXSwap() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetWakeUpMethod() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetWKUPType() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_1 : stm32l4xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_2 : stm32l4xx_ll_lpuart.h
  • LL_LPUART_StructInit() : stm32l4xx_ll_lpuart.c
  • LL_LPUART_TransmitData8() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_TransmitData9() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_INVERTED : stm32l4xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_STANDARD : stm32l4xx_ll_lpuart.h
  • LL_LPUART_TXRX_STANDARD : stm32l4xx_ll_lpuart.h
  • LL_LPUART_TXRX_SWAPPED : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ADDRESSMARK : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_IDLELINE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_ADDRESS : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_RXNE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_STARTBIT : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WriteReg : stm32l4xx_ll_lpuart.h
  • LL_MAX_DELAY : stm32l4xx_ll_utils.h
  • LL_mDelay() : stm32l4xx_ll_utils.c
  • LL_MPU_ACCESS_BUFFERABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ConfigRegion() : stm32l4xx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32l4xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32l4xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32l4xx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32l4xx_ll_cortex.h
  • LL_MPU_Disable() : stm32l4xx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32l4xx_ll_cortex.h
  • LL_MPU_Enable() : stm32l4xx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32l4xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128B : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32B : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64B : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32l4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32l4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32l4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32l4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32l4xx_ll_cortex.h
  • LL_OPAMP_DeInit() : stm32l4xx_ll_opamp.c
  • LL_OPAMP_Disable() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_Enable() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetCalibrationSelection() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetCommonPowerRange() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetFunctionalMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetInputInverting() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetInputNonInverting() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetPGAGain() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetPowerMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingValue() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_Init() : stm32l4xx_ll_opamp.c
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO0 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO1 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO0 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INVERTINGINPUT_CONNECT_NO : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INVERTINGINPUT_IO0 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INVERTINGINPUT_IO1 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_IsCalibrationOutputSet() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_IsEnabled() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_MODE_CALIBRATION : stm32l4xx_ll_opamp.h
  • LL_OPAMP_MODE_FOLLOWER : stm32l4xx_ll_opamp.h
  • LL_OPAMP_MODE_FUNCTIONAL : stm32l4xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA : stm32l4xx_ll_opamp.h
  • LL_OPAMP_MODE_STANDALONE : stm32l4xx_ll_opamp.h
  • LL_OPAMP_NONINVERTINGINPUT_DAC_CH : stm32l4xx_ll_opamp.h
  • LL_OPAMP_NONINVERTINGINPUT_IO0 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_16 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_2 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_4 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_8 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_LOWPOWER : stm32l4xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_NORMAL : stm32l4xx_ll_opamp.h
  • LL_OPAMP_POWERSUPPLY_RANGE_HIGH : stm32l4xx_ll_opamp.h
  • LL_OPAMP_POWERSUPPLY_RANGE_LOW : stm32l4xx_ll_opamp.h
  • LL_OPAMP_ReadReg : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetCalibrationSelection() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetCommonPowerRange() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetFunctionalMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetInputInverting() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetInputNonInverting() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetInvertingInput() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetNonInvertingInput() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetPGAGain() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetPowerMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingValue() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_StructInit() : stm32l4xx_ll_opamp.c
  • LL_OPAMP_TRIMMING_FACTORY : stm32l4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS : stm32l4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS : stm32l4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_USER : stm32l4xx_ll_opamp.h
  • LL_OPAMP_WriteReg : stm32l4xx_ll_opamp.h
  • LL_PLL_ConfigSystemClock_HSE() : stm32l4xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32l4xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_MSI() : stm32l4xx_ll_utils.c
  • LL_PWR_BATT_CHARG_RESISTOR_5K : stm32l4xx_ll_pwr.h
  • LL_PWR_BATT_CHARGRESISTOR_1_5K : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_SB() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU1() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU2() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU3() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU4() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU5() : stm32l4xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32l4xx_ll_pwr.c
  • LL_PWR_DisableBatteryCharging() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableBkUpAccess() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullDown() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullUp() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableInternWU() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableLowPowerRunMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisablePUPDCfg() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisablePVM() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableSRAM2Retention() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableVddIO2() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableVddUSB() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableBatteryCharging() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullDown() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullUp() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableInternWU() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableLowPowerRunMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnablePUPDCfg() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnablePVM() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableSRAM2Retention() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableVddIO2() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableVddUSB() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnterLowPowerRunMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_ExitLowPowerRunMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_GetBattChargResistor() : stm32l4xx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32l4xx_ll_pwr.h
  • LL_PWR_GetRegulVoltageScaling() : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_A : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_B : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_0 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_1 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_10 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_11 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_12 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_13 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_14 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_15 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_2 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_3 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_4 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_5 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_6 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_7 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_8 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_9 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_C : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_D : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_E : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_F : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_G : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_H : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_InternWU() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO1() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO2() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO3() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO4() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPF() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPS() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SB() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOSF() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU1() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU2() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU3() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU4() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU5() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledBatteryCharging() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullDown() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullUp() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledInternWU() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledLowPowerRunMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledPUPDCfg() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledPVM() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledSRAM2Retention() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledVddIO2() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledVddUSB() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsWakeUpPinPolarityLow() : stm32l4xx_ll_pwr.h
  • LL_PWR_MODE_SHUTDOWN : stm32l4xx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32l4xx_ll_pwr.h
  • LL_PWR_MODE_STOP0 : stm32l4xx_ll_pwr.h
  • LL_PWR_MODE_STOP1 : stm32l4xx_ll_pwr.h
  • LL_PWR_MODE_STOP2 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_1_62V : stm32l4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_2_2V : stm32l4xx_ll_pwr.h
  • LL_PWR_PVM_VDDIO2_0_9V : stm32l4xx_ll_pwr.h
  • LL_PWR_PVM_VDDUSB_1_2V : stm32l4xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32l4xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE1 : stm32l4xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE2 : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CSBF : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF1 : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF2 : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF3 : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF4 : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF5 : stm32l4xx_ll_pwr.h
  • LL_PWR_SetBattChargResistor() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetRegulVoltageScaling() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityHigh() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityLow() : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_SBF : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUF1 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUF2 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUF3 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUF4 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUF5 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUFI : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_PVDO : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO1 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO2 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO3 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO4 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_REGLPF : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_REGLPS : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_VOSF : stm32l4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32l4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32l4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32l4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN4 : stm32l4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN5 : stm32l4xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32l4xx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLLSAI2 : stm32l4xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_CSSC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_HSERDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_HSIRDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_LSECSSC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_LSERDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_LSIRDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_MSIRDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_PLLRDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_PLLSAI1RDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_PLLSAI2RDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_HSERDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_HSIRDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_LSECSSIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_LSERDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_LSIRDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_MSIRDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_PLLRDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_PLLSAI1RDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_PLLSAI2RDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_CSSF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_HSERDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_HSIRDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_LSECSSF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_LSERDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_LSIRDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_MSIRDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_PLLRDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_PLLSAI1RDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_PLLSAI2RDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_MSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLSAI1RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLSAI2RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32l4xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_BORRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_FWRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_OBLRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32l4xx_ll_rcc.c
  • LL_RCC_DFSDM1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_DFSDM1_CLKSOURCE_PCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_DFSDM1_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_HSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_MSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLSAI1RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLSAI2RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_MSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLSAI1RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLSAI2RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32l4xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetClkAfterWakeFromStop() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetDFSDMClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetDFSDMClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetLPTIMClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetLPTIMClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetLPUARTClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetLPUARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetRNGClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetRNGClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetRTCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetSAIClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetSAIClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetSDMMCClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetSDMMCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetSWPMIClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetSWPMIClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetUARTClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetUARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetUSARTClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_DisableAutoFromStop() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_DisableInStopMode() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_EnableAutoFromStop() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_EnableInStopMode() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_BORRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_FWRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_MSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_OBLRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLSAI1RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLSAI2RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_MSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLSAI1RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLSAI2RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_GetSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_SetSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_DisableCSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_EnableCSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_IsCSSDetected() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32l4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32l4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32l4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32l4xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_16 : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_DisablePLLMode() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_EnablePLLMode() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_EnableRangeSelection() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_GetCalibration() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_GetCalibTrimming() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_GetRange() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_GetRangeAfterStandby() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_IsEnabledRangeSelect() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_SetCalibTrimming() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_SetRange() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_SetRangeAfterStandby() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_0 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_10 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_11 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_3 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_5 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_9 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGESEL_RUN : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGESEL_STANDBY : stm32l4xx_ll_rcc.h
  • LL_RCC_MSISRANGE_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSISRANGE_5 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSISRANGE_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSISRANGE_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32l4xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SYS() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SYS() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetDivider() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetN() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetP() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetQ() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetR() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_3 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_5 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_17 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetN() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetP() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetQ() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetR() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_17 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_ConfigDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_ConfigDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_DisableDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_DisableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_EnableDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_EnableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_GetN() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_GetP() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_GetR() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2P_DIV_17 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2P_DIV_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2R_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2R_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2R_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2R_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32l4xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32l4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32 : stm32l4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32l4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PIN : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI2 : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI2_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI2_CLKSOURCE_PIN : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI2_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI2_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI2_CLKSOURCE_PLLSAI2 : stm32l4xx_ll_rcc.h
  • LL_RCC_SDMMC1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_SDMMC1_CLKSOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SDMMC1_CLKSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_SDMMC1_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetClkAfterWakeFromStop() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetDFSDMClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetLPTIMClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetLPUARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetRNGClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetSAIClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetSDMMCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetSWPMIClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetUARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_STOP_WAKEUPCLOCK_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_STOP_WAKEUPCLOCK_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SWPMI1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_SWPMI1_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SWPMI1_CLKSOURCE_PCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_UART5_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_UART5_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_UART5_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_UART5_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_UART5_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_PCLK2 : stm32l4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32l4xx_ll_rcc.h
  • LL_RNG_ClearFlag_CEIS() : stm32l4xx_ll_rng.h
  • LL_RNG_ClearFlag_SEIS() : stm32l4xx_ll_rng.h
  • LL_RNG_CR_IE : stm32l4xx_ll_rng.h
  • LL_RNG_DeInit() : stm32l4xx_ll_rng.c
  • LL_RNG_Disable() : stm32l4xx_ll_rng.h
  • LL_RNG_DisableIT() : stm32l4xx_ll_rng.h
  • LL_RNG_Enable() : stm32l4xx_ll_rng.h
  • LL_RNG_EnableIT() : stm32l4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_CECS() : stm32l4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_CEIS() : stm32l4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_DRDY() : stm32l4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SECS() : stm32l4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SEIS() : stm32l4xx_ll_rng.h
  • LL_RNG_IsEnabled() : stm32l4xx_ll_rng.h
  • LL_RNG_IsEnabledIT() : stm32l4xx_ll_rng.h
  • LL_RNG_ReadRandData32() : stm32l4xx_ll_rng.h
  • LL_RNG_ReadReg : stm32l4xx_ll_rng.h
  • LL_RNG_SR_CECS : stm32l4xx_ll_rng.h
  • LL_RNG_SR_CEIS : stm32l4xx_ll_rng.h
  • LL_RNG_SR_DRDY : stm32l4xx_ll_rng.h
  • LL_RNG_SR_SECS : stm32l4xx_ll_rng.h
  • LL_RNG_SR_SEIS : stm32l4xx_ll_rng.h
  • LL_RNG_WriteReg : stm32l4xx_ll_rng.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32l4xx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32l4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32l4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32l4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32l4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_ConfigTime() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32l4xx_ll_rtc.c
  • LL_RTC_ALMA_MASK_ALL : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_ConfigTime() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32l4xx_ll_rtc.c
  • LL_RTC_ALMB_MASK_ALL : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32l4xx_ll_rtc.h
  • LL_RTC_BAK_GetRegister() : stm32l4xx_ll_rtc.h
  • LL_RTC_BAK_SetRegister() : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR10 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR11 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR12 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR13 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR14 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR15 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR16 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR17 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR18 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR19 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR20 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR21 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR22 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR23 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR24 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR25 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR26 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR27 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR28 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR29 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR30 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR31 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR5 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR6 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR7 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR8 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR9 : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITS() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32l4xx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32l4xx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32l4xx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32l4xx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32l4xx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_DeInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_DisableInitMode() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP1() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP2() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP3() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableOutRemap() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP1() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP2() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP3() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableOutRemap() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32l4xx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32l4xx_ll_rtc.c
  • LL_RTC_FORMAT_BCD : stm32l4xx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32l4xx_ll_rtc.h
  • LL_RTC_GetAlarmOutEvent() : stm32l4xx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32l4xx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32l4xx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32l4xx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32l4xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32l4xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32l4xx_ll_rtc.h
  • LL_RTC_Init() : stm32l4xx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITS() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP1() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP2() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP3() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_ALRAF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_ALRAWF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_ALRBF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_ALRBWF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_INITF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_INITS : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_ITSF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_RECALPF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_RSF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_SHPF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_TAMP1F : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_TAMP2F : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_TAMP3F : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_TSF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_TSOVF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_WUTF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_WUTWF : stm32l4xx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32l4xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32l4xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32l4xx_ll_rtc.h
  • LL_RTC_ReadReg : stm32l4xx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32l4xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32l4xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32l4xx_ll_rtc.h
  • LL_RTC_StructInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_TAMPCR_TAMP1IE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMP2IE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMP3IE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMPIE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_1 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_Disable() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableEraseBKP() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableEraseBKP() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32l4xx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32l4xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_DisableInternalEvent() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_EnableInternalEvent() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32l4xx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32l4xx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WriteReg : stm32l4xx_ll_rtc.h
  • LL_SetSystemCoreClock() : stm32l4xx_ll_utils.c
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32l4xx_ll_spi.h
  • LL_SPI_ClearFlag_CRCERR() : stm32l4xx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32l4xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32l4xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32l4xx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32l4xx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32l4xx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32l4xx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32l4xx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32l4xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32l4xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DeInit() : stm32l4xx_ll_spi.c
  • LL_SPI_Disable() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32l4xx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32l4xx_ll_spi.h
  • LL_SPI_DMA_PARITY_EVEN : stm32l4xx_ll_spi.h
  • LL_SPI_DMA_PARITY_ODD : stm32l4xx_ll_spi.h
  • LL_SPI_Enable() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32l4xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32l4xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32l4xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32l4xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32l4xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32l4xx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32l4xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32l4xx_ll_spi.h
  • LL_SPI_GetDMAParity_RX() : stm32l4xx_ll_spi.h
  • LL_SPI_GetDMAParity_TX() : stm32l4xx_ll_spi.h
  • LL_SPI_GetMode() : stm32l4xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32l4xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32l4xx_ll_spi.h
  • LL_SPI_GetRxFIFOLevel() : stm32l4xx_ll_spi.h
  • LL_SPI_GetRxFIFOThreshold() : stm32l4xx_ll_spi.h
  • LL_SPI_GetStandard() : stm32l4xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32l4xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32l4xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32l4xx_ll_spi.h
  • LL_SPI_GetTxFIFOLevel() : stm32l4xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32l4xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32l4xx_ll_spi.h
  • LL_SPI_Init() : stm32l4xx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32l4xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32l4xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32l4xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32l4xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32l4xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32l4xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32l4xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32l4xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32l4xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32l4xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32l4xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32l4xx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32l4xx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32l4xx_ll_spi.h
  • LL_SPI_ReadReg : stm32l4xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32l4xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_EMPTY : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_HALF_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_QUARTER_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_HALF : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_QUARTER : stm32l4xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32l4xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32l4xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32l4xx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32l4xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32l4xx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32l4xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32l4xx_ll_spi.h
  • LL_SPI_SetDMAParity_RX() : stm32l4xx_ll_spi.h
  • LL_SPI_SetDMAParity_TX() : stm32l4xx_ll_spi.h
  • LL_SPI_SetMode() : stm32l4xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32l4xx_ll_spi.h
  • LL_SPI_SetRxFIFOThreshold() : stm32l4xx_ll_spi.h
  • LL_SPI_SetStandard() : stm32l4xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32l4xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32l4xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32l4xx_ll_spi.h
  • LL_SPI_SR_BSY : stm32l4xx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32l4xx_ll_spi.h
  • LL_SPI_SR_FRE : stm32l4xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32l4xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32l4xx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32l4xx_ll_spi.h
  • LL_SPI_SR_TXE : stm32l4xx_ll_spi.h
  • LL_SPI_SR_UDR : stm32l4xx_ll_spi.h
  • LL_SPI_StructInit() : stm32l4xx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32l4xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32l4xx_ll_spi.h
  • LL_SPI_TX_FIFO_EMPTY : stm32l4xx_ll_spi.h
  • LL_SPI_TX_FIFO_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_TX_FIFO_HALF_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_TX_FIFO_QUARTER_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_WriteReg : stm32l4xx_ll_spi.h
  • LL_SWPMI_Activate() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXBER() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXBF() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXOVR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_SR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TC() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TXBE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TXUNR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_Deactivate() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DeInit() : stm32l4xx_ll_swpmi.c
  • LL_SWPMI_DisableDMAReq_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableDMAReq_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXBER() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXBF() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXOVR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_SR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TC() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TXBE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TXUNR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableLoopback() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableTXBypass() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DMA_GetRegAddr() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DMA_REG_DATA_RECEIVE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DMA_REG_DATA_TRANSMIT : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableDMAReq_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableDMAReq_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXBER() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXBF() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXOVR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_SR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TC() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TXBE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TXUNR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableLoopback() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableTXBypass() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_GetBitRatePrescaler() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_GetReceiveFrameLength() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_GetReceptionMode() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_GetTransmissionMode() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_GetVoltageClass() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXBERF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXBFF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXOVRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CSRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTCF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTXBEF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTXUNRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_RIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_RXBERIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_RXBFIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_RXOVRIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_SRIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_TCIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_TIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_TXBEIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_TXUNRIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_Init() : stm32l4xx_ll_swpmi.c
  • LL_SWPMI_IsActivated() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_DEACT() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXBER() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXBF() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXNE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXOVR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_SR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_SUSP() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TC() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXBE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXUNR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledDMAReq_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledDMAReq_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXBER() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXBF() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXOVR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_SR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TC() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TXBE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TXUNR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_DEACTF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXBERF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXBFF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXNE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXOVRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_SRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_SUSP : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_TCF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXBEF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXUNRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ReadReg : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ReceiveData32() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_RequestDeactivation() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SetBitRatePrescaler() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SetReceptionMode() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SetTransmissionMode() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SetVoltageClass() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_StructInit() : stm32l4xx_ll_swpmi.c
  • LL_SWPMI_SW_BUFFER_RX_MULTI : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_RX_SINGLE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_TX_MULTI : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_TX_SINGLE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_TransmitData32() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_VOLTAGE_CLASS_B : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_VOLTAGE_CLASS_C : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_WriteReg : stm32l4xx_ll_swpmi.h
  • LL_SYSCFG_BANKMODE_BANK1 : stm32l4xx_ll_system.h
  • LL_SYSCFG_BANKMODE_BANK2 : stm32l4xx_ll_system.h
  • LL_SYSCFG_ClearFlag_SP() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableAnalogBooster() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_DZC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IDC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IOC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IXC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_OFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_UFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableAnalogBooster() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableFirewall() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_DZC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IDC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IOC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IXC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_OFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_UFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableSRAM2Erase() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableSRAM2PageWRP() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE0 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE1 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE10 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE11 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE12 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE13 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE14 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE15 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE2 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE3 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE4 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE5 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE6 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE7 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE8 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE9 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTA : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTB : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTC : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTD : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTE : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTF : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTG : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTH : stm32l4xx_ll_system.h
  • LL_SYSCFG_GetEXTISource() : stm32l4xx_ll_system.h
  • LL_SYSCFG_GetFlashBankMode() : stm32l4xx_ll_system.h
  • LL_SYSCFG_GetRemapMemory() : stm32l4xx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SP() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledFirewall() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_DZC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IDC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IOC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IXC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_OFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_UFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsSRAM2EraseOngoing() : stm32l4xx_ll_system.h
  • LL_SYSCFG_LockSRAM2WRP() : stm32l4xx_ll_system.h
  • LL_SYSCFG_REMAP_FLASH : stm32l4xx_ll_system.h
  • LL_SYSCFG_REMAP_FMC : stm32l4xx_ll_system.h
  • LL_SYSCFG_REMAP_QUADSPI : stm32l4xx_ll_system.h
  • LL_SYSCFG_REMAP_SRAM : stm32l4xx_ll_system.h
  • LL_SYSCFG_REMAP_SYSTEMFLASH : stm32l4xx_ll_system.h
  • LL_SYSCFG_SetEXTISource() : stm32l4xx_ll_system.h
  • LL_SYSCFG_SetFlashBankMode() : stm32l4xx_ll_system.h
  • LL_SYSCFG_SetRemapMemory() : stm32l4xx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE0 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE1 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE10 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE11 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE12 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE13 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE14 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE15 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE16 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE17 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE18 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE19 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE2 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE20 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE21 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE22 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE23 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE24 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE25 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE26 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE27 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE28 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE29 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE3 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE30 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE31 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE4 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE5 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE6 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE7 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE8 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE9 : stm32l4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_ECC : stm32l4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_LOCKUP : stm32l4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32l4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM2_PARITY : stm32l4xx_ll_system.h
  • LL_SYSCFG_UnlockSRAM2WRP() : stm32l4xx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_DisableIT() : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32l4xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32l4xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32l4xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_HIGH : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_LOW : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP1 : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKIN : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_DF1BK : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N2 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N4 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_HIGH : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_LOW : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N2 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N4 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN2 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32l4xx_ll_tim.h
  • LL_TIM_CC_DisableChannel() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32l4xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32l4xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32l4xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32l4xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH5 : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH6 : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC5() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC6() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_SYSBRK() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32l4xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32l4xx_ll_tim.h
  • LL_TIM_ConfigBRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32l4xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32l4xx_ll_tim.h
  • LL_TIM_DeInit() : stm32l4xx_ll_tim.c
  • LL_TIM_DIER_BIE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32l4xx_ll_tim.h
  • LL_TIM_DisableAllOutputs() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableBreakInputSource() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableBRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableUIFRemap() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR5 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR6 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR1 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR2 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR3 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableBreakInputSource() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableBRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableUIFRemap() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32l4xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32l4xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32l4xx_ll_tim.c
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32l4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32l4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP1 : stm32l4xx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_ETRSOURCE_LEGACY : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32l4xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32l4xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32l4xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32l4xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32l4xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32l4xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32l4xx_ll_tim.h
  • LL_TIM_GROUPCH5_NONE : stm32l4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC1REFC : stm32l4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC2REFC : stm32l4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC3REFC : stm32l4xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32l4xx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32l4xx_ll_tim.c
  • LL_TIM_IC_Config() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32l4xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32l4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32l4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32l4xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32l4xx_ll_tim.c
  • LL_TIM_ICPSC_DIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32l4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32l4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32l4xx_ll_tim.h
  • LL_TIM_Init() : stm32l4xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_BRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC5() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC6() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_SYSBRK() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32l4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32l4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32l4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32l4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32l4xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH5() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH6() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32l4xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH5() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH6() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32l4xx_ll_tim.c
  • LL_TIM_OCIDLESTATE_HIGH : stm32l4xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM1 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM2 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM1 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM2 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32l4xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32l4xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32l4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_ETR : stm32l4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_NC : stm32l4xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32l4xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32l4xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32l4xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32l4xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32l4xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32l4xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32l4xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32l4xx_ll_tim.h
  • LL_TIM_ReadReg : stm32l4xx_ll_tim.h
  • LL_TIM_SetAutoReload() : stm32l4xx_ll_tim.h
  • LL_TIM_SetBreakInputSourcePolarity() : stm32l4xx_ll_tim.h
  • LL_TIM_SetCH5CombinedChannels() : stm32l4xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32l4xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32l4xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32l4xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32l4xx_ll_tim.h
  • LL_TIM_SetETRSource() : stm32l4xx_ll_tim.h
  • LL_TIM_SetOCRefClearInputSource() : stm32l4xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32l4xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32l4xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32l4xx_ll_tim.h
  • LL_TIM_SetRemap() : stm32l4xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32l4xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32l4xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32l4xx_ll_tim.h
  • LL_TIM_SetTriggerOutput2() : stm32l4xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32l4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32l4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32l4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32l4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32l4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32l4xx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC5IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC6IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_SBIF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32l4xx_ll_tim.h
  • LL_TIM_StructInit() : stm32l4xx_ll_tim.c
  • LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_ENCODERMODE_TIM2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_ENCODERMODE_TIM3 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_ENCODERMODE_TIM4 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_LSE : stm32l4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSE : stm32l4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSI : stm32l4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_RTC : stm32l4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_HSE_32 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MCO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MSI : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_NC : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC3_RMP_NC : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_ETR_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_ETR_RMP_LSE : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC2_RMP_NC : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC3_RMP_NC : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_CC1F : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_ENABLE : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC1 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC2 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC3 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISINGFALLING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC6 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC6_RISINGFALLING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_RESET : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_UPDATE : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32l4xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32l4xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32l4xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32l4xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32l4xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32l4xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32l4xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32l4xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32l4xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32l4xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32l4xx_ll_tim.h
  • LL_TIM_WriteReg : stm32l4xx_ll_tim.h
  • LL_USART_ADDRESS_DETECT_4B : stm32l4xx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32l4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32l4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32l4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32l4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32l4xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32l4xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32l4xx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32l4xx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_CM() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32l4xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32l4xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32l4xx_ll_usart.h
  • LL_USART_ClockInit() : stm32l4xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32l4xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32l4xx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_RXNEIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_TXEIE : stm32l4xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32l4xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32l4xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32l4xx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32l4xx_ll_usart.h
  • LL_USART_DATAWIDTH_7B : stm32l4xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32l4xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32l4xx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32l4xx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32l4xx_ll_usart.h
  • LL_USART_DeInit() : stm32l4xx_ll_usart.c
  • LL_USART_DIRECTION_NONE : stm32l4xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32l4xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32l4xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32l4xx_ll_usart.h
  • LL_USART_Disable() : stm32l4xx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32l4xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32l4xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32l4xx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_RXNE() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_TXE() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32l4xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32l4xx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32l4xx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32l4xx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32l4xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32l4xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32l4xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32l4xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32l4xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32l4xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32l4xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32l4xx_ll_usart.h
  • LL_USART_Enable() : stm32l4xx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32l4xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32l4xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32l4xx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_RXNE() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_TXE() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32l4xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32l4xx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32l4xx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32l4xx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32l4xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32l4xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32l4xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32l4xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32l4xx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32l4xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32l4xx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32l4xx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32l4xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32l4xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32l4xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32l4xx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32l4xx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32l4xx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32l4xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32l4xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32l4xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32l4xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32l4xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32l4xx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32l4xx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32l4xx_ll_usart.h
  • LL_USART_GetParity() : stm32l4xx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32l4xx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32l4xx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32l4xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32l4xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32l4xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32l4xx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32l4xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32l4xx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32l4xx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32l4xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32l4xx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32l4xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32l4xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32l4xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32l4xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32l4xx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_FECF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_NCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_PECF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32l4xx_ll_usart.h
  • LL_USART_Init() : stm32l4xx_ll_usart.c
  • LL_USART_IRDA_POWER_LOW : stm32l4xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABR() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32l4xx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32l4xx_ll_usart.h
  • LL_USART_ISR_CMF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_CTS : stm32l4xx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_FE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_NE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_ORE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_PE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_REACK : stm32l4xx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_RWU : stm32l4xx_ll_usart.h
  • LL_USART_ISR_RXNE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_TC : stm32l4xx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32l4xx_ll_usart.h
  • LL_USART_ISR_TXE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_WUF : stm32l4xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32l4xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32l4xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32l4xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32l4xx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32l4xx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32l4xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32l4xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32l4xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32l4xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32l4xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32l4xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32l4xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32l4xx_ll_usart.h
  • LL_USART_ReadReg : stm32l4xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32l4xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32l4xx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32l4xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32l4xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32l4xx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32l4xx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32l4xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32l4xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32l4xx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32l4xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32l4xx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32l4xx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32l4xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32l4xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32l4xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32l4xx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32l4xx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32l4xx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32l4xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32l4xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32l4xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32l4xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32l4xx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32l4xx_ll_usart.h
  • LL_USART_SetParity() : stm32l4xx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32l4xx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32l4xx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32l4xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32l4xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32l4xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32l4xx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32l4xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32l4xx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32l4xx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32l4xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32l4xx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32l4xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32l4xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32l4xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32l4xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32l4xx_ll_usart.h
  • LL_USART_StructInit() : stm32l4xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32l4xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32l4xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32l4xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32l4xx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32l4xx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32l4xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32l4xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32l4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32l4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32l4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32l4xx_ll_usart.h
  • LL_USART_WriteReg : stm32l4xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32l4xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_BGA132 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP100 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP144_CSP72 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP48 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP64 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA100 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA64 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFQFPN32 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFQFPN48 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP49 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP64 : stm32l4xx_ll_utils.h
  • LL_VREFBUF_Disable() : stm32l4xx_ll_system.h
  • LL_VREFBUF_DisableHIZ() : stm32l4xx_ll_system.h
  • LL_VREFBUF_Enable() : stm32l4xx_ll_system.h
  • LL_VREFBUF_EnableHIZ() : stm32l4xx_ll_system.h
  • LL_VREFBUF_GetTrimming() : stm32l4xx_ll_system.h
  • LL_VREFBUF_GetVoltageScaling() : stm32l4xx_ll_system.h
  • LL_VREFBUF_IsVREFReady() : stm32l4xx_ll_system.h
  • LL_VREFBUF_SetTrimming() : stm32l4xx_ll_system.h
  • LL_VREFBUF_SetVoltageScaling() : stm32l4xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE0 : stm32l4xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE1 : stm32l4xx_ll_system.h
  • LL_WWDG_CFR_EWI : stm32l4xx_ll_wwdg.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32l4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32l4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32l4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32l4xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32l4xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32l4xx_ll_wwdg.h
  • LPM_L0 : stm32l4xx_hal_pcd.h
  • LPM_L1 : stm32l4xx_hal_pcd.h
  • LPM_L2 : stm32l4xx_hal_pcd.h
  • LPM_L3 : stm32l4xx_hal_pcd.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32l4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32l4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32l4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32l4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1_COMP2 : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP2 : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32l4xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32l4xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32l4xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32l4xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32l4xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32l4xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32l4xx_hal_lptim.h
  • LPTIM_IT_UP : stm32l4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32l4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32l4xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32l4xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32l4xx_hal_lptim.h
  • LPUART_BRR_MASK : stm32l4xx_ll_lpuart.h
  • LPUART_BRR_MIN_VALUE : stm32l4xx_ll_lpuart.h
  • LPUART_LPUARTDIV_FREQ_MUL : stm32l4xx_ll_lpuart.h
  • LPUART_POSITION_CR1_DEAT : stm32l4xx_ll_lpuart.h
  • LPUART_POSITION_CR1_DEDT : stm32l4xx_ll_lpuart.h
  • LPUART_POSITION_CR2_ADD : stm32l4xx_ll_lpuart.h
  • LSCO_GPIO_PORT : stm32l4xx_hal_rcc_ex.c
  • LSCO_PIN : stm32l4xx_hal_rcc_ex.c
  • LSE_STARTUP_TIMEOUT : stm32l4xx_hal_conf.h
  • LSE_VALUE : stm32l4xx_ll_rcc.h , stm32l4xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • LSI_VALUE : stm32l4xx_ll_rcc.h , stm32l4xx_hal_conf.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
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  • e
  • f
  • g
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAX_NBYTE_SIZE : stm32l4xx_hal_i2c.c , stm32l4xx_hal_smbus.c
  • MC_ADDRESS : stm32l4xx_hal_nor.h
  • MCO1_GPIO_PORT : stm32l4xx_hal_rcc.c
  • MCO1_PIN : stm32l4xx_hal_rcc.c
  • MEMRMP_OFFSET : stm32l4xx_hal.c
  • MPU_ACCESS_BUFFERABLE : stm32l4xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32l4xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32l4xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32l4xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32l4xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32l4xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32l4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32l4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32l4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32l4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32l4xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32l4xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32l4xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32l4xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32l4xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32l4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32l4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32l4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32l4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32l4xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32l4xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32l4xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32l4xx_hal_cortex.h
  • MSI_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • MSI_VALUE : stm32l4xx_hal_conf.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NAND_AddressIncrement() : stm32l4xx_hal_nand.c
  • NAND_BUSY : stm32l4xx_hal_nand.h
  • NAND_CMD_AREA_A : stm32l4xx_hal_nand.h
  • NAND_CMD_AREA_B : stm32l4xx_hal_nand.h
  • NAND_CMD_AREA_C : stm32l4xx_hal_nand.h
  • NAND_CMD_AREA_TRUE1 : stm32l4xx_hal_nand.h
  • NAND_CMD_ERASE0 : stm32l4xx_hal_nand.h
  • NAND_CMD_ERASE1 : stm32l4xx_hal_nand.h
  • NAND_CMD_LOCK_STATUS : stm32l4xx_hal_nand.h
  • NAND_CMD_READID : stm32l4xx_hal_nand.h
  • NAND_CMD_RESET : stm32l4xx_hal_nand.h
  • NAND_CMD_STATUS : stm32l4xx_hal_nand.h
  • NAND_CMD_WRITE0 : stm32l4xx_hal_nand.h
  • NAND_CMD_WRITE_TRUE1 : stm32l4xx_hal_nand.h
  • NAND_DEVICE : stm32l4xx_hal_nand.h
  • NAND_ERROR : stm32l4xx_hal_nand.h
  • NAND_INVALID_ADDRESS : stm32l4xx_hal_nand.h
  • NAND_READY : stm32l4xx_hal_nand.h
  • NAND_TIMEOUT_ERROR : stm32l4xx_hal_nand.h
  • NAND_VALID_ADDRESS : stm32l4xx_hal_nand.h
  • NAND_WRITE_TIMEOUT : stm32l4xx_hal_nand.h
  • NOR_ADDR_SHIFT : stm32l4xx_hal_nor.h
  • NOR_CMD_ADDRESS_FIFTH : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST_CFI : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_FOURTH : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_SECOND : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_SIXTH : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_THIRD : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_AUTO_SELECT : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_BLOCK_ERASE : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_CFI : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_ERASE : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_FIRST : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_PROGRAM : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_READ_RESET : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_SECOND : stm32l4xx_hal_nor.c
  • NOR_MASK_STATUS_DQ5 : stm32l4xx_hal_nor.c
  • NOR_MASK_STATUS_DQ6 : stm32l4xx_hal_nor.c
  • NOR_MEMORY_16B : stm32l4xx_hal_nor.h
  • NOR_MEMORY_8B : stm32l4xx_hal_nor.h
  • NOR_MEMORY_ADRESS1 : stm32l4xx_hal_nor.h
  • NOR_MEMORY_ADRESS2 : stm32l4xx_hal_nor.h
  • NOR_MEMORY_ADRESS3 : stm32l4xx_hal_nor.h
  • NOR_MEMORY_ADRESS4 : stm32l4xx_hal_nor.h
  • NOR_WRITE : stm32l4xx_hal_nor.h
  • NVIC_PRIORITYGROUP_0 : stm32l4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32l4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32l4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32l4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32l4xx_hal_cortex.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB_BFB2_DISABLE : stm32l4xx_hal_flash.h
  • OB_BFB2_ENABLE : stm32l4xx_hal_flash.h
  • OB_BOOT1_SRAM : stm32l4xx_hal_flash.h
  • OB_BOOT1_SYSTEM : stm32l4xx_hal_flash.h
  • OB_BOR_LEVEL_0 : stm32l4xx_hal_flash.h
  • OB_BOR_LEVEL_1 : stm32l4xx_hal_flash.h
  • OB_BOR_LEVEL_2 : stm32l4xx_hal_flash.h
  • OB_BOR_LEVEL_3 : stm32l4xx_hal_flash.h
  • OB_BOR_LEVEL_4 : stm32l4xx_hal_flash.h
  • OB_DUALBANK_DUAL : stm32l4xx_hal_flash.h
  • OB_DUALBANK_SINGLE : stm32l4xx_hal_flash.h
  • OB_IWDG_HW : stm32l4xx_hal_flash.h
  • OB_IWDG_STDBY_FREEZE : stm32l4xx_hal_flash.h
  • OB_IWDG_STDBY_RUN : stm32l4xx_hal_flash.h
  • OB_IWDG_STOP_FREEZE : stm32l4xx_hal_flash.h
  • OB_IWDG_STOP_RUN : stm32l4xx_hal_flash.h
  • OB_IWDG_SW : stm32l4xx_hal_flash.h
  • OB_PCROP_RDP_ERASE : stm32l4xx_hal_flash.h
  • OB_PCROP_RDP_NOT_ERASE : stm32l4xx_hal_flash.h
  • OB_RDP_LEVEL_0 : stm32l4xx_hal_flash.h
  • OB_RDP_LEVEL_1 : stm32l4xx_hal_flash.h
  • OB_RDP_LEVEL_2 : stm32l4xx_hal_flash.h
  • OB_SHUTDOWN_NORST : stm32l4xx_hal_flash.h
  • OB_SHUTDOWN_RST : stm32l4xx_hal_flash.h
  • OB_SRAM2_PARITY_DISABLE : stm32l4xx_hal_flash.h
  • OB_SRAM2_PARITY_ENABLE : stm32l4xx_hal_flash.h
  • OB_SRAM2_RST_ERASE : stm32l4xx_hal_flash.h
  • OB_SRAM2_RST_NOT_ERASE : stm32l4xx_hal_flash.h
  • OB_STANDBY_NORST : stm32l4xx_hal_flash.h
  • OB_STANDBY_RST : stm32l4xx_hal_flash.h
  • OB_STOP_NORST : stm32l4xx_hal_flash.h
  • OB_STOP_RST : stm32l4xx_hal_flash.h
  • OB_USER_BFB2 : stm32l4xx_hal_flash.h
  • OB_USER_BOR_LEV : stm32l4xx_hal_flash.h
  • OB_USER_DUALBANK : stm32l4xx_hal_flash.h
  • OB_USER_IWDG_STDBY : stm32l4xx_hal_flash.h
  • OB_USER_IWDG_STOP : stm32l4xx_hal_flash.h
  • OB_USER_IWDG_SW : stm32l4xx_hal_flash.h
  • OB_USER_nBOOT1 : stm32l4xx_hal_flash.h
  • OB_USER_nRST_SHDW : stm32l4xx_hal_flash.h
  • OB_USER_nRST_STDBY : stm32l4xx_hal_flash.h
  • OB_USER_nRST_STOP : stm32l4xx_hal_flash.h
  • OB_USER_SRAM2_PE : stm32l4xx_hal_flash.h
  • OB_USER_SRAM2_RST : stm32l4xx_hal_flash.h
  • OB_USER_WWDG_SW : stm32l4xx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAA : stm32l4xx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAB : stm32l4xx_hal_flash.h
  • OB_WRPAREA_BANK2_AREAA : stm32l4xx_hal_flash.h
  • OB_WRPAREA_BANK2_AREAB : stm32l4xx_hal_flash.h
  • OB_WWDG_HW : stm32l4xx_hal_flash.h
  • OB_WWDG_SW : stm32l4xx_hal_flash.h
  • OC1Config() : stm32l4xx_ll_tim.c
  • OC2Config() : stm32l4xx_ll_tim.c
  • OC3Config() : stm32l4xx_ll_tim.c
  • OC4Config() : stm32l4xx_ll_tim.c
  • OC5Config() : stm32l4xx_ll_tim.c
  • OC6Config() : stm32l4xx_ll_tim.c
  • OFFSET_TAB_CCMRx : stm32l4xx_ll_tim.h
  • OPAMP_CSR_INIT_MASK_FOLLOWER : stm32l4xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_PGA : stm32l4xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_STANDALONE : stm32l4xx_hal_opamp.c
  • OPAMP_CSR_RESET_BITS : stm32l4xx_hal_opamp.c
  • OPAMP_CSR_RESET_VALUE : stm32l4xx_hal_opamp.c
  • OPAMP_FACTORYTRIMMING_DUMMY : stm32l4xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_N : stm32l4xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_P : stm32l4xx_hal_opamp.h
  • OPAMP_FOLLOWER_MODE : stm32l4xx_hal_opamp.h
  • OPAMP_INPUT_NONINVERTING : stm32l4xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_CONNECT_NO : stm32l4xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO0 : stm32l4xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO1 : stm32l4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_DAC_CH : stm32l4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO0 : stm32l4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_16 : stm32l4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_2 : stm32l4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_4 : stm32l4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_8 : stm32l4xx_hal_opamp.h
  • OPAMP_PGA_MODE : stm32l4xx_hal_opamp.h
  • OPAMP_POWERMODE_CSR_BIT_MASK : stm32l4xx_ll_opamp.h
  • OPAMP_POWERMODE_LOWPOWER : stm32l4xx_hal_opamp.h
  • OPAMP_POWERMODE_LPOTR_REGOFFSET : stm32l4xx_ll_opamp.h
  • OPAMP_POWERMODE_NORMAL : stm32l4xx_hal_opamp.h
  • OPAMP_POWERMODE_OTR_REGOFFSET : stm32l4xx_ll_opamp.h
  • OPAMP_POWERMODE_OTR_REGOFFSET_MASK : stm32l4xx_ll_opamp.h
  • OPAMP_POWERSUPPLY_HIGH : stm32l4xx_hal_opamp.h
  • OPAMP_POWERSUPPLY_LOW : stm32l4xx_hal_opamp.h
  • OPAMP_STANDALONE_MODE : stm32l4xx_hal_opamp.h
  • OPAMP_TRIMMING_DELAY : stm32l4xx_hal_opamp.h
  • OPAMP_TRIMMING_FACTORY : stm32l4xx_hal_opamp.h
  • OPAMP_TRIMMING_SELECT_MASK : stm32l4xx_ll_opamp.h
  • OPAMP_TRIMMING_USER : stm32l4xx_hal_opamp.h
  • OPAMP_TRIMMING_VALUE_MASK : stm32l4xx_ll_opamp.h
  • OPTIONBYTE_PCROP : stm32l4xx_hal_flash.h
  • OPTIONBYTE_RDP : stm32l4xx_hal_flash.h
  • OPTIONBYTE_USER : stm32l4xx_hal_flash.h
  • OPTIONBYTE_WRP : stm32l4xx_hal_flash.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PACKAGE_BASE_ADDRESS : stm32l4xx_ll_utils.h
  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_CONTACT_DETECTION : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_ERROR : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_MsgTypeDef : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32l4xx_hal_pcd_ex.h
  • PCD_EPTypeDef : stm32l4xx_hal_pcd.h
  • PCD_InitTypeDef : stm32l4xx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32l4xx_hal_pcd_ex.h
  • PCD_LPM_L1_ACTIVE : stm32l4xx_hal_pcd_ex.h
  • PCD_LPM_MsgTypeDef : stm32l4xx_hal_pcd_ex.h
  • PCD_LPM_StateTypeDef : stm32l4xx_hal_pcd.h
  • PCD_MAX : stm32l4xx_hal_pcd.c
  • PCD_MIN : stm32l4xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32l4xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32l4xx_hal_pcd.h
  • PCD_StateTypeDef : stm32l4xx_hal_pcd.h
  • PCD_TypeDef : stm32l4xx_hal_pcd.h
  • PCD_WriteEmptyTxFifo() : stm32l4xx_hal_pcd.c
  • pFlash : stm32l4xx_hal_flash.c , stm32l4xx_hal_flash_ex.c
  • PLL_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c , stm32l4xx_hal_rcc_ex.c
  • PLLSAI1_TIMEOUT_VALUE : stm32l4xx_hal_rcc_ex.c
  • PLLSAI2_TIMEOUT_VALUE : stm32l4xx_hal_rcc_ex.c
  • PREFETCH_ENABLE : stm32l4xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32l4xx_hal_pwr.c
  • PVD_MODE_EVT : stm32l4xx_hal_pwr.c
  • PVD_MODE_IT : stm32l4xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32l4xx_hal_pwr.c
  • PVM_FALLING_EDGE : stm32l4xx_hal_pwr_ex.c
  • PVM_MODE_EVT : stm32l4xx_hal_pwr_ex.c
  • PVM_MODE_IT : stm32l4xx_hal_pwr_ex.c
  • PVM_RISING_EDGE : stm32l4xx_hal_pwr_ex.c
  • PWR_BATTERY_CHARGING_DISABLE : stm32l4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_ENABLE : stm32l4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32l4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32l4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVD : stm32l4xx_hal_pwr.h
  • PWR_EVENT_LINE_PVM1 : stm32l4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM2 : stm32l4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM3 : stm32l4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM4 : stm32l4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVD : stm32l4xx_hal_pwr.h
  • PWR_EXTI_LINE_PVM1 : stm32l4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM2 : stm32l4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM3 : stm32l4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM4 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_PVDO : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO1 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO2 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO3 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO4 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_REGLPF : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_REGLPS : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_SB : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_SETTING_DELAY_US : stm32l4xx_hal_pwr_ex.c
  • PWR_FLAG_VOSF : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WU : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF1 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF2 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF3 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF4 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF5 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUFI : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_A : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_B : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_0 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_1 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_10 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_11 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_12 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_13 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_14 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_15 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_2 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_3 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_4 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_5 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_6 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_7 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_8 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_9 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_C : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_D : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_E : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_F : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_G : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_H : stm32l4xx_hal_pwr_ex.h
  • PWR_LOWPOWERREGULATOR_ON : stm32l4xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32l4xx_hal_pwr.h
  • PWR_PORTH_AVAILABLE_PINS : stm32l4xx_hal_pwr_ex.c
  • PWR_PVD_MODE_EVENT_FALLING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32l4xx_hal_pwr.h
  • PWR_PVM_1 : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_2 : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_3 : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_4 : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_FALLING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING_FALLING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_FALLING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING_FALLING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_NORMAL : stm32l4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32l4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32l4xx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32l4xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32l4xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32l4xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32l4xx_hal_pwr.h
  • PWR_WAKEUP_PIN1 : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32l4xx_hal_pwr_ex.h
  • PWR_WUP_POLARITY_SHIFT : stm32l4xx_hal_pwr_ex.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- q -

  • QSPI_ADDRESS_16_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_1_LINE : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_24_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_2_LINES : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_32_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_4_LINES : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_8_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_NONE : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_16_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_1_LINE : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_24_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_2_LINES : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_32_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_4_LINES : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_8_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_NONE : stm32l4xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_DISABLE : stm32l4xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_ENABLE : stm32l4xx_hal_qspi.h
  • QSPI_CLOCK_MODE_0 : stm32l4xx_hal_qspi.h
  • QSPI_CLOCK_MODE_3 : stm32l4xx_hal_qspi.h
  • QSPI_Config() : stm32l4xx_hal_qspi.c
  • QSPI_CS_HIGH_TIME_1_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_2_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_3_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_4_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_5_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_6_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_7_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_8_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_DATA_1_LINE : stm32l4xx_hal_qspi.h
  • QSPI_DATA_2_LINES : stm32l4xx_hal_qspi.h
  • QSPI_DATA_4_LINES : stm32l4xx_hal_qspi.h
  • QSPI_DATA_NONE : stm32l4xx_hal_qspi.h
  • QSPI_DDR_HHC_ANALOG_DELAY : stm32l4xx_hal_qspi.h
  • QSPI_DDR_MODE_DISABLE : stm32l4xx_hal_qspi.h
  • QSPI_DDR_MODE_ENABLE : stm32l4xx_hal_qspi.h
  • QSPI_DMAAbortCplt() : stm32l4xx_hal_qspi.c
  • QSPI_DMAError() : stm32l4xx_hal_qspi.c
  • QSPI_DMARxCplt() : stm32l4xx_hal_qspi.c
  • QSPI_DMARxHalfCplt() : stm32l4xx_hal_qspi.c
  • QSPI_DMATxCplt() : stm32l4xx_hal_qspi.c
  • QSPI_DMATxHalfCplt() : stm32l4xx_hal_qspi.c
  • QSPI_FLAG_BUSY : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_FT : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_SM : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_TC : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_TE : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_TO : stm32l4xx_hal_qspi.h
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING : stm32l4xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ : stm32l4xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE : stm32l4xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED : stm32l4xx_hal_qspi.c
  • QSPI_INSTRUCTION_1_LINE : stm32l4xx_hal_qspi.h
  • QSPI_INSTRUCTION_2_LINES : stm32l4xx_hal_qspi.h
  • QSPI_INSTRUCTION_4_LINES : stm32l4xx_hal_qspi.h
  • QSPI_INSTRUCTION_NONE : stm32l4xx_hal_qspi.h
  • QSPI_IT_FT : stm32l4xx_hal_qspi.h
  • QSPI_IT_SM : stm32l4xx_hal_qspi.h
  • QSPI_IT_TC : stm32l4xx_hal_qspi.h
  • QSPI_IT_TE : stm32l4xx_hal_qspi.h
  • QSPI_IT_TO : stm32l4xx_hal_qspi.h
  • QSPI_MATCH_MODE_AND : stm32l4xx_hal_qspi.h
  • QSPI_MATCH_MODE_OR : stm32l4xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_HALFCYCLE : stm32l4xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_NONE : stm32l4xx_hal_qspi.h
  • QSPI_SIOO_INST_EVERY_CMD : stm32l4xx_hal_qspi.h
  • QSPI_SIOO_INST_ONLY_FIRST_CMD : stm32l4xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_DISABLE : stm32l4xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_ENABLE : stm32l4xx_hal_qspi.h
  • QSPI_WaitFlagStateUntilTimeout() : stm32l4xx_hal_qspi.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCC_ADCCLKSOURCE_NONE : stm32l4xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLLSAI2 : stm32l4xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_HCLK : stm32l4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32l4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32l4xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32l4xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32l4xx_hal_rcc.h
  • RCC_DFSDM1CLKSOURCE_PCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_DFSDM1CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_EXTI_LINE_LSECSS : stm32l4xx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_FWRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_LSECSSD : stm32l4xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32l4xx_hal_rcc.h
  • RCC_FLAG_MSIRDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_OBLRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_PLLSAI1RDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_PLLSAI2RDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_RMVF : stm32l4xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32l4xx_hal_rcc.h
  • RCC_GetHCLKClockFreq() : stm32l4xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32l4xx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32l4xx_ll_rcc.c
  • RCC_GetSystemClockFreq() : stm32l4xx_ll_rcc.c
  • RCC_HCLK_DIV1 : stm32l4xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32l4xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32l4xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32l4xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32l4xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32l4xx_hal_rcc.h
  • RCC_HSE_OFF : stm32l4xx_hal_rcc.h
  • RCC_HSE_ON : stm32l4xx_hal_rcc.h
  • RCC_HSI48_OFF : stm32l4xx_hal_rcc.h
  • RCC_HSI_OFF : stm32l4xx_hal_rcc.h
  • RCC_HSI_ON : stm32l4xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32l4xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32l4xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32l4xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32l4xx_hal_rcc.h
  • RCC_IT_LSECSS : stm32l4xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32l4xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32l4xx_hal_rcc.h
  • RCC_IT_MSIRDY : stm32l4xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32l4xx_hal_rcc.h
  • RCC_IT_PLLSAI1RDY : stm32l4xx_hal_rcc.h
  • RCC_IT_PLLSAI2RDY : stm32l4xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32l4xx_hal_rcc.h
  • RCC_LSE_OFF : stm32l4xx_hal_rcc.h
  • RCC_LSE_ON : stm32l4xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32l4xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32l4xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32l4xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32l4xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32l4xx_hal_rcc.h
  • RCC_LSI_OFF : stm32l4xx_hal_rcc.h
  • RCC_LSI_ON : stm32l4xx_hal_rcc.h
  • RCC_MCO : stm32l4xx_hal_rcc.h
  • RCC_MCO1 : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSI : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_MSI : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_SYSCLK : stm32l4xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32l4xx_hal_rcc.h
  • RCC_MCODIV_16 : stm32l4xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32l4xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32l4xx_hal_rcc.h
  • RCC_MCODIV_8 : stm32l4xx_hal_rcc.h
  • RCC_MSI_OFF : stm32l4xx_hal_rcc.h
  • RCC_MSI_ON : stm32l4xx_hal_rcc.h
  • RCC_MSICALIBRATION_DEFAULT : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_0 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_1 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_10 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_11 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_2 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_3 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_4 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_5 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_6 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_7 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_8 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_9 : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_MSI : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32l4xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DFSDM1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM2 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI2 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SDMMC1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SWPMI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART4 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART5 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32l4xx_hal_rcc_ex.h
  • RCC_PLL_48M1CLK : stm32l4xx_hal_rcc.h
  • RCC_PLL_GetFreqDomain_48M() : stm32l4xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SAI() : stm32l4xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SYS() : stm32l4xx_ll_rcc.c
  • RCC_PLL_NONE : stm32l4xx_hal_rcc.h
  • RCC_PLL_OFF : stm32l4xx_hal_rcc.h
  • RCC_PLL_ON : stm32l4xx_hal_rcc.h
  • RCC_PLL_OSCSOURCE_CONFIG : stm32l4xx_hal_rcc.c
  • RCC_PLL_SAI3CLK : stm32l4xx_hal_rcc.h
  • RCC_PLL_SYSCLK : stm32l4xx_hal_rcc.h
  • RCC_PLLP_DIV17 : stm32l4xx_hal_rcc.h
  • RCC_PLLP_DIV7 : stm32l4xx_hal_rcc.h
  • RCC_PLLQ_DIV2 : stm32l4xx_hal_rcc.h
  • RCC_PLLQ_DIV4 : stm32l4xx_hal_rcc.h
  • RCC_PLLQ_DIV6 : stm32l4xx_hal_rcc.h
  • RCC_PLLQ_DIV8 : stm32l4xx_hal_rcc.h
  • RCC_PLLR_DIV2 : stm32l4xx_hal_rcc.h
  • RCC_PLLR_DIV4 : stm32l4xx_hal_rcc.h
  • RCC_PLLR_DIV6 : stm32l4xx_hal_rcc.h
  • RCC_PLLR_DIV8 : stm32l4xx_hal_rcc.h
  • RCC_PLLSAI1_48M2CLK : stm32l4xx_hal_rcc.h
  • RCC_PLLSAI1_ADC1CLK : stm32l4xx_hal_rcc.h
  • RCC_PLLSAI1_GetFreqDomain_48M() : stm32l4xx_ll_rcc.c
  • RCC_PLLSAI1_GetFreqDomain_ADC() : stm32l4xx_ll_rcc.c
  • RCC_PLLSAI1_GetFreqDomain_SAI() : stm32l4xx_ll_rcc.c
  • RCC_PLLSAI1_SAI1CLK : stm32l4xx_hal_rcc.h
  • RCC_PLLSAI2_ADC2CLK : stm32l4xx_hal_rcc.h
  • RCC_PLLSAI2_GetFreqDomain_ADC() : stm32l4xx_ll_rcc.c
  • RCC_PLLSAI2_GetFreqDomain_SAI() : stm32l4xx_ll_rcc.c
  • RCC_PLLSAI2_SAI2CLK : stm32l4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32l4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32l4xx_hal_rcc.h
  • RCC_PLLSOURCE_MSI : stm32l4xx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32l4xx_hal_rcc.h
  • RCC_POSITION_HPRE : stm32l4xx_ll_rcc.h
  • RCC_POSITION_HSICAL : stm32l4xx_ll_rcc.h
  • RCC_POSITION_HSITRIM : stm32l4xx_ll_rcc.h
  • RCC_POSITION_MSICAL : stm32l4xx_ll_rcc.h
  • RCC_POSITION_MSITRIM : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLM : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLN : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLP : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLQ : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLR : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI1N : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI1P : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI1Q : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI1R : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI2N : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI2P : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI2R : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PPRE1 : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PPRE2 : stm32l4xx_ll_rcc.h
  • RCC_RNGCLKSOURCE_MSI : stm32l4xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_NONE : stm32l4xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32l4xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32l4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32l4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32l4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NO_CLK : stm32l4xx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_PIN : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLLSAI2 : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PIN : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLL : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLLSAI2 : stm32l4xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_MSI : stm32l4xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_NONE : stm32l4xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_PLL : stm32l4xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_SetFlashLatencyFromMSIRange() : stm32l4xx_hal_rcc.c
  • RCC_STOP_WAKEUPCLOCK_HSI : stm32l4xx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_MSI : stm32l4xx_hal_rcc.h
  • RCC_SWPMI1CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_SWPMI1CLKSOURCE_PCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_MSI : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_MSI : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32l4xx_hal_rcc.h
  • RCC_UART4CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK2 : stm32l4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_MSI : stm32l4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_NONE : stm32l4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32l4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCCEx_PLLSAI1_Config() : stm32l4xx_hal_rcc_ex.c
  • RCCEx_PLLSAI2_Config() : stm32l4xx_hal_rcc_ex.c
  • RISING_EDGE : stm32l4xx_hal_gpio.c
  • RNG_FLAG_CECS : stm32l4xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32l4xx_hal_rng.h
  • RNG_FLAG_SECS : stm32l4xx_hal_rng.h
  • RNG_IT_CEI : stm32l4xx_hal_rng.h
  • RNG_IT_DRDY : stm32l4xx_hal_rng.h
  • RNG_IT_SEI : stm32l4xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32l4xx_hal_rng.c
  • RTC_ALARM_A : stm32l4xx_hal_rtc.h
  • RTC_ALARM_B : stm32l4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32l4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32l4xx_hal_rtc.h
  • RTC_ALL_TAMPER_INTERRUPT : stm32l4xx_hal_rtc_ex.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32l4xx_ll_rtc.c
  • RTC_Bcd2ToByte() : stm32l4xx_hal_rtc.c
  • RTC_BKP_DR0 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR20 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR21 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR22 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR23 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR24 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR25 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR26 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR27 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR28 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR29 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR30 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR31 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32l4xx_hal_rtc_ex.h
  • RTC_ByteToBcd2() : stm32l4xx_hal_rtc.c
  • RTC_CALIBOUTPUT_1HZ : stm32l4xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32l4xx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32l4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32l4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32l4xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32l4xx_hal_rtc.h
  • RTC_EnterInitMode() : stm32l4xx_hal_rtc.c
  • RTC_EXTI_LINE_ALARM_EVENT : stm32l4xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32l4xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32l4xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32l4xx_hal_rtc.h
  • RTC_FLAG_ITSF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32l4xx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32l4xx_hal_rtc.h
  • RTC_FLAG_TAMP3F : stm32l4xx_hal_rtc.h
  • RTC_FLAG_TSF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32l4xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32l4xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32l4xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32l4xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32l4xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32l4xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32l4xx_hal_rtc.h
  • RTC_INIT_MASK : stm32l4xx_hal_rtc.h , stm32l4xx_ll_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32l4xx_ll_rtc.c
  • RTC_IT_ALRA : stm32l4xx_hal_rtc.h
  • RTC_IT_ALRB : stm32l4xx_hal_rtc.h
  • RTC_IT_TAMP : stm32l4xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32l4xx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32l4xx_hal_rtc.h
  • RTC_IT_TAMP3 : stm32l4xx_hal_rtc.h
  • RTC_IT_TS : stm32l4xx_hal_rtc.h
  • RTC_IT_WUT : stm32l4xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32l4xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32l4xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32l4xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32l4xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32l4xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32l4xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32l4xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32l4xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32l4xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32l4xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32l4xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32l4xx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32l4xx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32l4xx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32l4xx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32l4xx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32l4xx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32l4xx_hal_rtc_ex.h
  • RTC_OUTPUT_ALARMB : stm32l4xx_hal_rtc_ex.h
  • RTC_OUTPUT_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32l4xx_hal_rtc_ex.h
  • RTC_POSITION_ALMA_DT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_DU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_HT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_HU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_MASKSS : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_MT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_MU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_ST : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_SU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_DT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_DU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_HT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_HU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_MASKSS : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_MT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_MU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_ST : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_SU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_DT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_DU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_MT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_MU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_WDU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_YT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_YU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_PRER_PREDIV_A : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_HT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_HU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_MT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_MU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_ST : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_SU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TS_HU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TS_MNU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TS_MU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TS_WDU : stm32l4xx_ll_rtc.h
  • RTC_RSF_MASK : stm32l4xx_hal_rtc.h , stm32l4xx_ll_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32l4xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32l4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32l4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32l4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32l4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32l4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32l4xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32l4xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32l4xx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32l4xx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32l4xx_ll_rtc.c
  • RTC_TAMPCR_MASK : stm32l4xx_hal_rtc_ex.c
  • RTC_TAMPER1_INTERRUPT : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER2_INTERRUPT : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER3_INTERRUPT : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_1 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32l4xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32l4xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32l4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32l4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32l4xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32l4xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32l4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32l4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32l4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32l4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32l4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32l4xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32l4xx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32l4xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32l4xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32l4xx_ll_rtc.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SAI_AC97_PROTOCOL : stm32l4xx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32l4xx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32l4xx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32l4xx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32l4xx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_10 : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_16 : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_20 : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_24 : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_32 : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_8 : stm32l4xx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32l4xx_hal_sai.c
  • SAI_Disable() : stm32l4xx_hal_sai.c
  • SAI_DMAAbort() : stm32l4xx_hal_sai.c
  • SAI_DMAError() : stm32l4xx_hal_sai.c
  • SAI_DMARxCplt() : stm32l4xx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32l4xx_hal_sai.c
  • SAI_DMATxCplt() : stm32l4xx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32l4xx_hal_sai.c
  • SAI_FIFO_SIZE : stm32l4xx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32l4xx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32l4xx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32l4xx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32l4xx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32l4xx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32l4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32l4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32l4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32l4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32l4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32l4xx_hal_sai.h
  • SAI_FillFifo() : stm32l4xx_hal_sai.c
  • SAI_FIRSTBIT_LSB : stm32l4xx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32l4xx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32l4xx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32l4xx_hal_sai.h
  • SAI_FLAG_FREQ : stm32l4xx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32l4xx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32l4xx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32l4xx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32l4xx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32l4xx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32l4xx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32l4xx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32l4xx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32l4xx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32l4xx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32l4xx_hal_sai.h
  • SAI_HandleTypeDef : stm32l4xx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32l4xx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32l4xx_hal_sai.h
  • SAI_I2S_STANDARD : stm32l4xx_hal_sai.h
  • SAI_InitI2S() : stm32l4xx_hal_sai.c
  • SAI_InitPCM() : stm32l4xx_hal_sai.c
  • SAI_InterruptFlag() : stm32l4xx_hal_sai.c
  • SAI_IT_AFSDET : stm32l4xx_hal_sai.h
  • SAI_IT_CNRDY : stm32l4xx_hal_sai.h
  • SAI_IT_FREQ : stm32l4xx_hal_sai.h
  • SAI_IT_LFSDET : stm32l4xx_hal_sai.h
  • SAI_IT_MUTEDET : stm32l4xx_hal_sai.h
  • SAI_IT_OVRUDR : stm32l4xx_hal_sai.h
  • SAI_IT_WCKCFG : stm32l4xx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32l4xx_hal_sai.h
  • SAI_MASTERDIVIDER_DISABLE : stm32l4xx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32l4xx_hal_sai.h
  • SAI_MODE_DMA : stm32l4xx_hal_sai.c
  • SAI_MODE_IT : stm32l4xx_hal_sai.c
  • SAI_MODEMASTER_RX : stm32l4xx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32l4xx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32l4xx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32l4xx_hal_sai.h
  • SAI_ModeTypedef : stm32l4xx_hal_sai.c
  • SAI_MONOMODE : stm32l4xx_hal_sai.h
  • SAI_NOCOMPANDING : stm32l4xx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32l4xx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32l4xx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32l4xx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32l4xx_hal_sai.h
  • SAI_PCM_LONG : stm32l4xx_hal_sai.h
  • SAI_PCM_SHORT : stm32l4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32l4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32l4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32l4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32l4xx_hal_sai.h
  • SAI_Receive_IT16Bit() : stm32l4xx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32l4xx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32l4xx_hal_sai.c
  • SAI_SLOT_NOTACTIVE : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32l4xx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32l4xx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32l4xx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32l4xx_hal_sai.h
  • SAI_SPDIF_PROTOCOL : stm32l4xx_hal_sai.h
  • SAI_STEREOMODE : stm32l4xx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32l4xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKA_ENABLE : stm32l4xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKB_ENABLE : stm32l4xx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32l4xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI1 : stm32l4xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI2 : stm32l4xx_hal_sai.h
  • SAI_Transmit_IT16Bit() : stm32l4xx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32l4xx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32l4xx_hal_sai.c
  • SAI_ULAW_1CPL_COMPANDING : stm32l4xx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32l4xx_hal_sai.h
  • SAI_xCR2_MUTECNT_OFFSET : stm32l4xx_hal_sai.c
  • SAI_ZERO_VALUE : stm32l4xx_hal_sai.h
  • SAIcallback : stm32l4xx_hal_sai.h
  • SCSR_OFFSET : stm32l4xx_hal.c
  • SCSR_SRAM2ER_BB : stm32l4xx_hal.c
  • SD_0TO7BITS : stm32l4xx_hal_sd.c
  • SD_16TO23BITS : stm32l4xx_hal_sd.c
  • SD_24TO31BITS : stm32l4xx_hal_sd.c
  • SD_8TO15BITS : stm32l4xx_hal_sd.c
  • SD_ALLZERO : stm32l4xx_hal_sd.c
  • SD_CARD_LOCKED : stm32l4xx_hal_sd.c
  • SD_CCCC_ERASE : stm32l4xx_hal_sd.c
  • SD_CCCC_LOCK_UNLOCK : stm32l4xx_hal_sd.c
  • SD_CCCC_WRITE_PROT : stm32l4xx_hal_sd.c
  • SD_CHECK_PATTERN : stm32l4xx_hal_sd.c
  • SD_CmdError() : stm32l4xx_hal_sd.c
  • SD_CmdResp1Error() : stm32l4xx_hal_sd.c
  • SD_CmdResp2Error() : stm32l4xx_hal_sd.c
  • SD_CmdResp3Error() : stm32l4xx_hal_sd.c
  • SD_CmdResp6Error() : stm32l4xx_hal_sd.c
  • SD_CmdResp7Error() : stm32l4xx_hal_sd.c
  • SD_DATATIMEOUT : stm32l4xx_hal_sd.c
  • SD_DMA_RxCplt() : stm32l4xx_hal_sd.c
  • SD_DMA_RxError() : stm32l4xx_hal_sd.c
  • SD_DMA_TxCplt() : stm32l4xx_hal_sd.c
  • SD_DMA_TxError() : stm32l4xx_hal_sd.c
  • SD_FindSCR() : stm32l4xx_hal_sd.c
  • SD_GetState() : stm32l4xx_hal_sd.c
  • SD_HALFFIFO : stm32l4xx_hal_sd.c
  • SD_HALFFIFOBYTES : stm32l4xx_hal_sd.c
  • SD_HIGH_CAPACITY : stm32l4xx_hal_sd.c
  • SD_Initialize_Cards() : stm32l4xx_hal_sd.c
  • SD_IsCardProgramming() : stm32l4xx_hal_sd.c
  • SD_MAX_DATA_LENGTH : stm32l4xx_hal_sd.c
  • SD_MAX_VOLT_TRIAL : stm32l4xx_hal_sd.c
  • SD_OCR_ADDR_MISALIGNED : stm32l4xx_hal_sd.c
  • SD_OCR_ADDR_OUT_OF_RANGE : stm32l4xx_hal_sd.c
  • SD_OCR_AKE_SEQ_ERROR : stm32l4xx_hal_sd.c
  • SD_OCR_BAD_ERASE_PARAM : stm32l4xx_hal_sd.c
  • SD_OCR_BLOCK_LEN_ERR : stm32l4xx_hal_sd.c
  • SD_OCR_CARD_ECC_DISABLED : stm32l4xx_hal_sd.c
  • SD_OCR_CARD_ECC_FAILED : stm32l4xx_hal_sd.c
  • SD_OCR_CC_ERROR : stm32l4xx_hal_sd.c
  • SD_OCR_CID_CSD_OVERWRITE : stm32l4xx_hal_sd.c
  • SD_OCR_COM_CRC_FAILED : stm32l4xx_hal_sd.c
  • SD_OCR_ERASE_RESET : stm32l4xx_hal_sd.c
  • SD_OCR_ERASE_SEQ_ERR : stm32l4xx_hal_sd.c
  • SD_OCR_ERRORBITS : stm32l4xx_hal_sd.c
  • SD_OCR_GENERAL_UNKNOWN_ERROR : stm32l4xx_hal_sd.c
  • SD_OCR_ILLEGAL_CMD : stm32l4xx_hal_sd.c
  • SD_OCR_LOCK_UNLOCK_FAILED : stm32l4xx_hal_sd.c
  • SD_OCR_STREAM_READ_UNDERRUN : stm32l4xx_hal_sd.c
  • SD_OCR_STREAM_WRITE_OVERRUN : stm32l4xx_hal_sd.c
  • SD_OCR_WP_ERASE_SKIP : stm32l4xx_hal_sd.c
  • SD_OCR_WRITE_PROT_VIOLATION : stm32l4xx_hal_sd.c
  • SD_PowerOFF() : stm32l4xx_hal_sd.c
  • SD_PowerON() : stm32l4xx_hal_sd.c
  • SD_R6_COM_CRC_FAILED : stm32l4xx_hal_sd.c
  • SD_R6_GENERAL_UNKNOWN_ERROR : stm32l4xx_hal_sd.c
  • SD_R6_ILLEGAL_CMD : stm32l4xx_hal_sd.c
  • SD_SDMMC_SEND_IF_COND : stm32l4xx_hal_sd.c
  • SD_Select_Deselect() : stm32l4xx_hal_sd.c
  • SD_SendStatus() : stm32l4xx_hal_sd.c
  • SD_SINGLE_BUS_SUPPORT : stm32l4xx_hal_sd.c
  • SD_STD_CAPACITY : stm32l4xx_hal_sd.c
  • SD_VOLTAGE_WINDOW_SD : stm32l4xx_hal_sd.c
  • SD_WIDE_BUS_SUPPORT : stm32l4xx_hal_sd.c
  • SD_WideBus_Disable() : stm32l4xx_hal_sd.c
  • SD_WideBus_Enable() : stm32l4xx_hal_sd.c
  • SDMMC_CMD0TIMEOUT : stm32l4xx_hal_sd.c
  • SDMMC_STATIC_FLAGS : stm32l4xx_hal_sd.c
  • SHIFT_TAB_CCxP : stm32l4xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32l4xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32l4xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32l4xx_ll_tim.h
  • SlaveAddr_MSK : stm32l4xx_hal_i2c.c
  • SlaveAddr_SHIFT : stm32l4xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_AdvFeatureConfig() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_CLEAR_EOBF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK1 : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK2 : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ClockSourceTypeDef : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CR3_SCARCNT_LSB_POS : stm32l4xx_hal_smartcard.h
  • SMARTCARD_DMAError() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_FLAG_BUSY : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_GTPR_GT_LSB_POS : stm32l4xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32l4xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32l4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32l4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32l4xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32l4xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32l4xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32l4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32l4xx_hal_smartcard.h
  • SMARTCARD_Receive_IT() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_RTOR_BLEN_LSB_POS : stm32l4xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32l4xx_hal_smartcard.h
  • SMARTCARD_SetConfig() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_STOPBITS_0_5 : stm32l4xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32l4xx_hal_smartcard.h
  • SMARTCARD_TC : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32l4xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_Transmit_IT() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32l4xx_hal_smartcard.h
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_WORDLENGTH_9B : stm32l4xx_hal_smartcard.h
  • SMBUS_ADDRESSINGMODE_10BIT : stm32l4xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32l4xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32l4xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32l4xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32l4xx_hal_smbus.h
  • SMBUS_Disable_IRQ() : stm32l4xx_hal_smbus.c
  • SMBUS_DUALADDRESS_DISABLE : stm32l4xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32l4xx_hal_smbus.h
  • SMBUS_Enable_IRQ() : stm32l4xx_hal_smbus.c
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32l4xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32l4xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32l4xx_hal_smbus.h
  • SMBUS_GENERALCALL_DISABLE : stm32l4xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32l4xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32l4xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32l4xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32l4xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32l4xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32l4xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32l4xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32l4xx_hal_smbus.h
  • SMBUS_GET_ISR_REG : stm32l4xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32l4xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32l4xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_RX : stm32l4xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_TX : stm32l4xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32l4xx_hal_smbus.h
  • SMBUS_LAST_FRAME_NO_PEC : stm32l4xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32l4xx_hal_smbus.h
  • SMBUS_Master_ISR() : stm32l4xx_hal_smbus.c
  • SMBUS_NEXT_FRAME : stm32l4xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32l4xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32l4xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32l4xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32l4xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32l4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32l4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32l4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32l4xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32l4xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32l4xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_Slave_ISR() : stm32l4xx_hal_smbus.c
  • SMBUS_SOFTEND_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_TransferConfig() : stm32l4xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32l4xx_hal_smbus.c
  • SPI_1LINE_RX : stm32l4xx_hal_spi.h
  • SPI_1LINE_TX : stm32l4xx_hal_spi.h
  • SPI_2linesRxISR_16BIT() : stm32l4xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32l4xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32l4xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32l4xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32l4xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32l4xx_hal_spi.c
  • SPI_BAUDRATEPRESCALER_128 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32l4xx_hal_spi.h
  • SPI_CloseRx_ISR() : stm32l4xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32l4xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32l4xx_hal_spi.c
  • SPI_CR1_CLEAR_MASK : stm32l4xx_ll_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32l4xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32l4xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32l4xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32l4xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32l4xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32l4xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32l4xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32l4xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32l4xx_hal_spi.h
  • SPI_DMAError() : stm32l4xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32l4xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32l4xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32l4xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32l4xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32l4xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32l4xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32l4xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32l4xx_hal_spi.c
  • SPI_FIFO_SIZE : stm32l4xx_hal_spi_ex.c
  • SPI_FIRSTBIT_LSB : stm32l4xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32l4xx_hal_spi.h
  • SPI_FLAG_BSY : stm32l4xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32l4xx_hal_spi.h
  • SPI_FLAG_FRE : stm32l4xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32l4xx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32l4xx_hal_spi.h
  • SPI_FLAG_MODF : stm32l4xx_hal_spi.h
  • SPI_FLAG_OVR : stm32l4xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32l4xx_hal_spi.h
  • SPI_FLAG_TXE : stm32l4xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32l4xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32l4xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32l4xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32l4xx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32l4xx_hal_spi.h
  • SPI_FTLVL_FULL : stm32l4xx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32l4xx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32l4xx_hal_spi.h
  • SPI_HandleTypeDef : stm32l4xx_hal_spi.h
  • SPI_IT_ERR : stm32l4xx_hal_spi.h
  • SPI_IT_RXNE : stm32l4xx_hal_spi.h
  • SPI_IT_TXE : stm32l4xx_hal_spi.h
  • SPI_MODE_MASTER : stm32l4xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32l4xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32l4xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32l4xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32l4xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32l4xx_hal_spi.h
  • SPI_NSS_SOFT : stm32l4xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32l4xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32l4xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32l4xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32l4xx_hal_spi.h
  • SPI_RESET_CRC : stm32l4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32l4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32l4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32l4xx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32l4xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32l4xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32l4xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32l4xx_hal_spi.c
  • SPI_TIMODE_DISABLE : stm32l4xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32l4xx_hal_spi.h
  • SPI_TxISR_16BIT() : stm32l4xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32l4xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32l4xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32l4xx_hal_spi.c
  • SWPMI_DMAError() : stm32l4xx_hal_swpmi.c
  • SWPMI_DMAReceiveCplt() : stm32l4xx_hal_swpmi.c
  • SWPMI_DMARxHalfCplt() : stm32l4xx_hal_swpmi.c
  • SWPMI_DMATransmitCplt() : stm32l4xx_hal_swpmi.c
  • SWPMI_DMATxHalfCplt() : stm32l4xx_hal_swpmi.c
  • SWPMI_EndReceive_IT() : stm32l4xx_hal_swpmi.c
  • SWPMI_EndTransmit_IT() : stm32l4xx_hal_swpmi.c
  • SWPMI_EndTransmitReceive_IT() : stm32l4xx_hal_swpmi.c
  • SWPMI_FLAG_DEACTF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_RXBERF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_RXBFF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_RXNE : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_RXOVRF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_SRF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_SUSP : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_TCF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_TXBEF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_TXE : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_TXUNRF : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_RIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_RXBERIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_RXBFIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_RXOVRIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_SRIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_TCIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_TIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_TXBEIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_TXUNRIE : stm32l4xx_hal_swpmi.h
  • SWPMI_Receive_IT() : stm32l4xx_hal_swpmi.c
  • SWPMI_RX_MULTI_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_RX_NO_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_RX_SINGLE_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_TIMEOUT_VALUE : stm32l4xx_hal_swpmi.c
  • SWPMI_Transmit_IT() : stm32l4xx_hal_swpmi.c
  • SWPMI_TX_MULTI_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_TX_NO_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_TX_SINGLE_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_B : stm32l4xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_C : stm32l4xx_hal_swpmi.h
  • SWPMI_WaitOnFlagSetUntilTimeout() : stm32l4xx_hal_swpmi.c
  • SYSCFG_BOOT_FMC : stm32l4xx_hal.h
  • SYSCFG_BOOT_MAINFLASH : stm32l4xx_hal.h
  • SYSCFG_BOOT_QUADSPI : stm32l4xx_hal.h
  • SYSCFG_BOOT_SRAM : stm32l4xx_hal.h
  • SYSCFG_BOOT_SYSTEMFLASH : stm32l4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32l4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32l4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32l4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32l4xx_hal.h
  • SYSCFG_FLAG_SRAM2_BUSY : stm32l4xx_hal.h
  • SYSCFG_FLAG_SRAM2_PE : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_DZC : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_IDC : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_IOC : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_IXC : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_OFC : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_UFC : stm32l4xx_hal.h
  • SYSCFG_OFFSET : stm32l4xx_hal.c
  • SYSCFG_SRAM2WRP_PAGE0 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE1 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE10 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE11 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE12 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE13 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE14 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE15 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE16 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE17 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE18 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE19 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE2 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE20 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE21 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE22 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE23 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE24 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE25 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE26 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE27 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE28 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE29 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE3 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE30 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE31 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE4 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE5 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE6 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE7 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE8 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE9 : stm32l4xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32l4xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32l4xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32l4xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32l4xx_hal.h
  • SYSTICK_CLKSOURCE_HCLK : stm32l4xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32l4xx_hal_cortex.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TEMPSENSOR_CAL1_ADDR : stm32l4xx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32l4xx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32l4xx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32l4xx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32l4xx_ll_adc.h
  • TICK_INT_PRIORITY : stm32l4xx_hal_conf.h
  • TIM15_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM16_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM17_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM1_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM2_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM3_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM8_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32l4xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32l4xx_hal_tim.h
  • TIM_Base_SetConfig() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32l4xx_hal_tim.h
  • TIM_BREAK2_ENABLE : stm32l4xx_hal_tim.h
  • TIM_BREAK2POLARITY_HIGH : stm32l4xx_hal_tim.h
  • TIM_BREAK2POLARITY_LOW : stm32l4xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32l4xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32l4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_ECC : stm32l4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_LOCKUP : stm32l4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_PVD : stm32l4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR : stm32l4xx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_BKIN : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DFSDM1 : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32l4xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32l4xx_hal_tim.h
  • TIM_CALC_DTS : stm32l4xx_ll_tim.h
  • TIM_CCER_CCxE_MASK : stm32l4xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32l4xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32l4xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32l4xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32l4xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32l4xx_hal_tim.h
  • TIM_CCxNChannelCmd() : stm32l4xx_hal_tim_ex.c
  • TIM_CHANNEL_1 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_5 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_6 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_OCREFCLR : stm32l4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32l4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32l4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32l4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32l4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32l4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32l4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32l4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32l4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32l4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32l4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32l4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32l4xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32l4xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32l4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32l4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32l4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32l4xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32l4xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32l4xx_hal_tim.h
  • TIM_DMA_CC1 : stm32l4xx_hal_tim.h
  • TIM_DMA_CC2 : stm32l4xx_hal_tim.h
  • TIM_DMA_CC3 : stm32l4xx_hal_tim.h
  • TIM_DMA_CC4 : stm32l4xx_hal_tim.h
  • TIM_DMA_COM : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32l4xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32l4xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCMR3 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR5 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR6 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32l4xx_hal_tim.h
  • TIM_DMABASE_DMAR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_OR1 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_OR2 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_OR3 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32l4xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_SR : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMACaptureCplt() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_DMADelayPulseCplt() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_DMAError() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_DMAPeriodElapsedCplt() : stm32l4xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32l4xx_hal_tim.c
  • TIM_ENCODERMODE_TI1 : stm32l4xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32l4xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32l4xx_hal_tim.h
  • TIM_ETR_SetConfig() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32l4xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32l4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32l4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32l4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32l4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32l4xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32l4xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC5 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC6 : stm32l4xx_hal_tim.h
  • TIM_FLAG_COM : stm32l4xx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32l4xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32l4xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32l4xx_ll_tim.h
  • TIM_GROUPCH5_NONE : stm32l4xx_hal_tim.h
  • TIM_GROUPCH5_OC1REFC : stm32l4xx_hal_tim.h
  • TIM_GROUPCH5_OC2REFC : stm32l4xx_hal_tim.h
  • TIM_GROUPCH5_OC3REFC : stm32l4xx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32l4xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32l4xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32l4xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32l4xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32l4xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32l4xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32l4xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32l4xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32l4xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32l4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32l4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32l4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32l4xx_hal_tim.h
  • TIM_IT_BREAK : stm32l4xx_hal_tim.h
  • TIM_IT_CC1 : stm32l4xx_hal_tim.h
  • TIM_IT_CC2 : stm32l4xx_hal_tim.h
  • TIM_IT_CC3 : stm32l4xx_hal_tim.h
  • TIM_IT_CC4 : stm32l4xx_hal_tim.h
  • TIM_IT_COM : stm32l4xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_IT_UPDATE : stm32l4xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_LOCKLEVEL_1 : stm32l4xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32l4xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32l4xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32l4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32l4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32l4xx_hal_tim.h
  • TIM_OC1_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_OC3_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_OC5_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_OCFAST_DISABLE : stm32l4xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32l4xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32l4xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32l4xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32l4xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32l4xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32l4xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32l4xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32l4xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32l4xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32l4xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32l4xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32l4xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32l4xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32l4xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32l4xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32l4xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32l4xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32l4xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32l4xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32l4xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32l4xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32l4xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32l4xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32l4xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32l4xx_hal_tim.h
  • TIM_POSITION_ICPSC : stm32l4xx_ll_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32l4xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32l4xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32l4xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_SlaveTimer_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32l4xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_TI1SELECTION_CH1 : stm32l4xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32l4xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32l4xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_TIM15_ENCODERMODE_NONE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM15_ENCODERMODE_TIM2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM15_ENCODERMODE_TIM3 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM15_ENCODERMODE_TIM4 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM15_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM15_TI1_LSE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSI : stm32l4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RTC : stm32l4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_HSE_32 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_MCO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_MSI : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_NONE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD3 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_NONE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_LSE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ITR1_OTG_FS_SOF : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ITR1_TIM8_TRGO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD3 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_NONE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD3 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_NONE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_RESET : stm32l4xx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32l4xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32l4xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32l4xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32l4xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32l4xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32l4xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32l4xx_hal_tim.h
  • TIM_TRGO_RESET : stm32l4xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32l4xx_hal_tim.h
  • TIM_TS_ETRF : stm32l4xx_hal_tim.h
  • TIM_TS_ITR0 : stm32l4xx_hal_tim.h
  • TIM_TS_ITR1 : stm32l4xx_hal_tim.h
  • TIM_TS_ITR2 : stm32l4xx_hal_tim.h
  • TIM_TS_ITR3 : stm32l4xx_hal_tim.h
  • TIM_TS_NONE : stm32l4xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32l4xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32l4xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32l4xx_hal_tim.h
  • TIMEOUT_DAC_CALIBCONFIG : stm32l4xx_hal_dac.c
  • TIMEx_DMACommutationCplt() : stm32l4xx_hal_tim_ex.c , stm32l4xx_hal_tim_ex.h
  • TIMING_CLEAR_MASK : stm32l4xx_hal_i2c.c , stm32l4xx_hal_smbus.c
  • TIMx_ETRSEL_MASK : stm32l4xx_hal_tim_ex.c
  • TIMx_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIMx_OR1_RMP_SHIFT : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKCOMP1E : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKCOMP1P : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKCOMP2E : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKCOMP2P : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKDF1BK0E : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKINE : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKINP : stm32l4xx_ll_tim.h
  • TIMx_OR2_ETRSEL : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2COMP1E : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2COMP1P : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2COMP2E : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2COMP2P : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2DF1BK1E : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2INE : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2INP : stm32l4xx_ll_tim.h
  • TSC_ACQ_MODE_NORMAL : stm32l4xx_hal_tsc.h
  • TSC_ACQ_MODE_SYNCHRO : stm32l4xx_hal_tsc.h
  • TSC_ALL_GROUPS : stm32l4xx_hal_tsc.h
  • TSC_ALL_GROUPS_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_CTPH_10CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_11CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_12CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_13CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_14CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_15CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_16CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_1CYCLE : stm32l4xx_hal_tsc.h
  • TSC_CTPH_2CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_3CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_4CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_5CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_6CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_7CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_8CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_9CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_10CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_11CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_12CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_13CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_14CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_15CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_16CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_1CYCLE : stm32l4xx_hal_tsc.h
  • TSC_CTPL_2CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_3CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_4CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_5CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_6CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_7CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_8CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_9CYCLES : stm32l4xx_hal_tsc.h
  • TSC_extract_groups() : stm32l4xx_hal_tsc.c
  • TSC_FLAG_EOA : stm32l4xx_hal_tsc.h
  • TSC_FLAG_MCE : stm32l4xx_hal_tsc.h
  • TSC_GROUP1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP5 : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP6 : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP7 : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP8 : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP_COMPLETED : stm32l4xx_hal_tsc.h
  • TSC_GROUP_ONGOING : stm32l4xx_hal_tsc.h
  • TSC_GroupStatusTypeDef : stm32l4xx_hal_tsc.h
  • TSC_IODEF_IN_FLOAT : stm32l4xx_hal_tsc.h
  • TSC_IODEF_OUT_PP_LOW : stm32l4xx_hal_tsc.h
  • TSC_IOMODE_CHANNEL : stm32l4xx_hal_tsc.h
  • TSC_IOMODE_SAMPLING : stm32l4xx_hal_tsc.h
  • TSC_IOMODE_SHIELD : stm32l4xx_hal_tsc.h
  • TSC_IOMODE_UNUSED : stm32l4xx_hal_tsc.h
  • TSC_IT_EOA : stm32l4xx_hal_tsc.h
  • TSC_IT_MCE : stm32l4xx_hal_tsc.h
  • TSC_MCV_1023 : stm32l4xx_hal_tsc.h
  • TSC_MCV_16383 : stm32l4xx_hal_tsc.h
  • TSC_MCV_2047 : stm32l4xx_hal_tsc.h
  • TSC_MCV_255 : stm32l4xx_hal_tsc.h
  • TSC_MCV_4095 : stm32l4xx_hal_tsc.h
  • TSC_MCV_511 : stm32l4xx_hal_tsc.h
  • TSC_MCV_8191 : stm32l4xx_hal_tsc.h
  • TSC_NB_OF_GROUPS : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV1 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV128 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV16 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV2 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV32 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV4 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV64 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV8 : stm32l4xx_hal_tsc.h
  • TSC_SS_PRESC_DIV1 : stm32l4xx_hal_tsc.h
  • TSC_SS_PRESC_DIV2 : stm32l4xx_hal_tsc.h
  • TSC_SYNC_POLARITY_FALLING : stm32l4xx_hal_tsc.h
  • TSC_SYNC_POLARITY_RISING : stm32l4xx_hal_tsc.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
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  • Typedefs
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  • u
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_ADDRESS_DETECT_4B : stm32l4xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32l4xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32l4xx_hal_uart.h
  • UART_AdvFeatureConfig() : stm32l4xx_hal_uart.c
  • UART_AUTOBAUD_REQUEST : stm32l4xx_hal_uart.h
  • UART_CheckIdleState() : stm32l4xx_hal_uart.c
  • UART_CLEAR_CMF : stm32l4xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32l4xx_hal_uart.h
  • UART_CLEAR_EOBF : stm32l4xx_hal_uart.h
  • UART_CLEAR_FEF : stm32l4xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32l4xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32l4xx_hal_uart.h
  • UART_CLEAR_NEF : stm32l4xx_hal_uart.h
  • UART_CLEAR_OREF : stm32l4xx_hal_uart.h
  • UART_CLEAR_PEF : stm32l4xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32l4xx_hal_uart.h
  • UART_CLEAR_TCF : stm32l4xx_hal_uart.h
  • UART_CLEAR_WUF : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_HSI : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK2 : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32l4xx_hal_uart.h
  • UART_ClockSourceTypeDef : stm32l4xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32l4xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32l4xx_hal_uart.h
  • UART_CR1_FIELDS : stm32l4xx_hal_uart.c
  • UART_CR2_ADDRESS_LSB_POS : stm32l4xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32l4xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32l4xx_hal_uart.h
  • UART_DIV_LPUART : stm32l4xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32l4xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32l4xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32l4xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32l4xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32l4xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32l4xx_hal_uart.h
  • UART_DMAAbortOnError() : stm32l4xx_hal_uart.c
  • UART_DMAError() : stm32l4xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32l4xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32l4xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32l4xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32l4xx_hal_uart.c
  • UART_EndRxTransfer() : stm32l4xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32l4xx_hal_uart.c
  • UART_EndTxTransfer() : stm32l4xx_hal_uart.c
  • UART_FLAG_ABRE : stm32l4xx_hal_uart.h
  • UART_FLAG_ABRF : stm32l4xx_hal_uart.h
  • UART_FLAG_BUSY : stm32l4xx_hal_uart.h
  • UART_FLAG_CMF : stm32l4xx_hal_uart.h
  • UART_FLAG_CTS : stm32l4xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32l4xx_hal_uart.h
  • UART_FLAG_EOBF : stm32l4xx_hal_uart.h
  • UART_FLAG_FE : stm32l4xx_hal_uart.h
  • UART_FLAG_IDLE : stm32l4xx_hal_uart.h
  • UART_FLAG_LBDF : stm32l4xx_hal_uart.h
  • UART_FLAG_NE : stm32l4xx_hal_uart.h
  • UART_FLAG_ORE : stm32l4xx_hal_uart.h
  • UART_FLAG_PE : stm32l4xx_hal_uart.h
  • UART_FLAG_REACK : stm32l4xx_hal_uart.h
  • UART_FLAG_RTOF : stm32l4xx_hal_uart.h
  • UART_FLAG_RWU : stm32l4xx_hal_uart.h
  • UART_FLAG_RXNE : stm32l4xx_hal_uart.h
  • UART_FLAG_SBKF : stm32l4xx_hal_uart.h
  • UART_FLAG_TC : stm32l4xx_hal_uart.h
  • UART_FLAG_TEACK : stm32l4xx_hal_uart.h
  • UART_FLAG_TXE : stm32l4xx_hal_uart.h
  • UART_FLAG_WUF : stm32l4xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32l4xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32l4xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32l4xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32l4xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32l4xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32l4xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32l4xx_hal_uart.h
  • UART_INSTANCE_LOWPOWER : stm32l4xx_hal_uart.h
  • UART_IT_CM : stm32l4xx_hal_uart.h
  • UART_IT_CTS : stm32l4xx_hal_uart.h
  • UART_IT_ERR : stm32l4xx_hal_uart.h
  • UART_IT_FE : stm32l4xx_hal_uart.h
  • UART_IT_IDLE : stm32l4xx_hal_uart.h
  • UART_IT_LBD : stm32l4xx_hal_uart.h
  • UART_IT_MASK : stm32l4xx_hal_uart.h
  • UART_IT_NE : stm32l4xx_hal_uart.h
  • UART_IT_ORE : stm32l4xx_hal_uart.h
  • UART_IT_PE : stm32l4xx_hal_uart.h
  • UART_IT_RXNE : stm32l4xx_hal_uart.h
  • UART_IT_TC : stm32l4xx_hal_uart.h
  • UART_IT_TXE : stm32l4xx_hal_uart.h
  • UART_IT_WUF : stm32l4xx_hal_uart.h
  • UART_LIN_DISABLE : stm32l4xx_hal_uart.h
  • UART_LIN_ENABLE : stm32l4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32l4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32l4xx_hal_uart.h
  • UART_LPUART_BRR_MAX : stm32l4xx_hal_uart.c
  • UART_LPUART_BRR_MIN : stm32l4xx_hal_uart.c
  • UART_MASK_COMPUTATION : stm32l4xx_hal_uart_ex.h
  • UART_MODE_RX : stm32l4xx_hal_uart.h
  • UART_MODE_TX : stm32l4xx_hal_uart.h
  • UART_MODE_TX_RX : stm32l4xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32l4xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32l4xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32l4xx_hal_uart.h
  • UART_PARITY_EVEN : stm32l4xx_hal_uart.h
  • UART_PARITY_NONE : stm32l4xx_hal_uart.h
  • UART_PARITY_ODD : stm32l4xx_hal_uart.h
  • UART_Receive_IT() : stm32l4xx_hal_uart.c
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32l4xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32l4xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32l4xx_hal_uart.h
  • UART_SENDBREAK_REQUEST : stm32l4xx_hal_uart.h
  • UART_SetConfig() : stm32l4xx_hal_uart.c
  • UART_STATE_DISABLE : stm32l4xx_hal_uart.h
  • UART_STATE_ENABLE : stm32l4xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32l4xx_hal_uart.h
  • UART_STOPBITS_1 : stm32l4xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32l4xx_hal_uart.h
  • UART_STOPBITS_2 : stm32l4xx_hal_uart.h
  • UART_Transmit_IT() : stm32l4xx_hal_uart.c
  • UART_TXDATA_FLUSH_REQUEST : stm32l4xx_hal_uart.h
  • UART_WaitOnFlagUntilTimeout() : stm32l4xx_hal_uart.c
  • UART_WAKEUP_ON_ADDRESS : stm32l4xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32l4xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32l4xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32l4xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32l4xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32l4xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32l4xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32l4xx_hal_uart_ex.h
  • UARTEx_Wakeup_AddressConfig() : stm32l4xx_hal_uart_ex.c
  • UID_BASE_ADDRESS : stm32l4xx_ll_utils.h
  • USART_CheckIdleState() : stm32l4xx_hal_usart.c
  • USART_CLEAR_FEF : stm32l4xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32l4xx_hal_usart.h
  • USART_CLEAR_NEF : stm32l4xx_hal_usart.h
  • USART_CLEAR_OREF : stm32l4xx_hal_usart.h
  • USART_CLEAR_PEF : stm32l4xx_hal_usart.h
  • USART_CLEAR_TCF : stm32l4xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32l4xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_HSI : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK1 : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK2 : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32l4xx_hal_usart.h
  • USART_ClockSourceTypeDef : stm32l4xx_hal_usart.h
  • USART_CR1_FIELDS : stm32l4xx_hal_usart.c , stm32l4xx_hal_smartcard.c
  • USART_CR2_CLK_FIELDS : stm32l4xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32l4xx_hal_smartcard.c , stm32l4xx_hal_usart.c
  • USART_CR3_FIELDS : stm32l4xx_hal_smartcard.c
  • USART_DMAAbortOnError() : stm32l4xx_hal_usart.c
  • USART_DMAError() : stm32l4xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32l4xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32l4xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32l4xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32l4xx_hal_usart.c
  • USART_DUMMY_DATA : stm32l4xx_hal_usart.c
  • USART_EndTransfer() : stm32l4xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32l4xx_hal_usart.c
  • USART_FLAG_BUSY : stm32l4xx_hal_usart.h
  • USART_FLAG_CTS : stm32l4xx_hal_usart.h
  • USART_FLAG_CTSIF : stm32l4xx_hal_usart.h
  • USART_FLAG_FE : stm32l4xx_hal_usart.h
  • USART_FLAG_IDLE : stm32l4xx_hal_usart.h
  • USART_FLAG_LBDF : stm32l4xx_hal_usart.h
  • USART_FLAG_NE : stm32l4xx_hal_usart.h
  • USART_FLAG_ORE : stm32l4xx_hal_usart.h
  • USART_FLAG_PE : stm32l4xx_hal_usart.h
  • USART_FLAG_REACK : stm32l4xx_hal_usart.h
  • USART_FLAG_RXNE : stm32l4xx_hal_usart.h
  • USART_FLAG_TC : stm32l4xx_hal_usart.h
  • USART_FLAG_TEACK : stm32l4xx_hal_usart.h
  • USART_FLAG_TXE : stm32l4xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32l4xx_hal_usart_ex.h
  • USART_IT_ERR : stm32l4xx_hal_usart.h
  • USART_IT_FE : stm32l4xx_hal_usart.h
  • USART_IT_IDLE : stm32l4xx_hal_usart.h
  • USART_IT_MASK : stm32l4xx_hal_usart.h
  • USART_IT_NE : stm32l4xx_hal_usart.h
  • USART_IT_ORE : stm32l4xx_hal_usart.h
  • USART_IT_PE : stm32l4xx_hal_usart.h
  • USART_IT_RXNE : stm32l4xx_hal_usart.h
  • USART_IT_TC : stm32l4xx_hal_usart.h
  • USART_IT_TXE : stm32l4xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32l4xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32l4xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32l4xx_hal_usart_ex.h
  • USART_MODE_RX : stm32l4xx_hal_usart.h
  • USART_MODE_TX : stm32l4xx_hal_usart.h
  • USART_MODE_TX_RX : stm32l4xx_hal_usart.h
  • USART_OVERSAMPLING_16 : stm32l4xx_hal_usart.h
  • USART_OVERSAMPLING_8 : stm32l4xx_hal_usart.h
  • USART_PARITY_EVEN : stm32l4xx_hal_usart.h
  • USART_PARITY_NONE : stm32l4xx_hal_usart.h
  • USART_PARITY_ODD : stm32l4xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32l4xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32l4xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32l4xx_hal_usart.h
  • USART_POLARITY_LOW : stm32l4xx_hal_usart.h
  • USART_POSITION_CR1_DEAT : stm32l4xx_ll_usart.h
  • USART_POSITION_CR1_DEDT : stm32l4xx_ll_usart.h
  • USART_POSITION_CR2_ADD : stm32l4xx_ll_usart.h
  • USART_POSITION_CR3_SCARCNT : stm32l4xx_ll_usart.h
  • USART_POSITION_GTPR_GT : stm32l4xx_ll_usart.h
  • USART_POSITION_RTOR_BLEN : stm32l4xx_ll_usart.h
  • USART_Receive_IT() : stm32l4xx_hal_usart.c
  • USART_RXDATA_FLUSH_REQUEST : stm32l4xx_hal_usart.h
  • USART_SetConfig() : stm32l4xx_hal_usart.c
  • USART_STOPBITS_0_5 : stm32l4xx_hal_usart.h
  • USART_STOPBITS_1 : stm32l4xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32l4xx_hal_usart.h
  • USART_STOPBITS_2 : stm32l4xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32l4xx_hal_usart.c
  • USART_Transmit_IT() : stm32l4xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32l4xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32l4xx_hal_usart.h
  • USART_WaitOnFlagUntilTimeout() : stm32l4xx_hal_usart.c
  • USART_WORDLENGTH_7B : stm32l4xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32l4xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32l4xx_hal_usart_ex.h
  • USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE : stm32l4xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_LINE : stm32l4xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE : stm32l4xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32l4xx_hal_pcd.h
  • USBD_FS_TRDT_VALUE : stm32l4xx_hal_pcd.h
  • USE_RTOS : stm32l4xx_hal_conf.h
  • UTILS_EnablePLLAndSwitchSystem() : stm32l4xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32l4xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MAX : stm32l4xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32l4xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE1 : stm32l4xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE2 : stm32l4xx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32l4xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX : stm32l4xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN : stm32l4xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MAX : stm32l4xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MIN : stm32l4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY1_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY2_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY3_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY4_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY1_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY2_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY3_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SetFlashLatency() : stm32l4xx_ll_utils.c
  • uwNORMemoryDataWidth : stm32l4xx_hal_nor.c
  • uwTick : stm32l4xx_hal.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
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  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • v_dfsdm1ChannelCounter : stm32l4xx_hal_dfsdm.c
  • VDD_VALUE : stm32l4xx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32l4xx_hal.c
  • VREFINT_CAL_ADDR : stm32l4xx_ll_adc.h
  • VREFINT_CAL_VREF : stm32l4xx_ll_adc.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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  • q
  • r
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  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WWDG_EWI_DISABLE : stm32l4xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32l4xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32l4xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32l4xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32l4xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32l4xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32l4xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32l4xx_hal_wwdg.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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  • d
  • f
  • h
  • i
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  • q
  • r
  • s
  • t
  • u

- a -

  • ADC_ConversionStop() : stm32l4xx_hal_adc.c
  • ADC_Disable() : stm32l4xx_hal_adc.c
  • ADC_DMAConvCplt() : stm32l4xx_hal_adc.c
  • ADC_DMAError() : stm32l4xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32l4xx_hal_adc.c
  • ADC_Enable() : stm32l4xx_hal_adc.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
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  • h
  • i
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  • n
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  • t
  • u

- c -

  • CAN_Receive_IT() : stm32l4xx_hal_can.c
  • CAN_Transmit_IT() : stm32l4xx_hal_can.c
  • CRC_Handle_16() : stm32l4xx_hal_crc.c
  • CRC_Handle_8() : stm32l4xx_hal_crc.c
  • CRYP_AES_Auth_IT() : stm32l4xx_hal_cryp_ex.c
  • CRYP_AES_IT() : stm32l4xx_hal_cryp.c
  • CRYP_DMAError() : stm32l4xx_hal_cryp_ex.c
  • CRYP_DMAInCplt() : stm32l4xx_hal_cryp_ex.c
  • CRYP_DMAOutCplt() : stm32l4xx_hal_cryp_ex.c
  • CRYP_GCMCMAC_DMAError() : stm32l4xx_hal_cryp_ex.c
  • CRYP_GCMCMAC_DMAInCplt() : stm32l4xx_hal_cryp_ex.c
  • CRYP_GCMCMAC_DMAOutCplt() : stm32l4xx_hal_cryp_ex.c
  • CRYP_GCMCMAC_SetDMAConfig() : stm32l4xx_hal_cryp_ex.c
  • CRYP_Padding() : stm32l4xx_hal_cryp_ex.c
  • CRYP_ProcessData() : stm32l4xx_hal_cryp_ex.c
  • CRYP_ReadKey() : stm32l4xx_hal_cryp_ex.c
  • CRYP_SetDMAConfig() : stm32l4xx_hal_cryp_ex.c
  • CRYP_SetInitVector() : stm32l4xx_hal_cryp.c
  • CRYP_SetKey() : stm32l4xx_hal_cryp.c
  • CRYP_WaitOnBusyFlagReset() : stm32l4xx_hal_cryp_ex.c
  • CRYP_WaitOnCCFlag() : stm32l4xx_hal_cryp_ex.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u

- d -

  • DAC_DMAConvCpltCh1() : stm32l4xx_hal_dac.c
  • DAC_DMAConvCpltCh2() : stm32l4xx_hal_dac_ex.c
  • DAC_DMAErrorCh1() : stm32l4xx_hal_dac.c
  • DAC_DMAErrorCh2() : stm32l4xx_hal_dac_ex.c
  • DAC_DMAHalfConvCpltCh1() : stm32l4xx_hal_dac.c
  • DAC_DMAHalfConvCpltCh2() : stm32l4xx_hal_dac_ex.c
  • DFSDM_DMAError() : stm32l4xx_hal_dfsdm.c
  • DFSDM_DMAInjectedConvCplt() : stm32l4xx_hal_dfsdm.c
  • DFSDM_DMAInjectedHalfConvCplt() : stm32l4xx_hal_dfsdm.c
  • DFSDM_DMARegularConvCplt() : stm32l4xx_hal_dfsdm.c
  • DFSDM_DMARegularHalfConvCplt() : stm32l4xx_hal_dfsdm.c
  • DFSDM_GetChannelFromInstance() : stm32l4xx_hal_dfsdm.c
  • DFSDM_GetInjChannelsNbr() : stm32l4xx_hal_dfsdm.c
  • DFSDM_InjConvStart() : stm32l4xx_hal_dfsdm.c
  • DFSDM_InjConvStop() : stm32l4xx_hal_dfsdm.c
  • DFSDM_RegConvStart() : stm32l4xx_hal_dfsdm.c
  • DFSDM_RegConvStop() : stm32l4xx_hal_dfsdm.c
  • DMA_SetConfig() : stm32l4xx_hal_dma.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- f -

  • FLASH_FlushCaches() : stm32l4xx_hal_flash.c , stm32l4xx_hal_flash_ex.c
  • FLASH_MassErase() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_GetPCROP() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_PCROPConfig() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_RDPConfig() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32l4xx_hal_flash_ex.c
  • FLASH_OB_WRPConfig() : stm32l4xx_hal_flash_ex.c
  • FLASH_PageErase() : stm32l4xx_hal_flash_ex.c , stm32l4xx_hal_flash.c
  • FLASH_Program_DoubleWord() : stm32l4xx_hal_flash.c
  • FLASH_Program_Fast() : stm32l4xx_hal_flash.c
  • FLASH_SetErrorCode() : stm32l4xx_hal_flash.c
  • FLASH_WaitForLastOperation() : stm32l4xx_hal_flash.c , stm32l4xx_hal_flash_ex.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • a
  • c
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- h -

  • HAL_ADC_AnalogWDGConfig() : stm32l4xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32l4xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32l4xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32l4xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32l4xx_hal_adc.c
  • HAL_ADC_ErrorCallback() : stm32l4xx_hal_adc.c
  • HAL_ADC_GetError() : stm32l4xx_hal_adc.c
  • HAL_ADC_GetState() : stm32l4xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32l4xx_hal_adc.c
  • HAL_ADC_Init() : stm32l4xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32l4xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32l4xx_hal_adc.c
  • HAL_ADC_MspDeInit() : stm32l4xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32l4xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32l4xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32l4xx_hal_adc.c
  • HAL_ADC_Start() : stm32l4xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32l4xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32l4xx_hal_adc.c
  • HAL_ADC_Stop() : stm32l4xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32l4xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32l4xx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_DisableInjectedQueue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_EnableInjectedQueue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_EndOfSamplingCallback() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_EnterADCDeepPowerDownMode() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedQueueOverflowCallback() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularMultiModeStop_DMA() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_DMA() : stm32l4xx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_IT() : stm32l4xx_hal_adc_ex.c
  • HAL_CAN_ConfigFilter() : stm32l4xx_hal_can.c
  • HAL_CAN_DeInit() : stm32l4xx_hal_can.c
  • HAL_CAN_ErrorCallback() : stm32l4xx_hal_can.c
  • HAL_CAN_GetError() : stm32l4xx_hal_can.c
  • HAL_CAN_GetState() : stm32l4xx_hal_can.c
  • HAL_CAN_Init() : stm32l4xx_hal_can.c
  • HAL_CAN_IRQHandler() : stm32l4xx_hal_can.c
  • HAL_CAN_MspDeInit() : stm32l4xx_hal_can.c
  • HAL_CAN_MspInit() : stm32l4xx_hal_can.c
  • HAL_CAN_Receive() : stm32l4xx_hal_can.c
  • HAL_CAN_Receive_IT() : stm32l4xx_hal_can.c
  • HAL_CAN_RxCpltCallback() : stm32l4xx_hal_can.c
  • HAL_CAN_Sleep() : stm32l4xx_hal_can.c
  • HAL_CAN_Transmit() : stm32l4xx_hal_can.c
  • HAL_CAN_Transmit_IT() : stm32l4xx_hal_can.c
  • HAL_CAN_TxCpltCallback() : stm32l4xx_hal_can.c
  • HAL_CAN_WakeUp() : stm32l4xx_hal_can.c
  • HAL_COMP_DeInit() : stm32l4xx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32l4xx_hal_comp.c
  • HAL_COMP_GetState() : stm32l4xx_hal_comp.c
  • HAL_COMP_Init() : stm32l4xx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32l4xx_hal_comp.c
  • HAL_COMP_Lock() : stm32l4xx_hal_comp.c
  • HAL_COMP_MspDeInit() : stm32l4xx_hal_comp.c
  • HAL_COMP_MspInit() : stm32l4xx_hal_comp.c
  • HAL_COMP_Start() : stm32l4xx_hal_comp.c
  • HAL_COMP_Stop() : stm32l4xx_hal_comp.c
  • HAL_COMP_TriggerCallback() : stm32l4xx_hal_comp.c
  • HAL_CRC_Accumulate() : stm32l4xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32l4xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32l4xx_hal_crc.c
  • HAL_CRC_GetState() : stm32l4xx_hal_crc.c
  • HAL_CRC_Init() : stm32l4xx_hal_crc.c
  • HAL_CRC_MspDeInit() : stm32l4xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32l4xx_hal_crc.c
  • HAL_CRCEx_Input_Data_Reverse() : stm32l4xx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32l4xx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32l4xx_hal_crc_ex.c
  • HAL_CRYP_AESCBC_Decrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCBC_Decrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCBC_Decrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCBC_Encrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCBC_Encrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCBC_Encrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Decrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Decrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Decrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Encrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Encrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESCTR_Encrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Decrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Decrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Decrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Encrypt() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Encrypt_DMA() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_AESECB_Encrypt_IT() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_DeInit() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_ErrorCallback() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_GetError() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_GetState() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_InCpltCallback() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_Init() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_IRQHandler() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_MspDeInit() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_MspInit() : stm32l4xx_hal_cryp.c
  • HAL_CRYP_OutCpltCallback() : stm32l4xx_hal_cryp.c
  • HAL_CRYPEx_AES() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_AES_Auth() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_AES_Auth_DMA() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_AES_Auth_IT() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_AES_DMA() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_AES_IT() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_ComputationCpltCallback() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_ProcessSuspend() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Read_ControlRegister() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Read_IVRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Read_KeyRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Read_SuspendRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Write_ControlRegister() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Write_IVRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Write_KeyRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_CRYPEx_Write_SuspendRegisters() : stm32l4xx_hal_cryp_ex.c
  • HAL_DAC_ConfigChannel() : stm32l4xx_hal_dac.c
  • HAL_DAC_ConvCpltCallbackCh1() : stm32l4xx_hal_dac.c
  • HAL_DAC_ConvHalfCpltCallbackCh1() : stm32l4xx_hal_dac.c
  • HAL_DAC_DeInit() : stm32l4xx_hal_dac.c
  • HAL_DAC_DMAUnderrunCallbackCh1() : stm32l4xx_hal_dac.c
  • HAL_DAC_ErrorCallbackCh1() : stm32l4xx_hal_dac.c
  • HAL_DAC_GetError() : stm32l4xx_hal_dac.c
  • HAL_DAC_GetState() : stm32l4xx_hal_dac.c
  • HAL_DAC_GetValue() : stm32l4xx_hal_dac.c
  • HAL_DAC_Init() : stm32l4xx_hal_dac.c
  • HAL_DAC_IRQHandler() : stm32l4xx_hal_dac.c
  • HAL_DAC_MspDeInit() : stm32l4xx_hal_dac.c
  • HAL_DAC_MspInit() : stm32l4xx_hal_dac.c
  • HAL_DAC_SetValue() : stm32l4xx_hal_dac.c
  • HAL_DAC_Start() : stm32l4xx_hal_dac.c
  • HAL_DAC_Start_DMA() : stm32l4xx_hal_dac.c
  • HAL_DAC_Stop() : stm32l4xx_hal_dac.c
  • HAL_DAC_Stop_DMA() : stm32l4xx_hal_dac.c
  • HAL_DACEx_ConvCpltCallbackCh2() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_ConvHalfCpltCallbackCh2() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_DMAUnderrunCallbackCh2() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_DualGetValue() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_DualSetValue() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_ErrorCallbackCh2() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_GetTrimOffset() : stm32l4xx_hal_dac_ex.c , stm32l4xx_hal_dac_ex.h
  • HAL_DACEx_NoiseWaveGenerate() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_SelfCalibrate() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_SetUserTrimming() : stm32l4xx_hal_dac_ex.c
  • HAL_DACEx_TriangleWaveGenerate() : stm32l4xx_hal_dac_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32l4xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32l4xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32l4xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32l4xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32l4xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32l4xx_hal.c
  • HAL_DeInit() : stm32l4xx_hal.c
  • HAL_Delay() : stm32l4xx_hal.c
  • HAL_DFSDM_ChannelCkabCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStart_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelCkabStop_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelDeInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetAwdValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelGetState() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelModifyOffset() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspDeInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelMspInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForCkab() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelPollForScd() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStart_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_ChannelScdStop_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStart_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterAwdStop_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigInjChannel() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterConfigRegChannel() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterDeInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterErrorCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStart() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterExdStop() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetConvTimeValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetError() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMaxValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetExdMinValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetInjectedValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetRegularValue() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterGetState() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvCpltCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjConvHalfCpltCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedMsbStart_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStart_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterInjectedStop_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspDeInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterMspInit() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForInjConversion() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterPollForRegConversion() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvCpltCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegConvHalfCpltCallback() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularMsbStart_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStart_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_DMA() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_FilterRegularStop_IT() : stm32l4xx_hal_dfsdm.c
  • HAL_DFSDM_IRQHandler() : stm32l4xx_hal_dfsdm.c
  • HAL_DMA_Abort() : stm32l4xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32l4xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32l4xx_hal_dma.c
  • HAL_DMA_GetError() : stm32l4xx_hal_dma.c
  • HAL_DMA_GetState() : stm32l4xx_hal_dma.c
  • HAL_DMA_Init() : stm32l4xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32l4xx_hal_dma.c
  • HAL_DMA_PollForTransfer() : stm32l4xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32l4xx_hal_dma.c
  • HAL_DMA_Start() : stm32l4xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32l4xx_hal_dma.c
  • HAL_DMA_UnRegisterCallback() : stm32l4xx_hal_dma.c
  • HAL_FIREWALL_Config() : stm32l4xx_hal_firewall.c
  • HAL_FIREWALL_DisablePreArmFlag() : stm32l4xx_hal_firewall.c
  • HAL_FIREWALL_EnableFirewall() : stm32l4xx_hal_firewall.c
  • HAL_FIREWALL_EnablePreArmFlag() : stm32l4xx_hal_firewall.c
  • HAL_FIREWALL_GetConfig() : stm32l4xx_hal_firewall.c
  • HAL_FLASH_EndOfOperationCallback() : stm32l4xx_hal_flash.c
  • HAL_FLASH_GetError() : stm32l4xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32l4xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32l4xx_hal_flash.c
  • HAL_FLASH_OB_Launch() : stm32l4xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32l4xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32l4xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32l4xx_hal_flash.c
  • HAL_FLASH_Program() : stm32l4xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32l4xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32l4xx_hal_flash.c
  • HAL_FLASHEx_DisableRunPowerDown() : stm32l4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_EnableRunPowerDown() : stm32l4xx_hal_flash_ramfunc.c
  • HAL_FLASHEx_Erase() : stm32l4xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32l4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32l4xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32l4xx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32l4xx_hal.c
  • HAL_GetHalVersion() : stm32l4xx_hal.c
  • HAL_GetREVID() : stm32l4xx_hal.c
  • HAL_GetTick() : stm32l4xx_hal.c
  • HAL_GPIO_DeInit() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_ReadPin() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32l4xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32l4xx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32l4xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32l4xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32l4xx_hal_uart.c
  • HAL_HCD_Connect_Callback() : stm32l4xx_hal_hcd.c
  • HAL_HCD_DeInit() : stm32l4xx_hal_hcd.c
  • HAL_HCD_Disconnect_Callback() : stm32l4xx_hal_hcd.c
  • HAL_HCD_GetCurrentFrame() : stm32l4xx_hal_hcd.c
  • HAL_HCD_GetCurrentSpeed() : stm32l4xx_hal_hcd.c
  • HAL_HCD_GetState() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_GetState() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_GetURBState() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_GetXferCount() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_Halt() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_Init() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_NotifyURBChange_Callback() : stm32l4xx_hal_hcd.c
  • HAL_HCD_HC_SubmitRequest() : stm32l4xx_hal_hcd.c
  • HAL_HCD_Init() : stm32l4xx_hal_hcd.c
  • HAL_HCD_IRQHandler() : stm32l4xx_hal_hcd.c
  • HAL_HCD_MspDeInit() : stm32l4xx_hal_hcd.c
  • HAL_HCD_MspInit() : stm32l4xx_hal_hcd.c
  • HAL_HCD_ResetPort() : stm32l4xx_hal_hcd.c
  • HAL_HCD_SOF_Callback() : stm32l4xx_hal_hcd.c
  • HAL_HCD_Start() : stm32l4xx_hal_hcd.c
  • HAL_HCD_Stop() : stm32l4xx_hal_hcd.c
  • HAL_I2C_AbortCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32l4xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32l4xx_hal_i2c.c
  • HAL_I2C_ErrorCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32l4xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32l4xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32l4xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Init() : stm32l4xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32l4xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Receive_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Transmit_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MspDeInit() : stm32l4xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Receive_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Transmit_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32l4xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32l4xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32l4xx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32l4xx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32l4xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32l4xx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32l4xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32l4xx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32l4xx_hal_i2c_ex.c
  • HAL_IncTick() : stm32l4xx_hal.c
  • HAL_Init() : stm32l4xx_hal.c
  • HAL_InitTick() : stm32l4xx_hal.c
  • HAL_IRDA_DeInit() : stm32l4xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32l4xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32l4xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32l4xx_hal_irda.c
  • HAL_IRDA_ErrorCallback() : stm32l4xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32l4xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Init() : stm32l4xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32l4xx_hal_irda.c
  • HAL_IRDA_MspDeInit() : stm32l4xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32l4xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32l4xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Transmit() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32l4xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32l4xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32l4xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32l4xx_hal_irda.c
  • HAL_IWDG_Init() : stm32l4xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32l4xx_hal_iwdg.c
  • HAL_LCD_Clear() : stm32l4xx_hal_lcd.c
  • HAL_LCD_DeInit() : stm32l4xx_hal_lcd.c
  • HAL_LCD_GetError() : stm32l4xx_hal_lcd.c
  • HAL_LCD_GetState() : stm32l4xx_hal_lcd.c
  • HAL_LCD_Init() : stm32l4xx_hal_lcd.c
  • HAL_LCD_MspDeInit() : stm32l4xx_hal_lcd.c
  • HAL_LCD_MspInit() : stm32l4xx_hal_lcd.c
  • HAL_LCD_UpdateDisplayRequest() : stm32l4xx_hal_lcd.c
  • HAL_LCD_Write() : stm32l4xx_hal_lcd.c
  • HAL_LIN_Init() : stm32l4xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32l4xx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_CompareWriteCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_DeInit() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_DirectionUpCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_GetState() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_Init() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_IRQHandler() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_MspDeInit() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_ReadAutoReload() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_ReadCompare() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_ReadCounter() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32l4xx_hal_lptim.c , stm32l4xx_hal_lptim.h
  • HAL_MPU_ConfigRegion() : stm32l4xx_hal_cortex.c
  • HAL_MPU_Disable() : stm32l4xx_hal_cortex.h
  • HAL_MPU_Enable() : stm32l4xx_hal_cortex.h
  • HAL_MspDeInit() : stm32l4xx_hal.c
  • HAL_MspInit() : stm32l4xx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32l4xx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32l4xx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32l4xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32l4xx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32l4xx_hal_uart_ex.c
  • HAL_NAND_Address_Inc() : stm32l4xx_hal_nand.c
  • HAL_NAND_DeInit() : stm32l4xx_hal_nand.c
  • HAL_NAND_ECC_Disable() : stm32l4xx_hal_nand.c
  • HAL_NAND_ECC_Enable() : stm32l4xx_hal_nand.c
  • HAL_NAND_Erase_Block() : stm32l4xx_hal_nand.c
  • HAL_NAND_GetECC() : stm32l4xx_hal_nand.c
  • HAL_NAND_GetState() : stm32l4xx_hal_nand.c
  • HAL_NAND_Init() : stm32l4xx_hal_nand.c
  • HAL_NAND_IRQHandler() : stm32l4xx_hal_nand.c
  • HAL_NAND_ITCallback() : stm32l4xx_hal_nand.c
  • HAL_NAND_MspDeInit() : stm32l4xx_hal_nand.c
  • HAL_NAND_MspInit() : stm32l4xx_hal_nand.c
  • HAL_NAND_Read_ID() : stm32l4xx_hal_nand.c
  • HAL_NAND_Read_Page() : stm32l4xx_hal_nand.c
  • HAL_NAND_Read_SpareArea() : stm32l4xx_hal_nand.c
  • HAL_NAND_Read_Status() : stm32l4xx_hal_nand.c , stm32l4xx_hal_nand.h
  • HAL_NAND_Reset() : stm32l4xx_hal_nand.c
  • HAL_NAND_Write_Page() : stm32l4xx_hal_nand.c
  • HAL_NAND_Write_SpareArea() : stm32l4xx_hal_nand.c
  • HAL_NOR_DeInit() : stm32l4xx_hal_nor.c
  • HAL_NOR_Erase_Block() : stm32l4xx_hal_nor.c
  • HAL_NOR_Erase_Chip() : stm32l4xx_hal_nor.c
  • HAL_NOR_GetState() : stm32l4xx_hal_nor.c
  • HAL_NOR_GetStatus() : stm32l4xx_hal_nor.c
  • HAL_NOR_Init() : stm32l4xx_hal_nor.c
  • HAL_NOR_MspDeInit() : stm32l4xx_hal_nor.c
  • HAL_NOR_MspInit() : stm32l4xx_hal_nor.c
  • HAL_NOR_MspWait() : stm32l4xx_hal_nor.c
  • HAL_NOR_Program() : stm32l4xx_hal_nor.c
  • HAL_NOR_ProgramBuffer() : stm32l4xx_hal_nor.c
  • HAL_NOR_Read() : stm32l4xx_hal_nor.c
  • HAL_NOR_Read_CFI() : stm32l4xx_hal_nor.c
  • HAL_NOR_Read_ID() : stm32l4xx_hal_nor.c
  • HAL_NOR_ReadBuffer() : stm32l4xx_hal_nor.c
  • HAL_NOR_ReturnToReadMode() : stm32l4xx_hal_nor.c
  • HAL_NOR_WriteOperation_Disable() : stm32l4xx_hal_nor.c
  • HAL_NOR_WriteOperation_Enable() : stm32l4xx_hal_nor.c
  • HAL_NVIC_ClearPendingIRQ() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32l4xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32l4xx_hal_cortex.c
  • HAL_OPAMP_DeInit() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_GetState() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_GetTrimOffset() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_Init() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_Lock() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_MspDeInit() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_MspInit() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_SelfCalibrate() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_Start() : stm32l4xx_hal_opamp.c
  • HAL_OPAMP_Stop() : stm32l4xx_hal_opamp.c
  • HAL_OPAMPEx_SelfCalibrateAll() : stm32l4xx_hal_opamp_ex.c , stm32l4xx_hal_opamp_ex.h
  • HAL_OPAMPEx_Unlock() : stm32l4xx_hal_opamp_ex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32l4xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32l4xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32l4xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32l4xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32l4xx_hal_pcd.c
  • HAL_PCD_Init() : stm32l4xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32l4xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_MspDeInit() : stm32l4xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32l4xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32l4xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCD_Start() : stm32l4xx_hal_pcd.c
  • HAL_PCD_Stop() : stm32l4xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32l4xx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_SetRxFiFo() : stm32l4xx_hal_pcd_ex.c
  • HAL_PCDEx_SetTxFiFo() : stm32l4xx_hal_pcd_ex.c
  • HAL_PWR_ConfigPVD() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32l4xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32l4xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32l4xx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32l4xx_hal_pwr.c
  • HAL_PWREx_ConfigPVM() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullDown() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullUp() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableInternalWakeUpLine() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowPowerRunMode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePullUpPullDownConfig() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM1() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM2() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM3() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM4() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableSRAM2ContentRetention() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableVddIO2() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_DisableVddUSB() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullDown() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullUp() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableInternalWakeUpLine() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowPowerRunMode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePullUpPullDownConfig() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM1() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM2() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM3() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM4() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableSRAM2ContentRetention() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableVddIO2() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnableVddUSB() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSHUTDOWNMode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP0Mode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP1Mode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP2Mode() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_IRQHandler() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM1Callback() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM2Callback() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM3Callback() : stm32l4xx_hal_pwr_ex.c
  • HAL_PWREx_PVM4Callback() : stm32l4xx_hal_pwr_ex.c
  • HAL_QSPI_Abort() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_Abort_IT() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_AbortCpltCallback() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_AutoPolling() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_AutoPolling_IT() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_CmdCpltCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Command() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_Command_IT() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_DeInit() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_ErrorCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_FifoThresholdCallback() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_GetError() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_GetFifoThreshold() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_GetState() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Init() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_IRQHandler() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_MemoryMapped() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_MspDeInit() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_MspInit() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_Receive() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Receive_DMA() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Receive_IT() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_RxCpltCallback() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_RxHalfCpltCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_SetFifoThreshold() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_SetTimeout() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_StatusMatchCallback() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_TimeOutCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Transmit() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Transmit_DMA() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_Transmit_IT() : stm32l4xx_hal_qspi.h , stm32l4xx_hal_qspi.c
  • HAL_QSPI_TxCpltCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_QSPI_TxHalfCpltCallback() : stm32l4xx_hal_qspi.c , stm32l4xx_hal_qspi.h
  • HAL_RCC_ClockConfig() : stm32l4xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32l4xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32l4xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32l4xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32l4xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32l4xx_hal_rcc.c
  • HAL_RCC_NMI_IRQHandler() : stm32l4xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32l4xx_hal_rcc.c
  • HAL_RCCEx_DisableLSCO() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSECSS() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisableMSIPLLMode() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisablePLLSAI1() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_DisablePLLSAI2() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSCO() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS_IT() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnableMSIPLLMode() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnablePLLSAI1() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_EnablePLLSAI2() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_Callback() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_IRQHandler() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_StandbyMSIRangeConfig() : stm32l4xx_hal_rcc_ex.c
  • HAL_RCCEx_WakeUpStopCLKConfig() : stm32l4xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32l4xx_hal.c
  • HAL_RNG_DeInit() : stm32l4xx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32l4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32l4xx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32l4xx_hal_rng.c
  • HAL_RNG_GetRandomNumber() : stm32l4xx_hal_rng.c
  • HAL_RNG_GetRandomNumber_IT() : stm32l4xx_hal_rng.c
  • HAL_RNG_GetState() : stm32l4xx_hal_rng.c
  • HAL_RNG_Init() : stm32l4xx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32l4xx_hal_rng.c
  • HAL_RNG_MspDeInit() : stm32l4xx_hal_rng.c
  • HAL_RNG_MspInit() : stm32l4xx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32l4xx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32l4xx_hal_rng.c
  • HAL_RS485Ex_Init() : stm32l4xx_hal_uart_ex.c
  • HAL_RTC_AlarmAEventCallback() : stm32l4xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32l4xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32l4xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32l4xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32l4xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32l4xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32l4xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32l4xx_hal_rtc.c
  • HAL_RTC_Init() : stm32l4xx_hal_rtc.c
  • HAL_RTC_MspDeInit() : stm32l4xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32l4xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32l4xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32l4xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32l4xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32l4xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32l4xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32l4xx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32l4xx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32l4xx_hal_rtc_ex.c
  • HAL_SAI_Abort() : stm32l4xx_hal_sai.c
  • HAL_SAI_DeInit() : stm32l4xx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32l4xx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32l4xx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32l4xx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32l4xx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32l4xx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32l4xx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32l4xx_hal_sai.c
  • HAL_SAI_ErrorCallback() : stm32l4xx_hal_sai.c
  • HAL_SAI_GetError() : stm32l4xx_hal_sai.c
  • HAL_SAI_GetState() : stm32l4xx_hal_sai.c
  • HAL_SAI_Init() : stm32l4xx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32l4xx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32l4xx_hal_sai.c
  • HAL_SAI_MspDeInit() : stm32l4xx_hal_sai.c
  • HAL_SAI_MspInit() : stm32l4xx_hal_sai.c
  • HAL_SAI_Receive() : stm32l4xx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32l4xx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32l4xx_hal_sai.c
  • HAL_SAI_RxCpltCallback() : stm32l4xx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32l4xx_hal_sai.c
  • HAL_SAI_Transmit() : stm32l4xx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32l4xx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32l4xx_hal_sai.c
  • HAL_SAI_TxCpltCallback() : stm32l4xx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32l4xx_hal_sai.c
  • HAL_SD_CheckReadOperation() : stm32l4xx_hal_sd.c
  • HAL_SD_CheckWriteOperation() : stm32l4xx_hal_sd.c
  • HAL_SD_DeInit() : stm32l4xx_hal_sd.c
  • HAL_SD_DMA_RxCpltCallback() : stm32l4xx_hal_sd.c
  • HAL_SD_DMA_RxErrorCallback() : stm32l4xx_hal_sd.c
  • HAL_SD_DMA_TxCpltCallback() : stm32l4xx_hal_sd.c
  • HAL_SD_DMA_TxErrorCallback() : stm32l4xx_hal_sd.c
  • HAL_SD_Erase() : stm32l4xx_hal_sd.c
  • HAL_SD_Get_CardInfo() : stm32l4xx_hal_sd.c
  • HAL_SD_GetCardStatus() : stm32l4xx_hal_sd.c
  • HAL_SD_GetStatus() : stm32l4xx_hal_sd.c
  • HAL_SD_HighSpeed() : stm32l4xx_hal_sd.c
  • HAL_SD_Init() : stm32l4xx_hal_sd.c
  • HAL_SD_IRQHandler() : stm32l4xx_hal_sd.c
  • HAL_SD_MspDeInit() : stm32l4xx_hal_sd.c
  • HAL_SD_MspInit() : stm32l4xx_hal_sd.c
  • HAL_SD_ReadBlocks() : stm32l4xx_hal_sd.c
  • HAL_SD_ReadBlocks_DMA() : stm32l4xx_hal_sd.c
  • HAL_SD_SendSDStatus() : stm32l4xx_hal_sd.c
  • HAL_SD_StopTransfer() : stm32l4xx_hal_sd.c
  • HAL_SD_WideBusOperation_Config() : stm32l4xx_hal_sd.c
  • HAL_SD_WriteBlocks() : stm32l4xx_hal_sd.c
  • HAL_SD_WriteBlocks_DMA() : stm32l4xx_hal_sd.c
  • HAL_SD_XferCpltCallback() : stm32l4xx_hal_sd.c
  • HAL_SD_XferErrorCallback() : stm32l4xx_hal_sd.c
  • HAL_SMARTCARD_DeInit() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorCallback() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_MspDeInit() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32l4xx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32l4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32l4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32l4xx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32l4xx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_DisableListen_IT() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_EnableAlert_IT() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_EnableListen_IT() : stm32l4xx_hal_smbus.c , stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ER_IRQHandler() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_ErrorCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32l4xx_hal_smbus.h , stm32l4xx_hal_smbus.c
  • HAL_SMBUS_ListenCpltCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32l4xx_hal_smbus.c , stm32l4xx_hal_smbus.h
  • HAL_SMBUS_Master_Receive_IT() : stm32l4xx_hal_smbus.c , stm32l4xx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32l4xx_hal_smbus.c , stm32l4xx_hal_smbus.h
  • HAL_SMBUS_MasterRxCpltCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_MspDeInit() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_MspInit() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32l4xx_hal_smbus.c , stm32l4xx_hal_smbus.h
  • HAL_SMBUS_Slave_Transmit_IT() : stm32l4xx_hal_smbus.c , stm32l4xx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32l4xx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32l4xx_hal_smbus.c
  • HAL_SPI_DeInit() : stm32l4xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32l4xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32l4xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32l4xx_hal_spi.c
  • HAL_SPI_ErrorCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_GetError() : stm32l4xx_hal_spi.c
  • HAL_SPI_GetState() : stm32l4xx_hal_spi.c
  • HAL_SPI_Init() : stm32l4xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32l4xx_hal_spi.c
  • HAL_SPI_MspDeInit() : stm32l4xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32l4xx_hal_spi.c
  • HAL_SPI_Receive() : stm32l4xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32l4xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32l4xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_Transmit() : stm32l4xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32l4xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32l4xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32l4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32l4xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32l4xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32l4xx_hal_spi.c
  • HAL_SPIEx_FlushRxFifo() : stm32l4xx_hal_spi_ex.c
  • HAL_SRAM_DeInit() : stm32l4xx_hal_sram.c
  • HAL_SRAM_DMA_XferCpltCallback() : stm32l4xx_hal_sram.c
  • HAL_SRAM_DMA_XferErrorCallback() : stm32l4xx_hal_sram.c
  • HAL_SRAM_GetState() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Init() : stm32l4xx_hal_sram.c
  • HAL_SRAM_MspDeInit() : stm32l4xx_hal_sram.c
  • HAL_SRAM_MspInit() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Read_16b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Read_32b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Read_8b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Read_DMA() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Write_16b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Write_32b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Write_8b() : stm32l4xx_hal_sram.c
  • HAL_SRAM_Write_DMA() : stm32l4xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Disable() : stm32l4xx_hal_sram.c
  • HAL_SRAM_WriteOperation_Enable() : stm32l4xx_hal_sram.c
  • HAL_SuspendTick() : stm32l4xx_hal.c
  • HAL_SWPMI_DeInit() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_DisableLoopback() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_DMAStop() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_EnableLoopback() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ErrorCallback() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_GetError() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_GetState() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_Init() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_IRQHandler() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_MspDeInit() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_MspInit() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_Receive() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_Receive_DMA() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_Receive_IT() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_RxCpltCallback() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_RxHalfCpltCallback() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_Transmit() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_Transmit_DMA() : stm32l4xx_hal_swpmi.h , stm32l4xx_hal_swpmi.c
  • HAL_SWPMI_Transmit_IT() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_TxCpltCallback() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_TxHalfCpltCallback() : stm32l4xx_hal_swpmi.c , stm32l4xx_hal_swpmi.h
  • HAL_SYSCFG_DisableIOAnalogSwitchBooster() : stm32l4xx_hal.c
  • HAL_SYSCFG_DisableMemorySwappingBank() : stm32l4xx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32l4xx_hal.c
  • HAL_SYSCFG_EnableIOAnalogSwitchBooster() : stm32l4xx_hal.c
  • HAL_SYSCFG_EnableMemorySwappingBank() : stm32l4xx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32l4xx_hal.c
  • HAL_SYSCFG_SRAM2Erase() : stm32l4xx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32l4xx_hal.c
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32l4xx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32l4xx_hal.c
  • HAL_SYSTICK_Callback() : stm32l4xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32l4xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32l4xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32l4xx_hal_cortex.c
  • HAL_TIM_Base_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32l4xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32l4xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32l4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32l4xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32l4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32l4xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32l4xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_ConfigChannel() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32l4xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32l4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32l4xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32l4xx_hal_tim.c
  • HAL_TIM_TriggerCallback() : stm32l4xx_hal_tim.c
  • HAL_TIMEx_BreakCallback() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32l4xx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32l4xx_hal_tim_ex.c
  • HAL_TSC_ConvCpltCallback() : stm32l4xx_hal_tsc.c
  • HAL_TSC_DeInit() : stm32l4xx_hal_tsc.c
  • HAL_TSC_ErrorCallback() : stm32l4xx_hal_tsc.c
  • HAL_TSC_GetState() : stm32l4xx_hal_tsc.c
  • HAL_TSC_GroupGetStatus() : stm32l4xx_hal_tsc.c
  • HAL_TSC_GroupGetValue() : stm32l4xx_hal_tsc.c
  • HAL_TSC_Init() : stm32l4xx_hal_tsc.c
  • HAL_TSC_IOConfig() : stm32l4xx_hal_tsc.c
  • HAL_TSC_IODischarge() : stm32l4xx_hal_tsc.c
  • HAL_TSC_IRQHandler() : stm32l4xx_hal_tsc.c
  • HAL_TSC_MspDeInit() : stm32l4xx_hal_tsc.c
  • HAL_TSC_MspInit() : stm32l4xx_hal_tsc.c
  • HAL_TSC_PollForAcquisition() : stm32l4xx_hal_tsc.c
  • HAL_TSC_Start() : stm32l4xx_hal_tsc.c
  • HAL_TSC_Start_IT() : stm32l4xx_hal_tsc.c
  • HAL_TSC_Stop() : stm32l4xx_hal_tsc.c
  • HAL_TSC_Stop_IT() : stm32l4xx_hal_tsc.c
  • HAL_UART_DeInit() : stm32l4xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32l4xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32l4xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32l4xx_hal_uart.c
  • HAL_UART_ErrorCallback() : stm32l4xx_hal_uart.c
  • HAL_UART_GetError() : stm32l4xx_hal_uart.c
  • HAL_UART_GetState() : stm32l4xx_hal_uart.c
  • HAL_UART_Init() : stm32l4xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32l4xx_hal_uart.c
  • HAL_UART_MspDeInit() : stm32l4xx_hal_uart.c
  • HAL_UART_MspInit() : stm32l4xx_hal_uart.c
  • HAL_UART_Receive() : stm32l4xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32l4xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32l4xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32l4xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32l4xx_hal_uart.c
  • HAL_UART_Transmit() : stm32l4xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32l4xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32l4xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32l4xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32l4xx_hal_uart.c
  • HAL_UARTEx_DisableStopMode() : stm32l4xx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32l4xx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32l4xx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32l4xx_hal_uart_ex.c
  • HAL_USART_DeInit() : stm32l4xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32l4xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32l4xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32l4xx_hal_usart.c
  • HAL_USART_ErrorCallback() : stm32l4xx_hal_usart.c
  • HAL_USART_GetError() : stm32l4xx_hal_usart.c
  • HAL_USART_GetState() : stm32l4xx_hal_usart.c
  • HAL_USART_Init() : stm32l4xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32l4xx_hal_usart.c
  • HAL_USART_MspDeInit() : stm32l4xx_hal_usart.c
  • HAL_USART_MspInit() : stm32l4xx_hal_usart.c
  • HAL_USART_Receive() : stm32l4xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32l4xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32l4xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32l4xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32l4xx_hal_usart.c
  • HAL_USART_Transmit() : stm32l4xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32l4xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32l4xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32l4xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32l4xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32l4xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32l4xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32l4xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32l4xx_hal_usart.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32l4xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32l4xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32l4xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32l4xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32l4xx_hal_wwdg.c
  • HCD_HC_IN_IRQHandler() : stm32l4xx_hal_hcd.c
  • HCD_HC_OUT_IRQHandler() : stm32l4xx_hal_hcd.c
  • HCD_Port_IRQHandler() : stm32l4xx_hal_hcd.c
  • HCD_RXQLVL_IRQHandler() : stm32l4xx_hal_hcd.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- i -

  • I2C_Disable_IRQ() : stm32l4xx_hal_i2c.c
  • I2C_DMAAbort() : stm32l4xx_hal_i2c.c
  • I2C_DMAError() : stm32l4xx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32l4xx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32l4xx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32l4xx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32l4xx_hal_i2c.c
  • I2C_Enable_IRQ() : stm32l4xx_hal_i2c.c
  • I2C_Flush_TXDR() : stm32l4xx_hal_i2c.c
  • I2C_IsAcknowledgeFailed() : stm32l4xx_hal_i2c.c
  • I2C_ITAddrCplt() : stm32l4xx_hal_i2c.c
  • I2C_ITError() : stm32l4xx_hal_i2c.c
  • I2C_ITListenCplt() : stm32l4xx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32l4xx_hal_i2c.c
  • I2C_ITMasterSequentialCplt() : stm32l4xx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32l4xx_hal_i2c.c
  • I2C_ITSlaveSequentialCplt() : stm32l4xx_hal_i2c.c
  • I2C_Master_ISR_DMA() : stm32l4xx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32l4xx_hal_i2c.c
  • I2C_RequestMemoryRead() : stm32l4xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32l4xx_hal_i2c.c
  • I2C_Slave_ISR_DMA() : stm32l4xx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32l4xx_hal_i2c.c
  • I2C_TransferConfig() : stm32l4xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32l4xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32l4xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32l4xx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32l4xx_hal_i2c.c
  • IC1Config() : stm32l4xx_ll_tim.c
  • IC2Config() : stm32l4xx_ll_tim.c
  • IC3Config() : stm32l4xx_ll_tim.c
  • IC4Config() : stm32l4xx_ll_tim.c
  • IRDA_CheckIdleState() : stm32l4xx_hal_irda.c
  • IRDA_DMAError() : stm32l4xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32l4xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32l4xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32l4xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32l4xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32l4xx_hal_irda.c
  • IRDA_Receive_IT() : stm32l4xx_hal_irda.c
  • IRDA_SetConfig() : stm32l4xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32l4xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32l4xx_hal_irda.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
  • Globals
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  • u

- l -

  • LCD_WaitForSynchro() : stm32l4xx_hal_lcd.c
  • LL_ADC_ClearFlag_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_ClearFlag_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32l4xx_ll_adc.c
  • LL_ADC_CommonInit() : stm32l4xx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32l4xx_ll_adc.c
  • LL_ADC_ConfigAnalogWDThresholds() : stm32l4xx_ll_adc.h
  • LL_ADC_ConfigOverSamplingRatioShift() : stm32l4xx_ll_adc.h
  • LL_ADC_DeInit() : stm32l4xx_ll_adc.c
  • LL_ADC_Disable() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableDeepPowerDown() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableInternalRegulator() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_DisableIT_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32l4xx_ll_adc.h
  • LL_ADC_Enable() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableDeepPowerDown() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableInternalRegulator() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_EnableIT_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32l4xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32l4xx_ll_adc.h
  • LL_ADC_GetCalibrationFactor() : stm32l4xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32l4xx_ll_adc.h
  • LL_ADC_GetChannelSingleDiff() : stm32l4xx_ll_adc.h
  • LL_ADC_GetCommonClock() : stm32l4xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32l4xx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32l4xx_ll_adc.h
  • LL_ADC_GetLowPowerMode() : stm32l4xx_ll_adc.h
  • LL_ADC_GetMultiDMATransfer() : stm32l4xx_ll_adc.h
  • LL_ADC_GetMultimode() : stm32l4xx_ll_adc.h
  • LL_ADC_GetMultiTwoSamplingDelay() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOffsetChannel() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOffsetLevel() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOffsetState() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOverSamplingDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOverSamplingRatio() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOverSamplingScope() : stm32l4xx_ll_adc.h
  • LL_ADC_GetOverSamplingShift() : stm32l4xx_ll_adc.h
  • LL_ADC_GetResolution() : stm32l4xx_ll_adc.h
  • LL_ADC_Init() : stm32l4xx_ll_adc.c
  • LL_ADC_INJ_ConfigQueueContext() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetQueueMode() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerEdge() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32l4xx_ll_adc.c
  • LL_ADC_INJ_IsConversionOngoing() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_IsStopConversionOngoing() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData10() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData6() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData8() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetQueueMode() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerEdge() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SetTrigSource() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_StartConversion() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_StopConversion() : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32l4xx_ll_adc.c
  • LL_ADC_IsActiveFlag_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32l4xx_ll_adc.h
  • LL_ADC_IsDeepPowerDownEnabled() : stm32l4xx_ll_adc.h
  • LL_ADC_IsDisableOngoing() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_ADRDY() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD2() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD3() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOSMP() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOC() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JQOVF() : stm32l4xx_ll_adc.h
  • LL_ADC_IsEnabledIT_OVR() : stm32l4xx_ll_adc.h
  • LL_ADC_IsInternalRegulatorEnabled() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetOverrun() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetTriggerEdge() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32l4xx_ll_adc.c
  • LL_ADC_REG_IsConversionOngoing() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_IsStopConversionOngoing() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData10() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData6() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData8() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_ReadMultiConversionData32() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetOverrun() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetTriggerEdge() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SetTrigSource() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_StopConversion() : stm32l4xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32l4xx_ll_adc.c
  • LL_ADC_SetAnalogWDMonitChannels() : stm32l4xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32l4xx_ll_adc.h
  • LL_ADC_SetCalibrationFactor() : stm32l4xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32l4xx_ll_adc.h
  • LL_ADC_SetChannelSingleDiff() : stm32l4xx_ll_adc.h
  • LL_ADC_SetCommonClock() : stm32l4xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32l4xx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32l4xx_ll_adc.h
  • LL_ADC_SetLowPowerMode() : stm32l4xx_ll_adc.h
  • LL_ADC_SetMultiDMATransfer() : stm32l4xx_ll_adc.h
  • LL_ADC_SetMultimode() : stm32l4xx_ll_adc.h
  • LL_ADC_SetMultiTwoSamplingDelay() : stm32l4xx_ll_adc.h
  • LL_ADC_SetOffset() : stm32l4xx_ll_adc.h
  • LL_ADC_SetOffsetState() : stm32l4xx_ll_adc.h
  • LL_ADC_SetOverSamplingDiscont() : stm32l4xx_ll_adc.h
  • LL_ADC_SetOverSamplingScope() : stm32l4xx_ll_adc.h
  • LL_ADC_SetResolution() : stm32l4xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32l4xx_ll_adc.h
  • LL_ADC_StructInit() : stm32l4xx_ll_adc.c
  • LL_AHB1_GRP1_DisableClock() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClock() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClock() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_ForceReset() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClock() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClock() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_ForceReset() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_DisableClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_EnableClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_ForceReset() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_DisableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_EnableClockStopSleep() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32l4xx_ll_bus.h
  • LL_COMP_ConfigInputs() : stm32l4xx_ll_comp.h
  • LL_COMP_DeInit() : stm32l4xx_ll_comp.c
  • LL_COMP_Disable() : stm32l4xx_ll_comp.h
  • LL_COMP_Enable() : stm32l4xx_ll_comp.h
  • LL_COMP_GetCommonWindowMode() : stm32l4xx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32l4xx_ll_comp.h
  • LL_COMP_GetInputInverting() : stm32l4xx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32l4xx_ll_comp.h
  • LL_COMP_GetInputNonInverting() : stm32l4xx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32l4xx_ll_comp.h
  • LL_COMP_GetOutputBlankingSource() : stm32l4xx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32l4xx_ll_comp.h
  • LL_COMP_GetPowerMode() : stm32l4xx_ll_comp.h
  • LL_COMP_Init() : stm32l4xx_ll_comp.c
  • LL_COMP_IsEnabled() : stm32l4xx_ll_comp.h
  • LL_COMP_IsLocked() : stm32l4xx_ll_comp.h
  • LL_COMP_Lock() : stm32l4xx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32l4xx_ll_comp.h
  • LL_COMP_SetCommonWindowMode() : stm32l4xx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32l4xx_ll_comp.h
  • LL_COMP_SetInputInverting() : stm32l4xx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32l4xx_ll_comp.h
  • LL_COMP_SetInputNonInverting() : stm32l4xx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32l4xx_ll_comp.h
  • LL_COMP_SetOutputBlankingSource() : stm32l4xx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32l4xx_ll_comp.h
  • LL_COMP_SetPowerMode() : stm32l4xx_ll_comp.h
  • LL_COMP_StructInit() : stm32l4xx_ll_comp.c
  • LL_CPUID_GetConstant() : stm32l4xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32l4xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32l4xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32l4xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32l4xx_ll_cortex.h
  • LL_CRC_DeInit() : stm32l4xx_ll_crc.c
  • LL_CRC_FeedData16() : stm32l4xx_ll_crc.h
  • LL_CRC_FeedData32() : stm32l4xx_ll_crc.h
  • LL_CRC_FeedData8() : stm32l4xx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32l4xx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32l4xx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32l4xx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32l4xx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32l4xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32l4xx_ll_crc.h
  • LL_CRC_ReadData16() : stm32l4xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32l4xx_ll_crc.h
  • LL_CRC_ReadData7() : stm32l4xx_ll_crc.h
  • LL_CRC_ReadData8() : stm32l4xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32l4xx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32l4xx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32l4xx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32l4xx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32l4xx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32l4xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32l4xx_ll_crc.h
  • LL_DAC_ClearFlag_DMAUDR1() : stm32l4xx_ll_dac.h
  • LL_DAC_ClearFlag_DMAUDR2() : stm32l4xx_ll_dac.h
  • LL_DAC_ConfigOutput() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertData12LeftAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertData12RightAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertData8RightAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertDualData12LeftAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertDualData12RightAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_ConvertDualData8RightAligned() : stm32l4xx_ll_dac.h
  • LL_DAC_DeInit() : stm32l4xx_ll_dac.c
  • LL_DAC_Disable() : stm32l4xx_ll_dac.h
  • LL_DAC_DisableDMAReq() : stm32l4xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR1() : stm32l4xx_ll_dac.h
  • LL_DAC_DisableIT_DMAUDR2() : stm32l4xx_ll_dac.h
  • LL_DAC_DisableTrigger() : stm32l4xx_ll_dac.h
  • LL_DAC_DMA_GetRegAddr() : stm32l4xx_ll_dac.h
  • LL_DAC_Enable() : stm32l4xx_ll_dac.h
  • LL_DAC_EnableDMAReq() : stm32l4xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR1() : stm32l4xx_ll_dac.h
  • LL_DAC_EnableIT_DMAUDR2() : stm32l4xx_ll_dac.h
  • LL_DAC_EnableTrigger() : stm32l4xx_ll_dac.h
  • LL_DAC_GetMode() : stm32l4xx_ll_dac.h
  • LL_DAC_GetOutputBuffer() : stm32l4xx_ll_dac.h
  • LL_DAC_GetOutputConnection() : stm32l4xx_ll_dac.h
  • LL_DAC_GetOutputMode() : stm32l4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldHoldTime() : stm32l4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldRefreshTime() : stm32l4xx_ll_dac.h
  • LL_DAC_GetSampleAndHoldSampleTime() : stm32l4xx_ll_dac.h
  • LL_DAC_GetTriggerSource() : stm32l4xx_ll_dac.h
  • LL_DAC_GetTrimmingValue() : stm32l4xx_ll_dac.h
  • LL_DAC_GetWaveAutoGeneration() : stm32l4xx_ll_dac.h
  • LL_DAC_GetWaveMode() : stm32l4xx_ll_dac.h
  • LL_DAC_GetWaveNoiseLFSR() : stm32l4xx_ll_dac.h
  • LL_DAC_GetWaveTriangleAmplitude() : stm32l4xx_ll_dac.h
  • LL_DAC_Init() : stm32l4xx_ll_dac.c
  • LL_DAC_IsActiveFlag_BWST1() : stm32l4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_BWST2() : stm32l4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL1() : stm32l4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_CAL2() : stm32l4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR1() : stm32l4xx_ll_dac.h
  • LL_DAC_IsActiveFlag_DMAUDR2() : stm32l4xx_ll_dac.h
  • LL_DAC_IsDMAReqEnabled() : stm32l4xx_ll_dac.h
  • LL_DAC_IsEnabled() : stm32l4xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR1() : stm32l4xx_ll_dac.h
  • LL_DAC_IsEnabledIT_DMAUDR2() : stm32l4xx_ll_dac.h
  • LL_DAC_IsTriggerEnabled() : stm32l4xx_ll_dac.h
  • LL_DAC_RetrieveOutputData() : stm32l4xx_ll_dac.h
  • LL_DAC_SetMode() : stm32l4xx_ll_dac.h
  • LL_DAC_SetOutputBuffer() : stm32l4xx_ll_dac.h
  • LL_DAC_SetOutputConnection() : stm32l4xx_ll_dac.h
  • LL_DAC_SetOutputMode() : stm32l4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldHoldTime() : stm32l4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldRefreshTime() : stm32l4xx_ll_dac.h
  • LL_DAC_SetSampleAndHoldSampleTime() : stm32l4xx_ll_dac.h
  • LL_DAC_SetTriggerSource() : stm32l4xx_ll_dac.h
  • LL_DAC_SetTrimmingValue() : stm32l4xx_ll_dac.h
  • LL_DAC_SetWaveAutoGeneration() : stm32l4xx_ll_dac.h
  • LL_DAC_SetWaveMode() : stm32l4xx_ll_dac.h
  • LL_DAC_SetWaveNoiseLFSR() : stm32l4xx_ll_dac.h
  • LL_DAC_SetWaveTriangleAmplitude() : stm32l4xx_ll_dac.h
  • LL_DAC_StructInit() : stm32l4xx_ll_dac.c
  • LL_DAC_TrigSWConversion() : stm32l4xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_FreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_UnFreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32l4xx_ll_system.h
  • LL_DBGMCU_DisableDBGSleepMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_EnableDBGSleepMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32l4xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32l4xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32l4xx_ll_system.h
  • LL_DBGMCU_GetTracePinAssignment() : stm32l4xx_ll_system.h
  • LL_DBGMCU_SetTracePinAssignment() : stm32l4xx_ll_system.h
  • LL_DMA_ClearFlag_GI1() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_GI7() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32l4xx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32l4xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32l4xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32l4xx_ll_dma.h
  • LL_DMA_DeInit() : stm32l4xx_ll_dma.c
  • LL_DMA_DisableChannel() : stm32l4xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32l4xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32l4xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32l4xx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32l4xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32l4xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32l4xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32l4xx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32l4xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32l4xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32l4xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32l4xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32l4xx_ll_dma.h
  • LL_DMA_GetMode() : stm32l4xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32l4xx_ll_dma.h
  • LL_DMA_GetPeriphRequest() : stm32l4xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32l4xx_ll_dma.h
  • LL_DMA_Init() : stm32l4xx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI7() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32l4xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32l4xx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32l4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32l4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32l4xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32l4xx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32l4xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32l4xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32l4xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32l4xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32l4xx_ll_dma.h
  • LL_DMA_SetMode() : stm32l4xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32l4xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32l4xx_ll_dma.h
  • LL_DMA_SetPeriphRequest() : stm32l4xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32l4xx_ll_dma.h
  • LL_DMA_StructInit() : stm32l4xx_ll_dma.c
  • LL_EXTI_ClearFlag_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_ClearFlag_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32l4xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableEvent_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableIT_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableEvent_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableIT_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_GenerateSWI_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_Init() : stm32l4xx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsActiveFlag_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32l4xx_ll_exti.h
  • LL_EXTI_ReadFlag_32_63() : stm32l4xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32l4xx_ll_exti.c
  • LL_FLASH_DisableDataCache() : stm32l4xx_ll_system.h
  • LL_FLASH_DisableDataCacheReset() : stm32l4xx_ll_system.h
  • LL_FLASH_DisableInstCache() : stm32l4xx_ll_system.h
  • LL_FLASH_DisableInstCacheReset() : stm32l4xx_ll_system.h
  • LL_FLASH_DisablePrefetch() : stm32l4xx_ll_system.h
  • LL_FLASH_DisableRunPowerDown() : stm32l4xx_ll_system.h
  • LL_FLASH_DisableSleepPowerDown() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableDataCache() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableDataCacheReset() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableInstCache() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableInstCacheReset() : stm32l4xx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableRunPowerDown() : stm32l4xx_ll_system.h
  • LL_FLASH_EnableSleepPowerDown() : stm32l4xx_ll_system.h
  • LL_FLASH_GetLatency() : stm32l4xx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32l4xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32l4xx_ll_system.h
  • LL_GetFlashSize() : stm32l4xx_ll_utils.h
  • LL_GetPackageType() : stm32l4xx_ll_utils.h
  • LL_GetUID_Word0() : stm32l4xx_ll_utils.h
  • LL_GetUID_Word1() : stm32l4xx_ll_utils.h
  • LL_GetUID_Word2() : stm32l4xx_ll_utils.h
  • LL_GPIO_DeInit() : stm32l4xx_ll_gpio.c
  • LL_GPIO_DisablePinAnalogControl() : stm32l4xx_ll_gpio.h
  • LL_GPIO_EnablePinAnalogControl() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetAFPin_0_7() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32l4xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32l4xx_ll_gpio.h
  • LL_GPIO_Init() : stm32l4xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32l4xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32l4xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32l4xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32l4xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32l4xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32l4xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32l4xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32l4xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32l4xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32l4xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32l4xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32l4xx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32l4xx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32l4xx_ll_cortex.h
  • LL_I2C_AcknowledgeNextData() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32l4xx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32l4xx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32l4xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32l4xx_ll_i2c.c
  • LL_I2C_Disable() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32l4xx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32l4xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32l4xx_ll_i2c.h
  • LL_I2C_Enable() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32l4xx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32l4xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32l4xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32l4xx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32l4xx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32l4xx_ll_i2c.h
  • LL_I2C_Init() : stm32l4xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32l4xx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32l4xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32l4xx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32l4xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32l4xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32l4xx_ll_i2c.h
  • LL_Init1msTick() : stm32l4xx_ll_utils.c
  • LL_InitTick() : stm32l4xx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32l4xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32l4xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32l4xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32l4xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32l4xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32l4xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32l4xx_ll_cortex.h
  • LL_LPTIM_ClearFLAG_ARRM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_ARROK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFLAG_CMPM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPOK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_DOWN() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_EXTTRIG() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ClearFlag_UP() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ConfigClock() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ConfigOutput() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ConfigTrigger() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DeInit() : stm32l4xx_ll_lptim.c
  • LL_LPTIM_Disable() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableEncoderMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARRM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARROK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPOK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_DOWN() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_EXTTRIG() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableIT_UP() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_DisableTimeout() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_Enable() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableEncoderMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARRM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARROK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPOK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_DOWN() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_EXTTRIG() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableIT_UP() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_EnableTimeout() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetAutoReload() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetClockFilter() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetClockPolarity() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetClockSource() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetCompare() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetCounter() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetCounterMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetEncoderMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetPolarity() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetPrescaler() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerFilter() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerPolarity() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetTriggerSource() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetUpdateMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_GetWaveform() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_Init() : stm32l4xx_ll_lptim.c
  • LL_LPTIM_IsActiveFlag_ARRM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARROK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPOK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_DOWN() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_EXTTRIG() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_UP() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabled() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledEncoderMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARRM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARROK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPM() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPOK() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_DOWN() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_EXTTRIG() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_UP() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IsEnabledTimeout() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetAutoReload() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetClockSource() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetCompare() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetCounterMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetEncoderMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetInput1Src() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetInput2Src() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetPolarity() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetPrescaler() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetUpdateMode() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_SetWaveform() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_StartCounter() : stm32l4xx_ll_lptim.h
  • LL_LPTIM_StructInit() : stm32l4xx_ll_lptim.c
  • LL_LPTIM_TrigSw() : stm32l4xx_ll_lptim.h
  • LL_LPUART_ClearFlag_CM() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_FE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_IDLE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_nCTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_NE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_ORE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_PE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TC() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ClearFlag_WKUP() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ConfigCharacter() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ConfigNodeAddress() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DeInit() : stm32l4xx_ll_lpuart.c
  • LL_LPUART_Disable() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableCTSHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDEMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionRx() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDirectionTx() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDMADeactOnRxErr() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_RX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_TX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableHalfDuplex() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableInStopMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CM() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_CTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_ERROR() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_IDLE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_PE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TC() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableIT_WKUP() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableMuteMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableOverrunDetect() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DisableRTSHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DMA_GetRegAddr() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_Enable() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableCTSHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDEMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionRx() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDirectionTx() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDMADeactOnRxErr() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_RX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_TX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableHalfDuplex() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableInStopMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CM() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_CTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_ERROR() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_IDLE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_PE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TC() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableIT_WKUP() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableMuteMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableOverrunDetect() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_EnableRTSHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetBaudRate() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetBinaryDataLogic() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetDataWidth() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetDEAssertionTime() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetDEDeassertionTime() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetDESignalPolarity() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddress() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetNodeAddressLen() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetParity() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetRXPinLevel() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetStopBitsLength() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetTransferBitOrder() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetTransferDirection() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetTXPinLevel() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetTXRXSwap() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetWakeUpMethod() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_GetWKUPType() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_Init() : stm32l4xx_ll_lpuart.c
  • LL_LPUART_IsActiveFlag_BUSY() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CM() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_FE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_IDLE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_nCTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_NE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_ORE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_PE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_REACK() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RWU() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_SBK() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TC() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TEACK() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_WKUP() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabled() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDEMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMADeactOnRxErr() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_RX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_TX() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledHalfDuplex() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledInStopMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CM() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CTS() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_ERROR() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_IDLE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_PE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TC() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_WKUP() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledMuteMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_IsEnabledOverrunDetect() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ReceiveData8() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ReceiveData9() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_RequestBreakSending() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_RequestEnterMuteMode() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_RequestRxDataFlush() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetBaudRate() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetBinaryDataLogic() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetDataWidth() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetDEAssertionTime() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetDEDeassertionTime() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetDESignalPolarity() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetHWFlowCtrl() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetParity() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetRXPinLevel() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetStopBitsLength() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetTransferBitOrder() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetTransferDirection() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetTXPinLevel() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetTXRXSwap() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetWakeUpMethod() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_SetWKUPType() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_StructInit() : stm32l4xx_ll_lpuart.c
  • LL_LPUART_TransmitData8() : stm32l4xx_ll_lpuart.h
  • LL_LPUART_TransmitData9() : stm32l4xx_ll_lpuart.h
  • LL_mDelay() : stm32l4xx_ll_utils.c
  • LL_MPU_ConfigRegion() : stm32l4xx_ll_cortex.h
  • LL_MPU_Disable() : stm32l4xx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32l4xx_ll_cortex.h
  • LL_MPU_Enable() : stm32l4xx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32l4xx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32l4xx_ll_cortex.h
  • LL_OPAMP_DeInit() : stm32l4xx_ll_opamp.c
  • LL_OPAMP_Disable() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_Enable() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetCalibrationSelection() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetCommonPowerRange() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetFunctionalMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetInputInverting() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetInputNonInverting() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetPGAGain() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetPowerMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_GetTrimmingValue() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_Init() : stm32l4xx_ll_opamp.c
  • LL_OPAMP_IsCalibrationOutputSet() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_IsEnabled() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetCalibrationSelection() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetCommonPowerRange() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetFunctionalMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetInputInverting() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetInputNonInverting() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetInvertingInput() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetNonInvertingInput() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetPGAGain() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetPowerMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingMode() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_SetTrimmingValue() : stm32l4xx_ll_opamp.h
  • LL_OPAMP_StructInit() : stm32l4xx_ll_opamp.c
  • LL_PLL_ConfigSystemClock_HSE() : stm32l4xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32l4xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_MSI() : stm32l4xx_ll_utils.c
  • LL_PWR_ClearFlag_SB() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU1() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU2() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU3() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU4() : stm32l4xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU5() : stm32l4xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32l4xx_ll_pwr.c
  • LL_PWR_DisableBatteryCharging() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableBkUpAccess() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullDown() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableGPIOPullUp() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableInternWU() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableLowPowerRunMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisablePUPDCfg() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisablePVM() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableSRAM2Retention() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableVddIO2() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableVddUSB() : stm32l4xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableBatteryCharging() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullDown() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableGPIOPullUp() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableInternWU() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableLowPowerRunMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnablePUPDCfg() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnablePVM() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableSRAM2Retention() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableVddIO2() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableVddUSB() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32l4xx_ll_pwr.h
  • LL_PWR_EnterLowPowerRunMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_ExitLowPowerRunMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_GetBattChargResistor() : stm32l4xx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32l4xx_ll_pwr.h
  • LL_PWR_GetRegulVoltageScaling() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_InternWU() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO1() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO2() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO3() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO4() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPF() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPS() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SB() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOSF() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU1() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU2() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU3() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU4() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU5() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledBatteryCharging() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullDown() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullUp() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledInternWU() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledLowPowerRunMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledPUPDCfg() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledPVM() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledSRAM2Retention() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledVddIO2() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledVddUSB() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32l4xx_ll_pwr.h
  • LL_PWR_IsWakeUpPinPolarityLow() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetBattChargResistor() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetRegulVoltageScaling() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityHigh() : stm32l4xx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityLow() : stm32l4xx_ll_pwr.h
  • LL_RCC_ClearFlag_HSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_MSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLSAI1RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLSAI2RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32l4xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32l4xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32l4xx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_MSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLSAI1RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLSAI2RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_MSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLSAI1RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLSAI2RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32l4xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetClkAfterWakeFromStop() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetDFSDMClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetDFSDMClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetLPTIMClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetLPTIMClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetLPUARTClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetLPUARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetRNGClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetRNGClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetRTCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetSAIClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetSAIClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetSDMMCClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetSDMMCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetSWPMIClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetSWPMIClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetUARTClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetUARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetUSARTClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32l4xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_DisableAutoFromStop() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_DisableInStopMode() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_EnableAutoFromStop() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_EnableInStopMode() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_BORRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_FWRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_MSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_OBLRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLSAI1RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLSAI2RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSECSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_MSIRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLSAI1RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLSAI2RDY() : stm32l4xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_GetSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_SetSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_DisableCSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_EnableCSS() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_IsCSSDetected() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_DisablePLLMode() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_EnablePLLMode() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_EnableRangeSelection() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_GetCalibration() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_GetCalibTrimming() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_GetRange() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_GetRangeAfterStandby() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_IsEnabledRangeSelect() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_SetCalibTrimming() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_SetRange() : stm32l4xx_ll_rcc.h
  • LL_RCC_MSI_SetRangeAfterStandby() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SYS() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SYS() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetDivider() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetN() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetP() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetQ() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_GetR() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_48M() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetN() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetP() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetQ() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetR() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_ConfigDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_ConfigDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_Disable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_DisableDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_DisableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_Enable() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_EnableDomain_ADC() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_EnableDomain_SAI() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_GetN() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_GetP() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_GetR() : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2_IsReady() : stm32l4xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetClkAfterWakeFromStop() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetDFSDMClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetLPTIMClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetLPUARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetRNGClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetSAIClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetSDMMCClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetSWPMIClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetUARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32l4xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32l4xx_ll_rcc.h
  • LL_RNG_ClearFlag_CEIS() : stm32l4xx_ll_rng.h
  • LL_RNG_ClearFlag_SEIS() : stm32l4xx_ll_rng.h
  • LL_RNG_DeInit() : stm32l4xx_ll_rng.c
  • LL_RNG_Disable() : stm32l4xx_ll_rng.h
  • LL_RNG_DisableIT() : stm32l4xx_ll_rng.h
  • LL_RNG_Enable() : stm32l4xx_ll_rng.h
  • LL_RNG_EnableIT() : stm32l4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_CECS() : stm32l4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_CEIS() : stm32l4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_DRDY() : stm32l4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SECS() : stm32l4xx_ll_rng.h
  • LL_RNG_IsActiveFlag_SEIS() : stm32l4xx_ll_rng.h
  • LL_RNG_IsEnabled() : stm32l4xx_ll_rng.h
  • LL_RNG_IsEnabledIT() : stm32l4xx_ll_rng.h
  • LL_RNG_ReadRandData32() : stm32l4xx_ll_rng.h
  • LL_RTC_ALMA_ConfigTime() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32l4xx_ll_rtc.c
  • LL_RTC_ALMA_SetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_ALMB_ConfigTime() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32l4xx_ll_rtc.c
  • LL_RTC_ALMB_SetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_BAK_GetRegister() : stm32l4xx_ll_rtc.h
  • LL_RTC_BAK_SetRegister() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32l4xx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_ITS() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32l4xx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32l4xx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32l4xx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_DeInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_DisableInitMode() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP1() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP2() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP3() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableOutRemap() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32l4xx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP1() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP2() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP3() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableOutRemap() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32l4xx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32l4xx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32l4xx_ll_rtc.c
  • LL_RTC_GetAlarmOutEvent() : stm32l4xx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32l4xx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32l4xx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32l4xx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32l4xx_ll_rtc.h
  • LL_RTC_Init() : stm32l4xx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITS() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP1() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP2() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP3() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32l4xx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32l4xx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32l4xx_ll_rtc.h
  • LL_RTC_StructInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_TAMPER_Disable() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableEraseBKP() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisableMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableEraseBKP() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnableMask() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32l4xx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32l4xx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_DisableInternalEvent() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_EnableInternalEvent() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32l4xx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32l4xx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32l4xx_ll_rtc.h
  • LL_SetSystemCoreClock() : stm32l4xx_ll_utils.c
  • LL_SPI_ClearFlag_CRCERR() : stm32l4xx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32l4xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32l4xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32l4xx_ll_spi.h
  • LL_SPI_DeInit() : stm32l4xx_ll_spi.c
  • LL_SPI_Disable() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32l4xx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32l4xx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32l4xx_ll_spi.h
  • LL_SPI_Enable() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32l4xx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32l4xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32l4xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32l4xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32l4xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32l4xx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32l4xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32l4xx_ll_spi.h
  • LL_SPI_GetDMAParity_RX() : stm32l4xx_ll_spi.h
  • LL_SPI_GetDMAParity_TX() : stm32l4xx_ll_spi.h
  • LL_SPI_GetMode() : stm32l4xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32l4xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32l4xx_ll_spi.h
  • LL_SPI_GetRxFIFOLevel() : stm32l4xx_ll_spi.h
  • LL_SPI_GetRxFIFOThreshold() : stm32l4xx_ll_spi.h
  • LL_SPI_GetStandard() : stm32l4xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32l4xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32l4xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32l4xx_ll_spi.h
  • LL_SPI_GetTxFIFOLevel() : stm32l4xx_ll_spi.h
  • LL_SPI_Init() : stm32l4xx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32l4xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32l4xx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32l4xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32l4xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32l4xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32l4xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32l4xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32l4xx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32l4xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32l4xx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32l4xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32l4xx_ll_spi.h
  • LL_SPI_SetDMAParity_RX() : stm32l4xx_ll_spi.h
  • LL_SPI_SetDMAParity_TX() : stm32l4xx_ll_spi.h
  • LL_SPI_SetMode() : stm32l4xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32l4xx_ll_spi.h
  • LL_SPI_SetRxFIFOThreshold() : stm32l4xx_ll_spi.h
  • LL_SPI_SetStandard() : stm32l4xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32l4xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32l4xx_ll_spi.h
  • LL_SPI_StructInit() : stm32l4xx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32l4xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32l4xx_ll_spi.h
  • LL_SWPMI_Activate() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXBER() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXBF() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_RXOVR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_SR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TC() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TXBE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ClearFlag_TXUNR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_Deactivate() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DeInit() : stm32l4xx_ll_swpmi.c
  • LL_SWPMI_DisableDMAReq_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableDMAReq_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXBER() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXBF() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_RXOVR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_SR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TC() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TXBE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableIT_TXUNR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableLoopback() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DisableTXBypass() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DMA_GetRegAddr() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableDMAReq_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableDMAReq_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXBER() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXBF() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_RXOVR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_SR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TC() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TXBE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableIT_TXUNR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableLoopback() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_EnableTXBypass() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_GetBitRatePrescaler() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_GetReceiveFrameLength() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_GetReceptionMode() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_GetTransmissionMode() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_GetVoltageClass() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_Init() : stm32l4xx_ll_swpmi.c
  • LL_SWPMI_IsActivated() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_DEACT() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXBER() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXBF() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXNE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_RXOVR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_SR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_SUSP() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TC() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXBE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsActiveFlag_TXUNR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledDMAReq_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledDMAReq_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXBER() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXBF() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_RXOVR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_SR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TC() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TX() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TXBE() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IsEnabledIT_TXUNR() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ReceiveData32() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_RequestDeactivation() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SetBitRatePrescaler() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SetReceptionMode() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SetTransmissionMode() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SetVoltageClass() : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_StructInit() : stm32l4xx_ll_swpmi.c
  • LL_SWPMI_TransmitData32() : stm32l4xx_ll_swpmi.h
  • LL_SYSCFG_ClearFlag_SP() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableAnalogBooster() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_DZC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IDC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IOC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IXC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_OFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_UFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableAnalogBooster() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableFirewall() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_DZC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IDC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IOC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IXC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_OFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_UFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableSRAM2Erase() : stm32l4xx_ll_system.h
  • LL_SYSCFG_EnableSRAM2PageWRP() : stm32l4xx_ll_system.h
  • LL_SYSCFG_GetEXTISource() : stm32l4xx_ll_system.h
  • LL_SYSCFG_GetFlashBankMode() : stm32l4xx_ll_system.h
  • LL_SYSCFG_GetRemapMemory() : stm32l4xx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SP() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledFirewall() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_DZC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IDC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IOC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IXC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_OFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_UFC() : stm32l4xx_ll_system.h
  • LL_SYSCFG_IsSRAM2EraseOngoing() : stm32l4xx_ll_system.h
  • LL_SYSCFG_LockSRAM2WRP() : stm32l4xx_ll_system.h
  • LL_SYSCFG_SetEXTISource() : stm32l4xx_ll_system.h
  • LL_SYSCFG_SetFlashBankMode() : stm32l4xx_ll_system.h
  • LL_SYSCFG_SetRemapMemory() : stm32l4xx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32l4xx_ll_system.h
  • LL_SYSCFG_UnlockSRAM2WRP() : stm32l4xx_ll_system.h
  • LL_SYSTICK_DisableIT() : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32l4xx_ll_cortex.h
  • LL_TIM_CC_DisableChannel() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32l4xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC5() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_CC6() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_SYSBRK() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32l4xx_ll_tim.h
  • LL_TIM_ConfigBRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32l4xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32l4xx_ll_tim.h
  • LL_TIM_DeInit() : stm32l4xx_ll_tim.c
  • LL_TIM_DisableAllOutputs() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableBreakInputSource() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableBRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableUIFRemap() : stm32l4xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableBreakInputSource() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableBRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableUIFRemap() : stm32l4xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32l4xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32l4xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32l4xx_ll_tim.c
  • LL_TIM_GenerateEvent_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32l4xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32l4xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32l4xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32l4xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32l4xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32l4xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32l4xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32l4xx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32l4xx_ll_tim.c
  • LL_TIM_IC_Config() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32l4xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32l4xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32l4xx_ll_tim.c
  • LL_TIM_Init() : stm32l4xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_BRK2() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC5() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC6() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_SYSBRK() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32l4xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH5() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH6() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32l4xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH5() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH6() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32l4xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32l4xx_ll_tim.c
  • LL_TIM_SetAutoReload() : stm32l4xx_ll_tim.h
  • LL_TIM_SetBreakInputSourcePolarity() : stm32l4xx_ll_tim.h
  • LL_TIM_SetCH5CombinedChannels() : stm32l4xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32l4xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32l4xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32l4xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32l4xx_ll_tim.h
  • LL_TIM_SetETRSource() : stm32l4xx_ll_tim.h
  • LL_TIM_SetOCRefClearInputSource() : stm32l4xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32l4xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32l4xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32l4xx_ll_tim.h
  • LL_TIM_SetRemap() : stm32l4xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32l4xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32l4xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32l4xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32l4xx_ll_tim.h
  • LL_TIM_SetTriggerOutput2() : stm32l4xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32l4xx_ll_tim.h
  • LL_TIM_StructInit() : stm32l4xx_ll_tim.c
  • LL_USART_ClearFlag_CM() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32l4xx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32l4xx_ll_usart.h
  • LL_USART_ClockInit() : stm32l4xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32l4xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32l4xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32l4xx_ll_usart.h
  • LL_USART_DeInit() : stm32l4xx_ll_usart.c
  • LL_USART_Disable() : stm32l4xx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32l4xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32l4xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32l4xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32l4xx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_RXNE() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_TXE() : stm32l4xx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32l4xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32l4xx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32l4xx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32l4xx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32l4xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32l4xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32l4xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32l4xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32l4xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32l4xx_ll_usart.h
  • LL_USART_Enable() : stm32l4xx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32l4xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32l4xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32l4xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32l4xx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_RXNE() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_TXE() : stm32l4xx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32l4xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32l4xx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32l4xx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32l4xx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32l4xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32l4xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32l4xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32l4xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32l4xx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32l4xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32l4xx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32l4xx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32l4xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32l4xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32l4xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32l4xx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32l4xx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32l4xx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32l4xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32l4xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32l4xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32l4xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32l4xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32l4xx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32l4xx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32l4xx_ll_usart.h
  • LL_USART_GetParity() : stm32l4xx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32l4xx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32l4xx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32l4xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32l4xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32l4xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32l4xx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32l4xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32l4xx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32l4xx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32l4xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32l4xx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32l4xx_ll_usart.h
  • LL_USART_Init() : stm32l4xx_ll_usart.c
  • LL_USART_IsActiveFlag_ABR() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE() : stm32l4xx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32l4xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32l4xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32l4xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32l4xx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32l4xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32l4xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32l4xx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32l4xx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32l4xx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32l4xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32l4xx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32l4xx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32l4xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32l4xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32l4xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32l4xx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32l4xx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32l4xx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32l4xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32l4xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32l4xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32l4xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32l4xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32l4xx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32l4xx_ll_usart.h
  • LL_USART_SetParity() : stm32l4xx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32l4xx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32l4xx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32l4xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32l4xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32l4xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32l4xx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32l4xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32l4xx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32l4xx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32l4xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32l4xx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32l4xx_ll_usart.h
  • LL_USART_StructInit() : stm32l4xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32l4xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32l4xx_ll_usart.h
  • LL_VREFBUF_Disable() : stm32l4xx_ll_system.h
  • LL_VREFBUF_DisableHIZ() : stm32l4xx_ll_system.h
  • LL_VREFBUF_Enable() : stm32l4xx_ll_system.h
  • LL_VREFBUF_EnableHIZ() : stm32l4xx_ll_system.h
  • LL_VREFBUF_GetTrimming() : stm32l4xx_ll_system.h
  • LL_VREFBUF_GetVoltageScaling() : stm32l4xx_ll_system.h
  • LL_VREFBUF_IsVREFReady() : stm32l4xx_ll_system.h
  • LL_VREFBUF_SetTrimming() : stm32l4xx_ll_system.h
  • LL_VREFBUF_SetVoltageScaling() : stm32l4xx_ll_system.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32l4xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32l4xx_ll_wwdg.h
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STM32L486xx HAL User Manual: Globals

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- n -

  • NAND_AddressIncrement() : stm32l4xx_hal_nand.c
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STM32L486xx HAL User Manual: Globals

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- o -

  • OC1Config() : stm32l4xx_ll_tim.c
  • OC2Config() : stm32l4xx_ll_tim.c
  • OC3Config() : stm32l4xx_ll_tim.c
  • OC4Config() : stm32l4xx_ll_tim.c
  • OC5Config() : stm32l4xx_ll_tim.c
  • OC6Config() : stm32l4xx_ll_tim.c
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STM32L486xx HAL User Manual: Globals

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- p -

  • PCD_WriteEmptyTxFifo() : stm32l4xx_hal_pcd.c
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STM32L486xx HAL User Manual: Globals

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- q -

  • QSPI_Config() : stm32l4xx_hal_qspi.c
  • QSPI_DMAAbortCplt() : stm32l4xx_hal_qspi.c
  • QSPI_DMAError() : stm32l4xx_hal_qspi.c
  • QSPI_DMARxCplt() : stm32l4xx_hal_qspi.c
  • QSPI_DMARxHalfCplt() : stm32l4xx_hal_qspi.c
  • QSPI_DMATxCplt() : stm32l4xx_hal_qspi.c
  • QSPI_DMATxHalfCplt() : stm32l4xx_hal_qspi.c
  • QSPI_WaitFlagStateUntilTimeout() : stm32l4xx_hal_qspi.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- r -

  • RCC_GetHCLKClockFreq() : stm32l4xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32l4xx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32l4xx_ll_rcc.c
  • RCC_GetSystemClockFreq() : stm32l4xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_48M() : stm32l4xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SAI() : stm32l4xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SYS() : stm32l4xx_ll_rcc.c
  • RCC_PLLSAI1_GetFreqDomain_48M() : stm32l4xx_ll_rcc.c
  • RCC_PLLSAI1_GetFreqDomain_ADC() : stm32l4xx_ll_rcc.c
  • RCC_PLLSAI1_GetFreqDomain_SAI() : stm32l4xx_ll_rcc.c
  • RCC_PLLSAI2_GetFreqDomain_ADC() : stm32l4xx_ll_rcc.c
  • RCC_PLLSAI2_GetFreqDomain_SAI() : stm32l4xx_ll_rcc.c
  • RCC_SetFlashLatencyFromMSIRange() : stm32l4xx_hal_rcc.c
  • RCCEx_PLLSAI1_Config() : stm32l4xx_hal_rcc_ex.c
  • RCCEx_PLLSAI2_Config() : stm32l4xx_hal_rcc_ex.c
  • RTC_Bcd2ToByte() : stm32l4xx_hal_rtc.c
  • RTC_ByteToBcd2() : stm32l4xx_hal_rtc.c
  • RTC_EnterInitMode() : stm32l4xx_hal_rtc.c
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STM32L486xx HAL User Manual: Globals

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- s -

  • SAI_Disable() : stm32l4xx_hal_sai.c
  • SAI_DMAAbort() : stm32l4xx_hal_sai.c
  • SAI_DMAError() : stm32l4xx_hal_sai.c
  • SAI_DMARxCplt() : stm32l4xx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32l4xx_hal_sai.c
  • SAI_DMATxCplt() : stm32l4xx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32l4xx_hal_sai.c
  • SAI_FillFifo() : stm32l4xx_hal_sai.c
  • SAI_InitI2S() : stm32l4xx_hal_sai.c
  • SAI_InitPCM() : stm32l4xx_hal_sai.c
  • SAI_InterruptFlag() : stm32l4xx_hal_sai.c
  • SAI_Receive_IT16Bit() : stm32l4xx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32l4xx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32l4xx_hal_sai.c
  • SAI_Transmit_IT16Bit() : stm32l4xx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32l4xx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32l4xx_hal_sai.c
  • SD_CmdError() : stm32l4xx_hal_sd.c
  • SD_CmdResp1Error() : stm32l4xx_hal_sd.c
  • SD_CmdResp2Error() : stm32l4xx_hal_sd.c
  • SD_CmdResp3Error() : stm32l4xx_hal_sd.c
  • SD_CmdResp6Error() : stm32l4xx_hal_sd.c
  • SD_CmdResp7Error() : stm32l4xx_hal_sd.c
  • SD_DMA_RxCplt() : stm32l4xx_hal_sd.c
  • SD_DMA_RxError() : stm32l4xx_hal_sd.c
  • SD_DMA_TxCplt() : stm32l4xx_hal_sd.c
  • SD_DMA_TxError() : stm32l4xx_hal_sd.c
  • SD_FindSCR() : stm32l4xx_hal_sd.c
  • SD_GetState() : stm32l4xx_hal_sd.c
  • SD_Initialize_Cards() : stm32l4xx_hal_sd.c
  • SD_IsCardProgramming() : stm32l4xx_hal_sd.c
  • SD_PowerOFF() : stm32l4xx_hal_sd.c
  • SD_PowerON() : stm32l4xx_hal_sd.c
  • SD_Select_Deselect() : stm32l4xx_hal_sd.c
  • SD_SendStatus() : stm32l4xx_hal_sd.c
  • SD_WideBus_Disable() : stm32l4xx_hal_sd.c
  • SD_WideBus_Enable() : stm32l4xx_hal_sd.c
  • SMARTCARD_AdvFeatureConfig() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_Receive_IT() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_Transmit_IT() : stm32l4xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32l4xx_hal_smartcard.c
  • SMBUS_Disable_IRQ() : stm32l4xx_hal_smbus.c
  • SMBUS_Enable_IRQ() : stm32l4xx_hal_smbus.c
  • SMBUS_Master_ISR() : stm32l4xx_hal_smbus.c
  • SMBUS_Slave_ISR() : stm32l4xx_hal_smbus.c
  • SMBUS_TransferConfig() : stm32l4xx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32l4xx_hal_smbus.c
  • SPI_2linesRxISR_16BIT() : stm32l4xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32l4xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32l4xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32l4xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32l4xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32l4xx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32l4xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32l4xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32l4xx_hal_spi.c
  • SPI_DMAError() : stm32l4xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32l4xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32l4xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32l4xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32l4xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32l4xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32l4xx_hal_spi.c
  • SPI_EndRxTransaction() : stm32l4xx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32l4xx_hal_spi.c
  • SPI_RxISR_16BIT() : stm32l4xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32l4xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32l4xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32l4xx_hal_spi.c
  • SPI_TxISR_16BIT() : stm32l4xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32l4xx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32l4xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32l4xx_hal_spi.c
  • SWPMI_DMAError() : stm32l4xx_hal_swpmi.c
  • SWPMI_DMAReceiveCplt() : stm32l4xx_hal_swpmi.c
  • SWPMI_DMARxHalfCplt() : stm32l4xx_hal_swpmi.c
  • SWPMI_DMATransmitCplt() : stm32l4xx_hal_swpmi.c
  • SWPMI_DMATxHalfCplt() : stm32l4xx_hal_swpmi.c
  • SWPMI_EndReceive_IT() : stm32l4xx_hal_swpmi.c
  • SWPMI_EndTransmit_IT() : stm32l4xx_hal_swpmi.c
  • SWPMI_EndTransmitReceive_IT() : stm32l4xx_hal_swpmi.c
  • SWPMI_Receive_IT() : stm32l4xx_hal_swpmi.c
  • SWPMI_Transmit_IT() : stm32l4xx_hal_swpmi.c
  • SWPMI_WaitOnFlagSetUntilTimeout() : stm32l4xx_hal_swpmi.c
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STM32L486xx HAL User Manual: Globals

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- t -

  • TIM_Base_SetConfig() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32l4xx_hal_tim.h , stm32l4xx_hal_tim.c
  • TIM_CCxNChannelCmd() : stm32l4xx_hal_tim_ex.c
  • TIM_DMACaptureCplt() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_DMADelayPulseCplt() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_DMAError() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_DMAPeriodElapsedCplt() : stm32l4xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32l4xx_hal_tim.c
  • TIM_ETR_SetConfig() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_OC1_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_OC3_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_OC5_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_SlaveTimer_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32l4xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32l4xx_hal_tim.c , stm32l4xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32l4xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32l4xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32l4xx_hal_tim.c
  • TIMEx_DMACommutationCplt() : stm32l4xx_hal_tim_ex.h , stm32l4xx_hal_tim_ex.c
  • TSC_extract_groups() : stm32l4xx_hal_tsc.c
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STM32L486xx HAL User Manual: Globals

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- u -

  • UART_AdvFeatureConfig() : stm32l4xx_hal_uart.c
  • UART_CheckIdleState() : stm32l4xx_hal_uart.c
  • UART_DMAAbortOnError() : stm32l4xx_hal_uart.c
  • UART_DMAError() : stm32l4xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32l4xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32l4xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32l4xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32l4xx_hal_uart.c
  • UART_EndRxTransfer() : stm32l4xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32l4xx_hal_uart.c
  • UART_EndTxTransfer() : stm32l4xx_hal_uart.c
  • UART_Receive_IT() : stm32l4xx_hal_uart.c
  • UART_SetConfig() : stm32l4xx_hal_uart.c
  • UART_Transmit_IT() : stm32l4xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32l4xx_hal_uart.c
  • UARTEx_Wakeup_AddressConfig() : stm32l4xx_hal_uart_ex.c
  • USART_CheckIdleState() : stm32l4xx_hal_usart.c
  • USART_DMAAbortOnError() : stm32l4xx_hal_usart.c
  • USART_DMAError() : stm32l4xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32l4xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32l4xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32l4xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32l4xx_hal_usart.c
  • USART_EndTransfer() : stm32l4xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32l4xx_hal_usart.c
  • USART_Receive_IT() : stm32l4xx_hal_usart.c
  • USART_SetConfig() : stm32l4xx_hal_usart.c
  • USART_Transmit_IT() : stm32l4xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32l4xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32l4xx_hal_usart.c
  • UTILS_EnablePLLAndSwitchSystem() : stm32l4xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32l4xx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32l4xx_ll_utils.c
  • UTILS_SetFlashLatency() : stm32l4xx_ll_utils.c
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STM32L486xx HAL User Manual: Globals

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  • a_dfsdm1ChannelHandle : stm32l4xx_hal_dfsdm.c
  • aRCC_APBAHBPrescTable : stm32l4xx_ll_rcc.h
  • CHANNEL_OFFSET_TAB : stm32l4xx_ll_dma.h
  • OFFSET_TAB_CCMRx : stm32l4xx_ll_tim.h
  • pFlash : stm32l4xx_hal_flash.c , stm32l4xx_hal_flash_ex.c
  • SHIFT_TAB_CCxP : stm32l4xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32l4xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32l4xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32l4xx_ll_tim.h
  • uwNORMemoryDataWidth : stm32l4xx_hal_nor.c
  • uwTick : stm32l4xx_hal.c
  • v_dfsdm1ChannelCounter : stm32l4xx_hal_dfsdm.c
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STM32L486xx HAL User Manual: Globals

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  • DMA_HandleTypeDef : stm32l4xx_hal_dma.h
  • HAL_LPTIM_StateTypeDef : stm32l4xx_hal_lptim.h
  • HAL_OPAMP_TrimmingValueTypeDef : stm32l4xx_hal_opamp.h
  • HCD_HCStateTypeDef : stm32l4xx_hal_hcd.h
  • HCD_HCTypeDef : stm32l4xx_hal_hcd.h
  • HCD_InitTypeDef : stm32l4xx_hal_hcd.h
  • HCD_TypeDef : stm32l4xx_hal_hcd.h
  • HCD_URBStateTypeDef : stm32l4xx_hal_hcd.h
  • I2C_HandleTypeDef : stm32l4xx_hal_i2c.h
  • PCD_EPTypeDef : stm32l4xx_hal_pcd.h
  • PCD_InitTypeDef : stm32l4xx_hal_pcd.h
  • PCD_TypeDef : stm32l4xx_hal_pcd.h
  • SAI_HandleTypeDef : stm32l4xx_hal_sai.h
  • SAIcallback : stm32l4xx_hal_sai.h
  • SPI_HandleTypeDef : stm32l4xx_hal_spi.h
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STM32L486xx HAL User Manual: Globals

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- _ -

  • __HAL_LPTIM_StateTypeDef : stm32l4xx_hal_lptim.h

- f -

  • FLASH_ProcedureTypeDef : stm32l4xx_hal_flash.h

- g -

  • GPIO_PinState : stm32l4xx_hal_gpio.h

- h -

  • HAL_CAN_StateTypeDef : stm32l4xx_hal_can.h
  • HAL_COMP_StateTypeDef : stm32l4xx_hal_comp.h
  • HAL_CRC_StateTypeDef : stm32l4xx_hal_crc.h
  • HAL_CRYP_STATETypeDef : stm32l4xx_hal_cryp.h
  • HAL_DAC_StateTypeDef : stm32l4xx_hal_dac.h
  • HAL_DFSDM_Channel_StateTypeDef : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_Filter_StateTypeDef : stm32l4xx_hal_dfsdm.h
  • HAL_DMA_CallbackIDTypeDef : stm32l4xx_hal_dma.h
  • HAL_DMA_LevelCompleteTypeDef : stm32l4xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32l4xx_hal_dma.h
  • HAL_I2C_ModeTypeDef : stm32l4xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32l4xx_hal_i2c.h
  • HAL_IRDA_ErrorTypeDef : stm32l4xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32l4xx_hal_irda.h
  • HAL_LCD_StateTypeDef : stm32l4xx_hal_lcd.h
  • HAL_NAND_StateTypeDef : stm32l4xx_hal_nand.h
  • HAL_NOR_StateTypeDef : stm32l4xx_hal_nor.h
  • HAL_NOR_StatusTypeDef : stm32l4xx_hal_nor.h
  • HAL_OPAMP_StateTypeDef : stm32l4xx_hal_opamp.h
  • HAL_PhaseTypeDef : stm32l4xx_hal_cryp.h
  • HAL_QSPI_StateTypeDef : stm32l4xx_hal_qspi.h
  • HAL_RNG_StateTypeDef : stm32l4xx_hal_rng.h
  • HAL_RTCStateTypeDef : stm32l4xx_hal_rtc.h
  • HAL_SAI_StateTypeDef : stm32l4xx_hal_sai.h
  • HAL_SMARTCARD_ErrorTypeDef : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32l4xx_hal_smartcard.h
  • HAL_SPI_StateTypeDef : stm32l4xx_hal_spi.h
  • HAL_SRAM_StateTypeDef : stm32l4xx_hal_sram.h
  • HAL_SuspendTypeDef : stm32l4xx_hal_cryp.h
  • HAL_SWPMI_StateTypeDef : stm32l4xx_hal_swpmi.h
  • HAL_TIM_ActiveChannel : stm32l4xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32l4xx_hal_tim.h
  • HAL_TSC_StateTypeDef : stm32l4xx_hal_tsc.h
  • HAL_UART_ErrorTypeDef : stm32l4xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32l4xx_hal_uart.h
  • HAL_USART_ErrorTypeDef : stm32l4xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32l4xx_hal_usart.h
  • HCD_StateTypeDef : stm32l4xx_hal_hcd.h

- i -

  • IRDA_ClockSourceTypeDef : stm32l4xx_hal_irda.h
  • IRDA_ControlTypeDef : stm32l4xx_hal_irda.h

- p -

  • PCD_BCD_MsgTypeDef : stm32l4xx_hal_pcd_ex.h
  • PCD_LPM_MsgTypeDef : stm32l4xx_hal_pcd_ex.h
  • PCD_LPM_StateTypeDef : stm32l4xx_hal_pcd.h
  • PCD_StateTypeDef : stm32l4xx_hal_pcd.h

- s -

  • SAI_ModeTypedef : stm32l4xx_hal_sai.c
  • SMARTCARD_ClockSourceTypeDef : stm32l4xx_hal_smartcard.h

- t -

  • TSC_GroupStatusTypeDef : stm32l4xx_hal_tsc.h

- u -

  • UART_ClockSourceTypeDef : stm32l4xx_hal_uart.h
  • USART_ClockSourceTypeDef : stm32l4xx_hal_usart.h
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STM32L486xx HAL User Manual: Globals

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- f -

  • FLASH_PROC_MASS_ERASE : stm32l4xx_hal_flash.h
  • FLASH_PROC_NONE : stm32l4xx_hal_flash.h
  • FLASH_PROC_PAGE_ERASE : stm32l4xx_hal_flash.h
  • FLASH_PROC_PROGRAM : stm32l4xx_hal_flash.h
  • FLASH_PROC_PROGRAM_LAST : stm32l4xx_hal_flash.h
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- g -

  • GPIO_PIN_RESET : stm32l4xx_hal_gpio.h
  • GPIO_PIN_SET : stm32l4xx_hal_gpio.h
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STM32L486xx HAL User Manual: Globals

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- h -

  • HAL_CAN_STATE_BUSY : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_ERROR : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_READY : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_RESET : stm32l4xx_hal_can.h
  • HAL_CAN_STATE_TIMEOUT : stm32l4xx_hal_can.h
  • HAL_COMP_STATE_BUSY : stm32l4xx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32l4xx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32l4xx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32l4xx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32l4xx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32l4xx_hal_comp.h
  • HAL_CRC_STATE_BUSY : stm32l4xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32l4xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32l4xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32l4xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32l4xx_hal_crc.h
  • HAL_CRYP_PHASE_FINAL_OVER : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_HEADER_OVER : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_HEADER_SUSPENDED : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_INIT_OVER : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_NOT_USED : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_PAYLOAD_OVER : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_PAYLOAD_SUSPENDED : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_PROCESS : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_READY : stm32l4xx_hal_cryp.h
  • HAL_CRYP_PHASE_START : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_BUSY : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_ERROR : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_READY : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_RESET : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_SUSPENDED : stm32l4xx_hal_cryp.h
  • HAL_CRYP_STATE_TIMEOUT : stm32l4xx_hal_cryp.h
  • HAL_CRYP_SUSPEND : stm32l4xx_hal_cryp.h
  • HAL_CRYP_SUSPEND_NONE : stm32l4xx_hal_cryp.h
  • HAL_DAC_STATE_BUSY : stm32l4xx_hal_dac.h
  • HAL_DAC_STATE_ERROR : stm32l4xx_hal_dac.h
  • HAL_DAC_STATE_READY : stm32l4xx_hal_dac.h
  • HAL_DAC_STATE_RESET : stm32l4xx_hal_dac.h
  • HAL_DAC_STATE_TIMEOUT : stm32l4xx_hal_dac.h
  • HAL_DFSDM_CHANNEL_STATE_ERROR : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_READY : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_CHANNEL_STATE_RESET : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_ERROR : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_INJ : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_READY : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_REG_INJ : stm32l4xx_hal_dfsdm.h
  • HAL_DFSDM_FILTER_STATE_RESET : stm32l4xx_hal_dfsdm.h
  • HAL_DMA_FULL_TRANSFER : stm32l4xx_hal_dma.h
  • HAL_DMA_HALF_TRANSFER : stm32l4xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32l4xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32l4xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32l4xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32l4xx_hal_dma.h
  • HAL_DMA_XFER_ABORT_CB_ID : stm32l4xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32l4xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32l4xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32l4xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32l4xx_hal_dma.h
  • HAL_HCD_STATE_BUSY : stm32l4xx_hal_hcd.h
  • HAL_HCD_STATE_ERROR : stm32l4xx_hal_hcd.h
  • HAL_HCD_STATE_READY : stm32l4xx_hal_hcd.h
  • HAL_HCD_STATE_RESET : stm32l4xx_hal_hcd.h
  • HAL_HCD_STATE_TIMEOUT : stm32l4xx_hal_hcd.h
  • HAL_I2C_MODE_MASTER : stm32l4xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32l4xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32l4xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_ABORT : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32l4xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32l4xx_hal_i2c.h
  • HAL_IRDA_ERROR_DMA : stm32l4xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32l4xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32l4xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32l4xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32l4xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32l4xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32l4xx_hal_irda.h
  • HAL_LCD_STATE_BUSY : stm32l4xx_hal_lcd.h
  • HAL_LCD_STATE_ERROR : stm32l4xx_hal_lcd.h
  • HAL_LCD_STATE_READY : stm32l4xx_hal_lcd.h
  • HAL_LCD_STATE_RESET : stm32l4xx_hal_lcd.h
  • HAL_LCD_STATE_TIMEOUT : stm32l4xx_hal_lcd.h
  • HAL_LPTIM_STATE_BUSY : stm32l4xx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32l4xx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32l4xx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32l4xx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32l4xx_hal_lptim.h
  • HAL_NAND_STATE_BUSY : stm32l4xx_hal_nand.h
  • HAL_NAND_STATE_ERROR : stm32l4xx_hal_nand.h
  • HAL_NAND_STATE_READY : stm32l4xx_hal_nand.h
  • HAL_NAND_STATE_RESET : stm32l4xx_hal_nand.h
  • HAL_NOR_STATE_BUSY : stm32l4xx_hal_nor.h
  • HAL_NOR_STATE_ERROR : stm32l4xx_hal_nor.h
  • HAL_NOR_STATE_PROTECTED : stm32l4xx_hal_nor.h
  • HAL_NOR_STATE_READY : stm32l4xx_hal_nor.h
  • HAL_NOR_STATE_RESET : stm32l4xx_hal_nor.h
  • HAL_NOR_STATUS_ERROR : stm32l4xx_hal_nor.h
  • HAL_NOR_STATUS_ONGOING : stm32l4xx_hal_nor.h
  • HAL_NOR_STATUS_SUCCESS : stm32l4xx_hal_nor.h
  • HAL_NOR_STATUS_TIMEOUT : stm32l4xx_hal_nor.h
  • HAL_OPAMP_STATE_BUSY : stm32l4xx_hal_opamp.h
  • HAL_OPAMP_STATE_BUSYLOCKED : stm32l4xx_hal_opamp.h
  • HAL_OPAMP_STATE_CALIBBUSY : stm32l4xx_hal_opamp.h
  • HAL_OPAMP_STATE_READY : stm32l4xx_hal_opamp.h
  • HAL_OPAMP_STATE_RESET : stm32l4xx_hal_opamp.h
  • HAL_PCD_STATE_BUSY : stm32l4xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32l4xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32l4xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32l4xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32l4xx_hal_pcd.h
  • HAL_QSPI_STATE_ABORT : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_AUTO_POLLING : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_RX : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_TX : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_MEM_MAPPED : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_ERROR : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_READY : stm32l4xx_hal_qspi.h
  • HAL_QSPI_STATE_RESET : stm32l4xx_hal_qspi.h
  • HAL_RNG_STATE_BUSY : stm32l4xx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32l4xx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32l4xx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32l4xx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32l4xx_hal_rng.h
  • HAL_RTC_STATE_BUSY : stm32l4xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32l4xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32l4xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32l4xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32l4xx_hal_rtc.h
  • HAL_SAI_STATE_BUSY : stm32l4xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32l4xx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32l4xx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32l4xx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32l4xx_hal_sai.h
  • HAL_SMARTCARD_ERROR_DMA : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32l4xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32l4xx_hal_smartcard.h
  • HAL_SPI_STATE_BUSY : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32l4xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32l4xx_hal_spi.h
  • HAL_SRAM_STATE_BUSY : stm32l4xx_hal_sram.h
  • HAL_SRAM_STATE_ERROR : stm32l4xx_hal_sram.h
  • HAL_SRAM_STATE_PROTECTED : stm32l4xx_hal_sram.h
  • HAL_SRAM_STATE_READY : stm32l4xx_hal_sram.h
  • HAL_SRAM_STATE_RESET : stm32l4xx_hal_sram.h
  • HAL_SWPMI_STATE_BUSY : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_RX : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_BUSY_TX_RX : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_ERROR : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_READY : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_RESET : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_STATE_TIMEOUT : stm32l4xx_hal_swpmi.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32l4xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32l4xx_hal_tim.h
  • HAL_TIM_STATE_BUSY : stm32l4xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32l4xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32l4xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32l4xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32l4xx_hal_tim.h
  • HAL_TSC_STATE_BUSY : stm32l4xx_hal_tsc.h
  • HAL_TSC_STATE_ERROR : stm32l4xx_hal_tsc.h
  • HAL_TSC_STATE_READY : stm32l4xx_hal_tsc.h
  • HAL_TSC_STATE_RESET : stm32l4xx_hal_tsc.h
  • HAL_UART_ERROR_DMA : stm32l4xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32l4xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32l4xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32l4xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32l4xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_BUSY : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32l4xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32l4xx_hal_uart.h
  • HAL_USART_ERROR_DMA : stm32l4xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32l4xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32l4xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32l4xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32l4xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_BUSY : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32l4xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32l4xx_hal_usart.h
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STM32L486xx HAL User Manual: Globals

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- i -

  • IRDA_BAUDRATE : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK1 : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK2 : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32l4xx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32l4xx_hal_irda.h
  • IRDA_MODE : stm32l4xx_hal_irda.h
  • IRDA_PARITY : stm32l4xx_hal_irda.h
  • IRDA_POWERMODE : stm32l4xx_hal_irda.h
  • IRDA_PRESCALER : stm32l4xx_hal_irda.h
  • IRDA_WORDLENGTH : stm32l4xx_hal_irda.h
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STM32L486xx HAL User Manual: Globals

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- l -

  • LPM_L0 : stm32l4xx_hal_pcd.h
  • LPM_L1 : stm32l4xx_hal_pcd.h
  • LPM_L2 : stm32l4xx_hal_pcd.h
  • LPM_L3 : stm32l4xx_hal_pcd.h
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STM32L486xx HAL User Manual: Globals

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- p -

  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_CONTACT_DETECTION : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_ERROR : stm32l4xx_hal_pcd_ex.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32l4xx_hal_pcd_ex.h
  • PCD_LPM_L0_ACTIVE : stm32l4xx_hal_pcd_ex.h
  • PCD_LPM_L1_ACTIVE : stm32l4xx_hal_pcd_ex.h
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STM32L486xx HAL User Manual: Globals

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- s -

  • SAI_MODE_DMA : stm32l4xx_hal_sai.c
  • SAI_MODE_IT : stm32l4xx_hal_sai.c
  • SMARTCARD_CLOCKSOURCE_HSI : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK1 : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK2 : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32l4xx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32l4xx_hal_smartcard.h
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STM32L486xx HAL User Manual: Globals

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- t -

  • TSC_GROUP_COMPLETED : stm32l4xx_hal_tsc.h
  • TSC_GROUP_ONGOING : stm32l4xx_hal_tsc.h
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STM32L486xx HAL User Manual: Globals

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- u -

  • UART_CLOCKSOURCE_HSI : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK2 : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32l4xx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32l4xx_hal_uart.h
  • USART_CLOCKSOURCE_HSI : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK1 : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK2 : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32l4xx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32l4xx_hal_usart.h
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STM32L486xx HAL User Manual: Globals

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- _ -

  • __ADC_MASK_SHIFT : stm32l4xx_ll_adc.h
  • __ADC_PTR_REG_OFFSET : stm32l4xx_ll_adc.h
  • __DAC_MASK_SHIFT : stm32l4xx_ll_dac.h
  • __DAC_PTR_REG_OFFSET : stm32l4xx_ll_dac.h
  • __HAL_ADC_CLEAR_FLAG : stm32l4xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32l4xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32l4xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32l4xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32l4xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32l4xx_hal_adc.h
  • __HAL_CAN_CANCEL_TRANSMIT : stm32l4xx_hal_can.h
  • __HAL_CAN_CLEAR_FLAG : stm32l4xx_hal_can.h
  • __HAL_CAN_DBG_FREEZE : stm32l4xx_hal_can.h
  • __HAL_CAN_DISABLE_IT : stm32l4xx_hal_can.h
  • __HAL_CAN_ENABLE_IT : stm32l4xx_hal_can.h
  • __HAL_CAN_FIFO_RELEASE : stm32l4xx_hal_can.h
  • __HAL_CAN_GET_FLAG : stm32l4xx_hal_can.h
  • __HAL_CAN_GET_IT_SOURCE : stm32l4xx_hal_can.h
  • __HAL_CAN_MSG_PENDING : stm32l4xx_hal_can.h
  • __HAL_CAN_RESET_HANDLE_STATE : stm32l4xx_hal_can.h
  • __HAL_CAN_TRANSMIT_STATUS : stm32l4xx_hal_can.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32l4xx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32l4xx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32l4xx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32l4xx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32l4xx_hal_comp.h
  • __HAL_COMP_LOCK : stm32l4xx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32l4xx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32l4xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32l4xx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32l4xx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32l4xx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32l4xx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32l4xx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32l4xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32l4xx_hal_crc.h
  • __HAL_CRYP_CLEAR_FLAG : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_CLEAR_IT : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_DISABLE : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_DISABLE_IT : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_ENABLE : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_ENABLE_IT : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_GET_FLAG : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_GET_IT : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_GET_IT_SOURCE : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_RESET_HANDLE_STATE : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_SET_CHAININGMODE : stm32l4xx_hal_cryp.h
  • __HAL_CRYP_SET_OPERATINGMODE : stm32l4xx_hal_cryp.h
  • __HAL_DAC_CLEAR_FLAG : stm32l4xx_hal_dac.h
  • __HAL_DAC_DISABLE : stm32l4xx_hal_dac.h
  • __HAL_DAC_DISABLE_IT : stm32l4xx_hal_dac.h
  • __HAL_DAC_ENABLE : stm32l4xx_hal_dac.h
  • __HAL_DAC_ENABLE_IT : stm32l4xx_hal_dac.h
  • __HAL_DAC_GET_FLAG : stm32l4xx_hal_dac.h
  • __HAL_DAC_GET_IT_SOURCE : stm32l4xx_hal_dac.h
  • __HAL_DAC_RESET_HANDLE_STATE : stm32l4xx_hal_dac.h
  • __HAL_DBGMCU_FREEZE_CAN1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM2 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM15 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM5 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM6 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM7 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM8 : stm32l4xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM2 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM15 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM16 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM17 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM5 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM6 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM7 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM8 : stm32l4xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32l4xx_hal.h
  • __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE : stm32l4xx_hal_dfsdm.h
  • __HAL_DFSDM_FILTER_RESET_HANDLE_STATE : stm32l4xx_hal_dfsdm.h
  • __HAL_DMA_CLEAR_FLAG : stm32l4xx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32l4xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32l4xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32l4xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32l4xx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32l4xx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32l4xx_hal_dma.h
  • __HAL_FIREWALL_GET_PREARM : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_GET_VOLATILEDATA_SHARED : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_IS_ENABLED : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_PREARM_DISABLE : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_PREARM_ENABLE : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE : stm32l4xx_hal_firewall.h
  • __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE : stm32l4xx_hal_firewall.h
  • __HAL_FLASH_CLEAR_FLAG : stm32l4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_DISABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_ENABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_RESET : stm32l4xx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32l4xx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32l4xx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32l4xx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32l4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_DISABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_ENABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_RESET : stm32l4xx_hal_flash.h
  • __HAL_FLASH_POWER_DOWN_DISABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_POWER_DOWN_ENABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32l4xx_hal_flash.h
  • __HAL_FLASH_SLEEP_POWERDOWN_DISABLE : stm32l4xx_hal_flash.h
  • __HAL_FLASH_SLEEP_POWERDOWN_ENABLE : stm32l4xx_hal_flash.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32l4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32l4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32l4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32l4xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32l4xx_hal_gpio.h
  • __HAL_HCD_CLEAR_FLAG : stm32l4xx_hal_hcd.h
  • __HAL_HCD_CLEAR_HC_INT : stm32l4xx_hal_hcd.h
  • __HAL_HCD_DISABLE : stm32l4xx_hal_hcd.h
  • __HAL_HCD_ENABLE : stm32l4xx_hal_hcd.h
  • __HAL_HCD_GET_FLAG : stm32l4xx_hal_hcd.h
  • __HAL_HCD_IS_INVALID_INTERRUPT : stm32l4xx_hal_hcd.h
  • __HAL_HCD_MASK_ACK_HC_INT : stm32l4xx_hal_hcd.h
  • __HAL_HCD_MASK_HALT_HC_INT : stm32l4xx_hal_hcd.h
  • __HAL_HCD_UNMASK_ACK_HC_INT : stm32l4xx_hal_hcd.h
  • __HAL_HCD_UNMASK_HALT_HC_INT : stm32l4xx_hal_hcd.h
  • __HAL_I2C_CLEAR_FLAG : stm32l4xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32l4xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32l4xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32l4xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32l4xx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32l4xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32l4xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32l4xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32l4xx_hal_i2c.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32l4xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32l4xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32l4xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32l4xx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32l4xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32l4xx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32l4xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32l4xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32l4xx_hal_iwdg.h
  • __HAL_LCD_BLINK_CONFIG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_CLEAR_FLAG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_CONTRAST_CONFIG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_DEADTIME_CONFIG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_DISABLE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_DISABLE_IT : stm32l4xx_hal_lcd.h
  • __HAL_LCD_ENABLE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_ENABLE_IT : stm32l4xx_hal_lcd.h
  • __HAL_LCD_GET_FLAG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_GET_IT_SOURCE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_HIGHDRIVER_DISABLE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_HIGHDRIVER_ENABLE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_PULSEONDURATION_CONFIG : stm32l4xx_hal_lcd.h
  • __HAL_LCD_RESET_HANDLE_STATE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_VOLTAGE_BUFFER_DISABLE : stm32l4xx_hal_lcd.h
  • __HAL_LCD_VOLTAGE_BUFFER_ENABLE : stm32l4xx_hal_lcd.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32l4xx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32l4xx_hal_lptim.h
  • __HAL_NAND_RESET_HANDLE_STATE : stm32l4xx_hal_nand.h
  • __HAL_NOR_RESET_HANDLE_STATE : stm32l4xx_hal_nor.h
  • __HAL_OPAMP_RESET_HANDLE_STATE : stm32l4xx_hal_opamp.h
  • __HAL_PCD_CLEAR_FLAG : stm32l4xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32l4xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32l4xx_hal_pcd.h
  • __HAL_PCD_GATE_PHYCLOCK : stm32l4xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32l4xx_hal_pcd.h
  • __HAL_PCD_IS_INVALID_INTERRUPT : stm32l4xx_hal_pcd.h
  • __HAL_PCD_IS_PHY_SUSPENDED : stm32l4xx_hal_pcd.h
  • __HAL_PCD_UNGATE_PHYCLOCK : stm32l4xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32l4xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32l4xx_hal_pwr.h
  • __HAL_PWR_PVM1_EXTI_CLEAR_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GENERATE_SWIT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GET_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_CLEAR_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_GENERATE_SWIT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM2_EXTI_GET_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_CLEAR_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GENERATE_SWIT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GET_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_CLEAR_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_EVENT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_IT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_GENERATE_SWIT : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_PVM4_EXTI_GET_FLAG : stm32l4xx_hal_pwr_ex.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32l4xx_hal_pwr_ex.h
  • __HAL_QSPI_CLEAR_FLAG : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_DISABLE : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_DISABLE_IT : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_ENABLE : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_ENABLE_IT : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_GET_FLAG : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_GET_IT_SOURCE : stm32l4xx_hal_qspi.h
  • __HAL_QSPI_RESET_HANDLE_STATE : stm32l4xx_hal_qspi.h
  • __HAL_RCC_ADC_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_ADC_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ADC_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AES_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CAN1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DAC1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_DFSDM1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DFSDM1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FIREWALL_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FIREWALL_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FLASH_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_FMC_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_DFSDM1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C2_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM2_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_MSI_RANGE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_PLLCLKOUT_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SAI2_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SDMMC1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SWPMI1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GET_UART4_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_UART5_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART2_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USART3_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOF_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOG_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSIAUTOMATIC_START_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSIAUTOMATIC_START_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LCD_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPTIM2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GET_FLAG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MSI_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MSI_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MSI_RANGE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_MSI_STANDBY_RANGE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_OPAMP_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PLLSAI1_CLEAR_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DISABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DISABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVP_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVQ_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVR_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_ENABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_ENABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_GET_FLAG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_GET_IT_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_MULN_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1CLKOUT_DISABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1CLKOUT_ENABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_CLEAR_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_DISABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_DISABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_DIVP_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_DIVR_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_ENABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_ENABLE_IT : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_GET_FLAG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_GET_IT_SOURCE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2_MULN_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2CLKOUT_DISABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI2CLKOUT_ENABLE : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_QSPI_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_SAI2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SAI2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_SDMMC1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SDMMC1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SPI3_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_SWPMI1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SWPMI1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM15_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM5_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM6_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM7_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TIM8_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_TSC_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_UART4_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART4_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_UART5_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_UART5_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32l4xx_hal_rcc_ex.h
  • __HAL_RCC_USB_OTG_FS_CLK_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_FORCE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_USB_OTG_FS_RELEASE_RESET : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WAKEUPSTOP_CLK_CONFIG : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED : stm32l4xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED : stm32l4xx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32l4xx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32l4xx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32l4xx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32l4xx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32l4xx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32l4xx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32l4xx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32l4xx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32l4xx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32l4xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32l4xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32l4xx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32l4xx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32l4xx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32l4xx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32l4xx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32l4xx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32l4xx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32l4xx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32l4xx_hal_sai.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32l4xx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32l4xx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32l4xx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32l4xx_hal_smbus.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32l4xx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32l4xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32l4xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32l4xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32l4xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32l4xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32l4xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32l4xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32l4xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32l4xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32l4xx_hal_spi.h
  • __HAL_SRAM_RESET_HANDLE_STATE : stm32l4xx_hal_sram.h
  • __HAL_SWPMI_CLEAR_FLAG : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_DISABLE_IT : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_ENABLE_IT : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_GET_FLAG : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_GET_IT_SOURCE : stm32l4xx_hal_swpmi.h
  • __HAL_SWPMI_RESET_HANDLE_STATE : stm32l4xx_hal_swpmi.h
  • __HAL_SYSCFG_BREAK_ECC_LOCK : stm32l4xx_hal.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32l4xx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32l4xx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK : stm32l4xx_hal.h
  • __HAL_SYSCFG_CLEAR_FLAG : stm32l4xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32l4xx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32l4xx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_DISABLE : stm32l4xx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_ENABLE : stm32l4xx_hal.h
  • __HAL_SYSCFG_GET_BOOT_MODE : stm32l4xx_hal.h
  • __HAL_SYSCFG_GET_FLAG : stm32l4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32l4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FMC : stm32l4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_QUADSPI : stm32l4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32l4xx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32l4xx_hal.h
  • __HAL_SYSCFG_SRAM2_ERASE : stm32l4xx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_ENABLE : stm32l4xx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_UNLOCK : stm32l4xx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32l4xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32l4xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32l4xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32l4xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32l4xx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32l4xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32l4xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32l4xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32l4xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32l4xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32l4xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32l4xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32l4xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32l4xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32l4xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32l4xx_hal_tim.h
  • __HAL_TSC_CLEAR_FLAG : stm32l4xx_hal_tsc.h
  • __HAL_TSC_CLOSE_ANALOG_SWITCH : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE_CHANNEL : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE_GROUP : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE_HYSTERESIS : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE_IT : stm32l4xx_hal_tsc.h
  • __HAL_TSC_DISABLE_SAMPLING : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE_CHANNEL : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE_GROUP : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE_HYSTERESIS : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE_IT : stm32l4xx_hal_tsc.h
  • __HAL_TSC_ENABLE_SAMPLING : stm32l4xx_hal_tsc.h
  • __HAL_TSC_GET_FLAG : stm32l4xx_hal_tsc.h
  • __HAL_TSC_GET_GROUP_STATUS : stm32l4xx_hal_tsc.h
  • __HAL_TSC_GET_IT_SOURCE : stm32l4xx_hal_tsc.h
  • __HAL_TSC_OPEN_ANALOG_SWITCH : stm32l4xx_hal_tsc.h
  • __HAL_TSC_RESET_HANDLE_STATE : stm32l4xx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_INFLOAT : stm32l4xx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_OUTPPLOW : stm32l4xx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_FALL : stm32l4xx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_RISE_HIGH : stm32l4xx_hal_tsc.h
  • __HAL_TSC_START_ACQ : stm32l4xx_hal_tsc.h
  • __HAL_TSC_STOP_ACQ : stm32l4xx_hal_tsc.h
  • __HAL_UART_CLEAR_FEFLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32l4xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32l4xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32l4xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32l4xx_hal_uart.h
  • __HAL_UART_GET_IT : stm32l4xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32l4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32l4xx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32l4xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32l4xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32l4xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32l4xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32l4xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32l4xx_hal_usart.h
  • __HAL_USART_GET_IT : stm32l4xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32l4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32l4xx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32l4xx_hal_usart.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT : stm32l4xx_hal_pcd.h
  • __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG : stm32l4xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32l4xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32l4xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32l4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32l4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32l4xx_ll_adc.h
  • __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW : stm32l4xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32l4xx_ll_adc.h
  • __LL_ADC_CALC_DATA_VOLTAGE : stm32l4xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32l4xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32l4xx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32l4xx_ll_adc.h
  • __LL_ADC_CALIB_FACTOR_SINGLE_DIFF : stm32l4xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32l4xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32l4xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32l4xx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32l4xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32l4xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32l4xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32l4xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32l4xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32l4xx_ll_adc.h
  • __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32l4xx_ll_adc.h
  • __LL_COMP_COMMON_INSTANCE : stm32l4xx_ll_comp.h
  • __LL_DAC_CALC_VOLTAGE_TO_DATA : stm32l4xx_ll_dac.h
  • __LL_DAC_CHANNEL_TO_DECIMAL_NB : stm32l4xx_ll_dac.h
  • __LL_DAC_DECIMAL_NB_TO_CHANNEL : stm32l4xx_ll_dac.h
  • __LL_DAC_DIGITAL_SCALE : stm32l4xx_ll_dac.h
  • __LL_DMA_GET_CHANNEL : stm32l4xx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32l4xx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32l4xx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32l4xx_ll_i2c.h
  • __LL_LPUART_DIV : stm32l4xx_ll_lpuart.h
  • __LL_OPAMP_COMMON_INSTANCE : stm32l4xx_ll_opamp.h
  • __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE : stm32l4xx_ll_opamp.h
  • __LL_RCC_CALC_HCLK_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_MSI_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK2_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_48M_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_SAI_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_48M_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_ADC_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_SAI_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI2_ADC_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI2_SAI_FREQ : stm32l4xx_ll_rcc.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32l4xx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32l4xx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32l4xx_ll_rtc.h
  • __LL_SWPMI_CALC_BITRATE_PRESCALER : stm32l4xx_ll_swpmi.h
  • __LL_TIM_CALC_ARR : stm32l4xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32l4xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32l4xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32l4xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32l4xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32l4xx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32l4xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32l4xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32l4xx_ll_usart.h
  • __LSCO_CLK_ENABLE : stm32l4xx_hal_rcc_ex.c
  • __MCO1_CLK_ENABLE : stm32l4xx_hal_rcc.c
  • __OPAMP_PTR_REG_OFFSET : stm32l4xx_ll_opamp.h
  • __STM32L4xx_HAL_VERSION : stm32l4xx_hal.c
  • __STM32L4xx_HAL_VERSION_MAIN : stm32l4xx_hal.c
  • __STM32L4xx_HAL_VERSION_RC : stm32l4xx_hal.c
  • __STM32L4xx_HAL_VERSION_SUB1 : stm32l4xx_hal.c
  • __STM32L4xx_HAL_VERSION_SUB2 : stm32l4xx_hal.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- a -

  • ADC_ANALOGWATCHDOG_1 : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_2 : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_3 : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_NONE : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32l4xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32l4xx_hal_adc_ex.h
  • ADC_ANY_OTHER_ENABLED : stm32l4xx_hal_adc_ex.h
  • ADC_AWD1_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32l4xx_hal_adc_ex.h
  • ADC_AWD23THRESHOLD_SHIFT_RESOLUTION : stm32l4xx_hal_adc_ex.h
  • ADC_AWD2_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_AWD3_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_AWD_CR12_REGOFFSETGAP_MASK : stm32l4xx_ll_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_VAL : stm32l4xx_ll_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32l4xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_CR23_CHANNEL_MASK : stm32l4xx_ll_adc.h
  • ADC_AWD_CR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_CR3_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32l4xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_AWD_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_AWD_TR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_TR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_TR3_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_BATTERY_VOLTAGE_INSTANCE : stm32l4xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_GET : stm32l4xx_hal_adc_ex.h
  • ADC_CALFACT_DIFF_SET : stm32l4xx_hal_adc_ex.h
  • ADC_CALIBRATION_TIMEOUT : stm32l4xx_hal_adc_ex.c
  • ADC_CCR_MULTI_DMACONTREQ : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR2_FIELDS : stm32l4xx_hal_adc.c
  • ADC_CFGR2_INJ_FIELDS : stm32l4xx_hal_adc_ex.c
  • ADC_CFGR_AUTOWAIT : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_AWD1EN_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CFGR_AWD1SGL_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CFGR_CONTINUOUS : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_DFSDM : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_DISCONTINUOUS_NUM : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_DMACONTREQ : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_FIELDS_1 : stm32l4xx_hal_adc.c
  • ADC_CFGR_FIELDS_2 : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_CONTEXT_QUEUE : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_INJECT_DISCCONTINUOUS : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_JAWD1EN_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CFGR_REG_DISCONTINUOUS : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_RES_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CFGR_SET_AWD1CH : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_SET_AWD23CR : stm32l4xx_hal_adc_ex.h
  • ADC_CFGR_WD_FIELDS : stm32l4xx_hal_adc.c
  • ADC_CHANNEL_0 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_0_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_10_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_11_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_12_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_13_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_14_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_15_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_16_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_17_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_18 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_18_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_18_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_18_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_1_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_2_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_3_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_4_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_5_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_6_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_7_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_8_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_9_BITFIELD : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_BITFIELD_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_2 : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_VBAT : stm32l4xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32l4xx_hal_adc.h
  • ADC_CLEAR_COMMON_CONTROL_REGISTER : stm32l4xx_hal_adc_ex.h
  • ADC_CLEAR_ERRORCODE : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_RATIO_VS_CPU_HIGHEST : stm32l4xx_ll_adc.c
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32l4xx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32l4xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV1 : stm32l4xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV2 : stm32l4xx_hal_adc.h
  • ADC_CLOCKPRESCALER_PCLK_DIV4 : stm32l4xx_hal_adc.h
  • ADC_COMMON_REGISTER : stm32l4xx_hal_adc_ex.h
  • ADC_CONVERSION_TIME_MAX_CPU_CYCLES : stm32l4xx_hal_adc.c
  • ADC_CR_BITS_PROPERTY_RS : stm32l4xx_ll_adc.h
  • ADC_DATAALIGN_LEFT : stm32l4xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32l4xx_hal_adc.h
  • ADC_DIFFERENTIAL_ENDED : stm32l4xx_hal_adc_ex.h
  • ADC_DIFSEL_CHANNEL : stm32l4xx_hal_adc_ex.h
  • ADC_DISABLE : stm32l4xx_hal_adc_ex.h
  • ADC_DISABLE_TIMEOUT : stm32l4xx_hal_adc.c
  • ADC_DISABLING_CONDITIONS : stm32l4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_12_10_BITS : stm32l4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_8_6_BITS : stm32l4xx_hal_adc_ex.h
  • ADC_DMAACCESSMODE_DISABLED : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_ALTERTRIG : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERL : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGINTERL_INJECSIMULT : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32l4xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32l4xx_hal_adc_ex.h
  • ADC_ENABLE : stm32l4xx_hal_adc_ex.h
  • ADC_ENABLE_TIMEOUT : stm32l4xx_hal_adc.c
  • ADC_ENABLING_CONDITIONS : stm32l4xx_hal_adc_ex.h
  • ADC_EOC_SEQ_CONV : stm32l4xx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32l4xx_hal_adc.h
  • ADC_EOC_SINGLE_SEQ_CONV : stm32l4xx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T15_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC1 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC2 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC3 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_CC4 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T3_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_CC4 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T4_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T6_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIG_T8_TRGO2 : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32l4xx_hal_adc.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T15_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC4 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO2 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC1 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC3 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_CC4 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T3_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T4_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T6_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_CC4 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T8_TRGO2 : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32l4xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_ALL : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_AWD1 : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_AWD2 : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_AWD3 : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_EOC : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_EOS : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_EOSMP : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_JEOC : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_JEOS : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_JQOVF : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_OVR : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_POSTCONV_ALL : stm32l4xx_hal_adc_ex.h
  • ADC_FLAG_RDY : stm32l4xx_hal_adc_ex.h
  • ADC_GET_RESOLUTION : stm32l4xx_hal_adc.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE : stm32l4xx_hal_adc_ex.h
  • ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE : stm32l4xx_hal_adc_ex.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_INJ_RANK_1_JSQR_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_RANK_2_JSQR_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_RANK_3_JSQR_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_RANK_4_JSQR_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32l4xx_ll_adc.h
  • ADC_INJ_TRIG_EDGE_MASK : stm32l4xx_ll_adc.h
  • ADC_INJ_TRIG_EXT_EDGE_DEFAULT : stm32l4xx_ll_adc.h
  • ADC_INJ_TRIG_EXTEN_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_INJ_TRIG_SOURCE_MASK : stm32l4xx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32l4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32l4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32l4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32l4xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32l4xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32l4xx_hal_adc_ex.h
  • ADC_INSTANCE_IS_ENABLED : stm32l4xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_INJECTED : stm32l4xx_hal_adc_ex.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR : stm32l4xx_hal_adc.h
  • ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED : stm32l4xx_hal_adc_ex.h
  • ADC_IS_DUAL_CONVERSION_ENABLE : stm32l4xx_hal_adc_ex.h
  • ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE : stm32l4xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32l4xx_hal_adc.h
  • ADC_IS_INDEPENDENT : stm32l4xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32l4xx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32l4xx_hal_adc.h
  • ADC_IT_AWD : stm32l4xx_hal_adc_ex.h
  • ADC_IT_AWD1 : stm32l4xx_hal_adc_ex.h
  • ADC_IT_AWD2 : stm32l4xx_hal_adc_ex.h
  • ADC_IT_AWD3 : stm32l4xx_hal_adc_ex.h
  • ADC_IT_EOC : stm32l4xx_hal_adc_ex.h
  • ADC_IT_EOS : stm32l4xx_hal_adc_ex.h
  • ADC_IT_EOSMP : stm32l4xx_hal_adc_ex.h
  • ADC_IT_JEOC : stm32l4xx_hal_adc_ex.h
  • ADC_IT_JEOS : stm32l4xx_hal_adc_ex.h
  • ADC_IT_JQOVF : stm32l4xx_hal_adc_ex.h
  • ADC_IT_OVR : stm32l4xx_hal_adc_ex.h
  • ADC_IT_RDY : stm32l4xx_hal_adc_ex.h
  • ADC_JDR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_JQOVF_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_JSQR_FIELDS : stm32l4xx_hal_adc_ex.c
  • ADC_JSQR_RK : stm32l4xx_hal_adc_ex.h
  • ADC_MASTER_REGISTER : stm32l4xx_hal_adc_ex.h
  • ADC_MODE_INDEPENDENT : stm32l4xx_hal_adc_ex.h
  • ADC_MULTI_SLAVE : stm32l4xx_hal_adc_ex.h
  • ADC_MULTIMODE_DMA_ENABLED : stm32l4xx_hal_adc_ex.h
  • ADC_NONMULTIMODE_OR_MULTIMODEMASTER : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_1 : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_2 : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_3 : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_4 : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_NONE : stm32l4xx_hal_adc_ex.h
  • ADC_OFFSET_SHIFT_RESOLUTION : stm32l4xx_hal_adc_ex.h
  • ADC_OFR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_OFR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_OFR3_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_OFR4_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_OFR_CHANNEL : stm32l4xx_hal_adc_ex.h
  • ADC_OFR_FIELDS : stm32l4xx_hal_adc.c
  • ADC_OFRx_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_OVERSAMPLING_RATIO_128 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_16 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_2 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_256 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_32 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_4 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_64 : stm32l4xx_hal_adc_ex.h
  • ADC_OVERSAMPLING_RATIO_8 : stm32l4xx_hal_adc_ex.h
  • ADC_OVR_DATA_OVERWRITTEN : stm32l4xx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32l4xx_hal_adc.h
  • ADC_OVR_EVENT : stm32l4xx_hal_adc_ex.h
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32l4xx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32l4xx_ll_adc.h
  • ADC_REG_TRIG_EDGE_MASK : stm32l4xx_ll_adc.h
  • ADC_REG_TRIG_EXT_EDGE_DEFAULT : stm32l4xx_ll_adc.h
  • ADC_REG_TRIG_EXTEN_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_TRIG_EXTSEL_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_REG_TRIG_SOURCE_MASK : stm32l4xx_ll_adc.h
  • ADC_REGOVERSAMPLING_CONTINUED_MODE : stm32l4xx_hal_adc_ex.h
  • ADC_REGOVERSAMPLING_RESUMED_MODE : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_GROUP : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_10 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_11 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_12 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_13 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_14 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_15 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_16 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_2 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_3 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_4 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_5 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_6 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_7 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_8 : stm32l4xx_hal_adc_ex.h
  • ADC_REGULAR_RANK_9 : stm32l4xx_hal_adc_ex.h
  • ADC_RESOLUTION_10B : stm32l4xx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32l4xx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32l4xx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32l4xx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_2 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_3 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_4 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_5 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_6 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_7 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_8 : stm32l4xx_hal_adc_ex.h
  • ADC_RIGHTBITSHIFT_NONE : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_12CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_247CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_24CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_2CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_47CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_640CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_6CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SAMPLETIME_92CYCLES_5 : stm32l4xx_hal_adc_ex.h
  • ADC_SCAN_DISABLE : stm32l4xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32l4xx_hal_adc.h
  • ADC_SINGLE_ENDED : stm32l4xx_hal_adc_ex.h
  • ADC_SINGLEDIFF_CALIB_FACTOR_MASK : stm32l4xx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_START_MASK : stm32l4xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_MASK : stm32l4xx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK : stm32l4xx_ll_adc.h
  • ADC_SMPR1 : stm32l4xx_hal_adc_ex.h
  • ADC_SMPR1_FIELDS : stm32l4xx_hal_adc_ex.h
  • ADC_SMPR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SMPR1_SETTING : stm32l4xx_hal_adc_ex.h
  • ADC_SMPR2 : stm32l4xx_hal_adc_ex.h
  • ADC_SMPR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SMPR2_SETTING : stm32l4xx_hal_adc_ex.h
  • ADC_SOFTWARE_START : stm32l4xx_hal_adc.h
  • ADC_SQR1_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SQR1_RK : stm32l4xx_hal_adc_ex.h
  • ADC_SQR2_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SQR2_RK : stm32l4xx_hal_adc_ex.h
  • ADC_SQR3_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SQR3_RK : stm32l4xx_hal_adc_ex.h
  • ADC_SQR4_REGOFFSET : stm32l4xx_ll_adc.h
  • ADC_SQR4_RK : stm32l4xx_hal_adc_ex.h
  • ADC_STAB_DELAY_US : stm32l4xx_hal_adc.c
  • ADC_STATE_CLR_SET : stm32l4xx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32l4xx_hal_adc.h
  • ADC_TEMPERATURE_SENSOR_INSTANCE : stm32l4xx_hal_adc_ex.h
  • ADC_TEMPSENSOR_DELAY_US : stm32l4xx_hal_adc.h
  • ADC_TIMEOUT_DISABLE_CPU_CYCLES : stm32l4xx_ll_adc.c
  • ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES : stm32l4xx_ll_adc.c
  • ADC_TR1_HT1_BITOFFSET_POS : stm32l4xx_ll_adc.h
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32l4xx_hal_adc_ex.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32l4xx_hal_adc_ex.h
  • ADC_TRX_HIGHTHRESHOLD : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_10CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_11CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_12CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_1CYCLE : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_2CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_3CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_4CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_5CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_6CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_7CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_8CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_TWOSAMPLINGDELAY_9CYCLES : stm32l4xx_hal_adc_ex.h
  • ADC_VREFINT_INSTANCE : stm32l4xx_hal_adc_ex.h
  • ADDR_1ST_CYCLE : stm32l4xx_hal_nand.h
  • ADDR_2ND_CYCLE : stm32l4xx_hal_nand.h
  • ADDR_3RD_CYCLE : stm32l4xx_hal_nand.h
  • ADDR_4TH_CYCLE : stm32l4xx_hal_nand.h
  • ADDR_AREA : stm32l4xx_hal_nand.h
  • ANALOG_MODE : stm32l4xx_hal_gpio.c
  • ARRAY_ADDRESS : stm32l4xx_hal_nand.h
  • assert_param : stm32l4xx_ll_gpio.c , stm32l4xx_ll_usart.c , stm32l4xx_ll_adc.c , stm32l4xx_ll_exti.c , stm32l4xx_ll_tim.c , stm32l4xx_ll_lptim.c , stm32l4xx_ll_swpmi.c , stm32l4xx_hal_conf.h , stm32l4xx_ll_dac.c , stm32l4xx_ll_rcc.c , stm32l4xx_ll_dma.c , stm32l4xx_ll_rtc.c , stm32l4xx_ll_crc.c , stm32l4xx_ll_opamp.c , stm32l4xx_ll_comp.c , stm32l4xx_ll_i2c.c , stm32l4xx_ll_lpuart.c , stm32l4xx_ll_rng.c , stm32l4xx_ll_utils.c , stm32l4xx_ll_spi.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- b -

  • BDCR_REG_INDEX : stm32l4xx_hal_rcc.h
  • BDTR_BK2F_SHIFT : stm32l4xx_hal_tim_ex.c
  • BDTR_BKF_SHIFT : stm32l4xx_hal_tim_ex.c
  • BRER_BitNumber : stm32l4xx_hal.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
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- c -

  • CAN_BS1_10TQ : stm32l4xx_hal_can.h
  • CAN_BS1_11TQ : stm32l4xx_hal_can.h
  • CAN_BS1_12TQ : stm32l4xx_hal_can.h
  • CAN_BS1_13TQ : stm32l4xx_hal_can.h
  • CAN_BS1_14TQ : stm32l4xx_hal_can.h
  • CAN_BS1_15TQ : stm32l4xx_hal_can.h
  • CAN_BS1_16TQ : stm32l4xx_hal_can.h
  • CAN_BS1_1TQ : stm32l4xx_hal_can.h
  • CAN_BS1_2TQ : stm32l4xx_hal_can.h
  • CAN_BS1_3TQ : stm32l4xx_hal_can.h
  • CAN_BS1_4TQ : stm32l4xx_hal_can.h
  • CAN_BS1_5TQ : stm32l4xx_hal_can.h
  • CAN_BS1_6TQ : stm32l4xx_hal_can.h
  • CAN_BS1_7TQ : stm32l4xx_hal_can.h
  • CAN_BS1_8TQ : stm32l4xx_hal_can.h
  • CAN_BS1_9TQ : stm32l4xx_hal_can.h
  • CAN_BS2_1TQ : stm32l4xx_hal_can.h
  • CAN_BS2_2TQ : stm32l4xx_hal_can.h
  • CAN_BS2_3TQ : stm32l4xx_hal_can.h
  • CAN_BS2_4TQ : stm32l4xx_hal_can.h
  • CAN_BS2_5TQ : stm32l4xx_hal_can.h
  • CAN_BS2_6TQ : stm32l4xx_hal_can.h
  • CAN_BS2_7TQ : stm32l4xx_hal_can.h
  • CAN_BS2_8TQ : stm32l4xx_hal_can.h
  • CAN_FIFO0 : stm32l4xx_hal_can.h
  • CAN_FIFO1 : stm32l4xx_hal_can.h
  • CAN_FILTER_FIFO0 : stm32l4xx_hal_can.h
  • CAN_FILTER_FIFO1 : stm32l4xx_hal_can.h
  • CAN_FILTERMODE_IDLIST : stm32l4xx_hal_can.h
  • CAN_FILTERMODE_IDMASK : stm32l4xx_hal_can.h
  • CAN_FILTERSCALE_16BIT : stm32l4xx_hal_can.h
  • CAN_FILTERSCALE_32BIT : stm32l4xx_hal_can.h
  • CAN_FLAG_BOF : stm32l4xx_hal_can.h
  • CAN_FLAG_EPV : stm32l4xx_hal_can.h
  • CAN_FLAG_EWG : stm32l4xx_hal_can.h
  • CAN_FLAG_FF0 : stm32l4xx_hal_can.h
  • CAN_FLAG_FF1 : stm32l4xx_hal_can.h
  • CAN_FLAG_FOV0 : stm32l4xx_hal_can.h
  • CAN_FLAG_FOV1 : stm32l4xx_hal_can.h
  • CAN_FLAG_MASK : stm32l4xx_hal_can.h
  • CAN_FLAG_RQCP0 : stm32l4xx_hal_can.h
  • CAN_FLAG_RQCP1 : stm32l4xx_hal_can.h
  • CAN_FLAG_RQCP2 : stm32l4xx_hal_can.h
  • CAN_FLAG_SLAK : stm32l4xx_hal_can.h
  • CAN_FLAG_SLAKI : stm32l4xx_hal_can.h
  • CAN_FLAG_TME0 : stm32l4xx_hal_can.h
  • CAN_FLAG_TME1 : stm32l4xx_hal_can.h
  • CAN_FLAG_TME2 : stm32l4xx_hal_can.h
  • CAN_FLAG_TXOK0 : stm32l4xx_hal_can.h
  • CAN_FLAG_TXOK1 : stm32l4xx_hal_can.h
  • CAN_FLAG_TXOK2 : stm32l4xx_hal_can.h
  • CAN_FLAG_WKU : stm32l4xx_hal_can.h
  • CAN_ID_EXT : stm32l4xx_hal_can.h
  • CAN_ID_STD : stm32l4xx_hal_can.h
  • CAN_INITSTATUS_FAILED : stm32l4xx_hal_can.h
  • CAN_INITSTATUS_SUCCESS : stm32l4xx_hal_can.h
  • CAN_IT_BOF : stm32l4xx_hal_can.h
  • CAN_IT_EPV : stm32l4xx_hal_can.h
  • CAN_IT_ERR : stm32l4xx_hal_can.h
  • CAN_IT_EWG : stm32l4xx_hal_can.h
  • CAN_IT_FF0 : stm32l4xx_hal_can.h
  • CAN_IT_FF1 : stm32l4xx_hal_can.h
  • CAN_IT_FMP0 : stm32l4xx_hal_can.h
  • CAN_IT_FMP1 : stm32l4xx_hal_can.h
  • CAN_IT_FOV0 : stm32l4xx_hal_can.h
  • CAN_IT_FOV1 : stm32l4xx_hal_can.h
  • CAN_IT_LEC : stm32l4xx_hal_can.h
  • CAN_IT_SLK : stm32l4xx_hal_can.h
  • CAN_IT_TME : stm32l4xx_hal_can.h
  • CAN_IT_WKU : stm32l4xx_hal_can.h
  • CAN_MODE_LOOPBACK : stm32l4xx_hal_can.h
  • CAN_MODE_NORMAL : stm32l4xx_hal_can.h
  • CAN_MODE_SILENT : stm32l4xx_hal_can.h
  • CAN_MODE_SILENT_LOOPBACK : stm32l4xx_hal_can.h
  • CAN_RTR_DATA : stm32l4xx_hal_can.h
  • CAN_RTR_REMOTE : stm32l4xx_hal_can.h
  • CAN_SJW_1TQ : stm32l4xx_hal_can.h
  • CAN_SJW_2TQ : stm32l4xx_hal_can.h
  • CAN_SJW_3TQ : stm32l4xx_hal_can.h
  • CAN_SJW_4TQ : stm32l4xx_hal_can.h
  • CAN_TIMEOUT_VALUE : stm32l4xx_hal_can.c
  • CAN_TXMAILBOX_0 : stm32l4xx_hal_can.h
  • CAN_TXMAILBOX_1 : stm32l4xx_hal_can.h
  • CAN_TXMAILBOX_2 : stm32l4xx_hal_can.h
  • CAN_TXSTATUS_NOMAILBOX : stm32l4xx_hal_can.h
  • CFI1_ADDRESS : stm32l4xx_hal_nor.h
  • CFI2_ADDRESS : stm32l4xx_hal_nor.h
  • CFI3_ADDRESS : stm32l4xx_hal_nor.h
  • CFI4_ADDRESS : stm32l4xx_hal_nor.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • CMD_AREA : stm32l4xx_hal_nand.h
  • COMP_BLANKINGSRC_NONE : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM15_OC1_COMP2 : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5_COMP1 : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3_COMP1 : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC3_COMP1 : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM3_OC4_COMP2 : stm32l4xx_hal_comp.h
  • COMP_BLANKINGSRC_TIM8_OC5_COMP2 : stm32l4xx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32l4xx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32l4xx_hal_comp.c
  • COMP_EXTI_EVENT : stm32l4xx_hal_comp.h
  • COMP_EXTI_FALLING : stm32l4xx_hal_comp.h
  • COMP_EXTI_IT : stm32l4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32l4xx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32l4xx_hal_comp.h
  • COMP_EXTI_RISING : stm32l4xx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32l4xx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32l4xx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32l4xx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32l4xx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH1 : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_DAC1_CH2 : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32l4xx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32l4xx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32l4xx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32l4xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32l4xx_hal_comp.c
  • COMP_OUTPUT_LEVEL_HIGH : stm32l4xx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32l4xx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32l4xx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32l4xx_hal_comp.h
  • COMP_POWERMODE_HIGHSPEED : stm32l4xx_hal_comp.h
  • COMP_POWERMODE_MEDIUMSPEED : stm32l4xx_hal_comp.h
  • COMP_POWERMODE_ULTRALOWPOWER : stm32l4xx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32l4xx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32l4xx_hal_comp.h
  • COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32l4xx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32l4xx_hal_comp.h
  • CR_REG_INDEX : stm32l4xx_hal_rcc.h
  • CRC_INPUTDATA_FORMAT_BYTES : stm32l4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32l4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32l4xx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32l4xx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32l4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32l4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32l4xx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32l4xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32l4xx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32l4xx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32l4xx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32l4xx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32l4xx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32l4xx_hal_crc.h
  • CRYP_AES_DISABLE : stm32l4xx_hal_cryp.h
  • CRYP_AES_ENABLE : stm32l4xx_hal_cryp.h
  • CRYP_ALGOMODE_DECRYPT : stm32l4xx_hal_cryp.h
  • CRYP_ALGOMODE_ENCRYPT : stm32l4xx_hal_cryp.h
  • CRYP_ALGOMODE_KEYDERIVATION : stm32l4xx_hal_cryp.h
  • CRYP_ALGOMODE_KEYDERIVATION_DECRYPT : stm32l4xx_hal_cryp.h
  • CRYP_ALGOMODE_TAG_GENERATION : stm32l4xx_hal_cryp.h
  • CRYP_BUSY_TIMEOUTVALUE : stm32l4xx_hal_cryp_ex.c
  • CRYP_CCF_CLEAR : stm32l4xx_hal_cryp.h
  • CRYP_CCF_TIMEOUTVALUE : stm32l4xx_hal_cryp_ex.c
  • CRYP_CHAINMODE_AES_CBC : stm32l4xx_hal_cryp.h
  • CRYP_CHAINMODE_AES_CMAC : stm32l4xx_hal_cryp.h
  • CRYP_CHAINMODE_AES_CTR : stm32l4xx_hal_cryp.h
  • CRYP_CHAINMODE_AES_ECB : stm32l4xx_hal_cryp.h
  • CRYP_CHAINMODE_AES_GCM_GMAC : stm32l4xx_hal_cryp.h
  • CRYP_DATATYPE_16B : stm32l4xx_hal_cryp.h
  • CRYP_DATATYPE_1B : stm32l4xx_hal_cryp.h
  • CRYP_DATATYPE_32B : stm32l4xx_hal_cryp.h
  • CRYP_DATATYPE_8B : stm32l4xx_hal_cryp.h
  • CRYP_DMAIN_DISABLE : stm32l4xx_hal_cryp.h
  • CRYP_DMAIN_ENABLE : stm32l4xx_hal_cryp.h
  • CRYP_DMAOUT_DISABLE : stm32l4xx_hal_cryp.h
  • CRYP_DMAOUT_ENABLE : stm32l4xx_hal_cryp.h
  • CRYP_ERR_CLEAR : stm32l4xx_hal_cryp.h
  • CRYP_FLAG_BUSY : stm32l4xx_hal_cryp.h
  • CRYP_FLAG_CCF : stm32l4xx_hal_cryp.h
  • CRYP_FLAG_RDERR : stm32l4xx_hal_cryp.h
  • CRYP_FLAG_WRERR : stm32l4xx_hal_cryp.h
  • CRYP_GCM_INIT_PHASE : stm32l4xx_hal_cryp.h
  • CRYP_GCM_PAYLOAD_PHASE : stm32l4xx_hal_cryp.h
  • CRYP_GCMCMAC_FINAL_PHASE : stm32l4xx_hal_cryp.h
  • CRYP_GCMCMAC_HEADER_PHASE : stm32l4xx_hal_cryp.h
  • CRYP_IT_CCF : stm32l4xx_hal_cryp.h
  • CRYP_IT_CCFIE : stm32l4xx_hal_cryp.h
  • CRYP_IT_ERRIE : stm32l4xx_hal_cryp.h
  • CRYP_IT_RDERR : stm32l4xx_hal_cryp.h
  • CRYP_IT_WRERR : stm32l4xx_hal_cryp.h
  • CRYP_KEY_WRITE_DISABLE : stm32l4xx_hal_cryp.h
  • CRYP_KEY_WRITE_ENABLE : stm32l4xx_hal_cryp.h
  • CRYP_KEYSIZE_128B : stm32l4xx_hal_cryp.h
  • CRYP_KEYSIZE_256B : stm32l4xx_hal_cryp.h
  • CRYP_POLLING_OFF : stm32l4xx_hal_cryp_ex.c
  • CRYP_POLLING_ON : stm32l4xx_hal_cryp_ex.c
  • CSR_REG_INDEX : stm32l4xx_hal_rcc.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- d -

  • DAC_ALIGN_12B_L : stm32l4xx_hal_dac.h
  • DAC_ALIGN_12B_R : stm32l4xx_hal_dac.h
  • DAC_ALIGN_8B_R : stm32l4xx_hal_dac.h
  • DAC_CHANNEL_1 : stm32l4xx_hal_dac.h
  • DAC_CHANNEL_2 : stm32l4xx_hal_dac.h
  • DAC_CHIPCONNECT_DISABLE : stm32l4xx_hal_dac.h
  • DAC_CHIPCONNECT_ENABLE : stm32l4xx_hal_dac.h
  • DAC_CR_CH1_BITOFFSET : stm32l4xx_ll_dac.h
  • DAC_CR_CH2_BITOFFSET : stm32l4xx_ll_dac.h
  • DAC_CR_CHX_BITOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_DHR12LD_DACC2DHR_BITOFFSET_POS : stm32l4xx_ll_dac.h
  • DAC_DHR12R1_ALIGNMENT : stm32l4xx_hal_dac.h
  • DAC_DHR12R2_ALIGNMENT : stm32l4xx_hal_dac.h
  • DAC_DHR12RD_ALIGNMENT : stm32l4xx_hal_dac.h
  • DAC_DHR12RD_DACC2DHR_BITOFFSET_POS : stm32l4xx_ll_dac.h
  • DAC_DHR8RD_DACC2DHR_BITOFFSET_POS : stm32l4xx_ll_dac.h
  • DAC_DIGITAL_SCALE_12BITS : stm32l4xx_ll_dac.h
  • DAC_FLAG_DMAUDR1 : stm32l4xx_hal_dac.h
  • DAC_FLAG_DMAUDR2 : stm32l4xx_hal_dac.h
  • DAC_IT_DMAUDR1 : stm32l4xx_hal_dac.h
  • DAC_IT_DMAUDR2 : stm32l4xx_hal_dac.h
  • DAC_LFSRUNMASK_BIT0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS10_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS11_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS1_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS2_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS3_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS4_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS5_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS6_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS7_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS8_0 : stm32l4xx_hal_dac_ex.h
  • DAC_LFSRUNMASK_BITS9_0 : stm32l4xx_hal_dac_ex.h
  • DAC_OUTPUTBUFFER_DISABLE : stm32l4xx_hal_dac.h
  • DAC_OUTPUTBUFFER_ENABLE : stm32l4xx_hal_dac.h
  • DAC_REG_DHR12L1_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR12L2_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR12LX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_REG_DHR12R1_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR12R2_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR12RX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_REG_DHR8R1_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR8R2_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DHR8RX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_REG_DHRX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_REG_DOR1_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DOR2_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_DORX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_REG_SHSR1_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_SHSR2_REGOFFSET : stm32l4xx_ll_dac.h
  • DAC_REG_SHSRX_REGOFFSET_MASK : stm32l4xx_ll_dac.h
  • DAC_SAMPLEANDHOLD_DISABLE : stm32l4xx_hal_dac.h
  • DAC_SAMPLEANDHOLD_ENABLE : stm32l4xx_hal_dac.h
  • DAC_SWTR_CH1 : stm32l4xx_ll_dac.h
  • DAC_SWTR_CH2 : stm32l4xx_ll_dac.h
  • DAC_SWTR_CHX_MASK : stm32l4xx_ll_dac.h
  • DAC_TRIANGLEAMPLITUDE_1 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_1023 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_127 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_15 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_2047 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_255 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_3 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_31 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_4095 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_511 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_63 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIANGLEAMPLITUDE_7 : stm32l4xx_hal_dac_ex.h
  • DAC_TRIGGER_EXT_IT9 : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_NONE : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_SOFTWARE : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T2_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T4_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T5_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T6_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T7_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIGGER_T8_TRGO : stm32l4xx_hal_dac.h
  • DAC_TRIMMING_FACTORY : stm32l4xx_hal_dac.h
  • DAC_TRIMMING_USER : stm32l4xx_hal_dac.h
  • DATA_BLOCK_SIZE : stm32l4xx_hal_sd.c
  • DATA_CACHE_ENABLE : stm32l4xx_hal_conf.h
  • DBGMCU_REVID_POSITION : stm32l4xx_ll_system.h
  • DEFAULT_CRC32_POLY : stm32l4xx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32l4xx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32l4xx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32l4xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32l4xx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32l4xx_hal_crc.h
  • DEVICE_CODE1_ADDR : stm32l4xx_hal_nor.h
  • DEVICE_CODE2_ADDR : stm32l4xx_hal_nor.h
  • DEVICE_CODE3_ADDR : stm32l4xx_hal_nor.h
  • DFSDM1_CHANNEL_NUMBER : stm32l4xx_hal_dfsdm.c
  • DFSDM_AWD_HIGH_THRESHOLD : stm32l4xx_hal_dfsdm.h
  • DFSDM_AWD_LOW_THRESHOLD : stm32l4xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_0 : stm32l4xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_1 : stm32l4xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_2 : stm32l4xx_hal_dfsdm.h
  • DFSDM_BREAK_SIGNAL_3 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_0 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_1 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_2 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_3 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_4 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_5 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_6 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_7 : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_DUAL_MODE : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_EXTERNAL_INPUTS : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FASTSINC_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERLEAVED_MODE : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_INTERNAL_REGISTER : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_FALLING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_MANCHESTER_RISING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SAME_CHANNEL_PINS : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC1_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC2_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SINC3_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_FALLING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_SPI_RISING : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHANNEL_STANDARD_MODE : stm32l4xx_hal_dfsdm.h
  • DFSDM_CHAWSCDR_BKSCD_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_CHAWSCDR_FOSR_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_CHCFGR1_CLK_DIV_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_CHCFGR2_DTRBS_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_CHCFGR2_OFFSET_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_CKAB_TIMEOUT : stm32l4xx_hal_dfsdm.c
  • DFSDM_CONTINUOUS_CONV_OFF : stm32l4xx_hal_dfsdm.h
  • DFSDM_CONTINUOUS_CONV_ON : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_AWD_CHANNEL_DATA : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_AWD_FILTER_DATA : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_DMA : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_INJECTED_OVERRUN : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_NONE : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_ERROR_REGULAR_OVERRUN : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_BOTH_EDGES : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI11 : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_EXTI15 : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_FALLING_EDGE : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_RISING_EDGE : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM16_OC1 : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM3_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM4_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM6_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM7_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_EXT_TRIGGER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_FASTSINC_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC1_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC2_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC3_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC4_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SINC5_ORDER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SW_TRIGGER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FILTER_SYNC_TRIGGER : stm32l4xx_hal_dfsdm.h
  • DFSDM_FLTAWHTR_THRESHOLD_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTAWLTR_THRESHOLD_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTAWSR_HIGH_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTCNVTIMR_DATA_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTCR1_MSB_RCH_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTCR2_AWDCH_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTCR2_EXCH_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTEXMAX_DATA_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTEXMIN_DATA_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTFCR_FOSR_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTICR_CLRCKABF_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTICR_CLRSCDF_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTISR_CKABF_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTISR_SCDF_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTJDATAR_DATA_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_FLTRDATAR_DATA_OFFSET : stm32l4xx_hal_dfsdm.c
  • DFSDM_LSB_MASK : stm32l4xx_hal_dfsdm.c
  • DFSDM_MSB_MASK : stm32l4xx_hal_dfsdm.c
  • DFSDM_NO_BREAK_SIGNAL : stm32l4xx_hal_dfsdm.h
  • DIVIDER_P_UPDATE : stm32l4xx_hal_rcc_ex.c
  • DIVIDER_Q_UPDATE : stm32l4xx_hal_rcc_ex.c
  • DIVIDER_R_UPDATE : stm32l4xx_hal_rcc_ex.c
  • DMA_CIRCULAR : stm32l4xx_hal_dma.h
  • DMA_CSELR_OFFSET : stm32l4xx_ll_dma.h
  • DMA_FLAG_GL1 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL2 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL3 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL4 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL5 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL6 : stm32l4xx_hal_dma.h
  • DMA_FLAG_GL7 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT1 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT2 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT3 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT4 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT5 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT6 : stm32l4xx_hal_dma.h
  • DMA_FLAG_HT7 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC1 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC2 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC3 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC4 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC5 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC6 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TC7 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE1 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE2 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE3 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE4 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE5 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE6 : stm32l4xx_hal_dma.h
  • DMA_FLAG_TE7 : stm32l4xx_hal_dma.h
  • DMA_IT_HT : stm32l4xx_hal_dma.h
  • DMA_IT_TC : stm32l4xx_hal_dma.h
  • DMA_IT_TE : stm32l4xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32l4xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32l4xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32l4xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32l4xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32l4xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32l4xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32l4xx_hal_dma.h
  • DMA_NORMAL : stm32l4xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32l4xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32l4xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32l4xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32l4xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32l4xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32l4xx_hal_dma.h
  • DMA_POSITION_CSELR_CXS : stm32l4xx_ll_dma.h
  • DMA_PRIORITY_HIGH : stm32l4xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32l4xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32l4xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32l4xx_hal_dma.h
  • DMA_REQUEST_0 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_1 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_2 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_3 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_4 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_5 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_6 : stm32l4xx_hal_dma.h
  • DMA_REQUEST_7 : stm32l4xx_hal_dma.h
  • DT_DELAY_1 : stm32l4xx_ll_tim.h
  • DT_DELAY_2 : stm32l4xx_ll_tim.h
  • DT_DELAY_3 : stm32l4xx_ll_tim.h
  • DT_DELAY_4 : stm32l4xx_ll_tim.h
  • DT_RANGE_1 : stm32l4xx_ll_tim.h
  • DT_RANGE_2 : stm32l4xx_ll_tim.h
  • DT_RANGE_3 : stm32l4xx_ll_tim.h
  • DT_RANGE_4 : stm32l4xx_ll_tim.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- e -

  • EXTERNAL_SAI1_CLOCK_VALUE : stm32l4xx_hal_conf.h
  • EXTERNAL_SAI2_CLOCK_VALUE : stm32l4xx_hal_conf.h
  • EXTI_MODE : stm32l4xx_hal_gpio.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- f -

  • FALLING_EDGE : stm32l4xx_hal_gpio.c
  • FB_MODE_BB : stm32l4xx_hal.c
  • FB_MODE_BitNumber : stm32l4xx_hal.c
  • FIREWALL_PRE_ARM_RESET : stm32l4xx_hal_firewall.h
  • FIREWALL_PRE_ARM_SET : stm32l4xx_hal_firewall.h
  • FIREWALL_VOLATILEDATA_EXECUTABLE : stm32l4xx_hal_firewall.h
  • FIREWALL_VOLATILEDATA_NOT_EXECUTABLE : stm32l4xx_hal_firewall.h
  • FIREWALL_VOLATILEDATA_NOT_SHARED : stm32l4xx_hal_firewall.h
  • FIREWALL_VOLATILEDATA_SHARED : stm32l4xx_hal_firewall.h
  • FLASH_BANK_1 : stm32l4xx_hal_flash.h
  • FLASH_BANK_2 : stm32l4xx_hal_flash.h
  • FLASH_BANK_BOTH : stm32l4xx_hal_flash.h
  • FLASH_BANK_SIZE : stm32l4xx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS : stm32l4xx_hal_flash.h
  • FLASH_FLAG_BSY : stm32l4xx_hal_flash.h
  • FLASH_FLAG_ECCC : stm32l4xx_hal_flash.h
  • FLASH_FLAG_ECCD : stm32l4xx_hal_flash.h
  • FLASH_FLAG_EOP : stm32l4xx_hal_flash.h
  • FLASH_FLAG_FASTERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_MISERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_OPTVERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_PROGERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_RDERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_SIZERR : stm32l4xx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32l4xx_hal_flash.h
  • FLASH_IT_ECCC : stm32l4xx_hal_flash.h
  • FLASH_IT_EOP : stm32l4xx_hal_flash.h
  • FLASH_IT_OPERR : stm32l4xx_hal_flash.h
  • FLASH_IT_RDERR : stm32l4xx_hal_flash.h
  • FLASH_KEY1 : stm32l4xx_hal_flash.h
  • FLASH_KEY2 : stm32l4xx_hal_flash.h
  • FLASH_LATENCY_0 : stm32l4xx_hal_flash.h
  • FLASH_LATENCY_1 : stm32l4xx_hal_flash.h
  • FLASH_LATENCY_2 : stm32l4xx_hal_flash.h
  • FLASH_LATENCY_3 : stm32l4xx_hal_flash.h
  • FLASH_LATENCY_4 : stm32l4xx_hal_flash.h
  • FLASH_OPTKEY1 : stm32l4xx_hal_flash.h
  • FLASH_OPTKEY2 : stm32l4xx_hal_flash.h
  • FLASH_PAGE_SIZE : stm32l4xx_hal_flash.h
  • FLASH_PDKEY1 : stm32l4xx_ll_system.h , stm32l4xx_hal_flash.h
  • FLASH_PDKEY2 : stm32l4xx_ll_system.h , stm32l4xx_hal_flash.h
  • FLASH_SIZE : stm32l4xx_hal_flash.h
  • FLASH_SIZE_DATA_REGISTER : stm32l4xx_hal_flash.h
  • FLASH_TIMEOUT_VALUE : stm32l4xx_hal_flash.h
  • FLASH_TYPEERASE_MASSERASE : stm32l4xx_hal_flash.h
  • FLASH_TYPEERASE_PAGES : stm32l4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32l4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST : stm32l4xx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST_AND_LAST : stm32l4xx_hal_flash.h
  • FLASHSIZE_BASE_ADDRESS : stm32l4xx_ll_utils.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- g -

  • GPIO_AF0_LCDBIAS : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF0_MCO : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF0_RTC_50Hz : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF0_SWJ : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF0_TRACE : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF10_OTG_FS : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF10_QUADSPI : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF11_LCD : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF12_COMP1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF12_COMP2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF12_FMC : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF12_SDMMC1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF12_SWPMI1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF13_SAI1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF13_SAI2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF13_TIM8_COMP1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF13_TIM8_COMP2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_LPTIM2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM15 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM16 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM17 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF14_TIM8_COMP1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_IR : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM5 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF1_TIM8 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM3 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM4 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF2_TIM5 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM1_COMP1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM1_COMP2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF3_TIM8 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF6_DFSDM1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF6_SPI3 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF7_USART2 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF7_USART3 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF8_LPUART1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF8_UART4 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF8_UART5 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF9_CAN1 : stm32l4xx_hal_gpio_ex.h
  • GPIO_AF9_TSC : stm32l4xx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32l4xx_hal_gpio_ex.h
  • GPIO_MODE : stm32l4xx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32l4xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32l4xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32l4xx_hal_gpio.h
  • GPIO_MODE_ANALOG_ADC_CONTROL : stm32l4xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32l4xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32l4xx_hal_gpio.h
  • GPIO_MODE_IT : stm32l4xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32l4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32l4xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32l4xx_hal_gpio.h
  • GPIO_NOPULL : stm32l4xx_hal_gpio.h
  • GPIO_NUMBER : stm32l4xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32l4xx_hal_gpio.c
  • GPIO_PIN_0 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_1 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_10 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_11 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_12 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_13 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_14 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_15 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_2 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_3 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_4 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_5 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_6 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_7 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_8 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_9 : stm32l4xx_hal_gpio.h
  • GPIO_PIN_All : stm32l4xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32l4xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32l4xx_hal_gpio.h
  • GPIO_PULLUP : stm32l4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32l4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32l4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32l4xx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32l4xx_hal_gpio.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- h -

  • HAL_ADC_ERROR_DMA : stm32l4xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32l4xx_hal_adc.h
  • HAL_ADC_ERROR_JQOVF : stm32l4xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32l4xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32l4xx_hal_adc.h
  • HAL_ADC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_ADC_STATE_AWD1 : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32l4xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32l4xx_hal_adc.h
  • HAL_CAN_ERROR_ACK : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_BD : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_BOF : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_BR : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_CRC : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_EPV : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_EWG : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_FOR : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_NONE : stm32l4xx_hal_can.h
  • HAL_CAN_ERROR_STF : stm32l4xx_hal_can.h
  • HAL_CAN_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_COMP_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_CRC_Input_Data_Reverse : stm32l4xx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32l4xx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32l4xx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32l4xx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32l4xx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_CRC_Output_Data_Reverse : stm32l4xx_hal_crc.h
  • HAL_CRYP_BUSY_ERROR : stm32l4xx_hal_cryp.h
  • HAL_CRYP_DMA_ERROR : stm32l4xx_hal_cryp.h
  • HAL_CRYP_ERROR_NONE : stm32l4xx_hal_cryp.h
  • HAL_CRYP_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_CRYP_READ_ERROR : stm32l4xx_hal_cryp.h
  • HAL_CRYP_WRITE_ERROR : stm32l4xx_hal_cryp.h
  • HAL_DAC_ERROR_DMA : stm32l4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH1 : stm32l4xx_hal_dac.h
  • HAL_DAC_ERROR_DMAUNDERRUNCH2 : stm32l4xx_hal_dac.h
  • HAL_DAC_ERROR_NONE : stm32l4xx_hal_dac.h
  • HAL_DAC_ERROR_TIMEOUT : stm32l4xx_hal_dac.h
  • HAL_DAC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_DFSDM_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_DMA_ERROR_NO_XFER : stm32l4xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32l4xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32l4xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32l4xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32l4xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_FIREWALL_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_FLASH_ERROR_ECCD : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_FAST : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_MIS : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_OP : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_OPTV : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_RD : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_SIZ : stm32l4xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32l4xx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_GPIO_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_HCD_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_I2C_ERROR_AF : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32l4xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32l4xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_IRDA_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32l4xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_LCD_ERROR_ENS : stm32l4xx_hal_lcd.h
  • HAL_LCD_ERROR_FCRSF : stm32l4xx_hal_lcd.h
  • HAL_LCD_ERROR_NONE : stm32l4xx_hal_lcd.h
  • HAL_LCD_ERROR_RDY : stm32l4xx_hal_lcd.h
  • HAL_LCD_ERROR_UDD : stm32l4xx_hal_lcd.h
  • HAL_LCD_ERROR_UDR : stm32l4xx_hal_lcd.h
  • HAL_LCD_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_LPTIM_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_NAND_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_OPAMP_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_PCD_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_PWR_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_QPSI_TIMEOUT_DEFAULT_VALUE : stm32l4xx_hal_qspi.h
  • HAL_QSPI_ERROR_DMA : stm32l4xx_hal_qspi.h
  • HAL_QSPI_ERROR_INVALID_PARAM : stm32l4xx_hal_qspi.h
  • HAL_QSPI_ERROR_NONE : stm32l4xx_hal_qspi.h
  • HAL_QSPI_ERROR_TIMEOUT : stm32l4xx_hal_qspi.h
  • HAL_QSPI_ERROR_TRANSFER : stm32l4xx_hal_qspi.h
  • HAL_QSPI_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_RCC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_RNG_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_RTC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SAI_ERROR_AFSDET : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_DMA : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32l4xx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32l4xx_hal_sai.h
  • HAL_SAI_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SD_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SMARTCARD_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SMBUS_ERROR_ACKF : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SMBUS_STATE_BUSY : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32l4xx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32l4xx_hal_smbus.h
  • HAL_SPI_ERROR_CRC : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32l4xx_hal_spi.h
  • HAL_SPI_ERROR_UNKNOW : stm32l4xx_hal_spi.h
  • HAL_SPI_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SRAM_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_SWPMI_ERROR_CRC : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_DMA : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_NONE : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_OVR : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_ERROR_UDR : stm32l4xx_hal_swpmi.h
  • HAL_SWPMI_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_TIM_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_TIMEOUT_ADDR : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_DIR : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_RXNE : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32l4xx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32l4xx_hal_smbus.c
  • HAL_TSC_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_UART_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_UART_TIMEOUT_VALUE : stm32l4xx_hal_uart.h
  • HAL_USART_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HAL_WWDG_MODULE_ENABLED : stm32l4xx_hal_conf.h
  • HCD_PHY_EMBEDDED : stm32l4xx_hal_hcd.h
  • HCD_SPEED_FULL : stm32l4xx_hal_hcd.h
  • HCD_SPEED_HIGH : stm32l4xx_hal_hcd.h
  • HCD_SPEED_LOW : stm32l4xx_hal_hcd.h
  • HSE_STARTUP_TIMEOUT : stm32l4xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • HSE_VALUE : stm32l4xx_hal_conf.h , stm32l4xx_ll_rcc.h
  • HSI48_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • HSI48_VALUE : stm32l4xx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • HSI_VALUE : stm32l4xx_hal_conf.h , stm32l4xx_ll_rcc.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32l4xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32l4xx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32l4xx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32l4xx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32l4xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32l4xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32l4xx_hal_i2c.h
  • I2C_DUALADDRESS_DISABLE : stm32l4xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32l4xx_hal_i2c.h
  • I2C_FASTMODEPLUS_I2C1 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C2 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32l4xx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32l4xx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32l4xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32l4xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_AF : stm32l4xx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32l4xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32l4xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32l4xx_hal_i2c.h
  • I2C_FLAG_DIR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32l4xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32l4xx_hal_i2c.h
  • I2C_FLAG_TC : stm32l4xx_hal_i2c.h
  • I2C_FLAG_TCR : stm32l4xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32l4xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32l4xx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32l4xx_hal_i2c.h
  • I2C_GENERALCALL_DISABLE : stm32l4xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32l4xx_hal_i2c.h
  • I2C_GENERATE_START : stm32l4xx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32l4xx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32l4xx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32l4xx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32l4xx_hal_i2c.h
  • I2C_GET_DIR : stm32l4xx_hal_i2c.h
  • I2C_GET_DMA_REMAIN_DATA : stm32l4xx_hal_i2c.c
  • I2C_GET_OWN_ADDRESS1 : stm32l4xx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32l4xx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32l4xx_hal_i2c.h
  • I2C_IT_ADDRI : stm32l4xx_hal_i2c.h
  • I2C_IT_ERRI : stm32l4xx_hal_i2c.h
  • I2C_IT_NACKI : stm32l4xx_hal_i2c.h
  • I2C_IT_RXI : stm32l4xx_hal_i2c.h
  • I2C_IT_STOPI : stm32l4xx_hal_i2c.h
  • I2C_IT_TCI : stm32l4xx_hal_i2c.h
  • I2C_IT_TXI : stm32l4xx_hal_i2c.h
  • I2C_LAST_FRAME : stm32l4xx_hal_i2c.h
  • I2C_MEM_ADD_LSB : stm32l4xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32l4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32l4xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32l4xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32l4xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32l4xx_hal_i2c.h
  • I2C_NO_STARTSTOP : stm32l4xx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32l4xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32l4xx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32l4xx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32l4xx_hal_i2c.h
  • I2C_POSITION_CR1_DNF : stm32l4xx_ll_i2c.h
  • I2C_POSITION_CR2_NBYTES : stm32l4xx_ll_i2c.h
  • I2C_POSITION_ISR_ADDCODE : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMEOUTR_TIMEOUTB : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMINGR_PRESC : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMINGR_SCLDEL : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMINGR_SCLH : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMINGR_SCLL : stm32l4xx_ll_i2c.h
  • I2C_POSITION_TIMINGR_SDADEL : stm32l4xx_ll_i2c.h
  • I2C_RELOAD_MODE : stm32l4xx_hal_i2c.h
  • I2C_RESET_CR2 : stm32l4xx_hal_i2c.h
  • I2C_SOFTEND_MODE : stm32l4xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32l4xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32l4xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32l4xx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32l4xx_hal_i2c.c
  • I2C_STATE_MSK : stm32l4xx_hal_i2c.c
  • I2C_STATE_NONE : stm32l4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32l4xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32l4xx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32l4xx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32l4xx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32l4xx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32l4xx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32l4xx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32l4xx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32l4xx_hal_i2c.c
  • INSTRUCTION_CACHE_ENABLE : stm32l4xx_hal_conf.h
  • IRDA_AUTOBAUD_REQUEST : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_FEF : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32l4xx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32l4xx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32l4xx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32l4xx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32l4xx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32l4xx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_ABRE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32l4xx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32l4xx_hal_irda.h
  • IRDA_FLAG_FE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_NE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_PE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_REACK : stm32l4xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32l4xx_hal_irda.h
  • IRDA_FLAG_TC : stm32l4xx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32l4xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32l4xx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32l4xx_hal_irda_ex.h
  • IRDA_IT_ERR : stm32l4xx_hal_irda.h
  • IRDA_IT_FE : stm32l4xx_hal_irda.h
  • IRDA_IT_IDLE : stm32l4xx_hal_irda.h
  • IRDA_IT_MASK : stm32l4xx_hal_irda.h
  • IRDA_IT_NE : stm32l4xx_hal_irda.h
  • IRDA_IT_ORE : stm32l4xx_hal_irda.h
  • IRDA_IT_PE : stm32l4xx_hal_irda.h
  • IRDA_IT_RXNE : stm32l4xx_hal_irda.h
  • IRDA_IT_TC : stm32l4xx_hal_irda.h
  • IRDA_IT_TXE : stm32l4xx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32l4xx_hal_irda.h
  • IRDA_MODE_DISABLE : stm32l4xx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32l4xx_hal_irda.h
  • IRDA_MODE_RX : stm32l4xx_hal_irda.h
  • IRDA_MODE_TX : stm32l4xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32l4xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32l4xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32l4xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32l4xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32l4xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32l4xx_hal_irda.h
  • IRDA_RXDATA_FLUSH_REQUEST : stm32l4xx_hal_irda.h
  • IRDA_STATE_DISABLE : stm32l4xx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32l4xx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32l4xx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32l4xx_hal_irda.h
  • IRDA_WORDLENGTH_7B : stm32l4xx_hal_irda.h
  • IRDA_WORDLENGTH_8B : stm32l4xx_hal_irda.h
  • IRDA_WORDLENGTH_9B : stm32l4xx_hal_irda.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32l4xx_hal_adc_ex.h
  • IS_ADC_CALFACT : stm32l4xx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32l4xx_hal_adc_ex.h
  • IS_ADC_CLOCKPRESCALER : stm32l4xx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32l4xx_hal_adc_ex.h
  • IS_ADC_DATA_ALIGN : stm32l4xx_hal_adc.h
  • IS_ADC_DFSDMCFG_MODE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_DIFF_CHANNEL : stm32l4xx_hal_adc_ex.h
  • IS_ADC_DMA_ACCESS_MULTIMODE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_EOC_SELECTION : stm32l4xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32l4xx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32l4xx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32l4xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32l4xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32l4xx_hal_adc_ex.h
  • IS_ADC_MULTIMODE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_OFFSET_NUMBER : stm32l4xx_hal_adc_ex.h
  • IS_ADC_OVERRUN : stm32l4xx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32l4xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32l4xx_hal_adc.h
  • IS_ADC_REGOVERSAMPLING_MODE : stm32l4xx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32l4xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32l4xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32l4xx_hal_adc_ex.h
  • IS_ADC_RESOLUTION : stm32l4xx_hal_adc.h
  • IS_ADC_RESOLUTION_8_6_BITS : stm32l4xx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32l4xx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32l4xx_hal_adc.h
  • IS_ADC_SAMPLING_DELAY : stm32l4xx_hal_adc_ex.h
  • IS_ADC_SCAN_MODE : stm32l4xx_hal_adc.h
  • IS_ADC_SINGLE_DIFFERENTIAL : stm32l4xx_hal_adc_ex.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32l4xx_hal_adc_ex.h
  • IS_CAN_BANKNUMBER : stm32l4xx_hal_can.h
  • IS_CAN_BS1 : stm32l4xx_hal_can.h
  • IS_CAN_BS2 : stm32l4xx_hal_can.h
  • IS_CAN_DLC : stm32l4xx_hal_can.h
  • IS_CAN_EXTID : stm32l4xx_hal_can.h
  • IS_CAN_FIFO : stm32l4xx_hal_can.h
  • IS_CAN_FILTER_FIFO : stm32l4xx_hal_can.h
  • IS_CAN_FILTER_MODE : stm32l4xx_hal_can.h
  • IS_CAN_FILTER_NUMBER : stm32l4xx_hal_can.h
  • IS_CAN_FILTER_SCALE : stm32l4xx_hal_can.h
  • IS_CAN_IDTYPE : stm32l4xx_hal_can.h
  • IS_CAN_MODE : stm32l4xx_hal_can.h
  • IS_CAN_PRESCALER : stm32l4xx_hal_can.h
  • IS_CAN_RTR : stm32l4xx_hal_can.h
  • IS_CAN_SJW : stm32l4xx_hal_can.h
  • IS_CAN_STDID : stm32l4xx_hal_can.h
  • IS_CAN_TRANSMITMAILBOX : stm32l4xx_hal_can.h
  • IS_COMP_BLANKINGSRC_INSTANCE : stm32l4xx_hal_comp.h
  • IS_COMP_BLANKINGSRCE : stm32l4xx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32l4xx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32l4xx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32l4xx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32l4xx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32l4xx_hal_comp.h
  • IS_COMP_POWERMODE : stm32l4xx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32l4xx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32l4xx_hal_comp.h
  • IS_CRC_INPUTDATA_FORMAT : stm32l4xx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32l4xx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32l4xx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32l4xx_hal_crc.h
  • IS_CRYP_AES : stm32l4xx_hal_cryp.h
  • IS_CRYP_ALGOMODE : stm32l4xx_hal_cryp.h
  • IS_CRYP_CHAINMODE : stm32l4xx_hal_cryp.h
  • IS_CRYP_DATATYPE : stm32l4xx_hal_cryp.h
  • IS_CRYP_DMAIN : stm32l4xx_hal_cryp.h
  • IS_CRYP_DMAOUT : stm32l4xx_hal_cryp.h
  • IS_CRYP_GCMCMAC_PHASE : stm32l4xx_hal_cryp.h
  • IS_CRYP_KEYSIZE : stm32l4xx_hal_cryp.h
  • IS_CRYP_WRITE : stm32l4xx_hal_cryp.h
  • IS_DAC_ALIGN : stm32l4xx_hal_dac.h
  • IS_DAC_CHANNEL : stm32l4xx_hal_dac.h
  • IS_DAC_CHIP_CONNECTION : stm32l4xx_hal_dac_ex.h
  • IS_DAC_DATA : stm32l4xx_hal_dac.h
  • IS_DAC_HOLDTIME : stm32l4xx_hal_dac_ex.h
  • IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE : stm32l4xx_hal_dac_ex.h
  • IS_DAC_NEWTRIMMINGVALUE : stm32l4xx_hal_dac_ex.h
  • IS_DAC_OUTPUT_BUFFER_STATE : stm32l4xx_hal_dac.h
  • IS_DAC_REFRESHTIME : stm32l4xx_hal_dac.h
  • IS_DAC_SAMPLEANDHOLD : stm32l4xx_hal_dac_ex.h
  • IS_DAC_SAMPLETIME : stm32l4xx_hal_dac_ex.h
  • IS_DAC_TRIGGER : stm32l4xx_hal_dac_ex.h
  • IS_DAC_TRIMMING : stm32l4xx_hal_dac_ex.h
  • IS_DAC_TRIMMINGVALUE : stm32l4xx_hal_dac_ex.h
  • IS_DEFAULT_INIT_VALUE : stm32l4xx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32l4xx_hal_crc.h
  • IS_DFSDM_BREAK_SIGNALS : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_DATA_PACKING : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_ORDER : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_FILTER_OVS_RATIO : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_INPUT_PINS : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OFFSET : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SCD_THRESHOLD : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CHANNEL_SPI_CLOCK : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_CONTINUOUS_MODE : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_DATA_SOURCE : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_AWD_THRESHOLD : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_EXT_TRIG_EDGE : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INJ_TRIGGER : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_OVS_RATIO : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_REG_TRIGGER : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_FILTER_SINC_ORDER : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_INJECTED_CHANNEL : stm32l4xx_hal_dfsdm.h
  • IS_DFSDM_REGULAR_CHANNEL : stm32l4xx_hal_dfsdm.h
  • IS_DMA_ALL_REQUEST : stm32l4xx_hal_dma.h
  • IS_DMA_BUFFER_SIZE : stm32l4xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32l4xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32l4xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32l4xx_hal_dma.h
  • IS_DMA_MODE : stm32l4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32l4xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32l4xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32l4xx_hal_dma.h
  • IS_FIREWALL_CODE_SEGMENT_ADDRESS : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_CODE_SEGMENT_LENGTH : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_VOLATILEDATA_EXECUTE : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH : stm32l4xx_hal_firewall.h
  • IS_FIREWALL_VOLATILEDATA_SHARE : stm32l4xx_hal_firewall.h
  • IS_FLASH_BANK : stm32l4xx_hal_flash.h
  • IS_FLASH_BANK_EXCLUSIVE : stm32l4xx_hal_flash.h
  • IS_FLASH_LATENCY : stm32l4xx_hal_flash.h
  • IS_FLASH_MAIN_MEM_ADDRESS : stm32l4xx_hal_flash.h
  • IS_FLASH_OTP_ADDRESS : stm32l4xx_hal_flash.h
  • IS_FLASH_PAGE : stm32l4xx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32l4xx_hal_flash.h
  • IS_FLASH_TYPEERASE : stm32l4xx_hal_flash.h
  • IS_FLASH_TYPEPROGRAM : stm32l4xx_hal_flash.h
  • IS_GPIO_AF : stm32l4xx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32l4xx_hal_gpio.h
  • IS_GPIO_PIN : stm32l4xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32l4xx_hal_gpio.h
  • IS_GPIO_PULL : stm32l4xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32l4xx_hal_gpio.h
  • IS_I2C_ADDRESSING_MODE : stm32l4xx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32l4xx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32l4xx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32l4xx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32l4xx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32l4xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32l4xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32l4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32l4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32l4xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32l4xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32l4xx_hal_i2c.h
  • IS_IRDA_BAUDRATE : stm32l4xx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32l4xx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32l4xx_hal_irda.h
  • IS_IRDA_MODE : stm32l4xx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32l4xx_hal_irda.h
  • IS_IRDA_PARITY : stm32l4xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32l4xx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32l4xx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32l4xx_hal_irda.h
  • IS_IRDA_STATE : stm32l4xx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32l4xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32l4xx_hal_irda.h
  • IS_IWDG_PRESCALER : stm32l4xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32l4xx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32l4xx_hal_iwdg.h
  • IS_LCD_BIAS : stm32l4xx_hal_lcd.h
  • IS_LCD_BLINK_FREQUENCY : stm32l4xx_hal_lcd.h
  • IS_LCD_BLINK_MODE : stm32l4xx_hal_lcd.h
  • IS_LCD_CONTRAST : stm32l4xx_hal_lcd.h
  • IS_LCD_DEAD_TIME : stm32l4xx_hal_lcd.h
  • IS_LCD_DIVIDER : stm32l4xx_hal_lcd.h
  • IS_LCD_DUTY : stm32l4xx_hal_lcd.h
  • IS_LCD_HIGH_DRIVE : stm32l4xx_hal_lcd.h
  • IS_LCD_MUX_SEGMENT : stm32l4xx_hal_lcd.h
  • IS_LCD_PRESCALER : stm32l4xx_hal_lcd.h
  • IS_LCD_PULSE_ON_DURATION : stm32l4xx_hal_lcd.h
  • IS_LCD_RAM_REGISTER : stm32l4xx_hal_lcd.h
  • IS_LCD_VOLTAGE_SOURCE : stm32l4xx_hal_lcd.h
  • IS_LL_ADC_COMMON_CLOCK : stm32l4xx_ll_adc.c
  • IS_LL_ADC_DATA_ALIGN : stm32l4xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32l4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32l4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_EXT_EDGE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_LOW_POWER : stm32l4xx_ll_adc.c
  • IS_LL_ADC_MULTI_DMA_TRANSFER : stm32l4xx_ll_adc.c
  • IS_LL_ADC_MULTI_MASTER_SLAVE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_MULTI_MODE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_MULTI_TWOSMP_DELAY : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_OVR_DATA_BEHAVIOR : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32l4xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32l4xx_ll_adc.c
  • IS_LL_ADC_RESOLUTION : stm32l4xx_ll_adc.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32l4xx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32l4xx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32l4xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_BLANKING_SOURCE : stm32l4xx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32l4xx_ll_comp.c
  • IS_LL_COMP_POWER_MODE : stm32l4xx_ll_comp.c
  • IS_LL_DAC_CHANNEL : stm32l4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_BUFFER : stm32l4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_CONNECTION : stm32l4xx_ll_dac.c
  • IS_LL_DAC_OUTPUT_MODE : stm32l4xx_ll_dac.c
  • IS_LL_DAC_TRIGGER_SOURCE : stm32l4xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_CONFIG : stm32l4xx_ll_dac.c
  • IS_LL_DAC_WAVE_AUTO_GENER_MODE : stm32l4xx_ll_dac.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32l4xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32l4xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32l4xx_ll_dma.c
  • IS_LL_DMA_PERIPHREQUEST : stm32l4xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32l4xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32l4xx_ll_exti.c
  • IS_LL_EXTI_LINE_32_63 : stm32l4xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32l4xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32l4xx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32l4xx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32l4xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32l4xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32l4xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32l4xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32l4xx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32l4xx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32l4xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32l4xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32l4xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32l4xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32l4xx_ll_i2c.c
  • IS_LL_LPUART_BAUDRATE : stm32l4xx_ll_lpuart.c
  • IS_LL_LPUART_DATAWIDTH : stm32l4xx_ll_lpuart.c
  • IS_LL_LPUART_DIRECTION : stm32l4xx_ll_lpuart.c
  • IS_LL_LPUART_HWCONTROL : stm32l4xx_ll_lpuart.c
  • IS_LL_LPUART_PARITY : stm32l4xx_ll_lpuart.c
  • IS_LL_LPUART_STOPBITS : stm32l4xx_ll_lpuart.c
  • IS_LL_OPAMP_FUNCTIONAL_MODE : stm32l4xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_INVERTING : stm32l4xx_ll_opamp.c
  • IS_LL_OPAMP_INPUT_NONINVERTING : stm32l4xx_ll_opamp.c
  • IS_LL_OPAMP_POWER_MODE : stm32l4xx_ll_opamp.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_DFSDM_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_LPTIM_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_LPUART_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_RNG_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_SAI_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_SDMMC_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_SWPMI_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_UART_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32l4xx_ll_rcc.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32l4xx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32l4xx_ll_rtc.c
  • IS_LL_SPI_BAUDRATE : stm32l4xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32l4xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32l4xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32l4xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32l4xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32l4xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32l4xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32l4xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32l4xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32l4xx_ll_spi.c
  • IS_LL_SWPMI_BITRATE_VALUE : stm32l4xx_ll_swpmi.c
  • IS_LL_SWPMI_SW_BUFFER_RX : stm32l4xx_ll_swpmi.c
  • IS_LL_SWPMI_SW_BUFFER_TX : stm32l4xx_ll_swpmi.c
  • IS_LL_SWPMI_VOLTAGE_CLASS : stm32l4xx_ll_swpmi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32l4xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32l4xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32l4xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32l4xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32l4xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32l4xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32l4xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32l4xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32l4xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32l4xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32l4xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32l4xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32l4xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32l4xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32l4xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32l4xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32l4xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32l4xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32l4xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32l4xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32l4xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32l4xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32l4xx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLLM_VALUE : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLLN_VALUE : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLLR_VALUE : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_INPUT : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_OUTPUT : stm32l4xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32l4xx_ll_utils.c
  • IS_LPTIM_AUTORELOAD : stm32l4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32l4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32l4xx_hal_lptim.h , stm32l4xx_ll_lptim.c
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32l4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32l4xx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32l4xx_hal_lptim.h , stm32l4xx_ll_lptim.c
  • IS_LPTIM_COMPARE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32l4xx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32l4xx_ll_lptim.c , stm32l4xx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32l4xx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32l4xx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32l4xx_hal_lptim.h
  • IS_LPTIM_WAVEFORM : stm32l4xx_ll_lptim.c
  • IS_LPUART_STOPBITS : stm32l4xx_hal_uart.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32l4xx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32l4xx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32l4xx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32l4xx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32l4xx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32l4xx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32l4xx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32l4xx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32l4xx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32l4xx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32l4xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32l4xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32l4xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32l4xx_hal_cortex.h
  • IS_OB_PCROP_RDP : stm32l4xx_hal_flash.h
  • IS_OB_RDP_LEVEL : stm32l4xx_hal_flash.h
  • IS_OB_USER_BFB2 : stm32l4xx_hal_flash.h
  • IS_OB_USER_BOOT1 : stm32l4xx_hal_flash.h
  • IS_OB_USER_BOR_LEVEL : stm32l4xx_hal_flash.h
  • IS_OB_USER_DUALBANK : stm32l4xx_hal_flash.h
  • IS_OB_USER_IWDG : stm32l4xx_hal_flash.h
  • IS_OB_USER_IWDG_STDBY : stm32l4xx_hal_flash.h
  • IS_OB_USER_IWDG_STOP : stm32l4xx_hal_flash.h
  • IS_OB_USER_SHUTDOWN : stm32l4xx_hal_flash.h
  • IS_OB_USER_SRAM2_PARITY : stm32l4xx_hal_flash.h
  • IS_OB_USER_SRAM2_RST : stm32l4xx_hal_flash.h
  • IS_OB_USER_STANDBY : stm32l4xx_hal_flash.h
  • IS_OB_USER_STOP : stm32l4xx_hal_flash.h
  • IS_OB_USER_TYPE : stm32l4xx_hal_flash.h
  • IS_OB_USER_WWDG : stm32l4xx_hal_flash.h
  • IS_OB_WRPAREA : stm32l4xx_hal_flash.h
  • IS_OPAMP_FACTORYTRIMMING : stm32l4xx_hal_opamp.h
  • IS_OPAMP_FUNCTIONAL_NORMALMODE : stm32l4xx_hal_opamp.h
  • IS_OPAMP_INVERTING_INPUT_PGA : stm32l4xx_hal_opamp.h
  • IS_OPAMP_INVERTING_INPUT_STANDALONE : stm32l4xx_hal_opamp.h
  • IS_OPAMP_NONINVERTING_INPUT : stm32l4xx_hal_opamp.h
  • IS_OPAMP_PGA_GAIN : stm32l4xx_hal_opamp.h
  • IS_OPAMP_POWER_SUPPLY_RANGE : stm32l4xx_hal_opamp.h
  • IS_OPAMP_POWERMODE : stm32l4xx_hal_opamp.h
  • IS_OPAMP_TRIMMING : stm32l4xx_hal_opamp.h
  • IS_OPAMP_TRIMMINGVALUE : stm32l4xx_hal_opamp.h
  • IS_OPTIONBYTE : stm32l4xx_hal_flash.h
  • IS_PWR_BATTERY_CHARGING : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_GPIO : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_GPIO_BIT_NUMBER : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32l4xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32l4xx_hal_pwr.h
  • IS_PWR_PVM_MODE : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_PVM_TYPE : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_REGULATOR : stm32l4xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32l4xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32l4xx_hal_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32l4xx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32l4xx_hal_pwr_ex.h
  • IS_QSPI_ADDRESS_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_ADDRESS_SIZE : stm32l4xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_SIZE : stm32l4xx_hal_qspi.h
  • IS_QSPI_AUTOMATIC_STOP : stm32l4xx_hal_qspi.h
  • IS_QSPI_CLOCK_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_CLOCK_PRESCALER : stm32l4xx_hal_qspi.h
  • IS_QSPI_CS_HIGH_TIME : stm32l4xx_hal_qspi.h
  • IS_QSPI_DATA_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_DDR_HHC : stm32l4xx_hal_qspi.h
  • IS_QSPI_DDR_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_DUMMY_CYCLES : stm32l4xx_hal_qspi.h
  • IS_QSPI_FIFO_THRESHOLD : stm32l4xx_hal_qspi.h
  • IS_QSPI_FLASH_SIZE : stm32l4xx_hal_qspi.h
  • IS_QSPI_FUNCTIONAL_MODE : stm32l4xx_hal_qspi.c
  • IS_QSPI_INSTRUCTION : stm32l4xx_hal_qspi.h
  • IS_QSPI_INSTRUCTION_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_INTERVAL : stm32l4xx_hal_qspi.h
  • IS_QSPI_MATCH_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_SIOO_MODE : stm32l4xx_hal_qspi.h
  • IS_QSPI_SSHIFT : stm32l4xx_hal_qspi.h
  • IS_QSPI_STATUS_BYTES_SIZE : stm32l4xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_ACTIVATION : stm32l4xx_hal_qspi.h
  • IS_QSPI_TIMEOUT_PERIOD : stm32l4xx_hal_qspi.h
  • IS_RCC_ADCCLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32l4xx_hal_rcc.h
  • IS_RCC_DFSDM1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_HCLK : stm32l4xx_hal_rcc.h
  • IS_RCC_HSE : stm32l4xx_hal_rcc.h
  • IS_RCC_HSI : stm32l4xx_hal_rcc.h
  • IS_RCC_HSI_CALIBRATION_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_I2C2CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLK : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_LPTIM2CLK : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_LSCOSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32l4xx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32l4xx_hal_rcc.h
  • IS_RCC_LSI : stm32l4xx_hal_rcc.h
  • IS_RCC_MCO : stm32l4xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32l4xx_hal_rcc.h
  • IS_RCC_MCODIV : stm32l4xx_hal_rcc.h
  • IS_RCC_MSI : stm32l4xx_hal_rcc.h
  • IS_RCC_MSI_CLOCK_RANGE : stm32l4xx_hal_rcc.h
  • IS_RCC_MSI_STANDBY_CLOCK_RANGE : stm32l4xx_hal_rcc.h
  • IS_RCC_MSICALIBRATION_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32l4xx_hal_rcc.h
  • IS_RCC_PCLK : stm32l4xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLM_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLSAI1CLOCKOUT_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLSAI1M_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1N_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1P_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1Q_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1R_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1SOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI2CLOCKOUT_VALUE : stm32l4xx_hal_rcc.h
  • IS_RCC_PLLSAI2M_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI2N_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI2P_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI2R_VALUE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSAI2SOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_PLLSOURCE : stm32l4xx_hal_rcc.h
  • IS_RCC_RNGCLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32l4xx_hal_rcc.h
  • IS_RCC_SAI1CLK : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_SAI2CLK : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_SDMMC1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_STOP_WAKEUPCLOCK : stm32l4xx_hal_rcc.h
  • IS_RCC_SWPMI1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_SYSCLKSOURCE : stm32l4xx_hal_rcc.h
  • IS_RCC_UART4CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_UART5CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_USART2CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_USART3CLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32l4xx_hal_rcc_ex.h
  • IS_RTC_ALARM : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32l4xx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32l4xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32l4xx_hal_rtc.h
  • IS_RTC_BKP : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32l4xx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32l4xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32l4xx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32l4xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32l4xx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32l4xx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32l4xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32l4xx_hal_rtc.h
  • IS_RTC_MONTH : stm32l4xx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_OUTPUT_POL : stm32l4xx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32l4xx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32l4xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32l4xx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32l4xx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32l4xx_hal_rtc.h
  • IS_RTC_TAMPER : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_INTERRUPT : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32l4xx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32l4xx_hal_rtc.h
  • IS_RTC_YEAR : stm32l4xx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32l4xx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32l4xx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32l4xx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32l4xx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32l4xx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32l4xx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32l4xx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32l4xx_hal_smartcard_ex.h
  • IS_SMARTCARD_WORD_LENGTH : stm32l4xx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32l4xx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32l4xx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32l4xx_hal_smbus.h
  • IS_SMBUS_GENERAL_CALL : stm32l4xx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32l4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32l4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32l4xx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32l4xx_hal_smbus.h
  • IS_SMBUS_PEC : stm32l4xx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32l4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32l4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32l4xx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32l4xx_hal_smbus.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32l4xx_hal_spi.h
  • IS_SPI_CPHA : stm32l4xx_hal_spi.h
  • IS_SPI_CPOL : stm32l4xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32l4xx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32l4xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32l4xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32l4xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32l4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32l4xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32l4xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32l4xx_hal_spi.h
  • IS_SPI_MODE : stm32l4xx_hal_spi.h
  • IS_SPI_NSS : stm32l4xx_hal_spi.h
  • IS_SPI_NSSP : stm32l4xx_hal_spi.h
  • IS_SPI_TIMODE : stm32l4xx_hal_spi.h
  • IS_SWPMI_BITRATE_VALUE : stm32l4xx_hal_swpmi.h
  • IS_SWPMI_RX_BUFFERING_MODE : stm32l4xx_hal_swpmi.h
  • IS_SWPMI_TX_BUFFERING_MODE : stm32l4xx_hal_swpmi.h
  • IS_SWPMI_VOLTAGE_CLASS : stm32l4xx_hal_swpmi.h
  • IS_SYSCFG_BREAK_CONFIG : stm32l4xx_hal.h
  • IS_SYSCFG_FASTMODEPLUS : stm32l4xx_hal.h
  • IS_SYSCFG_FPU_INTERRUPT : stm32l4xx_hal.h
  • IS_SYSCFG_SRAM2WRP_PAGE : stm32l4xx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32l4xx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32l4xx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32l4xx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32l4xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32l4xx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32l4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32l4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32l4xx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32l4xx_hal_tim_ex.h
  • IS_TIM_CHANNELS : stm32l4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32l4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32l4xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32l4xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32l4xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32l4xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32l4xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32l4xx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32l4xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32l4xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32l4xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32l4xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32l4xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32l4xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32l4xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32l4xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32l4xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32l4xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_REMAP : stm32l4xx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32l4xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32l4xx_hal_tim.h
  • IS_TIM_TRGO2_SOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32l4xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32l4xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32l4xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32l4xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32l4xx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32l4xx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32l4xx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32l4xx_hal_i2c.h
  • IS_TSC_ACQ_MODE : stm32l4xx_hal_tsc.h
  • IS_TSC_CTPH : stm32l4xx_hal_tsc.h
  • IS_TSC_CTPL : stm32l4xx_hal_tsc.h
  • IS_TSC_GROUP_INDEX : stm32l4xx_hal_tsc.h
  • IS_TSC_IODEF : stm32l4xx_hal_tsc.h
  • IS_TSC_IOMODE : stm32l4xx_hal_tsc.h
  • IS_TSC_MCE_IT : stm32l4xx_hal_tsc.h
  • IS_TSC_MCV : stm32l4xx_hal_tsc.h
  • IS_TSC_PG_PRESC : stm32l4xx_hal_tsc.h
  • IS_TSC_SS : stm32l4xx_hal_tsc.h
  • IS_TSC_SS_PRESC : stm32l4xx_hal_tsc.h
  • IS_TSC_SSD : stm32l4xx_hal_tsc.h
  • IS_TSC_SYNC_POL : stm32l4xx_hal_tsc.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32l4xx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32l4xx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32l4xx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32l4xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32l4xx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32l4xx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32l4xx_hal_uart.h
  • IS_UART_DMA_RX : stm32l4xx_hal_uart.h
  • IS_UART_DMA_TX : stm32l4xx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32l4xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32l4xx_hal_uart.h
  • IS_UART_LIN : stm32l4xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32l4xx_hal_uart.h
  • IS_UART_MODE : stm32l4xx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32l4xx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32l4xx_hal_uart.h
  • IS_UART_OVERRUN : stm32l4xx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32l4xx_hal_uart.h
  • IS_UART_PARITY : stm32l4xx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32l4xx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32l4xx_hal_uart.h
  • IS_UART_STATE : stm32l4xx_hal_uart.h
  • IS_UART_STOPBITS : stm32l4xx_hal_uart.h
  • IS_UART_WAKEUP_SELECTION : stm32l4xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32l4xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32l4xx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32l4xx_hal_usart.h
  • IS_USART_CLOCK : stm32l4xx_hal_usart.h
  • IS_USART_LASTBIT : stm32l4xx_hal_usart.h
  • IS_USART_MODE : stm32l4xx_hal_usart.h
  • IS_USART_OVERSAMPLING : stm32l4xx_hal_usart.h
  • IS_USART_PARITY : stm32l4xx_hal_usart.h
  • IS_USART_PHASE : stm32l4xx_hal_usart.h
  • IS_USART_POLARITY : stm32l4xx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32l4xx_hal_usart.h
  • IS_USART_STOPBITS : stm32l4xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32l4xx_hal_usart_ex.h
  • IS_WWDG_COUNTER : stm32l4xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32l4xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32l4xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32l4xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32l4xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32l4xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32l4xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32l4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32l4xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32l4xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32l4xx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32l4xx_hal_iwdg.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

  • File List
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- l -

  • LCD_BIAS_1_2 : stm32l4xx_hal_lcd.h
  • LCD_BIAS_1_3 : stm32l4xx_hal_lcd.h
  • LCD_BIAS_1_4 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV1024 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV128 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV16 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV256 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV32 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV512 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV64 : stm32l4xx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV8 : stm32l4xx_hal_lcd.h
  • LCD_BLINKMODE_ALLSEG_ALLCOM : stm32l4xx_hal_lcd.h
  • LCD_BLINKMODE_OFF : stm32l4xx_hal_lcd.h
  • LCD_BLINKMODE_SEG0_ALLCOM : stm32l4xx_hal_lcd.h
  • LCD_BLINKMODE_SEG0_COM0 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_0 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_1 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_2 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_3 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_4 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_5 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_6 : stm32l4xx_hal_lcd.h
  • LCD_CONTRASTLEVEL_7 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_0 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_1 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_2 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_3 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_4 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_5 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_6 : stm32l4xx_hal_lcd.h
  • LCD_DEADTIME_7 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_16 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_17 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_18 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_19 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_20 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_21 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_22 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_23 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_24 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_25 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_26 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_27 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_28 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_29 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_30 : stm32l4xx_hal_lcd.h
  • LCD_DIVIDER_31 : stm32l4xx_hal_lcd.h
  • LCD_DUTY_1_2 : stm32l4xx_hal_lcd.h
  • LCD_DUTY_1_3 : stm32l4xx_hal_lcd.h
  • LCD_DUTY_1_4 : stm32l4xx_hal_lcd.h
  • LCD_DUTY_1_8 : stm32l4xx_hal_lcd.h
  • LCD_DUTY_STATIC : stm32l4xx_hal_lcd.h
  • LCD_FLAG_ENS : stm32l4xx_hal_lcd.h
  • LCD_FLAG_FCRSF : stm32l4xx_hal_lcd.h
  • LCD_FLAG_RDY : stm32l4xx_hal_lcd.h
  • LCD_FLAG_SOF : stm32l4xx_hal_lcd.h
  • LCD_FLAG_UDD : stm32l4xx_hal_lcd.h
  • LCD_FLAG_UDR : stm32l4xx_hal_lcd.h
  • LCD_HIGHDRIVE_DISABLE : stm32l4xx_hal_lcd.h
  • LCD_HIGHDRIVE_ENABLE : stm32l4xx_hal_lcd.h
  • LCD_IT_SOF : stm32l4xx_hal_lcd.h
  • LCD_IT_UDD : stm32l4xx_hal_lcd.h
  • LCD_MUXSEGMENT_DISABLE : stm32l4xx_hal_lcd.h
  • LCD_MUXSEGMENT_ENABLE : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_1 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_1024 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_128 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_16 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_16384 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_2 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_2048 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_256 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_32 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_32768 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_4 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_4096 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_512 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_64 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_8 : stm32l4xx_hal_lcd.h
  • LCD_PRESCALER_8192 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_0 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_1 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_2 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_3 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_4 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_5 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_6 : stm32l4xx_hal_lcd.h
  • LCD_PULSEONDURATION_7 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER0 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER1 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER10 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER11 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER12 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER13 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER14 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER15 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER2 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER3 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER4 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER5 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER6 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER7 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER8 : stm32l4xx_hal_lcd.h
  • LCD_RAM_REGISTER9 : stm32l4xx_hal_lcd.h
  • LCD_TIMEOUT_VALUE : stm32l4xx_hal_lcd.c
  • LCD_VOLTAGESOURCE_EXTERNAL : stm32l4xx_hal_lcd.h
  • LCD_VOLTAGESOURCE_INTERNAL : stm32l4xx_hal_lcd.h
  • LL_ADC_AWD1 : stm32l4xx_ll_adc.h
  • LL_ADC_AWD2 : stm32l4xx_ll_adc.h
  • LL_ADC_AWD3 : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32l4xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW : stm32l4xx_ll_adc.h
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_18 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH1_ADC2 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH1_ADC3 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH2_ADC2 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_DAC1CH2_ADC3 : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_VBAT : stm32l4xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV1 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV10 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV12 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV128 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV16 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV2 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV256 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV32 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV4 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV6 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV64 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV8 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2 : stm32l4xx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4 : stm32l4xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_LEFT : stm32l4xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32l4xx_ll_adc.h
  • LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_DELAY_INTERNAL_REGUL_STAB_US : stm32l4xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32l4xx_ll_adc.h
  • LL_ADC_DELAY_VREFINT_STAB_US : stm32l4xx_ll_adc.h
  • LL_ADC_DIFFERENTIAL_ENDED : stm32l4xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32l4xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_ADRDY_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2 : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD2_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3 : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_AWD3_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOC : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOC_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOC_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOS_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOS_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_EOSMP_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOC_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_JQOVF_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_OVR : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_OVR_MST : stm32l4xx_ll_adc.h
  • LL_ADC_FLAG_OVR_SLV : stm32l4xx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32l4xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32l4xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_QUEUE_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_FALLING : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM15_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CC4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CC1 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CC1 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CC3 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CC4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH1 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH3 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM6_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_CC4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32l4xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SW_START : stm32l4xx_ll_adc.h
  • LL_ADC_IT_ADRDY : stm32l4xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32l4xx_ll_adc.h
  • LL_ADC_IT_AWD2 : stm32l4xx_ll_adc.h
  • LL_ADC_IT_AWD3 : stm32l4xx_ll_adc.h
  • LL_ADC_IT_EOC : stm32l4xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32l4xx_ll_adc.h
  • LL_ADC_IT_EOSMP : stm32l4xx_ll_adc.h
  • LL_ADC_IT_JEOC : stm32l4xx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32l4xx_ll_adc.h
  • LL_ADC_IT_JQOVF : stm32l4xx_ll_adc.h
  • LL_ADC_IT_OVR : stm32l4xx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT : stm32l4xx_ll_adc.h
  • LL_ADC_LP_MODE_NONE : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_ALTERN : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_SIMULT : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTERL : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIMULT : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_INDEPENDENT : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_MASTER : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_MASTER_SLAVE : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_EACH_ADC : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_SLAVE : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_1 : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_2 : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_3 : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_4 : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_OFFSET_ENABLE : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_1 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_2 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_3 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_4 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_5 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_6 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_7 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_8 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DATA_SHIFT_NONE : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_GRP_INJECTED : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_RESUMED : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_128 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_16 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_2 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_256 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_32 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_4 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_64 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_RATIO_8 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_REG_CONT : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_REG_DISCONT : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_NONE : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_1 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_2 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_3 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_4 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_5 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_6 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_7 : stm32l4xx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_8 : stm32l4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32l4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32l4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VBAT : stm32l4xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32l4xx_ll_adc.h
  • LL_ADC_ReadReg : stm32l4xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32l4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_LIMITED : stm32l4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32l4xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32l4xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN : stm32l4xx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_PRESERVED : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_FALLING : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM15_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CC1 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CC2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CC3 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CC2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_CC4 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_CH4 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CC4 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM6_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32l4xx_ll_adc.h
  • LL_ADC_REG_TRIG_SW_START : stm32l4xx_ll_adc.h
  • LL_ADC_RESOLUTION_10B : stm32l4xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32l4xx_ll_adc.h
  • LL_ADC_RESOLUTION_6B : stm32l4xx_ll_adc.h
  • LL_ADC_RESOLUTION_8B : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_12CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_247CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_24CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_2CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_47CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_640CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_6CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_92CYCLES_5 : stm32l4xx_ll_adc.h
  • LL_ADC_SINGLE_ENDED : stm32l4xx_ll_adc.h
  • LL_ADC_WriteReg : stm32l4xx_ll_adc.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FLASH : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM1 : stm32l4xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_TSC : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ADC : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_AES : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOA : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOB : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOC : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOD : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOE : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOF : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOG : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOH : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_OTGFS : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_RNG : stm32l4xx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_SRAM2 : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_FMC : stm32l4xx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_QSPI : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CAN1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_DAC1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C3 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LCD : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_OPAMP : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_PWR : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI3 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM5 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM6 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM7 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART4 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_UART5 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_LPTIM2 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_LPUART1 : stm32l4xx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_SWPMI1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_DFSDM1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_FW : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI2 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SDMMC1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SYSCFG : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM15 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM8 : stm32l4xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32l4xx_ll_bus.h
  • LL_COMP_BLANKINGSRC_NONE : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC1 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC4 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5 : stm32l4xx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 : stm32l4xx_ll_comp.h
  • LL_COMP_DELAY_STARTUP_US : stm32l4xx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32l4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32l4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32l4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32l4xx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH1 : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_DAC1_CH2 : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32l4xx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO2 : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_1_2VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_1_4VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_3_4VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_DAC1 : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_DAC2 : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_IO1 : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_IO2 : stm32l4xx_ll_comp.h
  • LL_COMP_INVERTINGINPUT_VREFINT : stm32l4xx_ll_comp.h
  • LL_COMP_NONINVERTINGINPUT_IO1 : stm32l4xx_ll_comp.h
  • LL_COMP_NONINVERTINGINPUT_IO2 : stm32l4xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32l4xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32l4xx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32l4xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32l4xx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32l4xx_ll_comp.h
  • LL_COMP_POWERMODE_HIGHSPEED : stm32l4xx_ll_comp.h
  • LL_COMP_POWERMODE_MEDIUMSPEED : stm32l4xx_ll_comp.h
  • LL_COMP_POWERMODE_ULTRALOWPOWER : stm32l4xx_ll_comp.h
  • LL_COMP_ReadReg : stm32l4xx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32l4xx_ll_comp.h
  • LL_COMP_WINDOWMODE_DISABLE : stm32l4xx_ll_comp.h
  • LL_COMP_WINDOWMODE_ENABLE : stm32l4xx_ll_comp.h
  • LL_COMP_WriteReg : stm32l4xx_ll_comp.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32l4xx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32l4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32l4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32l4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32l4xx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32l4xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32l4xx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32l4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32l4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32l4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32l4xx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32l4xx_ll_crc.h
  • LL_CRC_ReadReg : stm32l4xx_ll_crc.h
  • LL_CRC_WriteReg : stm32l4xx_ll_crc.h
  • LL_DAC_CHANNEL_1 : stm32l4xx_ll_dac.h
  • LL_DAC_CHANNEL_2 : stm32l4xx_ll_dac.h
  • LL_DAC_CONNECT_GPIO : stm32l4xx_ll_dac.h
  • LL_DAC_CONNECT_INTERNAL : stm32l4xx_ll_dac.h
  • LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US : stm32l4xx_ll_dac.h
  • LL_DAC_DELAY_VOLTAGE_SETTLING_US : stm32l4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED : stm32l4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED : stm32l4xx_ll_dac.h
  • LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_BWST1 : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_BWST2 : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_CAL1 : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_CAL2 : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR1 : stm32l4xx_ll_dac.h
  • LL_DAC_FLAG_DMAUDR2 : stm32l4xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE1 : stm32l4xx_ll_dac.h
  • LL_DAC_IT_DMAUDRIE2 : stm32l4xx_ll_dac.h
  • LL_DAC_MODE_CALIBRATION : stm32l4xx_ll_dac.h
  • LL_DAC_MODE_NORMAL_OPERATION : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BIT0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 : stm32l4xx_ll_dac.h
  • LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_DISABLE : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_BUFFER_ENABLE : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_GPIO : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_CONNECT_INTERNAL : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_NORMAL : stm32l4xx_ll_dac.h
  • LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD : stm32l4xx_ll_dac.h
  • LL_DAC_ReadReg : stm32l4xx_ll_dac.h
  • LL_DAC_RESOLUTION_12B : stm32l4xx_ll_dac.h
  • LL_DAC_RESOLUTION_8B : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_1023 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_127 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_15 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_2047 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_255 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_3 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_31 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_4095 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_511 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_63 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIANGLE_AMPLITUDE_7 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_EXTI_LINE9 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM2_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM4_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM5_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM6_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM7_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_EXT_TIM8_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIG_SOFTWARE : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_EXT_IT9 : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_SOFTWARE : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM2_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM4_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM5_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM6_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM7_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_TRIGGER_TIM8_TRGO : stm32l4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NOISE : stm32l4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_NONE : stm32l4xx_ll_dac.h
  • LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE : stm32l4xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_NOISE : stm32l4xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_NONE : stm32l4xx_ll_dac.h
  • LL_DAC_WAVEGENERATION_TRIANGLE : stm32l4xx_ll_dac.h
  • LL_DAC_WriteReg : stm32l4xx_ll_dac.h
  • LL_DBGMCU_APB1_GRP1_CAN_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_LPTIM2_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP : stm32l4xx_ll_system.h
  • LL_DBGMCU_TRACE_ASYNCH : stm32l4xx_ll_system.h
  • LL_DBGMCU_TRACE_NONE : stm32l4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE1 : stm32l4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE2 : stm32l4xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE4 : stm32l4xx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32l4xx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32l4xx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_7 : stm32l4xx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32l4xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32l4xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32l4xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CGIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_GIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_HTIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TCIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32l4xx_ll_dma.h
  • LL_DMA_ISR_TEIF7 : stm32l4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32l4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32l4xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32l4xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32l4xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32l4xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32l4xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32l4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32l4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32l4xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32l4xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32l4xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32l4xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32l4xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32l4xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32l4xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32l4xx_ll_dma.h
  • LL_DMA_ReadReg : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_0 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_1 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_2 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_3 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_4 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_5 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_6 : stm32l4xx_ll_dma.h
  • LL_DMA_REQUEST_7 : stm32l4xx_ll_dma.h
  • LL_DMA_WriteReg : stm32l4xx_ll_dma.h
  • LL_EXTI_LINE_0 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_26 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_27 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_29 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_30 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_31 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_32 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_33 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_34 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_35 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_36 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_37 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_38 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_39 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_ALL_32_63 : stm32l4xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32l4xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32l4xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32l4xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32l4xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32l4xx_ll_exti.h
  • LL_EXTI_TRIGGER_FALLING : stm32l4xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32l4xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32l4xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32l4xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32l4xx_ll_exti.h
  • LL_FLASH_LATENCY_0 : stm32l4xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32l4xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32l4xx_ll_system.h
  • LL_FLASH_LATENCY_3 : stm32l4xx_ll_system.h
  • LL_FLASH_LATENCY_4 : stm32l4xx_ll_system.h
  • LL_GPIO_AF_0 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_11 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_12 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_13 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_14 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_15 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32l4xx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32l4xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32l4xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32l4xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32l4xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32l4xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32l4xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32l4xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32l4xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32l4xx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32l4xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32l4xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_FAST : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_VERY_HIGH : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_HIGH : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_LOW : stm32l4xx_ll_gpio.h
  • LL_GPIO_SPEED_MEDIUM : stm32l4xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32l4xx_ll_gpio.h
  • LL_HANDLER_FAULT_BUS : stm32l4xx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32l4xx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32l4xx_ll_cortex.h
  • LL_I2C_ACK : stm32l4xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32l4xx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32l4xx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32l4xx_ll_i2c.h
  • LL_I2C_DIRECTION_READ : stm32l4xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32l4xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32l4xx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32l4xx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32l4xx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32l4xx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32l4xx_ll_i2c.h
  • LL_I2C_NACK : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32l4xx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32l4xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32l4xx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32l4xx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32l4xx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32l4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32l4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32l4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32l4xx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32l4xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32l4xx_ll_i2c.h
  • LL_IWDG_KEY_ENABLE : stm32l4xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32l4xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32l4xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32l4xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32l4xx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32l4xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32l4xx_ll_iwdg.h
  • LL_LPTIM_CLK_FILTER_2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_4 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_8 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_NONE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_EXTERNAL : stm32l4xx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_INTERNAL : stm32l4xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_EXTERNAL : stm32l4xx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_INTERNAL : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_ARRMIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_ARROKIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_CMPMIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_CMPOKIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_DOWNIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_EXTTRIGIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_IER_UPIE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_GPIO : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_GPIO : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_ARRM : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_ARROK : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPM : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_CMPOK : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_DOWN : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_EXTTRIG : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ISR_UP : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_ONESHOT : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM : stm32l4xx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV1 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV128 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV16 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV32 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV4 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV64 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV8 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_ReadReg : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_4 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_8 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_NONE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP1 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_GPIO : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 : stm32l4xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD : stm32l4xx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE : stm32l4xx_ll_lptim.h
  • LL_LPTIM_WriteReg : stm32l4xx_ll_lptim.h
  • LL_LPUART_ADDRESS_DETECT_4B : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ADDRESS_DETECT_7B : stm32l4xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_NEGATIVE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_POSITIVE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_BITORDER_LSBFIRST : stm32l4xx_ll_lpuart.h
  • LL_LPUART_BITORDER_MSBFIRST : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_CMIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_IDLEIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_PEIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_RXNEIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_TCIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR1_TXEIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR3_CTSIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR3_EIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_CR3_WUFIE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_7B : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_8B : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_9B : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_HIGH : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_LOW : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_NONE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_RX : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX_RX : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_RECEIVE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_TRANSMIT : stm32l4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_CTS : stm32l4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_NONE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS : stm32l4xx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS_CTS : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_CMCF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_CTSCF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_FECF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_IDLECF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_NCF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_ORECF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_PECF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_TCCF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ICR_WUCF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_BUSY : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_CMF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_CTS : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_CTSIF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_FE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_IDLE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_NE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_ORE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_PE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_REACK : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_RWU : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_RXNE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_SBKF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_TC : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_TEACK : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_TXE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ISR_WUF : stm32l4xx_ll_lpuart.h
  • LL_LPUART_PARITY_EVEN : stm32l4xx_ll_lpuart.h
  • LL_LPUART_PARITY_NONE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_PARITY_ODD : stm32l4xx_ll_lpuart.h
  • LL_LPUART_ReadReg : stm32l4xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_INVERTED : stm32l4xx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_STANDARD : stm32l4xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_1 : stm32l4xx_ll_lpuart.h
  • LL_LPUART_STOPBITS_2 : stm32l4xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_INVERTED : stm32l4xx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_STANDARD : stm32l4xx_ll_lpuart.h
  • LL_LPUART_TXRX_STANDARD : stm32l4xx_ll_lpuart.h
  • LL_LPUART_TXRX_SWAPPED : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ADDRESSMARK : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_IDLELINE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_ADDRESS : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_RXNE : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_STARTBIT : stm32l4xx_ll_lpuart.h
  • LL_LPUART_WriteReg : stm32l4xx_ll_lpuart.h
  • LL_MAX_DELAY : stm32l4xx_ll_utils.h
  • LL_MPU_ACCESS_BUFFERABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32l4xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32l4xx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32l4xx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32l4xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128B : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32B : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64B : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32l4xx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32l4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32l4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32l4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32l4xx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32l4xx_ll_cortex.h
  • LL_OPAMP_INPUT_INVERT_CONNECT_NO : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO0 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INPUT_INVERT_IO1 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INPUT_NONINVERT_IO0 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INVERTINGINPUT_CONNECT_NO : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INVERTINGINPUT_IO0 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_INVERTINGINPUT_IO1 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_MODE_CALIBRATION : stm32l4xx_ll_opamp.h
  • LL_OPAMP_MODE_FOLLOWER : stm32l4xx_ll_opamp.h
  • LL_OPAMP_MODE_FUNCTIONAL : stm32l4xx_ll_opamp.h
  • LL_OPAMP_MODE_PGA : stm32l4xx_ll_opamp.h
  • LL_OPAMP_MODE_STANDALONE : stm32l4xx_ll_opamp.h
  • LL_OPAMP_NONINVERTINGINPUT_DAC_CH : stm32l4xx_ll_opamp.h
  • LL_OPAMP_NONINVERTINGINPUT_IO0 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_16 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_2 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_4 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_PGA_GAIN_8 : stm32l4xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_LOWPOWER : stm32l4xx_ll_opamp.h
  • LL_OPAMP_POWERMODE_NORMAL : stm32l4xx_ll_opamp.h
  • LL_OPAMP_POWERSUPPLY_RANGE_HIGH : stm32l4xx_ll_opamp.h
  • LL_OPAMP_POWERSUPPLY_RANGE_LOW : stm32l4xx_ll_opamp.h
  • LL_OPAMP_ReadReg : stm32l4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_FACTORY : stm32l4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_NMOS : stm32l4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_PMOS : stm32l4xx_ll_opamp.h
  • LL_OPAMP_TRIMMING_USER : stm32l4xx_ll_opamp.h
  • LL_OPAMP_WriteReg : stm32l4xx_ll_opamp.h
  • LL_PWR_BATT_CHARG_RESISTOR_5K : stm32l4xx_ll_pwr.h
  • LL_PWR_BATT_CHARGRESISTOR_1_5K : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_A : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_B : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_0 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_1 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_10 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_11 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_12 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_13 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_14 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_15 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_2 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_3 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_4 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_5 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_6 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_7 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_8 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_BIT_9 : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_C : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_D : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_E : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_F : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_G : stm32l4xx_ll_pwr.h
  • LL_PWR_GPIO_H : stm32l4xx_ll_pwr.h
  • LL_PWR_MODE_SHUTDOWN : stm32l4xx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32l4xx_ll_pwr.h
  • LL_PWR_MODE_STOP0 : stm32l4xx_ll_pwr.h
  • LL_PWR_MODE_STOP1 : stm32l4xx_ll_pwr.h
  • LL_PWR_MODE_STOP2 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32l4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_1_62V : stm32l4xx_ll_pwr.h
  • LL_PWR_PVM_VDDA_2_2V : stm32l4xx_ll_pwr.h
  • LL_PWR_PVM_VDDIO2_0_9V : stm32l4xx_ll_pwr.h
  • LL_PWR_PVM_VDDUSB_1_2V : stm32l4xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32l4xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE1 : stm32l4xx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE2 : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CSBF : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF1 : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF2 : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF3 : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF4 : stm32l4xx_ll_pwr.h
  • LL_PWR_SCR_CWUF5 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_SBF : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUF1 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUF2 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUF3 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUF4 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUF5 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR1_WUFI : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_PVDO : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO1 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO2 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO3 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_PVMO4 : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_REGLPF : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_REGLPS : stm32l4xx_ll_pwr.h
  • LL_PWR_SR2_VOSF : stm32l4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32l4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32l4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32l4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN4 : stm32l4xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN5 : stm32l4xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32l4xx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLLSAI2 : stm32l4xx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_CSSC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_HSERDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_HSIRDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_LSECSSC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_LSERDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_LSIRDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_MSIRDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_PLLRDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_PLLSAI1RDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CICR_PLLSAI2RDYC : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_HSERDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_HSIRDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_LSECSSIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_LSERDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_LSIRDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_MSIRDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_PLLRDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_PLLSAI1RDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIER_PLLSAI2RDYIE : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_CSSF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_HSERDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_HSIRDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_LSECSSF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_LSERDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_LSIRDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_MSIRDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_PLLRDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_PLLSAI1RDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CIFR_PLLSAI2RDYF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_BORRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_FWRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_OBLRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32l4xx_ll_rcc.h
  • LL_RCC_DFSDM1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_DFSDM1_CLKSOURCE_PCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_DFSDM1_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C2_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSI : stm32l4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32l4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32l4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32l4xx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_16 : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_0 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_10 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_11 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_3 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_5 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGE_9 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGESEL_RUN : stm32l4xx_ll_rcc.h
  • LL_RCC_MSIRANGESEL_STANDBY : stm32l4xx_ll_rcc.h
  • LL_RCC_MSISRANGE_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSISRANGE_5 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSISRANGE_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_MSISRANGE_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32l4xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_3 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_5 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLM_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_17 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLP_DIV_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLR_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_17 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2P_DIV_17 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2P_DIV_7 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2R_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2R_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2R_DIV_6 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSAI2R_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32l4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32 : stm32l4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32l4xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PIN : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI2 : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI2_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI2_CLKSOURCE_PIN : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI2_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI2_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_SAI2_CLKSOURCE_PLLSAI2 : stm32l4xx_ll_rcc.h
  • LL_RCC_SDMMC1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_SDMMC1_CLKSOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SDMMC1_CLKSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_SDMMC1_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_STOP_WAKEUPCLOCK_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_STOP_WAKEUPCLOCK_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SWPMI1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_SWPMI1_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SWPMI1_CLKSOURCE_PCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32l4xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32l4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_UART4_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_UART5_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_UART5_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_UART5_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_UART5_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_UART5_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_PCLK2 : stm32l4xx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_USART2_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_HSI : stm32l4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_LSE : stm32l4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_PCLK1 : stm32l4xx_ll_rcc.h
  • LL_RCC_USART3_CLKSOURCE_SYSCLK : stm32l4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32l4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_MSI : stm32l4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_NONE : stm32l4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32l4xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLLSAI1 : stm32l4xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32l4xx_ll_rcc.h
  • LL_RNG_CR_IE : stm32l4xx_ll_rng.h
  • LL_RNG_ReadReg : stm32l4xx_ll_rng.h
  • LL_RNG_SR_CECS : stm32l4xx_ll_rng.h
  • LL_RNG_SR_CEIS : stm32l4xx_ll_rng.h
  • LL_RNG_SR_DRDY : stm32l4xx_ll_rng.h
  • LL_RNG_SR_SECS : stm32l4xx_ll_rng.h
  • LL_RNG_SR_SEIS : stm32l4xx_ll_rng.h
  • LL_RNG_WriteReg : stm32l4xx_ll_rng.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32l4xx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32l4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32l4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32l4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32l4xx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_ALL : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_ALL : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32l4xx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR10 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR11 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR12 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR13 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR14 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR15 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR16 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR17 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR18 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR19 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR20 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR21 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR22 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR23 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR24 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR25 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR26 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR27 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR28 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR29 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR30 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR31 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR5 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR6 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR7 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR8 : stm32l4xx_ll_rtc.h
  • LL_RTC_BKP_DR9 : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32l4xx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32l4xx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32l4xx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32l4xx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32l4xx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32l4xx_ll_rtc.h
  • LL_RTC_FORMAT_BCD : stm32l4xx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32l4xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32l4xx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_ALRAF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_ALRAWF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_ALRBF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_ALRBWF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_INITF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_INITS : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_ITSF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_RECALPF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_RSF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_SHPF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_TAMP1F : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_TAMP2F : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_TAMP3F : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_TSF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_TSOVF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_WUTF : stm32l4xx_ll_rtc.h
  • LL_RTC_ISR_WUTWF : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32l4xx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32l4xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32l4xx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32l4xx_ll_rtc.h
  • LL_RTC_ReadReg : stm32l4xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32l4xx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMP1IE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMP2IE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMP3IE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMPIE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_1 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32l4xx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32l4xx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32l4xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32l4xx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32l4xx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32l4xx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32l4xx_ll_rtc.h
  • LL_RTC_WriteReg : stm32l4xx_ll_rtc.h
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32l4xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32l4xx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32l4xx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32l4xx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32l4xx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32l4xx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32l4xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32l4xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32l4xx_ll_spi.h
  • LL_SPI_DMA_PARITY_EVEN : stm32l4xx_ll_spi.h
  • LL_SPI_DMA_PARITY_ODD : stm32l4xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32l4xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32l4xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32l4xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32l4xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32l4xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32l4xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32l4xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32l4xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32l4xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32l4xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32l4xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32l4xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32l4xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32l4xx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32l4xx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32l4xx_ll_spi.h
  • LL_SPI_ReadReg : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_EMPTY : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_HALF_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_QUARTER_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_HALF : stm32l4xx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_QUARTER : stm32l4xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32l4xx_ll_spi.h
  • LL_SPI_SR_BSY : stm32l4xx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32l4xx_ll_spi.h
  • LL_SPI_SR_FRE : stm32l4xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32l4xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32l4xx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32l4xx_ll_spi.h
  • LL_SPI_SR_TXE : stm32l4xx_ll_spi.h
  • LL_SPI_SR_UDR : stm32l4xx_ll_spi.h
  • LL_SPI_TX_FIFO_EMPTY : stm32l4xx_ll_spi.h
  • LL_SPI_TX_FIFO_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_TX_FIFO_HALF_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_TX_FIFO_QUARTER_FULL : stm32l4xx_ll_spi.h
  • LL_SPI_WriteReg : stm32l4xx_ll_spi.h
  • LL_SWPMI_DMA_REG_DATA_RECEIVE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_DMA_REG_DATA_TRANSMIT : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXBERF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXBFF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CRXOVRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CSRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTCF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTXBEF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ICR_CTXUNRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_RIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_RXBERIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_RXBFIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_RXOVRIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_SRIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_TCIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_TIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_TXBEIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_IER_TXUNRIE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_DEACTF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXBERF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXBFF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXNE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_RXOVRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_SRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_SUSP : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_TCF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXBEF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ISR_TXUNRF : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_ReadReg : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_RX_MULTI : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_RX_SINGLE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_TX_MULTI : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_SW_BUFFER_TX_SINGLE : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_VOLTAGE_CLASS_B : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_VOLTAGE_CLASS_C : stm32l4xx_ll_swpmi.h
  • LL_SWPMI_WriteReg : stm32l4xx_ll_swpmi.h
  • LL_SYSCFG_BANKMODE_BANK1 : stm32l4xx_ll_system.h
  • LL_SYSCFG_BANKMODE_BANK2 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE0 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE1 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE10 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE11 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE12 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE13 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE14 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE15 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE2 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE3 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE4 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE5 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE6 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE7 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE8 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_LINE9 : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTA : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTB : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTC : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTD : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTE : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTF : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTG : stm32l4xx_ll_system.h
  • LL_SYSCFG_EXTI_PORTH : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32l4xx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32l4xx_ll_system.h
  • LL_SYSCFG_REMAP_FLASH : stm32l4xx_ll_system.h
  • LL_SYSCFG_REMAP_FMC : stm32l4xx_ll_system.h
  • LL_SYSCFG_REMAP_QUADSPI : stm32l4xx_ll_system.h
  • LL_SYSCFG_REMAP_SRAM : stm32l4xx_ll_system.h
  • LL_SYSCFG_REMAP_SYSTEMFLASH : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE0 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE1 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE10 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE11 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE12 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE13 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE14 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE15 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE16 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE17 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE18 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE19 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE2 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE20 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE21 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE22 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE23 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE24 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE25 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE26 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE27 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE28 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE29 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE3 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE30 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE31 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE4 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE5 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE6 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE7 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE8 : stm32l4xx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE9 : stm32l4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_ECC : stm32l4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_LOCKUP : stm32l4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32l4xx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM2_PARITY : stm32l4xx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32l4xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32l4xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32l4xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32l4xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_HIGH : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_LOW : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP1 : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKIN : stm32l4xx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_DF1BK : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N2 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N4 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_HIGH : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_LOW : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N2 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N4 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN2 : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32l4xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32l4xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32l4xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32l4xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32l4xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH5 : stm32l4xx_ll_tim.h
  • LL_TIM_CHANNEL_CH6 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32l4xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32l4xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_BIE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32l4xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR5 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR6 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR1 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR2 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR3 : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32l4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32l4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32l4xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32l4xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32l4xx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP1 : stm32l4xx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_ETRSOURCE_LEGACY : stm32l4xx_ll_tim.h
  • LL_TIM_GROUPCH5_NONE : stm32l4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC1REFC : stm32l4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC2REFC : stm32l4xx_ll_tim.h
  • LL_TIM_GROUPCH5_OC3REFC : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32l4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32l4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32l4xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32l4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV1 : stm32l4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32l4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32l4xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32l4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32l4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32l4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32l4xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32l4xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_HIGH : stm32l4xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM1 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM2 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM1 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM2 : stm32l4xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32l4xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32l4xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32l4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_ETR : stm32l4xx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_NC : stm32l4xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32l4xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32l4xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32l4xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32l4xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32l4xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32l4xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32l4xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32l4xx_ll_tim.h
  • LL_TIM_ReadReg : stm32l4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32l4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32l4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32l4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32l4xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32l4xx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC5IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_CC6IF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_SBIF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32l4xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_ENCODERMODE_TIM2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_ENCODERMODE_TIM3 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_ENCODERMODE_TIM4 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM15_TI1_RMP_LSE : stm32l4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSE : stm32l4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSI : stm32l4xx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_RTC : stm32l4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_HSE_32 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MCO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MSI : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_NC : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC3_RMP_NC : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_ETR_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_ETR_RMP_LSE : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM3_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC2_RMP_NC : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_ETR_ADC3_RMP_NC : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_COMP2 : stm32l4xx_ll_tim.h
  • LL_TIM_TIM8_TI1_RMP_GPIO : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_CC1F : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_ENABLE : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC1 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC2 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC3 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISINGFALLING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC6 : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_OC6_RISINGFALLING : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_RESET : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO2_UPDATE : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32l4xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32l4xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32l4xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32l4xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32l4xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32l4xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32l4xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32l4xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32l4xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32l4xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32l4xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32l4xx_ll_tim.h
  • LL_TIM_WriteReg : stm32l4xx_ll_tim.h
  • LL_USART_ADDRESS_DETECT_4B : stm32l4xx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32l4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32l4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32l4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32l4xx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32l4xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32l4xx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32l4xx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32l4xx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32l4xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32l4xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_RXNEIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32l4xx_ll_usart.h
  • LL_USART_CR1_TXEIE : stm32l4xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32l4xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32l4xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32l4xx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32l4xx_ll_usart.h
  • LL_USART_DATAWIDTH_7B : stm32l4xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32l4xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32l4xx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32l4xx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32l4xx_ll_usart.h
  • LL_USART_DIRECTION_NONE : stm32l4xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32l4xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32l4xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32l4xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32l4xx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32l4xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32l4xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32l4xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32l4xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32l4xx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_FECF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_NCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_PECF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32l4xx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32l4xx_ll_usart.h
  • LL_USART_IRDA_POWER_LOW : stm32l4xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32l4xx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32l4xx_ll_usart.h
  • LL_USART_ISR_CMF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_CTS : stm32l4xx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_FE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_NE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_ORE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_PE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_REACK : stm32l4xx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_RWU : stm32l4xx_ll_usart.h
  • LL_USART_ISR_RXNE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32l4xx_ll_usart.h
  • LL_USART_ISR_TC : stm32l4xx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32l4xx_ll_usart.h
  • LL_USART_ISR_TXE : stm32l4xx_ll_usart.h
  • LL_USART_ISR_WUF : stm32l4xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32l4xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32l4xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32l4xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32l4xx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32l4xx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32l4xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32l4xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32l4xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32l4xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32l4xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32l4xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32l4xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32l4xx_ll_usart.h
  • LL_USART_ReadReg : stm32l4xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32l4xx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32l4xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32l4xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32l4xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32l4xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32l4xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32l4xx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32l4xx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32l4xx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32l4xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32l4xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32l4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32l4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32l4xx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32l4xx_ll_usart.h
  • LL_USART_WriteReg : stm32l4xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32l4xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_BGA132 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP100 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP144_CSP72 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP48 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_LQFP64 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA100 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFBGA64 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFQFPN32 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_UFQFPN48 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP49 : stm32l4xx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_WLCSP64 : stm32l4xx_ll_utils.h
  • LL_VREFBUF_VOLTAGE_SCALE0 : stm32l4xx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE1 : stm32l4xx_ll_system.h
  • LL_WWDG_CFR_EWI : stm32l4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32l4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32l4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32l4xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32l4xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32l4xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32l4xx_ll_wwdg.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32l4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32l4xx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32l4xx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32l4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32l4xx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32l4xx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1_COMP2 : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP2 : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32l4xx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32l4xx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32l4xx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32l4xx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32l4xx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32l4xx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32l4xx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32l4xx_hal_lptim.h
  • LPTIM_IT_UP : stm32l4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32l4xx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32l4xx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32l4xx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32l4xx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32l4xx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32l4xx_hal_lptim.h
  • LPUART_BRR_MASK : stm32l4xx_ll_lpuart.h
  • LPUART_BRR_MIN_VALUE : stm32l4xx_ll_lpuart.h
  • LPUART_LPUARTDIV_FREQ_MUL : stm32l4xx_ll_lpuart.h
  • LPUART_POSITION_CR1_DEAT : stm32l4xx_ll_lpuart.h
  • LPUART_POSITION_CR1_DEDT : stm32l4xx_ll_lpuart.h
  • LPUART_POSITION_CR2_ADD : stm32l4xx_ll_lpuart.h
  • LSCO_GPIO_PORT : stm32l4xx_hal_rcc_ex.c
  • LSCO_PIN : stm32l4xx_hal_rcc_ex.c
  • LSE_STARTUP_TIMEOUT : stm32l4xx_hal_conf.h
  • LSE_VALUE : stm32l4xx_hal_conf.h , stm32l4xx_ll_rcc.h
  • LSI_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • LSI_VALUE : stm32l4xx_ll_rcc.h , stm32l4xx_hal_conf.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- m -

  • MAX_NBYTE_SIZE : stm32l4xx_hal_i2c.c , stm32l4xx_hal_smbus.c
  • MC_ADDRESS : stm32l4xx_hal_nor.h
  • MCO1_GPIO_PORT : stm32l4xx_hal_rcc.c
  • MCO1_PIN : stm32l4xx_hal_rcc.c
  • MEMRMP_OFFSET : stm32l4xx_hal.c
  • MPU_ACCESS_BUFFERABLE : stm32l4xx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32l4xx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32l4xx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32l4xx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32l4xx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32l4xx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32l4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32l4xx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32l4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32l4xx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32l4xx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32l4xx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32l4xx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32l4xx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32l4xx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32l4xx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32l4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32l4xx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32l4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32l4xx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32l4xx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32l4xx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32l4xx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32l4xx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32l4xx_hal_cortex.h
  • MSI_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c
  • MSI_VALUE : stm32l4xx_hal_conf.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- n -

  • NAND_BUSY : stm32l4xx_hal_nand.h
  • NAND_CMD_AREA_A : stm32l4xx_hal_nand.h
  • NAND_CMD_AREA_B : stm32l4xx_hal_nand.h
  • NAND_CMD_AREA_C : stm32l4xx_hal_nand.h
  • NAND_CMD_AREA_TRUE1 : stm32l4xx_hal_nand.h
  • NAND_CMD_ERASE0 : stm32l4xx_hal_nand.h
  • NAND_CMD_ERASE1 : stm32l4xx_hal_nand.h
  • NAND_CMD_LOCK_STATUS : stm32l4xx_hal_nand.h
  • NAND_CMD_READID : stm32l4xx_hal_nand.h
  • NAND_CMD_RESET : stm32l4xx_hal_nand.h
  • NAND_CMD_STATUS : stm32l4xx_hal_nand.h
  • NAND_CMD_WRITE0 : stm32l4xx_hal_nand.h
  • NAND_CMD_WRITE_TRUE1 : stm32l4xx_hal_nand.h
  • NAND_DEVICE : stm32l4xx_hal_nand.h
  • NAND_ERROR : stm32l4xx_hal_nand.h
  • NAND_INVALID_ADDRESS : stm32l4xx_hal_nand.h
  • NAND_READY : stm32l4xx_hal_nand.h
  • NAND_TIMEOUT_ERROR : stm32l4xx_hal_nand.h
  • NAND_VALID_ADDRESS : stm32l4xx_hal_nand.h
  • NAND_WRITE_TIMEOUT : stm32l4xx_hal_nand.h
  • NOR_ADDR_SHIFT : stm32l4xx_hal_nor.h
  • NOR_CMD_ADDRESS_FIFTH : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_FIRST_CFI : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_FOURTH : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_SECOND : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_SIXTH : stm32l4xx_hal_nor.c
  • NOR_CMD_ADDRESS_THIRD : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_AUTO_SELECT : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_BLOCK_ERASE : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_CFI : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_CHIP_ERASE : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_FIRST : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_PROGRAM : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_READ_RESET : stm32l4xx_hal_nor.c
  • NOR_CMD_DATA_SECOND : stm32l4xx_hal_nor.c
  • NOR_MASK_STATUS_DQ5 : stm32l4xx_hal_nor.c
  • NOR_MASK_STATUS_DQ6 : stm32l4xx_hal_nor.c
  • NOR_MEMORY_16B : stm32l4xx_hal_nor.h
  • NOR_MEMORY_8B : stm32l4xx_hal_nor.h
  • NOR_MEMORY_ADRESS1 : stm32l4xx_hal_nor.h
  • NOR_MEMORY_ADRESS2 : stm32l4xx_hal_nor.h
  • NOR_MEMORY_ADRESS3 : stm32l4xx_hal_nor.h
  • NOR_MEMORY_ADRESS4 : stm32l4xx_hal_nor.h
  • NOR_WRITE : stm32l4xx_hal_nor.h
  • NVIC_PRIORITYGROUP_0 : stm32l4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32l4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32l4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32l4xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32l4xx_hal_cortex.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- o -

  • OB_BFB2_DISABLE : stm32l4xx_hal_flash.h
  • OB_BFB2_ENABLE : stm32l4xx_hal_flash.h
  • OB_BOOT1_SRAM : stm32l4xx_hal_flash.h
  • OB_BOOT1_SYSTEM : stm32l4xx_hal_flash.h
  • OB_BOR_LEVEL_0 : stm32l4xx_hal_flash.h
  • OB_BOR_LEVEL_1 : stm32l4xx_hal_flash.h
  • OB_BOR_LEVEL_2 : stm32l4xx_hal_flash.h
  • OB_BOR_LEVEL_3 : stm32l4xx_hal_flash.h
  • OB_BOR_LEVEL_4 : stm32l4xx_hal_flash.h
  • OB_DUALBANK_DUAL : stm32l4xx_hal_flash.h
  • OB_DUALBANK_SINGLE : stm32l4xx_hal_flash.h
  • OB_IWDG_HW : stm32l4xx_hal_flash.h
  • OB_IWDG_STDBY_FREEZE : stm32l4xx_hal_flash.h
  • OB_IWDG_STDBY_RUN : stm32l4xx_hal_flash.h
  • OB_IWDG_STOP_FREEZE : stm32l4xx_hal_flash.h
  • OB_IWDG_STOP_RUN : stm32l4xx_hal_flash.h
  • OB_IWDG_SW : stm32l4xx_hal_flash.h
  • OB_PCROP_RDP_ERASE : stm32l4xx_hal_flash.h
  • OB_PCROP_RDP_NOT_ERASE : stm32l4xx_hal_flash.h
  • OB_RDP_LEVEL_0 : stm32l4xx_hal_flash.h
  • OB_RDP_LEVEL_1 : stm32l4xx_hal_flash.h
  • OB_RDP_LEVEL_2 : stm32l4xx_hal_flash.h
  • OB_SHUTDOWN_NORST : stm32l4xx_hal_flash.h
  • OB_SHUTDOWN_RST : stm32l4xx_hal_flash.h
  • OB_SRAM2_PARITY_DISABLE : stm32l4xx_hal_flash.h
  • OB_SRAM2_PARITY_ENABLE : stm32l4xx_hal_flash.h
  • OB_SRAM2_RST_ERASE : stm32l4xx_hal_flash.h
  • OB_SRAM2_RST_NOT_ERASE : stm32l4xx_hal_flash.h
  • OB_STANDBY_NORST : stm32l4xx_hal_flash.h
  • OB_STANDBY_RST : stm32l4xx_hal_flash.h
  • OB_STOP_NORST : stm32l4xx_hal_flash.h
  • OB_STOP_RST : stm32l4xx_hal_flash.h
  • OB_USER_BFB2 : stm32l4xx_hal_flash.h
  • OB_USER_BOR_LEV : stm32l4xx_hal_flash.h
  • OB_USER_DUALBANK : stm32l4xx_hal_flash.h
  • OB_USER_IWDG_STDBY : stm32l4xx_hal_flash.h
  • OB_USER_IWDG_STOP : stm32l4xx_hal_flash.h
  • OB_USER_IWDG_SW : stm32l4xx_hal_flash.h
  • OB_USER_nBOOT1 : stm32l4xx_hal_flash.h
  • OB_USER_nRST_SHDW : stm32l4xx_hal_flash.h
  • OB_USER_nRST_STDBY : stm32l4xx_hal_flash.h
  • OB_USER_nRST_STOP : stm32l4xx_hal_flash.h
  • OB_USER_SRAM2_PE : stm32l4xx_hal_flash.h
  • OB_USER_SRAM2_RST : stm32l4xx_hal_flash.h
  • OB_USER_WWDG_SW : stm32l4xx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAA : stm32l4xx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAB : stm32l4xx_hal_flash.h
  • OB_WRPAREA_BANK2_AREAA : stm32l4xx_hal_flash.h
  • OB_WRPAREA_BANK2_AREAB : stm32l4xx_hal_flash.h
  • OB_WWDG_HW : stm32l4xx_hal_flash.h
  • OB_WWDG_SW : stm32l4xx_hal_flash.h
  • OPAMP_CSR_INIT_MASK_FOLLOWER : stm32l4xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_PGA : stm32l4xx_hal_opamp.c
  • OPAMP_CSR_INIT_MASK_STANDALONE : stm32l4xx_hal_opamp.c
  • OPAMP_CSR_RESET_BITS : stm32l4xx_hal_opamp.c
  • OPAMP_CSR_RESET_VALUE : stm32l4xx_hal_opamp.c
  • OPAMP_FACTORYTRIMMING_DUMMY : stm32l4xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_N : stm32l4xx_hal_opamp.h
  • OPAMP_FACTORYTRIMMING_P : stm32l4xx_hal_opamp.h
  • OPAMP_FOLLOWER_MODE : stm32l4xx_hal_opamp.h
  • OPAMP_INPUT_NONINVERTING : stm32l4xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_CONNECT_NO : stm32l4xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO0 : stm32l4xx_hal_opamp.h
  • OPAMP_INVERTINGINPUT_IO1 : stm32l4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_DAC_CH : stm32l4xx_hal_opamp.h
  • OPAMP_NONINVERTINGINPUT_IO0 : stm32l4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_16 : stm32l4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_2 : stm32l4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_4 : stm32l4xx_hal_opamp.h
  • OPAMP_PGA_GAIN_8 : stm32l4xx_hal_opamp.h
  • OPAMP_PGA_MODE : stm32l4xx_hal_opamp.h
  • OPAMP_POWERMODE_CSR_BIT_MASK : stm32l4xx_ll_opamp.h
  • OPAMP_POWERMODE_LOWPOWER : stm32l4xx_hal_opamp.h
  • OPAMP_POWERMODE_LPOTR_REGOFFSET : stm32l4xx_ll_opamp.h
  • OPAMP_POWERMODE_NORMAL : stm32l4xx_hal_opamp.h
  • OPAMP_POWERMODE_OTR_REGOFFSET : stm32l4xx_ll_opamp.h
  • OPAMP_POWERMODE_OTR_REGOFFSET_MASK : stm32l4xx_ll_opamp.h
  • OPAMP_POWERSUPPLY_HIGH : stm32l4xx_hal_opamp.h
  • OPAMP_POWERSUPPLY_LOW : stm32l4xx_hal_opamp.h
  • OPAMP_STANDALONE_MODE : stm32l4xx_hal_opamp.h
  • OPAMP_TRIMMING_DELAY : stm32l4xx_hal_opamp.h
  • OPAMP_TRIMMING_FACTORY : stm32l4xx_hal_opamp.h
  • OPAMP_TRIMMING_SELECT_MASK : stm32l4xx_ll_opamp.h
  • OPAMP_TRIMMING_USER : stm32l4xx_hal_opamp.h
  • OPAMP_TRIMMING_VALUE_MASK : stm32l4xx_ll_opamp.h
  • OPTIONBYTE_PCROP : stm32l4xx_hal_flash.h
  • OPTIONBYTE_RDP : stm32l4xx_hal_flash.h
  • OPTIONBYTE_USER : stm32l4xx_hal_flash.h
  • OPTIONBYTE_WRP : stm32l4xx_hal_flash.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- p -

  • PACKAGE_BASE_ADDRESS : stm32l4xx_ll_utils.h
  • PCD_MAX : stm32l4xx_hal_pcd.c
  • PCD_MIN : stm32l4xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32l4xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32l4xx_hal_pcd.h
  • PLL_TIMEOUT_VALUE : stm32l4xx_hal_rcc.c , stm32l4xx_hal_rcc_ex.c
  • PLLSAI1_TIMEOUT_VALUE : stm32l4xx_hal_rcc_ex.c
  • PLLSAI2_TIMEOUT_VALUE : stm32l4xx_hal_rcc_ex.c
  • PREFETCH_ENABLE : stm32l4xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32l4xx_hal_pwr.c
  • PVD_MODE_EVT : stm32l4xx_hal_pwr.c
  • PVD_MODE_IT : stm32l4xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32l4xx_hal_pwr.c
  • PVM_FALLING_EDGE : stm32l4xx_hal_pwr_ex.c
  • PVM_MODE_EVT : stm32l4xx_hal_pwr_ex.c
  • PVM_MODE_IT : stm32l4xx_hal_pwr_ex.c
  • PVM_RISING_EDGE : stm32l4xx_hal_pwr_ex.c
  • PWR_BATTERY_CHARGING_DISABLE : stm32l4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_ENABLE : stm32l4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32l4xx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32l4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVD : stm32l4xx_hal_pwr.h
  • PWR_EVENT_LINE_PVM1 : stm32l4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM2 : stm32l4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM3 : stm32l4xx_hal_pwr_ex.h
  • PWR_EVENT_LINE_PVM4 : stm32l4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVD : stm32l4xx_hal_pwr.h
  • PWR_EXTI_LINE_PVM1 : stm32l4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM2 : stm32l4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM3 : stm32l4xx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM4 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_PVDO : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO1 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO2 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO3 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_PVMO4 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_REGLPF : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_REGLPS : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_SB : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_SETTING_DELAY_US : stm32l4xx_hal_pwr_ex.c
  • PWR_FLAG_VOSF : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WU : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF1 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF2 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF3 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF4 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUF5 : stm32l4xx_hal_pwr_ex.h
  • PWR_FLAG_WUFI : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_A : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_B : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_0 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_1 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_10 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_11 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_12 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_13 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_14 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_15 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_2 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_3 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_4 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_5 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_6 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_7 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_8 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_BIT_9 : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_C : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_D : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_E : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_F : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_G : stm32l4xx_hal_pwr_ex.h
  • PWR_GPIO_H : stm32l4xx_hal_pwr_ex.h
  • PWR_LOWPOWERREGULATOR_ON : stm32l4xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32l4xx_hal_pwr.h
  • PWR_PORTH_AVAILABLE_PINS : stm32l4xx_hal_pwr_ex.c
  • PWR_PVD_MODE_EVENT_FALLING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32l4xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32l4xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32l4xx_hal_pwr.h
  • PWR_PVM_1 : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_2 : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_3 : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_4 : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_FALLING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING_FALLING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_FALLING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING_FALLING : stm32l4xx_hal_pwr_ex.h
  • PWR_PVM_MODE_NORMAL : stm32l4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32l4xx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32l4xx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32l4xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32l4xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32l4xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32l4xx_hal_pwr.h
  • PWR_WAKEUP_PIN1 : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32l4xx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32l4xx_hal_pwr_ex.h
  • PWR_WUP_POLARITY_SHIFT : stm32l4xx_hal_pwr_ex.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- q -

  • QSPI_ADDRESS_16_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_1_LINE : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_24_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_2_LINES : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_32_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_4_LINES : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_8_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ADDRESS_NONE : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_16_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_1_LINE : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_24_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_2_LINES : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_32_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_4_LINES : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_8_BITS : stm32l4xx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_NONE : stm32l4xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_DISABLE : stm32l4xx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_ENABLE : stm32l4xx_hal_qspi.h
  • QSPI_CLOCK_MODE_0 : stm32l4xx_hal_qspi.h
  • QSPI_CLOCK_MODE_3 : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_1_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_2_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_3_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_4_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_5_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_6_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_7_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_8_CYCLE : stm32l4xx_hal_qspi.h
  • QSPI_DATA_1_LINE : stm32l4xx_hal_qspi.h
  • QSPI_DATA_2_LINES : stm32l4xx_hal_qspi.h
  • QSPI_DATA_4_LINES : stm32l4xx_hal_qspi.h
  • QSPI_DATA_NONE : stm32l4xx_hal_qspi.h
  • QSPI_DDR_HHC_ANALOG_DELAY : stm32l4xx_hal_qspi.h
  • QSPI_DDR_MODE_DISABLE : stm32l4xx_hal_qspi.h
  • QSPI_DDR_MODE_ENABLE : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_BUSY : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_FT : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_SM : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_TC : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_TE : stm32l4xx_hal_qspi.h
  • QSPI_FLAG_TO : stm32l4xx_hal_qspi.h
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING : stm32l4xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ : stm32l4xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE : stm32l4xx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED : stm32l4xx_hal_qspi.c
  • QSPI_INSTRUCTION_1_LINE : stm32l4xx_hal_qspi.h
  • QSPI_INSTRUCTION_2_LINES : stm32l4xx_hal_qspi.h
  • QSPI_INSTRUCTION_4_LINES : stm32l4xx_hal_qspi.h
  • QSPI_INSTRUCTION_NONE : stm32l4xx_hal_qspi.h
  • QSPI_IT_FT : stm32l4xx_hal_qspi.h
  • QSPI_IT_SM : stm32l4xx_hal_qspi.h
  • QSPI_IT_TC : stm32l4xx_hal_qspi.h
  • QSPI_IT_TE : stm32l4xx_hal_qspi.h
  • QSPI_IT_TO : stm32l4xx_hal_qspi.h
  • QSPI_MATCH_MODE_AND : stm32l4xx_hal_qspi.h
  • QSPI_MATCH_MODE_OR : stm32l4xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_HALFCYCLE : stm32l4xx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_NONE : stm32l4xx_hal_qspi.h
  • QSPI_SIOO_INST_EVERY_CMD : stm32l4xx_hal_qspi.h
  • QSPI_SIOO_INST_ONLY_FIRST_CMD : stm32l4xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_DISABLE : stm32l4xx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_ENABLE : stm32l4xx_hal_qspi.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- r -

  • RCC_ADCCLKSOURCE_NONE : stm32l4xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLLSAI2 : stm32l4xx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_HCLK : stm32l4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32l4xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32l4xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32l4xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32l4xx_hal_rcc.h
  • RCC_DFSDM1CLKSOURCE_PCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_DFSDM1CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_EXTI_LINE_LSECSS : stm32l4xx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_FWRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_LSECSSD : stm32l4xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32l4xx_hal_rcc.h
  • RCC_FLAG_MSIRDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_OBLRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_PLLSAI1RDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_PLLSAI2RDY : stm32l4xx_hal_rcc.h
  • RCC_FLAG_RMVF : stm32l4xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32l4xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32l4xx_hal_rcc.h
  • RCC_HCLK_DIV1 : stm32l4xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32l4xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32l4xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32l4xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32l4xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32l4xx_hal_rcc.h
  • RCC_HSE_OFF : stm32l4xx_hal_rcc.h
  • RCC_HSE_ON : stm32l4xx_hal_rcc.h
  • RCC_HSI48_OFF : stm32l4xx_hal_rcc.h
  • RCC_HSI_OFF : stm32l4xx_hal_rcc.h
  • RCC_HSI_ON : stm32l4xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32l4xx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C2CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_IT_CSS : stm32l4xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32l4xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32l4xx_hal_rcc.h
  • RCC_IT_LSECSS : stm32l4xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32l4xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32l4xx_hal_rcc.h
  • RCC_IT_MSIRDY : stm32l4xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32l4xx_hal_rcc.h
  • RCC_IT_PLLSAI1RDY : stm32l4xx_hal_rcc.h
  • RCC_IT_PLLSAI2RDY : stm32l4xx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSI : stm32l4xx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32l4xx_hal_rcc.h
  • RCC_LSE_OFF : stm32l4xx_hal_rcc.h
  • RCC_LSE_ON : stm32l4xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32l4xx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32l4xx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32l4xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32l4xx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32l4xx_hal_rcc.h
  • RCC_LSI_OFF : stm32l4xx_hal_rcc.h
  • RCC_LSI_ON : stm32l4xx_hal_rcc.h
  • RCC_MCO : stm32l4xx_hal_rcc.h
  • RCC_MCO1 : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_LSI : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_MSI : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32l4xx_hal_rcc.h
  • RCC_MCO1SOURCE_SYSCLK : stm32l4xx_hal_rcc.h
  • RCC_MCODIV_1 : stm32l4xx_hal_rcc.h
  • RCC_MCODIV_16 : stm32l4xx_hal_rcc.h
  • RCC_MCODIV_2 : stm32l4xx_hal_rcc.h
  • RCC_MCODIV_4 : stm32l4xx_hal_rcc.h
  • RCC_MCODIV_8 : stm32l4xx_hal_rcc.h
  • RCC_MSI_OFF : stm32l4xx_hal_rcc.h
  • RCC_MSI_ON : stm32l4xx_hal_rcc.h
  • RCC_MSICALIBRATION_DEFAULT : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_0 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_1 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_10 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_11 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_2 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_3 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_4 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_5 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_6 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_7 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_8 : stm32l4xx_hal_rcc.h
  • RCC_MSIRANGE_9 : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_MSI : stm32l4xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32l4xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_DFSDM1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C2 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM2 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI2 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SDMMC1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SWPMI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART4 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_UART5 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART2 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART3 : stm32l4xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32l4xx_hal_rcc_ex.h
  • RCC_PLL_48M1CLK : stm32l4xx_hal_rcc.h
  • RCC_PLL_NONE : stm32l4xx_hal_rcc.h
  • RCC_PLL_OFF : stm32l4xx_hal_rcc.h
  • RCC_PLL_ON : stm32l4xx_hal_rcc.h
  • RCC_PLL_OSCSOURCE_CONFIG : stm32l4xx_hal_rcc.c
  • RCC_PLL_SAI3CLK : stm32l4xx_hal_rcc.h
  • RCC_PLL_SYSCLK : stm32l4xx_hal_rcc.h
  • RCC_PLLP_DIV17 : stm32l4xx_hal_rcc.h
  • RCC_PLLP_DIV7 : stm32l4xx_hal_rcc.h
  • RCC_PLLQ_DIV2 : stm32l4xx_hal_rcc.h
  • RCC_PLLQ_DIV4 : stm32l4xx_hal_rcc.h
  • RCC_PLLQ_DIV6 : stm32l4xx_hal_rcc.h
  • RCC_PLLQ_DIV8 : stm32l4xx_hal_rcc.h
  • RCC_PLLR_DIV2 : stm32l4xx_hal_rcc.h
  • RCC_PLLR_DIV4 : stm32l4xx_hal_rcc.h
  • RCC_PLLR_DIV6 : stm32l4xx_hal_rcc.h
  • RCC_PLLR_DIV8 : stm32l4xx_hal_rcc.h
  • RCC_PLLSAI1_48M2CLK : stm32l4xx_hal_rcc.h
  • RCC_PLLSAI1_ADC1CLK : stm32l4xx_hal_rcc.h
  • RCC_PLLSAI1_SAI1CLK : stm32l4xx_hal_rcc.h
  • RCC_PLLSAI2_ADC2CLK : stm32l4xx_hal_rcc.h
  • RCC_PLLSAI2_SAI2CLK : stm32l4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32l4xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32l4xx_hal_rcc.h
  • RCC_PLLSOURCE_MSI : stm32l4xx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32l4xx_hal_rcc.h
  • RCC_POSITION_HPRE : stm32l4xx_ll_rcc.h
  • RCC_POSITION_HSICAL : stm32l4xx_ll_rcc.h
  • RCC_POSITION_HSITRIM : stm32l4xx_ll_rcc.h
  • RCC_POSITION_MSICAL : stm32l4xx_ll_rcc.h
  • RCC_POSITION_MSITRIM : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLM : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLN : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLP : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLQ : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLR : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI1N : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI1P : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI1Q : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI1R : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI2N : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI2P : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PLLSAI2R : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PPRE1 : stm32l4xx_ll_rcc.h
  • RCC_POSITION_PPRE2 : stm32l4xx_ll_rcc.h
  • RCC_RNGCLKSOURCE_MSI : stm32l4xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_NONE : stm32l4xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32l4xx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32l4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32l4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32l4xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NO_CLK : stm32l4xx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_PIN : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLLSAI2 : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PIN : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLL : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_SAI2CLKSOURCE_PLLSAI2 : stm32l4xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_MSI : stm32l4xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_NONE : stm32l4xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_PLL : stm32l4xx_hal_rcc_ex.h
  • RCC_SDMMC1CLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RCC_STOP_WAKEUPCLOCK_HSI : stm32l4xx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_MSI : stm32l4xx_hal_rcc.h
  • RCC_SWPMI1CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_SWPMI1CLKSOURCE_PCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_SYSCLK_DIV1 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_MSI : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_MSI : stm32l4xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32l4xx_hal_rcc.h
  • RCC_UART4CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_UART4CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_UART5CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK2 : stm32l4xx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_USART2CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_HSI : stm32l4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_LSE : stm32l4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_PCLK1 : stm32l4xx_hal_rcc_ex.h
  • RCC_USART3CLKSOURCE_SYSCLK : stm32l4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_MSI : stm32l4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_NONE : stm32l4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32l4xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLLSAI1 : stm32l4xx_hal_rcc_ex.h
  • RISING_EDGE : stm32l4xx_hal_gpio.c
  • RNG_FLAG_CECS : stm32l4xx_hal_rng.h
  • RNG_FLAG_DRDY : stm32l4xx_hal_rng.h
  • RNG_FLAG_SECS : stm32l4xx_hal_rng.h
  • RNG_IT_CEI : stm32l4xx_hal_rng.h
  • RNG_IT_DRDY : stm32l4xx_hal_rng.h
  • RNG_IT_SEI : stm32l4xx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32l4xx_hal_rng.c
  • RTC_ALARM_A : stm32l4xx_hal_rtc.h
  • RTC_ALARM_B : stm32l4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32l4xx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32l4xx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32l4xx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32l4xx_hal_rtc.h
  • RTC_ALL_TAMPER_INTERRUPT : stm32l4xx_hal_rtc_ex.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32l4xx_ll_rtc.c
  • RTC_BKP_DR0 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR20 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR21 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR22 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR23 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR24 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR25 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR26 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR27 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR28 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR29 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR30 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR31 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32l4xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32l4xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_1HZ : stm32l4xx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32l4xx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32l4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32l4xx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32l4xx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32l4xx_hal_rtc.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32l4xx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32l4xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32l4xx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_INITF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_INITS : stm32l4xx_hal_rtc.h
  • RTC_FLAG_ITSF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32l4xx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32l4xx_hal_rtc.h
  • RTC_FLAG_TAMP3F : stm32l4xx_hal_rtc.h
  • RTC_FLAG_TSF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32l4xx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32l4xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32l4xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32l4xx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32l4xx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32l4xx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32l4xx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32l4xx_hal_rtc.h
  • RTC_INIT_MASK : stm32l4xx_ll_rtc.h , stm32l4xx_hal_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32l4xx_ll_rtc.c
  • RTC_IT_ALRA : stm32l4xx_hal_rtc.h
  • RTC_IT_ALRB : stm32l4xx_hal_rtc.h
  • RTC_IT_TAMP : stm32l4xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32l4xx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32l4xx_hal_rtc.h
  • RTC_IT_TAMP3 : stm32l4xx_hal_rtc.h
  • RTC_IT_TS : stm32l4xx_hal_rtc.h
  • RTC_IT_WUT : stm32l4xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32l4xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32l4xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32l4xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32l4xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32l4xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32l4xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32l4xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32l4xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32l4xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32l4xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32l4xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32l4xx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32l4xx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32l4xx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32l4xx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32l4xx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32l4xx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32l4xx_hal_rtc_ex.h
  • RTC_OUTPUT_ALARMB : stm32l4xx_hal_rtc_ex.h
  • RTC_OUTPUT_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32l4xx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32l4xx_hal_rtc_ex.h
  • RTC_POSITION_ALMA_DT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_DU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_HT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_HU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_MASKSS : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_MT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_MU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_ST : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMA_SU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_DT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_DU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_HT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_HU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_MASKSS : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_MT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_MU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_ST : stm32l4xx_ll_rtc.h
  • RTC_POSITION_ALMB_SU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_DT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_DU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_MT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_MU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_WDU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_YT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_DR_YU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_PRER_PREDIV_A : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_HT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_HU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_MT : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_MU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_ST : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TR_SU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TS_HU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TS_MNU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TS_MU : stm32l4xx_ll_rtc.h
  • RTC_POSITION_TS_WDU : stm32l4xx_ll_rtc.h
  • RTC_RSF_MASK : stm32l4xx_ll_rtc.h , stm32l4xx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32l4xx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32l4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32l4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32l4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32l4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32l4xx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32l4xx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32l4xx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32l4xx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32l4xx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32l4xx_ll_rtc.c
  • RTC_TAMPCR_MASK : stm32l4xx_hal_rtc_ex.c
  • RTC_TAMPER1_INTERRUPT : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER2_INTERRUPT : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER3_INTERRUPT : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_1 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32l4xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32l4xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32l4xx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32l4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32l4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32l4xx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32l4xx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32l4xx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32l4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32l4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32l4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32l4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32l4xx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32l4xx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32l4xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32l4xx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32l4xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32l4xx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32l4xx_ll_rtc.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- s -

  • SAI_AC97_PROTOCOL : stm32l4xx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32l4xx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32l4xx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32l4xx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32l4xx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32l4xx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_10 : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_16 : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_20 : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_24 : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_32 : stm32l4xx_hal_sai.h
  • SAI_DATASIZE_8 : stm32l4xx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32l4xx_hal_sai.c
  • SAI_FIFO_SIZE : stm32l4xx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32l4xx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32l4xx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32l4xx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32l4xx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32l4xx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32l4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32l4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32l4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32l4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32l4xx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32l4xx_hal_sai.h
  • SAI_FIRSTBIT_LSB : stm32l4xx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32l4xx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32l4xx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32l4xx_hal_sai.h
  • SAI_FLAG_FREQ : stm32l4xx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32l4xx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32l4xx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32l4xx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32l4xx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32l4xx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32l4xx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32l4xx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32l4xx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32l4xx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32l4xx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32l4xx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32l4xx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32l4xx_hal_sai.h
  • SAI_I2S_STANDARD : stm32l4xx_hal_sai.h
  • SAI_IT_AFSDET : stm32l4xx_hal_sai.h
  • SAI_IT_CNRDY : stm32l4xx_hal_sai.h
  • SAI_IT_FREQ : stm32l4xx_hal_sai.h
  • SAI_IT_LFSDET : stm32l4xx_hal_sai.h
  • SAI_IT_MUTEDET : stm32l4xx_hal_sai.h
  • SAI_IT_OVRUDR : stm32l4xx_hal_sai.h
  • SAI_IT_WCKCFG : stm32l4xx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32l4xx_hal_sai.h
  • SAI_MASTERDIVIDER_DISABLE : stm32l4xx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32l4xx_hal_sai.h
  • SAI_MODEMASTER_RX : stm32l4xx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32l4xx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32l4xx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32l4xx_hal_sai.h
  • SAI_MONOMODE : stm32l4xx_hal_sai.h
  • SAI_NOCOMPANDING : stm32l4xx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32l4xx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32l4xx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32l4xx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32l4xx_hal_sai.h
  • SAI_PCM_LONG : stm32l4xx_hal_sai.h
  • SAI_PCM_SHORT : stm32l4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32l4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32l4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32l4xx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32l4xx_hal_sai.h
  • SAI_SLOT_NOTACTIVE : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32l4xx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32l4xx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32l4xx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32l4xx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32l4xx_hal_sai.h
  • SAI_SPDIF_PROTOCOL : stm32l4xx_hal_sai.h
  • SAI_STEREOMODE : stm32l4xx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32l4xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKA_ENABLE : stm32l4xx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKB_ENABLE : stm32l4xx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32l4xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI1 : stm32l4xx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI2 : stm32l4xx_hal_sai.h
  • SAI_ULAW_1CPL_COMPANDING : stm32l4xx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32l4xx_hal_sai.h
  • SAI_xCR2_MUTECNT_OFFSET : stm32l4xx_hal_sai.c
  • SAI_ZERO_VALUE : stm32l4xx_hal_sai.h
  • SCSR_OFFSET : stm32l4xx_hal.c
  • SCSR_SRAM2ER_BB : stm32l4xx_hal.c
  • SD_0TO7BITS : stm32l4xx_hal_sd.c
  • SD_16TO23BITS : stm32l4xx_hal_sd.c
  • SD_24TO31BITS : stm32l4xx_hal_sd.c
  • SD_8TO15BITS : stm32l4xx_hal_sd.c
  • SD_ALLZERO : stm32l4xx_hal_sd.c
  • SD_CARD_LOCKED : stm32l4xx_hal_sd.c
  • SD_CCCC_ERASE : stm32l4xx_hal_sd.c
  • SD_CCCC_LOCK_UNLOCK : stm32l4xx_hal_sd.c
  • SD_CCCC_WRITE_PROT : stm32l4xx_hal_sd.c
  • SD_CHECK_PATTERN : stm32l4xx_hal_sd.c
  • SD_DATATIMEOUT : stm32l4xx_hal_sd.c
  • SD_HALFFIFO : stm32l4xx_hal_sd.c
  • SD_HALFFIFOBYTES : stm32l4xx_hal_sd.c
  • SD_HIGH_CAPACITY : stm32l4xx_hal_sd.c
  • SD_MAX_DATA_LENGTH : stm32l4xx_hal_sd.c
  • SD_MAX_VOLT_TRIAL : stm32l4xx_hal_sd.c
  • SD_OCR_ADDR_MISALIGNED : stm32l4xx_hal_sd.c
  • SD_OCR_ADDR_OUT_OF_RANGE : stm32l4xx_hal_sd.c
  • SD_OCR_AKE_SEQ_ERROR : stm32l4xx_hal_sd.c
  • SD_OCR_BAD_ERASE_PARAM : stm32l4xx_hal_sd.c
  • SD_OCR_BLOCK_LEN_ERR : stm32l4xx_hal_sd.c
  • SD_OCR_CARD_ECC_DISABLED : stm32l4xx_hal_sd.c
  • SD_OCR_CARD_ECC_FAILED : stm32l4xx_hal_sd.c
  • SD_OCR_CC_ERROR : stm32l4xx_hal_sd.c
  • SD_OCR_CID_CSD_OVERWRITE : stm32l4xx_hal_sd.c
  • SD_OCR_COM_CRC_FAILED : stm32l4xx_hal_sd.c
  • SD_OCR_ERASE_RESET : stm32l4xx_hal_sd.c
  • SD_OCR_ERASE_SEQ_ERR : stm32l4xx_hal_sd.c
  • SD_OCR_ERRORBITS : stm32l4xx_hal_sd.c
  • SD_OCR_GENERAL_UNKNOWN_ERROR : stm32l4xx_hal_sd.c
  • SD_OCR_ILLEGAL_CMD : stm32l4xx_hal_sd.c
  • SD_OCR_LOCK_UNLOCK_FAILED : stm32l4xx_hal_sd.c
  • SD_OCR_STREAM_READ_UNDERRUN : stm32l4xx_hal_sd.c
  • SD_OCR_STREAM_WRITE_OVERRUN : stm32l4xx_hal_sd.c
  • SD_OCR_WP_ERASE_SKIP : stm32l4xx_hal_sd.c
  • SD_OCR_WRITE_PROT_VIOLATION : stm32l4xx_hal_sd.c
  • SD_R6_COM_CRC_FAILED : stm32l4xx_hal_sd.c
  • SD_R6_GENERAL_UNKNOWN_ERROR : stm32l4xx_hal_sd.c
  • SD_R6_ILLEGAL_CMD : stm32l4xx_hal_sd.c
  • SD_SDMMC_SEND_IF_COND : stm32l4xx_hal_sd.c
  • SD_SINGLE_BUS_SUPPORT : stm32l4xx_hal_sd.c
  • SD_STD_CAPACITY : stm32l4xx_hal_sd.c
  • SD_VOLTAGE_WINDOW_SD : stm32l4xx_hal_sd.c
  • SD_WIDE_BUS_SUPPORT : stm32l4xx_hal_sd.c
  • SDMMC_CMD0TIMEOUT : stm32l4xx_hal_sd.c
  • SDMMC_STATIC_FLAGS : stm32l4xx_hal_sd.c
  • SlaveAddr_MSK : stm32l4xx_hal_i2c.c
  • SlaveAddr_SHIFT : stm32l4xx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_EOBF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_CR3_SCARCNT_LSB_POS : stm32l4xx_hal_smartcard.h
  • SMARTCARD_FLAG_BUSY : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_GTPR_GT_LSB_POS : stm32l4xx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32l4xx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32l4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32l4xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32l4xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32l4xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32l4xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32l4xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32l4xx_hal_smartcard.h
  • SMARTCARD_RTOR_BLEN_LSB_POS : stm32l4xx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32l4xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_0_5 : stm32l4xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32l4xx_hal_smartcard.h
  • SMARTCARD_TC : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32l4xx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32l4xx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32l4xx_hal_smartcard_ex.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32l4xx_hal_smartcard.h
  • SMARTCARD_WORDLENGTH_9B : stm32l4xx_hal_smartcard.h
  • SMBUS_ADDRESSINGMODE_10BIT : stm32l4xx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32l4xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32l4xx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32l4xx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32l4xx_hal_smbus.h
  • SMBUS_DUALADDRESS_DISABLE : stm32l4xx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32l4xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32l4xx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32l4xx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32l4xx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32l4xx_hal_smbus.h
  • SMBUS_GENERALCALL_DISABLE : stm32l4xx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32l4xx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32l4xx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32l4xx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32l4xx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32l4xx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32l4xx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32l4xx_hal_smbus.h
  • SMBUS_GET_DIR : stm32l4xx_hal_smbus.h
  • SMBUS_GET_ISR_REG : stm32l4xx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32l4xx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32l4xx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_RX : stm32l4xx_hal_smbus.h
  • SMBUS_IT_RXI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_TCI : stm32l4xx_hal_smbus.h
  • SMBUS_IT_TX : stm32l4xx_hal_smbus.h
  • SMBUS_IT_TXI : stm32l4xx_hal_smbus.h
  • SMBUS_LAST_FRAME_NO_PEC : stm32l4xx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32l4xx_hal_smbus.h
  • SMBUS_NEXT_FRAME : stm32l4xx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32l4xx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32l4xx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32l4xx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32l4xx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32l4xx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32l4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32l4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32l4xx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32l4xx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32l4xx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32l4xx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32l4xx_hal_smbus.h
  • SMBUS_SOFTEND_MODE : stm32l4xx_hal_smbus.h
  • SPI_1LINE_RX : stm32l4xx_hal_spi.h
  • SPI_1LINE_TX : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_128 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32l4xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32l4xx_hal_spi.h
  • SPI_CR1_CLEAR_MASK : stm32l4xx_ll_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32l4xx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32l4xx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32l4xx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32l4xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32l4xx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32l4xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32l4xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32l4xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32l4xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32l4xx_hal_spi.h
  • SPI_FIFO_SIZE : stm32l4xx_hal_spi_ex.c
  • SPI_FIRSTBIT_LSB : stm32l4xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32l4xx_hal_spi.h
  • SPI_FLAG_BSY : stm32l4xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32l4xx_hal_spi.h
  • SPI_FLAG_FRE : stm32l4xx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32l4xx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32l4xx_hal_spi.h
  • SPI_FLAG_MODF : stm32l4xx_hal_spi.h
  • SPI_FLAG_OVR : stm32l4xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32l4xx_hal_spi.h
  • SPI_FLAG_TXE : stm32l4xx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32l4xx_hal_spi.h
  • SPI_FRLVL_FULL : stm32l4xx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32l4xx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32l4xx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32l4xx_hal_spi.h
  • SPI_FTLVL_FULL : stm32l4xx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32l4xx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32l4xx_hal_spi.h
  • SPI_IT_ERR : stm32l4xx_hal_spi.h
  • SPI_IT_RXNE : stm32l4xx_hal_spi.h
  • SPI_IT_TXE : stm32l4xx_hal_spi.h
  • SPI_MODE_MASTER : stm32l4xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32l4xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32l4xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32l4xx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32l4xx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32l4xx_hal_spi.h
  • SPI_NSS_SOFT : stm32l4xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32l4xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32l4xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32l4xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32l4xx_hal_spi.h
  • SPI_RESET_CRC : stm32l4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32l4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32l4xx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32l4xx_hal_spi.h
  • SPI_TIMODE_DISABLE : stm32l4xx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32l4xx_hal_spi.h
  • SWPMI_FLAG_DEACTF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_RXBERF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_RXBFF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_RXNE : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_RXOVRF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_SRF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_SUSP : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_TCF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_TXBEF : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_TXE : stm32l4xx_hal_swpmi.h
  • SWPMI_FLAG_TXUNRF : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_RIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_RXBERIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_RXBFIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_RXOVRIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_SRIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_TCIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_TIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_TXBEIE : stm32l4xx_hal_swpmi.h
  • SWPMI_IT_TXUNRIE : stm32l4xx_hal_swpmi.h
  • SWPMI_RX_MULTI_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_RX_NO_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_RX_SINGLE_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_TIMEOUT_VALUE : stm32l4xx_hal_swpmi.c
  • SWPMI_TX_MULTI_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_TX_NO_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_TX_SINGLE_SOFTWAREBUFFER : stm32l4xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_B : stm32l4xx_hal_swpmi.h
  • SWPMI_VOLTAGE_CLASS_C : stm32l4xx_hal_swpmi.h
  • SYSCFG_BOOT_FMC : stm32l4xx_hal.h
  • SYSCFG_BOOT_MAINFLASH : stm32l4xx_hal.h
  • SYSCFG_BOOT_QUADSPI : stm32l4xx_hal.h
  • SYSCFG_BOOT_SRAM : stm32l4xx_hal.h
  • SYSCFG_BOOT_SYSTEMFLASH : stm32l4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32l4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32l4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32l4xx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32l4xx_hal.h
  • SYSCFG_FLAG_SRAM2_BUSY : stm32l4xx_hal.h
  • SYSCFG_FLAG_SRAM2_PE : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_DZC : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_IDC : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_IOC : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_IXC : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_OFC : stm32l4xx_hal.h
  • SYSCFG_IT_FPU_UFC : stm32l4xx_hal.h
  • SYSCFG_OFFSET : stm32l4xx_hal.c
  • SYSCFG_SRAM2WRP_PAGE0 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE1 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE10 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE11 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE12 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE13 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE14 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE15 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE16 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE17 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE18 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE19 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE2 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE20 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE21 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE22 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE23 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE24 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE25 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE26 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE27 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE28 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE29 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE3 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE30 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE31 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE4 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE5 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE6 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE7 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE8 : stm32l4xx_hal.h
  • SYSCFG_SRAM2WRP_PAGE9 : stm32l4xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32l4xx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32l4xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32l4xx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32l4xx_hal.h
  • SYSTICK_CLKSOURCE_HCLK : stm32l4xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32l4xx_hal_cortex.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- t -

  • TEMPSENSOR_CAL1_ADDR : stm32l4xx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32l4xx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32l4xx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32l4xx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32l4xx_ll_adc.h
  • TICK_INT_PRIORITY : stm32l4xx_hal_conf.h
  • TIM15_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM16_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM17_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM1_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM2_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM3_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM8_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32l4xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32l4xx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32l4xx_hal_tim.h
  • TIM_BREAK2_ENABLE : stm32l4xx_hal_tim.h
  • TIM_BREAK2POLARITY_HIGH : stm32l4xx_hal_tim.h
  • TIM_BREAK2POLARITY_LOW : stm32l4xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32l4xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32l4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_ECC : stm32l4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_LOCKUP : stm32l4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_PVD : stm32l4xx_hal_tim.h
  • TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR : stm32l4xx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_BKIN : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DFSDM1 : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32l4xx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32l4xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32l4xx_hal_tim.h
  • TIM_CALC_DTS : stm32l4xx_ll_tim.h
  • TIM_CCER_CCxE_MASK : stm32l4xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32l4xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32l4xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32l4xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32l4xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_1 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_5 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_6 : stm32l4xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32l4xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_OCREFCLR : stm32l4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32l4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32l4xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32l4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32l4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32l4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32l4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32l4xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32l4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32l4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32l4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32l4xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32l4xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32l4xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32l4xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32l4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32l4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32l4xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32l4xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32l4xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32l4xx_hal_tim.h
  • TIM_DMA_CC1 : stm32l4xx_hal_tim.h
  • TIM_DMA_CC2 : stm32l4xx_hal_tim.h
  • TIM_DMA_CC3 : stm32l4xx_hal_tim.h
  • TIM_DMA_CC4 : stm32l4xx_hal_tim.h
  • TIM_DMA_COM : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32l4xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32l4xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCMR3 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR5 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CCR6 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32l4xx_hal_tim.h
  • TIM_DMABASE_DMAR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_OR1 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_OR2 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_OR3 : stm32l4xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32l4xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32l4xx_hal_tim.h
  • TIM_DMABASE_SR : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32l4xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32l4xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32l4xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32l4xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32l4xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32l4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32l4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32l4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32l4xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32l4xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32l4xx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC5 : stm32l4xx_hal_tim.h
  • TIM_FLAG_CC6 : stm32l4xx_hal_tim.h
  • TIM_FLAG_COM : stm32l4xx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32l4xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32l4xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32l4xx_ll_tim.h
  • TIM_GROUPCH5_NONE : stm32l4xx_hal_tim.h
  • TIM_GROUPCH5_OC1REFC : stm32l4xx_hal_tim.h
  • TIM_GROUPCH5_OC2REFC : stm32l4xx_hal_tim.h
  • TIM_GROUPCH5_OC3REFC : stm32l4xx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32l4xx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32l4xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32l4xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32l4xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32l4xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32l4xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32l4xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32l4xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32l4xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32l4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32l4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32l4xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32l4xx_hal_tim.h
  • TIM_IT_BREAK : stm32l4xx_hal_tim.h
  • TIM_IT_CC1 : stm32l4xx_hal_tim.h
  • TIM_IT_CC2 : stm32l4xx_hal_tim.h
  • TIM_IT_CC3 : stm32l4xx_hal_tim.h
  • TIM_IT_CC4 : stm32l4xx_hal_tim.h
  • TIM_IT_COM : stm32l4xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_IT_UPDATE : stm32l4xx_hal_tim.h
  • TIM_LOCKLEVEL_1 : stm32l4xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32l4xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32l4xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32l4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32l4xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32l4xx_hal_tim.h
  • TIM_OCFAST_DISABLE : stm32l4xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32l4xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32l4xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32l4xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32l4xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32l4xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32l4xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32l4xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32l4xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32l4xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32l4xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32l4xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32l4xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32l4xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32l4xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32l4xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32l4xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32l4xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32l4xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32l4xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32l4xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32l4xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32l4xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32l4xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32l4xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32l4xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32l4xx_hal_tim.h
  • TIM_POSITION_ICPSC : stm32l4xx_ll_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32l4xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32l4xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32l4xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32l4xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32l4xx_hal_tim.h
  • TIM_TI1SELECTION_CH1 : stm32l4xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32l4xx_hal_tim.h
  • TIM_TIM15_ENCODERMODE_NONE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM15_ENCODERMODE_TIM2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM15_ENCODERMODE_TIM3 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM15_ENCODERMODE_TIM4 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM15_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM15_TI1_LSE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSI : stm32l4xx_hal_tim_ex.h
  • TIM_TIM16_TI1_RTC : stm32l4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_HSE_32 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_MCO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM17_TI1_MSI : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_NONE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_AWD3 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC3_NONE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ETR_LSE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ITR1_OTG_FS_SOF : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_ITR1_TIM8_TRGO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM2_TI4_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_ETR_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP1_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM3_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_AWD3 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC2_NONE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_AWD3 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_ADC3_NONE : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP1 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_ETR_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_COMP2 : stm32l4xx_hal_tim_ex.h
  • TIM_TIM8_TI1_GPIO : stm32l4xx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32l4xx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32l4xx_hal_tim.h
  • TIM_TRGO2_RESET : stm32l4xx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32l4xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32l4xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32l4xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32l4xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32l4xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32l4xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32l4xx_hal_tim.h
  • TIM_TRGO_RESET : stm32l4xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32l4xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32l4xx_hal_tim.h
  • TIM_TS_ETRF : stm32l4xx_hal_tim.h
  • TIM_TS_ITR0 : stm32l4xx_hal_tim.h
  • TIM_TS_ITR1 : stm32l4xx_hal_tim.h
  • TIM_TS_ITR2 : stm32l4xx_hal_tim.h
  • TIM_TS_ITR3 : stm32l4xx_hal_tim.h
  • TIM_TS_NONE : stm32l4xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32l4xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32l4xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32l4xx_hal_tim.h
  • TIMEOUT_DAC_CALIBCONFIG : stm32l4xx_hal_dac.c
  • TIMING_CLEAR_MASK : stm32l4xx_hal_i2c.c , stm32l4xx_hal_smbus.c
  • TIMx_ETRSEL_MASK : stm32l4xx_hal_tim_ex.c
  • TIMx_OR1_RMP_MASK : stm32l4xx_ll_tim.h
  • TIMx_OR1_RMP_SHIFT : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKCOMP1E : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKCOMP1P : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKCOMP2E : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKCOMP2P : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKDF1BK0E : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKINE : stm32l4xx_ll_tim.h
  • TIMx_OR2_BKINP : stm32l4xx_ll_tim.h
  • TIMx_OR2_ETRSEL : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2COMP1E : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2COMP1P : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2COMP2E : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2COMP2P : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2DF1BK1E : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2INE : stm32l4xx_ll_tim.h
  • TIMx_OR3_BK2INP : stm32l4xx_ll_tim.h
  • TSC_ACQ_MODE_NORMAL : stm32l4xx_hal_tsc.h
  • TSC_ACQ_MODE_SYNCHRO : stm32l4xx_hal_tsc.h
  • TSC_ALL_GROUPS : stm32l4xx_hal_tsc.h
  • TSC_ALL_GROUPS_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_CTPH_10CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_11CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_12CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_13CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_14CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_15CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_16CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_1CYCLE : stm32l4xx_hal_tsc.h
  • TSC_CTPH_2CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_3CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_4CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_5CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_6CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_7CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_8CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPH_9CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_10CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_11CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_12CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_13CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_14CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_15CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_16CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_1CYCLE : stm32l4xx_hal_tsc.h
  • TSC_CTPL_2CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_3CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_4CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_5CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_6CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_7CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_8CYCLES : stm32l4xx_hal_tsc.h
  • TSC_CTPL_9CYCLES : stm32l4xx_hal_tsc.h
  • TSC_FLAG_EOA : stm32l4xx_hal_tsc.h
  • TSC_FLAG_MCE : stm32l4xx_hal_tsc.h
  • TSC_GROUP1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP1_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP2_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP3_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP4_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP5 : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP5_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP6 : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP6_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP7 : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP7_IO4 : stm32l4xx_hal_tsc.h
  • TSC_GROUP8 : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_ALL_IOS : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_IDX : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_IO1 : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_IO2 : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_IO3 : stm32l4xx_hal_tsc.h
  • TSC_GROUP8_IO4 : stm32l4xx_hal_tsc.h
  • TSC_IODEF_IN_FLOAT : stm32l4xx_hal_tsc.h
  • TSC_IODEF_OUT_PP_LOW : stm32l4xx_hal_tsc.h
  • TSC_IOMODE_CHANNEL : stm32l4xx_hal_tsc.h
  • TSC_IOMODE_SAMPLING : stm32l4xx_hal_tsc.h
  • TSC_IOMODE_SHIELD : stm32l4xx_hal_tsc.h
  • TSC_IOMODE_UNUSED : stm32l4xx_hal_tsc.h
  • TSC_IT_EOA : stm32l4xx_hal_tsc.h
  • TSC_IT_MCE : stm32l4xx_hal_tsc.h
  • TSC_MCV_1023 : stm32l4xx_hal_tsc.h
  • TSC_MCV_16383 : stm32l4xx_hal_tsc.h
  • TSC_MCV_2047 : stm32l4xx_hal_tsc.h
  • TSC_MCV_255 : stm32l4xx_hal_tsc.h
  • TSC_MCV_4095 : stm32l4xx_hal_tsc.h
  • TSC_MCV_511 : stm32l4xx_hal_tsc.h
  • TSC_MCV_8191 : stm32l4xx_hal_tsc.h
  • TSC_NB_OF_GROUPS : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV1 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV128 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV16 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV2 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV32 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV4 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV64 : stm32l4xx_hal_tsc.h
  • TSC_PG_PRESC_DIV8 : stm32l4xx_hal_tsc.h
  • TSC_SS_PRESC_DIV1 : stm32l4xx_hal_tsc.h
  • TSC_SS_PRESC_DIV2 : stm32l4xx_hal_tsc.h
  • TSC_SYNC_POLARITY_FALLING : stm32l4xx_hal_tsc.h
  • TSC_SYNC_POLARITY_RISING : stm32l4xx_hal_tsc.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- u -

  • UART_ADDRESS_DETECT_4B : stm32l4xx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32l4xx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32l4xx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32l4xx_hal_uart.h
  • UART_AUTOBAUD_REQUEST : stm32l4xx_hal_uart.h
  • UART_CLEAR_CMF : stm32l4xx_hal_uart.h
  • UART_CLEAR_CTSF : stm32l4xx_hal_uart.h
  • UART_CLEAR_EOBF : stm32l4xx_hal_uart.h
  • UART_CLEAR_FEF : stm32l4xx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32l4xx_hal_uart.h
  • UART_CLEAR_LBDF : stm32l4xx_hal_uart.h
  • UART_CLEAR_NEF : stm32l4xx_hal_uart.h
  • UART_CLEAR_OREF : stm32l4xx_hal_uart.h
  • UART_CLEAR_PEF : stm32l4xx_hal_uart.h
  • UART_CLEAR_RTOF : stm32l4xx_hal_uart.h
  • UART_CLEAR_TCF : stm32l4xx_hal_uart.h
  • UART_CLEAR_WUF : stm32l4xx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32l4xx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32l4xx_hal_uart.h
  • UART_CR1_FIELDS : stm32l4xx_hal_uart.c
  • UART_CR2_ADDRESS_LSB_POS : stm32l4xx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32l4xx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32l4xx_hal_uart.h
  • UART_DIV_LPUART : stm32l4xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32l4xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32l4xx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32l4xx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32l4xx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32l4xx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32l4xx_hal_uart.h
  • UART_FLAG_ABRE : stm32l4xx_hal_uart.h
  • UART_FLAG_ABRF : stm32l4xx_hal_uart.h
  • UART_FLAG_BUSY : stm32l4xx_hal_uart.h
  • UART_FLAG_CMF : stm32l4xx_hal_uart.h
  • UART_FLAG_CTS : stm32l4xx_hal_uart.h
  • UART_FLAG_CTSIF : stm32l4xx_hal_uart.h
  • UART_FLAG_EOBF : stm32l4xx_hal_uart.h
  • UART_FLAG_FE : stm32l4xx_hal_uart.h
  • UART_FLAG_IDLE : stm32l4xx_hal_uart.h
  • UART_FLAG_LBDF : stm32l4xx_hal_uart.h
  • UART_FLAG_NE : stm32l4xx_hal_uart.h
  • UART_FLAG_ORE : stm32l4xx_hal_uart.h
  • UART_FLAG_PE : stm32l4xx_hal_uart.h
  • UART_FLAG_REACK : stm32l4xx_hal_uart.h
  • UART_FLAG_RTOF : stm32l4xx_hal_uart.h
  • UART_FLAG_RWU : stm32l4xx_hal_uart.h
  • UART_FLAG_RXNE : stm32l4xx_hal_uart.h
  • UART_FLAG_SBKF : stm32l4xx_hal_uart.h
  • UART_FLAG_TC : stm32l4xx_hal_uart.h
  • UART_FLAG_TEACK : stm32l4xx_hal_uart.h
  • UART_FLAG_TXE : stm32l4xx_hal_uart.h
  • UART_FLAG_WUF : stm32l4xx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32l4xx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32l4xx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32l4xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32l4xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32l4xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32l4xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32l4xx_hal_uart.h
  • UART_INSTANCE_LOWPOWER : stm32l4xx_hal_uart.h
  • UART_IT_CM : stm32l4xx_hal_uart.h
  • UART_IT_CTS : stm32l4xx_hal_uart.h
  • UART_IT_ERR : stm32l4xx_hal_uart.h
  • UART_IT_FE : stm32l4xx_hal_uart.h
  • UART_IT_IDLE : stm32l4xx_hal_uart.h
  • UART_IT_LBD : stm32l4xx_hal_uart.h
  • UART_IT_MASK : stm32l4xx_hal_uart.h
  • UART_IT_NE : stm32l4xx_hal_uart.h
  • UART_IT_ORE : stm32l4xx_hal_uart.h
  • UART_IT_PE : stm32l4xx_hal_uart.h
  • UART_IT_RXNE : stm32l4xx_hal_uart.h
  • UART_IT_TC : stm32l4xx_hal_uart.h
  • UART_IT_TXE : stm32l4xx_hal_uart.h
  • UART_IT_WUF : stm32l4xx_hal_uart.h
  • UART_LIN_DISABLE : stm32l4xx_hal_uart.h
  • UART_LIN_ENABLE : stm32l4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32l4xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32l4xx_hal_uart.h
  • UART_LPUART_BRR_MAX : stm32l4xx_hal_uart.c
  • UART_LPUART_BRR_MIN : stm32l4xx_hal_uart.c
  • UART_MASK_COMPUTATION : stm32l4xx_hal_uart_ex.h
  • UART_MODE_RX : stm32l4xx_hal_uart.h
  • UART_MODE_TX : stm32l4xx_hal_uart.h
  • UART_MODE_TX_RX : stm32l4xx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32l4xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32l4xx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32l4xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32l4xx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32l4xx_hal_uart.h
  • UART_PARITY_EVEN : stm32l4xx_hal_uart.h
  • UART_PARITY_NONE : stm32l4xx_hal_uart.h
  • UART_PARITY_ODD : stm32l4xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32l4xx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32l4xx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32l4xx_hal_uart.h
  • UART_SENDBREAK_REQUEST : stm32l4xx_hal_uart.h
  • UART_STATE_DISABLE : stm32l4xx_hal_uart.h
  • UART_STATE_ENABLE : stm32l4xx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32l4xx_hal_uart.h
  • UART_STOPBITS_1 : stm32l4xx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32l4xx_hal_uart.h
  • UART_STOPBITS_2 : stm32l4xx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32l4xx_hal_uart.h
  • UART_WAKEUP_ON_ADDRESS : stm32l4xx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32l4xx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32l4xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32l4xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32l4xx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32l4xx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32l4xx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32l4xx_hal_uart_ex.h
  • UID_BASE_ADDRESS : stm32l4xx_ll_utils.h
  • USART_CLEAR_FEF : stm32l4xx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32l4xx_hal_usart.h
  • USART_CLEAR_NEF : stm32l4xx_hal_usart.h
  • USART_CLEAR_OREF : stm32l4xx_hal_usart.h
  • USART_CLEAR_PEF : stm32l4xx_hal_usart.h
  • USART_CLEAR_TCF : stm32l4xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32l4xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32l4xx_hal_usart.h
  • USART_CR1_FIELDS : stm32l4xx_hal_smartcard.c , stm32l4xx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32l4xx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32l4xx_hal_usart.c , stm32l4xx_hal_smartcard.c
  • USART_CR3_FIELDS : stm32l4xx_hal_smartcard.c
  • USART_DUMMY_DATA : stm32l4xx_hal_usart.c
  • USART_FLAG_BUSY : stm32l4xx_hal_usart.h
  • USART_FLAG_CTS : stm32l4xx_hal_usart.h
  • USART_FLAG_CTSIF : stm32l4xx_hal_usart.h
  • USART_FLAG_FE : stm32l4xx_hal_usart.h
  • USART_FLAG_IDLE : stm32l4xx_hal_usart.h
  • USART_FLAG_LBDF : stm32l4xx_hal_usart.h
  • USART_FLAG_NE : stm32l4xx_hal_usart.h
  • USART_FLAG_ORE : stm32l4xx_hal_usart.h
  • USART_FLAG_PE : stm32l4xx_hal_usart.h
  • USART_FLAG_REACK : stm32l4xx_hal_usart.h
  • USART_FLAG_RXNE : stm32l4xx_hal_usart.h
  • USART_FLAG_TC : stm32l4xx_hal_usart.h
  • USART_FLAG_TEACK : stm32l4xx_hal_usart.h
  • USART_FLAG_TXE : stm32l4xx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32l4xx_hal_usart_ex.h
  • USART_IT_ERR : stm32l4xx_hal_usart.h
  • USART_IT_FE : stm32l4xx_hal_usart.h
  • USART_IT_IDLE : stm32l4xx_hal_usart.h
  • USART_IT_MASK : stm32l4xx_hal_usart.h
  • USART_IT_NE : stm32l4xx_hal_usart.h
  • USART_IT_ORE : stm32l4xx_hal_usart.h
  • USART_IT_PE : stm32l4xx_hal_usart.h
  • USART_IT_RXNE : stm32l4xx_hal_usart.h
  • USART_IT_TC : stm32l4xx_hal_usart.h
  • USART_IT_TXE : stm32l4xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32l4xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32l4xx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32l4xx_hal_usart_ex.h
  • USART_MODE_RX : stm32l4xx_hal_usart.h
  • USART_MODE_TX : stm32l4xx_hal_usart.h
  • USART_MODE_TX_RX : stm32l4xx_hal_usart.h
  • USART_OVERSAMPLING_16 : stm32l4xx_hal_usart.h
  • USART_OVERSAMPLING_8 : stm32l4xx_hal_usart.h
  • USART_PARITY_EVEN : stm32l4xx_hal_usart.h
  • USART_PARITY_NONE : stm32l4xx_hal_usart.h
  • USART_PARITY_ODD : stm32l4xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32l4xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32l4xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32l4xx_hal_usart.h
  • USART_POLARITY_LOW : stm32l4xx_hal_usart.h
  • USART_POSITION_CR1_DEAT : stm32l4xx_ll_usart.h
  • USART_POSITION_CR1_DEDT : stm32l4xx_ll_usart.h
  • USART_POSITION_CR2_ADD : stm32l4xx_ll_usart.h
  • USART_POSITION_CR3_SCARCNT : stm32l4xx_ll_usart.h
  • USART_POSITION_GTPR_GT : stm32l4xx_ll_usart.h
  • USART_POSITION_RTOR_BLEN : stm32l4xx_ll_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32l4xx_hal_usart.h
  • USART_STOPBITS_0_5 : stm32l4xx_hal_usart.h
  • USART_STOPBITS_1 : stm32l4xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32l4xx_hal_usart.h
  • USART_STOPBITS_2 : stm32l4xx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32l4xx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32l4xx_hal_usart.h
  • USART_WORDLENGTH_7B : stm32l4xx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32l4xx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32l4xx_hal_usart_ex.h
  • USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE : stm32l4xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_LINE : stm32l4xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE : stm32l4xx_hal_pcd.h
  • USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE : stm32l4xx_hal_pcd.h
  • USBD_FS_TRDT_VALUE : stm32l4xx_hal_pcd.h
  • USE_RTOS : stm32l4xx_hal_conf.h
  • UTILS_HSE_FREQUENCY_MAX : stm32l4xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32l4xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE1 : stm32l4xx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE2 : stm32l4xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX : stm32l4xx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN : stm32l4xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MAX : stm32l4xx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MIN : stm32l4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY1_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY2_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY3_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE1_LATENCY4_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY1_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY2_FREQ : stm32l4xx_ll_utils.c
  • UTILS_SCALE2_LATENCY3_FREQ : stm32l4xx_ll_utils.c
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- v -

  • VDD_VALUE : stm32l4xx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32l4xx_hal.c
  • VREFINT_CAL_ADDR : stm32l4xx_ll_adc.h
  • VREFINT_CAL_VREF : stm32l4xx_ll_adc.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Globals

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- w -

  • WWDG_EWI_DISABLE : stm32l4xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32l4xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32l4xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32l4xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32l4xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32l4xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32l4xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32l4xx_hal_wwdg.h
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal.h File Reference

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Defines | Functions
stm32l4xx_hal.h File Reference

This file contains all the functions prototypes for the HAL module driver. More...

#include "stm32l4xx_hal_conf.h"

Go to the source code of this file.

Defines

#define | SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
#define | SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#define | SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1
#define | SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#define | SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
#define | SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0
#define | SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1
#define | SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2
#define | SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3
#define | SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4
#define | SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5
#define | SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0
#define | SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1
#define | SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2
#define | SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3
#define | SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4
#define | SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5
#define | SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6
#define | SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7
#define | SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8
#define | SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9
#define | SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10
#define | SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11
#define | SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12
#define | SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13
#define | SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14
#define | SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15
#define | SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16
#define | SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17
#define | SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18
#define | SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19
#define | SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20
#define | SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21
#define | SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22
#define | SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23
#define | SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24
#define | SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25
#define | SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26
#define | SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27
#define | SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28
#define | SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29
#define | SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30
#define | SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000)
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ
#define | SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF
#define | SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY
#define | SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
Fast-mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
Freeze/Unfreeze Peripherals in Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define | __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define | __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define | __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
#define | __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
Embedded SRAM mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
QUADSPI mapped at 0x00000000.
#define | __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
Return the boot mode as configured by user.
#define | __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__)
SRAM2 page write protection enable macro.
#define | __HAL_SYSCFG_SRAM2_WRP_UNLOCK()
SRAM2 page write protection unlock prior to erase.
#define | __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
SRAM2 erase.
#define | __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)
Floating Point Unit interrupt enable/disable macros.
#define | __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)
#define | __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
SYSCFG Break ECC lock.
#define | __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
SYSCFG Break Cortex-M4 Lockup lock.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
SYSCFG Break PVD lock.
#define | __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
SYSCFG Break SRAM2 parity lock.
#define | __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
Check SYSCFG flag is set or not.
#define | __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
Set the SPF bit to clear the SRAM Parity Error Flag.
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast-mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)
#define | IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__)
#define | IS_SYSCFG_BREAK_CONFIG(__CONFIG__)
#define | IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)

Functions

HAL_StatusTypeDef | HAL_Init (void)
Configure the Flash prefetch, the Instruction and Data caches, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32l4xx_hal_msp.c.
HAL_StatusTypeDef | HAL_DeInit (void)
De-initialize common part of the HAL and stop the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitialize the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak void | HAL_Delay (uint32_t Delay)
Provide accurate delay (in milliseconds) based on variable incremented.
__weak uint32_t | HAL_GetTick (void)
Provide a tick value in millisecond.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Return the HAL revision.
uint32_t | HAL_GetREVID (void)
Return the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Return the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_SYSCFG_SRAM2Erase (void)
Start a hardware SRAM2 erase operation.
void | HAL_SYSCFG_EnableMemorySwappingBank (void)
Enable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_DisableMemorySwappingBank (void)
Disable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOAnalogSwitchBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOAnalogSwitchBooster (void)
Disable the I/O analog switch voltage booster.

Detailed Description

This file contains all the functions prototypes for the HAL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_adc.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32l4xx_hal_adc.h File Reference

Header file of ADC HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_adc_ex.h"

Go to the source code of this file.

Data Structures

struct | ADC_OversamplingTypeDef
ADC Regular Conversion Oversampling structure definition. More...
struct | ADC_InjectionConfigTypeDef
ADC Injection Configuration. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...

Defines

#define | HAL_ADC_STATE_RESET ((uint32_t)0x00000000)
HAL ADC state machine: ADC State bitfield definition.
#define | HAL_ADC_STATE_READY ((uint32_t)0x00000001)
#define | HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002)
#define | HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004)
#define | HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010)
#define | HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020)
#define | HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040)
#define | HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100)
#define | HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200)
#define | HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400)
#define | HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800)
#define | HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000)
#define | HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000)
#define | HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000)
#define | HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000)
#define | HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000)
#define | HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000)
#define | HAL_ADC_ERROR_NONE ((uint32_t)0x00)
#define | HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01)
#define | HAL_ADC_ERROR_OVR ((uint32_t)0x02)
#define | HAL_ADC_ERROR_DMA ((uint32_t)0x04)
#define | HAL_ADC_ERROR_JQOVF ((uint32_t)0x08)
#define | ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE)
#define | ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
#define | ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
#define | ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
#define | ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000)
#define | ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0)
#define | ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1)
#define | ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2))
#define | ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1))
#define | ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3))
#define | ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0))
#define | ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1))
#define | ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))
#define | ADC_RESOLUTION_12B ((uint32_t)0x00000000)
#define | ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0)
#define | ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1)
#define | ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES)
#define | ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define | ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN)
#define | ADC_SCAN_DISABLE ((uint32_t)0x00000000)
#define | ADC_SCAN_ENABLE ((uint32_t)0x00000001)
#define | ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)
#define | ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define | ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define | ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
#define | ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
#define | ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
#define | ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define | ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define | ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
#define | ADC_SOFTWARE_START ((uint32_t)0x00000001)
#define | ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
#define | ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS))
#define | ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
#define | ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD)
#define | ADC_CHANNEL_0 ((uint32_t)(0x00000000))
#define | ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
#define | ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
#define | ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
#define | ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
#define | ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
#define | ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_17
#define | ADC_CHANNEL_VBAT ADC_CHANNEL_18
#define | ADC_CHANNEL_VREFINT ADC_CHANNEL_0
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
Return resolution bits in CFGR register RES[1:0] field.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)
Check if conversion is on going on regular group.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clear and set specific bits of the handle State.
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
Verify the length of the scheduled regular conversions group.
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
Verify the number of scheduled regular conversions in discontinuous mode.
#define | IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
Verify the ADC clock setting.
#define | IS_ADC_RESOLUTION(__RESOLUTION__)
Verify the ADC resolution setting.
#define | IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__)
Verify the ADC resolution setting when limited to 6 or 8 bits.
#define | IS_ADC_DATA_ALIGN(__ALIGN__)
Verify the ADC converted data alignment.
#define | IS_ADC_SCAN_MODE(__SCAN_MODE__)
Verify the ADC scan mode.
#define | IS_ADC_EXTTRIG_EDGE(__EDGE__)
Verify the ADC edge trigger setting for regular group.
#define | IS_ADC_EXTTRIG(__REGTRIG__)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
Verify the ADC regular conversions check for converted data availability.
#define | IS_ADC_OVERRUN(__OVR__)
Verify the ADC regular conversions overrun handling.
#define | IS_ADC_SAMPLE_TIME(__TIME__)
Verify the ADC conversions sampling time.
#define | ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5)
#define | ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120)
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified ADC interrupt source is enabled or not.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable an ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable an ADC interrupt.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Check whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear a specified ADC flag.

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular and injected groups, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups when interruptions are enabled.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups and disable ADC DMA transfer.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure the selected channel to be linked to the regular group.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Header file of ADC HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_adc.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_adc_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32l4xx_hal_adc_ex.h File Reference

Header file of ADC HAL extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ADC_InitTypeDef
Structure definition of ADC initialization and regular group. More...
struct | ADC_HandleTypeDef
ADC handle Structure definition. More...
struct | ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition. More...
struct | ADC_InjectionConfTypeDef
Structure definition of ADC injected group and ADC channel for injected group. More...
struct | ADC_MultiModeTypeDef
Structure definition of ADC multimode. More...

Defines

#define | ADC_SINGLE_ENDED ((uint32_t)0x00000000)
#define | ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF)
#define | ADC_OFFSET_NONE ((uint32_t)0x00)
#define | ADC_OFFSET_1 ((uint32_t)0x01)
#define | ADC_OFFSET_2 ((uint32_t)0x02)
#define | ADC_OFFSET_3 ((uint32_t)0x03)
#define | ADC_OFFSET_4 ((uint32_t)0x04)
#define | ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
#define | ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
#define | ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
#define | ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
#define | ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
#define | ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
#define | ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
#define | ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
#define | ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
#define | ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
#define | ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
#define | ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
#define | ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
#define | ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
#define | ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
#define | ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
#define | ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
#define | ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
#define | ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
#define | ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
#define | ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
#define | ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
#define | ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
#define | ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
#define | ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
#define | ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
#define | ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000))
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1))
#define | ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1))
#define | ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))
#define | ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0))
#define | ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000)
#define | ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC_CCR_MDMA_1)
#define | ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC_CCR_MDMA)
#define | ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000))
#define | ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2))
#define | ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3))
#define | ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
#define | ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
#define | ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
#define | ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001)
#define | ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002)
#define | ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003)
#define | ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
#define | ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
#define | ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))
#define | ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))
#define | ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
#define | ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF)
#define | ADC_AWD_EVENT ADC_AWD1_EVENT
#define | ADC_IT_RDY ADC_IER_ADRDY
#define | ADC_IT_EOSMP ADC_IER_EOSMP
#define | ADC_IT_EOC ADC_IER_EOC
#define | ADC_IT_EOS ADC_IER_EOS
#define | ADC_IT_OVR ADC_IER_OVR
#define | ADC_IT_JEOC ADC_IER_JEOC
#define | ADC_IT_JEOS ADC_IER_JEOS
#define | ADC_IT_AWD1 ADC_IER_AWD1
#define | ADC_IT_AWD2 ADC_IER_AWD2
#define | ADC_IT_AWD3 ADC_IER_AWD3
#define | ADC_IT_JQOVF ADC_IER_JQOVF
#define | ADC_IT_AWD ADC_IT_AWD1
#define | ADC_FLAG_RDY ADC_ISR_ADRDY
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_JEOC ADC_ISR_JEOC
#define | ADC_FLAG_JEOS ADC_ISR_JEOS
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | ADC_FLAG_AWD ADC_FLAG_AWD1
#define | ADC_FLAG_ALL
#define | ADC_FLAG_POSTCONV_ALL
#define | ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
#define | ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
#define | ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
#define | ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
#define | ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000)
#define | ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0)
#define | ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1)
#define | ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0))
#define | ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2)
#define | ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0))
#define | ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1))
#define | ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR))
#define | ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000)
#define | ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0)
#define | ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1)
#define | ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2)
#define | ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1))
#define | ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))
#define | ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3)
#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS)
#define | ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000)
#define | ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM)
#define | ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)0x00000000)
#define | ADC_SAMPLETIME_6CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0)
#define | ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1)
#define | ADC_SAMPLETIME_24CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0))
#define | ADC_SAMPLETIME_47CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2)
#define | ADC_SAMPLETIME_92CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0))
#define | ADC_SAMPLETIME_247CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1))
#define | ADC_SAMPLETIME_640CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10)
#define | ADC_CFGR_FIELDS
#define | ADC_SMPR1_FIELDS
#define | ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)
Check if conversion is on going on regular or injected groups.
#define | ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)
Check if conversion is on going on injected group.
#define | ADC_IS_INDEPENDENT(__HANDLE__)
Check whether or not ADC is independent.
#define | ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
Set the sample time for Channels numbers between 0 and 9.
#define | ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
Set the sample time for Channels numbers between 10 and 18.
#define | ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)
Write SMPR1 register.
#define | ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)
Write SMPR2 register.
#define | ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
Set the selected regular Channel rank for rank between 1 and 4.
#define | ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
Set the selected regular Channel rank for rank between 5 and 9.
#define | ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
Set the selected regular Channel rank for rank between 10 and 14.
#define | ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
Set the selected regular Channel rank for rank between 15 and 16.
#define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2))
Set the selected injected Channel rank.
#define | ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
Set the Analog Watchdog 1 channel.
#define | ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
Configure the channel number in Analog Watchdog 2 or 3.
#define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
Configure ADC injected context queue.
#define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN))
Configure ADC discontinuous conversion mode for injected group.
#define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
Configure ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
Configure the number of discontinuous conversions for regular group.
#define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
Configure the ADC auto delay mode.
#define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
Configure ADC continuous conversion mode.
#define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CFGR_DMACFG))
Configure the ADC DMA continuous request.
#define | ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
Configure the channel number into offset OFRx register.
#define | ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
Configure the channel number into differential mode selection register.
#define | ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
Configure calibration factor in differential mode to be set into calibration register.
#define | ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
Calibration factor in differential mode to be retrieved from calibration register.
#define | ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
#define | ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
Configure the ADC DMA continuous request for ADC multimode.
#define | ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
Enable the ADC peripheral.
#define | ADC_ENABLING_CONDITIONS(__HANDLE__)
Verification of hardware constraints before ADC can be enabled.
#define | ADC_DISABLE(__HANDLE__)
Disable the ADC peripheral.
#define | ADC_DISABLING_CONDITIONS(__HANDLE__)
Verification of hardware constraints before ADC can be disabled.
#define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
Shift the offset with respect to the selected ADC resolution.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
Shift the AWD1 threshold with respect to the selected ADC resolution.
#define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
#define | ADC_COMMON_REGISTER(__HANDLE__) (ADC123_COMMON)
Report ADC common register.
#define | ADC_MASTER_REGISTER(__HANDLE__)
Report Master Instance.
#define | ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__)
Clear Common Control Register.
#define | ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__)
Check whether or not dual conversions are enabled.
#define | ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)
Check whether or not dual regular conversions are enabled.
#define | ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
#define | ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)
Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
#define | ADC_INSTANCE_IS_ENABLED(__INSTANCE__)
Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
#define | ADC_ANY_OTHER_ENABLED(__HANDLE__)
Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
#define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
Set handle instance of the ADC slave associated to the ADC master.
#define | ADC_MULTIMODE_DMA_ENABLED()
Check whether or not multimode is configured in DMA mode.
#define | ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
Verify the ADC instance connected to the temperature sensor.
#define | ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
Verify the ADC instance connected to the battery voltage VBAT.
#define | ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
Verify the ADC instance connected to the internal voltage reference VREFINT.
#define | IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
Verify the length of scheduled injected conversions group.
#define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F))
Calibration factor size verification (7 bits maximum).
#define | IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting.
#define | IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting in differential mode.
#define | IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__)
Verify the ADC single-ended input or differential mode setting.
#define | IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__)
Verify the ADC offset management setting.
#define | IS_ADC_REGULAR_RANK(__CHANNEL__)
Verify the ADC regular channel setting.
#define | IS_ADC_INJECTED_RANK(__CHANNEL__)
Verify the ADC injected channel setting.
#define | IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__)
Verify the ADC edge trigger setting for injected group.
#define | IS_ADC_EXTTRIGINJEC(__INJTRIG__)
Verify the ADC injected conversions external trigger.
#define | IS_ADC_MULTIMODE(__MODE__)
Verify the ADC multimode setting.
#define | IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__)
Verify the ADC multimode DMA access setting.
#define | IS_ADC_SAMPLING_DELAY(__DELAY__)
Verify the ADC multimode delay setting.
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__)
Verify the ADC analog watchdog setting.
#define | IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__)
Verify the ADC analog watchdog mode setting.
#define | IS_ADC_CONVERSION_GROUP(__CONVERSION__)
Verify the ADC conversion (regular or injected or both).
#define | IS_ADC_EVENT_TYPE(__EVENT__)
Verify the ADC event type.
#define | IS_ADC_OVERSAMPLING_RATIO(__RATIO__)
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
Verify the ADC oversampling shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling triggered mode.
#define | IS_ADC_REGOVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling regular conversion resumed or continued mode.
#define | IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
Verify the DFSDM mode configuration.
#define | ADC_CFGR_DFSDM(__HANDLE__) (0x0)
Return the DFSDM configuration mode.

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable ADC peripheral if no regular conversion is on going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups when interruptions are enabled, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups and disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure the ADC injected group and the selected channel to be linked to the injected group.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

Header file of ADC HAL extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_adc_ex.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_can.h File Reference

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stm32l4xx_hal_can.h File Reference

Header file of CAN HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CAN_InitTypeDef
CAN init structure definition. More...
struct | CAN_FilterConfTypeDef
CAN filter configuration structure definition. More...
struct | CanTxMsgTypeDef
CAN Tx message structure definition. More...
struct | CanRxMsgTypeDef
CAN Rx message structure definition. More...
struct | CAN_HandleTypeDef
CAN handle Structure definition. More...

Defines

#define | HAL_CAN_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_CAN_ERROR_EWG ((uint32_t)0x00000001)
#define | HAL_CAN_ERROR_EPV ((uint32_t)0x00000002)
#define | HAL_CAN_ERROR_BOF ((uint32_t)0x00000004)
#define | HAL_CAN_ERROR_STF ((uint32_t)0x00000008)
#define | HAL_CAN_ERROR_FOR ((uint32_t)0x00000010)
#define | HAL_CAN_ERROR_ACK ((uint32_t)0x00000020)
#define | HAL_CAN_ERROR_BR ((uint32_t)0x00000040)
#define | HAL_CAN_ERROR_BD ((uint32_t)0x00000080)
#define | HAL_CAN_ERROR_CRC ((uint32_t)0x00000100)
#define | CAN_INITSTATUS_FAILED ((uint32_t)0x00000000)
#define | CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001)
#define | CAN_MODE_NORMAL ((uint32_t)0x00000000)
#define | CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)
#define | CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)
#define | CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))
#define | CAN_SJW_1TQ ((uint32_t)0x00000000)
#define | CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)
#define | CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)
#define | CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)
#define | CAN_BS1_1TQ ((uint32_t)0x00000000)
#define | CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)
#define | CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)
#define | CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)
#define | CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)
#define | CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))
#define | CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))
#define | CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))
#define | CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)
#define | CAN_BS2_1TQ ((uint32_t)0x00000000)
#define | CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)
#define | CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)
#define | CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))
#define | CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)
#define | CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))
#define | CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))
#define | CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)
#define | CAN_FILTERMODE_IDMASK ((uint8_t)0x00)
#define | CAN_FILTERMODE_IDLIST ((uint8_t)0x01)
#define | CAN_FILTERSCALE_16BIT ((uint8_t)0x00)
#define | CAN_FILTERSCALE_32BIT ((uint8_t)0x01)
#define | CAN_FILTER_FIFO0 ((uint8_t)0x00)
#define | CAN_FILTER_FIFO1 ((uint8_t)0x01)
#define | CAN_ID_STD ((uint32_t)0x00000000)
#define | CAN_ID_EXT ((uint32_t)0x00000004)
#define | CAN_RTR_DATA ((uint32_t)0x00000000)
#define | CAN_RTR_REMOTE ((uint32_t)0x00000002)
#define | CAN_FIFO0 ((uint8_t)0x00)
#define | CAN_FIFO1 ((uint8_t)0x01)
#define | CAN_FLAG_RQCP0 ((uint32_t)0x00000500)
#define | CAN_FLAG_RQCP1 ((uint32_t)0x00000508)
#define | CAN_FLAG_RQCP2 ((uint32_t)0x00000510)
#define | CAN_FLAG_TXOK0 ((uint32_t)0x00000501)
#define | CAN_FLAG_TXOK1 ((uint32_t)0x00000509)
#define | CAN_FLAG_TXOK2 ((uint32_t)0x00000511)
#define | CAN_FLAG_TME0 ((uint32_t)0x0000051A)
#define | CAN_FLAG_TME1 ((uint32_t)0x0000051B)
#define | CAN_FLAG_TME2 ((uint32_t)0x0000051C)
#define | CAN_FLAG_FF0 ((uint32_t)0x00000203)
#define | CAN_FLAG_FOV0 ((uint32_t)0x00000204)
#define | CAN_FLAG_FF1 ((uint32_t)0x00000403)
#define | CAN_FLAG_FOV1 ((uint32_t)0x00000404)
#define | CAN_FLAG_WKU ((uint32_t)0x00000103)
#define | CAN_FLAG_SLAK ((uint32_t)0x00000101)
#define | CAN_FLAG_SLAKI ((uint32_t)0x00000104)
#define | CAN_FLAG_EWG ((uint32_t)0x00000300)
#define | CAN_FLAG_EPV ((uint32_t)0x00000301)
#define | CAN_FLAG_BOF ((uint32_t)0x00000302)
#define | CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)
#define | CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)
#define | CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)
#define | CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)
#define | CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)
#define | CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)
#define | CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)
#define | CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)
#define | CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)
#define | CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)
#define | CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)
#define | CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)
#define | CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)
#define | CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)
#define | CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define | CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define | CAN_TXMAILBOX_2 ((uint8_t)0x02)
#define | __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
Reset CAN handle state.
#define | __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable the specified CAN interrupt.
#define | __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable the specified CAN interrupt.
#define | __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__)
Return the number of pending received messages.
#define | __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified CAN flag is set or not.
#define | __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified CAN pending flag.
#define | __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified CAN interrupt source is enabled or not.
#define | __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)
Check the transmission status of a CAN Frame.
#define | __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__)
Release the specified receive FIFO.
#define | __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)
Cancel a transmit request.
#define | __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__)
Enable or disable the DBG Freeze for CAN.
#define | CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04)
#define | CAN_FLAG_MASK ((uint32_t)0x000000FF)
#define | IS_CAN_MODE(MODE)
#define | IS_CAN_SJW(SJW)
#define | IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define | IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define | IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
#define | IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
#define | IS_CAN_FILTER_MODE(MODE)
#define | IS_CAN_FILTER_SCALE(SCALE)
#define | IS_CAN_FILTER_FIFO(FIFO)
#define | IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
#define | IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define | IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
#define | IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
#define | IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define | IS_CAN_IDTYPE(IDTYPE)
#define | IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define | IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Enumerations

enum HAL_CAN_StateTypeDef {
HAL_CAN_STATE_RESET = 0x00, HAL_CAN_STATE_READY = 0x01, HAL_CAN_STATE_BUSY = 0x02, HAL_CAN_STATE_BUSY_TX = 0x12,
HAL_CAN_STATE_BUSY_RX = 0x22, HAL_CAN_STATE_BUSY_TX_RX = 0x32, HAL_CAN_STATE_TIMEOUT = 0x03, HAL_CAN_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initialize the CAN peripheral according to the specified parameters in the CAN_InitStruct structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configure the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
DeInitialize the CAN peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initialize the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitialize the CAN MSP.
HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiate and transmit a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiate and transmit a CAN frame message in Interrupt mode.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receive a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receive a correct CAN frame in Interrupt mode.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enter the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wake up the CAN peripheral from sleep mode (after that the CAN peripheral is in the normal mode).
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handle CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non-blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Reception complete callback in non-blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.
HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
Return the CAN handle state.

Detailed Description

Header file of CAN HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_can.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_comp.h File Reference

  • File List
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  • Drivers
  • STM32L4xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32l4xx_hal_comp.h File Reference

Header file of COMP HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)
HAL COMP state machine: HAL COMP states definition.
#define | COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000)
#define | COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)
#define | COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000)
#define | COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)
#define | COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE)
#define | COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000)
#define | COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)
#define | COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 )
#define | COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_HYSTERESIS_NONE ((uint32_t)0x00000000)
#define | COMP_HYSTERESIS_LOW (COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1)
#define | COMP_HYSTERESIS_HIGH (COMP_CSR_HYST)
#define | COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)
#define | COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000)
#define | COMP_BLANKINGSRC_TIM1_OC5_COMP1 (COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC3_COMP1 (COMP_CSR_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM3_OC3_COMP1 (COMP_CSR_BLANKING_2)
#define | COMP_BLANKINGSRC_TIM3_OC4_COMP2 (COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_1)
#define | COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2)
#define | COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)
#define | COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)
#define | COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
Reset COMP handle state.
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
Check whether the specified comparator is locked.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI flag.
#define | COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM21)
#define | COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM22)
#define | COMP_EXTI_IT ((uint32_t) 0x01)
#define | COMP_EXTI_EVENT ((uint32_t) 0x02)
#define | COMP_EXTI_RISING ((uint32_t) 0x10)
#define | COMP_EXTI_FALLING ((uint32_t) 0x20)
#define | COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.
#define | IS_COMP_WINDOWMODE(__WINDOWMODE__)
#define | IS_COMP_POWERMODE(__POWERMODE__)
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__SOURCE__)
#define | IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__)
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.

Detailed Description

Header file of COMP HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_comp.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cortex.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_hal_cortex.h File Reference

Header file of CORTEX HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MPU_Region_InitTypeDef

Defines

#define | NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007)
#define | NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006)
#define | NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005)
#define | NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004)
#define | NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define | MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define | MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define | MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Set the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.
__STATIC_INLINE void | HAL_MPU_Disable (void)
Disable the MPU.
__STATIC_INLINE void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Get the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Get the priority of an interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Get active interrupt (read the active register in NVIC and return the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

Header file of CORTEX HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_cortex.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_crc.h File Reference

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stm32l4xx_hal_crc.h File Reference

Header file of CRC HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_crc_ex.h"

Go to the source code of this file.

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Defines

#define | DEFAULT_CRC32_POLY 0x04C11DB7
#define | DEFAULT_CRC_INITVALUE 0xFFFFFFFF
#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)
#define | CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
#define | CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define | CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define | CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
#define | HAL_CRC_LENGTH_32B 32
#define | HAL_CRC_LENGTH_16B 16
#define | HAL_CRC_LENGTH_8B 8
#define | HAL_CRC_LENGTH_7B 7
#define | CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
#define | CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
#define | CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
#define | CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)
#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store a 8-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the 8-bit data stored in the Independent Data(ID) register.
#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00, HAL_CRC_STATE_READY = 0x01, HAL_CRC_STATE_BUSY = 0x02, HAL_CRC_STATE_TIMEOUT = 0x03,
HAL_CRC_STATE_ERROR = 0x04
}
CRC HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Header file of CRC HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_crc.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_crc_ex.h File Reference

  • File List
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  • Drivers
  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_hal_crc_ex.h File Reference

Header file of CRC HAL extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
#define | CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define | CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define | CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
#define | CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)
#define | CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.
#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Header file of CRC HAL extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_crc_ex.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cryp.h File Reference

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stm32l4xx_hal_cryp.h File Reference

Header file of CRYP HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_cryp_ex.h"

Go to the source code of this file.

Data Structures

struct | CRYP_InitTypeDef
CRYP Configuration Structure definition. More...
struct | CRYP_HandleTypeDef
CRYP handle Structure definition. More...

Defines

#define | HAL_CRYP_ERROR_NONE ((uint32_t)0x00000000)
HAL CRYP Error Codes definition.
#define | HAL_CRYP_WRITE_ERROR ((uint32_t)0x00000001)
#define | HAL_CRYP_READ_ERROR ((uint32_t)0x00000002)
#define | HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004)
#define | HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008)
#define | CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
#define | CRYP_KEYSIZE_256B AES_CR_KEYSIZE
#define | CRYP_DATATYPE_32B ((uint32_t)0x00000000)
#define | CRYP_DATATYPE_16B AES_CR_DATATYPE_0
#define | CRYP_DATATYPE_8B AES_CR_DATATYPE_1
#define | CRYP_DATATYPE_1B AES_CR_DATATYPE
#define | CRYP_AES_DISABLE ((uint32_t)0x00000000)
#define | CRYP_AES_ENABLE AES_CR_EN
#define | CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000)
#define | CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0
#define | CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1
#define | CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
#define | CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000)
#define | CRYP_CHAINMODE_AES_ECB ((uint32_t)0x00000000)
#define | CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0
#define | CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1
#define | CRYP_CHAINMODE_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1)
#define | CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2
#define | CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000)
#define | CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001)
#define | CRYP_DMAIN_DISABLE ((uint32_t)0x00000000)
#define | CRYP_DMAIN_ENABLE AES_CR_DMAINEN
#define | CRYP_DMAOUT_DISABLE ((uint32_t)0x00000000)
#define | CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN
#define | CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000)
#define | CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0
#define | CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1
#define | CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH
#define | CRYP_FLAG_BUSY AES_SR_BUSY
#define | CRYP_FLAG_WRERR AES_SR_WRERR
#define | CRYP_FLAG_RDERR AES_SR_RDERR
#define | CRYP_FLAG_CCF AES_SR_CCF
#define | CRYP_CCF_CLEAR AES_CR_CCFC
#define | CRYP_ERR_CLEAR AES_CR_ERRC
#define | CRYP_IT_CCFIE AES_CR_CCFIE
#define | CRYP_IT_ERRIE AES_CR_ERRIE
#define | CRYP_IT_WRERR AES_SR_WRERR
#define | CRYP_IT_RDERR AES_SR_RDERR
#define | CRYP_IT_CCF AES_SR_CCF
#define | __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
Reset CRYP handle state.
#define | __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN)
Enable the CRYP AES peripheral.
#define | __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN)
Disable the CRYP AES peripheral.
#define | __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))
Set the algorithm operating mode.
#define | __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
Set the algorithm chaining mode.
#define | __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified CRYP status flag is set or not.
#define | __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))
Clear the CRYP pending status flag.
#define | __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt source is enabled or not.
#define | __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt is set or not.
#define | __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))
Clear the CRYP pending interrupt.
#define | __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
Enable the CRYP interrupt.
#define | __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
Disable the CRYP interrupt.
#define | IS_CRYP_KEYSIZE(__KEYSIZE__)
Verify the key size length.
#define | IS_CRYP_DATATYPE(__DATATYPE__)
Verify the input data type.
#define | IS_CRYP_AES(__MODE__)
Verify the CRYP AES IP running mode.
#define | IS_CRYP_ALGOMODE(__ALGOMODE__)
Verify the selected CRYP algorithm.
#define | IS_CRYP_CHAINMODE(__CHAINMODE__)
Verify the selected CRYP chaining algorithm.
#define | IS_CRYP_WRITE(__WRITE__)
Verify the deciphering key write option.
#define | IS_CRYP_DMAIN(__MODE__)
Verify the CRYP input data DMA mode.
#define | IS_CRYP_DMAOUT(__MODE__)
Verify the CRYP output data DMA mode.
#define | IS_CRYP_GCMCMAC_PHASE(__PHASE__)
Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.

Enumerations

enum HAL_CRYP_STATETypeDef {
HAL_CRYP_STATE_RESET = 0x00, HAL_CRYP_STATE_READY = 0x01, HAL_CRYP_STATE_BUSY = 0x02, HAL_CRYP_STATE_TIMEOUT = 0x03,
HAL_CRYP_STATE_ERROR = 0x04, HAL_CRYP_STATE_SUSPENDED = 0x05
}
HAL CRYP State structures definition. More...
enum HAL_PhaseTypeDef {
HAL_CRYP_PHASE_READY = 0x01, HAL_CRYP_PHASE_PROCESS = 0x02, HAL_CRYP_PHASE_START = 0x03, HAL_CRYP_PHASE_INIT_OVER = 0x04,
HAL_CRYP_PHASE_HEADER_OVER = 0x05, HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, HAL_CRYP_PHASE_FINAL_OVER = 0x07, HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08,
HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, HAL_CRYP_PHASE_NOT_USED = 0x0a
}
HAL CRYP phase structures definition. More...
enum | HAL_SuspendTypeDef { HAL_CRYP_SUSPEND_NONE = 0x00, HAL_CRYP_SUSPEND = 0x01 }
HAL CRYP mode suspend definitions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initialize the CRYP according to the specified parameters in the CRYP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
DeInitialize the CRYP peripheral.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initialize the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitialize CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Encrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
Encrypt pPlainData in AES ECB encryption mode.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Decrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
Decrypt pCypherData in AES ECB decryption mode with key derivation, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Encrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
Encrypt pPlainData in AES CBC encryption mode with key derivation.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Decrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
Decrypt pCypherData in AES ECB decryption mode with key derivation, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Encrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
Encrypt pPlainData in AES CTR encryption mode.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Decrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
Decrypt pCypherData in AES CTR decryption mode, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES ECB encryption mode using Interrupt, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CBC encryption mode using Interrupt, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CTR encryption mode using Interrupt, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES ECB decryption mode using Interrupt, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CTR decryption mode using Interrupt, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CBC decryption mode using Interrupt, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES ECB encryption mode using DMA, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES ECB decryption mode using DMA, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CBC encryption mode using DMA, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CBC decryption mode using DMA, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CTR encryption mode using DMA, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CTR decryption mode using DMA, the decyphered data are available in pPlainData.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input DMA transfer complete callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output DMA transfer complete callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.
void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
Handle AES interrupt request.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Return the CRYP handle state.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP peripheral error.

Detailed Description

Header file of CRYP HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_cryp.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cryp_ex.h File Reference

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Functions
stm32l4xx_hal_cryp_ex.h File Reference

Header file of CRYPEx HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Functions

__weak void | HAL_CRYPEx_ComputationCpltCallback (CRYP_HandleTypeDef *hcryp)
Computation completed callbacks.
HAL_StatusTypeDef | HAL_CRYPEx_AES (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout)
Carry out in polling mode the ciphering or deciphering operation according to hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and chaining modes ECB, CBC and CTR are managed by this function in polling mode.
HAL_StatusTypeDef | HAL_CRYPEx_AES_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
Carry out in interrupt mode the ciphering or deciphering operation according to hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and chaining modes ECB, CBC and CTR are managed by this function in interrupt mode.
HAL_StatusTypeDef | HAL_CRYPEx_AES_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
Carry out in DMA mode the ciphering or deciphering operation according to hcryp->Init structure fields.
HAL_StatusTypeDef | HAL_CRYPEx_AES_Auth (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout)
Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.
HAL_StatusTypeDef | HAL_CRYPEx_AES_Auth_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.
HAL_StatusTypeDef | HAL_CRYPEx_AES_Auth_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.
void | HAL_CRYPEx_Read_IVRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Output)
In case of message processing suspension, read the Initialization Vector.
void | HAL_CRYPEx_Write_IVRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Input)
In case of message processing resumption, rewrite the Initialization Vector in the AES_IVRx registers.
void | HAL_CRYPEx_Read_SuspendRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Output)
In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers.
void | HAL_CRYPEx_Write_SuspendRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Input)
In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend Registers in the AES_SUSPxR registers.
void | HAL_CRYPEx_Read_KeyRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Output, uint32_t KeySize)
In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers.
void | HAL_CRYPEx_Write_KeyRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint32_t KeySize)
In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key Registers in the AES_KEYRx registers.
void | HAL_CRYPEx_Read_ControlRegister (CRYP_HandleTypeDef *hcryp, uint8_t *Output)
In case of message GCM/GMAC or CMAC processing suspension, read the Control Register.
void | HAL_CRYPEx_Write_ControlRegister (CRYP_HandleTypeDef *hcryp, uint8_t *Input)
In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control Registers in the AES_CR register.
void | HAL_CRYPEx_ProcessSuspend (CRYP_HandleTypeDef *hcryp)
Request CRYP processing suspension when in polling or interruption mode.
HAL_StatusTypeDef | CRYP_AES_Auth_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption for GCM, GMAC or CMAC chainging modes.

Detailed Description

Header file of CRYPEx HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_cryp_ex.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dac.h File Reference

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stm32l4xx_hal_dac.h File Reference

Header file of DAC HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_dac_ex.h"

Go to the source code of this file.

Data Structures

struct | DAC_HandleTypeDef
DAC handle Structure definition. More...
struct | DAC_SampleAndHoldConfTypeDef
DAC Configuration sample and hold Channel structure definition. More...
struct | DAC_ChannelConfTypeDef
DAC Configuration regular Channel structure definition. More...

Defines

#define | HAL_DAC_ERROR_NONE 0x00
#define | HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01
#define | HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02
#define | HAL_DAC_ERROR_DMA 0x04
#define | HAL_DAC_ERROR_TIMEOUT 0x08
#define | DAC_TRIGGER_NONE ((uint32_t)0x00000000)
#define | DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1)
#define | DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1))
#define | DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1))
#define | DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1))
#define | DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define | DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1)
#define | DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define | DAC_CHANNEL_2 ((uint32_t)0x00000010)
#define | DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define | DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define | DAC_ALIGN_8B_R ((uint32_t)0x00000008)
#define | DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define | DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define | DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define | DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000)
#define | DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0)
#define | DAC_TRIMMING_FACTORY ((uint32_t)0x00000000)
#define | DAC_TRIMMING_USER ((uint32_t)0x00000001)
#define | DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000)
#define | DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2)
#define | __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
Reset DAC handle state.
#define | __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
Enable the DAC channel.
#define | __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
Disable the DAC channel.
#define | DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
Set DHR12R1 alignment.
#define | DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
Set DHR12R2 alignment.
#define | DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
Set DHR12RD alignment.
#define | __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the DAC interrupt.
#define | __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the DAC interrupt.
#define | __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified DAC interrupt source is enabled or not.
#define | __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected DAC's flag status.
#define | __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
Clear the DAC's flag.
#define | IS_DAC_OUTPUT_BUFFER_STATE(STATE)
#define | IS_DAC_CHANNEL(CHANNEL)
#define | IS_DAC_ALIGN(ALIGN)
#define | IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define | IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x0000000FF)

Enumerations

enum HAL_DAC_StateTypeDef {
HAL_DAC_STATE_RESET = 0x00, HAL_DAC_STATE_READY = 0x01, HAL_DAC_STATE_BUSY = 0x02, HAL_DAC_STATE_TIMEOUT = 0x03,
HAL_DAC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

Header file of DAC HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_dac.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dac_ex.h File Reference

  • File List
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  • Drivers
  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_hal_dac_ex.h File Reference

Header file of DAC HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000)
#define | DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000)
#define | DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2)
#define | DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3)
#define | DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1)
#define | DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | IS_DAC_TRIGGER(TRIGGER)
#define | IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
#define | IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x0000003FF)
#define | IS_DAC_SAMPLEANDHOLD(MODE)
#define | IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_DAC_CHIP_CONNECTION(CONNECT)
#define | IS_DAC_TRIMMING(TRIMMING)
#define | IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)

Functions

HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.

Detailed Description

Header file of DAC HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_dac_ex.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dfsdm.h File Reference

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  • STM32L4xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32l4xx_hal_dfsdm.h File Reference

Header file of DFSDM HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | DFSDM_Channel_OutputClockTypeDef
DFSDM channel output clock structure definition. More...
struct | DFSDM_Channel_InputTypeDef
DFSDM channel input structure definition. More...
struct | DFSDM_Channel_SerialInterfaceTypeDef
DFSDM channel serial interface structure definition. More...
struct | DFSDM_Channel_AwdTypeDef
DFSDM channel analog watchdog structure definition. More...
struct | DFSDM_Channel_InitTypeDef
DFSDM channel init structure definition. More...
struct | DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition. More...
struct | DFSDM_Filter_RegularParamTypeDef
DFSDM filter regular conversion parameters structure definition. More...
struct | DFSDM_Filter_InjectedParamTypeDef
DFSDM filter injected conversion parameters structure definition. More...
struct | DFSDM_Filter_FilterParamTypeDef
DFSDM filter parameters structure definition. More...
struct | DFSDM_Filter_InitTypeDef
DFSDM filter init structure definition. More...
struct | DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition. More...
struct | DFSDM_Filter_AwdParamTypeDef
DFSDM filter analog watchdog parameters structure definition. More...

Defines

#define | DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC
#define | DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1
#define | DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0
#define | DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1
#define | DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL
#define | DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0
#define | DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1
#define | DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP
#define | DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1
#define | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL
#define | DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U)
#define | DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0
#define | DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1
#define | DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD
#define | DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U)
#define | DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U)
#define | DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U)
#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U)
#define | DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
#define | DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
#define | DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2
#define | DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2
#define | DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2)
#define | DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL
#define | DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0
#define | DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1
#define | DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN
#define | DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U)
#define | DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0
#define | DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1
#define | DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)
#define | DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2
#define | DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)
#define | DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U)
#define | DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL
#define | DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U)
#define | DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U)
#define | DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U)
#define | DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U)
#define | DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U)
#define | DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U)
#define | DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U)
#define | DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U)
#define | DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U)
#define | DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
#define | DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
#define | DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
#define | DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
#define | DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)
#define | DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
#define | DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
#define | DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)
#define | DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U)
#define | DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U)
#define | DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U)
#define | DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U)
#define | __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
Reset DFSDM channel handle state.
#define | __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
Reset DFSDM filter handle state.
#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)
#define | IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
#define | IS_DFSDM_CHANNEL_INPUT(INPUT)
#define | IS_DFSDM_CHANNEL_DATA_PACKING(MODE)
#define | IS_DFSDM_CHANNEL_INPUT_PINS(PINS)
#define | IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)
#define | IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)
#define | IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)
#define | IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
#define | IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
#define | IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
#define | IS_DFSDM_FILTER_REG_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG(TRIG)
#define | IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)
#define | IS_DFSDM_FILTER_SINC_ORDER(ORDER)
#define | IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
#define | IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
#define | IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)
#define | IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define | IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
#define | IS_DFSDM_REGULAR_CHANNEL(CHANNEL)
#define | IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
#define | IS_DFSDM_CONTINUOUS_MODE(MODE)

Enumerations

enum | HAL_DFSDM_Channel_StateTypeDef { HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU }
HAL DFSDM Channel states definition. More...
enum HAL_DFSDM_Filter_StateTypeDef {
HAL_DFSDM_FILTER_STATE_RESET = 0x00U, HAL_DFSDM_FILTER_STATE_READY = 0x01U, HAL_DFSDM_FILTER_STATE_REG = 0x02U, HAL_DFSDM_FILTER_STATE_INJ = 0x03U,
HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU
}
HAL DFSDM Filter states definition. More...

Functions

HAL_StatusTypeDef | HAL_DFSDM_ChannelInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_ChannelDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
__weak void | HAL_DFSDM_ChannelMspInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
__weak void | HAL_DFSDM_ChannelMspDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
int16_t | HAL_DFSDM_ChannelGetAwdValue (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelModifyOffset (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForCkab (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForScd (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
__weak void | HAL_DFSDM_ChannelCkabCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
__weak void | HAL_DFSDM_ChannelScdCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
HAL_DFSDM_Channel_StateTypeDef | HAL_DFSDM_ChannelGetState (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.
HAL_StatusTypeDef | HAL_DFSDM_FilterInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_FilterDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
__weak void | HAL_DFSDM_FilterMspInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
__weak void | HAL_DFSDM_FilterMspDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigRegChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigInjChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
int32_t | HAL_DFSDM_FilterGetRegularValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
int32_t | HAL_DFSDM_FilterGetInjectedValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
int32_t | HAL_DFSDM_FilterGetExdMaxValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
int32_t | HAL_DFSDM_FilterGetExdMinValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
uint32_t | HAL_DFSDM_FilterGetConvTimeValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
void | HAL_DFSDM_IRQHandler (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForRegConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForInjConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
__weak void | HAL_DFSDM_FilterRegConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
__weak void | HAL_DFSDM_FilterRegConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
__weak void | HAL_DFSDM_FilterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
__weak void | HAL_DFSDM_FilterErrorCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.
HAL_DFSDM_Filter_StateTypeDef | HAL_DFSDM_FilterGetState (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
uint32_t | HAL_DFSDM_FilterGetError (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.

Detailed Description

Header file of DFSDM HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_dfsdm.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dma.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32l4xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Defines

#define | HAL_DMA_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_DMA_ERROR_TE ((uint32_t)0x00000001)
#define | HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004)
#define | HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020)
#define | HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100)
#define | DMA_REQUEST_0 ((uint32_t)0x00000000)
#define | DMA_REQUEST_1 ((uint32_t)0x00000001)
#define | DMA_REQUEST_2 ((uint32_t)0x00000002)
#define | DMA_REQUEST_3 ((uint32_t)0x00000003)
#define | DMA_REQUEST_4 ((uint32_t)0x00000004)
#define | DMA_REQUEST_5 ((uint32_t)0x00000005)
#define | DMA_REQUEST_6 ((uint32_t)0x00000006)
#define | DMA_REQUEST_7 ((uint32_t)0x00000007)
#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000)
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)
#define | DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000)
#define | DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000)
#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000)
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)
#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000)
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)
#define | DMA_NORMAL ((uint32_t)0x00000000)
#define | DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)
#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000)
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)
#define | DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
#define | DMA_FLAG_GL1 ((uint32_t)0x00000001)
#define | DMA_FLAG_TC1 ((uint32_t)0x00000002)
#define | DMA_FLAG_HT1 ((uint32_t)0x00000004)
#define | DMA_FLAG_TE1 ((uint32_t)0x00000008)
#define | DMA_FLAG_GL2 ((uint32_t)0x00000010)
#define | DMA_FLAG_TC2 ((uint32_t)0x00000020)
#define | DMA_FLAG_HT2 ((uint32_t)0x00000040)
#define | DMA_FLAG_TE2 ((uint32_t)0x00000080)
#define | DMA_FLAG_GL3 ((uint32_t)0x00000100)
#define | DMA_FLAG_TC3 ((uint32_t)0x00000200)
#define | DMA_FLAG_HT3 ((uint32_t)0x00000400)
#define | DMA_FLAG_TE3 ((uint32_t)0x00000800)
#define | DMA_FLAG_GL4 ((uint32_t)0x00001000)
#define | DMA_FLAG_TC4 ((uint32_t)0x00002000)
#define | DMA_FLAG_HT4 ((uint32_t)0x00004000)
#define | DMA_FLAG_TE4 ((uint32_t)0x00008000)
#define | DMA_FLAG_GL5 ((uint32_t)0x00010000)
#define | DMA_FLAG_TC5 ((uint32_t)0x00020000)
#define | DMA_FLAG_HT5 ((uint32_t)0x00040000)
#define | DMA_FLAG_TE5 ((uint32_t)0x00080000)
#define | DMA_FLAG_GL6 ((uint32_t)0x00100000)
#define | DMA_FLAG_TC6 ((uint32_t)0x00200000)
#define | DMA_FLAG_HT6 ((uint32_t)0x00400000)
#define | DMA_FLAG_TE6 ((uint32_t)0x00800000)
#define | DMA_FLAG_GL7 ((uint32_t)0x01000000)
#define | DMA_FLAG_TC7 ((uint32_t)0x02000000)
#define | DMA_FLAG_HT7 ((uint32_t)0x04000000)
#define | DMA_FLAG_TE7 ((uint32_t)0x08000000)
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Channel pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enable the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disable the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Check whether the specified DMA Channel interrupt is enabled or not.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Return the number of remaining data units in the current DMA Channel transfer.
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_ALL_REQUEST(REQUEST)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00, HAL_DMA_STATE_READY = 0x01, HAL_DMA_STATE_BUSY = 0x02, HAL_DMA_STATE_TIMEOUT = 0x03 }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00, HAL_DMA_HALF_TRANSFER = 0x01 }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, HAL_DMA_XFER_ERROR_CB_ID = 0x02, HAL_DMA_XFER_ABORT_CB_ID = 0x03,
HAL_DMA_XFER_ALL_CB_ID = 0x04
}
HAL DMA Callback ID structure definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA hande state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_dma.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_firewall.h File Reference

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stm32l4xx_hal_firewall.h File Reference

Header file of FIREWALL HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FIREWALL_InitTypeDef
FIREWALL Initialization Structure definition. More...

Defines

#define | FIREWALL_VOLATILEDATA_NOT_EXECUTABLE ((uint32_t)0x0000)
#define | FIREWALL_VOLATILEDATA_EXECUTABLE ((uint32_t)FW_CR_VDE)
#define | FIREWALL_VOLATILEDATA_NOT_SHARED ((uint32_t)0x0000)
#define | FIREWALL_VOLATILEDATA_SHARED ((uint32_t)FW_CR_VDS)
#define | FIREWALL_PRE_ARM_RESET ((uint32_t)0x0000)
#define | FIREWALL_PRE_ARM_SET ((uint32_t)FW_CR_FPA)
#define | IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
#define | IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
#define | IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
#define | IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
#define | IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= SRAM1_BASE) && ((ADDRESS) < (SRAM1_BASE + SRAM1_SIZE_MAX)))
#define | IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM1_BASE + SRAM1_SIZE_MAX))
#define | IS_FIREWALL_VOLATILEDATA_SHARE(SHARE)
#define | IS_FIREWALL_VOLATILEDATA_EXECUTE(EXECUTE)
#define | __HAL_FIREWALL_IS_ENABLED() HAL_IS_BIT_CLR(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS)
Check whether the FIREWALL is enabled or not.
#define | __HAL_FIREWALL_PREARM_ENABLE()
Enable FIREWALL pre arm.
#define | __HAL_FIREWALL_PREARM_DISABLE()
Disable FIREWALL pre arm.
#define | __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE()
Enable volatile data sharing in setting VDS bit.
#define | __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE()
Disable volatile data sharing in resetting VDS bit.
#define | __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE()
Enable volatile data execution in setting VDE bit.
#define | __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE()
Disable volatile data execution in resetting VDE bit.
#define | __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FIREWALL->CR & FW_CR_VDS) == FW_CR_VDS)
Check whether or not the volatile data segment is shared.
#define | __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FIREWALL->CR & FW_CR_VDE) == FW_CR_VDE)
Check whether or not the volatile data segment is declared executable.
#define | __HAL_FIREWALL_GET_PREARM() ((FIREWALL->CR & FW_CR_FPA) == FW_CR_FPA)
Check whether or not the Firewall pre arm bit is set.

Functions

HAL_StatusTypeDef | HAL_FIREWALL_Config (FIREWALL_InitTypeDef *fw_init)
Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters.
void | HAL_FIREWALL_GetConfig (FIREWALL_InitTypeDef *fw_config)
Retrieve the Firewall configuration.
void | HAL_FIREWALL_EnableFirewall (void)
Enable FIREWALL.
void | HAL_FIREWALL_EnablePreArmFlag (void)
Enable FIREWALL pre arm.
void | HAL_FIREWALL_DisablePreArmFlag (void)
Disable FIREWALL pre arm.

Detailed Description

Header file of FIREWALL HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_firewall.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash.h File Reference

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stm32l4xx_hal_flash.h File Reference

Header file of FLASH HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_flash_ex.h"
#include "stm32l4xx_hal_flash_ramfunc.h"

Go to the source code of this file.

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Defines

#define | HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_FLASH_ERROR_OP ((uint32_t)0x00000001)
#define | HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002)
#define | HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004)
#define | HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)
#define | HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010)
#define | HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020)
#define | HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040)
#define | HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080)
#define | HAL_FLASH_ERROR_RD ((uint32_t)0x00000100)
#define | HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200)
#define | HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400)
#define | FLASH_TYPEERASE_PAGES ((uint32_t)0x00)
#define | FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)
#define | FLASH_BANK_1 ((uint32_t)0x01)
#define | FLASH_BANK_2 ((uint32_t)0x02)
#define | FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2))
#define | FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00)
#define | FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01)
#define | FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02)
#define | OPTIONBYTE_WRP ((uint32_t)0x01)
#define | OPTIONBYTE_RDP ((uint32_t)0x02)
#define | OPTIONBYTE_USER ((uint32_t)0x04)
#define | OPTIONBYTE_PCROP ((uint32_t)0x08)
#define | OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00)
#define | OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01)
#define | OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02)
#define | OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04)
#define | OB_RDP_LEVEL_0 ((uint32_t)0xAA)
#define | OB_RDP_LEVEL_1 ((uint32_t)0xBB)
#define | OB_RDP_LEVEL_2 ((uint32_t)0xCC)
#define | OB_USER_BOR_LEV ((uint32_t)0x0001)
#define | OB_USER_nRST_STOP ((uint32_t)0x0002)
#define | OB_USER_nRST_STDBY ((uint32_t)0x0004)
#define | OB_USER_IWDG_SW ((uint32_t)0x0008)
#define | OB_USER_IWDG_STOP ((uint32_t)0x0010)
#define | OB_USER_IWDG_STDBY ((uint32_t)0x0020)
#define | OB_USER_WWDG_SW ((uint32_t)0x0040)
#define | OB_USER_BFB2 ((uint32_t)0x0080)
#define | OB_USER_DUALBANK ((uint32_t)0x0100)
#define | OB_USER_nBOOT1 ((uint32_t)0x0200)
#define | OB_USER_SRAM2_PE ((uint32_t)0x0400)
#define | OB_USER_SRAM2_RST ((uint32_t)0x0800)
#define | OB_USER_nRST_SHDW ((uint32_t)0x1000)
#define | OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0)
#define | OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1)
#define | OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2)
#define | OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3)
#define | OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4)
#define | OB_STOP_RST ((uint32_t)0x0000)
#define | OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP)
#define | OB_STANDBY_RST ((uint32_t)0x0000)
#define | OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY)
#define | OB_SHUTDOWN_RST ((uint32_t)0x0000)
#define | OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW)
#define | OB_IWDG_HW ((uint32_t)0x00000)
#define | OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW)
#define | OB_IWDG_STOP_FREEZE ((uint32_t)0x00000)
#define | OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP)
#define | OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000)
#define | OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY)
#define | OB_WWDG_HW ((uint32_t)0x00000)
#define | OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW)
#define | OB_BFB2_DISABLE ((uint32_t)0x000000)
#define | OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2)
#define | OB_DUALBANK_SINGLE ((uint32_t)0x000000)
#define | OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK)
#define | OB_BOOT1_SRAM ((uint32_t)0x000000)
#define | OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1)
#define | OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000)
#define | OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE)
#define | OB_SRAM2_RST_ERASE ((uint32_t)0x0000000)
#define | OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST)
#define | OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000)
#define | OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP)
#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
#define | FLASH_KEY1 ((uint32_t)0x45670123U)
#define | FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
#define | FLASH_PDKEY1 ((uint32_t)0x04152637U)
#define | FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU)
#define | FLASH_OPTKEY1 ((uint32_t)0x08192A3BU)
#define | FLASH_OPTKEY2 ((uint32_t)0x4C5D6E7FU)
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPERR FLASH_SR_OPERR
#define | FLASH_FLAG_PROGERR FLASH_SR_PROGERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_SIZERR FLASH_SR_SIZERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_MISERR FLASH_SR_MISERR
#define | FLASH_FLAG_FASTERR FLASH_SR_FASTERR
#define | FLASH_FLAG_RDERR FLASH_SR_RDERR
#define | FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_ECCC FLASH_ECCR_ECCC
#define | FLASH_FLAG_ECCD FLASH_ECCR_ECCD
#define | FLASH_FLAG_ALL_ERRORS
#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_OPERR FLASH_CR_ERRIE
#define | FLASH_IT_RDERR FLASH_CR_RDERRIE
#define | FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24)
#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Enable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Disable the FLASH instruction cache.
#define | __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Enable the FLASH data cache.
#define | __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Disable the FLASH data cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_RESET()
Reset the FLASH instruction Cache.
#define | __HAL_FLASH_DATA_CACHE_RESET()
Reset the FLASH data Cache.
#define | __HAL_FLASH_POWER_DOWN_ENABLE()
Enable the FLASH power down during Low-power run mode.
#define | __HAL_FLASH_POWER_DOWN_DISABLE()
Disable the FLASH power down during Low-power run mode.
#define | __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Enable the FLASH power down during Low-Power sleep mode.
#define | __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Disable the FLASH power down during Low-Power sleep mode.
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
Check whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the FLASH's pending flags.
#define | FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
#define | FLASH_SIZE
#define | FLASH_BANK_SIZE (FLASH_SIZE >> 1)
#define | FLASH_PAGE_SIZE ((uint32_t)0x800)
#define | FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
#define | IS_FLASH_TYPEERASE(VALUE)
#define | IS_FLASH_BANK(BANK)
#define | IS_FLASH_BANK_EXCLUSIVE(BANK)
#define | IS_FLASH_TYPEPROGRAM(VALUE)
#define | IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)
#define | IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
#define | IS_FLASH_PAGE(PAGE)
#define | IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
#define | IS_OB_WRPAREA(VALUE)
#define | IS_OB_RDP_LEVEL(LEVEL)
#define | IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
#define | IS_OB_USER_BOR_LEVEL(LEVEL)
#define | IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
#define | IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
#define | IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
#define | IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
#define | IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
#define | IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
#define | IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
#define | IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
#define | IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
#define | IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
#define | IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
#define | IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
#define | IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
#define | IS_FLASH_LATENCY(LATENCY)

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0, FLASH_PROC_PAGE_ERASE, FLASH_PROC_MASS_ERASE, FLASH_PROC_PROGRAM,
FLASH_PROC_PROGRAM_LAST
}
FLASH Procedure structure definition. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Detailed Description

Header file of FLASH HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_flash.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash_ex.h File Reference

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Functions
stm32l4xx_hal_flash_ex.h File Reference

Header file of FLASH HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.

Detailed Description

Header file of FLASH HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_flash_ex.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash_ramfunc.h File Reference

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Functions
stm32l4xx_hal_flash_ramfunc.h File Reference

Header file of FLASH RAMFUNC driver. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Functions

__RAM_FUNC | HAL_FLASHEx_EnableRunPowerDown (void)
Enable the Power down in Run Mode.
__RAM_FUNC | HAL_FLASHEx_DisableRunPowerDown (void)
Disable the Power down in Run Mode.

Detailed Description

Header file of FLASH RAMFUNC driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_flash_ramfunc.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_gpio.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32l4xx_hal_gpio.h File Reference

Header file of GPIO HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_gpio_ex.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
#define | GPIO_MODE_INPUT ((uint32_t)0x00000000)
#define | GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001)
#define | GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011)
#define | GPIO_MODE_AF_PP ((uint32_t)0x00000002)
#define | GPIO_MODE_AF_OD ((uint32_t)0x00000012)
#define | GPIO_MODE_ANALOG ((uint32_t)0x00000003)
#define | GPIO_MODE_ANALOG_ADC_CONTROL ((uint32_t)0x0000000B)
#define | GPIO_MODE_IT_RISING ((uint32_t)0x10110000)
#define | GPIO_MODE_IT_FALLING ((uint32_t)0x10210000)
#define | GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000)
#define | GPIO_MODE_EVT_RISING ((uint32_t)0x10120000)
#define | GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000)
#define | GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000)
#define | GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000)
#define | GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001)
#define | GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002)
#define | GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003)
#define | GPIO_NOPULL ((uint32_t)0x00000000)
#define | GPIO_PULLUP ((uint32_t)0x00000001)
#define | GPIO_PULLDOWN ((uint32_t)0x00000002)
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generate a Software interrupt on selected EXTI line.
#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
#define | IS_GPIO_MODE(__MODE__)
#define | IS_GPIO_SPEED(__SPEED__)
#define | IS_GPIO_PULL(__PULL__)

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

Header file of GPIO HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_gpio.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_gpio_ex.h File Reference

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Defines
stm32l4xx_hal_gpio_ex.h File Reference

Header file of GPIO HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
AF 0 selection.
#define | GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define | GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define | GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define | GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define | GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
AF 1 selection.
#define | GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define | GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
#define | GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define | GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
#define | GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
AF 2 selection.
#define | GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define | GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define | GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define | GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define | GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
AF 3 selection.
#define | GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
AF 4 selection.
#define | GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define | GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define | GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define | GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
AF 6 selection.
#define | GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
#define | GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
AF 7 selection.
#define | GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define | GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define | GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
AF 8 selection.
#define | GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define | GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#define | GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
AF 9 selection.
#define | GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */
#define | GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
AF 10 selection.
#define | GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define | GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
AF 11 selection.
#define | GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
AF 12 selection.
#define | GPIO_AF12_SWPMI1 ((uint8_t)0xC) /* SWPMI1 Alternate Function mapping */
#define | GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
#define | GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
#define | GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
#define | GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
AF 13 selection.
#define | GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */
#define | GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */
#define | GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
AF 14 selection.
#define | GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define | GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */
#define | GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */
#define | GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
#define | GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
AF 15 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#define | GPIO_GET_INDEX(__GPIOx__)

Detailed Description

Header file of GPIO HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_gpio_ex.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_hcd.h File Reference

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stm32l4xx_hal_hcd.h File Reference

Header file of HCD HAL module. More...

#include "stm32l4xx_ll_usb.h"

Go to the source code of this file.

Data Structures

struct | HCD_HandleTypeDef

Defines

#define | HCD_SPEED_HIGH 0
#define | HCD_SPEED_LOW 2
#define | HCD_SPEED_FULL 3
#define | HCD_PHY_EMBEDDED 1
#define | __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define | __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define | __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define | __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define | __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

Typedefs

typedef USB_OTG_GlobalTypeDef | HCD_TypeDef
typedef USB_OTG_CfgTypeDef | HCD_InitTypeDef
typedef USB_OTG_HCTypeDef | HCD_HCTypeDef
typedef USB_OTG_URBStateTypeDef | HCD_URBStateTypeDef
typedef USB_OTG_HCStateTypeDef | HCD_HCStateTypeDef

Enumerations

enum HCD_StateTypeDef {
HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, HAL_HCD_STATE_ERROR = 0x02, HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
}

Functions

HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the Host driver.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the Host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a Host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a Host channel.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.
HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the Host port.
HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the Host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the Host driver.
HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last Host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

Header file of HCD HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_hcd.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_i2c.h File Reference

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stm32l4xx_hal_i2c.h File Reference

Header file of I2C HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_i2c_ex.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
struct | __I2C_HandleTypeDef

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)
#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)
#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)
#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)
#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)
#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP I2C_CR2_STOP
#define | I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE I2C_CR2_START
#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE
#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR
#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified I2C interrupt source is enabled or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.
#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
#define | I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Header file of I2C HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_i2c.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_i2c_ex.h File Reference

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Defines | Functions
stm32l4xx_hal_i2c_ex.h File Reference

Header file of I2C HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from stop mode.
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Header file of I2C HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_i2c_ex.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_irda.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32l4xx_hal_irda.h File Reference

Header file of IRDA HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_irda_ex.h"

Go to the source code of this file.

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Defines

#define | IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | IRDA_PARITY_NONE ((uint32_t)0x00000000)
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define | IRDA_STATE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define | IRDA_MODE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)
#define | IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define | IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
#define | IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000)
#define | IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
#define | IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ)
#define | IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)
#define | IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)
#define | IRDA_FLAG_REACK ((uint32_t)0x00400000)
#define | IRDA_FLAG_TEACK ((uint32_t)0x00200000)
#define | IRDA_FLAG_BUSY ((uint32_t)0x00010000)
#define | IRDA_FLAG_ABRF ((uint32_t)0x00008000)
#define | IRDA_FLAG_ABRE ((uint32_t)0x00004000)
#define | IRDA_FLAG_TXE ((uint32_t)0x00000080)
#define | IRDA_FLAG_TC ((uint32_t)0x00000040)
#define | IRDA_FLAG_RXNE ((uint32_t)0x00000020)
#define | IRDA_FLAG_ORE ((uint32_t)0x00000008)
#define | IRDA_FLAG_NE ((uint32_t)0x00000004)
#define | IRDA_FLAG_FE ((uint32_t)0x00000002)
#define | IRDA_FLAG_PE ((uint32_t)0x00000001)
#define | IRDA_IT_PE ((uint16_t)0x0028)
#define | IRDA_IT_TXE ((uint16_t)0x0727)
#define | IRDA_IT_TC ((uint16_t)0x0626)
#define | IRDA_IT_RXNE ((uint16_t)0x0525)
#define | IRDA_IT_IDLE ((uint16_t)0x0424)
#define | IRDA_IT_ERR ((uint16_t)0x0060)
#define | IRDA_IT_ORE ((uint16_t)0x0300)
#define | IRDA_IT_NE ((uint16_t)0x0200)
#define | IRDA_IT_FE ((uint16_t)0x0100)
#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NCF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF
#define | IRDA_IT_MASK ((uint16_t)0x001F)
#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00U, HAL_IRDA_STATE_READY = 0x20U, HAL_IRDA_STATE_BUSY = 0x24U, HAL_IRDA_STATE_BUSY_TX = 0x21U,
HAL_IRDA_STATE_BUSY_RX = 0x22U, HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, HAL_IRDA_STATE_TIMEOUT = 0xA0U, HAL_IRDA_STATE_ERROR = 0xE0U
}
HAL IRDA State structures definition. More...
enum HAL_IRDA_ErrorTypeDef {
HAL_IRDA_ERROR_NONE = 0x00, HAL_IRDA_ERROR_PE = 0x01, HAL_IRDA_ERROR_NE = 0x02, HAL_IRDA_ERROR_FE = 0x04,
HAL_IRDA_ERROR_ORE = 0x08, HAL_IRDA_ERROR_DMA = 0x10
}
HAL IRDA Error Code structure definition. More...
enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK1 = 0x00, IRDA_CLOCKSOURCE_PCLK2 = 0x01, IRDA_CLOCKSOURCE_HSI = 0x02, IRDA_CLOCKSOURCE_SYSCLK = 0x04,
IRDA_CLOCKSOURCE_LSE = 0x08, IRDA_CLOCKSOURCE_UNDEFINED = 0x10
}
IRDA clock sources definition. More...
enum IRDA_ControlTypeDef {
IRDA_BAUDRATE = 0x00, IRDA_PARITY = 0x01, IRDA_WORDLENGTH = 0x02, IRDA_MODE = 0x03,
IRDA_PRESCALER = 0x04, IRDA_POWERMODE = 0x05
}
IRDA Configuration enumeration values definition. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

Header file of IRDA HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_irda.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_irda_ex.h File Reference

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Defines
stm32l4xx_hal_irda_ex.h File Reference

Header file of IRDA HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Defines

#define IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.

Detailed Description

Header file of IRDA HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_irda_ex.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_iwdg.h File Reference

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stm32l4xx_hal_iwdg.h File Reference

Header file of IWDG HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | IWDG_WINDOW_DISABLE IWDG_WINR_WIN
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u
#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

Header file of IWDG HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_iwdg.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_lcd.h File Reference

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stm32l4xx_hal_lcd.h File Reference

Header file of LCD Controller HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LCD_InitTypeDef
LCD Init structure definition. More...
struct | LCD_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | HAL_LCD_ERROR_NONE ((uint32_t)0x00)
#define | HAL_LCD_ERROR_FCRSF ((uint32_t)0x01)
#define | HAL_LCD_ERROR_UDR ((uint32_t)0x02)
#define | HAL_LCD_ERROR_UDD ((uint32_t)0x04)
#define | HAL_LCD_ERROR_ENS ((uint32_t)0x08)
#define | HAL_LCD_ERROR_RDY ((uint32_t)0x10)
#define | LCD_PRESCALER_1 ((uint32_t)0x00000000)
#define | LCD_PRESCALER_2 ((uint32_t)0x00400000)
#define | LCD_PRESCALER_4 ((uint32_t)0x00800000)
#define | LCD_PRESCALER_8 ((uint32_t)0x00C00000)
#define | LCD_PRESCALER_16 ((uint32_t)0x01000000)
#define | LCD_PRESCALER_32 ((uint32_t)0x01400000)
#define | LCD_PRESCALER_64 ((uint32_t)0x01800000)
#define | LCD_PRESCALER_128 ((uint32_t)0x01C00000)
#define | LCD_PRESCALER_256 ((uint32_t)0x02000000)
#define | LCD_PRESCALER_512 ((uint32_t)0x02400000)
#define | LCD_PRESCALER_1024 ((uint32_t)0x02800000)
#define | LCD_PRESCALER_2048 ((uint32_t)0x02C00000)
#define | LCD_PRESCALER_4096 ((uint32_t)0x03000000)
#define | LCD_PRESCALER_8192 ((uint32_t)0x03400000)
#define | LCD_PRESCALER_16384 ((uint32_t)0x03800000)
#define | LCD_PRESCALER_32768 ((uint32_t)0x03C00000)
#define | LCD_DIVIDER_16 ((uint32_t)0x00000000)
#define | LCD_DIVIDER_17 ((uint32_t)0x00040000)
#define | LCD_DIVIDER_18 ((uint32_t)0x00080000)
#define | LCD_DIVIDER_19 ((uint32_t)0x000C0000)
#define | LCD_DIVIDER_20 ((uint32_t)0x00100000)
#define | LCD_DIVIDER_21 ((uint32_t)0x00140000)
#define | LCD_DIVIDER_22 ((uint32_t)0x00180000)
#define | LCD_DIVIDER_23 ((uint32_t)0x001C0000)
#define | LCD_DIVIDER_24 ((uint32_t)0x00200000)
#define | LCD_DIVIDER_25 ((uint32_t)0x00240000)
#define | LCD_DIVIDER_26 ((uint32_t)0x00280000)
#define | LCD_DIVIDER_27 ((uint32_t)0x002C0000)
#define | LCD_DIVIDER_28 ((uint32_t)0x00300000)
#define | LCD_DIVIDER_29 ((uint32_t)0x00340000)
#define | LCD_DIVIDER_30 ((uint32_t)0x00380000)
#define | LCD_DIVIDER_31 ((uint32_t)0x003C0000)
#define | LCD_DUTY_STATIC ((uint32_t)0x00000000)
#define | LCD_DUTY_1_2 (LCD_CR_DUTY_0)
#define | LCD_DUTY_1_3 (LCD_CR_DUTY_1)
#define | LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0))
#define | LCD_DUTY_1_8 (LCD_CR_DUTY_2)
#define | LCD_BIAS_1_4 ((uint32_t)0x00000000)
#define | LCD_BIAS_1_2 LCD_CR_BIAS_0
#define | LCD_BIAS_1_3 LCD_CR_BIAS_1
#define | LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000)
#define | LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL
#define | LCD_IT_SOF LCD_FCR_SOFIE
#define | LCD_IT_UDD LCD_FCR_UDDIE
#define | LCD_PULSEONDURATION_0 ((uint32_t)0x00000000)
#define | LCD_PULSEONDURATION_1 (LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_2 (LCD_FCR_PON_1)
#define | LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_4 (LCD_FCR_PON_2)
#define | LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1)
#define | LCD_PULSEONDURATION_7 (LCD_FCR_PON)
#define | LCD_DEADTIME_0 ((uint32_t)0x00000000)
#define | LCD_DEADTIME_1 (LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_2 (LCD_FCR_DEAD_1)
#define | LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_4 (LCD_FCR_DEAD_2)
#define | LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1)
#define | LCD_DEADTIME_7 (LCD_FCR_DEAD)
#define | LCD_BLINKMODE_OFF ((uint32_t)0x00000000)
#define | LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0)
#define | LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1)
#define | LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK)
#define | LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000)
#define | LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1)
#define | LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2)
#define | LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)
#define | LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF)
#define | LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000)
#define | LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1)
#define | LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2)
#define | LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1)
#define | LCD_CONTRASTLEVEL_7 (LCD_FCR_CC)
#define | LCD_RAM_REGISTER0 ((uint32_t)0x00000000)
#define | LCD_RAM_REGISTER1 ((uint32_t)0x00000001)
#define | LCD_RAM_REGISTER2 ((uint32_t)0x00000002)
#define | LCD_RAM_REGISTER3 ((uint32_t)0x00000003)
#define | LCD_RAM_REGISTER4 ((uint32_t)0x00000004)
#define | LCD_RAM_REGISTER5 ((uint32_t)0x00000005)
#define | LCD_RAM_REGISTER6 ((uint32_t)0x00000006)
#define | LCD_RAM_REGISTER7 ((uint32_t)0x00000007)
#define | LCD_RAM_REGISTER8 ((uint32_t)0x00000008)
#define | LCD_RAM_REGISTER9 ((uint32_t)0x00000009)
#define | LCD_RAM_REGISTER10 ((uint32_t)0x0000000A)
#define | LCD_RAM_REGISTER11 ((uint32_t)0x0000000B)
#define | LCD_RAM_REGISTER12 ((uint32_t)0x0000000C)
#define | LCD_RAM_REGISTER13 ((uint32_t)0x0000000D)
#define | LCD_RAM_REGISTER14 ((uint32_t)0x0000000E)
#define | LCD_RAM_REGISTER15 ((uint32_t)0x0000000F)
#define | LCD_HIGHDRIVE_DISABLE ((uint32_t)0x00000000)
#define | LCD_HIGHDRIVE_ENABLE (LCD_FCR_HD)
#define | LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000)
#define | LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG)
#define | LCD_FLAG_ENS LCD_SR_ENS
#define | LCD_FLAG_SOF LCD_SR_SOF
#define | LCD_FLAG_UDR LCD_SR_UDR
#define | LCD_FLAG_UDD LCD_SR_UDD
#define | LCD_FLAG_RDY LCD_SR_RDY
#define | LCD_FLAG_FCRSF LCD_SR_FCRSR
#define | __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
Reset LCD handle state.
#define | __HAL_LCD_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
Enable the LCD peripheral.
#define | __HAL_LCD_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
Disable the LCD peripheral.
#define | __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)
Enable the low resistance divider.
#define | __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)
Disable the low resistance divider.
#define | __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
Enable the voltage output buffer for higher driving capability.
#define | __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
Disable the voltage output buffer for higher driving capability.
#define | __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)
Configure the LCD pulse on duration.
#define | __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)
Configure the LCD dead time.
#define | __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)
Configure the LCD contrast.
#define | __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)
Configure the LCD Blink mode and Blink frequency.
#define | __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified LCD interrupt.
#define | __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified LCD interrupt.
#define | __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
Check whether the specified LCD interrupt source is enabled or not.
#define | __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified LCD flag is set or not.
#define | __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))
Clear the specified LCD pending flag.
#define | IS_LCD_PRESCALER(__PRESCALER__)
#define | IS_LCD_DIVIDER(__DIVIDER__)
#define | IS_LCD_DUTY(__DUTY__)
#define | IS_LCD_BIAS(__BIAS__)
#define | IS_LCD_VOLTAGE_SOURCE(SOURCE)
#define | IS_LCD_PULSE_ON_DURATION(__DURATION__)
#define | IS_LCD_DEAD_TIME(__TIME__)
#define | IS_LCD_BLINK_MODE(__MODE__)
#define | IS_LCD_BLINK_FREQUENCY(__FREQUENCY__)
#define | IS_LCD_CONTRAST(__CONTRAST__)
#define | IS_LCD_RAM_REGISTER(__REGISTER__)
#define | IS_LCD_HIGH_DRIVE(__VALUE__)
#define | IS_LCD_MUX_SEGMENT(__VALUE__)

Enumerations

enum HAL_LCD_StateTypeDef {
HAL_LCD_STATE_RESET = 0x00, HAL_LCD_STATE_READY = 0x01, HAL_LCD_STATE_BUSY = 0x02, HAL_LCD_STATE_TIMEOUT = 0x03,
HAL_LCD_STATE_ERROR = 0x04
}
HAL LCD State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_LCD_DeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD peripheral.
HAL_StatusTypeDef | HAL_LCD_Init (LCD_HandleTypeDef *hlcd)
Initialize the LCD peripheral according to the specified parameters in the LCD_InitStruct and initialize the associated handle.
__weak void | HAL_LCD_MspInit (LCD_HandleTypeDef *hlcd)
Initialize the LCD MSP.
__weak void | HAL_LCD_MspDeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD MSP.
HAL_StatusTypeDef | HAL_LCD_Write (LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
Write a word in the specific LCD RAM.
HAL_StatusTypeDef | HAL_LCD_Clear (LCD_HandleTypeDef *hlcd)
Clear the LCD RAM registers.
HAL_StatusTypeDef | HAL_LCD_UpdateDisplayRequest (LCD_HandleTypeDef *hlcd)
Enable the Update Display Request.
HAL_LCD_StateTypeDef | HAL_LCD_GetState (LCD_HandleTypeDef *hlcd)
Return the LCD handle state.
uint32_t | HAL_LCD_GetError (LCD_HandleTypeDef *hlcd)
Return the LCD error code.
HAL_StatusTypeDef | LCD_WaitForSynchro (LCD_HandleTypeDef *hlcd)
Wait until the LCD FCR register is synchronized in the LCDCLK domain.

Detailed Description

Header file of LCD Controller HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_lcd.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_lptim.h File Reference

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stm32l4xx_hal_lptim.h File Reference

Header file of LPTIM HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
#define | LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define | LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
#define | LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)
#define | LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
#define | LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)
#define | LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)
#define | LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
#define | LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LPTIM_INPUT1SOURCE_GPIO ((uint32_t)0x00000000)
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0
#define | LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1
#define | LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR
#define | LPTIM_INPUT2SOURCE_GPIO ((uint32_t)0x00000000)
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1
#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE
#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous or in single mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified LPTIM interrupt source is enabled or not.
#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
#define | IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFF)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Typedefs

typedef enum
__HAL_LPTIM_StateTypeDef 		HAL_LPTIM_StateTypeDef
HAL LPTIM State structure definition.

Enumerations

enum __HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00, HAL_LPTIM_STATE_READY = 0x01, HAL_LPTIM_STATE_BUSY = 0x02, HAL_LPTIM_STATE_TIMEOUT = 0x03,
HAL_LPTIM_STATE_ERROR = 0x04
}
HAL LPTIM State structure definition. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.

Detailed Description

Header file of LPTIM HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_lptim.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_nand.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
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Data Structures | Defines | Enumerations | Functions
stm32l4xx_hal_nand.h File Reference

Header file of NAND HAL module. More...

#include "stm32l4xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | NAND_IDTypeDef
NAND Memory electronic signature Structure definition. More...
struct | NAND_AddressTypeDef
NAND Memory address Structure definition. More...
struct | NAND_InfoTypeDef
NAND Memory info Structure definition. More...
struct | NAND_HandleTypeDef
NAND handle Structure definition. More...

Defines

#define | NAND_DEVICE FMC_BANK3
#define | NAND_WRITE_TIMEOUT ((uint32_t)1000)
#define | CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define | ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
#define | NAND_CMD_AREA_A ((uint8_t)0x00)
#define | NAND_CMD_AREA_B ((uint8_t)0x01)
#define | NAND_CMD_AREA_C ((uint8_t)0x50)
#define | NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define | NAND_CMD_READID ((uint8_t)0x90)
#define | NAND_CMD_STATUS ((uint8_t)0x70)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define | NAND_CMD_RESET ((uint8_t)0xFF)
#define | NAND_VALID_ADDRESS ((uint32_t)0x00000100)
#define | NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
#define | NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
#define | NAND_BUSY ((uint32_t)0x00000000)
#define | NAND_ERROR ((uint32_t)0x00000001)
#define | NAND_READY ((uint32_t)0x00000040)
#define | ARRAY_ADDRESS(__ADDRESS__, __HANDLE__)
NAND memory address computation.
#define | ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
NAND memory address cycling.
#define | ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define | ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define | ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
#define | __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
Reset NAND handle state.

Enumerations

enum | HAL_NAND_StateTypeDef { HAL_NAND_STATE_RESET = 0x00, HAL_NAND_STATE_READY = 0x01, HAL_NAND_STATE_BUSY = 0x02, HAL_NAND_STATE_ERROR = 0x03 }
HAL NAND State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
Initialize the NAND MSP.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
DeInitialize the NAND MSP.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.
HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_Read_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Write_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory.
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory.
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.
HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enable dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disable dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disable dynamically NAND ECC feature.
HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
Return the NAND handle state.
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.

Detailed Description

Header file of NAND HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_nand.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_nor.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Inc
Data Structures | Defines | Enumerations | Functions
stm32l4xx_hal_nor.h File Reference

Header file of NOR HAL module. More...

#include "stm32l4xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | NOR_IDTypeDef
FMC NOR ID typedef. More...
struct | NOR_CFITypeDef
FMC NOR CFI typedef. More...
struct | NOR_HandleTypeDef
NOR handle Structure definition. More...

Defines

#define | MC_ADDRESS ((uint16_t)0x0000)
#define | DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define | DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define | DEVICE_CODE3_ADDR ((uint16_t)0x000F)
#define | CFI1_ADDRESS ((uint16_t)0x10)
#define | CFI2_ADDRESS ((uint16_t)0x11)
#define | CFI3_ADDRESS ((uint16_t)0x12)
#define | CFI4_ADDRESS ((uint16_t)0x13)
#define | NOR_MEMORY_8B ((uint8_t)0x0)
#define | NOR_MEMORY_16B ((uint8_t)0x1)
#define | NOR_MEMORY_ADRESS1 FMC_BANK1_1
#define | NOR_MEMORY_ADRESS2 FMC_BANK1_2
#define | NOR_MEMORY_ADRESS3 FMC_BANK1_3
#define | NOR_MEMORY_ADRESS4 FMC_BANK1_4
#define | NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)
NOR memory address shifting.
#define | NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
NOR memory write data to specified address.
#define | __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
Reset NOR handle state.

Enumerations

enum HAL_NOR_StateTypeDef {
HAL_NOR_STATE_RESET = 0x00, HAL_NOR_STATE_READY = 0x01, HAL_NOR_STATE_BUSY = 0x02, HAL_NOR_STATE_ERROR = 0x03,
HAL_NOR_STATE_PROTECTED = 0x04
}
HAL SRAM State structures definition. More...
enum | HAL_NOR_StatusTypeDef { HAL_NOR_STATUS_SUCCESS = 0, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT }
FMC NOR Status typedef. More...

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
Initialize the NOR MSP.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
DeInitialize the NOR MSP.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.
HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Return the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Read a block of data from the FMC NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Write a half-word buffer to the FMC NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enable dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disable dynamically NOR write operation.
HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
Return the NOR controller handle state.
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Return the NOR operation status.

Detailed Description

Header file of NOR HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_nor.h.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_opamp.h File Reference

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stm32l4xx_hal_opamp.h File Reference

Header file of OPAMP HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_opamp_ex.h"

Go to the source code of this file.

Data Structures

struct | OPAMP_InitTypeDef
OPAMP Init structure definition. More...
struct | OPAMP_HandleTypeDef
OPAMP Handle Structure definition. More...

Defines

#define | OPAMP_STANDALONE_MODE ((uint32_t)0x00000000)
#define | OPAMP_PGA_MODE OPAMP_CSR_OPAMODE_1
#define | OPAMP_FOLLOWER_MODE OPAMP_CSR_OPAMODE
#define | OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000)
#define | OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL
#define | OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000)
#define | OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0
#define | OPAMP_INVERTINGINPUT_CONNECT_NO OPAMP_CSR_VMSEL_1
#define | OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000)
#define | OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0
#define | OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1
#define | OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)
#define | OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000)
#define | OPAMP_POWERMODE_LOWPOWER OPAMP_CSR_OPALPM
#define | OPAMP_POWERSUPPLY_LOW ((uint32_t)0x00000000)
#define | OPAMP_POWERSUPPLY_HIGH OPAMP1_CSR_OPARANGE
#define | OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000)
#define | OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM
#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF)
#define | OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000)
#define | OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001)
#define | OPAMP_INPUT_NONINVERTING ((uint32_t) 8)
#define | OPAMP_TRIMMING_DELAY ((uint32_t) 1)
#define | __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
Reset OPAMP handle state.
#define | IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT)
#define | IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT)
#define | IS_OPAMP_NONINVERTING_INPUT(INPUT)
#define | IS_OPAMP_INVERTING_INPUT_PGA(INPUT)
#define | IS_OPAMP_PGA_GAIN(GAIN)
#define | IS_OPAMP_POWERMODE(TRIMMING)
#define | IS_OPAMP_POWER_SUPPLY_RANGE(RANGE)
#define | IS_OPAMP_TRIMMING(TRIMMING)
#define | IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define | IS_OPAMP_FACTORYTRIMMING(TRIMMING)

Typedefs

typedef uint32_t | HAL_OPAMP_TrimmingValueTypeDef
HAl_OPAMP_TrimmingValueTypeDef definition.

Enumerations

enum HAL_OPAMP_StateTypeDef {
HAL_OPAMP_STATE_RESET = 0x00000000, HAL_OPAMP_STATE_READY = 0x00000001, HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, HAL_OPAMP_STATE_BUSY = 0x00000004,
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initializes the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.
HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected OPAMP configuration.
HAL_OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.
HAL_OPAMP_StateTypeDef | HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP handle state.

Detailed Description

Header file of OPAMP HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_opamp.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_opamp_ex.h File Reference

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Functions
stm32l4xx_hal_opamp_ex.h File Reference

Header file of OPAMP HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
Run the self calibration of the 2 OPAMPs in parallel.
HAL_StatusTypeDef | HAL_OPAMPEx_Unlock (OPAMP_HandleTypeDef *hopamp)
Unlock the selected OPAMP configuration.

Detailed Description

Header file of OPAMP HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_opamp_ex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pcd.h File Reference

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stm32l4xx_hal_pcd.h File Reference

Header file of PCD HAL module. More...

#include "stm32l4xx_ll_usb.h"
#include "stm32l4xx_hal_pcd_ex.h"

Go to the source code of this file.

Data Structures

struct | PCD_HandleTypeDef
PCD Handle Structure definition. More...

Defines

#define | PCD_SPEED_FULL 1
#define | PCD_PHY_EMBEDDED 1
#define | USBD_FS_TRDT_VALUE 5
#define | __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define | __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define | __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
#define | __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define | __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define | USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define | USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define | USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00020000)

Typedefs

typedef USB_OTG_GlobalTypeDef | PCD_TypeDef
typedef USB_OTG_CfgTypeDef | PCD_InitTypeDef
typedef USB_OTG_EPTypeDef | PCD_EPTypeDef

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB OTG Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB OTG Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
Handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_pcd.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pcd_ex.h File Reference

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stm32l4xx_hal_pcd_ex.h File Reference

Header file of PCD HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Enumerations

enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_pcd_ex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pwr.h File Reference

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stm32l4xx_hal_pwr.h File Reference

Header file of PWR HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_pwr_ex.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...

Defines

#define | PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0
#define | PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1
#define | PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2
#define | PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3
#define | PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4
#define | PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5
#define | PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6
#define | PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7
#define | PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000)
#define | PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001)
#define | PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002)
#define | PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)
#define | PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001)
#define | PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002)
#define | PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)
#define | PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR
#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
#define | PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define | PWR_EXTI_LINE_PVD ((uint32_t)0x00010000)
#define | PWR_EVENT_LINE_PVD ((uint32_t)0x00010000)
#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check whether or not a specific PWR flag is set.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__)
Clear a specific PWR flag.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Enable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
Disable the PVD Event Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
Check whether or not the PVD EXTI interrupt flag is set.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
Clear the PVD EXTI interrupt flag.
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers).
HAL_StatusTypeDef | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector (PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Power Voltage Detector (PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Power Voltage Detector (PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX M4 SEVONPEND bit.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

Header file of PWR HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_pwr.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pwr_ex.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_hal_pwr_ex.h File Reference

Header file of PWR HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVMTypeDef
PWR PVM configuration structure definition. More...

Defines

#define | PWR_WUP_POLARITY_SHIFT 0x05
#define | PWR_WAKEUP_PIN1 PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2 PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3 PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4 PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5 PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)
#define | PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)
#define | PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)
#define | PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)
#define | PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)
#define | PWR_PVM_1 PWR_CR2_PVME1
#define | PWR_PVM_2 PWR_CR2_PVME2
#define | PWR_PVM_3 PWR_CR2_PVME3
#define | PWR_PVM_4 PWR_CR2_PVME4
#define | PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000)
#define | PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001)
#define | PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002)
#define | PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003)
#define | PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001)
#define | PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002)
#define | PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003)
#define | PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0
#define | PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1
#define | PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000)
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS
#define | PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000)
#define | PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
#define | PWR_GPIO_BIT_0 PWR_PUCRA_PA0
#define | PWR_GPIO_BIT_1 PWR_PUCRA_PA1
#define | PWR_GPIO_BIT_2 PWR_PUCRA_PA2
#define | PWR_GPIO_BIT_3 PWR_PUCRA_PA3
#define | PWR_GPIO_BIT_4 PWR_PUCRA_PA4
#define | PWR_GPIO_BIT_5 PWR_PUCRA_PA5
#define | PWR_GPIO_BIT_6 PWR_PUCRA_PA6
#define | PWR_GPIO_BIT_7 PWR_PUCRA_PA7
#define | PWR_GPIO_BIT_8 PWR_PUCRA_PA8
#define | PWR_GPIO_BIT_9 PWR_PUCRA_PA9
#define | PWR_GPIO_BIT_10 PWR_PUCRA_PA10
#define | PWR_GPIO_BIT_11 PWR_PUCRA_PA11
#define | PWR_GPIO_BIT_12 PWR_PUCRA_PA12
#define | PWR_GPIO_BIT_13 PWR_PUCRA_PA13
#define | PWR_GPIO_BIT_14 PWR_PDCRA_PA14
#define | PWR_GPIO_BIT_15 PWR_PUCRA_PA15
#define | PWR_GPIO_A 0x00000000
#define | PWR_GPIO_B 0x00000001
#define | PWR_GPIO_C 0x00000002
#define | PWR_GPIO_D 0x00000003
#define | PWR_GPIO_E 0x00000004
#define | PWR_GPIO_F 0x00000005
#define | PWR_GPIO_G 0x00000006
#define | PWR_GPIO_H 0x00000007
#define | PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008)
#define | PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010)
#define | PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020)
#define | PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040)
#define | PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)
#define | PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)
#define | PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)
#define | PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)
#define | PWR_FLAG_WUF1 ((uint32_t)0x0020)
#define | PWR_FLAG_WUF2 ((uint32_t)0x0021)
#define | PWR_FLAG_WUF3 ((uint32_t)0x0022)
#define | PWR_FLAG_WUF4 ((uint32_t)0x0023)
#define | PWR_FLAG_WUF5 ((uint32_t)0x0024)
#define | PWR_FLAG_WU PWR_SR1_WUF
#define | PWR_FLAG_SB ((uint32_t)0x0028)
#define | PWR_FLAG_WUFI ((uint32_t)0x002F)
#define | PWR_FLAG_REGLPS ((uint32_t)0x0048)
#define | PWR_FLAG_REGLPF ((uint32_t)0x0049)
#define | PWR_FLAG_VOSF ((uint32_t)0x004A)
#define | PWR_FLAG_PVDO ((uint32_t)0x004B)
#define | PWR_FLAG_PVMO1 ((uint32_t)0x004C)
#define | PWR_FLAG_PVMO2 ((uint32_t)0x004D)
#define | PWR_FLAG_PVMO3 ((uint32_t)0x004E)
#define | PWR_FLAG_PVMO4 ((uint32_t)0x004F)
#define | __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
Enable the PVM1 Event Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
Disable the PVM1 Event Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM1 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
Check whether the specified PVM1 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
Clear the PVM1 EXTI flag.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Line.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Line.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
Enable the PVM2 Event Line.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
Disable the PVM2 Event Line.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
Enable the PVM2 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
Disable the PVM2 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM2 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
Check whether the specified PVM2 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
Clear the PVM2 EXTI flag.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
Enable the PVM3 Event Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
Disable the PVM3 Event Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM3 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
Check whether the specified PVM3 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
Clear the PVM3 EXTI flag.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Line.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Line.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
Enable the PVM4 Event Line.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
Disable the PVM4 Event Line.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
Enable the PVM4 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
Disable the PVM4 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM4 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
Check whether or not the specified PVM4 EXTI interrupt flag is set.
#define | __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
Clear the PVM4 EXTI flag.
#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
Configure the main internal regulator output voltage.
#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_PVM_TYPE(TYPE)
#define | IS_PWR_PVM_MODE(MODE)
#define | IS_PWR_VOLTAGE_SCALING_RANGE(RANGE)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)
#define | IS_PWR_BATTERY_CHARGING(CHARGING)
#define | IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
#define | IS_PWR_GPIO(GPIO)

Functions

uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnableVddUSB (void)
Enable VDDUSB supply.
void | HAL_PWREx_DisableVddUSB (void)
Disable VDDUSB supply.
void | HAL_PWREx_EnableVddIO2 (void)
Enable VDDIO2 supply.
void | HAL_PWREx_DisableVddIO2 (void)
Disable VDDIO2 supply.
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_EnableSRAM2ContentRetention (void)
Enable SRAM2 content retention in Standby mode.
void | HAL_PWREx_DisableSRAM2ContentRetention (void)
Disable SRAM2 content retention in Standby mode.
void | HAL_PWREx_EnablePVM1 (void)
Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_DisablePVM1 (void)
Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_EnablePVM2 (void)
Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
void | HAL_PWREx_DisablePVM2 (void)
Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
void | HAL_PWREx_EnablePVM3 (void)
Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
void | HAL_PWREx_DisablePVM3 (void)
Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
void | HAL_PWREx_EnablePVM4 (void)
Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
void | HAL_PWREx_DisablePVM4 (void)
Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSTOP0Mode (uint8_t STOPEntry)
Enter Stop 0 mode.
void | HAL_PWREx_EnterSTOP1Mode (uint8_t STOPEntry)
Enter Stop 1 mode.
void | HAL_PWREx_EnterSTOP2Mode (uint8_t STOPEntry)
Enter Stop 2 mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD/PVMx interrupt request.
__weak void | HAL_PWREx_PVM1Callback (void)
PWR PVM1 interrupt callback.
__weak void | HAL_PWREx_PVM2Callback (void)
PWR PVM2 interrupt callback.
__weak void | HAL_PWREx_PVM3Callback (void)
PWR PVM3 interrupt callback.
__weak void | HAL_PWREx_PVM4Callback (void)
PWR PVM4 interrupt callback.

Detailed Description

Header file of PWR HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_pwr_ex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_qspi.h File Reference

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stm32l4xx_hal_qspi.h File Reference

Header file of QSPI HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | QSPI_InitTypeDef
QSPI Init structure definition. More...
struct | QSPI_HandleTypeDef
QSPI Handle Structure definition. More...
struct | QSPI_CommandTypeDef
QSPI Command structure definition. More...
struct | QSPI_AutoPollingTypeDef
QSPI Auto Polling mode configuration structure definition. More...
struct | QSPI_MemoryMappedTypeDef
QSPI Memory Mapped mode configuration structure definition. More...

Defines

#define | HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001)
#define | HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002)
#define | HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004)
#define | HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008)
#define | QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000)
#define | QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)
#define | QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000)
#define | QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
#define | QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)
#define | QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000)
#define | QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)
#define | QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
#define | QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
#define | QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)
#define | QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
#define | QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
#define | QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)
#define | QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000)
#define | QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
#define | QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
#define | QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)
#define | QSPI_ADDRESS_NONE ((uint32_t)0x00000000)
#define | QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
#define | QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
#define | QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)
#define | QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000)
#define | QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
#define | QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
#define | QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)
#define | QSPI_DATA_NONE ((uint32_t)0X00000000)
#define | QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
#define | QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
#define | QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)
#define | QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000)
#define | QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)
#define | QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000)
#define | QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000)
#define | QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)
#define | QSPI_MATCH_MODE_AND ((uint32_t)0x00000000)
#define | QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)
#define | QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000)
#define | QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)
#define | QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000)
#define | QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)
#define | QSPI_FLAG_BUSY QUADSPI_SR_BUSY
#define | QSPI_FLAG_TO QUADSPI_SR_TOF
#define | QSPI_FLAG_SM QUADSPI_SR_SMF
#define | QSPI_FLAG_FT QUADSPI_SR_FTF
#define | QSPI_FLAG_TC QUADSPI_SR_TCF
#define | QSPI_FLAG_TE QUADSPI_SR_TEF
#define | QSPI_IT_TO QUADSPI_CR_TOIE
#define | QSPI_IT_SM QUADSPI_CR_SMIE
#define | QSPI_IT_FT QUADSPI_CR_FTIE
#define | QSPI_IT_TC QUADSPI_CR_TCIE
#define | QSPI_IT_TE QUADSPI_CR_TEIE
#define | HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
#define | __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
Reset QSPI handle state.
#define | __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Enable the QSPI peripheral.
#define | __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Disable the QSPI peripheral.
#define | __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Enable the specified QSPI interrupt.
#define | __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Disable the specified QSPI interrupt.
#define | __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified QSPI interrupt source is enabled or not.
#define | __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
Check whether the selected QSPI flag is set or not.
#define | __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Clears the specified QSPI's flag status.
#define | IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
#define | IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16))
#define | IS_QSPI_SSHIFT(SSHIFT)
#define | IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
#define | IS_QSPI_CS_HIGH_TIME(CSHTIME)
#define | IS_QSPI_CLOCK_MODE(CLKMODE)
#define | IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
#define | IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)
#define | IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)
#define | IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
#define | IS_QSPI_INSTRUCTION_MODE(MODE)
#define | IS_QSPI_ADDRESS_MODE(MODE)
#define | IS_QSPI_ALTERNATE_BYTES_MODE(MODE)
#define | IS_QSPI_DATA_MODE(MODE)
#define | IS_QSPI_DDR_MODE(DDR_MODE)
#define | IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
#define | IS_QSPI_SIOO_MODE(SIOO_MODE)
#define | IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define | IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
#define | IS_QSPI_MATCH_MODE(MODE)
#define | IS_QSPI_AUTOMATIC_STOP(APMS)
#define | IS_QSPI_TIMEOUT_ACTIVATION(TCEN)
#define | IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)

Enumerations

enum HAL_QSPI_StateTypeDef {
HAL_QSPI_STATE_RESET = 0x00, HAL_QSPI_STATE_READY = 0x01, HAL_QSPI_STATE_BUSY = 0x02, HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12,
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, HAL_QSPI_STATE_ABORT = 0x08,
HAL_QSPI_STATE_ERROR = 0x04
}
HAL QSPI State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.
void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.
HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.

Detailed Description

Header file of QSPI HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_qspi.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rcc.h File Reference

  • File List
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  • Drivers
  • STM32L4xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32l4xx_hal_rcc.h File Reference

Header file of RCC HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_rcc_ex.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...

Defines

#define | RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define | RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
#define | RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
#define | RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
#define | RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
#define | RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
#define | RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U)
#define | RCC_HSE_OFF ((uint32_t)0x00000000U)
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
#define | RCC_LSE_OFF ((uint32_t)0x00000000U)
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#define | RCC_HSI_OFF ((uint32_t)0x00000000U)
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT ((uint32_t)16)
#define | RCC_LSI_OFF ((uint32_t)0x00000000U)
#define | RCC_LSI_ON RCC_CSR_LSION
#define | RCC_MSI_OFF ((uint32_t)0x00000000U)
#define | RCC_MSI_ON RCC_CR_MSION
#define | RCC_MSICALIBRATION_DEFAULT ((uint32_t)0)
#define | RCC_HSI48_OFF ((uint32_t)0x00000000U)
#define | RCC_PLL_NONE ((uint32_t)0x00000000U)
#define | RCC_PLL_OFF ((uint32_t)0x00000001U)
#define | RCC_PLL_ON ((uint32_t)0x00000002U)
#define | RCC_PLLP_DIV7 ((uint32_t)0x00000007U)
#define | RCC_PLLP_DIV17 ((uint32_t)0x00000011U)
#define | RCC_PLLQ_DIV2 ((uint32_t)0x00000002U)
#define | RCC_PLLQ_DIV4 ((uint32_t)0x00000004U)
#define | RCC_PLLQ_DIV6 ((uint32_t)0x00000006U)
#define | RCC_PLLQ_DIV8 ((uint32_t)0x00000008U)
#define | RCC_PLLR_DIV2 ((uint32_t)0x00000002U)
#define | RCC_PLLR_DIV4 ((uint32_t)0x00000004U)
#define | RCC_PLLR_DIV6 ((uint32_t)0x00000006U)
#define | RCC_PLLR_DIV8 ((uint32_t)0x00000008U)
#define | RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U)
#define | RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI
#define | RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
#define | RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN
#define | RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN
#define | RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN
#define | RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN
#define | RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN
#define | RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN
#define | RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN
#define | RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN
#define | RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0
#define | RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1
#define | RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2
#define | RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3
#define | RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4
#define | RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5
#define | RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6
#define | RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7
#define | RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8
#define | RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9
#define | RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10
#define | RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11
#define | RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
#define | RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
#define | RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
#define | RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
#define | RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
#define | RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI
#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
#define | RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U)
#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
#define | RCC_MCO1 ((uint32_t)0x00000000U)
#define | RCC_MCO RCC_MCO1
#define | RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U)
#define | RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1
#define | RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1
#define | RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2
#define | RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4
#define | RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8
#define | RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16
#define | RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
#define | RCC_IT_LSERDY RCC_CIFR_LSERDYF
#define | RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
#define | RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
#define | RCC_IT_HSERDY RCC_CIFR_HSERDYF
#define | RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
#define | RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF
#define | RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF
#define | RCC_IT_CSS RCC_CIFR_CSSF
#define | RCC_IT_LSECSS RCC_CIFR_LSECSSF
#define | RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY)))
#define | RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY)))
#define | RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY)))
#define | RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY)))
#define | RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY)))
#define | RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY)))
#define | RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY)))
#define | RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD)))
#define | RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))
#define | RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF)))
#define | RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF)))
#define | RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))
#define | RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))
#define | RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF)))
#define | RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))
#define | RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF)))
#define | RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF)))
#define | RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF)))
#define | RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
#define | RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U)
#define | RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_DMA2_CLK_ENABLE()
#define | __HAL_RCC_FLASH_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_TSC_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
#define | __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
#define | __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
#define | __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
#define | __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOF_CLK_ENABLE()
#define | __HAL_RCC_GPIOG_CLK_ENABLE()
#define | __HAL_RCC_GPIOH_CLK_ENABLE()
#define | __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
#define | __HAL_RCC_ADC_CLK_ENABLE()
#define | __HAL_RCC_AES_CLK_ENABLE()
#define | __HAL_RCC_RNG_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
#define | __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
#define | __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
#define | __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
#define | __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
#define | __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
#define | __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
#define | __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
#define | __HAL_RCC_FMC_CLK_ENABLE()
#define | __HAL_RCC_QSPI_CLK_ENABLE()
#define | __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
#define | __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
#define | __HAL_RCC_TIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_TIM5_CLK_ENABLE()
#define | __HAL_RCC_TIM6_CLK_ENABLE()
#define | __HAL_RCC_TIM7_CLK_ENABLE()
#define | __HAL_RCC_LCD_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_SPI3_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_UART4_CLK_ENABLE()
#define | __HAL_RCC_UART5_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_I2C3_CLK_ENABLE()
#define | __HAL_RCC_CAN1_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_DAC1_CLK_ENABLE()
#define | __HAL_RCC_OPAMP_CLK_ENABLE()
#define | __HAL_RCC_LPTIM1_CLK_ENABLE()
#define | __HAL_RCC_LPUART1_CLK_ENABLE()
#define | __HAL_RCC_SWPMI1_CLK_ENABLE()
#define | __HAL_RCC_LPTIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
#define | __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
#define | __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
#define | __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
#define | __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
#define | __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
#define | __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
#define | __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
#define | __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
#define | __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
#define | __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
#define | __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
#define | __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
#define | __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
#define | __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
#define | __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
#define | __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
#define | __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
#define | __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
#define | __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
#define | __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
#define | __HAL_RCC_SYSCFG_CLK_ENABLE()
#define | __HAL_RCC_FIREWALL_CLK_ENABLE()
#define | __HAL_RCC_SDMMC1_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_TIM8_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_TIM15_CLK_ENABLE()
#define | __HAL_RCC_TIM16_CLK_ENABLE()
#define | __HAL_RCC_TIM17_CLK_ENABLE()
#define | __HAL_RCC_SAI1_CLK_ENABLE()
#define | __HAL_RCC_SAI2_CLK_ENABLE()
#define | __HAL_RCC_DFSDM1_CLK_ENABLE()
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
#define | __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
#define | __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
#define | __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
#define | __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
#define | __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
#define | __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
#define | __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
#define | __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
#define | __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
#define | __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
#define | __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
#define | __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
#define | __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
#define | __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
#define | __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
#define | __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
#define | __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
#define | __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
#define | __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
#define | __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
#define | __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
#define | __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
#define | __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
#define | __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
#define | __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
#define | __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
#define | __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
#define | __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
#define | __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
#define | __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
#define | __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
#define | __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
#define | __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
#define | __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
#define | __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
#define | __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
#define | __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
#define | __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
#define | __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
#define | __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
#define | __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
#define | __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
#define | __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
#define | __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
#define | __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
#define | __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)
#define | __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
#define | __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
#define | __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
#define | __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
#define | __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
#define | __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
#define | __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
#define | __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
#define | __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
#define | __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
#define | __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
#define | __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
#define | __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
#define | __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
#define | __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
#define | __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
#define | __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
#define | __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
#define | __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
#define | __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
#define | __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
#define | __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
#define | __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
#define | __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
#define | __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
#define | __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
#define | __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
#define | __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
#define | __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
#define | __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
#define | __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
#define | __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
#define | __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
#define | __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
#define | __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
#define | __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
#define | __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
#define | __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
#define | __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
#define | __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
#define | __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
#define | __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
#define | __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
#define | __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
#define | __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
#define | __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
#define | __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
#define | __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
#define | __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
#define | __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
#define | __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
#define | __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
#define | __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
#define | __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
#define | __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
#define | __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
#define | __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
#define | __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
#define | __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
#define | __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
#define | __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
#define | __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
#define | __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
#define | __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
#define | __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
#define | __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
#define | __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
#define | __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
#define | __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
#define | __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
#define | __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
#define | __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
#define | __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
#define | __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
#define | __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
#define | __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
#define | __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
#define | __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
#define | __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
#define | __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
#define | __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
#define | __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
#define | __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
#define | __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
#define | __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
#define | __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
#define | __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
#define | __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
#define | __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
#define | __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
#define | __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
#define | __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
#define | __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
#define | __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
#define | __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
#define | __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
#define | __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
#define | __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
#define | __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
#define | __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
#define | __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
#define | __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
#define | __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
#define | __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
#define | __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
#define | __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
#define | __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
#define | __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
#define | __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
#define | __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
#define | __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
#define | __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
#define | __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
#define | __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
#define | __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
#define | __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define | __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
#define | __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
#define | __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
#define | __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
#define | __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
#define | __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
#define | __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
#define | __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
#define | __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
#define | __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
#define | __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
#define | __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
#define | __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
#define | __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
#define | __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
#define | __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
#define | __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
#define | __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
#define | __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
#define | __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
#define | __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
#define | __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
#define | __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
#define | __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
#define | __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
#define | __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
#define | __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
#define | __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
#define | __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
#define | __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
#define | __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
#define | __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
#define | __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
#define | __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
#define | __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
#define | __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
#define | __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
#define | __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
#define | __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
#define | __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)
#define | __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
#define | __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
#define | __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
#define | __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
#define | __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
#define | __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
#define | __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
Macros to enable or disable the Internal Multi Speed oscillator (MSI).
#define | __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
#define | __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
#define | __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__)
Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode.
#define | __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
#define | __HAL_RCC_GET_MSI_RANGE()
Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode.
#define | __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Macros to enable or disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Macro to get the RTC clock source.
#define | __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
Macro to configure the PLL source division factor M.
#define | __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
#define | __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
Macro to configure the wake up from stop clock.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Macro to configure the MCO clock.
#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the RCC interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check whether the selected RCC flag is set or not.
#define | CR_REG_INDEX ((uint32_t)1U)
#define | BDCR_REG_INDEX ((uint32_t)2U)
#define | CSR_REG_INDEX ((uint32_t)3U)
#define | RCC_FLAG_MASK ((uint32_t)0x1FU)
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31U)
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
#define | IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
#define | IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define | IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
#define | IS_RCC_PLLQ_VALUE(__VALUE__)
#define | IS_RCC_PLLR_VALUE(__VALUE__)
#define | IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__)
#define | IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__)
#define | IS_RCC_MSI_CLOCK_RANGE(__RANGE__)
#define | IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__)
#define | IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_HCLK(__HCLK__)
#define | IS_RCC_PCLK(__PCLK__)
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define | IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
#define | IS_RCC_MCO1SOURCE(__SOURCE__)
#define | IS_RCC_MCODIV(__DIV__)
#define | IS_RCC_LSE_DRIVE(__DRIVE__)
#define | IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__)

Functions

void | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO pin(PA8).
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Return the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

Header file of RCC HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_rcc.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rcc_ex.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLSAI1InitTypeDef
PLLSAI1 Clock structure definition. More...
struct | RCC_PLLSAI2InitTypeDef
PLLSAI2 Clock structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...

Defines

#define | RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U
#define | RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL
#define | RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
#define | RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
#define | RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U)
#define | RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U)
#define | RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U)
#define | RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U)
#define | RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U)
#define | RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U)
#define | RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
#define | RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U)
#define | RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U)
#define | RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U)
#define | RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U)
#define | RCC_PERIPHCLK_USB ((uint32_t)0x00002000U)
#define | RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U)
#define | RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U)
#define | RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U)
#define | RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U)
#define | RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U)
#define | RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U)
#define | RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
#define | RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define | RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define | RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
#define | RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define | RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define | RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
#define | RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
#define | RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
#define | RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
#define | RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
#define | RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
#define | RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
#define | RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
#define | RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
#define | RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
#define | RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
#define | RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define | RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
#define | RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
#define | RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
#define | RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define | RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
#define | RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
#define | RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
#define | RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
#define | RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
#define | RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
#define | RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
#define | RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
#define | RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
#define | RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
#define | RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define | RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define | RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define | RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
#define | RCC_LPTIM2CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define | RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
#define | RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
#define | RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
#define | RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U)
#define | RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define | RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define | RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U)
#define | RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define | RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define | RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U)
#define | RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define | RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define | RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U)
#define | RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
#define | RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
#define | RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
#define | RCC_SWPMI1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define | RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
#define | RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define | RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
#define | RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19
#define | __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__)
Macro to configure the PLLSAI1 clock multiplication and division factors.
#define | __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
Macro to configure the PLLSAI1 clock multiplication factor N.
#define | __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
Macro to configure the PLLSAI1 clock division factor P.
#define | __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
Macro to configure the PLLSAI1 clock division factor Q.
#define | __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
Macro to configure the PLLSAI1 clock division factor R.
#define | __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
Macros to enable or disable the PLLSAI1.
#define | __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
#define | __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
#define | __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
#define | __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
#define | __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__)
Macro to configure the PLLSAI2 clock multiplication and division factors.
#define | __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
Macro to configure the PLLSAI2 clock multiplication factor N.
#define | __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
Macro to configure the PLLSAI2 clock division factor P.
#define | __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
Macro to configure the PLLSAI2 clock division factor R.
#define | __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
Macros to enable or disable the PLLSAI2.
#define | __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
#define | __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
#define | __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
#define | __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
#define | __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
Macro to configure the SAI1 clock source.
#define | __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
Macro to get the SAI1 clock source.
#define | __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
Macro to configure the SAI2 clock source.
#define | __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
Macro to get the SAI2 clock source.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
Macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Macro to configure the I2C2 clock (I2C2CLK).
#define | __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
Macro to get the I2C2 clock source.
#define | __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
Macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
Macro to get the I2C3 clock source.
#define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
Macro to get the USART1 clock source.
#define | __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Macro to configure the USART2 clock (USART2CLK).
#define | __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
Macro to get the USART2 clock source.
#define | __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Macro to configure the USART3 clock (USART3CLK).
#define | __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
Macro to get the USART3 clock source.
#define | __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
Macro to configure the UART4 clock (UART4CLK).
#define | __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
Macro to get the UART4 clock source.
#define | __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
Macro to configure the UART5 clock (UART5CLK).
#define | __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
Macro to get the UART5 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
Macro to configure the LPUART1 clock (LPUART1CLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
Macro to get the LPUART1 clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define | __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
Macro to get the LPTIM1 clock source.
#define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
Macro to configure the LPTIM2 clock (LPTIM2CLK).
#define | __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
Macro to get the LPTIM2 clock source.
#define | __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
Macro to configure the SDMMC1 clock.
#define | __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Macro to get the SDMMC1 clock.
#define | __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
Macro to configure the RNG clock.
#define | __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Macro to get the RNG clock.
#define | __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
Macro to get the USB clock source.
#define | __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
Macro to configure the ADC interface clock.
#define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
Macro to get the ADC clock source.
#define | __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
Macro to configure the SWPMI1 clock.
#define | __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
Macro to get the SWPMI1 clock source.
#define | __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
Macro to configure the DFSDM1 clock.
#define | __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))
Macro to get the DFSDM1 clock source.
#define | __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
Enable PLLSAI1RDY interrupt.
#define | __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
Disable PLLSAI1RDY interrupt.
#define | __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
Clear the PLLSAI1RDY interrupt pending bit.
#define | __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
Check whether PLLSAI1RDY interrupt has occurred or not.
#define | __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
Check whether the PLLSAI1RDY flag is set or not.
#define | __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
Enable PLLSAI2RDY interrupt.
#define | __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
Disable PLLSAI2RDY interrupt.
#define | __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
Clear the PLLSAI2RDY interrupt pending bit.
#define | __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
Check whether the PLLSAI2RDY interrupt has occurred or not.
#define | __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
Check whether the PLLSAI2RDY flag is set or not.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Event Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Event Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
#define | __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
Clear the RCC LSE CSS EXTI flag.
#define | __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
Generate a Software interrupt on the RCC LSE CSS EXTI line.
#define | IS_RCC_LSCOSOURCE(__SOURCE__)
#define | IS_RCC_PERIPHCLOCK(__SELECTION__)
#define | IS_RCC_USART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART2CLKSOURCE(__SOURCE__)
#define | IS_RCC_USART3CLKSOURCE(__SOURCE__)
#define | IS_RCC_UART4CLKSOURCE(__SOURCE__)
#define | IS_RCC_UART5CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPUART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C2CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C3CLKSOURCE(__SOURCE__)
#define | IS_RCC_SAI1CLK(__SOURCE__)
#define | IS_RCC_SAI2CLK(__SOURCE__)
#define | IS_RCC_LPTIM1CLK(__SOURCE__)
#define | IS_RCC_LPTIM2CLK(__SOURCE__)
#define | IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)
#define | IS_RCC_RNGCLKSOURCE(__SOURCE__)
#define | IS_RCC_USBCLKSOURCE(__SOURCE__)
#define | IS_RCC_ADCCLKSOURCE(__SOURCE__)
#define | IS_RCC_SWPMI1CLKSOURCE(__SOURCE__)
#define | IS_RCC_DFSDM1CLKSOURCE(__SOURCE__)
#define | IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
#define | IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
#define | IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define | IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
#define | IS_RCC_PLLSAI1Q_VALUE(__VALUE__)
#define | IS_RCC_PLLSAI1R_VALUE(__VALUE__)
#define | IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
#define | IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
#define | IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define | IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
#define | IS_RCC_PLLSAI2R_VALUE(__VALUE__)

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLLSAIs.
HAL_StatusTypeDef | HAL_RCCEx_EnablePLLSAI1 (RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
Enable PLLSAI1.
HAL_StatusTypeDef | HAL_RCCEx_DisablePLLSAI1 (void)
Disable PLLSAI1.
HAL_StatusTypeDef | HAL_RCCEx_EnablePLLSAI2 (RCC_PLLSAI2InitTypeDef *PLLSAI2Init)
Enable PLLSAI2.
HAL_StatusTypeDef | HAL_RCCEx_DisablePLLSAI2 (void)
Disable PLLISAI2.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_StandbyMSIRangeConfig (uint32_t MSIRange)
Configure the MSI range after standby mode.
void | HAL_RCCEx_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCCEx_EnableLSECSS_IT (void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
void | HAL_RCCEx_LSECSS_IRQHandler (void)
Handle the RCC LSE Clock Security System interrupt request.
__weak void | HAL_RCCEx_LSECSS_Callback (void)
RCCEx LSE Clock Security System interrupt callback.
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.
void | HAL_RCCEx_EnableMSIPLLMode (void)
Enable the PLL-mode of the MSI.
void | HAL_RCCEx_DisableMSIPLLMode (void)
Disable the PLL-mode of the MSI.

Detailed Description

Header file of RCC HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_rcc_ex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rng.h File Reference

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stm32l4xx_hal_rng.h File Reference

Header file of RNG HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RNG_HandleTypeDef
RNG Handle Structure definition. More...

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS
#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS
#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enable the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disable the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified RNG flag is set or not.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clear the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enable the RNG interrupt.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disable the RNG interrupt.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00, HAL_RNG_STATE_READY = 0x01, HAL_RNG_STATE_BUSY = 0x02, HAL_RNG_STATE_TIMEOUT = 0x03,
HAL_RNG_STATE_ERROR = 0x04
}
RNG HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initialize the RNG peripheral and initialize the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitialize the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initialize the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitialize the RNG MSP.
uint32_t | HAL_RNG_GetRandomNumber (RNG_HandleTypeDef *hrng)
Return generated random number in polling mode (Obsolete).
uint32_t | HAL_RNG_GetRandomNumber_IT (RNG_HandleTypeDef *hrng)
Return a 32-bit random number with interrupt enabled (Obsolete).
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generate a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generate a 32-bit random number in interrupt mode.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handle RNG interrupt request.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callback.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Return the RNG handle state.

Detailed Description

Header file of RNG HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_rng.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rtc.h File Reference

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stm32l4xx_hal_rtc.h File Reference

Header file of RTC HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_rtc_ex.h"

Go to the source code of this file.

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_HandleTypeDef
Time Handle Structure definition. More...

Defines

#define | RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define | RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
#define | RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define | RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
#define | RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define | RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)
#define | RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000)
#define | RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)
#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40)
#define | RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define | RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define | RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
#define | RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define | RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
#define | RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define | RTC_FORMAT_BCD ((uint32_t)0x000000001)
#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)
#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
#define | RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
#define | RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE
#define | RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000)
#define | RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000)
#define | RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000)
#define | RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000)
#define | RTC_IT_TS ((uint32_t)RTC_CR_TSIE)
#define | RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)
#define | RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
#define | RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
#define | RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE)
#define | RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
#define | RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)
#define | RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)
#define | RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
#define | RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
#define | RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
#define | RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
#define | RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define | RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#define | RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
#define | RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define | RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define | RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
#define | RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
#define | RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
#define | RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
#define | RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
#define | RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
#define | RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
#define | RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)
#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Alarm interrupt is enabled or not.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.
#define | RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define | RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define | RTC_TIMEOUT_VALUE 1000
#define | RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00040000)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
#define | IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00, HAL_RTC_STATE_READY = 0x01, HAL_RTC_STATE_BUSY = 0x02, HAL_RTC_STATE_TIMEOUT = 0x03,
HAL_RTC_STATE_ERROR = 0x04
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

Header file of RTC HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_rtc.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rtc_ex.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_hal_rtc_ex.h File Reference

Header file of RTC HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RTC_TamperTypeDef
RTC Tamper structure definition. More...

Defines

#define | RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define | RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
#define | RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
#define | RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
#define | RTC_BKP_DR0 ((uint32_t)0x00000000)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000A)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000B)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000C)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000D)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000E)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000F)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013)
#define | RTC_BKP_DR20 ((uint32_t)0x00000014)
#define | RTC_BKP_DR21 ((uint32_t)0x00000015)
#define | RTC_BKP_DR22 ((uint32_t)0x00000016)
#define | RTC_BKP_DR23 ((uint32_t)0x00000017)
#define | RTC_BKP_DR24 ((uint32_t)0x00000018)
#define | RTC_BKP_DR25 ((uint32_t)0x00000019)
#define | RTC_BKP_DR26 ((uint32_t)0x0000001A)
#define | RTC_BKP_DR27 ((uint32_t)0x0000001B)
#define | RTC_BKP_DR28 ((uint32_t)0x0000001C)
#define | RTC_BKP_DR29 ((uint32_t)0x0000001D)
#define | RTC_BKP_DR30 ((uint32_t)0x0000001E)
#define | RTC_BKP_DR31 ((uint32_t)0x0000001F)
#define | RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define | RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
#define | RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
#define | RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
#define | RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE
#define | RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
#define | RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE
#define | RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE
#define | RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
#define | RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
#define | RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)
#define | RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)
#define | RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800)
#define | RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000)
#define | RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700)
#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS)
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000)
#define | RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
#define | RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000)
#define | RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000)
#define | RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000)
#define | RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000)
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000)
#define | RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
#define | RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
#define | RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
#define | RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Wake Up timer interrupt is enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Tamper interrupt is enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the specified RTC Time Stamp interrupt is enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC Internal Time Stamp's flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Internal Time Stamp's pending flags.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
Get the selected RTC shift operation's flag status.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000)
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000)
#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
#define | IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != (uint32_t)RESET))
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TAMPER_ERASE_MODE(MODE)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(STATE)
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_PULLUP_STATE(STATE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Read data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Header file of RTC HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_rtc_ex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sai.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32l4xx_hal_sai.h File Reference

Header file of SAI HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SAI_InitTypeDef
struct | SAI_FrameInitTypeDef
struct | SAI_SlotInitTypeDef
struct | __SAI_HandleTypeDef

Defines

#define | HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U)
#define | HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U)
#define | HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U)
#define | HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U)
#define | HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)
#define | HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U)
#define | HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)
#define | HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U)
#define | SAI_SYNCEXT_DISABLE 0
#define | SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
#define | SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
#define | SAI_I2S_STANDARD 0
#define | SAI_I2S_MSBJUSTIFIED 1
#define | SAI_I2S_LSBJUSTIFIED 2
#define | SAI_PCM_LONG 3
#define | SAI_PCM_SHORT 4
#define | SAI_PROTOCOL_DATASIZE_16BIT 0
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
#define | SAI_PROTOCOL_DATASIZE_24BIT 2
#define | SAI_PROTOCOL_DATASIZE_32BIT 3
#define | SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U)
#define | SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U)
#define | SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U)
#define | SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U)
#define | SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U)
#define | SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U)
#define | SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U)
#define | SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U)
#define | SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U)
#define | SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U)
#define | SAI_MODEMASTER_TX ((uint32_t)0x00000000U)
#define | SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
#define | SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
#define | SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
#define | SAI_FREE_PROTOCOL ((uint32_t)0x00000000U)
#define | SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
#define | SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
#define | SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
#define | SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
#define | SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
#define | SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
#define | SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
#define | SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
#define | SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
#define | SAI_CLOCKSTROBING_FALLINGEDGE 0
#define | SAI_CLOCKSTROBING_RISINGEDGE 1
#define | SAI_ASYNCHRONOUS 0
#define | SAI_SYNCHRONOUS 1
#define | SAI_SYNCHRONOUS_EXT_SAI1 2
#define | SAI_SYNCHRONOUS_EXT_SAI2 3
#define | SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U)
#define | SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)
#define | SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U)
#define | SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)
#define | SAI_FS_STARTFRAME ((uint32_t)0x00000000U)
#define | SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
#define | SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U)
#define | SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)
#define | SAI_FS_FIRSTBIT ((uint32_t)0x00000000U)
#define | SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
#define | SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)
#define | SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
#define | SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
#define | SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U)
#define | SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U)
#define | SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U)
#define | SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U)
#define | SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U)
#define | SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U)
#define | SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U)
#define | SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U)
#define | SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U)
#define | SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U)
#define | SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U)
#define | SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U)
#define | SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U)
#define | SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U)
#define | SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U)
#define | SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U)
#define | SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U)
#define | SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU)
#define | SAI_STEREOMODE ((uint32_t)0x00000000U)
#define | SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
#define | SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U)
#define | SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
#define | SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U)
#define | SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))
#define | SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))
#define | SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
#define | SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))
#define | SAI_NOCOMPANDING ((uint32_t)0x00000000U)
#define | SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))
#define | SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
#define | SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
#define | SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
#define | SAI_ZERO_VALUE ((uint32_t)0x00000000U)
#define | SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
#define | SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
#define | SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
#define | SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
#define | SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
#define | SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
#define | SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
#define | SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
#define | SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
#define | SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
#define | SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
#define | SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
#define | SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
#define | SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
#define | SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
#define | SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U)
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U)
#define | SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U)
#define | SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U)
#define | SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U)
#define | SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U)
#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable or disable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SAI interrupt source is enabled or not.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
#define | IS_SAI_BLOCK_SYNCEXT(STATE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))

Typedefs

typedef void(* | SAIcallback )(void)
SAI Callback prototype.
typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00U, HAL_SAI_STATE_READY = 0x01U, HAL_SAI_STATE_BUSY = 0x02U, HAL_SAI_STATE_BUSY_TX = 0x12U,
HAL_SAI_STATE_BUSY_RX = 0x22U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Header file of SAI HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_sai.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smartcard.h File Reference

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stm32l4xx_hal_smartcard.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_smartcard_ex.h"

Go to the source code of this file.

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Defines

#define | SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
#define | SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ)
#define | SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ)
#define | SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)
#define | SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)
#define | SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)
#define | SMARTCARD_IT_MASK ((uint16_t)0x001F)
#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 5000001)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00U, HAL_SMARTCARD_STATE_READY = 0x20U, HAL_SMARTCARD_STATE_BUSY = 0x24U, HAL_SMARTCARD_STATE_BUSY_TX = 0x21U,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, HAL_SMARTCARD_STATE_ERROR = 0xE0U
}
HAL SMARTCARD State structures definition. More...
enum HAL_SMARTCARD_ErrorTypeDef {
HAL_SMARTCARD_ERROR_NONE = 0x00, HAL_SMARTCARD_ERROR_PE = 0x01, HAL_SMARTCARD_ERROR_NE = 0x02, HAL_SMARTCARD_ERROR_FE = 0x04,
HAL_SMARTCARD_ERROR_ORE = 0x08, HAL_SMARTCARD_ERROR_DMA = 0x10, HAL_SMARTCARD_ERROR_RTO = 0x20
}
HAL SMARTCARD Error Code structure definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, SMARTCARD_CLOCKSOURCE_HSI = 0x02, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04,
SMARTCARD_CLOCKSOURCE_LSE = 0x08, SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10
}
SMARTCARD clock sources. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_smartcard.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smartcard_ex.h File Reference

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stm32l4xx_hal_smartcard_ex.h File Reference

Header file of SMARTCARD HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TC SMARTCARD_IT_TC
#define | SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
#define | SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_IT_PE ((uint16_t)0x0028)
#define | SMARTCARD_IT_TXE ((uint16_t)0x0727)
#define | SMARTCARD_IT_TC ((uint16_t)0x0626)
#define | SMARTCARD_IT_RXNE ((uint16_t)0x0525)
#define | SMARTCARD_IT_IDLE ((uint16_t)0x0424)
#define | SMARTCARD_IT_ERR ((uint16_t)0x0060)
#define | SMARTCARD_IT_ORE ((uint16_t)0x0300)
#define | SMARTCARD_IT_NE ((uint16_t)0x0200)
#define | SMARTCARD_IT_FE ((uint16_t)0x0100)
#define | SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
#define | SMARTCARD_IT_RTO ((uint16_t)0x0B3A)
#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NCF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF
#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC)
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
Ensure that SMARTCARD frame transmission completion used flag is valid.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Header file of SMARTCARD HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_smartcard_ex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smbus.h File Reference

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stm32l4xx_hal_smbus.h File Reference

Header file of SMBUS HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SMBUS_InitTypeDef
struct | SMBUS_HandleTypeDef

Defines

#define | HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000)
#define | HAL_SMBUS_STATE_READY ((uint32_t)0x00000001)
#define | HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042)
#define | HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003)
#define | HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004)
#define | HAL_SMBUS_STATE_LISTEN ((uint32_t)0x00000008)
#define | HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001)
#define | HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002)
#define | HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004)
#define | HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008)
#define | HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020)
#define | HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040)
#define | HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080)
#define | SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
#define | SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
#define | SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | SMBUS_OA2_NOMASK ((uint8_t)0x00)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07)
#define | SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | SMBUS_PEC_DISABLE ((uint32_t)0x00000000)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN)
#define | SMBUS_SOFTEND_MODE ((uint32_t)0x00000000)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
#define | SMBUS_NO_STARTSTOP ((uint32_t)0x00000000)
#define | SMBUS_GENERATE_STOP I2C_CR2_STOP
#define | SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE I2C_CR2_START
#define | SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE))
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define | SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR
#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define | SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Header file of SMBUS HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_smbus.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_spi.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32l4xx_hal_spi.h File Reference

Header file of SPI HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_spi_ex.h"

Go to the source code of this file.

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Defines

#define | HAL_SPI_ERROR_NONE (uint32_t)0x00000000
#define | HAL_SPI_ERROR_MODF (uint32_t)0x00000001
#define | HAL_SPI_ERROR_CRC (uint32_t)0x00000002
#define | HAL_SPI_ERROR_OVR (uint32_t)0x00000004
#define | HAL_SPI_ERROR_FRE (uint32_t)0x00000008
#define | HAL_SPI_ERROR_DMA (uint32_t)0x00000010
#define | HAL_SPI_ERROR_FLAG (uint32_t)0x00000020
#define | HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040
#define | SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define | SPI_DATASIZE_4BIT ((uint32_t)0x0300)
#define | SPI_DATASIZE_5BIT ((uint32_t)0x0400)
#define | SPI_DATASIZE_6BIT ((uint32_t)0x0500)
#define | SPI_DATASIZE_7BIT ((uint32_t)0x0600)
#define | SPI_DATASIZE_8BIT ((uint32_t)0x0700)
#define | SPI_DATASIZE_9BIT ((uint32_t)0x0800)
#define | SPI_DATASIZE_10BIT ((uint32_t)0x0900)
#define | SPI_DATASIZE_11BIT ((uint32_t)0x0A00)
#define | SPI_DATASIZE_12BIT ((uint32_t)0x0B00)
#define | SPI_DATASIZE_13BIT ((uint32_t)0x0C00)
#define | SPI_DATASIZE_14BIT ((uint32_t)0x0D00)
#define | SPI_DATASIZE_15BIT ((uint32_t)0x0E00)
#define | SPI_DATASIZE_16BIT ((uint32_t)0x0F00)
#define | SPI_POLARITY_LOW ((uint32_t)0x00000000)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL
#define | SPI_PHASE_1EDGE ((uint32_t)0x00000000)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA
#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
#define | SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)
#define | SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
#define | SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
#define | SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
#define | SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
#define | SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
#define | SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
#define | SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
#define | SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
#define | SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define | SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF
#define | SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
#define | SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)
#define | SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)
#define | SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)
#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)
#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE
#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define | SPI_FTLVL_EMPTY ((uint32_t)0x0000)
#define | SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
#define | SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
#define | SPI_FTLVL_FULL ((uint32_t)0x1800)
#define | SPI_FRLVL_EMPTY ((uint32_t)0x0000)
#define | SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
#define | SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
#define | SPI_FRLVL_FULL ((uint32_t)0x0600)
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
Disable the SPI peripheral.
#define | SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_NSSP(NSSP)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_TIMODE(MODE)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_LENGTH(LENGTH)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00, HAL_SPI_STATE_READY = 0x01, HAL_SPI_STATE_BUSY = 0x02, HAL_SPI_STATE_BUSY_TX = 0x03,
HAL_SPI_STATE_BUSY_RX = 0x04, HAL_SPI_STATE_BUSY_TX_RX = 0x05, HAL_SPI_STATE_ERROR = 0x06
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
DeInitialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
DeInitialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

Header file of SPI HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_spi.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_spi_ex.h File Reference

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Functions
stm32l4xx_hal_spi_ex.h File Reference

Header file of SPI HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Header file of SPI HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_spi_ex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sram.h File Reference

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stm32l4xx_hal_sram.h File Reference

Header file of SRAM HAL module. More...

#include "stm32l4xx_ll_fmc.h"

Go to the source code of this file.

Data Structures

struct | SRAM_HandleTypeDef
SRAM handle Structure definition. More...

Defines

#define | __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
Reset SRAM handle state.

Enumerations

enum HAL_SRAM_StateTypeDef {
HAL_SRAM_STATE_RESET = 0x00, HAL_SRAM_STATE_READY = 0x01, HAL_SRAM_STATE_BUSY = 0x02, HAL_SRAM_STATE_ERROR = 0x03,
HAL_SRAM_STATE_PROTECTED = 0x04
}
HAL SRAM State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Perform the SRAM device de-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
Initialize the SRAM MSP.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
DeInitialize the SRAM MSP.
__weak void | HAL_SRAM_DMA_XferCpltCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
__weak void | HAL_SRAM_DMA_XferErrorCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Read 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Write 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Read 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Write 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Read 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Write 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Read a Word data buffer from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Write a Word data buffer to SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enable dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disable dynamically SRAM write operation.
HAL_SRAM_StateTypeDef | HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Return the SRAM controller handle state.

Detailed Description

Header file of SRAM HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_sram.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_swpmi.h File Reference

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stm32l4xx_hal_swpmi.h File Reference

Header file of SWPMI HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SWPMI_InitTypeDef
SWPMI Init Structure definition. More...
struct | SWPMI_HandleTypeDef
SWPMI handle Structure definition. More...

Defines

#define | HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000)
#define | HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004)
#define | HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008)
#define | HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C)
#define | HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010)
#define | SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define | SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS
#define | SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE
#define | SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define | SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE
#define | SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF
#define | SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF
#define | SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF
#define | SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF
#define | SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF
#define | SWPMI_FLAG_RXNE SWPMI_ISR_RXNE
#define | SWPMI_FLAG_TXE SWPMI_ISR_TXE
#define | SWPMI_FLAG_TCF SWPMI_ISR_TCF
#define | SWPMI_FLAG_SRF SWPMI_ISR_SRF
#define | SWPMI_FLAG_SUSP SWPMI_ISR_SUSP
#define | SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF
#define | SWPMI_IT_SRIE SWPMI_IER_SRIE
#define | SWPMI_IT_TCIE SWPMI_IER_TCIE
#define | SWPMI_IT_TIE SWPMI_IER_TIE
#define | SWPMI_IT_RIE SWPMI_IER_RIE
#define | SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE
#define | SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE
#define | SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE
#define | SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE
#define | SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE
#define | __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
Reset SWPMI handle state.
#define | __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Enable the SWPMI peripheral.
#define | __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
Disable the SWPMI peripheral.
#define | __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified SWPMI flag is set or not.
#define | __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
Clear the specified SWPMI ISR flag.
#define | __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Enable the specified SWPMI interrupt.
#define | __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
Disable the specified SWPMI interrupt.
#define | __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
Check whether the specified SWPMI interrupt has occurred or not.
#define | __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
Check whether the specified SWPMI interrupt source is enabled or not.
#define | IS_SWPMI_VOLTAGE_CLASS(__CLASS__)
#define | IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
#define | IS_SWPMI_TX_BUFFERING_MODE(__MODE__)
#define | IS_SWPMI_RX_BUFFERING_MODE(__MODE__)

Enumerations

enum HAL_SWPMI_StateTypeDef {
HAL_SWPMI_STATE_RESET = 0x00, HAL_SWPMI_STATE_READY = 0x01, HAL_SWPMI_STATE_BUSY = 0x02, HAL_SWPMI_STATE_BUSY_TX = 0x12,
HAL_SWPMI_STATE_BUSY_RX = 0x22, HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, HAL_SWPMI_STATE_TIMEOUT = 0x03, HAL_SWPMI_STATE_ERROR = 0x04
}
HAL SWPMI State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.
HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.
void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.
HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Detailed Description

Header file of SWPMI HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_swpmi.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tim.h File Reference

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stm32l4xx_hal_tim.h File Reference

Header file of TIM HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_tim_ex.h"

Go to the source code of this file.

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Defines

#define | TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
#define | TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
#define | TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
#define | TIM_DMABASE_CR1 (0x00000000)
#define | TIM_DMABASE_CR2 (0x00000001)
#define | TIM_DMABASE_SMCR (0x00000002)
#define | TIM_DMABASE_DIER (0x00000003)
#define | TIM_DMABASE_SR (0x00000004)
#define | TIM_DMABASE_EGR (0x00000005)
#define | TIM_DMABASE_CCMR1 (0x00000006)
#define | TIM_DMABASE_CCMR2 (0x00000007)
#define | TIM_DMABASE_CCER (0x00000008)
#define | TIM_DMABASE_CNT (0x00000009)
#define | TIM_DMABASE_PSC (0x0000000A)
#define | TIM_DMABASE_ARR (0x0000000B)
#define | TIM_DMABASE_RCR (0x0000000C)
#define | TIM_DMABASE_CCR1 (0x0000000D)
#define | TIM_DMABASE_CCR2 (0x0000000E)
#define | TIM_DMABASE_CCR3 (0x0000000F)
#define | TIM_DMABASE_CCR4 (0x00000010)
#define | TIM_DMABASE_BDTR (0x00000011)
#define | TIM_DMABASE_DCR (0x00000012)
#define | TIM_DMABASE_DMAR (0x00000013)
#define | TIM_DMABASE_OR1 (0x00000014)
#define | TIM_DMABASE_CCMR3 (0x00000015)
#define | TIM_DMABASE_CCR5 (0x00000016)
#define | TIM_DMABASE_CCR6 (0x00000017)
#define | TIM_DMABASE_OR2 (0x00000018)
#define | TIM_DMABASE_OR3 (0x00000019)
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
#define | TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000)
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000)
#define | TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000)
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)
#define | TIM_COUNTERMODE_UP ((uint32_t)0x0000)
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
#define | TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
#define | TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
#define | TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
#define | TIM_OCFAST_DISABLE ((uint32_t)0x0000)
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
#define | TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
#define | TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
#define | TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
#define | TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)
#define | TIM_ICPSC_DIV1 ((uint32_t)0x0000)
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)
#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)
#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)
#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_CC5 (TIM_SR_CC5IF)
#define | TIM_FLAG_CC6 (TIM_SR_CC6IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_BREAK2 (TIM_SR_B2IF)
#define | TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)
#define | TIM_CHANNEL_1 ((uint32_t)0x0000)
#define | TIM_CHANNEL_2 ((uint32_t)0x0004)
#define | TIM_CHANNEL_3 ((uint32_t)0x0008)
#define | TIM_CHANNEL_4 ((uint32_t)0x000C)
#define | TIM_CHANNEL_5 ((uint32_t)0x0010)
#define | TIM_CHANNEL_6 ((uint32_t)0x0014)
#define | TIM_CHANNEL_ALL ((uint32_t)0x003C)
#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE ((uint32_t)0x0000)
#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE ((uint32_t)0x0000)
#define | TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE ((uint32_t)0x0000)
#define | TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
#define | TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
#define | TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
#define | TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
#define | TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
#define | TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define | TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define | TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define | TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
#define | TIM_TRGO_RESET ((uint32_t)0x0000)
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO2_RESET ((uint32_t)0x00000000)
#define | TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
#define | TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
#define | TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
#define | TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
#define | TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
#define | TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
#define | TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
#define | TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
#define | TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
#define | TIM_OCMODE_TIMING ((uint32_t)0x0000)
#define | TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
#define | TIM_TS_ITR0 ((uint32_t)0x0000)
#define | TIM_TS_ITR1 ((uint32_t)0x0010)
#define | TIM_TS_ITR2 ((uint32_t)0x0020)
#define | TIM_TS_ITR3 ((uint32_t)0x0030)
#define | TIM_TS_TI1F_ED ((uint32_t)0x0040)
#define | TIM_TS_TI1FP1 ((uint32_t)0x0050)
#define | TIM_TS_TI2FP2 ((uint32_t)0x0060)
#define | TIM_TS_ETRF ((uint32_t)0x0070)
#define | TIM_TS_NONE ((uint32_t)0xFFFF)
#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
#define | TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
#define | TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
#define | TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
#define | TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
#define | TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
#define | TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
#define | TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
#define | TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
#define | TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
#define | TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
#define | TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
#define | TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
#define | TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
#define | TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
#define | TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
#define | TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
#define | TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
#define | TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x1)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x2)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x3)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x4)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x6)
#define | TIM_CCx_ENABLE ((uint32_t)0x0001)
#define | TIM_CCx_DISABLE ((uint32_t)0x0000)
#define | TIM_CCxN_ENABLE ((uint32_t)0x0004)
#define | TIM_CCxN_DISABLE ((uint32_t)0x0000)
#define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define | TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL
#define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL
#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00, HAL_TIM_STATE_READY = 0x01, HAL_TIM_STATE_BUSY = 0x02, HAL_TIM_STATE_TIMEOUT = 0x03,
HAL_TIM_STATE_ERROR = 0x04
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00
}
HAL Active channel structures definition. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM INput Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 2 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

Header file of TIM HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_tim.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tim_ex.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_hal_tim_ex.h File Reference

Header file of TIM HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...

Defines

#define | TIM_TIM1_ETR_ADC1_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define | TIM_TIM1_ETR_ADC1_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | TIM_TIM1_ETR_ADC1_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | TIM_TIM1_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define | TIM_TIM1_ETR_ADC3_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM1_ETR_ADC3_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */
#define | TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */
#define | TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */
#define | TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */
#define | TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */
#define | TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */
#define | TIM_TIM2_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM2_ETR is connected to GPIO */
#define | TIM_TIM2_ETR_LSE (TIM2_OR1_ETR1_RMP) /* !< TIM2_ETR is connected to LSE */
#define | TIM_TIM2_ETR_COMP1 (TIM2_OR2_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 output */
#define | TIM_TIM2_ETR_COMP2 (TIM2_OR2_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 output */
#define | TIM_TIM2_TI4_GPIO ((uint32_t)(0x00000000)) /* !< TIM2 TI4 is connected to GPIO */
#define | TIM_TIM2_TI4_COMP1 (TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to COMP1 output */
#define | TIM_TIM2_TI4_COMP2 (TIM2_OR1_TI4_RMP_1) /* !< TIM2 TI4 is connected to COMP2 output */
#define | TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
#define | TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */
#define | TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */
#define | TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */
#define | TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
#define | TIM_TIM3_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM3_ETR is connected to GPIO */
#define | TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */
#define | TIM_TIM8_ETR_ADC2_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define | TIM_TIM8_ETR_ADC2_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define | TIM_TIM8_ETR_ADC2_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define | TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define | TIM_TIM8_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define | TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define | TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define | TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */
#define | TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */
#define | TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */
#define | TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */
#define | TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */
#define | TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */
#define | TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */
#define | TIM_TIM15_ENCODERMODE_NONE ((uint32_t)(0x00000000)) /* !< No redirection */
#define | TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#define | TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#define | TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#define | TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */
#define | TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */
#define | TIM_TIM16_TI1_LSE (TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to LSE */
#define | TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
#define | TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */
#define | TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */
#define | TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */
#define | TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */
#define | TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */
#define | TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */
#define | TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */
#define | TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
#define | TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
#define | IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

Header file of TIM HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_tim_ex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tsc.h File Reference

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stm32l4xx_hal_tsc.h File Reference

Header file of TSC HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TSC_InitTypeDef
TSC init structure definition. More...
struct | TSC_IOConfigTypeDef
TSC IOs configuration structure definition. More...
struct | TSC_HandleTypeDef
TSC handle Structure definition. More...

Defines

#define | TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28))
#define | TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28))
#define | TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28))
#define | TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28))
#define | TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28))
#define | TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28))
#define | TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28))
#define | TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28))
#define | TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28))
#define | TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
#define | TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
#define | TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
#define | TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
#define | TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
#define | TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
#define | TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
#define | TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24))
#define | TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24))
#define | TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24))
#define | TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24))
#define | TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24))
#define | TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24))
#define | TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24))
#define | TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24))
#define | TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24))
#define | TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
#define | TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
#define | TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
#define | TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
#define | TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
#define | TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
#define | TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
#define | TSC_SS_PRESC_DIV1 ((uint32_t)0)
#define | TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
#define | TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))
#define | TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))
#define | TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12))
#define | TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12))
#define | TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12))
#define | TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))
#define | TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))
#define | TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
#define | TSC_MCV_255 ((uint32_t)(0 << 5))
#define | TSC_MCV_511 ((uint32_t)(1 << 5))
#define | TSC_MCV_1023 ((uint32_t)(2 << 5))
#define | TSC_MCV_2047 ((uint32_t)(3 << 5))
#define | TSC_MCV_4095 ((uint32_t)(4 << 5))
#define | TSC_MCV_8191 ((uint32_t)(5 << 5))
#define | TSC_MCV_16383 ((uint32_t)(6 << 5))
#define | TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
#define | TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
#define | TSC_SYNC_POLARITY_FALLING ((uint32_t)0)
#define | TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
#define | TSC_ACQ_MODE_NORMAL ((uint32_t)0)
#define | TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
#define | TSC_IOMODE_UNUSED ((uint32_t)0)
#define | TSC_IOMODE_CHANNEL ((uint32_t)1)
#define | TSC_IOMODE_SHIELD ((uint32_t)2)
#define | TSC_IOMODE_SAMPLING ((uint32_t)3)
#define | TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
#define | TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
#define | TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
#define | TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
#define | TSC_NB_OF_GROUPS (8)
#define | TSC_GROUP1 ((uint32_t)0x00000001)
#define | TSC_GROUP2 ((uint32_t)0x00000002)
#define | TSC_GROUP3 ((uint32_t)0x00000004)
#define | TSC_GROUP4 ((uint32_t)0x00000008)
#define | TSC_GROUP5 ((uint32_t)0x00000010)
#define | TSC_GROUP6 ((uint32_t)0x00000020)
#define | TSC_GROUP7 ((uint32_t)0x00000040)
#define | TSC_GROUP8 ((uint32_t)0x00000080)
#define | TSC_ALL_GROUPS ((uint32_t)0x000000FF)
#define | TSC_GROUP1_IDX ((uint32_t)0)
#define | TSC_GROUP2_IDX ((uint32_t)1)
#define | TSC_GROUP3_IDX ((uint32_t)2)
#define | TSC_GROUP4_IDX ((uint32_t)3)
#define | TSC_GROUP5_IDX ((uint32_t)4)
#define | TSC_GROUP6_IDX ((uint32_t)5)
#define | TSC_GROUP7_IDX ((uint32_t)6)
#define | TSC_GROUP8_IDX ((uint32_t)7)
#define | TSC_GROUP1_IO1 ((uint32_t)0x00000001)
#define | TSC_GROUP1_IO2 ((uint32_t)0x00000002)
#define | TSC_GROUP1_IO3 ((uint32_t)0x00000004)
#define | TSC_GROUP1_IO4 ((uint32_t)0x00000008)
#define | TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
#define | TSC_GROUP2_IO1 ((uint32_t)0x00000010)
#define | TSC_GROUP2_IO2 ((uint32_t)0x00000020)
#define | TSC_GROUP2_IO3 ((uint32_t)0x00000040)
#define | TSC_GROUP2_IO4 ((uint32_t)0x00000080)
#define | TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
#define | TSC_GROUP3_IO1 ((uint32_t)0x00000100)
#define | TSC_GROUP3_IO2 ((uint32_t)0x00000200)
#define | TSC_GROUP3_IO3 ((uint32_t)0x00000400)
#define | TSC_GROUP3_IO4 ((uint32_t)0x00000800)
#define | TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
#define | TSC_GROUP4_IO1 ((uint32_t)0x00001000)
#define | TSC_GROUP4_IO2 ((uint32_t)0x00002000)
#define | TSC_GROUP4_IO3 ((uint32_t)0x00004000)
#define | TSC_GROUP4_IO4 ((uint32_t)0x00008000)
#define | TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
#define | TSC_GROUP5_IO1 ((uint32_t)0x00010000)
#define | TSC_GROUP5_IO2 ((uint32_t)0x00020000)
#define | TSC_GROUP5_IO3 ((uint32_t)0x00040000)
#define | TSC_GROUP5_IO4 ((uint32_t)0x00080000)
#define | TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
#define | TSC_GROUP6_IO1 ((uint32_t)0x00100000)
#define | TSC_GROUP6_IO2 ((uint32_t)0x00200000)
#define | TSC_GROUP6_IO3 ((uint32_t)0x00400000)
#define | TSC_GROUP6_IO4 ((uint32_t)0x00800000)
#define | TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
#define | TSC_GROUP7_IO1 ((uint32_t)0x01000000)
#define | TSC_GROUP7_IO2 ((uint32_t)0x02000000)
#define | TSC_GROUP7_IO3 ((uint32_t)0x04000000)
#define | TSC_GROUP7_IO4 ((uint32_t)0x08000000)
#define | TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
#define | TSC_GROUP8_IO1 ((uint32_t)0x10000000)
#define | TSC_GROUP8_IO2 ((uint32_t)0x20000000)
#define | TSC_GROUP8_IO3 ((uint32_t)0x40000000)
#define | TSC_GROUP8_IO4 ((uint32_t)0x80000000)
#define | TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)
#define | TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)
#define | __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
Reset TSC handle state.
#define | __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
Enable the TSC peripheral.
#define | __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
Disable the TSC peripheral.
#define | __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
Start acquisition.
#define | __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
Stop acquisition.
#define | __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
Set IO default mode to output push-pull low.
#define | __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
Set IO default mode to input floating.
#define | __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
Set synchronization polarity to falling edge.
#define | __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
Set synchronization polarity to rising edge and high level.
#define | __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable TSC interrupt.
#define | __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
Disable TSC interrupt.
#define | __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified TSC interrupt source is enabled or not.
#define | __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified TSC flag is set or not.
#define | __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the TSC's pending flag.
#define | __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
Enable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Open analog switch on a group of IOs.
#define | __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
Close analog switch on a group of IOs.
#define | __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
Enable a group of IOs in channel mode.
#define | __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable a group of channel IOs.
#define | __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
Enable a group of IOs in sampling mode.
#define | __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
Disable a group of sampling IOs.
#define | __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
Enable acquisition groups.
#define | __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
Disable acquisition groups.
#define | __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
Gets acquisition group status.
#define | IS_TSC_CTPH(VAL)
#define | IS_TSC_CTPL(VAL)
#define | IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
#define | IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
#define | IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
#define | IS_TSC_PG_PRESC(VAL)
#define | IS_TSC_MCV(VAL)
#define | IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
#define | IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
#define | IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
#define | IS_TSC_IOMODE(VAL)
#define | IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
#define | IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))

Enumerations

enum | HAL_TSC_StateTypeDef { HAL_TSC_STATE_RESET = 0x00, HAL_TSC_STATE_READY = 0x01, HAL_TSC_STATE_BUSY = 0x02, HAL_TSC_STATE_ERROR = 0x03 }
TSC state structure definition. More...
enum | TSC_GroupStatusTypeDef { TSC_GROUP_ONGOING = 0x00, TSC_GROUP_COMPLETED = 0x01 }
TSC group status structure definition. More...

Functions

HAL_StatusTypeDef | HAL_TSC_Init (TSC_HandleTypeDef *htsc)
Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_TSC_DeInit (TSC_HandleTypeDef *htsc)
Deinitialize the TSC peripheral registers to their default reset values.
__weak void | HAL_TSC_MspInit (TSC_HandleTypeDef *htsc)
Initialize the TSC MSP.
__weak void | HAL_TSC_MspDeInit (TSC_HandleTypeDef *htsc)
DeInitialize the TSC MSP.
HAL_StatusTypeDef | HAL_TSC_Start (TSC_HandleTypeDef *htsc)
Start the acquisition.
HAL_StatusTypeDef | HAL_TSC_Start_IT (TSC_HandleTypeDef *htsc)
Start the acquisition in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_Stop (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in polling mode.
HAL_StatusTypeDef | HAL_TSC_Stop_IT (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_PollForAcquisition (TSC_HandleTypeDef *htsc)
Start acquisition and wait until completion.
TSC_GroupStatusTypeDef | HAL_TSC_GroupGetStatus (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition status for a group.
uint32_t | HAL_TSC_GroupGetValue (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition measure for a group.
HAL_StatusTypeDef | HAL_TSC_IOConfig (TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
Configure TSC IOs.
HAL_StatusTypeDef | HAL_TSC_IODischarge (TSC_HandleTypeDef *htsc, uint32_t choice)
Discharge TSC IOs.
HAL_TSC_StateTypeDef | HAL_TSC_GetState (TSC_HandleTypeDef *htsc)
Return the TSC handle state.
void | HAL_TSC_IRQHandler (TSC_HandleTypeDef *htsc)
Handle TSC interrupt request.
__weak void | HAL_TSC_ConvCpltCallback (TSC_HandleTypeDef *htsc)
Acquisition completed callback in non-blocking mode.
__weak void | HAL_TSC_ErrorCallback (TSC_HandleTypeDef *htsc)
Error callback in non-blocking mode.

Detailed Description

Header file of TSC HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_tsc.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_uart.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32l4xx_hal_uart.h File Reference

Header file of UART HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_uart_ex.h"

Go to the source code of this file.

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initalization structure definition. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 ((uint32_t)0x00000000)
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1
#define | UART_PARITY_NONE ((uint32_t)0x00000000)
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | UART_HWCONTROL_NONE ((uint32_t)0x00000000)
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | UART_STATE_DISABLE ((uint32_t)0x00000000)
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define | UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
#define | UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
#define | UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define | UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)
#define | UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000)
#define | UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
#define | UART_LIN_DISABLE ((uint32_t)0x00000000)
#define | UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)
#define | UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
#define | UART_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define | UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
#define | UART_DMA_RX_DISABLE ((uint32_t)0x00000000)
#define | UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
#define | UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000)
#define | UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)
#define | UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
#define | UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ)
#define | UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ)
#define | UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ)
#define | UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
#define | UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
#define | UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
#define | UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040)
#define | UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
#define | UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
#define | UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
#define | UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
#define | UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
#define | UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)
#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
#define | UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
#define | UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)
#define | UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000)
#define | UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)
#define | UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24)
#define | UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000)
#define | UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)
#define | UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)
#define | UART_DE_POLARITY_HIGH ((uint32_t)0x00000000)
#define | UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)
#define | UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21)
#define | UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16)
#define | UART_IT_MASK ((uint32_t)0x001F)
#define | HAL_UART_TIMEOUT_VALUE 0x1FFFFFF
#define | UART_FLAG_REACK ((uint32_t)0x00400000)
#define | UART_FLAG_TEACK ((uint32_t)0x00200000)
#define | UART_FLAG_WUF ((uint32_t)0x00100000)
#define | UART_FLAG_RWU ((uint32_t)0x00080000)
#define | UART_FLAG_SBKF ((uint32_t)0x00040000)
#define | UART_FLAG_CMF ((uint32_t)0x00020000)
#define | UART_FLAG_BUSY ((uint32_t)0x00010000)
#define | UART_FLAG_ABRF ((uint32_t)0x00008000)
#define | UART_FLAG_ABRE ((uint32_t)0x00004000)
#define | UART_FLAG_EOBF ((uint32_t)0x00001000)
#define | UART_FLAG_RTOF ((uint32_t)0x00000800)
#define | UART_FLAG_CTS ((uint32_t)0x00000400)
#define | UART_FLAG_CTSIF ((uint32_t)0x00000200)
#define | UART_FLAG_LBDF ((uint32_t)0x00000100)
#define | UART_FLAG_TXE ((uint32_t)0x00000080)
#define | UART_FLAG_TC ((uint32_t)0x00000040)
#define | UART_FLAG_RXNE ((uint32_t)0x00000020)
#define | UART_FLAG_IDLE ((uint32_t)0x00000010)
#define | UART_FLAG_ORE ((uint32_t)0x00000008)
#define | UART_FLAG_NE ((uint32_t)0x00000004)
#define | UART_FLAG_FE ((uint32_t)0x00000002)
#define | UART_FLAG_PE ((uint32_t)0x00000001)
#define | UART_IT_PE ((uint32_t)0x0028)
#define | UART_IT_TXE ((uint32_t)0x0727)
#define | UART_IT_TC ((uint32_t)0x0626)
#define | UART_IT_RXNE ((uint32_t)0x0525)
#define | UART_IT_IDLE ((uint32_t)0x0424)
#define | UART_IT_LBD ((uint32_t)0x0846)
#define | UART_IT_CTS ((uint32_t)0x096A)
#define | UART_IT_CM ((uint32_t)0x112E)
#define | UART_IT_WUF ((uint32_t)0x1476)
#define | UART_IT_ERR ((uint32_t)0x0060)
#define | UART_IT_ORE ((uint32_t)0x0300)
#define | UART_IT_NE ((uint32_t)0x0200)
#define | UART_IT_FE ((uint32_t)0x0100)
#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NCF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | UART_CLEAR_EOBF USART_ICR_EOBCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.
#define | UART_DIV_LPUART(__PCLK__, __BAUD__) ((((uint64_t)(__PCLK__)*256) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00U, HAL_UART_STATE_READY = 0x20U, HAL_UART_STATE_BUSY = 0x24U, HAL_UART_STATE_BUSY_TX = 0x21U,
HAL_UART_STATE_BUSY_RX = 0x22U, HAL_UART_STATE_BUSY_TX_RX = 0x23U, HAL_UART_STATE_TIMEOUT = 0xA0U, HAL_UART_STATE_ERROR = 0xE0U
}
HAL UART State structures definition. More...
enum HAL_UART_ErrorTypeDef {
HAL_UART_ERROR_NONE = 0x00, HAL_UART_ERROR_PE = 0x01, HAL_UART_ERROR_NE = 0x02, HAL_UART_ERROR_FE = 0x04,
HAL_UART_ERROR_ORE = 0x08, HAL_UART_ERROR_DMA = 0x10
}
HAL UART Error Code structure definition. More...
enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00, UART_CLOCKSOURCE_PCLK2 = 0x01, UART_CLOCKSOURCE_HSI = 0x02, UART_CLOCKSOURCE_SYSCLK = 0x04,
UART_CLOCKSOURCE_LSE = 0x08, UART_CLOCKSOURCE_UNDEFINED = 0x10
}
UART clock sources definition. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.

Detailed Description

Header file of UART HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_uart.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_uart_ex.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_hal_uart_ex.h File Reference

Header file of UART HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...

Defines

#define | UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | UART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000)
#define | UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)
#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.

Functions

HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.

Detailed Description

Header file of UART HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_uart_ex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_usart.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32l4xx_hal_usart.h File Reference

Header file of USART HAL module. More...

#include "stm32l4xx_hal_def.h"
#include "stm32l4xx_hal_usart_ex.h"

Go to the source code of this file.

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Defines

#define | USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | USART_STOPBITS_1 ((uint32_t)0x00000000)
#define | USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | USART_STOPBITS_2 USART_CR2_STOP_1
#define | USART_PARITY_NONE ((uint32_t)0x00000000)
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | USART_OVERSAMPLING_16 ((uint32_t)0x00000000)
#define | USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
#define | USART_CLOCK_DISABLE ((uint32_t)0x00000000)
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
#define | USART_POLARITY_LOW ((uint32_t)0x00000000)
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | USART_PHASE_1EDGE ((uint32_t)0x00000000)
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ)
#define | USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ)
#define | USART_FLAG_REACK ((uint32_t)0x00400000)
#define | USART_FLAG_TEACK ((uint32_t)0x00200000)
#define | USART_FLAG_BUSY ((uint32_t)0x00010000)
#define | USART_FLAG_CTS ((uint32_t)0x00000400)
#define | USART_FLAG_CTSIF ((uint32_t)0x00000200)
#define | USART_FLAG_LBDF ((uint32_t)0x00000100)
#define | USART_FLAG_TXE ((uint32_t)0x00000080)
#define | USART_FLAG_TC ((uint32_t)0x00000040)
#define | USART_FLAG_RXNE ((uint32_t)0x00000020)
#define | USART_FLAG_IDLE ((uint32_t)0x00000010)
#define | USART_FLAG_ORE ((uint32_t)0x00000008)
#define | USART_FLAG_NE ((uint32_t)0x00000004)
#define | USART_FLAG_FE ((uint32_t)0x00000002)
#define | USART_FLAG_PE ((uint32_t)0x00000001)
#define | USART_IT_PE ((uint16_t)0x0028)
#define | USART_IT_TXE ((uint16_t)0x0727)
#define | USART_IT_TC ((uint16_t)0x0626)
#define | USART_IT_RXNE ((uint16_t)0x0525)
#define | USART_IT_IDLE ((uint16_t)0x0424)
#define | USART_IT_ERR ((uint16_t)0x0060)
#define | USART_IT_ORE ((uint16_t)0x0300)
#define | USART_IT_NE ((uint16_t)0x0200)
#define | USART_IT_FE ((uint16_t)0x0100)
#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NCF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_IT_MASK ((uint16_t)0x001F)
#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
Ensure that USART communication mode is valid.
#define | IS_USART_OVERSAMPLING(__SAMPLING__)
Ensure that USART oversampling is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00, HAL_USART_STATE_READY = 0x01, HAL_USART_STATE_BUSY = 0x02, HAL_USART_STATE_BUSY_TX = 0x12,
HAL_USART_STATE_BUSY_RX = 0x22, HAL_USART_STATE_BUSY_TX_RX = 0x32, HAL_USART_STATE_TIMEOUT = 0x03, HAL_USART_STATE_ERROR = 0x04
}
HAL USART State structures definition. More...
enum HAL_USART_ErrorTypeDef {
HAL_USART_ERROR_NONE = 0x00, HAL_USART_ERROR_PE = 0x01, HAL_USART_ERROR_NE = 0x02, HAL_USART_ERROR_FE = 0x04,
HAL_USART_ERROR_ORE = 0x08, HAL_USART_ERROR_DMA = 0x10
}
HAL USART Error Code structure definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK1 = 0x00, USART_CLOCKSOURCE_PCLK2 = 0x01, USART_CLOCKSOURCE_HSI = 0x02, USART_CLOCKSOURCE_SYSCLK = 0x04,
USART_CLOCKSOURCE_LSE = 0x08, USART_CLOCKSOURCE_UNDEFINED = 0x10
}
USART clock sources definitions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

Header file of USART HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_usart.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_usart_ex.h File Reference

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Defines
stm32l4xx_hal_usart_ex.h File Reference

Header file of USART HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Defines

#define | USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | USART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.

Detailed Description

Header file of USART HAL Extended module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_usart_ex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_wwdg.h File Reference

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stm32l4xx_hal_wwdg.h File Reference

Header file of WWDG HAL module. More...

#include "stm32l4xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Defines

#define | WWDG_IT_EWI WWDG_CFR_EWI
#define | WWDG_FLAG_EWIF WWDG_SR_EWIF
#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 WWDG_CFR_WDGTB
#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI
#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified WWDG interrupt source is enabled or not.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

Header file of WWDG HAL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_wwdg.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_adc.h File Reference

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stm32l4xx_ll_adc.h File Reference

Header file of ADC LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...

Defines

#define | ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
#define | ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
#define | ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
#define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
#define | ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
#define | ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
#define | ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
#define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
#define | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
#define | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
#define | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
#define | ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_REG_TRIG_SOURCE_MASK
#define | ADC_REG_TRIG_EDGE_MASK
#define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
#define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
#define | ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_INJ_TRIG_SOURCE_MASK
#define | ADC_INJ_TRIG_EDGE_MASK
#define | ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
#define | ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define | ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
#define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
#define | ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
#define | ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
#define | ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
#define | ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
#define | ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define | ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define | ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define | ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define | ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define | ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define | ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define | ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define | ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define | ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define | ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define | ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define | ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define | ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define | ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define | ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define | ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define | ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define | ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
#define | ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
#define | ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
#define | ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
#define | ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
#define | ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
#define | ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
#define | ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
#define | ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
#define | ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
#define | ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
#define | ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
#define | ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
#define | ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
#define | ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
#define | ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
#define | ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
#define | ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
#define | ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
#define | ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define | ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
#define | ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define | ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
#define | ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00100000U)
#define | ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00200000U)
#define | ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024U)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define | ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define | ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define | ADC_OFR1_REGOFFSET ((uint32_t)0x00000000U)
#define | ADC_OFR2_REGOFFSET ((uint32_t)0x00000001U)
#define | ADC_OFR3_REGOFFSET ((uint32_t)0x00000002U)
#define | ADC_OFR4_REGOFFSET ((uint32_t)0x00000003U)
#define | ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
#define | ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
#define | ADC_CFGR_AWD1SGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
#define | ADC_CFGR_AWD1EN_BITOFFSET_POS ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
#define | ADC_CFGR_JAWD1EN_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
#define | ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
#define | ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define | VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | VREFINT_CAL_VREF ((uint32_t) 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
#define | __ADC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define | LL_ADC_FLAG_EOC ADC_ISR_EOC
#define | LL_ADC_FLAG_EOS ADC_ISR_EOS
#define | LL_ADC_FLAG_OVR ADC_ISR_OVR
#define | LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | LL_ADC_FLAG_JEOC ADC_ISR_JEOC
#define | LL_ADC_FLAG_JEOS ADC_ISR_JEOS
#define | LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST
#define | LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV
#define | LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST
#define | LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV
#define | LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST
#define | LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV
#define | LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST
#define | LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV
#define | LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST
#define | LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV
#define | LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST
#define | LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV
#define | LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST
#define | LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV
#define | LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST
#define | LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV
#define | LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST
#define | LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV
#define | LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST
#define | LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV
#define | LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST
#define | LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV
#define | LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define | LL_ADC_IT_EOC ADC_IER_EOCIE
#define | LL_ADC_IT_EOS ADC_IER_EOSIE
#define | LL_ADC_IT_OVR ADC_IER_OVRIE
#define | LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | LL_ADC_IT_JEOC ADC_IER_JEOCIE
#define | LL_ADC_IT_JEOS ADC_IER_JEOSIE
#define | LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define | LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define | LL_ADC_IT_AWD3 ADC_IER_AWD3IE
#define | LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define | LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U)
#define | LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
#define | LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define | LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
#define | LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)
#define | LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define | LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)
#define | LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )
#define | LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
#define | LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)
#define | LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)
#define | LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
#define | LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
#define | LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
#define | LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET
#define | LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)
#define | LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U)
#define | LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U)
#define | LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U)
#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)
#define | LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )
#define | LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)
#define | LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)
#define | LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)
#define | LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)
#define | LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
#define | LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
#define | LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
#define | LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
#define | LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)
#define | LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
#define | LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000U)
#define | LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 )
#define | LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
#define | LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
#define | LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)
#define | LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define | LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
#define | LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)
#define | LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 )
#define | LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1)
#define | LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1)
#define | LL_ADC_OVS_DISABLE ((uint32_t)0x00000000U)
#define | LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )
#define | LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_REG_CONT ((uint32_t)0x00000000U)
#define | LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)
#define | LL_ADC_OVS_RATIO_2 ((uint32_t)0x00000000U)
#define | LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )
#define | LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_SHIFT_NONE ((uint32_t)0x00000000U)
#define | LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
#define | LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )
#define | LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000U)
#define | LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 )
#define | LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 )
#define | LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
#define | LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000U)
#define | LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 )
#define | LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)
#define | LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 )
#define | LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000U)
#define | LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 )
#define | LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
#define | LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)
#define | LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )
#define | LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)
#define | LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
#define | LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
#define | LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
#define | LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
#define | LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
#define | LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define | LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define | LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define | LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define | LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define | LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define | LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define | LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define | LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
#define | LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U)
#define | LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 12U)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U)
#define | LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U)
#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.
#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.
#define | __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))
Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.
#define | __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC123_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE()
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Functions

__STATIC_INLINE uint32_t | LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void | LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution.
__STATIC_INLINE uint32_t | LL_ADC_GetResolution (ADC_TypeDef *ADCx)
Get ADC resolution.
__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
__STATIC_INLINE uint32_t | LL_ADC_GetLowPowerMode (ADC_TypeDef *ADCx)
Get ADC low power mode:
__STATIC_INLINE void | LL_ADC_SetOffset (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
Set ADC selected offset number 1, 2, 3 or 4.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetChannel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetLevel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void | LL_ADC_SetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
Set for the ADC selected offset number 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: offset state disabled or enabled.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void | LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetOverrun (ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group injected conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetQueueMode (ADC_TypeDef *ADCx, uint32_t QueueMode)
Set ADC group injected contexts queue mode.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetQueueMode (ADC_TypeDef *ADCx)
Get ADC group injected context queue mode.
__STATIC_INLINE void | LL_ADC_INJ_ConfigQueueContext (ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
Set one context on ADC group injected that will be checked in contexts queue.
__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
Set mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel)
Get mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_ConfigAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.
__STATIC_INLINE void | LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingScope (ADC_TypeDef *ADCx)
Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE void | LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingDiscont (ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void | LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingRatio (ADC_TypeDef *ADCx)
Get ADC oversampling ratio (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingShift (ADC_TypeDef *ADCx)
Get ADC oversampling shift (impacting both ADC groups regular and injected)
__STATIC_INLINE void | LL_ADC_SetMultimode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t | LL_ADC_GetMultimode (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE void | LL_ADC_SetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE void | LL_ADC_SetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
Set ADC multimode delay between 2 sampling phases.
__STATIC_INLINE uint32_t | LL_ADC_GetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode delay between 2 sampling phases.
__STATIC_INLINE void | LL_ADC_REG_SetTrigSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
__STATIC_INLINE void | LL_ADC_INJ_SetTrigSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
__STATIC_INLINE void | LL_ADC_EnableDeepPowerDown (ADC_TypeDef *ADCx)
Put ADC instance in deep power down state.
__STATIC_INLINE void | LL_ADC_DisableDeepPowerDown (ADC_TypeDef *ADCx)
Disable ADC deep power down mode.
__STATIC_INLINE uint32_t | LL_ADC_IsDeepPowerDownEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance deep power down state.
__STATIC_INLINE void | LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
__STATIC_INLINE void | LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t | LL_ADC_IsInternalRegulatorEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t | LL_ADC_IsDisableOngoing (ADC_TypeDef *ADCx)
Get the selected ADC instance disable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.
__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular conversion state.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData10 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData8 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData6 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadMultiConversionData32 (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.
__STATIC_INLINE void | LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group injected conversion.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected conversion state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData10 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData8 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData6 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_ADRDY (ADC_TypeDef *ADCx)
Get flag ADC ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOC (ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_OVR (ADC_TypeDef *ADCx)
Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOSMP (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOC (ADC_TypeDef *ADCx)
Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JQOVF (ADC_TypeDef *ADCx)
Get flag ADC group injected contexts queue overflow.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD2 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD3 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
Clear flag ADC ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOC (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JQOVF (ADC_TypeDef *ADCx)
Clear flag ADC group injected contexts queue overflow.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_ADRDY (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_ADRDY (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOSMP (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOSMP (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOC (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JQOVF (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JQOVF (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 1 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode analog watchdog 1 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD2 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD2 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD3 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD3 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC slave.
__STATIC_INLINE void | LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
Enable ADC ready.
__STATIC_INLINE void | LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun.
__STATIC_INLINE void | LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOC (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JQOVF (ADC_TypeDef *ADCx)
Enable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
Disable interruption ADC ready.
__STATIC_INLINE void | LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JQOVF (ADC_TypeDef *ADCx)
Disable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_ADRDY (ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_OVR (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOSMP (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JQOVF (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD2 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD3 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).
ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

Header file of ADC LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_adc.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_bus.h File Reference

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Defines | Functions
stm32l4xx_ll_bus.h File Reference

Header file of BUS LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
#define | LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
#define | LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
#define | LL_AHB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
#define | LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
#define | LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
#define | LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
#define | LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
#define | LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
#define | LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
#define | LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
#define | LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
#define | LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
#define | LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
#define | LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
#define | LL_AHB3_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
#define | LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
#define | LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
#define | LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
#define | LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
#define | LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
#define | LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
#define | LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
#define | LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
#define | LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
#define | LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
#define | LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
#define | LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
#define | LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
#define | LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
#define | LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
#define | LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
#define | LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
#define | LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
#define | LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
#define | LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
#define | LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define | LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define | LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
#define | LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
#define | LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
Disable AHB2 peripherals clock.
__STATIC_INLINE void | LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
Force AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
Disable AHB3 peripherals clock.
__STATIC_INLINE void | LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
Force AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable AHB3 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable AHB3 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE uint32_t | LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClockStopSleep (uint32_t Periphs)
Enable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClockStopSleep (uint32_t Periphs)
Disable APB1 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
Enable APB2 peripheral clocks in Sleep and Stop modes.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
Disable APB2 peripheral clocks in Sleep and Stop modes.

Detailed Description

Header file of BUS LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_bus.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_comp.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_ll_comp.h File Reference

Header file of COMP LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...

Defines

#define | LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
#define | LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U)
#define | LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)
#define | LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U)
#define | LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)
#define | LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0)
#define | LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U)
#define | LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)
#define | LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 )
#define | LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_WINDOWMODE_ENABLE LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
#define | LL_COMP_INVERTINGINPUT_1_4VREFINT LL_COMP_INPUT_MINUS_1_4VREFINT
#define | LL_COMP_INVERTINGINPUT_1_2VREFINT LL_COMP_INPUT_MINUS_1_2VREFINT
#define | LL_COMP_INVERTINGINPUT_3_4VREFINT LL_COMP_INPUT_MINUS_3_4VREFINT
#define | LL_COMP_INVERTINGINPUT_VREFINT LL_COMP_INPUT_MINUS_VREFINT
#define | LL_COMP_INVERTINGINPUT_DAC1 LL_COMP_INPUT_MINUS_DAC1_CH1
#define | LL_COMP_INVERTINGINPUT_DAC2 LL_COMP_INPUT_MINUS_DAC1_CH2
#define | LL_COMP_INVERTINGINPUT_IO1 LL_COMP_INPUT_MINUS_IO1
#define | LL_COMP_INVERTINGINPUT_IO2 LL_COMP_INPUT_MINUS_IO2
#define | LL_COMP_NONINVERTINGINPUT_IO1 LL_COMP_INPUT_PLUS_IO1
#define | LL_COMP_NONINVERTINGINPUT_IO2 LL_COMP_INPUT_PLUS_IO2
#define | LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U)
#define | LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )
#define | LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)
#define | LL_COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000U)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 (COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 (COMP_CSR_BLANKING_1)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 (COMP_CSR_BLANKING_2)
#define | LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 (COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_1)
#define | LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5 (LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3 (LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)
#define | LL_COMP_BLANKINGSRC_TIM3_OC3 (LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)
#define | LL_COMP_BLANKINGSRC_TIM3_OC4 (LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2)
#define | LL_COMP_BLANKINGSRC_TIM8_OC5 (LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)
#define | LL_COMP_BLANKINGSRC_TIM15_OC1 (LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2)
#define | LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U)
#define | LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U)
#define | LL_COMP_DELAY_STARTUP_US ((uint32_t) 80U)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)
#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in COMP register.
#define | __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Functions

__STATIC_INLINE void | LL_COMP_SetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON)
Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE void | LL_COMP_SetPowerMode (COMP_TypeDef *COMPx, uint32_t PowerMode)
Set comparator instance operating mode to adjust power and speed.
__STATIC_INLINE uint32_t | LL_COMP_GetPowerMode (COMP_TypeDef *COMPx)
Get comparator instance operating mode to adjust power and speed.
__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.
__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_SetOutputBlankingSource (COMP_TypeDef *COMPx, uint32_t BlankingSource)
Set comparator instance blanking source.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputBlankingSource (COMP_TypeDef *COMPx)
Get comparator instance blanking source.
__STATIC_INLINE void | LL_COMP_SetInputNonInverting (COMP_TypeDef *COMPx, uint32_t InputNonInverting)
__STATIC_INLINE uint32_t | LL_COMP_GetInputNonInverting (COMP_TypeDef *COMPx)
__STATIC_INLINE void | LL_COMP_SetInputInverting (COMP_TypeDef *COMPx, uint32_t InputInverting)
__STATIC_INLINE uint32_t | LL_COMP_GetInputInverting (COMP_TypeDef *COMPx)
__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (COMP_TypeDef *COMPx)
Read comparator instance output level.
ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

Header file of COMP LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_comp.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_cortex.h File Reference

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Defines | Functions
stm32l4xx_ll_cortex.h File Reference

Header file of CORTEX LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
#define | LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk)
#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
#define | LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U)
#define | LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U)
#define | LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U)
#define | LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U)
#define | LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U)
#define | LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U)
#define | LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U)
#define | LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U)
#define | LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos))
#define | LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos))
#define | LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos))
#define | LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos))
#define | LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos))
#define | LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos))
#define | LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos))
#define | LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos))
#define | LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos))
#define | LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos))
#define | LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos))
#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U)
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk
#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U)
#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U)
#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U)

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)
__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetConstant (void)
Get Constant number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Detailed Description

Header file of CORTEX LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL CORTEX driver contains a set of generic APIs that can be
    used by user:
      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
          functions
      (+) Low power mode configuration (SCB register of Cortex-MCU)
      (+) MPU API to configure and enable regions
      (+) API to access to MCU info (CPUID register)
      (+) API to enable fault handler (SHCSR accesses)
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_cortex.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_crc.h File Reference

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stm32l4xx_ll_crc.h File Reference

Header file of CRC LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Defines

#define | LL_CRC_POLYLENGTH_32B (uint32_t)0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)
#define | LL_CRC_INDATA_REVERSE_NONE (uint32_t)0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)
#define | LL_CRC_OUTDATA_REVERSE_NONE (uint32_t)0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT
#define | LL_CRC_DEFAULT_CRC32_POLY (uint32_t)0x04C11DB7U
#define | LL_CRC_DEFAULT_CRC_INITVALUE (uint32_t)0xFFFFFFFFU
#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (CRC_TypeDef *CRCx)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (CRC_TypeDef *CRCx)
Return current Programmable polynomial value.
__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.
ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

Header file of CRC LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_crc.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_dac.h File Reference

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stm32l4xx_ll_dac.h File Reference

Header file of DAC LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_DAC_InitTypeDef
Structure definition of some features of DAC instance. More...

Defines

#define | DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
#define | DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
#define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
#define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define | DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
#define | DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
#define | DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
#define | DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
#define | DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
#define | DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
#define | DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U)
#define | DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define | DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
#define | DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
#define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define | DAC_REG_SHSR1_REGOFFSET ((uint32_t)0x00000000U) /* Register SHSRx channel 1 taken as reference */
#define | DAC_REG_SHSR2_REGOFFSET ((uint32_t)0x00001000U) /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */
#define | DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
#define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
#define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
#define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
#define | DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
#define | __DAC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define | __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define | LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)
#define | LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)
#define | LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define | LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)
#define | LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)
#define | LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
#define | LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)
#define | LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
#define | LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)
#define | LL_DAC_MODE_NORMAL_OPERATION ((uint32_t)0x00000000U)
#define | LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)
#define | LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 )
#define | LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U)
#define | LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 )
#define | LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0)
#define | LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
#define | LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U)
#define | LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0)
#define | LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)
#define | LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U)
#define | LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
#define | LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
#define | LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
#define | LL_DAC_OUTPUT_MODE_NORMAL ((uint32_t)0x00000000U)
#define | LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)
#define | LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U)
#define | LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)
#define | LL_DAC_OUTPUT_CONNECT_GPIO ((uint32_t)0x00000000U)
#define | LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)
#define | LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
#define | LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
#define | LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
#define | LL_DAC_TRIGGER_TIM5_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO)
#define | LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
#define | LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
#define | LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
#define | LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
#define | LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
#define | LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
#define | LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
#define | LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
#define | LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)
#define | LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define | LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U)
#define | LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK
#define | LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK
#define | LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK
#define | LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 8U)
#define | LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 2U)
#define | LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DAC register.
#define | LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DAC register.
#define | __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
Helper macro to get DAC channel number in decimal format from literals LL_DAC_CHANNEL_x.
#define | __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x from number in decimal format.
#define | __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
Helper macro to define the DAC conversion data full-scale digital value corresponding to the selected DAC resolution.
#define | __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)
Helper macro to calculate the DAC conversion data (unit: digital value) corresponding to a voltage (unit: mVolt).

Functions

__STATIC_INLINE void | LL_DAC_SetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
Set the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE uint32_t | LL_DAC_GetMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the operating mode for the selected DAC channel: calibration or normal operating mode.
__STATIC_INLINE void | LL_DAC_SetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
Set the offset trimming value for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTrimmingValue (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the offset trimming value for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
Set the conversion trigger source for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetTriggerSource (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the conversion trigger source for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
Set the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveAutoGeneration (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the waveform automatic generation mode for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE uint32_t | LL_DAC_GetWaveNoiseLFSR (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Set the noise waveform generation for the selected DAC channel: Noise mode and parameters LFSR (linear feedback shift register).
__STATIC_INLINE void | LL_DAC_SetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE uint32_t | LL_DAC_GetWaveTriangleAmplitude (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Set the triangle waveform generation for the selected DAC channel: triangle mode and amplitude.
__STATIC_INLINE void | LL_DAC_ConfigOutput (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
Set the output for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
Set the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output mode normal or sample-and-hold for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
Set the output buffer for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputBuffer (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output buffer state for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
Set the output connection for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_GetOutputConnection (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the output connection for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
Set the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldSampleTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: sample time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
Set the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldHoldTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: hold time.
__STATIC_INLINE void | LL_DAC_SetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
Set the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE uint32_t | LL_DAC_GetSampleAndHoldRefreshTime (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get the sample-and-hold timing for the selected DAC channel: refresh time.
__STATIC_INLINE void | LL_DAC_SetWaveMode (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveMode)
__STATIC_INLINE uint32_t | LL_DAC_GetWaveMode (DAC_TypeDef *DACx, uint32_t DAC_Channel)
__STATIC_INLINE void | LL_DAC_EnableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC DMA transfer request of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableDMAReq (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC DMA transfer request of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsDMAReqEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC DMA transfer request state of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_DMA_GetRegAddr (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
Function to help to configure DMA transfer to DAC: retrieve the DAC register address from DAC instance and a list of DAC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_DAC_Enable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC selected channel.
__STATIC_INLINE void | LL_DAC_Disable (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC enable state of the selected channel.
__STATIC_INLINE void | LL_DAC_EnableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Enable DAC trigger of the selected channel.
__STATIC_INLINE void | LL_DAC_DisableTrigger (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Disable DAC trigger of the selected channel.
__STATIC_INLINE uint32_t | LL_DAC_IsTriggerEnabled (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Get DAC trigger state of the selected channel.
__STATIC_INLINE void | LL_DAC_TrigSWConversion (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Trig DAC conversion by software for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData12LeftAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertData8RightAligned (DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for the selected DAC channel.
__STATIC_INLINE void | LL_DAC_ConvertDualData12RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData12LeftAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 12 bits left alignment (MSB aligned on bit 15), for both DAC channels.
__STATIC_INLINE void | LL_DAC_ConvertDualData8RightAligned (DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
Set the data to be loaded in the data holding register in format 8 bits left alignment (LSB aligned on bit 0), for both DAC channels.
__STATIC_INLINE uint32_t | LL_DAC_RetrieveOutputData (DAC_TypeDef *DACx, uint32_t DAC_Channel)
Retrieve output data currently generated for the selected DAC channel.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL1 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_CAL2 (DAC_TypeDef *DACx)
Get DAC calibration offset flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST1 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_BWST2 (DAC_TypeDef *DACx)
Get DAC busy writing sample time flag for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR1 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsActiveFlag_DMAUDR2 (DAC_TypeDef *DACx)
Get DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR1 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 1.
__STATIC_INLINE void | LL_DAC_ClearFlag_DMAUDR2 (DAC_TypeDef *DACx)
Clear DAC underrun flag for DAC channel 2.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR1 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_EnableIT_DMAUDR2 (DAC_TypeDef *DACx)
Enable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR1 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE void | LL_DAC_DisableIT_DMAUDR2 (DAC_TypeDef *DACx)
Disable DMA underrun interrupt for DAC channel 2.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR1 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 1.
__STATIC_INLINE uint32_t | LL_DAC_IsEnabledIT_DMAUDR2 (DAC_TypeDef *DACx)
Get DMA underrun interrupt for DAC channel 2.
ErrorStatus | LL_DAC_DeInit (DAC_TypeDef *DACx)
De-initialize registers of the selected DAC instance to their default reset values.
ErrorStatus | LL_DAC_Init (DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
Initialize some features of DAC instance.
void | LL_DAC_StructInit (LL_DAC_InitTypeDef *DAC_InitStruct)
Set each LL_DAC_InitTypeDef field to default value.

Detailed Description

Header file of DAC LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_dac.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_dma.h File Reference

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Data Structures | Defines | Functions | Variables
stm32l4xx_ll_dma.h File Reference

Header file of DMA LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_DMA_InitTypeDef

Defines

#define | DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
#define | DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
#define | LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
#define | LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
#define | LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7
#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_ISR_GIF7 DMA_ISR_GIF7
#define | LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
#define | LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
#define | LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7
#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE
#define | LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U)
#define | LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U)
#define | LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U)
#define | LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U)
#define | LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U)
#define | LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U)
#define | LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U)
#define | LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U)
#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
#define | LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U)
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC
#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U)
#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U)
#define | LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
#define | LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
#define | LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL
#define | LL_DMA_REQUEST_0 ((uint32_t)0x00000000U)
#define | LL_DMA_REQUEST_1 ((uint32_t)0x00000001U)
#define | LL_DMA_REQUEST_2 ((uint32_t)0x00000002U)
#define | LL_DMA_REQUEST_3 ((uint32_t)0x00000003U)
#define | LL_DMA_REQUEST_4 ((uint32_t)0x00000004U)
#define | LL_DMA_REQUEST_5 ((uint32_t)0x00000005U)
#define | LL_DMA_REQUEST_6 ((uint32_t)0x00000006U)
#define | LL_DMA_REQUEST_7 ((uint32_t)0x00000007U)
#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.
#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_DMA_SetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
Set DMA request for DMA instance on Channel x.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA request for DMA instance on Channel x.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI7 (DMA_TypeDef *DMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI7 (DMA_TypeDef *DMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Variables

static const uint8_t | CHANNEL_OFFSET_TAB []

Detailed Description

Header file of DMA LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_dma.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_exti.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_ll_exti.h File Reference

Header file of EXTI LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_EXTI_InitTypeDef

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR1_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR1_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR1_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR1_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR1_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR1_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR1_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR1_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR1_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR1_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR1_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR1_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR1_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR1_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR1_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR1_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR1_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR1_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR1_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR1_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR1_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR1_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR1_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR1_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR1_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR1_IM25
#define | LL_EXTI_LINE_26 EXTI_IMR1_IM26
#define | LL_EXTI_LINE_27 EXTI_IMR1_IM27
#define | LL_EXTI_LINE_28 EXTI_IMR1_IM28
#define | LL_EXTI_LINE_29 EXTI_IMR1_IM29
#define | LL_EXTI_LINE_30 EXTI_IMR1_IM30
#define | LL_EXTI_LINE_31 EXTI_IMR1_IM31
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM
#define | LL_EXTI_LINE_32 EXTI_IMR2_IM32
#define | LL_EXTI_LINE_33 EXTI_IMR2_IM33
#define | LL_EXTI_LINE_34 EXTI_IMR2_IM34
#define | LL_EXTI_LINE_35 EXTI_IMR2_IM35
#define | LL_EXTI_LINE_36 EXTI_IMR2_IM36
#define | LL_EXTI_LINE_37 EXTI_IMR2_IM37
#define | LL_EXTI_LINE_38 EXTI_IMR2_IM38
#define | LL_EXTI_LINE_39 EXTI_IMR2_IM39
#define | LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM
#define | LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE ((uint32_t)0x00000000U)
#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)
#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_32_63 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_32_63 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_32_63 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 32 to 63.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

Header file of EXTI LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_exti.h.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_gpio.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32l4xx_ll_gpio.h File Reference

Header file of GPIO LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS15
#define | LL_GPIO_PIN_ALL
#define | LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0
#define | LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0
#define | LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1
#define | LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0
#define | LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define | LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define | LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define | LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
#define | LL_GPIO_PULL_NO ((uint32_t)0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1
#define | LL_GPIO_AF_0 ((uint32_t)0x0000000U)
#define | LL_GPIO_AF_1 ((uint32_t)0x0000001U)
#define | LL_GPIO_AF_2 ((uint32_t)0x0000002U)
#define | LL_GPIO_AF_3 ((uint32_t)0x0000003U)
#define | LL_GPIO_AF_4 ((uint32_t)0x0000004U)
#define | LL_GPIO_AF_5 ((uint32_t)0x0000005U)
#define | LL_GPIO_AF_6 ((uint32_t)0x0000006U)
#define | LL_GPIO_AF_7 ((uint32_t)0x0000007U)
#define | LL_GPIO_AF_8 ((uint32_t)0x0000008U)
#define | LL_GPIO_AF_9 ((uint32_t)0x0000009U)
#define | LL_GPIO_AF_10 ((uint32_t)0x000000AU)
#define | LL_GPIO_AF_11 ((uint32_t)0x000000BU)
#define | LL_GPIO_AF_12 ((uint32_t)0x000000CU)
#define | LL_GPIO_AF_13 ((uint32_t)0x000000DU)
#define | LL_GPIO_AF_14 ((uint32_t)0x000000EU)
#define | LL_GPIO_AF_15 ((uint32_t)0x000000FU)
#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_EnablePinAnalogControl (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Connect analog switch to ADC input of several pins for a dedicated port.
__STATIC_INLINE void | LL_GPIO_DisablePinAnalogControl (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Disconnect analog switch to ADC input of several pins for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.
__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.
ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

Header file of GPIO LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_gpio.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_i2c.h File Reference

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stm32l4xx_ll_i2c.h File Reference

Header file of I2C LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_I2C_InitTypeDef

Defines

#define | I2C_POSITION_CR1_DNF (uint32_t)POSITION_VAL(I2C_CR1_DNF)
#define | I2C_POSITION_CR2_NBYTES (uint32_t)POSITION_VAL(I2C_CR2_NBYTES)
#define | I2C_POSITION_TIMINGR_PRESC (uint32_t)POSITION_VAL(I2C_TIMINGR_PRESC)
#define | I2C_POSITION_TIMINGR_SCLDEL (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLDEL)
#define | I2C_POSITION_TIMINGR_SDADEL (uint32_t)POSITION_VAL(I2C_TIMINGR_SDADEL)
#define | I2C_POSITION_TIMINGR_SCLH (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLH)
#define | I2C_POSITION_TIMINGR_SCLL (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLL)
#define | I2C_POSITION_ISR_ADDCODE (uint32_t)POSITION_VAL(I2C_ISR_ADDCODE)
#define | I2C_POSITION_TIMEOUTR_TIMEOUTB (uint32_t)POSITION_VAL(I2C_TIMEOUTR_TIMEOUTB)
#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF
#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY
#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE
#define | LL_I2C_MODE_I2C ((uint32_t)0x00000000U)
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U)
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN
#define | LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U)
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10
#define | LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U)
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE
#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07
#define | LL_I2C_ACK ((uint32_t) 0x00000000U)
#define | LL_I2C_NACK I2C_CR2_NACK
#define | LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U)
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10
#define | LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U)
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN
#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U)
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
#define | LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U)
#define | LL_I2C_GENERATE_STOP I2C_CR2_STOP
#define | LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE I2C_CR2_START
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START
#define | LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START
#define | LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U)
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR
#define | LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U)
#define | LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U)
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U)
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE
#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)
#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.
#define | __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (I2C_TypeDef *I2Cx)
Get the SMBus Extented Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts is enabled of disabled.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.
__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .
uint32_t | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
uint32_t | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

Header file of I2C LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_i2c.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_iwdg.h File Reference

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Defines | Functions
stm32l4xx_ll_iwdg.h File Reference

Header file of IWDG LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Defines

#define | LL_IWDG_KEY_RELOAD ((uint32_t)0x0000AAAAU)
#define | LL_IWDG_KEY_ENABLE ((uint32_t)0x0000CCCCU)
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE ((uint32_t)0x00005555U)
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE ((uint32_t)0x00000000U)
#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU
#define | LL_IWDG_PRESCALER_4 ((uint32_t)0x00000000U)
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Detailed Description

Header file of IWDG LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_iwdg.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_lptim.h File Reference

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  • STM32L4xx_HAL_Driver
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stm32l4xx_ll_lptim.h File Reference

Header file of LPTIM LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_LPTIM_InitTypeDef
LPTIM Init structure definition. More...

Defines

#define | LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM
#define | LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM
#define | LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK
#define | LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK
#define | LL_LPTIM_ISR_UP LPTIM_ISR_UP
#define | LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN
#define | LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE
#define | LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE
#define | LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE
#define | LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE
#define | LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE
#define | LL_LPTIM_IER_UPIE LPTIM_IER_UPIE
#define | LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE
#define | LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT
#define | LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT
#define | LL_LPTIM_UPDATE_MODE_IMMEDIATE ((uint32_t)0x00000000U)
#define | LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LL_LPTIM_COUNTER_MODE_INTERNAL ((uint32_t)0x00000000U)
#define | LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LL_LPTIM_OUTPUT_WAVEFORM_PWM ((uint32_t)0x00000000U)
#define | LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE
#define | LL_LPTIM_OUTPUT_POLARITY_REGULAR ((uint32_t) 0x00000000U)
#define | LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL
#define | LL_LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
#define | LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)
#define | LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
#define | LL_LPTIM_TRIG_SOURCE_GPIO ((uint32_t)0x00000000U)
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)
#define | LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL
#define | LL_LPTIM_TRIG_FILTER_NONE ((uint32_t)0x00000000U)
#define | LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0
#define | LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1
#define | LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT
#define | LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0
#define | LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1
#define | LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LL_LPTIM_CLK_SOURCE_INTERNAL ((uint32_t)0x00000000U)
#define | LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL
#define | LL_LPTIM_CLK_FILTER_NONE ((uint32_t)0x00000000U)
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT
#define | LL_LPTIM_CLK_POLARITY_RISING ((uint32_t)0x00000000U)
#define | LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LL_LPTIM_ENCODER_MODE_RISING ((uint32_t)0x00000000U)
#define | LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LL_LPTIM_INPUT1_SRC_GPIO ((uint32_t)0x00000000U)
#define | LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0
#define | LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1
#define | LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR
#define | LL_LPTIM_INPUT2_SRC_GPIO ((uint32_t)0x00000000U)
#define | LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1
#define | LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPTIM register.
#define | LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPTIM register.

Functions

__STATIC_INLINE void | LL_LPTIM_Enable (LPTIM_TypeDef *LPTIMx)
Enable the LPTIM instance.
__STATIC_INLINE void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabled (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM instance is enabled.
__STATIC_INLINE void | LL_LPTIM_StartCounter (LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
Starts the LPTIM counter in the desired mode.
__STATIC_INLINE void | LL_LPTIM_SetUpdateMode (LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
Set the LPTIM registers update mode (enable/disable register preload)
__STATIC_INLINE uint32_t | LL_LPTIM_GetUpdateMode (LPTIM_TypeDef *LPTIMx)
Get the LPTIM registers update mode.
__STATIC_INLINE void | LL_LPTIM_SetAutoReload (LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
Set the auto reload value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetAutoReload (LPTIM_TypeDef *LPTIMx)
Get actual auto reload value.
__STATIC_INLINE void | LL_LPTIM_SetCompare (LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
Set the compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCompare (LPTIM_TypeDef *LPTIMx)
Get actual compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounter (LPTIM_TypeDef *LPTIMx)
Get actual counter value.
__STATIC_INLINE void | LL_LPTIM_SetCounterMode (LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
Set the counter mode (selection of the LPTIM counter clock source).
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounterMode (LPTIM_TypeDef *LPTIMx)
Get the counter mode.
__STATIC_INLINE void | LL_LPTIM_ConfigOutput (LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
Configure the LPTIM instance output (LPTIMx_OUT)
__STATIC_INLINE void | LL_LPTIM_SetWaveform (LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
Set waveform shape.
__STATIC_INLINE uint32_t | LL_LPTIM_GetWaveform (LPTIM_TypeDef *LPTIMx)
Get actual waveform shape.
__STATIC_INLINE void | LL_LPTIM_SetPolarity (LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
Set output polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPolarity (LPTIM_TypeDef *LPTIMx)
Get actual output polarity.
__STATIC_INLINE void | LL_LPTIM_SetPrescaler (LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
Set actual prescaler division ratio.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPrescaler (LPTIM_TypeDef *LPTIMx)
Get actual prescaler division ratio.
__STATIC_INLINE void | LL_LPTIM_SetInput1Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 1 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_SetInput2Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 2 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_EnableTimeout (LPTIM_TypeDef *LPTIMx)
Enable the timeout function.
__STATIC_INLINE void | LL_LPTIM_DisableTimeout (LPTIM_TypeDef *LPTIMx)
Disable the timeout function.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledTimeout (LPTIM_TypeDef *LPTIMx)
Indicate whether the timeout function is enabled.
__STATIC_INLINE void | LL_LPTIM_TrigSw (LPTIM_TypeDef *LPTIMx)
Start the LPTIM counter.
__STATIC_INLINE void | LL_LPTIM_ConfigTrigger (LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
Configure the external trigger used as a trigger event for the LPTIM.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerSource (LPTIM_TypeDef *LPTIMx)
Get actual external trigger source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerFilter (LPTIM_TypeDef *LPTIMx)
Get actual external trigger filter.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerPolarity (LPTIM_TypeDef *LPTIMx)
Get actual external trigger polarity.
__STATIC_INLINE void | LL_LPTIM_SetClockSource (LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
Set the source of the clock used by the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockSource (LPTIM_TypeDef *LPTIMx)
Get actual LPTIM instance clock source.
__STATIC_INLINE void | LL_LPTIM_ConfigClock (LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockPolarity (LPTIM_TypeDef *LPTIMx)
Get actual clock polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockFilter (LPTIM_TypeDef *LPTIMx)
Get actual clock digital filter.
__STATIC_INLINE void | LL_LPTIM_SetEncoderMode (LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
Configure the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_GetEncoderMode (LPTIM_TypeDef *LPTIMx)
Get actual encoder mode.
__STATIC_INLINE void | LL_LPTIM_EnableEncoderMode (LPTIM_TypeDef *LPTIMx)
Enable the encoder mode.
__STATIC_INLINE void | LL_LPTIM_DisableEncoderMode (LPTIM_TypeDef *LPTIMx)
Disable the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledEncoderMode (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM operates in encoder mode.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_CMPM (LPTIM_TypeDef *LPTIMx)
Clear the compare match flag (CMPMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPM (LPTIM_TypeDef *LPTIMx)
Inform application whether a compare match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_ARRM (LPTIM_TypeDef *LPTIMx)
Clear the autoreload match flag (ARRMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARRM (LPTIM_TypeDef *LPTIMx)
Inform application whether a autoreload match interrupt has occured.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Clear the external trigger valid edge flag(EXTTRIGCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Inform application whether a valid edge on the selected external trigger input has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_UP (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to up interrupt flag (UPCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_UP (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_ClearFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to down interrupt flag (DOWNCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Enable compare match interrupt (CMPMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Disable compare match interrupt (CMPMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPM (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare match interrupt (CMPMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Enable autoreload match interrupt (ARRMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Disable autoreload match interrupt (ARRMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARRM (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Enable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Disable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Enable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Disable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Enable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Disable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARROK (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_UP (LPTIM_TypeDef *LPTIMx)
Enable direction change to up interrupt (UPIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_UP (LPTIM_TypeDef *LPTIMx)
Disable direction change to up interrupt (UPIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_UP (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to up interrupt (UPIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Enable direction change to down interrupt (DOWNIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Disable direction change to down interrupt (DOWNIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_DOWN (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.

Detailed Description

Header file of LPTIM LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_lptim.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_lpuart.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_ll_lpuart.h File Reference

Header file of LPUART LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_LPUART_InitTypeDef
LL LPUART Init Structure definition. More...

Defines

#define | LPUART_POSITION_CR1_DEDT (uint32_t)POSITION_VAL(USART_CR1_DEDT)
#define | LPUART_POSITION_CR1_DEAT (uint32_t)POSITION_VAL(USART_CR1_DEAT)
#define | LPUART_POSITION_CR2_ADD (uint32_t)POSITION_VAL(USART_CR2_ADD)
#define | LPUART_LPUARTDIV_FREQ_MUL (uint32_t)(256U)
#define | LPUART_BRR_MASK (uint32_t)(0x000FFFFFU)
#define | LPUART_BRR_MIN_VALUE (uint32_t)(0x00000300U)
#define | LL_LPUART_ICR_PECF USART_ICR_PECF
#define | LL_LPUART_ICR_FECF USART_ICR_FECF
#define | LL_LPUART_ICR_NCF USART_ICR_NCF
#define | LL_LPUART_ICR_ORECF USART_ICR_ORECF
#define | LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_LPUART_ICR_TCCF USART_ICR_TCCF
#define | LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_LPUART_ICR_CMCF USART_ICR_CMCF
#define | LL_LPUART_ICR_WUCF USART_ICR_WUCF
#define | LL_LPUART_ISR_PE USART_ISR_PE
#define | LL_LPUART_ISR_FE USART_ISR_FE
#define | LL_LPUART_ISR_NE USART_ISR_NE
#define | LL_LPUART_ISR_ORE USART_ISR_ORE
#define | LL_LPUART_ISR_IDLE USART_ISR_IDLE
#define | LL_LPUART_ISR_RXNE USART_ISR_RXNE
#define | LL_LPUART_ISR_TC USART_ISR_TC
#define | LL_LPUART_ISR_TXE USART_ISR_TXE
#define | LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_LPUART_ISR_CTS USART_ISR_CTS
#define | LL_LPUART_ISR_BUSY USART_ISR_BUSY
#define | LL_LPUART_ISR_CMF USART_ISR_CMF
#define | LL_LPUART_ISR_SBKF USART_ISR_SBKF
#define | LL_LPUART_ISR_RWU USART_ISR_RWU
#define | LL_LPUART_ISR_WUF USART_ISR_WUF
#define | LL_LPUART_ISR_TEACK USART_ISR_TEACK
#define | LL_LPUART_ISR_REACK USART_ISR_REACK
#define | LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE
#define | LL_LPUART_CR1_TCIE USART_CR1_TCIE
#define | LL_LPUART_CR1_TXEIE USART_CR1_TXEIE
#define | LL_LPUART_CR1_PEIE USART_CR1_PEIE
#define | LL_LPUART_CR1_CMIE USART_CR1_CMIE
#define | LL_LPUART_CR3_EIE USART_CR3_EIE
#define | LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_LPUART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_LPUART_DIRECTION_NONE (uint32_t)0x00000000U
#define | LL_LPUART_DIRECTION_RX USART_CR1_RE
#define | LL_LPUART_DIRECTION_TX USART_CR1_TE
#define | LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_LPUART_PARITY_NONE (uint32_t)0x00000000U
#define | LL_LPUART_PARITY_EVEN USART_CR1_PCE
#define | LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_LPUART_WAKEUP_IDLELINE (uint32_t)0x00000000U
#define | LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_LPUART_DATAWIDTH_7B USART_CR1_M1
#define | LL_LPUART_DATAWIDTH_8B (uint32_t)0x00000000U
#define | LL_LPUART_DATAWIDTH_9B USART_CR1_M0
#define | LL_LPUART_STOPBITS_1 (uint32_t)0x00000000U
#define | LL_LPUART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_LPUART_TXRX_STANDARD (uint32_t)0x00000000U
#define | LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_LPUART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U
#define | LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_LPUART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U
#define | LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_LPUART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U
#define | LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_LPUART_BITORDER_LSBFIRST (uint32_t)0x00000000U
#define | LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_LPUART_ADDRESS_DETECT_4B (uint32_t)0x00000000U
#define | LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_LPUART_HWCONTROL_NONE (uint32_t)0x00000000U
#define | LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_LPUART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U
#define | LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_LPUART_DE_POLARITY_HIGH (uint32_t)0x00000000U
#define | LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_LPUART_DMA_REG_DATA_TRANSMIT (uint32_t)0U
#define | LL_LPUART_DMA_REG_DATA_RECEIVE (uint32_t)1U
#define | LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPUART register.
#define | LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPUART register.
#define | __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Functions

__STATIC_INLINE void | LL_LPUART_Enable (USART_TypeDef *LPUARTx)
LPUART Enable.
__STATIC_INLINE void | LL_LPUART_Disable (USART_TypeDef *LPUARTx)
LPUART Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabled (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled.
__STATIC_INLINE void | LL_LPUART_EnableInStopMode (USART_TypeDef *LPUARTx)
LPUART enabled in STOP Mode.
__STATIC_INLINE void | LL_LPUART_DisableInStopMode (USART_TypeDef *LPUARTx)
LPUART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledInStopMode (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_LPUART_EnableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_LPUART_DisableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Disable.
__STATIC_INLINE void | LL_LPUART_EnableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_LPUART_DisableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_LPUART_SetTransferDirection (USART_TypeDef *LPUARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferDirection (USART_TypeDef *LPUARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_LPUART_SetParity (USART_TypeDef *LPUARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled)
__STATIC_INLINE uint32_t | LL_LPUART_GetParity (USART_TypeDef *LPUARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_LPUART_SetWakeUpMethod (USART_TypeDef *LPUARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_LPUART_GetWakeUpMethod (USART_TypeDef *LPUARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_LPUART_SetDataWidth (USART_TypeDef *LPUARTx, uint32_t DataWidth)
Set Word length (nb of data bits, excluding start and stop bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetDataWidth (USART_TypeDef *LPUARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_LPUART_EnableMuteMode (USART_TypeDef *LPUARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_LPUART_DisableMuteMode (USART_TypeDef *LPUARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledMuteMode (USART_TypeDef *LPUARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_LPUART_SetStopBitsLength (USART_TypeDef *LPUARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_LPUART_GetStopBitsLength (USART_TypeDef *LPUARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_LPUART_ConfigCharacter (USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_LPUART_SetTXRXSwap (USART_TypeDef *LPUARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXRXSwap (USART_TypeDef *LPUARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_LPUART_SetRXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXPinLevel (USART_TypeDef *LPUARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetTXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXPinLevel (USART_TypeDef *LPUARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetBinaryDataLogic (USART_TypeDef *LPUARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetBinaryDataLogic (USART_TypeDef *LPUARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_LPUART_SetTransferBitOrder (USART_TypeDef *LPUARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferBitOrder (USART_TypeDef *LPUARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_LPUART_ConfigNodeAddress (USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the LPUART node.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddress (USART_TypeDef *LPUARTx)
Return 8 bit Address of the LPUART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddressLen (USART_TypeDef *LPUARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_LPUART_EnableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_EnableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_SetHWFlowCtrl (USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_LPUART_GetHWFlowCtrl (USART_TypeDef *LPUARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_LPUART_EnableOverrunDetect (USART_TypeDef *LPUARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_LPUART_DisableOverrunDetect (USART_TypeDef *LPUARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledOverrunDetect (USART_TypeDef *LPUARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_LPUART_SetWKUPType (USART_TypeDef *LPUARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetWKUPType (USART_TypeDef *LPUARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_LPUART_SetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
Configure LPUART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_LPUART_GetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk)
Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.
__STATIC_INLINE void | LL_LPUART_EnableHalfDuplex (USART_TypeDef *LPUARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_LPUART_DisableHalfDuplex (USART_TypeDef *LPUARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledHalfDuplex (USART_TypeDef *LPUARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDEDeassertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEDeassertionTime (USART_TypeDef *LPUARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_LPUART_SetDEAssertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEAssertionTime (USART_TypeDef *LPUARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_LPUART_EnableDEMode (USART_TypeDef *LPUARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_LPUART_DisableDEMode (USART_TypeDef *LPUARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDEMode (USART_TypeDef *LPUARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDESignalPolarity (USART_TypeDef *LPUARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_GetDESignalPolarity (USART_TypeDef *LPUARTx)
Return Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_FE (USART_TypeDef *LPUARTx)
Check if the LPUART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_NE (USART_TypeDef *LPUARTx)
Check if the LPUART Noise detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_ORE (USART_TypeDef *LPUARTx)
Check if the LPUART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXNE (USART_TypeDef *LPUARTx)
Check if the LPUART Read Data Register Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXE (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Data Register Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_nCTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_BUSY (USART_TypeDef *LPUARTx)
Check if the LPUART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_SBK (USART_TypeDef *LPUARTx)
Check if the LPUART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RWU (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TEACK (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_REACK (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE void | LL_LPUART_ClearFlag_PE (USART_TypeDef *LPUARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_FE (USART_TypeDef *LPUARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_NE (USART_TypeDef *LPUARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_ORE (USART_TypeDef *LPUARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_IDLE (USART_TypeDef *LPUARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TC (USART_TypeDef *LPUARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_nCTS (USART_TypeDef *LPUARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_CM (USART_TypeDef *LPUARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_WKUP (USART_TypeDef *LPUARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_LPUART_EnableIT_IDLE (USART_TypeDef *LPUARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXNE (USART_TypeDef *LPUARTx)
Enable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TC (USART_TypeDef *LPUARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXE (USART_TypeDef *LPUARTx)
Enable TX Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_PE (USART_TypeDef *LPUARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CM (USART_TypeDef *LPUARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_ERROR (USART_TypeDef *LPUARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CTS (USART_TypeDef *LPUARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_WKUP (USART_TypeDef *LPUARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_IDLE (USART_TypeDef *LPUARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXNE (USART_TypeDef *LPUARTx)
Disable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TC (USART_TypeDef *LPUARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXE (USART_TypeDef *LPUARTx)
Disable TX Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_PE (USART_TypeDef *LPUARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CM (USART_TypeDef *LPUARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_ERROR (USART_TypeDef *LPUARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CTS (USART_TypeDef *LPUARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_WKUP (USART_TypeDef *LPUARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXNE (USART_TypeDef *LPUARTx)
Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXE (USART_TypeDef *LPUARTx)
Check if the LPUART TX Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_ERROR (USART_TypeDef *LPUARTx)
Check if the LPUART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_RX (USART_TypeDef *LPUARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_RX (USART_TypeDef *LPUARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_RX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_TX (USART_TypeDef *LPUARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_TX (USART_TypeDef *LPUARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_TX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_LPUART_EnableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_LPUART_DisableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_LPUART_DMA_GetRegAddr (USART_TypeDef *LPUARTx, uint32_t Direction)
Get the LPUART data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_LPUART_ReceiveData8 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_LPUART_ReceiveData9 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData8 (USART_TypeDef *LPUARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData9 (USART_TypeDef *LPUARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_RequestBreakSending (USART_TypeDef *LPUARTx)
Request Break sending.
__STATIC_INLINE void | LL_LPUART_RequestEnterMuteMode (USART_TypeDef *LPUARTx)
Put LPUART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_LPUART_RequestRxDataFlush (USART_TypeDef *LPUARTx)
Request a Receive Data flush.
ErrorStatus | LL_LPUART_DeInit (USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Detailed Description

Header file of LPUART LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_lpuart.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_opamp.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_ll_opamp.h File Reference

Header file of OPAMP LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_OPAMP_InitTypeDef
Structure definition of some features of OPAMP instance. More...

Defines

#define | OPAMP_POWERMODE_OTR_REGOFFSET ((uint32_t)0x00000000U)
#define | OPAMP_POWERMODE_LPOTR_REGOFFSET ((uint32_t)0x00000001U)
#define | OPAMP_POWERMODE_OTR_REGOFFSET_MASK (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET)
#define | OPAMP_POWERMODE_CSR_BIT_MASK (OPAMP_CSR_OPALPM)
#define | OPAMP_TRIMMING_SELECT_MASK (OPAMP1_CSR_CALSEL)
#define | OPAMP_TRIMMING_VALUE_MASK (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)
#define | __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_OPAMP_POWERSUPPLY_RANGE_LOW ((uint32_t)0x00000000U)
#define | LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP1_CSR_OPARANGE)
#define | LL_OPAMP_POWERMODE_NORMAL (OPAMP_POWERMODE_OTR_REGOFFSET)
#define | LL_OPAMP_POWERMODE_LOWPOWER (OPAMP_POWERMODE_LPOTR_REGOFFSET | OPAMP_CSR_OPALPM)
#define | LL_OPAMP_MODE_FUNCTIONAL ((uint32_t)0x00000000U)
#define | LL_OPAMP_MODE_CALIBRATION (OPAMP1_CSR_CALON)
#define | LL_OPAMP_MODE_STANDALONE ((uint32_t)0x00000000U)
#define | LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_OPAMODE_1 | OPAMP_CSR_OPAMODE_0)
#define | LL_OPAMP_MODE_PGA (OPAMP_CSR_OPAMODE_1)
#define | LL_OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000U)
#define | LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGGAIN_0)
#define | LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGGAIN_1)
#define | LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 )
#define | LL_OPAMP_INPUT_NONINVERT_IO0 ((uint32_t)0x00000000U)
#define | LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 (OPAMP1_CSR_VPSEL)
#define | LL_OPAMP_INPUT_INVERT_IO0 ((uint32_t)0x00000000U)
#define | LL_OPAMP_INPUT_INVERT_IO1 (OPAMP1_CSR_VMSEL_0)
#define | LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP1_CSR_VMSEL_1)
#define | LL_OPAMP_NONINVERTINGINPUT_IO0 LL_OPAMP_INPUT_NONINVERT_IO0
#define | LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINVERT_DAC1_CH1
#define | LL_OPAMP_INVERTINGINPUT_IO0 LL_OPAMP_INPUT_INVERT_IO0
#define | LL_OPAMP_INVERTINGINPUT_IO1 LL_OPAMP_INPUT_INVERT_IO1
#define | LL_OPAMP_INVERTINGINPUT_CONNECT_NO LL_OPAMP_INPUT_INVERT_CONNECT_NO
#define | LL_OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000U)
#define | LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM)
#define | LL_OPAMP_TRIMMING_NMOS (OPAMP_OTR_TRIMOFFSETN)
#define | LL_OPAMP_TRIMMING_PMOS (OPAMP_OTR_TRIMOFFSETP | OPAMP1_CSR_CALSEL)
#define | LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in OPAMP register.
#define | LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in OPAMP register.
#define | __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__) (OPAMP12_COMMON)
Helper macro to select the OPAMP common instance to which is belonging the selected OPAMP instance.
#define | __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()
Helper macro to check if all OPAMP instances sharing the same OPAMP common instance are disabled.

Functions

__STATIC_INLINE void | LL_OPAMP_SetCommonPowerRange (OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange)
Set OPAMP power range.
__STATIC_INLINE uint32_t | LL_OPAMP_GetCommonPowerRange (OPAMP_Common_TypeDef *OPAMPxy_COMMON)
Get OPAMP power range.
__STATIC_INLINE void | LL_OPAMP_SetPowerMode (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
Set OPAMP power mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPowerMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP power mode.
__STATIC_INLINE void | LL_OPAMP_SetMode (OPAMP_TypeDef *OPAMPx, uint32_t Mode)
Set OPAMP mode calibration or functional.
__STATIC_INLINE uint32_t | LL_OPAMP_GetMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP mode calibration or functional.
__STATIC_INLINE void | LL_OPAMP_SetFunctionalMode (OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
Set OPAMP functional mode by setting internal connections.
__STATIC_INLINE uint32_t | LL_OPAMP_GetFunctionalMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP functional mode from setting of internal connections.
__STATIC_INLINE void | LL_OPAMP_SetPGAGain (OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
Set OPAMP PGA gain.
__STATIC_INLINE uint32_t | LL_OPAMP_GetPGAGain (OPAMP_TypeDef *OPAMPx)
Get OPAMP PGA gain.
__STATIC_INLINE void | LL_OPAMP_SetInputNonInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
Set OPAMP non-inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputNonInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP non-inverting input connection.
__STATIC_INLINE void | LL_OPAMP_SetInputInverting (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
Set OPAMP inverting input connection.
__STATIC_INLINE uint32_t | LL_OPAMP_GetInputInverting (OPAMP_TypeDef *OPAMPx)
Get OPAMP inverting input connection.
__STATIC_INLINE void | LL_OPAMP_SetNonInvertingInput (OPAMP_TypeDef *OPAMPx, uint32_t NonInvertingInput)
__STATIC_INLINE void | LL_OPAMP_SetInvertingInput (OPAMP_TypeDef *OPAMPx, uint32_t InvertingInput)
__STATIC_INLINE void | LL_OPAMP_SetTrimmingMode (OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
Set OPAMP trimming mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingMode (OPAMP_TypeDef *OPAMPx)
Get OPAMP trimming mode.
__STATIC_INLINE void | LL_OPAMP_SetCalibrationSelection (OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
Set OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_GetCalibrationSelection (OPAMP_TypeDef *OPAMPx)
Get OPAMP offset to calibrate the selected transistors differential pair NMOS or PMOS.
__STATIC_INLINE uint32_t | LL_OPAMP_IsCalibrationOutputSet (OPAMP_TypeDef *OPAMPx)
Get OPAMP calibration result of toggling output.
__STATIC_INLINE void | LL_OPAMP_SetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
Set OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.
__STATIC_INLINE uint32_t | LL_OPAMP_GetTrimmingValue (OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
Get OPAMP trimming factor for the selected transistors differential pair NMOS or PMOS, corresponding to the selected power mode.
__STATIC_INLINE void | LL_OPAMP_Enable (OPAMP_TypeDef *OPAMPx)
Enable OPAMP instance.
__STATIC_INLINE void | LL_OPAMP_Disable (OPAMP_TypeDef *OPAMPx)
Disable OPAMP instance.
__STATIC_INLINE uint32_t | LL_OPAMP_IsEnabled (OPAMP_TypeDef *OPAMPx)
Get OPAMP instance enable state (0: OPAMP is disabled, 1: OPAMP is enabled)
ErrorStatus | LL_OPAMP_DeInit (OPAMP_TypeDef *OPAMPx)
De-initialize registers of the selected OPAMP instance to their default reset values.
ErrorStatus | LL_OPAMP_Init (OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Initialize some features of OPAMP instance.
void | LL_OPAMP_StructInit (LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
Set each LL_OPAMP_InitTypeDef field to default value.

Detailed Description

Header file of OPAMP LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_opamp.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_pwr.h File Reference

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Defines | Functions
stm32l4xx_ll_pwr.h File Reference

Header file of PWR LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Defines

#define | LL_PWR_SCR_CSBF PWR_SCR_CSBF
#define | LL_PWR_SCR_CWUF PWR_SCR_CWUF
#define | LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
#define | LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
#define | LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
#define | LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
#define | LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
#define | LL_PWR_SR1_WUFI PWR_SR1_WUFI
#define | LL_PWR_SR1_SBF PWR_SR1_SBF
#define | LL_PWR_SR1_WUF5 PWR_SR1_WUF5
#define | LL_PWR_SR1_WUF4 PWR_SR1_WUF4
#define | LL_PWR_SR1_WUF3 PWR_SR1_WUF3
#define | LL_PWR_SR1_WUF2 PWR_SR1_WUF2
#define | LL_PWR_SR1_WUF1 PWR_SR1_WUF1
#define | LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
#define | LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
#define | LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
#define | LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
#define | LL_PWR_SR2_PVDO PWR_SR2_PVDO
#define | LL_PWR_SR2_VOSF PWR_SR2_VOSF
#define | LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
#define | LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
#define | LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
#define | LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
#define | LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
#define | LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
#define | LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2)
#define | LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
#define | LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
#define | LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */
#define | LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */
#define | LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
#define | LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */
#define | LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
#define | LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
#define | LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
#define | LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
#define | LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
#define | LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
#define | LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
#define | LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
#define | LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
#define | LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
#define | LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
#define | LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
#define | LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
#define | LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
#define | LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
#define | LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
#define | LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
#define | LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
#define | LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
#define | LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
#define | LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
#define | LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
#define | LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
#define | LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
#define | LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
#define | LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
#define | LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
#define | LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
#define | LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
#define | LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
#define | LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
#define | LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
#define | LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
#define | LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
#define | LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
#define | LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
#define | LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
#define | LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
#define | LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)
#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Functions

__STATIC_INLINE void | LL_PWR_EnableLowPowerRunMode (void)
Switch the regulator from main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_DisableLowPowerRunMode (void)
Switch the regulator from low-power mode to main mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledLowPowerRunMode (void)
Check if the regulator is in low-power mode.
__STATIC_INLINE void | LL_PWR_EnterLowPowerRunMode (void)
Switch from run main mode to run low-power mode.
__STATIC_INLINE void | LL_PWR_ExitLowPowerRunMode (void)
Switch from run main mode to low-power mode.
__STATIC_INLINE void | LL_PWR_SetRegulVoltageScaling (uint32_t VoltageScaling)
Set the main internal regulator output voltage.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulVoltageScaling (void)
Get the main internal regulator output voltage.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t LowPowerMode)
Set Low-Power mode.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Low-Power mode.
__STATIC_INLINE void | LL_PWR_EnableVddUSB (void)
Enable VDDUSB supply.
__STATIC_INLINE void | LL_PWR_DisableVddUSB (void)
Disable VDDUSB supply.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledVddUSB (void)
Check if VDDUSB supply is enabled.
__STATIC_INLINE void | LL_PWR_EnableVddIO2 (void)
Enable VDDIO2 supply.
__STATIC_INLINE void | LL_PWR_DisableVddIO2 (void)
Disable VDDIO2 supply.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledVddIO2 (void)
Check if VDDIO2 supply is enabled.
__STATIC_INLINE void | LL_PWR_EnablePVM (uint32_t PeriphVoltage)
Enable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE void | LL_PWR_DisablePVM (uint32_t PeriphVoltage)
Disable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVM (uint32_t PeriphVoltage)
Check if Power Voltage Monitoring is enabled on a peripheral.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableInternWU (void)
Enable Internal Wake-up line.
__STATIC_INLINE void | LL_PWR_DisableInternWU (void)
Disable Internal Wake-up line.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledInternWU (void)
Check if Internal Wake-up line is enabled.
__STATIC_INLINE void | LL_PWR_EnablePUPDCfg (void)
Enable pull-up and pull-down configuration.
__STATIC_INLINE void | LL_PWR_DisablePUPDCfg (void)
Disable pull-up and pull-down configuration.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPUPDCfg (void)
Check if pull-up and pull-down configuration is enabled.
__STATIC_INLINE void | LL_PWR_EnableSRAM2Retention (void)
Enable SRAM2 content retention in Standby mode.
__STATIC_INLINE void | LL_PWR_DisableSRAM2Retention (void)
Disable SRAM2 content retention in Standby mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSRAM2Retention (void)
Check if SRAM2 content retention in Standby mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_PWR_SetBattChargResistor (uint32_t Resistor)
Set the resistor impedance.
__STATIC_INLINE uint32_t | LL_PWR_GetBattChargResistor (void)
Get the resistor impedance.
__STATIC_INLINE void | LL_PWR_EnableBatteryCharging (void)
Enable battery charging.
__STATIC_INLINE void | LL_PWR_DisableBatteryCharging (void)
Disable battery charging.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBatteryCharging (void)
Check if battery charging is enabled.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityLow (uint32_t WakeUpPin)
Set the Wake-Up pin polarity low for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityHigh (uint32_t WakeUpPin)
Set the Wake-Up pin polarity high for the event detection.
__STATIC_INLINE uint32_t | LL_PWR_IsWakeUpPinPolarityLow (uint32_t WakeUpPin)
Get the Wake-Up pin polarity for the event detection.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-up state is enabled.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-down state is enabled.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_InternWU (void)
Get Internal Wake-up line Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SB (void)
Get Stand-By Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU5 (void)
Get Wake-up Flag 5.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU4 (void)
Get Wake-up Flag 4.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU3 (void)
Get Wake-up Flag 3.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU2 (void)
Get Wake-up Flag 2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU1 (void)
Get Wake-up Flag 1.
__STATIC_INLINE void | LL_PWR_ClearFlag_SB (void)
Clear Stand-By Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU5 (void)
Clear Wake-up Flag 5.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU4 (void)
Clear Wake-up Flag 4.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU3 (void)
Clear Wake-up Flag 3.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU2 (void)
Clear Wake-up Flag 2.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU1 (void)
Clear Wake-up Flag 1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO4 (void)
Indicate whether VDDA voltage is below or above PVM4 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO3 (void)
Indicate whether VDDA voltage is below or above PVM3 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO2 (void)
Indicate whether VDDIO2 voltage is below or above PVM2 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO1 (void)
Indicate whether VDDUSB voltage is below or above PVM1 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below or above the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VOSF (void)
Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPF (void)
Indicate whether the regulator is ready in main mode or is in low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPS (void)
Indicate whether or not the low-power regulator is ready.
ErrorStatus | LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

Header file of PWR LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_pwr.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rcc.h File Reference

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stm32l4xx_ll_rcc.h File Reference

Header file of RCC LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...

Defines

#define | RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)
#define | RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)
#define | RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)
#define | RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL)
#define | RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM)
#define | RCC_POSITION_MSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL)
#define | RCC_POSITION_MSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM)
#define | RCC_POSITION_PLLN (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLN)
#define | RCC_POSITION_PLLM (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLM)
#define | RCC_POSITION_PLLR (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLR)
#define | RCC_POSITION_PLLP (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLP)
#define | RCC_POSITION_PLLQ (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLQ)
#define | RCC_POSITION_PLLSAI1N (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)
#define | RCC_POSITION_PLLSAI1P (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)
#define | RCC_POSITION_PLLSAI1Q (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)
#define | RCC_POSITION_PLLSAI1R (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)
#define | RCC_POSITION_PLLSAI2N (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)
#define | RCC_POSITION_PLLSAI2P (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)
#define | RCC_POSITION_PLLSAI2R (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)
#define | HSE_VALUE ((uint32_t)8000000)
#define | HSI_VALUE ((uint32_t)16000000)
#define | LSE_VALUE ((uint32_t)32768)
#define | LSI_VALUE ((uint32_t)32000)
#define | LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC
#define | LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
#define | LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC
#define | LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
#define | LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
#define | LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
#define | LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC
#define | LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC
#define | LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
#define | LL_RCC_CICR_CSSC RCC_CICR_CSSC
#define | LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF
#define | LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
#define | LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF
#define | LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
#define | LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
#define | LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
#define | LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF
#define | LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF
#define | LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
#define | LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
#define | LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF
#define | LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE
#define | LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
#define | LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE
#define | LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
#define | LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
#define | LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
#define | LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE
#define | LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE
#define | LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE
#define | LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
#define | LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0
#define | LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1
#define | LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2
#define | LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3
#define | LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4
#define | LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5
#define | LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6
#define | LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7
#define | LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8
#define | LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9
#define | LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10
#define | LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11
#define | LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1
#define | LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2
#define | LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4
#define | LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8
#define | LL_RCC_LSCO_CLKSOURCE_LSI (uint32_t)0x00000000
#define | LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL
#define | LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI
#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL
#define | LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL
#define | LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
#define | LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
#define | LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
#define | LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
#define | LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
#define | LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
#define | LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
#define | LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512
#define | LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
#define | LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
#define | LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
#define | LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16
#define | LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
#define | LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
#define | LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
#define | LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16
#define | LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000)
#define | LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
#define | LL_RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000)
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1
#define | LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1
#define | LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2
#define | LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4
#define | LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8
#define | LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16
#define | LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000
#define | LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU
#define | LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16) | 0x00000000)
#define | LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_0)
#define | LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_1)
#define | LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL)
#define | LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16) | 0x00000000)
#define | LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_0)
#define | LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_1)
#define | LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL)
#define | LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART3SEL << 16) | 0x00000000)
#define | LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_0)
#define | LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_1)
#define | LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL)
#define | LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART4SEL << 16) | 0x00000000)
#define | LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_0)
#define | LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_1)
#define | LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL)
#define | LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART5SEL << 16) | 0x00000000)
#define | LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_0)
#define | LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_1)
#define | LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL)
#define | LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000
#define | LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL
#define | LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000 >> 4))
#define | LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4))
#define | LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4))
#define | LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (0x00000000 >> 4))
#define | LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_0 >> 4))
#define | LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_1 >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000 >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4))
#define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000 >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000 >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16))
#define | LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI1SEL | (0x00000000 >> 16))
#define | LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16))
#define | LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16))
#define | LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16))
#define | LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI2SEL | (0x00000000 >> 16))
#define | LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16))
#define | LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16))
#define | LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16))
#define | LL_RCC_SDMMC1_CLKSOURCE_NONE (uint32_t)(0x00000000)
#define | LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)
#define | LL_RCC_SDMMC1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)
#define | LL_RCC_SDMMC1_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)
#define | LL_RCC_RNG_CLKSOURCE_NONE (uint32_t)(0x00000000)
#define | LL_RCC_RNG_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)
#define | LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)
#define | LL_RCC_RNG_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)
#define | LL_RCC_USB_CLKSOURCE_NONE (uint32_t)(0x00000000)
#define | LL_RCC_USB_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)
#define | LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)
#define | LL_RCC_USB_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)
#define | LL_RCC_ADC_CLKSOURCE_NONE (uint32_t)(0x00000000)
#define | LL_RCC_ADC_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_ADCSEL_0)
#define | LL_RCC_ADC_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_ADCSEL_1)
#define | LL_RCC_ADC_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_ADCSEL)
#define | LL_RCC_SWPMI1_CLKSOURCE_PCLK (uint32_t)(0x00000000)
#define | LL_RCC_SWPMI1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_SWPMI1SEL)
#define | LL_RCC_DFSDM1_CLKSOURCE_PCLK (uint32_t)(0x00000000)
#define | LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_DFSDM1SEL)
#define | LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL
#define | LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL
#define | LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL
#define | LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL
#define | LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL
#define | LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL
#define | LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL
#define | LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL
#define | LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL
#define | LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL
#define | LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL
#define | LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL
#define | LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL
#define | LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL
#define | LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL
#define | LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL
#define | LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL
#define | LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL
#define | LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL
#define | LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000)
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
#define | LL_RCC_PLLSOURCE_NONE (uint32_t)0x00000000
#define | LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI
#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
#define | LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
#define | LL_RCC_PLLM_DIV_1 ((uint32_t)0x00000000)
#define | LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)
#define | LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1))
#define | LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM)
#define | LL_RCC_PLLR_DIV_2 ((uint32_t)0x00000000)
#define | LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)
#define | LL_RCC_PLLP_DIV_7 ((uint32_t)0x00000000)
#define | LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP)
#define | LL_RCC_PLLQ_DIV_2 ((uint32_t)0x00000000)
#define | LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)
#define | LL_RCC_PLLSAI1Q_DIV_2 ((uint32_t)0x00000000)
#define | LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0)
#define | LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1)
#define | LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q)
#define | LL_RCC_PLLSAI1P_DIV_7 ((uint32_t)0x00000000)
#define | LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P)
#define | LL_RCC_PLLSAI1R_DIV_2 ((uint32_t)0x00000000)
#define | LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0)
#define | LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1)
#define | LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R)
#define | LL_RCC_PLLSAI2P_DIV_7 ((uint32_t)0x00000000)
#define | LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P)
#define | LL_RCC_PLLSAI2R_DIV_2 ((uint32_t)0x00000000)
#define | LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0)
#define | LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1)
#define | LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R)
#define | LL_RCC_MSIRANGESEL_STANDBY (uint32_t)0
#define | LL_RCC_MSIRANGESEL_RUN (uint32_t)1
#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.
#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)
Helper macro to calculate the PLLCLK frequency on system domain.
#define | __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLCLK frequency used on SAI domain.
#define | __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLCLK frequency used on 48M domain.
#define | __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__)
Helper macro to calculate the PLLSAI1 frequency used for SAI domain.
#define | __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__)
Helper macro to calculate the PLLSAI1 frequency used on 48M domain.
#define | __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__)
Helper macro to calculate the PLLSAI1 frequency used on ADC domain.
#define | __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__)
Helper macro to calculate the PLLSAI2 frequency used for SAI domain.
#define | __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__)
Helper macro to calculate the PLLSAI2 frequency used on ADC domain.
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE])
Helper macro to calculate the HCLK frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2])
Helper macro to calculate the PCLK2 frequency (ABP2)
#define | __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__)
Helper macro to calculate the MSI frequency (in Hz)

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.
__STATIC_INLINE void | LL_RCC_HSI_EnableInStopMode (void)
Enable HSI even in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableInStopMode (void)
Disable HSI in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE void | LL_RCC_HSI_EnableAutoFromStop (void)
Enable HSI Automatic from stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableAutoFromStop (void)
Disable HSI Automatic from stop mode.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.
__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void)
Enable Clock security system on LSE.
__STATIC_INLINE void | LL_RCC_LSE_DisableCSS (void)
Disable Clock security system on LSE.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsCSSDetected (void)
Check if CSS on LSE failure Detection.
__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.
__STATIC_INLINE void | LL_RCC_MSI_Enable (void)
Enable MSI oscillator.
__STATIC_INLINE void | LL_RCC_MSI_Disable (void)
Disable MSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_MSI_IsReady (void)
Check if MSI oscillator Ready.
__STATIC_INLINE void | LL_RCC_MSI_EnablePLLMode (void)
Enable MSI PLL-mode (Hardware auto calibration with LSE)
__STATIC_INLINE void | LL_RCC_MSI_DisablePLLMode (void)
Disable MSI-PLL mode.
__STATIC_INLINE void | LL_RCC_MSI_EnableRangeSelection (void)
Enable MSI clock range selection with MSIRANGE register.
__STATIC_INLINE uint32_t | LL_RCC_MSI_IsEnabledRangeSelect (void)
Check if MSI clock range is selected with MSIRANGE register.
__STATIC_INLINE void | LL_RCC_MSI_SetRange (uint32_t Range)
Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetRange (void)
Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
__STATIC_INLINE void | LL_RCC_MSI_SetRangeAfterStandby (uint32_t Range)
Configure MSI range used after standby.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetRangeAfterStandby (void)
Get MSI range used after standby.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetCalibration (void)
Get MSI Calibration value.
__STATIC_INLINE void | LL_RCC_MSI_SetCalibTrimming (uint32_t Value)
Set MSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetCalibTrimming (void)
Get MSI Calibration trimming.
__STATIC_INLINE void | LL_RCC_LSCO_Enable (void)
Enable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_Disable (void)
Disable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_SetSource (uint32_t Source)
Configure Low speed clock selection.
__STATIC_INLINE uint32_t | LL_RCC_LSCO_GetSource (void)
Get Low speed clock selection.
__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.
__STATIC_INLINE void | LL_RCC_SetClkAfterWakeFromStop (uint32_t Clock)
Set Clock After Wake-Up From Stop mode.
__STATIC_INLINE uint32_t | LL_RCC_GetClkAfterWakeFromStop (void)
Get Clock After Wake-Up From Stop mode.
__STATIC_INLINE void | LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.
__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetUARTClockSource (uint32_t UARTxSource)
Configure UARTx clock source.
__STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t LPUARTxSource)
Configure LPUART1x clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t LPTIMxSource)
Configure LPTIMx clock source.
__STATIC_INLINE void | LL_RCC_SetSAIClockSource (uint32_t SAIxSource)
Configure SAIx clock source.
__STATIC_INLINE void | LL_RCC_SetSDMMCClockSource (uint32_t SDMMCxSource)
Configure SDMMC1 clock source.
__STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t RNGxSource)
Configure RNG clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE void | LL_RCC_SetSWPMIClockSource (uint32_t SWPMIxSource)
Configure SWPMI clock source.
__STATIC_INLINE void | LL_RCC_SetDFSDMClockSource (uint32_t DFSDMxSource)
Configure DFSDM clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t USARTx)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUARTClockSource (uint32_t UARTx)
Get UARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t LPUARTx)
Get LPUARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t I2Cx)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t LPTIMx)
Get LPTIMx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSAIClockSource (uint32_t SAIx)
Get SAIx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSDMMCClockSource (uint32_t SDMMCx)
Get SDMMCx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t RNGx)
Get RNGx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSWPMIClockSource (uint32_t SPWMIx)
Get SWPMIx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetDFSDMClockSource (uint32_t DFSDMx)
Get DFSDMx clock source.
__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.
__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for 48Mhz domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetN (void)
Get Main PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetP (void)
Get Main PLL division factor for PLLP.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetQ (void)
Get Main PLL division factor for PLLQ.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetR (void)
Get Main PLL division factor for PLLR.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetDivider (void)
Get Division factor for the main PLL and other PLL.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SAI (void)
Enable PLL output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SAI (void)
Disable PLL output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_48M (void)
Enable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_48M (void)
Disable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SYS (void)
Enable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SYS (void)
Disable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void | LL_RCC_PLLSAI1_Enable (void)
Enable PLLSAI1.
__STATIC_INLINE void | LL_RCC_PLLSAI1_Disable (void)
Disable PLLSAI1.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_IsReady (void)
Check if PLLSAI1 Ready.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLLSAI1 used for 48Mhz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLLSAI1 used for SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLLSAI1 used for ADC domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetN (void)
Get SAI1PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetP (void)
Get SAI1PLL division factor for PLLSAI1P.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetQ (void)
Get SAI1PLL division factor for PLLSAI1Q.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetR (void)
Get PLLSAI1 division factor for PLLSAIR.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_SAI (void)
Enable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_SAI (void)
Disable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_48M (void)
Enable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_48M (void)
Disable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_ADC (void)
Enable PLLSAI1 output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_ADC (void)
Disable PLLSAI1 output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI2_Enable (void)
Enable PLLSAI2.
__STATIC_INLINE void | LL_RCC_PLLSAI2_Disable (void)
Disable PLLSAI2.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI2_IsReady (void)
Check if PLLSAI2 Ready.
__STATIC_INLINE void | LL_RCC_PLLSAI2_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLLSAI2 used for SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI2_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLLSAI2 used for ADC domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI2_GetN (void)
Get SAI2PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI2_GetP (void)
Get SAI2PLL division factor for PLLSAI2P.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI2_GetR (void)
Get SAI2PLL division factor for PLLSAI2R.
__STATIC_INLINE void | LL_RCC_PLLSAI2_EnableDomain_SAI (void)
Enable PLLSAI2 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI2_DisableDomain_SAI (void)
Disable PLLSAI2 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI2_EnableDomain_ADC (void)
Enable PLLSAI2 output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI2_DisableDomain_ADC (void)
Disable PLLSAI2 output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_MSIRDY (void)
Clear MSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLSAI1RDY (void)
Clear PLLSAI1 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLSAI2RDY (void)
Clear PLLSAI1 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void)
Clear LSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_MSIRDY (void)
Check if MSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLSAI1RDY (void)
Check if PLLSAI1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLSAI2RDY (void)
Check if PLLSAI1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void)
Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_FWRST (void)
Check if RCC flag FW reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_OBLRST (void)
Check if RCC flag is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_BORRST (void)
Check if RCC flag BOR reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.
__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_MSIRDY (void)
Enable MSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLSAI1RDY (void)
Enable PLLSAI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLSAI2RDY (void)
Enable PLLSAI2 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSECSS (void)
Enable LSE clock security system interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_MSIRDY (void)
Disable MSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLSAI1RDY (void)
Disable PLLSAI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLSAI2RDY (void)
Disable PLLSAI2 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSECSS (void)
Disable LSE clock security system interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_MSIRDY (void)
Checks if MSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLSAI1RDY (void)
Checks if PLLSAI1 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLSAI2RDY (void)
Checks if PLLSAI2 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSECSS (void)
Checks if LSECSS interrupt source is enabled or disabled.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetUARTClockFreq (uint32_t UARTxSource)
Return UARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetSDMMCClockFreq (uint32_t SDMMCxSource)
Return SDMMCx clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetSWPMIClockFreq (uint32_t SWPMIxSource)
Return SWPMIx clock frequency.
uint32_t | LL_RCC_GetDFSDMClockFreq (uint32_t DFSDMxSource)
Return DFSDMx clock frequency.

Variables

static const uint8_t | aRCC_APBAHBPrescTable [8] = {0, 0, 0, 0, 1, 2, 3, 4}

Detailed Description

Header file of RCC LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_rcc.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rng.h File Reference

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stm32l4xx_ll_rng.h File Reference

Header file of RNG LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Defines

#define | LL_RNG_SR_DRDY RNG_SR_DRDY
#define | LL_RNG_SR_CECS RNG_SR_CECS
#define | LL_RNG_SR_SECS RNG_SR_SECS
#define | LL_RNG_SR_CEIS RNG_SR_CEIS
#define | LL_RNG_SR_SEIS RNG_SR_SEIS
#define | LL_RNG_CR_IE RNG_CR_IE
#define | LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RNG register.
#define | LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RNG register.

Functions

__STATIC_INLINE void | LL_RNG_Enable (RNG_TypeDef *RNGx)
Enable Random Number Generation.
__STATIC_INLINE void | LL_RNG_Disable (RNG_TypeDef *RNGx)
Disable Random Number Generation.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabled (RNG_TypeDef *RNGx)
Check if Random Number Generator is enabled.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_DRDY (RNG_TypeDef *RNGx)
Indicate if the RNG Data ready Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CECS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SECS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CEIS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Interrupt Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SEIS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Interrupt Status Flag is set or not.
__STATIC_INLINE void | LL_RNG_ClearFlag_CEIS (RNG_TypeDef *RNGx)
Clear Clock Error interrupt Status (CEIS) Flag.
__STATIC_INLINE void | LL_RNG_ClearFlag_SEIS (RNG_TypeDef *RNGx)
Clear Seed Error interrupt Status (SEIS) Flag.
__STATIC_INLINE void | LL_RNG_EnableIT (RNG_TypeDef *RNGx)
Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE void | LL_RNG_DisableIT (RNG_TypeDef *RNGx)
Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledIT (RNG_TypeDef *RNGx)
Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_ReadRandData32 (RNG_TypeDef *RNGx)
Return32-bit Random Number value.
ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).

Detailed Description

Header file of RNG LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_rng.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rtc.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_ll_rtc.h File Reference

Header file of RTC LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...

Defines

#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define | RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define | RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
#define | RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
#define | RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
#define | RTC_POSITION_TR_HT (uint32_t)POSITION_VAL(RTC_TR_HT)
#define | RTC_POSITION_TR_HU (uint32_t)POSITION_VAL(RTC_TR_HU)
#define | RTC_POSITION_TR_MT (uint32_t)POSITION_VAL(RTC_TR_MNT)
#define | RTC_POSITION_TR_MU (uint32_t)POSITION_VAL(RTC_TR_MNU)
#define | RTC_POSITION_TR_ST (uint32_t)POSITION_VAL(RTC_TR_ST)
#define | RTC_POSITION_TR_SU (uint32_t)POSITION_VAL(RTC_TR_SU)
#define | RTC_POSITION_DR_YT (uint32_t)POSITION_VAL(RTC_DR_YT)
#define | RTC_POSITION_DR_YU (uint32_t)POSITION_VAL(RTC_DR_YU)
#define | RTC_POSITION_DR_MT (uint32_t)POSITION_VAL(RTC_DR_MT)
#define | RTC_POSITION_DR_MU (uint32_t)POSITION_VAL(RTC_DR_MU)
#define | RTC_POSITION_DR_DT (uint32_t)POSITION_VAL(RTC_DR_DT)
#define | RTC_POSITION_DR_DU (uint32_t)POSITION_VAL(RTC_DR_DU)
#define | RTC_POSITION_DR_WDU (uint32_t)POSITION_VAL(RTC_DR_WDU)
#define | RTC_POSITION_ALMA_DT (uint32_t)POSITION_VAL(RTC_ALRMAR_DT)
#define | RTC_POSITION_ALMA_DU (uint32_t)POSITION_VAL(RTC_ALRMAR_DU)
#define | RTC_POSITION_ALMA_HT (uint32_t)POSITION_VAL(RTC_ALRMAR_HT)
#define | RTC_POSITION_ALMA_HU (uint32_t)POSITION_VAL(RTC_ALRMAR_HU)
#define | RTC_POSITION_ALMA_MT (uint32_t)POSITION_VAL(RTC_ALRMAR_MNT)
#define | RTC_POSITION_ALMA_MU (uint32_t)POSITION_VAL(RTC_ALRMAR_MNU)
#define | RTC_POSITION_ALMA_SU (uint32_t)POSITION_VAL(RTC_ALRMAR_SU)
#define | RTC_POSITION_ALMA_ST (uint32_t)POSITION_VAL(RTC_ALRMAR_ST)
#define | RTC_POSITION_ALMB_DT (uint32_t)POSITION_VAL(RTC_ALRMBR_DT)
#define | RTC_POSITION_ALMB_DU (uint32_t)POSITION_VAL(RTC_ALRMBR_DU)
#define | RTC_POSITION_ALMB_HT (uint32_t)POSITION_VAL(RTC_ALRMBR_HT)
#define | RTC_POSITION_ALMB_HU (uint32_t)POSITION_VAL(RTC_ALRMBR_HU)
#define | RTC_POSITION_ALMB_MT (uint32_t)POSITION_VAL(RTC_ALRMBR_MNT)
#define | RTC_POSITION_ALMB_MU (uint32_t)POSITION_VAL(RTC_ALRMBR_MNU)
#define | RTC_POSITION_ALMB_SU (uint32_t)POSITION_VAL(RTC_ALRMBR_SU)
#define | RTC_POSITION_ALMB_ST (uint32_t)POSITION_VAL(RTC_ALRMBR_ST)
#define | RTC_POSITION_PRER_PREDIV_A (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)
#define | RTC_POSITION_ALMA_MASKSS (uint32_t)POSITION_VAL(RTC_ALRMASSR_MASKSS)
#define | RTC_POSITION_ALMB_MASKSS (uint32_t)POSITION_VAL(RTC_ALRMBSSR_MASKSS)
#define | RTC_POSITION_TS_HU (uint32_t)POSITION_VAL(RTC_TSTR_HU)
#define | RTC_POSITION_TS_MNU (uint32_t)POSITION_VAL(RTC_TSTR_MNU)
#define | RTC_POSITION_TS_WDU (uint32_t)POSITION_VAL(RTC_TSDR_WDU)
#define | RTC_POSITION_TS_MU (uint32_t)POSITION_VAL(RTC_TSDR_MU)
#define | RTC_OFFSET_WEEKDAY (uint32_t)24U
#define | RTC_OFFSET_DAY (uint32_t)16U
#define | RTC_OFFSET_MONTH (uint32_t)8U
#define | RTC_OFFSET_HOUR (uint32_t)16U
#define | RTC_OFFSET_MINUTE (uint32_t)8U
#define | LL_RTC_FORMAT_BIN ((uint32_t)0x000000000U)
#define | LL_RTC_FORMAT_BCD ((uint32_t)0x000000001U)
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL
#define | LL_RTC_ISR_ITSF RTC_ISR_ITSF
#define | LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
#define | LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
#define | LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
#define | LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
#define | LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
#define | LL_RTC_ISR_TSF RTC_ISR_TSF
#define | LL_RTC_ISR_WUTF RTC_ISR_WUTF
#define | LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
#define | LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
#define | LL_RTC_ISR_INITF RTC_ISR_INITF
#define | LL_RTC_ISR_RSF RTC_ISR_RSF
#define | LL_RTC_ISR_INITS RTC_ISR_INITS
#define | LL_RTC_ISR_SHPF RTC_ISR_SHPF
#define | LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
#define | LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
#define | LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
#define | LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE
#define | LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE
#define | LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE
#define | LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE
#define | LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | LL_RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | LL_RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | LL_RTC_MONTH_MAY ((uint8_t)0x05U)
#define | LL_RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | LL_RTC_MONTH_JULY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)
#define | LL_RTC_HOURFORMAT_24HOUR (uint32_t)0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT
#define | LL_RTC_ALARMOUT_DISABLE ((uint32_t)0x00000000U)
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL
#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN (uint32_t)0x00000000U
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE
#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH (uint32_t)0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL
#define | LL_RTC_TIME_FORMAT_AM_OR_24 (uint32_t)0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM
#define | LL_RTC_SHIFT_SECOND_DELAY (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
#define | LL_RTC_ALMA_MASK_NONE ((uint32_t)0x00000000U)
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)
#define | LL_RTC_ALMA_TIME_FORMAT_AM (uint32_t)0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM
#define | LL_RTC_ALMB_MASK_NONE ((uint32_t)0x00000000U)
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)
#define | LL_RTC_ALMB_TIME_FORMAT_AM (uint32_t)0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM
#define | LL_RTC_TIMESTAMP_EDGE_RISING (uint32_t)0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE
#define | LL_RTC_TS_TIME_FORMAT_AM (uint32_t)0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM
#define | LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
#define | LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF
#define | LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF
#define | LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF
#define | LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE
#define | LL_RTC_TAMPER_DURATION_1RTCCLK ((uint32_t)0x00000000U)
#define | LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH
#define | LL_RTC_TAMPER_FILTER_DISABLE ((uint32_t)0x00000000U)
#define | LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT
#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 ((uint32_t)0x00000000U)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG
#define | LL_RTC_WAKEUPCLOCK_DIV_16 ((uint32_t)0x00000000U)
#define | LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1)
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)
#define | LL_RTC_BKP_DR0 ((uint32_t)0x00000000U)
#define | LL_RTC_BKP_DR1 ((uint32_t)0x00000001U)
#define | LL_RTC_BKP_DR2 ((uint32_t)0x00000002U)
#define | LL_RTC_BKP_DR3 ((uint32_t)0x00000003U)
#define | LL_RTC_BKP_DR4 ((uint32_t)0x00000004U)
#define | LL_RTC_BKP_DR5 ((uint32_t)0x00000005U)
#define | LL_RTC_BKP_DR6 ((uint32_t)0x00000006U)
#define | LL_RTC_BKP_DR7 ((uint32_t)0x00000007U)
#define | LL_RTC_BKP_DR8 ((uint32_t)0x00000008U)
#define | LL_RTC_BKP_DR9 ((uint32_t)0x00000009U)
#define | LL_RTC_BKP_DR10 ((uint32_t)0x0000000AU)
#define | LL_RTC_BKP_DR11 ((uint32_t)0x0000000BU)
#define | LL_RTC_BKP_DR12 ((uint32_t)0x0000000CU)
#define | LL_RTC_BKP_DR13 ((uint32_t)0x0000000DU)
#define | LL_RTC_BKP_DR14 ((uint32_t)0x0000000EU)
#define | LL_RTC_BKP_DR15 ((uint32_t)0x0000000FU)
#define | LL_RTC_BKP_DR16 ((uint32_t)0x00000010U)
#define | LL_RTC_BKP_DR17 ((uint32_t)0x00000011U)
#define | LL_RTC_BKP_DR18 ((uint32_t)0x00000012U)
#define | LL_RTC_BKP_DR19 ((uint32_t)0x00000013U)
#define | LL_RTC_BKP_DR20 ((uint32_t)0x00000014U)
#define | LL_RTC_BKP_DR21 ((uint32_t)0x00000015U)
#define | LL_RTC_BKP_DR22 ((uint32_t)0x00000016U)
#define | LL_RTC_BKP_DR23 ((uint32_t)0x00000017U)
#define | LL_RTC_BKP_DR24 ((uint32_t)0x00000018U)
#define | LL_RTC_BKP_DR25 ((uint32_t)0x00000019U)
#define | LL_RTC_BKP_DR26 ((uint32_t)0x0000001AU)
#define | LL_RTC_BKP_DR27 ((uint32_t)0x0000001BU)
#define | LL_RTC_BKP_DR28 ((uint32_t)0x0000001CU)
#define | LL_RTC_BKP_DR29 ((uint32_t)0x0000001DU)
#define | LL_RTC_BKP_DR30 ((uint32_t)0x0000001EU)
#define | LL_RTC_BKP_DR31 ((uint32_t)0x0000001FU)
#define | LL_RTC_CALIB_OUTPUT_NONE (uint32_t)0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE)
#define | LL_RTC_CALIB_INSERTPULSE_NONE (uint32_t)0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP
#define | LL_RTC_CALIB_PERIOD_32SEC (uint32_t)0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RTC register.
#define | LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RTC register.
#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
Helper macro to convert a value from BCD format to 2 digit decimal format.
#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.
#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_EnableOutRemap (RTC_TypeDef *RTCx)
Enable RTC_OUT remap.
__STATIC_INLINE void | LL_RTC_DisableOutRemap (RTC_TypeDef *RTCx)
Disable RTC_OUT remap.
__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.
__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.
__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.
__STATIC_INLINE void | LL_RTC_TS_EnableInternalEvent (RTC_TypeDef *RTCx)
Enable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_DisableInternalEvent (RTC_TypeDef *RTCx)
Disable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TAMPER_Enable (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (RTC_TypeDef *RTCx, uint32_t Tamper)
Clear RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Enable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Disable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (RTC_TypeDef *RTCx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (RTC_TypeDef *RTCx)
Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (RTC_TypeDef *RTCx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (RTC_TypeDef *RTCx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (RTC_TypeDef *RTCx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (RTC_TypeDef *RTCx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (RTC_TypeDef *RTCx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (RTC_TypeDef *RTCx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.
__STATIC_INLINE void | LL_RTC_BAK_SetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
__STATIC_INLINE uint32_t | LL_RTC_BAK_GetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITS (RTC_TypeDef *RTCx)
Get Internal Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (RTC_TypeDef *RTCx)
Get RTC_TAMP3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (RTC_TypeDef *RTCx)
Get RTC_TAMP2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (RTC_TypeDef *RTCx)
Get RTC_TAMP1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITS (RTC_TypeDef *RTCx)
Clear Internal Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (RTC_TypeDef *RTCx)
Clear RTC_TAMP3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (RTC_TypeDef *RTCx)
Clear RTC_TAMP2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (RTC_TypeDef *RTCx)
Clear RTC_TAMP1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.
__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP3 (RTC_TypeDef *RTCx)
Enable Tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP3 (RTC_TypeDef *RTCx)
Disable Tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP2 (RTC_TypeDef *RTCx)
Enable Tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP2 (RTC_TypeDef *RTCx)
Disable Tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP1 (RTC_TypeDef *RTCx)
Enable Tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP1 (RTC_TypeDef *RTCx)
Disable Tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP (RTC_TypeDef *RTCx)
Enable all Tamper Interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP (RTC_TypeDef *RTCx)
Disable all Tamper Interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP3 (RTC_TypeDef *RTCx)
Check if Tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP2 (RTC_TypeDef *RTCx)
Check if Tamper 2 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP1 (RTC_TypeDef *RTCx)
Check if Tamper 1 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP (RTC_TypeDef *RTCx)
Check if all the TAMPER interrupts are enabled or not.
ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Header file of RTC LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_rtc.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_spi.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_ll_spi.h File Reference

Header file of SPI LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_SPI_InitTypeDef
SPI Init structures definition. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_UDR SPI_SR_UDR
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE
#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE
#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U)
#define | LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U)
#define | LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)
#define | LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U)
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)
#define | LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U)
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)
#define | LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U)
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST ((uint32_t)0x00000000U)
#define | LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U)
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)
#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))
#define | LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)
#define | LL_SPI_CRC_8BIT ((uint32_t)0x00000000U)
#define | LL_SPI_CRC_16BIT (SPI_CR1_CRCL)
#define | LL_SPI_RX_FIFO_TH_HALF ((uint32_t)0x00000000U)
#define | LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)
#define | LL_SPI_RX_FIFO_EMPTY ((uint32_t)0x00000000U)
#define | LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)
#define | LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)
#define | LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)
#define | LL_SPI_TX_FIFO_EMPTY ((uint32_t)0x00000000U)
#define | LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)
#define | LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)
#define | LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)
#define | LL_SPI_DMA_PARITY_EVEN ((uint32_t)0x00000000U)
#define | LL_SPI_DMA_PARITY_ODD ((uint32_t)0x00000001U)
#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_SetRxFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.
__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse management.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse management.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t | LL_SPI_GetTxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.
__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void | LL_SPI_SetDMAParity_RX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA reception.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_RX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA reception.
__STATIC_INLINE void | LL_SPI_SetDMAParity_TX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_TX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.
ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Detailed Description

Header file of SPI LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_spi.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_swpmi.h File Reference

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stm32l4xx_ll_swpmi.h File Reference

Header file of SWPMI LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_SWPMI_InitTypeDef
SWPMI Init structures definition. More...

Defines

#define | LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF
#define | LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF
#define | LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF
#define | LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF
#define | LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF
#define | LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF
#define | LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF
#define | LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF
#define | LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF
#define | LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF
#define | LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF
#define | LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF
#define | LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE
#define | LL_SWPMI_ISR_TXE SWPMI_ISR_TXE
#define | LL_SWPMI_ISR_TCF SWPMI_ISR_TCF
#define | LL_SWPMI_ISR_SRF SWPMI_ISR_SRF
#define | LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP
#define | LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF
#define | LL_SWPMI_IER_SRIE SWPMI_IER_SRIE
#define | LL_SWPMI_IER_TCIE SWPMI_IER_TCIE
#define | LL_SWPMI_IER_TIE SWPMI_IER_TIE
#define | LL_SWPMI_IER_RIE SWPMI_IER_RIE
#define | LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE
#define | LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE
#define | LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE
#define | LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE
#define | LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE
#define | LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)
#define | LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE
#define | LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)
#define | LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE
#define | LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define | LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS
#define | LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0
#define | LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1
#define | LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SWPMI register.
#define | LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SWPMI register.
#define | __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
Helper macro to calculate bit rate value to set in BRR register (LL_SWPMI_SetBitRatePrescaler function)

Functions

__STATIC_INLINE void | LL_SWPMI_SetReceptionMode (SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
Set Reception buffering mode.
__STATIC_INLINE uint32_t | LL_SWPMI_GetReceptionMode (SWPMI_TypeDef *SWPMIx)
Get Reception buffering mode.
__STATIC_INLINE void | LL_SWPMI_SetTransmissionMode (SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
Set Transmission buffering mode.
__STATIC_INLINE uint32_t | LL_SWPMI_GetTransmissionMode (SWPMI_TypeDef *SWPMIx)
Get Transmission buffering mode.
__STATIC_INLINE void | LL_SWPMI_EnableLoopback (SWPMI_TypeDef *SWPMIx)
Enable loopback mode.
__STATIC_INLINE void | LL_SWPMI_DisableLoopback (SWPMI_TypeDef *SWPMIx)
Disable loopback mode.
__STATIC_INLINE void | LL_SWPMI_Activate (SWPMI_TypeDef *SWPMIx)
Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActivated (SWPMI_TypeDef *SWPMIx)
Check if Single wire protocol bus is in ACTIVATED state.
__STATIC_INLINE void | LL_SWPMI_Deactivate (SWPMI_TypeDef *SWPMIx)
Deactivate immediately Single wire protocol bus (immediate transition to DEACTIVATED state)
__STATIC_INLINE void | LL_SWPMI_RequestDeactivation (SWPMI_TypeDef *SWPMIx)
Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED state if no resume from slave)
__STATIC_INLINE void | LL_SWPMI_SetBitRatePrescaler (SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)
__STATIC_INLINE uint32_t | LL_SWPMI_GetBitRatePrescaler (SWPMI_TypeDef *SWPMIx)
Get Bitrate prescaler.
__STATIC_INLINE void | LL_SWPMI_SetVoltageClass (SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
Set SWP Voltage Class.
__STATIC_INLINE uint32_t | LL_SWPMI_GetVoltageClass (SWPMI_TypeDef *SWPMIx)
Get SWP Voltage Class.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXBF (SWPMI_TypeDef *SWPMIx)
Check if the last word of the frame under reception has arrived in SWPMI_RDR.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXBE (SWPMI_TypeDef *SWPMIx)
Check if Frame transmission buffer has been emptied.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXBER (SWPMI_TypeDef *SWPMIx)
Check if CRC error in reception has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXOVR (SWPMI_TypeDef *SWPMIx)
Check if Overrun in reception has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXUNR (SWPMI_TypeDef *SWPMIx)
Check if underrun error in transmission has been detected.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_RXNE (SWPMI_TypeDef *SWPMIx)
Check if Receive data register not empty (it means that Received data is ready to be read in the SWPMI_RDR register)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TXE (SWPMI_TypeDef *SWPMIx)
Check if Transmit data register is empty (it means that Data written in transmit data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_TC (SWPMI_TypeDef *SWPMIx)
Check if Both transmission and reception are completed and SWP is switched to the SUSPENDED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_SR (SWPMI_TypeDef *SWPMIx)
Check if a Resume by slave state has been detected during the SWP bus SUSPENDED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_SUSP (SWPMI_TypeDef *SWPMIx)
Check if SWP bus is in SUSPENDED or DEACTIVATED state.
__STATIC_INLINE uint32_t | LL_SWPMI_IsActiveFlag_DEACT (SWPMI_TypeDef *SWPMIx)
Check if SWP bus is in DEACTIVATED state.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXBF (SWPMI_TypeDef *SWPMIx)
Clear receive buffer full flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TXBE (SWPMI_TypeDef *SWPMIx)
Clear transmit buffer empty flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXBER (SWPMI_TypeDef *SWPMIx)
Clear receive CRC error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_RXOVR (SWPMI_TypeDef *SWPMIx)
Clear receive overrun error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TXUNR (SWPMI_TypeDef *SWPMIx)
Clear transmit underrun error flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_TC (SWPMI_TypeDef *SWPMIx)
Clear transfer complete flag.
__STATIC_INLINE void | LL_SWPMI_ClearFlag_SR (SWPMI_TypeDef *SWPMIx)
Clear slave resume flag.
__STATIC_INLINE void | LL_SWPMI_EnableIT_SR (SWPMI_TypeDef *SWPMIx)
Enable Slave resume interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TC (SWPMI_TypeDef *SWPMIx)
Enable Transmit complete interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TX (SWPMI_TypeDef *SWPMIx)
Enable Transmit interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RX (SWPMI_TypeDef *SWPMIx)
Enable Receive interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Enable Transmit underrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Enable Receive overrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXBER (SWPMI_TypeDef *SWPMIx)
Enable Receive CRC error interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_TXBE (SWPMI_TypeDef *SWPMIx)
Enable Transmit buffer empty interrupt.
__STATIC_INLINE void | LL_SWPMI_EnableIT_RXBF (SWPMI_TypeDef *SWPMIx)
Enable Receive buffer full interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_SR (SWPMI_TypeDef *SWPMIx)
Disable Slave resume interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TC (SWPMI_TypeDef *SWPMIx)
Disable Transmit complete interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TX (SWPMI_TypeDef *SWPMIx)
Disable Transmit interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RX (SWPMI_TypeDef *SWPMIx)
Disable Receive interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Disable Transmit underrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Disable Receive overrun error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXBER (SWPMI_TypeDef *SWPMIx)
Disable Receive CRC error interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_TXBE (SWPMI_TypeDef *SWPMIx)
Disable Transmit buffer empty interrupt.
__STATIC_INLINE void | LL_SWPMI_DisableIT_RXBF (SWPMI_TypeDef *SWPMIx)
Disable Receive buffer full interrupt.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_SR (SWPMI_TypeDef *SWPMIx)
Check if Slave resume interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TC (SWPMI_TypeDef *SWPMIx)
Check if Transmit complete interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TX (SWPMI_TypeDef *SWPMIx)
Check if Transmit interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RX (SWPMI_TypeDef *SWPMIx)
Check if Receive interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TXUNR (SWPMI_TypeDef *SWPMIx)
Check if Transmit underrun error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXOVR (SWPMI_TypeDef *SWPMIx)
Check if Receive overrun error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXBER (SWPMI_TypeDef *SWPMIx)
Check if Receive CRC error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_TXBE (SWPMI_TypeDef *SWPMIx)
Check if Transmit buffer empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledIT_RXBF (SWPMI_TypeDef *SWPMIx)
Check if Receive buffer full interrupt is enabled.
__STATIC_INLINE void | LL_SWPMI_EnableDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Enable DMA mode for reception.
__STATIC_INLINE void | LL_SWPMI_DisableDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Disable DMA mode for reception.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledDMAReq_RX (SWPMI_TypeDef *SWPMIx)
Check if DMA mode for reception is enabled.
__STATIC_INLINE void | LL_SWPMI_EnableDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Enable DMA mode for transmission.
__STATIC_INLINE void | LL_SWPMI_DisableDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Disable DMA mode for transmission.
__STATIC_INLINE uint32_t | LL_SWPMI_IsEnabledDMAReq_TX (SWPMI_TypeDef *SWPMIx)
Check if DMA mode for transmission is enabled.
__STATIC_INLINE uint32_t | LL_SWPMI_DMA_GetRegAddr (SWPMI_TypeDef *SWPMIx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint32_t | LL_SWPMI_GetReceiveFrameLength (SWPMI_TypeDef *SWPMIx)
Retrieve number of data bytes present in payload of received frame.
__STATIC_INLINE void | LL_SWPMI_TransmitData32 (SWPMI_TypeDef *SWPMIx, uint32_t TxData)
Transmit Data Register.
__STATIC_INLINE uint32_t | LL_SWPMI_ReceiveData32 (SWPMI_TypeDef *SWPMIx)
Receive Data Register.
__STATIC_INLINE void | LL_SWPMI_EnableTXBypass (SWPMI_TypeDef *SWPMIx)
Enable SWP Transceiver Bypass.
__STATIC_INLINE void | LL_SWPMI_DisableTXBypass (SWPMI_TypeDef *SWPMIx)
Disable SWP Transceiver Bypass.
ErrorStatus | LL_SWPMI_DeInit (SWPMI_TypeDef *SWPMIx)
De-initialize the SWPMI peripheral registers to their default reset values.
ErrorStatus | LL_SWPMI_Init (SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
void | LL_SWPMI_StructInit (LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
Set each LL_SWPMI_InitTypeDef field to default value.

Detailed Description

Header file of SWPMI LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_swpmi.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_system.h File Reference

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Defines | Functions
stm32l4xx_ll_system.h File Reference

Header file of SYSTEM LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Defines

#define | DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
#define | FLASH_PDKEY1 ((uint32_t)0x04152637U)
Power-down in Run mode Flash key.
#define | FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU)
#define | LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000
#define | LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#define | LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#define | LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1
#define | LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
#define | LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000
#define | LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | LL_SYSCFG_EXTI_PORTA (uint32_t)0
#define | LL_SYSCFG_EXTI_PORTB (uint32_t)1
#define | LL_SYSCFG_EXTI_PORTC (uint32_t)2
#define | LL_SYSCFG_EXTI_PORTD (uint32_t)3
#define | LL_SYSCFG_EXTI_PORTE (uint32_t)4
#define | LL_SYSCFG_EXTI_PORTF (uint32_t)5
#define | LL_SYSCFG_EXTI_PORTG (uint32_t)6
#define | LL_SYSCFG_EXTI_PORTH (uint32_t)7
#define | LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /* !< EXTI_POSITION_0 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /* !< EXTI_POSITION_4 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /* !< EXTI_POSITION_8 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /* !< EXTI_POSITION_12 | EXTICR[0] */
#define | LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /* !< EXTI_POSITION_0 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /* !< EXTI_POSITION_4 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /* !< EXTI_POSITION_8 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /* !< EXTI_POSITION_12 | EXTICR[1] */
#define | LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /* !< EXTI_POSITION_0 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /* !< EXTI_POSITION_4 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /* !< EXTI_POSITION_8 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /* !< EXTI_POSITION_12 | EXTICR[2] */
#define | LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /* !< EXTI_POSITION_0 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /* !< EXTI_POSITION_4 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /* !< EXTI_POSITION_8 | EXTICR[3] */
#define | LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /* !< EXTI_POSITION_12 | EXTICR[3] */
#define | LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL
#define | LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL
#define | LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL
#define | LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0
#define | LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1
#define | LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2
#define | LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3
#define | LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4
#define | LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5
#define | LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6
#define | LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7
#define | LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8
#define | LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9
#define | LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10
#define | LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11
#define | LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12
#define | LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13
#define | LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14
#define | LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15
#define | LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16
#define | LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17
#define | LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18
#define | LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19
#define | LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20
#define | LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21
#define | LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22
#define | LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23
#define | LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24
#define | LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25
#define | LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26
#define | LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27
#define | LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28
#define | LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29
#define | LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30
#define | LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31
#define | LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000U
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)
#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP
#define | LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP
#define | LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP
#define | LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
#define | LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS
#define | LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

Functions

__STATIC_INLINE void | LL_SYSCFG_SetRemapMemory (uint32_t Memory)
Set memory mapping at address 0x00000000.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetRemapMemory (void)
Get memory mapping at address 0x00000000.
__STATIC_INLINE void | LL_SYSCFG_SetFlashBankMode (uint32_t Bank)
Select Flash bank mode (Bank flashed at 0x08000000)
__STATIC_INLINE uint32_t | LL_SYSCFG_GetFlashBankMode (void)
Get Flash bank mode (Bank flashed at 0x08000000)
__STATIC_INLINE void | LL_SYSCFG_EnableFirewall (void)
Firewall protection enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledFirewall (void)
Check if Firewall protection is enabled or not.
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogBooster (void)
Enable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogBooster (void)
Disable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IOC (void)
Enable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_DZC (void)
Enable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_UFC (void)
Enable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_OFC (void)
Enable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IDC (void)
Enable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IXC (void)
Enable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IOC (void)
Disable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_DZC (void)
Disable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_UFC (void)
Disable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_OFC (void)
Disable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IDC (void)
Disable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IXC (void)
Disable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IOC (void)
Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_DZC (void)
Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_UFC (void)
Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_OFC (void)
Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IDC (void)
Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IXC (void)
Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
__STATIC_INLINE void | LL_SYSCFG_EnableSRAM2Erase (void)
Enable SRAM2 Erase (starts a hardware SRAM2 erase operation.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsSRAM2EraseOngoing (void)
Check if SRAM2 erase operation is on going.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIM1/8/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIM1/8/15/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SP (void)
Check if SRAM2 parity error detected.
__STATIC_INLINE void | LL_SYSCFG_ClearFlag_SP (void)
Clear SRAM2 parity error flag.
__STATIC_INLINE void | LL_SYSCFG_EnableSRAM2PageWRP (uint32_t SRAM2WRP)
Enable SRAM2 page write protection.
__STATIC_INLINE void | LL_SYSCFG_LockSRAM2WRP (void)
SRAM2 page write protection lock prior to erase.
__STATIC_INLINE void | LL_SYSCFG_UnlockSRAM2WRP (void)
SRAM2 page write protection unlock prior to erase.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_SetTracePinAssignment (uint32_t PinAssignment)
Set Trace pin assignment control.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetTracePinAssignment (void)
Get Trace pin assignment control.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.
__STATIC_INLINE void | LL_VREFBUF_Enable (void)
Enable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_Disable (void)
Disable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_EnableHIZ (void)
Enable high impedance (VREF+pin is high impedance)
__STATIC_INLINE void | LL_VREFBUF_DisableHIZ (void)
Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
__STATIC_INLINE void | LL_VREFBUF_SetVoltageScaling (uint32_t Scale)
Set the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetVoltageScaling (void)
Get the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_IsVREFReady (void)
Check if Voltage reference buffer is ready.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetTrimming (void)
Get the trimming code for VREFBUF calibration.
__STATIC_INLINE void | LL_VREFBUF_SetTrimming (uint32_t Value)
Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.
__STATIC_INLINE void | LL_FLASH_EnableInstCache (void)
Enable Instruction cache.
__STATIC_INLINE void | LL_FLASH_DisableInstCache (void)
Disable Instruction cache.
__STATIC_INLINE void | LL_FLASH_EnableDataCache (void)
Enable Data cache.
__STATIC_INLINE void | LL_FLASH_DisableDataCache (void)
Disable Data cache.
__STATIC_INLINE void | LL_FLASH_EnableInstCacheReset (void)
Enable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_DisableInstCacheReset (void)
Disable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_EnableDataCacheReset (void)
Enable Data cache reset.
__STATIC_INLINE void | LL_FLASH_DisableDataCacheReset (void)
Disable Data cache reset.
__STATIC_INLINE void | LL_FLASH_EnableRunPowerDown (void)
Enable Flash Power-down mode during run mode or Low-power run mode.
__STATIC_INLINE void | LL_FLASH_DisableRunPowerDown (void)
Disable Flash Power-down mode during run mode or Low-power run mode.
__STATIC_INLINE void | LL_FLASH_EnableSleepPowerDown (void)
Enable Flash Power-down mode during Sleep or Low-power sleep mode.
__STATIC_INLINE void | LL_FLASH_DisableSleepPowerDown (void)
Disable Flash Power-down mode during Sleep or Low-power sleep mode.

Detailed Description

Header file of SYSTEM LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL SYSTEM driver contains a set of generic APIs that can be
    used by user:
      (+) Some of the FLASH features need to be handled in the SYSTEM file.
      (+) Access to DBGCMU registers
      (+) Access to SYSCFG registers
      (+) Access to VREFBUF registers
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_system.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_tim.h File Reference

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Data Structures | Defines | Functions | Variables
stm32l4xx_ll_tim.h File Reference

Header file of TIM LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...

Defines

#define | TIM_POSITION_ICPSC POSITION_VAL(TIM_CCMR1_IC1PSC)
#define | TIMx_OR2_BKINE TIM1_OR2_BKINE
#define | TIMx_OR2_BKCOMP1E TIM1_OR2_BKCMP1E
#define | TIMx_OR2_BKCOMP2E TIM1_OR2_BKCMP2E
#define | TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E
#define | TIMx_OR2_BKINP TIM1_OR2_BKINP
#define | TIMx_OR2_BKCOMP1P TIM1_OR2_BKCMP1P
#define | TIMx_OR2_BKCOMP2P TIM1_OR2_BKCMP2P
#define | TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL
#define | TIMx_OR3_BK2INE TIM1_OR3_BK2INE
#define | TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E
#define | TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E
#define | TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E
#define | TIMx_OR3_BK2INP TIM1_OR3_BK2INP
#define | TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P
#define | TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P
#define | TIMx_OR1_RMP_SHIFT ((uint32_t)16U)
#define | TIMx_OR1_RMP_MASK ((uint32_t)0x0000FFFFU)
#define | TIM1_OR1_RMP_MASK ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | TIM2_OR1_RMP_MASK ((uint32_t)((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | TIM3_OR1_RMP_MASK ((uint32_t)(TIM3_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
#define | TIM8_OR1_RMP_MASK ((uint32_t)((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | TIM15_OR1_RMP_MASK ((uint32_t)((TIM15_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | TIM16_OR1_RMP_MASK ((uint32_t)((TIM16_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | TIM17_OR1_RMP_MASK ((uint32_t)((TIM17_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
#define | DT_DELAY_1 ((uint8_t)0x7FU)
#define | DT_DELAY_2 ((uint8_t)0x3FU)
#define | DT_DELAY_3 ((uint8_t)0x1FU)
#define | DT_DELAY_4 ((uint8_t)0x1FU)
#define | DT_RANGE_1 ((uint8_t)0x00U)
#define | DT_RANGE_2 ((uint8_t)0x80U)
#define | DT_RANGE_3 ((uint8_t)0xC0U)
#define | DT_RANGE_4 ((uint8_t)0xE0U)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).
#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_CC5IF TIM_SR_CC5IF
#define | LL_TIM_SR_CC6IF TIM_SR_CC6IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_SR_SBIF TIM_SR_SBIF
#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE
#define | LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U)
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS
#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U)
#define | LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U)
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS
#define | LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000U)
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR
#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY ((uint32_t)0x00000000U)
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS
#define | LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000U)
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
#define | LL_TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U)
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E
#define | LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E
#define | LL_TIM_OCSTATE_DISABLE ((uint32_t)0x00000000U)
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E
#define | LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000U)
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3
#define | LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
#define | LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U)
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | LL_TIM_OCIDLESTATE_LOW ((uint32_t)0x00000000U)
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1
#define | LL_TIM_GROUPCH5_NONE (uint32_t)0x00000000U
#define | LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3
#define | LL_TIM_ACTIVEINPUT_DIRECTTI (uint32_t)(TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (uint32_t)(TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (uint32_t)(TIM_CCMR1_CC1S << 16U)
#define | LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_ICPSC_DIV2 (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (uint32_t)(TIM_CCMR1_IC1PSC << 16U)
#define | LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_IC_FILTER_FDIV1_N2 (uint32_t)(TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (uint32_t)(TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (uint32_t)(TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (uint32_t)(TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (uint32_t)(TIM_CCMR1_IC1F << 16U)
#define | LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000U)
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 )
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE
#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_TRGO_RESET ((uint32_t)0x00000000U)
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO2_RESET ((uint32_t)0x00000000U)
#define | LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2
#define | LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3
#define | LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000U)
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | LL_TIM_TS_ITR0 ((uint32_t)0x00000000U)
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF TIM_SMCR_TS
#define | LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000U)
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP
#define | LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS
#define | LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 )
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 )
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 )
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF
#define | LL_TIM_ETRSOURCE_LEGACY ((uint32_t)(0x00000000U))
#define | LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0
#define | LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1
#define | LL_TIM_BREAK_POLARITY_LOW ((uint32_t)0x00000000U)
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP
#define | LL_TIM_BREAK_FILTER_FDIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_BREAK_FILTER_FDIV1_N2 ((uint32_t)0x00010000U)
#define | LL_TIM_BREAK_FILTER_FDIV1_N4 ((uint32_t)0x00020000U)
#define | LL_TIM_BREAK_FILTER_FDIV1_N8 ((uint32_t)0x00030000U)
#define | LL_TIM_BREAK_FILTER_FDIV2_N6 ((uint32_t)0x00040000U)
#define | LL_TIM_BREAK_FILTER_FDIV2_N8 ((uint32_t)0x00050000U)
#define | LL_TIM_BREAK_FILTER_FDIV4_N6 ((uint32_t)0x00060000U)
#define | LL_TIM_BREAK_FILTER_FDIV4_N8 ((uint32_t)0x00070000U)
#define | LL_TIM_BREAK_FILTER_FDIV8_N6 ((uint32_t)0x00080000U)
#define | LL_TIM_BREAK_FILTER_FDIV8_N8 ((uint32_t)0x00090000U)
#define | LL_TIM_BREAK_FILTER_FDIV16_N5 ((uint32_t)0x000A0000U)
#define | LL_TIM_BREAK_FILTER_FDIV16_N6 ((uint32_t)0x000B0000U)
#define | LL_TIM_BREAK_FILTER_FDIV16_N8 ((uint32_t)0x000C0000U)
#define | LL_TIM_BREAK_FILTER_FDIV32_N5 ((uint32_t)0x000D0000U)
#define | LL_TIM_BREAK_FILTER_FDIV32_N6 ((uint32_t)0x000E0000U)
#define | LL_TIM_BREAK_FILTER_FDIV32_N8 ((uint32_t)0x000F0000U)
#define | LL_TIM_BREAK2_POLARITY_LOW ((uint32_t)0x00000000U)
#define | LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P
#define | LL_TIM_BREAK2_FILTER_FDIV1 ((uint32_t)0x00000000U)
#define | LL_TIM_BREAK2_FILTER_FDIV1_N2 ((uint32_t)0x00100000U)
#define | LL_TIM_BREAK2_FILTER_FDIV1_N4 ((uint32_t)0x00200000U)
#define | LL_TIM_BREAK2_FILTER_FDIV1_N8 ((uint32_t)0x00300000U)
#define | LL_TIM_BREAK2_FILTER_FDIV2_N6 ((uint32_t)0x00400000U)
#define | LL_TIM_BREAK2_FILTER_FDIV2_N8 ((uint32_t)0x00500000U)
#define | LL_TIM_BREAK2_FILTER_FDIV4_N6 ((uint32_t)0x00600000U)
#define | LL_TIM_BREAK2_FILTER_FDIV4_N8 ((uint32_t)0x00700000U)
#define | LL_TIM_BREAK2_FILTER_FDIV8_N6 ((uint32_t)0x00800000U)
#define | LL_TIM_BREAK2_FILTER_FDIV8_N8 ((uint32_t)0x00900000U)
#define | LL_TIM_BREAK2_FILTER_FDIV16_N5 ((uint32_t)0x00A00000U)
#define | LL_TIM_BREAK2_FILTER_FDIV16_N6 ((uint32_t)0x00B00000U)
#define | LL_TIM_BREAK2_FILTER_FDIV16_N8 ((uint32_t)0x00C00000U)
#define | LL_TIM_BREAK2_FILTER_FDIV32_N5 ((uint32_t)0x00D00000U)
#define | LL_TIM_BREAK2_FILTER_FDIV32_N6 ((uint32_t)0x00E00000U)
#define | LL_TIM_BREAK2_FILTER_FDIV32_N8 ((uint32_t)0x00F00000U)
#define | LL_TIM_OSSI_DISABLE ((uint32_t)0x00000000U)
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | LL_TIM_OSSR_DISABLE ((uint32_t)0x00000000U)
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | LL_TIM_BREAK_INPUT_BKIN ((uint32_t)0x00000000U)
#define | LL_TIM_BREAK_INPUT_BKIN2 ((uint32_t)0x00000004U)
#define | LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE
#define | LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E
#define | LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E
#define | LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E
#define | LL_TIM_BKIN_POLARITY_LOW ((uint32_t)0x00000000U)
#define | LL_TIM_BKIN_POLARITY_HIGH TIM1_OR2_BKINP
#define | LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000U) /*!< TIMx_CR1 register is the DMA base address for DMA burst */
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000U)
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_NC ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC3_RMP_NC ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK)
#define | LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_ETR_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK)
#define | LL_TIM_TIM3_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM3_OR1_RMP_MASK)
#define | LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK)
#define | LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK)
#define | LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC2_RMP_NC ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC3_RMP_NC ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK)
#define | LL_TIM_TIM15_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM15_OR1_RMP_MASK)
#define | LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK)
#define | LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION ((uint32_t)0x00000000U | TIM15_OR1_RMP_MASK)
#define | LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK)
#define | LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK)
#define | LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM16_OR1_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM17_OR1_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK)
#define | LL_TIM_OCREF_CLR_INT_NC ((uint32_t)0x00000000U )
#define | LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS
#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in TIM register.
#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> POSITION_VAL(TIM_CNT_UIFCPY))
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_POSITION_ICPSC)))
HELPER macro retrieving the ratio of the input capture prescaler.

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_EnableUIFRemap (TIM_TypeDef *TIMx)
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
__STATIC_INLINE void | LL_TIM_DisableUIFRemap (TIM_TypeDef *TIMx)
Disable update interrupt flag (UIF) remapping.
__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.
__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH5 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 5 (TIMx_CCR5).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH6 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 6 (TIMx_CCR6).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH5 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR5) set for output channel 5.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH6 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR6) set for output channel 6.
__STATIC_INLINE void | LL_TIM_SetCH5CombinedChannels (TIM_TypeDef *TIMx, uint32_t GroupCH5)
Select on which reference signal the OC5REF is combined to.
__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx)
Get captured value for input channel 4.
__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.
__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetTriggerOutput2 (TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
Set the trigger output 2 (TRGO2) used for ADC synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_SetETRSource (TIM_TypeDef *TIMx, uint32_t ETRSource)
Select the external trigger (ETR) input source.
__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
Configure the break input.
__STATIC_INLINE void | LL_TIM_EnableBRK2 (TIM_TypeDef *TIMx)
Enable the break 2 function.
__STATIC_INLINE void | LL_TIM_DisableBRK2 (TIM_TypeDef *TIMx)
Disable the break 2 function.
__STATIC_INLINE void | LL_TIM_ConfigBRK2 (TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
Configure the break 2 input.
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_EnableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Enable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_DisableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Disable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_SetBreakInputSourcePolarity (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
Set the polarity of the break signal for the timer break input.
__STATIC_INLINE void | LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.
__STATIC_INLINE void | LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).
__STATIC_INLINE void | LL_TIM_SetOCRefClearInputSource (TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
Set the OCREF clear source.
__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC5 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 5 interrupt flag (CC5F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC5 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC6 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 6 interrupt flag (CC6F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC6 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK2 (TIM_TypeDef *TIMx)
Clear the break 2 interrupt flag (B2IF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK2 (TIM_TypeDef *TIMx)
Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_SYSBRK (TIM_TypeDef *TIMx)
Clear the system break interrupt flag (SBIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_SYSBRK (TIM_TypeDef *TIMx)
Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.
__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK2 (TIM_TypeDef *TIMx)
Generate break 2 event.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Detailed Description

Header file of TIM LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_tim.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_usart.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_ll_usart.h File Reference

Header file of USART LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...

Defines

#define | USART_POSITION_CR1_DEDT (uint32_t)POSITION_VAL(USART_CR1_DEDT)
#define | USART_POSITION_CR1_DEAT (uint32_t)POSITION_VAL(USART_CR1_DEAT)
#define | USART_POSITION_CR2_ADD (uint32_t)POSITION_VAL(USART_CR2_ADD)
#define | USART_POSITION_CR3_SCARCNT (uint32_t)POSITION_VAL(USART_CR3_SCARCNT)
#define | USART_POSITION_RTOR_BLEN (uint32_t)POSITION_VAL(USART_RTOR_BLEN)
#define | USART_POSITION_GTPR_GT (uint32_t)POSITION_VAL(USART_GTPR_GT)
#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NCF USART_ICR_NCF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF
#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE USART_ISR_RXNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE USART_ISR_TXE
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK
#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE USART_CR1_RXNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE USART_CR1_TXEIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_USART_DIRECTION_NONE (uint32_t)0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_USART_PARITY_NONE (uint32_t)0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_USART_WAKEUP_IDLELINE (uint32_t)0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_USART_DATAWIDTH_7B USART_CR1_M1
#define | LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M0
#define | LL_USART_OVERSAMPLING_16 (uint32_t)0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8
#define | LL_USART_CLOCK_DISABLE (uint32_t)0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | LL_USART_LASTCLKPULSE_NO_OUTPUT (uint32_t)0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL
#define | LL_USART_PHASE_1EDGE (uint32_t)0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA
#define | LL_USART_POLARITY_LOW (uint32_t)0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL
#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 (uint32_t)0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_USART_TXRX_STANDARD (uint32_t)0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_USART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_USART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_USART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_USART_BITORDER_LSBFIRST (uint32_t)0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT (uint32_t)0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)
#define | LL_USART_ADDRESS_DETECT_4B (uint32_t)0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_USART_HWCONTROL_NONE (uint32_t)0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_USART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_USART_IRDA_POWER_NORMAL (uint32_t)0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP
#define | LL_USART_LINBREAK_DETECT_10B (uint32_t)0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL
#define | LL_USART_DE_POLARITY_HIGH (uint32_t)0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_USART_DMA_REG_DATA_TRANSMIT (uint32_t)0U
#define | LL_USART_DMA_REG_DATA_RECEIVE (uint32_t)1U
#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.
#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (USART_TypeDef *USARTx)
Get Block Length value in reception.
__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.
__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (USART_TypeDef *USARTx)
Return Driver Enable Polarity.
__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE (USART_TypeDef *USARTx)
Check if the USART Read Data Register Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE (USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE (USART_TypeDef *USARTx)
Enable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE (USART_TypeDef *USARTx)
Enable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE (USART_TypeDef *USARTx)
Disable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE (USART_TypeDef *USARTx)
Disable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE (USART_TypeDef *USARTx)
Check if the USART RX Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE (USART_TypeDef *USARTx)
Check if the USART TX Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data flush.
ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Detailed Description

Header file of USART LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_usart.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_utils.h File Reference

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Data Structures | Defines | Functions
stm32l4xx_ll_utils.h File Reference

Header file of UTILS LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...

Defines

#define | LL_MAX_DELAY (uint32_t)0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.
#define | LL_UTILS_HSEBYPASS_OFF (uint32_t)0x00000000U
#define | LL_UTILS_HSEBYPASS_ON (uint32_t)0x00000001U
#define | LL_UTILS_PACKAGETYPE_LQFP64 (uint32_t)0x00000000U
#define | LL_UTILS_PACKAGETYPE_WLCSP64 (uint32_t)0x00000001U
#define | LL_UTILS_PACKAGETYPE_LQFP100 (uint32_t)0x00000002U
#define | LL_UTILS_PACKAGETYPE_BGA132 (uint32_t)0x00000003U
#define | LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (uint32_t)0x00000004U
#define | LL_UTILS_PACKAGETYPE_UFQFPN32 (uint32_t)0x00000008U
#define | LL_UTILS_PACKAGETYPE_UFQFPN48 (uint32_t)0x0000000AU
#define | LL_UTILS_PACKAGETYPE_LQFP48 (uint32_t)0x0000000BU
#define | LL_UTILS_PACKAGETYPE_WLCSP49 (uint32_t)0x0000000CU
#define | LL_UTILS_PACKAGETYPE_UFBGA64 (uint32_t)0x0000000DU
#define | LL_UTILS_PACKAGETYPE_UFBGA100 (uint32_t)0x0000000EU

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE uint32_t | LL_GetPackageType (void)
Get Package type.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_MSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with MSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

Header file of UTILS LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL UTILS driver contains a set of generic APIs that can be
    used by user:
      (+) Device electronic signature
      (+) Timing functions
      (+) PLL configuration functions
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_utils.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_wwdg.h File Reference

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Defines | Functions
stm32l4xx_ll_wwdg.h File Reference

Header file of WWDG LL module. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Defines

#define | LL_WWDG_CFR_EWI WWDG_CFR_EWI
#define | LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)
__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)
__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Detailed Description

Header file of WWDG LL module.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_wwdg.h.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal.c File Reference

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  • STM32L4xx_HAL_Driver
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Defines | Functions | Variables
stm32l4xx_hal.c File Reference

HAL module driver. This is the common part of the HAL initialization. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | __STM32L4xx_HAL_VERSION_MAIN (0x01)
STM32L4xx HAL Driver version number V1.5.1.
#define | __STM32L4xx_HAL_VERSION_SUB1 (0x05)
#define | __STM32L4xx_HAL_VERSION_SUB2 (0x01)
#define | __STM32L4xx_HAL_VERSION_RC (0x00)
#define | __STM32L4xx_HAL_VERSION
#define | VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms (to be confirmed) */
#define | SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
#define | MEMRMP_OFFSET SYSCFG_OFFSET
#define | FB_MODE_BitNumber ((uint8_t)0x8)
#define | FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
#define | SCSR_OFFSET (SYSCFG_OFFSET + 0x18)
#define | BRER_BitNumber ((uint8_t)0x0)
#define | SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4))

Functions

HAL_StatusTypeDef | HAL_Init (void)
Configure the Flash prefetch, the Instruction and Data caches, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32l4xx_hal_msp.c.
HAL_StatusTypeDef | HAL_DeInit (void)
De-initialize common part of the HAL and stop the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitialize the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provide a tick value in millisecond.
__weak void | HAL_Delay (uint32_t Delay)
Provide accurate delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Return the HAL revision.
uint32_t | HAL_GetREVID (void)
Return the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Return the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP0/STOP1/STOP2 modes.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_SYSCFG_SRAM2Erase (void)
Start a hardware SRAM2 erase operation.
void | HAL_SYSCFG_EnableMemorySwappingBank (void)
Enable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_DisableMemorySwappingBank (void)
Disable the Internal FLASH Bank Swapping.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOAnalogSwitchBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOAnalogSwitchBooster (void)
Disable the I/O analog switch voltage booster.

Variables

__IO uint32_t | uwTick

Detailed Description

HAL module driver. This is the common part of the HAL initialization.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs' categories:
         (+) Common HAL APIs
         (+) Services HAL APIs
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_adc.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_hal_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Configuration of ADC + Operation functions ++ Start, stop, get result of regular conversions of regular using 3 possible modes: polling, interruption or DMA. + Control functions ++ Analog Watchdog configuration ++ Channels configuration on regular group + State functions ++ ADC state machine management ++ Interrupts and flags management. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_CFGR_FIELDS_1
#define | ADC_CFGR2_FIELDS
#define | ADC_CFGR_WD_FIELDS
#define | ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN))
#define | ADC_ENABLE_TIMEOUT ((uint32_t) 2)
#define | ADC_DISABLE_TIMEOUT ((uint32_t) 2)
#define | ADC_STAB_DELAY_US ((uint32_t) 10)
#define | ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168)

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular and injected groups, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups when interruptions are enabled.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups and disable ADC DMA transfer.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure the selected channel to be linked to the regular group.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Configuration of ADC + Operation functions ++ Start, stop, get result of regular conversions of regular using 3 possible modes: polling, interruption or DMA. + Control functions ++ Analog Watchdog configuration ++ Channels configuration on regular group + State functions ++ ADC state machine management ++ Interrupts and flags management.

Author:
MCD Application conversion
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                    ##### ADC specific features #####
  ==============================================================================
  [..]
  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.

  (#) Interrupt generation at the end of regular conversion and in case of
      analog watchdog and overrun events.

  (#) Single and continuous conversion modes.

  (#) Scan mode for automatic conversion of channel 0 to channel 'n'.

  (#) Data alignment with in-built data coherency.

  (#) Channel-wise programmable sampling time.

  (#) External trigger (timer or EXTI) with configurable polarity for
      regular groups.

  (#) DMA request generation for transfer of regular group converted data.

  (#) Configurable delay between conversions in Dual interleaved mode.

  (#) ADC channels selectable single/differential input.

  (#) ADC offset on regular groups.

  (#) ADC supply requirements: 1.62 V to 3.6 V.

  (#) ADC input range: from Vref_ (connected to Vssa) to Vref+ (connected to
      Vdda or to an external voltage reference).

                     ##### How to use this driver #####
  ==============================================================================
    [..]

    (#) Enable the ADC interface
        As prerequisite, in HAL_ADC_MspInit(), ADC clock source must be
        configured at RCC top level.

        Two different clock sources are available:
        (++) - the ADC clock can be a specific clock source, coming from the system
        clock, the PLLSAI1 or the PLLSAI2 running up to 80MHz.
        (++) - or the ADC clock can be derived from the AHB clock of the ADC bus
       interface, divided by a programmable factor

        (++) For example, in case of PLLSAI2:
            (+++) __HAL_RCC_ADC_CLK_ENABLE();
            (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
            (+++) where
              (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
              (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLLSAI2

    (#) ADC pins configuration
         (++) Enable the clock for the ADC GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
         (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();

    (#) Configure the ADC parameters (conversion resolution, data alignment,
         continuous mode, ...) using the HAL_ADC_Init() function.

    (#) Optionally, perform an automatic ADC calibration to improve the
        conversion accuracy using function HAL_ADCEx_Calibration_Start().

    (#) Activate the ADC peripheral using one of the start functions:
        HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(),
        HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or
        HAL_ADCEx_MultiModeStart_DMA() when multimode feature is available.

   *** Channels to regular group configuration ***
     ============================================
     [..]
       (+) To configure the ADC regular group features, use
           HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
       (+) To activate the continuous mode, use the HAL_ADC_Init() function.
       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.

     *** DMA for regular configuration ***
     =============================================================
     [..]
       (+) To enable the DMA mode for regular group, use the
           HAL_ADC_Start_DMA() function.
       (+) To enable the generation of DMA requests continuously at the end of
           the last DMA transfer, resort to DMAContinuousRequests parameter of
           ADC handle initialization structure.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_adc.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_adc_ex.c File Reference

  • File List
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  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Defines | Functions
stm32l4xx_hal_adc_ex.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Calibration functions ++ Calibration start-up ++ Calibration value reading or setting + Operation functions ++ Start, stop, get result of conversions of injected groups, using 3 possible modes: polling or interruption. ++ Multimode feature when available + Control functions ++ Configure channels on injected group + State functions ++ Injected group queues management. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_JSQR_FIELDS
#define | ADC_CFGR2_INJ_FIELDS
#define | ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000)

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor from automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable ADC peripheral if no regular conversion is on going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups when interruptions are enabled, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular groups and disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_RegularMultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure the ADC injected group and the selected channel to be linked to the injected group.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Calibration functions ++ Calibration start-up ++ Calibration value reading or setting + Operation functions ++ Start, stop, get result of conversions of injected groups, using 3 possible modes: polling or interruption. ++ Multimode feature when available + Control functions ++ Configure channels on injected group + State functions ++ Injected group queues management.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                    ##### ADC specific features #####
  ==============================================================================
  [..]
  (#) Interrupt generation at the end of injected conversion and in case of
      injected queues overflow.

  (#) External trigger (timer or EXTI) with configurable polarity for
      injected groups.

  (#) Multimode Dual mode when multimode feature is available.

  (#) Configurable DMA data storage in Multimode Dual mode.

  (#) Configurable delay between conversions in Dual interleaved mode.

  (#) ADC calibration.

  (#) ADC channels selectable single/differential input.

  (#) ADC Injected sequencer&channels configuration context queue.

  (#) ADC offset on injected groups.

  (#) ADC oversampling.

                     ##### How to use this driver #####
  ==============================================================================
    [..]

     (#) Configure the ADC parameters (conversion resolution, data alignment,
         continuous mode, ...) using the HAL_ADC_Init() function.

     (#) Activate the ADC peripheral using one of the start functions:
         HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() for injected conversions
         or
         HAL_ADC_MultiModeStart_DMA() for multimode conversions when multimode
         feature is available.

     *** Channels to injected group configuration ***
     =============================================
     [..]
       (+) To configure the ADC Injected channels group features, use
           HAL_ADCEx_InjectedConfigChannel() functions.
       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue()
           function.

     *** Multimode ADCs configuration (when  multimode feature is available) ***
     ========================================================================
     [..]
       (+) Multimode feature is available and applicable to Master and
           Slave ADCs.
       (+) Refer to "Channels to regular group configuration" description to
           configure the Master and Slave regular groups.
       (+) Select the Multi mode ADC  features (dual mode
           simultaneous, interleaved, ...) and configure the DMA mode using
           HAL_ADCEx_MultiModeConfigChannel() functions.
       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue()
           function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_adc_ex.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_can.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
  • Src
Defines | Functions
stm32l4xx_hal_can.c File Reference

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | CAN_TIMEOUT_VALUE 10

Functions

static HAL_StatusTypeDef | CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receive a correct CAN frame.
static HAL_StatusTypeDef | CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiate and transmit a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initialize the CAN peripheral according to the specified parameters in the CAN_InitStruct structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configure the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
DeInitialize the CAN peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initialize the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitialize the CAN MSP.
HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiate and transmit a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiate and transmit a CAN frame message in Interrupt mode.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receive a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receive a correct CAN frame in Interrupt mode.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enter the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wake up the CAN peripheral from sleep mode (after that the CAN peripheral is in the normal mode).
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handle CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non-blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Reception complete callback in non-blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.
HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
Return the CAN handle state.
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.

Detailed Description

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Enable the CAN controller interface clock using
          __HAL_RCC_CAN1_CLK_ENABLE() for CAN1.

      (#) CAN pins configuration
        (++) Enable the clock for the CAN GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
        (++) Connect and configure the involved CAN pins using the
              following function HAL_GPIO_Init();

      (#) Initialize and configure the CAN using HAL_CAN_Init() function.

      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or
          HAL_CAN_Transmit_IT() function.

      (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function.

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the CAN peripheral transmission and wait the end of this operation
           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
           according to his end application
       (+) Start the CAN peripheral reception and wait the end of this operation
           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
           according to his end application

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
            add his own code by customization of function pointer HAL_CAN_TxCpltCallback
       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_CAN_ErrorCallback

     *** CAN HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in CAN HAL driver.

      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status

     [..]
      (@) You can refer to the CAN HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_can.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_comp.c File Reference

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  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_hal_comp.c File Reference

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode (through EXTI interrupt) + Peripheral control functions + Peripheral state functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | COMP_DELAY_STARTUP_US ((uint32_t) 80U)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)
#define | COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t) 30U)

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.

Detailed Description

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode (through EXTI interrupt) + Peripheral control functions + Peripheral state functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
================================================================================
          ##### COMP Peripheral features #####
================================================================================

  [..]
      The STM32L4xx device family integrates two analog comparators instances
      COMP1 and COMP2:
      (#) The COMP input minus (inverting input) and input plus (non inverting input)
          can be set to internal references or to GPIO pins
          (refer to GPIO list in reference manual).

      (#) The COMP output level is available using HAL_COMP_GetOutputLevel()
          and can be redirected to other peripherals: GPIO pins (in mode
          alternate functions for comparator), timers.
          (refer to GPIO list in reference manual).

      (#) Pairs of comparators instances can be combined in window mode
          (2 consecutive instances odd and even COMP<x> and COMP<x+1>).

      (#) The comparators have interrupt capability through the EXTI controller
          with wake-up from sleep and stop modes:
          (++) COMP1 is internally connected to EXTI Line 21
          (++) COMP2 is internally connected to EXTI Line 22

          From the corresponding IRQ handler, the right interrupt source can be retrieved
          using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().

            ##### How to use this driver #####
================================================================================
  [..]
      This driver provides functions to configure and program the comparator instances
      of STM32L4xx devices.

      To use the comparator, perform the following steps:

      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
      (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
           using HAL_GPIO_Init().
      (++) If needed, configure the GPIO connected to comparator output in alternate function mode
           using HAL_GPIO_Init().
      (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
           interrupt vector using HAL_NVIC_EnableIRQ() function.

      (#) Configure the comparator using HAL_COMP_Init() function:
      (++) Select the input minus (inverting input)
      (++) Select the input plus (non-inverting input)
      (++) Select the hysteresis
      (++) Select the blanking source
      (++) Select the output polarity
      (++) Select the power mode
      (++) Select the window mode

      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
          to enable internal control clock of the comparators.
          However, this is a legacy strategy. In future STM32 families,
          COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
          Therefore, for compatibility anticipation, it is recommended to
          implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".

      (#) Reconfiguration on-the-fly of comparator can be done by calling again
          function HAL_COMP_Init() with new input structure parameters values.

      (#) Enable the comparator using HAL_COMP_Start() function.

      (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
          to manage comparator outputs (events and output level).

      (#) Disable the comparator using HAL_COMP_Stop() function.

      (#) De-initialize the comparator using HAL_COMP_DeInit() function.

      (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
          The only way to unlock the comparator is a device hardware reset.

Table 1. COMP inputs and output for STM32L4xx devices +---------------------------------------------------------+ | | | COMP1 | COMP2 | |----------------|----------------|-----------|-----------| | | IO1 | PC5 | PB4 | | Input plus | IO2 | PB2 | PB6 | | | IO3 (3) | PA1 | PA3 | |----------------|----------------|-----------------------| | | 1/4 VrefInt | Available | Available | | | 1/2 VrefInt | Available | Available | | | 3/4 VrefInt | Available | Available | | Input minus | VrefInt | Available | Available | | | DAC1 channel 1 | Available | Available | | | DAC1 channel 2 | Available | Available | | | IO1 | PB1 | PB3 | | | IO2 | PC4 | PB7 | | | IO3 (3) | PA0 | PA2 | | | IO4 (3) | PA4 | PA4 | | | IO5 (3) | PA5 | PA5 | +---------------------------------------------------------+ | Output | | PB0 (1) | PB5 (1) | | | | PB10 (1) | PB11 (1) | | | | TIM (2) | TIM (2) | +---------------------------------------------------------+ (1) GPIO must be set to alternate function for comparator (2) Comparators output to timers is set in timers instances. (3) Only STM32L43x/L44x

Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_comp.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cortex.c File Reference

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Functions
stm32l4xx_hal_cortex.c File Reference

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Set the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Get the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Get the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Get active interrupt (read the active register in NVIC and return the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================

    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex-M4 exceptions are managed by CMSIS functions.

    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().

     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
         The pending IRQ priority will be managed only by the sub priority.

     -@- IRQ priority order (sorted by highest to lowest priority):
        (+@) Lowest pre-emption priority
        (+@) Lowest sub priority
        (+@) Lowest hardware priority (IRQ number)

    [..]
    *** How to configure SysTick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base.

   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
       inside the stm32l4xx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF

The table below gives the allowed values of the pre-emption priority and subpriority according to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.

========================================================================================================================== NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ========================================================================================================================== NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority | | | 4 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority | | | 3 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority | | | 1 bit for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority | | | 0 bit for subpriority ==========================================================================================================================

Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_cortex.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_crc.c File Reference

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stm32l4xx_hal_crc.c File Reference

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the CRC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.
HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the CRC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..]
         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
         (+) Initialize CRC calculator
             (++) specify generating polynomial (IP default or non-default one)
             (++) specify initialization value (IP default or non-default one)
             (++) specify input data format
             (++) specify input or output data inversion mode if any
         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
             input data buffer starting with the previously computed CRC as
             initialization value
         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
             input data buffer starting with the defined initialization value
             (default or non-default) to initiate CRC calculation
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_crc.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_crc_ex.c File Reference

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stm32l4xx_hal_crc_ex.c File Reference

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
================================================================================
            ##### How to use this driver #####
================================================================================
    [..]
         (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
         (+) Configure Input or Output data inversion
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_crc_ex.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cryp.c File Reference

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Functions
stm32l4xx_hal_cryp.c File Reference

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + Processing functions using polling mode + Processing functions using interrupt mode + Processing functions using DMA mode + Peripheral State functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

static HAL_StatusTypeDef | CRYP_SetInitVector (CRYP_HandleTypeDef *hcryp)
Write the InitVector/InitCounter in IVRx registers.
static HAL_StatusTypeDef | CRYP_SetKey (CRYP_HandleTypeDef *hcryp)
Write the Key in KeyRx registers.
static HAL_StatusTypeDef | CRYP_AES_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.
HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initialize the CRYP according to the specified parameters in the CRYP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
DeInitialize the CRYP peripheral.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initialize the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitialize CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Encrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
Encrypt pPlainData in AES ECB encryption mode.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Encrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
Encrypt pPlainData in AES CBC encryption mode with key derivation.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Encrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
Encrypt pPlainData in AES CTR encryption mode.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Decrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
Decrypt pCypherData in AES ECB decryption mode with key derivation, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Decrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
Decrypt pCypherData in AES ECB decryption mode with key derivation, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Decrypt (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
Decrypt pCypherData in AES CTR decryption mode, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES ECB encryption mode using Interrupt, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CBC encryption mode using Interrupt, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CTR encryption mode using Interrupt, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES ECB decryption mode using Interrupt, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CBC decryption mode using Interrupt, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CTR decryption mode using Interrupt, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES ECB encryption mode using DMA, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CBC encryption mode using DMA, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
Encrypt pPlainData in AES CTR encryption mode using DMA, the cypher data are available in pCypherData.
HAL_StatusTypeDef | HAL_CRYP_AESECB_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES ECB decryption mode using DMA, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCBC_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CBC decryption mode using DMA, the decyphered data are available in pPlainData.
HAL_StatusTypeDef | HAL_CRYP_AESCTR_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
Decrypt pCypherData in AES CTR decryption mode using DMA, the decyphered data are available in pPlainData.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input DMA transfer complete callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output DMA transfer complete callback.
void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
Handle AES interrupt request.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Return the CRYP handle state.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP peripheral error.

Detailed Description

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + Processing functions using polling mode + Processing functions using interrupt mode + Processing functions using DMA mode + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The CRYP HAL driver can be used as follows:

      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
         (++) Enable the CRYP interface clock using __HAL_RCC_AES_CLK_ENABLE()
         (++) In case of using interrupts (e.g. HAL_CRYP_AES_IT())
             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the AES IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In AES IRQ handler, call HAL_CRYP_IRQHandler()
         (++) In case of using DMA to control data transfer (e.g. HAL_CRYPEx_AES_DMA())
             (+++) Enable the DMA2 interface clock using
                 __HAL_RCC_DMA2_CLK_ENABLE()
             (+++) Configure and enable two DMA channels one for managing data transfer from
                 memory to peripheral (input channel) and another channel for managing data
                 transfer from peripheral to memory (output channel)
             (+++) Associate the initialized DMA handle to the CRYP DMA handle
                 using __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA channels. The output channel should have higher
                 priority than the input channel.
                 Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures:
         (++) The data type: 1-bit, 8-bit, 16-bit and 32-bit
         (++) The AES operating mode (encryption, key derivation and/or decryption)
         (++) The AES chaining mode (ECB, CBC, CTR, GCM, GMAC, CMAC)
         (++) The encryption/decryption key if so required
         (++) The initialization vector or nonce if applicable (not used in ECB mode).

      (#)Three processing (encryption/decryption) functions are available:
         (++) Polling mode: encryption and decryption APIs are blocking functions
              i.e. they process the data and wait till the processing is finished
         (++) Interrupt mode: encryption and decryption APIs are not blocking functions
              i.e. they process the data under interrupt
         (++) DMA mode: encryption and decryption APIs are not blocking functions
              i.e. the data transfer is ensured by DMA

       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_cryp.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cryp_ex.c File Reference

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Defines | Functions
stm32l4xx_hal_cryp_ex.c File Reference

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | CRYP_CCF_TIMEOUTVALUE 22000
#define | CRYP_BUSY_TIMEOUTVALUE 22000
#define | CRYP_POLLING_OFF 0x0
#define | CRYP_POLLING_ON 0x1

Functions

static HAL_StatusTypeDef | CRYP_ProcessData (CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
Write/read input/output data in polling mode.
static HAL_StatusTypeDef | CRYP_ReadKey (CRYP_HandleTypeDef *hcryp, uint8_t *Output, uint32_t Timeout)
Read derivative key in polling mode when CRYP hardware block is set in key derivation operating mode (mode 2).
static void | CRYP_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
static void | CRYP_GCMCMAC_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer for GCM, GMAC or CMAC chainging modes.
static void | CRYP_GCMCMAC_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP Input Data process complete callback for GCM, GMAC or CMAC chainging modes.
static void | CRYP_GCMCMAC_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback for GCM, GMAC or CMAC chainging modes.
static void | CRYP_GCMCMAC_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP Output Data process complete callback for GCM, GMAC or CMAC chainging modes.
static HAL_StatusTypeDef | CRYP_WaitOnCCFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
static HAL_StatusTypeDef | CRYP_WaitOnBusyFlagReset (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Wait for Busy Flag to be reset during a GCM payload encryption process suspension.
static void | CRYP_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP Input Data process complete callback.
static void | CRYP_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP Output Data process complete callback.
static void | CRYP_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
static void | CRYP_Padding (CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling)
Last header or payload block padding when size is not a multiple of 128 bits.
__weak void | HAL_CRYPEx_ComputationCpltCallback (CRYP_HandleTypeDef *hcryp)
Computation completed callbacks.
HAL_StatusTypeDef | HAL_CRYPEx_AES (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout)
Carry out in polling mode the ciphering or deciphering operation according to hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and chaining modes ECB, CBC and CTR are managed by this function in polling mode.
HAL_StatusTypeDef | HAL_CRYPEx_AES_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
Carry out in interrupt mode the ciphering or deciphering operation according to hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and chaining modes ECB, CBC and CTR are managed by this function in interrupt mode.
HAL_StatusTypeDef | HAL_CRYPEx_AES_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
Carry out in DMA mode the ciphering or deciphering operation according to hcryp->Init structure fields.
HAL_StatusTypeDef | HAL_CRYPEx_AES_Auth (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout)
Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.
HAL_StatusTypeDef | HAL_CRYPEx_AES_Auth_IT (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.
HAL_StatusTypeDef | HAL_CRYPEx_AES_Auth_DMA (CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering operation according to hcryp->Init structure fields.
void | HAL_CRYPEx_Read_IVRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Output)
In case of message processing suspension, read the Initialization Vector.
void | HAL_CRYPEx_Write_IVRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Input)
In case of message processing resumption, rewrite the Initialization Vector in the AES_IVRx registers.
void | HAL_CRYPEx_Read_SuspendRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Output)
In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers.
void | HAL_CRYPEx_Write_SuspendRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Input)
In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend Registers in the AES_SUSPxR registers.
void | HAL_CRYPEx_Read_KeyRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Output, uint32_t KeySize)
In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers.
void | HAL_CRYPEx_Write_KeyRegisters (CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint32_t KeySize)
In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key Registers in the AES_KEYRx registers.
void | HAL_CRYPEx_Read_ControlRegister (CRYP_HandleTypeDef *hcryp, uint8_t *Output)
In case of message GCM/GMAC or CMAC processing suspension, read the Control Register.
void | HAL_CRYPEx_Write_ControlRegister (CRYP_HandleTypeDef *hcryp, uint8_t *Input)
In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control Registers in the AES_CR register.
void | HAL_CRYPEx_ProcessSuspend (CRYP_HandleTypeDef *hcryp)
Request CRYP processing suspension when in polling or interruption mode.
HAL_StatusTypeDef | CRYP_AES_Auth_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption for GCM, GMAC or CMAC chainging modes.

Detailed Description

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_cryp_ex.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dac.c File Reference

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Defines | Functions
stm32l4xx_hal_dac.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1ms */

Functions

static void | DAC_DMAConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
static void | DAC_DMAErrorCh1 (DMA_HandleTypeDef *hdma)
DMA error callback.
static void | DAC_DMAHalfConvCpltCh1 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
HAL_StatusTypeDef | HAL_DAC_Init (DAC_HandleTypeDef *hdac)
Initialize the DAC peripheral according to the specified parameters in the DAC_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_DAC_DeInit (DAC_HandleTypeDef *hdac)
Deinitialize the DAC peripheral registers to their default reset values.
__weak void | HAL_DAC_MspInit (DAC_HandleTypeDef *hdac)
Initialize the DAC MSP.
__weak void | HAL_DAC_MspDeInit (DAC_HandleTypeDef *hdac)
DeInitialize the DAC MSP.
HAL_StatusTypeDef | HAL_DAC_Start (DAC_HandleTypeDef *hdac, uint32_t Channel)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Start_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
Enables DAC and starts conversion of channel.
HAL_StatusTypeDef | HAL_DAC_Stop_DMA (DAC_HandleTypeDef *hdac, uint32_t Channel)
Disables DAC and stop conversion of channel.
void | HAL_DAC_IRQHandler (DAC_HandleTypeDef *hdac)
Handles DAC interrupt request This function uses the interruption of DMA underrun.
HAL_StatusTypeDef | HAL_DAC_SetValue (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
Set the specified data holding register value for DAC channel.
__weak void | HAL_DAC_ConvCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ConvHalfCpltCallbackCh1 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel1.
__weak void | HAL_DAC_ErrorCallbackCh1 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel1.
__weak void | HAL_DAC_DMAUnderrunCallbackCh1 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for channel1.
uint32_t | HAL_DAC_GetValue (DAC_HandleTypeDef *hdac, uint32_t Channel)
Returns the last data output value of the selected DAC channel.
HAL_StatusTypeDef | HAL_DAC_ConfigChannel (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Configures the selected DAC channel.
HAL_DAC_StateTypeDef | HAL_DAC_GetState (DAC_HandleTypeDef *hdac)
return the DAC handle state
uint32_t | HAL_DAC_GetError (DAC_HandleTypeDef *hdac)
Return the DAC error code.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                      ##### DAC Peripheral features #####
  ==============================================================================
    [..]
      *** DAC Channels ***
      ====================
    [..]
    STM32L4 devices integrate two 12-bit Digital Analog Converters

    The 2 converters (i.e. channel1 & channel2)
    can be used independently or simultaneously (dual mode):
      (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
          peripherals (ex. OPAMPs, comparators).
      (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
          peripherals (ex. OPAMPs, comparators).

      *** DAC Triggers ***
      ====================
    [..]
    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
    [..]
    Digital to Analog conversion can be triggered by:
      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
          The used pin (GPIOx_PIN_9) must be configured in input mode.

      (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7
          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)

      (#) Software using DAC_TRIGGER_SOFTWARE

      *** DAC Buffer mode feature ***
      ===============================
      [..]
      Each DAC channel integrates an output buffer that can be used to
      reduce the output impedance, and to drive external loads directly
      without having to add an external operational amplifier.
      To enable, the output buffer use
      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
      [..]
      (@) Refer to the device datasheet for more details about output
          impedance value with and without output buffer.

      *** DAC connect feature ***
      ===============================
      [..]
      Each DAC channel can be connected internally.
      To connect, use
      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;

      *** GPIO configurations guidelines ***
      =====================
      [..]
      When a DAC channel is used (ex channel1 on PA4) and the other is not
      (ex channel2 on PA5 is configured in Analog and disabled).
      Channel1 may disturb channel2 as coupling effect.
      Note that there is no coupling on channel2 as soon as channel2 is turned on.
      Coupling on adjacent channel could be avoided as follows:
      when unused PA5 is configured as INPUT PULL-UP or DOWN.
      PA5 is configured in ANALOG just before it is turned on.

      *** DAC Sample and Hold feature ***
      ========================
      [..]
      For each converter, 2 modes are supported: normal mode and
      "sample and hold" mode (i.e. low power mode).
      In the sample and hold mode, the DAC core converts data, then holds the
      converted voltage on a capacitor. When not converting, the DAC cores and
      buffer are completely turned off between samples and the DAC output is
      tri-stated, therefore  reducing the overall power consumption. A new
      stabilization period is needed before each new conversion.

      The sample and hold allow setting internal or external voltage @
      low power consumption cost (output value can be at any given rate either
      by CPU or DMA).

      The Sample and hold block and registers uses either LSI & run in
      several power modes: run mode, sleep mode, low power run, low power sleep
      mode & stop1 mode.

      Low power stop1 mode allows only static conversion.

      To enable Sample and Hold mode
      Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
      RCC_LSI_ON parameters.

      Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
         & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
           DAC_HoldTime & DAC_RefreshTime;

       *** DAC calibration feature ***
       ===================================
      [..]
       (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
       (++) Calibration aims at correcting some offset of output buffer.
       (++) The DAC uses either factory calibration settings OR user defined
           calibration (trimming) settings (i.e. trimming mode).
       (++) The user defined settings can be figured out using self calibration
           handled by HAL_DACEx_SelfCalibrate.
       (++) HAL_DACEx_SelfCalibrate:
       (+++) Runs automatically the calibration.
       (+++) Enables the user trimming mode
       (+++) Updates a structure with trimming values with fresh calibration
            results.
            The user may store the calibration results for larger
            (ex monitoring the trimming as a function of temperature
            for instance)

       *** DAC wave generation feature ***
       ===================================
       [..]
       Both DAC channels can be used to generate
         (#) Noise wave
         (#) Triangle wave

       *** DAC data format ***
       =======================
       [..]
       The DAC data format can be:
         (#) 8-bit right alignment using DAC_ALIGN_8B_R
         (#) 12-bit left alignment using DAC_ALIGN_12B_L
         (#) 12-bit right alignment using DAC_ALIGN_12B_R

       *** DAC data value to voltage correspondence ***
       ================================================
       [..]
       The analog output voltage on each DAC channel pin is determined
       by the following equation:
       [..]
       DAC_OUTx = VREF+ * DOR / 4095
       (+) with  DOR is the Data Output Register
       [..]
          VEF+ is the input voltage reference (refer to the device datasheet)
       [..]
        e.g. To set DAC_OUT1 to 0.7V, use
       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V

       *** DMA requests ***
       =====================
       [..]
       A DMA1 request can be generated when an external trigger (but not a software trigger)
       occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
       DMA requests are mapped as following:
      (#) DAC channel1: mapped either on
      (++) DMA1 request 6 channel3
      (++) or DMA2 request channel4 which must be already configured
      (#) DAC channel2: mapped either on
      (++) DMA1 request 5 channel4
      (++) or DMA2 request 3 channel5 which must be already configured
     [..]
    (@) For Dual mode and specific signal (Triangle and noise) generation please
        refer to Extended Features Driver description

                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) DAC APB clock must be enabled to get write access to DAC
          registers using HAL_DAC_Init()
      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.

     *** Calibration mode IO operation ***
     ======================================
     [..]
       (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
       (+) Run the calibration using HAL_DACEx_SelfCalibrate()
       (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start()
       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
       (+) Stop the DAC peripheral using HAL_DAC_Stop()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()

     *** DAC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DAC HAL driver.

      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status

     [..]
      (@) You can refer to the DAC HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_dac.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dac_ex.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Functions
stm32l4xx_hal_dac_ex.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_DACEx_TriangleWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_NoiseWaveGenerate (DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
Enable or disable the selected DAC channel wave generation.
HAL_StatusTypeDef | HAL_DACEx_DualSetValue (DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
Set the specified data holding register value for dual DAC channel.
__weak void | HAL_DACEx_ConvCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion complete callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ConvHalfCpltCallbackCh2 (DAC_HandleTypeDef *hdac)
Conversion half DMA transfer callback in non-blocking mode for Channel2.
__weak void | HAL_DACEx_ErrorCallbackCh2 (DAC_HandleTypeDef *hdac)
Error DAC callback for Channel2.
__weak void | HAL_DACEx_DMAUnderrunCallbackCh2 (DAC_HandleTypeDef *hdac)
DMA underrun DAC callback for Channel2.
HAL_StatusTypeDef | HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
Run the self calibration of one DAC channel.
HAL_StatusTypeDef | HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
Set the trimming mode and trimming value (user trimming mode applied).
uint32_t | HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
Return the DAC trimming value.
uint32_t | HAL_DACEx_DualGetValue (DAC_HandleTypeDef *hdac)
Return the last data output value of the selected DAC channel.
void | DAC_DMAConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA conversion complete callback.
void | DAC_DMAHalfConvCpltCh2 (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | DAC_DMAErrorCh2 (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.

      (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
      (+) HAL_DACEx_SetUserTrimming to set user trimming value.
      (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
          after reset, user setting if HAL_DACEx_SetUserTrimming have been used
          at least one time after reset).
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_dac_ex.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dfsdm.c File Reference

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Defines | Functions | Variables
stm32l4xx_hal_dfsdm.c File Reference

This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
#define | DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
#define | DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
#define | DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
#define | DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
#define | DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)
#define | DFSDM_FLTCR1_MSB_RCH_OFFSET 8
#define | DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)
#define | DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)
#define | DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)
#define | DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)
#define | DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
#define | DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)
#define | DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
#define | DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
#define | DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
#define | DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
#define | DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
#define | DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
#define | DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
#define | DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
#define | DFSDM_MSB_MASK 0xFFFF0000U
#define | DFSDM_LSB_MASK 0x0000FFFFU
#define | DFSDM_CKAB_TIMEOUT 5000U
#define | DFSDM1_CHANNEL_NUMBER 8U

Functions

static uint32_t | DFSDM_GetInjChannelsNbr (uint32_t Channels)
This function allows to get the number of injected channels.
static uint32_t | DFSDM_GetChannelFromInstance (DFSDM_Channel_TypeDef *Instance)
This function allows to get the channel number from channel instance.
static void | DFSDM_RegConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start regular conversion.
static void | DFSDM_RegConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop regular conversion.
static void | DFSDM_InjConvStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really start injected conversion.
static void | DFSDM_InjConvStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to really stop injected conversion.
static void | DFSDM_DMARegularHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for regular conversion.
static void | DFSDM_DMARegularConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for regular conversion.
static void | DFSDM_DMAInjectedHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback for injected conversion.
static void | DFSDM_DMAInjectedConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback for injected conversion.
static void | DFSDM_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_ChannelDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
__weak void | HAL_DFSDM_ChannelMspInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
__weak void | HAL_DFSDM_ChannelMspDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForCkab (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelCkabCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelCkabStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelPollForScd (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
__weak void | HAL_DFSDM_ChannelScdCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
HAL_StatusTypeDef | HAL_DFSDM_ChannelScdStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
int16_t | HAL_DFSDM_ChannelGetAwdValue (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
HAL_StatusTypeDef | HAL_DFSDM_ChannelModifyOffset (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.
HAL_DFSDM_Channel_StateTypeDef | HAL_DFSDM_ChannelGetState (DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.
HAL_StatusTypeDef | HAL_DFSDM_FilterInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_DFSDM_FilterDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
__weak void | HAL_DFSDM_FilterMspInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
__weak void | HAL_DFSDM_FilterMspDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigRegChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterConfigInjChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForRegConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterRegularStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetRegularValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterPollForInjConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant bits of conversion.
HAL_StatusTypeDef | HAL_DFSDM_FilterInjectedStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
int32_t | HAL_DFSDM_FilterGetInjectedValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterAwdStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
HAL_StatusTypeDef | HAL_DFSDM_FilterExdStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
int32_t | HAL_DFSDM_FilterGetExdMaxValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
int32_t | HAL_DFSDM_FilterGetExdMinValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
uint32_t | HAL_DFSDM_FilterGetConvTimeValue (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
void | HAL_DFSDM_IRQHandler (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
__weak void | HAL_DFSDM_FilterRegConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
__weak void | HAL_DFSDM_FilterRegConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
__weak void | HAL_DFSDM_FilterInjConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
__weak void | HAL_DFSDM_FilterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
__weak void | HAL_DFSDM_FilterErrorCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.
HAL_DFSDM_Filter_StateTypeDef | HAL_DFSDM_FilterGetState (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
uint32_t | HAL_DFSDM_FilterGetError (DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.

Variables

__IO uint32_t | v_dfsdm1ChannelCounter = 0
DFSDM_Channel_HandleTypeDef * | a_dfsdm1ChannelHandle [DFSDM1_CHANNEL_NUMBER] = {NULL}

Detailed Description

This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
    *** Channel initialization ***
    ==============================
    [..]
      (#) User has first to initialize channels (before filters initialization).
      (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
        (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
        (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
        (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the output clock, input, serial interface, analog watchdog,
          offset and data right bit shift parameters for this channel using the
          HAL_DFSDM_ChannelInit() function.

    *** Channel clock absence detector ***
    ======================================
    [..]
      (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
          HAL_DFSDM_ChannelCkabStart_IT().
      (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
          absence.
      (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
          clock absence is detected.
      (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
          HAL_DFSDM_ChannelCkabStop_IT().
      (#) Please note that the same mode (polling or interrupt) has to be used
          for all channels because the channels are sharing the same interrupt.
      (#) Please note also that in interrupt mode, if clock absence detector is
          stopped for one channel, interrupt will be disabled for all channels.

    *** Channel short circuit detector ***
    ======================================
    [..]
      (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
          or HAL_DFSDM_ChannelScdStart_IT().
      (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
          circuit.
      (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
          short circuit is detected.
      (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
          or HAL_DFSDM_ChannelScdStop_IT().
      (#) Please note that the same mode (polling or interrupt) has to be used
          for all channels because the channels are sharing the same interrupt.
      (#) Please note also that in interrupt mode, if short circuit detector is
          stopped for one channel, interrupt will be disabled for all channels.

    *** Channel analog watchdog value ***
    =====================================
    [..]
      (#) Get analog watchdog filter value of a channel using
          HAL_DFSDM_ChannelGetAwdValue().

    *** Channel offset value ***
    =====================================
    [..]
      (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().

    *** Filter initialization ***
    =============================
    [..]
      (#) After channel initialization, user has to init filters.
      (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
        (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
            Please note that DFSDMz_FLT0 global interrupt could be already
            enabled if interrupt is used for channel.
        (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
            with DFSDMz filter handle using __HAL_LINKDMA().
      (#) Configure the regular conversion, injected conversion and filter
          parameters for this filter using the HAL_DFSDM_FilterInit() function.

    *** Filter regular channel conversion ***
    =========================================
    [..]
      (#) Select regular channel and enable/disable continuous mode using
          HAL_DFSDM_FilterConfigRegChannel().
      (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
          HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
          HAL_DFSDM_FilterRegularMsbStart_DMA().
      (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
          the end of regular conversion.
      (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
          at the end of regular conversion.
      (#) Get value of regular conversion and corresponding channel using
          HAL_DFSDM_FilterGetRegularValue().
      (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
          HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
          half transfer and at the transfer complete. Please note that
          HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
          circular mode.
      (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
          HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().

    *** Filter injected channels conversion ***
    ===========================================
    [..]
      (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
      (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
          HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
          HAL_DFSDM_FilterInjectedMsbStart_DMA().
      (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
          the end of injected conversion.
      (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
          at the end of injected conversion.
      (#) Get value of injected conversion and corresponding channel using
          HAL_DFSDM_FilterGetInjectedValue().
      (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
          HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
          half transfer and at the transfer complete. Please note that
          HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
          circular mode.
      (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
          HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().

    *** Filter analog watchdog ***
    ==============================
    [..]
      (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
      (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
      (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().

    *** Filter extreme detector ***
    ===============================
    [..]
      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
      (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
      (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().

    *** Filter conversion time ***
    ==============================
    [..]
      (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_dfsdm.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dma.c File Reference

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  • STM32L4xx_HAL_Driver
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Functions
stm32l4xx_hal_dma.c File Reference

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA hande state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Channel
       (except for internal SRAM / FLASH memories: no initialization is
       necessary). Please refer to the Reference manual for connection between peripherals
       and DMA requests.

   (#) For a given Channel, program the required configuration through the following parameters:
       Channel request, Transfer Direction, Source and Destination data formats,
       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
       using HAL_DMA_Init() function.

   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
       detection.

   (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred
          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
              case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred.
              In this case the DMA interrupt is configured
          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
              add his own function by customization of function pointer XferCpltCallback and
              XferErrorCallback (i.e. a member of DMA handle structure).

     *** DMA HAL driver macros list ***
     =============================================
      [..]
       Below the list of most used macros in DMA HAL driver.

       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_dma.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_firewall.c File Reference

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  • STM32L4xx_HAL_Driver
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Functions
stm32l4xx_hal_firewall.c File Reference

FIREWALL HAL module driver. This file provides firmware functions to manage the Firewall Peripheral initialization and enabling. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_FIREWALL_Config (FIREWALL_InitTypeDef *fw_init)
Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters.
void | HAL_FIREWALL_GetConfig (FIREWALL_InitTypeDef *fw_config)
Retrieve the Firewall configuration.
void | HAL_FIREWALL_EnableFirewall (void)
Enable FIREWALL.
void | HAL_FIREWALL_EnablePreArmFlag (void)
Enable FIREWALL pre arm.
void | HAL_FIREWALL_DisablePreArmFlag (void)
Disable FIREWALL pre arm.

Detailed Description

FIREWALL HAL module driver. This file provides firmware functions to manage the Firewall Peripheral initialization and enabling.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    The FIREWALL HAL driver can be used as follows:

    (#) Declare a FIREWALL_InitTypeDef initialization structure.

    (#) Resort to HAL_FIREWALL_Config() API to initialize the Firewall

    (#) Enable the FIREWALL in calling HAL_FIREWALL_EnableFirewall() API

    (#) To ensure that any code executed outside the protected segment closes the
        FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling
        __HAL_FIREWALL_PREARM_ENABLE() macro if called within a protected code segment
        or
        HAL_FIREWALL_EnablePreArmFlag() API if called outside of protected code segment
        after HAL_FIREWALL_Config() call.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_firewall.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash.c File Reference

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  • STM32L4xx_HAL_Driver
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Functions | Variables
stm32l4xx_hal_flash.c File Reference

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
void | FLASH_PageErase (uint32_t Page, uint32_t Banks)
Erase the specified FLASH memory page.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.
static void | FLASH_SetErrorCode (void)
Set the specific FLASH error flag.
static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program double-word (64-bit) at a specified address.
static void | FLASH_Program_Fast (uint32_t Address, uint32_t DataAddress)
Fast program a 32 row double-word (64-bit) at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Detailed Description

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================

  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The Flash memory interface accelerates code execution with a system of instruction
       prefetch and cache lines.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Read / write protections
      (+) Option bytes programming
      (+) Prefetch on I-Code
      (+) 32 cache lines of 4*64 bits on I-Code
      (+) 8 cache lines of 4*64 bits on D-Code
      (+) Error code correction (ECC) : Data in flash are 72-bits word
          (8 bits added per double word)

                        ##### How to use this driver #####
 ==============================================================================
    [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32L4xx devices.

      (#) Flash Memory IO Programming functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Program functions: double word and fast program (full row programming)
           (++) There Two modes of programming :
            (+++) Polling mode using HAL_FLASH_Program() function
            (+++) Interrupt mode using HAL_FLASH_Program_IT() function

      (#) Interrupts and flags management functions :
           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
           (++) Callback functions are called when the flash operations are finished :
                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
                HAL_FLASH_OperationErrorCallback()
           (++) Get error flag status by calling HAL_GetError()

      (#) Option bytes management functions :
           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
                HAL_FLASH_OB_Lock() functions
           (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
                In this case, a reset is generated

    [..]
      In addition to these functions, this driver includes a set of macros allowing
      to handle the following operations:
       (+) Set the latency
       (+) Enable/Disable the prefetch buffer
       (+) Enable/Disable the Instruction cache and the Data cache
       (+) Reset the Instruction cache and the Data cache
       (+) Enable/Disable the Flash power-down during low-power run and sleep modes
       (+) Enable/Disable the Flash interrupts
       (+) Monitor the Flash flags status
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_flash.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash_ex.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Functions | Variables
stm32l4xx_hal_flash_ex.c File Reference

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.
void | FLASH_PageErase (uint32_t Page, uint32_t Banks)
Erase the specified FLASH memory page.
static void | FLASH_MassErase (uint32_t Banks)
Mass erase of FLASH memory.
void | FLASH_FlushCaches (void)
Flush the instruction and data caches.
static HAL_StatusTypeDef | FLASH_OB_WRPConfig (uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
Configure the write protection of the desired pages.
static HAL_StatusTypeDef | FLASH_OB_RDPConfig (uint32_t RDPLevel)
Set the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint32_t UserType, uint32_t UserConfig)
Program the FLASH User Option Byte.
static HAL_StatusTypeDef | FLASH_OB_PCROPConfig (uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
Configure the Proprietary code readout protection of the desired addresses.
static void | FLASH_OB_GetWRP (uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
Return the FLASH Write Protection Option Bytes value.
static uint32_t | FLASH_OB_GetRDP (void)
Return the FLASH Read Protection level.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static void | FLASH_OB_GetPCROP (uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr)
Return the FLASH Write Protection Option Bytes value.
HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Detailed Description

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
 ==============================================================================
                   ##### Flash Extended features #####
  ==============================================================================

  [..] Comparing to other previous devices, the FLASH interface for STM32L4xx
       devices contains the following additional features

       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
           capability (RWW)
       (+) Dual bank memory organization
       (+) PCROP protection for all banks

                        ##### How to use this driver #####
 ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32L4xx devices. It includes
      (#) Flash Memory Erase functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Erase function: Erase page, erase all sectors
           (++) There are two modes of erase :
             (+++) Polling Mode using HAL_FLASHEx_Erase()
             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()

      (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
        (++) Set/Reset the write protection
        (++) Set the Read protection Level
        (++) Program the user Option Bytes
        (++) Configure the PCROP protection

      (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
        (++) Get the value of a write protection area
        (++) Know if the read protection is activated
        (++) Get the value of the user Option Bytes
        (++) Get the value of a PCROP area
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_flash_ex.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash_ramfunc.c File Reference

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stm32l4xx_hal_flash_ramfunc.c File Reference

FLASH RAMFUNC driver. This file provides a Flash firmware functions which should be executed from internal SRAM + FLASH HalfPage Programming + FLASH Power Down in Run mode. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

__RAM_FUNC | HAL_FLASHEx_EnableRunPowerDown (void)
Enable the Power down in Run Mode.
__RAM_FUNC | HAL_FLASHEx_DisableRunPowerDown (void)
Disable the Power down in Run Mode.

Detailed Description

FLASH RAMFUNC driver. This file provides a Flash firmware functions which should be executed from internal SRAM + FLASH HalfPage Programming + FLASH Power Down in Run mode.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                   ##### Flash RAM functions #####
  ==============================================================================

    *** ARM Compiler ***
    --------------------
    [..] RAM functions are defined using the toolchain options.
         Functions that are executed in RAM should reside in a separate
         source module. Using the 'Options for File' dialog you can simply change
         the 'Code / Const' area of a module to a memory space in physical RAM.
         Available memory areas are declared in the 'Target' tab of the
         Options for Target' dialog.

    *** ICCARM Compiler ***
    -----------------------
    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".

    *** GNU Compiler ***
    --------------------
    [..] RAM functions are defined using a specific toolchain attribute
         "__attribute__((section(".RamFunc")))".
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_flash_ramfunc.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_gpio.c File Reference

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Defines | Functions
stm32l4xx_hal_gpio.c File Reference

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | GPIO_MODE ((uint32_t)0x00000003)
#define | ANALOG_MODE ((uint32_t)0x00000008)
#define | EXTI_MODE ((uint32_t)0x10000000)
#define | GPIO_MODE_IT ((uint32_t)0x00010000)
#define | GPIO_MODE_EVT ((uint32_t)0x00020000)
#define | RISING_EDGE ((uint32_t)0x00100000)
#define | FALLING_EDGE ((uint32_t)0x00200000)
#define | GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define | GPIO_NUMBER ((uint32_t)16)

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
        configured by software in several modes:
        (++) Input mode
        (++) Analog mode
        (++) Output mode
        (++) Alternate function mode
        (++) External interrupt/event lines

    (+) During and just after reset, the alternate functions and external interrupt
        lines are not active and the I/O ports are configured in input floating mode.

    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
        activated or not.

    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
        type and the IO speed can be selected depending on the VDD value.

    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
        multiplexer that allows only one peripheral alternate function (AF) connected
       to an IO pin at a time. In this way, there can be no conflict between peripherals
       sharing the same IO pin.

    (+) All ports have external interrupt/event capability. To use external interrupt
        lines, the port must be configured in input mode. All available GPIO pins are
        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

    (+) The external interrupt/event controller consists of up to 39 edge detectors
        (16 lines are connected to GPIO) for generating event/interrupt requests (each
        input line can be independently configured to select the type (interrupt or event)
        and the corresponding trigger event (rising or falling or both). Each line can
        also be masked independently.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().

    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
             structure.
        (++) In case of Output or alternate function mode selection: the speed is
             configured through "Speed" member from GPIO_InitTypeDef structure.
        (++) In alternate mode is selection, the alternate function connected to the IO
             is configured through "Alternate" member from GPIO_InitTypeDef structure.
        (++) Analog mode is required when a pin is to be used as ADC channel
             or DAC output.
        (++) In case of external interrupt/event selection the "Mode" member from
             GPIO_InitTypeDef structure select the type (interrupt or event) and
             the corresponding trigger event (rising or falling or both).

    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
        HAL_NVIC_EnableIRQ().

    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

    (#) To set/reset the level of a pin configured in output mode use
        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

    (#) During and just after reset, the alternate functions are not
        active and the GPIO pins are configured in input floating mode (except JTAG
        pins).

    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
        priority over the GPIO function.

    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
        The HSE has priority over the GPIO function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_gpio.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_hcd.c File Reference

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Functions
stm32l4xx_hal_hcd.c File Reference

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

static void | HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel IN interrupt requests.
static void | HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Handle Host Channel OUT interrupt requests.
static void | HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Rx Queue Level interrupt requests.
static void | HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle Host Port interrupt requests.
HAL_StatusTypeDef | HAL_HCD_Init (HCD_HandleTypeDef *hhcd)
Initialize the Host driver.
HAL_StatusTypeDef | HAL_HCD_HC_Init (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
Initialize a Host channel.
HAL_StatusTypeDef | HAL_HCD_HC_Halt (HCD_HandleTypeDef *hhcd, uint8_t ch_num)
Halt a Host channel.
HAL_StatusTypeDef | HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the Host driver.
__weak void | HAL_HCD_MspInit (HCD_HandleTypeDef *hhcd)
Initialize the HCD MSP.
__weak void | HAL_HCD_MspDeInit (HCD_HandleTypeDef *hhcd)
DeInitialize the HCD MSP.
HAL_StatusTypeDef | HAL_HCD_HC_SubmitRequest (HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping)
Submit a new URB for processing.
void | HAL_HCD_IRQHandler (HCD_HandleTypeDef *hhcd)
Handle HCD interrupt request.
__weak void | HAL_HCD_SOF_Callback (HCD_HandleTypeDef *hhcd)
SOF callback.
__weak void | HAL_HCD_Connect_Callback (HCD_HandleTypeDef *hhcd)
Connection Event callback.
__weak void | HAL_HCD_Disconnect_Callback (HCD_HandleTypeDef *hhcd)
Disconnection Event callback.
__weak void | HAL_HCD_HC_NotifyURBChange_Callback (HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
Notify URB state change callback.
HAL_StatusTypeDef | HAL_HCD_Start (HCD_HandleTypeDef *hhcd)
Start the Host driver.
HAL_StatusTypeDef | HAL_HCD_Stop (HCD_HandleTypeDef *hhcd)
Stop the Host driver.
HAL_StatusTypeDef | HAL_HCD_ResetPort (HCD_HandleTypeDef *hhcd)
Reset the Host port.
HCD_StateTypeDef | HAL_HCD_GetState (HCD_HandleTypeDef *hhcd)
Return the HCD handle state.
HCD_URBStateTypeDef | HAL_HCD_HC_GetURBState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return URB state for a channel.
uint32_t | HAL_HCD_HC_GetXferCount (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the last Host transfer size.
HCD_HCStateTypeDef | HAL_HCD_HC_GetState (HCD_HandleTypeDef *hhcd, uint8_t chnum)
Return the Host Channel state.
uint32_t | HAL_HCD_GetCurrentFrame (HCD_HandleTypeDef *hhcd)
Return the current Host frame number.
uint32_t | HAL_HCD_GetCurrentSpeed (HCD_HandleTypeDef *hhcd)
Return the Host enumeration speed.

Detailed Description

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
  [..]
    (#)Declare a HCD_HandleTypeDef handle structure, for example:
       HCD_HandleTypeDef  hhcd;

    (#)Fill parameters of Init structure in HCD handle

    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)

    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
        (##) Enable the HCD/USB Low Level interface clock using the following macro
             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE()

        (##) Initialize the related GPIO clocks
        (##) Configure HCD pin-out
        (##) Configure HCD NVIC interrupt

    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
        (##) hhcd.pData = phost;

    (#)Enable HCD transmission and reception:
        (##) HAL_HCD_Start();
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_hcd.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_i2c.c File Reference

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Defines | Functions
stm32l4xx_hal_i2c.c File Reference

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~HAL_I2C_STATE_READY)))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))
#define | I2C_XFER_TX_IT (0x00000001U)
#define | I2C_XFER_RX_IT (0x00000002U)
#define | I2C_XFER_LISTEN_IT (0x00000004U)
#define | I2C_XFER_ERROR_IT (0x00000011U)
#define | I2C_XFER_CPLT_IT (0x00000012U)
#define | I2C_XFER_RELOAD_IT (0x00000012U)
#define | I2C_GET_DMA_REMAIN_DATA(__HANDLE__)

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSequentialCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles Acknowledge failed detection during an I2C Communication.
static HAL_StatusTypeDef | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx channel
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx channel

    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode IO sequential operation ***
    ===================================
    [..]
      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
    [..]
      (+) A specific option field manage the different steps of a sequential transfer
      (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition
      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and without a final stop condition in both cases
      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and with a final stop condition in both cases

      (+) Differents sequential I2C interfaces are listed below:
      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
      (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
          HAL_I2C_Mem_Write_IT()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
          HAL_I2C_Mem_Read_IT()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
          HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
          HAL_I2C_Mem_Write_DMA()
      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
          HAL_I2C_Mem_Read_DMA()
      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()

     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_i2c.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_i2c_ex.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Functions
stm32l4xx_hal_i2c_ex.c File Reference

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from stop mode.
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from stop mode.
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
               ##### I2C peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the I2C interface for STM32L4xx
       devices contains the following additional features

       (+) Possibility to disable or enable Analog Noise Filter
       (+) Use of a configured Digital Noise Filter
       (+) Disable or enable wakeup from Stop modes

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
          (++) HAL_I2CEx_EnableWakeUp()
          (++) HAL_I2CEx_DisableWakeUp()
    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
          (++) HAL_I2CEx_EnableFastModePlus()
          (++) HAL_I2CEx_DisbleFastModePlus()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_i2c_ex.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_irda.c File Reference

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  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_hal_irda.c File Reference

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000
#define | IRDA_CR1_FIELDS

Functions

static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The IRDA HAL driver can be used as follows:

    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
        in setting the associated USART or UART in IRDA mode:
        (++) Enable the USARTx/UARTx interface clock.
        (++) USARTx/UARTx pins configuration:
            (+++) Enable the clock for the USARTx/UARTx GPIOs.
            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
             and HAL_IRDA_Receive_IT() APIs):
            (+++) Configure the USARTx/UARTx interrupt priority.
            (+++) Enable the NVIC USARTx/UARTx IRQ handle.
            (+++) The specific IRDA interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
             and HAL_IRDA_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
        the normal or low power mode and the clock prescaler in the hirda handle Init structure.

    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_IRDA_MspInit() API.

         -@@- The specific IRDA interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** IRDA HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IRDA HAL driver.

       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled

     [..]
       (@) You can refer to the IRDA HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_irda.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_iwdg.c File Reference

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  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_hal_iwdg.c File Reference

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT 48u

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                    ##### IWDG Generic features #####
  ==============================================================================
  [..]
    (+) The IWDG can be started by either software or hardware (configurable
        through option byte).

    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
        if the main clock fails.

    (+) Once the IWDG is started, the LSI is forced ON and both can not be
        disabled. The counter starts counting down from the reset value (0xFFF).
        When it reaches the end of count value (0x000) a reset signal is
        generated (IWDG reset).

    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
        prevented.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
        reset occurs.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the IWDG counter either continues to work normally or stops, depending
        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros

    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
         The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx
         devices provide the capability to measure the LSI frequency (LSI clock
         connected internally to TIM16 CH1 input capture). The measured value
         can be used to have an IWDG timeout with an acceptable accuracy.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Use IWDG using HAL_IWDG_Init() function to :
      (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
           clock is forced ON and IWDG counter starts downcounting.
      (+) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
           IWDG_WINR.
      (+) Configure the IWDG prescaler and counter reload value. This reload
           value will be loaded in the IWDG counter each time the watchdog is
           reloaded, then the IWDG will start counting down from this value.
      (+) wait for status flags to be reset"
      (+) Depending on window parameter:
        (++) If Window Init parameter is same as Window register value,
             nothing more is done but reload counter value in order to exit
             function withy exact time base.
        (++) Else modify Window register. This will automatically reload
             watchdog counter.

    (#) Then the application program must refresh the IWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver:
      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
          the reload register
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_iwdg.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_lcd.c File Reference

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Defines | Functions
stm32l4xx_hal_lcd.c File Reference

LCD Controller HAL module driver. This file provides firmware functions to manage the following functionalities of the LCD Controller (LCD) peripheral: + Initialization/de-initialization methods + I/O operation methods + Peripheral State methods. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | LCD_TIMEOUT_VALUE 1000

Functions

HAL_StatusTypeDef | HAL_LCD_Init (LCD_HandleTypeDef *hlcd)
Initialize the LCD peripheral according to the specified parameters in the LCD_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_LCD_DeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD peripheral.
__weak void | HAL_LCD_MspDeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD MSP.
__weak void | HAL_LCD_MspInit (LCD_HandleTypeDef *hlcd)
Initialize the LCD MSP.
HAL_StatusTypeDef | HAL_LCD_Write (LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
Write a word in the specific LCD RAM.
HAL_StatusTypeDef | HAL_LCD_Clear (LCD_HandleTypeDef *hlcd)
Clear the LCD RAM registers.
HAL_StatusTypeDef | HAL_LCD_UpdateDisplayRequest (LCD_HandleTypeDef *hlcd)
Enable the Update Display Request.
HAL_LCD_StateTypeDef | HAL_LCD_GetState (LCD_HandleTypeDef *hlcd)
Return the LCD handle state.
uint32_t | HAL_LCD_GetError (LCD_HandleTypeDef *hlcd)
Return the LCD error code.
HAL_StatusTypeDef | LCD_WaitForSynchro (LCD_HandleTypeDef *hlcd)
Wait until the LCD FCR register is synchronized in the LCDCLK domain.

Detailed Description

LCD Controller HAL module driver. This file provides firmware functions to manage the following functionalities of the LCD Controller (LCD) peripheral: + Initialization/de-initialization methods + I/O operation methods + Peripheral State methods.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
      [..] The LCD HAL driver can be used as follows:

      (#) Declare a LCD_HandleTypeDef handle structure.

      -@- The frequency generator allows you to achieve various LCD frame rates
          starting from an LCD input clock frequency (LCDCLK) which can vary
          from 32 kHz up to 1 MHz.

      (#) Initialize the LCD low level resources by implementing the HAL_LCD_MspInit() API:

          (++) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows:
               (+++) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and
                  selected clock source (HSE, LSI or LSE)

          (++) LCD pins configuration:
              (+++) Enable the clock for the LCD GPIOs.
              (+++) Configure these LCD pins as alternate function no-pull.
          (++) Enable the LCD interface clock.

      (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias,
          Voltage Source, Dead Time, Pulse On Duration, Contrast, High drive and Multiplexer
          Segment in the Init structure of the LCD handle.

      (#) Initialize the LCD registers by calling the HAL_LCD_Init() API.

      -@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc)
          by calling the customized HAL_LCD_MspInit() API.
      -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared

      (#) Optionally you can update the LCD configuration using these macros:
              (++) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
              (++) Voltage output buffer using __HAL_LCD_VOLTAGE_BUFFER_ENABLE() and __HAL_LCD_VOLTAGE_BUFFER_DISABLE() macros
              (++) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
              (++) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro
              (++) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
              (++) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro

      (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
          more time to update the different LCD RAM registers before calling
          HAL_LCD_UpdateDisplayRequest() API.

      (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.

      (#) When LCD RAM memory is updated enable the update display request using
          the HAL_LCD_UpdateDisplayRequest() API.

      [..] LCD and low power modes:
           (#) The LCD remain active during Sleep, Low Power run, Low Power Sleep and
               STOP modes.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_lcd.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_lptim.c File Reference

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Functions
stm32l4xx_hal_lptim.c File Reference

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.

Detailed Description

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The LPTIM HAL driver can be used as follows:

      (#)Initialize the LPTIM low level resources by implementing the
        HAL_LPTIM_MspInit():
         (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
         (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().

      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
         configures mainly:
         (++) The instance: LPTIM1 or LPTIM2.
         (++) Clock: the counter clock.
             (+++) Source   : it can be either the ULPTIM input (IN1) or one of
                              the internal clock; (APB, LSE, LSI or MSI).
             (+++) Prescaler: select the clock divider.
         (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
               as counter clock source.
             (+++) Polarity:   polarity of the active edge for the counter unit
                               if the ULPTIM input is selected.
             (+++) SampleTime: clock sampling time to configure the clock glitch
                               filter.
         (++) Trigger: How the counter start.
             (+++) Source: trigger can be software or one of the hardware triggers.
             (+++) ActiveEdge : only for hardware trigger.
             (+++) SampleTime : trigger sampling time to configure the trigger
                                glitch filter.
         (++) OutputPolarity : 2 opposite polarities are possible.
         (++) UpdateMode: specifies whether the update of the autoreload and
              the compare values is done immediately or after the end of current
              period.
         (++) Input1Source: Source selected for input1 (GPIO or comparator output).
         (++) Input2Source: Source selected for input2 (GPIO or comparator output).
              Input2 is used only for encoder feature so is used only for LPTIM1 instance.

      (#)Six modes are available:

         (++) PWM Mode: To generate a PWM signal with specified period and pulse,
         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
         mode.

         (++) One Pulse Mode: To generate pulse with specified width in response
         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.

         (++) Set once Mode: In this mode, the output changes the level (from
         low level to high level if the output polarity is configured high, else
         the opposite) when a compare match occurs. To start this mode, call
         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
         interruption mode.

         (++) Encoder Mode: To use the encoder interface call
         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
         interruption mode. Only available for LPTIM1 instance.

         (++) Time out Mode: an active edge on one selected trigger input rests
         the counter. The first trigger event will start the timer, any
         successive trigger event will reset the counter and the timer will
         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.

         (++) Counter Mode: counter can be used to count external events on
         the LPTIM Input1 or it can be used to count internal clock cycles.
         To start this mode, call HAL_LPTIM_Counter_Start() or
         HAL_LPTIM_Counter_Start_IT() for interruption mode.

      (#) User can stop any process by calling the corresponding API:
          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
          already started in interruption mode.

      (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_lptim.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_nand.c File Reference

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Functions
stm32l4xx_hal_nand.c File Reference

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | NAND_AddressIncrement (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *Address)
Increment the NAND memory address.
HAL_StatusTypeDef | HAL_NAND_Init (NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
Perform NAND memory Initialization sequence.
HAL_StatusTypeDef | HAL_NAND_DeInit (NAND_HandleTypeDef *hnand)
Perform NAND memory De-Initialization sequence.
__weak void | HAL_NAND_MspInit (NAND_HandleTypeDef *hnand)
Initialize the NAND MSP.
__weak void | HAL_NAND_MspDeInit (NAND_HandleTypeDef *hnand)
DeInitialize the NAND MSP.
void | HAL_NAND_IRQHandler (NAND_HandleTypeDef *hnand)
This function handles NAND device interrupt request.
__weak void | HAL_NAND_ITCallback (NAND_HandleTypeDef *hnand)
NAND interrupt feature callback.
HAL_StatusTypeDef | HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
Read the NAND memory electronic signature.
HAL_StatusTypeDef | HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
NAND memory reset.
HAL_StatusTypeDef | HAL_NAND_Read_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
Read Page(s) from NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Write_Page (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
Write Page(s) to NAND memory block.
HAL_StatusTypeDef | HAL_NAND_Read_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
Read Spare area(s) from NAND memory.
HAL_StatusTypeDef | HAL_NAND_Write_SpareArea (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
Write Spare area(s) to NAND memory.
HAL_StatusTypeDef | HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
NAND memory Block erase.
uint32_t | HAL_NAND_Read_Status (NAND_HandleTypeDef *hnand)
NAND memory read status.
uint32_t | HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
Increment the NAND memory address.
HAL_StatusTypeDef | HAL_NAND_ECC_Enable (NAND_HandleTypeDef *hnand)
Enable dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_ECC_Disable (NAND_HandleTypeDef *hnand)
Disable dynamically NAND ECC feature.
HAL_StatusTypeDef | HAL_NAND_GetECC (NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
Disable dynamically NAND ECC feature.
HAL_NAND_StateTypeDef | HAL_NAND_GetState (NAND_HandleTypeDef *hnand)
Return the NAND handle state.

Detailed Description

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                         ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NAND flash memories. It uses the FMC layer functions to interface
      with NAND devices. This driver is used as follows:

      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
          with control and timing parameters for both common and attribute spaces.

      (+) Read NAND flash memory maker and device IDs using the function
          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
          structure declared by the function caller.

      (+) Access NAND flash memory by read/write operations using the functions
          HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
          to read/write page(s)/spare area(s). These functions use specific device
          information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
          structure. The read/write address information is contained by the Nand_Address_Typedef
          structure passed as parameter.

      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().

      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
          The erase block address information is contained in the Nand_Address_Typedef
          structure passed as parameter.

      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().

      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
          feature or the function HAL_NAND_GetECC() to get the ECC correction code.

      (+) You can monitor the NAND device HAL state by calling the function
          HAL_NAND_GetState()

    [..]
      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
          If a NAND flash device contains different operations and/or implementations,
          it should be implemented separately.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_nand.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_nor.c File Reference

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Defines | Functions | Variables
stm32l4xx_hal_nor.c File Reference

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define | NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define | NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define | NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
#define | NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define | NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define | NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define | NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define | NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define | NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define | NOR_CMD_DATA_CFI (uint16_t)0x0098
#define | NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define | NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define | NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define | NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define | NOR_MASK_STATUS_DQ6 (uint16_t)0x0040

Functions

HAL_StatusTypeDef | HAL_NOR_Init (NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the NOR memory Initialization sequence.
HAL_StatusTypeDef | HAL_NOR_DeInit (NOR_HandleTypeDef *hnor)
Perform NOR memory De-Initialization sequence.
__weak void | HAL_NOR_MspInit (NOR_HandleTypeDef *hnor)
Initialize the NOR MSP.
__weak void | HAL_NOR_MspDeInit (NOR_HandleTypeDef *hnor)
DeInitialize the NOR MSP.
__weak void | HAL_NOR_MspWait (NOR_HandleTypeDef *hnor, uint32_t Timeout)
NOR MSP Wait for Ready/Busy signal.
HAL_StatusTypeDef | HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
Read NOR flash IDs.
HAL_StatusTypeDef | HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
Return the NOR memory to Read mode.
HAL_StatusTypeDef | HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Read data from NOR memory.
HAL_StatusTypeDef | HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
Program data to NOR memory.
HAL_StatusTypeDef | HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Read a block of data from the FMC NOR memory.
HAL_StatusTypeDef | HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
Write a half-word buffer to the FMC NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
Erase the specified block of the NOR memory.
HAL_StatusTypeDef | HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
Erase the entire NOR chip.
HAL_StatusTypeDef | HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
Read NOR flash CFI IDs.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Enable (NOR_HandleTypeDef *hnor)
Enable dynamically NOR write operation.
HAL_StatusTypeDef | HAL_NOR_WriteOperation_Disable (NOR_HandleTypeDef *hnor)
Disable dynamically NOR write operation.
HAL_NOR_StateTypeDef | HAL_NOR_GetState (NOR_HandleTypeDef *hnor)
Return the NOR controller handle state.
HAL_NOR_StatusTypeDef | HAL_NOR_GetStatus (NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
Return the NOR operation status.

Variables

static uint32_t | uwNORMemoryDataWidth = NOR_MEMORY_8B

Detailed Description

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NOR flash memories. It uses the FMC layer functions to interface
      with NOR devices. This driver is used as follows:

      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
          with control and timing parameters for both normal and extended mode.

      (+) Read NOR flash memory manufacturer code and device IDs using the function
          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
          structure declared by the function caller.

      (+) Access NOR flash memory by read/write data unit operations using the functions
          HAL_NOR_Read(), HAL_NOR_Program().

      (+) Perform NOR flash erase block/chip operations using the functions
          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().

      (+) Read the NOR flash CFI (common flash interface) IDs using the function
          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
          structure declared by the function caller.

      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation

      (+) You can monitor the NOR device HAL state by calling the function
          HAL_NOR_GetState()
    [..]
     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
         If a NOR flash device contains different operations and/or implementations,
         it should be implemented separately.

     *** NOR HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in NOR HAL driver.

      (+) NOR_WRITE : NOR memory write data to specified address
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_nor.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_opamp.c File Reference

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Defines | Functions
stm32l4xx_hal_opamp.c File Reference

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
#define | OPAMP_CSR_RESET_BITS
#define | OPAMP_CSR_INIT_MASK_PGA
#define | OPAMP_CSR_INIT_MASK_FOLLOWER
#define | OPAMP_CSR_INIT_MASK_STANDALONE

Functions

HAL_StatusTypeDef | HAL_OPAMP_Init (OPAMP_HandleTypeDef *hopamp)
Initializes the OPAMP according to the specified parameters in the OPAMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize the OPAMP peripheral.
__weak void | HAL_OPAMP_MspInit (OPAMP_HandleTypeDef *hopamp)
Initialize the OPAMP MSP.
__weak void | HAL_OPAMP_MspDeInit (OPAMP_HandleTypeDef *hopamp)
DeInitialize OPAMP MSP.
HAL_StatusTypeDef | HAL_OPAMP_Start (OPAMP_HandleTypeDef *hopamp)
Start the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Stop (OPAMP_HandleTypeDef *hopamp)
Stop the OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_SelfCalibrate (OPAMP_HandleTypeDef *hopamp)
Run the self calibration of one OPAMP.
HAL_StatusTypeDef | HAL_OPAMP_Lock (OPAMP_HandleTypeDef *hopamp)
Lock the selected OPAMP configuration.
HAL_OPAMP_TrimmingValueTypeDef | HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
Return the OPAMP factory trimming value.
HAL_OPAMP_StateTypeDef | HAL_OPAMP_GetState (OPAMP_HandleTypeDef *hopamp)
Return the OPAMP handle state.

Detailed Description

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
================================================================================
          ##### OPAMP Peripheral Features #####
================================================================================

  [..] The device integrates 1 or 2 operational amplifiers OPAMP1 & OPAMP2

       (#) The OPAMP(s) provide(s) several exclusive running modes.
       (++) 1 OPAMP: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx
       (++) 2 OPAMP: STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx

       (#) The OPAMP(s) provide(s) several exclusive running modes.
       (++) Standalone mode
       (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
       (++) Follower mode

       (#) All OPAMP (same for all OPAMPs) can operate in
       (++) Either Low range (VDDA < 2.4V) power supply
       (++) Or High range (VDDA > 2.4V) power supply

       (#) Each OPAMP(s) can be configured in normal and low power mode.

       (#) The OPAMP(s) provide(s) calibration capabilities.
       (++) Calibration aims at correcting some offset for running mode.
       (++) The OPAMP uses either factory calibration settings OR user defined
           calibration (trimming) settings (i.e. trimming mode).
       (++) The user defined settings can be figured out using self calibration
           handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
       (++) HAL_OPAMP_SelfCalibrate:
       (+++) Runs automatically the calibration.
       (+++) Enables the user trimming mode
       (+++) Updates the init structure with trimming values with fresh calibration
            results.
            The user may store the calibration results for larger
            (ex monitoring the trimming as a function of temperature
            for instance)
       (+++) HAL_OPAMPEx_SelfCalibrateAll
            runs calibration of all OPAMPs in parallel to save search time.

       (#) Running mode: Standalone mode
       (++) Gain is set externally (gain depends on external loads).
       (++) Follower mode also possible externally by connecting the inverting input to
           the output.

       (#) Running mode: Follower mode
       (++) No Inverting Input is connected.

       (#) Running mode: Programmable Gain Amplifier (PGA) mode
           (Resistor feedback output)
       (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
           output.
       (++) OPAMP gain is either 2, 4, 8 or 16.

       (#) The OPAMPs inverting input can be selected according to the Reference Manual
           "OPAMP function description" chapter.

       (#) The OPAMPs non inverting input can be selected according to the Reference Manual
           "OPAMP function description" chapter.

            ##### How to use this driver #####
================================================================================
  [..]

    *** Power supply range ***
    ============================================
    [..] To run in low power mode:

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) Select OPAMP_POWERSUPPLY_LOW (VDDA lower than 2.4V)
      (++) Otherwise select OPAMP_POWERSUPPLY_HIGH (VDDA higher than 2.4V)

    *** Low / normal power mode ***
    ============================================
    [..] To run in low power mode:

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) Select OPAMP_POWERMODE_LOWPOWER
      (++) Otherwise select OPAMP_POWERMODE_NORMAL

    *** Calibration ***
    ============================================
    [..] To run the OPAMP calibration self calibration:

      (#) Start calibration using HAL_OPAMP_SelfCalibrate.
           Store the calibration results.

    *** Running mode ***
    ============================================

    [..] To use the OPAMP, perform the following steps:

      (#) Fill in the HAL_OPAMP_MspInit() to
      (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
      (++) Configure the OPAMP input AND output in analog mode using
           HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) Select the mode
      (++) Select the inverting input
      (++) Select the non-inverting input
      (++) If PGA mode is enabled, Select if inverting input is connected.
      (++) Select either factory or user defined trimming mode.
      (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
          (typically values set by HAL_OPAMP_SelfCalibrate function).

      (#) Enable the OPAMP using HAL_OPAMP_Start() function.

      (#) Disable the OPAMP using HAL_OPAMP_Stop() function.

      (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
          Caution: On STM32L4, HAL OPAMP lock is software lock only (not
          hardware lock as on some other STM32 devices)

      (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.

    *** Running mode: change of configuration while OPAMP ON  ***
    ============================================
    [..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
      (#) If needed, fill in the HAL_OPAMP_MspInit()
      (++) This is the case for instance if you wish to use new OPAMP I/O

      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
      (++) As in configure case, select first the parameters you wish to modify.

      (#) Change from low power mode to normal power mode (& vice versa) requires
          first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
          In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
          alone.

Table 1. OPAMPs inverting/non-inverting inputs for the STM32L4 devices: +------------------------------------------------------------------------| | | | OPAMP1 | OPAMP2 | |-----------------|---------|----------------------|---------------------| | Inverting Input | VM_SEL | | | | | | IO0-> PA1 | IO0-> PA7 | | | | LOW LEAKAGE IO (2) | LOW LEAKAGE IO (2) | | | | Not connected | Not connected | | (1) | | PGA mode only | PGA mode only | |-----------------|---------|----------------------|---------------------| | Non Inverting | VP_SEL | | | | | | IO0-> PA0 (GPIO) | IO0-> PA6 (GPIO) | | Input | | DAC1_OUT1 internal | DAC1_OUT2 internal | +------------------------------------------------------------------------| (1): NA in follower mode. (2): Available on some package only (ex. BGA132).

Table 2. OPAMPs outputs for the STM32L4 devices:

+------------------------------------------------------------------------- | | | OPAMP1 | OPAMP2 | |-----------------|--------|-----------------------|---------------------| | Output | VOUT | PA3 | PB0 | | | | & (1) ADC12_IN if | & (1) ADC12_IN if | | | | connected internally | connected internally| |-----------------|--------|-----------------------|---------------------| (1): ADC1 or ADC2 shall select IN15.

Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_opamp.c.

Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_opamp_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
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Functions
stm32l4xx_hal_opamp_ex.c File Reference

Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions. More...

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_OPAMPEx_Unlock (OPAMP_HandleTypeDef *hopamp)
Unlock the selected OPAMP configuration.
HAL_StatusTypeDef | HAL_OPAMPEx_SelfCalibrateAll (OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
Run the self calibration of the 2 OPAMPs in parallel.

Detailed Description

Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"

/** @addtogroup STM32L4xx_HAL_Driver
  * @{
  */

/** @defgroup OPAMPEx OPAMPEx
  * @brief OPAMP Extended HAL module driver
  * @{
  */

#ifdef HAL_OPAMP_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
  * @{
  */

#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)

/** @addtogroup OPAMPEx_Exported_Functions_Group1
  * @brief    Extended operation functions
  *
@verbatim
 ===============================================================================
              ##### Extended IO operation functions #####
 ===============================================================================
  [..]
      (+) OPAMP Self calibration.

Definition in file stm32l4xx_hal_opamp_ex.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pcd.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_hal_pcd.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Functions

static HAL_StatusTypeDef | PCD_WriteEmptyTxFifo (PCD_HandleTypeDef *hpcd, uint32_t epnum)
Check FIFO for the next packet to be loaded.
HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB OTG Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB OTG Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
Handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      The PCD HAL driver can be used as follows:

     (#) Declare a PCD_HandleTypeDef handle structure, for example:
         PCD_HandleTypeDef  hpcd;

     (#) Fill parameters of Init structure in HCD handle

     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)

     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
         (##) Enable the PCD/USB Low Level interface clock using
              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
         (##) Initialize the related GPIO clocks
         (##) Configure PCD pin-out
         (##) Configure PCD NVIC interrupt

     (#)Associate the Upper USB device stack to the HAL PCD Driver:
         (##) hpcd.pData = pdev;

     (#)Enable PCD transmission and reception:
         (##) HAL_PCD_Start();
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_pcd.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pcd_ex.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Functions
stm32l4xx_hal_pcd_ex.c File Reference

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_SetTxFiFo (PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
Set Tx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_SetRxFiFo (PCD_HandleTypeDef *hpcd, uint16_t size)
Set Rx FIFO.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_pcd_ex.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pwr.c File Reference

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Defines | Functions
stm32l4xx_hal_pwr.c File Reference

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | PVD_MODE_IT ((uint32_t)0x00010000)
#define | PVD_MODE_EVT ((uint32_t)0x00020000)
#define | PVD_RISING_EDGE ((uint32_t)0x00000001)
#define | PVD_FALLING_EDGE ((uint32_t)0x00000002)

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers).
HAL_StatusTypeDef | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector (PVD).
void | HAL_PWR_EnablePVD (void)
Enable the Power Voltage Detector (PVD).
void | HAL_PWR_DisablePVD (void)
Disable the Power Voltage Detector (PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX M4 SEVONPEND bit.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_pwr.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pwr_ex.c File Reference

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  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_hal_pwr_ex.c File Reference

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1)
#define | PVM_MODE_IT ((uint32_t)0x00010000)
#define | PVM_MODE_EVT ((uint32_t)0x00020000)
#define | PVM_RISING_EDGE ((uint32_t)0x00000001)
#define | PVM_FALLING_EDGE ((uint32_t)0x00000002)
#define | PWR_FLAG_SETTING_DELAY_US 50

Functions

uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnableVddUSB (void)
Enable VDDUSB supply.
void | HAL_PWREx_DisableVddUSB (void)
Disable VDDUSB supply.
void | HAL_PWREx_EnableVddIO2 (void)
Enable VDDIO2 supply.
void | HAL_PWREx_DisableVddIO2 (void)
Disable VDDIO2 supply.
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_EnableSRAM2ContentRetention (void)
Enable SRAM2 content retention in Standby mode.
void | HAL_PWREx_DisableSRAM2ContentRetention (void)
Disable SRAM2 content retention in Standby mode.
void | HAL_PWREx_EnablePVM1 (void)
Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_DisablePVM1 (void)
Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_EnablePVM2 (void)
Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
void | HAL_PWREx_DisablePVM2 (void)
Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
void | HAL_PWREx_EnablePVM3 (void)
Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
void | HAL_PWREx_DisablePVM3 (void)
Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
void | HAL_PWREx_EnablePVM4 (void)
Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
void | HAL_PWREx_DisablePVM4 (void)
Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSTOP0Mode (uint8_t STOPEntry)
Enter Stop 0 mode.
void | HAL_PWREx_EnterSTOP1Mode (uint8_t STOPEntry)
Enter Stop 1 mode.
void | HAL_PWREx_EnterSTOP2Mode (uint8_t STOPEntry)
Enter Stop 2 mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD/PVMx interrupt request.
__weak void | HAL_PWREx_PVM1Callback (void)
PWR PVM1 interrupt callback.
__weak void | HAL_PWREx_PVM2Callback (void)
PWR PVM2 interrupt callback.
__weak void | HAL_PWREx_PVM3Callback (void)
PWR PVM3 interrupt callback.
__weak void | HAL_PWREx_PVM4Callback (void)
PWR PVM4 interrupt callback.

Detailed Description

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_pwr_ex.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_qspi.c File Reference

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Defines | Functions
stm32l4xx_hal_qspi.c File Reference

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)
#define | QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)
#define | QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)
#define | QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)
#define | IS_QSPI_FUNCTIONAL_MODE(MODE)

Functions

static void | QSPI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process complete callback.
static void | QSPI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process complete callback.
static void | QSPI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process half complete callback.
static void | QSPI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process half complete callback.
static void | QSPI_DMAError (DMA_HandleTypeDef *hdma)
DMA QSPI communication error callback.
static void | QSPI_DMAAbortCplt (DMA_HandleTypeDef *hdma)
DMA QSPI abort complete callback.
static HAL_StatusTypeDef | QSPI_WaitFlagStateUntilTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
Wait for a flag state until timeout.
static void | QSPI_Config (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
Configure the communication registers.
HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
__weak void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
__weak void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.
void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
__weak void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
__weak void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
__weak void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
__weak void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
__weak void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
__weak void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
__weak void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
__weak void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
__weak void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.
HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.

Detailed Description

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    *** Initialization ***
    ======================
    [..]
      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
        (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
        (++) If interrupt mode is used, enable and configure QuadSPI global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.

    *** Indirect functional mode ***
    ================================
    [..]
      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
          functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used and if present the number of bytes.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
      (#) If no data is required for the command, it is sent directly to the memory :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
          HAL_QSPI_Transmit_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
          HAL_QSPI_Receive_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.

    *** Auto-polling functional mode ***
    ====================================
    [..]
      (#) Configure the command sequence and the auto-polling functional mode using the
          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
             the polling interval and the automatic stop activation.
      (#) After the configuration :
         (++) In polling mode, the output of the function is done when the status match is reached. The
             automatic stop is activated to avoid an infinite loop.
         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.

    *** Memory-mapped functional mode ***
    =====================================
    [..]
      (#) Configure the command sequence and the memory-mapped functional mode using the
          HAL_QSPI_MemoryMapped() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and the size.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The timeout activation and the timeout period.
      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.

    *** Errors management and abort functionality ***
    =================================================
    [..]
      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
      (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
          flushes the fifo :
         (++) In polling mode, the output of the function is done when the transfer
              complete bit is set and the busy bit cleared.
         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
              the transfer complete bi is set.

    *** Control functions ***
    =========================
    [..]
      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold

    *** Workarounds linked to Silicon Limitation ***
    ====================================================
    [..]
      (#) Workarounds Implemented inside HAL Driver
         (++) Extra data written in the FIFO at the end of a read transfer
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_qspi.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rcc.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
  • Src
Defines | Functions
stm32l4xx_hal_rcc.c File Reference

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | MSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
#define | __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))

Functions

static HAL_StatusTypeDef | RCC_SetFlashLatencyFromMSIRange (uint32_t msirange)
Update number of Flash wait states in line with MSI range and current voltage range.
void | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO pin(PA8).
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Return the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from Multiple Speed Internal oscillator
      (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
      and I-Cache are disabled, and all peripherals are off except internal
      SRAM, Flash and JTAG.

      (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
          all peripherals mapped on these busses are running at MSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in analog mode, except the JTAG pins which
          are assigned to be used for debug purpose.

    [..]
      Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB busses prescalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock source(s) for peripherals which clocks are not
          derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG)
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_rcc.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rcc_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Defines | Functions
stm32l4xx_hal_rcc_ex.c File Reference

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | PLLSAI1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | PLLSAI2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define | DIVIDER_P_UPDATE 0U
#define | DIVIDER_Q_UPDATE 1U
#define | DIVIDER_R_UPDATE 2U
#define | __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | LSCO_GPIO_PORT GPIOA
#define | LSCO_PIN GPIO_PIN_2

Functions

static HAL_StatusTypeDef | RCCEx_PLLSAI1_Config (RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s).
static HAL_StatusTypeDef | RCCEx_PLLSAI2_Config (RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s).
HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLLSAIs.
HAL_StatusTypeDef | HAL_RCCEx_EnablePLLSAI1 (RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
Enable PLLSAI1.
HAL_StatusTypeDef | HAL_RCCEx_DisablePLLSAI1 (void)
Disable PLLSAI1.
HAL_StatusTypeDef | HAL_RCCEx_EnablePLLSAI2 (RCC_PLLSAI2InitTypeDef *PLLSAI2Init)
Enable PLLSAI2.
HAL_StatusTypeDef | HAL_RCCEx_DisablePLLSAI2 (void)
Disable PLLISAI2.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_StandbyMSIRangeConfig (uint32_t MSIRange)
Configure the MSI range after standby mode.
void | HAL_RCCEx_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCCEx_EnableLSECSS_IT (void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
void | HAL_RCCEx_LSECSS_IRQHandler (void)
Handle the RCC LSE Clock Security System interrupt request.
__weak void | HAL_RCCEx_LSECSS_Callback (void)
RCCEx LSE Clock Security System interrupt callback.
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.
void | HAL_RCCEx_EnableMSIPLLMode (void)
Enable the PLL-mode of the MSI.
void | HAL_RCCEx_DisableMSIPLLMode (void)
Disable the PLL-mode of the MSI.

Detailed Description

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_rcc_ex.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rng.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
  • Src
Defines | Functions
stm32l4xx_hal_rng.c File Reference

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | RNG_TIMEOUT_VALUE 2

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initialize the RNG peripheral and initialize the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitialize the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initialize the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitialize the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generate a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generate a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handle RNG interrupt request.
uint32_t | HAL_RNG_GetRandomNumber (RNG_HandleTypeDef *hrng)
Return generated random number in polling mode (Obsolete).
uint32_t | HAL_RNG_GetRandomNumber_IT (RNG_HandleTypeDef *hrng)
Return a 32-bit random number with interrupt enabled (Obsolete).
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callback.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Return the RNG handle state.

Detailed Description

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      The RNG HAL driver can be used as follows:

      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
          in HAL_RNG_MspInit().
      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
      (#) Wait until the 32-bit Random Number Generator contains a valid
          random data using (polling/interrupt) mode.
      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_rng.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rtc.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Functions
stm32l4xx_hal_rtc.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC according to the specified parameters in the RTC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
 ===============================================================================
                          ##### RTC Operating Condition #####
 ===============================================================================
  [..] The real-time clock (RTC) and the RTC backup registers can be powered
       from the VBAT voltage when the main VDD supply is powered off.
       To retain the content of the RTC backup registers and supply the RTC
       when VDD is turned off, VBAT pin can be connected to an optional
       standby voltage supplied by a battery or by another source.

                   ##### Backup Domain Reset #####
 ===============================================================================
  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
       to their reset values.
       A backup domain reset is generated when one of the following events occurs:
    (#) Software reset, triggered by setting the BDRST bit in the
        RCC Backup domain control register (RCC_BDCR).
    (#) VDD or VBAT power on, if both supplies have previously been powered off.
    (#) Tamper detection event resets all data backup registers.

                   ##### Backup Domain Access #####
 ===================================================================
  [..] After reset, the backup domain (RTC registers, RTC backup data
       registers and backup SRAM) is protected against possible unwanted write
       accesses.

  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
        PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
    (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.

                  ##### How to use RTC Driver #####
 ===================================================================
  [..]
    (#) Enable the RTC domain access (see description in the section above).
    (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** Time and Date configuration ***
  ===================================
  [..]
    (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
        and HAL_RTC_SetDate() functions.
    (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.

  *** Alarm configuration ***
  ===========================
  [..]
    (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
            You can also configure the RTC Alarm with interrupt mode using the
            HAL_RTC_SetAlarm_IT() function.
    (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.

                  ##### RTC and low power modes #####
 ===================================================================
  [..] The MCU can be woken up from a low power mode by an RTC alternate
       function.
  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
       These RTC alternate functions can wake up the system from the Stop and
       Standby low power modes.
  [..] The system can also wake up from low power modes without depending
       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
       or the RTC wakeup events.
  [..] The RTC provides a programmable time base for waking up from the
       Stop or Standby mode at regular intervals.
       Wakeup from STOP and Standby modes is possible only when the RTC clock source
       is LSE or LSI.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_rtc.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rtc_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Defines | Functions
stm32l4xx_hal_rtc_ex.c File Reference

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | RTC_TAMPCR_MASK

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
uint32_t | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Read data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable the RTC domain access.
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** RTC Wakeup configuration ***
  ================================
  [..]
    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
        function. You can also configure the RTC Wakeup timer with interrupt mode
        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
        function.

  *** Outputs configuration ***
  =============================
  [..]  The RTC has 2 different outputs:
    (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
        and WaKeUp signals.
        To output the selected RTC signal, use the HAL_RTC_Init() function.
    (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
        To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
    (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
        the RTC_OR register.
    (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
        automatically configured in output alternate function.

  *** Smooth digital Calibration configuration ***
  ================================================
  [..]
    (+) Configure the RTC Original Digital Calibration Value and the corresponding
        calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
        function.

  *** TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
        You can also configure the RTC TimeStamp with interrupt mode using the
        HAL_RTCEx_SetTimeStamp_IT() function.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

  *** Internal TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
        User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

  *** Tamper configuration ***
  ============================
  [..]
    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
        or Level according to the Tamper filter (if equal to 0 Edge else Level)
        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
        Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
        with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
    (+) The default configuration of the Tamper erases the backup registers. To avoid
        erase, enable the NoErase field on the RTC_TAMPCR register.

  *** Backup Data Registers configuration ***
  ===========================================
  [..]
    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
        function.
    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
        function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_rtc_ex.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sai.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Defines | Enumerations | Functions
stm32l4xx_hal_sai.c File Reference

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | SAI_FIFO_SIZE 8
#define | SAI_DEFAULT_TIMEOUT 4
#define | SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)

Enumerations

enum | SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (SAI_HandleTypeDef *hsai, uint32_t mode)
Return the interrupt flag to set according the SAI setup.
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
Disable the SAI and wait for the disabling.
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8-Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
static void | SAI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA SAI Abort callback.
HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================

  [..]
    The SAI HAL driver can be used as follows:

    (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
        (##) Enable the SAI interface clock.
        (##) SAI pins configuration:
            (+++) Enable the clock for the SAI GPIOs.
            (+++) Configure these SAI pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
             and HAL_SAI_Receive_IT() APIs):
            (+++) Configure the SAI interrupt priority.
            (+++) Enable the NVIC SAI IRQ handle.

        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
             and HAL_SAI_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA Tx/Rx Stream.

    (#) The initialization can be done by two ways
        (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
        (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().

  [..]
    (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
        will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
        inside the transmit and receive process.
  [..]
    (@) Make sure that either:
        (+@) PLLSAI1CLK output is configured or
        (+@) PLLSAI2CLK output is configured or
        (+@) PLLSAI3CLK output is configured or
        (+@) External clock source is configured after setting correctly
             the define constant EXTERNAL_SAI1_CLOCK_VALUE or EXTERNAL_SAI2_CLOCK_VALUE in the stm32l4xx_hal_conf.h file.

  [..]
    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
        for the external slaves even if there is no data in the FIFO, However FS signal
        generation is conditioned by the presence of data in the FIFO.

  [..]
    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
        and FS signal for the external slaves.

  [..]
    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
        (+@) First bit Offset <= (SLOT size - Data size)
        (+@) Data size <= SLOT size
        (+@) Number of SLOT x SLOT size = Frame length
        (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.

  [..]
    Three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SAI_ErrorCallback()

    *** DMA mode IO operation ***
    =============================
    [..]
      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()

    *** SAI HAL driver additional function list ***
    ===============================================
    [..]
      Below the list the others API available SAI HAL driver :

      (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
      (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
      (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
      (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
      (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
      (+) HAL_SAI_Abort(): Abort the current transfer

    *** SAI HAL driver macros list ***
    ==================================
    [..]
      Below the list of most used macros in SAI HAL driver :

      (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
      (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
      (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
      (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
      (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
          enabled or disabled
      (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_sai.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sd.c File Reference

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Defines | Functions
stm32l4xx_hal_sd.c File Reference

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | DATA_BLOCK_SIZE ((uint32_t)(9 << 4))
SDMMC Data block size.
#define | SDMMC_STATIC_FLAGS
SDMMC Static flags, Timeout, FIFO Address.
#define | SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000)
#define | SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)
Mask for errors Card Status R1 (OCR Register)
#define | SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)
#define | SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)
#define | SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)
#define | SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)
#define | SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)
#define | SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)
#define | SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)
#define | SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)
#define | SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)
#define | SD_OCR_CC_ERROR ((uint32_t)0x00100000)
#define | SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
#define | SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
#define | SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
#define | SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
#define | SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
#define | SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
#define | SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
#define | SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)
#define | SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)
#define | SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)
Masks for R6 Response.
#define | SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)
#define | SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)
#define | SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)
#define | SD_HIGH_CAPACITY ((uint32_t)0x40000000)
#define | SD_STD_CAPACITY ((uint32_t)0x00000000)
#define | SD_CHECK_PATTERN ((uint32_t)0x000001AA)
#define | SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
#define | SD_ALLZERO ((uint32_t)0x00000000)
#define | SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)
#define | SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)
#define | SD_CARD_LOCKED ((uint32_t)0x02000000)
#define | SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)
#define | SD_0TO7BITS ((uint32_t)0x000000FF)
#define | SD_8TO15BITS ((uint32_t)0x0000FF00)
#define | SD_16TO23BITS ((uint32_t)0x00FF0000)
#define | SD_24TO31BITS ((uint32_t)0xFF000000)
#define | SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)
#define | SD_HALFFIFO ((uint32_t)0x00000008)
#define | SD_HALFFIFOBYTES ((uint32_t)0x00000020)
#define | SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)
Command Class Supported.
#define | SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)
#define | SD_CCCC_ERASE ((uint32_t)0x00000020)
#define | SD_SDMMC_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
Following commands are SD Card Specific commands.

Functions

static HAL_SD_ErrorTypedef | SD_Initialize_Cards (SD_HandleTypeDef *hsd)
Initializes all cards or single card as the case may be Card(s) come into standby state.
static HAL_SD_ErrorTypedef | SD_Select_Deselect (SD_HandleTypeDef *hsd, uint64_t addr)
Selects or Deselects the corresponding card.
static HAL_SD_ErrorTypedef | SD_PowerON (SD_HandleTypeDef *hsd)
Enquires cards about their operating voltage and configures clock controls and stores SD information that will be needed in future in the SD handle.
static HAL_SD_ErrorTypedef | SD_PowerOFF (SD_HandleTypeDef *hsd)
Turns the SDMMC output signals off.
static HAL_SD_ErrorTypedef | SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
Returns the current card's status.
static HAL_SD_CardStateTypedef | SD_GetState (SD_HandleTypeDef *hsd)
Returns the SD current state.
static HAL_SD_ErrorTypedef | SD_IsCardProgramming (SD_HandleTypeDef *hsd, uint8_t *pStatus)
Checks if the SD card is in programming state.
static HAL_SD_ErrorTypedef | SD_CmdError (SD_HandleTypeDef *hsd)
Checks for error conditions for CMD0.
static HAL_SD_ErrorTypedef | SD_CmdResp1Error (SD_HandleTypeDef *hsd, uint8_t SD_CMD)
Checks for error conditions for R1 response.
static HAL_SD_ErrorTypedef | SD_CmdResp7Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R7 response.
static HAL_SD_ErrorTypedef | SD_CmdResp3Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R3 (OCR) response.
static HAL_SD_ErrorTypedef | SD_CmdResp2Error (SD_HandleTypeDef *hsd)
Checks for error conditions for R2 (CID or CSD) response.
static HAL_SD_ErrorTypedef | SD_CmdResp6Error (SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
Checks for error conditions for R6 (RCA) response.
static HAL_SD_ErrorTypedef | SD_WideBus_Enable (SD_HandleTypeDef *hsd)
Enables the SDMMC wide bus mode.
static HAL_SD_ErrorTypedef | SD_WideBus_Disable (SD_HandleTypeDef *hsd)
Disables the SDMMC wide bus mode.
static HAL_SD_ErrorTypedef | SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR)
Finds the SD card SCR register value.
static void | SD_DMA_RxCplt (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Rx callback.
static void | SD_DMA_RxError (DMA_HandleTypeDef *hdma)
SD DMA transfer Error Rx callback.
static void | SD_DMA_TxCplt (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Tx callback.
static void | SD_DMA_TxError (DMA_HandleTypeDef *hdma)
SD DMA transfer Error Tx callback.
HAL_SD_ErrorTypedef | HAL_SD_Init (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
Initializes the SD card according to the specified parameters in the SD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SD_DeInit (SD_HandleTypeDef *hsd)
De-Initializes the SD card.
__weak void | HAL_SD_MspInit (SD_HandleTypeDef *hsd)
Initializes the SD MSP.
__weak void | HAL_SD_MspDeInit (SD_HandleTypeDef *hsd)
De-Initialize SD MSP.
HAL_SD_ErrorTypedef | HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Allows to write block(s) to a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Reads block(s) from a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_WriteBlocks_DMA (SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
Writes block(s) to a specified address in a card.
HAL_SD_ErrorTypedef | HAL_SD_CheckReadOperation (SD_HandleTypeDef *hsd, uint32_t Timeout)
This function waits until the SD DMA data read transfer is finished.
HAL_SD_ErrorTypedef | HAL_SD_CheckWriteOperation (SD_HandleTypeDef *hsd, uint32_t Timeout)
This function waits until the SD DMA data write transfer is finished.
HAL_SD_ErrorTypedef | HAL_SD_Erase (SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
Erases the specified memory area of the given SD card.
void | HAL_SD_IRQHandler (SD_HandleTypeDef *hsd)
This function handles SD card interrupt request.
__weak void | HAL_SD_XferCpltCallback (SD_HandleTypeDef *hsd)
SD end of transfer callback.
__weak void | HAL_SD_XferErrorCallback (SD_HandleTypeDef *hsd)
SD Transfer Error callback.
__weak void | HAL_SD_DMA_RxCpltCallback (DMA_HandleTypeDef *hdma)
SD Transfer complete Rx callback in non-blocking mode.
__weak void | HAL_SD_DMA_RxErrorCallback (DMA_HandleTypeDef *hdma)
SD DMA transfer complete Rx error callback.
__weak void | HAL_SD_DMA_TxCpltCallback (DMA_HandleTypeDef *hdma)
SD Transfer complete Tx callback in non-blocking mode.
__weak void | HAL_SD_DMA_TxErrorCallback (DMA_HandleTypeDef *hdma)
SD DMA transfer complete error Tx callback.
HAL_SD_ErrorTypedef | HAL_SD_Get_CardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
Returns information about specific card.
HAL_SD_ErrorTypedef | HAL_SD_WideBusOperation_Config (SD_HandleTypeDef *hsd, uint32_t WideMode)
Enables wide bus operation for the requested card if supported by card.
HAL_SD_ErrorTypedef | HAL_SD_StopTransfer (SD_HandleTypeDef *hsd)
Aborts an ongoing data transfer.
HAL_SD_ErrorTypedef | HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
Switches the SD card to High Speed mode.
HAL_SD_ErrorTypedef | HAL_SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
Returns the current SD card's status.
HAL_SD_TransferStateTypedef | HAL_SD_GetStatus (SD_HandleTypeDef *hsd)
Gets the current sd card data status.
HAL_SD_ErrorTypedef | HAL_SD_GetCardStatus (SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
Gets the SD card status.

Detailed Description

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver implements a high level communication layer for read and write from/to
    this memory. The needed STM32 hardware resources (SDMMC1 and GPIO) are performed by
    the user in HAL_SD_MspInit() function (MSP layer).
    Basically, the MSP layer configuration should be the same as we provide in the
    examples.
    You can easily tailor this configuration according to hardware resources.

  [..]
    This driver is a generic layered driver for SDMMC memories which uses the HAL
    SDMMC driver functions to interface with SD and uSD cards devices.
    It is used as follows:

    (#)Initialize the SDMMC1 low level resources by implementing the HAL_SD_MspInit() API:
        (##) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_SDMMC1 for
        PeriphClockSelection and select SDMMC1 clock source (MSI, main PLL or PLLSAI1)
        (##) Enable the SDMMC1 interface clock using __HAL_RCC_SDMMC1_CLK_ENABLE();
        (##) SDMMC pins configuration for SD card
            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
                  and according to your pin assignment;
        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
             and HAL_SD_WriteBlocks_DMA() APIs).
            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
            (+++) Configure the SDMMC and DMA interrupt priorities using functions
                  HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
            (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
            (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT()
                  and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process.
            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT()
                  and __HAL_SD_SDMMC_CLEAR_IT()
    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization

  *** SD Card Initialization and configuration ***
  ================================================
  [..]
    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes
    the SD Card and put it into StandBy State (Ready for data transfer).
    This function provide the following operations:

    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
        type (Standard Capacity or High Capacity). You can change or adapt this
        frequency by adjusting the "ClockDiv" field.
        The SD Card frequency (SDMMC_CK) is computed as follows:
     (++)

           SDMMC_CK = SDMMCCLK / (ClockDiv + 2)

     -@@-  In initialization mode and according to the SD Card standard,
          make sure that the SDMMC_CK frequency doesn't exceed 400KHz.

    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
        structure. This structure provide also ready computed SD Card capacity
        and Block size.

        -@- These information are stored in SD handle structure in case of future use.

    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
        frequency is set to 24MHz. You can change or adapt this frequency by adjusting
        the "ClockDiv" field.
        In transfer mode and according to the SD Card standard, make sure that the
        SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
        To be able to use a frequency higher than 24MHz, you should use the SDMMC
        peripheral in bypass mode. Refer to the corresponding reference manual
        for more details.

    (#) Select the corresponding SD Card according to the address read with the step 2.

    (#) Configure the SD Card in wide bus mode: 4-bits data.

  *** SD Card Read operation ***
  ==============================
  [..]
    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
        that the read transfer is done correctly in both DMA and SD sides.

  *** SD Card Write operation ***
  ===============================
  [..]
    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 bytes).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.

    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
        This function support only 512-bytes block length (the block size should be
        chosen as 512 byte).
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
        that the write transfer is done correctly in both DMA and SD sides.

  *** SD card status ***
  ======================
  [..]
    (+) At any time, you can check the SD Card status and get the SD card state
        by using the HAL_SD_GetStatus() function. This function checks first if the
        SD card is still connected and then get the internal SD Card transfer state.
    (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus()
        function.

  *** SD HAL driver macros list ***
  ==================================
  [..]
    Below the list of most used macros in SD HAL driver.

    (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device
    (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device
    (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer
    (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer
    (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt
    (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt
    (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not
    (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags
    [..]
    (@) You can refer to the SD HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_sd.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smartcard.c File Reference

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Defines | Functions
stm32l4xx_hal_smartcard.c File Reference

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))

Functions

static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The SMARTCARD HAL driver can be used as follows:

    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
    (#) Associate a USART to the SMARTCARD handle hsmartcard.
    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) USART pins configuration:
             (+++) Enable the clock for the USART GPIOs.
             (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
             and HAL_SMARTCARD_Receive_IT() APIs):
             (++) Configure the USARTx interrupt priority.
             (++) Enable the NVIC USART IRQ handle.
        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
             and HAL_SMARTCARD_Receive_DMA() APIs):
             (+++) Declare a DMA handle structure for the Tx/Rx channel.
             (+++) Enable the DMAx interface clock.
             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
             (+++) Configure the DMA Tx/Rx channel.
             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
        error enabling or disabling in the hsmartcard handle Init structure.

    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
        in the hsmartcard handle AdvancedInit structure.

    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMARTCARD_MspInit() API.
        [..]
        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.

    [..]
    [..] Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** SMARTCARD HAL driver macros list ***
     ========================================
     [..]
       Below the list of most used macros in SMARTCARD HAL driver.

       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled

     [..]
       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_smartcard.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smartcard_ex.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Functions
stm32l4xx_hal_smartcard_ex.c File Reference

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  =============================================================================
               ##### SMARTCARD peripheral extended features  #####
  =============================================================================
  [..]
  The Extended SMARTCARD HAL driver can be used as follows:

    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
        auto-retry counter,...) in the hsmartcard AdvancedInit structure.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_smartcard_ex.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smbus.c File Reference

  • File List
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Defines | Functions
stm32l4xx_hal_smbus.c File Reference

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */
#define | HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
#define | HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
#define | HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
#define | MAX_NBYTE_SIZE 255

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static HAL_StatusTypeDef | SMBUS_Enable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Disable_IRQ (SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Master_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (SMBUS_HandleTypeDef *hsmbus)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_TransferConfig (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The SMBUS HAL driver can be used as follows:

    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
        SMBUS_HandleTypeDef  hsmbus;

    (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
        (++) Enable the SMBUSx interface clock with __HAL_RCC_I2Cx_CLK_ENABLE()
        (++) SMBUS pins configuration
            (+++) Enable the clock for the SMBUS GPIOs
            (+++) Configure SMBUS pins as alternate function open-drain
        (++) NVIC configuration if you need to use interrupt process
            (+++) Configure the SMBUSx interrupt priority
            (+++) Enable the NVIC SMBUS IRQ Channel

    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing Mode,
        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.

    (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.

    (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()

    (#) For SMBUS IO operations, only one mode of operations is available within this driver :

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
      (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
      (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
      (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
      (++) The associated previous transfer callback is called at the end of abort process
      (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
      (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
           using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
      (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
      (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
      (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
      (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
      (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
      (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
           to check the Alert Error Code using function HAL_SMBUS_GetError()
      (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
      (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
           to check the Error Code using function HAL_SMBUS_GetError()

     *** SMBUS HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in SMBUS HAL driver.

      (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
      (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
      (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
      (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag
      (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt
      (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt

     [..]
       (@) You can refer to the SMBUS HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_smbus.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_spi.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_hal_spi.c File Reference

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_DEFAULT_TIMEOUT 50

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout)
Handle the check of the RXTX or TX transaction complete.
HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
DeInitialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
DeInitialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The SPI HAL driver can be used as follows:

      (#) Declare a SPI_HandleTypeDef handle structure, for example:
          SPI_HandleTypeDef  hspi;

      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
          (##) Enable the SPIx interface clock
          (##) SPI pins configuration
              (+++) Enable the clock for the SPI GPIOs
              (+++) Configure these SPI pins as alternate function push-pull
          (##) NVIC configuration if you need to use interrupt process
              (+++) Configure the SPIx interrupt priority
              (+++) Enable the NVIC SPI IRQ handle
          (##) DMA Configuration if you need to use DMA process
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
              (+++) Enable the DMAx clock
              (+++) Configure the DMA handle parameters
              (+++) Configure the DMA Tx or Rx channel
              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel

      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_SPI_MspInit() API.
     [..]
       Circular mode restriction:
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
          (##) Master 2Lines RxOnly
          (##) Master 1Line Rx
      (#) The CRC feature is not managed when the DMA circular mode is enabled
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_spi.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_spi_ex.c File Reference

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stm32l4xx_hal_spi_ex.c File Reference

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_FIFO_SIZE 4

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_spi_ex.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sram.c File Reference

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stm32l4xx_hal_sram.c File Reference

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_SRAM_Init (SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
Perform the SRAM device initialization sequence.
HAL_StatusTypeDef | HAL_SRAM_DeInit (SRAM_HandleTypeDef *hsram)
Perform the SRAM device de-initialization sequence.
__weak void | HAL_SRAM_MspInit (SRAM_HandleTypeDef *hsram)
Initialize the SRAM MSP.
__weak void | HAL_SRAM_MspDeInit (SRAM_HandleTypeDef *hsram)
DeInitialize the SRAM MSP.
__weak void | HAL_SRAM_DMA_XferCpltCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
__weak void | HAL_SRAM_DMA_XferErrorCallback (DMA_HandleTypeDef *hdma)
DMA transfer complete error callback.
HAL_StatusTypeDef | HAL_SRAM_Read_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
Read 8-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_8b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
Write 8-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
Read 16-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_16b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
Write 16-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Read 32-bit buffer from SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Write_32b (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Write 32-bit buffer to SRAM memory.
HAL_StatusTypeDef | HAL_SRAM_Read_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
Read a Word data buffer from the SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_Write_DMA (SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
Write a Word data buffer to SRAM memory using DMA transfer.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Enable (SRAM_HandleTypeDef *hsram)
Enable dynamically SRAM write operation.
HAL_StatusTypeDef | HAL_SRAM_WriteOperation_Disable (SRAM_HandleTypeDef *hsram)
Disable dynamically SRAM write operation.
HAL_SRAM_StateTypeDef | HAL_SRAM_GetState (SRAM_HandleTypeDef *hsram)
Return the SRAM controller handle state.

Detailed Description

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                          ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SRAM memories. It uses the FMC layer functions to interface
    with SRAM devices.
    The following sequence should be followed to configure the FMC to interface
    with SRAM/PSRAM memories:

   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
          SRAM_HandleTypeDef  hsram; and:

       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SRAM device

       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
            base register instance for NOR or SRAM extended mode

   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
       mode timings; for example:
          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
       (##) Control register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Init()
       (##) Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Timing_Init()
       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
            FMC_NORSRAM_Extended_Timing_Init()
       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation

   (#) You can continuously monitor the SRAM device HAL state by calling the function
       HAL_SRAM_GetState()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_sram.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_swpmi.c File Reference

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stm32l4xx_hal_swpmi.c File Reference

SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | SWPMI_TIMEOUT_VALUE ((uint32_t) 22000)

Functions

static void | SWPMI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process complete callback.
static void | SWPMI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI transmit process half complete callback.
static void | SWPMI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process complete callback.
static void | SWPMI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SWPMI receive process half complete callback.
static void | SWPMI_DMAError (DMA_HandleTypeDef *hdma)
DMA SWPMI communication error callback.
static HAL_StatusTypeDef | SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi)
Transmit an amount of data in interrupt mode.
static HAL_StatusTypeDef | SWPMI_EndTransmit_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi)
Receive an amount of data in interrupt mode.
static HAL_StatusTypeDef | SWPMI_EndReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up reception in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_EndTransmitReceive_IT (SWPMI_HandleTypeDef *hswpmi)
Wraps up transmission and reception in non-blocking mode.
static HAL_StatusTypeDef | SWPMI_WaitOnFlagSetUntilTimeout (SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
Handle SWPMI Communication Timeout.
HAL_StatusTypeDef | HAL_SWPMI_Init (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
HAL_StatusTypeDef | HAL_SWPMI_DeInit (SWPMI_HandleTypeDef *hswpmi)
De-initialize the SWPMI peripheral.
__weak void | HAL_SWPMI_MspInit (SWPMI_HandleTypeDef *hswpmi)
Initialize the SWPMI MSP.
__weak void | HAL_SWPMI_MspDeInit (SWPMI_HandleTypeDef *hswpmi)
DeInitialize the SWPMI MSP.
HAL_StatusTypeDef | HAL_SWPMI_Transmit (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Receive (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_IT (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Transmit_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_Receive_DMA (SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA interrupt.
HAL_StatusTypeDef | HAL_SWPMI_DMAStop (SWPMI_HandleTypeDef *hswpmi)
Stop all DMA transfers.
HAL_StatusTypeDef | HAL_SWPMI_EnableLoopback (SWPMI_HandleTypeDef *hswpmi)
Enable the Loopback mode.
HAL_StatusTypeDef | HAL_SWPMI_DisableLoopback (SWPMI_HandleTypeDef *hswpmi)
Disable the Loopback mode.
void | HAL_SWPMI_IRQHandler (SWPMI_HandleTypeDef *hswpmi)
Handle SWPMI interrupt request.
__weak void | HAL_SWPMI_TxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Transfer completed callback.
__weak void | HAL_SWPMI_TxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Tx Half Transfer completed callback.
__weak void | HAL_SWPMI_RxCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Transfer completed callback.
__weak void | HAL_SWPMI_RxHalfCpltCallback (SWPMI_HandleTypeDef *hswpmi)
Rx Half Transfer completed callback.
__weak void | HAL_SWPMI_ErrorCallback (SWPMI_HandleTypeDef *hswpmi)
SWPMI error callback.
HAL_SWPMI_StateTypeDef | HAL_SWPMI_GetState (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI handle state.
uint32_t | HAL_SWPMI_GetError (SWPMI_HandleTypeDef *hswpmi)
Return the SWPMI error code.

Detailed Description

SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
     The SWPMI HAL driver can be used as follows:

    (#) Declare a SWPMI_HandleTypeDef handle structure (eg. SWPMI_HandleTypeDef hswpmi).

    (#) Initialize the SWPMI low level resources by implementing the HAL_SWPMI_MspInit() API:
        (##) Enable the SWPMIx interface clock with __HAL_RCC_SWPMIx_CLK_ENABLE().
        (##) SWPMI IO configuration:
            (+++) Enable the clock for the SWPMI GPIO.
            (+++) Configure these SWPMI pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SWPMI_Transmit_IT()
             and HAL_SWPMI_Receive_IT() APIs):
            (+++) Configure the SWPMIx interrupt priority with HAL_NVIC_SetPriority().
            (+++) Enable the NVIC SWPMI IRQ handle with HAL_NVIC_EnableIRQ().

        (##) DMA Configuration if you need to use DMA process (HAL_SWPMI_Transmit_DMA()
             and HAL_SWPMI_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channels.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required
                  Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channels and requests.
            (+++) Associate the initialized DMA handle to the SWPMI DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete
                  interrupt on the DMA Tx/Rx channels.

    (#) Program the Bite Rate, Tx Buffering mode, Rx Buffering mode in the Init structure.

    (#) Enable the SWPMI peripheral by calling the HAL_SWPMI_Init() function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_swpmi.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tim.c File Reference

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Functions
stm32l4xx_hal_tim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 4 configuration.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Ouput Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Ouput Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM INput Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement on in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                      ##### TIMER Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
       Initialization function of this driver:
       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
            Output Compare signal.
       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
            PWM signal.
       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
            external signal.
         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
              in One Pulse Mode.
       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.

     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().

     (#) The DMA Burst is managed with the two following functions:
         HAL_TIM_DMABurst_WriteStart()
         HAL_TIM_DMABurst_ReadStart()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_tim.c.

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STM32L486xx HAL User Manual: stm32l4xx_hal_tim_ex.c File Reference

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Defines | Functions
stm32l4xx_hal_tim_ex.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | BDTR_BKF_SHIFT (16)
#define | BDTR_BK2F_SHIFT (20)
#define | TIMx_ETRSEL_MASK ((uint32_t)0x0001C000)

Functions

static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitialize the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitialize TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                      ##### TIMER Extended features #####
  ==============================================================================
  [..]
    The Timer Extended features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
              __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the
              Timer Hall Sensor Interface and the commutation event with the corresponding
              Interrupt and DMA request if needed (Note that One Timer is used to interface
             with the Hall sensor Interface and another Timer should be used to use
             the commutation event).

     (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_tim_ex.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tsc.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Functions
stm32l4xx_hal_tsc.c File Reference

This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | TSC_extract_groups (uint32_t iomask)
Utility function used to set the acquired groups mask.
HAL_StatusTypeDef | HAL_TSC_Init (TSC_HandleTypeDef *htsc)
Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_TSC_DeInit (TSC_HandleTypeDef *htsc)
Deinitialize the TSC peripheral registers to their default reset values.
__weak void | HAL_TSC_MspInit (TSC_HandleTypeDef *htsc)
Initialize the TSC MSP.
__weak void | HAL_TSC_MspDeInit (TSC_HandleTypeDef *htsc)
DeInitialize the TSC MSP.
HAL_StatusTypeDef | HAL_TSC_Start (TSC_HandleTypeDef *htsc)
Start the acquisition.
HAL_StatusTypeDef | HAL_TSC_Start_IT (TSC_HandleTypeDef *htsc)
Start the acquisition in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_Stop (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in polling mode.
HAL_StatusTypeDef | HAL_TSC_Stop_IT (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_PollForAcquisition (TSC_HandleTypeDef *htsc)
Start acquisition and wait until completion.
TSC_GroupStatusTypeDef | HAL_TSC_GroupGetStatus (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition status for a group.
uint32_t | HAL_TSC_GroupGetValue (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition measure for a group.
HAL_StatusTypeDef | HAL_TSC_IOConfig (TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
Configure TSC IOs.
HAL_StatusTypeDef | HAL_TSC_IODischarge (TSC_HandleTypeDef *htsc, uint32_t choice)
Discharge TSC IOs.
HAL_TSC_StateTypeDef | HAL_TSC_GetState (TSC_HandleTypeDef *htsc)
Return the TSC handle state.
void | HAL_TSC_IRQHandler (TSC_HandleTypeDef *htsc)
Handle TSC interrupt request.
__weak void | HAL_TSC_ConvCpltCallback (TSC_HandleTypeDef *htsc)
Acquisition completed callback in non-blocking mode.
__weak void | HAL_TSC_ErrorCallback (TSC_HandleTypeDef *htsc)
Error callback in non-blocking mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
================================================================================
                       ##### TSC specific features #####
================================================================================
  [..]
  (#) Proven and robust surface charge transfer acquisition principle

  (#) Supports up to 3 capacitive sensing channels per group

  (#) Capacitive sensing channels can be acquired in parallel offering a very good
      response time

  (#) Spread spectrum feature to improve system robustness in noisy environments

  (#) Full hardware management of the charge transfer acquisition sequence

  (#) Programmable charge transfer frequency

  (#) Programmable sampling capacitor I/O pin

  (#) Programmable channel I/O pin

  (#) Programmable max count value to avoid long acquisition when a channel is faulty

  (#) Dedicated end of acquisition and max count error flags with interrupt capability

  (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
      components

  (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation

                          ##### How to use this driver #####
================================================================================
  [..]
    (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.

    (#) GPIO pins configuration
      (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
      (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
           and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
           using HAL_GPIO_Init() function.

    (#) Interrupts configuration
      (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
           and HAL_NVIC_EnableIRQ() and function.

    (#) TSC configuration
      (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.

 [..]   TSC peripheral alternate functions are mapped on AF9.

  *** Acquisition sequence ***
  ===================================
  [..]
    (+) Discharge all IOs using HAL_TSC_IODischarge() function.
    (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
        of the sampling capacitor and electrodes design.
    (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
    (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
        If the synchronized mode is selected, the acquisition will start as soon as the signal
        is received on the synchro pin.
    (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
        HAL_TSC_GetState() function or using WFI instruction for example.
    (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
    (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.

Table 1. IOs for the STM32L4xx devices +--------------------------------+ | IOs | TSC functions | |--------------|-----------------| | PB12 (AF) | TSC_G1_IO1 | | PB13 (AF) | TSC_G1_IO2 | | PB14 (AF) | TSC_G1_IO3 | | PB15 (AF) | TSC_G1_IO4 | |--------------|-----------------| | PB4 (AF) | TSC_G2_IO1 | | PB5 (AF) | TSC_G2_IO2 | | PB6 (AF) | TSC_G2_IO3 | | PB7 (AF) | TSC_G2_IO4 | |--------------|-----------------| | PA15 (AF) | TSC_G3_IO1 | | PC10 (AF) | TSC_G3_IO2 | | PC11 (AF) | TSC_G3_IO3 | | PC12 (AF) | TSC_G3_IO4 | |--------------|-----------------| | PC6 (AF) | TSC_G4_IO1 | | PC7 (AF) | TSC_G4_IO2 | | PC8 (AF) | TSC_G4_IO3 | | PC9 (AF) | TSC_G4_IO4 | |--------------|-----------------| | PE10 (AF) | TSC_G5_IO1 | | PE11 (AF) | TSC_G5_IO2 | | PE12 (AF) | TSC_G5_IO3 | | PE13 (AF) | TSC_G5_IO4 | |--------------|-----------------| | PD10 (AF) | TSC_G6_IO1 | | PD11 (AF) | TSC_G6_IO2 | | PD12 (AF) | TSC_G6_IO3 | | PD13 (AF) | TSC_G6_IO4 | |--------------|-----------------| | PE2 (AF) | TSC_G7_IO1 | | PE3 (AF) | TSC_G7_IO2 | | PE4 (AF) | TSC_G7_IO3 | | PE5 (AF) | TSC_G7_IO4 | |--------------|-----------------| | PF14 (AF) | TSC_G8_IO1 | | PF15 (AF) | TSC_G8_IO2 | | PG0 (AF) | TSC_G8_IO3 | | PG1 (AF) | TSC_G8_IO4 | |--------------|-----------------| | PB10 (AF) | TSC_SYNC | | PD2 (AF) | | +--------------------------------+

Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_tsc.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_uart.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Defines | Functions
stm32l4xx_hal_uart.c File Reference

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | UART_CR1_FIELDS
#define | UART_LPUART_BRR_MIN ((uint32_t)0x00000300) /* LPUART BRR minimum authorized value */
#define | UART_LPUART_BRR_MAX ((uint32_t)0x000FFFFF) /* LPUART BRR maximum authorized value */

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when call by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Send an amount of data in interrupt mode.
static HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle .
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.

Detailed Description

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    The UART HAL driver can be used as follows:

    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) UART pins configuration:
            (+++) Enable the clock for the UART GPIOs.
            (+++) Configure these UART pins as alternate function pull-up.
        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
             and HAL_UART_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (++) UART interrupts handling:
              -@@-  The specific UART interrupts (Transmission complete interrupt,
                RXNE interrupt and Error Interrupts) are managed using the macros
                __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
             and HAL_UART_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.

    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
        in the huart handle AdvancedInit structure.

    (#) For the UART asynchronous mode, initialize the UART registers by calling
        the HAL_UART_Init() API.

    (#) For the UART Half duplex mode, initialize the UART registers by calling
        the HAL_HalfDuplex_Init() API.

    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
        by calling the HAL_LIN_Init() API.

    (#) For the UART Multiprocessor mode, initialize the UART registers
        by calling the HAL_MultiProcessor_Init() API.

    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

    [..]
    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
        calling the customized HAL_UART_MspInit() API.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_uart.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_uart_ex.c File Reference

  • File List
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  • STM32L4xx_HAL_Driver
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Functions
stm32l4xx_hal_uart_ex.c File Reference

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

static void | UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.
HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.

Detailed Description

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
               ##### UART peripheral extended features  #####
  ==============================================================================

    (#) Declare a UART_HandleTypeDef handle structure.

    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_uart_ex.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_usart.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Defines | Functions
stm32l4xx_hal_usart.c File Reference

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000)
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS

Functions

static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
      The USART HAL driver can be used as follows:

      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
          (++) Enable the USARTx interface clock.
          (++) USART pins configuration:
            (+++) Enable the clock for the USART GPIOs.
            (+++) Configure these USART pins as alternate function pull-up.
          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
            (++) USART interrupts handling:
              -@@-   The specific USART interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
          flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.

      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
               by calling the customized HAL_USART_MspInit(&husart) API.

    [..]
     (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
        HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
        HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_usart.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_wwdg.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Functions
stm32l4xx_hal_wwdg.c File Reference

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions. More...

#include "stm32l4xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
  ==============================================================================
                      ##### WWDG specific features #####
  ==============================================================================
  [..]
    Once enabled the WWDG generates a system reset on expiry of a programmed
    time period, unless the program refreshes the counter (T[6;0] downcounter)
    before reaching 0x3F value (i.e. a reset is generated when the counter
    value rolls over from 0x40 to 0x3F).

    (+) An MCU reset is also generated if the counter value is refreshed
        before the counter has reached the refresh window value. This
        implies that the counter must be refreshed in a limited window.

    (+) Once enabled the WWDG cannot be disabled except by a system reset.

    (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
        occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).

    (+) The WWDG downcounter input clock is derived from the APB clock divided
        by a programmable prescaler.

    (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)

    (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
        where T[5;0] are the lowest 6 bits of downcounter.

    (+) WWDG Counter refresh is allowed between the following limits :
        (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
        (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)

    (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms

    (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
        operations or data logging must be performed before the actual reset is
        generated. When the downcounter reaches the value 0x40, an EWI interrupt
        is generated and the corresponding interrupt service routine (ISR) can
        be used to trigger specific actions (such as communications or data
        logging), before resetting the device.
        In some applications, the EWI interrupt can be used to manage a software
        system check and/or system recovery/graceful degradation, without
        generating a WWDG reset. In this case, the corresponding interrupt
        service routine (ISR) should reload the WWDG counter to avoid the WWDG
        reset, then trigger the required actions.
        Note:When the EWI interrupt cannot be served, e.g. due to a system lock
        in a higher priority task, the WWDG reset will eventually be generated.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the WWDG counter either continues to work normally or stops, depending
        on DBG_WWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().

    (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
        Interrupt mode using using HAL_WWDG_Init() function.
        This enables WWDG peripheral and the downcounter starts downcounting
        from given counter value.
        Init function can be called again to modify all watchdog parameters,
        however if EWI mode has been set once, it can't be clear until next
        reset.

    (+) The application program must refresh the WWDG counter at regular
        intervals during normal operation to prevent an MCU reset using
        HAL_WWDG_Refresh() function. This operation must occur only when
        the counter is lower than the window value already programmed.

    (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
        the counter reaches 0x40. User can add his own code in weak function
        HAL_WWDG_EarlyWakeupCallback().

     *** WWDG HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in WWDG HAL driver.

      (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_hal_wwdg.c.

Generated on Wed Jun 1 2016 16:28:16 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_pwr.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Functions
stm32l4xx_ll_pwr.c File Reference

PWR LL module driver. More...

#include "stm32l4xx_ll_pwr.h"
#include "stm32l4xx_ll_bus.h"

Go to the source code of this file.

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

PWR LL module driver.

Author:
MCD Application Team
Version:
V1.5.1
Date:
31-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_pwr.c.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC_rmtollPages.txt File Reference

  • File List
  • Globals
ADC_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Structures

  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
__DMA_HandleTypeDef | DMA handle Structure definition
__I2C_HandleTypeDef |
__SAI_HandleTypeDef |
__SPI_HandleTypeDef | SPI handle Structure definition
ADC_AnalogWDGConfTypeDef | Structure definition of ADC analog watchdog
ADC_ChannelConfTypeDef | Structure definition of ADC channel for regular group
ADC_HandleTypeDef | ADC handle Structure definition
ADC_InitTypeDef | Structure definition of ADC initialization and regular group
ADC_InjectionConfigTypeDef | ADC Injection Configuration
ADC_InjectionConfTypeDef | Structure definition of ADC injected group and ADC channel for injected group
ADC_InjOversamplingTypeDef | ADC Injected Conversion Oversampling structure definition
ADC_MultiModeTypeDef | Structure definition of ADC multimode
ADC_OversamplingTypeDef | ADC Regular Conversion Oversampling structure definition
CAN_FilterConfTypeDef | CAN filter configuration structure definition
CAN_HandleTypeDef | CAN handle Structure definition
CAN_InitTypeDef | CAN init structure definition
CanRxMsgTypeDef | CAN Rx message structure definition
CanTxMsgTypeDef | CAN Tx message structure definition
COMP_HandleTypeDef | COMP Handle Structure definition
COMP_InitTypeDef | COMP Init structure definition
CRC_HandleTypeDef | CRC Handle Structure definition
CRC_InitTypeDef | CRC Init Structure definition
CRYP_HandleTypeDef | CRYP handle Structure definition
CRYP_InitTypeDef | CRYP Configuration Structure definition
DAC_ChannelConfTypeDef | DAC Configuration regular Channel structure definition
DAC_HandleTypeDef | DAC handle Structure definition
DAC_SampleAndHoldConfTypeDef | DAC Configuration sample and hold Channel structure definition
DFSDM_Channel_AwdTypeDef | DFSDM channel analog watchdog structure definition
DFSDM_Channel_HandleTypeDef | DFSDM channel handle structure definition
DFSDM_Channel_InitTypeDef | DFSDM channel init structure definition
DFSDM_Channel_InputTypeDef | DFSDM channel input structure definition
DFSDM_Channel_OutputClockTypeDef | DFSDM channel output clock structure definition
DFSDM_Channel_SerialInterfaceTypeDef | DFSDM channel serial interface structure definition
DFSDM_Filter_AwdParamTypeDef | DFSDM filter analog watchdog parameters structure definition
DFSDM_Filter_FilterParamTypeDef | DFSDM filter parameters structure definition
DFSDM_Filter_HandleTypeDef | DFSDM filter handle structure definition
DFSDM_Filter_InitTypeDef | DFSDM filter init structure definition
DFSDM_Filter_InjectedParamTypeDef | DFSDM filter injected conversion parameters structure definition
DFSDM_Filter_RegularParamTypeDef | DFSDM filter regular conversion parameters structure definition
DMA_InitTypeDef | DMA Configuration Structure definition
FIREWALL_InitTypeDef | FIREWALL Initialization Structure definition
FLASH_EraseInitTypeDef | FLASH Erase structure definition
FLASH_OBProgramInitTypeDef | FLASH Option Bytes Program structure definition
FLASH_ProcessTypeDef | FLASH handle Structure definition
GPIO_InitTypeDef | GPIO Init structure definition
HCD_HandleTypeDef |
I2C_InitTypeDef |
IRDA_HandleTypeDef | IRDA handle Structure definition
IRDA_InitTypeDef | IRDA Init Structure definition
IWDG_HandleTypeDef | IWDG Handle Structure definition
IWDG_InitTypeDef | IWDG Init structure definition
LCD_HandleTypeDef | UART handle Structure definition
LCD_InitTypeDef | LCD Init structure definition
LL_ADC_CommonInitTypeDef | Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance)
LL_ADC_InitTypeDef | Structure definition of some features of ADC instance
LL_ADC_INJ_InitTypeDef | Structure definition of some features of ADC group injected
LL_ADC_REG_InitTypeDef | Structure definition of some features of ADC group regular
LL_COMP_InitTypeDef | Structure definition of some features of COMP instance
LL_DAC_InitTypeDef | Structure definition of some features of DAC instance
LL_DMA_InitTypeDef |
LL_EXTI_InitTypeDef |
LL_GPIO_InitTypeDef | LL GPIO Init Structure definition
LL_I2C_InitTypeDef |
LL_LPTIM_InitTypeDef | LPTIM Init structure definition
LL_LPUART_InitTypeDef | LL LPUART Init Structure definition
LL_OPAMP_InitTypeDef | Structure definition of some features of OPAMP instance
LL_RCC_ClocksTypeDef | RCC Clocks Frequency Structure
LL_RTC_AlarmTypeDef | RTC Alarm structure definition
LL_RTC_DateTypeDef | RTC Date structure definition
LL_RTC_InitTypeDef | RTC Init structures definition
LL_RTC_TimeTypeDef | RTC Time structure definition
LL_SPI_InitTypeDef | SPI Init structures definition
LL_SWPMI_InitTypeDef | SWPMI Init structures definition
LL_TIM_ENCODER_InitTypeDef | TIM Encoder interface configuration structure definition
LL_TIM_HALLSENSOR_InitTypeDef | TIM Hall sensor interface configuration structure definition
LL_TIM_IC_InitTypeDef | TIM Input Capture configuration structure definition
LL_TIM_InitTypeDef | TIM Time Base configuration structure definition
LL_TIM_OC_InitTypeDef | TIM Output Compare configuration structure definition
LL_USART_ClockInitTypeDef | LL USART Clock Init Structure definition
LL_USART_InitTypeDef | LL USART Init Structure definition
LL_UTILS_ClkInitTypeDef | UTILS System, AHB and APB buses clock configuration structure definition
LL_UTILS_PLLInitTypeDef | UTILS PLL structure definition
LPTIM_ClockConfigTypeDef | LPTIM Clock configuration definition
LPTIM_HandleTypeDef | LPTIM handle Structure definition
LPTIM_InitTypeDef | LPTIM Initialization Structure definition
LPTIM_TriggerConfigTypeDef | LPTIM Trigger configuration definition
LPTIM_ULPClockConfigTypeDef | LPTIM Clock configuration definition
MPU_Region_InitTypeDef |
NAND_AddressTypeDef | NAND Memory address Structure definition
NAND_HandleTypeDef | NAND handle Structure definition
NAND_IDTypeDef | NAND Memory electronic signature Structure definition
NAND_InfoTypeDef | NAND Memory info Structure definition
NOR_CFITypeDef | FMC NOR CFI typedef
NOR_HandleTypeDef | NOR handle Structure definition
NOR_IDTypeDef | FMC NOR ID typedef
OPAMP_HandleTypeDef | OPAMP Handle Structure definition
OPAMP_InitTypeDef | OPAMP Init structure definition
PCD_HandleTypeDef | PCD Handle Structure definition
PWR_PVDTypeDef | PWR PVD configuration structure definition
PWR_PVMTypeDef | PWR PVM configuration structure definition
QSPI_AutoPollingTypeDef | QSPI Auto Polling mode configuration structure definition
QSPI_CommandTypeDef | QSPI Command structure definition
QSPI_HandleTypeDef | QSPI Handle Structure definition
QSPI_InitTypeDef | QSPI Init structure definition
QSPI_MemoryMappedTypeDef | QSPI Memory Mapped mode configuration structure definition
RCC_ClkInitTypeDef | RCC System, AHB and APB busses clock configuration structure definition
RCC_OscInitTypeDef | RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
RCC_PeriphCLKInitTypeDef | RCC extended clocks structure definition
RCC_PLLInitTypeDef | RCC PLL configuration structure definition
RCC_PLLSAI1InitTypeDef | PLLSAI1 Clock structure definition
RCC_PLLSAI2InitTypeDef | PLLSAI2 Clock structure definition
RNG_HandleTypeDef | RNG Handle Structure definition
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_DateTypeDef | RTC Date structure definition
RTC_HandleTypeDef | Time Handle Structure definition
RTC_InitTypeDef | RTC Configuration Structure definition
RTC_TamperTypeDef | RTC Tamper structure definition
RTC_TimeTypeDef | RTC Time structure definition
SAI_FrameInitTypeDef |
SAI_InitTypeDef |
SAI_SlotInitTypeDef |
SMARTCARD_AdvFeatureInitTypeDef | SMARTCARD advanced features initalization structure definition
SMARTCARD_HandleTypeDef | SMARTCARD handle Structure definition
SMARTCARD_InitTypeDef | SMARTCARD Init Structure definition
SMBUS_HandleTypeDef |
SMBUS_InitTypeDef |
SPI_InitTypeDef | SPI Configuration Structure definition
SRAM_HandleTypeDef | SRAM handle Structure definition
SWPMI_HandleTypeDef | SWPMI handle Structure definition
SWPMI_InitTypeDef | SWPMI Init Structure definition
TIM_Base_InitTypeDef | TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef | TIM Break input(s) and Dead time configuration Structure definition
TIM_ClearInputConfigTypeDef | Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef | Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef | TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef | TIM Hall sensor Configuration Structure definition
TIM_HandleTypeDef | TIM Time Base Handle Structure definition
TIM_IC_InitTypeDef | TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef | TIM Master configuration Structure definition
TIM_OC_InitTypeDef | TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef | TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef | TIM Slave configuration Structure definition
TIMEx_BreakInputConfigTypeDef | TIM Break/Break2 input configuration
TSC_HandleTypeDef | TSC handle Structure definition
TSC_InitTypeDef | TSC init structure definition
TSC_IOConfigTypeDef | TSC IOs configuration structure definition
UART_AdvFeatureInitTypeDef | UART Advanced Features initalization structure definition
UART_HandleTypeDef | UART handle Structure definition
UART_InitTypeDef | UART Init Structure definition
UART_WakeUpTypeDef | UART wake up from stop mode parameters
USART_HandleTypeDef | USART handle Structure definition
USART_InitTypeDef | USART Init Structure definition
WWDG_HandleTypeDef | WWDG handle Structure definition
WWDG_InitTypeDef | WWDG Init structure definition
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STM32L486xx HAL User Manual: BUS_rmtollPages.txt File Reference

  • File List
  • Globals
BUS_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Data Structure Index

  • Data Structure Index
  • Data Fields
Data Structure Index
A | C | D | F | G | H | I | L | M | N | O | P | Q | R | S | T | U | W | _
A
DFSDM_Filter_InjectedParamTypeDef LL_RCC_ClocksTypeDef PWR_PVDTypeDef TIM_BreakDeadTimeConfigTypeDef
DFSDM_Filter_RegularParamTypeDef LL_RTC_AlarmTypeDef PWR_PVMTypeDef TIM_ClearInputConfigTypeDef
ADC_AnalogWDGConfTypeDef DMA_InitTypeDef LL_RTC_DateTypeDef
Q
TIM_ClockConfigTypeDef
ADC_ChannelConfTypeDef
F
LL_RTC_InitTypeDef TIM_Encoder_InitTypeDef
ADC_HandleTypeDef LL_RTC_TimeTypeDef QSPI_AutoPollingTypeDef TIM_HallSensor_InitTypeDef
ADC_InitTypeDef FIREWALL_InitTypeDef LL_SPI_InitTypeDef QSPI_CommandTypeDef TIM_HandleTypeDef
ADC_InjectionConfigTypeDef FLASH_EraseInitTypeDef LL_SWPMI_InitTypeDef QSPI_HandleTypeDef TIM_IC_InitTypeDef
ADC_InjectionConfTypeDef FLASH_OBProgramInitTypeDef LL_TIM_ENCODER_InitTypeDef QSPI_InitTypeDef TIM_MasterConfigTypeDef
ADC_InjOversamplingTypeDef FLASH_ProcessTypeDef LL_TIM_HALLSENSOR_InitTypeDef QSPI_MemoryMappedTypeDef TIM_OC_InitTypeDef
ADC_MultiModeTypeDef
G
LL_TIM_IC_InitTypeDef
R
TIM_OnePulse_InitTypeDef
ADC_OversamplingTypeDef LL_TIM_InitTypeDef TIM_SlaveConfigTypeDef
C
GPIO_InitTypeDef LL_TIM_OC_InitTypeDef RCC_ClkInitTypeDef TIMEx_BreakInputConfigTypeDef
H
LL_USART_ClockInitTypeDef RCC_OscInitTypeDef TSC_HandleTypeDef
CAN_FilterConfTypeDef LL_USART_InitTypeDef RCC_PeriphCLKInitTypeDef TSC_InitTypeDef
CAN_HandleTypeDef HCD_HandleTypeDef LL_UTILS_ClkInitTypeDef RCC_PLLInitTypeDef TSC_IOConfigTypeDef
CAN_InitTypeDef
I
LL_UTILS_PLLInitTypeDef RCC_PLLSAI1InitTypeDef
U
CanRxMsgTypeDef LPTIM_ClockConfigTypeDef RCC_PLLSAI2InitTypeDef
CanTxMsgTypeDef I2C_InitTypeDef LPTIM_HandleTypeDef RNG_HandleTypeDef UART_AdvFeatureInitTypeDef
COMP_HandleTypeDef IRDA_HandleTypeDef LPTIM_InitTypeDef RTC_AlarmTypeDef UART_HandleTypeDef
COMP_InitTypeDef IRDA_InitTypeDef LPTIM_TriggerConfigTypeDef RTC_DateTypeDef UART_InitTypeDef
CRC_HandleTypeDef IWDG_HandleTypeDef LPTIM_ULPClockConfigTypeDef RTC_HandleTypeDef UART_WakeUpTypeDef
CRC_InitTypeDef IWDG_InitTypeDef
M
RTC_InitTypeDef USART_HandleTypeDef
CRYP_HandleTypeDef
L
RTC_TamperTypeDef USART_InitTypeDef
CRYP_InitTypeDef MPU_Region_InitTypeDef RTC_TimeTypeDef
W
D
LCD_HandleTypeDef
N
S
LCD_InitTypeDef WWDG_HandleTypeDef
DAC_ChannelConfTypeDef LL_ADC_CommonInitTypeDef NAND_AddressTypeDef SAI_FrameInitTypeDef WWDG_InitTypeDef
DAC_HandleTypeDef LL_ADC_InitTypeDef NAND_HandleTypeDef SAI_InitTypeDef
_
DAC_SampleAndHoldConfTypeDef LL_ADC_INJ_InitTypeDef NAND_IDTypeDef SAI_SlotInitTypeDef
DFSDM_Channel_AwdTypeDef LL_ADC_REG_InitTypeDef NAND_InfoTypeDef SMARTCARD_AdvFeatureInitTypeDef __DMA_HandleTypeDef
DFSDM_Channel_HandleTypeDef LL_COMP_InitTypeDef NOR_CFITypeDef SMARTCARD_HandleTypeDef __I2C_HandleTypeDef
DFSDM_Channel_InitTypeDef LL_DAC_InitTypeDef NOR_HandleTypeDef SMARTCARD_InitTypeDef __SAI_HandleTypeDef
DFSDM_Channel_InputTypeDef LL_DMA_InitTypeDef NOR_IDTypeDef SMBUS_HandleTypeDef __SPI_HandleTypeDef
DFSDM_Channel_OutputClockTypeDef LL_EXTI_InitTypeDef
O
SMBUS_InitTypeDef
DFSDM_Channel_SerialInterfaceTypeDef LL_GPIO_InitTypeDef SPI_InitTypeDef
DFSDM_Filter_AwdParamTypeDef LL_I2C_InitTypeDef OPAMP_HandleTypeDef SRAM_HandleTypeDef
DFSDM_Filter_FilterParamTypeDef LL_LPTIM_InitTypeDef OPAMP_InitTypeDef SWPMI_HandleTypeDef
DFSDM_Filter_HandleTypeDef LL_LPUART_InitTypeDef
P
SWPMI_InitTypeDef
DFSDM_Filter_InitTypeDef LL_OPAMP_InitTypeDef
T
PCD_HandleTypeDef
TIM_Base_InitTypeDef
A | C | D | F | G | H | I | L | M | N | O | P | Q | R | S | T | U | W | _
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STM32L486xx HAL User Manual: COMP_rmtollPages.txt File Reference

  • File List
  • Globals
COMP_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX_rmtollPages.txt File Reference

  • File List
  • Globals
CORTEX_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC_rmtollPages.txt File Reference

  • File List
  • Globals
CRC_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC_rmtollPages.txt File Reference

  • File List
  • Globals
DAC_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: X:/Drivers/STM32L4xx_HAL_Driver/Inc/ Directory Reference

  • Drivers
  • STM32L4xx_HAL_Driver
  • Inc
Inc Directory Reference

Files

file | stm32l4xx_hal.h [code]

This file contains all the functions prototypes for the HAL module driver.

file | stm32l4xx_hal_adc.h [code]

Header file of ADC HAL module.

file | stm32l4xx_hal_adc_ex.h [code]

Header file of ADC HAL extended module.

file | stm32l4xx_hal_can.h [code]

Header file of CAN HAL module.

file | stm32l4xx_hal_comp.h [code]

Header file of COMP HAL module.

file | stm32l4xx_hal_cortex.h [code]

Header file of CORTEX HAL module.

file | stm32l4xx_hal_crc.h [code]

Header file of CRC HAL module.

file | stm32l4xx_hal_crc_ex.h [code]

Header file of CRC HAL extended module.

file | stm32l4xx_hal_cryp.h [code]

Header file of CRYP HAL module.

file | stm32l4xx_hal_cryp_ex.h [code]

Header file of CRYPEx HAL module.

file | stm32l4xx_hal_dac.h [code]

Header file of DAC HAL module.

file | stm32l4xx_hal_dac_ex.h [code]

Header file of DAC HAL Extended module.

file | stm32l4xx_hal_dfsdm.h [code]

Header file of DFSDM HAL module.

file | stm32l4xx_hal_dma.h [code]

Header file of DMA HAL module.

file | stm32l4xx_hal_firewall.h [code]

Header file of FIREWALL HAL module.

file | stm32l4xx_hal_flash.h [code]

Header file of FLASH HAL module.

file | stm32l4xx_hal_flash_ex.h [code]

Header file of FLASH HAL Extended module.

file | stm32l4xx_hal_flash_ramfunc.h [code]

Header file of FLASH RAMFUNC driver.

file | stm32l4xx_hal_gpio.h [code]

Header file of GPIO HAL module.

file | stm32l4xx_hal_gpio_ex.h [code]

Header file of GPIO HAL Extended module.

file | stm32l4xx_hal_hcd.h [code]

Header file of HCD HAL module.

file | stm32l4xx_hal_i2c.h [code]

Header file of I2C HAL module.

file | stm32l4xx_hal_i2c_ex.h [code]

Header file of I2C HAL Extended module.

file | stm32l4xx_hal_irda.h [code]

Header file of IRDA HAL module.

file | stm32l4xx_hal_irda_ex.h [code]

Header file of IRDA HAL Extended module.

file | stm32l4xx_hal_iwdg.h [code]

Header file of IWDG HAL module.

file | stm32l4xx_hal_lcd.h [code]

Header file of LCD Controller HAL module.

file | stm32l4xx_hal_lptim.h [code]

Header file of LPTIM HAL module.

file | stm32l4xx_hal_nand.h [code]

Header file of NAND HAL module.

file | stm32l4xx_hal_nor.h [code]

Header file of NOR HAL module.

file | stm32l4xx_hal_opamp.h [code]

Header file of OPAMP HAL module.

file | stm32l4xx_hal_opamp_ex.h [code]

Header file of OPAMP HAL Extended module.

file | stm32l4xx_hal_pcd.h [code]

Header file of PCD HAL module.

file | stm32l4xx_hal_pcd_ex.h [code]

Header file of PCD HAL module.

file | stm32l4xx_hal_pwr.h [code]

Header file of PWR HAL module.

file | stm32l4xx_hal_pwr_ex.h [code]

Header file of PWR HAL Extended module.

file | stm32l4xx_hal_qspi.h [code]

Header file of QSPI HAL module.

file | stm32l4xx_hal_rcc.h [code]

Header file of RCC HAL module.

file | stm32l4xx_hal_rcc_ex.h [code]

Header file of RCC HAL Extended module.

file | stm32l4xx_hal_rng.h [code]

Header file of RNG HAL module.

file | stm32l4xx_hal_rtc.h [code]

Header file of RTC HAL module.

file | stm32l4xx_hal_rtc_ex.h [code]

Header file of RTC HAL Extended module.

file | stm32l4xx_hal_sai.h [code]

Header file of SAI HAL module.

file | stm32l4xx_hal_sd.h [code]

Header file of SD HAL module.

file | stm32l4xx_hal_smartcard.h [code]

Header file of SMARTCARD HAL module.

file | stm32l4xx_hal_smartcard_ex.h [code]

Header file of SMARTCARD HAL Extended module.

file | stm32l4xx_hal_smbus.h [code]

Header file of SMBUS HAL module.

file | stm32l4xx_hal_spi.h [code]

Header file of SPI HAL module.

file | stm32l4xx_hal_spi_ex.h [code]

Header file of SPI HAL Extended module.

file | stm32l4xx_hal_sram.h [code]

Header file of SRAM HAL module.

file | stm32l4xx_hal_swpmi.h [code]

Header file of SWPMI HAL module.

file | stm32l4xx_hal_tim.h [code]

Header file of TIM HAL module.

file | stm32l4xx_hal_tim_ex.h [code]

Header file of TIM HAL Extended module.

file | stm32l4xx_hal_tsc.h [code]

Header file of TSC HAL module.

file | stm32l4xx_hal_uart.h [code]

Header file of UART HAL module.

file | stm32l4xx_hal_uart_ex.h [code]

Header file of UART HAL Extended module.

file | stm32l4xx_hal_usart.h [code]

Header file of USART HAL module.

file | stm32l4xx_hal_usart_ex.h [code]

Header file of USART HAL Extended module.

file | stm32l4xx_hal_wwdg.h [code]

Header file of WWDG HAL module.

file | stm32l4xx_ll_adc.h [code]

Header file of ADC LL module.

file | stm32l4xx_ll_bus.h [code]

Header file of BUS LL module.

file | stm32l4xx_ll_comp.h [code]

Header file of COMP LL module.

file | stm32l4xx_ll_cortex.h [code]

Header file of CORTEX LL module.

file | stm32l4xx_ll_crc.h [code]

Header file of CRC LL module.

file | stm32l4xx_ll_crs.h [code]

CRS LL module driver.

file | stm32l4xx_ll_dac.h [code]

Header file of DAC LL module.

file | stm32l4xx_ll_dma.h [code]

Header file of DMA LL module.

file | stm32l4xx_ll_exti.h [code]

Header file of EXTI LL module.

file | stm32l4xx_ll_gpio.h [code]

Header file of GPIO LL module.

file | stm32l4xx_ll_i2c.h [code]

Header file of I2C LL module.

file | stm32l4xx_ll_iwdg.h [code]

Header file of IWDG LL module.

file | stm32l4xx_ll_lptim.h [code]

Header file of LPTIM LL module.

file | stm32l4xx_ll_lpuart.h [code]

Header file of LPUART LL module.

file | stm32l4xx_ll_opamp.h [code]

Header file of OPAMP LL module.

file | stm32l4xx_ll_pwr.h [code]

Header file of PWR LL module.

file | stm32l4xx_ll_rcc.h [code]

Header file of RCC LL module.

file | stm32l4xx_ll_rng.h [code]

Header file of RNG LL module.

file | stm32l4xx_ll_rtc.h [code]

Header file of RTC LL module.

file | stm32l4xx_ll_spi.h [code]

Header file of SPI LL module.

file | stm32l4xx_ll_swpmi.h [code]

Header file of SWPMI LL module.

file | stm32l4xx_ll_system.h [code]

Header file of SYSTEM LL module.

file | stm32l4xx_ll_tim.h [code]

Header file of TIM LL module.

file | stm32l4xx_ll_usart.h [code]

Header file of USART LL module.

file | stm32l4xx_ll_utils.h [code]

Header file of UTILS LL module.

file | stm32l4xx_ll_wwdg.h [code]

Header file of WWDG LL module.

Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: X:/Drivers/ Directory Reference

  • Drivers
Drivers Directory Reference

Directories

directory STM32L4xx_HAL_Driver
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: X:/Drivers/STM32L4xx_HAL_Driver/Src/ Directory Reference

  • Drivers
  • STM32L4xx_HAL_Driver
  • Src
Src Directory Reference

Files

file | stm32l4xx_hal.c [code]

HAL module driver. This is the common part of the HAL initialization.

file | stm32l4xx_hal_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Configuration of ADC + Operation functions ++ Start, stop, get result of regular conversions of regular using 3 possible modes: polling, interruption or DMA. + Control functions ++ Analog Watchdog configuration ++ Channels configuration on regular group + State functions ++ ADC state machine management ++ Interrupts and flags management.

file | stm32l4xx_hal_adc_ex.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Calibration functions ++ Calibration start-up ++ Calibration value reading or setting + Operation functions ++ Start, stop, get result of conversions of injected groups, using 3 possible modes: polling or interruption. ++ Multimode feature when available + Control functions ++ Configure channels on injected group + State functions ++ Injected group queues management.

file | stm32l4xx_hal_can.c [code]

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32l4xx_hal_comp.c [code]

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode (through EXTI interrupt) + Peripheral control functions + Peripheral state functions.

file | stm32l4xx_hal_cortex.c [code]

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions.

file | stm32l4xx_hal_crc.c [code]

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the CRC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32l4xx_hal_crc_ex.c [code]

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

file | stm32l4xx_hal_cryp.c [code]

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + Processing functions using polling mode + Processing functions using interrupt mode + Processing functions using DMA mode + Peripheral State functions.

file | stm32l4xx_hal_cryp_ex.c [code]

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral.

file | stm32l4xx_hal_dac.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32l4xx_hal_dac_ex.c [code]

DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral.

file | stm32l4xx_hal_dfsdm.c [code]

This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event.

file | stm32l4xx_hal_dma.c [code]

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

file | stm32l4xx_hal_firewall.c [code]

FIREWALL HAL module driver. This file provides firmware functions to manage the Firewall Peripheral initialization and enabling.

file | stm32l4xx_hal_flash.c [code]

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

file | stm32l4xx_hal_flash_ex.c [code]

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions.

file | stm32l4xx_hal_flash_ramfunc.c [code]

FLASH RAMFUNC driver. This file provides a Flash firmware functions which should be executed from internal SRAM + FLASH HalfPage Programming + FLASH Power Down in Run mode.

file | stm32l4xx_hal_gpio.c [code]

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32l4xx_hal_hcd.c [code]

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32l4xx_hal_i2c.c [code]

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32l4xx_hal_i2c_ex.c [code]

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

file | stm32l4xx_hal_irda.c [code]

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

file | stm32l4xx_hal_iwdg.c [code]

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

file | stm32l4xx_hal_lcd.c [code]

LCD Controller HAL module driver. This file provides firmware functions to manage the following functionalities of the LCD Controller (LCD) peripheral: + Initialization/de-initialization methods + I/O operation methods + Peripheral State methods.

file | stm32l4xx_hal_lptim.c [code]

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

file | stm32l4xx_hal_nand.c [code]

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

file | stm32l4xx_hal_nor.c [code]

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

file | stm32l4xx_hal_opamp.c [code]

OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32l4xx_hal_opamp_ex.c [code]

Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

file | stm32l4xx_hal_pcd.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32l4xx_hal_pcd_ex.c [code]

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

file | stm32l4xx_hal_pwr.c [code]

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions.

file | stm32l4xx_hal_pwr_ex.c [code]

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

file | stm32l4xx_hal_qspi.c [code]

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality.

file | stm32l4xx_hal_rcc.c [code]

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32l4xx_hal_rcc_ex.c [code]

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions.

file | stm32l4xx_hal_rng.c [code]

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32l4xx_hal_rtc.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

file | stm32l4xx_hal_rtc_ex.c [code]

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

file | stm32l4xx_hal_sai.c [code]

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32l4xx_hal_sd.c [code]

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32l4xx_hal_smartcard.c [code]

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32l4xx_hal_smartcard_ex.c [code]

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32l4xx_hal_smbus.c [code]

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32l4xx_hal_spi.c [code]

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32l4xx_hal_spi_ex.c [code]

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions.

file | stm32l4xx_hal_sram.c [code]

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

file | stm32l4xx_hal_swpmi.c [code]

SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management.

file | stm32l4xx_hal_tim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

file | stm32l4xx_hal_tim_ex.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

file | stm32l4xx_hal_tsc.c [code]

This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management.

file | stm32l4xx_hal_uart.c [code]

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32l4xx_hal_uart_ex.c [code]

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32l4xx_hal_usart.c [code]

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32l4xx_hal_wwdg.c [code]

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions.

file | stm32l4xx_ll_adc.c [code]

ADC LL module driver.

file | stm32l4xx_ll_comp.c [code]

COMP LL module driver.

file | stm32l4xx_ll_crc.c [code]

CRC LL module driver.

file | stm32l4xx_ll_crs.c [code]
file | stm32l4xx_ll_dac.c [code]

DAC LL module driver.

file | stm32l4xx_ll_dma.c [code]

DMA LL module driver.

file | stm32l4xx_ll_exti.c [code]

EXTI LL module driver.

file | stm32l4xx_ll_gpio.c [code]

GPIO LL module driver.

file | stm32l4xx_ll_i2c.c [code]

I2C LL module driver.

file | stm32l4xx_ll_lptim.c [code]

LPTIM LL module driver.

file | stm32l4xx_ll_lpuart.c [code]

LPUART LL module driver.

file | stm32l4xx_ll_opamp.c [code]

OPAMP LL module driver.

file | stm32l4xx_ll_pwr.c [code]

PWR LL module driver.

file | stm32l4xx_ll_rcc.c [code]

RCC LL module driver.

file | stm32l4xx_ll_rng.c [code]

RNG LL module driver.

file | stm32l4xx_ll_rtc.c [code]

RTC LL module driver.

file | stm32l4xx_ll_spi.c [code]

SPI LL module driver.

file | stm32l4xx_ll_swpmi.c [code]

SWPMI LL module driver.

file | stm32l4xx_ll_tim.c [code]

TIM LL module driver.

file | stm32l4xx_ll_usart.c [code]

USART LL module driver.

file | stm32l4xx_ll_utils.c [code]

UTILS LL module driver.

Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: X:/Drivers/STM32L4xx_HAL_Driver/ Directory Reference

  • Drivers
  • STM32L4xx_HAL_Driver
STM32L4xx_HAL_Driver Directory Reference

Directories

directory | Inc
directory | Src
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • Drivers
    • STM32L4xx_HAL_Driver
      • Inc
      • Src
Generated on Wed Jun 1 2016 16:28:32 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA_rmtollPages.txt File Reference

  • File List
  • Globals
DMA_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: EXTI_rmtollPages.txt File Reference

  • File List
  • Globals
EXTI_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm32l4xx_hal.c [code] | HAL module driver. This is the common part of the HAL initialization
stm32l4xx_hal.h [code] | This file contains all the functions prototypes for the HAL module driver
stm32l4xx_hal_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Configuration of ADC + Operation functions ++ Start, stop, get result of regular conversions of regular using 3 possible modes: polling, interruption or DMA. + Control functions ++ Analog Watchdog configuration ++ Channels configuration on regular group + State functions ++ ADC state machine management ++ Interrupts and flags management
stm32l4xx_hal_adc.h [code] | Header file of ADC HAL module
stm32l4xx_hal_adc_ex.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Calibration functions ++ Calibration start-up ++ Calibration value reading or setting + Operation functions ++ Start, stop, get result of conversions of injected groups, using 3 possible modes: polling or interruption. ++ Multimode feature when available + Control functions ++ Configure channels on injected group + State functions ++ Injected group queues management
stm32l4xx_hal_adc_ex.h [code] | Header file of ADC HAL extended module
stm32l4xx_hal_can.c [code] | CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32l4xx_hal_can.h [code] | Header file of CAN HAL module
stm32l4xx_hal_comp.c [code] | COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode (through EXTI interrupt) + Peripheral control functions + Peripheral state functions
stm32l4xx_hal_comp.h [code] | Header file of COMP HAL module
stm32l4xx_hal_conf.h [code] | HAL configuration template file. This file should be copied to the application folder and renamed to stm32l4xx_hal_conf.h
stm32l4xx_hal_cortex.c [code] | CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions
stm32l4xx_hal_cortex.h [code] | Header file of CORTEX HAL module
stm32l4xx_hal_crc.c [code] | CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the CRC peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32l4xx_hal_crc.h [code] | Header file of CRC HAL module
stm32l4xx_hal_crc_ex.c [code] | Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral
stm32l4xx_hal_crc_ex.h [code] | Header file of CRC HAL extended module
stm32l4xx_hal_cryp.c [code] | CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization and de-initialization functions + Processing functions using polling mode + Processing functions using interrupt mode + Processing functions using DMA mode + Peripheral State functions
stm32l4xx_hal_cryp.h [code] | Header file of CRYP HAL module
stm32l4xx_hal_cryp_ex.c [code] | CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral
stm32l4xx_hal_cryp_ex.h [code] | Header file of CRYPEx HAL module
stm32l4xx_hal_dac.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32l4xx_hal_dac.h [code] | Header file of DAC HAL module
stm32l4xx_hal_dac_ex.c [code] | DAC HAL module driver. This file provides firmware functions to manage the extended functionalities of the DAC peripheral
stm32l4xx_hal_dac_ex.h [code] | Header file of DAC HAL Extended module
stm32l4xx_hal_dfsdm.c [code] | This file provides firmware functions to manage the following functionalities of the Digital Filter for Sigma-Delta Modulators (DFSDM) peripherals: + Initialization and configuration of channels and filters + Regular channels configuration + Injected channels configuration + Regular/Injected Channels DMA Configuration + Interrupts and flags management + Analog watchdog feature + Short-circuit detector feature + Extremes detector feature + Clock absence detector feature + Break generation on analog watchdog or short-circuit event
stm32l4xx_hal_dfsdm.h [code] | Header file of DFSDM HAL module
stm32l4xx_hal_dma.c [code] | DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions
stm32l4xx_hal_dma.h [code] | Header file of DMA HAL module
stm32l4xx_hal_firewall.c [code] | FIREWALL HAL module driver. This file provides firmware functions to manage the Firewall Peripheral initialization and enabling
stm32l4xx_hal_firewall.h [code] | Header file of FIREWALL HAL module
stm32l4xx_hal_flash.c [code] | FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions
stm32l4xx_hal_flash.h [code] | Header file of FLASH HAL module
stm32l4xx_hal_flash_ex.c [code] | Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions
stm32l4xx_hal_flash_ex.h [code] | Header file of FLASH HAL Extended module
stm32l4xx_hal_flash_ramfunc.c [code] | FLASH RAMFUNC driver. This file provides a Flash firmware functions which should be executed from internal SRAM + FLASH HalfPage Programming + FLASH Power Down in Run mode
stm32l4xx_hal_flash_ramfunc.h [code] | Header file of FLASH RAMFUNC driver
stm32l4xx_hal_gpio.c [code] | GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32l4xx_hal_gpio.h [code] | Header file of GPIO HAL module
stm32l4xx_hal_gpio_ex.h [code] | Header file of GPIO HAL Extended module
stm32l4xx_hal_hcd.c [code] | HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32l4xx_hal_hcd.h [code] | Header file of HCD HAL module
stm32l4xx_hal_i2c.c [code] | I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32l4xx_hal_i2c.h [code] | Header file of I2C HAL module
stm32l4xx_hal_i2c_ex.c [code] | I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions
stm32l4xx_hal_i2c_ex.h [code] | Header file of I2C HAL Extended module
stm32l4xx_hal_irda.c [code] | IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions
stm32l4xx_hal_irda.h [code] | Header file of IRDA HAL module
stm32l4xx_hal_irda_ex.h [code] | Header file of IRDA HAL Extended module
stm32l4xx_hal_iwdg.c [code] | IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions
stm32l4xx_hal_iwdg.h [code] | Header file of IWDG HAL module
stm32l4xx_hal_lcd.c [code] | LCD Controller HAL module driver. This file provides firmware functions to manage the following functionalities of the LCD Controller (LCD) peripheral: + Initialization/de-initialization methods + I/O operation methods + Peripheral State methods
stm32l4xx_hal_lcd.h [code] | Header file of LCD Controller HAL module
stm32l4xx_hal_lptim.c [code] | LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions
stm32l4xx_hal_lptim.h [code] | Header file of LPTIM HAL module
stm32l4xx_hal_nand.c [code] | NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device
stm32l4xx_hal_nand.h [code] | Header file of NAND HAL module
stm32l4xx_hal_nor.c [code] | NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device
stm32l4xx_hal_nor.h [code] | Header file of NOR HAL module
stm32l4xx_hal_opamp.c [code] | OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s) peripheral: + OPAMP configuration + OPAMP calibration Thanks to + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32l4xx_hal_opamp.h [code] | Header file of OPAMP HAL module
stm32l4xx_hal_opamp_ex.c [code] | Extended OPAMP HAL module driver. This file provides firmware functions to manage the following functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions
stm32l4xx_hal_opamp_ex.h [code] | Header file of OPAMP HAL Extended module
stm32l4xx_hal_pcd.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32l4xx_hal_pcd.h [code] | Header file of PCD HAL module
stm32l4xx_hal_pcd_ex.c [code] | PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions
stm32l4xx_hal_pcd_ex.h [code] | Header file of PCD HAL module
stm32l4xx_hal_pwr.c [code] | PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions
stm32l4xx_hal_pwr.h [code] | Header file of PWR HAL module
stm32l4xx_hal_pwr_ex.c [code] | Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions
stm32l4xx_hal_pwr_ex.h [code] | Header file of PWR HAL Extended module
stm32l4xx_hal_qspi.c [code] | QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality
stm32l4xx_hal_qspi.h [code] | Header file of QSPI HAL module
stm32l4xx_hal_rcc.c [code] | RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32l4xx_hal_rcc.h [code] | Header file of RCC HAL module
stm32l4xx_hal_rcc_ex.c [code] | Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions
stm32l4xx_hal_rcc_ex.h [code] | Header file of RCC HAL Extended module
stm32l4xx_hal_rng.c [code] | RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32l4xx_hal_rng.h [code] | Header file of RNG HAL module
stm32l4xx_hal_rtc.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management
stm32l4xx_hal_rtc.h [code] | Header file of RTC HAL module
stm32l4xx_hal_rtc_ex.c [code] | Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions
stm32l4xx_hal_rtc_ex.h [code] | Header file of RTC HAL Extended module
stm32l4xx_hal_sai.c [code] | SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions
stm32l4xx_hal_sai.h [code] | Header file of SAI HAL module
stm32l4xx_hal_sd.c [code] | SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32l4xx_hal_sd.h [code] | Header file of SD HAL module
stm32l4xx_hal_smartcard.c [code] | SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32l4xx_hal_smartcard.h [code] | Header file of SMARTCARD HAL module
stm32l4xx_hal_smartcard_ex.c [code] | SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions
stm32l4xx_hal_smartcard_ex.h [code] | Header file of SMARTCARD HAL Extended module
stm32l4xx_hal_smbus.c [code] | SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32l4xx_hal_smbus.h [code] | Header file of SMBUS HAL module
stm32l4xx_hal_spi.c [code] | SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32l4xx_hal_spi.h [code] | Header file of SPI HAL module
stm32l4xx_hal_spi_ex.c [code] | Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions
stm32l4xx_hal_spi_ex.h [code] | Header file of SPI HAL Extended module
stm32l4xx_hal_sram.c [code] | SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device
stm32l4xx_hal_sram.h [code] | Header file of SRAM HAL module
stm32l4xx_hal_swpmi.c [code] | SWPMI HAL module driver. This file provides firmware functions to manage the following functionalities of the Single Wire Protocol Master Interface (SWPMI). + Initialization and Configuration + Data transfers functions + DMA transfers management + Interrupts and flags management
stm32l4xx_hal_swpmi.h [code] | Header file of SWPMI HAL module
stm32l4xx_hal_tim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration
stm32l4xx_hal_tim.h [code] | Header file of TIM HAL module
stm32l4xx_hal_tim_ex.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration
stm32l4xx_hal_tim_ex.h [code] | Header file of TIM HAL Extended module
stm32l4xx_hal_tsc.c [code] | This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management
stm32l4xx_hal_tsc.h [code] | Header file of TSC HAL module
stm32l4xx_hal_uart.c [code] | UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32l4xx_hal_uart.h [code] | Header file of UART HAL module
stm32l4xx_hal_uart_ex.c [code] | Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions
stm32l4xx_hal_uart_ex.h [code] | Header file of UART HAL Extended module
stm32l4xx_hal_usart.c [code] | USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32l4xx_hal_usart.h [code] | Header file of USART HAL module
stm32l4xx_hal_usart_ex.h [code] | Header file of USART HAL Extended module
stm32l4xx_hal_wwdg.c [code] | WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration function + IO operation functions
stm32l4xx_hal_wwdg.h [code] | Header file of WWDG HAL module
stm32l4xx_ll_adc.c [code] | ADC LL module driver
stm32l4xx_ll_adc.h [code] | Header file of ADC LL module
stm32l4xx_ll_bus.h [code] | Header file of BUS LL module
stm32l4xx_ll_comp.c [code] | COMP LL module driver
stm32l4xx_ll_comp.h [code] | Header file of COMP LL module
stm32l4xx_ll_cortex.h [code] | Header file of CORTEX LL module
stm32l4xx_ll_crc.c [code] | CRC LL module driver
stm32l4xx_ll_crc.h [code] | Header file of CRC LL module
stm32l4xx_ll_crs.c [code] |
stm32l4xx_ll_crs.h [code] | CRS LL module driver
stm32l4xx_ll_dac.c [code] | DAC LL module driver
stm32l4xx_ll_dac.h [code] | Header file of DAC LL module
stm32l4xx_ll_dma.c [code] | DMA LL module driver
stm32l4xx_ll_dma.h [code] | Header file of DMA LL module
stm32l4xx_ll_exti.c [code] | EXTI LL module driver
stm32l4xx_ll_exti.h [code] | Header file of EXTI LL module
stm32l4xx_ll_gpio.c [code] | GPIO LL module driver
stm32l4xx_ll_gpio.h [code] | Header file of GPIO LL module
stm32l4xx_ll_i2c.c [code] | I2C LL module driver
stm32l4xx_ll_i2c.h [code] | Header file of I2C LL module
stm32l4xx_ll_iwdg.h [code] | Header file of IWDG LL module
stm32l4xx_ll_lptim.c [code] | LPTIM LL module driver
stm32l4xx_ll_lptim.h [code] | Header file of LPTIM LL module
stm32l4xx_ll_lpuart.c [code] | LPUART LL module driver
stm32l4xx_ll_lpuart.h [code] | Header file of LPUART LL module
stm32l4xx_ll_opamp.c [code] | OPAMP LL module driver
stm32l4xx_ll_opamp.h [code] | Header file of OPAMP LL module
stm32l4xx_ll_pwr.c [code] | PWR LL module driver
stm32l4xx_ll_pwr.h [code] | Header file of PWR LL module
stm32l4xx_ll_rcc.c [code] | RCC LL module driver
stm32l4xx_ll_rcc.h [code] | Header file of RCC LL module
stm32l4xx_ll_rng.c [code] | RNG LL module driver
stm32l4xx_ll_rng.h [code] | Header file of RNG LL module
stm32l4xx_ll_rtc.c [code] | RTC LL module driver
stm32l4xx_ll_rtc.h [code] | Header file of RTC LL module
stm32l4xx_ll_spi.c [code] | SPI LL module driver
stm32l4xx_ll_spi.h [code] | Header file of SPI LL module
stm32l4xx_ll_swpmi.c [code] | SWPMI LL module driver
stm32l4xx_ll_swpmi.h [code] | Header file of SWPMI LL module
stm32l4xx_ll_system.h [code] | Header file of SYSTEM LL module
stm32l4xx_ll_tim.c [code] | TIM LL module driver
stm32l4xx_ll_tim.h [code] | Header file of TIM LL module
stm32l4xx_ll_usart.c [code] | USART LL module driver
stm32l4xx_ll_usart.h [code] | Header file of USART LL module
stm32l4xx_ll_utils.c [code] | UTILS LL module driver
stm32l4xx_ll_utils.h [code] | Header file of UTILS LL module
stm32l4xx_ll_wwdg.h [code] | Header file of WWDG LL module
Generated on Wed Jun 1 2016 16:28:30 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO_rmtollPages.txt File Reference

  • File List
  • Globals
GPIO_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC

Modules
ADC
STM32L4xx_HAL_Driver

ADC HAL module driver. More...

Modules

ADC Private Constants
ADC Exported Functions
ADC Private Functions
ADC Exported Types
ADC Exported Constants
ADC Private Macros
ADC Exported Macros

Detailed Description

ADC HAL module driver.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC Error Code
ADC Clock Prescaler
ADC Resolution
ADC Data Alignment
ADC Scan Mode
ADC External Trigger Source Edge for Regular Group
ADC External Trigger Source for Regular Group
ADC End of Regular Sequence/Conversion
ADC overrun
ADC Channels
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

ADC Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Exported Types

Data Structures | Modules
ADC Exported Types
ADC

Data Structures

struct | ADC_OversamplingTypeDef
ADC Regular Conversion Oversampling structure definition. More...
struct | ADC_InjectionConfigTypeDef
ADC Injection Configuration. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...

Modules

ADC States
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STM32L486xx HAL User Manual: ADC Exported Init structure

Data Structures
ADC Exported Init structure
ADC

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...
Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC flags

Flags defines which can be used with LL_ADC_ReadReg function.

ADC interruptions for configuration (interruption enable or disable)

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

ADC registers compliant with specific purpose
ADC common - Clock source
ADC common - Measurement path to internal channels
ADC instance - Resolution
ADC instance - Data alignment
ADC instance - Low power mode
ADC instance - Offset number
ADC instance - Offset state
ADC instance - Groups
ADC instance - Channel number
ADC group regular - Trigger source
ADC group regular - Trigger edge
ADC group regular - Continuous mode
ADC group regular - DMA transfer of ADC conversion data
ADC group regular - Overrun behavior on conversion data
ADC group regular - Sequencer scan length
ADC group regular - Sequencer discontinuous mode
ADC group regular - Sequencer ranks
ADC group injected - Trigger source
ADC group injected - Trigger edge
ADC group injected - Automatic trigger mode
ADC group injected - Context queue mode
ADC group injected - Sequencer scan length
ADC group injected - Sequencer discontinuous mode
ADC group injected - Sequencer ranks
Channel - Sampling time
Channel - Single or differential ending
Analog watchdog - Analog watchdog number
Analog watchdog - Monitored channels
Analog watchdog - Thresholds
Oversampling - Oversampling scope
Oversampling - Discontinuous mode
Oversampling - Ratio
Oversampling - Data shift
Multimode - Mode
Multimode - DMA transfer
Multimode - Delay between two sampling phases
Multimode - ADC master or slave
ADC literals legacy naming
Definitions of ADC hardware constraints delays
Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

ADC DMA management
Configuration of ADC hierarchical scope: common to several ADC instances
Configuration of ADC hierarchical scope: ADC instance
Configuration of ADC hierarchical scope: group regular
Configuration of ADC hierarchical scope: group injected
Configuration of ADC hierarchical scope: channels
Configuration of ADC transversal scope: analog watchdog
Configuration of ADC transversal scope: oversampling
Configuration of ADC hierarchical scope: multimode
Configuration of ADC alternate functions name
Operation on ADC hierarchical scope: ADC instance
Operation on ADC hierarchical scope: group regular
Operation on ADC hierarchical scope: group injected
ADC flag management
ADC IT management
Initialization and de-initialization functions
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC

Modules

Common write and read registers Macros
ADC helper macro
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STM32L486xx HAL User Manual: ADCEx

Modules
ADCEx
STM32L4xx_HAL_Driver

ADC Extended HAL module driver. More...

Modules

ADC Extended Private Constants
ADC Extended Exported Functions
ADC Extended Exported Types
ADC Extended Exported Constants
ADC Extended Private Macros

Detailed Description

ADC Extended HAL module driver.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Extended Exported Constants

Modules
ADC Extended Exported Constants
ADCEx

Modules

ADC Extended Single-ended/Differential input mode
ADC Extended Offset Number
ADC Extended Regular Channel Rank
ADC Extended Injected Channel Rank
ADC External Trigger Source Edge for Injected Group
ADC Extended External Trigger Source for Injected Group
ADC Extended Dual ADC Mode
ADC Extended DMA Mode for Dual ADC Mode
ADC Extended Delay Between 2 Sampling Phases
ADC Extended Analog Watchdog Selection
ADC Extended Analog Watchdog Mode
ADC Extended Conversion Group
ADC Extended Event Type
ADC Extended Interrupts Definition
ADC Extended Flags Definition
ADC Extended Oversampling Ratio
ADC Extended Oversampling Right Shift
ADC Extended Triggered Regular Oversampling
ADC Extended Regular Oversampling Continued or Resumed Mode
ADC Sampling Times
ADCx CFGR fields
ADCx SMPR1 fields
ADCx CFGR sub fields
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Extended Exported Functions

Modules
ADC Extended Exported Functions
ADCEx

Modules

Extended Input and Output operation functions

Extended IO operation functions.

Extended Peripheral Control functions

Extended Peripheral Control functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: ADC Extended Exported Types

Data Structures
ADC Extended Exported Types
ADCEx

Data Structures

struct | ADC_InitTypeDef
Structure definition of ADC initialization and regular group. More...
struct | ADC_HandleTypeDef
ADC handle Structure definition. More...
struct | ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition. More...
struct | ADC_InjectionConfTypeDef
Structure definition of ADC injected group and ADC channel for injected group. More...
struct | ADC_MultiModeTypeDef
Structure definition of ADC multimode. More...
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: BUS Exported Constants

Modules
BUS Exported Constants
BUS

Modules

AHB1 GRP1 PERIPH
AHB2 GRP1 PERIPH
AHB3 GRP1 PERIPH
APB1 GRP1 PERIPH
APB1 GRP2 PERIPH
APB2 GRP1 PERIPH
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: BUS Exported Functions

Modules
BUS Exported Functions
BUS

Modules

AHB1
AHB2
AHB3
APB1
APB2
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN

Modules
CAN
STM32L4xx_HAL_Driver

CAN driver modules. More...

Modules

CAN Private Constants
CAN Private Functions
CAN Exported Functions
CAN Exported Types
CAN Exported Constants
CAN Exported Macros
CAN Private Macros

Detailed Description

CAN driver modules.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CAN Exported Functions

Modules
CAN Exported Functions
CAN

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

I/O operation functions.

Peripheral State and Error functions

CAN Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP

Modules
COMP
STM32L4xx_HAL_Driver

COMP HAL module driver. More...

Modules

COMP Exported Functions
COMP Exported Types
COMP Exported Constants
COMP Exported Macros
COMP Private Constants
COMP Private Macros

Detailed Description

COMP HAL module driver.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

COMP Window Mode
COMP power mode
COMP input plus (non-inverting input)
COMP input minus (inverting input)
COMP hysteresis
COMP output Polarity
COMP blanking source
COMP Output Level
COMP output to EXTI
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Initialization/de-initialization functions

Initialization and de-initialization functions.

Start-Stop operation functions

Start-Stop operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Exported Macros

Modules
COMP Exported Macros
COMP

Modules

COMP Handle Management
COMP external interrupt line management
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Exported Init structure

Data Structures
COMP Exported Init structure
COMP

Data Structures

struct LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

Comparator common modes - Window mode
Comparator modes - Power mode
Comparator inputs - Input plus (input non-inverting) selection
Comparator inputs - Input minus (input inverting) selection
Comparator inputs legacy literals name
Comparator input - Hysteresis
Comparator output - Output polarity
Comparator output - Blanking source
Comparator output blanking source legacy literals name
Comparator output - Output level
Definitions of COMP hardware constraints delays
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Configuration of COMP hierarchical scope: common to several COMP instances
Configuration of comparator modes
Configuration of comparator inputs
Configuration of comparator output
Configuration of COMP, legacy functions name
Operation on comparator instance
Initialization and de-initialization functions
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Exported Macros

Modules
COMP Exported Macros
COMP

Modules

Common write and read registers macro
COMP helper macro
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: COMP Private Macros

Modules
COMP Private Macros
COMP

Modules

COMP private macros to get EXTI line associated with comparators
COMP private macros to check input parameters
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX

Modules
CORTEX
STM32L4xx_HAL_Driver

Modules

CORTEX Exported Types
CORTEX Exported Constants
CORTEX Exported Macros
CORTEX Exported Functions
CORTEX Private Macros
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

CORTEX Preemption Priority Group
CORTEX SysTick clock source
CORTEX MPU HFNMI and PRIVILEGED Access control
CORTEX MPU Region Enable
CORTEX MPU Instruction Access
CORTEX MPU Instruction Access Shareable
CORTEX MPU Instruction Access Cacheable
CORTEX MPU Instruction Access Bufferable
CORTEX MPU TEX Levels
CORTEX MPU Region Size
CORTEX MPU Region Permission Attributes
CORTEX MPU Region Number
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Peripheral Control functions

Cortex control functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX Exported Types

Modules
CORTEX Exported Types
CORTEX

Modules

MPU Region Initialization Structure Definition
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

SYSTICK Clock Source
Handler Fault type
MPU Control
MPU Region Number
MPU Region Size
MPU Region Privileges
MPU TEX Level
MPU Instruction Access
MPU Shareable Access
MPU Cacheable Access
MPU Bufferable Access
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

SYSTICK
LOW POWER MODE
HANDLER
MCU INFO
MPU
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: MPU Region Initialization Structure Definition

Data Structures
MPU Region Initialization Structure Definition
CORTEX Exported Types

Data Structures

struct MPU_Region_InitTypeDef
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC

Modules
CRC
STM32L4xx_HAL_Driver

CRC HAL module driver. More...

Modules

CRC Private Functions
CRC Exported Functions
CRC Exported Types
CRC Exported Constants
CRC Exported Macros
CRC Private Macros

Detailed Description

CRC HAL module driver.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Default CRC generating polynomial
Default CRC computation initialization value
Indicates whether or not default polynomial is used
Indicates whether or not default init value is used
Polynomial sizes to configure the IP
CRC polynomial possible sizes actual definitions
Input Buffer Format
CRC API aliases
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

management functions.

Peripheral State functions

Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Polynomial length
Input Data Reverse
Output Data Reverse
Default CRC generating polynomial value

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Default CRC computation initialization value
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

CRC Configuration functions
Data_Management
Initialization and de-initialization functions
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRC Exported Macros

Modules
CRC Exported Macros
CRC

Modules

Common Write and read registers Macros
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRCEx

Modules
CRCEx
STM32L4xx_HAL_Driver

CRC Extended HAL module driver. More...

Modules

CRC Extended Exported Functions
CRCEx Exported Constants
CRCEx Exported Macros
CRCEx Private Macros

Detailed Description

CRC Extended HAL module driver.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRCEx Exported Constants

Modules
CRCEx Exported Constants
CRCEx

Modules

Input Data Inversion Modes
Output Data Inversion Modes
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STM32L486xx HAL User Manual: CRC Extended Exported Functions

Modules
CRC Extended Exported Functions
CRCEx

Modules

Extended Initialization/de-initialization functions

Extended Initialization and Configuration functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYP

Modules
CRYP
STM32L4xx_HAL_Driver

CRYP HAL module driver. More...

Modules

CRYP Private Functions
CRYP Exported Functions
CRYP Exported Types
CRYP Exported Constants
CRYP Exported Macros
CRYP Private Macros

Detailed Description

CRYP HAL module driver.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYP Exported Constants

Modules
CRYP Exported Constants
CRYP

Modules

Key size selection
AES Data Type selection
AES Enable state
AES operating mode
AES chaining mode
AES decryption key write-up flag
DMA Input phase management enable state
DMA Output phase management enable state
GCM/GMAC and CMAC processing phase selection
AES status flags
AES clearing flags
AES Interrupts Enable bits
AES Interrupts flags
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYP Exported Functions

Modules
CRYP Exported Functions
CRYP

Modules

Initialization and deinitialization functions

Initialization and Configuration functions.

AES processing functions

Processing functions.

Callback functions

Callback functions.

CRYP IRQ handler

AES IRQ handler.

Peripheral State functions

Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYPEx

Modules
CRYPEx
STM32L4xx_HAL_Driver

CRYP Extended HAL module driver. More...

Modules

CRYPEx Private Constants
CRYPEx Private Functions
CRYPEx Exported Functions

Detailed Description

CRYP Extended HAL module driver.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: CRYPEx Exported Functions

Modules
CRYPEx Exported Functions
CRYPEx

Modules

Extended callback function

Extended callback functions.

AES extended processing functions

Extended processing functions.

AES suspension/resumption functions

Extended processing functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC

Modules
DAC
STM32L4xx_HAL_Driver

DAC driver modules. More...

Modules

DAC Private Functions
DAC Exported Functions
DAC Exported Types
DAC Exported Constants
DAC Exported Macros
DAC Private Macros
DAC Private Constants

Detailed Description

DAC driver modules.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC Error Code
DAC trigger selection
DAC output buffer
DAC Channel selection
DAC data alignment
DAC flags definition
DAC IT definition
DAC ConnectOnChipPeripheral
DAC User Trimming
DAC power mode
Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Exported Init structure

Data Structures
DAC Exported Init structure
DAC

Data Structures

struct LL_DAC_InitTypeDef
Structure definition of some features of DAC instance. More...
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STM32L486xx HAL User Manual: DAC Exported Constants

Modules
DAC Exported Constants
DAC

Modules

DAC flags

Flags defines which can be used with LL_DAC_ReadReg function.

DAC interruptions

IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions.

DAC channels
DAC operating mode
DAC trigger source
DAC waveform automatic generation mode
DAC wave generation - Noise LFSR unmask bits
DAC wave generation - Triangle amplitude
DAC channel output mode
DAC channel output buffer
DAC channel output connection
DAC literals legacy naming
DAC channel output resolution
DAC registers compliant with specific purpose
Definitions of DAC hardware constraints delays
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Exported Functions

Modules
DAC Exported Functions
DAC

Modules

Configuration of DAC channels
DAC configuration, legacy functions name
DMA Management
Operation on DAC channels
FLAG Management
IT management
Initialization and de-initialization functions
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DAC Exported Macros

Modules
DAC Exported Macros
DAC

Modules

Common write and read registers macros
DAC helper macro
Generated on Wed Jun 1 2016 16:28:24 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DACEx

Modules
DACEx
STM32L4xx_HAL_Driver

DAC Extended HAL module driver. More...

Modules

DACEx Exported Functions
DACEx private functions

Extended private functions.

DACEx Exported Constants

HAL State structures definition.

DACEx Private Macros

Detailed Description

DAC Extended HAL module driver.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DACEx Exported Constants

Modules
DACEx Exported Constants
DACEx

HAL State structures definition. More...

Modules

DACEx lfsrunmask triangleamplitude

Detailed Description

HAL State structures definition.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DACEx Exported Functions

Modules
DACEx Exported Functions
DACEx

Modules

IO operation functions

Extended IO operation functions.

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM

Modules
DFSDM
STM32L4xx_HAL_Driver

DFSDM HAL driver module. More...

Modules

DFSDM Private Define
DFSDM Private Variables
DFSDM Private Functions
DFSDM Exported Functions
DFSDM Exported Types
DFSDM Exported Constants
DFSDM Exported Macros
DFSDM Private Macros

Detailed Description

DFSDM HAL driver module.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DFSDM Exported Constants

Modules
DFSDM Exported Constants
DFSDM

Modules

DFSDM channel output clock selection
DFSDM channel input multiplexer
DFSDM channel input data packing
DFSDM channel input pins
DFSDM channel serial interface type
DFSDM channel SPI clock selection
DFSDM channel analog watchdog filter order
DFSDM filter conversion trigger
DFSDM filter external trigger
DFSDM filter external trigger edge
DFSDM filter sinc order
DFSDM filter analog watchdog data source
DFSDM filter error code
DFSDM break signals
DFSDM Channel Selection
DFSDM Continuous Mode
DFSDM analog watchdog threshold
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STM32L486xx HAL User Manual: DFSDM Exported Functions

Modules
DFSDM Exported Functions
DFSDM

Modules

Channel initialization and de-initialization functions

Channel initialization and de-initialization functions.

Channel operation functions

Channel operation functions.

Channel state function

Channel state function.

Filter initialization and de-initialization functions

Filter initialization and de-initialization functions.

Filter control functions

Filter control functions.

Filter operation functions

Filter operation functions.

Filter state functions

Filter state functions.

Generated on Wed Jun 1 2016 16:28:18 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA

Modules
DMA
STM32L4xx_HAL_Driver

DMA HAL module driver. More...

Modules

DMA Private Functions
DMA Exported Functions
DMA Exported Types
DMA Exported Constants
DMA Exported Macros
DMA Private Macros

Detailed Description

DMA HAL module driver.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

DMA Error Code
DMA request
DMA Data transfer direction
DMA Peripheral incremented mode
DMA Memory incremented mode
DMA Peripheral data size
DMA Memory data size
DMA mode
DMA Priority level
DMA interrupt enable definitions
DMA flag definitions
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STM32L486xx HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

Input and Output operation functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: DMA Exported Init structure

Data Structures
DMA Exported Init structure
DMA

Data Structures

struct LL_DMA_InitTypeDef
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STM32L486xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

Clear Flags Defines

Flags defines which can be used with LL_DMA_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_DMA_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

CHANNEL
Transfer Direction
Transfer mode
Peripheral increment mode
Memory increment mode
Peripheral data alignment
Memory data alignment
Transfer Priority level
Transfer peripheral request
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STM32L486xx HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Configuration
FLAG_Management
IT_Management
Initialization and de-initialization functions
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STM32L486xx HAL User Manual: DMA Exported Macros

Modules
DMA Exported Macros
DMA

Modules

Common Write and read registers macros
Convert DMAxChannely
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STM32L486xx HAL User Manual: EXTI Exported Init structure

Data Structures
EXTI Exported Init structure
EXTI

Data Structures

struct LL_EXTI_InitTypeDef
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STM32L486xx HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

LINE
Mode
Edge Trigger
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STM32L486xx HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

Modules

IT_Management
Event_Management
Rising_Trigger_Management
Falling_Trigger_Management
Software_Interrupt_Management
Flag_Management
Initialization and de-initialization functions
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STM32L486xx HAL User Manual: EXTI Exported Macros

Modules
EXTI Exported Macros
EXTI

Modules

Common Write and read registers Macros
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STM32L486xx HAL User Manual: FIREWALL

Modules
FIREWALL
STM32L4xx_HAL_Driver

HAL FIREWALL module driver. More...

Modules

FIREWALL Exported Functions
FIREWALL Exported Types
FIREWALL Exported Constants
FIREWALL Private Macros
FIREWALL Exported Macros

Detailed Description

HAL FIREWALL module driver.

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STM32L486xx HAL User Manual: FIREWALL Exported Constants

Modules
FIREWALL Exported Constants
FIREWALL

Modules

FIREWALL volatile data segment execution status
FIREWALL volatile data segment share status
FIREWALL pre arm status
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STM32L486xx HAL User Manual: FIREWALL Exported Functions

Modules
FIREWALL Exported Functions
FIREWALL

Modules

Initialization Functions

Initialization and Configuration Functions.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FIREWALL Exported Types

Data Structures
FIREWALL Exported Types
FIREWALL

Data Structures

struct FIREWALL_InitTypeDef
FIREWALL Initialization Structure definition. More...
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STM32L486xx HAL User Manual: FLASH

Modules
FLASH
STM32L4xx_HAL_Driver

FLASH HAL module driver. More...

Modules

FLASH Private Variables
FLASH Private Functions
FLASH Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASH Exported Macros

macros to control FLASH features

FLASH Interrupts Macros

macros to handle FLASH interrupts

FLASH Private Constants
FLASH Private Macros

Detailed Description

FLASH HAL module driver.

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STM32L486xx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASH

Modules

FLASH Error
FLASH Erase Type
FLASH Banks
FLASH Program Type
FLASH Option Bytes Type
FLASH WRP Area
FLASH Option Bytes Read Protection
FLASH Option Bytes User Type
FLASH Option Bytes User BOR Level
FLASH Option Bytes User Reset On Stop
FLASH Option Bytes User Reset On Standby
FLASH Option Bytes User Reset On Shutdown
FLASH Option Bytes User IWDG Type
FLASH Option Bytes User IWDG Mode On Stop
FLASH Option Bytes User IWDG Mode On Standby
FLASH Option Bytes User WWDG Type
FLASH Option Bytes User BFB2 Mode
FLASH Option Bytes User Dual-bank Type
FLASH Option Bytes User BOOT1 Type
FLASH Option Bytes User SRAM2 Parity Check Type
FLASH Option Bytes User SRAM2 Erase On Reset Type
FLASH Option Bytes PCROP On RDP Level Type
FLASH Latency
FLASH Keys
FLASH Flags Definition
FLASH Interrupts Definition

FLASH Interrupt definition.

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STM32L486xx HAL User Manual: FLASH Exported Functions

Modules
FLASH Exported Functions
FLASH

Modules

Programming operation functions

Programming operation functions.

Peripheral Control functions

Management functions.

Peripheral State and Errors functions

Peripheral Errors functions.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: FLASH_RAMFUNC

Modules
FLASH_RAMFUNC
STM32L4xx_HAL_Driver

FLASH functions executed from RAM. More...

Modules

FLASH in RAM function Exported Functions

__RAM_FUNC definition

Detailed Description

FLASH functions executed from RAM.

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STM32L486xx HAL User Manual: FLASH in RAM function Exported Functions

Modules
FLASH in RAM function Exported Functions
FLASH_RAMFUNC

__RAM_FUNC definition More...

Modules

Peripheral features functions

Data transfers functions.

Detailed Description

__RAM_FUNC definition

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STM32L486xx HAL User Manual: FLASHEx

Modules
FLASHEx
STM32L4xx_HAL_Driver

FALSH Extended HAL module driver. More...

Modules

FLASHEx Private Variables
FLASHEx Private Functions
FLASH Extended Exported Functions

Detailed Description

FALSH Extended HAL module driver.

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STM32L486xx HAL User Manual: FLASH Extended Exported Functions

Modules
FLASH Extended Exported Functions
FLASHEx

Modules

Extended IO operation functions

Extended IO operation functions.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO

Modules
GPIO
STM32L4xx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIO Private Defines
GPIO Private Macros
GPIO Exported Functions
GPIO Exported Types
GPIO Exported Constants
GPIO Exported Macros

Detailed Description

GPIO HAL module driver.

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STM32L486xx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

GPIO pins
GPIO mode

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

GPIO speed

GPIO Output Maximum frequency.

GPIO pull

GPIO Pull-Up or Pull-Down Activation.

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STM32L486xx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

IO operation functions

GPIO Read, Write, Toggle, Lock and EXTI management functions.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: GPIO Exported Init structures

Data Structures
GPIO Exported Init structures
GPIO

Data Structures

struct LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...
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STM32L486xx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Port Configuration
Data Access
Initialization and de-initialization functions
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STM32L486xx HAL User Manual: GPIO Exported Macros

Modules
GPIO Exported Macros
GPIO

Modules

Common Write and read registers Macros
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STM32L486xx HAL User Manual: GPIOEx

Modules
GPIOEx
STM32L4xx_HAL_Driver

GPIO Extended HAL module driver. More...

Modules

GPIOEx Exported Constants
GPIOEx Exported Macros

Detailed Description

GPIO Extended HAL module driver.

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STM32L486xx HAL User Manual: GPIOEx Exported Constants

Modules
GPIOEx Exported Constants
GPIOEx

Modules

GPIOEx Alternate function selection
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STM32L486xx HAL User Manual: GPIOEx Exported Macros

Modules
GPIOEx Exported Macros
GPIOEx

Modules

GPIOEx_Get Port Index
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STM32L486xx HAL User Manual: HAL Exported Functions

Modules
HAL Exported Functions
HAL

Modules

Initialization and de-initialization Functions

Initialization and de-initialization functions.

HAL Control functions

HAL Control functions.

HAL Debug functions

HAL Debug functions.

HAL SYSCFG configuration functions

HAL SYSCFG configuration functions.

Generated on Wed Jun 1 2016 16:28:17 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HCD

Modules
HCD
STM32L4xx_HAL_Driver

HCD HAL module driver. More...

Modules

HCD Private Functions
HCD Exported Functions
HCD Exported Types
HCD Exported Constants
HCD Exported Macros

macros to handle interrupts and specific clock configurations

HCD Private Macros

Detailed Description

HCD HAL module driver.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: HCD Exported Constants

Modules
HCD Exported Constants
HCD

Modules

HCD Speed
HCD PHY Module
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STM32L486xx HAL User Manual: HCD Exported Functions

Modules
HCD Exported Functions
HCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

HCD IO operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

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STM32L486xx HAL User Manual: HCD Exported Types

Modules
HCD Exported Types
HCD

Modules

HCD State Structure definition
HCD Handle Structure definition
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STM32L486xx HAL User Manual: HCD Handle Structure definition

Data Structures
HCD Handle Structure definition
HCD Exported Types

Data Structures

struct HCD_HandleTypeDef
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STM32L486xx HAL User Manual: I2C Configuration Structure definition

Data Structures
I2C Configuration Structure definition
I2C Exported Types

I2C Configuration Structure definition. More...

Data Structures

struct I2C_InitTypeDef

Detailed Description

I2C Configuration Structure definition.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

I2C Sequential Transfer Options
I2C Addressing Mode
I2C Dual Addressing Mode
I2C Own Address2 Masks
I2C General Call Addressing Mode
I2C No-Stretch Mode
I2C Memory Address Size
I2C Transfer Direction
I2C Reload End Mode
I2C Start or Stop Mode
I2C Interrupt configuration definition

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

I2C Flag definition
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STM32L486xx HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State, Mode and Error functions

Peripheral State, Mode and Error functions.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C Exported Types

Modules
I2C Exported Types
I2C

Modules

I2C Configuration Structure definition

I2C Configuration Structure definition.

HAL state structure definition

HAL State structure definition.

HAL mode structure definition

HAL Mode structure definition.

I2C Error Code definition

I2C Error Code definition.

I2C handle Structure definition

I2C handle Structure definition.

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STM32L486xx HAL User Manual: I2C Exported Init structure

Data Structures
I2C Exported Init structure
I2C

Data Structures

struct LL_I2C_InitTypeDef
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STM32L486xx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

Clear Flags Defines

Flags defines which can be used with LL_I2C_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_I2C_ReadReg function.

IT Defines

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Peripheral Mode
Analog Filter Selection
Master Addressing Mode
Own Address 1 Length
Own Address 2 Masks
Acknowledge Generation
Slave Address Length
Transfer Request Direction
Transfer End Mode
Start And Stop Generation
Read Write Direction
DMA Register Data
SMBus TimeoutA Mode SCL SDA Timeout
SMBus Timeout Selection
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STM32L486xx HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Configuration
IT_Management
FLAG_management
Data_Management
Initialization and de-initialization functions
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STM32L486xx HAL User Manual: I2C Exported Macros

Modules
I2C Exported Macros
I2C

Modules

Common Write and read registers Macros
Convert SDA SCL timings
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STM32L486xx HAL User Manual: I2CEx

Modules
I2CEx
STM32L4xx_HAL_Driver

I2C Extended HAL module driver. More...

Modules

I2C Extended Exported Functions
I2C Extended Exported Constants

Detailed Description

I2C Extended HAL module driver.

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STM32L486xx HAL User Manual: I2C Extended Exported Constants

Modules
I2C Extended Exported Constants
I2CEx

Modules

I2C Extended Analog Filter
I2C Extended Fast Mode Plus
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STM32L486xx HAL User Manual: I2C Extended Exported Functions

Modules
I2C Extended Exported Functions
I2CEx

Modules

Extended features functions

Extended features functions.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA

Modules
IRDA
STM32L4xx_HAL_Driver

HAL IRDA module driver. More...

Modules

IRDA Private Constants
IRDA Exported Functions
IRDA Private Functions
IRDA Exported Types
IRDA Exported Constants
IRDA Exported Macros
IRDA Private Macros

Detailed Description

HAL IRDA module driver.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDA Exported Constants

Modules
IRDA Exported Constants
IRDA

Modules

IRDA Word Length
IRDA Parity
IRDA Transfer Mode
IRDA Low Power
IRDA State
IRDA Mode
IRDA One Bit Sampling
IRDA DMA Tx
IRDA DMA Rx
IRDA Request Parameters
IRDA Flags

Elements values convention: 0xXXXX.

IRDA Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

IRDA Interruption Clear Flags
IRDA interruptions flags mask
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STM32L486xx HAL User Manual: IRDA Exported Functions

Modules
IRDA Exported Functions
IRDA

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IRDA Transmit and Receive functions.

Peripheral State and Error functions

IRDA State and Errors functions.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IRDAEx

Modules
IRDAEx
STM32L4xx_HAL_Driver

Modules

IRDAEx Private Macros
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG

Modules
IWDG
STM32L4xx_HAL_Driver

IWDG HAL module driver. More...

Modules

IWDG Private Defines
IWDG Exported Types
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
IWDG Private Constants
IWDG Private Macros

Detailed Description

IWDG HAL module driver.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

IWDG Prescaler
IWDG Window option
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STM32L486xx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Initialization and Start functions

Initialization and Start functions.

IO operation functions

IO operation functions.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG Exported Types

Data Structures
IWDG Exported Types
IWDG

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...
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STM32L486xx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

Get Flags Defines

Flags defines which can be used with LL_IWDG_ReadReg function.

Prescaler Divider
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STM32L486xx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Configuration
FLAG_Management
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG Exported Macros

Modules
IWDG Exported Macros
IWDG

Modules

Common Write and read registers Macros
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LCD

Modules
LCD
STM32L4xx_HAL_Driver

LCD HAL module driver. More...

Modules

LCD Private Defines
LCD Exported Functions
LCD Private Functions
LCD Exported Types
LCD Exported Constants
LCD Exported Macros
LCD Private Macros

Detailed Description

LCD HAL module driver.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LCD Exported Constants

Modules
LCD Exported Constants
LCD

Modules

LCD Error Code
LCD Prescaler
LCD Divider
LCD Duty
LCD Bias
LCD Voltage Source
LCD Interrupts
LCD Pulse On Duration
LCD Dead Time
LCD Blink Mode
LCD Blink Frequency
LCD Contrast
LCD RAMRegister
LCD High Drive
LCD Mux Segment
LCD Flags Definition
Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LCD Exported Functions

Modules
LCD Exported Functions
LCD

Modules

Initialization/de-initialization methods

Initialization and Configuration functions.

IO operation methods

LCD RAM functions.

Peripheral State methods

LCD State functions.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Clocks Frequency Structure

Data Structures
Clocks Frequency Structure
RCC Exported Types

Data Structures

struct LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM

Modules
LPTIM
STM32L4xx_HAL_Driver

LPTIM HAL module driver. More...

Modules

LPTIM Exported Functions
LPTIM Exported Types
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Private Types
LPTIM Private Variables
LPTIM Private Constants
LPTIM Private Macros
LPTIM Private Functions

Detailed Description

LPTIM HAL module driver.

Generated on Wed Jun 1 2016 16:28:19 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

LPTIM Clock Source
LPTIM Clock Prescaler
LPTIM Output Polarity
LPTIM Clock Sample Time
LPTIM Clock Polarity
LPTIM Trigger Source
LPTIM External Trigger Polarity
LPTIM Trigger Sample Time
LPTIM Updating Mode
LPTIM Counter Source
LPTIM Input1 Source
LPTIM Input2 Source
LPTIM Flags Definition
LPTIM Interrupts Definition
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STM32L486xx HAL User Manual: LPTIM Exported Init structure

Data Structures
LPTIM Exported Init structure
LPTIM

Data Structures

struct LL_LPTIM_InitTypeDef
LPTIM Init structure definition. More...
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

Get Flags Defines

Flags defines which can be used with LL_LPTIM_ReadReg function.

IT Defines

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions.

Operating Mode
Update Mode
Counter Mode
Output Waveform Type
Output Polarity
Prescaler Value
Trigger Source
Trigger Filter
Trigger Polarity
Clock Source
Clock Filter
Clock Polarity
Encoder Mode
Input1 Source
Input2 Source
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM Exported Functions

Modules
LPTIM Exported Functions
LPTIM

Modules

LPTIM Configuration
Trigger Configuration
Clock Configuration
Encoder Mode
FLAG Management
Interrupt Management
Initialisation and deinitialisation functions
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STM32L486xx HAL User Manual: LPTIM Exported Macros

Modules
LPTIM Exported Macros
LPTIM

Modules

Common Write and read registers Macros
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STM32L486xx HAL User Manual: LPUART Exported Init structures

Data Structures
LPUART Exported Init structures
LPUART

Data Structures

struct LL_LPUART_InitTypeDef
LL LPUART Init Structure definition. More...
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STM32L486xx HAL User Manual: LPUART Exported Constants

Modules
LPUART Exported Constants
LPUART

Modules

Clear Flags Defines

Flags defines which can be used with LL_LPUART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_LPUART_ReadReg function.

IT Defines

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions.

Direction
Parity Control
Wakeup
Datawidth
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Address Length Detection
Hardware Control
Wakeup Activation
Driver Enable Polarity
DMA Register Data
Generated on Wed Jun 1 2016 16:28:25 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPUART Exported Functions

Modules
LPUART Exported Functions
LPUART

Modules

Configuration functions
Configuration functions related to Half Duplex feature
Configuration functions related to Driver Enable feature
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPUART Exported Macros

Modules
LPUART Exported Macros
LPUART

Modules

Common Write and read registers Macros
Helper Macros
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STM32L486xx HAL User Manual: NAND

Modules
NAND
STM32L4xx_HAL_Driver

NAND HAL module driver. More...

Modules

NAND Private Constants
NAND Private Macros
NAND Private Functions
NAND Exported Functions
NAND Exported Types
NAND Exported Macros

Detailed Description

NAND HAL module driver.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NAND Exported Functions

Modules
NAND Exported Functions
NAND

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NOR

Modules
NOR
STM32L4xx_HAL_Driver

NOR HAL module driver. More...

Modules

NOR Private Constants
NOR Private Macros
NOR Private Variables
NOR Exported Functions
NOR Exported Types
NOR Exported Macros

Detailed Description

NOR HAL module driver.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: NOR Exported Functions

Modules
NOR Exported Functions
NOR

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output functions

Input Output and memory control functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP

Modules
OPAMP
STM32L4xx_HAL_Driver

OPAMP module driver. More...

Modules

OPAMP Exported Functions
OPAMP Exported Types
OPAMP Exported Constants
OPAMP Private Constants

OPAMP Private constants and defines.

OPAMP Exported Macros
OPAMP Private Macros

Detailed Description

OPAMP module driver.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP Exported Constants

Modules
OPAMP Exported Constants
OPAMP

Modules

OPAMP Mode
OPAMP Non Inverting Input
OPAMP Inverting Input
OPAMP Pga Gain
OPAMP PowerMode
OPAMP PowerSupplyRange
OPAMP User Trimming
OPAMP Factory Trimming
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP Exported Functions

Modules
OPAMP Exported Functions
OPAMP

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP Exported Init structure

Data Structures
OPAMP Exported Init structure
OPAMP

Data Structures

struct LL_OPAMP_InitTypeDef
Structure definition of some features of OPAMP instance. More...
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STM32L486xx HAL User Manual: OPAMP Exported Constants

Modules
OPAMP Exported Constants
OPAMP

Modules

OPAMP power supply range
OPAMP power mode
OPAMP mode calibration or functional.
OPAMP functional mode
OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
OPAMP input non-inverting
OPAMP input inverting
OPAMP inputs legacy literals name
OPAMP trimming mode
OPAMP trimming of transistors differential pair NMOS or PMOS
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP Exported Functions

Modules
OPAMP Exported Functions
OPAMP

Modules

Configuration of OPAMP hierarchical scope: common to several OPAMP instances
Configuration of OPAMP hierarchical scope: OPAMP instance
Configuration of OPAMP inputs
Configuration of OPAMP, legacy functions name
Configuration and operation of OPAMP trimming
Operation on OPAMP instance
Initialization and de-initialization functions
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMP Exported Macros

Modules
OPAMP Exported Macros
OPAMP

Modules

Common write and read registers macro
OPAMP helper macro
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STM32L486xx HAL User Manual: OPAMPEx

Modules
OPAMPEx
STM32L4xx_HAL_Driver

Modules

OPAMPEx Exported Functions
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: OPAMPEx Exported Functions

Modules
OPAMPEx Exported Functions
OPAMPEx

Modules

Extended Input and Output operation functions
Peripheral Control functions

Peripheral Control functions.

Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD

Modules
PCD
STM32L4xx_HAL_Driver

PCD HAL module driver. More...

Modules

PCD Private Macros
PCD Private Functions
PCD Exported Functions
PCD Exported Types
PCD Exported Constants
PCD Exported Macros

macros to handle interrupts and specific clock configurations

PCD Private Constants

Detailed Description

PCD HAL module driver.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD Exported Constants

Modules
PCD Exported Constants
PCD

Modules

PCD Speed
PCD PHY Module
Turnaround Timeout Value
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD Exported Functions

Modules
PCD Exported Functions
PCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCD Private Constants

Modules
PCD Private Constants
PCD

Modules

USB EXTI line interrupt
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PCDEx Exported Functions

Modules
PCDEx Exported Functions
PCDEx

Modules

Peripheral Control functions

PCDEx control functions.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR

Modules
PWR
STM32L4xx_HAL_Driver

PWR HAL module driver. More...

Modules

PWR Private Defines
PWR Exported Functions
PWR Exported Types
PWR Exported Constants
PWR Exported Macros
PWR Private Macros

Detailed Description

PWR HAL module driver.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

Programmable Voltage Detection levels
PWR PVD interrupt and event mode
PWR regulator mode
PWR SLEEP mode entry
PWR STOP mode entry
PWR PVD external interrupt line
PWR PVD event line
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Low Power modes configuration functions.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Exported Types

Data Structures
PWR Exported Types
PWR

Data Structures

struct PWR_PVDTypeDef
PWR PVD configuration structure definition. More...
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Extended Private Defines

Modules
PWR Extended Private Defines
PWREx

Modules

PWR PVM Mode Mask
PWR Extended Flag Setting Time Out Value
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

Clear Flags Defines

Flags defines which can be used with LL_PWR_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_PWR_ReadReg function.

REGU VOLTAGE
MODE PWR
PVM VDDUSB 1
PVDLEVEL
WAKEUP
BATT CHARG RESISTOR
GPIO
GPIO BIT
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STM32L486xx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Configuration
FLAG_Management
De-initialization function
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Exported Macros

Modules
PWR Exported Macros
PWR

Modules

Common Write and read registers Macros
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Private Defines

Modules
PWR Private Defines
PWR

Modules

PWR PVD Mode Mask
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Extended Exported Constants

Modules
PWR Extended Exported Constants
PWREx

Modules

Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
PWR wake-up pins
Peripheral Voltage Monitoring type
PWR PVM interrupt and event mode
PWR Regulator voltage scale
PWR battery charging resistor selection
PWR battery charging
GPIO bit number for I/O setting in standby/shutdown mode
GPIO port
PWR PVM external interrupts lines
PWR PVM event lines
PWR Status Flags

Elements values convention: 0000 0000 0XXY YYYYb.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Extended Exported Functions

Modules
PWR Extended Exported Functions
PWREx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: PWR Extended Exported Types

Data Structures
PWR Extended Exported Types
PWREx

Data Structures

struct PWR_PVMTypeDef
PWR PVM configuration structure definition. More...
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STM32L486xx HAL User Manual: QSPI

Modules
QSPI
STM32L4xx_HAL_Driver

QSPI HAL module driver. More...

Modules

QSPI Private Constants
QSPI Private Macros
QSPI Exported Functions
QSPI Exported Types
QSPI Exported Constants
QSPI Exported Macros

Detailed Description

QSPI HAL module driver.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: QSPI Exported Constants

Modules
QSPI Exported Constants
QSPI

Modules

QSPI Error Code
QSPI Sample Shifting
QSPI ChipSelect High Time
QSPI Clock Mode
QSPI Address Size
QSPI Alternate Bytes Size
QSPI Instruction Mode
QSPI Address Mode
QSPI Alternate Bytes Mode
QSPI Data Mode
QSPI DDR Mode
QSPI DDR Data Output Delay
QSPI Send Instruction Mode
QSPI Match Mode
QSPI Automatic Stop
QSPI Timeout Activation
QSPI Flags
QSPI Interrupts
QSPI Timeout definition

QSPI Timeout definition.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC

Modules
RCC
STM32L4xx_HAL_Driver

RCC HAL module driver. More...

Modules

RCC Private Constants
RCC Private Macros
RCC Private Variables
RCC Private Functions
RCC Exported Functions
RCC Exported Types
RCC Exported Constants
RCC Exported Macros

Detailed Description

RCC HAL module driver.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Timeout Values
Oscillator Type
HSE Config
LSE Config
HSI Config
LSI Config
MSI Config
HSI48 Config
PLL Config
PLLP Clock Divider
PLLQ Clock Divider
PLLR Clock Divider
PLL Clock Source
PLL Clock Output
PLLSAI1 Clock Output
PLLSAI2 Clock Output
MSI Clock Range
System Clock Type
System Clock Source
System Clock Source Status
AHB Clock Source
APB1 APB2 Clock Source
RTC Clock Source
MCO Index
MCO1 Clock Source
MCO1 Clock Prescaler
Interrupts
Flags

Elements values convention: XXXYYYYYb.

LSE Drive Config
Wake-Up from STOP Clock
Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

RCC clocks control functions.

Generated on Wed Jun 1 2016 16:28:20 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Exported Types

Data Structures
RCC Exported Types
RCC

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...
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STM32L486xx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Oscillator Values adaptation

Defines used to adapt values of different oscillators.

Clear Flags Defines

Flags defines which can be used with LL_RCC_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_RCC_ReadReg function.

IT Defines

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

LSE oscillator drive capability
MSI clock ranges
MSI range after Standby mode
LSCO Selection
System clock switch
System clock switch status
AHB prescaler
APB low-speed prescaler (APB1)
APB high-speed prescaler (APB2)
Wakeup from Stop and CSS backup clock selection
MCO1 SOURCE selection
MCO1 prescaler
Peripheral clock frequency
Peripheral USART clock source selection
Peripheral UART clock source selection
Peripheral LPUART clock source selection
Peripheral I2C clock source selection
Peripheral LPTIM clock source selection
Peripheral SAI clock source selection
Peripheral SDMMC clock source selection
Peripheral RNG clock source selection
Peripheral USB clock source selection
Peripheral ADC clock source selection
Peripheral SWPMI clock source selection
Peripheral DFSDM clock source selection
Peripheral USART get clock source
Peripheral UART get clock source
Peripheral LPUART get clock source
Peripheral I2C get clock source
Peripheral LPTIM get clock source
Peripheral SAI get clock source
Peripheral SDMMC get clock source
Peripheral RNG get clock source
Peripheral USB get clock source
Peripheral ADC get clock source
Peripheral SWPMI get clock source
Peripheral DFSDM get clock source
RTC clock source selection
PLL, PLLSAI1 and PLLSAI2 entry clock source
PLL, PLLSAI1 and PLLSAI2 division factor
PLL division factor (PLLR)
PLL division factor (PLLP)
PLL division factor (PLLQ)
PLLSAI1 division factor (PLLSAI1Q)
PLLSAI1 division factor (PLLSAI1P)
PLLSAI1 division factor (PLLSAI1R)
PLLSAI2 division factor (PLLSAI2P)
PLLSAI2 division factor (PLLSAI2R)
MSI clock range selection
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

HSE
HSI
LSE
LSI
MSI
LSCO
System
MCO
Peripheral Clock Source
RTC
PLL
PLLSAI1
PLLSAI2
FLAG Management
IT Management
De-initialization function
Get system and peripherals clocks frequency functions

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

Common Write and read registers Macros
Calculate frequencies
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCC Exported Types

Modules
RCC Exported Types
RCC

Modules

Clocks Frequency Structure
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCCEx

Modules
RCCEx
STM32L4xx_HAL_Driver

RCC Extended HAL module driver. More...

Modules

RCCEx Private Constants
RCCEx Private Functions
RCCEx Exported Functions
RCCEx Exported Types
RCCEx Exported Constants
RCCEx Exported Macros
RCCEx_Private_Macros

Detailed Description

RCC Extended HAL module driver.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCCEx Exported Constants

Modules
RCCEx Exported Constants
RCCEx

Modules

Low Speed Clock Source
Periph Clock Selection
USART1 Clock Source
USART2 Clock Source
USART3 Clock Source
UART4 Clock Source
UART5 Clock Source
LPUART1 Clock Source
I2C1 Clock Source
I2C2 Clock Source
I2C3 Clock Source
SAI1 Clock Source
SAI2 Clock Source
LPTIM1 Clock Source
LPTIM2 Clock Source
SDMMC1 Clock Source
RNG Clock Source
USB Clock Source
ADC Clock Source
SWPMI1 Clock Source
DFSDM1 Clock Source
RCC LSE CSS external interrupt line
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STM32L486xx HAL User Manual: RCCEx Exported Functions

Modules
RCCEx Exported Functions
RCCEx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended Clock management functions

Extended Clock management functions.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RCCEx Exported Types

Data Structures
RCCEx Exported Types
RCCEx

Data Structures

struct | RCC_PLLSAI1InitTypeDef
PLLSAI1 Clock structure definition. More...
struct | RCC_PLLSAI2InitTypeDef
PLLSAI2 Clock structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG

Modules
RNG
STM32L4xx_HAL_Driver

RNG HAL module driver. More...

Modules

RNG_Private_Constants
RNG Exported Types
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions

Detailed Description

RNG HAL module driver.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

RNG Interrupts Definition
RNG Flags Definition
Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

Get Flags Defines

Flags defines which can be used with LL_RNG_ReadReg function.

IT Defines

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros.

Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

RNG Configuration functions
FLAG Management
IT Management
Data Management
Initialization and de-initialization functions
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RNG Exported Macros

Modules
RNG Exported Macros
RNG

Modules

Common Write and read registers Macros
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC

Modules
RTC
STM32L4xx_HAL_Driver

RTC HAL module driver. More...

Modules

RTC Exported Functions
RTC Private functions
RTC Exported Types
RTC Exported Constants
RTC Exported Macros
RTC Private Constants
RTC Private Macros

Detailed Description

RTC HAL module driver.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

RTC Hour Formats
RTC Output Polarity Definitions
RTC Output Type ALARM OUT
RTC Output ALARM OUT Remap
RTC AM PM Definitions
RTC DayLight Saving Definitions
RTC Store Operation Definitions
RTC Input Parameter Format Definitions
RTC Month Date Definitions
RTC WeekDay Definitions
RTC Alarm Date WeekDay Definitions
RTC Alarm Mask Definitions
RTC Alarms Definitions
RTC Alarm Sub Seconds Masks Definitions
RTC Interrupts Definitions
RTC Flags Definitions
Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

RTC Time and Date functions

RTC Time and Date functions.

RTC Alarm functions

RTC Alarm functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Wed Jun 1 2016 16:28:21 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Exported Init structure

Data Structures
RTC Exported Init structure
RTC

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...
Generated on Wed Jun 1 2016 16:28:26 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

FORMAT
RTC Alarm A Date WeekDay
RTC Alarm B Date WeekDay
Get Flags Defines

Flags defines which can be used with LL_RTC_ReadReg function.

IT Defines

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

WEEK DAY
MONTH
HOUR FORMAT
ALARM OUTPUT
ALARM OUTPUT TYPE
OUTPUT POLARITY PIN
TIME FORMAT
SHIFT SECOND
ALARMA MASK
ALARMA TIME FORMAT
ALARMB MASK
ALARMB TIME FORMAT
TIMESTAMP EDGE
TIMESTAMP TIME FORMAT
TAMPER
TAMPER MASK
TAMPER NO ERASE
TAMPER DURATION
TAMPER FILTER
TAMPER SAMPLING FREQUENCY DIVIDER
TAMPER ACTIVE LEVEL
WAKEUP CLOCK DIV
BACKUP
Calibration output
Calibration pulse insertion
Calibration period
Generated on Wed Jun 1 2016 16:28:27 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Configuration
Time
Date
ALARMA
ALARMB
Timestamp
Tamper
Wakeup
Backup_Registers
Calibration
FLAG_Management
IT_Management
Initialization and de-initialization functions
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STM32L486xx HAL User Manual: RTC Exported Macros

Modules
RTC Exported Macros
RTC

Modules

Common Write and read registers Macros
Convert helper Macros
Date helper Macros
Time helper Macros
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STM32L486xx HAL User Manual: RTC Private Macros

Modules
RTC Private Macros
RTC

Modules

RTC Private macros to check input parameters
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STM32L486xx HAL User Manual: RTCEx Exported Constants

Modules
RTCEx Exported Constants
RTCEx

Modules

RTC Output Selection Definitions
RTC Backup Registers Definitions
RTC TimeStamp Edges Definitions
RTC TimeStamp Pins Selection
RTC Tamper Pins Definitions
RTC Tamper Interrupts Definitions
RTC Tamper Triggers Definitions
RTC Tamper EraseBackUp Definitions
RTC Tamper Mask Flag Definitions
RTC Tamper Filter Definitions
RTC Tamper Sampling Frequencies Definitions
RTC Tamper Pin Precharge Duration Definitions
RTC Tamper TimeStamp On Tamper Detection Definitions
RTC Tamper Pull Up Definitions
RTC Wakeup Timer Definitions
RTC Smooth Calib Period Definitions
RTC Smooth Calib Plus Pulses Definitions
RTC Calib Output Selection Definitions
RTC Add 1 Second Parameter Definitions
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STM32L486xx HAL User Manual: RTCEx Exported Functions

Modules
RTCEx Exported Functions
RTCEx

Modules

RTC TimeStamp and Tamper functions

RTC TimeStamp and Tamper functions.

RTC Wake-up functions

RTC Wake-up functions.

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended features functions

Extended features functions.

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STM32L486xx HAL User Manual: RTCEx Exported Types

Data Structures
RTCEx Exported Types
RTCEx

Data Structures

struct RTC_TamperTypeDef
RTC Tamper structure definition. More...
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STM32L486xx HAL User Manual: RTCEx Private Macros

Modules
RTCEx Private Macros
RTCEx

Modules

Private macros to check input parameters
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STM32L486xx HAL User Manual: SAI

Modules
SAI
STM32L4xx_HAL_Driver

SAI HAL module driver. More...

Modules

SAI Private Typedefs
SAI Private Constants
SAI Private Functions

Private functions.

SAI Exported Functions
SAI Exported Types
SAI Exported Constants
SAI Exported Macros

macros to handle interrupts and specific configurations

SAI_Private_Macros

Detailed Description

SAI HAL module driver.

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STM32L486xx HAL User Manual: SAI Exported Constants

Modules
SAI Exported Constants
SAI

Modules

SAI Error Code
SAI External synchronisation
SAI Supported protocol
SAI protocol data size
SAI Audio Frequency
SAI Block Mode
SAI Block Protocol
SAI Block Data Size
SAI Block MSB LSB transmission
SAI Block Clock Strobing
SAI Block Synchronization
SAI Block Output Drive
SAI Block NoDivider
SAI Block FS Definition
SAI Block FS Polarity
SAI Block FS Offset
SAI Block Slot Size
SAI Block Slot Active
SAI Mono Stereo Mode
SAI TRIState Management
SAI Block Fifo Threshold
SAI Block Companding Mode
SAI Block Mute Value
SAI Block Interrupts Definition
SAI Block Flags Definition
SAI Block Fifo Status Level
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STM32L486xx HAL User Manual: SAI Exported Functions

Modules
SAI Exported Functions
SAI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State functions

Peripheral State functions.

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STM32L486xx HAL User Manual: SAI Frame Structure definition

Data Structures
SAI Frame Structure definition
SAI Exported Types

SAI Frame Init structure definition. More...

Data Structures

struct SAI_FrameInitTypeDef

Detailed Description

SAI Frame Init structure definition.

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STM32L486xx HAL User Manual: SAI Init Structure definition

Data Structures
SAI Init Structure definition
SAI Exported Types

SAI Init Structure definition. More...

Data Structures

struct SAI_InitTypeDef

Detailed Description

SAI Init Structure definition.

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STM32L486xx HAL User Manual: SAI Slot Structure definition

Data Structures
SAI Slot Structure definition
SAI Exported Types

SAI Block Slot Init Structure definition. More...

Data Structures

struct SAI_SlotInitTypeDef

Detailed Description

SAI Block Slot Init Structure definition.

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STM32L486xx HAL User Manual: SD

Modules
SD
STM32L4xx_HAL_Driver

Modules

SD_Private_Defines
SD_Private_Functions_Prototypes
SD_Exported_Functions
SD_Private_Functions
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STM32L486xx HAL User Manual: SD_Exported_Functions

Modules
SD_Exported_Functions
SD

Modules

SD_Exported_Functions_Group1

Initialization and de-initialization functions.

SD_Exported_Functions_Group2

Data transfer functions.

SD_Exported_Functions_Group3

management functions

SD_Exported_Functions_Group4

Peripheral State functions.

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STM32L486xx HAL User Manual: SMARTCARD

Modules
SMARTCARD
STM32L4xx_HAL_Driver

HAL SMARTCARD module driver. More...

Modules

SMARTCARD Private Constants
SMARTCARD Exported Functions
SMARTCARD Private Functions
SMARTCARD Exported Types
SMARTCARD Exported Constants
SMARTCARD Exported Macros
SMARTCARD Private Macros

Detailed Description

HAL SMARTCARD module driver.

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STM32L486xx HAL User Manual: SMARTCARD Exported Constants

Modules
SMARTCARD Exported Constants
SMARTCARD

Modules

SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD Parity
SMARTCARD Transfer Mode
SMARTCARD Clock Polarity
SMARTCARD Clock Phase
SMARTCARD Last Bit
SMARTCARD One Bit Sampling Method
SMARTCARD NACK Enable
SMARTCARD Timeout Enable
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD advanced feature Binary Data inversion
SMARTCARD advanced feature RX TX pins swap
SMARTCARD advanced feature Overrun Disable
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD advanced feature MSB first
SMARTCARD Request Parameters
SMARTCARD auto retry counter LSB position in CR3 register
SMARTCARD guard time value LSB position in GTPR register
SMARTCARD block length LSB position in RTOR register
SMARTCARD interruptions flags mask
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STM32L486xx HAL User Manual: SMARTCARD Exported Functions

Modules
SMARTCARD Exported Functions
SMARTCARD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

SMARTCARD Transmit and Receive functions.

Peripheral State and Errors functions

SMARTCARD State and Errors functions.

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STM32L486xx HAL User Manual: SMARTCARDEx

Modules
SMARTCARDEx
STM32L4xx_HAL_Driver

SMARTCARD Extended HAL module driver. More...

Modules

SMARTCARD Extended Exported Functions
SMARTCARD Extended Private Macros
SMARTCARD Extended Exported Constants

Detailed Description

SMARTCARD Extended HAL module driver.

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STM32L486xx HAL User Manual: SMARTCARD Extended Exported Constants

Modules
SMARTCARD Extended Exported Constants
SMARTCARDEx

Modules

SMARTCARD Transmission Completion Indication
SMARTCARD advanced feature initialization type
SMARTCARD Flags

Elements values convention: 0xXXXX.

SMARTCARD Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

SMARTCARD Interruption Clear Flags
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STM32L486xx HAL User Manual: SMARTCARD Extended Exported Functions

Modules
SMARTCARD Extended Exported Functions
SMARTCARDEx

Modules

Extended Peripheral Control functions

Extended control functions.

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STM32L486xx HAL User Manual: SMBUS

Modules
SMBUS
STM32L4xx_HAL_Driver

SMBUS HAL module driver. More...

Modules

SMBUS Private Constants
SMBUS Exported Functions
SMBUS Exported Types
SMBUS Exported Constants
SMBUS Exported Macros
SMBUS Private Macros
SMBUS Private Functions

Data transfers Private functions.

Detailed Description

SMBUS HAL module driver.

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STM32L486xx HAL User Manual: SMBUS Configuration Structure definition

Data Structures
SMBUS Configuration Structure definition
SMBUS Exported Types

SMBUS Configuration Structure definition. More...

Data Structures

struct SMBUS_InitTypeDef

Detailed Description

SMBUS Configuration Structure definition.

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STM32L486xx HAL User Manual: SMBUS Exported Constants

Modules
SMBUS Exported Constants
SMBUS

Modules

SMBUS Analog Filter
SMBUS addressing mode
SMBUS dual addressing mode
SMBUS own address2 masks
SMBUS general call addressing mode
SMBUS nostretch mode
SMBUS packet error check mode
SMBUS peripheral mode
SMBUS ReloadEndMode definition
SMBUS StartStopMode definition
SMBUS XferOptions definition
SMBUS Interrupt configuration definition

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

SMBUS Flag definition

Flag definition Elements values convention: 0xXXXXYYYY.

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STM32L486xx HAL User Manual: SMBUS Exported Functions

Modules
SMBUS Exported Functions
SMBUS

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

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STM32L486xx HAL User Manual: SMBUS Exported Types

Modules
SMBUS Exported Types
SMBUS

Modules

SMBUS Configuration Structure definition

SMBUS Configuration Structure definition.

HAL state definition

HAL State definition.

SMBUS Error Code definition

SMBUS Error Code definition.

SMBUS handle Structure definition

SMBUS handle Structure definition.

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STM32L486xx HAL User Manual: SMBUS handle Structure definition

Data Structures
SMBUS handle Structure definition
SMBUS Exported Types

SMBUS handle Structure definition. More...

Data Structures

struct SMBUS_HandleTypeDef

Detailed Description

SMBUS handle Structure definition.

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STM32L486xx HAL User Manual: SPI

Modules
SPI
STM32L4xx_HAL_Driver

SPI HAL module driver. More...

Modules

SPI Private Constants
SPI Private Functions

Private functions.

SPI Exported Functions
SPI Exported Types
SPI Exported Constants
SPI Exported Macros
SPI Private Macros

Detailed Description

SPI HAL module driver.

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STM32L486xx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

SPI Error Code
SPI Mode
SPI Direction Mode
SPI Data Size
SPI Clock Polarity
SPI Clock Phase
SPI Slave Select management
SPI NSS Pulse Mode
SPI BaudRate Prescaler
SPI MSB LSB transmission
SPI TI mode
SPI CRC Calculation
SPI CRC Length

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

SPI FIFO Reception Threshold

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/2(16-bits).

SPI Interrupt configuration definition

SPI Interrupt definition Elements values convention: 0xXXXXXXXX.

SPI Flag definition

Flag definition Elements values convention: 0xXXXXYYYY.

SPI Transmission FIFO Status Level
SPI Reception FIFO Status Level
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STM32L486xx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

SPI control functions.

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STM32L486xx HAL User Manual: SPI Exported Init structure

Data Structures
SPI Exported Init structure
SPI

Data Structures

struct LL_SPI_InitTypeDef
SPI Init structures definition. More...
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STM32L486xx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

Get Flags Defines

Flags defines which can be used with LL_SPI_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Operation Mode
Serial Protocol
Clock Phase
Clock Polarity
Baud Rate Prescaler
Transmission Bit Order
Transfer Mode
Slave Select Pin Mode
Datawidth
CRC Calculation
CRC Length
RX FIFO Threshold
RX FIFO Level
TX FIFO Level
DMA Parity
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STM32L486xx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Configuration
CRC Management
Slave Select Pin Management
FLAG Management
Interrupt Management
DMA Management
DATA Management
Initialization and de-initialization functions
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STM32L486xx HAL User Manual: SPI Exported Macros

Modules
SPI Exported Macros
SPI

Modules

Common Write and read registers Macros
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STM32L486xx HAL User Manual: SPIEx

Modules
SPIEx
STM32L4xx_HAL_Driver

SPI Extended HAL module driver. More...

Modules

SPIEx Private Constants
SPIEx Exported Functions

Detailed Description

SPI Extended HAL module driver.

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STM32L486xx HAL User Manual: SPIEx Exported Functions

Modules
SPIEx Exported Functions
SPIEx

Modules

IO operation functions

Data transfers functions.

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STM32L486xx HAL User Manual: SRAM

Modules
SRAM
STM32L4xx_HAL_Driver

SRAM HAL module driver. More...

Modules

SRAM Exported Functions
SRAM Exported Types
SRAM Exported Macros

Detailed Description

SRAM HAL module driver.

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STM32L486xx HAL User Manual: SRAM Exported Functions

Modules
SRAM Exported Functions
SRAM

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input Output and memory control functions

Input Output and memory control functions.

Control functions

Control functions.

Peripheral State functions

Peripheral State functions.

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STM32L486xx HAL User Manual: STM32L4xx_HAL_Driver

Modules
STM32L4xx_HAL_Driver

Modules

HAL

HAL module driver.

ADC

ADC HAL module driver.

ADCEx

ADC Extended HAL module driver.

CAN

CAN driver modules.

COMP

COMP HAL module driver.

CORTEX
CRC

CRC HAL module driver.

CRCEx

CRC Extended HAL module driver.

CRYP

CRYP HAL module driver.

CRYPEx

CRYP Extended HAL module driver.

DAC

DAC driver modules.

DACEx

DAC Extended HAL module driver.

DFSDM

DFSDM HAL driver module.

DMA

DMA HAL module driver.

FIREWALL

HAL FIREWALL module driver.

FLASH

FLASH HAL module driver.

FLASHEx

FALSH Extended HAL module driver.

FLASH_RAMFUNC

FLASH functions executed from RAM.

GPIO

GPIO HAL module driver.

GPIOEx

GPIO Extended HAL module driver.

HCD

HCD HAL module driver.

I2C

I2C HAL module driver.

I2CEx

I2C Extended HAL module driver.

IRDA

HAL IRDA module driver.

IWDG

IWDG HAL module driver.

LCD

LCD HAL module driver.

LPTIM

LPTIM HAL module driver.

NAND

NAND HAL module driver.

NOR

NOR HAL module driver.

OPAMP

OPAMP module driver.

PCD

PCD HAL module driver.

PCDEx

PCD Extended HAL module driver.

PWR

PWR HAL module driver.

PWREx

PWR Extended HAL module driver.

QSPI

QSPI HAL module driver.

RCC

RCC HAL module driver.

RCCEx

RCC Extended HAL module driver.

RNG

RNG HAL module driver.

RTC

RTC HAL module driver.

RTCEx

RTC Extended HAL module driver.

SAI

SAI HAL module driver.

SMARTCARD

HAL SMARTCARD module driver.

SMARTCARDEx

SMARTCARD Extended HAL module driver.

SMBUS

SMBUS HAL module driver.

SPI

SPI HAL module driver.

SPIEx

SPI Extended HAL module driver.

SRAM

SRAM HAL module driver.

SWPMI

HAL SWPMI module driver.

TIM

TIM HAL module driver.

TIMEx

TIM Extended HAL module driver.

TSC

HAL TSC module driver.

UART

HAL UART module driver.

UARTEx

UART Extended HAL module driver.

USART

HAL USART Synchronous module driver.

WWDG

WWDG HAL module driver.

IRDAEx
OPAMPEx
SD
USARTEx
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STM32L486xx HAL User Manual: STM32L4xx_LL_Driver

Modules
STM32L4xx_LL_Driver

Modules

ADC
BUS
COMP
CORTEX
CRC
DAC
DMA
EXTI
GPIO
I2C
IWDG
LPTIM
LPUART
OPAMP
PWR
RCC
RNG
RTC
SPI
SWPMI
SYSTEM
TIM
USART
UTILS
WWDG
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STM32L486xx HAL User Manual: SWPMI

Modules
SWPMI
STM32L4xx_HAL_Driver

HAL SWPMI module driver. More...

Modules

SWPMI Exported Functions
SWPMI Private Functions
SWPMI Exported Types
SWPMI Exported Constants
SWPMI Exported Macros
SWPMI Private Types
SWPMI Private Variables
SWPMI Private Constants
SWPMI Private Macros

Detailed Description

HAL SWPMI module driver.

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STM32L486xx HAL User Manual: SWPMI Exported Constants

Modules
SWPMI Exported Constants
SWPMI

Modules

SWPMI Error Code Bitmap
SWPMI Voltage Class
SWPMI Tx Buffering Mode
SWPMI Rx Buffering Mode
SWPMI Status Flags

Elements values convention: 0xXXXXXXXX.

SWPMI Interrupts Definition

Elements values convention: 0xXXXX.

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STM32L486xx HAL User Manual: SWPMI Exported Init structure

Data Structures
SWPMI Exported Init structure
SWPMI

Data Structures

struct LL_SWPMI_InitTypeDef
SWPMI Init structures definition. More...
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STM32L486xx HAL User Manual: SWPMI Exported Constants

Modules
SWPMI Exported Constants
SWPMI

Modules

Clear Flags Defines

Flags defines which can be used with LL_SWPMI_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_SWPMI_ReadReg function.

IT Defines

IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions.

SW BUFFER RX
SW BUFFER TX
VOLTAGE CLASS
DMA register data
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STM32L486xx HAL User Manual: SWPMI Exported Functions

Modules
SWPMI Exported Functions
SWPMI

Modules

Configuration
FLAG_Management
IT_Management
DMA_Management
Data_Management
Initialization and de-initialization functions
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STM32L486xx HAL User Manual: SWPMI Exported Macros

Modules
SWPMI Exported Macros
SWPMI

Modules

Common Write and read registers Macros
Bit rate calculation helper Macros
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STM32L486xx HAL User Manual: SYSCFG Exported Constants

Modules
SYSCFG Exported Constants
HAL

Modules

Boot Mode
FPU Interrupts
SRAM2 Write protection
VREFBUF Voltage Scale
VREFBUF High Impedance
Flags
Fast-mode Plus on GPIO
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STM32L486xx HAL User Manual: SYSTEM Exported Constants

Modules
SYSTEM Exported Constants
SYSTEM

Modules

SYSCFG REMAP
SYSCFG BANK MODE
SYSCFG I2C FASTMODEPLUS
SYSCFG EXTI PORT
SYSCFG EXTI LINE
SYSCFG TIMER BREAK
SYSCFG SRAM2 WRP
DBGMCU TRACE Pin Assignment
DBGMCU APB1 GRP1 STOP IP
DBGMCU APB1 GRP2 STOP IP
DBGMCU APB2 GRP1 STOP IP
VREFBUF VOLTAGE
FLASH LATENCY
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STM32L486xx HAL User Manual: SYSTEM Exported Functions

Modules
SYSTEM Exported Functions
SYSTEM

Modules

SYSCFG
DBGMCU
VREFBUF
FLASH
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STM32L486xx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

TIM Clear Input Source
TIM DMA Base Address
TIM Extended Event Source
TIM Input Channel polarity
TIM ETR Polarity
TIM ETR Prescaler
TIM Counter Mode
TIM Clock Division
TIM Output Compare State
TIM Output Fast State
TIM Complementary Output Compare State
TIM Output Compare Polarity
TIM Complementary Output Compare Polarity
TIM Output Compare Idle State
TIM Complementary Output Compare Idle State
TIM Input Capture Polarity
TIM Input Capture Selection
TIM Input Capture Prescaler
TIM One Pulse Mode
TIM Encoder Mode
TIM interrupt Definition
TIM Commutation Source
TIM DMA Sources
TIM Flag Definition
TIM Channel
TIM Clock Source
TIM Clock Polarity
TIM Clock Prescaler
TIM Clear Input Polarity
TIM Clear Input Prescaler
TIM OSSR OffState Selection for Run mode state
TIM OSSI OffState Selection for Idle mode state
TIM Lock level
TIM Break Input Enable
TIM Break Input Polarity
TIM Break input 2 Enable
TIM Break Input 2 Polarity
TIM Automatic Output Enable
Group Channel 5 and Channel 1, 2 or 3
TIM Master Mode Selection
TIM Master Mode Selection 2 (TRGO2)
TIM Master/Slave Mode
TIM Slave mode
TIM Output Compare and PWM Modes
TIM Trigger Selection
TIM Trigger Polarity
TIM Trigger Prescaler
TIM TI1 Input Selection
TIM DMA Burst Length
TIM DMA Handle Index
TIM Capture/Compare Channel State
TIM Break System
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STM32L486xx HAL User Manual: TIM Exported Init structure

Data Structures
TIM Exported Init structure
TIM

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
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STM32L486xx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

Get Flags Defines

Flags defines which can be used with LL_TIM_ReadReg function.

IT Defines

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Update Source
One Pulse Mode
Counter Mode
Clock Division
Counter Direction
Capture Compare Update Source
Capture Compare DMA Request
Lock Level
Channel
Output Configuration State
Output Configuration Mode
Output Configuration Polarity
Output Configuration Idle State
GROUPCH5
Active Input Selection
Input Configuration Prescaler
Input Configuration Filter
Input Configuration Polarity
Clock Source
Encoder Mode
Trigger Output
Trigger Output 2
Slave Mode
Trigger Selection
External Trigger Polarity
External Trigger Prescaler
External Trigger Filter
External Trigger Source
break polarity
break filter
BREAK2 POLARITY
BREAK2 FILTER
OSSI
OSSR
BREAK INPUT
BKIN SOURCE
BKIN POLARITY
DMA Burst Base Address
DMA Burst Length
TIM1 External Trigger ADC1 Remap
TIM1 External Trigger ADC3 Remap
TIM1 External Input Ch1 Remap
TIM2 Internal Trigger1 Remap TIM8
TIM2 External Input Ch4 Remap
TIM3 External Input Ch1 Remap
TIM8 External Trigger ADC2 Remap
TIM8 External Trigger ADC3 Remap
TIM8 External Input Ch1 Remap
TIM15 External Input Ch1 Remap
TIM15 ENCODERMODE
TIM16 External Input Ch1 Remap
TIM17 Timer Input Ch1 Remap
OCREF clear input selection
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STM32L486xx HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

Time Base configuration
Capture Compare configuration
Output channel configuration
Input channel configuration
Counter clock selection
Timer synchronisation configuration
Break function configuration
DMA burst mode configuration
Timer input remapping
OCREF_Clear_Management
FLAG-Management
IT-Management
DMA-Management
EVENT-Management
Initialisation and deinitialisation functions
Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TIM Exported Macros

Modules
TIM Exported Macros
TIM

Modules

Common Write and read registers Macros
Exported_Macros
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STM32L486xx HAL User Manual: TIM Extended Exported Constants

Modules
TIM Extended Exported Constants
TIMEx

Modules

TIM Extended Remapping
TIM Extended Break input
TIM Extended Break input source
TIM Extended Break input source enabling
TIM Extended Break input polarity
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STM32L486xx HAL User Manual: TIM Extended Exported Types

Data Structures
TIM Extended Exported Types
TIMEx

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...
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STM32L486xx HAL User Manual: TSC

Modules
TSC
STM32L4xx_HAL_Driver

HAL TSC module driver. More...

Modules

Exported Functions
Private Functions
TSC Exported Types
TSC Exported Constants
TSC Exported Macros
TSC Private Macros

Detailed Description

HAL TSC module driver.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: TSC Exported Constants

Modules
TSC Exported Constants
TSC

Modules

CTPulse High Length
CTPulse Low Length
Spread Spectrum Prescaler
Pulse Generator Prescaler
Max Count Value
IO Default Mode
Synchro Pin Polarity
Acquisition Mode
IO Mode
Interrupts definition
Flags definition
Group definition
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STM32L486xx HAL User Manual: Exported Functions

Modules
Exported Functions
TSC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Input and Output operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

IRQ Handler and Callbacks
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STM32L486xx HAL User Manual: UART

Modules
UART
STM32L4xx_HAL_Driver

HAL UART module driver. More...

Modules

UART Private Constants
UART Exported Functions
UART Private Functions
UART Exported Types
UART Exported Constants
UART Exported Macros
UART Private Macros

Detailed Description

HAL UART module driver.

Generated on Wed Jun 1 2016 16:28:22 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UART Exported Constants

Modules
UART Exported Constants
UART

Modules

UART Number of Stop Bits
UART Parity
UART Hardware Flow Control
UART Transfer Mode
UART State
UART Over Sampling
UART One Bit Sampling Method
UART Advanced Feature AutoBaud Rate Mode
UART Receiver TimeOut
UART Local Interconnection Network mode
UART LIN Break Detection
UART DMA Tx
UART DMA Rx
UART Half Duplex Selection
UART WakeUp Methods
UART Request Parameters
UART Advanced Feature Initialization Type
UART Advanced Feature TX Pin Active Level Inversion
UART Advanced Feature RX Pin Active Level Inversion
UART Advanced Feature Binary Data Inversion
UART Advanced Feature RX TX Pins Swap
UART Advanced Feature Overrun Disable
UART Advanced Feature Auto BaudRate Enable
UART Advanced Feature DMA Disable On Rx Error
UART Advanced Feature MSB First
UART Advanced Feature Stop Mode Enable
UART Advanced Feature Mute Mode Enable
UART Address-matching LSB Position In CR2 Register
UART WakeUp From Stop Selection
UART DriverEnable Polarity
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Interruptions Flag Mask
UART polling-based communications time-out value
UART Status Flags

Elements values convention: 0xXXXX.

UART Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

UART Interruption Clear Flags
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STM32L486xx HAL User Manual: UART Exported Functions

Modules
UART Exported Functions
UART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

UART Transmit/Receive functions.

Peripheral Control functions

UART control functions.

Peripheral State and Error functions

UART Peripheral State functions.

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STM32L486xx HAL User Manual: UARTEx

Modules
UARTEx
STM32L4xx_HAL_Driver

UART Extended HAL module driver. More...

Modules

UARTEx Private Functions
UARTEx Exported Functions
UARTEx Exported Types
UARTEx Exported Constants
UARTEx Private Macros

Detailed Description

UART Extended HAL module driver.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UARTEx Exported Constants

Modules
UARTEx Exported Constants
UARTEx

Modules

UART Word Length
UART Extended WakeUp Address Length
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STM32L486xx HAL User Manual: UARTEx Exported Functions

Modules
UARTEx Exported Functions
UARTEx

Modules

Initialization and de-initialization functions

Extended Initialization and Configuration Functions.

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UARTEx Exported Types

Data Structures
UARTEx Exported Types
UARTEx

Data Structures

struct UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...
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STM32L486xx HAL User Manual: USART

Modules
USART
STM32L4xx_HAL_Driver

HAL USART Synchronous module driver. More...

Modules

USART Private Constants
USART Exported Functions
USART Private Functions
USART Exported Types
USART Exported Constants
USART Exported Macros
USART Private Macros

Detailed Description

HAL USART Synchronous module driver.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

USART Number of Stop Bits
USART Parity
USART Mode
USART Over Sampling
USART Clock
USART Clock Polarity
USART Clock Phase
USART Last Bit
USART Request Parameters
USART Flags

Elements values convention: 0xXXXX.

USART Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

USART Interruption Clear Flags
USART Interruption Flags Mask
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STM32L486xx HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

USART Transmit and Receive functions.

Peripheral State and Error functions

USART Peripheral State and Error functions.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Exported Init structures

Data Structures
USART Exported Init structures
USART

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...
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STM32L486xx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

Clear Flags Defines

Flags defines which can be used with LL_USART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_USART_ReadReg function.

IT Defines

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

Communication Direction
Parity Control
Wakeup
Datawidth
Oversampling
Clock Signal
Last Clock Pulse
Clock Phase
Clock Polarity
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Autobaud Detection
Address Length Detection
Hardware Control
Wakeup Activation
IrDA Power
LIN Break Detection Length
Driver Enable Polarity
DMA Register Data
Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Configuration functions
Configuration functions related to Irda feature
Configuration functions related to Smartcard feature
Configuration functions related to Half Duplex feature
Configuration functions related to LIN feature
Configuration functions related to Driver Enable feature
Advanced Configurations services
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: USART Exported Macros

Modules
USART Exported Macros
USART

Modules

Common Write and read registers Macros
Exported_Macros_Helper
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STM32L486xx HAL User Manual: USARTEx

Modules
USARTEx
STM32L4xx_HAL_Driver

Modules

USARTEx Exported Constants
USARTEx Private Macros
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STM32L486xx HAL User Manual: USARTEx Exported Constants

Modules
USARTEx Exported Constants
USARTEx

Modules

USARTEx Word Length
Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UTILS

Modules
UTILS
STM32L4xx_LL_Driver

Modules

UTILS Private functions
UTILS Private Constants
UTILS Private Macros
UTILS Exported structures
UTILS Exported Constants
UTILS Exported Functions
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STM32L486xx HAL User Manual: UTILS Exported structures

Data Structures
UTILS Exported structures
UTILS

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...
Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UTILS Exported Constants

Modules
UTILS Exported Constants
UTILS

Modules

HSE Bypass activation
PACKAGE TYPE
Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: UTILS Exported Functions

Modules
UTILS Exported Functions
UTILS

Modules

DEVICE ELECTRONIC SIGNATURE
DELAY
SYSTEM

System Configuration functions.

Generated on Wed Jun 1 2016 16:28:28 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG

Modules
WWDG
STM32L4xx_HAL_Driver

WWDG HAL module driver. More...

Modules

WWDG Exported Functions
WWDG Exported Types
WWDG Exported Constants
WWDG Private Macros
WWDG Exported Macros

Detailed Description

WWDG HAL module driver.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

WWDG Interrupt definition
WWDG Flag definition

WWDG Flag definition.

WWDG Prescaler
WWDG Early Wakeup Interrupt Mode
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STM32L486xx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Exported Types

Data Structures
WWDG Exported Types
WWDG

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...
Generated on Wed Jun 1 2016 16:28:23 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

IT Defines

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

PRESCALER
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Configuration
FLAG_Management
IT_Management
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: WWDG Exported Macros

Modules
WWDG Exported Macros
WWDG

Modules

Common Write and read registers macros
Generated on Wed Jun 1 2016 16:28:29 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: I2C_rmtollPages.txt File Reference

  • File List
  • Globals
I2C_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: IWDG_rmtollPages.txt File Reference

  • File List
  • Globals
IWDG_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPTIM_rmtollPages.txt File Reference

  • File List
  • Globals
LPTIM_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: LPUART_rmtollPages.txt File Reference

  • File List
  • Globals
LPUART_rmtollPages.txt File Reference
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: Modules

Modules
Here is a list of all modules:
  • STM32L4xx_LL_Driver
    • ADC
      • ADC Private Constants
      • ADC Private Macros
      • ADC Exported Init structure
      • ADC Exported Constants
        • ADC flags
        • ADC interruptions for configuration (interruption enable or disable)
        • ADC registers compliant with specific purpose
        • ADC common - Clock source
        • ADC common - Measurement path to internal channels
        • ADC instance - Resolution
        • ADC instance - Data alignment
        • ADC instance - Low power mode
        • ADC instance - Offset number
        • ADC instance - Offset state
        • ADC instance - Groups
        • ADC instance - Channel number
        • ADC group regular - Trigger source
        • ADC group regular - Trigger edge
        • ADC group regular - Continuous mode
        • ADC group regular - DMA transfer of ADC conversion data
        • ADC group regular - Overrun behavior on conversion data
        • ADC group regular - Sequencer scan length
        • ADC group regular - Sequencer discontinuous mode
        • ADC group regular - Sequencer ranks
        • ADC group injected - Trigger source
        • ADC group injected - Trigger edge
        • ADC group injected - Automatic trigger mode
        • ADC group injected - Context queue mode
        • ADC group injected - Sequencer scan length
        • ADC group injected - Sequencer discontinuous mode
        • ADC group injected - Sequencer ranks
        • Channel - Sampling time
        • Channel - Single or differential ending
        • Analog watchdog - Analog watchdog number
        • Analog watchdog - Monitored channels
        • Analog watchdog - Thresholds
        • Oversampling - Oversampling scope
        • Oversampling - Discontinuous mode
        • Oversampling - Ratio
        • Oversampling - Data shift
        • Multimode - Mode
        • Multimode - DMA transfer
        • Multimode - Delay between two sampling phases
        • Multimode - ADC master or slave
        • ADC literals legacy naming
        • Definitions of ADC hardware constraints delays
      • ADC Exported Macros
        • Common write and read registers Macros
        • ADC helper macro
      • ADC Exported Functions
        • ADC DMA management
        • Configuration of ADC hierarchical scope: common to several ADC instances
        • Configuration of ADC hierarchical scope: ADC instance
        • Configuration of ADC hierarchical scope: group regular
        • Configuration of ADC hierarchical scope: group injected
        • Configuration of ADC hierarchical scope: channels
        • Configuration of ADC transversal scope: analog watchdog
        • Configuration of ADC transversal scope: oversampling
        • Configuration of ADC hierarchical scope: multimode
        • Configuration of ADC alternate functions name
        • Operation on ADC hierarchical scope: ADC instance
        • Operation on ADC hierarchical scope: group regular
        • Operation on ADC hierarchical scope: group injected
        • ADC flag management
        • ADC IT management
        • Initialization and de-initialization functions
    • BUS
      • BUS Exported Constants
        • AHB1 GRP1 PERIPH
        • AHB2 GRP1 PERIPH
        • AHB3 GRP1 PERIPH
        • APB1 GRP1 PERIPH
        • APB1 GRP2 PERIPH
        • APB2 GRP1 PERIPH
      • BUS Exported Functions
        • AHB1
        • AHB2
        • AHB3
        • APB1
        • APB2
    • COMP
      • COMP Private Constants
      • COMP Exported Init structure
      • COMP Exported Constants
        • Comparator common modes - Window mode
        • Comparator modes - Power mode
        • Comparator inputs - Input plus (input non-inverting) selection
        • Comparator inputs - Input minus (input inverting) selection
        • Comparator inputs legacy literals name
        • Comparator input - Hysteresis
        • Comparator output - Output polarity
        • Comparator output - Blanking source
        • Comparator output blanking source legacy literals name
        • Comparator output - Output level
        • Definitions of COMP hardware constraints delays
      • COMP Exported Macros
        • Common write and read registers macro
        • COMP helper macro
      • COMP Exported Functions
        • Configuration of COMP hierarchical scope: common to several COMP instances
        • Configuration of comparator modes
        • Configuration of comparator inputs
        • Configuration of comparator output
        • Configuration of COMP, legacy functions name
        • Operation on comparator instance
        • Initialization and de-initialization functions
      • COMP_LL_Private_Macros
    • CORTEX
      • CORTEX Exported Constants
        • SYSTICK Clock Source
        • Handler Fault type
        • MPU Control
        • MPU Region Number
        • MPU Region Size
        • MPU Region Privileges
        • MPU TEX Level
        • MPU Instruction Access
        • MPU Shareable Access
        • MPU Cacheable Access
        • MPU Bufferable Access
      • CORTEX Exported Functions
        • SYSTICK
        • LOW POWER MODE
        • HANDLER
        • MCU INFO
        • MPU
    • CRC
      • CRC Exported Constants
        • Polynomial length
        • Input Data Reverse
        • Output Data Reverse
        • Default CRC generating polynomial value
        • Default CRC computation initialization value
      • CRC Exported Macros
        • Common Write and read registers Macros
      • CRC Exported Functions
        • CRC Configuration functions
        • Data_Management
        • Initialization and de-initialization functions
    • DAC
      • DAC Private Constants
      • DAC Private Macros
      • DAC Exported Init structure
      • DAC Exported Constants
        • DAC flags
        • DAC interruptions
        • DAC channels
        • DAC operating mode
        • DAC trigger source
        • DAC waveform automatic generation mode
        • DAC wave generation - Noise LFSR unmask bits
        • DAC wave generation - Triangle amplitude
        • DAC channel output mode
        • DAC channel output buffer
        • DAC channel output connection
        • DAC literals legacy naming
        • DAC channel output resolution
        • DAC registers compliant with specific purpose
        • Definitions of DAC hardware constraints delays
      • DAC Exported Macros
        • Common write and read registers macros
        • DAC helper macro
      • DAC Exported Functions
        • Configuration of DAC channels
        • DAC configuration, legacy functions name
        • DMA Management
        • Operation on DAC channels
        • FLAG Management
        • IT management
        • Initialization and de-initialization functions
    • DMA
      • DMA Private Variables
      • DMA Private Constants
      • DMA Private Macros
      • DMA Exported Init structure
      • DMA Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • CHANNEL
        • Transfer Direction
        • Transfer mode
        • Peripheral increment mode
        • Memory increment mode
        • Peripheral data alignment
        • Memory data alignment
        • Transfer Priority level
        • Transfer peripheral request
      • DMA Exported Macros
        • Common Write and read registers macros
        • Convert DMAxChannely
      • DMA Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • EXTI
      • EXTI Private Macros
      • EXTI Exported Init structure
      • EXTI Exported Constants
        • LINE
        • Mode
        • Edge Trigger
      • EXTI Exported Macros
        • Common Write and read registers Macros
      • EXTI Exported Functions
        • IT_Management
        • Event_Management
        • Rising_Trigger_Management
        • Falling_Trigger_Management
        • Software_Interrupt_Management
        • Flag_Management
        • Initialization and de-initialization functions
    • GPIO
      • GPIO Private Macros
      • GPIO Exported Init structures
      • GPIO Exported Constants
        • PIN
        • Mode
        • Output Type
        • Output Speed
        • Pull Up Pull Down
        • Alternate Function
      • GPIO Exported Macros
        • Common Write and read registers Macros
      • GPIO Exported Functions
        • Port Configuration
        • Data Access
        • Initialization and de-initialization functions
    • I2C
      • I2C Private Constants
      • I2C Private Macros
      • I2C Exported Init structure
      • I2C Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Peripheral Mode
        • Analog Filter Selection
        • Master Addressing Mode
        • Own Address 1 Length
        • Own Address 2 Masks
        • Acknowledge Generation
        • Slave Address Length
        • Transfer Request Direction
        • Transfer End Mode
        • Start And Stop Generation
        • Read Write Direction
        • DMA Register Data
        • SMBus TimeoutA Mode SCL SDA Timeout
        • SMBus Timeout Selection
      • I2C Exported Macros
        • Common Write and read registers Macros
        • Convert SDA SCL timings
      • I2C Exported Functions
        • Configuration
        • IT_Management
        • FLAG_management
        • Data_Management
        • Initialization and de-initialization functions
    • IWDG
      • IWDG Private Constants
      • IWDG Exported Constants
        • Get Flags Defines
        • Prescaler Divider
      • IWDG Exported Macros
        • Common Write and read registers Macros
      • IWDG Exported Functions
        • Configuration
        • FLAG_Management
    • LPTIM
      • LPTIM Private Macros
      • LPTIM Exported Init structure
      • LPTIM Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operating Mode
        • Update Mode
        • Counter Mode
        • Output Waveform Type
        • Output Polarity
        • Prescaler Value
        • Trigger Source
        • Trigger Filter
        • Trigger Polarity
        • Clock Source
        • Clock Filter
        • Clock Polarity
        • Encoder Mode
        • Input1 Source
        • Input2 Source
      • LPTIM Exported Macros
        • Common Write and read registers Macros
      • LPTIM Exported Functions
        • LPTIM Configuration
        • Trigger Configuration
        • Clock Configuration
        • Encoder Mode
        • FLAG Management
        • Interrupt Management
        • Initialisation and deinitialisation functions
    • LPUART
      • LPUART Private Constants
      • LPUART Private Macros
      • LPUART Exported Init structures
      • LPUART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • Driver Enable Polarity
        • DMA Register Data
      • LPUART Exported Macros
        • Common Write and read registers Macros
        • Helper Macros
      • LPUART Exported Functions
        • Configuration functions
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to Driver Enable feature
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • OPAMP
      • OPAMP Private Constants
      • OPAMP Private Macros
      • OPAMP Exported Init structure
      • OPAMP Exported Constants
        • OPAMP power supply range
        • OPAMP power mode
        • OPAMP mode calibration or functional.
        • OPAMP functional mode
        • OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
        • OPAMP input non-inverting
        • OPAMP input inverting
        • OPAMP inputs legacy literals name
        • OPAMP trimming mode
        • OPAMP trimming of transistors differential pair NMOS or PMOS
      • OPAMP Exported Macros
        • Common write and read registers macro
        • OPAMP helper macro
      • OPAMP Exported Functions
        • Configuration of OPAMP hierarchical scope: common to several OPAMP instances
        • Configuration of OPAMP hierarchical scope: OPAMP instance
        • Configuration of OPAMP inputs
        • Configuration of OPAMP, legacy functions name
        • Configuration and operation of OPAMP trimming
        • Operation on OPAMP instance
        • Initialization and de-initialization functions
    • PWR
      • PWR Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • REGU VOLTAGE
        • MODE PWR
        • PVM VDDUSB 1
        • PVDLEVEL
        • WAKEUP
        • BATT CHARG RESISTOR
        • GPIO
        • GPIO BIT
      • PWR Exported Macros
        • Common Write and read registers Macros
      • PWR Exported Functions
        • Configuration
        • FLAG_Management
          • De-initialization function
        • De-initialization function
    • RCC
      • RCC Private functions
      • RCC Private Variables
      • RCC Private Constants
      • RCC Private Macros
      • RCC Exported Types
        • Clocks Frequency Structure
      • RCC Exported Constants
        • Oscillator Values adaptation
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • LSE oscillator drive capability
        • MSI clock ranges
        • MSI range after Standby mode
        • LSCO Selection
        • System clock switch
        • System clock switch status
        • AHB prescaler
        • APB low-speed prescaler (APB1)
        • APB high-speed prescaler (APB2)
        • Wakeup from Stop and CSS backup clock selection
        • MCO1 SOURCE selection
        • MCO1 prescaler
        • Peripheral clock frequency
        • Peripheral USART clock source selection
        • Peripheral UART clock source selection
        • Peripheral LPUART clock source selection
        • Peripheral I2C clock source selection
        • Peripheral LPTIM clock source selection
        • Peripheral SAI clock source selection
        • Peripheral SDMMC clock source selection
        • Peripheral RNG clock source selection
        • Peripheral USB clock source selection
        • Peripheral ADC clock source selection
        • Peripheral SWPMI clock source selection
        • Peripheral DFSDM clock source selection
        • Peripheral USART get clock source
        • Peripheral UART get clock source
        • Peripheral LPUART get clock source
        • Peripheral I2C get clock source
        • Peripheral LPTIM get clock source
        • Peripheral SAI get clock source
        • Peripheral SDMMC get clock source
        • Peripheral RNG get clock source
        • Peripheral USB get clock source
        • Peripheral ADC get clock source
        • Peripheral SWPMI get clock source
        • Peripheral DFSDM get clock source
        • RTC clock source selection
        • PLL, PLLSAI1 and PLLSAI2 entry clock source
        • PLL, PLLSAI1 and PLLSAI2 division factor
        • PLL division factor (PLLR)
        • PLL division factor (PLLP)
        • PLL division factor (PLLQ)
        • PLLSAI1 division factor (PLLSAI1Q)
        • PLLSAI1 division factor (PLLSAI1P)
        • PLLSAI1 division factor (PLLSAI1R)
        • PLLSAI2 division factor (PLLSAI2P)
        • PLLSAI2 division factor (PLLSAI2R)
        • MSI clock range selection
      • RCC Exported Macros
        • Common Write and read registers Macros
        • Calculate frequencies
      • RCC Exported Functions
        • HSE
        • HSI
        • LSE
        • LSI
        • MSI
        • LSCO
        • System
        • MCO
        • Peripheral Clock Source
        • RTC
        • PLL
        • PLLSAI1
        • PLLSAI2
        • FLAG Management
        • IT Management
        • De-initialization function
        • Get system and peripherals clocks frequency functions
    • RNG
      • RNG Exported Constants
        • Get Flags Defines
        • IT Defines
      • RNG Exported Macros
        • Common Write and read registers Macros
      • RNG Exported Functions
        • RNG Configuration functions
        • FLAG Management
        • IT Management
        • Data Management
        • Initialization and de-initialization functions
    • RTC
      • RTC Private Constants
      • RTC Private Macros
      • RTC Exported Init structure
      • RTC Exported Constants
        • FORMAT
        • RTC Alarm A Date WeekDay
        • RTC Alarm B Date WeekDay
        • Get Flags Defines
        • IT Defines
        • WEEK DAY
        • MONTH
        • HOUR FORMAT
        • ALARM OUTPUT
        • ALARM OUTPUT TYPE
        • OUTPUT POLARITY PIN
        • TIME FORMAT
        • SHIFT SECOND
        • ALARMA MASK
        • ALARMA TIME FORMAT
        • ALARMB MASK
        • ALARMB TIME FORMAT
        • TIMESTAMP EDGE
        • TIMESTAMP TIME FORMAT
        • TAMPER
        • TAMPER MASK
        • TAMPER NO ERASE
        • TAMPER DURATION
        • TAMPER FILTER
        • TAMPER SAMPLING FREQUENCY DIVIDER
        • TAMPER ACTIVE LEVEL
        • WAKEUP CLOCK DIV
        • BACKUP
        • Calibration output
        • Calibration pulse insertion
        • Calibration period
      • RTC Exported Macros
        • Common Write and read registers Macros
        • Convert helper Macros
        • Date helper Macros
        • Time helper Macros
      • RTC Exported Functions
        • Configuration
        • Time
        • Date
        • ALARMA
        • ALARMB
        • Timestamp
        • Tamper
        • Wakeup
        • Backup_Registers
        • Calibration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • SPI
      • SPI Private Constants
      • SPI Private Macros
      • SPI Exported Init structure
      • SPI Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operation Mode
        • Serial Protocol
        • Clock Phase
        • Clock Polarity
        • Baud Rate Prescaler
        • Transmission Bit Order
        • Transfer Mode
        • Slave Select Pin Mode
        • Datawidth
        • CRC Calculation
        • CRC Length
        • RX FIFO Threshold
        • RX FIFO Level
        • TX FIFO Level
        • DMA Parity
      • SPI Exported Macros
        • Common Write and read registers Macros
      • SPI Exported Functions
        • Configuration
        • CRC Management
        • Slave Select Pin Management
        • FLAG Management
        • Interrupt Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • SWPMI
      • SWPMI Private Macros
      • SWPMI Exported Init structure
      • SWPMI Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • SW BUFFER RX
        • SW BUFFER TX
        • VOLTAGE CLASS
        • DMA register data
      • SWPMI Exported Macros
        • Common Write and read registers Macros
        • Bit rate calculation helper Macros
      • SWPMI Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Initialization and de-initialization functions
    • SYSTEM
      • SYSTEM Private Constants
      • SYSTEM Exported Constants
        • SYSCFG REMAP
        • SYSCFG BANK MODE
        • SYSCFG I2C FASTMODEPLUS
        • SYSCFG EXTI PORT
        • SYSCFG EXTI LINE
        • SYSCFG TIMER BREAK
        • SYSCFG SRAM2 WRP
        • DBGMCU TRACE Pin Assignment
        • DBGMCU APB1 GRP1 STOP IP
        • DBGMCU APB1 GRP2 STOP IP
        • DBGMCU APB2 GRP1 STOP IP
        • VREFBUF VOLTAGE
        • FLASH LATENCY
      • SYSTEM Exported Functions
        • SYSCFG
        • DBGMCU
        • VREFBUF
        • FLASH
    • TIM
      • TIM Private Functions
      • TIM Private Variables
      • TIM Private Constants
        • Bit Position Value
      • TIM Private Macros
      • TIM Exported Init structure
      • TIM Exported Constants
        • Get Flags Defines
        • IT Defines
        • Update Source
        • One Pulse Mode
        • Counter Mode
        • Clock Division
        • Counter Direction
        • Capture Compare Update Source
        • Capture Compare DMA Request
        • Lock Level
        • Channel
        • Output Configuration State
        • Output Configuration Mode
        • Output Configuration Polarity
        • Output Configuration Idle State
        • GROUPCH5
        • Active Input Selection
        • Input Configuration Prescaler
        • Input Configuration Filter
        • Input Configuration Polarity
        • Clock Source
        • Encoder Mode
        • Trigger Output
        • Trigger Output 2
        • Slave Mode
        • Trigger Selection
        • External Trigger Polarity
        • External Trigger Prescaler
        • External Trigger Filter
        • External Trigger Source
        • break polarity
        • break filter
        • BREAK2 POLARITY
        • BREAK2 FILTER
        • OSSI
        • OSSR
        • BREAK INPUT
        • BKIN SOURCE
        • BKIN POLARITY
        • DMA Burst Base Address
        • DMA Burst Length
        • TIM1 External Trigger ADC1 Remap
        • TIM1 External Trigger ADC3 Remap
        • TIM1 External Input Ch1 Remap
        • TIM2 Internal Trigger1 Remap TIM8
        • TIM2 External Input Ch4 Remap
        • TIM3 External Input Ch1 Remap
        • TIM8 External Trigger ADC2 Remap
        • TIM8 External Trigger ADC3 Remap
        • TIM8 External Input Ch1 Remap
        • TIM15 External Input Ch1 Remap
        • TIM15 ENCODERMODE
        • TIM16 External Input Ch1 Remap
        • TIM17 Timer Input Ch1 Remap
        • OCREF clear input selection
      • TIM Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros
      • TIM Exported Functions
        • Time Base configuration
        • Capture Compare configuration
        • Output channel configuration
        • Input channel configuration
        • Counter clock selection
        • Timer synchronisation configuration
        • Break function configuration
        • DMA burst mode configuration
        • Timer input remapping
        • OCREF_Clear_Management
        • FLAG-Management
        • IT-Management
        • DMA-Management
        • EVENT-Management
        • Initialisation and deinitialisation functions
    • USART
      • USART Private Constants
      • USART Private Macros
      • USART Exported Init structures
      • USART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Communication Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Oversampling
        • Clock Signal
        • Last Clock Pulse
        • Clock Phase
        • Clock Polarity
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Autobaud Detection
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • IrDA Power
        • LIN Break Detection Length
        • Driver Enable Polarity
        • DMA Register Data
      • USART Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Helper
      • USART Exported Functions
        • Configuration functions
        • Configuration functions related to Irda feature
        • Configuration functions related to Smartcard feature
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to LIN feature
        • Configuration functions related to Driver Enable feature
        • Advanced Configurations services
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • UTILS
      • UTILS Private functions
      • UTILS Private Constants
      • UTILS Private Macros
      • UTILS Exported structures
      • UTILS Exported Constants
        • HSE Bypass activation
        • PACKAGE TYPE
      • UTILS Exported Functions
        • DEVICE ELECTRONIC SIGNATURE
        • DELAY
        • SYSTEM
    • WWDG
      • WWDG Exported Constants
        • IT Defines
        • PRESCALER
      • WWDG Exported Macros
        • Common Write and read registers macros
      • WWDG Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
  • STM32L4xx_HAL_Driver
    • HAL
      • HAL Exported Functions
        • Initialization and de-initialization Functions
        • HAL Control functions
        • HAL Debug functions
        • HAL SYSCFG configuration functions
      • SYSCFG Exported Constants
        • Boot Mode
        • FPU Interrupts
        • SRAM2 Write protection
        • VREFBUF Voltage Scale
        • VREFBUF High Impedance
        • Flags
        • Fast-mode Plus on GPIO
      • DBGMCU Exported Macros
      • SYSCFG Exported Macros
      • SYSCFG Private Macros
    • ADC
      • ADC Private Constants
      • ADC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • ADC Private Functions
      • ADC Exported Types
        • ADC States
      • ADC Exported Constants
        • ADC Error Code
        • ADC Clock Prescaler
        • ADC Resolution
        • ADC Data Alignment
        • ADC Scan Mode
        • ADC External Trigger Source Edge for Regular Group
        • ADC External Trigger Source for Regular Group
        • ADC End of Regular Sequence/Conversion
        • ADC overrun
        • ADC Channels
      • ADC Private Macros
      • ADC Exported Macros
    • ADCEx
      • ADC Extended Private Constants
      • ADC Extended Exported Functions
        • Extended Input and Output operation functions
        • Extended Peripheral Control functions
      • ADC Extended Exported Types
      • ADC Extended Exported Constants
        • ADC Extended Single-ended/Differential input mode
        • ADC Extended Offset Number
        • ADC Extended Regular Channel Rank
        • ADC Extended Injected Channel Rank
        • ADC External Trigger Source Edge for Injected Group
        • ADC Extended External Trigger Source for Injected Group
        • ADC Extended Dual ADC Mode
        • ADC Extended DMA Mode for Dual ADC Mode
        • ADC Extended Delay Between 2 Sampling Phases
        • ADC Extended Analog Watchdog Selection
        • ADC Extended Analog Watchdog Mode
        • ADC Extended Conversion Group
        • ADC Extended Event Type
        • ADC Extended Interrupts Definition
        • ADC Extended Flags Definition
        • ADC Extended Oversampling Ratio
        • ADC Extended Oversampling Right Shift
        • ADC Extended Triggered Regular Oversampling
        • ADC Extended Regular Oversampling Continued or Resumed Mode
        • ADC Sampling Times
        • ADCx CFGR fields
        • ADCx SMPR1 fields
        • ADCx CFGR sub fields
      • ADC Extended Private Macros
    • CAN
      • CAN Private Constants
        • CAN Transmit Constants
      • CAN Private Functions
      • CAN Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral State and Error functions
      • CAN Exported Types
      • CAN Exported Constants
        • CAN Error Code
        • CAN initialization Status
        • CAN Operating Mode
        • CAN Synchronization Jump Width
        • CAN Time Quantum in Bit Segment 1
        • CAN Time Quantum in Bit Segment 2
        • CAN Filter Mode
        • CAN Filter Scale
        • CAN Filter FIFO
        • CAN Identifier Type
        • CAN Remote Transmission Request
        • CAN Receive FIFO Number
        • CAN Flags
        • CAN Interrupts
      • CAN Exported Macros
      • CAN Private Macros
    • COMP
      • COMP Exported Functions
        • Initialization/de-initialization functions
        • Start-Stop operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • COMP Exported Types
      • COMP Exported Constants
        • COMP Window Mode
        • COMP power mode
        • COMP input plus (non-inverting input)
        • COMP input minus (inverting input)
        • COMP hysteresis
        • COMP output Polarity
        • COMP blanking source
        • COMP Output Level
        • COMP output to EXTI
      • COMP Exported Macros
        • COMP Handle Management
        • COMP external interrupt line management
      • COMP Private Constants
        • COMP EXTI Lines
      • COMP Private Macros
        • COMP private macros to get EXTI line associated with comparators
        • COMP private macros to check input parameters
    • CORTEX
      • CORTEX Exported Types
        • MPU Region Initialization Structure Definition
      • CORTEX Exported Constants
        • CORTEX Preemption Priority Group
        • CORTEX SysTick clock source
        • CORTEX MPU HFNMI and PRIVILEGED Access control
        • CORTEX MPU Region Enable
        • CORTEX MPU Instruction Access
        • CORTEX MPU Instruction Access Shareable
        • CORTEX MPU Instruction Access Cacheable
        • CORTEX MPU Instruction Access Bufferable
        • CORTEX MPU TEX Levels
        • CORTEX MPU Region Size
        • CORTEX MPU Region Permission Attributes
        • CORTEX MPU Region Number
      • CORTEX Exported Macros
      • CORTEX Exported Functions
        • Initialization and Configuration functions
        • Peripheral Control functions
      • CORTEX Private Macros
    • CRC
      • CRC Private Functions
      • CRC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • CRC Exported Types
      • CRC Exported Constants
        • Default CRC generating polynomial
        • Default CRC computation initialization value
        • Indicates whether or not default polynomial is used
        • Indicates whether or not default init value is used
        • Polynomial sizes to configure the IP
        • CRC polynomial possible sizes actual definitions
        • Input Buffer Format
        • CRC API aliases
      • CRC Exported Macros
      • CRC Private Macros
    • CRCEx
      • CRC Extended Exported Functions
        • Extended Initialization/de-initialization functions
      • CRCEx Exported Constants
        • Input Data Inversion Modes
        • Output Data Inversion Modes
      • CRCEx Exported Macros
      • CRCEx Private Macros
    • CRYP
      • CRYP Private Functions
      • CRYP Exported Functions
        • Initialization and deinitialization functions
        • AES processing functions
        • Callback functions
        • CRYP IRQ handler
        • Peripheral State functions
      • CRYP Exported Types
      • CRYP Exported Constants
        • Key size selection
        • AES Data Type selection
        • AES Enable state
        • AES operating mode
        • AES chaining mode
        • AES decryption key write-up flag
        • DMA Input phase management enable state
        • DMA Output phase management enable state
        • GCM/GMAC and CMAC processing phase selection
        • AES status flags
        • AES clearing flags
        • AES Interrupts Enable bits
        • AES Interrupts flags
      • CRYP Exported Macros
      • CRYP Private Macros
    • CRYPEx
      • CRYPEx Private Constants
      • CRYPEx Private Functions
      • CRYPEx Exported Functions
        • Extended callback function
        • AES extended processing functions
        • AES suspension/resumption functions
    • DAC
      • DAC Private Functions
      • DAC Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • DAC Exported Types
      • DAC Exported Constants
        • DAC Error Code
        • DAC trigger selection
        • DAC output buffer
        • DAC Channel selection
        • DAC data alignment
        • DAC flags definition
        • DAC IT definition
        • DAC ConnectOnChipPeripheral
        • DAC User Trimming
        • DAC power mode
      • DAC Exported Macros
      • DAC Private Macros
      • DAC Private Constants
    • DACEx
      • DACEx Exported Functions
        • IO operation functions
        • Peripheral Control functions
      • DACEx private functions
      • DACEx Exported Constants
        • DACEx lfsrunmask triangleamplitude
      • DACEx Private Macros
    • DFSDM
      • DFSDM Private Define
      • DFSDM Private Variables
      • DFSDM Private Functions
      • DFSDM Exported Functions
        • Channel initialization and de-initialization functions
        • Channel operation functions
        • Channel state function
        • Filter initialization and de-initialization functions
        • Filter control functions
        • Filter operation functions
        • Filter state functions
      • DFSDM Exported Types
      • DFSDM Exported Constants
        • DFSDM channel output clock selection
        • DFSDM channel input multiplexer
        • DFSDM channel input data packing
        • DFSDM channel input pins
        • DFSDM channel serial interface type
        • DFSDM channel SPI clock selection
        • DFSDM channel analog watchdog filter order
        • DFSDM filter conversion trigger
        • DFSDM filter external trigger
        • DFSDM filter external trigger edge
        • DFSDM filter sinc order
        • DFSDM filter analog watchdog data source
        • DFSDM filter error code
        • DFSDM break signals
        • DFSDM Channel Selection
        • DFSDM Continuous Mode
        • DFSDM analog watchdog threshold
      • DFSDM Exported Macros
      • DFSDM Private Macros
    • DMA
      • DMA Private Functions
      • DMA Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral State and Errors functions
      • DMA Exported Types
      • DMA Exported Constants
        • DMA Error Code
        • DMA request
        • DMA Data transfer direction
        • DMA Peripheral incremented mode
        • DMA Memory incremented mode
        • DMA Peripheral data size
        • DMA Memory data size
        • DMA mode
        • DMA Priority level
        • DMA interrupt enable definitions
        • DMA flag definitions
      • DMA Exported Macros
      • DMA Private Macros
    • FIREWALL
      • FIREWALL Exported Functions
        • Initialization Functions
      • FIREWALL Exported Types
      • FIREWALL Exported Constants
        • FIREWALL volatile data segment execution status
        • FIREWALL volatile data segment share status
        • FIREWALL pre arm status
      • FIREWALL Private Macros
      • FIREWALL Exported Macros
    • FLASH
      • FLASH Private Variables
      • FLASH Private Functions
      • FLASH Exported Functions
        • Programming operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Error
        • FLASH Erase Type
        • FLASH Banks
        • FLASH Program Type
        • FLASH Option Bytes Type
        • FLASH WRP Area
        • FLASH Option Bytes Read Protection
        • FLASH Option Bytes User Type
        • FLASH Option Bytes User BOR Level
        • FLASH Option Bytes User Reset On Stop
        • FLASH Option Bytes User Reset On Standby
        • FLASH Option Bytes User Reset On Shutdown
        • FLASH Option Bytes User IWDG Type
        • FLASH Option Bytes User IWDG Mode On Stop
        • FLASH Option Bytes User IWDG Mode On Standby
        • FLASH Option Bytes User WWDG Type
        • FLASH Option Bytes User BFB2 Mode
        • FLASH Option Bytes User Dual-bank Type
        • FLASH Option Bytes User BOOT1 Type
        • FLASH Option Bytes User SRAM2 Parity Check Type
        • FLASH Option Bytes User SRAM2 Erase On Reset Type
        • FLASH Option Bytes PCROP On RDP Level Type
        • FLASH Latency
        • FLASH Keys
        • FLASH Flags Definition
        • FLASH Interrupts Definition
      • FLASH Exported Macros
      • FLASH Interrupts Macros
      • FLASH Private Constants
      • FLASH Private Macros
    • FLASHEx
      • FLASHEx Private Variables
      • FLASHEx Private Functions
      • FLASH Extended Exported Functions
        • Extended IO operation functions
    • FLASH_RAMFUNC
      • FLASH in RAM function Exported Functions
        • Peripheral features functions
    • GPIO
      • GPIO Private Defines
      • GPIO Private Macros
      • GPIO Exported Functions
        • Initialization/de-initialization functions
        • IO operation functions
      • GPIO Exported Types
      • GPIO Exported Constants
        • GPIO pins
        • GPIO mode
        • GPIO speed
        • GPIO pull
      • GPIO Exported Macros
    • GPIOEx
      • GPIOEx Exported Constants
        • GPIOEx Alternate function selection
      • GPIOEx Exported Macros
        • GPIOEx_Get Port Index
    • HCD
      • HCD Private Functions
      • HCD Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • HCD Exported Types
        • HCD State Structure definition
        • HCD Handle Structure definition
      • HCD Exported Constants
        • HCD Speed
        • HCD PHY Module
      • HCD Exported Macros
      • HCD Private Macros
    • I2C
      • I2C Private Define
      • I2C Private Functions
      • I2C Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • IRQ Handler and Callbacks
        • Peripheral State, Mode and Error functions
      • I2C Exported Types
        • I2C Configuration Structure definition
        • HAL state structure definition
        • HAL mode structure definition
        • I2C Error Code definition
        • I2C handle Structure definition
      • I2C Exported Constants
        • I2C Sequential Transfer Options
        • I2C Addressing Mode
        • I2C Dual Addressing Mode
        • I2C Own Address2 Masks
        • I2C General Call Addressing Mode
        • I2C No-Stretch Mode
        • I2C Memory Address Size
        • I2C Transfer Direction
        • I2C Reload End Mode
        • I2C Start or Stop Mode
        • I2C Interrupt configuration definition
        • I2C Flag definition
      • I2C Exported Macros
      • I2C Private Constants
      • I2C Private Macros
    • I2CEx
      • I2C Extended Exported Functions
        • Extended features functions
          • I2C Extended Private Constants
          • I2C Extended Private Macros
          • I2C Extended Private Functions
      • I2C Extended Exported Constants
        • I2C Extended Analog Filter
        • I2C Extended Fast Mode Plus
    • IRDA
      • IRDA Private Constants
      • IRDA Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • IRDA Private Functions
      • IRDA Exported Types
      • IRDA Exported Constants
        • IRDA Word Length
        • IRDA Parity
        • IRDA Transfer Mode
        • IRDA Low Power
        • IRDA State
        • IRDA Mode
        • IRDA One Bit Sampling
        • IRDA DMA Tx
        • IRDA DMA Rx
        • IRDA Request Parameters
        • IRDA Flags
        • IRDA Interrupts Definition
        • IRDA Interruption Clear Flags
        • IRDA interruptions flags mask
      • IRDA Exported Macros
      • IRDA Private Macros
    • IWDG
      • IWDG Private Defines
      • IWDG Exported Types
      • IWDG Exported Constants
        • IWDG Prescaler
        • IWDG Window option
      • IWDG Exported Macros
      • IWDG Exported Functions
        • Initialization and Start functions
        • IO operation functions
      • IWDG Private Constants
      • IWDG Private Macros
    • LCD
      • LCD Private Defines
      • LCD Exported Functions
        • Initialization/de-initialization methods
        • IO operation methods
        • Peripheral State methods
      • LCD Private Functions
      • LCD Exported Types
      • LCD Exported Constants
        • LCD Error Code
        • LCD Prescaler
        • LCD Divider
        • LCD Duty
        • LCD Bias
        • LCD Voltage Source
        • LCD Interrupts
        • LCD Pulse On Duration
        • LCD Dead Time
        • LCD Blink Mode
        • LCD Blink Frequency
        • LCD Contrast
        • LCD RAMRegister
        • LCD High Drive
        • LCD Mux Segment
        • LCD Flags Definition
      • LCD Exported Macros
      • LCD Private Macros
    • LPTIM
      • LPTIM Exported Functions
        • Initialization/de-initialization functions
        • LPTIM Start-Stop operation functions
        • LPTIM Read operation functions
        • LPTIM IRQ handler and callbacks
        • Peripheral State functions
      • LPTIM Exported Types
      • LPTIM Exported Constants
        • LPTIM Clock Source
        • LPTIM Clock Prescaler
        • LPTIM Output Polarity
        • LPTIM Clock Sample Time
        • LPTIM Clock Polarity
        • LPTIM Trigger Source
        • LPTIM External Trigger Polarity
        • LPTIM Trigger Sample Time
        • LPTIM Updating Mode
        • LPTIM Counter Source
        • LPTIM Input1 Source
        • LPTIM Input2 Source
        • LPTIM Flags Definition
        • LPTIM Interrupts Definition
      • LPTIM Exported Macros
      • LPTIM Private Types
      • LPTIM Private Variables
      • LPTIM Private Constants
      • LPTIM Private Macros
      • LPTIM Private Functions
    • NAND
      • NAND Private Constants
      • NAND Private Macros
      • NAND Private Functions
      • NAND Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • Peripheral Control functions
        • Peripheral State functions
      • NAND Exported Types
      • NAND Exported Macros
    • NOR
      • NOR Private Constants
      • NOR Private Macros
      • NOR Private Variables
      • NOR Exported Functions
        • Initialization and de-initialization functions
        • Input and Output functions
        • Peripheral Control functions
        • Peripheral State functions
      • NOR Exported Types
      • NOR Exported Macros
    • OPAMP
      • OPAMP Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • OPAMP Exported Types
      • OPAMP Exported Constants
        • OPAMP Mode
        • OPAMP Non Inverting Input
        • OPAMP Inverting Input
        • OPAMP Pga Gain
        • OPAMP PowerMode
        • OPAMP PowerSupplyRange
        • OPAMP User Trimming
        • OPAMP Factory Trimming
      • OPAMP Private Constants
      • OPAMP Exported Macros
      • OPAMP Private Macros
    • PCD
      • PCD Private Macros
      • PCD Private Functions
      • PCD Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • PCD Exported Types
      • PCD Exported Constants
        • PCD Speed
        • PCD PHY Module
        • Turnaround Timeout Value
      • PCD Exported Macros
      • PCD Private Constants
        • USB EXTI line interrupt
    • PCDEx
      • PCDEx Exported Functions
        • Peripheral Control functions
    • PWR
      • PWR Private Defines
        • PWR PVD Mode Mask
      • PWR Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • PWR Exported Types
      • PWR Exported Constants
        • Programmable Voltage Detection levels
        • PWR PVD interrupt and event mode
        • PWR regulator mode
        • PWR SLEEP mode entry
        • PWR STOP mode entry
        • PWR PVD external interrupt line
        • PWR PVD event line
      • PWR Exported Macros
      • PWR Private Macros
    • PWREx
      • PWR Extended Private Defines
        • PWR PVM Mode Mask
        • PWR Extended Flag Setting Time Out Value
      • PWR Extended Exported Functions
        • Extended Peripheral Control functions
      • PWR Extended Exported Types
      • PWR Extended Exported Constants
        • Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
        • PWR wake-up pins
        • Peripheral Voltage Monitoring type
        • PWR PVM interrupt and event mode
        • PWR Regulator voltage scale
        • PWR battery charging resistor selection
        • PWR battery charging
        • GPIO bit number for I/O setting in standby/shutdown mode
        • GPIO port
        • PWR PVM external interrupts lines
        • PWR PVM event lines
        • PWR Status Flags
      • PWR Extended Exported Macros
      • PWR Extended Private Macros
    • QSPI
      • QSPI Private Constants
      • QSPI Private Macros
      • QSPI Exported Functions
        • Initialization/de-initialization functions
        • Input and Output operation functions
        • Peripheral Control and State functions
      • QSPI Exported Types
      • QSPI Exported Constants
        • QSPI Error Code
        • QSPI Sample Shifting
        • QSPI ChipSelect High Time
        • QSPI Clock Mode
        • QSPI Address Size
        • QSPI Alternate Bytes Size
        • QSPI Instruction Mode
        • QSPI Address Mode
        • QSPI Alternate Bytes Mode
        • QSPI Data Mode
        • QSPI DDR Mode
        • QSPI DDR Data Output Delay
        • QSPI Send Instruction Mode
        • QSPI Match Mode
        • QSPI Automatic Stop
        • QSPI Timeout Activation
        • QSPI Flags
        • QSPI Interrupts
        • QSPI Timeout definition
      • QSPI Exported Macros
    • RCC
      • RCC Private Constants
      • RCC Private Macros
      • RCC Private Variables
      • RCC Private Functions
      • RCC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • RCC Exported Types
      • RCC Exported Constants
        • Timeout Values
        • Oscillator Type
        • HSE Config
        • LSE Config
        • HSI Config
        • LSI Config
        • MSI Config
        • HSI48 Config
        • PLL Config
        • PLLP Clock Divider
        • PLLQ Clock Divider
        • PLLR Clock Divider
        • PLL Clock Source
        • PLL Clock Output
        • PLLSAI1 Clock Output
        • PLLSAI2 Clock Output
        • MSI Clock Range
        • System Clock Type
        • System Clock Source
        • System Clock Source Status
        • AHB Clock Source
        • APB1 APB2 Clock Source
        • RTC Clock Source
        • MCO Index
        • MCO1 Clock Source
        • MCO1 Clock Prescaler
        • Interrupts
        • Flags
        • LSE Drive Config
        • Wake-Up from STOP Clock
      • RCC Exported Macros
        • AHB1 Peripheral Clock Enable Disable
        • AHB2 Peripheral Clock Enable Disable
        • AHB3 Peripheral Clock Enable Disable
        • APB1 Peripheral Clock Enable Disable
        • APB2 Peripheral Clock Enable Disable
        • AHB1 Peripheral Clock Enabled or Disabled Status
        • AHB2 Peripheral Clock Enabled or Disabled Status
        • AHB3 Peripheral Clock Enabled or Disabled Status
        • APB1 Peripheral Clock Enabled or Disabled Status
        • APB2 Peripheral Clock Enabled or Disabled Status
        • AHB1 Peripheral Force Release Reset
        • AHB2 Peripheral Force Release Reset
        • AHB3 Peripheral Force Release Reset
        • APB1 Peripheral Force Release Reset
        • APB2 Peripheral Force Release Reset
        • AHB1 Peripheral Clock Sleep Enable Disable
        • AHB2 Peripheral Clock Sleep Enable Disable
        • AHB3 Peripheral Clock Sleep Enable Disable
        • APB1 Peripheral Clock Sleep Enable Disable
        • APB2 Peripheral Clock Sleep Enable Disable
        • AHB1 Peripheral Clock Sleep Enabled or Disabled Status
        • AHB2 Peripheral Clock Sleep Enabled or Disabled Status
        • AHB3 Peripheral Clock Sleep Enabled or Disabled Status
        • APB1 Peripheral Clock Sleep Enabled or Disabled Status
        • APB2 Peripheral Clock Sleep Enabled or Disabled Status
        • RCC Backup Domain Reset
        • RCC RTC Clock Configuration
        • Flags Interrupts Management
    • RCCEx
      • RCCEx Private Constants
      • RCCEx Private Functions
      • RCCEx Exported Functions
        • Extended Peripheral Control functions
        • Extended Clock management functions
      • RCCEx Exported Types
      • RCCEx Exported Constants
        • Low Speed Clock Source
        • Periph Clock Selection
        • USART1 Clock Source
        • USART2 Clock Source
        • USART3 Clock Source
        • UART4 Clock Source
        • UART5 Clock Source
        • LPUART1 Clock Source
        • I2C1 Clock Source
        • I2C2 Clock Source
        • I2C3 Clock Source
        • SAI1 Clock Source
        • SAI2 Clock Source
        • LPTIM1 Clock Source
        • LPTIM2 Clock Source
        • SDMMC1 Clock Source
        • RNG Clock Source
        • USB Clock Source
        • ADC Clock Source
        • SWPMI1 Clock Source
        • DFSDM1 Clock Source
        • RCC LSE CSS external interrupt line
      • RCCEx Exported Macros
        • Flags Interrupts Management
      • RCCEx_Private_Macros
    • RNG
      • RNG_Private_Constants
      • RNG Exported Types
      • RNG Exported Constants
        • RNG Interrupts Definition
        • RNG Flags Definition
      • RNG Exported Macros
      • RNG Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
    • RTC
      • RTC Exported Functions
        • Initialization and de-initialization functions
        • RTC Time and Date functions
        • RTC Alarm functions
        • Peripheral Control functions
        • Peripheral State functions
      • RTC Private functions
      • RTC Exported Types
      • RTC Exported Constants
        • RTC Hour Formats
        • RTC Output Polarity Definitions
        • RTC Output Type ALARM OUT
        • RTC Output ALARM OUT Remap
        • RTC AM PM Definitions
        • RTC DayLight Saving Definitions
        • RTC Store Operation Definitions
        • RTC Input Parameter Format Definitions
        • RTC Month Date Definitions
        • RTC WeekDay Definitions
        • RTC Alarm Date WeekDay Definitions
        • RTC Alarm Mask Definitions
        • RTC Alarms Definitions
        • RTC Alarm Sub Seconds Masks Definitions
        • RTC Interrupts Definitions
        • RTC Flags Definitions
      • RTC Exported Macros
      • RTC Private Constants
      • RTC Private Macros
        • RTC Private macros to check input parameters
    • RTCEx
      • RTCEx Exported Functions
        • RTC TimeStamp and Tamper functions
        • RTC Wake-up functions
        • Extended Peripheral Control functions
        • Extended features functions
      • RTCEx Exported Types
      • RTCEx Exported Constants
        • RTC Output Selection Definitions
        • RTC Backup Registers Definitions
        • RTC TimeStamp Edges Definitions
        • RTC TimeStamp Pins Selection
        • RTC Tamper Pins Definitions
        • RTC Tamper Interrupts Definitions
        • RTC Tamper Triggers Definitions
        • RTC Tamper EraseBackUp Definitions
        • RTC Tamper Mask Flag Definitions
        • RTC Tamper Filter Definitions
        • RTC Tamper Sampling Frequencies Definitions
        • RTC Tamper Pin Precharge Duration Definitions
        • RTC Tamper TimeStamp On Tamper Detection Definitions
        • RTC Tamper Pull Up Definitions
        • RTC Wakeup Timer Definitions
        • RTC Smooth Calib Period Definitions
        • RTC Smooth Calib Plus Pulses Definitions
        • RTC Calib Output Selection Definitions
        • RTC Add 1 Second Parameter Definitions
      • RTCEx Exported Macros
      • RTCEx Private Constants
      • RTCEx Private Macros
        • Private macros to check input parameters
    • SAI
      • SAI Private Typedefs
      • SAI Private Constants
      • SAI Private Functions
      • SAI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • SAI Exported Types
        • SAI Init Structure definition
        • SAI Frame Structure definition
        • SAI Slot Structure definition
        • SAI Handle Structure definition
      • SAI Exported Constants
        • SAI Error Code
        • SAI External synchronisation
        • SAI Supported protocol
        • SAI protocol data size
        • SAI Audio Frequency
        • SAI Block Mode
        • SAI Block Protocol
        • SAI Block Data Size
        • SAI Block MSB LSB transmission
        • SAI Block Clock Strobing
        • SAI Block Synchronization
        • SAI Block Output Drive
        • SAI Block NoDivider
        • SAI Block FS Definition
        • SAI Block FS Polarity
        • SAI Block FS Offset
        • SAI Block Slot Size
        • SAI Block Slot Active
        • SAI Mono Stereo Mode
        • SAI TRIState Management
        • SAI Block Fifo Threshold
        • SAI Block Companding Mode
        • SAI Block Mute Value
        • SAI Block Interrupts Definition
        • SAI Block Flags Definition
        • SAI Block Fifo Status Level
      • SAI Exported Macros
      • SAI_Private_Macros
    • SMARTCARD
      • SMARTCARD Private Constants
      • SMARTCARD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SMARTCARD Private Functions
      • SMARTCARD Exported Types
      • SMARTCARD Exported Constants
        • SMARTCARD Word Length
        • SMARTCARD Number of Stop Bits
        • SMARTCARD Parity
        • SMARTCARD Transfer Mode
        • SMARTCARD Clock Polarity
        • SMARTCARD Clock Phase
        • SMARTCARD Last Bit
        • SMARTCARD One Bit Sampling Method
        • SMARTCARD NACK Enable
        • SMARTCARD Timeout Enable
        • SMARTCARD advanced feature TX pin active level inversion
        • SMARTCARD advanced feature RX pin active level inversion
        • SMARTCARD advanced feature Binary Data inversion
        • SMARTCARD advanced feature RX TX pins swap
        • SMARTCARD advanced feature Overrun Disable
        • SMARTCARD advanced feature DMA Disable on Rx Error
        • SMARTCARD advanced feature MSB first
        • SMARTCARD Request Parameters
        • SMARTCARD auto retry counter LSB position in CR3 register
        • SMARTCARD guard time value LSB position in GTPR register
        • SMARTCARD block length LSB position in RTOR register
        • SMARTCARD interruptions flags mask
      • SMARTCARD Exported Macros
      • SMARTCARD Private Macros
    • SMARTCARDEx
      • SMARTCARD Extended Exported Functions
        • Extended Peripheral Control functions
      • SMARTCARD Extended Private Macros
      • SMARTCARD Extended Exported Constants
        • SMARTCARD Transmission Completion Indication
        • SMARTCARD advanced feature initialization type
        • SMARTCARD Flags
        • SMARTCARD Interrupts Definition
        • SMARTCARD Interruption Clear Flags
    • SMBUS
      • SMBUS Private Constants
      • SMBUS Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
          • Blocking mode Polling
          • Non-Blocking mode Interrupt
          • IRQ Handler and Callbacks
          • Peripheral State and Errors functions
        • IRQ Handler and Callbacks
        • Peripheral State and Errors functions
      • SMBUS Exported Types
        • SMBUS Configuration Structure definition
        • HAL state definition
        • SMBUS Error Code definition
        • SMBUS handle Structure definition
      • SMBUS Exported Constants
        • SMBUS Analog Filter
        • SMBUS addressing mode
        • SMBUS dual addressing mode
        • SMBUS own address2 masks
        • SMBUS general call addressing mode
        • SMBUS nostretch mode
        • SMBUS packet error check mode
        • SMBUS peripheral mode
        • SMBUS ReloadEndMode definition
        • SMBUS StartStopMode definition
        • SMBUS XferOptions definition
        • SMBUS Interrupt configuration definition
        • SMBUS Flag definition
      • SMBUS Exported Macros
      • SMBUS Private Macros
      • SMBUS Private Functions
    • SPI
      • SPI Private Constants
      • SPI Private Functions
      • SPI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPI Exported Types
      • SPI Exported Constants
        • SPI Error Code
        • SPI Mode
        • SPI Direction Mode
        • SPI Data Size
        • SPI Clock Polarity
        • SPI Clock Phase
        • SPI Slave Select management
        • SPI NSS Pulse Mode
        • SPI BaudRate Prescaler
        • SPI MSB LSB transmission
        • SPI TI mode
        • SPI CRC Calculation
        • SPI CRC Length
        • SPI FIFO Reception Threshold
        • SPI Interrupt configuration definition
        • SPI Flag definition
        • SPI Transmission FIFO Status Level
        • SPI Reception FIFO Status Level
      • SPI Exported Macros
      • SPI Private Macros
    • SPIEx
      • SPIEx Private Constants
      • SPIEx Exported Functions
        • IO operation functions
    • SRAM
      • SRAM Exported Functions
        • Initialization and de-initialization functions
        • Input Output and memory control functions
        • Control functions
        • Peripheral State functions
      • SRAM Exported Types
      • SRAM Exported Macros
    • SWPMI
      • SWPMI Exported Functions
        • Initialization/de-initialization methods
        • IO operation methods
        • SWPMI IRQ handler and callbacks
        • Peripheral Control methods
      • SWPMI Private Functions
      • SWPMI Exported Types
      • SWPMI Exported Constants
        • SWPMI Error Code Bitmap
        • SWPMI Voltage Class
        • SWPMI Tx Buffering Mode
        • SWPMI Rx Buffering Mode
        • SWPMI Status Flags
        • SWPMI Interrupts Definition
      • SWPMI Exported Macros
      • SWPMI Private Types
      • SWPMI Private Variables
      • SWPMI Private Constants
      • SWPMI Private Macros
    • TIM
      • TIM Exported Functions
        • Time Base functions
        • Time Output Compare functions
        • Time PWM functions
        • Time Input Capture functions
        • Time One Pulse functions
        • Time Encoder functions
        • TIM IRQ handler management
        • Peripheral Control functions
        • TIM Callbacks functions
        • Peripheral State functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Clear Input Source
        • TIM DMA Base Address
        • TIM Extended Event Source
        • TIM Input Channel polarity
        • TIM ETR Polarity
        • TIM ETR Prescaler
        • TIM Counter Mode
        • TIM Clock Division
        • TIM Output Compare State
        • TIM Output Fast State
        • TIM Complementary Output Compare State
        • TIM Output Compare Polarity
        • TIM Complementary Output Compare Polarity
        • TIM Output Compare Idle State
        • TIM Complementary Output Compare Idle State
        • TIM Input Capture Polarity
        • TIM Input Capture Selection
        • TIM Input Capture Prescaler
        • TIM One Pulse Mode
        • TIM Encoder Mode
        • TIM interrupt Definition
        • TIM Commutation Source
        • TIM DMA Sources
        • TIM Flag Definition
        • TIM Channel
        • TIM Clock Source
        • TIM Clock Polarity
        • TIM Clock Prescaler
        • TIM Clear Input Polarity
        • TIM Clear Input Prescaler
        • TIM OSSR OffState Selection for Run mode state
        • TIM OSSI OffState Selection for Idle mode state
        • TIM Lock level
        • TIM Break Input Enable
        • TIM Break Input Polarity
        • TIM Break input 2 Enable
        • TIM Break Input 2 Polarity
        • TIM Automatic Output Enable
        • Group Channel 5 and Channel 1, 2 or 3
        • TIM Master Mode Selection
        • TIM Master Mode Selection 2 (TRGO2)
        • TIM Master/Slave Mode
        • TIM Slave mode
        • TIM Output Compare and PWM Modes
        • TIM Trigger Selection
        • TIM Trigger Polarity
        • TIM Trigger Prescaler
        • TIM TI1 Input Selection
        • TIM DMA Burst Length
        • TIM DMA Handle Index
        • TIM Capture/Compare Channel State
        • TIM Break System
      • TIM Exported Macros
      • TIM Private Constants
      • TIM Private Macros
      • TIM Private Functions
    • TIMEx
      • TIM Extended Exported Functions
        • Extended Timer Hall Sensor functions
        • Extended Timer Complementary Output Compare functions
        • Extended Timer Complementary PWM functions
        • Extended Timer Complementary One Pulse functions
        • Extended Peripheral Control functions
        • Extended Callbacks functions
        • Extended Peripheral State functions
      • TIM Extended Exported Types
      • TIM Extended Exported Constants
        • TIM Extended Remapping
        • TIM Extended Break input
        • TIM Extended Break input source
        • TIM Extended Break input source enabling
        • TIM Extended Break input polarity
      • TIM Extended Exported Macros
      • TIM Extended Private Macros
      • TIMEx Private Functions
    • TSC
      • Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
        • IRQ Handler and Callbacks
      • Private Functions
      • TSC Exported Types
      • TSC Exported Constants
        • CTPulse High Length
        • CTPulse Low Length
        • Spread Spectrum Prescaler
        • Pulse Generator Prescaler
        • Max Count Value
        • IO Default Mode
        • Synchro Pin Polarity
        • Acquisition Mode
        • IO Mode
        • Interrupts definition
        • Flags definition
        • Group definition
      • TSC Exported Macros
      • TSC Private Macros
    • UART
      • UART Private Constants
      • UART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • UART Private Functions
      • UART Exported Types
      • UART Exported Constants
        • UART Number of Stop Bits
        • UART Parity
        • UART Hardware Flow Control
        • UART Transfer Mode
        • UART State
        • UART Over Sampling
        • UART One Bit Sampling Method
        • UART Advanced Feature AutoBaud Rate Mode
        • UART Receiver TimeOut
        • UART Local Interconnection Network mode
        • UART LIN Break Detection
        • UART DMA Tx
        • UART DMA Rx
        • UART Half Duplex Selection
        • UART WakeUp Methods
        • UART Request Parameters
        • UART Advanced Feature Initialization Type
        • UART Advanced Feature TX Pin Active Level Inversion
        • UART Advanced Feature RX Pin Active Level Inversion
        • UART Advanced Feature Binary Data Inversion
        • UART Advanced Feature RX TX Pins Swap
        • UART Advanced Feature Overrun Disable
        • UART Advanced Feature Auto BaudRate Enable
        • UART Advanced Feature DMA Disable On Rx Error
        • UART Advanced Feature MSB First
        • UART Advanced Feature Stop Mode Enable
        • UART Advanced Feature Mute Mode Enable
        • UART Address-matching LSB Position In CR2 Register
        • UART WakeUp From Stop Selection
        • UART DriverEnable Polarity
        • UART Driver Enable Assertion Time LSB Position In CR1 Register
        • UART Driver Enable DeAssertion Time LSB Position In CR1 Register
        • UART Interruptions Flag Mask
        • UART polling-based communications time-out value
        • UART Status Flags
        • UART Interrupts Definition
        • UART Interruption Clear Flags
      • UART Exported Macros
      • UART Private Macros
    • UARTEx
      • UARTEx Private Functions
      • UARTEx Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • UARTEx Exported Types
      • UARTEx Exported Constants
        • UART Word Length
        • UART Extended WakeUp Address Length
      • UARTEx Private Macros
    • USART
      • USART Private Constants
      • USART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • USART Private Functions
      • USART Exported Types
      • USART Exported Constants
        • USART Number of Stop Bits
        • USART Parity
        • USART Mode
        • USART Over Sampling
        • USART Clock
        • USART Clock Polarity
        • USART Clock Phase
        • USART Last Bit
        • USART Request Parameters
        • USART Flags
        • USART Interrupts Definition
        • USART Interruption Clear Flags
        • USART Interruption Flags Mask
      • USART Exported Macros
      • USART Private Macros
    • WWDG
      • WWDG Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
      • WWDG Exported Types
      • WWDG Exported Constants
        • WWDG Interrupt definition
        • WWDG Flag definition
        • WWDG Prescaler
        • WWDG Early Wakeup Interrupt Mode
      • WWDG Private Macros
      • WWDG Exported Macros
    • IRDAEx
      • IRDAEx Private Macros
    • OPAMPEx
      • OPAMPEx Exported Functions
        • Extended Input and Output operation functions
        • Peripheral Control functions
    • SD
      • SD_Private_Defines
      • SD_Private_Functions_Prototypes
      • SD_Exported_Functions
        • SD_Exported_Functions_Group1
        • SD_Exported_Functions_Group2
        • SD_Exported_Functions_Group3
        • SD_Exported_Functions_Group4
      • SD_Private_Functions
    • USARTEx
      • USARTEx Exported Constants
        • USARTEx Word Length
      • USARTEx Private Macros
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STM32L486xx HAL User Manual: OPAMP_rmtollPages.txt File Reference

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OPAMP_rmtollPages.txt File Reference
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STM32L486xx HAL User Manual: PWR_rmtollPages.txt File Reference

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PWR_rmtollPages.txt File Reference
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STM32L486xx HAL User Manual: RCC_rmtollPages.txt File Reference

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RCC_rmtollPages.txt File Reference
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STM32L486xx HAL User Manual: RNG_rmtollPages.txt File Reference

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RNG_rmtollPages.txt File Reference
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STM32L486xx HAL User Manual: RTC_rmtollPages.txt File Reference

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RTC_rmtollPages.txt File Reference
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STM32L486xx HAL User Manual: SPI_rmtollPages.txt File Reference

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SPI_rmtollPages.txt File Reference
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STM32L486xx HAL User Manual: stm32l4xx_hal.c Source File

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  • STM32L4xx_HAL_Driver
  • Src
stm32l4xx_hal.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   HAL module driver.
00008   *          This is the common part of the HAL initialization
00009   *
00010   @verbatim
00011   ==============================================================================
00012                      ##### How to use this driver #####
00013   ==============================================================================
00014     [..]
00015     The common HAL driver contains a set of generic and common APIs that can be
00016     used by the PPP peripheral drivers and the user to start using the HAL.
00017     [..]
00018     The HAL contains two APIs' categories:
00019          (+) Common HAL APIs
00020          (+) Services HAL APIs
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00027   *
00028   * Redistribution and use in source and binary forms, with or without modification,
00029   * are permitted provided that the following conditions are met:
00030   *   1. Redistributions of source code must retain the above copyright notice,
00031   *      this list of conditions and the following disclaimer.
00032   *   2. Redistributions in binary form must reproduce the above copyright notice,
00033   *      this list of conditions and the following disclaimer in the documentation
00034   *      and/or other materials provided with the distribution.
00035   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00036   *      may be used to endorse or promote products derived from this software
00037   *      without specific prior written permission.
00038   *
00039   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00040   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00041   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00042   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00043   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00044   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00045   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00046   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00047   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00048   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32l4xx_hal.h"
00055
00056 /** @addtogroup STM32L4xx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @defgroup HAL HAL
00061   * @brief HAL module driver
00062   * @{
00063   */
00064
00065 #ifdef HAL_MODULE_ENABLED
00066
00067 /* Private typedef -----------------------------------------------------------*/
00068 /* Private define ------------------------------------------------------------*/
00069 /**
00070  * @brief STM32L4xx HAL Driver version number V1.5.1
00071    */
00072 #define __STM32L4xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
00073 #define __STM32L4xx_HAL_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
00074 #define __STM32L4xx_HAL_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
00075 #define __STM32L4xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
00076 #define __STM32L4xx_HAL_VERSION         ((__STM32L4xx_HAL_VERSION_MAIN << 24)\
00077                                         |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\
00078                                         |(__STM32L4xx_HAL_VERSION_SUB2 << 8 )\
00079                                         |(__STM32L4xx_HAL_VERSION_RC))
00080
00081 #if defined(VREFBUF)
00082 #define VREFBUF_TIMEOUT_VALUE     (uint32_t)10   /* 10 ms (to be confirmed) */
00083 #endif /* VREFBUF */
00084
00085 /* ------------ SYSCFG registers bit address in the alias region ------------ */
00086 #define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
00087 /* ---  MEMRMP Register ---*/
00088 /* Alias word address of FB_MODE bit */
00089 #define MEMRMP_OFFSET             SYSCFG_OFFSET
00090 #define FB_MODE_BitNumber         ((uint8_t)0x8)
00091 #define FB_MODE_BB                (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
00092
00093 /* --- SCSR Register ---*/
00094 /* Alias word address of SRAM2ER bit */
00095 #define SCSR_OFFSET              (SYSCFG_OFFSET + 0x18)
00096 #define BRER_BitNumber           ((uint8_t)0x0)
00097 #define SCSR_SRAM2ER_BB          (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4))
00098
00099 /* Private macro -------------------------------------------------------------*/
00100 /* Private variables ---------------------------------------------------------*/
00101 __IO uint32_t uwTick;
00102
00103 /* Private function prototypes -----------------------------------------------*/
00104 /* Exported functions --------------------------------------------------------*/
00105
00106 /** @defgroup HAL_Exported_Functions HAL Exported Functions
00107   * @{
00108   */
00109
00110 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
00111  *  @brief    Initialization and de-initialization functions
00112  *
00113 @verbatim
00114  ===============================================================================
00115               ##### Initialization and de-initialization functions #####
00116  ===============================================================================
00117     [..]  This section provides functions allowing to:
00118       (+) Initialize the Flash interface the NVIC allocation and initial time base
00119           clock configuration.
00120       (+) De-initialize common part of the HAL.
00121       (+) Configure the time base source to have 1ms time base with a dedicated
00122           Tick interrupt priority.
00123         (++) SysTick timer is used by default as source of time base, but user
00124              can eventually implement his proper time base source (a general purpose
00125              timer for example or other time source), keeping in mind that Time base
00126              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
00127              handled in milliseconds basis.
00128         (++) Time base configuration function (HAL_InitTick ()) is called automatically
00129              at the beginning of the program after reset by HAL_Init() or at any time
00130              when clock is configured, by HAL_RCC_ClockConfig().
00131         (++) Source of time base is configured  to generate interrupts at regular
00132              time intervals. Care must be taken if HAL_Delay() is called from a
00133              peripheral ISR process, the Tick interrupt line must have higher priority
00134             (numerically lower) than the peripheral interrupt. Otherwise the caller
00135             ISR process will be blocked.
00136        (++) functions affecting time base configurations are declared as __weak
00137              to make  override possible  in case of other  implementations in user file.
00138 @endverbatim
00139   * @{
00140   */
00141
00142 /**
00143   * @brief  Configure the Flash prefetch, the Instruction and Data caches,
00144   *         the time base source, NVIC and any required global low level hardware
00145   *         by calling the HAL_MspInit() callback function to be optionally defined in user file
00146   *         stm32l4xx_hal_msp.c.
00147   *
00148   * @note   HAL_Init() function is called at the beginning of program after reset and before
00149   *         the clock configuration.
00150   *
00151   * @note   In the default implementation the System Timer (Systick) is used as source of time base.
00152   *         The Systick configuration is based on MSI clock, as MSI is the clock
00153   *         used after a system Reset and the NVIC configuration is set to Priority group 4.
00154   *         Once done, time base tick starts incrementing: the tick variable counter is incremented
00155   *         each 1ms in the SysTick_Handler() interrupt handler.
00156   *
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef HAL_Init(void)
00160 {
00161   /* Configure Flash prefetch, Instruction cache, Data cache */
00162   /* Default configuration at reset is:                      */
00163   /* - Prefetch disabled                                     */
00164   /* - Instruction cache enabled                             */
00165   /* - Data cache enabled                                    */
00166 #if (INSTRUCTION_CACHE_ENABLE == 0)
00167    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
00168 #endif /* INSTRUCTION_CACHE_ENABLE */
00169
00170 #if (DATA_CACHE_ENABLE == 0)
00171    __HAL_FLASH_DATA_CACHE_DISABLE();
00172 #endif /* DATA_CACHE_ENABLE */
00173
00174 #if (PREFETCH_ENABLE != 0)
00175   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
00176 #endif /* PREFETCH_ENABLE */
00177
00178   /* Set Interrupt Group Priority */
00179   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
00180
00181   /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
00182   HAL_InitTick(TICK_INT_PRIORITY);
00183
00184   /* Init the low level hardware */
00185   HAL_MspInit();
00186
00187   /* Return function status */
00188   return HAL_OK;
00189 }
00190
00191 /**
00192   * @brief De-initialize common part of the HAL and stop the source of time base.
00193   * @note This function is optional.
00194   * @retval HAL status
00195   */
00196 HAL_StatusTypeDef HAL_DeInit(void)
00197 {
00198   /* Reset of all peripherals */
00199   __HAL_RCC_APB1_FORCE_RESET();
00200   __HAL_RCC_APB1_RELEASE_RESET();
00201
00202   __HAL_RCC_APB2_FORCE_RESET();
00203   __HAL_RCC_APB2_RELEASE_RESET();
00204
00205   __HAL_RCC_AHB1_FORCE_RESET();
00206   __HAL_RCC_AHB1_RELEASE_RESET();
00207
00208   __HAL_RCC_AHB2_FORCE_RESET();
00209   __HAL_RCC_AHB2_RELEASE_RESET();
00210
00211   __HAL_RCC_AHB3_FORCE_RESET();
00212   __HAL_RCC_AHB3_RELEASE_RESET();
00213
00214   /* De-Init the low level hardware */
00215   HAL_MspDeInit();
00216
00217   /* Return function status */
00218   return HAL_OK;
00219 }
00220
00221 /**
00222   * @brief  Initialize the MSP.
00223   * @retval None
00224   */
00225 __weak void HAL_MspInit(void)
00226 {
00227   /* NOTE : This function should not be modified, when the callback is needed,
00228             the HAL_MspInit could be implemented in the user file
00229    */
00230 }
00231
00232 /**
00233   * @brief  DeInitialize the MSP.
00234   * @retval None
00235   */
00236 __weak void HAL_MspDeInit(void)
00237 {
00238   /* NOTE : This function should not be modified, when the callback is needed,
00239             the HAL_MspDeInit could be implemented in the user file
00240    */
00241 }
00242
00243 /**
00244   * @brief This function configures the source of the time base:
00245   *        The time source is configured to have 1ms time base with a dedicated
00246   *        Tick interrupt priority.
00247   * @note This function is called  automatically at the beginning of program after
00248   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
00249   * @note In the default implementation, SysTick timer is the source of time base.
00250   *       It is used to generate interrupts at regular time intervals.
00251   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
00252   *       The SysTick interrupt must have higher priority (numerically lower)
00253   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
00254   *       The function is declared as __weak  to be overwritten  in case of other
00255   *       implementation  in user file.
00256   * @param TickPriority: Tick interrupt priority.
00257   * @retval HAL status
00258   */
00259 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00260 {
00261   /*Configure the SysTick to have interrupt in 1ms time basis*/
00262   HAL_SYSTICK_Config(SystemCoreClock/1000);
00263
00264   /*Configure the SysTick IRQ priority */
00265   HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
00266
00267   /* Return function status */
00268   return HAL_OK;
00269 }
00270
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
00276  *  @brief    HAL Control functions
00277  *
00278 @verbatim
00279  ===============================================================================
00280                       ##### HAL Control functions #####
00281  ===============================================================================
00282     [..]  This section provides functions allowing to:
00283       (+) Provide a tick value in millisecond
00284       (+) Provide a blocking delay in millisecond
00285       (+) Suspend the time base source interrupt
00286       (+) Resume the time base source interrupt
00287       (+) Get the HAL API driver version
00288       (+) Get the device identifier
00289       (+) Get the device revision identifier
00290
00291 @endverbatim
00292   * @{
00293   */
00294
00295 /**
00296   * @brief This function is called to increment a global variable "uwTick"
00297   *        used as application time base.
00298   * @note In the default implementation, this variable is incremented each 1ms
00299   *       in SysTick ISR.
00300  * @note This function is declared as __weak to be overwritten in case of other
00301   *      implementations in user file.
00302   * @retval None
00303   */
00304 __weak void HAL_IncTick(void)
00305 {
00306   uwTick++;
00307 }
00308
00309 /**
00310   * @brief Provide a tick value in millisecond.
00311   * @note This function is declared as __weak to be overwritten in case of other
00312   *       implementations in user file.
00313   * @retval tick value
00314   */
00315 __weak uint32_t HAL_GetTick(void)
00316 {
00317   return uwTick;
00318 }
00319
00320 /**
00321   * @brief Provide accurate delay (in milliseconds) based on variable incremented.
00322   * @note In the default implementation , SysTick timer is the source of time base.
00323   *       It is used to generate interrupts at regular time intervals where uwTick
00324   *       is incremented.
00325   * @note This function is declared as __weak to be overwritten in case of other
00326   *       implementations in user file.
00327   * @param Delay: specifies the delay time length, in milliseconds.
00328   * @retval None
00329   */
00330 __weak void HAL_Delay(uint32_t Delay)
00331 {
00332   uint32_t tickstart = 0;
00333   tickstart = HAL_GetTick();
00334   while((HAL_GetTick() - tickstart) < Delay)
00335   {
00336   }
00337 }
00338
00339 /**
00340   * @brief Suspend Tick increment.
00341   * @note In the default implementation , SysTick timer is the source of time base. It is
00342   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
00343   *       is called, the SysTick interrupt will be disabled and so Tick increment
00344   *       is suspended.
00345   * @note This function is declared as __weak to be overwritten in case of other
00346   *       implementations in user file.
00347   * @retval None
00348   */
00349 __weak void HAL_SuspendTick(void)
00350 {
00351   /* Disable SysTick Interrupt */
00352   SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
00353 }
00354
00355 /**
00356   * @brief Resume Tick increment.
00357   * @note In the default implementation , SysTick timer is the source of time base. It is
00358   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
00359   *       is called, the SysTick interrupt will be enabled and so Tick increment
00360   *       is resumed.
00361   * @note This function is declared as __weak to be overwritten in case of other
00362   *       implementations in user file.
00363   * @retval None
00364   */
00365 __weak void HAL_ResumeTick(void)
00366 {
00367   /* Enable SysTick Interrupt */
00368   SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
00369 }
00370
00371 /**
00372   * @brief  Return the HAL revision.
00373   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
00374   */
00375 uint32_t HAL_GetHalVersion(void)
00376 {
00377  return __STM32L4xx_HAL_VERSION;
00378 }
00379
00380 /**
00381   * @brief  Return the device revision identifier.
00382   * @retval Device revision identifier
00383   */
00384 uint32_t HAL_GetREVID(void)
00385 {
00386    return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);
00387 }
00388
00389 /**
00390   * @brief  Return the device identifier.
00391   * @retval Device identifier
00392   */
00393 uint32_t HAL_GetDEVID(void)
00394 {
00395    return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
00396 }
00397
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
00403  *  @brief    HAL Debug functions
00404  *
00405 @verbatim
00406  ===============================================================================
00407                       ##### HAL Debug functions #####
00408  ===============================================================================
00409     [..]  This section provides functions allowing to:
00410       (+) Enable/Disable Debug module during SLEEP mode
00411       (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
00412       (+) Enable/Disable Debug module during STANDBY mode
00413
00414 @endverbatim
00415   * @{
00416   */
00417
00418 /**
00419   * @brief  Enable the Debug Module during SLEEP mode.
00420   * @retval None
00421   */
00422 void HAL_DBGMCU_EnableDBGSleepMode(void)
00423 {
00424   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00425 }
00426
00427 /**
00428   * @brief  Disable the Debug Module during SLEEP mode.
00429   * @retval None
00430   */
00431 void HAL_DBGMCU_DisableDBGSleepMode(void)
00432 {
00433   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00434 }
00435
00436 /**
00437   * @brief  Enable the Debug Module during STOP0/STOP1/STOP2 modes.
00438   * @retval None
00439   */
00440 void HAL_DBGMCU_EnableDBGStopMode(void)
00441 {
00442   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00443 }
00444
00445 /**
00446   * @brief  Disable the Debug Module during STOP0/STOP1/STOP2 modes.
00447   * @retval None
00448   */
00449 void HAL_DBGMCU_DisableDBGStopMode(void)
00450 {
00451   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00452 }
00453
00454 /**
00455   * @brief  Enable the Debug Module during STANDBY mode.
00456   * @retval None
00457   */
00458 void HAL_DBGMCU_EnableDBGStandbyMode(void)
00459 {
00460   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00461 }
00462
00463 /**
00464   * @brief  Disable the Debug Module during STANDBY mode.
00465   * @retval None
00466   */
00467 void HAL_DBGMCU_DisableDBGStandbyMode(void)
00468 {
00469   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00470 }
00471
00472 /**
00473   * @}
00474   */
00475
00476 /** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
00477  *  @brief    HAL SYSCFG configuration functions
00478  *
00479 @verbatim
00480  ===============================================================================
00481                       ##### HAL SYSCFG configuration functions #####
00482  ===============================================================================
00483     [..]  This section provides functions allowing to:
00484       (+) Start a hardware SRAM2 erase operation
00485       (+) Enable/Disable the Internal FLASH Bank Swapping
00486       (+) Configure the Voltage reference buffer
00487       (+) Enable/Disable the Voltage reference buffer
00488       (+) Enable/Disable the I/O analog switch voltage booster
00489
00490 @endverbatim
00491   * @{
00492   */
00493
00494 /**
00495   * @brief  Start a hardware SRAM2 erase operation.
00496   * @note   As long as SRAM2 is not erased the SRAM2ER bit will be set.
00497   *         This bit is automatically reset at the end of the SRAM2 erase operation.
00498   * @retval None
00499   */
00500 void HAL_SYSCFG_SRAM2Erase(void)
00501 {
00502   /* unlock the write protection of the SRAM2ER bit */
00503   SYSCFG->SKR = 0xCA;
00504   SYSCFG->SKR = 0x53;
00505   /* Starts a hardware SRAM2 erase operation*/
00506   *(__IO uint32_t *) SCSR_SRAM2ER_BB = (uint8_t)0x00000001;
00507 }
00508
00509 /**
00510   * @brief  Enable the Internal FLASH Bank Swapping.
00511   *
00512   * @note   This function can be used only for STM32L4xx devices.
00513   *
00514   * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
00515   *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
00516   *
00517   * @retval None
00518   */
00519 void HAL_SYSCFG_EnableMemorySwappingBank(void)
00520 {
00521   *(__IO uint32_t *)FB_MODE_BB = (uint32_t)ENABLE;
00522 }
00523
00524 /**
00525   * @brief  Disable the Internal FLASH Bank Swapping.
00526   *
00527   * @note   This function can be used only for STM32L4xx devices.
00528   *
00529   * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
00530   *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
00531   *
00532   * @retval None
00533   */
00534 void HAL_SYSCFG_DisableMemorySwappingBank(void)
00535 {
00536
00537   *(__IO uint32_t *)FB_MODE_BB = (uint32_t)DISABLE;
00538 }
00539
00540 #if defined(VREFBUF)
00541 /**
00542   * @brief Configure the internal voltage reference buffer voltage scale.
00543   * @param  VoltageScaling: specifies the output voltage to achieve
00544   *          This parameter can be one of the following values:
00545   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
00546   *                                                This requires VDDA equal to or higher than 2.4 V.
00547   *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 2.5 V.
00548   *                                                This requires VDDA equal to or higher than 2.8 V.
00549   * @retval None
00550   */
00551 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
00552 {
00553   /* Check the parameters */
00554   assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
00555
00556   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
00557 }
00558
00559 /**
00560   * @brief Configure the internal voltage reference buffer high impedance mode.
00561   * @param  Mode: specifies the high impedance mode
00562   *          This parameter can be one of the following values:
00563   *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
00564   *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
00565   * @retval None
00566   */
00567 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
00568 {
00569   /* Check the parameters */
00570   assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
00571
00572   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
00573 }
00574
00575 /**
00576   * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
00577   * @retval None
00578   */
00579 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
00580 {
00581   /* Check the parameters */
00582   assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
00583
00584   MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
00585 }
00586
00587 /**
00588   * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
00589   * @retval HAL_OK/HAL_TIMEOUT
00590   */
00591 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
00592 {
00593   uint32_t  tickstart = 0;
00594
00595   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
00596
00597   /* Get Start Tick*/
00598   tickstart = HAL_GetTick();
00599
00600   /* Wait for VRR bit  */
00601   while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET)
00602   {
00603     if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
00604     {
00605       return HAL_TIMEOUT;
00606     }
00607   }
00608
00609   return HAL_OK;
00610 }
00611
00612 /**
00613   * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
00614   *
00615   * @retval None
00616   */
00617 void HAL_SYSCFG_DisableVREFBUF(void)
00618 {
00619   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
00620 }
00621 #endif /* VREFBUF */
00622
00623 /**
00624   * @brief  Enable the I/O analog switch voltage booster
00625   *
00626   * @retval None
00627   */
00628 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
00629 {
00630   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00631 }
00632
00633 /**
00634   * @brief  Disable the I/O analog switch voltage booster
00635   *
00636   * @retval None
00637   */
00638 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
00639 {
00640   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00641 }
00642
00643 /**
00644   * @}
00645   */
00646
00647 /**
00648   * @}
00649   */
00650
00651 #endif /* HAL_MODULE_ENABLED */
00652 /**
00653   * @}
00654   */
00655
00656 /**
00657   * @}
00658   */
00659
00660 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal.h Source File

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stm32l4xx_hal.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   This file contains all the functions prototypes for the HAL
00008   *          module driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */
00038
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef __STM32L4xx_HAL_H
00041 #define __STM32L4xx_HAL_H
00042
00043 #ifdef __cplusplus
00044  extern "C" {
00045 #endif
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32l4xx_hal_conf.h"
00049
00050 /** @addtogroup STM32L4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup HAL
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup SYSCFG_BootMode Boot Mode
00065   * @{
00066   */
00067 #define SYSCFG_BOOT_MAINFLASH          ((uint32_t)0x00000000)
00068 #define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0
00069 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00070 #define SYSCFG_BOOT_FMC                SYSCFG_MEMRMP_MEM_MODE_1
00071 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00072 #define SYSCFG_BOOT_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
00073 #define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
00080   * @{
00081   */
00082 #define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */
00083 #define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */
00084 #define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */
00085 #define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */
00086 #define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */
00087 #define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection
00094   * @{
00095   */
00096 #define SYSCFG_SRAM2WRP_PAGE0          SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
00097 #define SYSCFG_SRAM2WRP_PAGE1          SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
00098 #define SYSCFG_SRAM2WRP_PAGE2          SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
00099 #define SYSCFG_SRAM2WRP_PAGE3          SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
00100 #define SYSCFG_SRAM2WRP_PAGE4          SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
00101 #define SYSCFG_SRAM2WRP_PAGE5          SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
00102 #define SYSCFG_SRAM2WRP_PAGE6          SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
00103 #define SYSCFG_SRAM2WRP_PAGE7          SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
00104 #define SYSCFG_SRAM2WRP_PAGE8          SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
00105 #define SYSCFG_SRAM2WRP_PAGE9          SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
00106 #define SYSCFG_SRAM2WRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
00107 #define SYSCFG_SRAM2WRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
00108 #define SYSCFG_SRAM2WRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
00109 #define SYSCFG_SRAM2WRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
00110 #define SYSCFG_SRAM2WRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
00111 #define SYSCFG_SRAM2WRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
00112 #define SYSCFG_SRAM2WRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
00113 #define SYSCFG_SRAM2WRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
00114 #define SYSCFG_SRAM2WRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
00115 #define SYSCFG_SRAM2WRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
00116 #define SYSCFG_SRAM2WRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
00117 #define SYSCFG_SRAM2WRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
00118 #define SYSCFG_SRAM2WRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
00119 #define SYSCFG_SRAM2WRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
00120 #define SYSCFG_SRAM2WRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
00121 #define SYSCFG_SRAM2WRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
00122 #define SYSCFG_SRAM2WRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
00123 #define SYSCFG_SRAM2WRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
00124 #define SYSCFG_SRAM2WRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
00125 #define SYSCFG_SRAM2WRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
00126 #define SYSCFG_SRAM2WRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
00127 #define SYSCFG_SRAM2WRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
00128
00129 /**
00130   * @}
00131   */
00132
00133 #if defined(VREFBUF)
00134 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
00135   * @{
00136   */
00137 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0  ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
00138 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
00145   * @{
00146   */
00147 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
00148 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
00149
00150 /**
00151   * @}
00152   */
00153 #endif /* VREFBUF */
00154
00155 /** @defgroup SYSCFG_flags_definition Flags
00156   * @{
00157   */
00158
00159 #define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF       /*!< SRAM2 parity error */
00160 #define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY   /*!< SRAM2 busy by erase operation */
00161
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
00167   * @{
00168   */
00169
00170 /** @brief  Fast-mode Plus driving capability on a specific GPIO
00171   */
00172 #define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
00173 #define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
00174 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
00175 #define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
00176 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
00177 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
00178 #define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
00179 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
00180
00181 /**
00182  * @}
00183  */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /* Exported macros -----------------------------------------------------------*/
00190
00191 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
00192   * @{
00193   */
00194
00195 /** @brief  Freeze/Unfreeze Peripherals in Debug mode
00196   */
00197 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
00198 #define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
00199 #define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
00200 #endif
00201
00202 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
00203 #define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
00204 #define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
00205 #endif
00206
00207 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
00208 #define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
00209 #define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
00210 #endif
00211
00212 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
00213 #define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
00214 #define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
00215 #endif
00216
00217 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
00218 #define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
00219 #define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
00220 #endif
00221
00222 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
00223 #define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
00224 #define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
00225 #endif
00226
00227 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
00228 #define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
00229 #define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
00230 #endif
00231
00232 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
00233 #define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
00234 #define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
00235 #endif
00236
00237 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
00238 #define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
00239 #define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
00240 #endif
00241
00242 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
00243 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
00244 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
00245 #endif
00246
00247 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
00248 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
00249 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
00250 #endif
00251
00252 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
00253 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
00254 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
00255 #endif
00256
00257 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
00258 #define __HAL_DBGMCU_FREEZE_CAN1()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
00259 #define __HAL_DBGMCU_UNFREEZE_CAN1()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
00260 #endif
00261
00262 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
00263 #define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
00264 #define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
00265 #endif
00266
00267 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
00268 #define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
00269 #define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
00270 #endif
00271
00272 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
00273 #define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
00274 #define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
00275 #endif
00276
00277 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
00278 #define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
00279 #define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
00280 #endif
00281
00282 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
00283 #define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
00284 #define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
00285 #endif
00286
00287 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
00288 #define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
00289 #define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
00290 #endif
00291
00292 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
00293 #define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
00294 #define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
00295 #endif
00296
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
00302   * @{
00303   */
00304
00305 /** @brief  Main Flash memory mapped at 0x00000000.
00306   */
00307 #define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
00308
00309 /** @brief  System Flash memory mapped at 0x00000000.
00310   */
00311 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
00312
00313 /** @brief  Embedded SRAM mapped at 0x00000000.
00314   */
00315 #define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
00316
00317 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00318 /** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
00319   */
00320 #define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
00321 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00322
00323 /** @brief  QUADSPI mapped at 0x00000000.
00324   */
00325 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
00326
00327 /**
00328   * @brief  Return the boot mode as configured by user.
00329   * @retval The boot mode as configured by user. The returned value can be one
00330   *         of the following values:
00331   *           @arg @ref SYSCFG_BOOT_MAINFLASH
00332   *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
00333   @if STM32L486xx
00334   *           @arg @ref SYSCFG_BOOT_FMC
00335   @endif
00336   *           @arg @ref SYSCFG_BOOT_SRAM
00337   *           @arg @ref SYSCFG_BOOT_QUADSPI
00338   */
00339 #define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
00340
00341 /** @brief  SRAM2 page write protection enable macro
00342   * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP
00343   * @note   write protection can only be disabled by a system reset
00344   */
00345 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
00346                                                          SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
00347                                                         }while(0)
00348
00349 /** @brief  SRAM2 page write protection unlock prior to erase
00350   * @note   Writing a wrong key reactivates the write protection
00351   */
00352 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()      do {SYSCFG->SKR = 0xCA;\
00353                                                  SYSCFG->SKR = 0x53;\
00354                                                 }while(0)
00355
00356 /** @brief  SRAM2 erase
00357   * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
00358   */
00359 #define __HAL_SYSCFG_SRAM2_ERASE()           SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
00360
00361 /** @brief  Floating Point Unit interrupt enable/disable macros
00362   * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
00363   */
00364 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
00365                                                                 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
00366                                                             }while(0)
00367
00368 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
00369                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
00370                                                             }while(0)
00371
00372 /** @brief  SYSCFG Break ECC lock.
00373   *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
00374   * @note   The selected configuration is locked and can be unlocked only by system reset.
00375   */
00376 #define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
00377
00378 /** @brief  SYSCFG Break Cortex-M4 Lockup lock.
00379   *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
00380   * @note   The selected configuration is locked and can be unlocked only by system reset.
00381   */
00382 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
00383
00384 /** @brief  SYSCFG Break PVD lock.
00385   *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
00386   * @note   The selected configuration is locked and can be unlocked only by system reset.
00387   */
00388 #define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
00389
00390 /** @brief  SYSCFG Break SRAM2 parity lock.
00391   *         Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
00392   * @note   The selected configuration is locked and can be unlocked by system reset.
00393   */
00394 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
00395
00396 /** @brief  Check SYSCFG flag is set or not.
00397   * @param  __FLAG__: specifies the flag to check.
00398   *         This parameter can be one of the following values:
00399   *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag
00400   *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
00401   * @retval The new state of __FLAG__ (TRUE or FALSE).
00402   */
00403 #define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
00404
00405 /** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
00406   */
00407 #define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
00408
00409 /** @brief  Fast-mode Plus driving capability enable/disable macros
00410   * @param __FASTMODEPLUS__: This parameter can be a value of :
00411   *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
00412   *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
00413   *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
00414   *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
00415   */
00416 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00417                                                                 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
00418                                                                }while(0)
00419
00420 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00421                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
00422                                                                }while(0)
00423
00424 /**
00425   * @}
00426   */
00427
00428 /* Private macros ------------------------------------------------------------*/
00429 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
00430   * @{
00431   */
00432
00433 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
00434                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
00435                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
00436                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
00437                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
00438                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
00439
00440 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
00441                                             ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
00442                                             ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \
00443                                             ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
00444
00445 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)   (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
00446
00447 #if defined(VREFBUF)
00448 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
00449                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
00450
00451 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
00452                                                       ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
00453
00454 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
00455 #endif /* VREFBUF */
00456
00457 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
00458 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00459                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
00460                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
00461                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
00462 #elif defined(SYSCFG_FASTMODEPLUS_PB8)
00463 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00464                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
00465                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
00466 #elif defined(SYSCFG_FASTMODEPLUS_PB9)
00467 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00468                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
00469                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
00470 #else
00471 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00472                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
00473 #endif
00474 /**
00475   * @}
00476   */
00477
00478 /* Exported functions --------------------------------------------------------*/
00479
00480 /** @addtogroup HAL_Exported_Functions
00481   * @{
00482   */
00483
00484 /** @addtogroup HAL_Exported_Functions_Group1
00485   * @{
00486   */
00487
00488 /* Initialization and de-initialization functions  ******************************/
00489 HAL_StatusTypeDef HAL_Init(void);
00490 HAL_StatusTypeDef HAL_DeInit(void);
00491 void HAL_MspInit(void);
00492 void HAL_MspDeInit(void);
00493 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
00494
00495 /**
00496   * @}
00497   */
00498
00499 /** @addtogroup HAL_Exported_Functions_Group2
00500   * @{
00501   */
00502
00503 /* Peripheral Control functions  ************************************************/
00504 void HAL_IncTick(void);
00505 void HAL_Delay(uint32_t Delay);
00506 uint32_t HAL_GetTick(void);
00507 void HAL_SuspendTick(void);
00508 void HAL_ResumeTick(void);
00509 uint32_t HAL_GetHalVersion(void);
00510 uint32_t HAL_GetREVID(void);
00511 uint32_t HAL_GetDEVID(void);
00512
00513 /**
00514   * @}
00515   */
00516
00517 /** @addtogroup HAL_Exported_Functions_Group3
00518   * @{
00519   */
00520
00521 /* DBGMCU Peripheral Control functions  *****************************************/
00522 void HAL_DBGMCU_EnableDBGSleepMode(void);
00523 void HAL_DBGMCU_DisableDBGSleepMode(void);
00524 void HAL_DBGMCU_EnableDBGStopMode(void);
00525 void HAL_DBGMCU_DisableDBGStopMode(void);
00526 void HAL_DBGMCU_EnableDBGStandbyMode(void);
00527 void HAL_DBGMCU_DisableDBGStandbyMode(void);
00528
00529 /**
00530   * @}
00531   */
00532
00533 /** @addtogroup HAL_Exported_Functions_Group4
00534   * @{
00535   */
00536
00537 /* SYSCFG Control functions  ****************************************************/
00538 void HAL_SYSCFG_SRAM2Erase(void);
00539 void HAL_SYSCFG_EnableMemorySwappingBank(void);
00540 void HAL_SYSCFG_DisableMemorySwappingBank(void);
00541
00542 #if defined(VREFBUF)
00543 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
00544 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
00545 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
00546 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
00547 void HAL_SYSCFG_DisableVREFBUF(void);
00548 #endif /* VREFBUF */
00549
00550 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
00551 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
00552
00553 /**
00554   * @}
00555   */
00556
00557 /**
00558   * @}
00559   */
00560
00561 /**
00562   * @}
00563   */
00564
00565 /**
00566   * @}
00567   */
00568
00569 #ifdef __cplusplus
00570 }
00571 #endif
00572
00573 #endif /* __STM32L4xx_HAL_H */
00574
00575 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_adc.c Source File

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stm32l4xx_hal_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_adc.c
00004   * @author  MCD Application conversion
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Analog to Digital Convertor (ADC)
00009   *          peripheral:
00010   *           + Initialization and de-initialization functions
00011   *             ++ Configuration of ADC
00012   *           + Operation functions
00013   *             ++ Start, stop, get result of regular conversions of regular
00014   *                using 3 possible modes: polling, interruption or DMA.
00015   *           + Control functions
00016   *             ++ Analog Watchdog configuration
00017   *             ++ Channels configuration on regular group
00018   *           + State functions
00019   *             ++ ADC state machine management
00020   *             ++ Interrupts and flags management
00021   *
00022    @verbatim
00023   ==============================================================================
00024                     ##### ADC specific features #####
00025   ==============================================================================
00026   [..]
00027   (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
00028
00029   (#) Interrupt generation at the end of regular conversion and in case of
00030       analog watchdog and overrun events.
00031
00032   (#) Single and continuous conversion modes.
00033
00034   (#) Scan mode for automatic conversion of channel 0 to channel 'n'.
00035
00036   (#) Data alignment with in-built data coherency.
00037
00038   (#) Channel-wise programmable sampling time.
00039
00040   (#) External trigger (timer or EXTI) with configurable polarity for
00041       regular groups.
00042
00043   (#) DMA request generation for transfer of regular group converted data.
00044
00045   (#) Configurable delay between conversions in Dual interleaved mode.
00046
00047   (#) ADC channels selectable single/differential input.
00048
00049   (#) ADC offset on regular groups.
00050
00051   (#) ADC supply requirements: 1.62 V to 3.6 V.
00052
00053   (#) ADC input range: from Vref_ (connected to Vssa) to Vref+ (connected to
00054       Vdda or to an external voltage reference).
00055
00056
00057
00058                      ##### How to use this driver #####
00059   ==============================================================================
00060     [..]
00061
00062     (#) Enable the ADC interface
00063         As prerequisite, in HAL_ADC_MspInit(), ADC clock source must be
00064         configured at RCC top level.
00065
00066         Two different clock sources are available:
00067         (++) - the ADC clock can be a specific clock source, coming from the system
00068         clock, the PLLSAI1 or the PLLSAI2 running up to 80MHz.
00069         (++) - or the ADC clock can be derived from the AHB clock of the ADC bus
00070        interface, divided by a programmable factor
00071
00072
00073         (++) For example, in case of PLLSAI2:
00074             (+++) __HAL_RCC_ADC_CLK_ENABLE();
00075             (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
00076             (+++) where
00077               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
00078               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLLSAI2
00079
00080
00081     (#) ADC pins configuration
00082          (++) Enable the clock for the ADC GPIOs using the following function:
00083              __HAL_RCC_GPIOx_CLK_ENABLE();
00084          (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
00085
00086     (#) Configure the ADC parameters (conversion resolution, data alignment,
00087          continuous mode, ...) using the HAL_ADC_Init() function.
00088
00089     (#) Optionally, perform an automatic ADC calibration to improve the
00090         conversion accuracy using function HAL_ADCEx_Calibration_Start().
00091
00092     (#) Activate the ADC peripheral using one of the start functions:
00093         HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(),
00094         HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or
00095         HAL_ADCEx_MultiModeStart_DMA() when multimode feature is available.
00096
00097    *** Channels to regular group configuration ***
00098      ============================================
00099      [..]
00100        (+) To configure the ADC regular group features, use
00101            HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
00102        (+) To activate the continuous mode, use the HAL_ADC_Init() function.
00103        (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
00104
00105      *** DMA for regular configuration ***
00106      =============================================================
00107      [..]
00108        (+) To enable the DMA mode for regular group, use the
00109            HAL_ADC_Start_DMA() function.
00110        (+) To enable the generation of DMA requests continuously at the end of
00111            the last DMA transfer, resort to DMAContinuousRequests parameter of
00112            ADC handle initialization structure.
00113
00114
00115
00116     @endverbatim
00117   ******************************************************************************
00118   * @attention
00119   *
00120   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00121   *
00122   * Redistribution and use in source and binary forms, with or without modification,
00123   * are permitted provided that the following conditions are met:
00124   *   1. Redistributions of source code must retain the above copyright notice,
00125   *      this list of conditions and the following disclaimer.
00126   *   2. Redistributions in binary form must reproduce the above copyright notice,
00127   *      this list of conditions and the following disclaimer in the documentation
00128   *      and/or other materials provided with the distribution.
00129   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00130   *      may be used to endorse or promote products derived from this software
00131   *      without specific prior written permission.
00132   *
00133   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00134   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00135   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00136   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00137   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00138   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00139   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00140   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00141   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00142   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00143   *
00144   ******************************************************************************
00145   */
00146
00147 /* Includes ------------------------------------------------------------------*/
00148 #include "stm32l4xx_hal.h"
00149
00150 /** @addtogroup STM32L4xx_HAL_Driver
00151   * @{
00152   */
00153
00154 /** @defgroup ADC ADC
00155   * @brief ADC HAL module driver
00156   * @{
00157   */
00158
00159 #ifdef HAL_ADC_MODULE_ENABLED
00160
00161 /* Private typedef -----------------------------------------------------------*/
00162 /* Private define ------------------------------------------------------------*/
00163
00164 /** @defgroup ADC_Private_Constants ADC Private Constants
00165   * @{
00166   */
00167
00168 #define ADC_CFGR_FIELDS_1  ((uint32_t)(ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
00169                                        ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
00170                                        ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
00171                                        ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))   /*!< ADC_CFGR fields of parameters that can be updated
00172                                                                                   when no regular conversion is on-going */
00173
00174 #define ADC_CFGR2_FIELDS  ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR  |\
00175                                        ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
00176                                        ADC_CFGR2_ROVSM))                     /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
00177                                                                                  (neither regular nor injected) is on-going  */
00178
00179 #define ADC_CFGR_WD_FIELDS  ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \
00180                                         ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH))  /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
00181                                                                                   conversion (neither regular nor injected) is on-going  */
00182
00183 #define ADC_OFR_FIELDS  ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
00184                                                                                                         (neither regular nor injected) is on-going */
00185
00186
00187
00188 /* Delay to wait before setting ADEN once ADCAL has been reset
00189    must be at least 4 ADC clock cycles.
00190    Assuming lowest ADC clock (140 KHz according to DS), this
00191    4 ADC clock cycles duration is equal to
00192    4 / 140,000 = 0.028 ms.
00193    ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
00194    the 4 ADC clock cycles have elapsed while waiting for ADRDY
00195    to become 1 */
00196   #define ADC_ENABLE_TIMEOUT              ((uint32_t)  2)    /*!< ADC enable time-out value  */
00197   #define ADC_DISABLE_TIMEOUT             ((uint32_t)  2)    /*!< ADC disable time-out value */
00198
00199
00200
00201 /* Delay for ADC voltage regulator startup time                               */
00202 /*  Maximum delay is 10 microseconds                                          */
00203 /* (refer device RM, parameter Tadcvreg_stup).                                */
00204 #define ADC_STAB_DELAY_US               ((uint32_t) 10)     /*!< ADC voltage regulator startup time */
00205
00206
00207 /* Timeout to wait for current conversion on going to be completed.           */
00208 /* Timeout fixed to worst case, for 1 channel.                                */
00209 /*   - maximum sampling time (640.5 adc_clk)                                  */
00210 /*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                            */
00211 /*   - ADC clock with prescaler 256                                           */
00212 /*     653 * 256 = 167168 clock cycles max                                    */
00213 /* Unit: cycles of CPU clock.                                                 */
00214 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168)  /*!< ADC conversion completion time-out value */
00215
00216
00217
00218
00219 /**
00220   * @}
00221   */
00222
00223 /* Private macro -------------------------------------------------------------*/
00224 /* Private variables ---------------------------------------------------------*/
00225 /* Private function prototypes -----------------------------------------------*/
00226 /* Exported functions --------------------------------------------------------*/
00227
00228 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00229   * @{
00230   */
00231
00232 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00233  *  @brief    Initialization and Configuration functions
00234  *
00235 @verbatim
00236  ===============================================================================
00237               ##### Initialization and de-initialization functions #####
00238  ===============================================================================
00239     [..]  This section provides functions allowing to:
00240       (+) Initialize and configure the ADC.
00241       (+) De-initialize the ADC.
00242
00243 @endverbatim
00244   * @{
00245   */
00246
00247 /**
00248   * @brief  Initialize the ADC peripheral and regular group according to
00249   *         parameters specified in structure "ADC_InitTypeDef".
00250   * @note   As prerequisite, ADC clock must be configured at RCC top level
00251   *         depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks
00252   *         or AHB clock.
00253   * @note   Possibility to update parameters on the fly:
00254   *         this function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00255   *         coming from ADC state reset. Following calls to this function can
00256   *         be used to reconfigure some parameters of ADC_InitTypeDef
00257   *         structure on the fly, without modifying MSP configuration. If ADC
00258   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00259   *         before HAL_ADC_Init().
00260   *         The setting of these parameters is conditioned by ADC state.
00261   *         For parameters constraints, see comments of structure
00262   *         "ADC_InitTypeDef".
00263   * @note   This function configures the ADC within 2 scopes: scope of entire
00264   *         ADC and scope of regular group. For parameters details, see comments
00265   *         of structure "ADC_InitTypeDef".
00266   * @note   Parameters related to common ADC registers (ADC clock mode) are set
00267   *         only if all ADCs are disabled.
00268   *         If this is not the case, these common parameters setting are
00269   *         bypassed without error reporting: it can be the intended behaviour in
00270   *         case of update of a parameter of ADC_InitTypeDef on the fly,
00271   *         without  disabling the other ADCs.
00272   * @param  hadc: ADC handle
00273   * @retval HAL status
00274   */
00275 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
00276 {
00277   HAL_StatusTypeDef tmp_status = HAL_OK;
00278
00279   ADC_Common_TypeDef *tmpADC_Common;
00280   uint32_t tmpCFGR = 0;
00281   __IO uint32_t wait_loop_index = 0;
00282
00283   /* Check ADC handle */
00284   if(hadc == NULL)
00285   {
00286     return HAL_ERROR;
00287   }
00288
00289   /* Check the parameters */
00290   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00291   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
00292   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
00293   assert_param(IS_ADC_DFSDMCFG_MODE(hadc));
00294   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
00295   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
00296   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00297   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00298   assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
00299   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00300   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
00301   assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
00302   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
00303   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
00304
00305   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
00306   {
00307     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
00308     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00309
00310     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00311     {
00312       assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
00313     }
00314   }
00315
00316
00317   /* DISCEN and CONT bits can't be set at the same time */
00318   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
00319
00320
00321   /* Actions performed only if ADC is coming from state reset:                */
00322   /* - Initialization of ADC MSP                                              */
00323   if (hadc->State == HAL_ADC_STATE_RESET)
00324   {
00325     /* Init the low level hardware */
00326     HAL_ADC_MspInit(hadc);
00327
00328     /* Set ADC error code to none */
00329     ADC_CLEAR_ERRORCODE(hadc);
00330
00331     /* Initialize Lock */
00332     hadc->Lock = HAL_UNLOCKED;
00333   }
00334
00335
00336   /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
00337   /*  Exit deep power down mode if still in that state */
00338   if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
00339   {
00340     /* Exit deep power down mode */
00341     CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
00342
00343     /* System was in deep power down mode, calibration must
00344      be relaunched or a previously saved calibration factor
00345      re-applied once the ADC voltage regulator is enabled */
00346   }
00347
00348
00349   if  (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
00350   {
00351     /* Enable ADC internal voltage regulator */
00352     SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
00353
00354     /* Delay for ADC stabilization time */
00355     /* Wait loop initialization and execution */
00356     /* Note: Variable divided by 2 to compensate partially                    */
00357     /*       CPU processing cycles.                                           */
00358     wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
00359     while(wait_loop_index != 0)
00360     {
00361       wait_loop_index--;
00362     }
00363   }
00364
00365
00366
00367
00368   /* Verification that ADC voltage regulator is correctly enabled, whether    */
00369   /* or not ADC is coming from state reset (if any potential problem of       */
00370   /* clocking, voltage regulator would not be enabled).                       */
00371   if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
00372   {
00373     /* Update ADC state machine to error */
00374     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00375
00376     /* Set ADC error code to ADC IP internal error */
00377     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00378
00379     tmp_status = HAL_ERROR;
00380   }
00381
00382
00383   /* Configuration of ADC parameters if previous preliminary actions are      */
00384   /* correctly completed and if there is no conversion on going on regular    */
00385   /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
00386   /* called to update a parameter on the fly).                                */
00387   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
00388       (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  )
00389   {
00390
00391     /* Initialize the ADC state */
00392     SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00393
00394     /* Configuration of common ADC parameters                                 */
00395
00396     /* Pointer to the common control register                                 */
00397     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
00398
00399
00400     /* Parameters update conditioned to ADC state:                            */
00401     /* Parameters that can be updated only when ADC is disabled:              */
00402     /*  - clock configuration                                                 */
00403     if ((ADC_IS_ENABLE(hadc) == RESET)   &&
00404          (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
00405     {
00406       /* Reset configuration of ADC common register CCR:                      */
00407       /*                                                                      */
00408       /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
00409       /*     according to adc->Init.ClockPrescaler. It selects the clock      */
00410       /*    source and sets the clock division factor.                        */
00411       /*                                                                      */
00412       /* Some parameters of this register are not reset, since they are set   */
00413       /* by other functions and must be kept in case of usage of this         */
00414       /* function on the fly (update of a parameter of ADC_InitTypeDef        */
00415       /* without needing to reconfigure all other ADC groups/channels         */
00416       /* parameters):                                                         */
00417       /*   - when multimode feature is available, multimode-related           */
00418       /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
00419       /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
00420       /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
00421       /*     (set into HAL_ADC_ConfigChannel() or                             */
00422       /*     HAL_ADCEx_InjectedConfigChannel() )                              */
00423
00424       MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
00425     }
00426
00427
00428     /* Configuration of ADC:                                                  */
00429     /*  - resolution                               Init.Resolution            */
00430     /*  - data alignment                           Init.DataAlign             */
00431     /*  - external trigger to start conversion     Init.ExternalTrigConv      */
00432     /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
00433     /*  - continuous conversion mode               Init.ContinuousConvMode    */
00434     /*  - overrun                                  Init.Overrun               */
00435     /*  - discontinuous mode                       Init.DiscontinuousConvMode */
00436     /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */
00437     tmpCFGR  = ( ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode)          |
00438                  hadc->Init.Overrun                                          |
00439                  hadc->Init.DataAlign                                        |
00440                  hadc->Init.Resolution                                       |
00441                 ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) |
00442                 ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
00443
00444     /* Enable external trigger if trigger selection is different of software  */
00445     /* start.                                                                 */
00446     /*  - external trigger to start conversion     Init.ExternalTrigConv      */
00447     /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
00448     /* Note:  parameter ExternalTrigConvEdge set to "trigger edge none" is    */
00449     /*        equivalent to software start.                                   */
00450     if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
00451     &&  (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
00452     {
00453       tmpCFGR |= ( hadc->Init.ExternalTrigConv |  hadc->Init.ExternalTrigConvEdge);
00454     }
00455
00456      /* Update Configuration Register CFGR */
00457      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
00458
00459
00460     /* Parameters update conditioned to ADC state:                            */
00461     /* Parameters that can be updated when ADC is disabled or enabled without */
00462     /* conversion on going on regular and injected groups:                    */
00463     /*  - DMA continuous request          Init.DMAContinuousRequests          */
00464     /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
00465     /*  - Oversampling parameters         Init.Oversampling                     */
00466     if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
00467     {
00468       tmpCFGR = ( ADC_CFGR_DFSDM(hadc)                                 |
00469                   ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait)       |
00470                   ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
00471
00472       MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
00473
00474
00475       if (hadc->Init.OversamplingMode == ENABLE)
00476       {
00477         assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
00478         assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
00479         assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
00480         assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
00481
00482         if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
00483         ||  (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
00484         {
00485             /* Multi trigger is not applicable to software-triggered conversions */
00486             assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
00487         }
00488
00489
00490        /* Configuration of Oversampler:                                       */
00491        /*  - Oversampling Ratio                                               */
00492        /*  - Right bit shift                                                  */
00493        /*  - Triggered mode                                                   */
00494        /*  - Oversampling mode (continued/resumed)                            */
00495        MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
00496                                ADC_CFGR2_ROVSE                     |
00497                                hadc->Init.Oversampling.Ratio         |
00498                                hadc->Init.Oversampling.RightBitShift |
00499                                hadc->Init.Oversampling.TriggeredMode |
00500                                hadc->Init.Oversampling.OversamplingStopReset);
00501       }
00502       else
00503       {
00504         /* Disable Regular OverSampling */
00505         CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
00506       }
00507
00508
00509     }   /*  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
00510
00511
00512
00513
00514     /* Configuration of regular group sequencer:                              */
00515     /* - if scan mode is disabled, regular channels sequence length is set to */
00516     /*   0x00: 1 channel converted (channel on regular rank 1)                */
00517     /*   Parameter "NbrOfConversion" is discarded.                            */
00518     /*   Note: Scan mode is not present by hardware on this device, but       */
00519     /*   emulated by software for alignment over all STM32 devices.           */
00520     /* - if scan mode is enabled, regular channels sequence length is set to  */
00521     /*   parameter "NbrOfConversion"                                          */
00522
00523     if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
00524     {
00525       /* Set number of ranks in regular group sequencer */
00526       MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
00527     }
00528     else
00529     {
00530       CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
00531     }
00532
00533
00534     /* Initialize the ADC state */
00535     /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
00536     ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
00537   }
00538   else
00539   {
00540     /* Update ADC state machine to error */
00541     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00542
00543     tmp_status = HAL_ERROR;
00544   }  /*  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)  && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  ) */
00545
00546
00547   /* Return function status */
00548   return tmp_status;
00549
00550 }
00551
00552 /**
00553   * @brief  Deinitialize the ADC peripheral registers to their default reset
00554   *         values, with deinitialization of the ADC MSP.
00555   * @note   Keep in mind that all ADCs use the same clock: disabling
00556   *         the clock will reset all ADCs.
00557   * @note   By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by
00558   *         reducing the leakage currents and is particularly interesting before
00559   *         entering STOP 1 or STOP 2 modes.
00560   * @param  hadc: ADC handle
00561   * @retval HAL status
00562   */
00563 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
00564 {
00565   /* Check ADC handle */
00566   if(hadc == NULL)
00567   {
00568      return HAL_ERROR;
00569   }
00570
00571   /* Check the parameters */
00572   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00573
00574   /* Change ADC state */
00575   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00576
00577   /* Stop potential conversion on going, on regular and injected groups */
00578   /* No check on ADC_ConversionStop() return status, if the conversion
00579     stop failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
00580   ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
00581
00582
00583   /* Disable ADC peripheral if conversions are effectively stopped            */
00584   /* Flush register JSQR: reset the queue sequencer when injected             */
00585   /* queue sequencer is enabled and ADC disabled.                             */
00586   /* The software and hardware triggers of the injected sequence are both     */
00587   /* internally disabled just after the completion of the last valid          */
00588   /* injected sequence.                                                       */
00589   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
00590
00591   /* Disable the ADC peripheral */
00592   /* No check on ADC_Disable() return status, if the ADC disabling process
00593     failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
00594   ADC_Disable(hadc);
00595
00596
00597   /* ========== Reset ADC registers ========== */
00598   /* Reset register IER */
00599   __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
00600                               ADC_IT_JQOVF | ADC_IT_OVR  |
00601                               ADC_IT_JEOS  | ADC_IT_JEOC |
00602                               ADC_IT_EOS   | ADC_IT_EOC  |
00603                               ADC_IT_EOSMP | ADC_IT_RDY                 ) );
00604
00605   /* Reset register ISR */
00606   __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
00607                               ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
00608                               ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
00609                               ADC_FLAG_EOS   | ADC_FLAG_EOC  |
00610                               ADC_FLAG_EOSMP | ADC_FLAG_RDY                   ) );
00611
00612   /* Reset register CR */
00613  /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
00614     ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
00615     no direct reset applicable.
00616     Update CR register to reset value where doable by software */
00617   CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
00618   SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
00619
00620   /* Reset register CFGR */
00621   CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
00622   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00623
00624   /* Reset register CFGR2 */
00625   CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS |
00626                                   ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE    );
00627
00628   /* Reset register SMPR1 */
00629   CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
00630
00631   /* Reset register SMPR2 */
00632   CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
00633                              ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
00634                              ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10    );
00635
00636   /* Reset register TR1 */
00637   CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
00638
00639   /* Reset register TR2 */
00640   CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
00641
00642   /* Reset register TR3 */
00643   CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
00644
00645   /* Reset register SQR1 */
00646   CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
00647                             ADC_SQR1_SQ1 | ADC_SQR1_L);
00648
00649   /* Reset register SQR2 */
00650   CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
00651                             ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
00652
00653   /* Reset register SQR3 */
00654   CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
00655                             ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
00656
00657   /* Reset register SQR4 */
00658   CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00659
00660   /* Register JSQR was reset when the ADC was disabled */
00661
00662   /* Reset register DR */
00663   /* bits in access mode read only, no direct reset applicable*/
00664
00665   /* Reset register OFR1 */
00666   CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
00667   /* Reset register OFR2 */
00668   CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
00669   /* Reset register OFR3 */
00670   CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
00671   /* Reset register OFR4 */
00672   CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
00673
00674   /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00675   /* bits in access mode read only, no direct reset applicable*/
00676
00677   /* Reset register AWD2CR */
00678   CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
00679
00680   /* Reset register AWD3CR */
00681   CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
00682
00683   /* Reset register DIFSEL */
00684   CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
00685
00686   /* Reset register CALFACT */
00687   CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00688
00689
00690
00691
00692
00693
00694   /* ========== Reset common ADC registers ========== */
00695
00696   /* Software is allowed to change common parameters only when all the other
00697      ADCs are disabled.   */
00698   if ((ADC_IS_ENABLE(hadc) == RESET)   &&
00699        (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
00700   {
00701     /* Reset configuration of ADC common register CCR:
00702       - clock mode: CKMODE, PRESCEN
00703       - multimode related parameters (when this feature is available): MDMA,
00704         DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
00705       - internal measurement paths: Vbat, temperature sensor, Vref (set into
00706         HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
00707     */
00708     ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
00709   }
00710
00711   /* DeInit the low level hardware.
00712
00713      For example:
00714     __HAL_RCC_ADC_FORCE_RESET();
00715     __HAL_RCC_ADC_RELEASE_RESET();
00716     __HAL_RCC_ADC_CLK_DISABLE();
00717
00718     Keep in mind that all ADCs use the same clock: disabling
00719     the clock will reset all ADCs.
00720
00721   */
00722   HAL_ADC_MspDeInit(hadc);
00723
00724   /* Set ADC error code to none */
00725   ADC_CLEAR_ERRORCODE(hadc);
00726
00727   /* Reset injected channel configuration parameters */
00728   hadc->InjectionConfig.ContextQueue = 0;
00729   hadc->InjectionConfig.ChannelCount = 0;
00730
00731   /* Change ADC state */
00732   hadc->State = HAL_ADC_STATE_RESET;
00733
00734   /* Process unlocked */
00735   __HAL_UNLOCK(hadc);
00736
00737
00738   /* Return function status */
00739   return HAL_OK;
00740
00741 }
00742
00743 /**
00744   * @brief  Initialize the ADC MSP.
00745   * @param  hadc: ADC handle
00746   * @retval None
00747   */
00748 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
00749 {
00750   /* Prevent unused argument(s) compilation warning */
00751   UNUSED(hadc);
00752
00753   /* NOTE : This function should not be modified. When the callback is needed,
00754             function HAL_ADC_MspInit must be implemented in the user file.
00755    */
00756 }
00757
00758 /**
00759   * @brief  DeInitialize the ADC MSP.
00760   * @param  hadc: ADC handle
00761   * @note   All ADCs use the same clock: disabling the clock will reset all ADCs.
00762   * @retval None
00763   */
00764 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
00765 {
00766   /* Prevent unused argument(s) compilation warning */
00767   UNUSED(hadc);
00768
00769   /* NOTE : This function should not be modified. When the callback is needed,
00770             function HAL_ADC_MspDeInit must be implemented in the user file.
00771    */
00772 }
00773
00774 /**
00775   * @}
00776   */
00777
00778 /** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
00779  *  @brief    IO operation functions
00780  *
00781 @verbatim
00782  ===============================================================================
00783              ##### IO operation functions #####
00784  ===============================================================================
00785     [..]  This section provides functions allowing to:
00786       (+) Start conversion of regular group.
00787       (+) Stop conversion of regular group.
00788       (+) Poll for conversion complete on regular group.
00789       (+) Poll for conversion event.
00790       (+) Get result of regular channel conversion.
00791       (+) Start conversion of regular group and enable interruptions.
00792       (+) Stop conversion of regular group and disable interruptions.
00793       (+) Handle ADC interrupt request
00794       (+) Start conversion of regular group and enable DMA transfer.
00795       (+) Stop conversion of regular group and disable ADC DMA transfer.
00796
00797 @endverbatim
00798   * @{
00799   */
00800
00801 /**
00802   * @brief  Enable ADC, start conversion of regular group.
00803   * @note   Interruptions enabled in this function: None.
00804   * @note   Case of multimode enabled (when multimode feature is available):
00805   *           if ADC is Slave, ADC is enabled but conversion is not started,
00806   *           if ADC is master, ADC is enabled and multimode conversion is started.
00807   * @param  hadc: ADC handle
00808   * @retval HAL status
00809   */
00810 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
00811 {
00812   ADC_TypeDef        *tmpADC_Master;
00813   HAL_StatusTypeDef tmp_status = HAL_OK;
00814
00815   /* Check the parameters */
00816   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00817
00818
00819   /* if a regular conversion is already on-going (i.e. ADSTART is set),
00820      don't restart the conversion. */
00821   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
00822   {
00823     return HAL_BUSY;
00824   }
00825   else
00826   {
00827     /* Process locked */
00828     __HAL_LOCK(hadc);
00829
00830     /* Enable the ADC peripheral */
00831     tmp_status = ADC_Enable(hadc);
00832
00833     /* Start conversion if ADC is effectively enabled */
00834     if (tmp_status == HAL_OK)
00835     {
00836       /* State machine update: Check if an injected conversion is ongoing */
00837       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00838       {
00839         /* Reset ADC error code fields related to regular conversions only */
00840         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));
00841       }
00842       else
00843       {
00844         /* Set ADC error code to none */
00845         ADC_CLEAR_ERRORCODE(hadc);
00846       }
00847       /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
00848       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
00849
00850       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00851         - by default if ADC is Master or Independent or if multimode feature is not available
00852         - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
00853       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00854       {
00855         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00856       }
00857
00858       /* Clear regular group conversion flag and overrun flag                   */
00859       /* (To ensure of no unknown state from potential previous ADC operations) */
00860       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
00861
00862       /* Enable conversion of regular group.                                  */
00863       /* If software start has been selected, conversion starts immediately.  */
00864       /* If external trigger has been selected, conversion starts at next     */
00865       /* trigger event.                                                       */
00866       /* Case of multimode enabled (when multimode feature is available):     */
00867       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
00868       /*    enabled only (conversion is not started),                         */
00869       /*  - if ADC is master, ADC is enabled and conversion is started.       */
00870       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
00871       {
00872         /* Multimode feature is not available or ADC Instance is Independent or Master,
00873            or is not Slave ADC with dual regular conversions enabled.
00874            Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */
00875         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
00876         {
00877           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00878         }
00879         /* Process unlocked */
00880         __HAL_UNLOCK(hadc);
00881         /* Start ADC */
00882         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
00883       }
00884       else
00885       {
00886         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00887         /* if Master ADC JAUTO bit is set, update Slave State in setting
00888            HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
00889         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
00890         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
00891         {
00892           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00893
00894         }  /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
00895         /* Process unlocked */
00896         __HAL_UNLOCK(hadc);
00897       } /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */
00898     }
00899     else
00900     {
00901       /* Process unlocked */
00902       __HAL_UNLOCK(hadc);
00903     }
00904
00905   /* Return function status */
00906   return tmp_status;
00907   }
00908 }
00909
00910 /**
00911   * @brief  Stop ADC conversion of regular and injected groups, disable ADC peripheral.
00912   * @param  hadc: ADC handle
00913   * @retval HAL status.
00914   */
00915 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
00916 {
00917   HAL_StatusTypeDef tmp_status = HAL_OK;
00918
00919   /* Check the parameters */
00920   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00921
00922   /* Process locked */
00923   __HAL_LOCK(hadc);
00924
00925   /* 1. Stop potential regular and injected on-going conversions */
00926   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
00927
00928   /* Disable ADC peripheral if conversions are effectively stopped */
00929   if (tmp_status == HAL_OK)
00930   {
00931     /* 2. Disable the ADC peripheral */
00932     tmp_status = ADC_Disable(hadc);
00933
00934     /* Check if ADC is effectively disabled */
00935     if (tmp_status == HAL_OK)
00936     {
00937       /* Change ADC state */
00938       /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
00939       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
00940     }
00941   }
00942
00943   /* Process unlocked */
00944   __HAL_UNLOCK(hadc);
00945
00946   /* Return function status */
00947   return tmp_status;
00948 }
00949
00950
00951
00952 /**
00953   * @brief  Wait for regular group conversion to be completed.
00954   * @param  hadc: ADC handle
00955   * @param  Timeout: Timeout value in millisecond.
00956   * @note   Depending on hadc->Init.EOCSelection, EOS or EOC is
00957   *         checked and cleared depending on AUTDLY bit status.
00958   * @note   HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a
00959   *         DMA-managed conversions configuration: indeed, EOC is immediately
00960   *         reset by the DMA reading the DR register when the converted data is
00961   *         available. Therefore, EOC is set for a too short period to be
00962   *         reliably polled.
00963   * @retval HAL status
00964   */
00965 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00966 {
00967   uint32_t           tickstart;
00968   uint32_t           tmp_Flag_End   = 0x00;
00969   ADC_TypeDef        *tmpADC_Master;
00970   uint32_t           tmp_cfgr       = 0x00;
00971   uint32_t           tmp_eos_raised = 0x01; /* by default, assume that EOS is set,
00972                                                tmp_eos_raised will be corrected
00973                                                accordingly during API execution */
00974
00975   /* Check the parameters */
00976   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00977
00978   /* If end of sequence selected */
00979   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
00980   {
00981     tmp_Flag_End = ADC_FLAG_EOS;
00982   }
00983   else /* end of conversion selected */
00984   {
00985     /* Check that the ADC is not in a DMA-based configuration. Otherwise,
00986        returns an error.  */
00987
00988     /* Check whether dual regular conversions are disabled or unavailable. */
00989     if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
00990     {
00991       /* Check DMAEN bit in handle ADC CFGR register */
00992       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET)
00993       {
00994         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00995         return HAL_ERROR;
00996       }
00997     }
00998     else
00999     {
01000       /* Else need to check Common register CCR MDMA bit field. */
01001       if (ADC_MULTIMODE_DMA_ENABLED())
01002       {
01003         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01004         return HAL_ERROR;
01005       }
01006     }
01007
01008     /* no DMA transfer detected, polling ADC_FLAG_EOC is possible */
01009     tmp_Flag_End = ADC_FLAG_EOC;
01010   }
01011
01012   /* Get timeout */
01013   tickstart = HAL_GetTick();
01014
01015   /* Wait until End of Conversion or Sequence flag is raised */
01016   while (HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
01017   {
01018     /* Check if timeout is disabled (set to infinite wait) */
01019     if(Timeout != HAL_MAX_DELAY)
01020     {
01021       if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01022       {
01023         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01024         return HAL_TIMEOUT;
01025       }
01026     }
01027   }
01028
01029   /* Next, to clear the polled flag as well as to update the handle State,
01030      EOS is checked and the relevant configuration register is retrieved. */
01031   /*   1. Check whether or not EOS is set */
01032   if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS))
01033   {
01034     tmp_eos_raised = 0;
01035   }
01036   /*  2. Check whether or not hadc is the handle of a Slave ADC with dual
01037    regular conversions enabled. */
01038    if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
01039   {
01040     /* Retrieve handle ADC CFGR register */
01041     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
01042   }
01043   else
01044   {
01045     /* Retrieve Master ADC CFGR register */
01046     tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01047     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
01048   }
01049
01050   /* Clear polled flag */
01051   if (tmp_Flag_End == ADC_FLAG_EOS)
01052   {
01053     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
01054   }
01055   else
01056   {
01057
01058     /* Clear end of conversion EOC flag of regular group if low power feature */
01059     /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
01060     /* until data register is read using function HAL_ADC_GetValue().         */
01061     /* For regular groups, no new conversion will start before EOC is cleared.*/
01062     /* Note that 1. reading DR clears EOC.                                    */
01063     /*           2. in multimode with dual regular conversions enabled (when  */
01064     /*              multimode feature is available), Master AUTDLY bit is     */
01065     /*              checked.                                                  */
01066     if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
01067     {
01068       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
01069     }
01070   }
01071
01072
01073   /* Update ADC state machine */
01074   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01075   /* If 1. EOS is set
01076         2. conversions are software-triggered
01077         3. CONT bit is reset (that of handle ADC or Master ADC if applicable)
01078      Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset.
01079         4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY
01080           can be set */
01081   if ((tmp_eos_raised)
01082    && (ADC_IS_SOFTWARE_START_REGULAR(hadc))
01083    && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET))
01084    {
01085      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01086      /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
01087      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01088      {
01089        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01090      }
01091    }
01092
01093
01094   /* Return API HAL status */
01095   return HAL_OK;
01096 }
01097
01098 /**
01099   * @brief  Poll for ADC event.
01100   * @param  hadc: ADC handle
01101   * @param  EventType: the ADC event type.
01102   *          This parameter can be one of the following values:
01103   *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
01104   *            @arg @ref ADC_AWD_EVENT    ADC Analog watchdog 1 event
01105   *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event
01106   *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event
01107   *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
01108   *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
01109   * @param  Timeout: Timeout value in millisecond.
01110   * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
01111   *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
01112   *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, DR may be potentially overwritten
01113   *         by a new converted data as soon as OVR is cleared.
01114   *         To reset OVR flag once the preserved data is retrieved, the user can resort
01115   *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01116   * @retval HAL status
01117   */
01118 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
01119 {
01120   uint32_t tickstart;
01121
01122   /* Check the parameters */
01123   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01124   assert_param(IS_ADC_EVENT_TYPE(EventType));
01125
01126   tickstart = HAL_GetTick();
01127
01128   /* Check selected event flag */
01129   while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
01130   {
01131     /* Check if timeout is disabled (set to infinite wait) */
01132     if(Timeout != HAL_MAX_DELAY)
01133     {
01134       if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01135       {
01136         /* Update ADC state machine to timeout */
01137         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01138
01139         /* Process unlocked */
01140         __HAL_UNLOCK(hadc);
01141
01142         return HAL_TIMEOUT;
01143       }
01144     }
01145   }
01146
01147
01148   switch(EventType)
01149   {
01150   /* End Of Sampling event */
01151   case ADC_EOSMP_EVENT:
01152     /* Change ADC state */
01153     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01154
01155     /* Clear the End Of Sampling flag */
01156     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
01157
01158     break;
01159
01160   /* Analog watchdog (level out of window) event                              */
01161   /* Note: In case of several analog watchdog enabled, if needed to know      */
01162   /* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
01163   /* flags HAL_ADC_STATE_AWD/2/3 function.                                    */
01164   /* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) "        */
01165   /*              "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)"        */
01166   /*              "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)"        */
01167   case ADC_AWD_EVENT:
01168     /* Change ADC state */
01169     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01170
01171     /* Clear ADC analog watchdog flag */
01172     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01173
01174     break;
01175
01176   /* Check analog watchdog 2 flag */
01177   case ADC_AWD2_EVENT:
01178     /* Change ADC state */
01179     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01180
01181     /* Clear ADC analog watchdog flag */
01182     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01183
01184     break;
01185
01186   /* Check analog watchdog 3 flag */
01187   case ADC_AWD3_EVENT:
01188     /* Change ADC state */
01189     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01190
01191     /* Clear ADC analog watchdog flag */
01192     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01193
01194     break;
01195
01196   /* Injected context queue overflow event */
01197   case ADC_JQOVF_EVENT:
01198     /* Change ADC state */
01199     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
01200
01201     /* Set ADC error code to Injected context queue overflow */
01202     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
01203
01204     /* Clear ADC Injected context queue overflow flag */
01205     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
01206
01207     break;
01208
01209   /* Overrun event */
01210   default: /* Case ADC_OVR_EVENT */
01211     /* If overrun is set to overwrite previous data, overrun event is not     */
01212     /* considered as an error.                                                */
01213     /* (cf ref manual "Managing conversions without using the DMA and without */
01214     /* overrun ")                                                             */
01215     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01216     {
01217       /* Change ADC state */
01218       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
01219
01220       /* Set ADC error code to overrun */
01221       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
01222     }
01223     else
01224     {
01225       /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
01226          otherwise, DR is potentially overwritten by new converted data as soon
01227          as OVR is cleared. */
01228       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01229     }
01230     break;
01231   }
01232
01233   /* Return API HAL status */
01234   return HAL_OK;
01235 }
01236
01237
01238 /**
01239   * @brief  Enable ADC, start conversion of regular group with interruption.
01240   * @note   Interruptions enabled in this function according to initialization
01241   *         setting : EOC (end of conversion), EOS (end of sequence),
01242   *         OVR overrun.
01243   *         Each of these interruptions has its dedicated callback function.
01244   * @note   Case of multimode enabled (when multimode feature is available):
01245   *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
01246   *         ADC Master.
01247   *         For ADC Slave, ADC is enabled only (conversion is not started).
01248   *         For ADC Master, ADC is enabled and multimode conversion is started.
01249   * @note   To guarantee a proper reset of all interruptions once all the needed
01250   *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
01251   *         a correct stop of the IT-based conversions.
01252   * @note   By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling
01253   *         interruption. If required (e.g. in case of oversampling with trigger
01254   *         mode), the user must
01255   *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
01256   *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
01257   *          before calling HAL_ADC_Start_IT().
01258   * @param  hadc: ADC handle
01259   * @retval HAL status
01260   */
01261 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
01262 {
01263   HAL_StatusTypeDef tmp_status = HAL_OK;
01264   ADC_TypeDef        *tmpADC_Master;
01265
01266   /* Check the parameters */
01267   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01268
01269   /* if a regular conversion is already on-going (i.e. ADSTART is set),
01270      don't restart the conversion. */
01271   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
01272   {
01273     return HAL_BUSY;
01274   }
01275   else
01276   {
01277     /* Process locked */
01278     __HAL_LOCK(hadc);
01279
01280     /* Enable the ADC peripheral */
01281     tmp_status = ADC_Enable(hadc);
01282
01283     /* Start conversion if ADC is effectively enabled */
01284     if (tmp_status == HAL_OK)
01285     {
01286       /* State machine update: Check if an injected conversion is ongoing */
01287       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01288       {
01289         /* Reset ADC error code fields related to regular conversions only */
01290         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));
01291       }
01292       else
01293       {
01294         /* Set ADC error code to none */
01295         ADC_CLEAR_ERRORCODE(hadc);
01296       }
01297       /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
01298       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
01299
01300       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01301         - by default if ADC is Master or Independent or if multimode feature is not available
01302         - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
01303       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
01304       {
01305         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01306       }
01307
01308       /* Clear regular group conversion flag and overrun flag */
01309       /* (To ensure of no unknown state from potential previous ADC operations) */
01310       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01311
01312       /* By default, disable all interruptions before enabling the desired ones */
01313       __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01314
01315       /* Enable required interruptions */
01316       switch(hadc->Init.EOCSelection)
01317       {
01318         case ADC_EOC_SEQ_CONV:
01319           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
01320          break;
01321         /* case ADC_EOC_SINGLE_CONV */
01322         default:
01323          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
01324          break;
01325       }
01326
01327       /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
01328          ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
01329          behavior and no CPU time is lost for a non-processed interruption */
01330       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01331       {
01332         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01333       }
01334
01335       /* Enable conversion of regular group.                                  */
01336       /* If software start has been selected, conversion starts immediately.  */
01337       /* If external trigger has been selected, conversion starts at next     */
01338       /* trigger event.                                                       */
01339       /* Case of multimode enabled (when multimode feature is available):     */
01340       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
01341       /*    enabled only (conversion is not started),                         */
01342       /*  - if ADC is master, ADC is enabled and conversion is started.       */
01343       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)   )
01344       {
01345         /* Multimode feature is not available or ADC Instance is Independent or Master,
01346            or is not Slave ADC with dual regular conversions enabled.
01347            Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */
01348         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
01349         {
01350           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01351
01352           /* Enable as well injected interruptions in case
01353            HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
01354            allows to start regular and injected conversions when JAUTO is
01355            set with a single call to HAL_ADC_Start_IT() */
01356           switch(hadc->Init.EOCSelection)
01357           {
01358             case ADC_EOC_SEQ_CONV:
01359               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01360               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01361             break;
01362             /* case ADC_EOC_SINGLE_CONV */
01363             default:
01364               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
01365               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01366             break;
01367           }
01368         } /*  if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */
01369         /* Process unlocked */
01370         __HAL_UNLOCK(hadc);
01371         /* Start ADC */
01372         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01373       }
01374       else
01375       {
01376         /* hadc is the handle of a Slave ADC with dual regular conversions
01377            enabled. Therefore, ADC_CR_ADSTART is NOT set */
01378         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01379         /* if Master ADC JAUTO bit is set, Slave injected interruptions
01380            are enabled nevertheless (for same reason as above) */
01381         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01382         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
01383         {
01384           /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
01385              and in resetting HAL_ADC_STATE_INJ_EOC bit */
01386           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01387           /* Next, set Slave injected interruptions */
01388           switch(hadc->Init.EOCSelection)
01389           {
01390             case ADC_EOC_SEQ_CONV:
01391               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01392               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01393             break;
01394             /* case ADC_EOC_SINGLE_CONV */
01395             default:
01396               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
01397               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01398             break;
01399           }
01400         }  /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
01401         /* Process unlocked */
01402         __HAL_UNLOCK(hadc);
01403       } /*  if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)   ) */
01404     }  /*  if (tmp_status == HAL_OK) */
01405     else
01406     {
01407       /* Process unlocked */
01408       __HAL_UNLOCK(hadc);
01409     }
01410
01411     /* Return function status */
01412     return tmp_status;
01413
01414   }
01415 }
01416
01417
01418
01419 /**
01420   * @brief  Stop ADC conversion of regular groups when interruptions are enabled.
01421   * @note   Stop as well injected conversions and disable ADC peripheral.
01422   * @param  hadc: ADC handle
01423   * @retval HAL status.
01424   */
01425 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
01426 {
01427   HAL_StatusTypeDef tmp_status = HAL_OK;
01428
01429   /* Check the parameters */
01430   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01431
01432   /* Process locked */
01433   __HAL_LOCK(hadc);
01434
01435   /* 1. Stop potential regular and injected on-going conversions */
01436   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01437
01438   /* Disable ADC peripheral if conversions are effectively stopped */
01439   if (tmp_status == HAL_OK)
01440   {
01441     /* Disable all interrupts */
01442     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01443
01444     /* 2. Disable the ADC peripheral */
01445     tmp_status = ADC_Disable(hadc);
01446
01447     /* Check if ADC is effectively disabled */
01448     if (tmp_status == HAL_OK)
01449     {
01450       /* Change ADC state */
01451       /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
01452       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
01453     }
01454   }
01455
01456   /* Process unlocked */
01457   __HAL_UNLOCK(hadc);
01458
01459   /* Return function status */
01460   return tmp_status;
01461 }
01462
01463
01464 /**
01465   * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
01466   * @note   Interruptions enabled in this function:
01467   *         overrun (if applicable), DMA half transfer, DMA transfer complete.
01468   *         Each of these interruptions has its dedicated callback function.
01469   * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
01470   *         is designed for single-ADC mode only. For multimode, the dedicated
01471   *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
01472   * @param  hadc: ADC handle
01473   * @param  pData: Destination Buffer address.
01474   * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
01475   * @retval None
01476   */
01477 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
01478 {
01479   HAL_StatusTypeDef tmp_status = HAL_OK;
01480
01481   /* Check the parameters */
01482   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01483
01484   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
01485   {
01486     return HAL_BUSY;
01487   }
01488   else
01489   {
01490
01491     /* Process locked */
01492     __HAL_LOCK(hadc);
01493
01494     /* Ensure that dual regular conversions are not enabled or unavailable.   */
01495     /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
01496     if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
01497     {
01498       /* Enable the ADC peripheral */
01499       tmp_status = ADC_Enable(hadc);
01500
01501       /* Start conversion if ADC is effectively enabled */
01502       if (tmp_status == HAL_OK)
01503       {
01504         /* State machine update: Check if an injected conversion is ongoing */
01505         if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01506         {
01507           /* Reset ADC error code fields related to regular conversions only */
01508           CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));
01509         }
01510         else
01511         {
01512           /* Set ADC error code to none */
01513           ADC_CLEAR_ERRORCODE(hadc);
01514         }
01515         /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
01516         ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
01517
01518        /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01519         - by default if ADC is Master or Independent or if multimode feature is not available
01520         - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
01521         if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
01522         {
01523           CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01524         }
01525
01526         /* Set the DMA transfer complete callback */
01527         hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
01528
01529         /* Set the DMA half transfer complete callback */
01530         hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
01531
01532         /* Set the DMA error callback */
01533         hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
01534
01535
01536         /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
01537         /* ADC start (in case of SW start):                                   */
01538
01539         /* Clear regular group conversion flag and overrun flag               */
01540         /* (To ensure of no unknown state from potential previous ADC         */
01541         /* operations)                                                        */
01542         __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01543
01544         /* With DMA, overrun event is always considered as an error even if
01545            hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
01546            ADC_IT_OVR is enabled.  */
01547         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01548
01549
01550         /* Enable ADC DMA mode */
01551         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
01552
01553         /* Start the DMA channel */
01554         HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
01555
01556         /* Enable conversion of regular group.                                  */
01557         /* Process unlocked */
01558         __HAL_UNLOCK(hadc);
01559         /* If software start has been selected, conversion starts immediately.  */
01560         /* If external trigger has been selected, conversion will start at next */
01561         /* trigger event.                                                       */
01562         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01563
01564       }
01565       else
01566       {
01567         /* Process unlocked */
01568         __HAL_UNLOCK(hadc);
01569       }  /* if (tmp_status == HAL_OK) */
01570     }
01571     else
01572     {
01573       tmp_status = HAL_ERROR;
01574       /* Process unlocked */
01575       __HAL_UNLOCK(hadc);
01576     } /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */
01577
01578
01579
01580   /* Return function status */
01581   return tmp_status;
01582   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) */
01583 }
01584
01585
01586 /**
01587   * @brief  Stop ADC conversion of regular groups and disable ADC DMA transfer.
01588   * @note   Stop as well injected conversions and disable ADC peripheral.
01589   * @note   Case of multimode enabled (when multimode feature is available):
01590   *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
01591   *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
01592   * @param  hadc: ADC handle
01593   * @retval HAL status.
01594   */
01595 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
01596 {
01597   HAL_StatusTypeDef tmp_status = HAL_OK;
01598
01599   /* Check the parameters */
01600   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01601
01602   /* Process locked */
01603   __HAL_LOCK(hadc);
01604
01605   /* 1. Stop potential regular conversion on going */
01606   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01607
01608   /* Disable ADC peripheral if conversions are effectively stopped */
01609   if (tmp_status == HAL_OK)
01610   {
01611     /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
01612     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
01613
01614     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01615     /* while DMA transfer is on going)                                        */
01616     tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
01617
01618     /* Check if DMA channel effectively disabled */
01619     if (tmp_status != HAL_OK)
01620     {
01621       /* Update ADC state machine to error */
01622       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01623     }
01624
01625     /* Disable ADC overrun interrupt */
01626     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01627
01628     /* 2. Disable the ADC peripheral */
01629     /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
01630     /* memory a potential failing status.                                     */
01631     if (tmp_status == HAL_OK)
01632     {
01633       tmp_status = ADC_Disable(hadc);
01634     }
01635     else
01636     {
01637       ADC_Disable(hadc);
01638     }
01639
01640     /* Check if ADC is effectively disabled */
01641     if (tmp_status == HAL_OK)
01642     {
01643       /* Change ADC state */
01644       /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
01645       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
01646     }
01647
01648   }
01649
01650   /* Process unlocked */
01651   __HAL_UNLOCK(hadc);
01652
01653   /* Return function status */
01654   return tmp_status;
01655 }
01656
01657
01658 /**
01659   * @brief  Get ADC regular group conversion result.
01660   * @param  hadc: ADC handle
01661   * @note   Reading DR register automatically clears EOC flag. To reset EOS flag,
01662   *         the user must resort to the macro
01663   *         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS)
01664   * @retval Converted value
01665   */
01666 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
01667 {
01668   /* Check the parameters */
01669   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01670
01671   /* Return ADC converted value */
01672   return hadc->Instance->DR;
01673 }
01674
01675
01676 /**
01677   * @brief  Handle ADC interrupt request.
01678   * @param  hadc: ADC handle
01679   * @retval None
01680   */
01681 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
01682 {
01683   uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
01684   ADC_TypeDef        *tmpADC_Master;
01685   uint32_t tmp_isr      = hadc->Instance->ISR;
01686   uint32_t tmp_ier      = hadc->Instance->IER;
01687   uint32_t tmp_cfgr     = 0x0;
01688   uint32_t tmp_cfgr_jqm = 0x0;
01689
01690
01691   /* Check the parameters */
01692   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01693   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
01694
01695
01696   /* ====== Check End of Sampling flag for regular group ===== */
01697   if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
01698   {
01699     /* Update state machine on end of sampling status if not in error state */
01700     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01701     {
01702       /* Change ADC state */
01703       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01704     }
01705
01706     /* End Of Sampling callback */
01707       HAL_ADCEx_EndOfSamplingCallback(hadc);
01708
01709     /* Clear regular group conversion flag */
01710     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
01711   }
01712
01713   /* ====== Check End of Conversion or Sequence flags for regular group ===== */
01714   if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
01715       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))  )
01716   {
01717     /* Update state machine on conversion status if not in error state */
01718     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01719     {
01720       /* Change ADC state */
01721       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01722     }
01723
01724     /* Disable interruption if no further conversion upcoming by regular      */
01725     /* external trigger or by continuous mode,                                */
01726     /* and if scan sequence if completed.                                     */
01727     if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
01728     {
01729       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
01730       {
01731         /* check CONT bit directly in handle ADC CFGR register */
01732         tmp_cfgr = READ_REG(hadc->Instance->CFGR);
01733       }
01734       else
01735       {
01736         /* else need to check Master ADC CONT bit */
01737         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01738         tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
01739       }
01740
01741       /* Carry on if continuous mode is disabled */
01742       if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
01743       {
01744         /* If End of Sequence is reached, disable interrupts */
01745         if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
01746         {
01747           /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
01748           /* ADSTART==0 (no conversion on going)                                */
01749           if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
01750           {
01751             /* Disable ADC end of sequence conversion interrupt */
01752             /* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */
01753             /* in HAL_Start_IT(), it isn't disabled here because it can be used */
01754             /* by overrun IRQ process below.                                    */
01755             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
01756             /* Clear HAL_ADC_STATE_REG_BUSY bit */
01757              CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01758              /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
01759              if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01760              {
01761                SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01762              }
01763           }
01764           else
01765           {
01766             /* Change ADC state to error state */
01767             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01768
01769             /* Set ADC error code to ADC IP internal error */
01770             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
01771           }
01772         }
01773       } /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */
01774     }   /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   */
01775
01776     /* Conversion complete callback */
01777     /* Note:  HAL_ADC_ConvCpltCallback can resort to
01778               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or
01779               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether
01780               interruption has been triggered by end of conversion or end of
01781               sequence.    */
01782       HAL_ADC_ConvCpltCallback(hadc);
01783
01784
01785     /* Clear regular group conversion flag */
01786     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
01787   }
01788
01789
01790   /* ========== Check End of Conversion flag for injected group ========== */
01791   if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
01792       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))  )
01793   {
01794     /* Update state machine on conversion status if not in error state */
01795     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01796     {
01797       /* Change ADC state */
01798       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
01799     }
01800
01801
01802     /* Check whether interruptions can be disabled only if
01803         - injected conversions are software-triggered when injected queue management is disabled
01804         OR
01805         - auto-injection is enabled, continuous mode is disabled (CONT = 0)
01806           and regular conversions are software-triggered */
01807           /* If End of Sequence is reached, disable interrupts */
01808     if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
01809     {
01810
01811       /* First, retrieve proper registers to check */
01812       /* 1a. Are injected conversions that of a dual Slave ? */
01813       if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
01814       {
01815         /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
01816            check JQM bit directly in ADC CFGR register */
01817         tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
01818       }
01819       else
01820       {
01821         /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
01822            need to check JQM bit of Master ADC CFGR register */
01823           tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01824           tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR);
01825       }
01826       /* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */
01827       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
01828       {
01829         /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
01830            check JAUTO and CONT bits directly in ADC CFGR register */
01831           tmp_cfgr = READ_REG(hadc->Instance->CFGR);
01832       }
01833       else
01834       {
01835         /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
01836            check JAUTO and CONT bits of Master ADC CFGR register */
01837         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01838         tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
01839       }
01840
01841       /* Secondly, check whether JEOC and JEOS interruptions can be disabled */
01842       if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM))
01843          && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&
01844              (ADC_IS_SOFTWARE_START_REGULAR(hadc))))    )
01845       {
01846         /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit         */
01847         /* JADSTART==0 (no conversion on going)                               */
01848         if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01849         {
01850           /* Disable ADC end of sequence conversion interrupt  */
01851           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
01852           /* Clear HAL_ADC_STATE_INJ_BUSY bit */
01853            CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01854            /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
01855           if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
01856           {
01857             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01858           }
01859         }
01860         else
01861         {
01862           /* Change ADC state to error state */
01863           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01864
01865           /* Set ADC error code to ADC IP internal error */
01866           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
01867         }
01868       }
01869     } /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */
01870
01871     /* Injected Conversion complete callback */
01872     /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to
01873               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
01874               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
01875               interruption has been triggered by end of conversion or end of
01876               sequence.    */
01877     HAL_ADCEx_InjectedConvCpltCallback(hadc);
01878
01879     /* Clear injected group conversion flag */
01880     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
01881   }
01882
01883
01884   /* ========== Check Analog watchdog flags =================================================== */
01885
01886   /* ========== Check Analog watchdog 1 flags ========== */
01887   if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
01888   {
01889     /* Change ADC state */
01890     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01891
01892     /* Level out of window 1 callback */
01893     HAL_ADC_LevelOutOfWindowCallback(hadc);
01894     /* Clear ADC Analog watchdog flag */
01895     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01896   }
01897
01898   /* ========== Check Analog watchdog 2 flags ========== */
01899   if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
01900   {
01901     /* Change ADC state */
01902     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01903
01904     /* Level out of window 2 callback */
01905     HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
01906     /* Clear ADC Analog watchdog flag */
01907     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01908   }
01909
01910   /* ========== Check Analog watchdog 3 flags ========== */
01911   if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
01912   {
01913     /* Change ADC state */
01914     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01915
01916     /* Level out of window 3 callback */
01917     HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
01918     /* Clear ADC Analog watchdog flag */
01919     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01920   }
01921
01922
01923   /* ========== Check Overrun flag ========== */
01924   if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
01925   {
01926     /* If overrun is set to overwrite previous data (default setting),        */
01927     /* overrun event is not considered as an error.                           */
01928     /* (cf ref manual "Managing conversions without using the DMA and without */
01929     /* overrun ")                                                             */
01930     /* Exception for usage with DMA overrun event always considered as an     */
01931     /* error.                                                                 */
01932
01933     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01934     {
01935       overrun_error = 1;
01936     }
01937     else
01938     {
01939       /* check DMA configuration, depending on multimode set or not,
01940         or whether or not multimode feature is available */
01941       if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET)
01942       {
01943         /* Multimode not set or feature not available or ADC independent */
01944         if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
01945         {
01946           overrun_error = 1;
01947         }
01948       }
01949       else
01950       {
01951         /* Multimode (when feature is available) is enabled,
01952            Common Control Register MDMA bits must be checked. */
01953         if (ADC_MULTIMODE_DMA_ENABLED())
01954         {
01955           overrun_error = 1;
01956         }
01957       }
01958     }
01959
01960     if (overrun_error == 1)
01961     {
01962       /* Change ADC state to error state */
01963       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
01964
01965       /* Set ADC error code to overrun */
01966       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
01967
01968       /* Error callback */
01969       HAL_ADC_ErrorCallback(hadc);
01970     }
01971
01972     /* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since
01973        old data is preserved until OVR is reset */
01974     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01975
01976   }
01977
01978
01979   /* ========== Check Injected context queue overflow flag ========== */
01980   if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
01981   {
01982     /* Change ADC state to overrun state */
01983     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
01984
01985     /* Set ADC error code to Injected context queue overflow */
01986     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
01987
01988     /* Clear the Injected context queue overflow flag */
01989     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
01990
01991     /* Error callback */
01992     HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
01993   }
01994
01995 }
01996
01997 /**
01998   * @brief  Conversion complete callback in non-blocking mode.
01999   * @param  hadc: ADC handle
02000   * @retval None
02001   */
02002 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
02003 {
02004   /* Prevent unused argument(s) compilation warning */
02005   UNUSED(hadc);
02006
02007   /* NOTE : This function should not be modified. When the callback is needed,
02008             function HAL_ADC_ConvCpltCallback must be implemented in the user file.
02009    */
02010 }
02011
02012 /**
02013   * @brief  Conversion DMA half-transfer callback in non-blocking mode.
02014   * @param  hadc: ADC handle
02015   * @retval None
02016   */
02017 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
02018 {
02019   /* Prevent unused argument(s) compilation warning */
02020   UNUSED(hadc);
02021
02022   /* NOTE : This function should not be modified. When the callback is needed,
02023             function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
02024   */
02025 }
02026
02027 /**
02028   * @brief  Analog watchdog 1 callback in non-blocking mode.
02029   * @param  hadc: ADC handle
02030   * @retval None
02031   */
02032 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
02033 {
02034   /* Prevent unused argument(s) compilation warning */
02035   UNUSED(hadc);
02036
02037   /* NOTE : This function should not be modified. When the callback is needed,
02038             function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
02039   */
02040 }
02041
02042 /**
02043   * @brief  ADC error callback in non-blocking mode
02044   *        (ADC conversion with interruption or transfer by DMA).
02045   * @param  hadc: ADC handle
02046   * @retval None
02047   */
02048 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
02049 {
02050   /* Prevent unused argument(s) compilation warning */
02051   UNUSED(hadc);
02052
02053   /* NOTE : This function should not be modified. When the callback is needed,
02054             function HAL_ADC_ErrorCallback must be implemented in the user file.
02055   */
02056 }
02057
02058 /**
02059   * @}
02060   */
02061
02062 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
02063  *  @brief    Peripheral Control functions
02064  *
02065 @verbatim
02066  ===============================================================================
02067              ##### Peripheral Control functions #####
02068  ===============================================================================
02069     [..]  This section provides functions allowing to:
02070       (+) Configure channels on regular group
02071       (+) Configure the analog watchdog
02072
02073 @endverbatim
02074   * @{
02075   */
02076
02077
02078 /**
02079   * @brief  Configure the selected channel to be linked to the regular group.
02080   * @note   In case of usage of internal measurement channels (Vbat / VrefInt /
02081   *         TempSensor), the recommended sampling time is provided by the
02082   *         datasheet.
02083   *         These internal paths can be disabled using function
02084   *         HAL_ADC_DeInit().
02085   * @note   Possibility to update parameters on the fly:
02086   *         HAL_ADC_ConfigChannel() initializes channel into regular group,
02087   *         consecutive calls to this function can be used to reconfigure some
02088   *         parameters of structure "ADC_ChannelConfTypeDef" on the fly, without
02089   *         resetting the ADC.
02090   *         The setting of these parameters is conditioned to ADC state.
02091   *         For parameters constraints, see comments of structure
02092   *         "ADC_ChannelConfTypeDef".
02093   * @param  hadc: ADC handle
02094   * @param  sConfig: Structure ADC channel for regular group.
02095   * @retval HAL status
02096   */
02097 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
02098 {
02099   HAL_StatusTypeDef tmp_status = HAL_OK;
02100
02101   ADC_Common_TypeDef *tmpADC_Common;
02102   uint32_t tmpOffsetShifted;
02103   __IO uint32_t wait_loop_index = 0;
02104
02105   /* Check the parameters */
02106   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02107   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
02108   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
02109   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
02110   assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
02111   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
02112
02113   /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
02114      ignored (considered as reset) */
02115   assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
02116
02117   /* Verification of channel number */
02118   if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
02119   {
02120      assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
02121   }
02122   else
02123   {
02124     assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
02125   }
02126
02127   /* Process locked */
02128   __HAL_LOCK(hadc);
02129
02130
02131   /* Parameters update conditioned to ADC state:                              */
02132   /* Parameters that can be updated when ADC is disabled or enabled without   */
02133   /* conversion on going on regular group:                                    */
02134   /*  - Channel number                                                        */
02135   /*  - Channel rank                                                          */
02136   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
02137   {
02138
02139       /* Regular sequence configuration */
02140       /* Clear the old SQx bits then set the new ones for the selected rank */
02141       /* For Rank 1 to 4 */
02142       if (sConfig->Rank < 5)
02143       {
02144         MODIFY_REG(hadc->Instance->SQR1,
02145                   ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank),
02146                   ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));
02147       }
02148       /* For Rank 5 to 9 */
02149       else if (sConfig->Rank < 10)
02150       {
02151         MODIFY_REG(hadc->Instance->SQR2,
02152                   ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank),
02153                   ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));
02154       }
02155       /* For Rank 10 to 14 */
02156       else if (sConfig->Rank < 15)
02157       {
02158         MODIFY_REG(hadc->Instance->SQR3,
02159                   ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank),
02160                   ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));
02161       }
02162       /* For Rank 15 to 16 */
02163       else
02164       {
02165         MODIFY_REG(hadc->Instance->SQR4,
02166                   ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank),
02167                   ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));
02168       }
02169
02170
02171       /* Parameters update conditioned to ADC state:                              */
02172       /* Parameters that can be updated when ADC is disabled or enabled without   */
02173       /* conversion on going on regular group:                                    */
02174       /*  - Channel sampling time                                                 */
02175       /*  - Channel offset                                                        */
02176       if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02177       {
02178
02179         /* Channel sampling time configuration */
02180         /* Clear the old sample time then set the new one for the selected channel */
02181         /* For channels 10 to 18 */
02182         if (sConfig->Channel >= ADC_CHANNEL_10)
02183         {
02184           ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
02185         }
02186         else /* For channels 0 to 9 */
02187         {
02188           ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
02189         }
02190
02191
02192        /* Configure the offset: offset enable/disable, channel, offset value */
02193
02194        /* Shift the offset with respect to the selected ADC resolution. */
02195        /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
02196        tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
02197
02198        switch (sConfig->OffsetNumber)
02199        {
02200         /* Configure offset register i when applicable:                         */
02201         /* - Enable offset                                                      */
02202         /* - Set channel number                                                 */
02203         /* - Set offset value                                                   */
02204        case ADC_OFFSET_1:
02205           MODIFY_REG(hadc->Instance->OFR1,
02206                   ADC_OFR_FIELDS,
02207                   ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
02208          break;
02209
02210        case ADC_OFFSET_2:
02211          MODIFY_REG(hadc->Instance->OFR2,
02212                   ADC_OFR_FIELDS,
02213                   ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
02214          break;
02215
02216        case ADC_OFFSET_3:
02217          MODIFY_REG(hadc->Instance->OFR3,
02218                   ADC_OFR_FIELDS,
02219                   ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
02220          break;
02221
02222        case ADC_OFFSET_4:
02223          MODIFY_REG(hadc->Instance->OFR4,
02224                   ADC_OFR_FIELDS,
02225                   ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);
02226          break;
02227
02228        /* Case ADC_OFFSET_NONE */
02229        default :
02230        /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
02231           If this is the case, offset OFRx is disabled since
02232           sConfig->OffsetNumber = ADC_OFFSET_NONE. */
02233          if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02234          {
02235            CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
02236          }
02237          if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02238          {
02239            CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
02240          }
02241          if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02242          {
02243            CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
02244          }
02245          if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02246          {
02247            CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
02248          }
02249          break;
02250       }  /*  switch (sConfig->OffsetNumber) */
02251
02252     }  /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
02253
02254
02255
02256     /* Parameters update conditioned to ADC state:                              */
02257     /* Parameters that can be updated only when ADC is disabled:                */
02258     /*  - Single or differential mode                                           */
02259     /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
02260     if (ADC_IS_ENABLE(hadc) == RESET)
02261     {
02262       /* Configuration of differential mode */
02263       if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
02264       {
02265         /* Disable differential mode (default mode: single-ended) */
02266         CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
02267       }
02268       else
02269       {
02270         /* Enable differential mode */
02271         SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
02272
02273         /* Sampling time configuration of channel ADC_IN+1 (negative input)     */
02274         /* Clear the old sample time then set the new one for the selected      */
02275         /* channel.                                                             */
02276         /* Starting from channel 9, SMPR2 register must be configured           */
02277         if (sConfig->Channel >= ADC_CHANNEL_9)
02278         {
02279           ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
02280         }
02281         else /* For channels 0 to 8, SMPR1 must be configured */
02282         {
02283           ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
02284         }
02285       }
02286
02287
02288
02289       /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
02290       /* If internal channel selected, enable dedicated internal buffers and    */
02291       /*  paths.                                                                */
02292       /* Note: these internal measurement paths can be disabled using           */
02293       /* HAL_ADC_DeInit().                                                      */
02294
02295       /* Configuration of common ADC parameters                                 */
02296       tmpADC_Common = ADC_COMMON_REGISTER(hadc);
02297
02298
02299       /* If the requested internal measurement path has already been enabled,   */
02300       /* bypass the configuration processing.                                   */
02301       if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
02302             (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
02303           ( (sConfig->Channel == ADC_CHANNEL_VBAT)       &&
02304             (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
02305           ( (sConfig->Channel == ADC_CHANNEL_VREFINT)    &&
02306             (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
02307          )
02308       {
02309         /* Configuration of common ADC parameters (continuation)                */
02310
02311         /* Software is allowed to change common parameters only when all ADCs   */
02312         /* of the common group are disabled.                                    */
02313         if ((ADC_IS_ENABLE(hadc) == RESET)   &&
02314            (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
02315         {
02316           if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
02317           {
02318             if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
02319             {
02320               SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
02321
02322               /* Delay for temperature sensor stabilization time */
02323               /* Wait loop initialization and execution */
02324               /* Note: Variable divided by 2 to compensate partially          */
02325               /*       CPU processing cycles.                                 */
02326               wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2)));
02327               while(wait_loop_index != 0)
02328               {
02329                 wait_loop_index--;
02330               }
02331             }
02332           }
02333           else if (sConfig->Channel == ADC_CHANNEL_VBAT)
02334           {
02335             if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
02336             {
02337               SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
02338             }
02339           }
02340           else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
02341           {
02342             if (ADC_VREFINT_INSTANCE(hadc))
02343             {
02344               SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
02345             }
02346           }
02347         }
02348         /* If the requested internal measurement path has already been          */
02349         /* enabled and other ADC of the common group are enabled, internal      */
02350         /* measurement paths cannot be enabled.                                 */
02351         else
02352         {
02353           /* Update ADC state machine to error */
02354           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02355
02356           tmp_status = HAL_ERROR;
02357         }
02358       }
02359
02360     } /* if (ADC_IS_ENABLE(hadc) == RESET) */
02361
02362   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */
02363
02364   /* If a conversion is on going on regular group, no update on regular       */
02365   /* channel could be done on neither of the channel configuration structure  */
02366   /* parameters.                                                              */
02367   else
02368   {
02369     /* Update ADC state machine to error */
02370     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02371
02372     tmp_status = HAL_ERROR;
02373   }
02374
02375   /* Process unlocked */
02376   __HAL_UNLOCK(hadc);
02377
02378   /* Return function status */
02379   return tmp_status;
02380 }
02381
02382
02383
02384 /**
02385   * @brief  Configure the analog watchdog.
02386   * @note   Possibility to update parameters on the fly:
02387   *         This function initializes the selected analog watchdog, successive
02388   *         calls to this function can be used to reconfigure some parameters
02389   *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
02390   *         the ADC, e.g. to set several channels to monitor simultaneously.
02391   *         The setting of these parameters is conditioned to ADC state.
02392   *         For parameters constraints, see comments of structure
02393   *         "ADC_AnalogWDGConfTypeDef".
02394   * @param  hadc: ADC handle
02395   * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
02396   * @retval HAL status
02397   */
02398 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
02399 {
02400   HAL_StatusTypeDef tmp_status = HAL_OK;
02401
02402
02403   uint32_t tmpAWDHighThresholdShifted;
02404   uint32_t tmpAWDLowThresholdShifted;
02405
02406   uint32_t tmpADCFlagAWD2orAWD3;
02407   uint32_t tmpADCITAWD2orAWD3;
02408
02409   /* Check the parameters */
02410   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02411   assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
02412   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
02413   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
02414
02415   if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
02416      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
02417      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
02418   {
02419     assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
02420   }
02421
02422
02423   /* Verify if threshold is within the selected ADC resolution */
02424   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
02425   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
02426
02427   /* Process locked */
02428   __HAL_LOCK(hadc);
02429
02430   /* Parameters update conditioned to ADC state:                              */
02431   /* Parameters that can be updated when ADC is disabled or enabled without   */
02432   /* conversion on going on regular and injected groups:                      */
02433   /*  - Analog watchdog channels                                              */
02434   /*  - Analog watchdog thresholds                                            */
02435   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02436   {
02437
02438     /* Analog watchdogs configuration */
02439     if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
02440     {
02441       /* Configuration of analog watchdog:                                    */
02442       /*  - Set the analog watchdog enable mode: regular and/or injected      */
02443       /*    groups, one or overall group of channels.                         */
02444       /*  - Set the Analog watchdog channel (is not used if watchdog          */
02445       /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                         */
02446
02447         MODIFY_REG(hadc->Instance->CFGR,  ADC_CFGR_WD_FIELDS,
02448               AnalogWDGConfig->WatchdogMode | ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );
02449
02450       /* Shift the offset with respect to the selected ADC resolution:         */
02451       /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
02452       /* are set to 0                                                         */
02453       tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
02454       tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
02455
02456       /* Set the high and low thresholds */
02457       MODIFY_REG(hadc->Instance->TR1,  ADC_TR1_HT1 | ADC_TR1_LT1,
02458               ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );
02459
02460       /* Clear the ADC Analog watchdog flag (in case left enabled by          */
02461       /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
02462       /* or HAL_ADC_PollForEvent().                                           */
02463       __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
02464
02465       /* Configure ADC Analog watchdog interrupt */
02466       if(AnalogWDGConfig->ITMode == ENABLE)
02467       {
02468         /* Enable the ADC Analog watchdog interrupt */
02469         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
02470       }
02471       else
02472       {
02473         /* Disable the ADC Analog watchdog interrupt */
02474         __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
02475       }
02476
02477       /* Update state, clear previous result related to AWD1 */
02478       CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
02479     }
02480     /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
02481     else
02482     {
02483     /* Shift the threshold with respect to the selected ADC resolution         */
02484     /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0    */
02485       tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
02486       tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
02487
02488       if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
02489       {
02490         /* Set the Analog watchdog channel or group of channels. This also    */
02491         /* enables the watchdog.                                              */
02492         /* Note: Conditional register reset, because several channels can be */
02493         /*       set by successive calls of this function.                    */
02494         if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
02495         {
02496           SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
02497         }
02498         else
02499         {
02500           CLEAR_BIT(hadc->Instance->AWD2CR,  ADC_AWD2CR_AWD2CH);
02501         }
02502
02503         /* Set the high and low thresholds */
02504         MODIFY_REG(hadc->Instance->TR2,  ADC_TR2_HT2 | ADC_TR2_LT2,
02505               ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );
02506
02507         /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
02508         /* settings.                                                          */
02509         tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
02510         tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
02511
02512         /* Update state, clear previous result related to AWD2 */
02513         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
02514       }
02515       /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
02516       else
02517       {
02518         /* Set the Analog watchdog channel or group of channels. This also    */
02519         /* enables the watchdog.                                              */
02520         /* Note: Conditional register reset, because several channels can be */
02521         /*       set by successive calls of this function.                    */
02522         if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
02523         {
02524           SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
02525         }
02526         else
02527         {
02528           CLEAR_BIT(hadc->Instance->AWD3CR,  ADC_AWD3CR_AWD3CH);
02529         }
02530
02531         /* Set the high and low thresholds */
02532         MODIFY_REG(hadc->Instance->TR3,  ADC_TR3_HT3 | ADC_TR3_LT3,
02533               ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );
02534
02535         /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
02536         /* settings.                                                          */
02537         tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
02538         tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
02539
02540         /* Update state, clear previous result related to AWD3 */
02541         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
02542       }
02543
02544       /* Clear the ADC Analog watchdog flag (in case left enabled by          */
02545       /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
02546       /* or HAL_ADC_PollForEvent().                                           */
02547       __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
02548
02549       /* Configure ADC Analog watchdog interrupt */
02550       if(AnalogWDGConfig->ITMode == ENABLE)
02551       {
02552         __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
02553       }
02554       else
02555       {
02556         __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
02557       }
02558     }
02559
02560   }
02561   /* If a conversion is on going on regular or injected groups, no update     */
02562   /* could be done on neither of the AWD configuration structure parameters.  */
02563   else
02564   {
02565     /* Update ADC state machine to error */
02566     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02567
02568     tmp_status = HAL_ERROR;
02569   }
02570
02571
02572   /* Process unlocked */
02573   __HAL_UNLOCK(hadc);
02574
02575
02576   /* Return function status */
02577   return tmp_status;
02578 }
02579
02580
02581 /**
02582   * @}
02583   */
02584
02585 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
02586  *  @brief   ADC Peripheral State functions
02587  *
02588 @verbatim
02589  ===============================================================================
02590             ##### Peripheral state and errors functions #####
02591  ===============================================================================
02592     [..]
02593     This subsection provides functions to get in run-time the status of the
02594     peripheral.
02595       (+) Check the ADC state
02596       (+) Check the ADC error code
02597
02598 @endverbatim
02599   * @{
02600   */
02601
02602 /**
02603   * @brief  Return the ADC handle state.
02604   * @param  hadc: ADC handle
02605   * @retval HAL state  (uint32_t bit-map)
02606   */
02607 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
02608 {
02609   /* Check the parameters */
02610   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02611
02612   /* Return ADC handle state */
02613   return hadc->State;
02614 }
02615
02616
02617 /**
02618   * @brief  Return the ADC error code.
02619   * @param  hadc: ADC handle
02620   * @retval ADC Error Code (uint32_t bit-map)
02621   */
02622 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
02623 {
02624   /* Check the parameters */
02625   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02626
02627   return hadc->ErrorCode;
02628 }
02629
02630 /**
02631   * @}
02632   */
02633
02634 /**
02635   * @}
02636   */
02637
02638
02639
02640 /** @defgroup ADC_Private_Functions ADC Private Functions
02641   * @{
02642   */
02643
02644 /**
02645   * @brief  Stop ADC conversion.
02646   * @param  hadc: ADC handle
02647   * @param  ConversionGroup: ADC group regular and/or injected.
02648   *          This parameter can be one of the following values:
02649   *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
02650   *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
02651   *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
02652   * @retval HAL status.
02653   */
02654 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
02655 {
02656   uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
02657   uint32_t tickstart = 0;
02658   uint32_t Conversion_Timeout_CPU_cycles = 0;
02659
02660   /* Check the parameters */
02661   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02662   assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
02663
02664   /* Verification if ADC is not already stopped (on regular and injected      */
02665   /* groups) to bypass this function if not needed.                           */
02666   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
02667   {
02668     /* Particular case of continuous auto-injection mode combined with        */
02669     /* auto-delay mode.                                                       */
02670     /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
02671     /* injected group stop ADC_CR_JADSTP).                                    */
02672     /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
02673     /* (see reference manual).                                                */
02674     if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
02675          && (hadc->Init.ContinuousConvMode==ENABLE)
02676          && (hadc->Init.LowPowerAutoWait==ENABLE))
02677     {
02678       /* Use stop of regular group */
02679       ConversionGroup = ADC_REGULAR_GROUP;
02680
02681       /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
02682       while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
02683       {
02684         if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
02685         {
02686           /* Update ADC state machine to error */
02687           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02688
02689           /* Set ADC error code to ADC IP internal error */
02690           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02691
02692           return HAL_ERROR;
02693         }
02694         Conversion_Timeout_CPU_cycles ++;
02695       }
02696
02697       /* Clear JEOS */
02698       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
02699     }
02700
02701     /* Stop potential conversion on going on regular group */
02702     if (ConversionGroup != ADC_INJECTED_GROUP)
02703     {
02704       /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
02705       if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
02706           HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)     )
02707       {
02708         /* Stop conversions on regular group */
02709         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
02710       }
02711     }
02712
02713     /* Stop potential conversion on going on injected group */
02714     if (ConversionGroup != ADC_REGULAR_GROUP)
02715     {
02716       /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
02717       if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
02718           HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)      )
02719       {
02720         /* Stop conversions on injected group */
02721         SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP);
02722       }
02723     }
02724
02725     /* Selection of start and stop bits with respect to the regular or injected group */
02726     switch(ConversionGroup)
02727     {
02728     case ADC_REGULAR_INJECTED_GROUP:
02729         tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
02730         break;
02731     case ADC_INJECTED_GROUP:
02732         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
02733         break;
02734     /* Case ADC_REGULAR_GROUP only*/
02735     default:
02736         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
02737         break;
02738     }
02739
02740     /* Wait for conversion effectively stopped */
02741
02742
02743     tickstart = HAL_GetTick();
02744
02745     while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
02746     {
02747       if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
02748       {
02749         /* Update ADC state machine to error */
02750         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02751
02752         /* Set ADC error code to ADC IP internal error */
02753         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02754
02755         return HAL_ERROR;
02756       }
02757     }
02758
02759   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */
02760
02761   /* Return HAL status */
02762   return HAL_OK;
02763 }
02764
02765
02766
02767 /**
02768   * @brief  Enable the selected ADC.
02769   * @note   Prerequisite condition to use this function: ADC must be disabled
02770   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
02771   * @param  hadc: ADC handle
02772   * @retval HAL status.
02773   */
02774 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
02775 {
02776   uint32_t tickstart = 0;
02777
02778   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
02779   /* enabling phase not yet completed: flag ADC ready not set yet).           */
02780   /* Timeout implemented not to be stuck if ADC cannot be enabled (possible   */
02781   /* causes: ADC clock not running, ...).                                     */
02782   if (ADC_IS_ENABLE(hadc) == RESET)
02783   {
02784     /* Check if conditions to enable the ADC are fulfilled */
02785     if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
02786     {
02787       /* Update ADC state machine to error */
02788       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02789
02790       /* Set ADC error code to ADC IP internal error */
02791       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02792
02793       return HAL_ERROR;
02794     }
02795
02796     /* Enable the ADC peripheral */
02797     ADC_ENABLE(hadc);
02798
02799
02800     /* Wait for ADC effectively enabled */
02801     tickstart = HAL_GetTick();
02802
02803     while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
02804     {
02805       /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
02806           has been cleared (after a calibration), ADEN bit is reset by the
02807           calibration logic.
02808                             The workaround is to continue setting ADEN until ADRDY is becomes 1.
02809           Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
02810           4 ADC clock cycle duration */
02811       ADC_ENABLE(hadc);
02812
02813       if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
02814       {
02815         /* Update ADC state machine to error */
02816         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02817
02818         /* Set ADC error code to ADC IP internal error */
02819        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02820
02821         return HAL_ERROR;
02822       }
02823     }
02824   }
02825
02826   /* Return HAL status */
02827   return HAL_OK;
02828 }
02829
02830 /**
02831   * @brief  Disable the selected ADC.
02832   * @note   Prerequisite condition to use this function: ADC conversions must be
02833   *         stopped.
02834   * @param  hadc: ADC handle
02835   * @retval HAL status.
02836   */
02837 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
02838 {
02839   uint32_t tickstart = 0;
02840
02841   /* Verification if ADC is not already disabled:                             */
02842   /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
02843   /* disabled.                                                                */
02844   if (ADC_IS_ENABLE(hadc) != RESET )
02845   {
02846     /* Check if conditions to disable the ADC are fulfilled */
02847     if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
02848     {
02849       /* Disable the ADC peripheral */
02850       ADC_DISABLE(hadc);
02851     }
02852     else
02853     {
02854       /* Update ADC state machine to error */
02855       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02856
02857       /* Set ADC error code to ADC IP internal error */
02858       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02859
02860       return HAL_ERROR;
02861     }
02862
02863     /* Wait for ADC effectively disabled */
02864     tickstart = HAL_GetTick();
02865
02866     while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
02867     {
02868       if((HAL_GetTick()-tickstart) > ADC_DISABLE_TIMEOUT)
02869       {
02870         /* Update ADC state machine to error */
02871         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02872
02873         /* Set ADC error code to ADC IP internal error */
02874         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02875
02876         return HAL_ERROR;
02877       }
02878     }
02879   }
02880
02881   /* Return HAL status */
02882   return HAL_OK;
02883 }
02884
02885
02886 /**
02887   * @brief  DMA transfer complete callback.
02888   * @param  hdma: pointer to DMA handle.
02889   * @retval None
02890   */
02891 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
02892 {
02893   /* Retrieve ADC handle corresponding to current DMA handle */
02894   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02895
02896   /* Update state machine on conversion status if not in error state */
02897   if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL|HAL_ADC_STATE_ERROR_DMA)))
02898   {
02899     /* Update ADC state machine */
02900     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
02901     /* Is it the end of the regular sequence ? */
02902     if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS))
02903     {
02904       /* Are conversions software-triggered ? */
02905       if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
02906       {
02907         /* Is CONT bit set ? */
02908         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET)
02909         {
02910           /* CONT bit is not set, no more conversions expected */
02911           CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
02912           if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
02913           {
02914             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02915           }
02916         }
02917       }
02918     }
02919     else
02920     {
02921       /* DMA End of Transfer interrupt was triggered but conversions sequence
02922          is not over. If DMACFG is set to 0, conversions are stopped. */
02923       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET)
02924       {
02925         /* DMACFG bit is not set, conversions are stopped. */
02926         CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
02927         if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
02928         {
02929           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02930         }
02931       }
02932     }
02933
02934     /* Conversion complete callback */
02935     HAL_ADC_ConvCpltCallback(hadc);
02936   }
02937   else /* DMA or internal error occurred (or both) */
02938   {
02939     /* In case of internal error, */
02940     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
02941     {
02942       /* call Error Callback function */
02943       HAL_ADC_ErrorCallback(hadc);
02944     }
02945
02946   }
02947
02948
02949 }
02950
02951 /**
02952   * @brief  DMA half transfer complete callback.
02953   * @param  hdma: pointer to DMA handle.
02954   * @retval None
02955   */
02956 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
02957 {
02958   /* Retrieve ADC handle corresponding to current DMA handle */
02959   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02960
02961   /* Half conversion callback */
02962   HAL_ADC_ConvHalfCpltCallback(hadc);
02963 }
02964
02965 /**
02966   * @brief  DMA error callback.
02967   * @param  hdma: pointer to DMA handle.
02968   * @retval None
02969   */
02970 void ADC_DMAError(DMA_HandleTypeDef *hdma)
02971 {
02972   /* Retrieve ADC handle corresponding to current DMA handle */
02973   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02974
02975   /* Change ADC state */
02976   SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
02977
02978   /* Set ADC error code to DMA error */
02979   SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
02980
02981   /* Error callback */
02982   HAL_ADC_ErrorCallback(hadc);
02983 }
02984
02985
02986 /**
02987   * @}
02988   */
02989
02990
02991 #endif /* HAL_ADC_MODULE_ENABLED */
02992 /**
02993   * @}
02994   */
02995
02996 /**
02997   * @}
02998   */
02999
03000 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_adc.h Source File

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stm32l4xx_hal_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of ADC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_ADC_H
00040 #define __STM32L4xx_ADC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ADC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup ADC_Exported_Types ADC Exported Types
00059   * @{
00060   */
00061
00062
00063 /**
00064   * @brief  ADC Regular Conversion Oversampling structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
00069                                                This parameter can be a value of @ref ADCEx_Oversampling_Ratio */
00070
00071   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00072                                                This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
00073
00074   uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
00075                                                This parameter can be a value of @ref ADCEx_Triggered_Oversampling_Mode */
00076
00077   uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.
00078                                                The oversampling is either temporary stopped or reset upon an injected
00079                                                sequence interruption.
00080                                                If oversampling is enabled on both regular and injected groups, this parameter
00081                                                is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
00082                                                (the oversampling buffer is zeroed during injection sequence).
00083                                                This parameter can be a value of @ref ADCEx_Regular_Oversampling_Mode */
00084
00085 }ADC_OversamplingTypeDef;
00086
00087
00088
00089
00090 /** @defgroup ADC_States ADC States
00091   * @{
00092   */
00093
00094 /**
00095   * @brief  HAL ADC state machine: ADC State bitfield definition
00096   */
00097 /* States of ADC global scope */
00098 #define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
00099 #define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
00100 #define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy because of an internal process (initialization, calibration) */
00101 #define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
00102
00103 /* States of ADC errors */
00104 #define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
00105 #define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */
00106 #define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */
00107
00108 /* States of ADC regular group */
00109 #define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A regular conversion is ongoing or can occur (either by continuous mode,
00110                                                                        external trigger, low power auto power-on, multimode ADC master control
00111                                                                        when multimode feature available) */
00112 #define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Regular conversion data available */
00113 #define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Overrun occurrence  */
00114 #define HAL_ADC_STATE_REG_EOSMP         ((uint32_t)0x00000800)    /*!< End Of Sampling flag raised  */
00115
00116 /* States of ADC injected group */
00117 #define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< An injected conversion is ongoing or can occur (either by auto-injection mode,
00118                                                                        external trigger, low power auto power-on, multimode ADC master control
00119                                                                        when multimode feature available) */
00120 #define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Injected conversion data available */
00121 #define HAL_ADC_STATE_INJ_JQOVF         ((uint32_t)0x00004000)    /*!< Injected queue overflow occurrence */
00122
00123 /* States of ADC analog watchdogs */
00124 #define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of Analog Watchdog 1 */
00125 #define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000)    /*!< Out-of-window occurrence of Analog Watchdog 2 */
00126 #define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000)    /*!< Out-of-window occurrence of Analog Watchdog 3 */
00127
00128 /* States of ADC multi-mode when feature available */
00129 #define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000)    /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
00130
00131 /**
00132   * @}
00133   */
00134
00135 /**
00136   * @brief  ADC Injection Configuration
00137   */
00138 typedef struct
00139 {
00140   uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each
00141                                               HAL_ADCEx_InjectedConfigChannel() call to finally initialize
00142                                               JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
00143
00144   uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
00145 }ADC_InjectionConfigTypeDef;
00146
00147
00148
00149
00150 /**
00151   * @brief  Structure definition of ADC channel for regular group
00152   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned by ADC state.
00153   *         ADC state can be either:
00154   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
00155   *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
00156   *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
00157   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00158   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter
00159   *        (which fulfills the ADC state condition) on the fly).
00160   */
00161 typedef struct
00162 {
00163   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
00164                                         This parameter can be a value of @ref ADC_channels
00165                                         Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability. */
00166   uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
00167                                         This parameter can be a value of @ref ADCEx_regular_rank
00168                                         Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
00169                                         the new channel setting (or parameter number of conversions adjusted) */
00170   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00171                                         Unit: ADC clock cycles
00172                                         Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
00173                                         8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00174                                         This parameter can be a value of @ref ADC_sampling_times
00175                                         Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00176                                                  It overwrites the last setting.
00177                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00178                                               sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time setting)
00179                                               Refer to device DataSheet for timings values. */
00180   uint32_t SingleDiff;             /*!< Selection of single-ended or differential input.
00181                                         In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
00182                                                               Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
00183                                         This parameter must be a value of @ref ADCEx_SingleDifferential
00184                                         Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00185                                                  It overwrites the last setting.
00186                                         Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
00187                                         Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
00188                                         Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00189                                               If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case
00190                                         of another parameter update on the fly) */
00191   uint32_t OffsetNumber;           /*!< Selects the offset number
00192                                         This parameter can be a value of @ref ADCEx_OffsetNumber
00193                                         Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
00194   uint32_t Offset;                 /*!< Defines the offset to be subtracted from the raw converted data.
00195                                         Offset value must be a positive number.
00196                                         Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
00197                                         0x3FF, 0xFF or 0x3F respectively.
00198                                         Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
00199                                               without continuous mode or external trigger that could launch a conversion). */
00200 }ADC_ChannelConfTypeDef;
00201
00202
00203 /**
00204   * @brief  Structure definition of ADC analog watchdog
00205   * @note   The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned by ADC state.
00206   *         ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.
00207   */
00208 typedef struct
00209 {
00210   uint32_t WatchdogNumber;    /*!< Selects which ADC analog watchdog is applied to the selected channel.
00211                                    For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
00212                                    For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
00213                                    This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
00214   uint32_t WatchdogMode;      /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group.
00215                                    For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset
00216                                    channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored.
00217                                    This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
00218   uint32_t Channel;           /*!< Selects which ADC channel to monitor by analog watchdog.
00219                                    For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
00220                                    For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel.
00221                                    Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE').
00222                                    This parameter can be a value of @ref ADC_channels. */
00223   uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
00224                                    This parameter can be set to ENABLE or DISABLE */
00225   uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
00226                                    Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
00227                                    0x3FF, 0xFF or 0x3F respectively.
00228                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
00229                                          the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
00230   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
00231                                    Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
00232                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
00233                                          the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
00234 }ADC_AnalogWDGConfTypeDef;
00235
00236
00237 /**
00238   * @}
00239   */
00240
00241 /* Exported constants --------------------------------------------------------*/
00242
00243 /** @defgroup ADC_Exported_Constants ADC Exported Constants
00244   * @{
00245   */
00246
00247 /** @defgroup ADC_Error_Code ADC Error Code
00248   * @{
00249   */
00250 #define HAL_ADC_ERROR_NONE         ((uint32_t)0x00)   /*!< No error                                 */
00251 #define HAL_ADC_ERROR_INTERNAL     ((uint32_t)0x01)   /*!< ADC IP internal error: problem of
00252                                                           clocking, enable/disable, erroneous state */
00253 #define HAL_ADC_ERROR_OVR          ((uint32_t)0x02)   /*!< Overrun error                            */
00254 #define HAL_ADC_ERROR_DMA          ((uint32_t)0x04)   /*!< DMA transfer error                       */
00255 #define HAL_ADC_ERROR_JQOVF        ((uint32_t)0x08)   /*!< Injected context queue overflow error    */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
00261   * @{
00262   */
00263 #define ADC_CLOCK_SYNC_PCLK_DIV1      ((uint32_t)ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided  */
00264 #define ADC_CLOCK_SYNC_PCLK_DIV2      ((uint32_t)ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
00265 #define ADC_CLOCK_SYNC_PCLK_DIV4      ((uint32_t)ADC_CCR_CKMODE)   /*!< ADC synchronous clock derived from AHB clock divided by 4 */
00266
00267 #define ADC_CLOCKPRESCALER_PCLK_DIV1   ADC_CLOCK_SYNC_PCLK_DIV1    /*!< Obsolete naming, kept for compatibility with some other devices */
00268 #define ADC_CLOCKPRESCALER_PCLK_DIV2   ADC_CLOCK_SYNC_PCLK_DIV2    /*!< Obsolete naming, kept for compatibility with some other devices */
00269 #define ADC_CLOCKPRESCALER_PCLK_DIV4   ADC_CLOCK_SYNC_PCLK_DIV4    /*!< Obsolete naming, kept for compatibility with some other devices */
00270
00271 #define ADC_CLOCK_ASYNC_DIV1       ((uint32_t)0x00000000)                                        /*!< ADC asynchronous clock not divided    */
00272 #define ADC_CLOCK_ASYNC_DIV2       ((uint32_t)ADC_CCR_PRESC_0)                                   /*!< ADC asynchronous clock divided by 2   */
00273 #define ADC_CLOCK_ASYNC_DIV4       ((uint32_t)ADC_CCR_PRESC_1)                                   /*!< ADC asynchronous clock divided by 4   */
00274 #define ADC_CLOCK_ASYNC_DIV6       ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 6   */
00275 #define ADC_CLOCK_ASYNC_DIV8       ((uint32_t)(ADC_CCR_PRESC_2))                                 /*!< ADC asynchronous clock divided by 8   */
00276 #define ADC_CLOCK_ASYNC_DIV10      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 10  */
00277 #define ADC_CLOCK_ASYNC_DIV12      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1))                 /*!< ADC asynchronous clock divided by 12  */
00278 #define ADC_CLOCK_ASYNC_DIV16      ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 16  */
00279 #define ADC_CLOCK_ASYNC_DIV32      ((uint32_t)(ADC_CCR_PRESC_3))                                 /*!< ADC asynchronous clock divided by 32  */
00280 #define ADC_CLOCK_ASYNC_DIV64      ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0))                 /*!< ADC asynchronous clock divided by 64  */
00281 #define ADC_CLOCK_ASYNC_DIV128     ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1))                 /*!< ADC asynchronous clock divided by 128 */
00282 #define ADC_CLOCK_ASYNC_DIV256     ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 256 */
00283 /**
00284   * @}
00285   */
00286
00287
00288 /** @defgroup ADC_Resolution ADC Resolution
00289   * @{
00290   */
00291 #define ADC_RESOLUTION_12B      ((uint32_t)0x00000000)          /*!< ADC 12-bit resolution */
00292 #define ADC_RESOLUTION_10B      ((uint32_t)ADC_CFGR_RES_0)      /*!< ADC 10-bit resolution */
00293 #define ADC_RESOLUTION_8B       ((uint32_t)ADC_CFGR_RES_1)      /*!< ADC 8-bit resolution  */
00294 #define ADC_RESOLUTION_6B       ((uint32_t)ADC_CFGR_RES)        /*!< ADC 6-bit resolution  */
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup ADC_Data_align ADC Data Alignment
00300   * @{
00301   */
00302 #define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)         /*!< Data right alignment */
00303 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CFGR_ALIGN)     /*!< Data left alignment  */
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup ADC_Scan_mode ADC Scan Mode
00309   * @{
00310   */
00311 #define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)        /*!< Scan mode disabled */
00312 #define ADC_SCAN_ENABLE          ((uint32_t)0x00000001)        /*!< Scan mode enabled  */
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
00318   * @{
00319   */
00320 #define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)        /*!< Regular conversions hardware trigger detection disabled                             */
00321 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CFGR_EXTEN_0)  /*!< Regular conversions hardware trigger detection on the rising edge                   */
00322 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CFGR_EXTEN_1)  /*!< Regular conversions hardware trigger detection on the falling edge                  */
00323 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CFGR_EXTEN)    /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup ADC_Regular_External_Trigger_Source ADC External Trigger Source for Regular Group
00329   * @{
00330   */
00331
00332 /* External triggers of ADC regular group */
00333 #define ADC_EXTERNALTRIG_T1_CC1           ((uint32_t)0x00000000)                                                  /*!< Event 0 triggers regular group conversion start  */
00334 #define ADC_EXTERNALTRIG_T1_CC2           ((uint32_t)ADC_CFGR_EXTSEL_0)                                           /*!< Event 1 triggers regular group conversion start  */
00335 #define ADC_EXTERNALTRIG_T1_CC3           ((uint32_t)ADC_CFGR_EXTSEL_1)                                           /*!< Event 2 triggers regular group conversion start  */
00336 #define ADC_EXTERNALTRIG_T2_CC2           ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))                     /*!< Event 3 triggers regular group conversion start  */
00337 #define ADC_EXTERNALTRIG_T3_TRGO          ((uint32_t)ADC_CFGR_EXTSEL_2)                                           /*!< Event 4 triggers regular group conversion start  */
00338 #define ADC_EXTERNALTRIG_T4_CC4           ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))                     /*!< Event 5 triggers regular group conversion start  */
00339 #define ADC_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))                     /*!< Event 6 triggers regular group conversion start  */
00340 #define ADC_EXTERNALTRIG_T8_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 7 triggers regular group conversion start  */
00341 #define ADC_EXTERNALTRIG_T8_TRGO2         ((uint32_t) ADC_CFGR_EXTSEL_3)                                          /*!< Event 8 triggers regular group conversion start  */
00342 #define ADC_EXTERNALTRIG_T1_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))                     /*!< Event 9 triggers regular group conversion start  */
00343 #define ADC_EXTERNALTRIG_T1_TRGO2         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))                     /*!< Event 10 triggers regular group conversion start */
00344 #define ADC_EXTERNALTRIG_T2_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 11 triggers regular group conversion start */
00345 #define ADC_EXTERNALTRIG_T4_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))                     /*!< Event 12 triggers regular group conversion start */
00346 #define ADC_EXTERNALTRIG_T6_TRGO          ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 13 triggers regular group conversion start */
00347 #define ADC_EXTERNALTRIG_T15_TRGO         ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 14 triggers regular group conversion start */
00348 #define ADC_EXTERNALTRIG_T3_CC4           ((uint32_t)ADC_CFGR_EXTSEL)                                             /*!< Event 15 triggers regular group conversion start */
00349
00350 #define ADC_SOFTWARE_START                ((uint32_t)0x00000001)                                                  /*!< Software triggers regular group conversion start */
00351 /**
00352   * @}
00353   */
00354
00355
00356 /** @defgroup ADC_EOCSelection ADC End of Regular Sequence/Conversion
00357   * @{
00358   */
00359 #define ADC_EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)                 /*!< End of conversion flag  */
00360 #define ADC_EOC_SEQ_CONV            ((uint32_t) ADC_ISR_EOS)                 /*!< End of sequence flag    */
00361 #define ADC_EOC_SINGLE_SEQ_CONV     ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS))  /*!< Reserved for future use */
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup ADC_Overrun ADC overrun
00367   * @{
00368   */
00369 #define ADC_OVR_DATA_PRESERVED             ((uint32_t)0x00000000)           /*!< Data preserved in case of overrun   */
00370 #define ADC_OVR_DATA_OVERWRITTEN           ((uint32_t)ADC_CFGR_OVRMOD)      /*!< Data overwritten in case of overrun */
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup ADC_channels ADC Channels
00376   * @{
00377   */
00378 #define ADC_CHANNEL_0           ((uint32_t)(0x00000000))                                                            /*!< ADC channel 0  */
00379 #define ADC_CHANNEL_1           ((uint32_t)(ADC_SQR3_SQ10_0))                                                       /*!< ADC channel 1  */
00380 #define ADC_CHANNEL_2           ((uint32_t)(ADC_SQR3_SQ10_1))                                                       /*!< ADC channel 2  */
00381 #define ADC_CHANNEL_3           ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 3  */
00382 #define ADC_CHANNEL_4           ((uint32_t)(ADC_SQR3_SQ10_2))                                                       /*!< ADC channel 4  */
00383 #define ADC_CHANNEL_5           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 5  */
00384 #define ADC_CHANNEL_6           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))                                     /*!< ADC channel 6  */
00385 #define ADC_CHANNEL_7           ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))                   /*!< ADC channel 7  */
00386 #define ADC_CHANNEL_8           ((uint32_t)(ADC_SQR3_SQ10_3))                                                       /*!< ADC channel 8  */
00387 #define ADC_CHANNEL_9           ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 9  */
00388 #define ADC_CHANNEL_10          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))                                     /*!< ADC channel 10 */
00389 #define ADC_CHANNEL_11          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))                   /*!< ADC channel 11 */
00390 #define ADC_CHANNEL_12          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))                                     /*!< ADC channel 12 */
00391 #define ADC_CHANNEL_13          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))                   /*!< ADC channel 13 */
00392 #define ADC_CHANNEL_14          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))                   /*!< ADC channel 14 */
00393 #define ADC_CHANNEL_15          ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 15 */
00394 #define ADC_CHANNEL_16          ((uint32_t)(ADC_SQR3_SQ10_4))                                                       /*!< ADC channel 16 */
00395 #define ADC_CHANNEL_17          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))                                     /*!< ADC channel 17 */
00396 #define ADC_CHANNEL_18          ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))                                     /*!< ADC channel 18 */
00397
00398 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on all ADC's
00399          (information present in Reference Manual) */
00400 #define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_17                                                                      /*!< ADC temperature sensor channel */
00401 #define ADC_CHANNEL_VBAT        ADC_CHANNEL_18                                                                      /*!< ADC Vbat channel               */
00402 #define ADC_CHANNEL_VREFINT     ADC_CHANNEL_0                                                                       /*!< ADC Vrefint channel            */
00403 /**
00404   * @}
00405   */
00406
00407
00408
00409 /**
00410   * @}
00411   */
00412
00413 /* Private macros ------------------------------------------------------------*/
00414
00415 /** @defgroup ADC_Private_Macro ADC Private Macros
00416   * @{
00417   */
00418
00419 /**
00420   * @brief Test if conversion trigger of regular group is software start
00421   *        or external trigger.
00422   * @param __HANDLE__: ADC handle.
00423   * @retval SET (software start) or RESET (external trigger)
00424   */
00425 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                        \
00426        (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
00427
00428 /**
00429   * @brief Return resolution bits in CFGR register RES[1:0] field.
00430   * @param __HANDLE__: ADC handle.
00431   * @retval 2-bit field RES of CFGR register.
00432   */
00433 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
00434
00435 /**
00436   * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
00437   * @param __HANDLE__: ADC handle.
00438   * @retval None
00439   */
00440 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
00441
00442 /**
00443   * @brief Verification of ADC state: enabled or disabled.
00444   * @param __HANDLE__: ADC handle.
00445   * @retval SET (ADC enabled) or RESET (ADC disabled)
00446   */
00447 #define ADC_IS_ENABLE(__HANDLE__)                                                    \
00448        (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
00449           ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
00450         ) ? SET : RESET)
00451
00452
00453 /**
00454   * @brief Check if conversion is on going on regular group.
00455   * @param __HANDLE__: ADC handle.
00456   * @retval SET (conversion is on going) or RESET (no conversion is on going)
00457   */
00458 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                    \
00459        (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET             \
00460         ) ? RESET : SET)
00461
00462
00463 /**
00464   * @brief Simultaneously clear and set specific bits of the handle State.
00465   * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
00466   *        the first parameter is the ADC handle State, the second parameter is the
00467   *        bit field to clear, the third and last parameter is the bit field to set.
00468   * @retval None
00469   */
00470 #define ADC_STATE_CLR_SET MODIFY_REG
00471
00472 /**
00473   * @brief Verify that a given value is aligned with the ADC resolution range.
00474   * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits).
00475   * @param __ADC_VALUE__: value checked against the resolution.
00476   * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
00477   */
00478 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)                                         \
00479    ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
00480     (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
00481     (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
00482     (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F)))   )
00483
00484
00485 /**
00486   * @brief Verify the length of the scheduled regular conversions group.
00487   * @param __LENGTH__: number of programmed conversions.
00488   * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
00489   */
00490 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
00491
00492
00493 /**
00494   * @brief Verify the number of scheduled regular conversions in discontinuous mode.
00495   * @param NUMBER: number of scheduled regular conversions in discontinuous mode.
00496   * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)
00497   */
00498 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
00499
00500
00501 /**
00502   * @brief Verify the ADC clock setting.
00503   * @param __ADC_CLOCK__: programmed ADC clock.
00504   * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
00505   */
00506 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
00507                                               ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
00508                                               ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
00509                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
00510                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
00511                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
00512                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
00513                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
00514                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
00515                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
00516                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
00517                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
00518                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
00519                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
00520                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
00521
00522
00523 /**
00524   * @brief Verify the ADC resolution setting.
00525   * @param __RESOLUTION__: programmed ADC resolution.
00526   * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
00527   */
00528 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
00529                                            ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
00530                                            ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
00531                                            ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )
00532
00533 /**
00534   * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
00535   * @param __RESOLUTION__: programmed ADC resolution when limited to 6 or 8 bits.
00536   * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
00537   */
00538 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
00539                                                     ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )
00540
00541 /**
00542   * @brief Verify the ADC converted data alignment.
00543   * @param __ALIGN__: programmed ADC converted data alignment.
00544   * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
00545   */
00546 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
00547                                       ((__ALIGN__) == ADC_DATAALIGN_LEFT)    )
00548
00549
00550 /**
00551   * @brief Verify the ADC scan mode.
00552   * @param __SCAN_MODE__: programmed ADC scan mode.
00553   * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
00554   */
00555 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
00556                                          ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )
00557
00558 /**
00559   * @brief Verify the ADC edge trigger setting for regular group.
00560   * @param __EDGE__: programmed ADC edge trigger setting.
00561   * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
00562   */
00563 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
00564                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
00565                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
00566                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
00567
00568
00569
00570 /**
00571   * @brief Verify the ADC regular conversions external trigger.
00572   * @param __REGTRIG__: programmed ADC regular conversions external trigger.
00573   * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
00574   */
00575 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)   || \
00576                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)   || \
00577                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)   || \
00578                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)   || \
00579                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)  || \
00580                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)   || \
00581                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
00582                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)  || \
00583                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
00584                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)  || \
00585                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
00586                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)  || \
00587                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)  || \
00588                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)  || \
00589                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
00590                                      ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)   || \
00591                                                                                  \
00592                                      ((__REGTRIG__) == ADC_SOFTWARE_START)           )
00593
00594
00595
00596 /**
00597   * @brief Verify the ADC regular conversions check for converted data availability.
00598   * @param __EOC_SELECTION__: converted data availability check.
00599   * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
00600   */
00601 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
00602                                                  ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)       || \
00603                                                  ((__EOC_SELECTION__) == ADC_EOC_SINGLE_SEQ_CONV)  )
00604
00605 /**
00606   * @brief Verify the ADC regular conversions overrun handling.
00607   * @param __OVR__: ADC regular conversions overrun handling.
00608   * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
00609   */
00610 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
00611                                  ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )
00612
00613 /**
00614   * @brief Verify the ADC conversions sampling time.
00615   * @param __TIME__: ADC conversions sampling time.
00616   * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
00617   */
00618 #if defined (ADC_SMPR1_SMPPLUS)
00619 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
00620                                       ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5)   || \
00621                                       ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
00622                                       ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
00623                                       ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
00624                                       ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
00625                                       ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
00626                                       ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
00627                                       ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )
00628 #else
00629 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
00630                                       ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
00631                                       ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
00632                                       ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
00633                                       ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
00634                                       ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
00635                                       ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
00636                                       ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )
00637 #endif
00638 /**
00639   * @}
00640   */
00641
00642
00643 /* Private constants ---------------------------------------------------------*/
00644
00645 /** @defgroup ADC_Private_Constants ADC Private Constants
00646   * @{
00647   */
00648
00649 /* Fixed timeout values for ADC conversion (including sampling time)        */
00650 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111        */
00651 /* Maximum conversion time is 12.5 + Maximum sampling time                  */
00652 /*                       or 12.5  + 640.5 = 653 ADC clock cycles            */
00653 /* Minimum ADC Clock frequency is 0.14 MHz                                  */
00654 /* Maximum conversion time is                                               */
00655 /*              653 / 0.14 MHz = 4.66 ms                                    */
00656 #define ADC_STOP_CONVERSION_TIMEOUT     ((uint32_t) 5)      /*!< ADC stop time-out value */
00657
00658 /* Delay for temperature sensor stabilization time.                         */
00659 /* Maximum delay is 120us (refer device datasheet, parameter tSTART).         */
00660 /* Unit: us                                                                   */
00661 #define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 120)
00662
00663 /**
00664   * @}
00665   */
00666
00667 /* Exported macros -----------------------------------------------------------*/
00668
00669 /** @defgroup ADC_Exported_Macro ADC Exported Macros
00670   * @{
00671   */
00672
00673 /** @brief  Reset ADC handle state.
00674   * @param  __HANDLE__: ADC handle.
00675   * @retval None
00676   */
00677 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
00678
00679
00680 /** @brief  Check whether the specified ADC interrupt source is enabled or not.
00681   * @param __HANDLE__: ADC handle.
00682   * @param __INTERRUPT__: ADC interrupt source to check
00683   *          This parameter can be one of the following values:
00684   *            @arg @ref ADC_IT_RDY,    ADC Ready (ADRDY) interrupt source
00685   *            @arg @ref ADC_IT_EOSMP,  ADC End of Sampling interrupt source
00686   *            @arg @ref ADC_IT_EOC,    ADC End of Regular Conversion interrupt source
00687   *            @arg @ref ADC_IT_EOS,    ADC End of Regular sequence of Conversions interrupt source
00688   *            @arg @ref ADC_IT_OVR,    ADC overrun interrupt source
00689   *            @arg @ref ADC_IT_JEOC,   ADC End of Injected Conversion interrupt source
00690   *            @arg @ref ADC_IT_JEOS,   ADC End of Injected sequence of Conversions interrupt source
00691   *            @arg @ref ADC_IT_AWD1,   ADC Analog watchdog 1 interrupt source (main analog watchdog)
00692   *            @arg @ref ADC_IT_AWD2,   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
00693   *            @arg @ref ADC_IT_AWD3,   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
00694   *            @arg @ref ADC_IT_JQOVF,  ADC Injected Context Queue Overflow interrupt source.
00695   * @retval State of interruption (SET or RESET)
00696   */
00697 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
00698     (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)      \
00699      )? SET : RESET                                                            \
00700     )
00701
00702 /**
00703   * @brief Enable an ADC interrupt.
00704   * @param __HANDLE__: ADC handle.
00705   * @param __INTERRUPT__: ADC Interrupt to enable
00706    *          This parameter can be one of the following values:
00707   *            @arg @ref ADC_IT_RDY,    ADC Ready (ADRDY) interrupt source
00708   *            @arg @ref ADC_IT_EOSMP,  ADC End of Sampling interrupt source
00709   *            @arg @ref ADC_IT_EOC,    ADC End of Regular Conversion interrupt source
00710   *            @arg @ref ADC_IT_EOS,    ADC End of Regular sequence of Conversions interrupt source
00711   *            @arg @ref ADC_IT_OVR,    ADC overrun interrupt source
00712   *            @arg @ref ADC_IT_JEOC,   ADC End of Injected Conversion interrupt source
00713   *            @arg @ref ADC_IT_JEOS,   ADC End of Injected sequence of Conversions interrupt source
00714   *            @arg @ref ADC_IT_AWD1,   ADC Analog watchdog 1 interrupt source (main analog watchdog)
00715   *            @arg @ref ADC_IT_AWD2,   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
00716   *            @arg @ref ADC_IT_AWD3,  ADC Analog watchdog 3 interrupt source (additional analog watchdog)
00717   *            @arg @ref ADC_IT_JQOVF,  ADC Injected Context Queue Overflow interrupt source.
00718   * @retval None
00719   */
00720 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
00721
00722 /**
00723   * @brief Disable an ADC interrupt.
00724   * @param __HANDLE__: ADC handle.
00725   * @param __INTERRUPT__: ADC Interrupt to disable
00726   *            @arg @ref ADC_IT_RDY,    ADC Ready (ADRDY) interrupt source
00727   *            @arg @ref ADC_IT_EOSMP,  ADC End of Sampling interrupt source
00728   *            @arg @ref ADC_IT_EOC,    ADC End of Regular Conversion interrupt source
00729   *            @arg @ref ADC_IT_EOS,    ADC End of Regular sequence of Conversions interrupt source
00730   *            @arg @ref ADC_IT_OVR,    ADC overrun interrupt source
00731   *            @arg @ref ADC_IT_JEOC,   ADC End of Injected Conversion interrupt source
00732   *            @arg @ref ADC_IT_JEOS,   ADC End of Injected sequence of Conversions interrupt source
00733   *            @arg @ref ADC_IT_AWD1,   ADC Analog watchdog 1 interrupt source (main analog watchdog)
00734   *            @arg @ref ADC_IT_AWD2,   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
00735   *            @arg @ref ADC_IT_AWD3,   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
00736   *            @arg @ref ADC_IT_JQOVF,  ADC Injected Context Queue Overflow interrupt source.
00737   * @retval None
00738   */
00739 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
00740
00741 /**
00742   * @brief Check whether the specified ADC flag is set or not.
00743   * @param __HANDLE__: ADC handle.
00744   * @param __FLAG__: ADC flag to check
00745   *        This parameter can be one of the following values:
00746   *            @arg @ref ADC_FLAG_RDY,     ADC Ready (ADRDY) flag
00747   *            @arg @ref ADC_FLAG_EOSMP,   ADC End of Sampling flag
00748   *            @arg @ref ADC_FLAG_EOC,     ADC End of Regular Conversion flag
00749   *            @arg @ref ADC_FLAG_EOS,     ADC End of Regular sequence of Conversions flag
00750   *            @arg @ref ADC_FLAG_OVR,     ADC overrun flag
00751   *            @arg @ref ADC_FLAG_JEOC,    ADC End of Injected Conversion flag
00752   *            @arg @ref ADC_FLAG_JEOS,    ADC End of Injected sequence of Conversions flag
00753   *            @arg @ref ADC_FLAG_AWD1,    ADC Analog watchdog 1 flag (main analog watchdog)
00754   *            @arg @ref ADC_FLAG_AWD2,    ADC Analog watchdog 2 flag (additional analog watchdog)
00755   *            @arg @ref ADC_FLAG_AWD3,    ADC Analog watchdog 3 flag (additional analog watchdog)
00756   *            @arg @ref ADC_FLAG_JQOVF,   ADC Injected Context Queue Overflow flag.
00757   * @retval The new state of __FLAG__ (TRUE or FALSE).
00758   */
00759 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
00760
00761 /**
00762   * @brief Clear a specified ADC flag.
00763   * @param __HANDLE__: ADC handle.
00764   * @param __FLAG__: ADC flag to clear
00765   *        This parameter can be one of the following values:
00766   *            @arg @ref ADC_FLAG_RDY,     ADC Ready (ADRDY) flag
00767   *            @arg @ref ADC_FLAG_EOSMP,   ADC End of Sampling flag
00768   *            @arg @ref ADC_FLAG_EOC,     ADC End of Regular Conversion flag
00769   *            @arg @ref ADC_FLAG_EOS,     ADC End of Regular sequence of Conversions flag
00770   *            @arg @ref ADC_FLAG_OVR,     ADC overrun flag
00771   *            @arg @ref ADC_FLAG_JEOC,    ADC End of Injected Conversion flag
00772   *            @arg @ref ADC_FLAG_JEOS,    ADC End of Injected sequence of Conversions flag
00773   *            @arg @ref ADC_FLAG_AWD1,    ADC Analog watchdog 1 flag (main analog watchdog)
00774   *            @arg @ref ADC_FLAG_AWD2,    ADC Analog watchdog 2 flag (additional analog watchdog)
00775   *            @arg @ref ADC_FLAG_AWD3,    ADC Analog watchdog 3 flag (additional analog watchdog)
00776   *            @arg @ref ADC_FLAG_JQOVF,   ADC Injected Context Queue Overflow flag.
00777   * @note  Bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR).
00778   * @retval None
00779   */
00780 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
00781
00782
00783 /**
00784   * @}
00785   */
00786
00787 /* Include ADC HAL Extended module */
00788 #include "stm32l4xx_hal_adc_ex.h"
00789
00790 /* Exported functions --------------------------------------------------------*/
00791 /** @addtogroup ADC_Exported_Functions ADC Exported Functions
00792   * @{
00793   */
00794
00795 /** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00796  *  @brief    Initialization and Configuration functions
00797  * @{
00798  */
00799 /* Initialization and de-initialization functions  **********************************/
00800 HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
00801 HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
00802 void                    HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
00803 void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
00804 /**
00805   * @}
00806   */
00807
00808 /** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
00809  *  @brief    IO operation functions
00810  * @{
00811  */
00812 /* Blocking mode: Polling */
00813 HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
00814 HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
00815 HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
00816 HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
00817
00818 /* Non-blocking mode: Interruption */
00819 HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
00820 HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
00821
00822 /* Non-blocking mode: DMA */
00823 HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
00824 HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
00825
00826 /* ADC retrieve conversion value intended to be used with polling or interruption */
00827 uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
00828
00829 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
00830 void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
00831 void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
00832 void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
00833 void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
00834 void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
00835 /**
00836   * @}
00837   */
00838
00839 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
00840  *  @brief    Peripheral Control functions
00841  * @{
00842  */
00843 /* Peripheral Control functions ***********************************************/
00844 HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
00845 HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
00846 /**
00847   * @}
00848   */
00849
00850 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
00851  *  @brief   ADC Peripheral State functions
00852  * @{
00853  */
00854 /* Peripheral State functions *************************************************/
00855 uint32_t      HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
00856 uint32_t      HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
00857 /**
00858   * @}
00859   */
00860
00861 /**
00862   * @}
00863   */
00864
00865 /* Private functions -----------------------------------------------------------*/
00866 /** @addtogroup ADC_Private_Functions ADC Private Functions
00867   * @{
00868   */
00869
00870 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
00871 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
00872 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
00873 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
00874 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
00875 void ADC_DMAError(DMA_HandleTypeDef *hdma);
00876
00877 /**
00878   * @}
00879   */
00880
00881 /**
00882   * @}
00883   */
00884
00885 /**
00886   * @}
00887   */
00888
00889 #ifdef __cplusplus
00890 }
00891 #endif
00892
00893 #endif /*__STM32L4xx_ADC_H */
00894
00895
00896 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_adc_ex.c Source File

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stm32l4xx_hal_adc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Analog to Digital Convertor (ADC)
00009   *          peripheral:
00010   *           + Calibration functions
00011   *             ++ Calibration start-up
00012   *             ++ Calibration value reading or setting
00013   *           + Operation functions
00014   *             ++ Start, stop, get result of conversions of injected
00015   *             groups, using 3 possible modes: polling or interruption.
00016   *             ++ Multimode feature when available
00017   *           + Control functions
00018   *             ++ Configure channels on injected group
00019   *           + State functions
00020   *             ++ Injected group queues management
00021   *
00022    @verbatim
00023   ==============================================================================
00024                     ##### ADC specific features #####
00025   ==============================================================================
00026   [..]
00027   (#) Interrupt generation at the end of injected conversion and in case of
00028       injected queues overflow.
00029
00030   (#) External trigger (timer or EXTI) with configurable polarity for
00031       injected groups.
00032
00033   (#) Multimode Dual mode when multimode feature is available.
00034
00035   (#) Configurable DMA data storage in Multimode Dual mode.
00036
00037   (#) Configurable delay between conversions in Dual interleaved mode.
00038
00039   (#) ADC calibration.
00040
00041   (#) ADC channels selectable single/differential input.
00042
00043   (#) ADC Injected sequencer&channels configuration context queue.
00044
00045   (#) ADC offset on injected groups.
00046
00047   (#) ADC oversampling.
00048
00049
00050                      ##### How to use this driver #####
00051   ==============================================================================
00052     [..]
00053
00054      (#) Configure the ADC parameters (conversion resolution, data alignment,
00055          continuous mode, ...) using the HAL_ADC_Init() function.
00056
00057      (#) Activate the ADC peripheral using one of the start functions:
00058          HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() for injected conversions
00059          or
00060          HAL_ADC_MultiModeStart_DMA() for multimode conversions when multimode
00061          feature is available.
00062
00063
00064      *** Channels to injected group configuration ***
00065      =============================================
00066      [..]
00067        (+) To configure the ADC Injected channels group features, use
00068            HAL_ADCEx_InjectedConfigChannel() functions.
00069        (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue()
00070            function.
00071
00072
00073      *** Multimode ADCs configuration (when  multimode feature is available) ***
00074      ========================================================================
00075      [..]
00076        (+) Multimode feature is available and applicable to Master and
00077            Slave ADCs.
00078        (+) Refer to "Channels to regular group configuration" description to
00079            configure the Master and Slave regular groups.
00080        (+) Select the Multi mode ADC  features (dual mode
00081            simultaneous, interleaved, ...) and configure the DMA mode using
00082            HAL_ADCEx_MultiModeConfigChannel() functions.
00083        (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue()
00084            function.
00085
00086
00087     @endverbatim
00088   ******************************************************************************
00089   * @attention
00090   *
00091   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00092   *
00093   * Redistribution and use in source and binary forms, with or without modification,
00094   * are permitted provided that the following conditions are met:
00095   *   1. Redistributions of source code must retain the above copyright notice,
00096   *      this list of conditions and the following disclaimer.
00097   *   2. Redistributions in binary form must reproduce the above copyright notice,
00098   *      this list of conditions and the following disclaimer in the documentation
00099   *      and/or other materials provided with the distribution.
00100   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00101   *      may be used to endorse or promote products derived from this software
00102   *      without specific prior written permission.
00103   *
00104   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00105   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00106   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00107   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00108   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00109   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00110   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00111   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00112   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00113   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00114   *
00115   ******************************************************************************
00116   */
00117
00118 /* Includes ------------------------------------------------------------------*/
00119 #include "stm32l4xx_hal.h"
00120
00121 /** @addtogroup STM32L4xx_HAL_Driver
00122   * @{
00123   */
00124
00125 /** @defgroup ADCEx ADCEx
00126   * @brief ADC Extended HAL module driver
00127   * @{
00128   */
00129
00130 #ifdef HAL_ADC_MODULE_ENABLED
00131
00132 /* Private typedef -----------------------------------------------------------*/
00133 /* Private define ------------------------------------------------------------*/
00134
00135 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
00136   * @{
00137   */
00138
00139 #define ADC_JSQR_FIELDS  ((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
00140                                      ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
00141                                       ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters that can be updated anytime
00142                                                                              once the ADC is enabled */
00143
00144 #define ADC_CFGR2_INJ_FIELDS  ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR  |\
00145                                        ADC_CFGR2_OVSS ))     /*!< ADC_CFGR2 injected oversampling parameters that can be updated
00146                                                                   when no conversion is on-going (neither regular nor injected) */
00147
00148 /* Fixed timeout value for ADC calibration.                                   */
00149 /* Values defined to be higher than worst cases: low clock frequency,         */
00150 /* maximum prescalers.                                                        */
00151 /* Ex of profile low frequency : f_ADC at 0.14 MHz (minimum value             */
00152 /* according to Data sheet), calibration_time MAX = 112 / f_ADC               */
00153 /*           112 / 140,000 = 0.8 ms                                           */
00154 /* At maximum CPU speed (80 MHz), this means                                  */
00155 /*    0.8 ms * 80 MHz = 64000 CPU cycles                                      */
00156 #define ADC_CALIBRATION_TIMEOUT         ((uint32_t) 64000)    /*!< ADC calibration time-out value */
00157
00158 /**
00159   * @}
00160   */
00161
00162 /* Private macro -------------------------------------------------------------*/
00163 /* Private variables ---------------------------------------------------------*/
00164 /* Private function prototypes -----------------------------------------------*/
00165 /* Exported functions --------------------------------------------------------*/
00166
00167 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
00168   * @{
00169   */
00170
00171
00172
00173 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
00174   * @brief    Extended IO operation functions
00175   *
00176 @verbatim
00177  ===============================================================================
00178              ##### IO operation functions #####
00179  ===============================================================================
00180     [..]  This section provides functions allowing to:
00181
00182       (+) Perform the ADC self-calibration for single or differential ending.
00183       (+) Get calibration factors for single or differential ending.
00184       (+) Set calibration factors for single or differential ending.
00185
00186       (+) Start conversion of injected group.
00187       (+) Stop conversion of injected group.
00188       (+) Poll for conversion complete on injected group.
00189       (+) Get result of injected channel conversion.
00190       (+) Start conversion of injected group and enable interruptions.
00191       (+) Stop conversion of injected group and disable interruptions.
00192
00193       (+) When multimode feature is available, start multimode and enable DMA transfer.
00194       (+) Stop multimode and disable ADC DMA transfer.
00195       (+) Get result of multimode conversion.
00196
00197
00198
00199 @endverbatim
00200   * @{
00201   */
00202
00203
00204
00205 /**
00206   * @brief  Perform an ADC automatic self-calibration
00207   *         Calibration prerequisite: ADC must be disabled (execute this
00208   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
00209   * @param  hadc: ADC handle.
00210   * @param  SingleDiff: Selection of single-ended or differential input
00211   *          This parameter can be one of the following values:
00212   *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00213   *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00214   * @retval HAL status
00215   */
00216 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
00217 {
00218   HAL_StatusTypeDef tmp_status = HAL_OK;
00219   uint32_t WaitLoopIndex = 0;
00220
00221   /* Check the parameters */
00222   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00223   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00224
00225   /* Process locked */
00226   __HAL_LOCK(hadc);
00227
00228   /* Calibration prerequisite: ADC must be disabled. */
00229
00230   /* Disable the ADC (if not already disabled) */
00231   tmp_status = ADC_Disable(hadc);
00232
00233   /* Check if ADC is effectively disabled */
00234   if (tmp_status == HAL_OK)
00235   {
00236     /* Change ADC state */
00237     /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_BUSY_INTERNAL bit */
00238     ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_BUSY_INTERNAL);
00239
00240     /* Select calibration mode single ended or differential ended */
00241     MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff);
00242
00243     /* Start ADC calibration */
00244     SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL);
00245
00246
00247     /* Wait for calibration completion */
00248     while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
00249     {
00250       WaitLoopIndex++;
00251       if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT)
00252       {
00253         /* Update ADC state machine to error */
00254         /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_ERROR_INTERNAL bit */
00255         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
00256
00257         /* Process unlocked */
00258         __HAL_UNLOCK(hadc);
00259
00260         return HAL_ERROR;
00261       }
00262     }
00263
00264     /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
00265     ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
00266   }
00267   else
00268   {
00269     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00270
00271     /* Update ADC state machine to error */
00272     tmp_status = HAL_ERROR;
00273   }
00274
00275
00276   /* Process unlocked */
00277   __HAL_UNLOCK(hadc);
00278
00279   /* Return function status */
00280   return tmp_status;
00281 }
00282
00283
00284
00285
00286 /**
00287   * @brief  Get the calibration factor from automatic conversion result.
00288   * @param  hadc: ADC handle.
00289   * @param  SingleDiff: Selection of single-ended or differential input
00290   *          This parameter can be one of the following values:
00291   *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00292   *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00293   * @retval Converted value
00294   */
00295 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
00296 {
00297   /* Check the parameters */
00298   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00299   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00300
00301   /* Return the selected ADC calibration value */
00302   if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
00303   {
00304     return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
00305   }
00306   else
00307   {
00308     return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
00309   }
00310 }
00311
00312
00313
00314 /**
00315   * @brief  Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
00316   * @param  hadc: ADC handle.
00317   * @param  SingleDiff: Selection of single-ended or differential input.
00318   *          This parameter can be one of the following values:
00319   *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00320   *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00321   * @param  CalibrationFactor: Calibration factor (coded on 7 bits maximum)
00322   * @retval HAL state
00323   */
00324 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
00325 {
00326   HAL_StatusTypeDef tmp_status = HAL_OK;
00327
00328   /* Check the parameters */
00329   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00330   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00331   assert_param(IS_ADC_CALFACT(CalibrationFactor));
00332
00333   /* Process locked */
00334   __HAL_LOCK(hadc);
00335
00336   /* Verification of hardware constraints before modifying the calibration    */
00337   /* factors register: ADC must be enabled, no conversion on going.           */
00338   if ( (ADC_IS_ENABLE(hadc) != RESET)                            &&
00339        (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)  )
00340   {
00341     /* Set the selected ADC calibration value */
00342     if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
00343     {
00344       MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor));
00345     }
00346     else
00347     {
00348       MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor);
00349     }
00350   }
00351   else
00352   {
00353     /* Update ADC state machine */
00354     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00355
00356     /* Update ADC state machine to error */
00357     tmp_status = HAL_ERROR;
00358   }
00359
00360   /* Process unlocked */
00361   __HAL_UNLOCK(hadc);
00362
00363   /* Return function status */
00364   return tmp_status;
00365 }
00366
00367
00368
00369 /**
00370   * @brief  Enable ADC, start conversion of injected group.
00371   * @note   Interruptions enabled in this function: None.
00372   * @note   Case of multimode enabled when multimode feature is available:
00373   *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
00374   *         then for ADC master.
00375   *         For ADC slave, ADC is enabled only (conversion is not started).
00376   *         For ADC master, ADC is enabled and multimode conversion is started.
00377   * @param  hadc: ADC handle.
00378   * @retval HAL status
00379   */
00380 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
00381 {
00382   HAL_StatusTypeDef tmp_status = HAL_OK;
00383
00384   /* Check the parameters */
00385   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00386
00387   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
00388   {
00389     return HAL_BUSY;
00390   }
00391   else
00392   {
00393
00394     /* In case of software trigger detection enabled, JQDIS must be set
00395       (which can be done only if ADSTART and JADSTART are both cleared).
00396        If JQDIS is not set at that point, returns an error
00397        - since software trigger detection is disabled. User needs to
00398        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
00399        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
00400          the queue is empty */
00401     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)
00402     && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))
00403     {
00404       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00405       return HAL_ERROR;
00406     }
00407
00408
00409     /* Process locked */
00410     __HAL_LOCK(hadc);
00411
00412     /* Enable the ADC peripheral */
00413     tmp_status = ADC_Enable(hadc);
00414
00415     /* Start conversion if ADC is effectively enabled */
00416     if (tmp_status == HAL_OK)
00417     {
00418       /* Check if a regular conversion is ongoing */
00419       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
00420       {
00421         /* Reset ADC error code field related to injected conversions only */
00422         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
00423       }
00424       else
00425       {
00426         /* Set ADC error code to none */
00427         ADC_CLEAR_ERRORCODE(hadc);
00428       }
00429       /* Update ADC state */
00430       /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
00431       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
00432
00433       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00434         - by default if ADC is Master or Independent or if multimode feature is not available
00435         - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
00436       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00437       {
00438         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00439       }
00440
00441
00442       /* Clear injected group conversion flag */
00443       /* (To ensure of no unknown state from potential previous ADC operations) */
00444       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00445
00446       /* Enable conversion of injected group, if automatic injected conversion  */
00447       /* is disabled.                                                           */
00448       /* If software start has been selected, conversion starts immediately.    */
00449       /* If external trigger has been selected, conversion will start at next   */
00450       /* trigger event.                                                         */
00451       /* Case of multimode enabled (when multimode feature is available):       */
00452       /* if ADC is slave,                                                       */
00453       /*    - ADC is enabled only (conversion is not started).                  */
00454       /*    - if multimode only concerns regular conversion, ADC is enabled     */
00455       /*     and conversion is started.                                         */
00456       /* If ADC is master or independent,                                       */
00457       /*    - ADC is enabled and conversion is started.                         */
00458
00459       /* Are injected conversions that of a dual Slave ? */
00460       if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
00461       {
00462         /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
00463            set ADSTART only if JAUTO is cleared */
00464         /* Process unlocked */
00465         __HAL_UNLOCK(hadc);
00466         if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
00467         {
00468           SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
00469         }
00470       }
00471       else
00472       {
00473         /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
00474            ADSTART is not set */
00475           SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00476         /* Process unlocked */
00477         __HAL_UNLOCK(hadc);
00478       }
00479     }
00480     else
00481     {
00482       /* Process unlocked */
00483       __HAL_UNLOCK(hadc);
00484     } /* if (tmp_status == HAL_OK) */
00485
00486
00487     /* Return function status */
00488     return tmp_status;
00489   } /*  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) */
00490 }
00491
00492
00493
00494 /**
00495   * @brief  Stop conversion of injected channels, disable ADC peripheral if no regular conversion is on going.
00496   * @note   If ADC must be disabled and if regular conversion
00497   *         is on going, function HAL_ADC_Stop() must be used.
00498   * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
00499   * @note   In case of multimode enabled (when multimode feature is available),
00500   *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
00501   *         For ADC master, conversion is stopped and ADC is disabled.
00502   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00503   *         has already stopped conversion of ADC slave).
00504   * @param  hadc: ADC handle.
00505   * @retval None
00506   */
00507 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
00508 {
00509   HAL_StatusTypeDef tmp_status = HAL_OK;
00510
00511   /* Check the parameters */
00512   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00513
00514   /* Process locked */
00515   __HAL_LOCK(hadc);
00516
00517   /* 1. Stop potential conversion on going on injected group only. */
00518   tmp_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00519
00520   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00521   /* and if no conversion on regular group is on-going                       */
00522   if (tmp_status == HAL_OK)
00523   {
00524     if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
00525     {
00526       /* 2. Disable the ADC peripheral */
00527       tmp_status = ADC_Disable(hadc);
00528
00529       /* Check if ADC is effectively disabled */
00530       if (tmp_status == HAL_OK)
00531       {
00532         /* Change ADC state */
00533       /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
00534       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
00535       }
00536     }
00537     /* Conversion on injected group is stopped, but ADC not disabled since    */
00538     /* conversion on regular group is still running.                          */
00539     else
00540     {
00541       /* Clear HAL_ADC_STATE_INJ_BUSY bit */
00542       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00543     }
00544   }
00545
00546   /* Process unlocked */
00547   __HAL_UNLOCK(hadc);
00548
00549   /* Return function status */
00550   return tmp_status;
00551 }
00552
00553
00554
00555 /**
00556   * @brief  Wait for injected group conversion to be completed.
00557   * @param  hadc: ADC handle
00558   * @param  Timeout: Timeout value in millisecond.
00559   * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is
00560   *         checked and cleared depending on AUTDLY bit status.
00561   * @retval HAL status
00562   */
00563 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00564 {
00565   uint32_t           tickstart;
00566   uint32_t           tmp_Flag_End        = 0x00;
00567   ADC_TypeDef        *tmpADC_Master;
00568   uint32_t           tmp_cfgr            = 0x00;
00569   uint32_t           tmp_cfgr_jqm_autdly = 0x00;
00570   uint32_t           tmp_jeos_raised     = 0x01; /* by default, assume that JEOS is set,
00571                                                     tmp_jeos_raised will be corrected
00572                                                     accordingly during API execution */
00573
00574   /* Check the parameters */
00575   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00576
00577   /* If end of sequence selected */
00578   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
00579   {
00580     tmp_Flag_End = ADC_FLAG_JEOS;
00581   }
00582   else /* end of conversion selected */
00583   {
00584     tmp_Flag_End = ADC_FLAG_JEOC;
00585   }
00586
00587   /* Get timeout */
00588   tickstart = HAL_GetTick();
00589
00590    /* Wait until End of Conversion or Sequence flag is raised */
00591   while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
00592   {
00593     /* Check if timeout is disabled (set to infinite wait) */
00594     if(Timeout != HAL_MAX_DELAY)
00595     {
00596       if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00597       {
00598         /* Update ADC state machine to timeout */
00599         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00600
00601         /* Process unlocked */
00602         __HAL_UNLOCK(hadc);
00603
00604         return HAL_TIMEOUT;
00605       }
00606     }
00607   }
00608
00609   /* Next, to clear the polled flag as well as to update the handle State,
00610      JEOS is checked and the relevant configuration registers are retrieved.
00611      JQM, JAUTO and CONT bits will have to be read for the State update,
00612      AUTDLY for JEOS clearing. */
00613   /*   1. Check whether or not JEOS is set */
00614   if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_JEOS))
00615   {
00616     tmp_jeos_raised = 0;
00617   }
00618   /*  2. Check whether or not hadc is the handle of a Slave ADC with dual
00619         injected conversions enabled. */
00620   if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == RESET)
00621   {
00622     /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
00623         check JQM and AUTDLY bits directly in ADC CFGR register */
00624     tmp_cfgr_jqm_autdly = READ_REG(hadc->Instance->CFGR);
00625   }
00626   else
00627   {
00628     /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
00629         need to check JQM and AUTDLY bits of Master ADC CFGR register */
00630     tmpADC_Master = ADC_MASTER_REGISTER(hadc);
00631     tmp_cfgr_jqm_autdly = READ_REG(tmpADC_Master->CFGR);
00632   }
00633   /* 3. Check whether or not hadc is the handle of a Slave ADC with dual
00634         regular conversions enabled. */
00635   if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
00636   {
00637     /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
00638        check JAUTO and CONT bits directly in ADC CFGR register */
00639     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
00640   }
00641   else
00642   {
00643     /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
00644       check JAUTO and CONT bits of Master ADC CFGR register */
00645     tmpADC_Master = ADC_MASTER_REGISTER(hadc);
00646     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
00647   }
00648
00649
00650
00651   /* Clear polled flag */
00652   if (tmp_Flag_End == ADC_FLAG_JEOS)
00653   {
00654     /* Clear end of sequence JEOS flag of injected group if low power feature */
00655     /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
00656     /* For injected groups, no new conversion will start before JEOS is       */
00657     /* cleared.                                                               */
00658     /* Note that 1. reading ADCx_JDRy clears JEOC.                            */
00659     /*           2. in multimode with dual injected conversions enabled (when */
00660     /*              multimode feature is available), Master AUTDLY bit is     */
00661     /*              checked.                                                  */
00662     if (READ_BIT (tmp_cfgr_jqm_autdly, ADC_CFGR_AUTDLY) == RESET)
00663     {
00664       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00665     }
00666   }
00667   else
00668   {
00669     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00670   }
00671
00672
00673   /* Update ADC state machine */
00674   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
00675   /* Are injected conversions over ? This is the case if JEOS is set AND
00676         - injected conversions are software-triggered when injected queue management is disabled
00677         OR
00678         - auto-injection is enabled, continuous mode is disabled,
00679           and regular conversions are software-triggered */
00680
00681   if (tmp_jeos_raised)
00682   {
00683     if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm_autdly, ADC_CFGR_JQM) != ADC_CFGR_JQM))
00684        && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&
00685            (ADC_IS_SOFTWARE_START_REGULAR(hadc)))    ))
00686     {
00687       /* Clear HAL_ADC_STATE_INJ_BUSY bit */
00688       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00689       /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
00690       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00691       {
00692         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00693       }
00694     }
00695   }
00696
00697
00698
00699   /* Return API HAL status */
00700   return HAL_OK;
00701 }
00702
00703
00704
00705 /**
00706   * @brief  Enable ADC, start conversion of injected group with interruption.
00707   * @note   Interruptions enabled in this function according to initialization
00708   *         setting : JEOC (end of conversion) or JEOS (end of sequence)
00709   * @note   Case of multimode enabled (when multimode feature is enabled):
00710   *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
00711   *         then for ADC master.
00712   *         For ADC slave, ADC is enabled only (conversion is not started).
00713   *         For ADC master, ADC is enabled and multimode conversion is started.
00714   * @param  hadc: ADC handle.
00715   * @retval HAL status.
00716   */
00717 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
00718 {
00719   HAL_StatusTypeDef tmp_status = HAL_OK;
00720
00721   /* Check the parameters */
00722   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00723
00724   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
00725   {
00726     return HAL_BUSY;
00727   }
00728   else
00729   {
00730
00731     /* In case of software trigger detection enabled, JQDIS must be set
00732       (which can be done only if ADSTART and JADSTART are both cleared).
00733        If JQDIS is not set at that point, returns an error
00734        - since software trigger detection is disabled. User needs to
00735        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
00736        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
00737          the queue is empty */
00738     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)
00739     && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))
00740     {
00741       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00742       return HAL_ERROR;
00743     }
00744
00745     /* Process locked */
00746     __HAL_LOCK(hadc);
00747
00748     /* Enable the ADC peripheral */
00749     tmp_status = ADC_Enable(hadc);
00750
00751     /* Start conversion if ADC is effectively enabled */
00752     if (tmp_status == HAL_OK)
00753     {
00754       /* Check if a regular conversion is ongoing */
00755       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
00756       {
00757         /* Reset ADC error code field related to injected conversions only */
00758         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
00759       }
00760       else
00761       {
00762         /* Set ADC error code to none */
00763         ADC_CLEAR_ERRORCODE(hadc);
00764       }
00765       /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
00766       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
00767
00768       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00769         - by default if ADC is Master or Independent or if multimode feature is not available
00770         - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
00771       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00772       {
00773         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00774       }
00775
00776       /* Clear injected group conversion flag */
00777       /* (To ensure of no unknown state from potential previous ADC operations) */
00778       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00779
00780       /* Enable ADC Injected context queue overflow interrupt if this feature   */
00781       /* is enabled.                                                            */
00782       if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
00783       {
00784         __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
00785       }
00786
00787       /* Enable ADC end of conversion interrupt */
00788       switch(hadc->Init.EOCSelection)
00789       {
00790         case ADC_EOC_SEQ_CONV:
00791           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00792           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
00793           break;
00794         /* case ADC_EOC_SINGLE_CONV */
00795         default:
00796           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
00797           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
00798           break;
00799       }
00800
00801       /* Enable conversion of injected group, if automatic injected conversion  */
00802       /* is disabled.                                                           */
00803       /* If software start has been selected, conversion starts immediately.    */
00804       /* If external trigger has been selected, conversion will start at next   */
00805       /* trigger event.                                                         */
00806       /* Case of multimode enabled (when multimode feature is available):       */
00807       /* if ADC is slave,                                                       */
00808       /*    - ADC is enabled only (conversion is not started),                  */
00809       /*    - if multimode only concerns regular conversion, ADC is enabled     */
00810       /*     and conversion is started.                                         */
00811       /* If ADC is master or independent,                                       */
00812       /*    - ADC is enabled and conversion is started.                         */
00813
00814       /* Are injected conversions that of a dual Slave ? */
00815       if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
00816       {
00817         /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
00818            set ADSTART only if JAUTO is cleared */
00819         /* Process unlocked */
00820         __HAL_UNLOCK(hadc);
00821         if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
00822         {
00823           SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
00824         }
00825       }
00826       else
00827       {
00828         /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
00829            ADSTART is not set */
00830           SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00831         /* Process unlocked */
00832         __HAL_UNLOCK(hadc);
00833       }
00834     }
00835     else
00836     {
00837       /* Process unlocked */
00838       __HAL_UNLOCK(hadc);
00839     }
00840
00841     /* Return function status */
00842     return tmp_status;
00843 }
00844 }
00845
00846
00847
00848 /**
00849   * @brief  Stop conversion of injected channels, disable interruption of end-of-conversion.
00850   * @note   Disable ADC peripheral if no regular conversion
00851   *         is on going.
00852   * @note   If ADC must be disabled and if regular conversion
00853   *         is on going, function HAL_ADC_Stop must be used first.
00854   * @note   Case of multimode enabled (when multimode feature is available):
00855   *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
00856   *         then for ADC slave.
00857   *         For ADC master, conversion is stopped and ADC is disabled.
00858   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00859   *         has already stopped conversion of ADC slave).
00860   * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
00861   * @param  hadc: ADC handle
00862   * @retval None
00863   */
00864 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
00865 {
00866   HAL_StatusTypeDef tmp_status = HAL_OK;
00867
00868   /* Check the parameters */
00869   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00870
00871   /* Process locked */
00872   __HAL_LOCK(hadc);
00873
00874   /* 1. Stop potential conversion on going on injected group only. */
00875   tmp_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00876
00877   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00878   /* and if no conversion on the other group (regular group) is intended to   */
00879   /* continue.                                                                */
00880   if (tmp_status == HAL_OK)
00881   {
00882     /* Disable ADC end of conversion interrupt for injected channels */
00883     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
00884
00885     if ((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET))
00886     {
00887       /* 2. Disable the ADC peripheral */
00888       tmp_status = ADC_Disable(hadc);
00889
00890       /* Check if ADC is effectively disabled */
00891       if (tmp_status == HAL_OK)
00892       {
00893         /* Change ADC state */
00894         /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
00895         ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
00896       }
00897     }
00898     /* Conversion on injected group is stopped, but ADC not disabled since    */
00899     /* conversion on regular group is still running.                          */
00900     else
00901     {
00902       /* Clear HAL_ADC_STATE_INJ_BUSY bit */
00903       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00904     }
00905   }
00906
00907   /* Process unlocked */
00908   __HAL_UNLOCK(hadc);
00909
00910   /* Return function status */
00911   return tmp_status;
00912 }
00913
00914
00915 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00916 /**
00917   * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
00918   * @note   Multimode must have been previously configured using
00919   *         HAL_ADCEx_MultiModeConfigChannel() function.
00920   *         Interruptions enabled in this function:
00921   *          overrun, DMA half transfer, DMA transfer complete.
00922   *         Each of these interruptions has its dedicated callback function.
00923   * @note   State field of Slave ADC handle is not updated in this configuration:
00924   *          user should not rely on it for information related to Slave regular
00925   *         conversions.
00926   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
00927   * @param  pData: Destination Buffer address.
00928   * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes).
00929   * @retval None
00930   */
00931 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
00932 {
00933   HAL_StatusTypeDef tmp_status = HAL_OK;
00934   ADC_HandleTypeDef tmphadcSlave;
00935   ADC_Common_TypeDef *tmpADC_Common;
00936
00937   /* Check the parameters */
00938   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
00939   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00940   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00941   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00942
00943   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
00944   {
00945     return HAL_BUSY;
00946   }
00947   else
00948   {
00949     /* Process locked */
00950     __HAL_LOCK(hadc);
00951
00952     /* Set a temporary handle of the ADC slave associated to the ADC master   */
00953     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
00954
00955     if (tmphadcSlave.Instance == NULL)
00956     {
00957       /* Update ADC state machine to error */
00958       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00959
00960       /* Process unlocked */
00961       __HAL_UNLOCK(hadc);
00962
00963       return HAL_ERROR;
00964     }
00965
00966
00967     /* Enable the ADC peripherals: master and slave (in case if not already   */
00968     /* enabled previously)                                                    */
00969     tmp_status = ADC_Enable(hadc);
00970     if (tmp_status == HAL_OK)
00971     {
00972       tmp_status = ADC_Enable(&tmphadcSlave);
00973     }
00974
00975     /* Start multimode conversion of ADCs pair */
00976     if (tmp_status == HAL_OK)
00977     {
00978       /* Update Master State */
00979       /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
00980       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
00981
00982
00983       /* Set ADC error code to none */
00984       ADC_CLEAR_ERRORCODE(hadc);
00985
00986
00987       /* Set the DMA transfer complete callback */
00988       hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
00989
00990       /* Set the DMA half transfer complete callback */
00991       hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
00992
00993       /* Set the DMA error callback */
00994       hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
00995
00996       /* Pointer to the common control register  */
00997       tmpADC_Common = ADC_COMMON_REGISTER(hadc);
00998
00999
01000       /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
01001       /* start (in case of SW start):                                           */
01002
01003       /* Clear regular group conversion flag and overrun flag */
01004       /* (To ensure of no unknown state from potential previous ADC operations) */
01005       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01006
01007       /* Enable ADC overrun interrupt */
01008       __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01009
01010       /* Start the DMA channel */
01011       HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
01012
01013       /* Enable conversion of regular group.                                    */
01014       /* Process unlocked */
01015       __HAL_UNLOCK(hadc);
01016       /* If software start has been selected, conversion starts immediately.    */
01017       /* If external trigger has been selected, conversion will start at next   */
01018       /* trigger event.                                                         */
01019       SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01020
01021     }
01022     else
01023     {
01024       /* Process unlocked */
01025       __HAL_UNLOCK(hadc);
01026     }
01027
01028     /* Return function status */
01029     return tmp_status;
01030   }
01031 }
01032
01033 /**
01034   * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
01035   * @note   Multimode is kept enabled after this function. MultiMode DMA bits
01036   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
01037   *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
01038   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
01039   *         resort to HAL_ADCEx_DisableMultiMode() API.
01040   * @note   In case of DMA configured in circular mode, function
01041   *         HAL_ADC_Stop_DMA() must be called after this function with handle of
01042   *         ADC slave, to properly disable the DMA channel.
01043   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
01044   * @retval None
01045   */
01046 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
01047 {
01048   HAL_StatusTypeDef tmp_status = HAL_OK;
01049   uint32_t tickstart;
01050   ADC_HandleTypeDef tmphadcSlave;
01051
01052   /* Check the parameters */
01053   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01054
01055   /* Process locked */
01056   __HAL_LOCK(hadc);
01057
01058
01059   /* 1. Stop potential multimode conversion on going, on regular and injected groups */
01060   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01061
01062   /* Disable ADC peripheral if conversions are effectively stopped */
01063   if (tmp_status == HAL_OK)
01064   {
01065     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01066     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01067
01068     if (tmphadcSlave.Instance == NULL)
01069     {
01070       /* Update ADC state machine to error */
01071       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01072
01073       /* Process unlocked */
01074       __HAL_UNLOCK(hadc);
01075
01076       return HAL_ERROR;
01077     }
01078
01079     /* Procedure to disable the ADC peripheral: wait for conversions          */
01080     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
01081
01082     /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
01083     tickstart = HAL_GetTick();
01084
01085     while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          ||
01086           ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
01087     {
01088       if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
01089       {
01090         /* Update ADC state machine to error */
01091         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01092
01093         /* Process unlocked */
01094         __HAL_UNLOCK(hadc);
01095
01096         return HAL_ERROR;
01097       }
01098     }
01099
01100     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01101     /* while DMA transfer is on going)                                        */
01102     /* Note: DMA channel of ADC slave should be stopped after this function   */
01103     /*       with HAL_ADC_Stop_DMA() API.                                     */
01104     tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
01105
01106     /* Check if DMA channel effectively disabled */
01107     if (tmp_status == HAL_ERROR)
01108     {
01109       /* Update ADC state machine to error */
01110       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01111     }
01112
01113     /* Disable ADC overrun interrupt */
01114     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01115
01116
01117
01118     /* 2. Disable the ADC peripherals: master and slave */
01119     /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
01120     /* memory a potential failing status.                                     */
01121     if (tmp_status == HAL_OK)
01122     {
01123       /* Check if ADC are effectively disabled */
01124       if ((ADC_Disable(hadc) == HAL_OK)         &&
01125           (ADC_Disable(&tmphadcSlave) == HAL_OK)   )
01126       {
01127         tmp_status = HAL_OK;
01128       }
01129     }
01130     else
01131     {
01132       ADC_Disable(hadc);
01133       ADC_Disable(&tmphadcSlave);
01134     }
01135     /* Change ADC state (ADC master) */
01136     /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
01137     ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
01138
01139   }
01140
01141   /* Process unlocked */
01142   __HAL_UNLOCK(hadc);
01143
01144   /* Return function status */
01145   return tmp_status;
01146 }
01147
01148
01149 /**
01150   * @brief  Return the last ADC Master and Slave regular conversions results when in multimode configuration.
01151   * @param  hadc: ADC handle of ADC Master (handle of ADC Slave must not be used)
01152   * @retval The converted data values.
01153   */
01154 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
01155 {
01156   ADC_Common_TypeDef *tmpADC_Common;
01157
01158   /* Check the parameters */
01159   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01160
01161   /* Pointer to the common control register  */
01162   tmpADC_Common = ADC_COMMON_REGISTER(hadc);
01163
01164   /* Return the multi mode conversion value */
01165   return tmpADC_Common->CDR;
01166 }
01167 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01168
01169
01170 /**
01171   * @brief  Get ADC injected group conversion result.
01172   * @param  hadc: ADC handle
01173   * @param  InjectedRank: the converted ADC injected rank.
01174   *          This parameter can be one of the following values:
01175   *            @arg @ref ADC_INJECTED_RANK_1 Injected Channel1 selected
01176   *            @arg @ref ADC_INJECTED_RANK_2 Injected Channel2 selected
01177   *            @arg @ref ADC_INJECTED_RANK_3 Injected Channel3 selected
01178   *            @arg @ref ADC_INJECTED_RANK_4 Injected Channel4 selected
01179   * @note   Reading JDRy register automatically clears JEOC flag. To reset JEOS
01180   *         flag the user must resort to the macro
01181   *         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS).
01182   * @retval None
01183   */
01184 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
01185 {
01186   uint32_t tmp_jdr = 0;
01187
01188   /* Check the parameters */
01189   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01190   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
01191
01192
01193   /* Get ADC converted value */
01194   switch(InjectedRank)
01195   {
01196     case ADC_INJECTED_RANK_4:
01197       tmp_jdr = hadc->Instance->JDR4;
01198       break;
01199     case ADC_INJECTED_RANK_3:
01200       tmp_jdr = hadc->Instance->JDR3;
01201       break;
01202     case ADC_INJECTED_RANK_2:
01203       tmp_jdr = hadc->Instance->JDR2;
01204       break;
01205     case ADC_INJECTED_RANK_1:
01206     default:
01207       tmp_jdr = hadc->Instance->JDR1;
01208       break;
01209   }
01210
01211   /* Return ADC converted value */
01212   return tmp_jdr;
01213 }
01214
01215 /**
01216   * @brief  Injected conversion complete callback in non-blocking mode.
01217   * @param  hadc: ADC handle
01218   * @retval None
01219   */
01220 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
01221 {
01222   /* Prevent unused argument(s) compilation warning */
01223   UNUSED(hadc);
01224
01225   /* NOTE : This function should not be modified. When the callback is needed,
01226             function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
01227   */
01228 }
01229
01230
01231 /**
01232   * @brief  Injected context queue overflow callback.
01233   * @note   This callback is called if injected context queue is enabled
01234             (parameter "QueueInjectedContext" in injected channel configuration)
01235             and if a new injected context is set when queue is full (maximum 2
01236             contexts).
01237   * @param  hadc: ADC handle
01238   * @retval None
01239   */
01240 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
01241 {
01242   /* Prevent unused argument(s) compilation warning */
01243   UNUSED(hadc);
01244
01245   /* NOTE : This function should not be modified. When the callback is needed,
01246             function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
01247   */
01248 }
01249
01250 /**
01251   * @brief  Analog watchdog 2 callback in non-blocking mode.
01252   * @param  hadc: ADC handle
01253   * @retval None
01254   */
01255 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
01256 {
01257   /* Prevent unused argument(s) compilation warning */
01258   UNUSED(hadc);
01259
01260   /* NOTE : This function should not be modified. When the callback is needed,
01261             function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
01262   */
01263 }
01264
01265 /**
01266   * @brief  Analog watchdog 3 callback in non-blocking mode.
01267   * @param  hadc: ADC handle
01268   * @retval None
01269   */
01270 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
01271 {
01272   /* Prevent unused argument(s) compilation warning */
01273   UNUSED(hadc);
01274
01275   /* NOTE : This function should not be modified. When the callback is needed,
01276             function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
01277   */
01278 }
01279
01280
01281 /**
01282   * @brief  End Of Sampling callback in non-blocking mode.
01283   * @param  hadc: ADC handle
01284   * @retval None
01285   */
01286 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc)
01287 {
01288   /* Prevent unused argument(s) compilation warning */
01289   UNUSED(hadc);
01290
01291   /* NOTE : This function should not be modified. When the callback is needed,
01292             function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
01293   */
01294 }
01295
01296
01297
01298 /**
01299   * @brief  Stop ADC conversion of regular groups, disable ADC peripheral if no injected conversion is on-going.
01300   * @param  hadc: ADC handle
01301   * @retval HAL status.
01302   */
01303 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
01304 {
01305   HAL_StatusTypeDef tmp_status = HAL_OK;
01306
01307   /* Check the parameters */
01308   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01309
01310   /* Process locked */
01311   __HAL_LOCK(hadc);
01312
01313   /* 1. Stop potential regular conversion on going */
01314   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01315
01316   /* Disable ADC peripheral if regular conversions are effectively stopped
01317      and if no injected conversions are on-going */
01318   if (tmp_status == HAL_OK)
01319   {
01320     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01321     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01322
01323     if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01324     {
01325       /* 2. Disable the ADC peripheral */
01326       tmp_status = ADC_Disable(hadc);
01327
01328       /* Check if ADC is effectively disabled */
01329       if (tmp_status == HAL_OK)
01330       {
01331         /* Change ADC state */
01332         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01333         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01334       }
01335     }
01336     /* Conversion on injected group is stopped, but ADC not disabled since    */
01337     /* conversion on regular group is still running.                          */
01338     else
01339     {
01340       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01341     }
01342   }
01343
01344   /* Process unlocked */
01345   __HAL_UNLOCK(hadc);
01346
01347   /* Return function status */
01348   return tmp_status;
01349 }
01350
01351
01352 /**
01353   * @brief  Stop ADC conversion of regular groups when interruptions are enabled, disable ADC peripheral if no injected conversion is on-going.
01354   * @param  hadc: ADC handle
01355   * @retval HAL status.
01356   */
01357 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
01358 {
01359   HAL_StatusTypeDef tmp_status = HAL_OK;
01360
01361   /* Check the parameters */
01362   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01363
01364   /* Process locked */
01365   __HAL_LOCK(hadc);
01366
01367   /* 1. Stop potential regular conversion on going */
01368   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01369
01370   /* Disable ADC peripheral if conversions are effectively stopped
01371     and if no injected conversion is on-going */
01372   if (tmp_status == HAL_OK)
01373   {
01374     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01375     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01376
01377     /* Disable all regular-related interrupts */
01378     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01379
01380     /* 2. Disable ADC peripheral if no injected conversions are on-going */
01381     if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01382     {
01383       tmp_status = ADC_Disable(hadc);
01384       /* if no issue reported */
01385       if (tmp_status == HAL_OK)
01386       {
01387         /* Change ADC state */
01388         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01389         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01390       }
01391     }
01392     else
01393     {
01394       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01395     }
01396   }
01397
01398   /* Process unlocked */
01399   __HAL_UNLOCK(hadc);
01400
01401   /* Return function status */
01402   return tmp_status;
01403 }
01404
01405
01406 /**
01407   * @brief  Stop ADC conversion of regular groups and disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
01408   * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
01409   *         For multimode (when multimode feature is available),
01410   *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
01411   * @param  hadc: ADC handle
01412   * @retval HAL status.
01413   */
01414 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
01415 {
01416   HAL_StatusTypeDef tmp_status = HAL_OK;
01417
01418   /* Check the parameters */
01419   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01420
01421   /* Process locked */
01422   __HAL_LOCK(hadc);
01423
01424   /* 1. Stop potential regular conversion on going */
01425   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01426
01427   /* Disable ADC peripheral if conversions are effectively stopped
01428      and if no injected conversion is on-going */
01429   if (tmp_status == HAL_OK)
01430   {
01431     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01432     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01433
01434     /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
01435     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
01436
01437     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01438     /* while DMA transfer is on going)                                        */
01439     tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
01440
01441     /* Check if DMA channel effectively disabled */
01442     if (tmp_status != HAL_OK)
01443     {
01444       /* Update ADC state machine to error */
01445       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01446     }
01447
01448     /* Disable ADC overrun interrupt */
01449     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01450
01451     /* 2. Disable the ADC peripheral */
01452     /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
01453     /* memory a potential failing status.                                     */
01454     if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01455     {
01456       if (tmp_status == HAL_OK)
01457       {
01458         tmp_status = ADC_Disable(hadc);
01459       }
01460       else
01461       {
01462         ADC_Disable(hadc);
01463       }
01464
01465       /* Check if ADC is effectively disabled */
01466       if (tmp_status == HAL_OK)
01467       {
01468         /* Change ADC state */
01469         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01470         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01471       }
01472     }
01473     else
01474     {
01475       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01476     }
01477   }
01478
01479   /* Process unlocked */
01480   __HAL_UNLOCK(hadc);
01481
01482   /* Return function status */
01483   return tmp_status;
01484 }
01485
01486
01487 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01488 /**
01489   * @brief  Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
01490   * @note   Multimode is kept enabled after this function. Multimode DMA bits
01491   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
01492   *         multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
01493   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
01494   *         resort to HAL_ADCEx_DisableMultiMode() API.
01495   * @note   In case of DMA configured in circular mode, function
01496   *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
01497   *         ADC slave, to properly disable the DMA channel.
01498   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
01499   * @retval None
01500   */
01501 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
01502 {
01503   HAL_StatusTypeDef tmp_status = HAL_OK;
01504   uint32_t tickstart;
01505   ADC_HandleTypeDef tmphadcSlave;
01506
01507   /* Check the parameters */
01508   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01509
01510   /* Process locked */
01511   __HAL_LOCK(hadc);
01512
01513
01514   /* 1. Stop potential multimode conversion on going, on regular groups */
01515   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01516
01517   /* Disable ADC peripheral if conversions are effectively stopped */
01518   if (tmp_status == HAL_OK)
01519   {
01520     /* Clear HAL_ADC_STATE_REG_BUSY bit */
01521     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01522
01523     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01524     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01525
01526     if (tmphadcSlave.Instance == NULL)
01527     {
01528       /* Update ADC state machine to error */
01529       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01530
01531       /* Process unlocked */
01532       __HAL_UNLOCK(hadc);
01533
01534       return HAL_ERROR;
01535     }
01536
01537     /* Procedure to disable the ADC peripheral: wait for conversions          */
01538     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
01539
01540     /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
01541     tickstart = HAL_GetTick();
01542
01543     while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          ||
01544           ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
01545     {
01546       if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
01547       {
01548         /* Update ADC state machine to error */
01549         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01550
01551         /* Process unlocked */
01552         __HAL_UNLOCK(hadc);
01553
01554         return HAL_ERROR;
01555       }
01556     }
01557
01558     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01559     /* while DMA transfer is on going)                                        */
01560     /* Note: DMA channel of ADC slave should be stopped after this function   */
01561     /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
01562     tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
01563
01564     /* Check if DMA channel effectively disabled */
01565     if (tmp_status != HAL_OK)
01566     {
01567       /* Update ADC state machine to error */
01568       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01569     }
01570
01571     /* Disable ADC overrun interrupt */
01572     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01573
01574
01575
01576     /* 2. Disable the ADC peripherals: master and slave if no injected        */
01577     /*   conversion is on-going.                                              */
01578     /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
01579     /* memory a potential failing status.                                     */
01580     if (tmp_status == HAL_OK)
01581     {
01582        if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01583        {
01584          tmp_status =  ADC_Disable(hadc);
01585          if (tmp_status == HAL_OK)
01586          {
01587            if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET)
01588            {
01589              tmp_status =  ADC_Disable(&tmphadcSlave);
01590            }
01591          }
01592        }
01593
01594        if (tmp_status == HAL_OK)
01595        {
01596          /* Both Master and Slave ADC's could be disabled. Update Master State */
01597          /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01598          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01599        }
01600        else
01601        {
01602          /* injected (Master or Slave) conversions are still on-going,
01603             no Master State change */
01604        }
01605
01606
01607     }
01608
01609
01610   }
01611
01612   /* Process unlocked */
01613   __HAL_UNLOCK(hadc);
01614
01615   /* Return function status */
01616   return tmp_status;
01617 }
01618 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01619
01620 /**
01621   * @}
01622   */
01623
01624 /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
01625   * @brief    Extended Peripheral Control functions
01626   *
01627 @verbatim
01628  ===============================================================================
01629              ##### Peripheral Control functions #####
01630  ===============================================================================
01631     [..]  This section provides functions allowing to:
01632       (+) Configure channels on injected group
01633       (+) Configure multimode when multimode feature is available
01634       (+) Enable or Disable Injected Queue
01635       (+) Disable ADC voltage regulator
01636       (+) Enter ADC deep-power-down mode
01637
01638
01639 @endverbatim
01640   * @{
01641   */
01642
01643 /**
01644   * @brief  Configure the ADC injected group and the selected channel to be linked to the injected group.
01645   * @note   Possibility to update parameters on the fly:
01646   *         This function initializes injected group, consecutive calls to this
01647   *         function can be used to reconfigure some parameters of structure
01648   *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
01649   *         The setting of these parameters is conditioned to ADC state.
01650   *         For parameters constraints, see comments of structure
01651   *         "ADC_InjectionConfTypeDef".
01652   * @note   In case of usage of internal measurement channels (Vbat/VrefInt/TempSensor),
01653   *         The internal paths can be disabled using function HAL_ADC_DeInit().
01654   * @note   To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
01655   *         be used.
01656   * @note   Caution: For Injected Context Queue use, a context must be fully
01657   *         defined before start of injected conversion. All channels are configured
01658   *         consecutively for the same ADC instance. Therefore, the number of calls to
01659   *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
01660   *         InjectedNbrOfConversion for each context.
01661   *  - Example 1: If 1 context is intended to be used (or if there is no use of the
01662   *    Injected Queue Context feature) and if the context contains 3 injected ranks
01663   *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
01664   *    called once for each channel (i.e. 3 times) before starting a conversion.
01665   *    This function must not be called to configure a 4th injected channel:
01666   *    it would start a new context into context queue.
01667   *  - Example 2: If 2 contexts are intended to be used and each of them contains
01668   *    3 injected ranks (InjectedNbrOfConversion = 3),
01669   *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
01670   *    for each context (3 channels x 2 contexts = 6 calls). Conversion can
01671   *    start once the 1st context is set, that is after the first three
01672   *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
01673   * @param  hadc: ADC handle
01674   * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
01675   *         injected group.
01676   * @retval None
01677   */
01678 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
01679 {
01680   HAL_StatusTypeDef tmp_status = HAL_OK;
01681   ADC_Common_TypeDef *tmpADC_Common;
01682   uint32_t tmpOffsetShifted;
01683   uint32_t wait_loop_index = 0;
01684
01685
01686   uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
01687
01688   /* Check the parameters */
01689   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01690   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
01691   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
01692   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
01693   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
01694   assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
01695   assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
01696   assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
01697   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
01698   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
01699
01700   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
01701   {
01702     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
01703     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
01704     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
01705   }
01706
01707
01708   /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
01709      ignored (considered as reset) */
01710   assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
01711
01712   /* JDISCEN and JAUTO bits can't be set at the same time  */
01713   assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
01714
01715   /*  DISCEN and JAUTO bits can't be set at the same time */
01716   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
01717
01718   /* Verification of channel number */
01719   if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
01720   {
01721      assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
01722   }
01723   else
01724   {
01725     assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
01726   }
01727
01728
01729   /* Process locked */
01730   __HAL_LOCK(hadc);
01731
01732
01733
01734   /* Configuration of Injected group sequencer.                               */
01735   /* Hardware constraint: Must fully define injected context register JSQR    */
01736   /* before make it entering into injected sequencer queue.                   */
01737   /*                                                                          */
01738   /* - if scan mode is disabled:                                              */
01739   /*    * Injected channels sequence length is set to 0x00: 1 channel         */
01740   /*      converted (channel on injected rank 1)                              */
01741   /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
01742   /*    * Injected context register JSQR setting is simple: register is fully */
01743   /*      defined on one call of this function (for injected rank 1) and can  */
01744   /*      be entered into queue directly.                                     */
01745   /* - if scan mode is enabled:                                               */
01746   /*    * Injected channels sequence length is set to parameter               */
01747   /*      "InjectedNbrOfConversion".                                          */
01748   /*    * Injected context register JSQR setting more complex: register is    */
01749   /*      fully defined over successive calls of this function, for each      */
01750   /*      injected channel rank. It is entered into queue only when all       */
01751   /*      injected ranks have been set.                                       */
01752   /*   Note: Scan mode is not present by hardware on this device, but used    */
01753   /*   by software for alignment over all STM32 devices.                      */
01754
01755   if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
01756       (sConfigInjected->InjectedNbrOfConversion == 1)  )
01757   {
01758     /* Configuration of context register JSQR:                                */
01759     /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
01760     /*    (scan mode disabled, only rank 1 used)                              */
01761     /*  - external trigger to start conversion                                */
01762     /*  - external trigger polarity                                           */
01763     /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
01764
01765     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
01766     {
01767       /* Enable external trigger if trigger selection is different of         */
01768       /* software start.                                                      */
01769       /* Note: This configuration keeps the hardware feature of parameter     */
01770       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01771       /*       software start.                                                */
01772       if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01773          && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
01774       {
01775         tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
01776                                              sConfigInjected->ExternalTrigInjecConv     |
01777                                              sConfigInjected->ExternalTrigInjecConvEdge                                );
01778       }
01779       else
01780       {
01781         tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
01782       }
01783
01784
01785       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
01786       /* For debug and informative reasons, hadc handle saves JSQR setting */
01787       hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
01788
01789     }
01790   }
01791   else
01792   {
01793     /* Case of scan mode enabled, several channels to set into injected group */
01794     /* sequencer.                                                             */
01795     /*                                                                        */
01796     /* Procedure to define injected context register JSQR over successive     */
01797     /* calls of this function, for each injected channel rank:                */
01798     /* 1. Start new context and set parameters related to all injected        */
01799     /*    channels: injected sequence length and trigger.                     */
01800
01801     /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
01802     /*   call of the context under setting                                    */
01803     if (hadc->InjectionConfig.ChannelCount == 0)
01804     {
01805       /* Initialize number of channels that will be configured on the context */
01806       /*  being built                                                         */
01807       hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
01808       /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
01809          call, this context will be written in JSQR register at the last call.
01810          At this point, the context is merely reset  */
01811        hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
01812
01813       /* Configuration of context register JSQR:                              */
01814       /*  - number of ranks in injected group sequencer                       */
01815       /*  - external trigger to start conversion                              */
01816       /*  - external trigger polarity                                         */
01817
01818       /* Enable external trigger if trigger selection is different of         */
01819       /* software start.                                                      */
01820       /* Note: This configuration keeps the hardware feature of parameter     */
01821       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01822       /*       software start.                                                */
01823       if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01824          && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
01825       {
01826         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1)              |
01827                                              sConfigInjected->ExternalTrigInjecConv |
01828                                              sConfigInjected->ExternalTrigInjecConvEdge                            );
01829       }
01830       else
01831       {
01832         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
01833       }
01834
01835
01836     } /* if (hadc->InjectionConfig.ChannelCount == 0) */
01837
01838
01839     /* 2. Continue setting of context under definition with parameter       */
01840     /*    related to each channel: channel rank sequence                    */
01841     /* Clear the old JSQx bits for the selected rank */
01842     tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
01843
01844     /* Set the JSQx bits for the selected rank */
01845     tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
01846
01847     /* Decrease channel count  */
01848     hadc->InjectionConfig.ChannelCount--;
01849
01850
01851     /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
01852           call, aggregate the setting to those already built during the previous
01853           HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
01854     hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
01855
01856     /* 4. End of context setting: if this is the last channel set, then write context
01857         into register JSQR and make it enter into queue                   */
01858     if (hadc->InjectionConfig.ChannelCount == 0)
01859     {
01860       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
01861     }
01862
01863
01864   }
01865
01866   /* Parameters update conditioned to ADC state:                              */
01867   /* Parameters that can be updated when ADC is disabled or enabled without   */
01868   /* conversion on going on injected group:                                   */
01869   /*  - Injected context queue: Queue disable (active context is kept) or     */
01870   /*    enable (context decremented, up to 2 contexts queued)                 */
01871   /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
01872   /*    mode is disabled.                                                     */
01873   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01874   {
01875
01876     /* If auto-injected mode is disabled: no constraint                       */
01877     if (sConfigInjected->AutoInjectedConv == DISABLE)
01878     {
01879       MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
01880                                ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext)          |
01881                                ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
01882     }
01883     /* If auto-injected mode is enabled: Injected discontinuous setting is   */
01884     /* discarded.                                                             */
01885     else
01886     {
01887             MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
01888                                ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );
01889     }
01890
01891   }
01892
01893
01894   /* Parameters update conditioned to ADC state:                              */
01895   /* Parameters that can be updated when ADC is disabled or enabled without   */
01896   /* conversion on going on regular and injected groups:                      */
01897   /*  - Automatic injected conversion: can be enabled if injected group       */
01898   /*    external triggers are disabled.                                       */
01899   /*  - Channel sampling time                                                 */
01900   /*  - Channel offset                                                        */
01901   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
01902   {
01903     /* If injected group external triggers are disabled (set to injected      */
01904     /* software start): no constraint                                         */
01905     if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
01906        || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
01907     {
01908          if (sConfigInjected->AutoInjectedConv == ENABLE)
01909          {
01910            SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
01911          }
01912          else
01913          {
01914            CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
01915          }
01916     }
01917     /* If Automatic injected conversion was intended to be set and could not  */
01918     /* due to injected group external triggers enabled, error is reported.    */
01919     else
01920     {
01921       if (sConfigInjected->AutoInjectedConv == ENABLE)
01922       {
01923         /* Update ADC state machine to error */
01924         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01925
01926         tmp_status = HAL_ERROR;
01927       }
01928       else
01929       {
01930         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
01931       }
01932     }
01933
01934
01935
01936     if (sConfigInjected->InjecOversamplingMode == ENABLE)
01937     {
01938       assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
01939       assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
01940
01941       /*  JOVSE must be reset in case of triggered regular mode  */
01942       assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS)));
01943
01944       /* Configuration of Injected Oversampler:                                 */
01945       /*  - Oversampling Ratio                                                  */
01946       /*  - Right bit shift                                                     */
01947
01948       /* Enable OverSampling mode */
01949
01950        MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS,
01951                                  ADC_CFGR2_JOVSE                     |
01952                                  sConfigInjected->InjecOversampling.Ratio         |
01953                                  sConfigInjected->InjecOversampling.RightBitShift );
01954     }
01955     else
01956     {
01957       /* Disable Regular OverSampling */
01958        CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
01959     }
01960
01961
01962     /* Sampling time configuration of the selected channel */
01963     /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
01964     if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
01965     {
01966       /* Clear the old sample time and set the new one */
01967       ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
01968     }
01969     else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */
01970     {
01971      /* Clear the old sample time and set the new one */
01972       ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
01973     }
01974
01975
01976     /* Configure the offset: offset enable/disable, channel, offset value */
01977
01978     /* Shift the offset with respect to the selected ADC resolution. */
01979     /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
01980     tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
01981
01982     switch (sConfigInjected->InjectedOffsetNumber)
01983     {
01984     case ADC_OFFSET_1:
01985       /* Configure offset register 1:                                         */
01986       /* - Enable offset                                                      */
01987       /* - Set channel number                                                 */
01988       /* - Set offset value                                                   */
01989       MODIFY_REG(hadc->Instance->OFR1,
01990                 ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN,
01991                 ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
01992       break;
01993
01994     case ADC_OFFSET_2:
01995       /* Configure offset register 2:                                         */
01996       /* - Enable offset                                                      */
01997       /* - Set channel number                                                 */
01998       /* - Set offset value                                                   */
01999       MODIFY_REG(hadc->Instance->OFR2,
02000                 ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2_EN,
02001                 ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
02002       break;
02003
02004     case ADC_OFFSET_3:
02005       /* Configure offset register 3:                                         */
02006       /* - Enable offset                                                      */
02007       /* - Set channel number                                                 */
02008       /* - Set offset value                                                   */
02009       MODIFY_REG(hadc->Instance->OFR3,
02010                 ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3_EN,
02011                 ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
02012       break;
02013
02014     case ADC_OFFSET_4:
02015       /* Configure offset register 1:                                         */
02016       /* - Enable offset                                                      */
02017       /* - Set channel number                                                 */
02018       /* - Set offset value                                                   */
02019       MODIFY_REG(hadc->Instance->OFR4,
02020                 ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4_EN,
02021                 ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
02022       break;
02023
02024     /* Case ADC_OFFSET_NONE */
02025     default :
02026     /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */
02027       if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
02028       {
02029         /* Disable offset OFR1*/
02030         CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
02031       }
02032       if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
02033       {
02034         /* Disable offset OFR2*/
02035         CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
02036       }
02037       if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
02038       {
02039         /* Disable offset OFR3*/
02040         CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
02041       }
02042       if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
02043       {
02044         /* Disable offset OFR4*/
02045         CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
02046       }
02047       break;
02048     }
02049
02050   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
02051
02052
02053   /* Parameters update conditioned to ADC state:                              */
02054   /* Parameters that can be updated only when ADC is disabled:                */
02055   /*  - Single or differential mode                                           */
02056   /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
02057   if (ADC_IS_ENABLE(hadc) == RESET)
02058   {
02059     /* Configuration of differential mode */
02060     if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
02061     {
02062       /* Disable differential mode (default mode: single-ended) */
02063       CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
02064     }
02065     else
02066     {
02067       /* Enable differential mode */
02068       SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
02069
02070       /* Sampling time configuration of channel ADC_IN+1 (negative input).
02071          Starting from channel 9, SMPR2 register must be configured.      */
02072       if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9)
02073       {
02074         /* Clear the old sample time and set the new one */
02075         ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);
02076       }
02077       else /* For channels 0 to 8 */
02078       {
02079          /* Clear the old sample time and set the new one */
02080         ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);
02081       }
02082     }
02083
02084
02085     /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
02086     /* internal measurement paths enable: If internal channel selected,       */
02087     /* enable dedicated internal buffers and path.                            */
02088     /* Note: these internal measurement paths can be disabled using           */
02089     /* HAL_ADC_DeInit().                                                      */
02090
02091     /* Configuration of common ADC parameters                                 */
02092
02093     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
02094
02095     /* If the requested internal measurement path has already been enabled,   */
02096     /* bypass the configuration processing.                                   */
02097     if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
02098           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
02099         ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)       &&
02100           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
02101         ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)    &&
02102           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
02103        )
02104     {
02105       /* Configuration of common ADC parameters (continuation)                */
02106       /* Software is allowed to change common parameters only when all ADCs   */
02107       /* of the common group are disabled.                                    */
02108       if ((ADC_IS_ENABLE(hadc) == RESET)   &&
02109          (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
02110       {
02111         if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
02112         {
02113           if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
02114           {
02115             SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
02116
02117             /* Delay for temperature sensor stabilization time */
02118             /* Compute number of CPU cycles to wait for */
02119             wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
02120             while(wait_loop_index != 0)
02121             {
02122               wait_loop_index--;
02123             }
02124           }
02125         }
02126         else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
02127         {
02128           if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
02129           {
02130             SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
02131           }
02132         }
02133         else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
02134         {
02135           if (ADC_VREFINT_INSTANCE(hadc))
02136           {
02137             SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
02138           }
02139         }
02140       }
02141       /* If the requested internal measurement path has already been enabled  */
02142       /* and other ADC of the common group are enabled, internal              */
02143       /* measurement paths cannot be enabled.                                 */
02144       else
02145       {
02146         /* Update ADC state machine to error */
02147         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02148
02149         tmp_status = HAL_ERROR;
02150       }
02151     }
02152
02153   } /* if (ADC_IS_ENABLE(hadc) == RESET) */
02154
02155   /* Process unlocked */
02156   __HAL_UNLOCK(hadc);
02157
02158   /* Return function status */
02159   return tmp_status;
02160 }
02161
02162
02163
02164
02165 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
02166 /**
02167   * @brief  Enable ADC multimode and configure multimode parameters
02168   * @note   Possibility to update parameters on the fly:
02169   *         This function initializes multimode parameters, following
02170   *         calls to this function can be used to reconfigure some parameters
02171   *         of structure "ADC_MultiModeTypeDef" on the fly, without resetting
02172   *         the ADCs.
02173   *         The setting of these parameters is conditioned to ADC state.
02174   *         For parameters constraints, see comments of structure
02175   *         "ADC_MultiModeTypeDef".
02176   * @note   To move back configuration from multimode to single mode, ADC must
02177   *         be reset (using function HAL_ADC_Init() ).
02178   * @param  hadc: Master ADC handle
02179   * @param  multimode : Structure of ADC multimode configuration
02180   * @retval HAL status
02181   */
02182 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
02183 {
02184   HAL_StatusTypeDef  tmp_status = HAL_OK;
02185   ADC_Common_TypeDef *tmpADC_Common;
02186   ADC_HandleTypeDef  tmphadcSlave;
02187
02188   /* Check the parameters */
02189   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
02190   assert_param(IS_ADC_MULTIMODE(multimode->Mode));
02191   if(multimode->Mode != ADC_MODE_INDEPENDENT)
02192   {
02193     assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
02194     assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
02195   }
02196
02197   /* Process locked */
02198   __HAL_LOCK(hadc);
02199
02200   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
02201
02202   /* Parameters update conditioned to ADC state:                              */
02203   /* Parameters that can be updated when ADC is disabled or enabled without   */
02204   /* conversion on going on regular group:                                    */
02205   /*  - Multimode DMA configuration                                           */
02206   /*  - Multimode DMA mode                                                    */
02207   if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
02208     && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) )
02209   {
02210     /* Pointer to the common control register */
02211     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
02212
02213     /* If multimode is selected, configure all multimode paramaters.          */
02214     /* Otherwise, reset multimode parameters (can be used in case of          */
02215     /* transition from multimode to independent mode).                        */
02216     if(multimode->Mode != ADC_MODE_INDEPENDENT)
02217     {
02218       MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
02219                  multimode->DMAAccessMode |
02220                  ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests));
02221
02222       /* Parameters that can be updated only when ADC is disabled:                */
02223       /*  - Multimode mode selection                                              */
02224       /*  - Multimode delay                                                       */
02225       /*    Note: Delay range depends on selected resolution:                     */
02226       /*      from 1 to 12 clock cycles for 12 bits                               */
02227       /*      from 1 to 10 clock cycles for 10 bits,                              */
02228       /*      from 1 to 8 clock cycles for 8 bits                                 */
02229       /*      from 1 to 6 clock cycles for 6 bits                                 */
02230       /*    If a higher delay is selected, it will be clipped to maximum delay    */
02231       /*    range                                                                 */
02232       if ((ADC_IS_ENABLE(hadc) == RESET)                             &&
02233           (ADC_IS_ENABLE(&tmphadcSlave) == RESET)  )
02234       {
02235           MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY,
02236                      multimode->Mode | multimode->TwoSamplingDelay );
02237       }
02238     }
02239     else /* ADC_MODE_INDEPENDENT */
02240     {
02241       CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
02242
02243       /* Parameters that can be updated only when ADC is disabled:                */
02244       /*  - Multimode mode selection                                              */
02245       /*  - Multimode delay                                                       */
02246       if ((ADC_IS_ENABLE(hadc) == RESET)                             &&
02247           (ADC_IS_ENABLE(&tmphadcSlave) == RESET)  )
02248       {
02249         CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
02250       }
02251     }
02252   }
02253   /* If one of the ADC sharing the same common group is enabled, no update    */
02254   /* could be done on neither of the multimode structure parameters.          */
02255   else
02256   {
02257     /* Update ADC state machine to error */
02258     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02259
02260     tmp_status = HAL_ERROR;
02261   }
02262
02263
02264   /* Process unlocked */
02265   __HAL_UNLOCK(hadc);
02266
02267   /* Return function status */
02268   return tmp_status;
02269 }
02270 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
02271
02272
02273 /**
02274   * @brief  Enable Injected Queue
02275   * @note   This function resets CFGR register JQDIS bit in order to enable the
02276   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
02277   *         are both equal to 0 to ensure that no regular nor injected
02278   *         conversion is ongoing.
02279   * @param  hadc: ADC handle
02280   * @retval HAL status
02281   */
02282 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc)
02283 {
02284
02285   /* Parameter can be set only if no conversion is on-going                   */
02286   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02287   {
02288     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
02289
02290     /* Update state, clear previous result related to injected queue overflow */
02291     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
02292
02293     return HAL_OK;
02294   }
02295   else
02296   {
02297     return HAL_ERROR;
02298   }
02299
02300 }
02301
02302 /**
02303   * @brief  Disable Injected Queue
02304   * @note   This function sets CFGR register JQDIS bit in order to disable the
02305   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
02306   *         are both equal to 0 to ensure that no regular nor injected
02307   *         conversion is ongoing.
02308   * @param  hadc: ADC handle
02309   * @retval HAL status
02310   */
02311 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc)
02312 {
02313
02314   /* Parameter can be set only if no conversion is on-going                   */
02315   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02316   {
02317     SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
02318     return HAL_OK;
02319   }
02320   else
02321   {
02322     return HAL_ERROR;
02323   }
02324
02325 }
02326
02327
02328 /**
02329   * @brief  Disable ADC voltage regulator.
02330   * @note   Disabling voltage regulator allows to save power. This operation can
02331   *         be carried out only when ADC is disabled.
02332   * @note   To enable again the voltage regulator, the user is expected to
02333   *         resort to HAL_ADC_Init() API.
02334   * @param  hadc: ADC handle
02335   * @retval HAL status
02336   */
02337 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc)
02338 {
02339
02340   /* ADVREGEN can be written only when the ADC is disabled  */
02341   if (ADC_IS_ENABLE(hadc) == RESET)
02342   {
02343     CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
02344     return HAL_OK;
02345   }
02346   else
02347   {
02348     return HAL_ERROR;
02349   }
02350 }
02351
02352 /**
02353   * @brief  Enter ADC deep-power-down mode
02354   * @note   This mode is achieved in setting DEEPPWD bit and allows to save power
02355   *         in reducing leakage currents. It is particularly interesting before
02356   *         entering stop modes.
02357   * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
02358   *         ADC voltage regulator. This means that this API encompasses
02359   *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
02360   *         calibration is lost.
02361   * @note   To exit the ADC deep-power-down mode, the user is expected to
02362   *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
02363   *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
02364   *         saved calibration factor.
02365   * @param  hadc: ADC handle
02366   * @retval HAL status
02367   */
02368 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc)
02369 {
02370
02371   /* DEEPPWD can be written only when the ADC is disabled  */
02372   if (ADC_IS_ENABLE(hadc) == RESET)
02373   {
02374     SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
02375     return HAL_OK;
02376   }
02377   else
02378   {
02379     return HAL_ERROR;
02380   }
02381 }
02382
02383 /**
02384   * @}
02385   */
02386
02387 /**
02388   * @}
02389   */
02390
02391
02392
02393 #endif /* HAL_ADC_MODULE_ENABLED */
02394 /**
02395   * @}
02396   */
02397
02398 /**
02399   * @}
02400   */
02401
02402 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_adc_ex.h Source File

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stm32l4xx_hal_adc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_adc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of ADC HAL extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_ADC_EX_H
00040 #define __STM32L4xx_ADC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ADCEx ADCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  Structure definition of ADC initialization and regular group
00064   * @note   Parameters of this structure are shared within 2 scopes:
00065   *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler and ClockDivider, Resolution, DataAlign,
00066   *            ScanConvMode, EOCSelection, LowPowerAutoWait.
00067   *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge,
00068   *            ExternalTrigConv, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
00069   * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned by ADC state.
00070   *         ADC state can be either:
00071   *          - For all parameters: ADC disabled
00072   *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on regular group.
00073   *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups.
00074   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00075   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter
00076   *         (which fulfills the ADC state condition) on the fly).
00077   */
00078 typedef struct
00079 {
00080   uint32_t ClockPrescaler;        /*!< Selects ADC clock source (asynchronous System/PLLSAI1/PLLSAI2 clocks or synchronous AHB clock) as well as
00081                                        the division factor applied to the clock.
00082                                        This parameter can be a value of @ref ADC_ClockPrescaler.
00083                                        Note: The clock is common for all the ADCs.
00084                                        Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
00085                                              AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
00086                                        Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level.
00087                                        Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the AHB clock prescaler is set to 1
00088                                        and if the system clock has a 50% duty cycle.
00089                                        Note: This parameter can be modified only if all ADCs are disabled. */
00090
00091   uint32_t Resolution;            /*!< Configures the ADC resolution.
00092                                        This parameter can be a value of @ref ADC_Resolution */
00093
00094   uint32_t DataAlign;             /*!< Specifies ADC data alignment (right or left).
00095                                        See reference manual for alignments formats versus resolutions.
00096                                        This parameter can be a value of @ref ADC_Data_align */
00097
00098   uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
00099                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
00100                                        If disabled: Conversion is performed in single mode (one channel converted, that defined in rank 1).
00101                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
00102                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or'InjectedNbrOfConversion').
00103                                                     Scan direction is upward: from rank 1 to rank 'n'.
00104                                        This parameter can be a value of @ref ADC_Scan_mode */
00105
00106   uint32_t EOCSelection;          /*!< Specifies which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
00107                                        This parameter can be a value of @ref ADC_EOCSelection. */
00108
00109   uint32_t LowPowerAutoWait;      /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
00110                                        conversion (for regular group) or previous sequence (for injected group) has been processed by user software
00111                                        (EOC bit cleared or DR read for regular conversions, JEOS cleared for injected conversions).
00112                                        This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun
00113                                        for low frequency applications.
00114                                        This parameter can be set to ENABLE or DISABLE.
00115                                        Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(), HAL_ADCEx_InjectedStart_IT()) when it is necessary
00116                                        to clear immediately the EOC flag to free the IRQ vector sequencer.
00117                                        Do use with polling: 1. Start conversion with HAL_ADC_Start() or HAL_ADCEx_InjectedStart(), 2. When conversion data is available: use
00118                                        HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another
00119                                        conversion. For injected conversion, resort to HAL_ADCEx_InjectedPollForConversion() then HAL_ADCEx_InjectedGetValue() */
00120
00121   uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
00122                                        after software start or external trigger occurred.
00123                                        This parameter can be set to ENABLE or DISABLE. */
00124
00125   uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
00126                                        To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00127                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16.
00128                                        Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
00129                                        continuous mode or external trigger that could launch a conversion). */
00130
00131   uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence
00132                                        subdivided in successive parts).
00133                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00134                                        Discontinuous mode can be enabled only if continuous mode is disabled.
00135                                        This parameter can be set to ENABLE or DISABLE. */
00136
00137   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
00138                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
00139                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
00140
00141   uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
00142                                        If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
00143                                        This parameter can be a value of @ref ADC_Regular_External_Trigger_Source.
00144                                        Caution: external trigger source is common to ADCs.  */
00145
00146   uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
00147                                        If set to ADC_EXTERNALTRIGCONVEDGE_NONE, external triggers are disabled and software trigger is used instead.
00148                                        This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge */
00149
00150   uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
00151                                        or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
00152                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
00153                                        This parameter can be set to ENABLE or DISABLE.
00154                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups
00155                                        (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
00156
00157   uint32_t Overrun;               /*!< Select the behaviour in case of overrun: data overwritten or preserved (default).
00158                                        This parameter applies to regular group only.
00159                                        This parameter can be a value of @ref ADC_Overrun.
00160                                        Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear
00161                                        end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved by user-developped function
00162                                        HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear).
00163                                        Note: Error reporting with respect to the conversion mode:
00164                                         - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
00165                                           overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
00166                                         - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
00167
00168   uint32_t OversamplingMode;               /*!< Specifies whether the oversampling feature is enabled or disabled.
00169                                                 This parameter can be set to ENABLE or DISABLE.
00170                                                 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
00171
00172   ADC_OversamplingTypeDef  Oversampling;   /*!< Specifies the Oversampling parameters.
00173                                                 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
00174                                                 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
00175 }ADC_InitTypeDef;
00176
00177
00178 /**
00179   * @brief  ADC handle Structure definition
00180   */
00181 typedef struct
00182 {
00183   ADC_TypeDef                   *Instance;              /*!< Register base address */
00184
00185   ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
00186
00187   DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
00188
00189   HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
00190
00191   __IO uint32_t                 State;                  /*!< ADC communication state (bit-map of ADC states) */
00192
00193   __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
00194
00195   ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */
00196 }ADC_HandleTypeDef;
00197
00198
00199 /**
00200   * @brief  ADC Injected Conversion Oversampling structure definition
00201   */
00202 typedef struct
00203 {
00204   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
00205                                                This parameter can be a value of @ref ADCEx_Oversampling_Ratio */
00206
00207   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00208                                                This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
00209 }ADC_InjOversamplingTypeDef;
00210
00211
00212
00213 /**
00214   * @brief  Structure definition of ADC injected group and ADC channel for injected group
00215   * @note   Parameters of this structure are shared within 2 scopes:
00216   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
00217   *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
00218   *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv, InjecOversamplingMode, InjecOversampling.
00219   * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned by ADC state.
00220   *         ADC state can be either:
00221   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
00222   *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
00223   *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
00224   *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
00225   *            on regular and injected groups.
00226   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00227   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
00228   */
00229 typedef struct
00230 {
00231   uint32_t InjectedChannel;               /*!< Configure the ADC injected channel.
00232                                                This parameter can be a value of @ref ADC_channels
00233                                                 Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability. */
00234   uint32_t InjectedRank;                  /*!< The rank in the injected group sequencer.
00235                                                This parameter must be a value of @ref ADCEx_injected_rank.
00236                                                Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
00237                                                the new channel setting (or parameter number of conversions adjusted). */
00238   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
00239                                                Unit: ADC clock cycles.
00240                                                Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
00241                                                8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00242                                                This parameter can be a value of @ref ADC_sampling_times.
00243                                                Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00244                                                         It overwrites the last setting.
00245                                                Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00246                                                      sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time
00247                                                      setting). Refer to device DataSheet for timings values. */
00248   uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
00249                                                In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
00250                                                Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
00251                                                This parameter must be a value of @ref ADCEx_SingleDifferential.
00252                                                Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00253                                                         It overwrites the last setting.
00254                                                Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
00255                                                Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
00256                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00257                                                If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case
00258                                                of another parameter update on the fly) */
00259   uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
00260                                                This parameter can be a value of @ref ADCEx_OffsetNumber.
00261                                                Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
00262   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data.
00263                                                Offset value must be a positive number.
00264                                                Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
00265                                                0x3FF, 0xFF or 0x3F respectively.
00266                                                Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
00267                                                without continuous mode or external trigger that could launch a conversion). */
00268   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
00269                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00270                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
00271                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00272                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00273   uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence
00274                                                subdivided in successive parts).
00275                                                Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00276                                                Discontinuous mode can be enabled only if continuous mode is disabled.
00277                                                This parameter can be set to ENABLE or DISABLE.
00278                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00279                                                Note: For injected group, discontinuous mode converts the sequence channel by channel (only one channel at a time).
00280                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00281                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00282   uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
00283                                                This parameter can be set to ENABLE or DISABLE.
00284                                                Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
00285                                                Note: To use Automatic injected conversion, injected group external triggers must be disabled.
00286                                                Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
00287                                                      To maintain JAUTO always enabled, DMA must be configured in circular mode.
00288                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00289                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00290   uint32_t QueueInjectedContext;          /*!< Specifies whether the context queue feature is enabled.
00291                                                This parameter can be set to ENABLE or DISABLE.
00292                                                If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
00293                                                new injected context is set when queue is full, error is triggered by interruption and through function
00294                                                'HAL_ADCEx_InjectedQueueOverflowCallback'.
00295                                                Caution: This feature request that the sequence is fully configured before injected conversion start.
00296                                                         Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
00297                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00298                                                         configure a channel on injected group can impact the configuration of other channels previously set.
00299                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
00300   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
00301                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
00302                                                This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source.
00303                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00304                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00305   uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
00306                                                This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source_Edge.
00307                                                If trigger edge is set to ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, external triggers are disabled and software trigger is used instead.
00308                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00309                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00310
00311   uint32_t InjecOversamplingMode;             /*!< Specifies whether the oversampling feature is enabled or disabled.
00312                                               This parameter can be set to ENABLE or DISABLE.
00313                                               Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
00314
00315   ADC_InjOversamplingTypeDef  InjecOversampling;   /*!< Specifies the Oversampling parameters.
00316                                                    Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
00317                                                    Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
00318 }ADC_InjectionConfTypeDef;
00319
00320
00321 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00322 /**
00323   * @brief  Structure definition of ADC multimode
00324   * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
00325   *         Both Master and Slave ADCs must be disabled.
00326   */
00327 typedef struct
00328 {
00329   uint32_t Mode;              /*!< Configures the ADC to operate in independent or multimode.
00330                                    This parameter can be a value of @ref ADCEx_Common_mode. */
00331   uint32_t DMAAccessMode;     /*!< Configures the DMA mode for multimode ADC:
00332                                    selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
00333                                    This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode. */
00334   uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
00335                                    This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases.
00336                                    Delay range depends on selected resolution:
00337                                     from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
00338                                     from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits.     */
00339 }ADC_MultiModeTypeDef;
00340 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00341
00342 /**
00343   * @}
00344   */
00345
00346 /* Exported constants --------------------------------------------------------*/
00347
00348   /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
00349   * @{
00350   */
00351
00352 /** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
00353   * @{
00354   */
00355 #define ADC_SINGLE_ENDED                ((uint32_t)0x00000000)       /*!< ADC channel set in single-ended input mode */
00356 #define ADC_DIFFERENTIAL_ENDED          ((uint32_t)ADC_CR_ADCALDIF)  /*!< ADC channel set in differential mode       */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
00362   * @{
00363   */
00364 #define ADC_OFFSET_NONE               ((uint32_t)0x00)     /*!< No offset correction                           */
00365 #define ADC_OFFSET_1                  ((uint32_t)0x01)     /*!< Offset correction to apply to a first channel  */
00366 #define ADC_OFFSET_2                  ((uint32_t)0x02)     /*!< Offset correction to apply to a second channel */
00367 #define ADC_OFFSET_3                  ((uint32_t)0x03)     /*!< Offset correction to apply to a third channel  */
00368 #define ADC_OFFSET_4                  ((uint32_t)0x04)     /*!< Offset correction to apply to a fourth channel */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup ADCEx_regular_rank ADC Extended Regular Channel Rank
00374   * @{
00375   */
00376 #define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)       /*!< ADC regular conversion rank 1  */
00377 #define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)       /*!< ADC regular conversion rank 2  */
00378 #define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)       /*!< ADC regular conversion rank 3  */
00379 #define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)       /*!< ADC regular conversion rank 4  */
00380 #define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)       /*!< ADC regular conversion rank 5  */
00381 #define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)       /*!< ADC regular conversion rank 6  */
00382 #define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)       /*!< ADC regular conversion rank 7  */
00383 #define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)       /*!< ADC regular conversion rank 8  */
00384 #define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)       /*!< ADC regular conversion rank 9  */
00385 #define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)       /*!< ADC regular conversion rank 10 */
00386 #define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)       /*!< ADC regular conversion rank 11 */
00387 #define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)       /*!< ADC regular conversion rank 12 */
00388 #define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)       /*!< ADC regular conversion rank 13 */
00389 #define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)       /*!< ADC regular conversion rank 14 */
00390 #define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)       /*!< ADC regular conversion rank 15 */
00391 #define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)       /*!< ADC regular conversion rank 16 */
00392 /**
00393   * @}
00394   */
00395
00396 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
00397   * @{
00398   */
00399 #define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)      /*!< ADC injected conversion rank 1 */
00400 #define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)      /*!< ADC injected conversion rank 2 */
00401 #define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)      /*!< ADC injected conversion rank 3 */
00402 #define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)      /*!< ADC injected conversion rank 4 */
00403 /**injected
00404   * @}
00405   */
00406
00407 /** @defgroup ADCEx_Injected_External_Trigger_Source_Edge ADC External Trigger Source Edge for Injected Group
00408   * @{
00409   */
00410 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           ((uint32_t)0x00000000)          /*!< Injected conversions hardware trigger detection disabled                             */
00411 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_JSQR_JEXTEN_0)   /*!< Injected conversions hardware trigger detection on the rising edge                   */
00412 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        ((uint32_t)ADC_JSQR_JEXTEN_1)   /*!< Injected conversions hardware trigger detection on the falling edge                  */
00413 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  ((uint32_t)ADC_JSQR_JEXTEN)     /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup ADCEx_Injected_External_Trigger_Source ADC Extended External Trigger Source for Injected Group
00419   * @{
00420   */
00421 #define ADC_EXTERNALTRIGINJEC_T1_TRGO    ((uint32_t)0x00000000)                                                     /*!< Event 0 triggers injected group conversion start  */
00422 #define ADC_EXTERNALTRIGINJEC_T1_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_0)                                             /*!< Event 1 triggers injected group conversion start  */
00423 #define ADC_EXTERNALTRIGINJEC_T2_TRGO    ((uint32_t)ADC_JSQR_JEXTSEL_1)                                             /*!< Event 2 triggers injected group conversion start  */
00424 #define ADC_EXTERNALTRIGINJEC_T2_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))                      /*!< Event 3 triggers injected group conversion start  */
00425 #define ADC_EXTERNALTRIGINJEC_T3_CC4     ((uint32_t)ADC_JSQR_JEXTSEL_2)                                             /*!< Event 4 triggers injected group conversion start  */
00426 #define ADC_EXTERNALTRIGINJEC_T4_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))                      /*!< Event 5 triggers injected group conversion start  */
00427 #define ADC_EXTERNALTRIGINJEC_EXT_IT15   ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))                      /*!< Event 6 triggers injected group conversion start  */
00428 #define ADC_EXTERNALTRIGINJEC_T8_CC4     ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 7 triggers injected group conversion start  */
00429 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2   ((uint32_t)ADC_JSQR_JEXTSEL_3)                                             /*!< Event 8 triggers injected group conversion start  */
00430 #define ADC_EXTERNALTRIGINJEC_T8_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))                      /*!< Event 9 triggers injected group conversion start  */
00431 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2   ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))                      /*!< Event 10 triggers injected group conversion start */
00432 #define ADC_EXTERNALTRIGINJEC_T3_CC3     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 11 triggers injected group conversion start */
00433 #define ADC_EXTERNALTRIGINJEC_T3_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))                      /*!< Event 12 triggers injected group conversion start */
00434 #define ADC_EXTERNALTRIGINJEC_T3_CC1     ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 13 triggers injected group conversion start */
00435 #define ADC_EXTERNALTRIGINJEC_T6_TRGO    ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 14 triggers injected group conversion start */
00436 #define ADC_EXTERNALTRIGINJEC_T15_TRGO   ((uint32_t)ADC_JSQR_JEXTSEL)                                               /*!< Event 15 triggers injected group conversion start */
00437
00438 #define ADC_INJECTED_SOFTWARE_START      ((uint32_t)0x00000001)                                                     /*!< Software triggers injected group conversion start */
00439 /**
00440   * @}
00441   */
00442
00443 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00444 /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
00445   * @{
00446   */
00447 #define ADC_MODE_INDEPENDENT                  ((uint32_t)(0x00000000))                                       /*!< Independent ADC conversions mode                           */
00448 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)(ADC_CCR_DUAL_0))                                   /*!< Combined regular simultaneous + injected simultaneous mode */
00449 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)(ADC_CCR_DUAL_1))                                   /*!< Combined regular simultaneous + alternate trigger mode     */
00450 #define ADC_DUALMODE_REGINTERL_INJECSIMULT    ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0))                  /*!< Combined Interleaved mode + injected simultaneous mode     */
00451 #define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0))                  /*!< Injected simultaneous mode only                            */
00452 #define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1))                  /*!< Regular simultaneous mode only                             */
00453 #define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Interleaved mode only                                      */
00454 #define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0))                  /*!< Alternate trigger mode only                                */
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
00460   * @{
00461   */
00462 #define ADC_DMAACCESSMODE_DISABLED      ((uint32_t)0x00000000)       /*!< DMA multimode disabled: each ADC uses its own DMA channel */
00463 #define ADC_DMAACCESSMODE_12_10_BITS    ((uint32_t)ADC_CCR_MDMA_1)   /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
00464 #define ADC_DMAACCESSMODE_8_6_BITS      ((uint32_t)ADC_CCR_MDMA)     /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
00465 /**
00466   * @}
00467   */
00468
00469 /** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
00470   * @{
00471   */
00472 #define ADC_TWOSAMPLINGDELAY_1CYCLE     ((uint32_t)(0x00000000))                                          /*!< 1 ADC clock cycle delay                                     */
00473 #define ADC_TWOSAMPLINGDELAY_2CYCLES    ((uint32_t)(ADC_CCR_DELAY_0))                                     /*!< 2 ADC clock cycles delay                                    */
00474 #define ADC_TWOSAMPLINGDELAY_3CYCLES    ((uint32_t)(ADC_CCR_DELAY_1))                                     /*!< 3 ADC clock cycles delay                                    */
00475 #define ADC_TWOSAMPLINGDELAY_4CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))                   /*!< 4 ADC clock cycles delay                                    */
00476 #define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)(ADC_CCR_DELAY_2))                                     /*!< 5 ADC clock cycles delay                                    */
00477 #define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))                   /*!< 6 ADC clock cycles delay                                    */
00478 #define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))                   /*!< 7 ADC clock cycles delay (lower for non 12-bit resolution)  */
00479 #define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 8 ADC clock cycles delay (lower for non 12-bit resolution)  */
00480 #define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)(ADC_CCR_DELAY_3))                                     /*!< 9 ADC clock cycles delay (lower for non 12-bit resolution)  */
00481 #define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))                   /*!< 10 ADC clock cycles delay (lower for non 12-bit resolution) */
00482 #define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))                   /*!< 11 ADC clock cycles delay (lower for non 12-bit resolution) */
00483 #define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 12 ADC clock cycles delay (lower for non 12-bit resolution) */
00484 /**
00485   * @}
00486   */
00487 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00488 /** @defgroup ADCEx_Common_mode ADC Extended Independent ADC Mode
00489   * @{
00490   */
00491 #define ADC_MODE_INDEPENDENT                  ((uint32_t)(0x00000000))                                       /*!< Independent ADC conversions mode                           */
00492 /**
00493   * @}
00494   */
00495
00496 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00497
00498 /** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
00499   * @{
00500   */
00501 #define ADC_ANALOGWATCHDOG_1                    ((uint32_t)0x00000001)   /*!< Analog watchdog 1 selection */
00502 #define ADC_ANALOGWATCHDOG_2                    ((uint32_t)0x00000002)   /*!< Analog watchdog 2 selection */
00503 #define ADC_ANALOGWATCHDOG_3                    ((uint32_t)0x00000003)   /*!< Analog watchdog 3 selection */
00504 /**
00505   * @}
00506   */
00507
00508 /** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
00509   * @{
00510   */
00511 #define ADC_ANALOGWATCHDOG_NONE                 ((uint32_t) 0x00000000)                                             /*!< No analog watchdog selected                                             */
00512 #define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))                    /*!< Analog watchdog applied to a regular group single channel               */
00513 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))                   /*!< Analog watchdog applied to an injected group single channel             */
00514 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to a regular and injected groups single channel */
00515 #define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CFGR_AWD1EN)                                        /*!< Analog watchdog applied to regular group all channels                   */
00516 #define ADC_ANALOGWATCHDOG_ALL_INJEC            ((uint32_t) ADC_CFGR_JAWD1EN)                                       /*!< Analog watchdog applied to injected group all channels                  */
00517 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC         ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))                    /*!< Analog watchdog applied to regular and injected groups all channels     */
00518 /**
00519   * @}
00520   */
00521
00522 /** @defgroup ADCEx_conversion_group ADC Extended Conversion Group
00523   * @{
00524   */
00525 #define ADC_REGULAR_GROUP             ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))                                 /*!< ADC regular group selection               */
00526 #define ADC_INJECTED_GROUP            ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))                               /*!< ADC injected group selection              */
00527 #define ADC_REGULAR_INJECTED_GROUP    ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC regular and injected groups selection */
00528 /**
00529   * @}
00530   */
00531
00532 /** @defgroup ADCEx_Event_type ADC Extended Event Type
00533   * @{
00534   */
00535 #define ADC_EOSMP_EVENT          ((uint32_t)ADC_FLAG_EOSMP) /*!< ADC End of Sampling event                                */
00536 #define ADC_AWD1_EVENT           ((uint32_t)ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog)       */
00537 #define ADC_AWD2_EVENT           ((uint32_t)ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
00538 #define ADC_AWD3_EVENT           ((uint32_t)ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
00539 #define ADC_OVR_EVENT            ((uint32_t)ADC_FLAG_OVR)   /*!< ADC overrun event                                        */
00540 #define ADC_JQOVF_EVENT          ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event                */
00541
00542 #define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
00543 /**
00544   * @}
00545   */
00546
00547 /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
00548   * @{
00549   */
00550 #define ADC_IT_RDY           ADC_IER_ADRDY      /*!< ADC Ready (ADRDY) interrupt source */
00551 #define ADC_IT_EOSMP         ADC_IER_EOSMP      /*!< ADC End of sampling interrupt source */
00552 #define ADC_IT_EOC           ADC_IER_EOC        /*!< ADC End of regular conversion interrupt source */
00553 #define ADC_IT_EOS           ADC_IER_EOS        /*!< ADC End of regular sequence of conversions interrupt source */
00554 #define ADC_IT_OVR           ADC_IER_OVR        /*!< ADC overrun interrupt source */
00555 #define ADC_IT_JEOC          ADC_IER_JEOC       /*!< ADC End of injected conversion interrupt source */
00556 #define ADC_IT_JEOS          ADC_IER_JEOS       /*!< ADC End of injected sequence of conversions interrupt source */
00557 #define ADC_IT_AWD1          ADC_IER_AWD1       /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
00558 #define ADC_IT_AWD2          ADC_IER_AWD2       /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
00559 #define ADC_IT_AWD3          ADC_IER_AWD3       /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
00560 #define ADC_IT_JQOVF         ADC_IER_JQOVF      /*!< ADC Injected Context Queue Overflow interrupt source */
00561
00562 #define ADC_IT_AWD           ADC_IT_AWD1        /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
00563
00564 /**
00565   * @}
00566   */
00567
00568 /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
00569   * @{
00570   */
00571 #define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready (ADRDY) flag */
00572 #define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
00573 #define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
00574 #define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
00575 #define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
00576 #define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
00577 #define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
00578 #define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
00579 #define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
00580 #define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
00581 #define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
00582
00583 #define ADC_FLAG_AWD           ADC_FLAG_AWD1    /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */
00584
00585 #define ADC_FLAG_ALL    (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS |  \
00586                          ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
00587                          ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)   /*!< ADC all flags */
00588
00589 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
00590 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS  | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
00591                                ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
00592                                ADC_FLAG_JQOVF)                             /*!< ADC post-conversion all flags */
00593
00594 /**
00595   * @}
00596   */
00597
00598
00599 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
00600   * @{
00601   */
00602 #define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)   /*!< ADC injected conversion rank 1 */
00603 #define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)   /*!< ADC injected conversion rank 2 */
00604 #define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)   /*!< ADC injected conversion rank 3 */
00605 #define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)   /*!< ADC injected conversion rank 4 */
00606 /**
00607   * @}
00608   */
00609
00610
00611
00612 /** @defgroup ADCEx_Oversampling_Ratio    ADC Extended Oversampling Ratio
00613   * @{
00614   */
00615
00616 #define ADC_OVERSAMPLING_RATIO_2      ((uint32_t)0x00000000)                            /*!<  ADC Oversampling ratio 2x   */
00617 #define ADC_OVERSAMPLING_RATIO_4      ((uint32_t)ADC_CFGR2_OVSR_0)                      /*!<  ADC Oversampling ratio 4x   */
00618 #define ADC_OVERSAMPLING_RATIO_8      ((uint32_t)ADC_CFGR2_OVSR_1)                      /*!<  ADC Oversampling ratio 8x   */
00619 #define ADC_OVERSAMPLING_RATIO_16     ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)) /*!<  ADC Oversampling ratio 16x  */
00620 #define ADC_OVERSAMPLING_RATIO_32     ((uint32_t)ADC_CFGR2_OVSR_2)                      /*!<  ADC Oversampling ratio 32x  */
00621 #define ADC_OVERSAMPLING_RATIO_64     ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)) /*!<  ADC Oversampling ratio 64x  */
00622 #define ADC_OVERSAMPLING_RATIO_128    ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)) /*!<  ADC Oversampling ratio 128x */
00623 #define ADC_OVERSAMPLING_RATIO_256    ((uint32_t)(ADC_CFGR2_OVSR))                      /*!<  ADC Oversampling ratio 256x */
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup ADCEx_Right_Bit_Shift   ADC Extended Oversampling Right Shift
00629   * @{
00630   */
00631 #define ADC_RIGHTBITSHIFT_NONE  ((uint32_t)0x00000000)                                               /*!<  ADC No bit shift for oversampling */
00632 #define ADC_RIGHTBITSHIFT_1     ((uint32_t)ADC_CFGR2_OVSS_0)                                         /*!<  ADC 1 bit shift for oversampling  */
00633 #define ADC_RIGHTBITSHIFT_2     ((uint32_t)ADC_CFGR2_OVSS_1)                                         /*!<  ADC 2 bits shift for oversampling */
00634 #define ADC_RIGHTBITSHIFT_3     ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0))                    /*!<  ADC 3 bits shift for oversampling */
00635 #define ADC_RIGHTBITSHIFT_4     ((uint32_t)ADC_CFGR2_OVSS_2)                                         /*!<  ADC 4 bits shift for oversampling */
00636 #define ADC_RIGHTBITSHIFT_5     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0))                    /*!<  ADC 5 bits shift for oversampling */
00637 #define ADC_RIGHTBITSHIFT_6     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1))                    /*!<  ADC 6 bits shift for oversampling */
00638 #define ADC_RIGHTBITSHIFT_7     ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!<  ADC 7 bits shift for oversampling */
00639 #define ADC_RIGHTBITSHIFT_8     ((uint32_t)ADC_CFGR2_OVSS_3)                                         /*!<  ADC 8 bits shift for oversampling */
00640 /**
00641   * @}
00642   */
00643
00644 /** @defgroup ADCEx_Triggered_Oversampling_Mode   ADC Extended Triggered Regular Oversampling
00645   * @{
00646   */
00647 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER      ((uint32_t)0x00000000)      /*!<  A single trigger for all channel oversampled conversions */
00648 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER       ((uint32_t)ADC_CFGR2_TROVS) /*!<  A trigger for each oversampled conversion                */
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup ADCEx_Regular_Oversampling_Mode   ADC Extended Regular Oversampling Continued or Resumed Mode
00654   * @{
00655   */
00656 #define ADC_REGOVERSAMPLING_CONTINUED_MODE    ((uint32_t)0x00000000)      /*!<  Oversampling buffer maintained during injection sequence */
00657 #define ADC_REGOVERSAMPLING_RESUMED_MODE      ((uint32_t)ADC_CFGR2_ROVSM) /*!<  Oversampling buffer zeroed during injection sequence     */
00658 /**
00659   * @}
00660   */
00661
00662 /** @defgroup ADC_sampling_times ADC Sampling Times
00663   * @{
00664   */
00665 #define ADC_SAMPLETIME_2CYCLES_5       ((uint32_t)0x00000000)                             /*!< Sampling time 2.5 ADC clock cycle    */
00666 #define ADC_SAMPLETIME_6CYCLES_5      ((uint32_t)ADC_SMPR2_SMP10_0)                       /*!< Sampling time 6.5 ADC clock cycles   */
00667 #define ADC_SAMPLETIME_12CYCLES_5     ((uint32_t)ADC_SMPR2_SMP10_1)                       /*!< Sampling time 12.5 ADC clock cycles  */
00668 #define ADC_SAMPLETIME_24CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 24.5 ADC clock cycles  */
00669 #define ADC_SAMPLETIME_47CYCLES_5     ((uint32_t)ADC_SMPR2_SMP10_2)                       /*!< Sampling time 47.5 ADC clock cycles  */
00670 #define ADC_SAMPLETIME_92CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 92.5 ADC clock cycles  */
00671 #define ADC_SAMPLETIME_247CYCLES_5    ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 247.5 ADC clock cycles */
00672 #define ADC_SAMPLETIME_640CYCLES_5    ((uint32_t)ADC_SMPR2_SMP10)                         /*!< Sampling time 640.5 ADC clock cycles */
00673 /**
00674   * @}
00675   */
00676
00677 /** @defgroup ADC_CFGR_fields ADCx CFGR fields
00678   * @{
00679   */
00680 #define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
00681                             ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
00682                             ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
00683                             ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
00684                             ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
00685                             ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )
00686 /**
00687   * @}
00688   */
00689
00690 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
00691   * @{
00692   */
00693 #define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
00694                              ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
00695                              ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
00696                              ADC_SMPR1_SMP0)
00697 /**
00698   * @}
00699   */
00700
00701 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
00702   * @{
00703   */
00704 /* ADC_CFGR fields of parameters that can be updated when no conversion
00705    (neither regular nor injected) is on-going  */
00706 #define ADC_CFGR_FIELDS_2  ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
00707 /**
00708   * @}
00709   */
00710
00711 /**
00712   * @}
00713   */
00714
00715
00716
00717 /* Private macros -----------------------------------------------------------*/
00718
00719 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
00720   * @{
00721   */
00722
00723 /**
00724   * @brief Test if conversion trigger of injected group is software start
00725   *        or external trigger.
00726   * @param __HANDLE__: ADC handle.
00727   * @retval SET (software start) or RESET (external trigger).
00728   */
00729 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                       \
00730        (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
00731
00732 /**
00733   * @brief Check if conversion is on going on regular or injected groups.
00734   * @param __HANDLE__: ADC handle.
00735   * @retval SET (conversion is on going) or RESET (no conversion is on going).
00736   */
00737 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)                    \
00738        (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET  \
00739         ) ? RESET : SET)
00740
00741
00742 /**
00743   * @brief Check if conversion is on going on injected group.
00744   * @param __HANDLE__: ADC handle.
00745   * @retval SET (conversion is on going) or RESET (no conversion is on going).
00746   */
00747 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)                   \
00748        (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET            \
00749         ) ? RESET : SET)
00750
00751
00752
00753 /**
00754   * @brief Check whether or not ADC is independent.
00755   * @param __HANDLE__: ADC handle.
00756   * @note  When multimode feature is not available, the macro always returns SET.
00757   * @retval SET (ADC is independent) or RESET (ADC is not).
00758   */
00759 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00760 #define ADC_IS_INDEPENDENT(__HANDLE__)    \
00761   ( ( ( ((__HANDLE__)->Instance) == ADC3) \
00762     )?                                    \
00763      SET                                  \
00764      :                                    \
00765      RESET                                \
00766   )
00767 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00768 #define ADC_IS_INDEPENDENT(__HANDLE__)   (SET)
00769 #endif
00770
00771
00772 /**
00773   * @brief Set the sample time for Channels numbers between 0 and 9.
00774   * @param __SAMPLETIME__: Sample time parameter.
00775   * @param __CHANNELNB__: Channel number.
00776   * @retval None
00777   */
00778 #define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
00779
00780 /**
00781   * @brief Set the sample time for Channels numbers between 10 and 18.
00782   * @param __SAMPLETIME__: Sample time parameter.
00783   * @param __CHANNELNB__: Channel number.
00784   * @retval None
00785   */
00786 #define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
00787
00788 /**
00789   * @brief Write SMPR1 register.
00790   * @param __HANDLE__    : ADC handle.
00791   * @param __SAMPLETIME__: Sample time parameter.
00792   * @param __CHANNELNB__ : Channel number.
00793   * @retval None
00794   */
00795 #define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)           \
00796                     MODIFY_REG((__HANDLE__)->Instance->SMPR1,                  \
00797                                ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)),     \
00798                                ADC_SMPR1((__SAMPLETIME__), (__CHANNELNB__)))
00799
00800 /**
00801   * @brief Write SMPR2 register.
00802   * @param __HANDLE__    : ADC handle.
00803   * @param __SAMPLETIME__: Sample time parameter.
00804   * @param __CHANNELNB__ : Channel number.
00805   * @retval None
00806   */
00807 #define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__)           \
00808                     MODIFY_REG((__HANDLE__)->Instance->SMPR2,                  \
00809                                ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)),    \
00810                                ADC_SMPR2((__SAMPLETIME__), (__CHANNELNB__)))
00811
00812
00813 /**
00814   * @brief Set the selected regular Channel rank for rank between 1 and 4.
00815   * @param __CHANNELNB__: Channel number.
00816   * @param __RANKNB__: Rank number.
00817   * @retval None
00818   */
00819 #define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
00820
00821 /**
00822   * @brief Set the selected regular Channel rank for rank between 5 and 9.
00823   * @param __CHANNELNB__: Channel number.
00824   * @param __RANKNB__: Rank number.
00825   * @retval None
00826   */
00827 #define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
00828
00829 /**
00830   * @brief Set the selected regular Channel rank for rank between 10 and 14.
00831   * @param __CHANNELNB__: Channel number.
00832   * @param __RANKNB__: Rank number.
00833   * @retval None
00834   */
00835 #define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
00836
00837 /**
00838   * @brief Set the selected regular Channel rank for rank between 15 and 16.
00839   * @param __CHANNELNB__: Channel number.
00840   * @param __RANKNB__: Rank number.
00841   * @retval None
00842   */
00843 #define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
00844
00845 /**
00846   * @brief Set the selected injected Channel rank.
00847   * @param __CHANNELNB__: Channel number.
00848   * @param __RANKNB__: Rank number.
00849   * @retval None
00850   */
00851 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2))
00852
00853
00854 /**
00855   * @brief Set the Analog Watchdog 1 channel.
00856   * @param __CHANNEL__: channel to be monitored by Analog Watchdog 1.
00857   * @retval None
00858   */
00859 #define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
00860
00861 /**
00862   * @brief Configure the channel number in Analog Watchdog 2 or 3.
00863   * @param __CHANNEL__: ADC Channel
00864   * @retval None
00865   */
00866 #define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
00867
00868 /**
00869   * @brief Configure ADC injected context queue
00870   * @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode.
00871   * @retval None
00872   */
00873 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
00874
00875 /**
00876   * @brief Configure ADC discontinuous conversion mode for injected group
00877   * @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode.
00878   * @retval None
00879   */
00880 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) <<  POSITION_VAL(ADC_CFGR_JDISCEN))
00881
00882 /**
00883   * @brief Configure ADC discontinuous conversion mode for regular group
00884   * @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode.
00885   * @retval None
00886   */
00887 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
00888 /**
00889   * @brief Configure the number of discontinuous conversions for regular group.
00890   * @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions.
00891   * @retval None
00892   */
00893 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
00894
00895 /**
00896   * @brief Configure the ADC auto delay mode.
00897   * @param __AUTOWAIT__: Auto delay bit enable or disable.
00898   * @retval None
00899   */
00900 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
00901
00902 /**
00903   * @brief Configure ADC continuous conversion mode.
00904   * @param __CONTINUOUS_MODE__: Continuous mode.
00905   * @retval None
00906   */
00907 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
00908
00909 /**
00910   * @brief Configure the ADC DMA continuous request.
00911   * @param __DMACONTREQ_MODE__: DMA continuous request mode.
00912   * @retval None
00913   */
00914 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) <<  POSITION_VAL(ADC_CFGR_DMACFG))
00915
00916
00917 /**
00918   * @brief Configure the channel number into offset OFRx register.
00919   * @param __CHANNEL__: ADC Channel.
00920   * @retval None
00921   */
00922 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
00923
00924 /**
00925   * @brief Configure the channel number into differential mode selection register.
00926   * @param __CHANNEL__: ADC Channel.
00927   * @retval None
00928   */
00929 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
00930
00931 /**
00932   * @brief Configure calibration factor in differential mode to be set into calibration register.
00933   * @param __CALIBRATION_FACTOR__: Calibration factor value.
00934   * @retval None
00935   */
00936 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
00937 /**
00938   * @brief Calibration factor in differential mode to be retrieved from calibration register.
00939   * @param __CALIBRATION_FACTOR__: Calibration factor value.
00940   * @retval None
00941   */
00942 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
00943
00944 /**
00945   * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
00946   * @param __THRESHOLD__: Threshold value.
00947   * @retval None
00948   */
00949 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
00950
00951 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00952 /**
00953   * @brief Configure the ADC DMA continuous request for ADC multimode.
00954   * @param __DMACONTREQ_MODE__: DMA continuous request mode.
00955   * @retval None
00956   */
00957 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
00958 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00959
00960 /**
00961   * @brief Enable the ADC peripheral.
00962   * @param __HANDLE__: ADC handle.
00963   * @retval None
00964   */
00965 #define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
00966
00967 /**
00968   * @brief Verification of hardware constraints before ADC can be enabled.
00969   * @param __HANDLE__: ADC handle.
00970   * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
00971   */
00972 #define ADC_ENABLING_CONDITIONS(__HANDLE__)                             \
00973        (( ( ((__HANDLE__)->Instance->CR) &                                    \
00974             (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART |  \
00975              ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN                    ) \
00976            ) == RESET                                                         \
00977         ) ? SET : RESET)
00978
00979 /**
00980   * @brief Disable the ADC peripheral.
00981   * @param __HANDLE__: ADC handle.
00982   * @retval None
00983   */
00984 #define ADC_DISABLE(__HANDLE__)                                          \
00985   do{                                                                          \
00986          (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS;                           \
00987           __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
00988   } while(0)
00989
00990 /**
00991   * @brief Verification of hardware constraints before ADC can be disabled.
00992   * @param __HANDLE__: ADC handle.
00993   * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
00994   */
00995 #define ADC_DISABLING_CONDITIONS(__HANDLE__)                             \
00996        (( ( ((__HANDLE__)->Instance->CR) &                                     \
00997             (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
00998         ) ? SET : RESET)
00999
01000
01001 /**
01002   * @brief Shift the offset with respect to the selected ADC resolution.
01003   * @note   Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
01004   *         If resolution 12 bits, no shift.
01005   *         If resolution 10 bits, shift of 2 ranks on the left.
01006   *         If resolution 8 bits, shift of 4 ranks on the left.
01007   *         If resolution 6 bits, shift of 6 ranks on the left.
01008   *         Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
01009   * @param __HANDLE__: ADC handle
01010   * @param __OFFSET__: Value to be shifted
01011   * @retval None
01012   */
01013 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
01014         ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
01015
01016
01017 /**
01018   * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
01019   * @note  Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
01020   *        If resolution 12 bits, no shift.
01021   *        If resolution 10 bits, shift of 2 ranks on the left.
01022   *        If resolution 8 bits, shift of 4 ranks on the left.
01023   *        If resolution 6 bits, shift of 6 ranks on the left.
01024   *        Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
01025   * @param __HANDLE__: ADC handle
01026   * @param __THRESHOLD__: Value to be shifted
01027   * @retval None
01028   */
01029 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
01030         ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
01031
01032 /**
01033   * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
01034   * @note  Thresholds have to be left-aligned on bit 7.
01035   *        If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
01036   *        If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
01037   *        If resolution 8 bits, no shift.
01038   *        If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
01039   * @param __HANDLE__: ADC handle
01040   * @param __THRESHOLD__: Value to be shifted
01041   * @retval None
01042   */
01043 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
01044          ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
01045             ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
01046             (__THRESHOLD__) << 2 )
01047
01048
01049 /**
01050   * @brief Report ADC common register.
01051   * @param __HANDLE__: ADC handle.
01052   * @retval Common control register
01053   */
01054 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01055 #define ADC_COMMON_REGISTER(__HANDLE__)   (ADC123_COMMON)
01056 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01057 #define ADC_COMMON_REGISTER(__HANDLE__)   (ADC1_COMMON)
01058 #endif
01059
01060 /**
01061   * @brief Report Master Instance.
01062   * @param __HANDLE__: ADC handle.
01063   * @note Return same instance if ADC of input handle is independent ADC or if
01064   *       multimode feature is not available.
01065   * @retval Master Instance
01066   */
01067 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01068 #define ADC_MASTER_REGISTER(__HANDLE__)                                          \
01069   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
01070     )?                                                                           \
01071      ((__HANDLE__)->Instance)                                                    \
01072      :                                                                           \
01073      (ADC1)                                                                      \
01074   )
01075 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01076 #define ADC_MASTER_REGISTER(__HANDLE__)   ((__HANDLE__)->Instance)
01077 #endif
01078
01079
01080 /**
01081   * @brief Clear Common Control Register.
01082   * @param __HANDLE__: ADC handle.
01083   * @retval None
01084   */
01085 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01086 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \
01087                                                                                                       ADC_CCR_PRESC  | \
01088                                                                                                       ADC_CCR_VBATEN | \
01089                                                                                                       ADC_CCR_TSEN   | \
01090                                                                                                       ADC_CCR_VREFEN | \
01091                                                                                                       ADC_CCR_MDMA   | \
01092                                                                                                       ADC_CCR_DMACFG | \
01093                                                                                                       ADC_CCR_DELAY  | \
01094                                                                                                       ADC_CCR_DUAL  )
01095 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01096 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \
01097                                                                                                       ADC_CCR_PRESC  | \
01098                                                                                                       ADC_CCR_VBATEN | \
01099                                                                                                       ADC_CCR_TSEN   | \
01100                                                                                                       ADC_CCR_VREFEN )
01101 #endif
01102
01103
01104 /**
01105   * @brief Check whether or not dual conversions are enabled.
01106   * @param __HANDLE__: ADC handle.
01107   * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
01108   * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
01109   */
01110 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01111 #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__)                                \
01112   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
01113     )?                                                                           \
01114      ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)  )          \
01115      :                                                                           \
01116      RESET                                                                       \
01117   )
01118 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01119 #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__)    (RESET)
01120 #endif
01121
01122 /**
01123   * @brief Check whether or not dual regular conversions are enabled.
01124   * @param __HANDLE__: ADC handle.
01125   * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
01126   * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
01127   */
01128 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01129 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)                        \
01130   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
01131     )?                                                                           \
01132      ( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)     &&      \
01133        (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) &&      \
01134        (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) )         \
01135      :                                                                           \
01136      RESET                                                                       \
01137   )
01138 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01139 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)    (RESET)
01140 #endif
01141
01142
01143 /**
01144   * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.
01145   * @param __HANDLE__: ADC handle.
01146   * @note Return SET if multimode feature is not available.
01147   * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode)
01148   */
01149 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01150 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
01151   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)     \
01152     )?                                                                         \
01153      SET                                                                       \
01154      :                                                                         \
01155      ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
01156   )
01157 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01158 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)    (SET)
01159 #endif
01160
01161 /**
01162   * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
01163   * @param __HANDLE__: ADC handle.
01164   * @note Return SET if multimode feature is not available.
01165   * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
01166   */
01167 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01168 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \
01169   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)  \
01170     )?                                                                      \
01171      SET                                                                    \
01172      :                                                                      \
01173      ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
01174        ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
01175        ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
01176 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01177 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)    (SET)
01178 #endif
01179
01180 /**
01181   * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
01182   * @param __HANDLE__: ADC handle.
01183   * @note Return SET if multimode feature is not available.
01184   * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
01185   */
01186 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01187 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)          \
01188   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
01189     )?                                                                     \
01190      SET                                                                   \
01191      :                                                                     \
01192      ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
01193        ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
01194        ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
01195 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01196 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)    (SET)
01197 #endif
01198
01199 /**
01200   * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
01201   * @param __INSTANCE__: ADC instance.
01202   * @retval SET (ADC enabled) or RESET (ADC disabled)
01203   */
01204 #define ADC_INSTANCE_IS_ENABLED(__INSTANCE__)                                       \
01205        (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
01206           ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
01207         ) ? SET : RESET)
01208
01209 /**
01210   * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
01211   * @param __HANDLE__: ADC handle.
01212   * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)
01213   */
01214 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01215 #define ADC_ANY_OTHER_ENABLED(__HANDLE__)                                   \
01216   ( ( ((__HANDLE__)->Instance == ADC1)                                      \
01217     )?                                                                      \
01218      (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3))     \
01219      :                                                                      \
01220      ( ( ((__HANDLE__)->Instance == ADC2)                                   \
01221        )?                                                                   \
01222          (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \
01223         :                                                                   \
01224           ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \
01225      )
01226 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01227 #define ADC_ANY_OTHER_ENABLED(__HANDLE__)    (RESET)
01228 #endif
01229
01230
01231 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01232 /**
01233   * @brief Set handle instance of the ADC slave associated to the ADC master.
01234   * @param __HANDLE_MASTER__: ADC master handle.
01235   * @param __HANDLE_SLAVE__: ADC slave handle.
01236   * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL.
01237   * @retval None
01238   */
01239 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
01240   ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
01241 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01242
01243
01244 /**
01245   * @brief Check whether or not multimode is configured in DMA mode.
01246   * @note  Return RESET if multimode feature is not available.
01247   * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled)
01248   */
01249 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01250 #define ADC_MULTIMODE_DMA_ENABLED()                                     \
01251     ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \
01252   || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS))
01253 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01254 #define ADC_MULTIMODE_DMA_ENABLED()    (RESET)
01255 #endif
01256
01257
01258 /**
01259   * @brief Verify the ADC instance connected to the temperature sensor.
01260   * @param __HANDLE__: ADC handle.
01261   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
01262   */
01263 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01264 /*  The temperature sensor measurement path (channel 17) is available on ADC1 */
01265 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
01266 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01267 /*  The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */
01268 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
01269 #endif
01270
01271 /**
01272   * @brief Verify the ADC instance connected to the battery voltage VBAT.
01273   * @param __HANDLE__: ADC handle.
01274   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
01275   */
01276 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01277 /*  The battery voltage measurement path (channel 18) is available on ADC1 */
01278 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
01279 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01280 /*  The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */
01281 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
01282 #endif
01283
01284 /**
01285   * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
01286   * @param __HANDLE__: ADC handle.
01287   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
01288   */
01289 /*  The internal voltage reference  VREFINT measurement path (channel 0) is available on ADC1 */
01290 #define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
01291
01292
01293 /**
01294   * @brief Verify the length of scheduled injected conversions group.
01295   * @param __LENGTH__: number of programmed conversions.
01296   * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
01297   */
01298 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
01299
01300
01301 /**
01302   * @brief Calibration factor size verification (7 bits maximum).
01303   * @param __CALIBRATION_FACTOR__: Calibration factor value.
01304   * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
01305   */
01306 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F))
01307
01308
01309 /**
01310   * @brief Verify the ADC channel setting.
01311   * @param __HANDLE__: ADC handle.
01312   * @param __CHANNEL__: programmed ADC channel.
01313   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
01314   */
01315 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01316 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1)  && \
01317                                                          (((__CHANNEL__) == ADC_CHANNEL_VREFINT)     || \
01318                                                           ((__CHANNEL__) == ADC_CHANNEL_1)           || \
01319                                                           ((__CHANNEL__) == ADC_CHANNEL_2)           || \
01320                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
01321                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
01322                                                           ((__CHANNEL__) == ADC_CHANNEL_5)           || \
01323                                                           ((__CHANNEL__) == ADC_CHANNEL_6)           || \
01324                                                           ((__CHANNEL__) == ADC_CHANNEL_7)           || \
01325                                                           ((__CHANNEL__) == ADC_CHANNEL_8)           || \
01326                                                           ((__CHANNEL__) == ADC_CHANNEL_9)           || \
01327                                                           ((__CHANNEL__) == ADC_CHANNEL_10)          || \
01328                                                           ((__CHANNEL__) == ADC_CHANNEL_11)          || \
01329                                                           ((__CHANNEL__) == ADC_CHANNEL_12)          || \
01330                                                           ((__CHANNEL__) == ADC_CHANNEL_13)          || \
01331                                                           ((__CHANNEL__) == ADC_CHANNEL_14)          || \
01332                                                           ((__CHANNEL__) == ADC_CHANNEL_15)          || \
01333                                                           ((__CHANNEL__) == ADC_CHANNEL_16)          || \
01334                                                           ((__CHANNEL__) == ADC_CHANNEL_17)          || \
01335                                                           ((__CHANNEL__) == ADC_CHANNEL_18)          || \
01336                                                           ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
01337                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)))
01338 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01339 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (((((__HANDLE__)->Instance) == ADC1)  && \
01340                                                          (((__CHANNEL__) == ADC_CHANNEL_VREFINT)     || \
01341                                                           ((__CHANNEL__) == ADC_CHANNEL_1)           || \
01342                                                           ((__CHANNEL__) == ADC_CHANNEL_2)           || \
01343                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
01344                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
01345                                                           ((__CHANNEL__) == ADC_CHANNEL_5)           || \
01346                                                           ((__CHANNEL__) == ADC_CHANNEL_6)           || \
01347                                                           ((__CHANNEL__) == ADC_CHANNEL_7)           || \
01348                                                           ((__CHANNEL__) == ADC_CHANNEL_8)           || \
01349                                                           ((__CHANNEL__) == ADC_CHANNEL_9)           || \
01350                                                           ((__CHANNEL__) == ADC_CHANNEL_10)          || \
01351                                                           ((__CHANNEL__) == ADC_CHANNEL_11)          || \
01352                                                           ((__CHANNEL__) == ADC_CHANNEL_12)          || \
01353                                                           ((__CHANNEL__) == ADC_CHANNEL_13)          || \
01354                                                           ((__CHANNEL__) == ADC_CHANNEL_14)          || \
01355                                                           ((__CHANNEL__) == ADC_CHANNEL_15)          || \
01356                                                           ((__CHANNEL__) == ADC_CHANNEL_16)          || \
01357                                                           ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
01358                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)))      || \
01359                                                         ((((__HANDLE__)->Instance) == ADC2)  && \
01360                                                          (((__CHANNEL__) == ADC_CHANNEL_1)           || \
01361                                                           ((__CHANNEL__) == ADC_CHANNEL_2)           || \
01362                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
01363                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
01364                                                           ((__CHANNEL__) == ADC_CHANNEL_5)           || \
01365                                                           ((__CHANNEL__) == ADC_CHANNEL_6)           || \
01366                                                           ((__CHANNEL__) == ADC_CHANNEL_7)           || \
01367                                                           ((__CHANNEL__) == ADC_CHANNEL_8)           || \
01368                                                           ((__CHANNEL__) == ADC_CHANNEL_9)           || \
01369                                                           ((__CHANNEL__) == ADC_CHANNEL_10)          || \
01370                                                           ((__CHANNEL__) == ADC_CHANNEL_11)          || \
01371                                                           ((__CHANNEL__) == ADC_CHANNEL_12)          || \
01372                                                           ((__CHANNEL__) == ADC_CHANNEL_13)          || \
01373                                                           ((__CHANNEL__) == ADC_CHANNEL_14)          || \
01374                                                           ((__CHANNEL__) == ADC_CHANNEL_15)          || \
01375                                                           ((__CHANNEL__) == ADC_CHANNEL_16)          || \
01376                                                           ((__CHANNEL__) == ADC_CHANNEL_17)          || \
01377                                                           ((__CHANNEL__) == ADC_CHANNEL_18)))        || \
01378                                                         ((((__HANDLE__)->Instance) == ADC3)  && \
01379                                                          (((__CHANNEL__) == ADC_CHANNEL_1)           || \
01380                                                           ((__CHANNEL__) == ADC_CHANNEL_2)           || \
01381                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
01382                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
01383                                                           ((__CHANNEL__) == ADC_CHANNEL_6)           || \
01384                                                           ((__CHANNEL__) == ADC_CHANNEL_7)           || \
01385                                                           ((__CHANNEL__) == ADC_CHANNEL_8)           || \
01386                                                           ((__CHANNEL__) == ADC_CHANNEL_9)           || \
01387                                                           ((__CHANNEL__) == ADC_CHANNEL_10)          || \
01388                                                           ((__CHANNEL__) == ADC_CHANNEL_11)          || \
01389                                                           ((__CHANNEL__) == ADC_CHANNEL_12)          || \
01390                                                           ((__CHANNEL__) == ADC_CHANNEL_13)          || \
01391                                                           ((__CHANNEL__) == ADC_CHANNEL_14)          || \
01392                                                           ((__CHANNEL__) == ADC_CHANNEL_15)          || \
01393                                                           ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
01394                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)   )))
01395 #endif
01396
01397 /**
01398   * @brief Verify the ADC channel setting in differential mode.
01399   * @param __HANDLE__: ADC handle.
01400   * @param __CHANNEL__: programmed ADC channel.
01401   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
01402   */
01403 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
01404 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)      || \
01405                                                       ((__CHANNEL__) == ADC_CHANNEL_2)      || \
01406                                                       ((__CHANNEL__) == ADC_CHANNEL_3)      || \
01407                                                       ((__CHANNEL__) == ADC_CHANNEL_4)      || \
01408                                                       ((__CHANNEL__) == ADC_CHANNEL_5)      || \
01409                                                       ((__CHANNEL__) == ADC_CHANNEL_6)      || \
01410                                                       ((__CHANNEL__) == ADC_CHANNEL_7)      || \
01411                                                       ((__CHANNEL__) == ADC_CHANNEL_8)      || \
01412                                                       ((__CHANNEL__) == ADC_CHANNEL_9)      || \
01413                                                       ((__CHANNEL__) == ADC_CHANNEL_10)     || \
01414                                                       ((__CHANNEL__) == ADC_CHANNEL_11)     || \
01415                                                       ((__CHANNEL__) == ADC_CHANNEL_12)     || \
01416                                                       ((__CHANNEL__) == ADC_CHANNEL_13)     || \
01417                                                       ((__CHANNEL__) == ADC_CHANNEL_14)     || \
01418                                                       ((__CHANNEL__) == ADC_CHANNEL_15)       )
01419 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01420     /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode,
01421                           channels 0, 16 to 18 can be only used in single-ended mode.
01422        For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode,
01423                  channels 4, 5 and 13 to 18 can only be used in single-ended mode.  */
01424 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ((((((__HANDLE__)->Instance) == ADC1)   || \
01425                                                          (((__HANDLE__)->Instance) == ADC2))  && \
01426                                                          (((__CHANNEL__) == ADC_CHANNEL_1)    || \
01427                                                           ((__CHANNEL__) == ADC_CHANNEL_2)    || \
01428                                                           ((__CHANNEL__) == ADC_CHANNEL_3)    || \
01429                                                           ((__CHANNEL__) == ADC_CHANNEL_4)    || \
01430                                                           ((__CHANNEL__) == ADC_CHANNEL_5)    || \
01431                                                           ((__CHANNEL__) == ADC_CHANNEL_6)    || \
01432                                                           ((__CHANNEL__) == ADC_CHANNEL_7)    || \
01433                                                           ((__CHANNEL__) == ADC_CHANNEL_8)    || \
01434                                                           ((__CHANNEL__) == ADC_CHANNEL_9)    || \
01435                                                           ((__CHANNEL__) == ADC_CHANNEL_10)   || \
01436                                                           ((__CHANNEL__) == ADC_CHANNEL_11)   || \
01437                                                           ((__CHANNEL__) == ADC_CHANNEL_12)   || \
01438                                                           ((__CHANNEL__) == ADC_CHANNEL_13)   || \
01439                                                           ((__CHANNEL__) == ADC_CHANNEL_14)   || \
01440                                                           ((__CHANNEL__) == ADC_CHANNEL_15))) || \
01441                                                         ((((__HANDLE__)->Instance) == ADC3)  && \
01442                                                          (((__CHANNEL__) == ADC_CHANNEL_1)   || \
01443                                                           ((__CHANNEL__) == ADC_CHANNEL_2)   || \
01444                                                           ((__CHANNEL__) == ADC_CHANNEL_3)   || \
01445                                                           ((__CHANNEL__) == ADC_CHANNEL_6)   || \
01446                                                           ((__CHANNEL__) == ADC_CHANNEL_7)   || \
01447                                                           ((__CHANNEL__) == ADC_CHANNEL_8)   || \
01448                                                           ((__CHANNEL__) == ADC_CHANNEL_9)   || \
01449                                                           ((__CHANNEL__) == ADC_CHANNEL_10)  || \
01450                                                           ((__CHANNEL__) == ADC_CHANNEL_11)  || \
01451                                                           ((__CHANNEL__) == ADC_CHANNEL_12)   )))
01452 #endif
01453
01454 /**
01455   * @brief Verify the ADC single-ended input or differential mode setting.
01456   * @param __SING_DIFF__: programmed channel setting.
01457   * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
01458   */
01459 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
01460                                                    ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )
01461
01462 /**
01463   * @brief Verify the ADC offset management setting.
01464   * @param __OFFSET_NUMBER__: ADC offset management.
01465   * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
01466   */
01467 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
01468                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
01469                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
01470                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
01471                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )
01472
01473 /**
01474   * @brief Verify the ADC regular channel setting.
01475   * @param __CHANNEL__: programmed ADC regular channel.
01476   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
01477   */
01478 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
01479                                           ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
01480                                           ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
01481                                           ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
01482                                           ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
01483                                           ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
01484                                           ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
01485                                           ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
01486                                           ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
01487                                           ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
01488                                           ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
01489                                           ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
01490                                           ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
01491                                           ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
01492                                           ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
01493                                           ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )
01494
01495
01496 /**
01497   * @brief Verify the ADC injected channel setting.
01498   * @param __CHANNEL__: programmed ADC injected channel.
01499   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
01500   */
01501 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
01502                                            ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
01503                                            ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
01504                                            ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )
01505
01506 /**
01507   * @brief Verify the ADC edge trigger setting for injected group.
01508   * @param __EDGE__: programmed ADC edge trigger setting.
01509   * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
01510   */
01511 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)        || \
01512                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
01513                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
01514                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
01515
01516
01517 /**
01518   * @brief Verify the ADC injected conversions external trigger.
01519   * @param __INJTRIG__: programmed ADC injected conversions external trigger.
01520   * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
01521   */
01522 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
01523                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
01524                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
01525                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
01526                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \
01527                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \
01528                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
01529                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)      || \
01530                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
01531                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)     || \
01532                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)    || \
01533                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \
01534                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \
01535                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
01536                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
01537                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
01538                                                                                                   \
01539                                           ((__INJTRIG__) == ADC_SOFTWARE_START)                   )
01540
01541
01542 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01543 /**
01544   * @brief Verify the ADC multimode setting.
01545   * @param __MODE__: programmed ADC multimode setting.
01546   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01547   */
01548 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)          || \
01549                                ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
01550                                ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
01551                                ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
01552                                ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
01553                                ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
01554                                ((__MODE__) == ADC_DUALMODE_INTERL)                || \
01555                                ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )
01556
01557 /**
01558   * @brief Verify the ADC multimode DMA access setting.
01559   * @param __MODE__: programmed ADC multimode DMA access setting.
01560   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01561   */
01562 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED)   || \
01563                                                ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
01564                                                ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS)     )
01565
01566 /**
01567   * @brief Verify the ADC multimode delay setting.
01568   * @param __DELAY__: programmed ADC multimode delay setting.
01569   * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
01570   */
01571 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
01572                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
01573                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
01574                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
01575                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
01576                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
01577                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
01578                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
01579                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
01580                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
01581                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
01582                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES)   )
01583 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01584
01585 /**
01586   * @brief Verify the ADC analog watchdog setting.
01587   * @param __WATCHDOG__: programmed ADC analog watchdog setting.
01588   * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
01589   */
01590 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
01591                                                      ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
01592                                                      ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )
01593
01594 /**
01595   * @brief Verify the ADC analog watchdog mode setting.
01596   * @param __WATCHDOG_MODE__: programmed ADC analog watchdog mode setting.
01597   * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
01598   */
01599 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)             || \
01600                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
01601                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
01602                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
01603                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
01604                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
01605                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
01606
01607 /**
01608   * @brief Verify the ADC conversion (regular or injected or both).
01609   * @param __CONVERSION__: ADC conversion group.
01610   * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
01611   */
01612 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)     || \
01613                                              ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
01614                                              ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
01615
01616 /**
01617   * @brief Verify the ADC event type.
01618   * @param __EVENT__: ADC event.
01619   * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
01620   */
01621 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
01622                                      ((__EVENT__) == ADC_AWD_EVENT)    || \
01623                                      ((__EVENT__) == ADC_AWD2_EVENT)   || \
01624                                      ((__EVENT__) == ADC_AWD3_EVENT)   || \
01625                                      ((__EVENT__) == ADC_OVR_EVENT)    || \
01626                                      ((__EVENT__) == ADC_JQOVF_EVENT)  )
01627
01628 /**
01629   * @brief Verify the ADC oversampling ratio.
01630   * @param __RATIO__: programmed ADC oversampling ratio.
01631   * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
01632   */
01633 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
01634                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
01635                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
01636                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
01637                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
01638                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
01639                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
01640                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
01641
01642 /**
01643   * @brief Verify the ADC oversampling shift.
01644   * @param __SHIFT__: programmed ADC oversampling shift.
01645   * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
01646   */
01647 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
01648                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
01649                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
01650                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
01651                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
01652                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
01653                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
01654                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
01655                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
01656
01657 /**
01658   * @brief Verify the ADC oversampling triggered mode.
01659   * @param __MODE__: programmed ADC oversampling triggered mode.
01660   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01661   */
01662 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
01663                                                       ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
01664
01665 /**
01666   * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
01667   * @param __MODE__: programmed ADC oversampling regular conversion resumed or continued mode.
01668   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01669   */
01670 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
01671                                                ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
01672
01673
01674 /**
01675   * @brief Verify the DFSDM mode configuration.
01676   * @param __HANDLE__: ADC handle.
01677   * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
01678   *      this reason, the input parameter is the ADC handle and not the configuration parameter
01679   *      directly.
01680   * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
01681   */
01682 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
01683
01684 /**
01685   * @brief Return the DFSDM configuration mode.
01686   * @param __HANDLE__: ADC handle.
01687   * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
01688   *       For this reason, the input parameter is the ADC handle and not the configuration parameter
01689   *       directly.
01690   * @retval DFSDM configuration mode
01691   */
01692 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0)
01693
01694
01695 /**
01696   * @}
01697   */
01698
01699
01700 /* Exported functions --------------------------------------------------------*/
01701 /** @addtogroup ADCEx_Exported_Functions ADC Extended Exported Functions
01702   * @{
01703   */
01704
01705 /* Initialization/de-initialization functions *********************************/
01706
01707 /** @addtogroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
01708   * @brief    Extended IO operation functions
01709   * @{
01710   */
01711 /* I/O operation functions ****************************************************/
01712
01713 /* ADC calibration */
01714
01715 HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
01716 uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
01717 HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
01718
01719
01720
01721 /* Blocking mode: Polling */
01722 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
01723 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
01724 HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
01725
01726 /* Non-blocking mode: Interruption */
01727 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
01728 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
01729
01730
01731 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01732 /* ADC multimode */
01733 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
01734 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
01735 uint32_t                HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
01736 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01737
01738 /* ADC retrieve conversion value intended to be used with polling or interruption */
01739 uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
01740
01741 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
01742 void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
01743 void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
01744 void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
01745 void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
01746 void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
01747
01748
01749 /* ADC Regular conversions stop */
01750 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
01751 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
01752 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
01753 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01754 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
01755 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01756
01757 /**
01758   * @}
01759   */
01760
01761 /** @addtogroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
01762   * @brief    Extended Peripheral Control functions
01763   * @{
01764   */
01765 /* Peripheral Control functions ***********************************************/
01766 HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
01767 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01768 HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
01769 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01770 HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
01771 HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
01772 HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
01773 HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
01774
01775 /**
01776   * @}
01777   */
01778
01779 /**
01780   * @}
01781   */
01782
01783 /**
01784   * @}
01785   */
01786
01787 /**
01788   * @}
01789   */
01790
01791 #ifdef __cplusplus
01792 }
01793 #endif
01794
01795 #endif /*__STM32L4xx_ADC_EX_H */
01796
01797
01798 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_can.c Source File

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stm32l4xx_hal_can.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_can.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   CAN HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Controller Area Network (CAN) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Error functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       (#) Enable the CAN controller interface clock using
00021           __HAL_RCC_CAN1_CLK_ENABLE() for CAN1.
00022
00023       (#) CAN pins configuration
00024         (++) Enable the clock for the CAN GPIOs using the following function:
00025              __HAL_RCC_GPIOx_CLK_ENABLE();
00026         (++) Connect and configure the involved CAN pins using the
00027               following function HAL_GPIO_Init();
00028
00029       (#) Initialize and configure the CAN using HAL_CAN_Init() function.
00030
00031       (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or
00032           HAL_CAN_Transmit_IT() function.
00033
00034       (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function.
00035
00036      *** Polling mode IO operation ***
00037      =================================
00038      [..]
00039        (+) Start the CAN peripheral transmission and wait the end of this operation
00040            using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
00041            according to his end application
00042        (+) Start the CAN peripheral reception and wait the end of this operation
00043            using HAL_CAN_Receive(), at this stage user can specify the value of timeout
00044            according to his end application
00045
00046      *** Interrupt mode IO operation ***
00047      ===================================
00048      [..]
00049        (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
00050        (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
00051        (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
00052        (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
00053             add his own code by customization of function pointer HAL_CAN_TxCpltCallback
00054        (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
00055             add his own code by customization of function pointer HAL_CAN_ErrorCallback
00056
00057      *** CAN HAL driver macros list ***
00058      =============================================
00059      [..]
00060        Below the list of most used macros in CAN HAL driver.
00061
00062       (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
00063       (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
00064       (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
00065       (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
00066       (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
00067
00068      [..]
00069       (@) You can refer to the CAN HAL driver header file for more useful macros
00070
00071   @endverbatim
00072
00073   ******************************************************************************
00074   * @attention
00075   *
00076   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00077   *
00078   * Redistribution and use in source and binary forms, with or without modification,
00079   * are permitted provided that the following conditions are met:
00080   *   1. Redistributions of source code must retain the above copyright notice,
00081   *      this list of conditions and the following disclaimer.
00082   *   2. Redistributions in binary form must reproduce the above copyright notice,
00083   *      this list of conditions and the following disclaimer in the documentation
00084   *      and/or other materials provided with the distribution.
00085   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00086   *      may be used to endorse or promote products derived from this software
00087   *      without specific prior written permission.
00088   *
00089   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00090   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00091   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00092   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00093   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00094   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00095   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00096   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00097   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00098   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00099   *
00100   ******************************************************************************
00101   */
00102
00103 /* Includes ------------------------------------------------------------------*/
00104 #include "stm32l4xx_hal.h"
00105
00106 /** @addtogroup STM32L4xx_HAL_Driver
00107   * @{
00108   */
00109
00110 /** @defgroup CAN CAN
00111   * @brief CAN driver modules
00112   * @{
00113   */
00114
00115 #ifdef HAL_CAN_MODULE_ENABLED
00116
00117 /* Private typedef -----------------------------------------------------------*/
00118 /* Private define ------------------------------------------------------------*/
00119 /** @defgroup CAN_Private_Constants CAN Private Constants
00120   * @{
00121   */
00122 #define CAN_TIMEOUT_VALUE  10
00123 /**
00124   * @}
00125   */
00126 /* Private macro -------------------------------------------------------------*/
00127 /* Private variables ---------------------------------------------------------*/
00128 /* Private function prototypes -----------------------------------------------*/
00129 /** @defgroup CAN_Private_Functions CAN Private Functions
00130  * @{
00131  */
00132 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
00133 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
00134 /**
00135   * @}
00136   */
00137
00138 /* Exported functions --------------------------------------------------------*/
00139
00140 /** @defgroup CAN_Exported_Functions CAN Exported Functions
00141   * @{
00142   */
00143
00144 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
00145  *  @brief    Initialization and Configuration functions
00146  *
00147 @verbatim
00148   ==============================================================================
00149               ##### Initialization and de-initialization functions #####
00150   ==============================================================================
00151     [..]  This section provides functions allowing to:
00152       (+) Initialize and configure the CAN.
00153       (+) De-initialize the CAN.
00154
00155 @endverbatim
00156   * @{
00157   */
00158
00159 /**
00160   * @brief  Initialize the CAN peripheral according to the specified parameters
00161   *         in the CAN_InitStruct structure and initialize the associated handle.
00162   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00163   *         the configuration information for the specified CAN.
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
00167 {
00168   uint32_t status = CAN_INITSTATUS_FAILED;  /* Default init status */
00169   uint32_t tickstart = 0;
00170
00171   /* Check CAN handle */
00172   if(hcan == NULL)
00173   {
00174      return HAL_ERROR;
00175   }
00176
00177   /* Check the parameters */
00178   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00179   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
00180   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
00181   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
00182   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
00183   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
00184   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
00185   assert_param(IS_CAN_MODE(hcan->Init.Mode));
00186   assert_param(IS_CAN_SJW(hcan->Init.SJW));
00187   assert_param(IS_CAN_BS1(hcan->Init.BS1));
00188   assert_param(IS_CAN_BS2(hcan->Init.BS2));
00189   assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
00190
00191   if(hcan->State == HAL_CAN_STATE_RESET)
00192   {
00193     /* Allocate lock resource and initialize it */
00194     hcan->Lock = HAL_UNLOCKED;
00195
00196     /* Init the low level hardware */
00197     HAL_CAN_MspInit(hcan);
00198   }
00199
00200   /* Initialize the CAN state*/
00201   hcan->State = HAL_CAN_STATE_BUSY;
00202
00203   /* Exit from sleep mode */
00204   hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
00205
00206   /* Request initialisation */
00207   hcan->Instance->MCR |= CAN_MCR_INRQ ;
00208
00209   /* Get tick */
00210   tickstart = HAL_GetTick();
00211
00212   /* Wait the acknowledge */
00213   while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
00214   {
00215     if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
00216     {
00217       hcan->State= HAL_CAN_STATE_TIMEOUT;
00218       /* Process unlocked */
00219       __HAL_UNLOCK(hcan);
00220       return HAL_TIMEOUT;
00221     }
00222   }
00223
00224   /* Check acknowledge */
00225   if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
00226   {
00227     /* Set the time triggered communication mode */
00228     if (hcan->Init.TTCM == ENABLE)
00229     {
00230       hcan->Instance->MCR |= CAN_MCR_TTCM;
00231     }
00232     else
00233     {
00234       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
00235     }
00236
00237     /* Set the automatic bus-off management */
00238     if (hcan->Init.ABOM == ENABLE)
00239     {
00240       hcan->Instance->MCR |= CAN_MCR_ABOM;
00241     }
00242     else
00243     {
00244       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
00245     }
00246
00247     /* Set the automatic wake-up mode */
00248     if (hcan->Init.AWUM == ENABLE)
00249     {
00250       hcan->Instance->MCR |= CAN_MCR_AWUM;
00251     }
00252     else
00253     {
00254       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
00255     }
00256
00257     /* Set the no automatic retransmission */
00258     if (hcan->Init.NART == ENABLE)
00259     {
00260       hcan->Instance->MCR |= CAN_MCR_NART;
00261     }
00262     else
00263     {
00264       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
00265     }
00266
00267     /* Set the receive FIFO locked mode */
00268     if (hcan->Init.RFLM == ENABLE)
00269     {
00270       hcan->Instance->MCR |= CAN_MCR_RFLM;
00271     }
00272     else
00273     {
00274       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
00275     }
00276
00277     /* Set the transmit FIFO priority */
00278     if (hcan->Init.TXFP == ENABLE)
00279     {
00280       hcan->Instance->MCR |= CAN_MCR_TXFP;
00281     }
00282     else
00283     {
00284       hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
00285     }
00286
00287     /* Set the bit timing register */
00288     hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
00289                 ((uint32_t)hcan->Init.SJW) | \
00290                 ((uint32_t)hcan->Init.BS1) | \
00291                 ((uint32_t)hcan->Init.BS2) | \
00292                ((uint32_t)hcan->Init.Prescaler - 1);
00293
00294     /* Request leave initialisation */
00295     hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
00296
00297     /* Get tick */
00298     tickstart = HAL_GetTick();
00299
00300     /* Wait the acknowledge */
00301     while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
00302     {
00303       if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
00304       {
00305          hcan->State= HAL_CAN_STATE_TIMEOUT;
00306          /* Process unlocked */
00307          __HAL_UNLOCK(hcan);
00308          return HAL_TIMEOUT;
00309       }
00310     }
00311
00312     /* Check acknowledged */
00313     if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
00314     {
00315       status = CAN_INITSTATUS_SUCCESS;
00316     }
00317   }
00318
00319   if(status == CAN_INITSTATUS_SUCCESS)
00320   {
00321     /* Set CAN error code to none */
00322     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00323
00324     /* Initialize the CAN state */
00325     hcan->State = HAL_CAN_STATE_READY;
00326
00327     /* Return function status */
00328     return HAL_OK;
00329   }
00330   else
00331   {
00332     /* Initialize the CAN state */
00333     hcan->State = HAL_CAN_STATE_ERROR;
00334
00335     /* Return function status */
00336     return HAL_ERROR;
00337   }
00338 }
00339
00340 /**
00341   * @brief  Configure the CAN reception filter according to the specified
00342   *         parameters in the CAN_FilterInitStruct.
00343   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00344   *         the configuration information for the specified CAN.
00345   * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
00346   *         contains the filter configuration information.
00347   * @retval None
00348   */
00349 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
00350 {
00351   uint32_t filternbrbitpos = 0;
00352
00353   /* Prevent unused argument(s) compilation warning */
00354   UNUSED(hcan);
00355
00356   /* Check the parameters */
00357   assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
00358   assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
00359   assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
00360   assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
00361   assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
00362   assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
00363
00364   filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
00365
00366   /* Initialisation mode for the filter */
00367   CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
00368
00369   /* Filter Deactivation */
00370   CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
00371
00372   /* Filter Scale */
00373   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
00374   {
00375     /* 16-bit scale for the filter */
00376     CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
00377
00378     /* First 16-bit identifier and First 16-bit mask */
00379     /* Or First 16-bit identifier and Second 16-bit identifier */
00380     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00381        ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
00382         (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
00383
00384     /* Second 16-bit identifier and Second 16-bit mask */
00385     /* Or Third 16-bit identifier and Fourth 16-bit identifier */
00386     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00387        ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
00388         (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
00389   }
00390
00391   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
00392   {
00393     /* 32-bit scale for the filter */
00394     CAN1->FS1R |= filternbrbitpos;
00395     /* 32-bit identifier or First 32-bit identifier */
00396     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00397        ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
00398         (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
00399     /* 32-bit mask or Second 32-bit identifier */
00400     CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00401        ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
00402         (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
00403   }
00404
00405   /* Filter Mode */
00406   if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
00407   {
00408     /*Id/Mask mode for the filter*/
00409     CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
00410   }
00411   else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
00412   {
00413     /*Identifier list mode for the filter*/
00414     CAN1->FM1R |= (uint32_t)filternbrbitpos;
00415   }
00416
00417   /* Filter FIFO assignment */
00418   if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
00419   {
00420     /* FIFO 0 assignation for the filter */
00421     CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
00422   }
00423
00424   if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
00425   {
00426     /* FIFO 1 assignation for the filter */
00427     CAN1->FFA1R |= (uint32_t)filternbrbitpos;
00428   }
00429
00430   /* Filter activation */
00431   if (sFilterConfig->FilterActivation == ENABLE)
00432   {
00433     CAN1->FA1R |= filternbrbitpos;
00434   }
00435
00436   /* Leave the initialisation mode for the filter */
00437   CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
00438
00439   /* Return function status */
00440   return HAL_OK;
00441 }
00442
00443 /**
00444   * @brief  DeInitialize the CAN peripheral registers to their default reset values.
00445   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00446   *         the configuration information for the specified CAN.
00447   * @retval HAL status
00448   */
00449 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
00450 {
00451   /* Check CAN handle */
00452   if(hcan == NULL)
00453   {
00454      return HAL_ERROR;
00455   }
00456
00457   /* Check the parameters */
00458   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00459
00460   /* Change CAN state */
00461   hcan->State = HAL_CAN_STATE_BUSY;
00462
00463   /* DeInit the low level hardware */
00464   HAL_CAN_MspDeInit(hcan);
00465
00466   /* Change CAN state */
00467   hcan->State = HAL_CAN_STATE_RESET;
00468
00469   /* Release Lock */
00470   __HAL_UNLOCK(hcan);
00471
00472   /* Return function status */
00473   return HAL_OK;
00474 }
00475
00476 /**
00477   * @brief  Initialize the CAN MSP.
00478   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00479   *         the configuration information for the specified CAN.
00480   * @retval None
00481   */
00482 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
00483 {
00484   /* Prevent unused argument(s) compilation warning */
00485   UNUSED(hcan);
00486
00487   /* NOTE : This function should not be modified, when the callback is needed,
00488             the HAL_CAN_MspInit could be implemented in the user file
00489    */
00490 }
00491
00492 /**
00493   * @brief  DeInitialize the CAN MSP.
00494   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00495   *         the configuration information for the specified CAN.
00496   * @retval None
00497   */
00498 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
00499 {
00500   /* Prevent unused argument(s) compilation warning */
00501   UNUSED(hcan);
00502
00503   /* NOTE : This function should not be modified, when the callback is needed,
00504             the HAL_CAN_MspDeInit could be implemented in the user file
00505    */
00506 }
00507
00508 /**
00509   * @}
00510   */
00511
00512 /** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
00513  *  @brief    I/O operation functions
00514  *
00515 @verbatim
00516   ==============================================================================
00517                       ##### IO operation functions #####
00518   ==============================================================================
00519     [..]  This section provides functions allowing to:
00520       (+) Transmit a CAN frame message.
00521       (+) Receive a CAN frame message.
00522       (+) Enter CAN peripheral in sleep mode.
00523       (+) Wake up the CAN peripheral from sleep mode.
00524
00525 @endverbatim
00526   * @{
00527   */
00528
00529 /**
00530   * @brief  Initiate and transmit a CAN frame message.
00531   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00532   *         the configuration information for the specified CAN.
00533   * @param  Timeout: Timeout duration.
00534   * @retval HAL status
00535   */
00536 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
00537 {
00538   uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
00539   uint32_t tickstart = 0;
00540
00541   /* Check the parameters */
00542   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00543   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00544   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00545
00546   /* Process locked */
00547   __HAL_LOCK(hcan);
00548
00549   if(hcan->State == HAL_CAN_STATE_BUSY_RX)
00550   {
00551     /* Change CAN state */
00552     hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00553   }
00554   else
00555   {
00556     /* Change CAN state */
00557     hcan->State = HAL_CAN_STATE_BUSY_TX;
00558   }
00559
00560   /* Select one empty transmit mailbox */
00561   if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
00562   {
00563     transmitmailbox = 0;
00564   }
00565   else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
00566   {
00567     transmitmailbox = 1;
00568   }
00569   else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
00570   {
00571     transmitmailbox = 2;
00572   }
00573
00574   if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
00575   {
00576     /* Set up the Id */
00577     hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00578     if (hcan->pTxMsg->IDE == CAN_ID_STD)
00579     {
00580       assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00581       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
00582                                                   hcan->pTxMsg->RTR);
00583     }
00584     else
00585     {
00586       assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00587       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
00588                                                   hcan->pTxMsg->IDE | \
00589                                                   hcan->pTxMsg->RTR);
00590     }
00591
00592     /* Set up the DLC */
00593     hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
00594     hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
00595     hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00596
00597     /* Set up the data field */
00598     hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
00599                                              ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
00600                                              ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
00601                                              ((uint32_t)hcan->pTxMsg->Data[0]));
00602     hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
00603                                              ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
00604                                              ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
00605                                              ((uint32_t)hcan->pTxMsg->Data[4]));
00606     /* Request transmission */
00607     hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
00608
00609     /* Get tick */
00610     tickstart = HAL_GetTick();
00611
00612     /* Check End of transmission flag */
00613     while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
00614     {
00615       /* Check for the Timeout */
00616       if(Timeout != HAL_MAX_DELAY)
00617       {
00618         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00619         {
00620           hcan->State = HAL_CAN_STATE_TIMEOUT;
00621           /* Process unlocked */
00622           __HAL_UNLOCK(hcan);
00623           return HAL_TIMEOUT;
00624         }
00625       }
00626     }
00627     if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
00628     {
00629       /* Change CAN state */
00630       hcan->State = HAL_CAN_STATE_BUSY_RX;
00631     }
00632     else
00633     {
00634       /* Change CAN state */
00635       hcan->State = HAL_CAN_STATE_READY;
00636     }
00637
00638     /* Process unlocked */
00639     __HAL_UNLOCK(hcan);
00640
00641     /* Return function status */
00642     return HAL_OK;
00643   }
00644   else
00645   {
00646     /* Change CAN state */
00647     hcan->State = HAL_CAN_STATE_ERROR;
00648
00649     /* Process unlocked */
00650     __HAL_UNLOCK(hcan);
00651
00652     /* Return function status */
00653     return HAL_ERROR;
00654   }
00655 }
00656
00657 /**
00658   * @brief  Initiate and transmit a CAN frame message in Interrupt mode.
00659   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00660   *         the configuration information for the specified CAN.
00661   * @retval HAL status
00662   */
00663 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
00664 {
00665   uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
00666
00667   /* Check the parameters */
00668   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00669   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00670   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00671
00672   if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX))
00673   {
00674     /* Process Locked */
00675     __HAL_LOCK(hcan);
00676
00677     /* Select one empty transmit mailbox */
00678     if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
00679     {
00680       transmitmailbox = 0;
00681     }
00682     else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
00683     {
00684       transmitmailbox = 1;
00685     }
00686     else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
00687     {
00688       transmitmailbox = 2;
00689     }
00690
00691     if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
00692     {
00693       /* Set up the Id */
00694       hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00695       if(hcan->pTxMsg->IDE == CAN_ID_STD)
00696       {
00697         assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00698         hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
00699                                                   hcan->pTxMsg->RTR);
00700       }
00701       else
00702       {
00703         assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00704         hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
00705                                                   hcan->pTxMsg->IDE | \
00706                                                   hcan->pTxMsg->RTR);
00707       }
00708
00709       /* Set up the DLC */
00710       hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
00711       hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
00712       hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00713
00714       /* Set up the data field */
00715       hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
00716                                              ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
00717                                              ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
00718                                              ((uint32_t)hcan->pTxMsg->Data[0]));
00719       hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
00720                                              ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
00721                                              ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
00722                                              ((uint32_t)hcan->pTxMsg->Data[4]));
00723
00724       if(hcan->State == HAL_CAN_STATE_BUSY_RX)
00725       {
00726         /* Change CAN state */
00727         hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00728       }
00729       else
00730       {
00731         /* Change CAN state */
00732         hcan->State = HAL_CAN_STATE_BUSY_TX;
00733       }
00734
00735       /* Set CAN error code to none */
00736       hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00737
00738       /* Process Unlocked */
00739       __HAL_UNLOCK(hcan);
00740
00741       /* Enable interrupts: */
00742       /*  - Enable Error warning Interrupt */
00743       /*  - Enable Error passive Interrupt */
00744       /*  - Enable Bus-off Interrupt */
00745       /*  - Enable Last error code Interrupt */
00746       /*  - Enable Error Interrupt */
00747       /*  - Enable Transmit mailbox empty Interrupt */
00748       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
00749                                 CAN_IT_EPV |
00750                                 CAN_IT_BOF |
00751                                 CAN_IT_LEC |
00752                                 CAN_IT_ERR |
00753                                 CAN_IT_TME  );
00754
00755       /* Request transmission */
00756       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
00757     }
00758   }
00759   else
00760   {
00761     return HAL_BUSY;
00762   }
00763
00764   return HAL_OK;
00765 }
00766
00767 /**
00768   * @brief  Receive a correct CAN frame.
00769   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00770   *         the configuration information for the specified CAN.
00771   * @param  FIFONumber:    FIFO number.
00772   * @param  Timeout:       Timeout duration.
00773   * @retval HAL status
00774   */
00775 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
00776 {
00777   uint32_t tickstart = 0;
00778
00779   /* Check the parameters */
00780   assert_param(IS_CAN_FIFO(FIFONumber));
00781
00782   /* Process locked */
00783   __HAL_LOCK(hcan);
00784
00785   if(hcan->State == HAL_CAN_STATE_BUSY_TX)
00786   {
00787     /* Change CAN state */
00788     hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00789   }
00790   else
00791   {
00792     /* Change CAN state */
00793     hcan->State = HAL_CAN_STATE_BUSY_RX;
00794   }
00795
00796   /* Get tick */
00797   tickstart = HAL_GetTick();
00798
00799   /* Check pending message */
00800   while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
00801   {
00802     /* Check for the Timeout */
00803     if(Timeout != HAL_MAX_DELAY)
00804     {
00805       if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00806       {
00807         hcan->State = HAL_CAN_STATE_TIMEOUT;
00808         /* Process unlocked */
00809         __HAL_UNLOCK(hcan);
00810         return HAL_TIMEOUT;
00811       }
00812     }
00813   }
00814
00815   /* Get the Id */
00816   hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
00817   if (hcan->pRxMsg->IDE == CAN_ID_STD)
00818   {
00819     hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
00820   }
00821   else
00822   {
00823     hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
00824   }
00825
00826   hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
00827   /* Get the DLC */
00828   hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
00829   /* Get the FMI */
00830   hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
00831   /* Get the data field */
00832   hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
00833   hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
00834   hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
00835   hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
00836   hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
00837   hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
00838   hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
00839   hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
00840
00841   /* Release the FIFO */
00842   if(FIFONumber == CAN_FIFO0)
00843   {
00844     /* Release FIFO0 */
00845     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
00846   }
00847   else /* FIFONumber == CAN_FIFO1 */
00848   {
00849     /* Release FIFO1 */
00850     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
00851   }
00852
00853   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
00854   {
00855     /* Change CAN state */
00856     hcan->State = HAL_CAN_STATE_BUSY_TX;
00857   }
00858   else
00859   {
00860     /* Change CAN state */
00861     hcan->State = HAL_CAN_STATE_READY;
00862   }
00863
00864   /* Process unlocked */
00865   __HAL_UNLOCK(hcan);
00866
00867   /* Return function status */
00868   return HAL_OK;
00869 }
00870
00871 /**
00872   * @brief  Receive a correct CAN frame in Interrupt mode.
00873   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00874   *         the configuration information for the specified CAN.
00875   * @param  FIFONumber:    FIFO number.
00876   * @retval HAL status
00877   */
00878 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
00879 {
00880   /* Check the parameters */
00881   assert_param(IS_CAN_FIFO(FIFONumber));
00882
00883   if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
00884   {
00885     /* Process locked */
00886     __HAL_LOCK(hcan);
00887
00888     if(hcan->State == HAL_CAN_STATE_BUSY_TX)
00889     {
00890       /* Change CAN state */
00891       hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00892     }
00893     else
00894     {
00895       /* Change CAN state */
00896       hcan->State = HAL_CAN_STATE_BUSY_RX;
00897     }
00898
00899     /* Set CAN error code to none */
00900     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00901
00902     /* Enable interrupts: */
00903     /*  - Enable Error warning Interrupt */
00904     /*  - Enable Error passive Interrupt */
00905     /*  - Enable Bus-off Interrupt */
00906     /*  - Enable Last error code Interrupt */
00907     /*  - Enable Error Interrupt */
00908     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
00909                               CAN_IT_EPV |
00910                               CAN_IT_BOF |
00911                               CAN_IT_LEC |
00912                               CAN_IT_ERR );
00913
00914     /* Process unlocked */
00915     __HAL_UNLOCK(hcan);
00916
00917     if(FIFONumber == CAN_FIFO0)
00918     {
00919       /* Enable FIFO 0 message pending Interrupt */
00920       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
00921     }
00922     else
00923     {
00924       /* Enable FIFO 1 message pending Interrupt */
00925       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
00926     }
00927
00928   }
00929   else
00930   {
00931     return HAL_BUSY;
00932   }
00933
00934   /* Return function status */
00935   return HAL_OK;
00936 }
00937
00938 /**
00939   * @brief  Enter the Sleep (low power) mode.
00940   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00941   *         the configuration information for the specified CAN.
00942   * @retval HAL status.
00943   */
00944 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
00945 {
00946   uint32_t tickstart = 0;
00947
00948   /* Process locked */
00949   __HAL_LOCK(hcan);
00950
00951   /* Change CAN state */
00952   hcan->State = HAL_CAN_STATE_BUSY;
00953
00954   /* Request Sleep mode */
00955    hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
00956
00957   /* Sleep mode status */
00958   if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
00959   {
00960     /* Process unlocked */
00961     __HAL_UNLOCK(hcan);
00962
00963     /* Return function status */
00964     return HAL_ERROR;
00965   }
00966
00967   /* Get tick */
00968   tickstart = HAL_GetTick();
00969
00970   /* Wait the acknowledge */
00971   while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
00972   {
00973     if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
00974     {
00975       hcan->State = HAL_CAN_STATE_TIMEOUT;
00976       /* Process unlocked */
00977       __HAL_UNLOCK(hcan);
00978       return HAL_TIMEOUT;
00979     }
00980   }
00981
00982   /* Change CAN state */
00983   hcan->State = HAL_CAN_STATE_READY;
00984
00985   /* Process unlocked */
00986   __HAL_UNLOCK(hcan);
00987
00988   /* Return function status */
00989   return HAL_OK;
00990 }
00991
00992 /**
00993   * @brief  Wake up the CAN peripheral from sleep mode (after that the CAN peripheral
00994   *         is in the normal mode).
00995   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00996   *         the configuration information for the specified CAN.
00997   * @retval HAL status.
00998   */
00999 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
01000 {
01001   uint32_t tickstart = 0;
01002
01003   /* Process locked */
01004   __HAL_LOCK(hcan);
01005
01006   /* Change CAN state */
01007   hcan->State = HAL_CAN_STATE_BUSY;
01008
01009   /* Wake up request */
01010   hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
01011
01012   /* Get tick */
01013   tickstart = HAL_GetTick();
01014
01015   /* Sleep mode status */
01016   while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
01017   {
01018     if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
01019     {
01020       hcan->State= HAL_CAN_STATE_TIMEOUT;
01021       /* Process unlocked */
01022       __HAL_UNLOCK(hcan);
01023       return HAL_TIMEOUT;
01024     }
01025   }
01026   if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
01027   {
01028     /* Process unlocked */
01029     __HAL_UNLOCK(hcan);
01030
01031     /* Return function status */
01032     return HAL_ERROR;
01033   }
01034
01035   /* Change CAN state */
01036   hcan->State = HAL_CAN_STATE_READY;
01037
01038   /* Process unlocked */
01039   __HAL_UNLOCK(hcan);
01040
01041   /* Return function status */
01042   return HAL_OK;
01043 }
01044
01045 /**
01046   * @brief  Handle CAN interrupt request.
01047   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01048   *         the configuration information for the specified CAN.
01049   * @retval None
01050   */
01051 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
01052 {
01053   /* Check End of transmission flag */
01054   if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
01055   {
01056     if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
01057        (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
01058        (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
01059     {
01060       /* Call transmit function */
01061       CAN_Transmit_IT(hcan);
01062     }
01063   }
01064
01065   /* Check End of reception flag for FIFO0 */
01066   if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
01067      (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
01068   {
01069     /* Call receive function */
01070     CAN_Receive_IT(hcan, CAN_FIFO0);
01071   }
01072
01073   /* Check End of reception flag for FIFO1 */
01074   if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
01075      (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
01076   {
01077     /* Call receive function */
01078     CAN_Receive_IT(hcan, CAN_FIFO1);
01079   }
01080
01081   /* Check Error Warning Flag */
01082   if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG))    &&
01083      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
01084      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
01085   {
01086     /* Set CAN error code to EWG error */
01087     hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
01088     /* No need for clear of Error Warning Flag as read-only */
01089   }
01090
01091   /* Check Error Passive Flag */
01092   if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV))    &&
01093      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
01094      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
01095   {
01096     /* Set CAN error code to EPV error */
01097     hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
01098     /* No need for clear of Error Passive Flag as read-only */
01099   }
01100
01101   /* Check Bus-Off Flag */
01102   if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF))    &&
01103      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
01104      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
01105   {
01106     /* Set CAN error code to BOF error */
01107     hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
01108     /* No need for clear of Bus-Off Flag as read-only */
01109   }
01110
01111   /* Check Last error code Flag */
01112   if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
01113      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC))         &&
01114      (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
01115   {
01116     switch(hcan->Instance->ESR & CAN_ESR_LEC)
01117     {
01118       case(CAN_ESR_LEC_0):
01119           /* Set CAN error code to STF error */
01120           hcan->ErrorCode |= HAL_CAN_ERROR_STF;
01121           break;
01122       case(CAN_ESR_LEC_1):
01123           /* Set CAN error code to FOR error */
01124           hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
01125           break;
01126       case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
01127           /* Set CAN error code to ACK error */
01128           hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
01129           break;
01130       case(CAN_ESR_LEC_2):
01131           /* Set CAN error code to BR error */
01132           hcan->ErrorCode |= HAL_CAN_ERROR_BR;
01133           break;
01134       case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
01135           /* Set CAN error code to BD error */
01136           hcan->ErrorCode |= HAL_CAN_ERROR_BD;
01137           break;
01138       case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
01139           /* Set CAN error code to CRC error */
01140           hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
01141           break;
01142       default:
01143           break;
01144     }
01145
01146     /* Clear Last error code Flag */
01147     hcan->Instance->ESR &= ~(CAN_ESR_LEC);
01148   }
01149
01150   /* Call the Error call Back in case of Errors */
01151   if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
01152   {
01153     /* Clear ERRI bit */
01154     SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
01155     /* Set the CAN state ready to be able to start again the process */
01156     hcan->State = HAL_CAN_STATE_READY;
01157     /* Call Error callback function */
01158     HAL_CAN_ErrorCallback(hcan);
01159   }
01160 }
01161
01162 /**
01163   * @brief  Transmission complete callback in non-blocking mode.
01164   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01165   *         the configuration information for the specified CAN.
01166   * @retval None
01167   */
01168 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
01169 {
01170   /* Prevent unused argument(s) compilation warning */
01171   UNUSED(hcan);
01172
01173   /* NOTE : This function should not be modified, when the callback is needed,
01174             the HAL_CAN_TxCpltCallback could be implemented in the user file
01175    */
01176 }
01177
01178 /**
01179   * @brief  Reception complete callback in non-blocking mode.
01180   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01181   *         the configuration information for the specified CAN.
01182   * @retval None
01183   */
01184 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
01185 {
01186   /* Prevent unused argument(s) compilation warning */
01187   UNUSED(hcan);
01188
01189   /* NOTE : This function should not be modified, when the callback is needed,
01190             the HAL_CAN_RxCpltCallback could be implemented in the user file
01191    */
01192 }
01193
01194 /**
01195   * @brief  Error CAN callback.
01196   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01197   *         the configuration information for the specified CAN.
01198   * @retval None
01199   */
01200 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
01201 {
01202   /* Prevent unused argument(s) compilation warning */
01203   UNUSED(hcan);
01204
01205   /* NOTE : This function should not be modified, when the callback is needed,
01206             the HAL_CAN_ErrorCallback could be implemented in the user file
01207    */
01208 }
01209
01210 /**
01211   * @}
01212   */
01213
01214 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
01215  *  @brief   CAN Peripheral State functions
01216  *
01217 @verbatim
01218   ==============================================================================
01219             ##### Peripheral State and Error functions #####
01220   ==============================================================================
01221     [..]
01222     This subsection provides functions allowing to :
01223       (+) Check the CAN state.
01224       (+) Check CAN Errors detected during interrupt process.
01225
01226 @endverbatim
01227   * @{
01228   */
01229
01230 /**
01231   * @brief  Return the CAN handle state.
01232   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01233   *         the configuration information for the specified CAN.
01234   * @retval HAL state
01235   */
01236 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
01237 {
01238   /* Return CAN handle state */
01239   return hcan->State;
01240 }
01241
01242 /**
01243   * @brief  Return the CAN error code.
01244   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01245   *         the configuration information for the specified CAN.
01246   * @retval CAN Error Code
01247   */
01248 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
01249 {
01250   return hcan->ErrorCode;
01251 }
01252
01253 /**
01254   * @}
01255   */
01256
01257 /**
01258   * @}
01259   */
01260
01261 /** @defgroup CAN_Private_Functions CAN Private Functions
01262  * @{
01263  */
01264 /**
01265   * @brief  Initiate and transmit a CAN frame message.
01266   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01267   *         the configuration information for the specified CAN.
01268   * @retval HAL status
01269   */
01270 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
01271 {
01272   /* Disable Transmit mailbox empty Interrupt */
01273   __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
01274
01275   if(hcan->State == HAL_CAN_STATE_BUSY_TX)
01276   {
01277     /* Disable interrupts: */
01278     /*  - Disable Error warning Interrupt */
01279     /*  - Disable Error passive Interrupt */
01280     /*  - Disable Bus-off Interrupt */
01281     /*  - Disable Last error code Interrupt */
01282     /*  - Disable Error Interrupt */
01283     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
01284                                CAN_IT_EPV |
01285                                CAN_IT_BOF |
01286                                CAN_IT_LEC |
01287                                CAN_IT_ERR  );
01288   }
01289
01290   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
01291   {
01292     /* Change CAN state */
01293     hcan->State = HAL_CAN_STATE_BUSY_RX;
01294   }
01295   else
01296   {
01297     /* Change CAN state */
01298     hcan->State = HAL_CAN_STATE_READY;
01299   }
01300
01301   /* Transmission complete callback */
01302   HAL_CAN_TxCpltCallback(hcan);
01303
01304   return HAL_OK;
01305 }
01306
01307 /**
01308   * @brief  Receive a correct CAN frame.
01309   * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
01310   *         the configuration information for the specified CAN.
01311   * @param  FIFONumber: Specify the FIFO number
01312   * @retval HAL status
01313   */
01314 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
01315 {
01316   /* Get the Id */
01317   hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
01318   if (hcan->pRxMsg->IDE == CAN_ID_STD)
01319   {
01320     hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
01321   }
01322   else
01323   {
01324     hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
01325   }
01326
01327   hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
01328   /* Get the DLC */
01329   hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
01330   /* Get the FMI */
01331   hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
01332   /* Get the data field */
01333   hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
01334   hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
01335   hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
01336   hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
01337   hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
01338   hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
01339   hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
01340   hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
01341   /* Release the FIFO */
01342   /* Release FIFO0 */
01343   if (FIFONumber == CAN_FIFO0)
01344   {
01345     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
01346
01347     /* Disable FIFO 0 message pending Interrupt */
01348     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
01349   }
01350   /* Release FIFO1 */
01351   else /* FIFONumber == CAN_FIFO1 */
01352   {
01353     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
01354
01355     /* Disable FIFO 1 message pending Interrupt */
01356     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
01357   }
01358
01359   if(hcan->State == HAL_CAN_STATE_BUSY_RX)
01360   {
01361     /* Disable interrupts: */
01362     /*  - Disable Error warning Interrupt */
01363     /*  - Disable Error passive Interrupt */
01364     /*  - Disable Bus-off Interrupt */
01365     /*  - Disable Last error code Interrupt */
01366     /*  - Disable Error Interrupt */
01367     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
01368                                CAN_IT_EPV |
01369                                CAN_IT_BOF |
01370                                CAN_IT_LEC |
01371                                CAN_IT_ERR  );
01372   }
01373
01374   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
01375   {
01376     /* Disable CAN state */
01377     hcan->State = HAL_CAN_STATE_BUSY_TX;
01378   }
01379   else
01380   {
01381     /* Change CAN state */
01382     hcan->State = HAL_CAN_STATE_READY;
01383   }
01384
01385   /* Receive complete callback */
01386   HAL_CAN_RxCpltCallback(hcan);
01387
01388   /* Return function status */
01389   return HAL_OK;
01390 }
01391 /**
01392  * @}
01393  */
01394
01395 #endif /* HAL_CAN_MODULE_ENABLED */
01396 /**
01397   * @}
01398   */
01399
01400 /**
01401   * @}
01402   */
01403
01404 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_can.h Source File

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stm32l4xx_hal_can.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_can.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of CAN HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_CAN_H
00040 #define __STM32L4xx_CAN_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CAN
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup CAN_Exported_Types CAN Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  HAL State structures definition
00064   */
00065 typedef enum
00066 {
00067   HAL_CAN_STATE_RESET             = 0x00,  /*!< CAN not yet initialized or disabled */
00068   HAL_CAN_STATE_READY             = 0x01,  /*!< CAN initialized and ready for use   */
00069   HAL_CAN_STATE_BUSY              = 0x02,  /*!< CAN process is ongoing              */
00070   HAL_CAN_STATE_BUSY_TX           = 0x12,  /*!< CAN process is ongoing              */
00071   HAL_CAN_STATE_BUSY_RX           = 0x22,  /*!< CAN process is ongoing              */
00072   HAL_CAN_STATE_BUSY_TX_RX        = 0x32,  /*!< CAN process is ongoing              */
00073   HAL_CAN_STATE_TIMEOUT           = 0x03,  /*!< Timeout state                       */
00074   HAL_CAN_STATE_ERROR             = 0x04   /*!< CAN error state                     */
00075
00076 }HAL_CAN_StateTypeDef;
00077
00078 /**
00079   * @brief  CAN init structure definition
00080   */
00081 typedef struct
00082 {
00083   uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
00084                             This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
00085
00086   uint32_t Mode;       /*!< Specifies the CAN operating mode.
00087                             This parameter can be a value of @ref CAN_operating_mode */
00088
00089   uint32_t SJW;        /*!< Specifies the maximum number of time quanta
00090                             the CAN hardware is allowed to lengthen or
00091                             shorten a bit to perform resynchronization.
00092                             This parameter can be a value of @ref CAN_synchronisation_jump_width */
00093
00094   uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
00095                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
00096
00097   uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
00098                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
00099
00100   uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
00101                             This parameter can be set to ENABLE or DISABLE. */
00102
00103   uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
00104                             This parameter can be set to ENABLE or DISABLE */
00105
00106   uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
00107                             This parameter can be set to ENABLE or DISABLE */
00108
00109   uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
00110                             This parameter can be set to ENABLE or DISABLE */
00111
00112   uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
00113                             This parameter can be set to ENABLE or DISABLE */
00114
00115   uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
00116                             This parameter can be set to ENABLE or DISABLE */
00117 }CAN_InitTypeDef;
00118
00119 /**
00120   * @brief  CAN filter configuration structure definition
00121   */
00122 typedef struct
00123 {
00124   uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
00125                                        configuration, first one for a 16-bit configuration).
00126                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00127
00128   uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
00129                                        configuration, second one for a 16-bit configuration).
00130                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00131
00132   uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
00133                                        according to the mode (MSBs for a 32-bit configuration,
00134                                        first one for a 16-bit configuration).
00135                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00136
00137   uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
00138                                        according to the mode (LSBs for a 32-bit configuration,
00139                                        second one for a 16-bit configuration).
00140                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00141
00142   uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
00143                                        This parameter can be a value of @ref CAN_filter_FIFO */
00144
00145   uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
00146                                        This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
00147
00148   uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
00149                                        This parameter can be a value of @ref CAN_filter_mode */
00150
00151   uint32_t FilterScale;           /*!< Specifies the filter scale.
00152                                        This parameter can be a value of @ref CAN_filter_scale */
00153
00154   uint32_t FilterActivation;      /*!< Enable or disable the filter.
00155                                        This parameter can be set to ENABLE or DISABLE */
00156
00157   uint32_t BankNumber;            /*!< Select the start slave bank filter.
00158                                        This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
00159
00160 }CAN_FilterConfTypeDef;
00161
00162 /**
00163   * @brief  CAN Tx message structure definition
00164   */
00165 typedef struct
00166 {
00167   uint32_t StdId;    /*!< Specifies the standard identifier.
00168                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
00169
00170   uint32_t ExtId;    /*!< Specifies the extended identifier.
00171                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
00172
00173   uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
00174                           This parameter can be a value of @ref CAN_identifier_type */
00175
00176   uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
00177                           This parameter can be a value of @ref CAN_remote_transmission_request */
00178
00179   uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
00180                           This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
00181
00182   uint8_t Data[8];   /*!< Contains the data to be transmitted.
00183                           This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00184
00185 }CanTxMsgTypeDef;
00186
00187 /**
00188   * @brief  CAN Rx message structure definition
00189   */
00190 typedef struct
00191 {
00192   uint32_t StdId;       /*!< Specifies the standard identifier.
00193                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
00194
00195   uint32_t ExtId;       /*!< Specifies the extended identifier.
00196                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
00197
00198   uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
00199                              This parameter can be a value of @ref CAN_identifier_type */
00200
00201   uint32_t RTR;         /*!< Specifies the type of frame for the received message.
00202                              This parameter can be a value of @ref CAN_remote_transmission_request */
00203
00204   uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
00205                              This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
00206
00207   uint8_t Data[8];      /*!< Contains the data to be received.
00208                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00209
00210   uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
00211                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00212
00213   uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
00214                              This parameter can be CAN_FIFO0 or CAN_FIFO1 */
00215
00216 }CanRxMsgTypeDef;
00217
00218 /**
00219   * @brief  CAN handle Structure definition
00220   */
00221 typedef struct
00222 {
00223   CAN_TypeDef                 *Instance;  /*!< Register base address          */
00224
00225   CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
00226
00227   CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
00228
00229   CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
00230
00231   __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
00232
00233   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
00234
00235   __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
00236
00237 }CAN_HandleTypeDef;
00238
00239 /**
00240   * @}
00241   */
00242
00243 /* Exported constants --------------------------------------------------------*/
00244 /** @defgroup CAN_Exported_Constants CAN Exported Constants
00245   * @{
00246   */
00247
00248 /** @defgroup CAN_Error_Code CAN Error Code
00249   * @{
00250   */
00251 #define   HAL_CAN_ERROR_NONE        ((uint32_t)0x00000000)    /*!< No error             */
00252 #define   HAL_CAN_ERROR_EWG         ((uint32_t)0x00000001)    /*!< EWG error            */
00253 #define   HAL_CAN_ERROR_EPV         ((uint32_t)0x00000002)    /*!< EPV error            */
00254 #define   HAL_CAN_ERROR_BOF         ((uint32_t)0x00000004)    /*!< BOF error            */
00255 #define   HAL_CAN_ERROR_STF         ((uint32_t)0x00000008)    /*!< Stuff error          */
00256 #define   HAL_CAN_ERROR_FOR         ((uint32_t)0x00000010)    /*!< Form error           */
00257 #define   HAL_CAN_ERROR_ACK         ((uint32_t)0x00000020)    /*!< Acknowledgment error */
00258 #define   HAL_CAN_ERROR_BR          ((uint32_t)0x00000040)    /*!< Bit recessive        */
00259 #define   HAL_CAN_ERROR_BD          ((uint32_t)0x00000080)    /*!< LEC dominant         */
00260 #define   HAL_CAN_ERROR_CRC         ((uint32_t)0x00000100)   /*!< LEC transfer error   */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup CAN_InitStatus CAN initialization Status
00266   * @{
00267   */
00268 #define CAN_INITSTATUS_FAILED       ((uint32_t)0x00000000)  /*!< CAN initialization failed */
00269 #define CAN_INITSTATUS_SUCCESS      ((uint32_t)0x00000001)  /*!< CAN initialization OK */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup CAN_operating_mode CAN Operating Mode
00275   * @{
00276   */
00277 #define CAN_MODE_NORMAL             ((uint32_t)0x00000000)                     /*!< Normal mode   */
00278 #define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
00279 #define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
00280 #define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
00281 /**
00282   * @}
00283   */
00284
00285
00286 /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
00287   * @{
00288   */
00289 #define CAN_SJW_1TQ                 ((uint32_t)0x00000000)     /*!< 1 time quantum */
00290 #define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
00291 #define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
00292 #define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
00298   * @{
00299   */
00300 #define CAN_BS1_1TQ                 ((uint32_t)0x00000000)                                       /*!< 1 time quantum  */
00301 #define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
00302 #define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
00303 #define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
00304 #define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
00305 #define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
00306 #define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
00307 #define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
00308 #define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
00309 #define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
00310 #define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
00311 #define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
00312 #define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
00313 #define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
00314 #define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
00315 #define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
00321   * @{
00322   */
00323 #define CAN_BS2_1TQ                 ((uint32_t)0x00000000)                       /*!< 1 time quantum */
00324 #define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
00325 #define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
00326 #define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
00327 #define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
00328 #define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
00329 #define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
00330 #define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup CAN_filter_mode CAN Filter Mode
00336   * @{
00337   */
00338 #define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
00339 #define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup CAN_filter_scale CAN Filter Scale
00345   * @{
00346   */
00347 #define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
00348 #define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
00349 /**
00350   * @}
00351   */
00352
00353 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
00354   * @{
00355   */
00356 #define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
00357 #define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup CAN_identifier_type CAN Identifier Type
00363   * @{
00364   */
00365 #define CAN_ID_STD             ((uint32_t)0x00000000)  /*!< Standard Id */
00366 #define CAN_ID_EXT             ((uint32_t)0x00000004)  /*!< Extended Id */
00367 /**
00368   * @}
00369   */
00370
00371 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
00372   * @{
00373   */
00374 #define CAN_RTR_DATA                ((uint32_t)0x00000000)  /*!< Data frame */
00375 #define CAN_RTR_REMOTE              ((uint32_t)0x00000002)  /*!< Remote frame */
00376 /**
00377   * @}
00378   */
00379
00380 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
00381   * @{
00382   */
00383 #define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
00384 #define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup CAN_flags CAN Flags
00390   * @{
00391   */
00392 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
00393    and CAN_ClearFlag() functions. */
00394 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
00395    CAN_GetFlagStatus() function.  */
00396
00397 /* Transmit Flags */
00398 #define CAN_FLAG_RQCP0             ((uint32_t)0x00000500)  /*!< Request MailBox0 flag         */
00399 #define CAN_FLAG_RQCP1             ((uint32_t)0x00000508)  /*!< Request MailBox1 flag         */
00400 #define CAN_FLAG_RQCP2             ((uint32_t)0x00000510)  /*!< Request MailBox2 flag         */
00401 #define CAN_FLAG_TXOK0             ((uint32_t)0x00000501)  /*!< Transmission OK MailBox0 flag */
00402 #define CAN_FLAG_TXOK1             ((uint32_t)0x00000509)  /*!< Transmission OK MailBox1 flag */
00403 #define CAN_FLAG_TXOK2             ((uint32_t)0x00000511)  /*!< Transmission OK MailBox2 flag */
00404 #define CAN_FLAG_TME0              ((uint32_t)0x0000051A)  /*!< Transmit mailbox 0 empty flag */
00405 #define CAN_FLAG_TME1              ((uint32_t)0x0000051B)  /*!< Transmit mailbox 0 empty flag */
00406 #define CAN_FLAG_TME2              ((uint32_t)0x0000051C)  /*!< Transmit mailbox 0 empty flag */
00407
00408 /* Receive Flags */
00409 #define CAN_FLAG_FF0               ((uint32_t)0x00000203)  /*!< FIFO 0 Full flag    */
00410 #define CAN_FLAG_FOV0              ((uint32_t)0x00000204)  /*!< FIFO 0 Overrun flag */
00411
00412 #define CAN_FLAG_FF1               ((uint32_t)0x00000403)  /*!< FIFO 1 Full flag    */
00413 #define CAN_FLAG_FOV1              ((uint32_t)0x00000404)  /*!< FIFO 1 Overrun flag */
00414
00415 /* Operating Mode Flags */
00416 #define CAN_FLAG_WKU               ((uint32_t)0x00000103)  /*!< Wake up flag           */
00417 #define CAN_FLAG_SLAK              ((uint32_t)0x00000101)  /*!< Sleep acknowledge flag */
00418 #define CAN_FLAG_SLAKI             ((uint32_t)0x00000104)  /*!< Sleep acknowledge flag */
00419 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
00420          In this case the SLAK bit can be polled.*/
00421
00422 /* Error Flags */
00423 #define CAN_FLAG_EWG               ((uint32_t)0x00000300)  /*!< Error warning flag   */
00424 #define CAN_FLAG_EPV               ((uint32_t)0x00000301)  /*!< Error passive flag   */
00425 #define CAN_FLAG_BOF               ((uint32_t)0x00000302)  /*!< Bus-Off flag         */
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup CAN_interrupts CAN Interrupts
00431   * @{
00432   */
00433 #define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
00434
00435 /* Receive Interrupts */
00436 #define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
00437 #define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
00438 #define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
00439 #define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
00440 #define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
00441 #define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
00442
00443 /* Operating Mode Interrupts */
00444 #define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
00445 #define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
00446
00447 /* Error Interrupts */
00448 #define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
00449 #define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
00450 #define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
00451 #define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
00452 #define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
00453
00454 /**
00455   * @}
00456   */
00457
00458 /* Mailboxes definition */
00459 #define CAN_TXMAILBOX_0   ((uint8_t)0x00)
00460 #define CAN_TXMAILBOX_1   ((uint8_t)0x01)
00461 #define CAN_TXMAILBOX_2   ((uint8_t)0x02)
00462
00463 /**
00464   * @}
00465   */
00466
00467 /* Exported macros -----------------------------------------------------------*/
00468 /** @defgroup CAN_Exported_Macro CAN Exported Macros
00469   * @{
00470   */
00471
00472 /** @brief  Reset CAN handle state.
00473   * @param  __HANDLE__: CAN handle.
00474   * @retval None
00475   */
00476 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
00477
00478 /**
00479   * @brief  Enable the specified CAN interrupt.
00480   * @param  __HANDLE__: CAN handle.
00481   * @param  __INTERRUPT__: CAN Interrupt.
00482   * @retval None
00483   */
00484 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
00485
00486 /**
00487   * @brief  Disable the specified CAN interrupt.
00488   * @param  __HANDLE__: CAN handle.
00489   * @param  __INTERRUPT__: CAN Interrupt.
00490   * @retval None
00491   */
00492 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
00493
00494 /**
00495   * @brief  Return the number of pending received messages.
00496   * @param  __HANDLE__: CAN handle.
00497   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00498   * @retval The number of pending message.
00499   */
00500 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
00501 ((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
00502
00503 /** @brief  Check whether the specified CAN flag is set or not.
00504   * @param  __HANDLE__: specifies the CAN Handle.
00505   * @param  __FLAG__: specifies the flag to check.
00506   *         This parameter can be one of the following values:
00507   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
00508   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
00509   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
00510   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
00511   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
00512   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
00513   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
00514   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
00515   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
00516   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
00517   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
00518   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
00519   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
00520   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
00521   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
00522   *            @arg CAN_FLAG_WKU: Wake up Flag
00523   *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
00524   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
00525   *            @arg CAN_FLAG_EWG: Error Warning Flag
00526   *            @arg CAN_FLAG_EPV: Error Passive Flag
00527   *            @arg CAN_FLAG_BOF: Bus-Off Flag
00528   * @retval The new state of __FLAG__ (TRUE or FALSE).
00529   */
00530 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
00531 ((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00532  (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00533  (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00534  (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00535  ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
00536
00537 /** @brief  Clear the specified CAN pending flag.
00538   * @param  __HANDLE__: specifies the CAN Handle.
00539   * @param  __FLAG__: specifies the flag to check.
00540   *         This parameter can be one of the following values:
00541   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
00542   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
00543   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
00544   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
00545   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
00546   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
00547   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
00548   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
00549   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
00550   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
00551   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
00552   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
00553   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
00554   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
00555   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
00556   *            @arg CAN_FLAG_WKU: Wake up Flag
00557   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
00558   * @retval The new state of __FLAG__ (TRUE or FALSE).
00559   */
00560 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
00561 ((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00562  (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00563  (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00564  (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
00565
00566
00567 /** @brief  Check whether the specified CAN interrupt source is enabled or not.
00568   * @param  __HANDLE__: specifies the CAN Handle.
00569   * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
00570   *         This parameter can be one of the following values:
00571   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
00572   *            @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
00573   *            @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
00574   * @retval The new state of __IT__ (TRUE or FALSE).
00575   */
00576 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00577
00578 /**
00579   * @brief  Check the transmission status of a CAN Frame.
00580   * @param  __HANDLE__: specifies the CAN Handle.
00581   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
00582   * @retval The new status of transmission  (TRUE or FALSE).
00583   */
00584 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
00585 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
00586  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
00587  ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
00588
00589
00590
00591 /**
00592   * @brief  Release the specified receive FIFO.
00593   * @param  __HANDLE__: CAN handle.
00594   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00595   * @retval None
00596   */
00597 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
00598 ((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
00599
00600 /**
00601   * @brief  Cancel a transmit request.
00602   * @param  __HANDLE__: specifies the CAN Handle.
00603   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
00604   * @retval None
00605   */
00606 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
00607 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
00608  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
00609  ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
00610
00611 /**
00612   * @brief  Enable or disable the DBG Freeze for CAN.
00613   * @param  __HANDLE__: specifies the CAN Handle.
00614   * @param  __NEWSTATE__: new state of the CAN peripheral.
00615   *         This parameter can be: ENABLE (CAN reception/transmission is frozen
00616   *         during debug. Reception FIFO can still be accessed/controlled normally)
00617   *         or DISABLE (CAN is working during debug).
00618   * @retval None
00619   */
00620 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
00621 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
00622
00623 /**
00624  * @}
00625  */
00626
00627 /* Exported functions --------------------------------------------------------*/
00628 /** @addtogroup CAN_Exported_Functions CAN Exported Functions
00629   * @{
00630   */
00631
00632 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
00633  *  @brief    Initialization and Configuration functions
00634  * @{
00635  */
00636 /* addtogroup and de-initialization functions *****************************/
00637 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
00638 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
00639 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
00640 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
00641 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
00642 /**
00643  * @}
00644  */
00645
00646 /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
00647  *  @brief    I/O operation functions
00648  * @{
00649  */
00650 /* IO operation functions *****************************************************/
00651 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
00652 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
00653 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
00654 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
00655 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
00656 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
00657 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
00658 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
00659 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
00660 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
00661 /**
00662  * @}
00663  */
00664
00665 /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
00666  *  @brief   CAN Peripheral State functions
00667  * @{
00668  */
00669 /* Peripheral State and Error functions ***************************************/
00670 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
00671 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
00672 /**
00673  * @}
00674  */
00675
00676 /**
00677  * @}
00678  */
00679
00680 /* Private types -------------------------------------------------------------*/
00681 /* Private constants ---------------------------------------------------------*/
00682 /** @defgroup CAN_Private_Constants CAN Private Constants
00683   * @{
00684   */
00685 /** @defgroup CAN_transmit_constants CAN Transmit Constants
00686   * @{
00687   */
00688 #define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
00689 /**
00690   * @}
00691   */
00692 #define CAN_FLAG_MASK     ((uint32_t)0x000000FF)
00693
00694
00695 /**
00696   * @}
00697   */
00698
00699 /* Private macros ------------------------------------------------------------*/
00700 /** @defgroup CAN_Private_Macros CAN Private Macros
00701   * @{
00702   */
00703
00704 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
00705                            ((MODE) == CAN_MODE_LOOPBACK)|| \
00706                            ((MODE) == CAN_MODE_SILENT) || \
00707                            ((MODE) == CAN_MODE_SILENT_LOOPBACK))
00708
00709 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
00710                          ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
00711
00712 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
00713
00714 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
00715
00716 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
00717
00718 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
00719
00720 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
00721                                   ((MODE) == CAN_FILTERMODE_IDLIST))
00722
00723 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
00724                                     ((SCALE) == CAN_FILTERSCALE_32BIT))
00725
00726 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
00727                                   ((FIFO) == CAN_FILTER_FIFO1))
00728
00729 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
00730
00731 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
00732
00733 #define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
00734
00735 #define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
00736
00737 #define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
00738
00739 #define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
00740                                 ((IDTYPE) == CAN_ID_EXT))
00741
00742 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
00743
00744 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
00745
00746 /**
00747   * @}
00748   */
00749
00750 /* Private functions ---------------------------------------------------------*/
00751
00752 /**
00753   * @}
00754   */
00755
00756 /**
00757   * @}
00758   */
00759
00760
00761 #ifdef __cplusplus
00762 }
00763 #endif
00764
00765 #endif /* __STM32L4xx_CAN_H */
00766
00767
00768 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_comp.c Source File

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stm32l4xx_hal_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_comp.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   COMP HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the COMP peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Start/Stop operation functions in polling mode
00012   *           + Start/Stop operation functions in interrupt mode (through EXTI interrupt)
00013   *           + Peripheral control functions
00014   *           + Peripheral state functions
00015   *
00016   @verbatim
00017 ================================================================================
00018           ##### COMP Peripheral features #####
00019 ================================================================================
00020
00021   [..]
00022       The STM32L4xx device family integrates two analog comparators instances
00023       COMP1 and COMP2:
00024       (#) The COMP input minus (inverting input) and input plus (non inverting input)
00025           can be set to internal references or to GPIO pins
00026           (refer to GPIO list in reference manual).
00027
00028       (#) The COMP output level is available using HAL_COMP_GetOutputLevel()
00029           and can be redirected to other peripherals: GPIO pins (in mode
00030           alternate functions for comparator), timers.
00031           (refer to GPIO list in reference manual).
00032
00033       (#) Pairs of comparators instances can be combined in window mode
00034           (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
00035
00036       (#) The comparators have interrupt capability through the EXTI controller
00037           with wake-up from sleep and stop modes:
00038           (++) COMP1 is internally connected to EXTI Line 21
00039           (++) COMP2 is internally connected to EXTI Line 22
00040
00041           From the corresponding IRQ handler, the right interrupt source can be retrieved
00042           using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
00043
00044             ##### How to use this driver #####
00045 ================================================================================
00046   [..]
00047       This driver provides functions to configure and program the comparator instances
00048       of STM32L4xx devices.
00049
00050       To use the comparator, perform the following steps:
00051
00052       (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
00053       (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
00054            using HAL_GPIO_Init().
00055       (++) If needed, configure the GPIO connected to comparator output in alternate function mode
00056            using HAL_GPIO_Init().
00057       (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
00058            selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
00059            interrupt vector using HAL_NVIC_EnableIRQ() function.
00060
00061       (#) Configure the comparator using HAL_COMP_Init() function:
00062       (++) Select the input minus (inverting input)
00063       (++) Select the input plus (non-inverting input)
00064       (++) Select the hysteresis
00065       (++) Select the blanking source
00066       (++) Select the output polarity
00067       (++) Select the power mode
00068       (++) Select the window mode
00069
00070       -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
00071           to enable internal control clock of the comparators.
00072           However, this is a legacy strategy. In future STM32 families,
00073           COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
00074           Therefore, for compatibility anticipation, it is recommended to
00075           implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
00076
00077       (#) Reconfiguration on-the-fly of comparator can be done by calling again
00078           function HAL_COMP_Init() with new input structure parameters values.
00079
00080       (#) Enable the comparator using HAL_COMP_Start() function.
00081
00082       (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
00083           to manage comparator outputs (events and output level).
00084
00085       (#) Disable the comparator using HAL_COMP_Stop() function.
00086
00087       (#) De-initialize the comparator using HAL_COMP_DeInit() function.
00088
00089       (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
00090           The only way to unlock the comparator is a device hardware reset.
00091
00092   @endverbatim
00093   ******************************************************************************
00094
00095   Table 1. COMP inputs and output for STM32L4xx devices
00096   +---------------------------------------------------------+
00097   |                |                |   COMP1   |   COMP2   |
00098   |----------------|----------------|-----------|-----------|
00099   |                | IO1            |    PC5    |    PB4    |
00100   | Input plus     | IO2            |    PB2    |    PB6    |
00101   |                | IO3 (3)        |    PA1    |    PA3    |
00102   |----------------|----------------|-----------------------|
00103   |                | 1/4 VrefInt    | Available | Available |
00104   |                | 1/2 VrefInt    | Available | Available |
00105   |                | 3/4 VrefInt    | Available | Available |
00106   | Input minus    | VrefInt        | Available | Available |
00107   |                | DAC1 channel 1 | Available | Available |
00108   |                | DAC1 channel 2 | Available | Available |
00109   |                | IO1            |    PB1    |    PB3    |
00110   |                | IO2            |    PC4    |    PB7    |
00111   |                | IO3 (3)        |    PA0    |    PA2    |
00112   |                | IO4 (3)        |    PA4    |    PA4    |
00113   |                | IO5 (3)        |    PA5    |    PA5    |
00114   +---------------------------------------------------------+
00115   | Output         |                |  PB0  (1) |  PB5  (1) |
00116   |                |                |  PB10 (1) |  PB11 (1) |
00117   |                |                |  TIM  (2) |  TIM  (2) |
00118   +---------------------------------------------------------+
00119   (1) GPIO must be set to alternate function for comparator
00120   (2) Comparators output to timers is set in timers instances.
00121   (3) Only STM32L43x/L44x
00122
00123   ******************************************************************************
00124   * @attention
00125   *
00126   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00127   *
00128   * Redistribution and use in source and binary forms, with or without modification,
00129   * are permitted provided that the following conditions are met:
00130   *   1. Redistributions of source code must retain the above copyright notice,
00131   *      this list of conditions and the following disclaimer.
00132   *   2. Redistributions in binary form must reproduce the above copyright notice,
00133   *      this list of conditions and the following disclaimer in the documentation
00134   *      and/or other materials provided with the distribution.
00135   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00136   *      may be used to endorse or promote products derived from this software
00137   *      without specific prior written permission.
00138   *
00139   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00140   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00141   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00142   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00143   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00144   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00145   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00146   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00147   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00148   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00149   *
00150   ******************************************************************************
00151   */
00152
00153 /* Includes ------------------------------------------------------------------*/
00154 #include "stm32l4xx_hal.h"
00155
00156 /** @addtogroup STM32L4xx_HAL_Driver
00157   * @{
00158   */
00159
00160 /** @defgroup COMP COMP
00161   * @brief COMP HAL module driver
00162   * @{
00163   */
00164
00165 #ifdef HAL_COMP_MODULE_ENABLED
00166
00167 /* Private typedef -----------------------------------------------------------*/
00168 /* Private define ------------------------------------------------------------*/
00169 /** @addtogroup COMP_Private_Constants
00170   * @{
00171   */
00172
00173 /* Delay for COMP startup time.                                               */
00174 /* Note: Delay required to reach propagation delay specification.             */
00175 /* Literal set to maximum value (refer to device datasheet,                   */
00176 /* parameter "tSTART").                                                       */
00177 /* Unit: us                                                                   */
00178 #define COMP_DELAY_STARTUP_US             ((uint32_t) 80U)  /*!< Delay for COMP startup time */
00179
00180 /* Delay for COMP voltage scaler stabilization time.                          */
00181 /* Literal set to maximum value (refer to device datasheet,                   */
00182 /* parameter "tSTART_SCALER").                                                */
00183 /* Unit: us                                                                   */
00184 #define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)  /*!< Delay for COMP voltage scaler stabilization time */
00185
00186 #define COMP_OUTPUT_LEVEL_BITOFFSET_POS  ((uint32_t)  30U)
00187
00188 /**
00189   * @}
00190   */
00191
00192 /* Private macro -------------------------------------------------------------*/
00193 /* Private variables ---------------------------------------------------------*/
00194 /* Private function prototypes -----------------------------------------------*/
00195 /* Exported functions --------------------------------------------------------*/
00196
00197 /** @defgroup COMP_Exported_Functions COMP Exported Functions
00198   * @{
00199   */
00200
00201 /** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
00202  *  @brief    Initialization and de-initialization functions.
00203  *
00204 @verbatim
00205  ===============================================================================
00206               ##### Initialization and de-initialization functions #####
00207  ===============================================================================
00208     [..]  This section provides functions to initialize and de-initialize comparators
00209
00210 @endverbatim
00211   * @{
00212   */
00213
00214 /**
00215   * @brief  Initialize the COMP according to the specified
00216   *         parameters in the COMP_InitTypeDef and initialize the associated handle.
00217   * @note   If the selected comparator is locked, initialization can't be performed.
00218   *         To unlock the configuration, perform a system reset.
00219   * @param  hcomp  COMP handle
00220   * @retval HAL status
00221   */
00222 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
00223 {
00224   uint32_t tmp_csr = 0;
00225   uint32_t exti_line = 0;
00226   uint32_t comp_voltage_scaler_not_initialized = 0;
00227   __IO uint32_t wait_loop_index = 0;
00228   HAL_StatusTypeDef status = HAL_OK;
00229
00230   /* Check the COMP handle allocation and lock status */
00231   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00232   {
00233     status = HAL_ERROR;
00234   }
00235   else
00236   {
00237     /* Check the parameters */
00238     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00239     assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.NonInvertingInput));
00240     assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InvertingInput));
00241     assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
00242     assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
00243     assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
00244     assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
00245     assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
00246     assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
00247
00248     if(hcomp->State == HAL_COMP_STATE_RESET)
00249     {
00250       /* Allocate lock resource and initialize it */
00251       hcomp->Lock = HAL_UNLOCKED;
00252
00253       /* Init SYSCFG and the low level hardware to access comparators */
00254       /* Note: HAL_COMP_Init() calls __HAL_RCC_SYSCFG_CLK_ENABLE()            */
00255       /*       to enable internal control clock of the comparators.           */
00256       /*       However, this is a legacy strategy. In future STM32 families,  */
00257       /*       COMP clock enable must be implemented by user                  */
00258       /*       in "HAL_COMP_MspInit()".                                       */
00259       /*       Therefore, for compatibility anticipation, it is recommended   */
00260       /*       to implement __HAL_RCC_SYSCFG_CLK_ENABLE()                     */
00261       /*       in "HAL_COMP_MspInit()".                                       */
00262       __HAL_RCC_SYSCFG_CLK_ENABLE();
00263
00264       /* Init the low level hardware */
00265       HAL_COMP_MspInit(hcomp);
00266     }
00267
00268     /* Memorize voltage scaler state before initialization */
00269     comp_voltage_scaler_not_initialized = (READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) == 0);
00270
00271     /* Set COMP parameters */
00272     tmp_csr = (hcomp->Init.InvertingInput    |
00273                hcomp->Init.NonInvertingInput |
00274                hcomp->Init.BlankingSrce      |
00275                hcomp->Init.Hysteresis        |
00276                hcomp->Init.OutputPol         |
00277                hcomp->Init.Mode               );
00278
00279     /* Set parameters in COMP register */
00280     /* Note: Update all bits except read-only, lock and enable bits */
00281 #if defined (COMP_CSR_INMESEL)
00282     MODIFY_REG(hcomp->Instance->CSR,
00283                COMP_CSR_PWRMODE  | COMP_CSR_INMSEL   | COMP_CSR_INPSEL  |
00284                COMP_CSR_WINMODE  | COMP_CSR_POLARITY | COMP_CSR_HYST    |
00285                COMP_CSR_BLANKING | COMP_CSR_BRGEN    | COMP_CSR_SCALEN  | COMP_CSR_INMESEL,
00286                tmp_csr
00287               );
00288 #else
00289     MODIFY_REG(hcomp->Instance->CSR,
00290                COMP_CSR_PWRMODE  | COMP_CSR_INMSEL   | COMP_CSR_INPSEL  |
00291                COMP_CSR_WINMODE  | COMP_CSR_POLARITY | COMP_CSR_HYST    |
00292                COMP_CSR_BLANKING | COMP_CSR_BRGEN    | COMP_CSR_SCALEN,
00293                tmp_csr
00294               );
00295 #endif
00296
00297     /* Set window mode */
00298     /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP     */
00299     /*       instances. Therefore, this function can update another COMP      */
00300     /*       instance that the one currently selected.                        */
00301     if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
00302     {
00303       SET_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
00304     }
00305     else
00306     {
00307       CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
00308     }
00309
00310     /* Delay for COMP scaler bridge voltage stabilization */
00311     /* Apply the delay if voltage scaler bridge is enabled for the first time */
00312     if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0) &&
00313         (comp_voltage_scaler_not_initialized != 0)               )
00314     {
00315       /* Wait loop initialization and execution */
00316       /* Note: Variable divided by 2 to compensate partially                  */
00317       /*       CPU processing cycles.                                         */
00318       wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2)));
00319       while(wait_loop_index != 0)
00320       {
00321         wait_loop_index--;
00322       }
00323     }
00324
00325     /* Get the EXTI line corresponding to the selected COMP instance */
00326     exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00327
00328     /* Manage EXTI settings */
00329     if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != RESET)
00330     {
00331       /* Configure EXTI rising edge */
00332       if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET)
00333       {
00334         SET_BIT(EXTI->RTSR1, exti_line);
00335       }
00336       else
00337       {
00338         CLEAR_BIT(EXTI->RTSR1, exti_line);
00339       }
00340
00341       /* Configure EXTI falling edge */
00342       if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET)
00343       {
00344         SET_BIT(EXTI->FTSR1, exti_line);
00345       }
00346       else
00347       {
00348         CLEAR_BIT(EXTI->FTSR1, exti_line);
00349       }
00350
00351       /* Clear COMP EXTI pending bit (if any) */
00352       WRITE_REG(EXTI->PR1, exti_line);
00353
00354       /* Configure EXTI event mode */
00355       if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET)
00356       {
00357         SET_BIT(EXTI->EMR1, exti_line);
00358       }
00359       else
00360       {
00361         CLEAR_BIT(EXTI->EMR1, exti_line);
00362       }
00363
00364       /* Configure EXTI interrupt mode */
00365       if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET)
00366       {
00367         SET_BIT(EXTI->IMR1, exti_line);
00368       }
00369       else
00370       {
00371         CLEAR_BIT(EXTI->IMR1, exti_line);
00372       }
00373     }
00374     else
00375     {
00376       /* Disable EXTI event mode */
00377       CLEAR_BIT(EXTI->EMR1, exti_line);
00378
00379       /* Disable EXTI interrupt mode */
00380       CLEAR_BIT(EXTI->IMR1, exti_line);
00381     }
00382
00383     /* Set HAL COMP handle state */
00384     /* Note: Transition from state reset to state ready,                      */
00385     /*       otherwise (coming from state ready or busy) no state update.     */
00386     if (hcomp->State == HAL_COMP_STATE_RESET)
00387     {
00388       hcomp->State = HAL_COMP_STATE_READY;
00389     }
00390   }
00391
00392   return status;
00393 }
00394
00395 /**
00396   * @brief  DeInitialize the COMP peripheral.
00397   * @note   Deinitialization cannot be performed if the COMP configuration is locked.
00398   *         To unlock the configuration, perform a system reset.
00399   * @param  hcomp  COMP handle
00400   * @retval HAL status
00401   */
00402 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
00403 {
00404   HAL_StatusTypeDef status = HAL_OK;
00405
00406   /* Check the COMP handle allocation and lock status */
00407   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00408   {
00409     status = HAL_ERROR;
00410   }
00411   else
00412   {
00413     /* Check the parameter */
00414     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00415
00416     /* Set COMP_CSR register to reset value */
00417     WRITE_REG(hcomp->Instance->CSR, 0x00000000);
00418
00419     /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
00420     HAL_COMP_MspDeInit(hcomp);
00421
00422     /* Set HAL COMP handle state */
00423     hcomp->State = HAL_COMP_STATE_RESET;
00424
00425     /* Release Lock */
00426     __HAL_UNLOCK(hcomp);
00427   }
00428
00429   return status;
00430 }
00431
00432 /**
00433   * @brief  Initialize the COMP MSP.
00434   * @param  hcomp  COMP handle
00435   * @retval None
00436   */
00437 __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
00438 {
00439   /* Prevent unused argument(s) compilation warning */
00440   UNUSED(hcomp);
00441
00442   /* NOTE : This function should not be modified, when the callback is needed,
00443             the HAL_COMP_MspInit could be implemented in the user file
00444    */
00445 }
00446
00447 /**
00448   * @brief  DeInitialize the COMP MSP.
00449   * @param  hcomp  COMP handle
00450   * @retval None
00451   */
00452 __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
00453 {
00454   /* Prevent unused argument(s) compilation warning */
00455   UNUSED(hcomp);
00456
00457   /* NOTE : This function should not be modified, when the callback is needed,
00458             the HAL_COMP_MspDeInit could be implemented in the user file
00459    */
00460 }
00461
00462 /**
00463   * @}
00464   */
00465
00466 /** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
00467  *  @brief   Start-Stop operation functions.
00468  *
00469 @verbatim
00470  ===============================================================================
00471                       ##### IO operation functions #####
00472  ===============================================================================
00473     [..]  This section provides functions allowing to:
00474       (+) Start a comparator instance.
00475       (+) Stop a comparator instance.
00476
00477 @endverbatim
00478   * @{
00479   */
00480
00481 /**
00482   * @brief  Start the comparator.
00483   * @param  hcomp  COMP handle
00484   * @retval HAL status
00485   */
00486 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
00487 {
00488   __IO uint32_t wait_loop_index = 0;
00489   HAL_StatusTypeDef status = HAL_OK;
00490
00491   /* Check the COMP handle allocation and lock status */
00492   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00493   {
00494     status = HAL_ERROR;
00495   }
00496   else
00497   {
00498     /* Check the parameter */
00499     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00500
00501     if(hcomp->State == HAL_COMP_STATE_READY)
00502     {
00503       /* Enable the selected comparator */
00504       SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
00505
00506       /* Set HAL COMP handle state */
00507       hcomp->State = HAL_COMP_STATE_BUSY;
00508
00509       /* Delay for COMP startup time */
00510       /* Wait loop initialization and execution */
00511       /* Note: Variable divided by 2 to compensate partially                  */
00512       /*       CPU processing cycles.                                         */
00513       wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000 * 2)));
00514       while(wait_loop_index != 0)
00515       {
00516         wait_loop_index--;
00517       }
00518     }
00519     else
00520     {
00521       status = HAL_ERROR;
00522     }
00523   }
00524
00525   return status;
00526 }
00527
00528 /**
00529   * @brief  Stop the comparator.
00530   * @param  hcomp  COMP handle
00531   * @retval HAL status
00532   */
00533 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
00534 {
00535   HAL_StatusTypeDef status = HAL_OK;
00536
00537   /* Check the COMP handle allocation and lock status */
00538   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00539   {
00540     status = HAL_ERROR;
00541   }
00542   else
00543   {
00544     /* Check the parameter */
00545     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00546
00547     if((hcomp->State == HAL_COMP_STATE_BUSY)  ||
00548        (hcomp->State == HAL_COMP_STATE_READY)   )
00549     {
00550       /* Disable the selected comparator */
00551       CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
00552
00553       /* Set HAL COMP handle state */
00554       hcomp->State = HAL_COMP_STATE_READY;
00555     }
00556     else
00557     {
00558       status = HAL_ERROR;
00559     }
00560   }
00561
00562   return status;
00563 }
00564
00565 /**
00566   * @brief  Comparator IRQ handler.
00567   * @param  hcomp  COMP handle
00568   * @retval None
00569   */
00570 void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
00571 {
00572   /* Get the EXTI line corresponding to the selected COMP instance */
00573   uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00574
00575   /* Check COMP EXTI flag */
00576   if(READ_BIT(EXTI->PR1, exti_line) != RESET)
00577   {
00578     /* Check whether comparator is in independent or window mode */
00579     if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != RESET)
00580     {
00581       /* Clear COMP EXTI line pending bit of the pair of comparators          */
00582       /* in window mode.                                                      */
00583       /* Note: Pair of comparators in window mode can both trig IRQ when      */
00584       /*       input voltage is changing from "out of window" area            */
00585       /*       (low or high ) to the other "out of window" area (high or low).*/
00586       /*       Both flags must be cleared to call comparator trigger          */
00587       /*       callback is called once.                                       */
00588       WRITE_REG(EXTI->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
00589     }
00590     else
00591     {
00592       /* Clear COMP EXTI line pending bit */
00593       WRITE_REG(EXTI->PR1, exti_line);
00594     }
00595
00596     /* COMP trigger user callback */
00597     HAL_COMP_TriggerCallback(hcomp);
00598   }
00599 }
00600
00601 /**
00602   * @}
00603   */
00604
00605 /** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
00606  *  @brief   Management functions.
00607  *
00608 @verbatim
00609  ===============================================================================
00610                       ##### Peripheral Control functions #####
00611  ===============================================================================
00612     [..]
00613     This subsection provides a set of functions allowing to control the comparators.
00614
00615 @endverbatim
00616   * @{
00617   */
00618
00619 /**
00620   * @brief  Lock the selected comparator configuration.
00621   * @note   A system reset is required to unlock the comparator configuration.
00622   * @note   Locking the comparator from reset state is possible
00623   *         if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
00624   * @param  hcomp  COMP handle
00625   * @retval HAL status
00626   */
00627 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
00628 {
00629   HAL_StatusTypeDef status = HAL_OK;
00630
00631   /* Check the COMP handle allocation and lock status */
00632   if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
00633   {
00634     status = HAL_ERROR;
00635   }
00636   else
00637   {
00638     /* Check the parameter */
00639     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00640
00641     /* Set HAL COMP handle state */
00642     hcomp->State = ((HAL_COMP_StateTypeDef)(hcomp->State | COMP_STATE_BITFIELD_LOCK));
00643   }
00644
00645   if(status == HAL_OK)
00646   {
00647     /* Set the lock bit corresponding to selected comparator */
00648     __HAL_COMP_LOCK(hcomp);
00649   }
00650
00651   return status;
00652 }
00653
00654 /**
00655   * @brief  Return the output level (high or low) of the selected comparator.
00656   *         The output level depends on the selected polarity.
00657   *         If the polarity is not inverted:
00658   *           - Comparator output is low when the input plus is at a lower
00659   *             voltage than the input minus
00660   *           - Comparator output is high when the input plus is at a higher
00661   *             voltage than the input minus
00662   *         If the polarity is inverted:
00663   *           - Comparator output is high when the input plus is at a lower
00664   *             voltage than the input minus
00665   *           - Comparator output is low when the input plus is at a higher
00666   *             voltage than the input minus
00667   * @param  hcomp  COMP handle
00668   * @retval Returns the selected comparator output level:
00669   *         @arg @ref COMP_OUTPUT_LEVEL_LOW
00670   *         @arg @ref COMP_OUTPUT_LEVEL_HIGH
00671   *
00672   */
00673 uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
00674 {
00675   /* Check the parameter */
00676   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00677
00678   return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE)
00679                     >> COMP_OUTPUT_LEVEL_BITOFFSET_POS);
00680 }
00681
00682 /**
00683   * @brief  Comparator callback.
00684   * @param  hcomp  COMP handle
00685   * @retval None
00686   */
00687 __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
00688 {
00689   /* Prevent unused argument(s) compilation warning */
00690   UNUSED(hcomp);
00691
00692   /* NOTE : This function should not be modified, when the callback is needed,
00693             the HAL_COMP_TriggerCallback should be implemented in the user file
00694    */
00695 }
00696
00697
00698 /**
00699   * @}
00700   */
00701
00702 /** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
00703  *  @brief   Peripheral State functions.
00704  *
00705 @verbatim
00706  ===============================================================================
00707                       ##### Peripheral State functions #####
00708  ===============================================================================
00709     [..]
00710     This subsection permit to get in run-time the status of the peripheral.
00711
00712 @endverbatim
00713   * @{
00714   */
00715
00716 /**
00717   * @brief  Return the COMP handle state.
00718   * @param  hcomp  COMP handle
00719   * @retval HAL state
00720   */
00721 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
00722 {
00723   /* Check the COMP handle allocation */
00724   if(hcomp == NULL)
00725   {
00726     return HAL_COMP_STATE_RESET;
00727   }
00728
00729   /* Check the parameter */
00730   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00731
00732   /* Return HAL COMP handle state */
00733   return hcomp->State;
00734 }
00735
00736 /**
00737   * @}
00738   */
00739
00740 /**
00741   * @}
00742   */
00743
00744 #endif /* HAL_COMP_MODULE_ENABLED */
00745 /**
00746   * @}
00747   */
00748
00749 /**
00750   * @}
00751   */
00752
00753 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_comp.h Source File

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stm32l4xx_hal_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_comp.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of COMP HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_COMP_H
00040 #define __STM32L4xx_HAL_COMP_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup COMP
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup COMP_Exported_Types COMP Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  COMP Init structure definition
00064   */
00065 typedef struct
00066 {
00067
00068   uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
00069                                     (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
00070                                     Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
00071                                     This parameter can be a value of @ref COMP_WindowMode */
00072
00073   uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
00074                                     Note: For the characteritics of comparator power modes
00075                                           (propagation delay and power consumption), refer to device datasheet.
00076                                     This parameter can be a value of @ref COMP_PowerMode */
00077
00078   uint32_t NonInvertingInput;  /*!< Set comparator input plus (non-inverting input).
00079                                     This parameter can be a value of @ref COMP_InputPlus */
00080
00081   uint32_t InvertingInput;     /*!< Set comparator input minus (inverting input).
00082                                     This parameter can be a value of @ref COMP_InputMinus */
00083
00084   uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
00085                                     This parameter can be a value of @ref COMP_Hysteresis */
00086
00087   uint32_t OutputPol;          /*!< Set comparator output polarity.
00088                                     This parameter can be a value of @ref COMP_OutputPolarity */
00089
00090   uint32_t BlankingSrce;       /*!< Set comparator blanking source.
00091                                     This parameter can be a value of @ref COMP_BlankingSrce */
00092
00093   uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
00094                                     This parameter can be a value of @ref COMP_EXTI_TriggerMode */
00095
00096 }COMP_InitTypeDef;
00097
00098 /**
00099   * @brief  HAL COMP state machine: HAL COMP states definition
00100   */
00101 #define COMP_STATE_BITFIELD_LOCK  ((uint32_t)0x10)
00102 typedef enum
00103 {
00104   HAL_COMP_STATE_RESET             = 0x00,                                              /*!< COMP not yet initialized                             */
00105   HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
00106   HAL_COMP_STATE_READY             = 0x01,                                              /*!< COMP initialized and ready for use                   */
00107   HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
00108   HAL_COMP_STATE_BUSY              = 0x02,                                              /*!< COMP is running                                      */
00109   HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
00110 }HAL_COMP_StateTypeDef;
00111
00112 /**
00113   * @brief  COMP Handle Structure definition
00114   */
00115 typedef struct
00116 {
00117   COMP_TypeDef       *Instance;       /*!< Register base address    */
00118   COMP_InitTypeDef   Init;            /*!< COMP required parameters */
00119   HAL_LockTypeDef    Lock;            /*!< Locking object           */
00120   __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
00121 } COMP_HandleTypeDef;
00122
00123 /**
00124   * @}
00125   */
00126
00127 /* Exported constants --------------------------------------------------------*/
00128 /** @defgroup COMP_Exported_Constants COMP Exported Constants
00129   * @{
00130   */
00131
00132 /** @defgroup COMP_WindowMode COMP Window Mode
00133   * @{
00134   */
00135 #define COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
00136 #define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
00137
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup COMP_PowerMode COMP power mode
00143   * @{
00144   */
00145 /* Note: For the characteritics of comparator power modes                     */
00146 /*       (propagation delay and power consumption),                           */
00147 /*       refer to device datasheet.                                           */
00148 #define COMP_POWERMODE_HIGHSPEED       ((uint32_t)0x00000000) /*!< High Speed */
00149 #define COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_PWRMODE_0)   /*!< Medium Speed */
00150 #define COMP_POWERMODE_ULTRALOWPOWER   (COMP_CSR_PWRMODE)     /*!< Ultra-low power mode */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
00156   * @{
00157   */
00158 #define COMP_INPUT_PLUS_IO1            ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
00159 #define COMP_INPUT_PLUS_IO2            (COMP_CSR_INPSEL_0)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
00160 #if defined(COMP_CSR_INPSEL_1)
00161 #define COMP_INPUT_PLUS_IO3            (COMP_CSR_INPSEL_1)    /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
00162 #endif
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup COMP_InputMinus COMP input minus (inverting input)
00168   * @{
00169   */
00170 #define COMP_INPUT_MINUS_1_4VREFINT    (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt */
00171 #define COMP_INPUT_MINUS_1_2VREFINT    (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt */
00172 #define COMP_INPUT_MINUS_3_4VREFINT    (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt */
00173 #define COMP_INPUT_MINUS_VREFINT       (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
00174 #define COMP_INPUT_MINUS_DAC1_CH1      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
00175 #define COMP_INPUT_MINUS_DAC1_CH2      (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
00176 #define COMP_INPUT_MINUS_IO1           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
00177 #define COMP_INPUT_MINUS_IO2           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
00178 #if defined(COMP_CSR_INMESEL_1)
00179 #define COMP_INPUT_MINUS_IO3           (                     COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
00180 #define COMP_INPUT_MINUS_IO4           (COMP_CSR_INMESEL_1                      | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
00181 #define COMP_INPUT_MINUS_IO5           (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
00182 #endif
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup COMP_Hysteresis COMP hysteresis
00188   * @{
00189   */
00190 #define COMP_HYSTERESIS_NONE           ((uint32_t)0x00000000) /*!< No hysteresis */
00191 #define COMP_HYSTERESIS_LOW            (COMP_CSR_HYST_0)      /*!< Hysteresis level low */
00192 #define COMP_HYSTERESIS_MEDIUM         (COMP_CSR_HYST_1)      /*!< Hysteresis level medium */
00193 #define COMP_HYSTERESIS_HIGH           (COMP_CSR_HYST)        /*!< Hysteresis level high */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup COMP_OutputPolarity COMP output Polarity
00199   * @{
00200   */
00201 #define COMP_OUTPUTPOL_NONINVERTED     ((uint32_t)0x00000000) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
00202 #define COMP_OUTPUTPOL_INVERTED        (COMP_CSR_POLARITY)    /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup COMP_BlankingSrce  COMP blanking source
00208   * @{
00209   */
00210 #define COMP_BLANKINGSRC_NONE                    ((uint32_t)0x00000000) /*!< No blanking source */
00211 /* Blanking sources for COMP instance: COMP1 */
00212 #define COMP_BLANKINGSRC_TIM1_OC5_COMP1          (COMP_CSR_BLANKING_0)  /*!< Blanking source for COMP1: TIM1 OC5 selected as blanking source for comparator */
00213 #define COMP_BLANKINGSRC_TIM2_OC3_COMP1          (COMP_CSR_BLANKING_1)  /*!< Blanking source for COMP1: TIM2 OC3 selected as blanking source for comparator */
00214 #define COMP_BLANKINGSRC_TIM3_OC3_COMP1          (COMP_CSR_BLANKING_2)  /*!< Blanking source for COMP1: TIM3 OC3 selected as blanking source for comparator */
00215 /* Blanking sources for COMP instance: COMP2 */
00216 #define COMP_BLANKINGSRC_TIM3_OC4_COMP2          (COMP_CSR_BLANKING_0)  /*!< Blanking source for COMP2: TIM3 OC4 selected as blanking source for comparator */
00217 #define COMP_BLANKINGSRC_TIM8_OC5_COMP2          (COMP_CSR_BLANKING_1)  /*!< Blanking source for COMP2: TIM8 OC5 selected as blanking source for comparator */
00218 #define COMP_BLANKINGSRC_TIM15_OC1_COMP2         (COMP_CSR_BLANKING_2)  /*!< Blanking source for COMP2: TIM15 OC1 selected as blanking source for comparator */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup COMP_OutputLevel COMP Output Level
00224   * @{
00225   */
00226 /* Note: Comparator output level values are fixed to "0" and "1",             */
00227 /* corresponding COMP register bit is managed by HAL function to match        */
00228 /* with these values (independently of bit position in register).             */
00229
00230 /* When output polarity is not inverted, comparator output is low when
00231    the input plus is at a lower voltage than the input minus */
00232 #define COMP_OUTPUT_LEVEL_LOW              ((uint32_t)0x00000000)
00233 /* When output polarity is not inverted, comparator output is high when
00234    the input plus is at a higher voltage than the input minus */
00235 #define COMP_OUTPUT_LEVEL_HIGH             ((uint32_t)0x00000001)
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
00241   * @{
00242   */
00243 #define COMP_TRIGGERMODE_NONE                 ((uint32_t)0x00000000)                                    /*!< Comparator output triggering no External Interrupt Line */
00244 #define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
00245 #define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
00246 #define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
00247 #define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
00248 #define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
00249 #define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
00250 /**
00251   * @}
00252   */
00253
00254 /**
00255   * @}
00256   */
00257
00258 /* Exported macro ------------------------------------------------------------*/
00259 /** @defgroup COMP_Exported_Macros COMP Exported Macros
00260   * @{
00261   */
00262
00263 /** @defgroup COMP_Handle_Management  COMP Handle Management
00264   * @{
00265   */
00266
00267 /** @brief  Reset COMP handle state.
00268   * @param  __HANDLE__  COMP handle
00269   * @retval None
00270   */
00271 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
00272
00273 /**
00274   * @brief  Enable the specified comparator.
00275   * @param  __HANDLE__  COMP handle
00276   * @retval None
00277   */
00278 #define __HAL_COMP_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
00279
00280 /**
00281   * @brief  Disable the specified comparator.
00282   * @param  __HANDLE__  COMP handle
00283   * @retval None
00284   */
00285 #define __HAL_COMP_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
00286
00287 /**
00288   * @brief  Lock the specified comparator configuration.
00289   * @note   Using this macro induce HAL COMP handle state machine being no
00290   *         more in line with COMP instance state.
00291   *         To keep HAL COMP handle state machine updated, it is recommended
00292   *         to use function "HAL_COMP_Lock')".
00293   * @param  __HANDLE__  COMP handle
00294   * @retval None
00295   */
00296 #define __HAL_COMP_LOCK(__HANDLE__)                SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
00297
00298 /**
00299   * @brief  Check whether the specified comparator is locked.
00300   * @param  __HANDLE__  COMP handle
00301   * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
00302   */
00303 #define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
00304
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup COMP_Exti_Management  COMP external interrupt line management
00310   * @{
00311   */
00312
00313 /**
00314   * @brief  Enable the COMP1 EXTI line rising edge trigger.
00315   * @retval None
00316   */
00317 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
00318
00319 /**
00320   * @brief  Disable the COMP1 EXTI line rising edge trigger.
00321   * @retval None
00322   */
00323 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
00324
00325 /**
00326   * @brief  Enable the COMP1 EXTI line falling edge trigger.
00327   * @retval None
00328   */
00329 #define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
00330
00331 /**
00332   * @brief  Disable the COMP1 EXTI line falling edge trigger.
00333   * @retval None
00334   */
00335 #define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
00336
00337 /**
00338   * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
00339   * @retval None
00340   */
00341 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00342                                                                __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
00343                                                                __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
00344                                                              } while(0)
00345
00346 /**
00347   * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
00348   * @retval None
00349   */
00350 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00351                                                                __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
00352                                                                __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
00353                                                              } while(0)
00354
00355 /**
00356   * @brief  Enable the COMP1 EXTI line in interrupt mode.
00357   * @retval None
00358   */
00359 #define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
00360
00361 /**
00362   * @brief  Disable the COMP1 EXTI line in interrupt mode.
00363   * @retval None
00364   */
00365 #define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1)
00366
00367 /**
00368   * @brief  Generate a software interrupt on the COMP1 EXTI line.
00369   * @retval None
00370   */
00371 #define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
00372
00373 /**
00374   * @brief  Enable the COMP1 EXTI line in event mode.
00375   * @retval None
00376   */
00377 #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()          SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
00378
00379 /**
00380   * @brief  Disable the COMP1 EXTI line in event mode.
00381   * @retval None
00382   */
00383 #define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()         CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1)
00384
00385 /**
00386   * @brief  Check whether the COMP1 EXTI line flag is set.
00387   * @retval RESET or SET
00388   */
00389 #define __HAL_COMP_COMP1_EXTI_GET_FLAG()              READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP1)
00390
00391 /**
00392   * @brief  Clear the COMP1 EXTI flag.
00393   * @retval None
00394   */
00395 #define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP1)
00396
00397 /**
00398   * @brief  Enable the COMP2 EXTI line rising edge trigger.
00399   * @retval None
00400   */
00401 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
00402
00403 /**
00404   * @brief  Disable the COMP2 EXTI line rising edge trigger.
00405   * @retval None
00406   */
00407 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
00408
00409 /**
00410   * @brief  Enable the COMP2 EXTI line falling edge trigger.
00411   * @retval None
00412   */
00413 #define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
00414
00415 /**
00416   * @brief  Disable the COMP2 EXTI line falling edge trigger.
00417   * @retval None
00418   */
00419 #define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
00420
00421 /**
00422   * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
00423   * @retval None
00424   */
00425 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00426                                                                __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
00427                                                                __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
00428                                                              } while(0)
00429
00430 /**
00431   * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
00432   * @retval None
00433   */
00434 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
00435                                                                __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
00436                                                                __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
00437                                                              } while(0)
00438
00439 /**
00440   * @brief  Enable the COMP2 EXTI line in interrupt mode.
00441   * @retval None
00442   */
00443 #define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
00444
00445 /**
00446   * @brief  Disable the COMP2 EXTI line in interrupt mode.
00447   * @retval None
00448   */
00449 #define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2)
00450
00451 /**
00452   * @brief  Generate a software interrupt on the COMP2 EXTI line.
00453   * @retval None
00454   */
00455 #define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
00456
00457 /**
00458   * @brief  Enable the COMP2 EXTI line in event mode.
00459   * @retval None
00460   */
00461 #define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()           SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
00462
00463 /**
00464   * @brief  Disable the COMP2 EXTI line in event mode.
00465   * @retval None
00466   */
00467 #define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2)
00468
00469 /**
00470   * @brief  Check whether the COMP2 EXTI line flag is set.
00471   * @retval RESET or SET
00472   */
00473 #define __HAL_COMP_COMP2_EXTI_GET_FLAG()              READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP2)
00474
00475 /**
00476   * @brief  Clear the COMP2 EXTI flag.
00477   * @retval None
00478   */
00479 #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP2)
00480
00481 /**
00482   * @}
00483   */
00484
00485 /**
00486   * @}
00487   */
00488
00489
00490 /* Private types -------------------------------------------------------------*/
00491 /* Private constants ---------------------------------------------------------*/
00492 /** @defgroup COMP_Private_Constants COMP Private Constants
00493   * @{
00494   */
00495 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00496   * @{
00497   */
00498 #define COMP_EXTI_LINE_COMP1           (EXTI_IMR1_IM21)  /*!< EXTI line 21 connected to COMP1 output */
00499 #define COMP_EXTI_LINE_COMP2           (EXTI_IMR1_IM22)  /*!< EXTI line 22 connected to COMP2 output */
00500 /**
00501   * @}
00502   */
00503
00504 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00505   * @{
00506   */
00507 #define COMP_EXTI_IT                        ((uint32_t) 0x01)  /*!< EXTI line event with interruption */
00508 #define COMP_EXTI_EVENT                     ((uint32_t) 0x02)  /*!< EXTI line event only (without interruption) */
00509 #define COMP_EXTI_RISING                    ((uint32_t) 0x10)  /*!< EXTI line event on rising edge */
00510 #define COMP_EXTI_FALLING                   ((uint32_t) 0x20)  /*!< EXTI line event on falling edge */
00511 /**
00512   * @}
00513   */
00514
00515 /**
00516   * @}
00517   */
00518
00519 /* Private macros ------------------------------------------------------------*/
00520 /** @defgroup COMP_Private_Macros COMP Private Macros
00521   * @{
00522   */
00523
00524 /** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
00525   * @{
00526   */
00527 /**
00528   * @brief  Get the specified EXTI line for a comparator instance.
00529   * @param  __INSTANCE__  specifies the COMP instance.
00530   * @retval value of @ref COMP_ExtiLine
00531   */
00532 #define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ?                 \
00533                                              COMP_EXTI_LINE_COMP1 : COMP_EXTI_LINE_COMP2)
00534 /**
00535   * @}
00536   */
00537
00538 /** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
00539   * @{
00540   */
00541 #define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
00542                                              ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )
00543
00544 #define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
00545                                              ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
00546                                              ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
00547
00548 #if defined(COMP_CSR_INPSEL_1)
00549 #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
00550                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
00551                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
00552 #else
00553 #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
00554                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
00555 #endif
00556
00557 /* Note: On this STM32 family, comparator input minus parameters are          */
00558 /*       the same on all COMP instances.                                      */
00559 /*       However, comparator instance kept as macro parameter for             */
00560 /*       compatibility with other STM32 families.                             */
00561 #if defined(COMP_CSR_INMESEL_1)
00562 #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
00563                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
00564                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
00565                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
00566                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
00567                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
00568                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
00569                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
00570                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)         || \
00571                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4)         || \
00572                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
00573 #else
00574 #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
00575                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
00576                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
00577                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
00578                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
00579                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
00580                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
00581                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
00582 #endif
00583
00584 #define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
00585                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
00586                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
00587                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
00588
00589 #define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
00590                                              ((__POL__) == COMP_OUTPUTPOL_INVERTED))
00591
00592 #define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
00593                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  || \
00594                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  || \
00595                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  || \
00596                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2)  || \
00597                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)  || \
00598                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))
00599
00600 #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__)  \
00601    ((((__INSTANCE__) == COMP1) &&                                     \
00602     (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)            ||      \
00603      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
00604      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
00605      ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)))        \
00606     ||                                                                \
00607     (((__INSTANCE__) == COMP2) &&                                     \
00608      (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE)           ||      \
00609       ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) ||      \
00610       ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) ||      \
00611       ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
00612
00613 #define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
00614                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
00615                                              ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
00616                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
00617                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
00618                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
00619                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
00620
00621 #define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
00622                                                 ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
00623
00624 /**
00625   * @}
00626   */
00627
00628 /**
00629   * @}
00630   */
00631
00632
00633 /* Exported functions --------------------------------------------------------*/
00634 /** @addtogroup COMP_Exported_Functions
00635   * @{
00636   */
00637
00638 /** @addtogroup COMP_Exported_Functions_Group1
00639   * @{
00640   */
00641
00642 /* Initialization and de-initialization functions  **********************************/
00643 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
00644 HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
00645 void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
00646 void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
00647 /**
00648   * @}
00649   */
00650
00651 /* IO operation functions  *****************************************************/
00652 /** @addtogroup COMP_Exported_Functions_Group2
00653   * @{
00654   */
00655 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
00656 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
00657 void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
00658 /**
00659   * @}
00660   */
00661
00662 /* Peripheral Control functions  ************************************************/
00663 /** @addtogroup COMP_Exported_Functions_Group3
00664   * @{
00665   */
00666 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
00667 uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
00668 /* Callback in interrupt mode */
00669 void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
00670 /**
00671   * @}
00672   */
00673
00674 /* Peripheral State functions  **************************************************/
00675 /** @addtogroup COMP_Exported_Functions_Group4
00676   * @{
00677   */
00678 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
00679 /**
00680   * @}
00681   */
00682
00683 /**
00684   * @}
00685   */
00686
00687 /**
00688   * @}
00689   */
00690
00691 /**
00692   * @}
00693   */
00694
00695 #ifdef __cplusplus
00696 }
00697 #endif
00698
00699 #endif /* __STM32L4xx_HAL_COMP_H */
00700
00701 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_conf.h Source File

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stm32l4xx_hal_conf.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_conf.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   HAL configuration template file.
00008   *          This file should be copied to the application folder and renamed
00009   *          to stm32l4xx_hal_conf.h.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00014   *
00015   * Redistribution and use in source and binary forms, with or without modification,
00016   * are permitted provided that the following conditions are met:
00017   *   1. Redistributions of source code must retain the above copyright notice,
00018   *      this list of conditions and the following disclaimer.
00019   *   2. Redistributions in binary form must reproduce the above copyright notice,
00020   *      this list of conditions and the following disclaimer in the documentation
00021   *      and/or other materials provided with the distribution.
00022   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00023   *      may be used to endorse or promote products derived from this software
00024   *      without specific prior written permission.
00025   *
00026   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00027   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00028   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00029   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00030   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00032   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00033   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00034   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036   *
00037   ******************************************************************************
00038   */
00039
00040 /* Define to prevent recursive inclusion -------------------------------------*/
00041 #ifndef __STM32L4xx_HAL_CONF_H
00042 #define __STM32L4xx_HAL_CONF_H
00043
00044 #ifdef __cplusplus
00045  extern "C" {
00046 #endif
00047
00048 /* Exported types ------------------------------------------------------------*/
00049 /* Exported constants --------------------------------------------------------*/
00050
00051 /* ########################## Module Selection ############################## */
00052 /**
00053   * @brief This is the list of modules to be used in the HAL driver
00054   */
00055 #define HAL_MODULE_ENABLED
00056 #define HAL_ADC_MODULE_ENABLED
00057 #define HAL_CAN_MODULE_ENABLED
00058 #define HAL_COMP_MODULE_ENABLED
00059 #define HAL_CORTEX_MODULE_ENABLED
00060 #define HAL_CRC_MODULE_ENABLED
00061 #define HAL_CRYP_MODULE_ENABLED
00062 #define HAL_DAC_MODULE_ENABLED
00063 #define HAL_DFSDM_MODULE_ENABLED
00064 #define HAL_DMA_MODULE_ENABLED
00065 #define HAL_FIREWALL_MODULE_ENABLED
00066 #define HAL_FLASH_MODULE_ENABLED
00067 #define HAL_HCD_MODULE_ENABLED
00068 #define HAL_NAND_MODULE_ENABLED
00069 #define HAL_NOR_MODULE_ENABLED
00070 #define HAL_SRAM_MODULE_ENABLED
00071 #define HAL_GPIO_MODULE_ENABLED
00072 #define HAL_I2C_MODULE_ENABLED
00073 #define HAL_IRDA_MODULE_ENABLED
00074 #define HAL_IWDG_MODULE_ENABLED
00075 #define HAL_LCD_MODULE_ENABLED
00076 #define HAL_LPTIM_MODULE_ENABLED
00077 #define HAL_OPAMP_MODULE_ENABLED
00078 #define HAL_PCD_MODULE_ENABLED
00079 #define HAL_PWR_MODULE_ENABLED
00080 #define HAL_QSPI_MODULE_ENABLED
00081 #define HAL_RCC_MODULE_ENABLED
00082 #define HAL_RNG_MODULE_ENABLED
00083 #define HAL_RTC_MODULE_ENABLED
00084 #define HAL_SAI_MODULE_ENABLED
00085 #define HAL_SD_MODULE_ENABLED
00086 #define HAL_SMARTCARD_MODULE_ENABLED
00087 #define HAL_SMBUS_MODULE_ENABLED
00088 #define HAL_SPI_MODULE_ENABLED
00089 #define HAL_SWPMI_MODULE_ENABLED
00090 #define HAL_TIM_MODULE_ENABLED
00091 #define HAL_TSC_MODULE_ENABLED
00092 #define HAL_UART_MODULE_ENABLED
00093 #define HAL_USART_MODULE_ENABLED
00094 #define HAL_WWDG_MODULE_ENABLED
00095
00096
00097 /* ########################## Oscillator Values adaptation ####################*/
00098 /**
00099   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
00100   *        This value is used by the RCC HAL module to compute the system frequency
00101   *        (when HSE is used as system clock source, directly or through the PLL).
00102   */
00103 #if !defined  (HSE_VALUE)
00104   #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
00105 #endif /* HSE_VALUE */
00106
00107 #if !defined  (HSE_STARTUP_TIMEOUT)
00108   #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
00109 #endif /* HSE_STARTUP_TIMEOUT */
00110
00111 /**
00112   * @brief Internal Multiple Speed oscillator (MSI) default value.
00113   *        This value is the default MSI range value after Reset.
00114   */
00115 #if !defined  (MSI_VALUE)
00116   #define MSI_VALUE    ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/
00117 #endif /* MSI_VALUE */
00118
00119 /**
00120   * @brief Internal High Speed oscillator (HSI) value.
00121   *        This value is used by the RCC HAL module to compute the system frequency
00122   *        (when HSI is used as system clock source, directly or through the PLL).
00123   */
00124 #if !defined  (HSI_VALUE)
00125   #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
00126 #endif /* HSI_VALUE */
00127
00128 /**
00129   * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
00130   *        This internal oscillator is mainly dedicated to provide a high precision clock to
00131   *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
00132   *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
00133   *        which is subject to manufacturing process variations.
00134   */
00135 #if !defined  (HSI48_VALUE)
00136  #define HSI48_VALUE   ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
00137                                               The real value my vary depending on manufacturing process variations.*/
00138 #endif /* HSI48_VALUE */
00139
00140 /**
00141   * @brief Internal Low Speed oscillator (LSI) value.
00142   */
00143 #if !defined  (LSI_VALUE)
00144  #define LSI_VALUE  ((uint32_t)32000U)      /*!< LSI Typical Value in Hz*/
00145 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
00146                                              The real value may vary depending on the variations
00147                                              in voltage and temperature.*/
00148 /**
00149   * @brief External Low Speed oscillator (LSE) value.
00150   *        This value is used by the UART, RTC HAL module to compute the system frequency
00151   */
00152 #if !defined  (LSE_VALUE)
00153   #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
00154 #endif /* LSE_VALUE */
00155
00156 #if !defined  (LSE_STARTUP_TIMEOUT)
00157   #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)  /*!< Time out for LSE start up, in ms */
00158 #endif /* HSE_STARTUP_TIMEOUT */
00159
00160 /**
00161   * @brief External clock source for SAI1 peripheral
00162   *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
00163   *        frequency.
00164   */
00165 #if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
00166   #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/
00167 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
00168
00169 /**
00170   * @brief External clock source for SAI2 peripheral
00171   *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
00172   *        frequency.
00173   */
00174 #if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
00175   #define EXTERNAL_SAI2_CLOCK_VALUE    ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/
00176 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
00177
00178 /* Tip: To avoid modifying this file each time you need to use different HSE,
00179    ===  you can define the HSE value in your toolchain compiler preprocessor. */
00180
00181 /* ########################### System Configuration ######################### */
00182 /**
00183   * @brief This is the HAL system configuration section
00184   */
00185 #define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
00186 #define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
00187 #define  USE_RTOS                     0
00188 #define  PREFETCH_ENABLE              0
00189 #define  INSTRUCTION_CACHE_ENABLE     1
00190 #define  DATA_CACHE_ENABLE            1
00191
00192 /* ########################## Assert Selection ############################## */
00193 /**
00194   * @brief Uncomment the line below to expanse the "assert_param" macro in the
00195   *        HAL drivers code
00196   */
00197 /* #define USE_FULL_ASSERT    1 */
00198
00199 /* Includes ------------------------------------------------------------------*/
00200 /**
00201   * @brief Include module's header file
00202   */
00203
00204 #ifdef HAL_RCC_MODULE_ENABLED
00205   #include "stm32l4xx_hal_rcc.h"
00206 #endif /* HAL_RCC_MODULE_ENABLED */
00207
00208 #ifdef HAL_GPIO_MODULE_ENABLED
00209   #include "stm32l4xx_hal_gpio.h"
00210 #endif /* HAL_GPIO_MODULE_ENABLED */
00211
00212 #ifdef HAL_DMA_MODULE_ENABLED
00213   #include "stm32l4xx_hal_dma.h"
00214 #endif /* HAL_DMA_MODULE_ENABLED */
00215
00216 #ifdef HAL_DFSDM_MODULE_ENABLED
00217   #include "stm32l4xx_hal_dfsdm.h"
00218 #endif /* HAL_DFSDM_MODULE_ENABLED */
00219
00220 #ifdef HAL_CORTEX_MODULE_ENABLED
00221   #include "stm32l4xx_hal_cortex.h"
00222 #endif /* HAL_CORTEX_MODULE_ENABLED */
00223
00224 #ifdef HAL_ADC_MODULE_ENABLED
00225   #include "stm32l4xx_hal_adc.h"
00226 #endif /* HAL_ADC_MODULE_ENABLED */
00227
00228 #ifdef HAL_CAN_MODULE_ENABLED
00229   #include "stm32l4xx_hal_can.h"
00230 #endif /* HAL_CAN_MODULE_ENABLED */
00231
00232 #ifdef HAL_COMP_MODULE_ENABLED
00233   #include "stm32l4xx_hal_comp.h"
00234 #endif /* HAL_COMP_MODULE_ENABLED */
00235
00236 #ifdef HAL_CRC_MODULE_ENABLED
00237   #include "stm32l4xx_hal_crc.h"
00238 #endif /* HAL_CRC_MODULE_ENABLED */
00239
00240 #ifdef HAL_CRYP_MODULE_ENABLED
00241   #include "stm32l4xx_hal_cryp.h"
00242 #endif /* HAL_CRYP_MODULE_ENABLED */
00243
00244 #ifdef HAL_DAC_MODULE_ENABLED
00245   #include "stm32l4xx_hal_dac.h"
00246 #endif /* HAL_DAC_MODULE_ENABLED */
00247
00248 #ifdef HAL_FIREWALL_MODULE_ENABLED
00249   #include "stm32l4xx_hal_firewall.h"
00250 #endif /* HAL_FIREWALL_MODULE_ENABLED */
00251
00252 #ifdef HAL_FLASH_MODULE_ENABLED
00253   #include "stm32l4xx_hal_flash.h"
00254 #endif /* HAL_FLASH_MODULE_ENABLED */
00255
00256 #ifdef HAL_SRAM_MODULE_ENABLED
00257   #include "stm32l4xx_hal_sram.h"
00258 #endif /* HAL_SRAM_MODULE_ENABLED */
00259
00260 #ifdef HAL_NOR_MODULE_ENABLED
00261   #include "stm32l4xx_hal_nor.h"
00262 #endif /* HAL_NOR_MODULE_ENABLED */
00263
00264 #ifdef HAL_NAND_MODULE_ENABLED
00265   #include "stm32l4xx_hal_nand.h"
00266 #endif /* HAL_NAND_MODULE_ENABLED */
00267
00268 #ifdef HAL_I2C_MODULE_ENABLED
00269  #include "stm32l4xx_hal_i2c.h"
00270 #endif /* HAL_I2C_MODULE_ENABLED */
00271
00272 #ifdef HAL_IWDG_MODULE_ENABLED
00273  #include "stm32l4xx_hal_iwdg.h"
00274 #endif /* HAL_IWDG_MODULE_ENABLED */
00275
00276 #ifdef HAL_LCD_MODULE_ENABLED
00277  #include "stm32l4xx_hal_lcd.h"
00278 #endif /* HAL_LCD_MODULE_ENABLED */
00279
00280 #ifdef HAL_LPTIM_MODULE_ENABLED
00281 #include "stm32l4xx_hal_lptim.h"
00282 #endif /* HAL_LPTIM_MODULE_ENABLED */
00283
00284 #ifdef HAL_OPAMP_MODULE_ENABLED
00285 #include "stm32l4xx_hal_opamp.h"
00286 #endif /* HAL_OPAMP_MODULE_ENABLED */
00287
00288 #ifdef HAL_PWR_MODULE_ENABLED
00289  #include "stm32l4xx_hal_pwr.h"
00290 #endif /* HAL_PWR_MODULE_ENABLED */
00291
00292 #ifdef HAL_QSPI_MODULE_ENABLED
00293  #include "stm32l4xx_hal_qspi.h"
00294 #endif /* HAL_QSPI_MODULE_ENABLED */
00295
00296 #ifdef HAL_RNG_MODULE_ENABLED
00297  #include "stm32l4xx_hal_rng.h"
00298 #endif /* HAL_RNG_MODULE_ENABLED */
00299
00300 #ifdef HAL_RTC_MODULE_ENABLED
00301  #include "stm32l4xx_hal_rtc.h"
00302 #endif /* HAL_RTC_MODULE_ENABLED */
00303
00304 #ifdef HAL_SAI_MODULE_ENABLED
00305  #include "stm32l4xx_hal_sai.h"
00306 #endif /* HAL_SAI_MODULE_ENABLED */
00307
00308 #ifdef HAL_SD_MODULE_ENABLED
00309  #include "stm32l4xx_hal_sd.h"
00310 #endif /* HAL_SD_MODULE_ENABLED */
00311
00312 #ifdef HAL_SMBUS_MODULE_ENABLED
00313  #include "stm32l4xx_hal_smbus.h"
00314 #endif /* HAL_SMBUS_MODULE_ENABLED */
00315
00316 #ifdef HAL_SPI_MODULE_ENABLED
00317  #include "stm32l4xx_hal_spi.h"
00318 #endif /* HAL_SPI_MODULE_ENABLED */
00319
00320 #ifdef HAL_SWPMI_MODULE_ENABLED
00321  #include "stm32l4xx_hal_swpmi.h"
00322 #endif /* HAL_SWPMI_MODULE_ENABLED */
00323
00324 #ifdef HAL_TIM_MODULE_ENABLED
00325  #include "stm32l4xx_hal_tim.h"
00326 #endif /* HAL_TIM_MODULE_ENABLED */
00327
00328 #ifdef HAL_TSC_MODULE_ENABLED
00329  #include "stm32l4xx_hal_tsc.h"
00330 #endif /* HAL_TSC_MODULE_ENABLED */
00331
00332 #ifdef HAL_UART_MODULE_ENABLED
00333  #include "stm32l4xx_hal_uart.h"
00334 #endif /* HAL_UART_MODULE_ENABLED */
00335
00336 #ifdef HAL_USART_MODULE_ENABLED
00337  #include "stm32l4xx_hal_usart.h"
00338 #endif /* HAL_USART_MODULE_ENABLED */
00339
00340 #ifdef HAL_IRDA_MODULE_ENABLED
00341  #include "stm32l4xx_hal_irda.h"
00342 #endif /* HAL_IRDA_MODULE_ENABLED */
00343
00344 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00345  #include "stm32l4xx_hal_smartcard.h"
00346 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00347
00348 #ifdef HAL_WWDG_MODULE_ENABLED
00349  #include "stm32l4xx_hal_wwdg.h"
00350 #endif /* HAL_WWDG_MODULE_ENABLED */
00351
00352 #ifdef HAL_PCD_MODULE_ENABLED
00353  #include "stm32l4xx_hal_pcd.h"
00354 #endif /* HAL_PCD_MODULE_ENABLED */
00355
00356 #ifdef HAL_HCD_MODULE_ENABLED
00357  #include "stm32l4xx_hal_hcd.h"
00358 #endif /* HAL_HCD_MODULE_ENABLED */
00359
00360 /* Exported macro ------------------------------------------------------------*/
00361 #ifdef  USE_FULL_ASSERT
00362 /**
00363   * @brief  The assert_param macro is used for function's parameters check.
00364   * @param  expr: If expr is false, it calls assert_failed function
00365   *         which reports the name of the source file and the source
00366   *         line number of the call that failed.
00367   *         If expr is true, it returns no value.
00368   * @retval None
00369   */
00370   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
00371 /* Exported functions ------------------------------------------------------- */
00372   void assert_failed(uint8_t* file, uint32_t line);
00373 #else
00374   #define assert_param(expr) ((void)0U)
00375 #endif /* USE_FULL_ASSERT */
00376
00377 #ifdef __cplusplus
00378 }
00379 #endif
00380
00381 #endif /* __STM32L4xx_HAL_CONF_H */
00382
00383
00384 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cortex.c Source File

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stm32l4xx_hal_cortex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_cortex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   CORTEX HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the CORTEX:
00010   *           + Initialization and Configuration functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017
00018     [..]
00019     *** How to configure Interrupts using CORTEX HAL driver ***
00020     ===========================================================
00021     [..]
00022     This section provides functions allowing to configure the NVIC interrupts (IRQ).
00023     The Cortex-M4 exceptions are managed by CMSIS functions.
00024
00025     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
00026     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
00027     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
00028
00029      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
00030          The pending IRQ priority will be managed only by the sub priority.
00031
00032      -@- IRQ priority order (sorted by highest to lowest priority):
00033         (+@) Lowest pre-emption priority
00034         (+@) Lowest sub priority
00035         (+@) Lowest hardware priority (IRQ number)
00036
00037     [..]
00038     *** How to configure SysTick using CORTEX HAL driver ***
00039     ========================================================
00040     [..]
00041     Setup SysTick Timer for time base.
00042
00043    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
00044        is a CMSIS function that:
00045         (++) Configures the SysTick Reload register with value passed as function parameter.
00046         (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
00047         (++) Resets the SysTick Counter register.
00048         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
00049         (++) Enables the SysTick Interrupt.
00050         (++) Starts the SysTick Counter.
00051
00052    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
00053        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
00054        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
00055        inside the stm32l4xx_hal_cortex.h file.
00056
00057    (+) You can change the SysTick IRQ priority by calling the
00058        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
00059        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
00060
00061    (+) To adjust the SysTick time base, use the following formula:
00062
00063        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00064        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
00065        (++) Reload Value should not exceed 0xFFFFFF
00066
00067   @endverbatim
00068   ******************************************************************************
00069
00070   The table below gives the allowed values of the pre-emption priority and subpriority according
00071   to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
00072
00073     ==========================================================================================================================
00074       NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
00075     ==========================================================================================================================
00076      NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bit for pre-emption priority
00077                            |                                   |                             | 4 bits for subpriority
00078     --------------------------------------------------------------------------------------------------------------------------
00079      NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bit for pre-emption priority
00080                            |                                   |                             | 3 bits for subpriority
00081     --------------------------------------------------------------------------------------------------------------------------
00082      NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
00083                            |                                   |                             | 2 bits for subpriority
00084     --------------------------------------------------------------------------------------------------------------------------
00085      NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
00086                            |                                   |                             | 1 bit for subpriority
00087     --------------------------------------------------------------------------------------------------------------------------
00088      NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
00089                            |                                   |                             | 0 bit for subpriority
00090     ==========================================================================================================================
00091
00092   ******************************************************************************
00093   * @attention
00094   *
00095   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00096   *
00097   * Redistribution and use in source and binary forms, with or without modification,
00098   * are permitted provided that the following conditions are met:
00099   *   1. Redistributions of source code must retain the above copyright notice,
00100   *      this list of conditions and the following disclaimer.
00101   *   2. Redistributions in binary form must reproduce the above copyright notice,
00102   *      this list of conditions and the following disclaimer in the documentation
00103   *      and/or other materials provided with the distribution.
00104   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00105   *      may be used to endorse or promote products derived from this software
00106   *      without specific prior written permission.
00107   *
00108   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00109   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00110   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00111   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00112   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00113   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00114   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00115   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00116   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00117   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00118   *
00119   ******************************************************************************
00120   */
00121
00122 /* Includes ------------------------------------------------------------------*/
00123 #include "stm32l4xx_hal.h"
00124
00125 /** @addtogroup STM32L4xx_HAL_Driver
00126   * @{
00127   */
00128
00129 /** @addtogroup CORTEX
00130   * @{
00131   */
00132
00133 #ifdef HAL_CORTEX_MODULE_ENABLED
00134
00135 /* Private types -------------------------------------------------------------*/
00136 /* Private variables ---------------------------------------------------------*/
00137 /* Private constants ---------------------------------------------------------*/
00138 /* Private macros ------------------------------------------------------------*/
00139 /* Private functions ---------------------------------------------------------*/
00140 /* Exported functions --------------------------------------------------------*/
00141
00142 /** @addtogroup CORTEX_Exported_Functions
00143   * @{
00144   */
00145
00146
00147 /** @addtogroup CORTEX_Exported_Functions_Group1
00148  *  @brief    Initialization and Configuration functions
00149  *
00150 @verbatim
00151   ==============================================================================
00152               ##### Initialization and Configuration functions #####
00153   ==============================================================================
00154     [..]
00155       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
00156       SysTick functionalities
00157
00158 @endverbatim
00159   * @{
00160   */
00161
00162
00163 /**
00164   * @brief  Set the priority grouping field (pre-emption priority and subpriority)
00165   *         using the required unlock sequence.
00166   * @param  PriorityGroup: The priority grouping bits length.
00167   *         This parameter can be one of the following values:
00168   *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,
00169   *                                    4 bits for subpriority
00170   *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,
00171   *                                    3 bits for subpriority
00172   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
00173   *                                    2 bits for subpriority
00174   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
00175   *                                    1 bit  for subpriority
00176   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
00177   *                                    0 bit  for subpriority
00178   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
00179   *         The pending IRQ priority will be managed only by the subpriority.
00180   * @retval None
00181   */
00182 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
00183 {
00184   /* Check the parameters */
00185   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00186
00187   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
00188   NVIC_SetPriorityGrouping(PriorityGroup);
00189 }
00190
00191 /**
00192   * @brief  Set the priority of an interrupt.
00193   * @param  IRQn: External interrupt number.
00194   *         This parameter can be an enumerator of IRQn_Type enumeration
00195   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
00196   * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
00197   *         This parameter can be a value between 0 and 15
00198   *         A lower priority value indicates a higher priority
00199   * @param  SubPriority: the subpriority level for the IRQ channel.
00200   *         This parameter can be a value between 0 and 15
00201   *         A lower priority value indicates a higher priority.
00202   * @retval None
00203   */
00204 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
00205 {
00206   uint32_t prioritygroup = 0x00;
00207
00208   /* Check the parameters */
00209   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
00210   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
00211
00212   prioritygroup = NVIC_GetPriorityGrouping();
00213
00214   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
00215 }
00216
00217 /**
00218   * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
00219   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
00220   *         function should be called before.
00221   * @param  IRQn External interrupt number.
00222   *         This parameter can be an enumerator of IRQn_Type enumeration
00223   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
00224   * @retval None
00225   */
00226 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
00227 {
00228   /* Check the parameters */
00229   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00230
00231   /* Enable interrupt */
00232   NVIC_EnableIRQ(IRQn);
00233 }
00234
00235 /**
00236   * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
00237   * @param  IRQn External interrupt number.
00238   *         This parameter can be an enumerator of IRQn_Type enumeration
00239   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
00240   * @retval None
00241   */
00242 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
00243 {
00244   /* Check the parameters */
00245   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00246
00247   /* Disable interrupt */
00248   NVIC_DisableIRQ(IRQn);
00249 }
00250
00251 /**
00252   * @brief  Initiate a system reset request to reset the MCU.
00253   * @retval None
00254   */
00255 void HAL_NVIC_SystemReset(void)
00256 {
00257   /* System Reset */
00258   NVIC_SystemReset();
00259 }
00260
00261 /**
00262   * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
00263   *         Counter is in free running mode to generate periodic interrupts.
00264   * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
00265   * @retval status:  - 0  Function succeeded.
00266   *                  - 1  Function failed.
00267   */
00268 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
00269 {
00270    return SysTick_Config(TicksNumb);
00271 }
00272 /**
00273   * @}
00274   */
00275
00276 /** @addtogroup CORTEX_Exported_Functions_Group2
00277  *  @brief   Cortex control functions
00278  *
00279 @verbatim
00280   ==============================================================================
00281                       ##### Peripheral Control functions #####
00282   ==============================================================================
00283     [..]
00284       This subsection provides a set of functions allowing to control the CORTEX
00285       (NVIC, SYSTICK, MPU) functionalities.
00286
00287
00288 @endverbatim
00289   * @{
00290   */
00291
00292 /**
00293   * @brief  Get the priority grouping field from the NVIC Interrupt Controller.
00294   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
00295   */
00296 uint32_t HAL_NVIC_GetPriorityGrouping(void)
00297 {
00298   /* Get the PRIGROUP[10:8] field value */
00299   return NVIC_GetPriorityGrouping();
00300 }
00301
00302 /**
00303   * @brief  Get the priority of an interrupt.
00304   * @param  IRQn: External interrupt number.
00305   *         This parameter can be an enumerator of IRQn_Type enumeration
00306   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
00307   * @param   PriorityGroup: the priority grouping bits length.
00308   *         This parameter can be one of the following values:
00309   *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
00310   *                                      4 bits for subpriority
00311   *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
00312   *                                      3 bits for subpriority
00313   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
00314   *                                      2 bits for subpriority
00315   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
00316   *                                      1 bit for subpriority
00317   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
00318   *                                      0 bit for subpriority
00319   * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
00320   * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
00321   * @retval None
00322   */
00323 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
00324 {
00325   /* Check the parameters */
00326   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00327  /* Get priority for Cortex-M system or device specific interrupts */
00328   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
00329 }
00330
00331 /**
00332   * @brief  Set Pending bit of an external interrupt.
00333   * @param  IRQn External interrupt number
00334   *         This parameter can be an enumerator of IRQn_Type enumeration
00335   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
00336   * @retval None
00337   */
00338 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
00339 {
00340   /* Set interrupt pending */
00341   NVIC_SetPendingIRQ(IRQn);
00342 }
00343
00344 /**
00345   * @brief  Get Pending Interrupt (read the pending register in the NVIC
00346   *         and return the pending bit for the specified interrupt).
00347   * @param  IRQn External interrupt number.
00348   *          This parameter can be an enumerator of IRQn_Type enumeration
00349   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
00350   * @retval status: - 0  Interrupt status is not pending.
00351   *                 - 1  Interrupt status is pending.
00352   */
00353 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
00354 {
00355   /* Return 1 if pending else 0 */
00356   return NVIC_GetPendingIRQ(IRQn);
00357 }
00358
00359 /**
00360   * @brief  Clear the pending bit of an external interrupt.
00361   * @param  IRQn External interrupt number.
00362   *         This parameter can be an enumerator of IRQn_Type enumeration
00363   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
00364   * @retval None
00365   */
00366 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00367 {
00368   /* Clear pending interrupt */
00369   NVIC_ClearPendingIRQ(IRQn);
00370 }
00371
00372 /**
00373   * @brief Get active interrupt (read the active register in NVIC and return the active bit).
00374   * @param IRQn External interrupt number
00375   *         This parameter can be an enumerator of IRQn_Type enumeration
00376   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
00377   * @retval status: - 0  Interrupt status is not pending.
00378   *                 - 1  Interrupt status is pending.
00379   */
00380 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
00381 {
00382   /* Return 1 if active else 0 */
00383   return NVIC_GetActive(IRQn);
00384 }
00385
00386 /**
00387   * @brief  Configure the SysTick clock source.
00388   * @param  CLKSource: specifies the SysTick clock source.
00389   *          This parameter can be one of the following values:
00390   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
00391   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
00392   * @retval None
00393   */
00394 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
00395 {
00396   /* Check the parameters */
00397   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
00398   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
00399   {
00400     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
00401   }
00402   else
00403   {
00404     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
00405   }
00406 }
00407
00408 /**
00409   * @brief  Handle SYSTICK interrupt request.
00410   * @retval None
00411   */
00412 void HAL_SYSTICK_IRQHandler(void)
00413 {
00414   HAL_SYSTICK_Callback();
00415 }
00416
00417 /**
00418   * @brief  SYSTICK callback.
00419   * @retval None
00420   */
00421 __weak void HAL_SYSTICK_Callback(void)
00422 {
00423   /* NOTE : This function should not be modified, when the callback is needed,
00424             the HAL_SYSTICK_Callback could be implemented in the user file
00425    */
00426 }
00427
00428 #if (__MPU_PRESENT == 1)
00429 /**
00430   * @brief  Initialize and configure the Region and the memory to be protected.
00431   * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
00432   *                the initialization and configuration information.
00433   * @retval None
00434   */
00435 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
00436 {
00437   /* Check the parameters */
00438   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
00439   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
00440
00441   /* Set the Region number */
00442   MPU->RNR = MPU_Init->Number;
00443
00444   if ((MPU_Init->Enable) != RESET)
00445   {
00446     /* Check the parameters */
00447     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
00448     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
00449     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
00450     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
00451     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
00452     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
00453     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
00454     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
00455
00456     MPU->RBAR = MPU_Init->BaseAddress;
00457     MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |
00458                 ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |
00459                 ((uint32_t)MPU_Init->TypeExtField       << MPU_RASR_TEX_Pos)  |
00460                 ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |
00461                 ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |
00462                 ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |
00463                 ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |
00464                 ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |
00465                 ((uint32_t)MPU_Init->Enable             << MPU_RASR_ENABLE_Pos);
00466   }
00467   else
00468   {
00469     MPU->RBAR = 0x00;
00470     MPU->RASR = 0x00;
00471   }
00472 }
00473 #endif /* __MPU_PRESENT */
00474
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 #endif /* HAL_CORTEX_MODULE_ENABLED */
00484 /**
00485   * @}
00486   */
00487
00488 /**
00489   * @}
00490   */
00491
00492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cortex.h Source File

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stm32l4xx_hal_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of CORTEX HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_CORTEX_H
00040 #define __STM32L4xx_HAL_CORTEX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup CORTEX CORTEX
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
00059   * @{
00060   */
00061
00062 #if (__MPU_PRESENT == 1)
00063 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint8_t                Enable;                /*!< Specifies the status of the region.
00069                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
00070   uint8_t                Number;                /*!< Specifies the number of the region to protect.
00071                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
00072   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
00073   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
00074                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
00075   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
00076                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
00077   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
00078                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
00079   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
00080                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
00081   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
00082                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
00083   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
00084                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
00085   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
00086                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
00087   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
00088                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
00089 }MPU_Region_InitTypeDef;
00090 /**
00091   * @}
00092   */
00093 #endif /* __MPU_PRESENT */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100
00101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00102   * @{
00103   */
00104
00105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
00106   * @{
00107   */
00108 #define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
00109                                                                  4 bits for subpriority */
00110 #define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
00111                                                                  3 bits for subpriority */
00112 #define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
00113                                                                  2 bits for subpriority */
00114 #define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
00115                                                                  1 bit  for subpriority */
00116 #define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
00117                                                                  0 bit  for subpriority */
00118 /**
00119   * @}
00120   */
00121
00122 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
00123   * @{
00124   */
00125 #define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
00126 #define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
00127 /**
00128   * @}
00129   */
00130
00131 #if (__MPU_PRESENT == 1)
00132 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
00133   * @{
00134   */
00135 #define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
00136 #define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
00137 #define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
00138 #define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
00139 /**
00140   * @}
00141   */
00142
00143 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00144   * @{
00145   */
00146 #define  MPU_REGION_ENABLE           ((uint8_t)0x01)
00147 #define  MPU_REGION_DISABLE          ((uint8_t)0x00)
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00153   * @{
00154   */
00155 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
00156 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00162   * @{
00163   */
00164 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
00165 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00171   * @{
00172   */
00173 #define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01)
00174 #define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00)
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00180   * @{
00181   */
00182 #define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01)
00183 #define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00)
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
00189   * @{
00190   */
00191 #define  MPU_TEX_LEVEL0              ((uint8_t)0x00)
00192 #define  MPU_TEX_LEVEL1              ((uint8_t)0x01)
00193 #define  MPU_TEX_LEVEL2              ((uint8_t)0x02)
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00199   * @{
00200   */
00201 #define   MPU_REGION_SIZE_32B        ((uint8_t)0x04)
00202 #define   MPU_REGION_SIZE_64B        ((uint8_t)0x05)
00203 #define   MPU_REGION_SIZE_128B       ((uint8_t)0x06)
00204 #define   MPU_REGION_SIZE_256B       ((uint8_t)0x07)
00205 #define   MPU_REGION_SIZE_512B       ((uint8_t)0x08)
00206 #define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09)
00207 #define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0A)
00208 #define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0B)
00209 #define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0C)
00210 #define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0D)
00211 #define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0E)
00212 #define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0F)
00213 #define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10)
00214 #define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11)
00215 #define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12)
00216 #define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13)
00217 #define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14)
00218 #define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15)
00219 #define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16)
00220 #define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17)
00221 #define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18)
00222 #define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19)
00223 #define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1A)
00224 #define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1B)
00225 #define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1C)
00226 #define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1D)
00227 #define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1E)
00228 #define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1F)
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
00234   * @{
00235   */
00236 #define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)
00237 #define  MPU_REGION_PRIV_RW          ((uint8_t)0x01)
00238 #define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02)
00239 #define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03)
00240 #define  MPU_REGION_PRIV_RO          ((uint8_t)0x05)
00241 #define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06)
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00247   * @{
00248   */
00249 #define  MPU_REGION_NUMBER0          ((uint8_t)0x00)
00250 #define  MPU_REGION_NUMBER1          ((uint8_t)0x01)
00251 #define  MPU_REGION_NUMBER2          ((uint8_t)0x02)
00252 #define  MPU_REGION_NUMBER3          ((uint8_t)0x03)
00253 #define  MPU_REGION_NUMBER4          ((uint8_t)0x04)
00254 #define  MPU_REGION_NUMBER5          ((uint8_t)0x05)
00255 #define  MPU_REGION_NUMBER6          ((uint8_t)0x06)
00256 #define  MPU_REGION_NUMBER7          ((uint8_t)0x07)
00257 /**
00258   * @}
00259   */
00260 #endif /* __MPU_PRESENT */
00261
00262 /**
00263   * @}
00264   */
00265
00266 /* Exported macros -----------------------------------------------------------*/
00267 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
00268   * @{
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /* Exported functions --------------------------------------------------------*/
00276 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
00277   * @{
00278   */
00279
00280 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
00281   * @brief    Initialization and Configuration functions
00282   * @{
00283   */
00284 /* Initialization and Configuration functions *****************************/
00285 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
00286 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
00287 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00288 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00289 void HAL_NVIC_SystemReset(void);
00290 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00291
00292 #if (__MPU_PRESENT == 1)
00293 /**
00294   * @brief  Disable the MPU.
00295   * @retval None
00296   */
00297 __STATIC_INLINE void HAL_MPU_Disable(void)
00298 {
00299   /* Disable fault exceptions */
00300   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00301
00302   /* Disable the MPU */
00303   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
00304 }
00305
00306 /**
00307   * @brief  Enable the MPU.
00308   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
00309   *          NMI, FAULTMASK and privileged accessto the default memory
00310   *          This parameter can be one of the following values:
00311   *            @arg MPU_HFNMI_PRIVDEF_NONE
00312   *            @arg MPU_HARDFAULT_NMI
00313   *            @arg MPU_PRIVILEGED_DEFAULT
00314   *            @arg MPU_HFNMI_PRIVDEF
00315   * @retval None
00316   */
00317 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
00318 {
00319   /* Enable the MPU */
00320   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
00321
00322   /* Enable fault exceptions */
00323   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00324 }
00325 #endif /* __MPU_PRESENT */
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
00331   * @brief   Cortex control functions
00332   * @{
00333   */
00334 /* Peripheral Control functions ***********************************************/
00335 uint32_t HAL_NVIC_GetPriorityGrouping(void);
00336 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
00337 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00338 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00339 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00340 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
00341 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00342 void HAL_SYSTICK_IRQHandler(void);
00343 void HAL_SYSTICK_Callback(void);
00344
00345 #if (__MPU_PRESENT == 1)
00346 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00347 #endif /* __MPU_PRESENT */
00348 /**
00349   * @}
00350   */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /* Private types -------------------------------------------------------------*/
00357 /* Private variables ---------------------------------------------------------*/
00358 /* Private constants ---------------------------------------------------------*/
00359 /* Private macros ------------------------------------------------------------*/
00360 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00361   * @{
00362   */
00363 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
00364                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
00365                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
00366                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
00367                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
00368
00369 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
00370
00371 #define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10)
00372
00373 #define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)
00374
00375 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00376                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00377
00378 #if (__MPU_PRESENT == 1)
00379 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
00380                                      ((STATE) == MPU_REGION_DISABLE))
00381
00382 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00383                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00384
00385 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
00386                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00387
00388 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
00389                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00390
00391 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00392                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00393
00394 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
00395                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
00396                                 ((TYPE) == MPU_TEX_LEVEL2))
00397
00398 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00399                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
00400                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00401                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00402                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
00403                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
00404
00405 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
00406                                          ((NUMBER) == MPU_REGION_NUMBER1) || \
00407                                          ((NUMBER) == MPU_REGION_NUMBER2) || \
00408                                          ((NUMBER) == MPU_REGION_NUMBER3) || \
00409                                          ((NUMBER) == MPU_REGION_NUMBER4) || \
00410                                          ((NUMBER) == MPU_REGION_NUMBER5) || \
00411                                          ((NUMBER) == MPU_REGION_NUMBER6) || \
00412                                          ((NUMBER) == MPU_REGION_NUMBER7))
00413
00414 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
00415                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
00416                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
00417                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
00418                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
00419                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00420                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00421                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00422                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00423                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00424                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00425                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00426                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
00427                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
00428                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
00429                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00430                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00431                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00432                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00433                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00434                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00435                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00436                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
00437                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
00438                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
00439                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00440                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00441                                      ((SIZE) == MPU_REGION_SIZE_4GB))
00442
00443 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
00444 #endif /* __MPU_PRESENT */
00445
00446 /**
00447   * @}
00448   */
00449
00450 /* Private functions ---------------------------------------------------------*/
00451
00452 /**
00453   * @}
00454   */
00455
00456 /**
00457   * @}
00458   */
00459
00460 #ifdef __cplusplus
00461 }
00462 #endif
00463
00464 #endif /* __STM32L4xx_HAL_CORTEX_H */
00465
00466
00467 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_crc.c Source File

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stm32l4xx_hal_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_crc.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   CRC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the CRC peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015  ===============================================================================
00016                      ##### How to use this driver #####
00017  ===============================================================================
00018     [..]
00019          (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
00020          (+) Initialize CRC calculator
00021              (++) specify generating polynomial (IP default or non-default one)
00022              (++) specify initialization value (IP default or non-default one)
00023              (++) specify input data format
00024              (++) specify input or output data inversion mode if any
00025          (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
00026              input data buffer starting with the previously computed CRC as
00027              initialization value
00028          (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
00029              input data buffer starting with the defined initialization value
00030              (default or non-default) to initiate CRC calculation
00031
00032   @endverbatim
00033   ******************************************************************************
00034   * @attention
00035   *
00036   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00037   *
00038   * Redistribution and use in source and binary forms, with or without modification,
00039   * are permitted provided that the following conditions are met:
00040   *   1. Redistributions of source code must retain the above copyright notice,
00041   *      this list of conditions and the following disclaimer.
00042   *   2. Redistributions in binary form must reproduce the above copyright notice,
00043   *      this list of conditions and the following disclaimer in the documentation
00044   *      and/or other materials provided with the distribution.
00045   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00046   *      may be used to endorse or promote products derived from this software
00047   *      without specific prior written permission.
00048   *
00049   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00050   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00051   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00052   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00053   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00054   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00055   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00056   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00057   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00058   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00059   *
00060   ******************************************************************************
00061   */
00062
00063 /* Includes ------------------------------------------------------------------*/
00064 #include "stm32l4xx_hal.h"
00065
00066 /** @addtogroup STM32L4xx_HAL_Driver
00067   * @{
00068   */
00069
00070 /** @defgroup CRC CRC
00071   * @brief CRC HAL module driver.
00072   * @{
00073   */
00074
00075 #ifdef HAL_CRC_MODULE_ENABLED
00076
00077 /* Private typedef -----------------------------------------------------------*/
00078 /* Private define ------------------------------------------------------------*/
00079 /* Private macro -------------------------------------------------------------*/
00080 /* Private variables ---------------------------------------------------------*/
00081 /* Private function prototypes -----------------------------------------------*/
00082 /** @defgroup CRC_Private_Functions CRC Private Functions
00083  * @{
00084  */
00085 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
00086 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
00087 /**
00088   * @}
00089   */
00090
00091 /* Exported functions --------------------------------------------------------*/
00092
00093 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00094   * @{
00095   */
00096
00097 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00098  *  @brief    Initialization and Configuration functions.
00099  *
00100 @verbatim
00101  ===============================================================================
00102             ##### Initialization and de-initialization functions #####
00103  ===============================================================================
00104     [..]  This section provides functions allowing to:
00105       (+) Initialize the CRC according to the specified parameters
00106           in the CRC_InitTypeDef and create the associated handle
00107       (+) DeInitialize the CRC peripheral
00108       (+) Initialize the CRC MSP (MCU Specific Package)
00109       (+) DeInitialize the CRC MSP
00110
00111 @endverbatim
00112   * @{
00113   */
00114
00115 /**
00116   * @brief  Initialize the CRC according to the specified
00117   *         parameters in the CRC_InitTypeDef and create the associated handle.
00118   * @param  hcrc: CRC handle
00119   * @retval HAL status
00120   */
00121 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
00122 {
00123   /* Check the CRC handle allocation */
00124   if(hcrc == NULL)
00125   {
00126     return HAL_ERROR;
00127   }
00128
00129   /* Check the parameters */
00130   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00131
00132   if(hcrc->State == HAL_CRC_STATE_RESET)
00133   {
00134     /* Allocate lock resource and initialize it */
00135     hcrc->Lock = HAL_UNLOCKED;
00136
00137     /* Init the low level hardware */
00138     HAL_CRC_MspInit(hcrc);
00139   }
00140
00141   hcrc->State = HAL_CRC_STATE_BUSY;
00142
00143   /* check whether or not non-default generating polynomial has been
00144    * picked up by user */
00145   assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
00146   if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
00147   {
00148     /* initialize IP with default generating polynomial */
00149     WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
00150     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
00151   }
00152   else
00153   {
00154     /* initialize CRC IP with generating polynomial defined by user */
00155     if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
00156     {
00157       return HAL_ERROR;
00158     }
00159   }
00160
00161   /* check whether or not non-default CRC initial value has been
00162    * picked up by user */
00163   assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
00164   if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
00165   {
00166     WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
00167   }
00168   else
00169   {
00170     WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
00171   }
00172
00173
00174   /* set input data inversion mode */
00175   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
00176   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
00177
00178   /* set output data inversion mode */
00179   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
00180   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
00181
00182   /* makes sure the input data format (bytes, halfwords or words stream)
00183    * is properly specified by user */
00184   assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
00185
00186   /* Change CRC peripheral state */
00187   hcrc->State = HAL_CRC_STATE_READY;
00188
00189   /* Return function status */
00190   return HAL_OK;
00191 }
00192
00193 /**
00194   * @brief  DeInitialize the CRC peripheral.
00195   * @param  hcrc: CRC handle
00196   * @retval HAL status
00197   */
00198 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
00199 {
00200   /* Check the CRC handle allocation */
00201   if(hcrc == NULL)
00202   {
00203     return HAL_ERROR;
00204   }
00205
00206   /* Check the parameters */
00207   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00208
00209   /* Check the CRC peripheral state */
00210   if(hcrc->State == HAL_CRC_STATE_BUSY)
00211   {
00212     return HAL_BUSY;
00213   }
00214
00215   /* Change CRC peripheral state */
00216   hcrc->State = HAL_CRC_STATE_BUSY;
00217
00218   /* Reset CRC calculation unit */
00219   __HAL_CRC_DR_RESET(hcrc);
00220
00221   /* Reset IDR register content */
00222   CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
00223
00224   /* DeInit the low level hardware */
00225   HAL_CRC_MspDeInit(hcrc);
00226
00227   /* Change CRC peripheral state */
00228   hcrc->State = HAL_CRC_STATE_RESET;
00229
00230   /* Process unlocked */
00231   __HAL_UNLOCK(hcrc);
00232
00233   /* Return function status */
00234   return HAL_OK;
00235 }
00236
00237 /**
00238   * @brief  Initializes the CRC MSP.
00239   * @param  hcrc: CRC handle
00240   * @retval None
00241   */
00242 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
00243 {
00244   /* Prevent unused argument(s) compilation warning */
00245   UNUSED(hcrc);
00246
00247   /* NOTE : This function should not be modified, when the callback is needed,
00248             the HAL_CRC_MspInit can be implemented in the user file
00249    */
00250 }
00251
00252 /**
00253   * @brief  DeInitialize the CRC MSP.
00254   * @param  hcrc: CRC handle
00255   * @retval None
00256   */
00257 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
00258 {
00259   /* Prevent unused argument(s) compilation warning */
00260   UNUSED(hcrc);
00261
00262   /* NOTE : This function should not be modified, when the callback is needed,
00263             the HAL_CRC_MspDeInit can be implemented in the user file
00264    */
00265 }
00266
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00272  *  @brief    management functions.
00273  *
00274 @verbatim
00275  ===============================================================================
00276                       ##### Peripheral Control functions #####
00277  ===============================================================================
00278     [..]  This section provides functions allowing to:
00279       (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00280           using the combination of the previous CRC value and the new one
00281
00282        [..]  or
00283
00284       (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00285           independently of the previous CRC value.
00286
00287 @endverbatim
00288   * @{
00289   */
00290
00291 /**
00292   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00293   *         starting with the previously computed CRC as initialization value.
00294   * @param  hcrc: CRC handle
00295   * @param  pBuffer: pointer to the input data buffer, exact input data format is
00296   *         provided by hcrc->InputDataFormat.
00297   * @param  BufferLength: input data buffer length (number of bytes if pBuffer
00298   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00299   *         number of words if pBuffer type is * uint32_t).
00300   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00301   *        Input buffer pointers with other types simply need to be cast in uint32_t
00302   *        and the API will internally adjust its input data processing based on the
00303   *        handle field hcrc->InputDataFormat.
00304   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00305   */
00306 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00307 {
00308   uint32_t index = 0; /* CRC input data buffer index */
00309   uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */
00310
00311   /* Process locked */
00312   __HAL_LOCK(hcrc);
00313
00314   /* Change CRC peripheral state */
00315   hcrc->State = HAL_CRC_STATE_BUSY;
00316
00317   switch (hcrc->InputDataFormat)
00318   {
00319     case CRC_INPUTDATA_FORMAT_WORDS:
00320       /* Enter Data to the CRC calculator */
00321       for(index = 0; index < BufferLength; index++)
00322       {
00323         hcrc->Instance->DR = pBuffer[index];
00324       }
00325       temp = hcrc->Instance->DR;
00326       break;
00327
00328     case CRC_INPUTDATA_FORMAT_BYTES:
00329       temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
00330       break;
00331
00332     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00333       temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
00334       break;
00335
00336     default:
00337       break;
00338   }
00339
00340   /* Change CRC peripheral state */
00341   hcrc->State = HAL_CRC_STATE_READY;
00342
00343   /* Process unlocked */
00344   __HAL_UNLOCK(hcrc);
00345
00346   /* Return the CRC computed value */
00347   return temp;
00348 }
00349
00350
00351 /**
00352   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00353   *         starting with hcrc->Instance->INIT as initialization value.
00354   * @param  hcrc: CRC handle
00355   * @param  pBuffer: pointer to the input data buffer, exact input data format is
00356   *         provided by hcrc->InputDataFormat.
00357   * @param  BufferLength: input data buffer length (number of bytes if pBuffer
00358   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00359   *         number of words if pBuffer type is * uint32_t).
00360   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00361   *        Input buffer pointers with other types simply need to be cast in uint32_t
00362   *        and the API will internally adjust its input data processing based on the
00363   *        handle field hcrc->InputDataFormat.
00364   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00365   */
00366 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00367 {
00368   uint32_t index = 0; /* CRC input data buffer index */
00369   uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */
00370
00371   /* Process locked */
00372   __HAL_LOCK(hcrc);
00373
00374   /* Change CRC peripheral state */
00375   hcrc->State = HAL_CRC_STATE_BUSY;
00376
00377   /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
00378   *  written in hcrc->Instance->DR) */
00379   __HAL_CRC_DR_RESET(hcrc);
00380
00381   switch (hcrc->InputDataFormat)
00382   {
00383     case CRC_INPUTDATA_FORMAT_WORDS:
00384       /* Enter 32-bit input data to the CRC calculator */
00385       for(index = 0; index < BufferLength; index++)
00386       {
00387         hcrc->Instance->DR = pBuffer[index];
00388       }
00389       temp = hcrc->Instance->DR;
00390       break;
00391
00392     case CRC_INPUTDATA_FORMAT_BYTES:
00393       /* Specific 8-bit input data handling  */
00394       temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
00395       break;
00396
00397     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00398       /* Specific 16-bit input data handling  */
00399       temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
00400       break;
00401
00402     default:
00403       break;
00404   }
00405
00406   /* Change CRC peripheral state */
00407   hcrc->State = HAL_CRC_STATE_READY;
00408
00409   /* Process unlocked */
00410   __HAL_UNLOCK(hcrc);
00411
00412   /* Return the CRC computed value */
00413   return temp;
00414 }
00415
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00421  *  @brief    Peripheral State functions.
00422  *
00423 @verbatim
00424  ===============================================================================
00425                       ##### Peripheral State functions #####
00426  ===============================================================================
00427     [..]
00428     This subsection permits to get in run-time the status of the peripheral.
00429
00430 @endverbatim
00431   * @{
00432   */
00433
00434 /**
00435   * @brief  Return the CRC handle state.
00436   * @param  hcrc: CRC handle
00437   * @retval HAL state
00438   */
00439 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
00440 {
00441   /* Return CRC handle state */
00442   return hcrc->State;
00443 }
00444
00445 /**
00446   * @}
00447   */
00448
00449 /**
00450   * @}
00451   */
00452
00453 /** @defgroup CRC_Private_Functions CRC Private Functions
00454  * @{
00455  */
00456
00457 /**
00458   * @brief  Enter 8-bit input data to the CRC calculator.
00459   *         Specific data handling to optimize processing time.
00460   * @param  hcrc: CRC handle
00461   * @param  pBuffer: pointer to the input data buffer
00462   * @param  BufferLength: input data buffer length
00463   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00464   */
00465 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
00466 {
00467   uint32_t i = 0; /* input data buffer index */
00468
00469    /* Processing time optimization: 4 bytes are entered in a row with a single word write,
00470     * last bytes must be carefully fed to the CRC calculator to ensure a correct type
00471     * handling by the IP */
00472    for(i = 0; i < (BufferLength/4); i++)
00473    {
00474       hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3];
00475    }
00476    /* last bytes specific handling */
00477    if ((BufferLength%4) != 0)
00478    {
00479      if  (BufferLength%4 == 1)
00480      {
00481        *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
00482      }
00483      if  (BufferLength%4 == 2)
00484      {
00485        *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
00486      }
00487      if  (BufferLength%4 == 3)
00488      {
00489        *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
00490        *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
00491      }
00492    }
00493
00494   /* Return the CRC computed value */
00495   return hcrc->Instance->DR;
00496 }
00497
00498
00499
00500 /**
00501   * @brief  Enter 16-bit input data to the CRC calculator.
00502   *         Specific data handling to optimize processing time.
00503   * @param  hcrc: CRC handle
00504   * @param  pBuffer: pointer to the input data buffer
00505   * @param  BufferLength: input data buffer length
00506   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00507   */
00508 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
00509 {
00510   uint32_t i = 0;  /* input data buffer index */
00511
00512   /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
00513    * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
00514    * a correct type handling by the IP */
00515   for(i = 0; i < (BufferLength/2); i++)
00516   {
00517     hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1];
00518   }
00519   if ((BufferLength%2) != 0)
00520   {
00521        *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i];
00522   }
00523
00524   /* Return the CRC computed value */
00525   return hcrc->Instance->DR;
00526 }
00527
00528 /**
00529   * @}
00530   */
00531
00532 #endif /* HAL_CRC_MODULE_ENABLED */
00533 /**
00534   * @}
00535   */
00536
00537 /**
00538   * @}
00539   */
00540
00541 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_crc.h Source File

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stm32l4xx_hal_crc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_crc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of CRC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_CRC_H
00040 #define __STM32L4xx_HAL_CRC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CRC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup CRC_Exported_Types CRC Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  CRC HAL State Structure definition
00065   */
00066 typedef enum
00067 {
00068   HAL_CRC_STATE_RESET     = 0x00,  /*!< CRC not yet initialized or disabled */
00069   HAL_CRC_STATE_READY     = 0x01,  /*!< CRC initialized and ready for use   */
00070   HAL_CRC_STATE_BUSY      = 0x02,  /*!< CRC internal process is ongoing     */
00071   HAL_CRC_STATE_TIMEOUT   = 0x03,  /*!< CRC timeout state                   */
00072   HAL_CRC_STATE_ERROR     = 0x04   /*!< CRC error state                     */
00073 }HAL_CRC_StateTypeDef;
00074
00075
00076
00077 /**
00078   * @brief CRC Init Structure definition
00079   */
00080 typedef struct
00081 {
00082   uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
00083                                             If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
00084                                             X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
00085                                             In that case, there is no need to set GeneratingPolynomial field.
00086                                             If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
00087
00088   uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
00089                                            If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
00090                                            0xFFFFFFFF value. In that case, there is no need to set InitValue field.
00091                                            If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set. */
00092
00093   uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
00094                                            respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
00095                                            e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
00096                                            No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.   */
00097
00098   uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
00099                                            Value can be either one of
00100                                            @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
00101                                            @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
00102                                            @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
00103                                            @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
00104
00105   uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
00106                                            is set to DEFAULT_INIT_VALUE_ENABLE.   */
00107
00108   uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
00109                                            Can be either one of the following values
00110                                            @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
00111                                            @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
00112                                            @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
00113                                            @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
00114
00115   uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
00116                                             Can be either
00117                                             @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
00118                                             @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */
00119 }CRC_InitTypeDef;
00120
00121
00122
00123 /**
00124   * @brief  CRC Handle Structure definition
00125   */
00126 typedef struct
00127 {
00128   CRC_TypeDef                 *Instance;   /*!< Register base address        */
00129
00130   CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
00131
00132   HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
00133
00134   __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
00135
00136   uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
00137                                             Can be either
00138                                             @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
00139                                             @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
00140                                             @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bit data)
00141
00142                                            Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
00143                                            must occur if InputBufferFormat is not one of the three values listed above  */
00144 }CRC_HandleTypeDef;
00145
00146
00147 /**
00148   * @}
00149   */
00150
00151 /* Exported constants --------------------------------------------------------*/
00152 /** @defgroup CRC_Exported_Constants CRC Exported Constants
00153   * @{
00154   */
00155
00156 /** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
00157   * @{
00158   */
00159 #define DEFAULT_CRC32_POLY      0x04C11DB7  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
00165   * @{
00166   */
00167 #define DEFAULT_CRC_INITVALUE   0xFFFFFFFF  /*!< Initial CRC default value */
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
00173   * @{
00174   */
00175 #define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00)  /*!< Enable default generating polynomial 0x04C11DB7  */
00176 #define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01)  /*!< Disable default generating polynomial 0x04C11DB7 */
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
00182   * @{
00183   */
00184 #define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00) /*!< Enable initial CRC default value  */
00185 #define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01) /*!< Disable initial CRC default value */
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
00191   * @{
00192   */
00193 #define CRC_POLYLENGTH_32B                  ((uint32_t)0x00000000)        /*!< Resort to a 32-bit long generating polynomial */
00194 #define CRC_POLYLENGTH_16B                  ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */
00195 #define CRC_POLYLENGTH_8B                   ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial  */
00196 #define CRC_POLYLENGTH_7B                   ((uint32_t)CRC_CR_POLYSIZE)   /*!< Resort to a 7-bit long generating polynomial  */
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
00202   * @{
00203   */
00204 #define HAL_CRC_LENGTH_32B     32          /*!< 32-bit long CRC */
00205 #define HAL_CRC_LENGTH_16B     16          /*!< 16-bit long CRC */
00206 #define HAL_CRC_LENGTH_8B       8          /*!< 8-bit long CRC  */
00207 #define HAL_CRC_LENGTH_7B       7          /*!< 7-bit long CRC  */
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup CRC_Input_Buffer_Format Input Buffer Format
00213   * @{
00214   */
00215 /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
00216  * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
00217  * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
00218  * the CRC APIs to provide a correct result */
00219 #define CRC_INPUTDATA_FORMAT_UNDEFINED             ((uint32_t)0x00000000)  /*!< Undefined input data format    */
00220 #define CRC_INPUTDATA_FORMAT_BYTES                 ((uint32_t)0x00000001)  /*!< Input data in byte format      */
00221 #define CRC_INPUTDATA_FORMAT_HALFWORDS             ((uint32_t)0x00000002)  /*!< Input data in half-word format */
00222 #define CRC_INPUTDATA_FORMAT_WORDS                 ((uint32_t)0x00000003)  /*!< Input data in word format      */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup CRC_Aliases CRC API aliases
00228   * @{
00229   */
00230 #define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
00231 #define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
00232 /**
00233   * @}
00234   */
00235
00236 /**
00237   * @}
00238   */
00239
00240
00241 /* Exported macros -----------------------------------------------------------*/
00242 /** @defgroup CRC_Exported_Macros CRC Exported Macros
00243   * @{
00244   */
00245
00246 /** @brief Reset CRC handle state.
00247   * @param  __HANDLE__: CRC handle.
00248   * @retval None
00249   */
00250 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
00251
00252 /**
00253   * @brief  Reset CRC Data Register.
00254   * @param  __HANDLE__: CRC handle
00255   * @retval None
00256   */
00257 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
00258
00259 /**
00260   * @brief  Set CRC INIT non-default value
00261   * @param  __HANDLE__: CRC handle
00262   * @param  __INIT__: 32-bit initial value
00263   * @retval None
00264   */
00265 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
00266
00267 /**
00268   * @brief Store a 8-bit data in the Independent Data(ID) register.
00269   * @param __HANDLE__: CRC handle
00270   * @param __VALUE__: 8-bit value to be stored in the ID register
00271   * @retval None
00272   */
00273 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
00274
00275 /**
00276   * @brief Return the 8-bit data stored in the Independent Data(ID) register.
00277   * @param __HANDLE__: CRC handle
00278   * @retval 8-bit value of the ID register
00279   */
00280 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
00281 /**
00282   * @}
00283   */
00284
00285
00286 /* Private macros --------------------------------------------------------*/
00287 /** @addtogroup  CRC_Private_Macros   CRC Private Macros
00288   * @{
00289   */
00290
00291 #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
00292                                         ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
00293
00294
00295 #define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
00296                                        ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
00297
00298 #define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
00299                                        ((LENGTH) == CRC_POLYLENGTH_16B) || \
00300                                        ((LENGTH) == CRC_POLYLENGTH_8B)  || \
00301                                        ((LENGTH) == CRC_POLYLENGTH_7B))
00302
00303 #define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
00304                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
00305                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
00306
00307 /**
00308   * @}
00309   */
00310
00311 /* Include CRC HAL Extended module */
00312 #include "stm32l4xx_hal_crc_ex.h"
00313
00314 /* Exported functions --------------------------------------------------------*/
00315 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00316   * @{
00317   */
00318
00319 /* Initialization and de-initialization functions  ****************************/
00320 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00321   * @{
00322   */
00323 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
00324 HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
00325 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
00326 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
00327 /**
00328   * @}
00329   */
00330
00331 /* Peripheral Control functions ***********************************************/
00332 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00333   * @{
00334   */
00335 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00336 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00337 /**
00338   * @}
00339   */
00340
00341 /* Peripheral State and Error functions ***************************************/
00342 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00343   * @{
00344   */
00345 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
00346 /**
00347   * @}
00348   */
00349
00350 /**
00351   * @}
00352   */
00353
00354 /**
00355   * @}
00356   */
00357
00358 /**
00359   * @}
00360   */
00361
00362 #ifdef __cplusplus
00363 }
00364 #endif
00365
00366 #endif /* __STM32L4xx_HAL_CRC_H */
00367
00368 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_crc_ex.c Source File

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stm32l4xx_hal_crc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_crc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Extended CRC HAL module driver.
00008   *          This file provides firmware functions to manage the extended
00009   *          functionalities of the CRC peripheral.
00010   *
00011   @verbatim
00012 ================================================================================
00013             ##### How to use this driver #####
00014 ================================================================================
00015     [..]
00016          (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
00017          (+) Configure Input or Output data inversion
00018
00019   @endverbatim
00020   ******************************************************************************
00021   * @attention
00022   *
00023   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00024   *
00025   * Redistribution and use in source and binary forms, with or without modification,
00026   * are permitted provided that the following conditions are met:
00027   *   1. Redistributions of source code must retain the above copyright notice,
00028   *      this list of conditions and the following disclaimer.
00029   *   2. Redistributions in binary form must reproduce the above copyright notice,
00030   *      this list of conditions and the following disclaimer in the documentation
00031   *      and/or other materials provided with the distribution.
00032   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00033   *      may be used to endorse or promote products derived from this software
00034   *      without specific prior written permission.
00035   *
00036   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00037   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00038   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00039   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00040   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00041   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00042   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00043   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00044   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00045   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00046   *
00047   ******************************************************************************
00048   */
00049
00050 /* Includes ------------------------------------------------------------------*/
00051 #include "stm32l4xx_hal.h"
00052
00053 /** @addtogroup STM32L4xx_HAL_Driver
00054   * @{
00055   */
00056
00057 /** @defgroup CRCEx CRCEx
00058   * @brief CRC Extended HAL module driver
00059   * @{
00060   */
00061
00062 #ifdef HAL_CRC_MODULE_ENABLED
00063
00064 /* Private typedef -----------------------------------------------------------*/
00065 /* Private define ------------------------------------------------------------*/
00066 /* Private macro -------------------------------------------------------------*/
00067 /* Private variables ---------------------------------------------------------*/
00068 /* Private function prototypes -----------------------------------------------*/
00069 /* Exported functions --------------------------------------------------------*/
00070
00071 /** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
00072   * @{
00073   */
00074
00075 /** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
00076   * @brief    Extended Initialization and Configuration functions.
00077   *
00078 @verbatim
00079  ===============================================================================
00080             ##### Extended configuration functions #####
00081  ===============================================================================
00082     [..]  This section provides functions allowing to:
00083       (+) Configure the generating polynomial
00084       (+) Configure the input data inversion
00085       (+) Configure the output data inversion
00086
00087 @endverbatim
00088   * @{
00089   */
00090
00091
00092 /**
00093   * @brief  Initialize the CRC polynomial if different from default one.
00094   * @param  hcrc: CRC handle
00095   * @param  Pol: CRC generating polynomial (7, 8, 16 or 32-bit long).
00096   *         This parameter is written in normal representation, e.g.
00097   *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00098   *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
00099   * @param  PolyLength: CRC polynomial length.
00100   *         This parameter can be one of the following values:
00101   *          @arg @ref CRC_POLYLENGTH_7B  7-bit long CRC (generating polynomial of degree 7)
00102   *          @arg @ref CRC_POLYLENGTH_8B  8-bit long CRC (generating polynomial of degree 8)
00103   *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
00104   *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
00105   * @retval HAL status
00106   */
00107 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
00108 {
00109   uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
00110
00111   /* Check the parameters */
00112   assert_param(IS_CRC_POL_LENGTH(PolyLength));
00113
00114   /* check polynomial definition vs polynomial size:
00115    * polynomial length must be aligned with polynomial
00116    * definition. HAL_ERROR is reported if Pol degree is
00117    * larger than that indicated by PolyLength.
00118    * Look for MSB position: msb will contain the degree of
00119    *  the second to the largest polynomial member. E.g., for
00120    *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
00121   while (((Pol & (1U << msb)) == 0) && (msb-- > 0)) {}
00122
00123   switch (PolyLength)
00124   {
00125     case CRC_POLYLENGTH_7B:
00126       if (msb >= HAL_CRC_LENGTH_7B)
00127       {
00128         return  HAL_ERROR;
00129       }
00130       break;
00131     case CRC_POLYLENGTH_8B:
00132       if (msb >= HAL_CRC_LENGTH_8B)
00133       {
00134         return  HAL_ERROR;
00135       }
00136       break;
00137     case CRC_POLYLENGTH_16B:
00138       if (msb >= HAL_CRC_LENGTH_16B)
00139       {
00140         return  HAL_ERROR;
00141       }
00142       break;
00143     case CRC_POLYLENGTH_32B:
00144       /* no polynomial definition vs. polynomial length issue possible */
00145       break;
00146     default:
00147       break;
00148   }
00149
00150   /* set generating polynomial */
00151   WRITE_REG(hcrc->Instance->POL, Pol);
00152
00153   /* set generating polynomial size */
00154   MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
00155
00156   /* Return function status */
00157   return HAL_OK;
00158 }
00159
00160 /**
00161   * @brief  Set the Reverse Input data mode.
00162   * @param  hcrc: CRC handle
00163   * @param  InputReverseMode: Input Data inversion mode.
00164   *         This parameter can be one of the following values:
00165   *          @arg @ref CRC_INPUTDATA_INVERSION_NONE     no change in bit order (default value)
00166   *          @arg @ref CRC_INPUTDATA_INVERSION_BYTE     Byte-wise bit reversal
00167   *          @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
00168   *          @arg @ref CRC_INPUTDATA_INVERSION_WORD     Word-wise bit reversal
00169   * @retval HAL status
00170   */
00171 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
00172 {
00173   /* Check the parameters */
00174   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
00175
00176   /* Change CRC peripheral state */
00177   hcrc->State = HAL_CRC_STATE_BUSY;
00178
00179   /* set input data inversion mode */
00180   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
00181   /* Change CRC peripheral state */
00182   hcrc->State = HAL_CRC_STATE_READY;
00183
00184   /* Return function status */
00185   return HAL_OK;
00186 }
00187
00188 /**
00189   * @brief  Set the Reverse Output data mode.
00190   * @param  hcrc: CRC handle
00191   * @param  OutputReverseMode: Output Data inversion mode.
00192   *         This parameter can be one of the following values:
00193   *          @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
00194   *          @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE  bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
00195   * @retval HAL status
00196   */
00197 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
00198 {
00199   /* Check the parameters */
00200   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
00201
00202   /* Change CRC peripheral state */
00203   hcrc->State = HAL_CRC_STATE_BUSY;
00204
00205   /* set output data inversion mode */
00206   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
00207
00208   /* Change CRC peripheral state */
00209   hcrc->State = HAL_CRC_STATE_READY;
00210
00211   /* Return function status */
00212   return HAL_OK;
00213 }
00214
00215
00216
00217
00218 /**
00219   * @}
00220   */
00221
00222
00223 /**
00224   * @}
00225   */
00226
00227
00228 #endif /* HAL_CRC_MODULE_ENABLED */
00229 /**
00230   * @}
00231   */
00232
00233 /**
00234   * @}
00235   */
00236
00237 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_crc_ex.h Source File

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stm32l4xx_hal_crc_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_crc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of CRC HAL extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_CRC_EX_H
00040 #define __STM32L4xx_HAL_CRC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CRCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup CRCEx_Exported_Constants CRCEx Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
00064   * @{
00065   */
00066 #define CRC_INPUTDATA_INVERSION_NONE              ((uint32_t)0x00000000)      /*!< No input data inversion            */
00067 #define CRC_INPUTDATA_INVERSION_BYTE              ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion     */
00068 #define CRC_INPUTDATA_INVERSION_HALFWORD          ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */
00069 #define CRC_INPUTDATA_INVERSION_WORD              ((uint32_t)CRC_CR_REV_IN)   /*!< Word-wise input data inversion     */
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
00075   * @{
00076   */
00077 #define CRC_OUTPUTDATA_INVERSION_DISABLE         ((uint32_t)0x00000000)     /*!< No output data inversion       */
00078 #define CRC_OUTPUTDATA_INVERSION_ENABLE          ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */
00079 /**
00080   * @}
00081   */
00082
00083 /**
00084   * @}
00085   */
00086
00087 /* Exported macro ------------------------------------------------------------*/
00088 /** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros
00089   * @{
00090   */
00091
00092 /**
00093   * @brief  Set CRC output reversal
00094   * @param  __HANDLE__: CRC handle
00095   * @retval None
00096   */
00097 #define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
00098
00099 /**
00100   * @brief  Unset CRC output reversal
00101   * @param  __HANDLE__: CRC handle
00102   * @retval None
00103   */
00104 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
00105
00106 /**
00107   * @brief  Set CRC non-default polynomial
00108   * @param  __HANDLE__: CRC handle
00109   * @param  __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
00110   * @retval None
00111   */
00112 #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
00113
00114 /**
00115   * @}
00116   */
00117
00118 /* Private macros --------------------------------------------------------*/
00119 /** @addtogroup  CRCEx_Private_Macros   CRCEx Private Macros
00120   * @{
00121   */
00122
00123 #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
00124                                                    ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
00125                                                    ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
00126                                                    ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
00127
00128
00129 #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
00130                                                    ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
00131
00132 /**
00133   * @}
00134   */
00135
00136 /* Exported functions --------------------------------------------------------*/
00137
00138 /** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions
00139   * @{
00140   */
00141
00142 /** @addtogroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
00143   * @{
00144   */
00145
00146 /* Initialization and de-initialization functions  ****************************/
00147 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
00148 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
00149 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
00150
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 #ifdef __cplusplus
00168 }
00169 #endif
00170
00171 #endif /* __STM32L4xx_HAL_CRC_EX_H */
00172
00173 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cryp.c Source File

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stm32l4xx_hal_cryp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_cryp.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   CRYP HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Cryptography (CRYP) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Processing functions using polling mode
00012   *           + Processing functions using interrupt mode
00013   *           + Processing functions using DMA mode
00014   *           + Peripheral State functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                      ##### How to use this driver #####
00019   ==============================================================================
00020     [..]
00021       The CRYP HAL driver can be used as follows:
00022
00023       (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
00024          (++) Enable the CRYP interface clock using __HAL_RCC_AES_CLK_ENABLE()
00025          (++) In case of using interrupts (e.g. HAL_CRYP_AES_IT())
00026              (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
00027              (+++) Enable the AES IRQ handler using HAL_NVIC_EnableIRQ()
00028              (+++) In AES IRQ handler, call HAL_CRYP_IRQHandler()
00029          (++) In case of using DMA to control data transfer (e.g. HAL_CRYPEx_AES_DMA())
00030              (+++) Enable the DMA2 interface clock using
00031                  __HAL_RCC_DMA2_CLK_ENABLE()
00032              (+++) Configure and enable two DMA channels one for managing data transfer from
00033                  memory to peripheral (input channel) and another channel for managing data
00034                  transfer from peripheral to memory (output channel)
00035              (+++) Associate the initialized DMA handle to the CRYP DMA handle
00036                  using __HAL_LINKDMA()
00037              (+++) Configure the priority and enable the NVIC for the transfer complete
00038                  interrupt on the two DMA channels. The output channel should have higher
00039                  priority than the input channel.
00040                  Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00041
00042       (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures:
00043          (++) The data type: 1-bit, 8-bit, 16-bit and 32-bit
00044          (++) The AES operating mode (encryption, key derivation and/or decryption)
00045          (++) The AES chaining mode (ECB, CBC, CTR, GCM, GMAC, CMAC)
00046          (++) The encryption/decryption key if so required
00047          (++) The initialization vector or nonce if applicable (not used in ECB mode).
00048
00049       (#)Three processing (encryption/decryption) functions are available:
00050          (++) Polling mode: encryption and decryption APIs are blocking functions
00051               i.e. they process the data and wait till the processing is finished
00052          (++) Interrupt mode: encryption and decryption APIs are not blocking functions
00053               i.e. they process the data under interrupt
00054          (++) DMA mode: encryption and decryption APIs are not blocking functions
00055               i.e. the data transfer is ensured by DMA
00056
00057        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
00058
00059   @endverbatim
00060   ******************************************************************************
00061   * @attention
00062   *
00063   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00064   *
00065   * Redistribution and use in source and binary forms, with or without modification,
00066   * are permitted provided that the following conditions are met:
00067   *   1. Redistributions of source code must retain the above copyright notice,
00068   *      this list of conditions and the following disclaimer.
00069   *   2. Redistributions in binary form must reproduce the above copyright notice,
00070   *      this list of conditions and the following disclaimer in the documentation
00071   *      and/or other materials provided with the distribution.
00072   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00073   *      may be used to endorse or promote products derived from this software
00074   *      without specific prior written permission.
00075   *
00076   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00077   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00078   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00079   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00080   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00081   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00082   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00083   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00084   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00085   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00086   *
00087   ******************************************************************************
00088   */
00089
00090 /* Includes ------------------------------------------------------------------*/
00091 #include "stm32l4xx_hal.h"
00092
00093 #ifdef HAL_CRYP_MODULE_ENABLED
00094
00095 #if defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx)
00096
00097 /** @addtogroup STM32L4xx_HAL_Driver
00098   * @{
00099   */
00100
00101 /** @defgroup CRYP CRYP
00102   * @brief CRYP HAL module driver.
00103   * @{
00104   */
00105
00106
00107
00108 /* Private typedef -----------------------------------------------------------*/
00109 /* Private define ------------------------------------------------------------*/
00110 /* Private macro -------------------------------------------------------------*/
00111 /* Private variables ---------------------------------------------------------*/
00112 /* Private functions --------------------------------------------------------*/
00113
00114 /** @defgroup CRYP_Private_Functions CRYP Private Functions
00115   * @{
00116   */
00117
00118 static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp);
00119 static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp);
00120 static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
00121
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported functions ---------------------------------------------------------*/
00127
00128 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
00129   * @{
00130   */
00131
00132 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
00133  *  @brief    Initialization and Configuration functions.
00134  *
00135 @verbatim
00136   ==============================================================================
00137               ##### Initialization and deinitialization functions #####
00138   ==============================================================================
00139     [..]  This section provides functions allowing to:
00140       (+) Initialize the CRYP according to the specified parameters
00141           in the CRYP_InitTypeDef and creates the associated handle
00142       (+) DeInitialize the CRYP peripheral
00143       (+) Initialize the CRYP MSP (MCU Specific Package)
00144       (+) De-Initialize the CRYP MSP
00145
00146     [..]
00147     (@) Specific care must be taken to format the key and the Initialization Vector IV!
00148
00149    [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
00150         b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
00151         (+) as a sequence of words where the MSB word comes first (occupies the
00152           lowest memory address)
00153         (+) where each word is byte-swapped:
00154          (++)   address n+0 : 0b b103 .. b96 b111 .. b104 b119 .. b112 b127 .. b120
00155          (++)   address n+4 : 0b b71 .. b64 b79 .. b72 b87 .. b80 b95 .. b88
00156          (++)   address n+8 : 0b b39 .. b32 b47 .. b40 b55 .. b48 b63 .. b56
00157          (++)   address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24
00158     [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
00159         The 4 32-bit words that make the key must be stored as follows in MCU memory:
00160          (+)    address n+0 : 0x B12 B13 B14 B15
00161          (+)    address n+4 : 0x B8 B9 B10 B11
00162          (+)    address n+8 : 0x B4 B5 B6 B7
00163          (+)    address n+C : 0x B0 B1 B2 B3
00164     [..]  which leads to the expected setting
00165       (+)       AES_KEYR3 = 0x B15 B14 B13 B12
00166       (+)       AES_KEYR2 = 0x B11 B10 B9 B8
00167       (+)       AES_KEYR1 = 0x B7 B6 B5 B4
00168       (+)       AES_KEYR0 = 0x B3 B2 B1 B0
00169
00170    [..]  Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
00171          The 8 32-bit words that make the key must be stored as follows in MCU memory:
00172          (+)    address n+00 : 0x B28 B29 B30 B31
00173          (+)    address n+04 : 0x B24 B25 B26 B27
00174          (+)    address n+08 : 0x B20 B21 B22 B23
00175          (+)    address n+0C : 0x B16 B17 B18 B19
00176          (+)    address n+10 : 0x B12 B13 B14 B15
00177          (+)    address n+14 : 0x B8 B9 B10 B11
00178          (+)    address n+18 : 0x B4 B5 B6 B7
00179          (+)    address n+1C : 0x B0 B1 B2 B3
00180     [..]  which leads to the expected setting
00181       (+)       AES_KEYR7 = 0x B31 B30 B29 B28
00182       (+)       AES_KEYR6 = 0x B27 B26 B25 B24
00183       (+)       AES_KEYR5 = 0x B23 B22 B21 B20
00184       (+)       AES_KEYR4 = 0x B19 B18 B17 B16
00185       (+)       AES_KEYR3 = 0x B15 B14 B13 B12
00186       (+)       AES_KEYR2 = 0x B11 B10 B9 B8
00187       (+)       AES_KEYR1 = 0x B7 B6 B5 B4
00188       (+)       AES_KEYR0 = 0x B3 B2 B1 B0
00189
00190    [..] Initialization Vector IV (4 32-bit words) format must follow the same as
00191         that of a 128-bit long key.
00192
00193   [..]
00194
00195 @endverbatim
00196   * @{
00197   */
00198
00199   /**
00200   * @brief  Initialize the CRYP according to the specified
00201   *         parameters in the CRYP_InitTypeDef and initialize the associated handle.
00202   * @note Specific care must be taken to format the key and the Initialization Vector IV
00203   *       stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations
00204   *       hereabove.
00205   * @retval HAL status
00206   */
00207 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
00208 {
00209   /* Check the CRYP handle allocation */
00210   if(hcryp == NULL)
00211   {
00212     return HAL_ERROR;
00213   }
00214
00215   /* Check the instance */
00216   assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
00217
00218   /* Check the parameters */
00219   assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
00220   assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
00221   assert_param(IS_CRYP_ALGOMODE(hcryp->Init.OperatingMode));
00222   /* ChainingMode parameter is irrelevant when mode is set to Key derivation */
00223   if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
00224   {
00225     assert_param(IS_CRYP_CHAINMODE(hcryp->Init.ChainingMode));
00226   }
00227   assert_param(IS_CRYP_WRITE(hcryp->Init.KeyWriteFlag));
00228
00229   /*========================================================*/
00230   /* Check the proper operating/chaining modes combinations */
00231   /*========================================================*/
00232   /* Check the proper chaining when the operating mode is key derivation and decryption */
00233   if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
00234          ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR)           \
00235        || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)      \
00236        || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)))
00237   {
00238     return HAL_ERROR;
00239   }
00240   /* Check that key derivation is not set in CMAC mode */
00241   if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
00242    && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
00243   {
00244     return HAL_ERROR;
00245   }
00246
00247
00248   /*================*/
00249   /* Initialization */
00250   /*================*/
00251   /* Initialization start */
00252   if(hcryp->State == HAL_CRYP_STATE_RESET)
00253   {
00254     /* Allocate lock resource and initialize it */
00255     hcryp->Lock = HAL_UNLOCKED;
00256
00257     /* Init the low level hardware */
00258     HAL_CRYP_MspInit(hcryp);
00259   }
00260
00261   /* Change the CRYP state */
00262   hcryp->State = HAL_CRYP_STATE_BUSY;
00263
00264   /* Disable the Peripheral */
00265   __HAL_CRYP_DISABLE();
00266
00267   /*=============================================================*/
00268   /* AES initialization common to all operating modes            */
00269   /*=============================================================*/
00270   /* Set the Key size selection */
00271   MODIFY_REG(hcryp->Instance->CR, AES_CR_KEYSIZE, hcryp->Init.KeySize);
00272
00273   /* Set the default CRYP phase when this parameter is not used.
00274      Phase is updated below in case of GCM/GMAC/CMAC setting. */
00275   hcryp->Phase = HAL_CRYP_PHASE_NOT_USED;
00276
00277
00278
00279   /*=============================================================*/
00280   /* Carry on the initialization based on the AES operating mode */
00281   /*=============================================================*/
00282   /* Key derivation */
00283   if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
00284   {
00285     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_ALGOMODE_KEYDERIVATION);
00286
00287     /* Configure the Key registers */
00288     if (CRYP_SetKey(hcryp) != HAL_OK)
00289     {
00290       return HAL_ERROR;
00291     }
00292   }
00293   else
00294   /* Encryption / Decryption (with or without key derivation) / authentication */
00295   {
00296     /* Set data type, operating and chaining modes.
00297        In case of GCM or GMAC, data type is forced to 0b00 */
00298     if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
00299     {
00300       MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
00301     }
00302     else
00303     {
00304       MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.DataType|hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
00305     }
00306
00307
00308    /* Specify the encryption/decryption phase in case of Galois counter mode (GCM),
00309       Galois message authentication code (GMAC) or cipher message authentication code (CMAC) */
00310    if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
00311     || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
00312     {
00313       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, hcryp->Init.GCMCMACPhase);
00314       hcryp->Phase = HAL_CRYP_PHASE_START;
00315     }
00316
00317
00318     /* Configure the Key registers if no need to bypass this step */
00319     if (hcryp->Init.KeyWriteFlag == CRYP_KEY_WRITE_ENABLE)
00320     {
00321       if (CRYP_SetKey(hcryp) != HAL_OK)
00322       {
00323         return HAL_ERROR;
00324       }
00325     }
00326
00327     /* If applicable, configure the Initialization Vector */
00328     if (hcryp->Init.ChainingMode != CRYP_CHAINMODE_AES_ECB)
00329     {
00330       if (CRYP_SetInitVector(hcryp) != HAL_OK)
00331       {
00332         return HAL_ERROR;
00333       }
00334     }
00335   }
00336
00337   /* Reset CrypInCount and CrypOutCount */
00338   hcryp->CrypInCount = 0;
00339   hcryp->CrypOutCount = 0;
00340
00341   /* Reset ErrorCode field */
00342   hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00343
00344   /* Reset Mode suspension request */
00345   hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
00346
00347   /* Change the CRYP state */
00348   hcryp->State = HAL_CRYP_STATE_READY;
00349
00350   /* Enable the Peripheral */
00351   __HAL_CRYP_ENABLE();
00352
00353   /* Return function status */
00354   return HAL_OK;
00355 }
00356
00357 /**
00358   * @brief  DeInitialize the CRYP peripheral.
00359   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00360   *         the configuration information for CRYP module
00361   * @retval HAL status
00362   */
00363 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
00364 {
00365   /* Check the CRYP handle allocation */
00366   if(hcryp == NULL)
00367   {
00368     return HAL_ERROR;
00369   }
00370
00371   /* Change the CRYP state */
00372   hcryp->State = HAL_CRYP_STATE_BUSY;
00373
00374   /* Set the default CRYP phase */
00375   hcryp->Phase = HAL_CRYP_PHASE_READY;
00376
00377   /* Reset CrypInCount and CrypOutCount */
00378   hcryp->CrypInCount = 0;
00379   hcryp->CrypOutCount = 0;
00380
00381   /* Disable the CRYP Peripheral Clock */
00382   __HAL_CRYP_DISABLE();
00383
00384   /* DeInit the low level hardware: CLOCK, NVIC.*/
00385   HAL_CRYP_MspDeInit(hcryp);
00386
00387   /* Change the CRYP state */
00388   hcryp->State = HAL_CRYP_STATE_RESET;
00389
00390   /* Release Lock */
00391   __HAL_UNLOCK(hcryp);
00392
00393   /* Return function status */
00394   return HAL_OK;
00395 }
00396
00397 /**
00398   * @brief  Initialize the CRYP MSP.
00399   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00400   *         the configuration information for CRYP module
00401   * @retval None
00402   */
00403 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
00404 {
00405   /* Prevent unused argument(s) compilation warning */
00406   UNUSED(hcryp);
00407
00408   /* NOTE : This function should not be modified; when the callback is needed,
00409             the HAL_CRYP_MspInit can be implemented in the user file
00410    */
00411 }
00412
00413 /**
00414   * @brief  DeInitialize CRYP MSP.
00415   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00416   *         the configuration information for CRYP module
00417   * @retval None
00418   */
00419 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
00420 {
00421   /* Prevent unused argument(s) compilation warning */
00422   UNUSED(hcryp);
00423
00424   /* NOTE : This function should not be modified; when the callback is needed,
00425             the HAL_CRYP_MspDeInit can be implemented in the user file
00426    */
00427 }
00428
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
00434  *  @brief   Processing functions.
00435  *
00436 @verbatim
00437   ==============================================================================
00438                       ##### AES processing functions #####
00439   ==============================================================================
00440     [..]  This section provides functions allowing to:
00441       (+) Encrypt plaintext using AES algorithm in different chaining modes
00442       (+) Decrypt cyphertext using AES algorithm in different chaining modes
00443     [..]  Three processing functions are available:
00444       (+) Polling mode
00445       (+) Interrupt mode
00446       (+) DMA mode
00447
00448 @endverbatim
00449   * @{
00450   */
00451
00452
00453 /**
00454   * @brief  Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData.
00455   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00456   *         the configuration information for CRYP module
00457   * @param  pPlainData: Pointer to the plaintext buffer
00458   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00459   * @param  pCypherData: Pointer to the cyphertext buffer
00460   * @param  Timeout: Specify Timeout value
00461   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00462   *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
00463   * @retval HAL status
00464   */
00465 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00466 {
00467   /* Re-initialize AES IP with proper parameters */
00468   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00469   {
00470     return HAL_ERROR;
00471   }
00472   hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
00473   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
00474   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00475   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00476   {
00477     return HAL_ERROR;
00478   }
00479
00480   return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
00481 }
00482
00483
00484 /**
00485   * @brief  Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData.
00486   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00487   *         the configuration information for CRYP module
00488   * @param  pPlainData: Pointer to the plaintext buffer
00489   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00490   * @param  pCypherData: Pointer to the cyphertext buffer
00491   * @param  Timeout: Specify Timeout value
00492   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00493   *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
00494   * @retval HAL status
00495   */
00496 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00497 {
00498   /* Re-initialize AES IP with proper parameters */
00499   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00500   {
00501     return HAL_ERROR;
00502   }
00503   hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
00504   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
00505   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00506   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00507   {
00508     return HAL_ERROR;
00509   }
00510
00511   return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
00512 }
00513
00514
00515 /**
00516   * @brief  Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData
00517   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00518   *         the configuration information for CRYP module
00519   * @param  pPlainData: Pointer to the plaintext buffer
00520   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00521   * @param  pCypherData: Pointer to the cyphertext buffer
00522   * @param  Timeout: Specify Timeout value
00523   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00524   *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
00525   * @retval HAL status
00526   */
00527 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
00528 {
00529   /* Re-initialize AES IP with proper parameters */
00530   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00531   {
00532     return HAL_ERROR;
00533   }
00534   hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
00535   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
00536   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00537   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00538   {
00539     return HAL_ERROR;
00540   }
00541
00542   return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
00543 }
00544
00545 /**
00546   * @brief  Decrypt pCypherData in AES ECB decryption mode with key derivation,
00547   *         the decyphered data are available in pPlainData.
00548   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00549   *         the configuration information for CRYP module
00550   * @param  pCypherData: Pointer to the cyphertext buffer
00551   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00552   * @param  pPlainData: Pointer to the plaintext buffer
00553   * @param  Timeout: Specify Timeout value
00554   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00555   *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
00556   * @retval HAL status
00557   */
00558 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
00559 {
00560   /* Re-initialize AES IP with proper parameters */
00561   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00562   {
00563     return HAL_ERROR;
00564   }
00565   hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
00566   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
00567   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00568   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00569   {
00570     return HAL_ERROR;
00571   }
00572
00573   return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
00574 }
00575
00576 /**
00577   * @brief  Decrypt pCypherData in AES ECB decryption mode with key derivation,
00578   *         the decyphered data are available in pPlainData.
00579   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00580   *         the configuration information for CRYP module
00581   * @param  pCypherData: Pointer to the cyphertext buffer
00582   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00583   * @param  pPlainData: Pointer to the plaintext buffer
00584   * @param  Timeout: Specify Timeout value
00585   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00586   *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
00587   * @retval HAL status
00588   */
00589 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
00590 {
00591   /* Re-initialize AES IP with proper parameters */
00592   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00593   {
00594     return HAL_ERROR;
00595   }
00596   hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
00597   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
00598   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00599   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00600   {
00601     return HAL_ERROR;
00602   }
00603
00604   return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
00605 }
00606
00607 /**
00608   * @brief  Decrypt pCypherData in AES CTR decryption mode,
00609   *         the decyphered data are available in pPlainData.
00610   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00611   *         the configuration information for CRYP module
00612   * @param  pCypherData: Pointer to the cyphertext buffer
00613   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00614   * @param  pPlainData: Pointer to the plaintext buffer
00615   * @param  Timeout: Specify Timeout value
00616   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00617   *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
00618   * @retval HAL status
00619   */
00620 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
00621 {
00622   /* Re-initialize AES IP with proper parameters */
00623   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00624   {
00625     return HAL_ERROR;
00626   }
00627   hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
00628   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
00629   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00630   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00631   {
00632     return HAL_ERROR;
00633   }
00634
00635   return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
00636 }
00637
00638 /**
00639   * @brief  Encrypt pPlainData in AES ECB encryption mode using Interrupt,
00640   *         the cypher data are available in pCypherData.
00641   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00642   *         the configuration information for CRYP module
00643   * @param  pPlainData: Pointer to the plaintext buffer
00644   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00645   * @param  pCypherData: Pointer to the cyphertext buffer
00646   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00647   *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
00648   * @retval HAL status
00649   */
00650 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
00651 {
00652   /* Re-initialize AES IP with proper parameters */
00653   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00654   {
00655     return HAL_ERROR;
00656   }
00657   hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
00658   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
00659   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00660   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00661   {
00662     return HAL_ERROR;
00663   }
00664
00665   return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
00666 }
00667
00668 /**
00669   * @brief  Encrypt pPlainData in AES CBC encryption mode using Interrupt,
00670   *         the cypher data are available in pCypherData.
00671   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00672   *         the configuration information for CRYP module
00673   * @param  pPlainData: Pointer to the plaintext buffer
00674   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00675   * @param  pCypherData: Pointer to the cyphertext buffer
00676   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00677   *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
00678   * @retval HAL status
00679   */
00680 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
00681 {
00682   /* Re-initialize AES IP with proper parameters */
00683   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00684   {
00685     return HAL_ERROR;
00686   }
00687   hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
00688   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
00689   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00690   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00691   {
00692     return HAL_ERROR;
00693   }
00694
00695   return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
00696 }
00697
00698
00699 /**
00700   * @brief  Encrypt pPlainData in AES CTR encryption mode using Interrupt,
00701   *         the cypher data are available in pCypherData.
00702   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00703   *         the configuration information for CRYP module
00704   * @param  pPlainData: Pointer to the plaintext buffer
00705   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00706   * @param  pCypherData: Pointer to the cyphertext buffer
00707   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00708   *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
00709   * @retval HAL status
00710   */
00711 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
00712 {
00713   /* Re-initialize AES IP with proper parameters */
00714   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00715   {
00716     return HAL_ERROR;
00717   }
00718   hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
00719   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
00720   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00721   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00722   {
00723     return HAL_ERROR;
00724   }
00725
00726   return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
00727 }
00728
00729 /**
00730   * @brief  Decrypt pCypherData in AES ECB decryption mode using Interrupt,
00731   *         the decyphered data are available in pPlainData.
00732   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00733   *         the configuration information for CRYP module
00734   * @param  pCypherData: Pointer to the cyphertext buffer
00735   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00736   * @param  pPlainData: Pointer to the plaintext buffer.
00737   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00738   *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
00739   * @retval HAL status
00740   */
00741 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
00742 {
00743   /* Re-initialize AES IP with proper parameters */
00744   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00745   {
00746     return HAL_ERROR;
00747   }
00748   hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
00749   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
00750   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00751   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00752   {
00753     return HAL_ERROR;
00754   }
00755
00756   return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
00757 }
00758
00759 /**
00760   * @brief  Decrypt pCypherData in AES CBC decryption mode using Interrupt,
00761   *         the decyphered data are available in pPlainData.
00762   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00763   *         the configuration information for CRYP module
00764   * @param  pCypherData: Pointer to the cyphertext buffer
00765   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00766   * @param  pPlainData: Pointer to the plaintext buffer
00767   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00768   *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
00769   * @retval HAL status
00770   */
00771 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
00772 {
00773   /* Re-initialize AES IP with proper parameters */
00774   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00775   {
00776     return HAL_ERROR;
00777   }
00778   hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
00779   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
00780   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00781   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00782   {
00783     return HAL_ERROR;
00784   }
00785
00786   return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
00787 }
00788
00789 /**
00790   * @brief  Decrypt pCypherData in AES CTR decryption mode using Interrupt,
00791   *         the decyphered data are available in pPlainData.
00792   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00793   *         the configuration information for CRYP module
00794   * @param  pCypherData: Pointer to the cyphertext buffer
00795   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00796   * @param  pPlainData: Pointer to the plaintext buffer
00797   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00798   *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
00799   * @retval HAL status
00800   */
00801 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
00802 {
00803   /* Re-initialize AES IP with proper parameters */
00804   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00805   {
00806     return HAL_ERROR;
00807   }
00808   hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
00809   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
00810   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00811   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00812   {
00813     return HAL_ERROR;
00814   }
00815
00816   return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
00817 }
00818
00819 /**
00820   * @brief  Encrypt pPlainData in AES ECB encryption mode using DMA,
00821   *         the cypher data are available in pCypherData.
00822   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00823   *         the configuration information for CRYP module
00824   * @param  pPlainData: Pointer to the plaintext buffer
00825   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00826   * @param  pCypherData: Pointer to the cyphertext buffer
00827   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00828   *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
00829   * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
00830   * @retval HAL status
00831   */
00832 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
00833 {
00834   /* Re-initialize AES IP with proper parameters */
00835   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00836   {
00837     return HAL_ERROR;
00838   }
00839   hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
00840   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
00841   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00842   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00843   {
00844     return HAL_ERROR;
00845   }
00846
00847   return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
00848 }
00849
00850
00851
00852 /**
00853   * @brief  Encrypt pPlainData in AES CBC encryption mode using DMA,
00854   *         the cypher data are available in pCypherData.
00855   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00856   *         the configuration information for CRYP module
00857   * @param  pPlainData: Pointer to the plaintext buffer
00858   * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
00859   * @param  pCypherData: Pointer to the cyphertext buffer
00860   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00861   *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
00862   * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
00863   * @retval HAL status
00864   */
00865 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
00866 {
00867   /* Re-initialize AES IP with proper parameters */
00868   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00869   {
00870     return HAL_ERROR;
00871   }
00872   hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
00873   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
00874   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00875   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00876   {
00877     return HAL_ERROR;
00878   }
00879
00880   return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
00881 }
00882
00883 /**
00884   * @brief  Encrypt pPlainData in AES CTR encryption mode using DMA,
00885   *         the cypher data are available in pCypherData.
00886   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00887   *         the configuration information for CRYP module
00888   * @param  pPlainData: Pointer to the plaintext buffer
00889   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00890   * @param  pCypherData: Pointer to the cyphertext buffer.
00891   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00892   *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
00893   * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
00894   * @retval HAL status
00895   */
00896 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
00897 {
00898   /* Re-initialize AES IP with proper parameters */
00899   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00900   {
00901     return HAL_ERROR;
00902   }
00903   hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
00904   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
00905   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00906   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00907   {
00908     return HAL_ERROR;
00909   }
00910
00911   return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
00912 }
00913
00914 /**
00915   * @brief  Decrypt pCypherData in AES ECB decryption mode using DMA,
00916   *         the decyphered data are available in pPlainData.
00917   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00918   *         the configuration information for CRYP module
00919   * @param  pCypherData: Pointer to the cyphertext buffer
00920   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00921   * @param  pPlainData: Pointer to the plaintext buffer
00922   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00923   *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
00924   * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
00925   * @retval HAL status
00926   */
00927 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
00928 {
00929   /* Re-initialize AES IP with proper parameters */
00930   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00931   {
00932     return HAL_ERROR;
00933   }
00934   hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
00935   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
00936   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00937   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00938   {
00939     return HAL_ERROR;
00940   }
00941
00942   return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
00943 }
00944
00945 /**
00946   * @brief  Decrypt pCypherData in AES CBC decryption mode using DMA,
00947   *         the decyphered data are available in pPlainData.
00948   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00949   *         the configuration information for CRYP module
00950   * @param  pCypherData: Pointer to the cyphertext buffer
00951   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00952   * @param  pPlainData: Pointer to the plaintext buffer
00953   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00954   *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
00955   * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
00956   * @retval HAL status
00957   */
00958 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
00959 {
00960   /* Re-initialize AES IP with proper parameters */
00961   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00962   {
00963     return HAL_ERROR;
00964   }
00965   hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
00966   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
00967   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00968   if (HAL_CRYP_Init(hcryp) != HAL_OK)
00969   {
00970     return HAL_ERROR;
00971   }
00972
00973   return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
00974 }
00975
00976 /**
00977   * @brief  Decrypt pCypherData in AES CTR decryption mode using DMA,
00978   *         the decyphered data are available in pPlainData.
00979   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00980   *         the configuration information for CRYP module
00981   * @param  pCypherData: Pointer to the cyphertext buffer
00982   * @param  Size: Length of the plaintext buffer in bytes, must be a multiple of 16.
00983   * @param  pPlainData: Pointer to the plaintext buffer
00984   * @note   This API is provided only to maintain compatibility with legacy software. Users should directly
00985   *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
00986   * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
00987   * @retval HAL status
00988   */
00989 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
00990 {
00991   /* Re-initialize AES IP with proper parameters */
00992   if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
00993   {
00994     return HAL_ERROR;
00995   }
00996   hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
00997   hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
00998   hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
00999   if (HAL_CRYP_Init(hcryp) != HAL_OK)
01000   {
01001     return HAL_ERROR;
01002   }
01003
01004   return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
01005 }
01006
01007
01008 /**
01009   * @}
01010   */
01011
01012 /** @defgroup CRYP_Exported_Functions_Group3 Callback functions
01013  *  @brief   Callback functions.
01014  *
01015 @verbatim
01016   ==============================================================================
01017                       ##### Callback functions  #####
01018   ==============================================================================
01019     [..]  This section provides Interruption and DMA callback functions:
01020       (+) DMA Input data transfer complete
01021       (+) DMA Output data transfer complete
01022       (+) DMA or Interrupt error
01023
01024 @endverbatim
01025   * @{
01026   */
01027
01028 /**
01029   * @brief  CRYP error callback.
01030   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01031   *         the configuration information for CRYP module
01032   * @retval None
01033   */
01034 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
01035 {
01036   /* Prevent unused argument(s) compilation warning */
01037   UNUSED(hcryp);
01038
01039   /* NOTE : This function should not be modified; when the callback is needed,
01040             the HAL_CRYP_ErrorCallback can be implemented in the user file
01041    */
01042 }
01043
01044 /**
01045   * @brief  Input DMA transfer complete callback.
01046   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01047   *         the configuration information for CRYP module
01048   * @retval None
01049   */
01050 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
01051 {
01052   /* Prevent unused argument(s) compilation warning */
01053   UNUSED(hcryp);
01054
01055   /* NOTE : This function should not be modified; when the callback is needed,
01056             the HAL_CRYP_InCpltCallback can be implemented in the user file
01057    */
01058 }
01059
01060 /**
01061   * @brief  Output DMA transfer complete callback.
01062   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01063   *         the configuration information for CRYP module
01064   * @retval None
01065   */
01066 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
01067 {
01068   /* Prevent unused argument(s) compilation warning */
01069   UNUSED(hcryp);
01070
01071   /* NOTE : This function should not be modified; when the callback is needed,
01072             the HAL_CRYP_OutCpltCallback can be implemented in the user file
01073    */
01074 }
01075
01076 /**
01077   * @}
01078   */
01079
01080 /** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
01081  *  @brief   AES IRQ handler.
01082  *
01083 @verbatim
01084   ==============================================================================
01085                 ##### AES IRQ handler management #####
01086   ==============================================================================
01087 [..]  This section provides AES IRQ handler function.
01088
01089 @endverbatim
01090   * @{
01091   */
01092
01093 /**
01094   * @brief  Handle AES interrupt request.
01095   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01096   *         the configuration information for CRYP module
01097   * @retval None
01098   */
01099 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
01100 {
01101   /* Check if error occurred */
01102   if (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_ERRIE) != RESET)
01103   {
01104     /* If Write Error occurred */
01105     if (__HAL_CRYP_GET_FLAG(CRYP_IT_WRERR) != RESET)
01106     {
01107       hcryp->ErrorCode |= HAL_CRYP_WRITE_ERROR;
01108       hcryp->State = HAL_CRYP_STATE_ERROR;
01109     }
01110     /* If Read Error occurred */
01111     if (__HAL_CRYP_GET_FLAG(CRYP_IT_RDERR) != RESET)
01112     {
01113       hcryp->ErrorCode |= HAL_CRYP_READ_ERROR;
01114       hcryp->State = HAL_CRYP_STATE_ERROR;
01115     }
01116
01117     /* If an error has been reported */
01118     if (hcryp->State == HAL_CRYP_STATE_ERROR)
01119     {
01120       /* Disable Error and Computation Complete Interrupts */
01121       __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
01122       /* Clear all Interrupt flags */
01123       __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR|CRYP_CCF_CLEAR);
01124
01125       /* Process Unlocked */
01126       __HAL_UNLOCK(hcryp);
01127
01128       HAL_CRYP_ErrorCallback(hcryp);
01129
01130       return;
01131     }
01132   }
01133
01134   /* Check if computation complete interrupt is enabled
01135      and if the computation complete flag is raised */
01136   if((__HAL_CRYP_GET_FLAG(CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_CCFIE) != RESET))
01137   {
01138     if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
01139      || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
01140     {
01141      /* To ensure proper suspension requests management, CCF flag
01142         is reset in CRYP_AES_Auth_IT() according to the current
01143         phase under handling */
01144       CRYP_AES_Auth_IT(hcryp);
01145     }
01146     else
01147     {
01148       /* Clear Computation Complete Flag */
01149       __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
01150       CRYP_AES_IT(hcryp);
01151     }
01152   }
01153 }
01154
01155 /**
01156   * @}
01157   */
01158
01159 /** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions
01160  *  @brief   Peripheral State functions.
01161  *
01162 @verbatim
01163   ==============================================================================
01164                       ##### Peripheral State functions #####
01165   ==============================================================================
01166     [..]
01167     This subsection permits to get in run-time the status of the peripheral.
01168
01169 @endverbatim
01170   * @{
01171   */
01172
01173 /**
01174   * @brief  Return the CRYP handle state.
01175   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01176   *         the configuration information for CRYP module
01177   * @retval HAL state
01178   */
01179 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
01180 {
01181   /* Return CRYP handle state */
01182   return hcryp->State;
01183 }
01184
01185 /**
01186   * @brief  Return the CRYP peripheral error.
01187   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01188   *         the configuration information for CRYP module
01189   * @note   The returned error is a bit-map combination of possible errors
01190   * @retval Error bit-map
01191   */
01192 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
01193 {
01194   return hcryp->ErrorCode;
01195 }
01196
01197 /**
01198   * @}
01199   */
01200
01201 /**
01202   * @}
01203   */
01204
01205 /** @addtogroup CRYP_Private_Functions
01206   * @{
01207   */
01208
01209
01210 /**
01211   * @brief  Write the Key in KeyRx registers.
01212   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01213   *         the configuration information for CRYP module
01214   * @retval None
01215   */
01216 static HAL_StatusTypeDef  CRYP_SetKey(CRYP_HandleTypeDef *hcryp)
01217 {
01218   uint32_t keyaddr = 0x0;
01219
01220   if ((uint32_t)(hcryp->Init.pKey == NULL))
01221   {
01222     return HAL_ERROR;
01223   }
01224
01225
01226   keyaddr = (uint32_t)(hcryp->Init.pKey);
01227
01228   if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
01229   {
01230     hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
01231     keyaddr+=4;
01232     hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
01233     keyaddr+=4;
01234     hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
01235     keyaddr+=4;
01236     hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
01237     keyaddr+=4;
01238   }
01239
01240   hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
01241   keyaddr+=4;
01242   hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
01243   keyaddr+=4;
01244   hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
01245   keyaddr+=4;
01246   hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
01247
01248   return HAL_OK;
01249 }
01250
01251 /**
01252   * @brief  Write the InitVector/InitCounter in IVRx registers.
01253   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01254   *         the configuration information for CRYP module
01255   * @retval None
01256   */
01257 static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp)
01258 {
01259   uint32_t ivaddr = 0x0;
01260
01261   if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
01262   {
01263     hcryp->Instance->IVR3 = 0;
01264     hcryp->Instance->IVR2 = 0;
01265     hcryp->Instance->IVR1 = 0;
01266     hcryp->Instance->IVR0 = 0;
01267   }
01268   else
01269   {
01270     if (hcryp->Init.pInitVect == NULL)
01271     {
01272       return HAL_ERROR;
01273     }
01274
01275     ivaddr = (uint32_t)(hcryp->Init.pInitVect);
01276
01277     hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
01278     ivaddr+=4;
01279     hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
01280     ivaddr+=4;
01281     hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
01282     ivaddr+=4;
01283     hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
01284   }
01285   return HAL_OK;
01286 }
01287
01288
01289
01290 /**
01291   * @brief  Handle CRYP block input/output data handling under interruption.
01292   * @note   The function is called under interruption only, once
01293   *         interruptions have been enabled by HAL_CRYPEx_AES_IT().
01294   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01295   *         the configuration information for CRYP module.
01296   * @retval HAL status
01297   */
01298 static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
01299 {
01300   uint32_t inputaddr = 0;
01301   uint32_t outputaddr = 0;
01302
01303   if(hcryp->State == HAL_CRYP_STATE_BUSY)
01304   {
01305     if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
01306     {
01307       /* Get the output data address */
01308       outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
01309
01310       /* Read the last available output block from the Data Output Register */
01311       *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
01312       outputaddr+=4;
01313       *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
01314       outputaddr+=4;
01315       *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
01316       outputaddr+=4;
01317       *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
01318       hcryp->pCrypOutBuffPtr += 16;
01319       hcryp->CrypOutCount -= 16;
01320
01321     }
01322     else
01323     {
01324       /* Read the derived key from the Key registers */
01325       if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
01326       {
01327         *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);
01328         outputaddr+=4;
01329         *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);
01330         outputaddr+=4;
01331         *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);
01332         outputaddr+=4;
01333         *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);
01334         outputaddr+=4;
01335       }
01336
01337         *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);
01338         outputaddr+=4;
01339         *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);
01340         outputaddr+=4;
01341         *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);
01342         outputaddr+=4;
01343         *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);
01344     }
01345
01346     /* In case of ciphering or deciphering, check if all output text has been retrieved;
01347        In case of key derivation, stop right there */
01348     if ((hcryp->CrypOutCount == 0) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION))
01349     {
01350       /* Disable Computation Complete Flag and Errors Interrupts */
01351       __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
01352       /* Change the CRYP state */
01353       hcryp->State = HAL_CRYP_STATE_READY;
01354
01355      /* Process Unlocked */
01356       __HAL_UNLOCK(hcryp);
01357
01358       /* Call computation complete callback */
01359       HAL_CRYPEx_ComputationCpltCallback(hcryp);
01360
01361       return HAL_OK;
01362     }
01363     /* If suspension flag has been raised, suspend processing */
01364     else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
01365     {
01366       /* reset ModeSuspend */
01367       hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
01368
01369       /* Disable Computation Complete Flag and Errors Interrupts */
01370       __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
01371       /* Change the CRYP state */
01372       hcryp->State = HAL_CRYP_STATE_SUSPENDED;
01373
01374      /* Process Unlocked */
01375       __HAL_UNLOCK(hcryp);
01376
01377       return HAL_OK;
01378     }
01379     else /* Process the rest of input data */
01380     {
01381       /* Get the Intput data address */
01382       inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01383
01384       /* Increment/decrement instance pointer/counter */
01385       hcryp->pCrypInBuffPtr += 16;
01386       hcryp->CrypInCount -= 16;
01387
01388       /* Write the next input block in the Data Input register */
01389       hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01390       inputaddr+=4;
01391       hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01392       inputaddr+=4;
01393       hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
01394       inputaddr+=4;
01395       hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01396
01397       return HAL_OK;
01398     }
01399   }
01400   else
01401   {
01402     return HAL_BUSY;
01403   }
01404 }
01405
01406
01407
01408
01409 /**
01410   * @}
01411   */
01412
01413
01414
01415 /**
01416   * @}
01417   */
01418
01419 /**
01420   * @}
01421   */
01422
01423 #endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx) */
01424
01425 #endif /* HAL_CRYP_MODULE_ENABLED */
01426
01427 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cryp.h Source File

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stm32l4xx_hal_cryp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_cryp.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of CRYP HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_CRYP_H
00040 #define __STM32L4xx_HAL_CRYP_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32l4xx_hal_def.h"
00050
00051 /** @addtogroup STM32L4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup CRYP
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup CRYP_Exported_Types CRYP Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  CRYP Configuration Structure definition
00066   */
00067 typedef struct
00068 {
00069   uint32_t DataType;       /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
00070                              This parameter can be a value of @ref CRYP_Data_Type */
00071
00072   uint32_t KeySize;        /*!< 128 or 256-bit key length.
00073                              This parameter can be a value of @ref CRYP_Key_Size */
00074
00075   uint32_t OperatingMode;  /*!< AES operating mode.
00076                              This parameter can be a value of @ref CRYP_AES_OperatingMode */
00077
00078   uint32_t ChainingMode;   /*!< AES chaining mode.
00079                              This parameter can be a value of @ref CRYP_AES_ChainingMode */
00080
00081   uint32_t KeyWriteFlag;   /*!< Allows to bypass or not key write-up before decryption.
00082                              This parameter can be a value of @ref CRYP_Key_Write */
00083
00084   uint32_t GCMCMACPhase;   /*!< Indicates the processing phase of the Galois Counter Mode (GCM),
00085                              Galois Message Authentication Code (GMAC) or Cipher Message
00086                              Authentication Code (CMAC) mode.
00087                              This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */
00088
00089   uint8_t* pKey;           /*!< Encryption/Decryption Key */
00090
00091   uint8_t* pInitVect;      /*!< Initialization Vector used for CTR, CBC, GCM/GMAC and CMAC modes */
00092
00093   uint8_t* Header;         /*!< Header used in GCM/GMAC and CMAC modes */
00094
00095   uint64_t HeaderSize;     /*!< Header size in bytes */
00096
00097 }CRYP_InitTypeDef;
00098
00099 /**
00100   * @brief HAL CRYP State structures definition
00101   */
00102 typedef enum
00103 {
00104   HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */
00105   HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */
00106   HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */
00107   HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */
00108   HAL_CRYP_STATE_ERROR             = 0x04,  /*!< CRYP error state                      */
00109   HAL_CRYP_STATE_SUSPENDED         = 0x05   /*!< CRYP suspended                        */
00110 }HAL_CRYP_STATETypeDef;
00111
00112 /**
00113   * @brief HAL CRYP phase structures definition
00114   */
00115 typedef enum
00116 {
00117   HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization.     */
00118   HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase           */
00119   HAL_CRYP_PHASE_START             = 0x03,    /*!< CRYP peripheral has been initialized but GCM/GMAC/CMAC
00120                                                    initialization phase has not started             */
00121   HAL_CRYP_PHASE_INIT_OVER         = 0x04,    /*!< GCM/GMAC/CMAC init phase has been carried out    */
00122   HAL_CRYP_PHASE_HEADER_OVER       = 0x05,    /*!< GCM/GMAC/CMAC header phase has been carried out  */
00123   HAL_CRYP_PHASE_PAYLOAD_OVER      = 0x06,    /*!< GCM/GMAC/CMAC payload phase has been carried out */
00124   HAL_CRYP_PHASE_FINAL_OVER        = 0x07,    /*!< GCM/GMAC/CMAC final phase has been carried out   */
00125   HAL_CRYP_PHASE_HEADER_SUSPENDED  = 0x08,    /*!< GCM/GMAC/CMAC header phase has been suspended    */
00126   HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09,    /*!< GCM/GMAC payload phase has been suspended        */
00127   HAL_CRYP_PHASE_NOT_USED          = 0x0a     /*!< Phase is irrelevant to the current chaining mode */
00128 }HAL_PhaseTypeDef;
00129
00130 /**
00131   * @brief HAL CRYP mode suspend definitions
00132   */
00133 typedef enum
00134 {
00135   HAL_CRYP_SUSPEND_NONE            = 0x00,    /*!< CRYP peripheral suspension not requested */
00136   HAL_CRYP_SUSPEND                 = 0x01     /*!< CRYP peripheral suspension requested     */
00137 }HAL_SuspendTypeDef;
00138
00139
00140 /**
00141   * @brief  HAL CRYP Error Codes definition
00142   */
00143 #define HAL_CRYP_ERROR_NONE      ((uint32_t)0x00000000)  /*!< No error        */
00144 #define HAL_CRYP_WRITE_ERROR     ((uint32_t)0x00000001)  /*!< Write error     */
00145 #define HAL_CRYP_READ_ERROR      ((uint32_t)0x00000002)  /*!< Read error      */
00146 #define HAL_CRYP_DMA_ERROR       ((uint32_t)0x00000004)  /*!< DMA error       */
00147 #define HAL_CRYP_BUSY_ERROR      ((uint32_t)0x00000008)  /*!< Busy flag error */
00148
00149 /**
00150   * @brief  CRYP handle Structure definition
00151   */
00152 typedef struct
00153 {
00154       AES_TypeDef              *Instance;        /*!< Register base address        */
00155
00156       CRYP_InitTypeDef         Init;             /*!< CRYP initialization parameters */
00157
00158       uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */
00159
00160       uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */
00161
00162       uint32_t                 CrypInCount;      /*!< Input data size in bytes or, after suspension, the remaining
00163                                                        number of bytes to process */
00164
00165       uint32_t                 CrypOutCount;     /*!< Output data size in bytes */
00166
00167       HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral processing phase for GCM, GMAC or CMAC modes.
00168                                                      Indicates the last phase carried out to ease
00169                                                      phase transitions  */
00170
00171       DMA_HandleTypeDef        *hdmain;          /*!< CRYP peripheral Input DMA handle parameters */
00172
00173       DMA_HandleTypeDef        *hdmaout;         /*!< CRYP peripheral Output DMA handle parameters */
00174
00175       HAL_LockTypeDef          Lock;             /*!< CRYP locking object */
00176
00177    __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
00178
00179     __IO uint32_t              ErrorCode;        /*!< CRYP peripheral error code */
00180
00181      HAL_SuspendTypeDef        SuspendRequest;   /*!< CRYP peripheral suspension request flag */
00182 }CRYP_HandleTypeDef;
00183
00184 /**
00185   * @}
00186   */
00187
00188
00189 /* Exported constants --------------------------------------------------------*/
00190 /** @defgroup CRYP_Exported_Constants CRYP Exported Constants
00191   * @{
00192   */
00193
00194 /** @defgroup CRYP_Key_Size  Key size selection
00195   * @{
00196   */
00197 #define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000)  /*!< 128-bit long key */
00198 #define CRYP_KEYSIZE_256B         AES_CR_KEYSIZE          /*!< 256-bit long key */
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup CRYP_Data_Type  AES Data Type selection
00204   * @{
00205   */
00206 #define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)  /*!< 32-bit data type (no swapping)        */
00207 #define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0       /*!< 16-bit data type (half-word swapping) */
00208 #define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1       /*!< 8-bit data type (byte swapping)       */
00209 #define CRYP_DATATYPE_1B          AES_CR_DATATYPE         /*!< 1-bit data type (bit swapping)        */
00210 /**
00211   * @}
00212   */
00213
00214  /** @defgroup CRYP_AES_State  AES Enable state
00215   * @{
00216   */
00217 #define CRYP_AES_DISABLE                 ((uint32_t)0x00000000)   /*!< Disable AES */
00218 #define CRYP_AES_ENABLE                   AES_CR_EN               /*!< Enable AES  */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup CRYP_AES_OperatingMode AES operating mode
00224   * @{
00225   */
00226 #define CRYP_ALGOMODE_ENCRYPT                   ((uint32_t)0x00000000)  /*!< Encryption mode                            */
00227 #define CRYP_ALGOMODE_KEYDERIVATION             AES_CR_MODE_0           /*!< Key derivation mode                        */
00228 #define CRYP_ALGOMODE_DECRYPT                   AES_CR_MODE_1           /*!< Decryption                                 */
00229 #define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE             /*!< Key derivation and decryption              */
00230 #define CRYP_ALGOMODE_TAG_GENERATION            ((uint32_t)0x00000000)  /*!< GMAC or CMAC authentication tag generation */
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup CRYP_AES_ChainingMode AES chaining mode
00236   * @{
00237   */
00238 #define CRYP_CHAINMODE_AES_ECB            ((uint32_t)0x00000000)            /*!< Electronic codebook chaining algorithm                   */
00239 #define CRYP_CHAINMODE_AES_CBC            AES_CR_CHMOD_0                    /*!< Cipher block chaining algorithm                          */
00240 #define CRYP_CHAINMODE_AES_CTR            AES_CR_CHMOD_1                    /*!< Counter mode chaining algorithm                          */
00241 #define CRYP_CHAINMODE_AES_GCM_GMAC       (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
00242 #define CRYP_CHAINMODE_AES_CMAC           AES_CR_CHMOD_2                    /*!< Cipher message authentication code                       */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup CRYP_Key_Write AES decryption key write-up flag
00248   * @{
00249   */
00250 #define CRYP_KEY_WRITE_ENABLE            ((uint32_t)0x00000000)  /*!< Enable decryption key writing  */
00251 #define CRYP_KEY_WRITE_DISABLE           ((uint32_t)0x00000001)  /*!< Disable decryption key writing */
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup CRYP_DMAIN DMA Input phase management enable state
00257   * @{
00258   */
00259 #define CRYP_DMAIN_DISABLE             ((uint32_t)0x00000000)    /*!< Disable DMA Input phase management */
00260 #define CRYP_DMAIN_ENABLE              AES_CR_DMAINEN            /*!< Enable DMA Input phase management  */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup CRYP_DMAOUT DMA Output phase management enable state
00266   * @{
00267   */
00268 #define CRYP_DMAOUT_DISABLE             ((uint32_t)0x00000000)   /*!< Disable DMA Output phase management */
00269 #define CRYP_DMAOUT_ENABLE              AES_CR_DMAOUTEN          /*!< Enable DMA Output phase management  */
00270 /**
00271   * @}
00272   */
00273
00274
00275 /** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CMAC processing phase selection
00276   * @{
00277   */
00278 #define CRYP_GCM_INIT_PHASE             ((uint32_t)0x00000000)  /*!< GCM/GMAC init phase           */
00279 #define CRYP_GCMCMAC_HEADER_PHASE       AES_CR_GCMPH_0          /*!< GCM/GMAC or CMAC header phase */
00280 #define CRYP_GCM_PAYLOAD_PHASE          AES_CR_GCMPH_1          /*!< GCM payload phaset            */
00281 #define CRYP_GCMCMAC_FINAL_PHASE        AES_CR_GCMPH            /*!< GCM/GMAC or CMAC final phase  */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup CRYP_Flags   AES status flags
00287   * @{
00288   */
00289
00290 #define CRYP_FLAG_BUSY    AES_SR_BUSY   /*!< GCM process suspension forbidden */
00291 #define CRYP_FLAG_WRERR   AES_SR_WRERR  /*!< Write Error                      */
00292 #define CRYP_FLAG_RDERR   AES_SR_RDERR  /*!< Read error                       */
00293 #define CRYP_FLAG_CCF     AES_SR_CCF    /*!< Computation completed            */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup CRYP_Clear_Flags   AES clearing flags
00299   * @{
00300   */
00301
00302 #define CRYP_CCF_CLEAR    AES_CR_CCFC   /*!< Computation Complete Flag Clear */
00303 #define CRYP_ERR_CLEAR    AES_CR_ERRC   /*!< Error Flag Clear                */
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits
00309   * @{
00310   */
00311 #define CRYP_IT_CCFIE                         AES_CR_CCFIE /*!< Computation Complete interrupt enable */
00312 #define CRYP_IT_ERRIE                         AES_CR_ERRIE /*!< Error interrupt enable                */
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup CRYP_Interrupts_Flags   AES Interrupts flags
00318   * @{
00319   */
00320 #define CRYP_IT_WRERR   AES_SR_WRERR  /*!< Write Error           */
00321 #define CRYP_IT_RDERR   AES_SR_RDERR  /*!< Read Error            */
00322 #define CRYP_IT_CCF     AES_SR_CCF    /*!< Computation completed */
00323 /**
00324   * @}
00325   */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /* Exported macros -----------------------------------------------------------*/
00332 /** @defgroup CRYP_Exported_Macros CRYP Exported Macros
00333   * @{
00334   */
00335
00336 /** @brief Reset CRYP handle state.
00337   * @param  __HANDLE__: specifies the CRYP handle.
00338   * @retval None
00339   */
00340 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
00341
00342 /**
00343   * @brief  Enable the CRYP AES peripheral.
00344   * @retval None
00345   */
00346 #define __HAL_CRYP_ENABLE()  (AES->CR |=  AES_CR_EN)
00347
00348 /**
00349   * @brief  Disable the CRYP AES peripheral.
00350   * @retval None
00351   */
00352 #define __HAL_CRYP_DISABLE() (AES->CR &=  ~AES_CR_EN)
00353
00354 /**
00355   * @brief  Set the algorithm operating mode.
00356   * @param  __OPERATING_MODE__: specifies the operating mode
00357   *          This parameter can be one of the following values:
00358   *            @arg @ref CRYP_ALGOMODE_ENCRYPT encryption
00359   *            @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation
00360   *            @arg @ref CRYP_ALGOMODE_DECRYPT decryption
00361   *            @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption
00362   * @retval None
00363   */
00364 #define __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))
00365
00366
00367 /**
00368   * @brief  Set the algorithm chaining mode.
00369   * @param  __CHAINING_MODE__: specifies the chaining mode
00370   *          This parameter can be one of the following values:
00371   *            @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook
00372   *            @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
00373   *            @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode
00374   *            @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code
00375   *            @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code
00376   * @retval None
00377   */
00378 #define __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
00379
00380
00381
00382 /** @brief  Check whether the specified CRYP status flag is set or not.
00383   * @param  __FLAG__: specifies the flag to check.
00384   *         This parameter can be one of the following values:
00385   *            @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
00386   *            @arg @ref CRYP_IT_WRERR Write Error
00387   *            @arg @ref CRYP_IT_RDERR Read Error
00388   *            @arg @ref CRYP_IT_CCF Computation Complete
00389   * @retval The state of __FLAG__ (TRUE or FALSE).
00390   */
00391 #define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
00392
00393
00394 /** @brief  Clear the CRYP pending status flag.
00395   * @param  __FLAG__: specifies the flag to clear.
00396   *         This parameter can be one of the following values:
00397   *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
00398   *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
00399   * @retval None
00400   */
00401 #define __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))
00402
00403
00404
00405 /** @brief  Check whether the specified CRYP interrupt source is enabled or not.
00406   * @param __INTERRUPT__: CRYP interrupt source to check
00407   *         This parameter can be one of the following values:
00408   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00409   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00410   * @retval State of interruption (TRUE or FALSE).
00411   */
00412 #define __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))
00413
00414
00415 /** @brief  Check whether the specified CRYP interrupt is set or not.
00416   * @param  __INTERRUPT__: specifies the interrupt to check.
00417   *         This parameter can be one of the following values:
00418   *            @arg @ref CRYP_IT_WRERR Write Error
00419   *            @arg @ref CRYP_IT_RDERR Read Error
00420   *            @arg @ref CRYP_IT_CCF  Computation Complete
00421   * @retval The state of __INTERRUPT__ (TRUE or FALSE).
00422   */
00423 #define __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00424
00425
00426
00427 /** @brief  Clear the CRYP pending interrupt.
00428   * @param  __INTERRUPT__: specifies the IT to clear.
00429   *         This parameter can be one of the following values:
00430   *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
00431   *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
00432   * @retval None
00433   */
00434 #define __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))
00435
00436
00437 /**
00438   * @brief  Enable the CRYP interrupt.
00439   * @param  __INTERRUPT__: CRYP Interrupt.
00440   *         This parameter can be one of the following values:
00441   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00442   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00443   * @retval None
00444   */
00445 #define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
00446
00447
00448 /**
00449   * @brief  Disable the CRYP interrupt.
00450   * @param  __INTERRUPT__: CRYP Interrupt.
00451   *         This parameter can be one of the following values:
00452   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00453   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00454   * @retval None
00455   */
00456 #define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
00457
00458 /**
00459   * @}
00460   */
00461
00462 /* Private macros --------------------------------------------------------*/
00463 /** @addtogroup  CRYP_Private_Macros   CRYP Private Macros
00464   * @{
00465   */
00466
00467 /**
00468   * @brief Verify the key size length.
00469   * @param __KEYSIZE__: Ciphering/deciphering algorithm key size.
00470   * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
00471   */
00472 #define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \
00473                                        ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
00474
00475 /**
00476   * @brief Verify the input data type.
00477   * @param __DATATYPE__: Ciphering/deciphering algorithm input data type.
00478   * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
00479   */
00480 #define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
00481                                         ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
00482                                         ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \
00483                                         ((__DATATYPE__) == CRYP_DATATYPE_1B))
00484
00485 /**
00486   * @brief Verify the CRYP AES IP running mode.
00487   * @param __MODE__: CRYP AES IP running mode.
00488   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00489   */
00490 #define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
00491                                ((__MODE__) == CRYP_AES_ENABLE))
00492
00493 /**
00494   * @brief Verify the selected CRYP algorithm.
00495   * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
00496   * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
00497   */
00498 #define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT)        || \
00499                                         ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION)  || \
00500                                         ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT)        || \
00501                                         ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \
00502                                         ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))
00503
00504 /**
00505   * @brief Verify the selected CRYP chaining algorithm.
00506   * @param __CHAINMODE__: Selected CRYP chaining algorithm.
00507   * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
00508   */
00509 #define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB)     || \
00510                                          ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC)      || \
00511                                          ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR)      || \
00512                                          ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
00513                                          ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))
00514
00515 /**
00516   * @brief Verify the deciphering key write option.
00517   * @param __WRITE__: deciphering key write option.
00518   * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
00519   */
00520 #define IS_CRYP_WRITE(__WRITE__)   (((__WRITE__) == CRYP_KEY_WRITE_ENABLE)      || \
00521                                     ((__WRITE__) == CRYP_KEY_WRITE_DISABLE))
00522
00523 /**
00524   * @brief Verify the CRYP input data DMA mode.
00525   * @param __MODE__: CRYP input data DMA mode.
00526   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00527   */
00528 #define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
00529                                  ((__MODE__) == CRYP_DMAIN_ENABLE))
00530
00531 /**
00532   * @brief Verify the CRYP output data DMA mode.
00533   * @param __MODE__: CRYP output data DMA mode.
00534   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00535   */
00536 #define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
00537                                   ((__MODE__) == CRYP_DMAOUT_ENABLE))
00538
00539 /**
00540   * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
00541   * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase.
00542   * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
00543   */
00544 #define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE)       || \
00545                                           ((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \
00546                                           ((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE)    || \
00547                                           ((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE))
00548
00549 /**
00550   * @}
00551   */
00552
00553 /* Include CRYP HAL Extended module */
00554 #include "stm32l4xx_hal_cryp_ex.h"
00555
00556 /* Exported functions --------------------------------------------------------*/
00557 /** @addtogroup CRYP_Exported_Functions CRYP Exported Functions
00558   * @{
00559   */
00560
00561 /** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
00562   * @{
00563   */
00564
00565 /* Initialization/de-initialization functions  ********************************/
00566 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
00567 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
00568
00569 /* MSP initialization/de-initialization functions  ****************************/
00570 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
00571 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
00572
00573 /**
00574   * @}
00575   */
00576
00577 /** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions
00578   * @{
00579   */
00580
00581 /* AES encryption/decryption processing functions  ****************************/
00582
00583 /* AES encryption/decryption using polling  ***********************************/
00584 HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00585 HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00586 HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00587 HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00588 HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
00589 HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
00590
00591 /* AES encryption/decryption using interrupt  *********************************/
00592 HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00593 HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00594 HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00595 HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00596 HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00597 HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00598
00599 /* AES encryption/decryption using DMA  ***************************************/
00600 HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00601 HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00602 HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00603 HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00604 HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
00605 HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
00606
00607 /**
00608   * @}
00609   */
00610
00611 /** @addtogroup CRYP_Exported_Functions_Group3 Callback functions
00612   * @{
00613   */
00614 /* CallBack functions  ********************************************************/
00615 void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
00616 void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
00617 void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
00618
00619 /**
00620   * @}
00621   */
00622
00623 /** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
00624   * @{
00625   */
00626
00627 /* AES interrupt handling function  *******************************************/
00628 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
00629
00630 /**
00631   * @}
00632   */
00633
00634 /** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions
00635   * @{
00636   */
00637
00638 /* Peripheral State functions  ************************************************/
00639 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
00640 uint32_t              HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
00641
00642 /**
00643   * @}
00644   */
00645
00646 /**
00647   * @}
00648   */
00649
00650 /**
00651   * @}
00652   */
00653
00654 /**
00655   * @}
00656   */
00657
00658 #endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx) */
00659
00660 #ifdef __cplusplus
00661 }
00662 #endif
00663
00664 #endif /* __STM32L4xx_HAL_CRYP_H */
00665
00666 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cryp_ex.c Source File

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stm32l4xx_hal_cryp_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_cryp_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   CRYPEx HAL module driver.
00008   *          This file provides firmware functions to manage the extended
00009   *          functionalities of the Cryptography (CRYP) peripheral.
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00015   *
00016   * Redistribution and use in source and binary forms, with or without modification,
00017   * are permitted provided that the following conditions are met:
00018   *   1. Redistributions of source code must retain the above copyright notice,
00019   *      this list of conditions and the following disclaimer.
00020   *   2. Redistributions in binary form must reproduce the above copyright notice,
00021   *      this list of conditions and the following disclaimer in the documentation
00022   *      and/or other materials provided with the distribution.
00023   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00024   *      may be used to endorse or promote products derived from this software
00025   *      without specific prior written permission.
00026   *
00027   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00028   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00029   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00030   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00031   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00032   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00033   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00034   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00035   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00036   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00037   *
00038   ******************************************************************************
00039   */
00040
00041 /* Includes ------------------------------------------------------------------*/
00042 #include "stm32l4xx_hal.h"
00043
00044 #ifdef HAL_CRYP_MODULE_ENABLED
00045
00046 #if defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx)
00047
00048 /** @addtogroup STM32L4xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @defgroup CRYPEx CRYPEx
00053   * @brief CRYP Extended HAL module driver
00054   * @{
00055   */
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
00060   * @{
00061   */
00062 #define CRYP_CCF_TIMEOUTVALUE                      22000  /*!< CCF flag raising time-out value */
00063 #define CRYP_BUSY_TIMEOUTVALUE                     22000  /*!< BUSY flag reset time-out value  */
00064
00065 #define CRYP_POLLING_OFF                             0x0  /*!< No polling when padding */
00066 #define CRYP_POLLING_ON                              0x1  /*!< Polling when padding    */
00067 /**
00068   * @}
00069   */
00070
00071 /* Private macro -------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073 /* Private function prototypes -----------------------------------------------*/
00074 /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
00075  * @{
00076  */
00077 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
00078 static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout);
00079 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00080 static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00081 static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma);
00082 static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma);
00083 static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma);
00084 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00085 static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00086 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
00087 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
00088 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
00089 static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling);
00090 /**
00091   * @}
00092   */
00093
00094 /* Exported functions ---------------------------------------------------------*/
00095
00096 /** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
00097   * @{
00098   */
00099
00100
00101 /** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function
00102  *  @brief    Extended callback functions.
00103  *
00104 @verbatim
00105  ===============================================================================
00106                  ##### Extended callback functions #####
00107  ===============================================================================
00108     [..]  This section provides callback function:
00109       (+) Computation completed.
00110
00111 @endverbatim
00112   * @{
00113   */
00114
00115
00116 /**
00117   * @brief  Computation completed callbacks.
00118   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00119   *         the configuration information for CRYP module
00120   * @retval None
00121   */
00122 __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
00123 {
00124   /* Prevent unused argument(s) compilation warning */
00125   UNUSED(hcryp);
00126
00127   /* NOTE : This function should not be modified; when the callback is needed,
00128             the HAL_CRYPEx_ComputationCpltCallback can be implemented in the user file
00129    */
00130 }
00131
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions
00137  *  @brief   Extended processing functions.
00138  *
00139 @verbatim
00140   ==============================================================================
00141                       ##### AES extended processing functions #####
00142   ==============================================================================
00143     [..]  This section provides functions allowing to:
00144       (+) Encrypt plaintext or decrypt cipher text using AES algorithm in different chaining modes.
00145           Functions are generic (handles ECB, CBC and CTR and all modes) and are only differentiated
00146           based on the processing type. Three processing types are available:
00147           (++) Polling mode
00148           (++) Interrupt mode
00149           (++) DMA mode
00150       (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES
00151           algorithm in different chaining modes.
00152           Functions are generic (handles GCM, GMAC and CMAC) and process only one phase so that steps
00153           can be skipped if so required. Functions are only differentiated based on the processing type.
00154           Three processing types are available:
00155           (++) Polling mode
00156           (++) Interrupt mode
00157           (++) DMA mode
00158
00159 @endverbatim
00160   * @{
00161   */
00162
00163 /**
00164   * @brief  Carry out in polling mode the ciphering or deciphering operation according to
00165   *         hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and
00166   *         chaining modes ECB, CBC and CTR are managed by this function in polling mode.
00167   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00168   *         the configuration information for CRYP module
00169   * @param  pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption
00170   *                     or key derivation+decryption.
00171   *                     Parameter is meaningless in case of key derivation.
00172   * @param  Size: Length of the input data buffer in bytes, must be a multiple of 16.
00173   *               Parameter is meaningless in case of key derivation.
00174   * @param  pOutputData: Pointer to the cipher text in case of encryption or plain text in case of
00175   *                     decryption/key derivation+decryption, or pointer to the derivative keys in
00176   *                     case of key derivation only.
00177   * @param  Timeout: Specify Timeout value
00178   * @retval HAL status
00179   */
00180 HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout)
00181 {
00182
00183   if (hcryp->State == HAL_CRYP_STATE_READY)
00184   {
00185     /* Check parameters setting */
00186     if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
00187     {
00188       if (pOutputData == NULL)
00189       {
00190         return  HAL_ERROR;
00191       }
00192     }
00193     else
00194     {
00195       if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
00196       {
00197         return  HAL_ERROR;
00198       }
00199     }
00200
00201     /* Process Locked */
00202     __HAL_LOCK(hcryp);
00203
00204     /* Change the CRYP state */
00205     hcryp->State = HAL_CRYP_STATE_BUSY;
00206
00207     /* Call CRYP_ReadKey() API if the operating mode is set to
00208        key derivation, CRYP_ProcessData() otherwise  */
00209     if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
00210     {
00211       if(CRYP_ReadKey(hcryp, pOutputData, Timeout) != HAL_OK)
00212       {
00213         return HAL_TIMEOUT;
00214       }
00215     }
00216     else
00217     {
00218       if(CRYP_ProcessData(hcryp, pInputData, Size, pOutputData, Timeout) != HAL_OK)
00219       {
00220         return HAL_TIMEOUT;
00221       }
00222     }
00223
00224     /* If the state has not been set to SUSPENDED, set it to
00225        READY, otherwise keep it as it is */
00226     if (hcryp->State != HAL_CRYP_STATE_SUSPENDED)
00227     {
00228       hcryp->State = HAL_CRYP_STATE_READY;
00229     }
00230
00231     /* Process Unlocked */
00232     __HAL_UNLOCK(hcryp);
00233
00234     return HAL_OK;
00235   }
00236   else
00237   {
00238     return HAL_BUSY;
00239   }
00240 }
00241
00242
00243
00244 /**
00245   * @brief  Carry out in interrupt mode the ciphering or deciphering operation according to
00246   *         hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and
00247   *         chaining modes ECB, CBC and CTR are managed by this function in interrupt mode.
00248   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00249   *         the configuration information for CRYP module
00250   * @param  pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption
00251   *                     or key derivation+decryption.
00252   *                     Parameter is meaningless in case of key derivation.
00253   * @param  Size: Length of the input data buffer in bytes, must be a multiple of 16.
00254   *               Parameter is meaningless in case of key derivation.
00255   * @param  pOutputData: Pointer to the cipher text in case of encryption or plain text in case of
00256   *                     decryption/key derivation+decryption, or pointer to the derivative keys in
00257   *                     case of key derivation only.
00258   * @retval HAL status
00259   */
00260 HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
00261 {
00262   uint32_t inputaddr = 0;
00263
00264   if(hcryp->State == HAL_CRYP_STATE_READY)
00265   {
00266     /* Check parameters setting */
00267     if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
00268     {
00269       if (pOutputData == NULL)
00270       {
00271         return  HAL_ERROR;
00272       }
00273     }
00274     else
00275     {
00276       if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
00277       {
00278         return  HAL_ERROR;
00279       }
00280     }
00281     /* Process Locked */
00282     __HAL_LOCK(hcryp);
00283
00284     /* If operating mode is not limited to key derivation only,
00285        get the buffers addresses and sizes */
00286     if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
00287     {
00288
00289       hcryp->CrypInCount = Size;
00290       hcryp->pCrypInBuffPtr = pInputData;
00291       hcryp->pCrypOutBuffPtr = pOutputData;
00292       hcryp->CrypOutCount = Size;
00293     }
00294
00295     /* Change the CRYP state */
00296     hcryp->State = HAL_CRYP_STATE_BUSY;
00297
00298       /* Process Unlocked */
00299     __HAL_UNLOCK(hcryp);
00300
00301     /* Enable Computation Complete Flag and Error Interrupts */
00302     __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
00303
00304
00305     /* If operating mode is key derivation only, the input data have
00306        already been entered during the initialization process. For
00307        the other operating modes, they are fed to the CRYP hardware
00308        block at this point. */
00309     if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
00310     {
00311       /* Initiate the processing under interrupt in entering
00312          the first input data */
00313       inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
00314       /* Increment/decrement instance pointer/counter */
00315       hcryp->pCrypInBuffPtr += 16;
00316       hcryp->CrypInCount -= 16;
00317       /* Write the first input block in the Data Input register */
00318       hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00319       inputaddr+=4;
00320       hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00321       inputaddr+=4;
00322       hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
00323       inputaddr+=4;
00324       hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00325     }
00326
00327     /* Return function status */
00328     return HAL_OK;
00329   }
00330   else
00331   {
00332     return HAL_BUSY;
00333   }
00334 }
00335
00336
00337
00338
00339
00340 /**
00341   * @brief  Carry out in DMA mode the ciphering or deciphering operation according to
00342   *         hcryp->Init structure fields.
00343   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00344   *         the configuration information for CRYP module
00345   * @param  pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption
00346   *                     or key derivation+decryption.
00347   * @param  Size: Length of the input data buffer in bytes, must be a multiple of 16.
00348   * @param  pOutputData: Pointer to the cipher text in case of encryption or plain text in case of
00349   *                     decryption/key derivation+decryption.
00350   * @note   Chaining modes ECB, CBC and CTR are managed by this function in DMA mode.
00351   * @note   Supported operating modes are encryption, decryption and key derivation with decryption.
00352   * @note   No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx
00353   *         registers must be done by software.
00354   * @note   This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx
00355   *         registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs.
00356   * @note   pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
00357   * @retval HAL status
00358   */
00359 HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
00360 {
00361   uint32_t inputaddr = 0;
00362   uint32_t outputaddr = 0;
00363
00364   if (hcryp->State == HAL_CRYP_STATE_READY)
00365   {
00366     /* Check parameters setting */
00367     if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
00368     {
00369       /* no DMA channel is provided for key derivation operating mode,
00370          access to AES_KEYRx registers must be done by software */
00371       return  HAL_ERROR;
00372     }
00373     else
00374     {
00375       if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
00376       {
00377         return  HAL_ERROR;
00378       }
00379     }
00380
00381
00382     /* Process Locked */
00383     __HAL_LOCK(hcryp);
00384
00385     inputaddr  = (uint32_t)pInputData;
00386     outputaddr = (uint32_t)pOutputData;
00387
00388     /* Change the CRYP state */
00389     hcryp->State = HAL_CRYP_STATE_BUSY;
00390
00391     /* Set the input and output addresses and start DMA transfer */
00392     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
00393
00394     /* Process Unlocked */
00395     __HAL_UNLOCK(hcryp);
00396
00397     /* Return function status */
00398     return HAL_OK;
00399   }
00400   else
00401   {
00402     return HAL_BUSY;
00403   }
00404 }
00405
00406
00407
00408
00409
00410
00411 /**
00412   * @brief  Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering
00413   *         operation according to hcryp->Init structure fields.
00414   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00415   *         the configuration information for CRYP module
00416   * @param  pInputData:
00417   *         - pointer to payload data in GCM payload phase,
00418   *         - pointer to B0 block in CMAC header phase,
00419   *         - pointer to C block in CMAC final phase.
00420   *         - Parameter is meaningless in case of GCM/GMAC init, header and final phases.
00421   * @param  Size:
00422   *         - length of the input payload data buffer in bytes,
00423   *         - length of B0 block (in bytes) in CMAC header phase,
00424   *         - length of C block (in bytes) in CMAC final phase.
00425   *         - Parameter is meaningless in case of GCM/GMAC init and header phases.
00426   * @param  pOutputData:
00427   *         - pointer to plain or cipher text in GCM payload phase,
00428   *         - pointer to authentication tag in GCM/GMAC and CMAC final phases.
00429   *         - Parameter is meaningless in case of GCM/GMAC init and header phases
00430   *           and in case of CMAC header phase.
00431   * @param  Timeout: Specify Timeout value
00432   * @note   Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
00433   * @note   Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
00434   *         can be skipped by the user if so required.
00435   * @retval HAL status
00436   */
00437 HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout)
00438 {
00439   uint32_t index          = 0;
00440   uint32_t inputaddr      = 0;
00441   uint32_t outputaddr     = 0;
00442   uint32_t tagaddr        = 0;
00443   uint64_t headerlength   = 0;
00444   uint64_t inputlength    = 0;
00445   uint64_t payloadlength  = 0;
00446   uint32_t difflength     = 0;
00447   uint32_t addhoc_process = 0;
00448
00449   if (hcryp->State == HAL_CRYP_STATE_READY)
00450   {
00451     /* input/output parameters check */
00452     if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
00453     {
00454       if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0))
00455       {
00456         return  HAL_ERROR;
00457       }
00458       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
00459       {
00460         /* In case of CMAC header phase resumption, we can have pInputData = NULL and  Size = 0 */
00461         if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0)))
00462         {
00463           return  HAL_ERROR;
00464         }
00465       }
00466     }
00467     else if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
00468     {
00469       if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
00470       {
00471         return  HAL_ERROR;
00472       }
00473     }
00474     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_FINAL_PHASE)
00475     {
00476       if (pOutputData == NULL)
00477       {
00478         return  HAL_ERROR;
00479       }
00480       if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
00481       {
00482         return  HAL_ERROR;
00483       }
00484     }
00485
00486
00487     /* Process Locked */
00488     __HAL_LOCK(hcryp);
00489
00490     /* Change the CRYP state */
00491     hcryp->State = HAL_CRYP_STATE_BUSY;
00492
00493     /*=====================*/
00494     /* GCM/GMAC init phase */
00495     /*=====================*/
00496     /* In case of init phase, the input data (Key and Initialization Vector) have
00497        already been entered during the initialization process. Therefore, the
00498        API just waits for the CCF flag to be set. */
00499     if (hcryp->Init.GCMCMACPhase == CRYP_GCM_INIT_PHASE)
00500     {
00501       /* just wait for hash computation */
00502       if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
00503       {
00504         hcryp->State = HAL_CRYP_STATE_READY;
00505         __HAL_UNLOCK(hcryp);
00506         return HAL_TIMEOUT;
00507       }
00508
00509       /* Clear CCF Flag */
00510       __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
00511       /* Mark that the initialization phase is over */
00512       hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
00513     }
00514     /*===============================*/
00515     /* GCM/GMAC or CMAC header phase */
00516     /*===============================*/
00517     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
00518     {
00519       /* Set header phase; for GCM or GMAC, set data-byte at this point */
00520       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
00521       {
00522         MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_GCMCMAC_HEADER_PHASE|hcryp->Init.DataType);
00523       }
00524       else
00525       {
00526         MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_HEADER_PHASE);
00527       }
00528
00529       /* Enable the Peripheral */
00530       __HAL_CRYP_ENABLE();
00531
00532       /* in case of CMAC, enter B0 block in header phase, before the header itself. */
00533       /* If Size = 0 (possible case of resumption after CMAC header phase suspension),
00534          skip these steps and go directly to header buffer feeding to the HW */
00535       if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0))
00536       {
00537         inputaddr = (uint32_t)pInputData;
00538
00539         for(index=0; (index < Size); index += 16)
00540         {
00541           /* Write the Input block in the Data Input register */
00542           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00543           inputaddr+=4;
00544           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00545           inputaddr+=4;
00546           hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
00547           inputaddr+=4;
00548           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00549           inputaddr+=4;
00550
00551           if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
00552           {
00553             hcryp->State = HAL_CRYP_STATE_READY;
00554             __HAL_UNLOCK(hcryp);
00555             return HAL_TIMEOUT;
00556           }
00557           /* Clear CCF Flag */
00558           __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
00559
00560           /* If the suspension flag has been raised and if the processing is not about
00561            to end, suspend processing */
00562           if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Size))
00563           {
00564             /* reset SuspendRequest */
00565             hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
00566             /* Change the CRYP state */
00567             hcryp->State = HAL_CRYP_STATE_SUSPENDED;
00568             /* Mark that the header phase is over */
00569             hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
00570
00571            /* Save current reading and writing locations of Input and Output buffers */
00572            hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
00573            /* Save the total number of bytes (B blocks + header) that remain to be
00574               processed at this point */
00575            hcryp->CrypInCount     =  hcryp->Init.HeaderSize + Size - (index+16);
00576
00577            /* Process Unlocked */
00578             __HAL_UNLOCK(hcryp);
00579
00580             return HAL_OK;
00581           }
00582         } /* for(index=0; (index < Size); index += 16) */
00583       }
00584
00585       /* Enter header */
00586       inputaddr = (uint32_t)hcryp->Init.Header;
00587       /* Local variable headerlength is a number of bytes multiple of 128 bits,
00588          remaining header data (if any) are handled after this loop */
00589       headerlength =  (((hcryp->Init.HeaderSize)/16)*16) ;
00590       if ((hcryp->Init.HeaderSize % 16) != 0)
00591       {
00592         difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength);
00593       }
00594       for(index=0; index < headerlength; index += 16)
00595       {
00596         /* Write the Input block in the Data Input register */
00597         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00598         inputaddr+=4;
00599         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00600         inputaddr+=4;
00601         hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
00602         inputaddr+=4;
00603         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00604         inputaddr+=4;
00605
00606         if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
00607         {
00608           hcryp->State = HAL_CRYP_STATE_READY;
00609           __HAL_UNLOCK(hcryp);
00610           return HAL_TIMEOUT;
00611         }
00612         /* Clear CCF Flag */
00613         __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
00614
00615         /* If the suspension flag has been raised and if the processing is not about
00616          to end, suspend processing */
00617         if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < headerlength))
00618         {
00619           /* reset SuspendRequest */
00620           hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
00621           /* Change the CRYP state */
00622           hcryp->State = HAL_CRYP_STATE_SUSPENDED;
00623           /* Mark that the header phase is over */
00624           hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
00625
00626          /* Save current reading and writing locations of Input and Output buffers */
00627          hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
00628          /* Save the total number of bytes that remain to be processed at this point */
00629           hcryp->CrypInCount =  hcryp->Init.HeaderSize - (index+16);
00630
00631          /* Process Unlocked */
00632           __HAL_UNLOCK(hcryp);
00633
00634           return HAL_OK;
00635         }
00636       }
00637
00638       /* Case header length is not a multiple of 16 bytes */
00639       if (difflength != 0)
00640       {
00641         hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
00642         CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
00643       }
00644
00645       /* Mark that the header phase is over */
00646       hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
00647     }
00648     /*========================*/
00649     /* GCM/GMAC payload phase */
00650     /*========================*/
00651     else if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
00652     {
00653
00654       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCM_PAYLOAD_PHASE);
00655
00656       /* if the header phase has been bypassed, AES must be enabled again */
00657       if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
00658       {
00659         __HAL_CRYP_ENABLE();
00660       }
00661
00662       inputaddr  = (uint32_t)pInputData;
00663       outputaddr = (uint32_t)pOutputData;
00664
00665       /* Enter payload */
00666       /* Specific handling to manage payload last block size less than 128 bits
00667         when GCM encryption or decryption is selected */
00668       if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \
00669           ((Size % 16) != 0))
00670       {
00671         payloadlength = (Size/16) * 16;
00672         difflength = (uint32_t) (Size - payloadlength);
00673         addhoc_process = 1;
00674       }
00675       else
00676       {
00677         payloadlength = Size;
00678         addhoc_process = 0;
00679       }
00680
00681       /* Feed payload */
00682       for(index=0; index < payloadlength; index += 16)
00683       {
00684         /* Write the Input block in the Data Input register */
00685         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00686         inputaddr+=4;
00687         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00688         inputaddr+=4;
00689         hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
00690         inputaddr+=4;
00691         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00692         inputaddr+=4;
00693
00694         if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
00695         {
00696           hcryp->State = HAL_CRYP_STATE_READY;
00697           __HAL_UNLOCK(hcryp);
00698           return HAL_TIMEOUT;
00699         }
00700
00701         /* Clear CCF Flag */
00702         __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
00703
00704         /* Retrieve output data: read the output block
00705            from the Data Output Register */
00706         *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
00707         outputaddr+=4;
00708         *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
00709         outputaddr+=4;
00710         *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
00711         outputaddr+=4;
00712         *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
00713         outputaddr+=4;
00714
00715         /* If the suspension flag has been raised and if the processing is not about
00716          to end, suspend processing */
00717         if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < payloadlength))
00718         {
00719           /* no flag waiting under IRQ handling */
00720           if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
00721           {
00722             /* Ensure that Busy flag is reset */
00723             if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)
00724             {
00725               hcryp->State = HAL_CRYP_STATE_READY;
00726               __HAL_UNLOCK(hcryp);
00727               return HAL_TIMEOUT;
00728             }
00729           }
00730           /* reset SuspendRequest */
00731           hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
00732           /* Change the CRYP state */
00733           hcryp->State = HAL_CRYP_STATE_SUSPENDED;
00734           /* Mark that the header phase is over */
00735           hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
00736
00737           /* Save current reading and writing locations of Input and Output buffers */
00738           hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;
00739           hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
00740           /* Save the number of bytes that remain to be processed at this point */
00741           hcryp->CrypInCount     =  Size - (index+16);
00742
00743           /* Process Unlocked */
00744           __HAL_UNLOCK(hcryp);
00745
00746           return HAL_OK;
00747         }
00748
00749       }
00750
00751       /* Additional processing to manage GCM encryption and decryption cases when
00752          payload last block size less than 128 bits */
00753       if (addhoc_process == 1)
00754       {
00755
00756         hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
00757         hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;
00758         CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
00759
00760       } /* (addhoc_process == 1) */
00761
00762       /* Mark that the payload phase is over */
00763       hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
00764     }
00765     /*==============================*/
00766     /* GCM/GMAC or CMAC final phase */
00767     /*==============================*/
00768     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_FINAL_PHASE)
00769     {
00770       tagaddr = (uint32_t)pOutputData;
00771
00772       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
00773
00774       /* if the header and payload phases have been bypassed, AES must be enabled again */
00775       if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
00776       {
00777         __HAL_CRYP_ENABLE();
00778       }
00779
00780       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
00781       {
00782         headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
00783         inputlength = Size * 8;                    /* input length in bits */
00784
00785
00786         if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
00787         {
00788           hcryp->Instance->DINR = __RBIT((headerlength)>>32);
00789           hcryp->Instance->DINR = __RBIT(headerlength);
00790           hcryp->Instance->DINR = __RBIT((inputlength)>>32);
00791           hcryp->Instance->DINR = __RBIT(inputlength);
00792         }
00793         else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
00794         {
00795           hcryp->Instance->DINR = __REV((headerlength)>>32);
00796           hcryp->Instance->DINR = __REV(headerlength);
00797           hcryp->Instance->DINR = __REV((inputlength)>>32);
00798           hcryp->Instance->DINR = __REV(inputlength);
00799         }
00800         else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
00801         {
00802           hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);
00803           hcryp->Instance->DINR = __ROR(headerlength, 16);
00804           hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);
00805           hcryp->Instance->DINR = __ROR(inputlength, 16);
00806         }
00807         else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
00808         {
00809           hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
00810           hcryp->Instance->DINR = (uint32_t)(headerlength);
00811           hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
00812           hcryp->Instance->DINR = (uint32_t)(inputlength);
00813         }
00814       }
00815       else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
00816       {
00817         inputaddr  = (uint32_t)pInputData;
00818         /* Enter the last block made of a 128-bit value formatted
00819            from the original B0 packet. */
00820         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00821         inputaddr+=4;
00822         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00823         inputaddr+=4;
00824         hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
00825         inputaddr+=4;
00826         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
00827       }
00828
00829
00830       if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
00831       {
00832           hcryp->State = HAL_CRYP_STATE_READY;
00833           __HAL_UNLOCK(hcryp);
00834           return HAL_TIMEOUT;
00835       }
00836
00837       /* Read the Auth TAG in the Data Out register */
00838       *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
00839       tagaddr+=4;
00840       *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
00841       tagaddr+=4;
00842       *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
00843       tagaddr+=4;
00844       *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
00845
00846
00847       /* Clear CCF Flag */
00848       __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
00849       /* Mark that the final phase is over */
00850       hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
00851       /* Disable the Peripheral */
00852       __HAL_CRYP_DISABLE();
00853     }
00854     /*=================================================*/
00855     /* case incorrect hcryp->Init.GCMCMACPhase setting */
00856     /*=================================================*/
00857     else
00858     {
00859       hcryp->State = HAL_CRYP_STATE_ERROR;
00860       __HAL_UNLOCK(hcryp);
00861       return HAL_ERROR;
00862     }
00863
00864     /* Change the CRYP state */
00865     hcryp->State = HAL_CRYP_STATE_READY;
00866
00867     /* Process Unlocked */
00868     __HAL_UNLOCK(hcryp);
00869
00870     return HAL_OK;
00871   }
00872   else
00873   {
00874     return HAL_BUSY;
00875   }
00876 }
00877
00878
00879
00880
00881 /**
00882   * @brief  Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering
00883   *         operation according to hcryp->Init structure fields.
00884   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
00885   *         the configuration information for CRYP module
00886   * @param  pInputData:
00887   *         - pointer to payload data in GCM payload phase,
00888   *         - pointer to B0 block in CMAC header phase,
00889   *         - pointer to C block in CMAC final phase.
00890   *         Parameter is meaningless in case of GCM/GMAC init, header and final phases.
00891   * @param  Size:
00892   *         - length of the input payload data buffer in bytes,
00893   *         - length of B0 block (in bytes) in CMAC header phase,
00894   *         - length of C block (in bytes) in CMAC final phase.
00895   *         - Parameter is meaningless in case of GCM/GMAC init and header phases.
00896   * @param  pOutputData:
00897   *         - pointer to plain or cipher text in GCM payload phase,
00898   *         - pointer to authentication tag in GCM/GMAC and CMAC final phases.
00899   *         - Parameter is meaningless in case of GCM/GMAC init and header phases
00900   *           and in case of CMAC header phase.
00901   * @note   Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
00902   * @note   Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
00903   *         can be skipped by the user if so required.
00904   * @retval HAL status
00905   */
00906 HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
00907 {
00908
00909   uint32_t inputaddr      = 0;
00910   uint64_t headerlength   = 0;
00911   uint64_t inputlength    = 0;
00912   uint32_t index          = 0;
00913   uint32_t addhoc_process = 0;
00914   uint32_t difflength     = 0;
00915   uint32_t difflengthmod4 = 0;
00916   uint32_t mask[3]        = {0x0FF, 0x0FFFF, 0x0FFFFFF};
00917
00918
00919   if (hcryp->State == HAL_CRYP_STATE_READY)
00920   {
00921     /* input/output parameters check */
00922     if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
00923     {
00924       if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0))
00925       {
00926         return  HAL_ERROR;
00927       }
00928       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
00929       {
00930         /* In case of CMAC header phase resumption, we can have pInputData = NULL and  Size = 0 */
00931         if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0)))
00932         {
00933           return  HAL_ERROR;
00934         }
00935       }
00936     }
00937     else if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
00938     {
00939       if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
00940       {
00941         return  HAL_ERROR;
00942       }
00943     }
00944     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_FINAL_PHASE)
00945     {
00946       if (pOutputData == NULL)
00947       {
00948         return  HAL_ERROR;
00949       }
00950       if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
00951       {
00952         return  HAL_ERROR;
00953       }
00954     }
00955
00956
00957     /* Process Locked */
00958     __HAL_LOCK(hcryp);
00959
00960     /* Change the CRYP state */
00961     hcryp->State = HAL_CRYP_STATE_BUSY;
00962
00963     /* Process Unlocked */
00964     __HAL_UNLOCK(hcryp);
00965
00966     /* Enable Computation Complete Flag and Error Interrupts */
00967     __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
00968
00969
00970
00971     /*=====================*/
00972     /* GCM/GMAC init phase */
00973     /*=====================*/
00974     if (hcryp->Init.GCMCMACPhase == CRYP_GCM_INIT_PHASE)
00975     {
00976     /* In case of init phase, the input data (Key and Initialization Vector) have
00977        already been entered during the initialization process. Therefore, the
00978        software just waits for the CCF interrupt to be raised and which will
00979        be handled by CRYP_AES_Auth_IT() API. */
00980     }
00981     /*===============================*/
00982     /* GCM/GMAC or CMAC header phase */
00983     /*===============================*/
00984     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
00985     {
00986       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
00987       {
00988         /* In case of CMAC, B blocks are first entered, before the header.
00989            Therefore, B blocks and the header are entered back-to-back
00990            as if it was only one single block.
00991            However, in case of resumption after suspension, if all the
00992            B blocks have been entered (in that case, Size = 0), only the
00993            remainder of the non-processed header bytes are entered. */
00994           if (Size != 0)
00995           {
00996             hcryp->CrypInCount = Size + hcryp->Init.HeaderSize;
00997             hcryp->pCrypInBuffPtr = pInputData;
00998           }
00999           else
01000           {
01001             hcryp->CrypInCount = hcryp->Init.HeaderSize;
01002             hcryp->pCrypInBuffPtr = hcryp->Init.Header;
01003           }
01004       }
01005       else
01006       {
01007         /* Get the header addresses and sizes */
01008         hcryp->CrypInCount = hcryp->Init.HeaderSize;
01009         hcryp->pCrypInBuffPtr = hcryp->Init.Header;
01010       }
01011
01012       inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01013
01014       /* Set header phase; for GCM or GMAC, set data-byte at this point */
01015       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
01016       {
01017         MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_GCMCMAC_HEADER_PHASE|hcryp->Init.DataType);
01018       }
01019       else
01020       {
01021         MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_HEADER_PHASE);
01022       }
01023
01024       /* Enable the Peripheral */
01025       __HAL_CRYP_ENABLE();
01026
01027       /* Increment/decrement instance pointer/counter */
01028       if (hcryp->CrypInCount == 0)
01029       {
01030         /* Case of no header */
01031         hcryp->State = HAL_CRYP_STATE_READY;
01032         return HAL_OK;
01033       }
01034       else if (hcryp->CrypInCount < 16)
01035       {
01036         hcryp->CrypInCount = 0;
01037         addhoc_process = 1;
01038         difflength = (uint32_t) (hcryp->Init.HeaderSize);
01039         difflengthmod4 = difflength%4;
01040       }
01041       else
01042       {
01043         hcryp->pCrypInBuffPtr += 16;
01044         hcryp->CrypInCount -= 16;
01045       }
01046
01047
01048       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
01049       {
01050         if (hcryp->CrypInCount == hcryp->Init.HeaderSize)
01051         {
01052           /* All B blocks will have been entered after the next
01053              four DINR writing, so point at header buffer for
01054              the next iteration */
01055           hcryp->pCrypInBuffPtr = hcryp->Init.Header;
01056         }
01057       }
01058
01059       /* Enter header first block to initiate the process
01060          in the Data Input register */
01061       if (addhoc_process == 0)
01062       {
01063         /* Header has size equal or larger than 128 bits */
01064         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01065         inputaddr+=4;
01066         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01067         inputaddr+=4;
01068         hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
01069         inputaddr+=4;
01070         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01071       }
01072       else
01073       {
01074         /* Header has size less than 128 bits */
01075         /* Enter complete words when possible */
01076         for(index=0; index < (difflength/4); index ++)
01077         {
01078           /* Write the Input block in the Data Input register */
01079           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01080           inputaddr+=4;
01081         }
01082         /* Enter incomplete word padded with zeroes if applicable
01083           (case of header length not a multiple of 32-bits) */
01084         if (difflengthmod4 != 0)
01085         {
01086           hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
01087         }
01088         /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
01089         for(index=0; index < (4 - ((difflength+3)/4)); index ++)
01090         {
01091           hcryp->Instance->DINR = 0;
01092         }
01093
01094       }
01095     }
01096     /*========================*/
01097     /* GCM/GMAC payload phase */
01098     /*========================*/
01099     else if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
01100     {
01101       /* Get the buffer addresses and sizes */
01102       hcryp->CrypInCount = Size;
01103       hcryp->pCrypInBuffPtr = pInputData;
01104       hcryp->pCrypOutBuffPtr = pOutputData;
01105       hcryp->CrypOutCount = Size;
01106
01107       inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
01108
01109       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCM_PAYLOAD_PHASE);
01110
01111       /* if the header phase has been bypassed, AES must be enabled again */
01112       if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
01113       {
01114         __HAL_CRYP_ENABLE();
01115       }
01116
01117      /* Specific handling to manage payload size less than 128 bits
01118         when GCM encryption or decryption is selected */
01119       if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \
01120           (Size < 16))
01121       {
01122         /* Software workaround applied to GCM encryption only */
01123         if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
01124         {
01125           /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
01126           __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
01127         }
01128
01129         /* Set hcryp->CrypInCount to 0 (no more data to enter) */
01130         hcryp->CrypInCount = 0;
01131
01132         /*  Insert the last block (which size is inferior to 128 bits) padded with zeroes,
01133             to have a complete block of 128 bits */
01134         difflength = (uint32_t) (Size);
01135         difflengthmod4 = difflength%4;
01136         /*  Insert the last block (which size is inferior to 128 bits) padded with zeroes
01137             to have a complete block of 128 bits */
01138         for(index=0; index < (difflength/4); index ++)
01139         {
01140           /* Write the Input block in the Data Input register */
01141           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01142           inputaddr+=4;
01143         }
01144         /* If required, manage input data size not multiple of 32 bits */
01145         if (difflengthmod4 != 0)
01146         {
01147           hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
01148         }
01149         /* Wrap-up in padding with zero-words if applicable */
01150         for(index=0; index < (4 - ((difflength+3)/4)); index ++)
01151         {
01152           hcryp->Instance->DINR = 0;
01153         }
01154       }
01155       else
01156       {
01157         /* Increment/decrement instance pointer/counter */
01158         hcryp->pCrypInBuffPtr += 16;
01159         hcryp->CrypInCount -= 16;
01160
01161         /* Enter payload first block to initiate the process
01162            in the Data Input register */
01163         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01164         inputaddr+=4;
01165         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01166         inputaddr+=4;
01167         hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
01168         inputaddr+=4;
01169         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01170       }
01171     }
01172     /*==============================*/
01173     /* GCM/GMAC or CMAC final phase */
01174     /*==============================*/
01175     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_FINAL_PHASE)
01176     {
01177        hcryp->pCrypOutBuffPtr = pOutputData;
01178
01179        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
01180
01181       /* if the header and payload phases have been bypassed, AES must be enabled again */
01182       if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
01183       {
01184         __HAL_CRYP_ENABLE();
01185       }
01186
01187       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
01188       {
01189         headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
01190         inputlength = Size * 8;                   /* input length in bits */
01191         /* Write the number of bits in the header on 64 bits followed by the number
01192            of bits in the payload on 64 bits as well */
01193         if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
01194         {
01195           hcryp->Instance->DINR = __RBIT((headerlength)>>32);
01196           hcryp->Instance->DINR = __RBIT(headerlength);
01197           hcryp->Instance->DINR = __RBIT((inputlength)>>32);
01198           hcryp->Instance->DINR = __RBIT(inputlength);
01199         }
01200         else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
01201         {
01202           hcryp->Instance->DINR = __REV((headerlength)>>32);
01203           hcryp->Instance->DINR = __REV(headerlength);
01204           hcryp->Instance->DINR = __REV((inputlength)>>32);
01205           hcryp->Instance->DINR = __REV(inputlength);
01206         }
01207         else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
01208         {
01209           hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);
01210           hcryp->Instance->DINR = __ROR(headerlength, 16);
01211           hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);
01212           hcryp->Instance->DINR = __ROR(inputlength, 16);
01213         }
01214         else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
01215         {
01216           hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
01217           hcryp->Instance->DINR = (uint32_t)(headerlength);
01218           hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
01219           hcryp->Instance->DINR = (uint32_t)(inputlength);
01220         }
01221       }
01222       else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
01223       {
01224         inputaddr  = (uint32_t)pInputData;
01225         /* Enter the last block made of a 128-bit value formatted
01226            from the original B0 packet. */
01227         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01228         inputaddr+=4;
01229         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01230         inputaddr+=4;
01231         hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
01232         inputaddr+=4;
01233         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01234         inputaddr+=4;
01235       }
01236     }
01237     /*=================================================*/
01238     /* case incorrect hcryp->Init.GCMCMACPhase setting */
01239     /*=================================================*/
01240     else
01241     {
01242       hcryp->State = HAL_CRYP_STATE_ERROR;
01243       return HAL_ERROR;
01244     }
01245
01246     return HAL_OK;
01247   }
01248   else
01249   {
01250     return HAL_BUSY;
01251   }
01252 }
01253
01254
01255
01256
01257 /**
01258   * @brief  Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering
01259   *         operation according to hcryp->Init structure fields.
01260   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01261   *         the configuration information for CRYP module
01262   * @param  pInputData:
01263   *         - pointer to payload data in GCM payload phase,
01264   *         - pointer to B0 block in CMAC header phase,
01265   *         - pointer to C block in CMAC final phase.
01266   *         - Parameter is meaningless in case of GCM/GMAC init, header and final phases.
01267   * @param  Size:
01268   *         - length of the input payload data buffer in bytes,
01269   *         - length of B block (in bytes) in CMAC header phase,
01270   *         - length of C block (in bytes) in CMAC final phase.
01271   *         - Parameter is meaningless in case of GCM/GMAC init and header phases.
01272   * @param  pOutputData:
01273   *         - pointer to plain or cipher text in GCM payload phase,
01274   *         - pointer to authentication tag in GCM/GMAC and CMAC final phases.
01275   *         - Parameter is meaningless in case of GCM/GMAC init and header phases
01276   *           and in case of CMAC header phase.
01277   * @note   Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
01278   * @note   Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
01279   *         can be skipped by the user if so required.
01280   * @note   pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
01281   * @retval HAL status
01282   */
01283 HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
01284 {
01285   uint32_t inputaddr      = 0;
01286   uint32_t outputaddr     = 0;
01287   uint32_t tagaddr        = 0;
01288   uint64_t headerlength   = 0;
01289   uint64_t inputlength    = 0;
01290   uint64_t payloadlength  = 0;
01291
01292
01293   if (hcryp->State == HAL_CRYP_STATE_READY)
01294   {
01295     /* input/output parameters check */
01296     if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
01297     {
01298       if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0))
01299       {
01300         return  HAL_ERROR;
01301       }
01302       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
01303       {
01304         if ((pInputData == NULL) || (Size == 0))
01305         {
01306           return  HAL_ERROR;
01307         }
01308       }
01309     }
01310     else if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
01311     {
01312       if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
01313       {
01314         return  HAL_ERROR;
01315       }
01316     }
01317     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_FINAL_PHASE)
01318     {
01319       if (pOutputData == NULL)
01320       {
01321         return  HAL_ERROR;
01322       }
01323       if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
01324       {
01325         return  HAL_ERROR;
01326       }
01327     }
01328
01329
01330     /* Process Locked */
01331     __HAL_LOCK(hcryp);
01332
01333     /* Change the CRYP state */
01334     hcryp->State = HAL_CRYP_STATE_BUSY;
01335
01336     /*=====================*/
01337     /* GCM/GMAC init phase */
01338     /*=====================*/
01339     /* In case of init phase, the input data (Key and Initialization Vector) have
01340        already been entered during the initialization process. No DMA transfer is
01341        required at that point therefore, the software just waits for the CCF flag
01342        to be raised. */
01343     if (hcryp->Init.GCMCMACPhase == CRYP_GCM_INIT_PHASE)
01344     {
01345       /* just wait for hash computation */
01346       if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
01347       {
01348         hcryp->State = HAL_CRYP_STATE_READY;
01349         __HAL_UNLOCK(hcryp);
01350         return HAL_TIMEOUT;
01351       }
01352
01353       /* Clear CCF Flag */
01354       __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
01355       /* Mark that the initialization phase is over */
01356       hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
01357       hcryp->State = HAL_CRYP_STATE_READY;
01358     }
01359     /*===============================*/
01360     /* GCM/GMAC or CMAC header phase */
01361     /*===============================*/
01362     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
01363     {
01364       /* Set header phase; for GCM or GMAC, set data-byte at this point */
01365       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
01366       {
01367         MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_GCMCMAC_HEADER_PHASE|hcryp->Init.DataType);
01368       }
01369       else
01370       {
01371         MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_HEADER_PHASE);
01372       }
01373
01374       /* enter first B0 block in polling mode (no DMA transfer for B0) */
01375       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
01376       {
01377          /* Enable the CRYP peripheral */
01378         __HAL_CRYP_ENABLE();
01379
01380         inputaddr  = (uint32_t)pInputData;
01381         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01382         inputaddr+=4;
01383         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01384         inputaddr+=4;
01385         hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
01386         inputaddr+=4;
01387         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01388
01389         if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
01390         {
01391           hcryp->State = HAL_CRYP_STATE_READY;
01392           __HAL_UNLOCK(hcryp);
01393           return HAL_TIMEOUT;
01394         }
01395         /* Clear CCF Flag */
01396         __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
01397       }
01398
01399       /* No header case */
01400       if (hcryp->Init.Header == NULL)
01401       {
01402         hcryp->State = HAL_CRYP_STATE_READY;
01403         /* Mark that the header phase is over */
01404         hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
01405         /* Process Unlocked */
01406         __HAL_UNLOCK(hcryp);
01407
01408         return HAL_OK;
01409       }
01410
01411       inputaddr = (uint32_t)hcryp->Init.Header;
01412       if ((hcryp->Init.HeaderSize % 16) != 0)
01413       {
01414
01415         if (hcryp->Init.HeaderSize < 16)
01416         {
01417           /*difflength = (uint32_t) (hcryp->Init.HeaderSize);*/
01418
01419           CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF);
01420
01421           hcryp->State = HAL_CRYP_STATE_READY;
01422           /* Mark that the header phase is over */
01423           hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
01424
01425           /* CCF flag indicating header phase AES processing completion
01426              will be checked at the start of the next phase:
01427             - payload phase (GCM)
01428             - final phase (GMAC or CMAC).  */
01429         }
01430         else
01431         {
01432           /* Local variable headerlength is a number of bytes multiple of 128 bits,
01433             remaining header data (if any) are handled after this loop */
01434           headerlength =  (((hcryp->Init.HeaderSize)/16)*16) ;
01435           /* Store the ending transfer point */
01436           hcryp->pCrypInBuffPtr = hcryp->Init.Header + headerlength;
01437           hcryp->CrypInCount = (uint32_t)(hcryp->Init.HeaderSize - headerlength); /* remainder */
01438
01439           /* Set the input and output addresses and start DMA transfer */
01440           /* (incomplete DMA transfer, will be wrapped up after completion of
01441              the first one (initiated here) with data padding */
01442           CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, headerlength, 0);
01443         }
01444       }
01445       else
01446       {
01447         hcryp->CrypInCount = 0;
01448         /* Set the input address and start DMA transfer */
01449         CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0);
01450       }
01451
01452
01453     }
01454     /*========================*/
01455     /* GCM/GMAC payload phase */
01456     /*========================*/
01457     else if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
01458     {
01459       /* Coming from header phase, wait for CCF flag to be raised
01460           if header present and fed to the IP in the previous phase */
01461       if (hcryp->Init.Header != NULL)
01462       {
01463         if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
01464         {
01465           hcryp->State = HAL_CRYP_STATE_READY;
01466           __HAL_UNLOCK(hcryp);
01467           return HAL_TIMEOUT;
01468         }
01469       }
01470       else
01471       {
01472         /* Enable the Peripheral since wasn't in header phase (no header case) */
01473         __HAL_CRYP_ENABLE();
01474       }
01475       /* Clear CCF Flag */
01476       __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
01477
01478       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCM_PAYLOAD_PHASE);
01479
01480       /* Specific handling to manage payload size less than 128 bits
01481         when GCM encryption or decryption is selected */
01482       if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \
01483           ((Size % 16) != 0))
01484       {
01485         inputaddr  = (uint32_t)pInputData;
01486         outputaddr = (uint32_t)pOutputData;
01487         if (Size < 16)
01488         {
01489           /* Block is now entered in polling mode, no actual gain in resorting to DMA */
01490           /*difflength = (uint32_t)Size;*/
01491           hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
01492           hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;
01493
01494           CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON);
01495
01496           /* Change the CRYP state to ready */
01497           hcryp->State = HAL_CRYP_STATE_READY;
01498           /* Mark that the payload phase is over */
01499           hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
01500
01501           /* Call output data transfer complete callback */
01502           HAL_CRYP_OutCpltCallback(hcryp);
01503         }
01504         else
01505         {
01506           payloadlength = (Size/16) * 16;
01507
01508           /* Store the ending transfer points */
01509           hcryp->pCrypInBuffPtr = pInputData + payloadlength;
01510           hcryp->pCrypOutBuffPtr = pOutputData + payloadlength;
01511           hcryp->CrypInCount = (uint32_t)(Size - payloadlength); /* remainder */
01512
01513           /* Set the input and output addresses and start DMA transfer */
01514           /* (incomplete DMA transfer, will be wrapped up with data padding
01515              after completion of the one initiated here) */
01516           CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr);
01517         }
01518       }
01519       else
01520       {
01521         hcryp->CrypInCount = 0;
01522         inputaddr  = (uint32_t)pInputData;
01523         outputaddr = (uint32_t)pOutputData;
01524
01525         /* Set the input and output addresses and start DMA transfer */
01526         CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
01527       }
01528     }
01529     /*==============================*/
01530     /* GCM/GMAC or CMAC final phase */
01531     /*==============================*/
01532     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_FINAL_PHASE)
01533     {
01534       /* If coming from header phase (GMAC or CMAC case),
01535          wait for CCF flag to be raised */
01536       if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_GCMCMAC_HEADER_PHASE)
01537       {
01538         if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
01539         {
01540           hcryp->State = HAL_CRYP_STATE_READY;
01541           __HAL_UNLOCK(hcryp);
01542           return HAL_TIMEOUT;
01543         }
01544         /* Clear CCF Flag */
01545         __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
01546       }
01547
01548       tagaddr = (uint32_t)pOutputData;
01549
01550       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
01551
01552       /* if the header and payload phases have been bypassed, AES must be enabled again */
01553       if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
01554       {
01555         __HAL_CRYP_ENABLE();
01556       }
01557
01558       if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
01559       {
01560         headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
01561         inputlength = Size * 8;  /* input length in bits */
01562         /* Write the number of bits in the header on 64 bits followed by the number
01563            of bits in the payload on 64 bits as well */
01564         if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
01565         {
01566           hcryp->Instance->DINR = __RBIT((headerlength)>>32);
01567           hcryp->Instance->DINR = __RBIT(headerlength);
01568           hcryp->Instance->DINR = __RBIT((inputlength)>>32);
01569           hcryp->Instance->DINR = __RBIT(inputlength);
01570         }
01571         else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
01572         {
01573           hcryp->Instance->DINR = __REV((headerlength)>>32);
01574           hcryp->Instance->DINR = __REV(headerlength);
01575           hcryp->Instance->DINR = __REV((inputlength)>>32);
01576           hcryp->Instance->DINR = __REV(inputlength);
01577         }
01578         else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
01579         {
01580           hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);
01581           hcryp->Instance->DINR = __ROR(headerlength, 16);
01582           hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);
01583           hcryp->Instance->DINR = __ROR(inputlength, 16);
01584         }
01585         else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
01586         {
01587           hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
01588           hcryp->Instance->DINR = (uint32_t)(headerlength);
01589           hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
01590           hcryp->Instance->DINR = (uint32_t)(inputlength);
01591         }
01592       }
01593       else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
01594       {
01595         __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
01596
01597         inputaddr  = (uint32_t)pInputData;
01598         /* Enter the last block made of a 128-bit value formatted
01599            from the original B0 packet. */
01600         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01601         inputaddr+=4;
01602         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01603         inputaddr+=4;
01604         hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
01605         inputaddr+=4;
01606         hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
01607         inputaddr+=4;
01608       }
01609
01610       /* No DMA transfer is required at that point therefore, the software
01611          just waits for the CCF flag to be raised. */
01612       if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
01613       {
01614           hcryp->State = HAL_CRYP_STATE_READY;
01615           __HAL_UNLOCK(hcryp);
01616           return HAL_TIMEOUT;
01617       }
01618       /* Clear CCF Flag */
01619       __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
01620       /* Read the Auth TAG in the IN FIFO */
01621       *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
01622       tagaddr+=4;
01623       *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
01624       tagaddr+=4;
01625       *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
01626       tagaddr+=4;
01627       *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
01628
01629       /* Mark that the final phase is over */
01630       hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
01631       hcryp->State = HAL_CRYP_STATE_READY;
01632       /* Disable the Peripheral */
01633       __HAL_CRYP_DISABLE();
01634     }
01635     /*=================================================*/
01636     /* case incorrect hcryp->Init.GCMCMACPhase setting */
01637     /*=================================================*/
01638     else
01639     {
01640       hcryp->State = HAL_CRYP_STATE_ERROR;
01641       __HAL_UNLOCK(hcryp);
01642       return HAL_ERROR;
01643     }
01644
01645     /* Process Unlocked */
01646     __HAL_UNLOCK(hcryp);
01647
01648     return HAL_OK;
01649   }
01650   else
01651   {
01652     return HAL_BUSY;
01653   }
01654 }
01655
01656 /**
01657   * @}
01658   */
01659
01660 /** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions
01661  *  @brief   Extended processing functions.
01662  *
01663 @verbatim
01664   ==============================================================================
01665                     ##### AES extended suspension and resumption functions #####
01666   ==============================================================================
01667     [..]  This section provides functions allowing to:
01668       (+) save in memory the Initialization Vector, the Key registers, the Control register or
01669           the Suspend registers when a process is suspended by a higher priority message
01670       (+) write back in CRYP hardware block the saved values listed above when the suspended
01671           lower priority message processing is resumed.
01672
01673 @endverbatim
01674   * @{
01675   */
01676
01677
01678 /**
01679   * @brief  In case of message processing suspension, read the Initialization Vector.
01680   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01681   *         the configuration information for CRYP module.
01682   * @param  Output: Pointer to the buffer containing the saved Initialization Vector.
01683   * @note   This value has to be stored for reuse by writing the AES_IVRx registers
01684   *         as soon as the interrupted processing has to be resumed.
01685   *         Applicable to all chaining modes.
01686   * @note   AES must be disabled when reading or resetting the IV values.
01687   * @retval None
01688   */
01689 void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
01690 {
01691   uint32_t outputaddr = (uint32_t)Output;
01692
01693   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR3);
01694   outputaddr+=4;
01695   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR2);
01696   outputaddr+=4;
01697   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR1);
01698   outputaddr+=4;
01699   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR0);
01700 }
01701
01702 /**
01703   * @brief  In case of message processing resumption, rewrite the Initialization
01704   *         Vector in the AES_IVRx registers.
01705   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01706   *         the configuration information for CRYP module.
01707   * @param  Input: Pointer to the buffer containing the saved Initialization Vector to
01708   *         write back in the CRYP hardware block.
01709   * @note   Applicable to all chaining modes.
01710   * @note   AES must be disabled when reading or resetting the IV values.
01711   * @retval None
01712   */
01713 void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
01714 {
01715   uint32_t ivaddr = (uint32_t)Input;
01716
01717   hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
01718   ivaddr+=4;
01719   hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
01720   ivaddr+=4;
01721   hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
01722   ivaddr+=4;
01723   hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
01724 }
01725
01726
01727 /**
01728   * @brief  In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers.
01729   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01730   *         the configuration information for CRYP module.
01731   * @param  Output: Pointer to the buffer containing the saved Suspend Registers.
01732   * @note   These values have to be stored for reuse by writing back the AES_SUSPxR registers
01733   *         as soon as the interrupted processing has to be resumed.
01734   * @retval None
01735   */
01736 void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
01737 {
01738   uint32_t outputaddr = (uint32_t)Output;
01739
01740   /* In case of GCM payload phase encryption, check that suspension can be carried out */
01741   if (READ_BIT(hcryp->Instance->CR, (AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_GCM_PAYLOAD_PHASE|CRYP_ALGOMODE_ENCRYPT))
01742   {
01743     /* Ensure that Busy flag is reset */
01744     if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)
01745     {
01746       hcryp->ErrorCode |= HAL_CRYP_BUSY_ERROR;
01747       hcryp->State = HAL_CRYP_STATE_ERROR;
01748
01749       /* Process Unlocked */
01750       __HAL_UNLOCK(hcryp);
01751
01752       HAL_CRYP_ErrorCallback(hcryp);
01753       return ;
01754     }
01755   }
01756
01757   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP7R);
01758   outputaddr+=4;
01759   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP6R);
01760   outputaddr+=4;
01761   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP5R);
01762   outputaddr+=4;
01763   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP4R);
01764   outputaddr+=4;
01765   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP3R);
01766   outputaddr+=4;
01767   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP2R);
01768   outputaddr+=4;
01769   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R);
01770   outputaddr+=4;
01771   *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R);
01772 }
01773
01774 /**
01775   * @brief  In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend
01776   *         Registers in the AES_SUSPxR registers.
01777   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01778   *         the configuration information for CRYP module.
01779   * @param  Input: Pointer to the buffer containing the saved suspend registers to
01780   *         write back in the CRYP hardware block.
01781   * @retval None
01782   */
01783 void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
01784 {
01785   uint32_t ivaddr = (uint32_t)Input;
01786
01787   hcryp->Instance->SUSP7R = __REV(*(uint32_t*)(ivaddr));
01788   ivaddr+=4;
01789   hcryp->Instance->SUSP6R = __REV(*(uint32_t*)(ivaddr));
01790   ivaddr+=4;
01791   hcryp->Instance->SUSP5R = __REV(*(uint32_t*)(ivaddr));
01792   ivaddr+=4;
01793   hcryp->Instance->SUSP4R = __REV(*(uint32_t*)(ivaddr));
01794   ivaddr+=4;
01795   hcryp->Instance->SUSP3R = __REV(*(uint32_t*)(ivaddr));
01796   ivaddr+=4;
01797   hcryp->Instance->SUSP2R = __REV(*(uint32_t*)(ivaddr));
01798   ivaddr+=4;
01799   hcryp->Instance->SUSP1R = __REV(*(uint32_t*)(ivaddr));
01800   ivaddr+=4;
01801   hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr));
01802 }
01803
01804
01805 /**
01806   * @brief  In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers.
01807   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01808   *         the configuration information for CRYP module.
01809   * @param  Output: Pointer to the buffer containing the saved Key Registers.
01810   * @param  KeySize: Indicates the key size (128 or 256 bits).
01811   * @note   These values have to be stored for reuse by writing back the AES_KEYRx registers
01812   *         as soon as the interrupted processing has to be resumed.
01813   * @retval None
01814   */
01815 void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize)
01816 {
01817   uint32_t keyaddr = (uint32_t)Output;
01818
01819   if (KeySize == CRYP_KEYSIZE_256B)
01820   {
01821     *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR7);
01822     keyaddr+=4;
01823     *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR6);
01824     keyaddr+=4;
01825     *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR5);
01826     keyaddr+=4;
01827     *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR4);
01828     keyaddr+=4;
01829   }
01830
01831   *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR3);
01832   keyaddr+=4;
01833   *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR2);
01834   keyaddr+=4;
01835   *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR1);
01836   keyaddr+=4;
01837   *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0);
01838 }
01839
01840 /**
01841   * @brief  In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key
01842   *         Registers in the AES_KEYRx registers.
01843   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01844   *         the configuration information for CRYP module.
01845   * @param  Input: Pointer to the buffer containing the saved key registers to
01846   *         write back in the CRYP hardware block.
01847   * @param  KeySize: Indicates the key size (128 or 256 bits)
01848   * @retval None
01849   */
01850 void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize)
01851 {
01852   uint32_t keyaddr = (uint32_t)Input;
01853
01854   if (KeySize == CRYP_KEYSIZE_256B)
01855   {
01856     hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
01857     keyaddr+=4;
01858     hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
01859     keyaddr+=4;
01860     hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
01861     keyaddr+=4;
01862     hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
01863     keyaddr+=4;
01864   }
01865
01866     hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
01867     keyaddr+=4;
01868     hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
01869     keyaddr+=4;
01870     hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
01871     keyaddr+=4;
01872     hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
01873 }
01874
01875
01876 /**
01877   * @brief  In case of message GCM/GMAC or CMAC processing suspension, read the Control Register.
01878   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01879   *         the configuration information for CRYP module.
01880   * @param  Output: Pointer to the buffer containing the saved Control Register.
01881   * @note   This values has to be stored for reuse by writing back the AES_CR register
01882   *         as soon as the interrupted processing has to be resumed.
01883   * @retval None
01884   */
01885 void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
01886 {
01887   *(uint32_t*)(Output) = hcryp->Instance->CR;
01888 }
01889
01890 /**
01891   * @brief  In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control
01892   *         Registers in the AES_CR register.
01893   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01894   *         the configuration information for CRYP module.
01895   * @param  Input: Pointer to the buffer containing the saved Control Register to
01896   *         write back in the CRYP hardware block.
01897   * @retval None
01898   */
01899 void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
01900 {
01901   hcryp->Instance->CR = *(uint32_t*)(Input);
01902   /* At the same time, set handle state back to READY to be able to resume the AES calculations
01903      without the processing APIs returning HAL_BUSY when called. */
01904   hcryp->State        = HAL_CRYP_STATE_READY;
01905 }
01906
01907 /**
01908   * @brief  Request CRYP processing suspension when in polling or interruption mode.
01909   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
01910   *         the configuration information for CRYP module.
01911   * @note   Set the handle field SuspendRequest to the appropriate value so that
01912   *         the on-going CRYP processing is suspended as soon as the required
01913   *         conditions are met.
01914   * @note   It is advised not to suspend the CRYP processing when the DMA controller
01915   *         is managing the data transfer
01916   * @retval None
01917   */
01918 void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
01919 {
01920   /* Set Handle Suspend Request field */
01921   hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
01922 }
01923
01924 /**
01925   * @}
01926   */
01927
01928 /**
01929   * @}
01930   */
01931
01932 /** @addtogroup CRYPEx_Private_Functions
01933   * @{
01934   */
01935
01936 /**
01937   * @brief  DMA CRYP Input Data process complete callback
01938   *         for GCM, GMAC or CMAC chainging modes.
01939   * @note   Specific setting of hcryp fields are required only
01940   *         in the case of header phase where no output data DMA
01941   *         transfer is on-going (only input data transfer is enabled
01942   *         in such a case).
01943   * @param  hdma: DMA handle.
01944   * @retval None
01945   */
01946 static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma)
01947 {
01948   uint32_t difflength     = 0;
01949
01950   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01951
01952   /* Disable the DMA transfer for input request  */
01953   CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
01954
01955   if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
01956   {
01957
01958     if (hcryp->CrypInCount != 0)
01959     {
01960       /* Last block is now entered in polling mode, no actual gain in resorting to DMA */
01961       difflength = hcryp->CrypInCount;
01962       hcryp->CrypInCount = 0;
01963
01964       CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF);
01965     }
01966     hcryp->State = HAL_CRYP_STATE_READY;
01967     /* Mark that the header phase is over */
01968     hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
01969   }
01970   /* CCF flag indicating header phase AES processing completion
01971      will be checked at the start of the next phase:
01972      - payload phase (GCM)
01973      - final phase (GMAC or CMAC).
01974     This allows to avoid the Wait on Flag within the IRQ handling.  */
01975
01976   /* Call input data transfer complete callback */
01977   HAL_CRYP_InCpltCallback(hcryp);
01978 }
01979
01980 /**
01981   * @brief  DMA CRYP Output Data process complete callback
01982   *         for GCM, GMAC or CMAC chainging modes.
01983   * @note   This callback is called only in the payload phase.
01984   * @param  hdma: DMA handle.
01985   * @retval None
01986   */
01987 static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma)
01988 {
01989   uint32_t difflength     = 0;
01990   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01991
01992   /* Disable the DMA transfer for output request */
01993   CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
01994
01995   /* Clear CCF Flag */
01996   __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
01997
01998   /* Initiate additional transfer to wrap-up data feeding to the IP */
01999   if (hcryp->CrypInCount != 0)
02000   {
02001     /* Last block is now entered in polling mode, no actual gain in resorting to DMA */
02002     difflength = hcryp->CrypInCount;
02003     hcryp->CrypInCount = 0;
02004
02005     CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
02006   }
02007
02008   /* Change the CRYP state to ready */
02009   hcryp->State = HAL_CRYP_STATE_READY;
02010   /* Mark that the payload phase is over */
02011   hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
02012
02013   /* Call output data transfer complete callback */
02014   HAL_CRYP_OutCpltCallback(hcryp);
02015 }
02016
02017 /**
02018   * @brief  DMA CRYP communication error callback
02019   *         for GCM, GMAC or CMAC chainging modes.
02020   * @param  hdma: DMA handle
02021   * @retval None
02022   */
02023 static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma)
02024 {
02025   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02026
02027   hcryp->State= HAL_CRYP_STATE_ERROR;
02028   hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
02029   HAL_CRYP_ErrorCallback(hcryp);
02030   /* Clear Error Flag */
02031   __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR);
02032 }
02033
02034
02035
02036 /**
02037   * @brief  Handle CRYP block input/output data handling under interruption
02038   *         for GCM, GMAC or CMAC chainging modes.
02039   * @note   The function is called under interruption only, once
02040   *         interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT().
02041   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02042   *         the configuration information for CRYP module
02043   * @retval HAL status
02044   */
02045 HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
02046 {
02047   uint32_t inputaddr   = 0x0;
02048   uint32_t outputaddr  = 0x0;
02049   uint32_t index       = 0x0;
02050   uint32_t addhoc_process = 0;
02051   uint32_t difflength     = 0;
02052   uint32_t difflengthmod4 = 0;
02053   uint32_t mask[3]        = {0x0FF, 0x0FFFF, 0x0FFFFFF};
02054   uint32_t intermediate_data[4] = {0};
02055
02056   if(hcryp->State == HAL_CRYP_STATE_BUSY)
02057   {
02058     /*=====================*/
02059     /* GCM/GMAC init phase */
02060     /*=====================*/
02061     if (hcryp->Init.GCMCMACPhase == CRYP_GCM_INIT_PHASE)
02062     {
02063       /* Clear Computation Complete Flag */
02064       __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02065       /* Disable Computation Complete Flag and Errors Interrupts */
02066       __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
02067       /* Change the CRYP state */
02068       hcryp->State = HAL_CRYP_STATE_READY;
02069
02070       /* Mark that the initialization phase is over */
02071       hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
02072
02073       /* Process Unlocked */
02074       __HAL_UNLOCK(hcryp);
02075       /* Call computation complete callback */
02076       HAL_CRYPEx_ComputationCpltCallback(hcryp);
02077       return HAL_OK;
02078     }
02079     /*===============================*/
02080     /* GCM/GMAC or CMAC header phase */
02081     /*===============================*/
02082     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
02083     {
02084       /* Check if all input header data have been entered */
02085       if (hcryp->CrypInCount == 0)
02086       {
02087         /* Clear Computation Complete Flag */
02088         __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02089         /* Disable Computation Complete Flag and Errors Interrupts */
02090         __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
02091         /* Change the CRYP state */
02092         hcryp->State = HAL_CRYP_STATE_READY;
02093        /* Mark that the header phase is over */
02094         hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
02095
02096        /* Process Unlocked */
02097         __HAL_UNLOCK(hcryp);
02098
02099         /* Call computation complete callback */
02100         HAL_CRYPEx_ComputationCpltCallback(hcryp);
02101
02102         return HAL_OK;
02103       }
02104       /* If suspension flag has been raised, suspend processing */
02105       else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
02106       {
02107         /* Clear CCF Flag */
02108         __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02109
02110         /* reset SuspendRequest */
02111         hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
02112         /* Disable Computation Complete Flag and Errors Interrupts */
02113         __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
02114         /* Change the CRYP state */
02115         hcryp->State = HAL_CRYP_STATE_SUSPENDED;
02116         /* Mark that the header phase is over */
02117         hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
02118
02119        /* Process Unlocked */
02120         __HAL_UNLOCK(hcryp);
02121
02122         return HAL_OK;
02123       }
02124       else /* Carry on feeding input data to the CRYP hardware block */
02125       {
02126         /* Clear Computation Complete Flag */
02127         __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02128         /* Get the last Input data address */
02129         inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02130
02131         /* Increment/decrement instance pointer/counter */
02132         if (hcryp->CrypInCount < 16)
02133         {
02134           difflength = hcryp->CrypInCount;
02135           hcryp->CrypInCount = 0;
02136           addhoc_process = 1;
02137           difflengthmod4 = difflength%4;
02138         }
02139         else
02140         {
02141           hcryp->pCrypInBuffPtr += 16;
02142           hcryp->CrypInCount -= 16;
02143         }
02144
02145         if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
02146         {
02147           if (hcryp->CrypInCount == hcryp->Init.HeaderSize)
02148           {
02149             /* All B blocks will have been entered after the next
02150               four DINR writing, so point at header buffer for
02151               the next iteration */
02152             hcryp->pCrypInBuffPtr = hcryp->Init.Header;
02153           }
02154         }
02155
02156         /* Write the Input block in the Data Input register */
02157         if (addhoc_process == 0)
02158         {
02159           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02160           inputaddr+=4;
02161           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02162           inputaddr+=4;
02163           hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
02164           inputaddr+=4;
02165           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02166         }
02167         else
02168         {
02169           /* Header remainder has size less than 128 bits */
02170           /* Enter complete words when possible */
02171           for(index=0; index < (difflength/4); index ++)
02172           {
02173             /* Write the Input block in the Data Input register */
02174             hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02175             inputaddr+=4;
02176           }
02177           /* Enter incomplete word padded with zeroes if applicable
02178             (case of header length not a multiple of 32-bits) */
02179           if (difflengthmod4 != 0)
02180           {
02181             hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
02182           }
02183           /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
02184           for(index=0; index < (4 - ((difflength+3)/4)); index ++)
02185           {
02186             hcryp->Instance->DINR = 0;
02187           }
02188         }
02189
02190         return HAL_OK;
02191       }
02192     }
02193     /*========================*/
02194     /* GCM/GMAC payload phase */
02195     /*========================*/
02196     else if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
02197     {
02198       /* Get the last output data address */
02199       outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02200
02201      /* Specific handling to manage payload size less than 128 bits
02202         when GCM encryption or decryption is selected.
02203         Check here if the last block output data are read */
02204       if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \
02205           (hcryp->CrypOutCount < 16)                                && \
02206           (hcryp->CrypOutCount > 0))
02207       {
02208         addhoc_process = 1;
02209         difflength = hcryp->CrypOutCount;
02210         difflengthmod4 = difflength%4;
02211         hcryp->CrypOutCount = 0;   /* mark that no more output data will be needed */
02212         /* Retrieve intermediate data */
02213         for(index=0; index < 4; index ++)
02214         {
02215           intermediate_data[index] = hcryp->Instance->DOUTR;
02216         }
02217         /* Retrieve last words of cyphered data */
02218         /* First, retrieve complete output words */
02219         for(index=0; index < (difflength/4); index ++)
02220         {
02221           *(uint32_t*)(outputaddr) = intermediate_data[index];
02222           outputaddr+=4;
02223         }
02224         /* Next, retrieve partial output word if applicable;
02225            at the same time, start masking intermediate data
02226            with a mask of zeros of same size than the padding
02227            applied to the last block of payload */
02228         if (difflengthmod4 != 0)
02229         {
02230           intermediate_data[difflength/4] &= mask[difflengthmod4-1];
02231           *(uint32_t*)(outputaddr) = intermediate_data[difflength/4];
02232         }
02233
02234         if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
02235         {
02236           /* Change again CHMOD configuration to GCM mode */
02237           __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC);
02238
02239           /* Select FINAL phase */
02240           MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
02241
02242           /* Before inserting the intermediate data, carry on masking operation
02243              with a mask of zeros of same size than the padding applied to the last block of payload */
02244           for(index=0; index < (4 - ((difflength+3)/4)); index ++)
02245           {
02246             intermediate_data[(difflength+3)/4+index] = 0;
02247           }
02248
02249           /* Insert intermediate data to trigger an additional DOUTR reading round */
02250           /* Clear Computation Complete Flag before entering new block */
02251           __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02252           for(index=0; index < 4; index ++)
02253           {
02254             hcryp->Instance->DINR = intermediate_data[index];
02255           }
02256         }
02257         else
02258         {
02259           /* Deciphering case: payload phase is now over */
02260           /* Clear Computation Complete Flag */
02261           __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02262           /* Disable Computation Complete Flag and Errors Interrupts */
02263           __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
02264           /* Change the CRYP state */
02265           hcryp->State = HAL_CRYP_STATE_READY;
02266           /* Mark that the payload phase is over */
02267           hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
02268
02269           /* Process Unlocked */
02270           __HAL_UNLOCK(hcryp);
02271
02272           /* Call computation complete callback */
02273           HAL_CRYPEx_ComputationCpltCallback(hcryp);
02274         }
02275         return HAL_OK;
02276       }
02277       else
02278       {
02279         if (hcryp->CrypOutCount != 0)
02280         {
02281           /* Usual case (different than GCM last block < 128 bits ciphering) */
02282           /* Retrieve the last block available from the CRYP hardware block:
02283             read the output block from the Data Output Register */
02284           *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02285           outputaddr+=4;
02286           *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02287           outputaddr+=4;
02288           *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02289           outputaddr+=4;
02290           *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02291
02292           /* Increment/decrement instance pointer/counter */
02293           hcryp->pCrypOutBuffPtr += 16;
02294           hcryp->CrypOutCount -= 16;
02295         }
02296         else
02297         {
02298           /* Software work-around: additional DOUTR reading round to discard the data */
02299           for(index=0; index < 4; index ++)
02300           {
02301             intermediate_data[index] = hcryp->Instance->DOUTR;
02302           }
02303
02304         }
02305       }
02306
02307       /* Check if all output text has been retrieved */
02308       if (hcryp->CrypOutCount == 0)
02309       {
02310         /* Make sure that software-work around is not running before disabling
02311           the interruptions (indeed, if software work-around is running, the
02312           interruptions must not be disabled to allow the additional DOUTR
02313           reading round */
02314         if (addhoc_process == 0)
02315         {
02316           /* Clear Computation Complete Flag */
02317           __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02318           /* Disable Computation Complete Flag and Errors Interrupts */
02319           __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
02320           /* Change the CRYP state */
02321           hcryp->State = HAL_CRYP_STATE_READY;
02322          /* Mark that the payload phase is over */
02323           hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
02324
02325          /* Process Unlocked */
02326           __HAL_UNLOCK(hcryp);
02327
02328           /* Call computation complete callback */
02329           HAL_CRYPEx_ComputationCpltCallback(hcryp);
02330         }
02331
02332         return HAL_OK;
02333       }
02334       /* If suspension flag has been raised, suspend processing */
02335       else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
02336       {
02337         /* Clear CCF Flag */
02338         __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02339
02340         /* reset SuspendRequest */
02341         hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
02342         /* Disable Computation Complete Flag and Errors Interrupts */
02343         __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
02344         /* Change the CRYP state */
02345         hcryp->State = HAL_CRYP_STATE_SUSPENDED;
02346         /* Mark that the header phase is over */
02347         hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
02348
02349        /* Process Unlocked */
02350         __HAL_UNLOCK(hcryp);
02351
02352         return HAL_OK;
02353       }
02354       else /* Output data are still expected, carry on feeding the CRYP
02355                hardware block with input data */
02356       {
02357         /* Clear Computation Complete Flag */
02358         __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02359         /* Get the last Input data address */
02360         inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
02361
02362         /* Usual input data feeding case */
02363         if (hcryp->CrypInCount < 16)
02364         {
02365           difflength = (uint32_t) (hcryp->CrypInCount);
02366           difflengthmod4 = difflength%4;
02367           hcryp->CrypInCount = 0;
02368
02369           /* Software workaround applied to GCM encryption only */
02370           if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
02371           {
02372             /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
02373             __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
02374           }
02375
02376           /*  Insert the last block (which size is inferior to 128 bits) padded with zeroes
02377               to have a complete block of 128 bits */
02378           for(index=0; index < (difflength/4); index ++)
02379           {
02380             /* Write the Input block in the Data Input register */
02381             hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02382             inputaddr+=4;
02383           }
02384           /* If required, manage input data size not multiple of 32 bits */
02385           if (difflengthmod4 != 0)
02386           {
02387             hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
02388           }
02389           /* Wrap-up in padding with zero-words if applicable */
02390           for(index=0; index < (4 - ((difflength+3)/4)); index ++)
02391           {
02392             hcryp->Instance->DINR = 0;
02393           }
02394
02395         }
02396         else
02397         {
02398           hcryp->pCrypInBuffPtr += 16;
02399           hcryp->CrypInCount -= 16;
02400
02401           /* Write the Input block in the Data Input register */
02402           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02403           inputaddr+=4;
02404           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02405           inputaddr+=4;
02406           hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
02407           inputaddr+=4;
02408           hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02409         }
02410
02411
02412         return HAL_OK;
02413       }
02414     }
02415     /*==============================*/
02416     /* GCM/GMAC or CMAC final phase */
02417     /*==============================*/
02418     else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_FINAL_PHASE)
02419     {
02420       /* Clear Computation Complete Flag */
02421       __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02422
02423       /* Get the last output data address */
02424       outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
02425
02426       /* Retrieve the last expected data from the CRYP hardware block:
02427          read the output block from the Data Output Register */
02428       *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02429       outputaddr+=4;
02430       *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02431       outputaddr+=4;
02432       *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02433       outputaddr+=4;
02434       *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02435
02436       /* Disable Computation Complete Flag and Errors Interrupts */
02437       __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
02438       /* Change the CRYP state */
02439       hcryp->State = HAL_CRYP_STATE_READY;
02440       /* Mark that the header phase is over */
02441       hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
02442
02443       /* Disable the Peripheral */
02444       __HAL_CRYP_DISABLE();
02445       /* Process Unlocked */
02446        __HAL_UNLOCK(hcryp);
02447
02448       /* Call computation complete callback */
02449       HAL_CRYPEx_ComputationCpltCallback(hcryp);
02450
02451       return HAL_OK;
02452     }
02453     else
02454     {
02455       /* Clear Computation Complete Flag */
02456       __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02457       hcryp->State = HAL_CRYP_STATE_ERROR;
02458       __HAL_UNLOCK(hcryp);
02459       return HAL_ERROR;
02460     }
02461   }
02462   else
02463   {
02464     return HAL_BUSY;
02465   }
02466 }
02467
02468
02469
02470 /**
02471   * @brief  Set the DMA configuration and start the DMA transfer
02472   *         for GCM, GMAC or CMAC chainging modes.
02473   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02474   *         the configuration information for CRYP module.
02475   * @param  inputaddr: Address of the Input buffer.
02476   * @param  Size: Size of the Input buffer un bytes, must be a multiple of 16.
02477   * @param  outputaddr: Address of the Output buffer, null pointer when no output DMA stream
02478   *         has to be configured.
02479   * @retval None
02480   */
02481 static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
02482 {
02483
02484   /* Set the input CRYP DMA transfer complete callback */
02485   hcryp->hdmain->XferCpltCallback = CRYP_GCMCMAC_DMAInCplt;
02486   /* Set the DMA error callback */
02487   hcryp->hdmain->XferErrorCallback = CRYP_GCMCMAC_DMAError;
02488
02489   if (outputaddr != 0)
02490   {
02491     /* Set the output CRYP DMA transfer complete callback */
02492     hcryp->hdmaout->XferCpltCallback = CRYP_GCMCMAC_DMAOutCplt;
02493     /* Set the DMA error callback */
02494     hcryp->hdmaout->XferErrorCallback = CRYP_GCMCMAC_DMAError;
02495   }
02496
02497   /* Enable the CRYP peripheral */
02498   __HAL_CRYP_ENABLE();
02499
02500   /* Enable the DMA input stream */
02501   HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
02502
02503   /* Enable the DMA input request */
02504   SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
02505
02506
02507   if (outputaddr != 0)
02508   {
02509     /* Enable the DMA output stream */
02510     HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
02511
02512     /* Enable the DMA output request */
02513     SET_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
02514   }
02515 }
02516
02517
02518
02519 /**
02520   * @brief  Write/read input/output data in polling mode.
02521   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02522   *         the configuration information for CRYP module.
02523   * @param  Input: Pointer to the Input buffer.
02524   * @param  Ilength: Length of the Input buffer in bytes, must be a multiple of 16.
02525   * @param  Output: Pointer to the returned buffer.
02526   * @param  Timeout: Specify Timeout value.
02527   * @retval HAL status
02528   */
02529 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
02530 {
02531   uint32_t index = 0;
02532   uint32_t inputaddr  = (uint32_t)Input;
02533   uint32_t outputaddr = (uint32_t)Output;
02534
02535
02536   for(index=0; (index < Ilength); index += 16)
02537   {
02538     /* Write the Input block in the Data Input register */
02539     hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02540     inputaddr+=4;
02541     hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02542     inputaddr+=4;
02543     hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
02544     inputaddr+=4;
02545     hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02546     inputaddr+=4;
02547
02548     /* Wait for CCF flag to be raised */
02549     if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
02550     {
02551       hcryp->State = HAL_CRYP_STATE_READY;
02552       __HAL_UNLOCK(hcryp);
02553       return HAL_TIMEOUT;
02554     }
02555
02556     /* Clear CCF Flag */
02557     __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02558
02559     /* Read the Output block from the Data Output Register */
02560     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02561     outputaddr+=4;
02562     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02563     outputaddr+=4;
02564     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02565     outputaddr+=4;
02566     *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
02567     outputaddr+=4;
02568
02569     /* If the suspension flag has been raised and if the processing is not about
02570        to end, suspend processing */
02571     if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Ilength))
02572     {
02573       /* Reset SuspendRequest */
02574       hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
02575
02576       /* Save current reading and writing locations of Input and Output buffers */
02577       hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;
02578       hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;
02579       /* Save the number of bytes that remain to be processed at this point */
02580       hcryp->CrypInCount     =  Ilength - (index+16);
02581
02582       /* Change the CRYP state */
02583       hcryp->State = HAL_CRYP_STATE_SUSPENDED;
02584
02585       return HAL_OK;
02586     }
02587
02588
02589   }
02590   /* Return function status */
02591   return HAL_OK;
02592
02593 }
02594
02595
02596
02597
02598
02599 /**
02600   * @brief  Read derivative key in polling mode when CRYP hardware block is set
02601   *         in key derivation operating mode (mode 2).
02602   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02603   *         the configuration information for CRYP module.
02604   * @param  Output: Pointer to the returned buffer.
02605   * @param  Timeout: Specify Timeout value.
02606   * @retval HAL status
02607   */
02608 static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout)
02609 {
02610   uint32_t outputaddr = (uint32_t)Output;
02611
02612   /* Wait for CCF flag to be raised */
02613   if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
02614   {
02615     hcryp->State = HAL_CRYP_STATE_READY;
02616     __HAL_UNLOCK(hcryp);
02617     return HAL_TIMEOUT;
02618   }
02619   /* Clear CCF Flag */
02620   __HAL_CRYP_CLEAR_FLAG( CRYP_CCF_CLEAR);
02621
02622     /* Read the derivative key from the AES_KEYRx registers */
02623   if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
02624   {
02625     *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);
02626     outputaddr+=4;
02627     *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);
02628     outputaddr+=4;
02629     *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);
02630     outputaddr+=4;
02631     *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);
02632     outputaddr+=4;
02633   }
02634
02635     *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);
02636     outputaddr+=4;
02637     *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);
02638     outputaddr+=4;
02639     *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);
02640     outputaddr+=4;
02641     *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);
02642
02643
02644   /* Return function status */
02645   return HAL_OK;
02646 }
02647
02648 /**
02649   * @brief  Set the DMA configuration and start the DMA transfer.
02650   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02651   *         the configuration information for CRYP module.
02652   * @param  inputaddr: Address of the Input buffer.
02653   * @param  Size: Size of the Input buffer in bytes, must be a multiple of 16.
02654   * @param  outputaddr: Address of the Output buffer.
02655   * @retval None
02656   */
02657 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
02658 {
02659   /* Set the CRYP DMA transfer complete callback */
02660   hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
02661   /* Set the DMA error callback */
02662   hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
02663
02664   /* Set the CRYP DMA transfer complete callback */
02665   hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
02666   /* Set the DMA error callback */
02667   hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
02668
02669   /* Enable the DMA input stream */
02670   HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
02671
02672   /* Enable the DMA output stream */
02673   HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
02674
02675   /* Enable In and Out DMA requests */
02676   SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
02677
02678   /* Enable the CRYP peripheral */
02679   __HAL_CRYP_ENABLE();
02680 }
02681
02682
02683 /**
02684   * @brief  Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
02685   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02686   *         the configuration information for CRYP module.
02687   * @param  Timeout: Timeout duration.
02688   * @retval HAL status
02689   */
02690 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02691 {
02692   uint32_t tickstart = 0;
02693
02694   /* Get timeout */
02695   tickstart = HAL_GetTick();
02696
02697   while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
02698   {
02699     /* Check for the Timeout */
02700     if(Timeout != HAL_MAX_DELAY)
02701     {
02702       if((HAL_GetTick() - tickstart ) > Timeout)
02703       {
02704         return HAL_TIMEOUT;
02705       }
02706     }
02707   }
02708   return HAL_OK;
02709 }
02710
02711 /**
02712   * @brief  Wait for Busy Flag to be reset during a GCM payload encryption process suspension.
02713   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02714   *         the configuration information for CRYP module.
02715   * @param  Timeout: Timeout duration.
02716   * @retval HAL status
02717   */
02718 static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02719 {
02720   uint32_t tickstart = 0;
02721
02722   /* Get timeout */
02723   tickstart = HAL_GetTick();
02724
02725   while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY))
02726   {
02727     /* Check for the Timeout */
02728     if(Timeout != HAL_MAX_DELAY)
02729     {
02730       if((HAL_GetTick() - tickstart ) > Timeout)
02731       {
02732         return HAL_TIMEOUT;
02733       }
02734     }
02735   }
02736   return HAL_OK;
02737 }
02738
02739
02740 /**
02741   * @brief  DMA CRYP Input Data process complete callback.
02742   * @param  hdma: DMA handle.
02743   * @retval None
02744   */
02745 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
02746 {
02747   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02748
02749   /* Disable the DMA transfer for input request  */
02750   CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
02751
02752   /* Call input data transfer complete callback */
02753   HAL_CRYP_InCpltCallback(hcryp);
02754 }
02755
02756 /**
02757   * @brief  DMA CRYP Output Data process complete callback.
02758   * @param  hdma: DMA handle.
02759   * @retval None
02760   */
02761 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
02762 {
02763   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02764
02765   /* Disable the DMA transfer for output request */
02766   CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
02767
02768   /* Clear CCF Flag */
02769   __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02770
02771   /* Disable CRYP */
02772   __HAL_CRYP_DISABLE();
02773
02774   /* Change the CRYP state to ready */
02775   hcryp->State = HAL_CRYP_STATE_READY;
02776
02777   /* Call output data transfer complete callback */
02778   HAL_CRYP_OutCpltCallback(hcryp);
02779 }
02780
02781 /**
02782   * @brief  DMA CRYP communication error callback.
02783   * @param  hdma: DMA handle.
02784   * @retval None
02785   */
02786 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
02787 {
02788   CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02789
02790   hcryp->State= HAL_CRYP_STATE_ERROR;
02791   hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
02792   HAL_CRYP_ErrorCallback(hcryp);
02793   /* Clear Error Flag */
02794   __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR);
02795 }
02796
02797 /**
02798   * @brief  Last header or payload block padding when size is not a multiple of 128 bits.
02799   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
02800   *         the configuration information for CRYP module.
02801   * @param  difflength: size remainder after having fed all complete 128-bit blocks.
02802   * @param  polling: specifies whether or not polling on CCF must be done after having
02803   *                  entered a complete block.
02804   * @retval None
02805   */
02806 static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling)
02807 {
02808   uint32_t index          = 0;
02809   uint32_t difflengthmod4 = difflength%4;
02810   uint32_t inputaddr      = (uint32_t)hcryp->pCrypInBuffPtr;
02811   uint32_t outputaddr     = (uint32_t)hcryp->pCrypOutBuffPtr;
02812   uint32_t mask[3]        = {0x0FF, 0x0FFFF, 0x0FFFFFF};
02813   uint32_t intermediate_data[4] = {0};
02814
02815   /* Software workaround applied to GCM encryption only */
02816   if ((hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) &&
02817       (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT))
02818   {
02819     /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
02820     __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
02821   }
02822
02823   /* Wrap-up entering header data */
02824   /* Enter complete words when possible */
02825   for(index=0; index < (difflength/4); index ++)
02826   {
02827     /* Write the Input block in the Data Input register */
02828     hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
02829     inputaddr+=4;
02830   }
02831   /* Enter incomplete word padded with zeroes if applicable
02832     (case of header length not a multiple of 32-bits) */
02833   if (difflengthmod4 != 0)
02834   {
02835     hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
02836   }
02837   /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
02838   for(index=0; index < (4 - ((difflength+3)/4)); index ++)
02839   {
02840     hcryp->Instance->DINR = 0;
02841   }
02842
02843   if (polling == CRYP_POLLING_ON)
02844   {
02845                 if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
02846     {
02847         hcryp->State = HAL_CRYP_STATE_READY;
02848         __HAL_UNLOCK(hcryp);
02849        HAL_CRYP_ErrorCallback(hcryp);
02850       }
02851
02852     /* Clear CCF Flag */
02853     __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02854   }
02855
02856         /* if payload */
02857   if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
02858         {
02859
02860     /* Retrieve intermediate data */
02861     for(index=0; index < 4; index ++)
02862     {
02863       intermediate_data[index] = hcryp->Instance->DOUTR;
02864     }
02865     /* Retrieve last words of cyphered data */
02866     /* First, retrieve complete output words */
02867     for(index=0; index < (difflength/4); index ++)
02868     {
02869       *(uint32_t*)(outputaddr) = intermediate_data[index];
02870       outputaddr+=4;
02871     }
02872     /* Next, retrieve partial output word if applicable;
02873        at the same time, start masking intermediate data
02874        with a mask of zeros of same size than the padding
02875        applied to the last block of payload */
02876     if (difflengthmod4 != 0)
02877     {
02878       intermediate_data[difflength/4] &= mask[difflengthmod4-1];
02879       *(uint32_t*)(outputaddr) = intermediate_data[difflength/4];
02880     }
02881
02882     /* Software workaround applied to GCM encryption only */
02883     if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
02884     {
02885       /* Change again CHMOD configuration to GCM mode */
02886       __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC);
02887
02888       /* Select FINAL phase */
02889       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
02890
02891       /* Before inserting the intermediate data, carry on masking operation
02892          with a mask of zeros of same size than the padding applied to the last block of payload */
02893       for(index=0; index < (4 - ((difflength+3)/4)); index ++)
02894       {
02895         intermediate_data[(difflength+3)/4+index] = 0;
02896       }
02897       /* Insert intermediate data */
02898       for(index=0; index < 4; index ++)
02899       {
02900         hcryp->Instance->DINR = intermediate_data[index];
02901       }
02902
02903       /*  Wait for completion, and read data on DOUT. This data is to discard. */
02904       if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
02905       {
02906         hcryp->State = HAL_CRYP_STATE_READY;
02907         __HAL_UNLOCK(hcryp);
02908         HAL_CRYP_ErrorCallback(hcryp);
02909       }
02910
02911       /* Read data to discard */
02912       /* Clear CCF Flag */
02913       __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
02914       for(index=0; index < 4; index ++)
02915       {
02916         intermediate_data[index] = hcryp->Instance->DOUTR;
02917       }
02918
02919           } /* if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) */
02920         }   /* if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) */
02921
02922 }
02923
02924 /**
02925   * @}
02926   */
02927
02928 /**
02929   * @}
02930   */
02931
02932 /**
02933   * @}
02934   */
02935
02936 #endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx) */
02937
02938 #endif /* HAL_CRYP_MODULE_ENABLED */
02939 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_cryp_ex.h Source File

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stm32l4xx_hal_cryp_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_cryp_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of CRYPEx HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_CRYP_EX_H
00040 #define __STM32L4xx_HAL_CRYP_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx)
00047
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32l4xx_hal_def.h"
00051
00052 /** @addtogroup STM32L4xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup CRYPEx
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /* Exported constants --------------------------------------------------------*/
00062 /* Exported functions --------------------------------------------------------*/
00063
00064 /** @addtogroup CRYPEx_Exported_Functions
00065   * @{
00066   */
00067
00068 /** @addtogroup CRYPEx_Exported_Functions_Group1
00069   * @{
00070   */
00071
00072 /* CallBack functions  ********************************************************/
00073 void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
00074
00075 /**
00076   * @}
00077   */
00078
00079 /** @addtogroup CRYPEx_Exported_Functions_Group2
00080   * @{
00081   */
00082
00083 /* AES encryption/decryption processing functions  ****************************/
00084 HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);
00085 HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
00086 HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
00087
00088 /* AES encryption/decryption/authentication processing functions  *************/
00089 HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);
00090 HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
00091 HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
00092
00093 /**
00094   * @}
00095   */
00096
00097 /** @addtogroup CRYPEx_Exported_Functions_Group3
00098   * @{
00099   */
00100
00101 /* AES suspension/resumption functions  ***************************************/
00102 void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
00103 void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
00104 void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
00105 void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
00106 void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);
00107 void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);
00108 void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
00109 void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
00110 void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
00111
00112 /**
00113   * @}
00114   */
00115
00116
00117 /**
00118   * @}
00119   */
00120
00121 /* Private functions -----------------------------------------------------------*/
00122 /** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions
00123   * @{
00124   */
00125 HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
00126
00127 /**
00128   * @}
00129   */
00130
00131
00132 /**
00133   * @}
00134   */
00135
00136 /**
00137   * @}
00138   */
00139
00140 #endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined(STM32L485xx) || defined(STM32L486xx) */
00141
00142 #ifdef __cplusplus
00143 }
00144 #endif
00145
00146 #endif /* __STM32L4xx_HAL_CRYP_EX_H */
00147
00148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dac.c Source File

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stm32l4xx_hal_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_dac.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   DAC HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   *
00016   @verbatim
00017   ==============================================================================
00018                       ##### DAC Peripheral features #####
00019   ==============================================================================
00020     [..]
00021       *** DAC Channels ***
00022       ====================
00023     [..]
00024     STM32L4 devices integrate two 12-bit Digital Analog Converters
00025
00026     The 2 converters (i.e. channel1 & channel2)
00027     can be used independently or simultaneously (dual mode):
00028       (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
00029           peripherals (ex. OPAMPs, comparators).
00030       (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
00031           peripherals (ex. OPAMPs, comparators).
00032
00033       *** DAC Triggers ***
00034       ====================
00035     [..]
00036     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
00037     and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
00038     [..]
00039     Digital to Analog conversion can be triggered by:
00040       (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
00041           The used pin (GPIOx_PIN_9) must be configured in input mode.
00042
00043       (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7
00044           (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)
00045
00046       (#) Software using DAC_TRIGGER_SOFTWARE
00047
00048       *** DAC Buffer mode feature ***
00049       ===============================
00050       [..]
00051       Each DAC channel integrates an output buffer that can be used to
00052       reduce the output impedance, and to drive external loads directly
00053       without having to add an external operational amplifier.
00054       To enable, the output buffer use
00055       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
00056       [..]
00057       (@) Refer to the device datasheet for more details about output
00058           impedance value with and without output buffer.
00059
00060       *** DAC connect feature ***
00061       ===============================
00062       [..]
00063       Each DAC channel can be connected internally.
00064       To connect, use
00065       sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
00066
00067       *** GPIO configurations guidelines ***
00068       =====================
00069       [..]
00070       When a DAC channel is used (ex channel1 on PA4) and the other is not
00071       (ex channel2 on PA5 is configured in Analog and disabled).
00072       Channel1 may disturb channel2 as coupling effect.
00073       Note that there is no coupling on channel2 as soon as channel2 is turned on.
00074       Coupling on adjacent channel could be avoided as follows:
00075       when unused PA5 is configured as INPUT PULL-UP or DOWN.
00076       PA5 is configured in ANALOG just before it is turned on.
00077
00078       *** DAC Sample and Hold feature ***
00079       ========================
00080       [..]
00081       For each converter, 2 modes are supported: normal mode and
00082       "sample and hold" mode (i.e. low power mode).
00083       In the sample and hold mode, the DAC core converts data, then holds the
00084       converted voltage on a capacitor. When not converting, the DAC cores and
00085       buffer are completely turned off between samples and the DAC output is
00086       tri-stated, therefore  reducing the overall power consumption. A new
00087       stabilization period is needed before each new conversion.
00088
00089       The sample and hold allow setting internal or external voltage @
00090       low power consumption cost (output value can be at any given rate either
00091       by CPU or DMA).
00092
00093       The Sample and hold block and registers uses either LSI & run in
00094       several power modes: run mode, sleep mode, low power run, low power sleep
00095       mode & stop1 mode.
00096
00097       Low power stop1 mode allows only static conversion.
00098
00099       To enable Sample and Hold mode
00100       Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
00101       RCC_LSI_ON parameters.
00102
00103       Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
00104          & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
00105            DAC_HoldTime & DAC_RefreshTime;
00106
00107
00108
00109        *** DAC calibration feature ***
00110        ===================================
00111       [..]
00112        (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
00113        (++) Calibration aims at correcting some offset of output buffer.
00114        (++) The DAC uses either factory calibration settings OR user defined
00115            calibration (trimming) settings (i.e. trimming mode).
00116        (++) The user defined settings can be figured out using self calibration
00117            handled by HAL_DACEx_SelfCalibrate.
00118        (++) HAL_DACEx_SelfCalibrate:
00119        (+++) Runs automatically the calibration.
00120        (+++) Enables the user trimming mode
00121        (+++) Updates a structure with trimming values with fresh calibration
00122             results.
00123             The user may store the calibration results for larger
00124             (ex monitoring the trimming as a function of temperature
00125             for instance)
00126
00127        *** DAC wave generation feature ***
00128        ===================================
00129        [..]
00130        Both DAC channels can be used to generate
00131          (#) Noise wave
00132          (#) Triangle wave
00133
00134        *** DAC data format ***
00135        =======================
00136        [..]
00137        The DAC data format can be:
00138          (#) 8-bit right alignment using DAC_ALIGN_8B_R
00139          (#) 12-bit left alignment using DAC_ALIGN_12B_L
00140          (#) 12-bit right alignment using DAC_ALIGN_12B_R
00141
00142        *** DAC data value to voltage correspondence ***
00143        ================================================
00144        [..]
00145        The analog output voltage on each DAC channel pin is determined
00146        by the following equation:
00147        [..]
00148        DAC_OUTx = VREF+ * DOR / 4095
00149        (+) with  DOR is the Data Output Register
00150        [..]
00151           VEF+ is the input voltage reference (refer to the device datasheet)
00152        [..]
00153         e.g. To set DAC_OUT1 to 0.7V, use
00154        (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
00155
00156        *** DMA requests ***
00157        =====================
00158        [..]
00159        A DMA1 request can be generated when an external trigger (but not a software trigger)
00160        occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
00161        DMA requests are mapped as following:
00162       (#) DAC channel1: mapped either on
00163       (++) DMA1 request 6 channel3
00164       (++) or DMA2 request channel4 which must be already configured
00165       (#) DAC channel2: mapped either on
00166       (++) DMA1 request 5 channel4
00167       (++) or DMA2 request 3 channel5 which must be already configured
00168      [..]
00169     (@) For Dual mode and specific signal (Triangle and noise) generation please
00170         refer to Extended Features Driver description
00171
00172                       ##### How to use this driver #####
00173   ==============================================================================
00174     [..]
00175       (+) DAC APB clock must be enabled to get write access to DAC
00176           registers using HAL_DAC_Init()
00177       (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
00178       (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
00179       (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
00180
00181      *** Calibration mode IO operation ***
00182      ======================================
00183      [..]
00184        (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
00185        (+) Run the calibration using HAL_DACEx_SelfCalibrate()
00186        (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
00187
00188      *** Polling mode IO operation ***
00189      =================================
00190      [..]
00191        (+) Start the DAC peripheral using HAL_DAC_Start()
00192        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
00193        (+) Stop the DAC peripheral using HAL_DAC_Stop()
00194
00195      *** DMA mode IO operation ***
00196      ==============================
00197      [..]
00198        (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
00199            of data to be transferred at each end of conversion
00200        (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00201            function is executed and user can add his own code by customization of function pointer
00202            HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00203        (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00204            function is executed and user can add his own code by customization of function pointer
00205            HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
00206        (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
00207             add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
00208        (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
00209            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
00210            function is executed and user can add his own code by customization of function pointer
00211            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
00212            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
00213        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
00214
00215      *** DAC HAL driver macros list ***
00216      =============================================
00217      [..]
00218        Below the list of most used macros in DAC HAL driver.
00219
00220       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
00221       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
00222       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
00223       (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
00224
00225      [..]
00226       (@) You can refer to the DAC HAL driver header file for more useful macros
00227
00228  @endverbatim
00229   ******************************************************************************
00230   * @attention
00231   *
00232   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00233   *
00234   * Redistribution and use in source and binary forms, with or without modification,
00235   * are permitted provided that the following conditions are met:
00236   *   1. Redistributions of source code must retain the above copyright notice,
00237   *      this list of conditions and the following disclaimer.
00238   *   2. Redistributions in binary form must reproduce the above copyright notice,
00239   *      this list of conditions and the following disclaimer in the documentation
00240   *      and/or other materials provided with the distribution.
00241   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00242   *      may be used to endorse or promote products derived from this software
00243   *      without specific prior written permission.
00244   *
00245   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00246   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00247   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00248   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00249   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00250   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00251   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00252   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00253   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00254   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00255   *
00256   ******************************************************************************
00257   */
00258
00259
00260 /* Includes ------------------------------------------------------------------*/
00261 #include "stm32l4xx_hal.h"
00262
00263 /** @addtogroup STM32L4xx_HAL_Driver
00264   * @{
00265   */
00266
00267   /** @defgroup DAC DAC
00268   * @brief DAC driver modules
00269   * @{
00270   */
00271
00272 #ifdef HAL_DAC_MODULE_ENABLED
00273
00274 /* Private typedef -----------------------------------------------------------*/
00275 /* Private define ------------------------------------------------------------*/
00276 /* Private constants ---------------------------------------------------------*/
00277 /** @addtogroup DAC_Private_Constants DAC Private Constants
00278   * @{
00279   */
00280 #define TIMEOUT_DAC_CALIBCONFIG    ((uint32_t)1)  /* 1ms                  */
00281 /**
00282   * @}
00283   */
00284
00285 /* Private macro -------------------------------------------------------------*/
00286 /* Private macro -------------------------------------------------------------*/
00287 /* Private variables ---------------------------------------------------------*/
00288 /* Private function prototypes -----------------------------------------------*/
00289 /** @defgroup DAC_Private_Functions DAC Private Functions
00290   * @{
00291   */
00292 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
00293 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
00294 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
00295 /**
00296   * @}
00297   */
00298 /* Exported functions -------------------------------------------------------*/
00299
00300 /** @defgroup DAC_Exported_Functions DAC Exported Functions
00301   * @{
00302   */
00303
00304 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
00305  *  @brief    Initialization and Configuration functions
00306  *
00307 @verbatim
00308   ==============================================================================
00309               ##### Initialization and de-initialization functions #####
00310   ==============================================================================
00311     [..]  This section provides functions allowing to:
00312       (+) Initialize and configure the DAC.
00313       (+) De-initialize the DAC.
00314
00315 @endverbatim
00316   * @{
00317   */
00318
00319 /**
00320   * @brief  Initialize the DAC peripheral according to the specified parameters
00321   *         in the DAC_InitStruct and initialize the associated handle.
00322   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00323   *         the configuration information for the specified DAC.
00324   * @retval HAL status
00325   */
00326 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
00327 {
00328   /* Check DAC handle */
00329   if(hdac == NULL)
00330   {
00331      return HAL_ERROR;
00332   }
00333   /* Check the parameters */
00334   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00335
00336   if(hdac->State == HAL_DAC_STATE_RESET)
00337   {
00338     /* Allocate lock resource and initialize it */
00339     hdac->Lock = HAL_UNLOCKED;
00340
00341     /* Init the low level hardware */
00342     HAL_DAC_MspInit(hdac);
00343   }
00344
00345   /* Initialize the DAC state*/
00346   hdac->State = HAL_DAC_STATE_BUSY;
00347
00348   /* Set DAC error code to none */
00349   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00350
00351   /* Initialize the DAC state*/
00352   hdac->State = HAL_DAC_STATE_READY;
00353
00354   /* Return function status */
00355   return HAL_OK;
00356 }
00357
00358 /**
00359   * @brief  Deinitialize the DAC peripheral registers to their default reset values.
00360   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00361   *         the configuration information for the specified DAC.
00362   * @retval HAL status
00363   */
00364 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
00365 {
00366   /* Check DAC handle */
00367   if(hdac == NULL)
00368   {
00369      return HAL_ERROR;
00370   }
00371
00372   /* Check the parameters */
00373   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00374
00375   /* Change DAC state */
00376   hdac->State = HAL_DAC_STATE_BUSY;
00377
00378   /* DeInit the low level hardware */
00379   HAL_DAC_MspDeInit(hdac);
00380
00381   /* Set DAC error code to none */
00382   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00383
00384   /* Change DAC state */
00385   hdac->State = HAL_DAC_STATE_RESET;
00386
00387   /* Release Lock */
00388   __HAL_UNLOCK(hdac);
00389
00390   /* Return function status */
00391   return HAL_OK;
00392 }
00393
00394 /**
00395   * @brief  Initialize the DAC MSP.
00396   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00397   *         the configuration information for the specified DAC.
00398   * @retval None
00399   */
00400 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
00401 {
00402   /* Prevent unused argument(s) compilation warning */
00403   UNUSED(hdac);
00404
00405   /* NOTE : This function should not be modified, when the callback is needed,
00406             the HAL_DAC_MspInit could be implemented in the user file
00407    */
00408 }
00409
00410 /**
00411   * @brief  DeInitialize the DAC MSP.
00412   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00413   *         the configuration information for the specified DAC.
00414   * @retval None
00415   */
00416 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
00417 {
00418   /* Prevent unused argument(s) compilation warning */
00419   UNUSED(hdac);
00420
00421   /* NOTE : This function should not be modified, when the callback is needed,
00422             the HAL_DAC_MspDeInit could be implemented in the user file
00423    */
00424 }
00425
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
00431  *  @brief    IO operation functions
00432  *
00433 @verbatim
00434   ==============================================================================
00435              ##### IO operation functions #####
00436   ==============================================================================
00437     [..]  This section provides functions allowing to:
00438       (+) Start conversion.
00439       (+) Stop conversion.
00440       (+) Start conversion and enable DMA transfer.
00441       (+) Stop conversion and disable DMA transfer.
00442       (+) Get result of conversion.
00443
00444 @endverbatim
00445   * @{
00446   */
00447
00448 /**
00449   * @brief  Enables DAC and starts conversion of channel.
00450   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00451   *         the configuration information for the specified DAC.
00452   * @param  Channel: The selected DAC channel.
00453   *          This parameter can be one of the following values:
00454   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00455   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00456   * @retval HAL status
00457   */
00458 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
00459 {
00460   /* Check the parameters */
00461   assert_param(IS_DAC_CHANNEL(Channel));
00462
00463   /* Process locked */
00464   __HAL_LOCK(hdac);
00465
00466   /* Change DAC state */
00467   hdac->State = HAL_DAC_STATE_BUSY;
00468
00469   /* Enable the Peripheral */
00470   __HAL_DAC_ENABLE(hdac, Channel);
00471
00472   if(Channel == DAC_CHANNEL_1)
00473   {
00474     /* Check if software trigger enabled */
00475     if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
00476     {
00477       /* Enable the selected DAC software conversion */
00478       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
00479     }
00480   }
00481   else
00482   {
00483     /* Check if software trigger enabled */
00484     if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
00485     {
00486       /* Enable the selected DAC software conversion*/
00487       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
00488     }
00489   }
00490
00491   /* Change DAC state */
00492   hdac->State = HAL_DAC_STATE_READY;
00493
00494   /* Process unlocked */
00495   __HAL_UNLOCK(hdac);
00496
00497   /* Return function status */
00498   return HAL_OK;
00499 }
00500
00501 /**
00502   * @brief  Disables DAC and stop conversion of channel.
00503   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00504   *         the configuration information for the specified DAC.
00505   * @param  Channel: The selected DAC channel.
00506   *          This parameter can be one of the following values:
00507   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00508   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00509   * @retval HAL status
00510   */
00511 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
00512 {
00513   /* Check the parameters */
00514   assert_param(IS_DAC_CHANNEL(Channel));
00515
00516   /* Disable the Peripheral */
00517   __HAL_DAC_DISABLE(hdac, Channel);
00518
00519   /* Change DAC state */
00520   hdac->State = HAL_DAC_STATE_READY;
00521
00522   /* Return function status */
00523   return HAL_OK;
00524 }
00525
00526 /**
00527   * @brief  Enables DAC and starts conversion of channel.
00528   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00529   *         the configuration information for the specified DAC.
00530   * @param  Channel: The selected DAC channel.
00531   *          This parameter can be one of the following values:
00532   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00533   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00534   * @param  pData: The destination peripheral Buffer address.
00535   * @param  Length: The length of data to be transferred from memory to DAC peripheral
00536   * @param  Alignment: Specifies the data alignment for DAC channel.
00537   *          This parameter can be one of the following values:
00538   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00539   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00540   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00541   * @retval HAL status
00542   */
00543 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
00544 {
00545   uint32_t tmpreg = 0;
00546
00547   /* Check the parameters */
00548   assert_param(IS_DAC_CHANNEL(Channel));
00549   assert_param(IS_DAC_ALIGN(Alignment));
00550
00551   /* Process locked */
00552   __HAL_LOCK(hdac);
00553
00554   /* Change DAC state */
00555   hdac->State = HAL_DAC_STATE_BUSY;
00556
00557   if(Channel == DAC_CHANNEL_1)
00558   {
00559     /* Set the DMA transfer complete callback for channel1 */
00560     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00561
00562     /* Set the DMA half transfer complete callback for channel1 */
00563     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00564
00565     /* Set the DMA error callback for channel1 */
00566     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00567
00568     /* Enable the selected DAC channel1 DMA request */
00569     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00570
00571     /* Case of use of channel 1 */
00572     switch(Alignment)
00573     {
00574       case DAC_ALIGN_12B_R:
00575         /* Get DHR12R1 address */
00576         tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00577         break;
00578       case DAC_ALIGN_12B_L:
00579         /* Get DHR12L1 address */
00580         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00581         break;
00582       case DAC_ALIGN_8B_R:
00583         /* Get DHR8R1 address */
00584         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00585         break;
00586       default:
00587         break;
00588     }
00589   }
00590   else
00591   {
00592     /* Set the DMA transfer complete callback for channel2 */
00593     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00594
00595     /* Set the DMA half transfer complete callback for channel2 */
00596     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00597
00598     /* Set the DMA error callback for channel2 */
00599     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00600
00601     /* Enable the selected DAC channel2 DMA request */
00602     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00603
00604     /* Case of use of channel 2 */
00605     switch(Alignment)
00606     {
00607       case DAC_ALIGN_12B_R:
00608         /* Get DHR12R2 address */
00609         tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
00610         break;
00611       case DAC_ALIGN_12B_L:
00612         /* Get DHR12L2 address */
00613         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
00614         break;
00615       case DAC_ALIGN_8B_R:
00616         /* Get DHR8R2 address */
00617         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
00618         break;
00619       default:
00620         break;
00621     }
00622   }
00623
00624   /* Enable the DMA channel */
00625   if(Channel == DAC_CHANNEL_1)
00626   {
00627     /* Enable the DAC DMA underrun interrupt */
00628     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00629
00630     /* Enable the DMA channel */
00631     HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00632   }
00633   else
00634   {
00635     /* Enable the DAC DMA underrun interrupt */
00636     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00637
00638     /* Enable the DMA channel */
00639     HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00640   }
00641
00642   /* Process Unlocked */
00643   __HAL_UNLOCK(hdac);
00644
00645   /* Enable the Peripheral */
00646   __HAL_DAC_ENABLE(hdac, Channel);
00647
00648   /* Return function status */
00649   return HAL_OK;
00650 }
00651
00652 /**
00653   * @brief  Disables DAC and stop conversion of channel.
00654   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00655   *         the configuration information for the specified DAC.
00656   * @param  Channel: The selected DAC channel.
00657   *          This parameter can be one of the following values:
00658   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00659   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00660   * @retval HAL status
00661   */
00662 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
00663 {
00664    HAL_StatusTypeDef status = HAL_OK;
00665
00666   /* Check the parameters */
00667   assert_param(IS_DAC_CHANNEL(Channel));
00668
00669   /* Disable the selected DAC channel DMA request */
00670     hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
00671
00672   /* Disable the Peripheral */
00673   __HAL_DAC_DISABLE(hdac, Channel);
00674
00675   /* Disable the DMA channel */
00676   /* Channel1 is used */
00677   if (Channel == DAC_CHANNEL_1)
00678   {
00679     /* Disable the DMA channel */
00680     status = HAL_DMA_Abort(hdac->DMA_Handle1);
00681
00682     /* Disable the DAC DMA underrun interrupt */
00683     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
00684   }
00685   else /* Channel2 is used for */
00686   {
00687     /* Disable the DMA channel */
00688     status = HAL_DMA_Abort(hdac->DMA_Handle2);
00689
00690     /* Disable the DAC DMA underrun interrupt */
00691     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
00692   }
00693
00694   /* Check if DMA Channel effectively disabled */
00695   if (status != HAL_OK)
00696   {
00697     /* Update DAC state machine to error */
00698     hdac->State = HAL_DAC_STATE_ERROR;
00699   }
00700   else
00701   {
00702     /* Change DAC state */
00703     hdac->State = HAL_DAC_STATE_READY;
00704   }
00705
00706   /* Return function status */
00707   return status;
00708 }
00709
00710 /* DAC channel 2 is available on top of DAC channel 1 */
00711
00712 /**
00713   * @brief  Handles DAC interrupt request
00714   *         This function uses the interruption of DMA
00715   *         underrun.
00716   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00717   *         the configuration information for the specified DAC.
00718   * @retval None
00719   */
00720 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
00721 {
00722   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
00723   {
00724     /* Check underrun flag of DAC channel 1 */
00725     if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
00726     {
00727       /* Change DAC state to error state */
00728       hdac->State = HAL_DAC_STATE_ERROR;
00729
00730       /* Set DAC error code to chanel1 DMA underrun error */
00731       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
00732
00733       /* Clear the underrun flag */
00734       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
00735
00736       /* Disable the selected DAC channel1 DMA request */
00737       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00738
00739       /* Error callback */
00740       HAL_DAC_DMAUnderrunCallbackCh1(hdac);
00741     }
00742   }
00743   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
00744   {
00745     /* Check underrun flag of DAC channel 1 */
00746     if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
00747     {
00748       /* Change DAC state to error state */
00749       hdac->State = HAL_DAC_STATE_ERROR;
00750
00751       /* Set DAC error code to channel2 DMA underrun error */
00752       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
00753
00754       /* Clear the underrun flag */
00755       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
00756
00757       /* Disable the selected DAC channel1 DMA request */
00758       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00759
00760       /* Error callback */
00761       HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
00762     }
00763   }
00764 }
00765
00766 /**
00767   * @brief  Set the specified data holding register value for DAC channel.
00768   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00769   *         the configuration information for the specified DAC.
00770   * @param  Channel: The selected DAC channel.
00771   *          This parameter can be one of the following values:
00772   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00773   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00774   * @param  Alignment: Specifies the data alignment.
00775   *          This parameter can be one of the following values:
00776   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00777   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00778   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00779   * @param  Data: Data to be loaded in the selected data holding register.
00780   * @retval HAL status
00781   */
00782 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
00783 {
00784   __IO uint32_t tmp = 0;
00785
00786   /* Check the parameters */
00787   assert_param(IS_DAC_CHANNEL(Channel));
00788   assert_param(IS_DAC_ALIGN(Alignment));
00789   assert_param(IS_DAC_DATA(Data));
00790
00791   tmp = (uint32_t)hdac->Instance;
00792   if(Channel == DAC_CHANNEL_1)
00793   {
00794     tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
00795   }
00796   else
00797   {
00798     tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
00799   }
00800
00801   /* Set the DAC channel selected data holding register */
00802   *(__IO uint32_t *) tmp = Data;
00803
00804   /* Return function status */
00805   return HAL_OK;
00806 }
00807
00808 /**
00809   * @brief  Conversion complete callback in non-blocking mode for Channel1
00810   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00811   *         the configuration information for the specified DAC.
00812   * @retval None
00813   */
00814 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00815 {
00816   /* Prevent unused argument(s) compilation warning */
00817   UNUSED(hdac);
00818
00819   /* NOTE : This function should not be modified, when the callback is needed,
00820             the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
00821    */
00822 }
00823
00824 /**
00825   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1
00826   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00827   *         the configuration information for the specified DAC.
00828   * @retval None
00829   */
00830 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00831 {
00832   /* Prevent unused argument(s) compilation warning */
00833   UNUSED(hdac);
00834
00835   /* NOTE : This function should not be modified, when the callback is needed,
00836             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
00837    */
00838 }
00839
00840 /**
00841   * @brief  Error DAC callback for Channel1.
00842   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00843   *         the configuration information for the specified DAC.
00844   * @retval None
00845   */
00846 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
00847 {
00848   /* Prevent unused argument(s) compilation warning */
00849   UNUSED(hdac);
00850
00851   /* NOTE : This function should not be modified, when the callback is needed,
00852             the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
00853    */
00854 }
00855
00856 /**
00857   * @brief  DMA underrun DAC callback for channel1.
00858   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00859   *         the configuration information for the specified DAC.
00860   * @retval None
00861   */
00862 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
00863 {
00864   /* Prevent unused argument(s) compilation warning */
00865   UNUSED(hdac);
00866
00867   /* NOTE : This function should not be modified, when the callback is needed,
00868             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
00869    */
00870 }
00871
00872 /**
00873   * @}
00874   */
00875
00876 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
00877  *  @brief    Peripheral Control functions
00878  *
00879 @verbatim
00880   ==============================================================================
00881              ##### Peripheral Control functions #####
00882   ==============================================================================
00883     [..]  This section provides functions allowing to:
00884       (+) Configure channels.
00885       (+) Set the specified data holding register value for DAC channel.
00886
00887 @endverbatim
00888   * @{
00889   */
00890
00891 /**
00892   * @brief  Returns the last data output value of the selected DAC channel.
00893   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00894   *         the configuration information for the specified DAC.
00895   * @param  Channel: The selected DAC channel.
00896   *          This parameter can be one of the following values:
00897   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00898   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00899   * @retval The selected DAC channel data output value.
00900   */
00901 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
00902 {
00903   /* Check the parameters */
00904   assert_param(IS_DAC_CHANNEL(Channel));
00905
00906   /* Returns the DAC channel data output register value */
00907   if(Channel == DAC_CHANNEL_1)
00908   {
00909     return hdac->Instance->DOR1;
00910   }
00911   else
00912   {
00913     return hdac->Instance->DOR2;
00914   }
00915 }
00916
00917 /**
00918   * @brief  Configures the selected DAC channel.
00919   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00920   *         the configuration information for the specified DAC.
00921   * @param  sConfig: DAC configuration structure.
00922   * @param  Channel: The selected DAC channel.
00923   *          This parameter can be one of the following values:
00924   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00925   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00926   * @retval HAL status
00927   */
00928 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
00929 {
00930   uint32_t tmpreg1 = 0, tmpreg2 = 0;
00931   uint32_t tickstart = 0;
00932
00933   /* Check the DAC parameters */
00934   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
00935   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
00936   assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
00937   assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
00938   if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
00939   {
00940     assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
00941   }
00942   assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
00943   if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
00944   {
00945     assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
00946     assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
00947     assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
00948   }
00949   assert_param(IS_DAC_CHANNEL(Channel));
00950
00951   /* Process locked */
00952   __HAL_LOCK(hdac);
00953
00954   /* Change DAC state */
00955   hdac->State = HAL_DAC_STATE_BUSY;
00956
00957   if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
00958   /* Sample on old configuration */
00959   {
00960     /* SampleTime */
00961     if (Channel == DAC_CHANNEL_1)
00962     {
00963       /* Get timeout */
00964       tickstart = HAL_GetTick();
00965
00966       /* SHSR1 can be written when BWST1  equals RESET */
00967       while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET)
00968       {
00969         /* Check for the Timeout */
00970         if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
00971         {
00972           /* Update error code */
00973           SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
00974
00975           /* Change the DMA state */
00976           hdac->State = HAL_DAC_STATE_TIMEOUT;
00977
00978           return HAL_TIMEOUT;
00979         }
00980       }
00981       HAL_Delay(1);
00982       hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
00983     }
00984     else /* Channel 2 */
00985     {
00986       /* SHSR2 can be written when BWST2 equals RESET */
00987
00988       while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET)
00989       {
00990         /* Check for the Timeout */
00991         if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
00992         {
00993           /* Update error code */
00994           SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
00995
00996           /* Change the DMA state */
00997           hdac->State = HAL_DAC_STATE_TIMEOUT;
00998
00999           return HAL_TIMEOUT;
01000         }
01001       }
01002       HAL_Delay(1);
01003       hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
01004     }
01005     /* HoldTime */
01006     hdac->Instance->SHHR = (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel;
01007     /* RefreshTime */
01008     hdac->Instance->SHRR = (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel;
01009   }
01010
01011   if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
01012   /* USER TRIMMING */
01013   {
01014   /* Get the DAC CCR value */
01015   tmpreg1 = hdac->Instance->CCR;
01016   /* Clear trimming value */
01017   tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel);
01018   /* Configure for the selected trimming offset */
01019   tmpreg2 = sConfig->DAC_TrimmingValue;
01020   /* Calculate CCR register value depending on DAC_Channel */
01021   tmpreg1 |= tmpreg2 << Channel;
01022   /* Write to DAC CCR */
01023   hdac->Instance->CCR = tmpreg1;
01024   }
01025   /* else factory trimming is used (factory setting are available at reset)*/
01026   /* SW Nothing has nothing to do */
01027
01028   /* Get the DAC MCR value */
01029   tmpreg1 = hdac->Instance->MCR;
01030   /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */
01031   tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel);
01032   /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
01033   tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
01034   /* Calculate MCR register value depending on DAC_Channel */
01035   tmpreg1 |= tmpreg2 << Channel;
01036   /* Write to DAC MCR */
01037   hdac->Instance->MCR = tmpreg1;
01038
01039   /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
01040   CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel);
01041
01042   /* Get the DAC CR value */
01043   tmpreg1 = hdac->Instance->CR;
01044   /* Clear TENx, TSELx, WAVEx and MAMPx bits */
01045   tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel);
01046   /* Configure for the selected DAC channel: trigger */
01047   /* Set TSELx and TENx bits according to DAC_Trigger value */
01048   tmpreg2 = (sConfig->DAC_Trigger);
01049   /* Calculate CR register value depending on DAC_Channel */
01050   tmpreg1 |= tmpreg2 << Channel;
01051   /* Write to DAC CR */
01052   hdac->Instance->CR = tmpreg1;
01053
01054   /* Disable wave generation */
01055   hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
01056
01057   /* Change DAC state */
01058   hdac->State = HAL_DAC_STATE_READY;
01059
01060   /* Process unlocked */
01061   __HAL_UNLOCK(hdac);
01062
01063   /* Return function status */
01064   return HAL_OK;
01065 }
01066
01067 /**
01068   * @}
01069   */
01070
01071 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
01072  *  @brief   Peripheral State and Errors functions
01073  *
01074 @verbatim
01075   ==============================================================================
01076             ##### Peripheral State and Errors functions #####
01077   ==============================================================================
01078     [..]
01079     This subsection provides functions allowing to
01080       (+) Check the DAC state.
01081       (+) Check the DAC Errors.
01082
01083 @endverbatim
01084   * @{
01085   */
01086
01087 /**
01088   * @brief  return the DAC handle state
01089   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
01090   *         the configuration information for the specified DAC.
01091   * @retval HAL state
01092   */
01093 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
01094 {
01095   /* Return DAC handle state */
01096   return hdac->State;
01097 }
01098
01099
01100 /**
01101   * @brief  Return the DAC error code
01102   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
01103   *         the configuration information for the specified DAC.
01104   * @retval DAC Error Code
01105   */
01106 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
01107 {
01108   return hdac->ErrorCode;
01109 }
01110
01111 /**
01112   * @}
01113   */
01114
01115 /**
01116   * @}
01117   */
01118
01119 /** @addtogroup DAC_Private_Functions
01120   * @{
01121   */
01122
01123 /**
01124   * @brief  DMA conversion complete callback.
01125   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01126   *                the configuration information for the specified DMA module.
01127   * @retval None
01128   */
01129 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
01130 {
01131   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01132
01133   HAL_DAC_ConvCpltCallbackCh1(hdac);
01134
01135   hdac->State= HAL_DAC_STATE_READY;
01136 }
01137
01138 /**
01139   * @brief  DMA half transfer complete callback.
01140   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01141   *                the configuration information for the specified DMA module.
01142   * @retval None
01143   */
01144 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
01145 {
01146     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01147     /* Conversion complete callback */
01148     HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
01149 }
01150
01151 /**
01152   * @brief  DMA error callback
01153   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01154   *                the configuration information for the specified DMA module.
01155   * @retval None
01156   */
01157 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
01158 {
01159   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01160
01161   /* Set DAC error code to DMA error */
01162   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
01163
01164   HAL_DAC_ErrorCallbackCh1(hdac);
01165
01166   hdac->State= HAL_DAC_STATE_READY;
01167 }
01168
01169 /**
01170   * @}
01171   */
01172
01173 #endif /* HAL_DAC_MODULE_ENABLED */
01174
01175 /**
01176   * @}
01177   */
01178
01179 /**
01180   * @}
01181   */
01182
01183 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dac.h Source File

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stm32l4xx_hal_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of DAC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_DAC_H
00040 #define __STM32L4xx_HAL_DAC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32l4xx_hal_def.h"
00049
00050 /** @addtogroup STM32L4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup DAC
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059
00060 /** @defgroup DAC_Exported_Types DAC Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  HAL State structures definition
00066   */
00067 typedef enum
00068 {
00069   HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
00070   HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
00071   HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
00072   HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
00073   HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
00074
00075 }HAL_DAC_StateTypeDef;
00076
00077 /**
00078   * @brief  DAC handle Structure definition
00079   */
00080 typedef struct
00081 {
00082   DAC_TypeDef                 *Instance;     /*!< Register base address             */
00083
00084   __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
00085
00086   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
00087
00088   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
00089
00090   DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
00091
00092   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
00093
00094 }DAC_HandleTypeDef;
00095
00096 /**
00097   * @brief   DAC Configuration sample and hold Channel structure definition
00098   */
00099 typedef struct
00100 {
00101   uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
00102                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00103                                           This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
00104
00105   uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
00106                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00107                                           This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
00108
00109   uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
00110                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
00111                                           This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
00112 }
00113 DAC_SampleAndHoldConfTypeDef;
00114
00115 /**
00116   * @brief   DAC Configuration regular Channel structure definition
00117   */
00118 typedef struct
00119 {
00120   uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
00121                                               This parameter can be a value of @ref DAC_SampleAndHold */
00122
00123   uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
00124                                               This parameter can be a value of @ref DAC_trigger_selection */
00125
00126   uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00127                                                This parameter can be a value of @ref DAC_output_buffer */
00128
00129   uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
00130                                               This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
00131
00132   uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
00133                                               This parameter must be a value of @ref DAC_UserTrimming
00134                                               DAC_UserTrimming is either factory or user trimming */
00135
00136   uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
00137                                                i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
00138                                                This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00139
00140   DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
00141
00142 }DAC_ChannelConfTypeDef;
00143
00144 /**
00145   * @}
00146   */
00147
00148 /* Exported constants --------------------------------------------------------*/
00149
00150 /** @defgroup DAC_Exported_Constants DAC Exported Constants
00151   * @{
00152   */
00153
00154 /** @defgroup DAC_Error_Code DAC Error Code
00155   * @{
00156   */
00157 #define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
00158 #define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DMA underrun error   */
00159 #define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DMA underrun error   */
00160 #define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */
00161 #define  HAL_DAC_ERROR_TIMEOUT           0x08    /*!< Timeout error                     */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup DAC_trigger_selection DAC trigger selection
00167   * @{
00168   */
00169
00170 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00171 #define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register
00172                                                                        has been loaded, and not by external trigger */
00173 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00174 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00175 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00176 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00177 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00178 #endif     /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
00179
00180 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00181 #define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register
00182                                                                        has been loaded, and not by external trigger */
00183 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00184 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00185 #define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00186 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00187 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00188 #define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
00189 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00190 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00191 #endif     /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */
00192
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup DAC_output_buffer DAC output buffer
00198   * @{
00199   */
00200 #define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
00201 #define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_MCR_MODE1_1)
00202
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup DAC_Channel_selection DAC Channel selection
00208   * @{
00209   */
00210 #define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
00211 #define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
00212
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup DAC_data_alignment DAC data alignment
00218   * @{
00219   */
00220 #define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
00221 #define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
00222 #define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
00223
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup DAC_flags_definition DAC flags definition
00229   * @{
00230   */
00231 #define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00232 #define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00233
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup DAC_IT_definition  DAC IT definition
00239   * @{
00240   */
00241 #define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00242 #define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00243
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
00249   * @{
00250   */
00251 #define DAC_CHIPCONNECT_DISABLE  ((uint32_t)0x00000000)
00252 #define DAC_CHIPCONNECT_ENABLE     ((uint32_t)DAC_MCR_MODE1_0)
00253
00254 /**
00255   * @}
00256   */
00257
00258   /** @defgroup DAC_UserTrimming DAC User Trimming
00259   * @{
00260   */
00261
00262 #define DAC_TRIMMING_FACTORY        ((uint32_t)0x00000000)           /*!< Factory trimming */
00263 #define DAC_TRIMMING_USER           ((uint32_t)0x00000001)           /*!< User trimming */
00264
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup DAC_SampleAndHold DAC power mode
00270   * @{
00271   */
00272 #define DAC_SAMPLEANDHOLD_DISABLE     ((uint32_t)0x00000000)
00273 #define DAC_SAMPLEANDHOLD_ENABLE      ((uint32_t)DAC_MCR_MODE1_2)
00274
00275 /**
00276   * @}
00277   */
00278
00279 /**
00280   * @}
00281   */
00282
00283 /* Exported macro ------------------------------------------------------------*/
00284
00285 /** @defgroup DAC_Exported_Macros DAC Exported Macros
00286   * @{
00287   */
00288
00289 /** @brief Reset DAC handle state.
00290   * @param  __HANDLE__: specifies the DAC handle.
00291   * @retval None
00292   */
00293 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
00294
00295 /** @brief Enable the DAC channel.
00296   * @param  __HANDLE__: specifies the DAC handle.
00297   * @param  __DAC_Channel__: specifies the DAC channel
00298   * @retval None
00299   */
00300 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
00301 ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
00302
00303 /** @brief Disable the DAC channel.
00304   * @param  __HANDLE__: specifies the DAC handle
00305   * @param  __DAC_Channel__: specifies the DAC channel.
00306   * @retval None
00307   */
00308 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
00309 ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
00310
00311 /** @brief Set DHR12R1 alignment.
00312   * @param  __ALIGNMENT__: specifies the DAC alignment
00313   * @retval None
00314   */
00315 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
00316
00317 /** @brief  Set DHR12R2 alignment.
00318   * @param  __ALIGNMENT__: specifies the DAC alignment
00319   * @retval None
00320   */
00321 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
00322
00323 /** @brief  Set DHR12RD alignment.
00324   * @param  __ALIGNMENT__: specifies the DAC alignment
00325   * @retval None
00326   */
00327 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
00328
00329 /** @brief Enable the DAC interrupt.
00330   * @param  __HANDLE__: specifies the DAC handle
00331   * @param  __INTERRUPT__: specifies the DAC interrupt.
00332   *          This parameter can be any combination of the following values:
00333   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00334   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00335   * @retval None
00336   */
00337 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00338
00339 /** @brief Disable the DAC interrupt.
00340   * @param  __HANDLE__: specifies the DAC handle
00341   * @param  __INTERRUPT__: specifies the DAC interrupt.
00342   *          This parameter can be any combination of the following values:
00343   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00344   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00345   * @retval None
00346   */
00347 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00348
00349 /** @brief  Check whether the specified DAC interrupt source is enabled or not.
00350   * @param __HANDLE__: DAC handle
00351   * @param __INTERRUPT__: DAC interrupt source to check
00352   *          This parameter can be any combination of the following values:
00353   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00354   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00355   * @retval State of interruption (SET or RESET)
00356   */
00357 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
00358
00359 /** @brief  Get the selected DAC's flag status.
00360   * @param  __HANDLE__: specifies the DAC handle.
00361   * @param  __FLAG__: specifies the DAC flag to get.
00362   *          This parameter can be any combination of the following values:
00363   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
00364   *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
00365   * @retval None
00366   */
00367 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00368
00369 /** @brief  Clear the DAC's flag.
00370   * @param  __HANDLE__: specifies the DAC handle.
00371   * @param  __FLAG__: specifies the DAC flag to clear.
00372   *          This parameter can be any combination of the following values:
00373   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
00374   *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
00375   * @retval None
00376   */
00377 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
00378
00379 /**
00380   * @}
00381   */
00382
00383 /* Private macro -------------------------------------------------------------*/
00384
00385 /** @defgroup DAC_Private_Macros DAC Private Macros
00386   * @{
00387   */
00388 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
00389                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
00390
00391 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
00392                                 ((CHANNEL) == DAC_CHANNEL_2))
00393
00394 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
00395                              ((ALIGN) == DAC_ALIGN_12B_L) || \
00396                              ((ALIGN) == DAC_ALIGN_8B_R))
00397
00398 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
00399
00400 #define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x0000000FF)
00401
00402 /**
00403   * @}
00404   */
00405
00406 /* Include DAC HAL Extended module */
00407 #include "stm32l4xx_hal_dac_ex.h"
00408
00409 /* Exported functions --------------------------------------------------------*/
00410
00411 /** @addtogroup DAC_Exported_Functions
00412   * @{
00413   */
00414
00415 /** @addtogroup DAC_Exported_Functions_Group1
00416   * @{
00417   */
00418 /* Initialization and de-initialization functions *****************************/
00419 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
00420 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
00421 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
00422 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
00423
00424 /**
00425   * @}
00426   */
00427
00428 /** @addtogroup DAC_Exported_Functions_Group2
00429  * @{
00430  */
00431 /* IO operation functions *****************************************************/
00432 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
00433 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
00434 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
00435 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
00436
00437 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
00438
00439 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
00440
00441 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00442 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00443 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
00444 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
00445 /**
00446   * @}
00447   */
00448
00449 /** @addtogroup DAC_Exported_Functions_Group3
00450   * @{
00451   */
00452 /* Peripheral Control functions ***********************************************/
00453 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
00454
00455 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
00456 /**
00457   * @}
00458   */
00459
00460 /** @addtogroup DAC_Exported_Functions_Group4
00461   * @{
00462   */
00463 /* Peripheral State and Error functions ***************************************/
00464 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
00465 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
00466
00467 /**
00468   * @}
00469   */
00470
00471 /**
00472   * @}
00473   */
00474
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 #ifdef __cplusplus
00484 }
00485 #endif
00486
00487
00488 #endif /*__STM32L4xx_HAL_DAC_H */
00489
00490 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00491
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dac_ex.c Source File

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stm32l4xx_hal_dac_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_dac_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   DAC HAL module driver.
00008   *          This file provides firmware functions to manage the extended
00009   *          functionalities of the DAC peripheral.
00010   *
00011   *
00012   @verbatim
00013   ==============================================================================
00014                       ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017       (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
00018           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
00019           HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
00020       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
00021       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
00022
00023       (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
00024       (+) HAL_DACEx_SetUserTrimming to set user trimming value.
00025       (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
00026           after reset, user setting if HAL_DACEx_SetUserTrimming have been used
00027           at least one time after reset).
00028
00029  @endverbatim
00030   ******************************************************************************
00031   * @attention
00032   *
00033   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00034   *
00035   * Redistribution and use in source and binary forms, with or without modification,
00036   * are permitted provided that the following conditions are met:
00037   *   1. Redistributions of source code must retain the above copyright notice,
00038   *      this list of conditions and the following disclaimer.
00039   *   2. Redistributions in binary form must reproduce the above copyright notice,
00040   *      this list of conditions and the following disclaimer in the documentation
00041   *      and/or other materials provided with the distribution.
00042   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00043   *      may be used to endorse or promote products derived from this software
00044   *      without specific prior written permission.
00045   *
00046   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00047   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00048   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00049   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00050   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00051   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00052   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00053   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00054   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00055   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00056   *
00057   ******************************************************************************
00058   */
00059
00060
00061 /* Includes ------------------------------------------------------------------*/
00062 #include "stm32l4xx_hal.h"
00063
00064 /** @addtogroup STM32L4xx_HAL_Driver
00065   * @{
00066   */
00067
00068 /** @defgroup DACEx DACEx
00069   * @brief DAC Extended HAL module driver
00070   * @{
00071   */
00072
00073 #ifdef HAL_DAC_MODULE_ENABLED
00074
00075 /* Private typedef -----------------------------------------------------------*/
00076 /* Private define ------------------------------------------------------------*/
00077 /* Private macro -------------------------------------------------------------*/
00078 /* Private variables ---------------------------------------------------------*/
00079 /* Private function prototypes -----------------------------------------------*/
00080 /* Exported functions --------------------------------------------------------*/
00081
00082 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
00083   * @{
00084   */
00085
00086 /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
00087  *  @brief    Extended IO operation functions
00088  *
00089 @verbatim
00090   ==============================================================================
00091                  ##### Extended features functions #####
00092   ==============================================================================
00093     [..]  This section provides functions allowing to:
00094       (+) Start conversion.
00095       (+) Stop conversion.
00096       (+) Start conversion and enable DMA transfer.
00097       (+) Stop conversion and disable DMA transfer.
00098       (+) Get result of conversion.
00099       (+) Get result of dual mode conversion.
00100
00101 @endverbatim
00102   * @{
00103   */
00104
00105 /**
00106   * @brief  Enable or disable the selected DAC channel wave generation.
00107   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00108   *         the configuration information for the specified DAC.
00109   * @param  Channel: The selected DAC channel.
00110   *          This parameter can be one of the following values:
00111   *            DAC_CHANNEL_1 / DAC_CHANNEL_2
00112   * @param  Amplitude: Select max triangle amplitude.
00113   *          This parameter can be one of the following values:
00114   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
00115   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
00116   *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
00117   *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
00118   *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
00119   *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
00120   *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
00121   *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
00122   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
00123   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
00124   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
00125   *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
00126   * @retval HAL status
00127   */
00128 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00129 {
00130   /* Check the parameters */
00131   assert_param(IS_DAC_CHANNEL(Channel));
00132   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00133
00134   /* Process locked */
00135   __HAL_LOCK(hdac);
00136
00137   /* Change DAC state */
00138   hdac->State = HAL_DAC_STATE_BUSY;
00139
00140   /* Enable the triangle wave generation for the selected DAC channel */
00141   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
00142
00143   /* Change DAC state */
00144   hdac->State = HAL_DAC_STATE_READY;
00145
00146   /* Process unlocked */
00147   __HAL_UNLOCK(hdac);
00148
00149   /* Return function status */
00150   return HAL_OK;
00151 }
00152
00153 /**
00154   * @brief  Enable or disable the selected DAC channel wave generation.
00155   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00156   *         the configuration information for the specified DAC.
00157   * @param  Channel: The selected DAC channel.
00158   *          This parameter can be one of the following values:
00159   *            DAC_CHANNEL_1 / DAC_CHANNEL_2
00160   * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation.
00161   *          This parameter can be one of the following values:
00162   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
00163   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
00164   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
00165   *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
00166   *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
00167   *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
00168   *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
00169   *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
00170   *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
00171   *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
00172   *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
00173   *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
00174   * @retval HAL status
00175   */
00176 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00177 {
00178   /* Check the parameters */
00179   assert_param(IS_DAC_CHANNEL(Channel));
00180   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00181
00182   /* Process locked */
00183   __HAL_LOCK(hdac);
00184
00185   /* Change DAC state */
00186   hdac->State = HAL_DAC_STATE_BUSY;
00187
00188   /* Enable the noise wave generation for the selected DAC channel */
00189   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
00190
00191   /* Change DAC state */
00192   hdac->State = HAL_DAC_STATE_READY;
00193
00194   /* Process unlocked */
00195   __HAL_UNLOCK(hdac);
00196
00197   /* Return function status */
00198   return HAL_OK;
00199 }
00200
00201
00202
00203 /**
00204   * @brief  Set the specified data holding register value for dual DAC channel.
00205   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00206   *               the configuration information for the specified DAC.
00207   * @param  Alignment: Specifies the data alignment for dual channel DAC.
00208   *          This parameter can be one of the following values:
00209   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
00210   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
00211   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
00212   * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
00213   * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
00214   * @note   In dual mode, a unique register access is required to write in both
00215   *          DAC channels at the same time.
00216   * @retval HAL status
00217   */
00218 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
00219 {
00220   uint32_t data = 0, tmp = 0;
00221
00222   /* Check the parameters */
00223   assert_param(IS_DAC_ALIGN(Alignment));
00224   assert_param(IS_DAC_DATA(Data1));
00225   assert_param(IS_DAC_DATA(Data2));
00226
00227   /* Calculate and set dual DAC data holding register value */
00228   if (Alignment == DAC_ALIGN_8B_R)
00229   {
00230     data = ((uint32_t)Data2 << 8) | Data1;
00231   }
00232   else
00233   {
00234     data = ((uint32_t)Data2 << 16) | Data1;
00235   }
00236
00237   tmp = (uint32_t)hdac->Instance;
00238   tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
00239
00240   /* Set the dual DAC selected data holding register */
00241   *(__IO uint32_t *)tmp = data;
00242
00243   /* Return function status */
00244   return HAL_OK;
00245 }
00246
00247 /**
00248   * @brief  Conversion complete callback in non-blocking mode for Channel2.
00249   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00250   *         the configuration information for the specified DAC.
00251   * @retval None
00252   */
00253 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00254 {
00255   /* Prevent unused argument(s) compilation warning */
00256   UNUSED(hdac);
00257
00258   /* NOTE : This function should not be modified, when the callback is needed,
00259             the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
00260    */
00261 }
00262
00263 /**
00264   * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2.
00265   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00266   *         the configuration information for the specified DAC.
00267   * @retval None
00268   */
00269 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00270 {
00271   /* Prevent unused argument(s) compilation warning */
00272   UNUSED(hdac);
00273
00274   /* NOTE : This function should not be modified, when the callback is needed,
00275             the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
00276    */
00277 }
00278
00279 /**
00280   * @brief  Error DAC callback for Channel2.
00281   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00282   *         the configuration information for the specified DAC.
00283   * @retval None
00284   */
00285 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
00286 {
00287   /* Prevent unused argument(s) compilation warning */
00288   UNUSED(hdac);
00289
00290   /* NOTE : This function should not be modified, when the callback is needed,
00291             the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
00292    */
00293 }
00294
00295 /**
00296   * @brief  DMA underrun DAC callback for Channel2.
00297   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00298   *         the configuration information for the specified DAC.
00299   * @retval None
00300   */
00301 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
00302 {
00303   /* Prevent unused argument(s) compilation warning */
00304   UNUSED(hdac);
00305
00306   /* NOTE : This function should not be modified, when the callback is needed,
00307             the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
00308    */
00309 }
00310
00311 /**
00312   * @brief  Run the self calibration of one DAC channel.
00313   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00314   *         the configuration information for the specified DAC.
00315   * @param  sConfig: DAC channel configuration structure.
00316   * @param  Channel: The selected DAC channel.
00317   *          This parameter can be one of the following values:
00318   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00319   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00320   * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
00321   * @retval HAL status
00322   * @note   Calibration runs about 7 ms.
00323   */
00324
00325 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
00326 {
00327   HAL_StatusTypeDef status = HAL_OK;
00328
00329   __IO uint32_t tmp = 0;
00330   uint32_t trimmingvalue = 0;
00331   uint32_t delta;
00332
00333   /* store/restore channel configuration structure purpose */
00334   uint32_t oldmodeconfiguration = 0;
00335
00336   /* Check the parameters */
00337   assert_param(IS_DAC_CHANNEL(Channel));
00338
00339  /* Check the DAC handle allocation */
00340  /* Check if DAC running */
00341   if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_BUSY))
00342   {
00343     status = HAL_ERROR;
00344   }
00345
00346   /* Process locked */
00347   __HAL_LOCK(hdac);
00348
00349   /* Store configuration */
00350   oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel));
00351
00352   /* Disable the selected DAC channel */
00353   CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel));
00354
00355   /* Set mode in MCR  for calibration */
00356    MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0);
00357
00358   /* Set DAC Channel1 DHR register to the middle value */
00359   /* HAL_DAC_SetValue(hdac, Channel, DAC_ALIGN_12B_R, 0x0800); */
00360   tmp = (uint32_t)hdac->Instance;
00361   if(Channel == DAC_CHANNEL_1)
00362   {
00363     tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
00364   }
00365   else
00366   {
00367     tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
00368   }
00369   *(__IO uint32_t *) tmp = 0x0800;
00370
00371   /* Enable the selected DAC channel calibration */
00372   /* i.e. set DAC_CR_CENx bit */
00373   SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
00374
00375   /* Init trimming counter */
00376   /* Medium value */
00377   trimmingvalue = 16;
00378   delta = 8;
00379   while (delta != 0)
00380     {
00381     /* Set candidate trimming */
00382     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
00383
00384     /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
00385     /* i.e. minimum time needed between two calibration steps */
00386     HAL_Delay(1);
00387
00388     if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == RESET)
00389       {
00390         /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
00391         trimmingvalue += delta;
00392       }
00393       else
00394       {
00395         /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
00396         trimmingvalue -= delta;
00397        }
00398      delta >>= 1;
00399     }
00400
00401     /* Still need to check if right calibration is current value or one step below */
00402     /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1  */
00403     /* Set candidate trimming */
00404     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
00405
00406     /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
00407     /* i.e. minimum time needed between two calibration steps */
00408     HAL_Delay(1);
00409
00410     if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == RESET)
00411       {
00412       /* OPAMP_CSR_OUTCAL is actually one value more */
00413       trimmingvalue++;
00414       /* Set right trimming */
00415         MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
00416       }
00417
00418   /* Disable the selected DAC channel calibration */
00419   /* i.e. clear DAC_CR_CENx bit */
00420   CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
00421
00422   sConfig->DAC_TrimmingValue = trimmingvalue;
00423   sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
00424
00425   /* Restore configuration */
00426   MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration);
00427
00428   /* Process unlocked */
00429   __HAL_UNLOCK(hdac);
00430
00431   return status;
00432 }
00433
00434 /**
00435   * @brief  Set the trimming mode and trimming value (user trimming mode applied).
00436   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00437   *         the configuration information for the specified DAC.
00438   * @param  sConfig: DAC configuration structure updated with new DAC trimming value.
00439   * @param  Channel: The selected DAC channel.
00440   *          This parameter can be one of the following values:
00441   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00442   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00443   * @param  NewTrimmingValue: DAC new trimming value
00444   * @retval HAL status
00445   */
00446
00447 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
00448 {
00449   HAL_StatusTypeDef status = HAL_OK;
00450
00451   /* Check the parameters */
00452   assert_param(IS_DAC_CHANNEL(Channel));
00453   assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
00454
00455  /* Check the DAC handle allocation */
00456   if(hdac == NULL)
00457   {
00458     status = HAL_ERROR;
00459   }
00460
00461   /* Process locked */
00462   __HAL_LOCK(hdac);
00463
00464   /* Set new trimming */
00465   MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (NewTrimmingValue<<Channel));
00466
00467   /* Update trimming mode */
00468   sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
00469   sConfig->DAC_TrimmingValue = NewTrimmingValue;
00470
00471   /* Process unlocked */
00472   __HAL_UNLOCK(hdac);
00473
00474   return status;
00475 }
00476
00477 /**
00478   * @brief  Return the DAC trimming value.
00479   * @param  hdac : DAC handle
00480   * @param  Channel: The selected DAC channel.
00481   *          This parameter can be one of the following values:
00482   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00483   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00484   * @retval Trimming value : range: 0->31
00485   *
00486  */
00487
00488 uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
00489 {
00490   uint32_t trimmingvalue = 0;
00491
00492   /* Check the DAC handle allocation */
00493   /* And not in Reset state */
00494   if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_RESET))
00495   {
00496     return HAL_ERROR;
00497   }
00498   else
00499   {
00500     /* Check the parameter */
00501     assert_param(IS_DAC_CHANNEL(Channel));
00502
00503     /* Retrieve trimming  */
00504     trimmingvalue = ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << Channel)) >> Channel);
00505   }
00506   return trimmingvalue;
00507 }
00508
00509 /**
00510   * @}
00511   */
00512
00513 /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
00514  *  @brief    Extended Peripheral Control functions
00515  *
00516 @verbatim
00517   ==============================================================================
00518              ##### Peripheral Control functions #####
00519   ==============================================================================
00520     [..]  This section provides functions allowing to:
00521       (+) Configure channels.
00522       (+) Set the specified data holding register value for DAC channel.
00523
00524 @endverbatim
00525   * @{
00526   */
00527
00528 /**
00529   * @brief  Return the last data output value of the selected DAC channel.
00530   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00531   *         the configuration information for the specified DAC.
00532   * @retval The selected DAC channel data output value.
00533   */
00534 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
00535 {
00536   uint32_t tmp = 0;
00537
00538   tmp |= hdac->Instance->DOR1;
00539
00540   tmp |= hdac->Instance->DOR2 << 16;
00541
00542   /* Returns the DAC channel data output register value */
00543   return tmp;
00544 }
00545
00546 /**
00547   * @}
00548   */
00549
00550 /**
00551   * @}
00552   */
00553
00554 /* Private functions ---------------------------------------------------------*/
00555 /** @defgroup DACEx_Private_Functions DACEx private functions
00556  *  @brief    Extended private functions
00557    * @{
00558   */
00559
00560 /**
00561   * @brief  DMA conversion complete callback.
00562   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00563   *                the configuration information for the specified DMA module.
00564   * @retval None
00565   */
00566 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
00567 {
00568   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00569
00570   HAL_DACEx_ConvCpltCallbackCh2(hdac);
00571
00572   hdac->State= HAL_DAC_STATE_READY;
00573 }
00574
00575 /**
00576   * @brief  DMA half transfer complete callback.
00577   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00578   *                the configuration information for the specified DMA module.
00579   * @retval None
00580   */
00581 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
00582 {
00583     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00584     /* Conversion complete callback */
00585     HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
00586 }
00587
00588 /**
00589   * @brief  DMA error callback.
00590   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00591   *                the configuration information for the specified DMA module.
00592   * @retval None
00593   */
00594 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
00595 {
00596   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00597
00598   /* Set DAC error code to DMA error */
00599   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00600
00601   HAL_DACEx_ErrorCallbackCh2(hdac);
00602
00603   hdac->State= HAL_DAC_STATE_READY;
00604 }
00605
00606 /**
00607   * @}
00608   */
00609
00610 #endif /* HAL_DAC_MODULE_ENABLED */
00611
00612 /**
00613   * @}
00614   */
00615
00616 /**
00617   * @}
00618   */
00619
00620 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dac_ex.h Source File

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stm32l4xx_hal_dac_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_dac_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of DAC HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_DAC_EX_H
00040 #define __STM32L4xx_HAL_DAC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DACEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /**
00060   * @brief  HAL State structures definition
00061   */
00062
00063 /* Exported constants --------------------------------------------------------*/
00064
00065 /** @defgroup DACEx_Exported_Constants DACEx Exported Constants
00066   * @{
00067   */
00068
00069 /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
00070   * @{
00071   */
00072 #define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00073 #define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00074 #define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00075 #define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00076 #define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00077 #define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00078 #define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00079 #define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00080 #define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00081 #define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00082 #define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00083 #define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00084 #define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
00085 #define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
00086 #define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
00087 #define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
00088 #define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
00089 #define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
00090 #define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
00091 #define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
00092 #define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
00093 #define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
00094 #define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
00095 #define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
00096
00097 /**
00098   * @}
00099   */
00100
00101 /**
00102   * @}
00103   */
00104
00105 /* Exported macro ------------------------------------------------------------*/
00106
00107
00108 /* Private macro -------------------------------------------------------------*/
00109
00110 /** @defgroup DACEx_Private_Macros DACEx Private Macros
00111   * @{
00112   */
00113 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00114 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00115                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00116                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00117                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00118                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00119                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00120 #endif     /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
00121
00122 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00123 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
00124                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00125                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
00126                                  ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
00127                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00128                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00129                                  ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
00130                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00131                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00132 #endif     /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */
00133
00134 #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
00135
00136 #define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x0000003FF)
00137
00138 #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
00139                                     ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
00140
00141
00142 #define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
00143
00144 #define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
00145
00146 #define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
00147                                          ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
00148
00149 #define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
00150                                      ((TRIMMING) == DAC_TRIMMING_USER))
00151
00152 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
00153                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
00154                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
00155                                                       ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
00156                                                       ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
00157                                                       ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
00158                                                       ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
00159                                                       ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
00160                                                       ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
00161                                                       ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
00162                                                       ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
00163                                                       ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
00164                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
00165                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
00166                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
00167                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
00168                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
00169                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
00170                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
00171                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
00172                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
00173                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
00174                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
00175                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
00176
00177
00178
00179 /**
00180   * @}
00181   */
00182
00183 /* Exported functions --------------------------------------------------------*/
00184 /* Extended features functions ***********************************************/
00185
00186 /** @addtogroup DACEx_Exported_Functions
00187   * @{
00188   */
00189
00190 /** @addtogroup DACEx_Exported_Functions_Group2
00191  * @{
00192  */
00193 /* IO operation functions *****************************************************/
00194
00195 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00196 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00197 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
00198
00199 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00200 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00201 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
00202 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
00203
00204 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
00205 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
00206
00207 /**
00208   * @}
00209   */
00210
00211 /** @addtogroup DACEx_Exported_Functions_Group3
00212   * @{
00213   */
00214 /* Peripheral Control functions ***********************************************/
00215
00216 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
00217 uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
00218
00219 /**
00220   * @}
00221   */
00222
00223 /**
00224   * @}
00225   */
00226
00227 /** @addtogroup DACEx_Private_Functions
00228   * @{
00229   */
00230
00231 /* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
00232 /* are called by HAL_DAC_Start_DMA */
00233 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
00234 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
00235 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
00236
00237 /**
00238  * @}
00239  */
00240
00241 /**
00242   * @}
00243   */
00244
00245 /**
00246   * @}
00247   */
00248
00249 #ifdef __cplusplus
00250 }
00251 #endif
00252
00253 #endif /*__STM32L4xx_HAL_DAC_EX_H */
00254
00255 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dfsdm.c Source File

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stm32l4xx_hal_dfsdm.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_dfsdm.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Digital Filter for Sigma-Delta Modulators
00009   *          (DFSDM) peripherals:
00010   *           + Initialization and configuration of channels and filters
00011   *           + Regular channels configuration
00012   *           + Injected channels configuration
00013   *           + Regular/Injected Channels DMA Configuration
00014   *           + Interrupts and flags management
00015   *           + Analog watchdog feature
00016   *           + Short-circuit detector feature
00017   *           + Extremes detector feature
00018   *           + Clock absence detector feature
00019   *           + Break generation on analog watchdog or short-circuit event
00020   *
00021   @verbatim
00022   ==============================================================================
00023                      ##### How to use this driver #####
00024   ==============================================================================
00025   [..]
00026     *** Channel initialization ***
00027     ==============================
00028     [..]
00029       (#) User has first to initialize channels (before filters initialization).
00030       (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
00031         (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
00032         (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00033         (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
00034         (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
00035             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00036       (#) Configure the output clock, input, serial interface, analog watchdog,
00037           offset and data right bit shift parameters for this channel using the
00038           HAL_DFSDM_ChannelInit() function.
00039
00040     *** Channel clock absence detector ***
00041     ======================================
00042     [..]
00043       (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
00044           HAL_DFSDM_ChannelCkabStart_IT().
00045       (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
00046           absence.
00047       (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
00048           clock absence is detected.
00049       (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
00050           HAL_DFSDM_ChannelCkabStop_IT().
00051       (#) Please note that the same mode (polling or interrupt) has to be used
00052           for all channels because the channels are sharing the same interrupt.
00053       (#) Please note also that in interrupt mode, if clock absence detector is
00054           stopped for one channel, interrupt will be disabled for all channels.
00055
00056     *** Channel short circuit detector ***
00057     ======================================
00058     [..]
00059       (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
00060           or HAL_DFSDM_ChannelScdStart_IT().
00061       (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
00062           circuit.
00063       (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
00064           short circuit is detected.
00065       (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
00066           or HAL_DFSDM_ChannelScdStop_IT().
00067       (#) Please note that the same mode (polling or interrupt) has to be used
00068           for all channels because the channels are sharing the same interrupt.
00069       (#) Please note also that in interrupt mode, if short circuit detector is
00070           stopped for one channel, interrupt will be disabled for all channels.
00071
00072     *** Channel analog watchdog value ***
00073     =====================================
00074     [..]
00075       (#) Get analog watchdog filter value of a channel using
00076           HAL_DFSDM_ChannelGetAwdValue().
00077
00078     *** Channel offset value ***
00079     =====================================
00080     [..]
00081       (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
00082
00083     *** Filter initialization ***
00084     =============================
00085     [..]
00086       (#) After channel initialization, user has to init filters.
00087       (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
00088         (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
00089             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00090             Please note that DFSDMz_FLT0 global interrupt could be already
00091             enabled if interrupt is used for channel.
00092         (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
00093             with DFSDMz filter handle using __HAL_LINKDMA().
00094       (#) Configure the regular conversion, injected conversion and filter
00095           parameters for this filter using the HAL_DFSDM_FilterInit() function.
00096
00097     *** Filter regular channel conversion ***
00098     =========================================
00099     [..]
00100       (#) Select regular channel and enable/disable continuous mode using
00101           HAL_DFSDM_FilterConfigRegChannel().
00102       (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
00103           HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
00104           HAL_DFSDM_FilterRegularMsbStart_DMA().
00105       (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
00106           the end of regular conversion.
00107       (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
00108           at the end of regular conversion.
00109       (#) Get value of regular conversion and corresponding channel using
00110           HAL_DFSDM_FilterGetRegularValue().
00111       (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
00112           HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
00113           half transfer and at the transfer complete. Please note that
00114           HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
00115           circular mode.
00116       (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
00117           HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().
00118
00119     *** Filter injected channels conversion ***
00120     ===========================================
00121     [..]
00122       (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
00123       (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
00124           HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
00125           HAL_DFSDM_FilterInjectedMsbStart_DMA().
00126       (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
00127           the end of injected conversion.
00128       (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
00129           at the end of injected conversion.
00130       (#) Get value of injected conversion and corresponding channel using
00131           HAL_DFSDM_FilterGetInjectedValue().
00132       (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
00133           HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
00134           half transfer and at the transfer complete. Please note that
00135           HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
00136           circular mode.
00137       (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
00138           HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().
00139
00140     *** Filter analog watchdog ***
00141     ==============================
00142     [..]
00143       (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
00144       (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
00145       (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().
00146
00147     *** Filter extreme detector ***
00148     ===============================
00149     [..]
00150       (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
00151       (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
00152       (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
00153       (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().
00154
00155     *** Filter conversion time ***
00156     ==============================
00157     [..]
00158       (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
00159
00160     @endverbatim
00161   ******************************************************************************
00162   * @attention
00163   *
00164   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00165   *
00166   * Redistribution and use in source and binary forms, with or without modification,
00167   * are permitted provided that the following conditions are met:
00168   *   1. Redistributions of source code must retain the above copyright notice,
00169   *      this list of conditions and the following disclaimer.
00170   *   2. Redistributions in binary form must reproduce the above copyright notice,
00171   *      this list of conditions and the following disclaimer in the documentation
00172   *      and/or other materials provided with the distribution.
00173   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00174   *      may be used to endorse or promote products derived from this software
00175   *      without specific prior written permission.
00176   *
00177   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00178   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00179   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00180   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00181   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00182   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00183   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00184   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00185   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00186   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00187   *
00188   ******************************************************************************
00189   */
00190
00191 /* Includes ------------------------------------------------------------------*/
00192 #include "stm32l4xx_hal.h"
00193
00194 /** @addtogroup STM32L4xx_HAL_Driver
00195   * @{
00196   */
00197 #ifdef HAL_DFSDM_MODULE_ENABLED
00198 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00199 /** @defgroup DFSDM DFSDM
00200   * @brief DFSDM HAL driver module
00201   * @{
00202   */
00203
00204 /* Private typedef -----------------------------------------------------------*/
00205 /* Private define ------------------------------------------------------------*/
00206 /** @defgroup DFSDM_Private_Define DFSDM Private Define
00207  * @{
00208  */
00209 #define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
00210 #define DFSDM_CHAWSCDR_BKSCD_OFFSET     POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
00211 #define DFSDM_CHAWSCDR_FOSR_OFFSET      POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
00212 #define DFSDM_CHCFGR2_OFFSET_OFFSET  POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
00213 #define DFSDM_CHCFGR2_DTRBS_OFFSET   POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
00214 #define DFSDM_FLTFCR_FOSR_OFFSET        POSITION_VAL(DFSDM_FLTFCR_FOSR)
00215 #define DFSDM_FLTCR1_MSB_RCH_OFFSET     8
00216 #define DFSDM_FLTCR2_EXCH_OFFSET        POSITION_VAL(DFSDM_FLTCR2_EXCH)
00217 #define DFSDM_FLTCR2_AWDCH_OFFSET       POSITION_VAL(DFSDM_FLTCR2_AWDCH)
00218 #define DFSDM_FLTISR_CKABF_OFFSET       POSITION_VAL(DFSDM_FLTISR_CKABF)
00219 #define DFSDM_FLTISR_SCDF_OFFSET        POSITION_VAL(DFSDM_FLTISR_SCDF)
00220 #define DFSDM_FLTICR_CLRCKABF_OFFSET    POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
00221 #define DFSDM_FLTICR_CLRSCDF_OFFSET     POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)
00222 #define DFSDM_FLTRDATAR_DATA_OFFSET     POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
00223 #define DFSDM_FLTJDATAR_DATA_OFFSET     POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
00224 #define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
00225 #define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
00226 #define DFSDM_FLTEXMAX_DATA_OFFSET      POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
00227 #define DFSDM_FLTEXMIN_DATA_OFFSET      POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
00228 #define DFSDM_FLTCNVTIMR_DATA_OFFSET    POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
00229 #define DFSDM_FLTAWSR_HIGH_OFFSET       POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
00230 #define DFSDM_MSB_MASK               0xFFFF0000U
00231 #define DFSDM_LSB_MASK               0x0000FFFFU
00232 #define DFSDM_CKAB_TIMEOUT           5000U
00233 #define DFSDM1_CHANNEL_NUMBER           8U
00234 /**
00235   * @}
00236   */
00237
00238 /* Private macro -------------------------------------------------------------*/
00239 /* Private variables ---------------------------------------------------------*/
00240 /** @defgroup DFSDM_Private_Variables DFSDM Private Variables
00241   * @{
00242   */
00243 __IO uint32_t                v_dfsdm1ChannelCounter = 0;
00244 DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
00245 /**
00246   * @}
00247   */
00248
00249 /* Private function prototypes -----------------------------------------------*/
00250 /** @defgroup DFSDM_Private_Functions DFSDM Private Functions
00251   * @{
00252   */
00253 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
00254 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);
00255 static void     DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00256 static void     DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
00257 static void     DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
00258 static void     DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
00259 static void     DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
00260 static void     DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
00261 static void     DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
00262 static void     DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
00263 static void     DFSDM_DMAError(DMA_HandleTypeDef *hdma);
00264 /**
00265   * @}
00266   */
00267
00268 /* Exported functions --------------------------------------------------------*/
00269 /** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions
00270   * @{
00271   */
00272
00273 /** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
00274  *  @brief    Channel initialization and de-initialization functions
00275  *
00276 @verbatim
00277   ==============================================================================
00278         ##### Channel initialization and de-initialization functions #####
00279   ==============================================================================
00280     [..]  This section provides functions allowing to:
00281       (+) Initialize the DFSDM channel.
00282       (+) De-initialize the DFSDM channel.
00283 @endverbatim
00284   * @{
00285   */
00286
00287 /**
00288   * @brief  Initialize the DFSDM channel according to the specified parameters
00289   *         in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
00290   * @param  hdfsdm_channel : DFSDM channel handle.
00291   * @retval HAL status.
00292   */
00293 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00294 {
00295   /* Check DFSDM Channel handle */
00296   if(hdfsdm_channel == NULL)
00297   {
00298     return HAL_ERROR;
00299   }
00300
00301   /* Check parameters */
00302   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00303   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
00304   assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
00305   assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
00306   assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
00307   assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
00308   assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
00309   assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
00310   assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
00311   assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
00312   assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
00313
00314   /* Check that channel has not been already initialized */
00315   if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
00316   {
00317     return HAL_ERROR;
00318   }
00319
00320   /* Call MSP init function */
00321   HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
00322
00323   /* Update the channel counter */
00324   v_dfsdm1ChannelCounter++;
00325
00326   /* Configure output serial clock and enable global DFSDM interface only for first channel */
00327   if(v_dfsdm1ChannelCounter == 1)
00328   {
00329     assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
00330     /* Set the output serial clock source */
00331     DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
00332     DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
00333
00334     /* Reset clock divider */
00335     DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
00336     if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
00337     {
00338       assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
00339       /* Set the output clock divider */
00340       DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) <<
00341                                              DFSDM_CHCFGR1_CLK_DIV_OFFSET);
00342     }
00343
00344     /* enable the DFSDM global interface */
00345     DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
00346   }
00347
00348   /* Set channel input parameters */
00349   hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
00350                                          DFSDM_CHCFGR1_CHINSEL);
00351   hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
00352                                         hdfsdm_channel->Init.Input.DataPacking |
00353                                         hdfsdm_channel->Init.Input.Pins);
00354
00355   /* Set serial interface parameters */
00356   hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
00357   hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
00358                                         hdfsdm_channel->Init.SerialInterface.SpiClock);
00359
00360   /* Set analog watchdog parameters */
00361   hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
00362   hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
00363                                        ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET));
00364
00365   /* Set channel offset and right bit shift */
00366   hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
00367   hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) |
00368                                         (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));
00369
00370   /* Enable DFSDM channel */
00371   hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
00372
00373   /* Set DFSDM Channel to ready state */
00374   hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
00375
00376   /* Store channel handle in DFSDM channel handle table */
00377   a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
00378
00379   return HAL_OK;
00380 }
00381
00382 /**
00383   * @brief  De-initialize the DFSDM channel.
00384   * @param  hdfsdm_channel : DFSDM channel handle.
00385   * @retval HAL status.
00386   */
00387 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00388 {
00389   /* Check DFSDM Channel handle */
00390   if(hdfsdm_channel == NULL)
00391   {
00392     return HAL_ERROR;
00393   }
00394
00395   /* Check parameters */
00396   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00397
00398   /* Check that channel has not been already deinitialized */
00399   if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
00400   {
00401     return HAL_ERROR;
00402   }
00403
00404   /* Disable the DFSDM channel */
00405   hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
00406
00407   /* Update the channel counter */
00408   v_dfsdm1ChannelCounter--;
00409
00410   /* Disable global DFSDM at deinit of last channel */
00411   if(v_dfsdm1ChannelCounter == 0)
00412   {
00413     DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
00414   }
00415
00416   /* Call MSP deinit function */
00417   HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
00418
00419   /* Set DFSDM Channel in reset state */
00420   hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
00421
00422   /* Reset channel handle in DFSDM channel handle table */
00423   a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
00424
00425   return HAL_OK;
00426 }
00427
00428 /**
00429   * @brief  Initialize the DFSDM channel MSP.
00430   * @param  hdfsdm_channel : DFSDM channel handle.
00431   * @retval None
00432   */
00433 __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00434 {
00435   /* Prevent unused argument(s) compilation warning */
00436   UNUSED(hdfsdm_channel);
00437
00438   /* NOTE : This function should not be modified, when the function is needed,
00439             the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
00440    */
00441 }
00442
00443 /**
00444   * @brief  De-initialize the DFSDM channel MSP.
00445   * @param  hdfsdm_channel : DFSDM channel handle.
00446   * @retval None
00447   */
00448 __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00449 {
00450   /* Prevent unused argument(s) compilation warning */
00451   UNUSED(hdfsdm_channel);
00452
00453   /* NOTE : This function should not be modified, when the function is needed,
00454             the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
00455    */
00456 }
00457
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
00463  *  @brief    Channel operation functions
00464  *
00465 @verbatim
00466   ==============================================================================
00467                    ##### Channel operation functions #####
00468   ==============================================================================
00469     [..]  This section provides functions allowing to:
00470       (+) Manage clock absence detector feature.
00471       (+) Manage short circuit detector feature.
00472       (+) Get analog watchdog value.
00473       (+) Modify offset value.
00474 @endverbatim
00475   * @{
00476   */
00477
00478 /**
00479   * @brief  This function allows to start clock absence detection in polling mode.
00480   * @note   Same mode has to be used for all channels.
00481   * @note   If clock is not available on this channel during 5 seconds,
00482   *         clock absence detection will not be activated and function
00483   *         will return HAL_TIMEOUT error.
00484   * @param  hdfsdm_channel : DFSDM channel handle.
00485   * @retval HAL status
00486   */
00487 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00488 {
00489   HAL_StatusTypeDef status = HAL_OK;
00490   uint32_t channel;
00491   uint32_t tickstart;
00492
00493   /* Check parameters */
00494   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00495
00496   /* Check DFSDM channel state */
00497   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00498   {
00499     /* Return error status */
00500     status = HAL_ERROR;
00501   }
00502   else
00503   {
00504     /* Get channel number from channel instance */
00505     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00506
00507     /* Get timeout */
00508     tickstart = HAL_GetTick();
00509
00510     /* Clear clock absence flag */
00511     while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
00512     {
00513       DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
00514
00515       /* Check the Timeout */
00516       if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
00517       {
00518         /* Set timeout status */
00519         status = HAL_TIMEOUT;
00520         break;
00521       }
00522     }
00523
00524     if(status == HAL_OK)
00525     {
00526       /* Start clock absence detection */
00527       hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
00528     }
00529   }
00530   /* Return function status */
00531   return status;
00532 }
00533
00534 /**
00535   * @brief  This function allows to poll for the clock absence detection.
00536   * @param  hdfsdm_channel : DFSDM channel handle.
00537   * @param  Timeout : Timeout value in milliseconds.
00538   * @retval HAL status
00539   */
00540 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00541                                                uint32_t Timeout)
00542 {
00543   uint32_t tickstart;
00544   uint32_t channel;
00545
00546   /* Check parameters */
00547   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00548
00549   /* Check DFSDM channel state */
00550   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00551   {
00552     /* Return error status */
00553     return HAL_ERROR;
00554   }
00555   else
00556   {
00557     /* Get channel number from channel instance */
00558     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00559
00560     /* Get timeout */
00561     tickstart = HAL_GetTick();
00562
00563     /* Wait clock absence detection */
00564     while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0)
00565     {
00566       /* Check the Timeout */
00567       if(Timeout != HAL_MAX_DELAY)
00568       {
00569         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00570         {
00571           /* Return timeout status */
00572           return HAL_TIMEOUT;
00573         }
00574       }
00575     }
00576
00577     /* Clear clock absence detection flag */
00578     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
00579
00580     /* Return function status */
00581     return HAL_OK;
00582   }
00583 }
00584
00585 /**
00586   * @brief  This function allows to stop clock absence detection in polling mode.
00587   * @param  hdfsdm_channel : DFSDM channel handle.
00588   * @retval HAL status
00589   */
00590 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00591 {
00592   HAL_StatusTypeDef status = HAL_OK;
00593   uint32_t channel;
00594
00595   /* Check parameters */
00596   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00597
00598   /* Check DFSDM channel state */
00599   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00600   {
00601     /* Return error status */
00602     status = HAL_ERROR;
00603   }
00604   else
00605   {
00606     /* Stop clock absence detection */
00607     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
00608
00609     /* Clear clock absence flag */
00610     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00611     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
00612   }
00613   /* Return function status */
00614   return status;
00615 }
00616
00617 /**
00618   * @brief  This function allows to start clock absence detection in interrupt mode.
00619   * @note   Same mode has to be used for all channels.
00620   * @note   If clock is not available on this channel during 5 seconds,
00621   *         clock absence detection will not be activated and function
00622   *         will return HAL_TIMEOUT error.
00623   * @param  hdfsdm_channel : DFSDM channel handle.
00624   * @retval HAL status
00625   */
00626 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00627 {
00628   HAL_StatusTypeDef status = HAL_OK;
00629   uint32_t channel;
00630   uint32_t tickstart;
00631
00632   /* Check parameters */
00633   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00634
00635   /* Check DFSDM channel state */
00636   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00637   {
00638     /* Return error status */
00639     status = HAL_ERROR;
00640   }
00641   else
00642   {
00643     /* Get channel number from channel instance */
00644     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00645
00646     /* Get timeout */
00647     tickstart = HAL_GetTick();
00648
00649     /* Clear clock absence flag */
00650     while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
00651     {
00652       DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
00653
00654       /* Check the Timeout */
00655       if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
00656       {
00657         /* Set timeout status */
00658         status = HAL_TIMEOUT;
00659         break;
00660       }
00661     }
00662
00663     if(status == HAL_OK)
00664     {
00665       /* Activate clock absence detection interrupt */
00666       DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
00667
00668       /* Start clock absence detection */
00669       hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
00670     }
00671   }
00672   /* Return function status */
00673   return status;
00674 }
00675
00676 /**
00677   * @brief  Clock absence detection callback.
00678   * @param  hdfsdm_channel : DFSDM channel handle.
00679   * @retval None
00680   */
00681 __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00682 {
00683   /* Prevent unused argument(s) compilation warning */
00684   UNUSED(hdfsdm_channel);
00685
00686   /* NOTE : This function should not be modified, when the callback is needed,
00687             the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
00688    */
00689 }
00690
00691 /**
00692   * @brief  This function allows to stop clock absence detection in interrupt mode.
00693   * @note   Interrupt will be disabled for all channels
00694   * @param  hdfsdm_channel : DFSDM channel handle.
00695   * @retval HAL status
00696   */
00697 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00698 {
00699   HAL_StatusTypeDef status = HAL_OK;
00700   uint32_t channel;
00701
00702   /* Check parameters */
00703   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00704
00705   /* Check DFSDM channel state */
00706   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00707   {
00708     /* Return error status */
00709     status = HAL_ERROR;
00710   }
00711   else
00712   {
00713     /* Stop clock absence detection */
00714     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
00715
00716     /* Clear clock absence flag */
00717     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00718     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
00719
00720     /* Disable clock absence detection interrupt */
00721     DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
00722   }
00723   /* Return function status */
00724   return status;
00725 }
00726
00727 /**
00728   * @brief  This function allows to start short circuit detection in polling mode.
00729   * @note   Same mode has to be used for all channels
00730   * @param  hdfsdm_channel : DFSDM channel handle.
00731   * @param  Threshold : Short circuit detector threshold.
00732   *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.
00733   * @param  BreakSignal : Break signals assigned to short circuit event.
00734   *         This parameter can be a values combination of @ref DFSDM_BreakSignals.
00735   * @retval HAL status
00736   */
00737 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00738                                             uint32_t Threshold,
00739                                             uint32_t BreakSignal)
00740 {
00741   HAL_StatusTypeDef status = HAL_OK;
00742
00743   /* Check parameters */
00744   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00745   assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
00746   assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
00747
00748   /* Check DFSDM channel state */
00749   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00750   {
00751     /* Return error status */
00752     status = HAL_ERROR;
00753   }
00754   else
00755   {
00756     /* Configure threshold and break signals */
00757     hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
00758     hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
00759                                          Threshold);
00760
00761     /* Start short circuit detection */
00762     hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
00763   }
00764   /* Return function status */
00765   return status;
00766 }
00767
00768 /**
00769   * @brief  This function allows to poll for the short circuit detection.
00770   * @param  hdfsdm_channel : DFSDM channel handle.
00771   * @param  Timeout : Timeout value in milliseconds.
00772   * @retval HAL status
00773   */
00774 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00775                                               uint32_t Timeout)
00776 {
00777   uint32_t tickstart;
00778   uint32_t channel;
00779
00780   /* Check parameters */
00781   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00782
00783   /* Check DFSDM channel state */
00784   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00785   {
00786     /* Return error status */
00787     return HAL_ERROR;
00788   }
00789   else
00790   {
00791     /* Get channel number from channel instance */
00792     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00793
00794     /* Get timeout */
00795     tickstart = HAL_GetTick();
00796
00797     /* Wait short circuit detection */
00798     while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0)
00799     {
00800       /* Check the Timeout */
00801       if(Timeout != HAL_MAX_DELAY)
00802       {
00803         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00804         {
00805           /* Return timeout status */
00806           return HAL_TIMEOUT;
00807         }
00808       }
00809     }
00810
00811     /* Clear short circuit detection flag */
00812     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
00813
00814     /* Return function status */
00815     return HAL_OK;
00816   }
00817 }
00818
00819 /**
00820   * @brief  This function allows to stop short circuit detection in polling mode.
00821   * @param  hdfsdm_channel : DFSDM channel handle.
00822   * @retval HAL status
00823   */
00824 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00825 {
00826   HAL_StatusTypeDef status = HAL_OK;
00827   uint32_t channel;
00828
00829   /* Check parameters */
00830   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00831
00832   /* Check DFSDM channel state */
00833   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00834   {
00835     /* Return error status */
00836     status = HAL_ERROR;
00837   }
00838   else
00839   {
00840     /* Stop short circuit detection */
00841     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
00842
00843     /* Clear short circuit detection flag */
00844     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00845     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
00846   }
00847   /* Return function status */
00848   return status;
00849 }
00850
00851 /**
00852   * @brief  This function allows to start short circuit detection in interrupt mode.
00853   * @note   Same mode has to be used for all channels
00854   * @param  hdfsdm_channel : DFSDM channel handle.
00855   * @param  Threshold : Short circuit detector threshold.
00856   *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.
00857   * @param  BreakSignal : Break signals assigned to short circuit event.
00858   *         This parameter can be a values combination of @ref DFSDM_BreakSignals.
00859   * @retval HAL status
00860   */
00861 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00862                                                uint32_t Threshold,
00863                                                uint32_t BreakSignal)
00864 {
00865   HAL_StatusTypeDef status = HAL_OK;
00866
00867   /* Check parameters */
00868   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00869   assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
00870   assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
00871
00872   /* Check DFSDM channel state */
00873   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00874   {
00875     /* Return error status */
00876     status = HAL_ERROR;
00877   }
00878   else
00879   {
00880     /* Activate short circuit detection interrupt */
00881     DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
00882
00883     /* Configure threshold and break signals */
00884     hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
00885     hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
00886                                          Threshold);
00887
00888     /* Start short circuit detection */
00889     hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
00890   }
00891   /* Return function status */
00892   return status;
00893 }
00894
00895 /**
00896   * @brief  Short circuit detection callback.
00897   * @param  hdfsdm_channel : DFSDM channel handle.
00898   * @retval None
00899   */
00900 __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00901 {
00902   /* Prevent unused argument(s) compilation warning */
00903   UNUSED(hdfsdm_channel);
00904
00905   /* NOTE : This function should not be modified, when the callback is needed,
00906             the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
00907    */
00908 }
00909
00910 /**
00911   * @brief  This function allows to stop short circuit detection in interrupt mode.
00912   * @note   Interrupt will be disabled for all channels
00913   * @param  hdfsdm_channel : DFSDM channel handle.
00914   * @retval HAL status
00915   */
00916 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00917 {
00918   HAL_StatusTypeDef status = HAL_OK;
00919   uint32_t channel;
00920
00921   /* Check parameters */
00922   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00923
00924   /* Check DFSDM channel state */
00925   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00926   {
00927     /* Return error status */
00928     status = HAL_ERROR;
00929   }
00930   else
00931   {
00932     /* Stop short circuit detection */
00933     hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
00934
00935     /* Clear short circuit detection flag */
00936     channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
00937     DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
00938
00939     /* Disable short circuit detection interrupt */
00940     DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
00941   }
00942   /* Return function status */
00943   return status;
00944 }
00945
00946 /**
00947   * @brief  This function allows to get channel analog watchdog value.
00948   * @param  hdfsdm_channel : DFSDM channel handle.
00949   * @retval Channel analog watchdog value.
00950   */
00951 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
00952 {
00953   return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
00954 }
00955
00956 /**
00957   * @brief  This function allows to modify channel offset value.
00958   * @param  hdfsdm_channel : DFSDM channel handle.
00959   * @param  Offset : DFSDM channel offset.
00960   *         This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
00961   * @retval HAL status.
00962   */
00963 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
00964                                                 int32_t Offset)
00965 {
00966   HAL_StatusTypeDef status = HAL_OK;
00967
00968   /* Check parameters */
00969   assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
00970   assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
00971
00972   /* Check DFSDM channel state */
00973   if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
00974   {
00975     /* Return error status */
00976     status = HAL_ERROR;
00977   }
00978   else
00979   {
00980     /* Modify channel offset */
00981     hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
00982     hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);
00983   }
00984   /* Return function status */
00985   return status;
00986 }
00987
00988 /**
00989   * @}
00990   */
00991
00992 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
00993  *  @brief    Channel state function
00994  *
00995 @verbatim
00996   ==============================================================================
00997                    ##### Channel state function #####
00998   ==============================================================================
00999     [..]  This section provides function allowing to:
01000       (+) Get channel handle state.
01001 @endverbatim
01002   * @{
01003   */
01004
01005 /**
01006   * @brief  This function allows to get the current DFSDM channel handle state.
01007   * @param  hdfsdm_channel : DFSDM channel handle.
01008   * @retval DFSDM channel state.
01009   */
01010 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
01011 {
01012   /* Return DFSDM channel handle state */
01013   return hdfsdm_channel->State;
01014 }
01015
01016 /**
01017   * @}
01018   */
01019
01020 /** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
01021  *  @brief    Filter initialization and de-initialization functions
01022  *
01023 @verbatim
01024   ==============================================================================
01025         ##### Filter initialization and de-initialization functions #####
01026   ==============================================================================
01027     [..]  This section provides functions allowing to:
01028       (+) Initialize the DFSDM filter.
01029       (+) De-initialize the DFSDM filter.
01030 @endverbatim
01031   * @{
01032   */
01033
01034 /**
01035   * @brief  Initialize the DFSDM filter according to the specified parameters
01036   *         in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
01037   * @param  hdfsdm_filter : DFSDM filter handle.
01038   * @retval HAL status.
01039   */
01040 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01041 {
01042   /* Check DFSDM Channel handle */
01043   if(hdfsdm_filter == NULL)
01044   {
01045     return HAL_ERROR;
01046   }
01047
01048   /* Check parameters */
01049   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01050   assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
01051   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
01052   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
01053   assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
01054   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
01055   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
01056   assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
01057   assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
01058   assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
01059
01060   /* Check parameters compatibility */
01061   if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
01062     ((hdfsdm_filter->Init.RegularParam.Trigger  == DFSDM_FILTER_SYNC_TRIGGER) ||
01063      (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
01064   {
01065     return HAL_ERROR;
01066   }
01067
01068   /* Initialize DFSDM filter variables with default values */
01069   hdfsdm_filter->RegularContMode     = DFSDM_CONTINUOUS_CONV_OFF;
01070   hdfsdm_filter->InjectedChannelsNbr = 1;
01071   hdfsdm_filter->InjConvRemaining    = 1;
01072   hdfsdm_filter->ErrorCode           = DFSDM_FILTER_ERROR_NONE;
01073
01074   /* Call MSP init function */
01075   HAL_DFSDM_FilterMspInit(hdfsdm_filter);
01076
01077   /* Set regular parameters */
01078   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
01079   if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
01080   {
01081     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
01082   }
01083   else
01084   {
01085     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
01086   }
01087
01088   if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
01089   {
01090     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
01091   }
01092   else
01093   {
01094     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
01095   }
01096
01097   /* Set injected parameters */
01098   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
01099   if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
01100   {
01101     assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
01102     assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
01103     hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
01104   }
01105
01106   if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
01107   {
01108     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
01109   }
01110   else
01111   {
01112     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
01113   }
01114
01115   if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
01116   {
01117     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
01118   }
01119   else
01120   {
01121     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
01122   }
01123
01124   /* Set filter parameters */
01125   hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
01126   hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
01127                                     ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) |
01128                                   (hdfsdm_filter->Init.FilterParam.IntOversampling - 1));
01129
01130   /* Store regular and injected triggers and injected scan mode*/
01131   hdfsdm_filter->RegularTrigger   = hdfsdm_filter->Init.RegularParam.Trigger;
01132   hdfsdm_filter->InjectedTrigger  = hdfsdm_filter->Init.InjectedParam.Trigger;
01133   hdfsdm_filter->ExtTriggerEdge   = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
01134   hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
01135
01136   /* Enable DFSDM filter */
01137   hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
01138
01139   /* Set DFSDM filter to ready state */
01140   hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
01141
01142   return HAL_OK;
01143 }
01144
01145 /**
01146   * @brief  De-initializes the DFSDM filter.
01147   * @param  hdfsdm_filter : DFSDM filter handle.
01148   * @retval HAL status.
01149   */
01150 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01151 {
01152   /* Check DFSDM filter handle */
01153   if(hdfsdm_filter == NULL)
01154   {
01155     return HAL_ERROR;
01156   }
01157
01158   /* Check parameters */
01159   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01160
01161   /* Disable the DFSDM filter */
01162   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
01163
01164   /* Call MSP deinit function */
01165   HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
01166
01167   /* Set DFSDM filter in reset state */
01168   hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
01169
01170   return HAL_OK;
01171 }
01172
01173 /**
01174   * @brief  Initializes the DFSDM filter MSP.
01175   * @param  hdfsdm_filter : DFSDM filter handle.
01176   * @retval None
01177   */
01178 __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01179 {
01180   /* Prevent unused argument(s) compilation warning */
01181   UNUSED(hdfsdm_filter);
01182
01183   /* NOTE : This function should not be modified, when the function is needed,
01184             the HAL_DFSDM_FilterMspInit could be implemented in the user file.
01185    */
01186 }
01187
01188 /**
01189   * @brief  De-initializes the DFSDM filter MSP.
01190   * @param  hdfsdm_filter : DFSDM filter handle.
01191   * @retval None
01192   */
01193 __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01194 {
01195   /* Prevent unused argument(s) compilation warning */
01196   UNUSED(hdfsdm_filter);
01197
01198   /* NOTE : This function should not be modified, when the function is needed,
01199             the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
01200    */
01201 }
01202
01203 /**
01204   * @}
01205   */
01206
01207 /** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
01208  *  @brief    Filter control functions
01209  *
01210 @verbatim
01211   ==============================================================================
01212                     ##### Filter control functions #####
01213   ==============================================================================
01214     [..]  This section provides functions allowing to:
01215       (+) Select channel and enable/disable continuous mode for regular conversion.
01216       (+) Select channels for injected conversion.
01217 @endverbatim
01218   * @{
01219   */
01220
01221 /**
01222   * @brief  This function allows to select channel and to enable/disable
01223   *         continuous mode for regular conversion.
01224   * @param  hdfsdm_filter : DFSDM filter handle.
01225   * @param  Channel : Channel for regular conversion.
01226   *         This parameter can be a value of @ref DFSDM_Channel_Selection.
01227   * @param  ContinuousMode : Enable/disable continuous mode for regular conversion.
01228   *         This parameter can be a value of @ref DFSDM_ContinuousMode.
01229   * @retval HAL status
01230   */
01231 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01232                                                    uint32_t                    Channel,
01233                                                    uint32_t                    ContinuousMode)
01234 {
01235   HAL_StatusTypeDef status = HAL_OK;
01236
01237   /* Check parameters */
01238   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01239   assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
01240   assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
01241
01242   /* Check DFSDM filter state */
01243   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
01244      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
01245   {
01246     /* Configure channel and continuous mode for regular conversion */
01247     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
01248     if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
01249     {
01250       hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
01251                                                      DFSDM_FLTCR1_RCONT);
01252     }
01253     else
01254     {
01255       hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
01256     }
01257     /* Store continuous mode information */
01258     hdfsdm_filter->RegularContMode = ContinuousMode;
01259   }
01260   else
01261   {
01262     status = HAL_ERROR;
01263   }
01264
01265   /* Return function status */
01266   return status;
01267 }
01268
01269 /**
01270   * @brief  This function allows to select channels for injected conversion.
01271   * @param  hdfsdm_filter : DFSDM filter handle.
01272   * @param  Channel : Channels for injected conversion.
01273   *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.
01274   * @retval HAL status
01275   */
01276 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01277                                                    uint32_t                    Channel)
01278 {
01279   HAL_StatusTypeDef status = HAL_OK;
01280
01281   /* Check parameters */
01282   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01283   assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
01284
01285   /* Check DFSDM filter state */
01286   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
01287      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
01288   {
01289     /* Configure channel for injected conversion */
01290     hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
01291     /* Store number of injected channels */
01292     hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
01293     /* Update number of injected channels remaining */
01294     hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
01295                                       hdfsdm_filter->InjectedChannelsNbr : 1;
01296   }
01297   else
01298   {
01299     status = HAL_ERROR;
01300   }
01301   /* Return function status */
01302   return status;
01303 }
01304
01305 /**
01306   * @}
01307   */
01308
01309 /** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
01310  *  @brief    Filter operation functions
01311  *
01312 @verbatim
01313   ==============================================================================
01314                     ##### Filter operation functions #####
01315   ==============================================================================
01316     [..]  This section provides functions allowing to:
01317       (+) Start conversion of regular/injected channel.
01318       (+) Poll for the end of regular/injected conversion.
01319       (+) Stop conversion of regular/injected channel.
01320       (+) Start conversion of regular/injected channel and enable interrupt.
01321       (+) Call the callback functions at the end of regular/injected conversions.
01322       (+) Stop conversion of regular/injected channel and disable interrupt.
01323       (+) Start conversion of regular/injected channel and enable DMA transfer.
01324       (+) Stop conversion of regular/injected channel and disable DMA transfer.
01325       (+) Start analog watchdog and enable interrupt.
01326       (+) Call the callback function when analog watchdog occurs.
01327       (+) Stop analog watchdog and disable interrupt.
01328       (+) Start extreme detector.
01329       (+) Stop extreme detector.
01330       (+) Get result of regular channel conversion.
01331       (+) Get result of injected channel conversion.
01332       (+) Get extreme detector maximum and minimum values.
01333       (+) Get conversion time.
01334       (+) Handle DFSDM interrupt request.
01335 @endverbatim
01336   * @{
01337   */
01338
01339 /**
01340   * @brief  This function allows to start regular conversion in polling mode.
01341   * @note   This function should be called only when DFSDM filter instance is
01342   *         in idle state or if injected conversion is ongoing.
01343   * @param  hdfsdm_filter : DFSDM filter handle.
01344   * @retval HAL status
01345   */
01346 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01347 {
01348   HAL_StatusTypeDef status = HAL_OK;
01349
01350   /* Check parameters */
01351   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01352
01353   /* Check DFSDM filter state */
01354   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01355      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
01356   {
01357     /* Start regular conversion */
01358     DFSDM_RegConvStart(hdfsdm_filter);
01359   }
01360   else
01361   {
01362     status = HAL_ERROR;
01363   }
01364   /* Return function status */
01365   return status;
01366 }
01367
01368 /**
01369   * @brief  This function allows to poll for the end of regular conversion.
01370   * @note   This function should be called only if regular conversion is ongoing.
01371   * @param  hdfsdm_filter : DFSDM filter handle.
01372   * @param  Timeout : Timeout value in milliseconds.
01373   * @retval HAL status
01374   */
01375 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01376                                                        uint32_t                    Timeout)
01377 {
01378   uint32_t tickstart;
01379
01380   /* Check parameters */
01381   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01382
01383   /* Check DFSDM filter state */
01384   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
01385      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01386   {
01387     /* Return error status */
01388     return HAL_ERROR;
01389   }
01390   else
01391   {
01392     /* Get timeout */
01393     tickstart = HAL_GetTick();
01394
01395     /* Wait end of regular conversion */
01396     while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
01397     {
01398       /* Check the Timeout */
01399       if(Timeout != HAL_MAX_DELAY)
01400       {
01401         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01402         {
01403           /* Return timeout status */
01404           return HAL_TIMEOUT;
01405         }
01406       }
01407     }
01408     /* Check if overrun occurs */
01409     if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
01410     {
01411       /* Update error code and call error callback */
01412       hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
01413       HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
01414
01415       /* Clear regular overrun flag */
01416       hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
01417     }
01418     /* Update DFSDM filter state only if not continuous conversion and SW trigger */
01419     if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
01420        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
01421     {
01422       hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
01423                              HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
01424     }
01425     /* Return function status */
01426     return HAL_OK;
01427   }
01428 }
01429
01430 /**
01431   * @brief  This function allows to stop regular conversion in polling mode.
01432   * @note   This function should be called only if regular conversion is ongoing.
01433   * @param  hdfsdm_filter : DFSDM filter handle.
01434   * @retval HAL status
01435   */
01436 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01437 {
01438   HAL_StatusTypeDef status = HAL_OK;
01439
01440   /* Check parameters */
01441   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01442
01443   /* Check DFSDM filter state */
01444   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
01445      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01446   {
01447     /* Return error status */
01448     status = HAL_ERROR;
01449   }
01450   else
01451   {
01452     /* Stop regular conversion */
01453     DFSDM_RegConvStop(hdfsdm_filter);
01454   }
01455   /* Return function status */
01456   return status;
01457 }
01458
01459 /**
01460   * @brief  This function allows to start regular conversion in interrupt mode.
01461   * @note   This function should be called only when DFSDM filter instance is
01462   *         in idle state or if injected conversion is ongoing.
01463   * @param  hdfsdm_filter : DFSDM filter handle.
01464   * @retval HAL status
01465   */
01466 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01467 {
01468   HAL_StatusTypeDef status = HAL_OK;
01469
01470   /* Check parameters */
01471   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01472
01473   /* Check DFSDM filter state */
01474   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01475      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
01476   {
01477     /* Enable interrupts for regular conversions */
01478     hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
01479
01480     /* Start regular conversion */
01481     DFSDM_RegConvStart(hdfsdm_filter);
01482   }
01483   else
01484   {
01485     status = HAL_ERROR;
01486   }
01487   /* Return function status */
01488   return status;
01489 }
01490
01491 /**
01492   * @brief  This function allows to stop regular conversion in interrupt mode.
01493   * @note   This function should be called only if regular conversion is ongoing.
01494   * @param  hdfsdm_filter : DFSDM filter handle.
01495   * @retval HAL status
01496   */
01497 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01498 {
01499   HAL_StatusTypeDef status = HAL_OK;
01500
01501   /* Check parameters */
01502   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01503
01504   /* Check DFSDM filter state */
01505   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
01506      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01507   {
01508     /* Return error status */
01509     status = HAL_ERROR;
01510   }
01511   else
01512   {
01513     /* Disable interrupts for regular conversions */
01514     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
01515
01516     /* Stop regular conversion */
01517     DFSDM_RegConvStop(hdfsdm_filter);
01518   }
01519   /* Return function status */
01520   return status;
01521 }
01522
01523 /**
01524   * @brief  This function allows to start regular conversion in DMA mode.
01525   * @note   This function should be called only when DFSDM filter instance is
01526   *         in idle state or if injected conversion is ongoing.
01527   *         Please note that data on buffer will contain signed regular conversion
01528   *         value on 24 most significant bits and corresponding channel on 3 least
01529   *         significant bits.
01530   * @param  hdfsdm_filter : DFSDM filter handle.
01531   * @param  pData : The destination buffer address.
01532   * @param  Length : The length of data to be transferred from DFSDM filter to memory.
01533   * @retval HAL status
01534   */
01535 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01536                                                    int32_t                    *pData,
01537                                                    uint32_t                    Length)
01538 {
01539   HAL_StatusTypeDef status = HAL_OK;
01540
01541   /* Check parameters */
01542   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01543
01544   /* Check destination address and length */
01545   if((pData == NULL) || (Length == 0))
01546   {
01547     status = HAL_ERROR;
01548   }
01549   /* Check that DMA is enabled for regular conversion */
01550   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
01551   {
01552     status = HAL_ERROR;
01553   }
01554   /* Check parameters compatibility */
01555   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01556           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
01557           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
01558           (Length != 1))
01559   {
01560     status = HAL_ERROR;
01561   }
01562   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01563           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
01564           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
01565   {
01566     status = HAL_ERROR;
01567   }
01568   /* Check DFSDM filter state */
01569   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01570           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
01571   {
01572     /* Set callbacks on DMA handler */
01573     hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
01574     hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
01575     hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
01576                                                    DFSDM_DMARegularHalfConvCplt : NULL;
01577
01578     /* Start DMA in interrupt mode */
01579     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
01580                         (uint32_t) pData, Length) != HAL_OK)
01581     {
01582       /* Set DFSDM filter in error state */
01583       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
01584       status = HAL_ERROR;
01585     }
01586     else
01587     {
01588       /* Start regular conversion */
01589       DFSDM_RegConvStart(hdfsdm_filter);
01590     }
01591   }
01592   else
01593   {
01594     status = HAL_ERROR;
01595   }
01596   /* Return function status */
01597   return status;
01598 }
01599
01600 /**
01601   * @brief  This function allows to start regular conversion in DMA mode and to get
01602   *         only the 16 most significant bits of conversion.
01603   * @note   This function should be called only when DFSDM filter instance is
01604   *         in idle state or if injected conversion is ongoing.
01605   *         Please note that data on buffer will contain signed 16 most significant
01606   *         bits of regular conversion.
01607   * @param  hdfsdm_filter : DFSDM filter handle.
01608   * @param  pData : The destination buffer address.
01609   * @param  Length : The length of data to be transferred from DFSDM filter to memory.
01610   * @retval HAL status
01611   */
01612 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01613                                                       int16_t                    *pData,
01614                                                       uint32_t                    Length)
01615 {
01616   HAL_StatusTypeDef status = HAL_OK;
01617
01618   /* Check parameters */
01619   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01620
01621   /* Check destination address and length */
01622   if((pData == NULL) || (Length == 0))
01623   {
01624     status = HAL_ERROR;
01625   }
01626   /* Check that DMA is enabled for regular conversion */
01627   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
01628   {
01629     status = HAL_ERROR;
01630   }
01631   /* Check parameters compatibility */
01632   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01633           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
01634           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
01635           (Length != 1))
01636   {
01637     status = HAL_ERROR;
01638   }
01639   else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01640           (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
01641           (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
01642   {
01643     status = HAL_ERROR;
01644   }
01645   /* Check DFSDM filter state */
01646   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01647           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
01648   {
01649     /* Set callbacks on DMA handler */
01650     hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
01651     hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
01652     hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
01653                                                    DFSDM_DMARegularHalfConvCplt : NULL;
01654
01655     /* Start DMA in interrupt mode */
01656     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \
01657                         (uint32_t) pData, Length) != HAL_OK)
01658     {
01659       /* Set DFSDM filter in error state */
01660       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
01661       status = HAL_ERROR;
01662     }
01663     else
01664     {
01665       /* Start regular conversion */
01666       DFSDM_RegConvStart(hdfsdm_filter);
01667     }
01668   }
01669   else
01670   {
01671     status = HAL_ERROR;
01672   }
01673   /* Return function status */
01674   return status;
01675 }
01676
01677 /**
01678   * @brief  This function allows to stop regular conversion in DMA mode.
01679   * @note   This function should be called only if regular conversion is ongoing.
01680   * @param  hdfsdm_filter : DFSDM filter handle.
01681   * @retval HAL status
01682   */
01683 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01684 {
01685   HAL_StatusTypeDef status = HAL_OK;
01686
01687   /* Check parameters */
01688   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01689
01690   /* Check DFSDM filter state */
01691   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
01692      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01693   {
01694     /* Return error status */
01695     status = HAL_ERROR;
01696   }
01697   else
01698   {
01699     /* Stop current DMA transfer */
01700     if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
01701     {
01702       /* Set DFSDM filter in error state */
01703       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
01704       status = HAL_ERROR;
01705     }
01706     else
01707     {
01708       /* Stop regular conversion */
01709       DFSDM_RegConvStop(hdfsdm_filter);
01710     }
01711   }
01712   /* Return function status */
01713   return status;
01714 }
01715
01716 /**
01717   * @brief  This function allows to get regular conversion value.
01718   * @param  hdfsdm_filter : DFSDM filter handle.
01719   * @param  Channel : Corresponding channel of regular conversion.
01720   * @retval Regular conversion value
01721   */
01722 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01723                                         uint32_t                   *Channel)
01724 {
01725   uint32_t reg = 0;
01726   int32_t  value = 0;
01727
01728   /* Check parameters */
01729   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01730   assert_param(Channel != NULL);
01731
01732   /* Get value of data register for regular channel */
01733   reg = hdfsdm_filter->Instance->FLTRDATAR;
01734
01735   /* Extract channel and regular conversion value */
01736   *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
01737   value = ((reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
01738
01739   /* return regular conversion value */
01740   return value;
01741 }
01742
01743 /**
01744   * @brief  This function allows to start injected conversion in polling mode.
01745   * @note   This function should be called only when DFSDM filter instance is
01746   *         in idle state or if regular conversion is ongoing.
01747   * @param  hdfsdm_filter : DFSDM filter handle.
01748   * @retval HAL status
01749   */
01750 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01751 {
01752   HAL_StatusTypeDef status = HAL_OK;
01753
01754   /* Check parameters */
01755   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01756
01757   /* Check DFSDM filter state */
01758   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01759      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
01760   {
01761     /* Start injected conversion */
01762     DFSDM_InjConvStart(hdfsdm_filter);
01763   }
01764   else
01765   {
01766     status = HAL_ERROR;
01767   }
01768   /* Return function status */
01769   return status;
01770 }
01771
01772 /**
01773   * @brief  This function allows to poll for the end of injected conversion.
01774   * @note   This function should be called only if injected conversion is ongoing.
01775   * @param  hdfsdm_filter : DFSDM filter handle.
01776   * @param  Timeout : Timeout value in milliseconds.
01777   * @retval HAL status
01778   */
01779 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01780                                                        uint32_t                    Timeout)
01781 {
01782   uint32_t tickstart;
01783
01784   /* Check parameters */
01785   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01786
01787   /* Check DFSDM filter state */
01788   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
01789      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01790   {
01791     /* Return error status */
01792     return HAL_ERROR;
01793   }
01794   else
01795   {
01796     /* Get timeout */
01797     tickstart = HAL_GetTick();
01798
01799     /* Wait end of injected conversions */
01800     while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
01801     {
01802       /* Check the Timeout */
01803       if(Timeout != HAL_MAX_DELAY)
01804       {
01805         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01806         {
01807           /* Return timeout status */
01808           return HAL_TIMEOUT;
01809         }
01810       }
01811     }
01812     /* Check if overrun occurs */
01813     if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
01814     {
01815       /* Update error code and call error callback */
01816       hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
01817       HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
01818
01819       /* Clear injected overrun flag */
01820       hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
01821     }
01822
01823     /* Update remaining injected conversions */
01824     hdfsdm_filter->InjConvRemaining--;
01825     if(hdfsdm_filter->InjConvRemaining == 0)
01826     {
01827       /* Update DFSDM filter state only if trigger is software */
01828       if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
01829       {
01830         hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
01831                                HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
01832       }
01833
01834       /* end of injected sequence, reset the value */
01835       hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
01836                                          hdfsdm_filter->InjectedChannelsNbr : 1;
01837     }
01838
01839     /* Return function status */
01840     return HAL_OK;
01841   }
01842 }
01843
01844 /**
01845   * @brief  This function allows to stop injected conversion in polling mode.
01846   * @note   This function should be called only if injected conversion is ongoing.
01847   * @param  hdfsdm_filter : DFSDM filter handle.
01848   * @retval HAL status
01849   */
01850 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01851 {
01852   HAL_StatusTypeDef status = HAL_OK;
01853
01854   /* Check parameters */
01855   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01856
01857   /* Check DFSDM filter state */
01858   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
01859      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01860   {
01861     /* Return error status */
01862     status = HAL_ERROR;
01863   }
01864   else
01865   {
01866     /* Stop injected conversion */
01867     DFSDM_InjConvStop(hdfsdm_filter);
01868   }
01869   /* Return function status */
01870   return status;
01871 }
01872
01873 /**
01874   * @brief  This function allows to start injected conversion in interrupt mode.
01875   * @note   This function should be called only when DFSDM filter instance is
01876   *         in idle state or if regular conversion is ongoing.
01877   * @param  hdfsdm_filter : DFSDM filter handle.
01878   * @retval HAL status
01879   */
01880 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01881 {
01882   HAL_StatusTypeDef status = HAL_OK;
01883
01884   /* Check parameters */
01885   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01886
01887   /* Check DFSDM filter state */
01888   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01889      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
01890   {
01891     /* Enable interrupts for injected conversions */
01892     hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
01893
01894     /* Start injected conversion */
01895     DFSDM_InjConvStart(hdfsdm_filter);
01896   }
01897   else
01898   {
01899     status = HAL_ERROR;
01900   }
01901   /* Return function status */
01902   return status;
01903 }
01904
01905 /**
01906   * @brief  This function allows to stop injected conversion in interrupt mode.
01907   * @note   This function should be called only if injected conversion is ongoing.
01908   * @param  hdfsdm_filter : DFSDM filter handle.
01909   * @retval HAL status
01910   */
01911 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
01912 {
01913   HAL_StatusTypeDef status = HAL_OK;
01914
01915   /* Check parameters */
01916   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01917
01918   /* Check DFSDM filter state */
01919   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
01920      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
01921   {
01922     /* Return error status */
01923     status = HAL_ERROR;
01924   }
01925   else
01926   {
01927     /* Disable interrupts for injected conversions */
01928     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
01929
01930     /* Stop injected conversion */
01931     DFSDM_InjConvStop(hdfsdm_filter);
01932   }
01933   /* Return function status */
01934   return status;
01935 }
01936
01937 /**
01938   * @brief  This function allows to start injected conversion in DMA mode.
01939   * @note   This function should be called only when DFSDM filter instance is
01940   *         in idle state or if regular conversion is ongoing.
01941   *         Please note that data on buffer will contain signed injected conversion
01942   *         value on 24 most significant bits and corresponding channel on 3 least
01943   *         significant bits.
01944   * @param  hdfsdm_filter : DFSDM filter handle.
01945   * @param  pData : The destination buffer address.
01946   * @param  Length : The length of data to be transferred from DFSDM filter to memory.
01947   * @retval HAL status
01948   */
01949 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
01950                                                     int32_t                    *pData,
01951                                                     uint32_t                    Length)
01952 {
01953   HAL_StatusTypeDef status = HAL_OK;
01954
01955   /* Check parameters */
01956   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
01957
01958   /* Check destination address and length */
01959   if((pData == NULL) || (Length == 0))
01960   {
01961     status = HAL_ERROR;
01962   }
01963   /* Check that DMA is enabled for injected conversion */
01964   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
01965   {
01966     status = HAL_ERROR;
01967   }
01968   /* Check parameters compatibility */
01969   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01970           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
01971           (Length > hdfsdm_filter->InjConvRemaining))
01972   {
01973     status = HAL_ERROR;
01974   }
01975   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
01976           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
01977   {
01978     status = HAL_ERROR;
01979   }
01980   /* Check DFSDM filter state */
01981   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
01982           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
01983   {
01984     /* Set callbacks on DMA handler */
01985     hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
01986     hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
01987     hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
01988                                                    DFSDM_DMAInjectedHalfConvCplt : NULL;
01989
01990     /* Start DMA in interrupt mode */
01991     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
01992                         (uint32_t) pData, Length) != HAL_OK)
01993     {
01994       /* Set DFSDM filter in error state */
01995       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
01996       status = HAL_ERROR;
01997     }
01998     else
01999     {
02000       /* Start injected conversion */
02001       DFSDM_InjConvStart(hdfsdm_filter);
02002     }
02003   }
02004   else
02005   {
02006     status = HAL_ERROR;
02007   }
02008   /* Return function status */
02009   return status;
02010 }
02011
02012 /**
02013   * @brief  This function allows to start injected conversion in DMA mode and to get
02014   *         only the 16 most significant bits of conversion.
02015   * @note   This function should be called only when DFSDM filter instance is
02016   *         in idle state or if regular conversion is ongoing.
02017   *         Please note that data on buffer will contain signed 16 most significant
02018   *         bits of injected conversion.
02019   * @param  hdfsdm_filter : DFSDM filter handle.
02020   * @param  pData : The destination buffer address.
02021   * @param  Length : The length of data to be transferred from DFSDM filter to memory.
02022   * @retval HAL status
02023   */
02024 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02025                                                        int16_t                    *pData,
02026                                                        uint32_t                    Length)
02027 {
02028   HAL_StatusTypeDef status = HAL_OK;
02029
02030   /* Check parameters */
02031   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02032
02033   /* Check destination address and length */
02034   if((pData == NULL) || (Length == 0))
02035   {
02036     status = HAL_ERROR;
02037   }
02038   /* Check that DMA is enabled for injected conversion */
02039   else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
02040   {
02041     status = HAL_ERROR;
02042   }
02043   /* Check parameters compatibility */
02044   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02045           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
02046           (Length > hdfsdm_filter->InjConvRemaining))
02047   {
02048     status = HAL_ERROR;
02049   }
02050   else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
02051           (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
02052   {
02053     status = HAL_ERROR;
02054   }
02055   /* Check DFSDM filter state */
02056   else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
02057           (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
02058   {
02059     /* Set callbacks on DMA handler */
02060     hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
02061     hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
02062     hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
02063                                                    DFSDM_DMAInjectedHalfConvCplt : NULL;
02064
02065     /* Start DMA in interrupt mode */
02066     if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \
02067                         (uint32_t) pData, Length) != HAL_OK)
02068     {
02069       /* Set DFSDM filter in error state */
02070       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
02071       status = HAL_ERROR;
02072     }
02073     else
02074     {
02075       /* Start injected conversion */
02076       DFSDM_InjConvStart(hdfsdm_filter);
02077     }
02078   }
02079   else
02080   {
02081     status = HAL_ERROR;
02082   }
02083   /* Return function status */
02084   return status;
02085 }
02086
02087 /**
02088   * @brief  This function allows to stop injected conversion in DMA mode.
02089   * @note   This function should be called only if injected conversion is ongoing.
02090   * @param  hdfsdm_filter : DFSDM filter handle.
02091   * @retval HAL status
02092   */
02093 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02094 {
02095   HAL_StatusTypeDef status = HAL_OK;
02096
02097   /* Check parameters */
02098   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02099
02100   /* Check DFSDM filter state */
02101   if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
02102      (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
02103   {
02104     /* Return error status */
02105     status = HAL_ERROR;
02106   }
02107   else
02108   {
02109     /* Stop current DMA transfer */
02110     if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
02111     {
02112       /* Set DFSDM filter in error state */
02113       hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
02114       status = HAL_ERROR;
02115     }
02116     else
02117     {
02118       /* Stop regular conversion */
02119       DFSDM_InjConvStop(hdfsdm_filter);
02120     }
02121   }
02122   /* Return function status */
02123   return status;
02124 }
02125
02126 /**
02127   * @brief  This function allows to get injected conversion value.
02128   * @param  hdfsdm_filter : DFSDM filter handle.
02129   * @param  Channel : Corresponding channel of injected conversion.
02130   * @retval Injected conversion value
02131   */
02132 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02133                                          uint32_t                   *Channel)
02134 {
02135   uint32_t reg = 0;
02136   int32_t  value = 0;
02137
02138   /* Check parameters */
02139   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02140   assert_param(Channel != NULL);
02141
02142   /* Get value of data register for injected channel */
02143   reg = hdfsdm_filter->Instance->FLTJDATAR;
02144
02145   /* Extract channel and injected conversion value */
02146   *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
02147   value = ((reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
02148
02149   /* return regular conversion value */
02150   return value;
02151 }
02152
02153 /**
02154   * @brief  This function allows to start filter analog watchdog in interrupt mode.
02155   * @param  hdfsdm_filter : DFSDM filter handle.
02156   * @param  awdParam : DFSDM filter analog watchdog parameters.
02157   * @retval HAL status
02158   */
02159 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef   *hdfsdm_filter,
02160                                               DFSDM_Filter_AwdParamTypeDef *awdParam)
02161 {
02162   HAL_StatusTypeDef status = HAL_OK;
02163
02164   /* Check parameters */
02165   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02166   assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
02167   assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
02168   assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
02169   assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
02170   assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
02171   assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
02172
02173   /* Check DFSDM filter state */
02174   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02175      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02176   {
02177     /* Return error status */
02178     status = HAL_ERROR;
02179   }
02180   else
02181   {
02182     /* Set analog watchdog data source */
02183     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
02184     hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
02185
02186     /* Set thresholds and break signals */
02187     hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
02188     hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \
02189                                         awdParam->HighBreakSignal);
02190     hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
02191     hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \
02192                                         awdParam->LowBreakSignal);
02193
02194     /* Set channels and interrupt for analog watchdog */
02195     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
02196     hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \
02197                                         DFSDM_FLTCR2_AWDIE);
02198   }
02199   /* Return function status */
02200   return status;
02201 }
02202
02203 /**
02204   * @brief  This function allows to stop filter analog watchdog in interrupt mode.
02205   * @param  hdfsdm_filter : DFSDM filter handle.
02206   * @retval HAL status
02207   */
02208 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02209 {
02210   HAL_StatusTypeDef status = HAL_OK;
02211
02212   /* Check parameters */
02213   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02214
02215   /* Check DFSDM filter state */
02216   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02217      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02218   {
02219     /* Return error status */
02220     status = HAL_ERROR;
02221   }
02222   else
02223   {
02224     /* Reset channels for analog watchdog and deactivate interrupt */
02225     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
02226
02227     /* Clear all analog watchdog flags */
02228     hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
02229
02230     /* Reset thresholds and break signals */
02231     hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
02232     hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
02233
02234     /* Reset analog watchdog data source */
02235     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
02236   }
02237   /* Return function status */
02238   return status;
02239 }
02240
02241 /**
02242   * @brief  This function allows to start extreme detector feature.
02243   * @param  hdfsdm_filter : DFSDM filter handle.
02244   * @param  Channel : Channels where extreme detector is enabled.
02245   *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.
02246   * @retval HAL status
02247   */
02248 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02249                                            uint32_t                    Channel)
02250 {
02251   HAL_StatusTypeDef status = HAL_OK;
02252
02253   /* Check parameters */
02254   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02255   assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
02256
02257   /* Check DFSDM filter state */
02258   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02259      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02260   {
02261     /* Return error status */
02262     status = HAL_ERROR;
02263   }
02264   else
02265   {
02266     /* Set channels for extreme detector */
02267     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
02268     hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET);
02269   }
02270   /* Return function status */
02271   return status;
02272 }
02273
02274 /**
02275   * @brief  This function allows to stop extreme detector feature.
02276   * @param  hdfsdm_filter : DFSDM filter handle.
02277   * @retval HAL status
02278   */
02279 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02280 {
02281   HAL_StatusTypeDef status = HAL_OK;
02282   __IO uint32_t     reg1;
02283   __IO uint32_t     reg2;
02284
02285   /* Check parameters */
02286   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02287
02288   /* Check DFSDM filter state */
02289   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
02290      (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
02291   {
02292     /* Return error status */
02293     status = HAL_ERROR;
02294   }
02295   else
02296   {
02297     /* Reset channels for extreme detector */
02298     hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
02299
02300     /* Clear extreme detector values */
02301     reg1 = hdfsdm_filter->Instance->FLTEXMAX;
02302     reg2 = hdfsdm_filter->Instance->FLTEXMIN;
02303     UNUSED(reg1); /* To avoid GCC warning */
02304     UNUSED(reg2); /* To avoid GCC warning */
02305   }
02306   /* Return function status */
02307   return status;
02308 }
02309
02310 /**
02311   * @brief  This function allows to get extreme detector maximum value.
02312   * @param  hdfsdm_filter : DFSDM filter handle.
02313   * @param  Channel : Corresponding channel.
02314   * @retval Extreme detector maximum value
02315   *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
02316   */
02317 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02318                                        uint32_t                   *Channel)
02319 {
02320   uint32_t reg = 0;
02321   int32_t  value = 0;
02322
02323   /* Check parameters */
02324   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02325   assert_param(Channel != NULL);
02326
02327   /* Get value of extreme detector maximum register */
02328   reg = hdfsdm_filter->Instance->FLTEXMAX;
02329
02330   /* Extract channel and extreme detector maximum value */
02331   *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
02332   value = ((reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
02333
02334   /* return extreme detector maximum value */
02335   return value;
02336 }
02337
02338 /**
02339   * @brief  This function allows to get extreme detector minimum value.
02340   * @param  hdfsdm_filter : DFSDM filter handle.
02341   * @param  Channel : Corresponding channel.
02342   * @retval Extreme detector minimum value
02343   *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
02344   */
02345 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02346                                        uint32_t                   *Channel)
02347 {
02348   uint32_t reg = 0;
02349   int32_t  value = 0;
02350
02351   /* Check parameters */
02352   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02353   assert_param(Channel != NULL);
02354
02355   /* Get value of extreme detector minimum register */
02356   reg = hdfsdm_filter->Instance->FLTEXMIN;
02357
02358   /* Extract channel and extreme detector minimum value */
02359   *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
02360   value = ((reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
02361
02362   /* return extreme detector minimum value */
02363   return value;
02364 }
02365
02366 /**
02367   * @brief  This function allows to get conversion time value.
02368   * @param  hdfsdm_filter : DFSDM filter handle.
02369   * @retval Conversion time value
02370   * @note   To get time in second, this value has to be divided by DFSDM clock frequency.
02371   */
02372 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02373 {
02374   uint32_t reg = 0;
02375   uint32_t value = 0;
02376
02377   /* Check parameters */
02378   assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
02379
02380   /* Get value of conversion timer register */
02381   reg = hdfsdm_filter->Instance->FLTCNVTIMR;
02382
02383   /* Extract conversion time value */
02384   value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);
02385
02386   /* return extreme detector minimum value */
02387   return value;
02388 }
02389
02390 /**
02391   * @brief  This function handles the DFSDM interrupts.
02392   * @param  hdfsdm_filter : DFSDM filter handle.
02393   * @retval None
02394   */
02395 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02396 {
02397   /* Check if overrun occurs during regular conversion */
02398   if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \
02399      ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0))
02400   {
02401     /* Clear regular overrun flag */
02402     hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
02403
02404     /* Update error code */
02405     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
02406
02407     /* Call error callback */
02408     HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
02409   }
02410   /* Check if overrun occurs during injected conversion */
02411   else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \
02412           ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0))
02413   {
02414     /* Clear injected overrun flag */
02415     hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
02416
02417     /* Update error code */
02418     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
02419
02420     /* Call error callback */
02421     HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
02422   }
02423   /* Check if end of regular conversion */
02424   else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \
02425           ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0))
02426   {
02427     /* Call regular conversion complete callback */
02428     HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
02429
02430     /* End of conversion if mode is not continuous and software trigger */
02431     if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
02432        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
02433     {
02434       /* Disable interrupts for regular conversions */
02435       hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
02436
02437       /* Update DFSDM filter state */
02438       hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
02439                              HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
02440     }
02441   }
02442   /* Check if end of injected conversion */
02443   else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \
02444           ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0))
02445   {
02446     /* Call injected conversion complete callback */
02447     HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
02448
02449     /* Update remaining injected conversions */
02450     hdfsdm_filter->InjConvRemaining--;
02451     if(hdfsdm_filter->InjConvRemaining == 0)
02452     {
02453       /* End of conversion if trigger is software */
02454       if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
02455       {
02456         /* Disable interrupts for injected conversions */
02457         hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
02458
02459         /* Update DFSDM filter state */
02460         hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
02461                                HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
02462       }
02463       /* end of injected sequence, reset the value */
02464       hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
02465                                          hdfsdm_filter->InjectedChannelsNbr : 1;
02466     }
02467   }
02468   /* Check if analog watchdog occurs */
02469   else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \
02470           ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0))
02471   {
02472     uint32_t reg = 0;
02473     uint32_t threshold = 0;
02474     uint32_t channel = 0;
02475
02476     /* Get channel and threshold */
02477     reg = hdfsdm_filter->Instance->FLTAWSR;
02478     threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
02479     if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
02480     {
02481       reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;
02482     }
02483     while((reg & 1) == 0)
02484     {
02485       channel++;
02486       reg = reg >> 1;
02487     }
02488     /* Clear analog watchdog flag */
02489     hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
02490                                         (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \
02491                                      (1 << channel);
02492
02493     /* Call analog watchdog callback */
02494     HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
02495   }
02496   /* Check if clock absence occurs */
02497   else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
02498          ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \
02499          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0))
02500   {
02501     uint32_t reg = 0;
02502     uint32_t channel = 0;
02503
02504     reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);
02505
02506     while(channel < DFSDM1_CHANNEL_NUMBER)
02507     {
02508       /* Check if flag is set and corresponding channel is enabled */
02509       if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL))
02510       {
02511         /* Check clock absence has been enabled for this channel */
02512         if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0)
02513         {
02514           /* Clear clock absence flag */
02515           hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
02516
02517           /* Call clock absence callback */
02518           HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
02519         }
02520       }
02521       channel++;
02522       reg = reg >> 1;
02523     }
02524   }
02525   /* Check if short circuit detection occurs */
02526   else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
02527          ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \
02528          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0))
02529   {
02530     uint32_t reg = 0;
02531     uint32_t channel = 0;
02532
02533     /* Get channel */
02534     reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);
02535     while((reg & 1) == 0)
02536     {
02537       channel++;
02538       reg = reg >> 1;
02539     }
02540
02541     /* Clear short circuit detection flag */
02542     hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
02543
02544     /* Call short circuit detection callback */
02545     HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
02546   }
02547 }
02548
02549 /**
02550   * @brief  Regular conversion complete callback.
02551   * @note   In interrupt mode, user has to read conversion value in this function
02552   *         using HAL_DFSDM_FilterGetRegularValue.
02553   * @param  hdfsdm_filter : DFSDM filter handle.
02554   * @retval None
02555   */
02556 __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02557 {
02558   /* Prevent unused argument(s) compilation warning */
02559   UNUSED(hdfsdm_filter);
02560
02561   /* NOTE : This function should not be modified, when the callback is needed,
02562             the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
02563    */
02564 }
02565
02566 /**
02567   * @brief  Half regular conversion complete callback.
02568   * @param  hdfsdm_filter : DFSDM filter handle.
02569   * @retval None
02570   */
02571 __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02572 {
02573   /* Prevent unused argument(s) compilation warning */
02574   UNUSED(hdfsdm_filter);
02575
02576   /* NOTE : This function should not be modified, when the callback is needed,
02577             the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
02578    */
02579 }
02580
02581 /**
02582   * @brief  Injected conversion complete callback.
02583   * @note   In interrupt mode, user has to read conversion value in this function
02584   *         using HAL_DFSDM_FilterGetInjectedValue.
02585   * @param  hdfsdm_filter : DFSDM filter handle.
02586   * @retval None
02587   */
02588 __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02589 {
02590   /* Prevent unused argument(s) compilation warning */
02591   UNUSED(hdfsdm_filter);
02592
02593   /* NOTE : This function should not be modified, when the callback is needed,
02594             the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
02595    */
02596 }
02597
02598 /**
02599   * @brief  Half injected conversion complete callback.
02600   * @param  hdfsdm_filter : DFSDM filter handle.
02601   * @retval None
02602   */
02603 __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02604 {
02605   /* Prevent unused argument(s) compilation warning */
02606   UNUSED(hdfsdm_filter);
02607
02608   /* NOTE : This function should not be modified, when the callback is needed,
02609             the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
02610    */
02611 }
02612
02613 /**
02614   * @brief  Filter analog watchdog callback.
02615   * @param  hdfsdm_filter : DFSDM filter handle.
02616   * @param  Channel : Corresponding channel.
02617   * @param  Threshold : Low or high threshold has been reached.
02618   * @retval None
02619   */
02620 __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
02621                                         uint32_t Channel, uint32_t Threshold)
02622 {
02623   /* Prevent unused argument(s) compilation warning */
02624   UNUSED(hdfsdm_filter);
02625   UNUSED(Channel);
02626   UNUSED(Threshold);
02627
02628   /* NOTE : This function should not be modified, when the callback is needed,
02629             the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
02630    */
02631 }
02632
02633 /**
02634   * @brief  Error callback.
02635   * @param  hdfsdm_filter : DFSDM filter handle.
02636   * @retval None
02637   */
02638 __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02639 {
02640   /* Prevent unused argument(s) compilation warning */
02641   UNUSED(hdfsdm_filter);
02642
02643   /* NOTE : This function should not be modified, when the callback is needed,
02644             the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
02645    */
02646 }
02647
02648 /**
02649   * @}
02650   */
02651
02652 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
02653  *  @brief    Filter state functions
02654  *
02655 @verbatim
02656   ==============================================================================
02657                      ##### Filter state functions #####
02658   ==============================================================================
02659     [..]  This section provides functions allowing to:
02660       (+) Get the DFSDM filter state.
02661       (+) Get the DFSDM filter error.
02662 @endverbatim
02663   * @{
02664   */
02665
02666 /**
02667   * @brief  This function allows to get the current DFSDM filter handle state.
02668   * @param  hdfsdm_filter : DFSDM filter handle.
02669   * @retval DFSDM filter state.
02670   */
02671 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02672 {
02673   /* Return DFSDM filter handle state */
02674   return hdfsdm_filter->State;
02675 }
02676
02677 /**
02678   * @brief  This function allows to get the current DFSDM filter error.
02679   * @param  hdfsdm_filter : DFSDM filter handle.
02680   * @retval DFSDM filter error code.
02681   */
02682 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
02683 {
02684   return hdfsdm_filter->ErrorCode;
02685 }
02686
02687 /**
02688   * @}
02689   */
02690
02691 /**
02692   * @}
02693   */
02694 /* End of exported functions -------------------------------------------------*/
02695
02696 /* Private functions ---------------------------------------------------------*/
02697 /** @addtogroup DFSDM_Private_Functions DFSDM Private Functions
02698   * @{
02699   */
02700
02701 /**
02702   * @brief  DMA half transfer complete callback for regular conversion.
02703   * @param  hdma : DMA handle.
02704   * @retval None
02705   */
02706 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
02707 {
02708   /* Get DFSDM filter handle */
02709   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02710
02711   /* Call regular half conversion complete callback */
02712   HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
02713 }
02714
02715 /**
02716   * @brief  DMA transfer complete callback for regular conversion.
02717   * @param  hdma : DMA handle.
02718   * @retval None
02719   */
02720 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
02721 {
02722   /* Get DFSDM filter handle */
02723   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02724
02725   /* Call regular conversion complete callback */
02726   HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
02727 }
02728
02729 /**
02730   * @brief  DMA half transfer complete callback for injected conversion.
02731   * @param  hdma : DMA handle.
02732   * @retval None
02733   */
02734 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
02735 {
02736   /* Get DFSDM filter handle */
02737   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02738
02739   /* Call injected half conversion complete callback */
02740   HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
02741 }
02742
02743 /**
02744   * @brief  DMA transfer complete callback for injected conversion.
02745   * @param  hdma : DMA handle.
02746   * @retval None
02747   */
02748 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
02749 {
02750   /* Get DFSDM filter handle */
02751   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02752
02753   /* Call injected conversion complete callback */
02754   HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
02755 }
02756
02757 /**
02758   * @brief  DMA error callback.
02759   * @param  hdma : DMA handle.
02760   * @retval None
02761   */
02762 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
02763 {
02764   /* Get DFSDM filter handle */
02765   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
02766
02767   /* Update error code */
02768   hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
02769
02770   /* Call error callback */
02771   HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
02772 }
02773
02774 /**
02775   * @brief  This function allows to get the number of injected channels.
02776   * @param  Channels : bitfield of injected channels.
02777   * @retval Number of injected channels.
02778   */
02779 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
02780 {
02781   uint32_t nbChannels = 0;
02782   uint32_t tmp;
02783
02784   /* Get the number of channels from bitfield */
02785   tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
02786   while(tmp != 0)
02787   {
02788     if((tmp & 1) != 0)
02789     {
02790       nbChannels++;
02791     }
02792     tmp = (uint32_t) (tmp >> 1);
02793   }
02794   return nbChannels;
02795 }
02796
02797 /**
02798   * @brief  This function allows to get the channel number from channel instance.
02799   * @param  Instance : DFSDM channel instance.
02800   * @retval Channel number.
02801   */
02802 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
02803 {
02804   uint32_t channel = 0xFF;
02805
02806   /* Get channel from instance */
02807   if(Instance == DFSDM1_Channel0)
02808   {
02809     channel = 0;
02810   }
02811   else if(Instance == DFSDM1_Channel1)
02812   {
02813     channel = 1;
02814   }
02815   else if(Instance == DFSDM1_Channel2)
02816   {
02817     channel = 2;
02818   }
02819   else if(Instance == DFSDM1_Channel3)
02820   {
02821     channel = 3;
02822   }
02823   else if(Instance == DFSDM1_Channel4)
02824   {
02825     channel = 4;
02826   }
02827   else if(Instance == DFSDM1_Channel5)
02828   {
02829     channel = 5;
02830   }
02831   else if(Instance == DFSDM1_Channel6)
02832   {
02833     channel = 6;
02834   }
02835   else if(Instance == DFSDM1_Channel7)
02836   {
02837     channel = 7;
02838   }
02839
02840   return channel;
02841 }
02842
02843 /**
02844   * @brief  This function allows to really start regular conversion.
02845   * @param  hdfsdm_filter : DFSDM filter handle.
02846   * @retval None
02847   */
02848 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
02849 {
02850   /* Check regular trigger */
02851   if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
02852   {
02853     /* Software start of regular conversion */
02854     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
02855   }
02856   else /* synchronous trigger */
02857   {
02858     /* Disable DFSDM filter */
02859     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
02860
02861     /* Set RSYNC bit in DFSDM_FLTCR1 register */
02862     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
02863
02864     /* Enable DFSDM  filter */
02865     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
02866
02867     /* If injected conversion was in progress, restart it */
02868     if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
02869     {
02870       if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
02871       {
02872         hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
02873       }
02874       /* Update remaining injected conversions */
02875       hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
02876                                          hdfsdm_filter->InjectedChannelsNbr : 1;
02877     }
02878   }
02879   /* Update DFSDM filter state */
02880   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
02881                           HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
02882 }
02883
02884 /**
02885   * @brief  This function allows to really stop regular conversion.
02886   * @param  hdfsdm_filter : DFSDM filter handle.
02887   * @retval None
02888   */
02889 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
02890 {
02891   /* Disable DFSDM filter */
02892   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
02893
02894   /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
02895   if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
02896   {
02897     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
02898   }
02899
02900   /* Enable DFSDM filter */
02901   hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
02902
02903   /* If injected conversion was in progress, restart it */
02904   if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
02905   {
02906     if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
02907     {
02908       hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
02909     }
02910     /* Update remaining injected conversions */
02911     hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
02912                                        hdfsdm_filter->InjectedChannelsNbr : 1;
02913   }
02914
02915   /* Update DFSDM filter state */
02916   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
02917                           HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
02918 }
02919
02920 /**
02921   * @brief  This function allows to really start injected conversion.
02922   * @param  hdfsdm_filter : DFSDM filter handle.
02923   * @retval None
02924   */
02925 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
02926 {
02927   /* Check injected trigger */
02928   if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
02929   {
02930     /* Software start of injected conversion */
02931     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
02932   }
02933   else /* external or synchronous trigger */
02934   {
02935     /* Disable DFSDM filter */
02936     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
02937
02938     if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
02939     {
02940       /* Set JSYNC bit in DFSDM_FLTCR1 register */
02941       hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
02942     }
02943     else /* external trigger */
02944     {
02945       /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
02946       hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
02947     }
02948
02949     /* Enable DFSDM filter */
02950     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
02951
02952     /* If regular conversion was in progress, restart it */
02953     if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
02954        (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
02955     {
02956       hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
02957     }
02958   }
02959   /* Update DFSDM filter state */
02960   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
02961                          HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
02962 }
02963
02964 /**
02965   * @brief  This function allows to really stop injected conversion.
02966   * @param  hdfsdm_filter : DFSDM filter handle.
02967   * @retval None
02968   */
02969 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
02970 {
02971   /* Disable DFSDM filter */
02972   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
02973
02974   /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
02975   if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
02976   {
02977     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
02978   }
02979   else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
02980   {
02981     /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
02982     hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
02983   }
02984
02985   /* Enable DFSDM filter */
02986   hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
02987
02988   /* If regular conversion was in progress, restart it */
02989   if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
02990      (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
02991   {
02992     hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
02993   }
02994
02995   /* Update remaining injected conversions */
02996   hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
02997                                      hdfsdm_filter->InjectedChannelsNbr : 1;
02998
02999   /* Update DFSDM filter state */
03000   hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
03001                           HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
03002 }
03003
03004 /**
03005   * @}
03006   */
03007 /* End of private functions --------------------------------------------------*/
03008
03009 /**
03010   * @}
03011   */
03012 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
03013 #endif /* HAL_DFSDM_MODULE_ENABLED */
03014 /**
03015   * @}
03016   */
03017
03018 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dfsdm.h Source File

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stm32l4xx_hal_dfsdm.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_dfsdm.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of DFSDM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_DFSDM_H
00040 #define __STM32L4xx_HAL_DFSDM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32l4xx_hal_def.h"
00049
00050 /** @addtogroup STM32L4xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup DFSDM
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  HAL DFSDM Channel states definition
00065   */
00066 typedef enum
00067 {
00068   HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
00069   HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
00070   HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */
00071 }HAL_DFSDM_Channel_StateTypeDef;
00072
00073 /**
00074   * @brief  DFSDM channel output clock structure definition
00075   */
00076 typedef struct
00077 {
00078   FunctionalState Activation; /*!< Output clock enable/disable */
00079   uint32_t        Selection;  /*!< Output clock is system clock or audio clock.
00080                                    This parameter can be a value of @ref DFSDM_Channel_OuputClock */
00081   uint32_t        Divider;    /*!< Output clock divider.
00082                                    This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
00083 }DFSDM_Channel_OutputClockTypeDef;
00084
00085 /**
00086   * @brief  DFSDM channel input structure definition
00087   */
00088 typedef struct
00089 {
00090   uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
00091                              This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
00092   uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
00093                              This parameter can be a value of @ref DFSDM_Channel_DataPacking */
00094   uint32_t Pins;        /*!< Input pins are taken from same or following channel.
00095                              This parameter can be a value of @ref DFSDM_Channel_InputPins */
00096 }DFSDM_Channel_InputTypeDef;
00097
00098 /**
00099   * @brief  DFSDM channel serial interface structure definition
00100   */
00101 typedef struct
00102 {
00103   uint32_t Type;     /*!< SPI or Manchester modes.
00104                           This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
00105   uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
00106                           This parameter can be a value of @ref DFSDM_Channel_SpiClock */
00107 }DFSDM_Channel_SerialInterfaceTypeDef;
00108
00109 /**
00110   * @brief  DFSDM channel analog watchdog structure definition
00111   */
00112 typedef struct
00113 {
00114   uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.
00115                               This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
00116   uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
00117                               This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
00118 }DFSDM_Channel_AwdTypeDef;
00119
00120 /**
00121   * @brief  DFSDM channel init structure definition
00122   */
00123 typedef struct
00124 {
00125   DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */
00126   DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */
00127   DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
00128   DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */
00129   int32_t                              Offset;          /*!< DFSDM channel offset.
00130                                                              This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00131   uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.
00132                                                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
00133 }DFSDM_Channel_InitTypeDef;
00134
00135 /**
00136   * @brief  DFSDM channel handle structure definition
00137   */
00138 typedef struct
00139 {
00140   DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */
00141   DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */
00142   HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */
00143 }DFSDM_Channel_HandleTypeDef;
00144
00145 /**
00146   * @brief  HAL DFSDM Filter states definition
00147   */
00148 typedef enum
00149 {
00150   HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */
00151   HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */
00152   HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */
00153   HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */
00154   HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
00155   HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */
00156 }HAL_DFSDM_Filter_StateTypeDef;
00157
00158 /**
00159   * @brief  DFSDM filter regular conversion parameters structure definition
00160   */
00161 typedef struct
00162 {
00163   uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.
00164                                  This parameter can be a value of @ref DFSDM_Filter_Trigger */
00165   FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
00166   FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */
00167 }DFSDM_Filter_RegularParamTypeDef;
00168
00169 /**
00170   * @brief  DFSDM filter injected conversion parameters structure definition
00171   */
00172 typedef struct
00173 {
00174   uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.
00175                                        This parameter can be a value of @ref DFSDM_Filter_Trigger */
00176   FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */
00177   FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */
00178   uint32_t        ExtTrigger;     /*!< External trigger.
00179                                        This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
00180   uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
00181                                        This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
00182 }DFSDM_Filter_InjectedParamTypeDef;
00183
00184 /**
00185   * @brief  DFSDM filter parameters structure definition
00186   */
00187 typedef struct
00188 {
00189   uint32_t SincOrder;       /*!< Sinc filter order.
00190                                  This parameter can be a value of @ref DFSDM_Filter_SincOrder */
00191   uint32_t Oversampling;    /*!< Filter oversampling ratio.
00192                                  This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
00193   uint32_t IntOversampling; /*!< Integrator oversampling ratio.
00194                                  This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
00195 }DFSDM_Filter_FilterParamTypeDef;
00196
00197 /**
00198   * @brief  DFSDM filter init structure definition
00199   */
00200 typedef struct
00201 {
00202   DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */
00203   DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
00204   DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */
00205 }DFSDM_Filter_InitTypeDef;
00206
00207 /**
00208   * @brief  DFSDM filter handle structure definition
00209   */
00210 typedef struct
00211 {
00212   DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */
00213   DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */
00214   DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */
00215   DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */
00216   uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */
00217   uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */
00218   uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */
00219   uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */
00220   FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */
00221   uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */
00222   uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */
00223   HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */
00224   uint32_t                      ErrorCode;           /*!< DFSDM filter error code */
00225 }DFSDM_Filter_HandleTypeDef;
00226
00227 /**
00228   * @brief  DFSDM filter analog watchdog parameters structure definition
00229   */
00230 typedef struct
00231 {
00232   uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.
00233                                  This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
00234   uint32_t Channel;         /*!< Analog watchdog channel selection.
00235                                  This parameter can be a values combination of @ref DFSDM_Channel_Selection */
00236   int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.
00237                                  This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00238   int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.
00239                                  This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00240   uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
00241                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
00242   uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.
00243                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
00244 }DFSDM_Filter_AwdParamTypeDef;
00245
00246 /**
00247   * @}
00248   */
00249 /* End of exported types -----------------------------------------------------*/
00250
00251 /* Exported constants --------------------------------------------------------*/
00252 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
00253   * @{
00254   */
00255
00256 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
00257   * @{
00258   */
00259 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
00260 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC  /*!< Source for ouput clock is audio clock */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
00266   * @{
00267   */
00268 #define DFSDM_CHANNEL_EXTERNAL_INPUTS    ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
00269 #define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
00275   * @{
00276   */
00277 #define DFSDM_CHANNEL_STANDARD_MODE         ((uint32_t)0x00000000U) /*!< Standard data packing mode */
00278 #define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
00279 #define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
00285   * @{
00286   */
00287 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS      ((uint32_t)0x00000000U) /*!< Input from pins on same channel */
00288 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL   /*!< Input from pins on following channel */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
00294   * @{
00295   */
00296 #define DFSDM_CHANNEL_SPI_RISING         ((uint32_t)0x00000000U) /*!< SPI with rising edge */
00297 #define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0    /*!< SPI with falling edge */
00298 #define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1    /*!< Manchester with rising edge */
00299 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP      /*!< Manchester with falling edge */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
00305   * @{
00306   */
00307 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              ((uint32_t)0x00000000U)  /*!< External SPI clock */
00308 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
00309 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
00310 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
00316   * @{
00317   */
00318 #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
00319 #define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
00320 #define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
00321 #define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
00327   * @{
00328   */
00329 #define DFSDM_FILTER_SW_TRIGGER   ((uint32_t)0x00000000U) /*!< Software trigger */
00330 #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */
00331 #define DFSDM_FILTER_EXT_TRIGGER  ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
00337   * @{
00338   */
00339 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  ((uint32_t)0x00000000U)                           /*!< For DFSDM filter 0, 1, 2 and 3 */
00340 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM filter 0, 1, 2 and 3 */
00341 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM filter 0, 1, 2 and 3 */
00342 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */
00343 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */
00344 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 0, 1 and 2 */
00345 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM filter 3 */
00346 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */
00347 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */
00348 #define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
00349 #define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM filter 0, 1, 2 and 3 */
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
00355   * @{
00356   */
00357 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
00358 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
00359 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
00365   * @{
00366   */
00367 #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U)               /*!< FastSinc filter type */
00368 #define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */
00369 #define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */
00370 #define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
00371 #define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */
00372 #define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
00378   * @{
00379   */
00380 #define DFSDM_FILTER_AWD_FILTER_DATA  ((uint32_t)0x00000000U) /*!< From digital filter */
00381 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
00387   * @{
00388   */
00389 #define DFSDM_FILTER_ERROR_NONE             ((uint32_t)0x00000000U) /*!< No error */
00390 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
00391 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
00392 #define DFSDM_FILTER_ERROR_DMA              ((uint32_t)0x00000003U) /*!< DMA error occurs */
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup DFSDM_BreakSignals DFSDM break signals
00398   * @{
00399   */
00400 #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */
00401 #define DFSDM_BREAK_SIGNAL_0  ((uint32_t)0x00000001U) /*!< Break signal 0 */
00402 #define DFSDM_BREAK_SIGNAL_1  ((uint32_t)0x00000002U) /*!< Break signal 1 */
00403 #define DFSDM_BREAK_SIGNAL_2  ((uint32_t)0x00000004U) /*!< Break signal 2 */
00404 #define DFSDM_BREAK_SIGNAL_3  ((uint32_t)0x00000008U) /*!< Break signal 3 */
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
00410   * @{
00411   */
00412 /* DFSDM Channels ------------------------------------------------------------*/
00413 /* The DFSDM channels are defined as follows:
00414    - in 16-bit LSB the channel mask is set
00415    - in 16-bit MSB the channel number is set
00416    e.g. for channel 5 definition:
00417         - the channel mask is 0x00000020 (bit 5 is set)
00418         - the channel number 5 is 0x00050000
00419         --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
00420 #define DFSDM_CHANNEL_0                              ((uint32_t)0x00000001U)
00421 #define DFSDM_CHANNEL_1                              ((uint32_t)0x00010002U)
00422 #define DFSDM_CHANNEL_2                              ((uint32_t)0x00020004U)
00423 #define DFSDM_CHANNEL_3                              ((uint32_t)0x00030008U)
00424 #define DFSDM_CHANNEL_4                              ((uint32_t)0x00040010U)
00425 #define DFSDM_CHANNEL_5                              ((uint32_t)0x00050020U)
00426 #define DFSDM_CHANNEL_6                              ((uint32_t)0x00060040U)
00427 #define DFSDM_CHANNEL_7                              ((uint32_t)0x00070080U)
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
00433   * @{
00434   */
00435 #define DFSDM_CONTINUOUS_CONV_OFF            ((uint32_t)0x00000000U) /*!< Conversion are not continuous */
00436 #define DFSDM_CONTINUOUS_CONV_ON             ((uint32_t)0x00000001U) /*!< Conversion are continuous */
00437 /**
00438   * @}
00439   */
00440
00441 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
00442   * @{
00443   */
00444 #define DFSDM_AWD_HIGH_THRESHOLD            ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */
00445 #define DFSDM_AWD_LOW_THRESHOLD             ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */
00446 /**
00447   * @}
00448   */
00449
00450 /**
00451   * @}
00452   */
00453 /* End of exported constants -------------------------------------------------*/
00454
00455 /* Exported macros -----------------------------------------------------------*/
00456 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
00457  * @{
00458  */
00459
00460 /** @brief  Reset DFSDM channel handle state.
00461   * @param  __HANDLE__: DFSDM channel handle.
00462   * @retval None
00463   */
00464 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
00465
00466 /** @brief  Reset DFSDM filter handle state.
00467   * @param  __HANDLE__: DFSDM filter handle.
00468   * @retval None
00469   */
00470 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
00471
00472 /**
00473   * @}
00474   */
00475 /* End of exported macros ----------------------------------------------------*/
00476
00477 /* Exported functions --------------------------------------------------------*/
00478 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
00479   * @{
00480   */
00481
00482 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
00483   * @{
00484   */
00485 /* Channel initialization and de-initialization functions *********************/
00486 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00487 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00488 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00489 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00490 /**
00491   * @}
00492   */
00493
00494 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
00495   * @{
00496   */
00497 /* Channel operation functions ************************************************/
00498 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00499 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00500 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00501 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00502
00503 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
00504 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
00505 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00506 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00507
00508 int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00509 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
00510
00511 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
00512 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
00513
00514 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00515 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00516 /**
00517   * @}
00518   */
00519
00520 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
00521   * @{
00522   */
00523 /* Channel state function *****************************************************/
00524 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00525 /**
00526   * @}
00527   */
00528
00529 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
00530   * @{
00531   */
00532 /* Filter initialization and de-initialization functions *********************/
00533 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00534 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00535 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00536 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00537 /**
00538   * @}
00539   */
00540
00541 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
00542   * @{
00543   */
00544 /* Filter control functions *********************/
00545 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00546                                                    uint32_t                    Channel,
00547                                                    uint32_t                    ContinuousMode);
00548 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00549                                                    uint32_t                    Channel);
00550 /**
00551   * @}
00552   */
00553
00554 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
00555   * @{
00556   */
00557 /* Filter operation functions *********************/
00558 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00559 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00560 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
00561 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
00562 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00563 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00564 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00565 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00566 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00567 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
00568 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
00569 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00570 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00571 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00572 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00573                                               DFSDM_Filter_AwdParamTypeDef* awdParam);
00574 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00575 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
00576 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00577
00578 int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00579 int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00580 int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00581 int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00582 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00583
00584 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00585
00586 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
00587 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
00588
00589 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00590 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00591 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00592 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00593 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
00594 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00595 /**
00596   * @}
00597   */
00598
00599 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
00600   * @{
00601   */
00602 /* Filter state functions *****************************************************/
00603 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00604 uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00605 /**
00606   * @}
00607   */
00608
00609 /**
00610   * @}
00611   */
00612 /* End of exported functions -------------------------------------------------*/
00613
00614 /* Private macros ------------------------------------------------------------*/
00615 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros
00616 * @{
00617 */
00618 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
00619                                                        ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
00620 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
00621 #define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
00622                                                        ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
00623 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
00624                                                        ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
00625                                                        ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
00626 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
00627                                                        ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
00628 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
00629                                                        ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
00630                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
00631                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
00632 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
00633                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
00634                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
00635                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
00636 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
00637                                                        ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
00638                                                        ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
00639                                                        ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
00640 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1 <= (RATIO)) && ((RATIO) <= 32))
00641 #define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
00642 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1F)
00643 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFF)
00644 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
00645                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
00646 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
00647                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
00648                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
00649 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
00650                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
00651                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
00652                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
00653                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
00654                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
00655                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
00656                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
00657                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
00658                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
00659                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
00660 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
00661                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
00662                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
00663 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
00664                                                        ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
00665                                                        ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
00666                                                        ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
00667                                                        ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
00668                                                        ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
00669 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1 <= (RATIO)) && ((RATIO) <= 1024))
00670 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1 <= (RATIO)) && ((RATIO) <= 256))
00671 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
00672                                                        ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
00673 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
00674 #define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xFU)
00675 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
00676                                                        ((CHANNEL) == DFSDM_CHANNEL_1)  || \
00677                                                        ((CHANNEL) == DFSDM_CHANNEL_2)  || \
00678                                                        ((CHANNEL) == DFSDM_CHANNEL_3)  || \
00679                                                        ((CHANNEL) == DFSDM_CHANNEL_4)  || \
00680                                                        ((CHANNEL) == DFSDM_CHANNEL_5)  || \
00681                                                        ((CHANNEL) == DFSDM_CHANNEL_6)  || \
00682                                                        ((CHANNEL) == DFSDM_CHANNEL_7))
00683 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
00684 #define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
00685                                                        ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
00686 /**
00687   * @}
00688   */
00689 /* End of private macros -----------------------------------------------------*/
00690
00691 /**
00692   * @}
00693   */
00694
00695 /**
00696   * @}
00697   */
00698 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00699 #ifdef __cplusplus
00700 }
00701 #endif
00702
00703 #endif /* __STM32L4xx_HAL_DFSDM_H */
00704
00705 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dma.c Source File

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stm32l4xx_hal_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_dma.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   DMA HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of the Direct Memory Access (DMA) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and errors functions
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018    (#) Enable and configure the peripheral to be connected to the DMA Channel
00019        (except for internal SRAM / FLASH memories: no initialization is
00020        necessary). Please refer to the Reference manual for connection between peripherals
00021        and DMA requests.
00022
00023    (#) For a given Channel, program the required configuration through the following parameters:
00024        Channel request, Transfer Direction, Source and Destination data formats,
00025        Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
00026        using HAL_DMA_Init() function.
00027
00028    (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
00029        detection.
00030
00031    (#) Use HAL_DMA_Abort() function to abort the current transfer
00032
00033      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
00034      *** Polling mode IO operation ***
00035      =================================
00036     [..]
00037           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
00038               address and destination address and the Length of data to be transferred
00039           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
00040               case a fixed Timeout can be configured by User depending from his application.
00041
00042      *** Interrupt mode IO operation ***
00043      ===================================
00044     [..]
00045           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
00046           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
00047           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
00048               Source address and destination address and the Length of data to be transferred.
00049               In this case the DMA interrupt is configured
00050           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
00051           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
00052               add his own function by customization of function pointer XferCpltCallback and
00053               XferErrorCallback (i.e. a member of DMA handle structure).
00054
00055      *** DMA HAL driver macros list ***
00056      =============================================
00057       [..]
00058        Below the list of most used macros in DMA HAL driver.
00059
00060        (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
00061        (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
00062        (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
00063        (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
00064        (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
00065        (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
00066        (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
00067
00068      [..]
00069       (@) You can refer to the DMA HAL driver header file for more useful macros
00070
00071   @endverbatim
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00076   *
00077   * Redistribution and use in source and binary forms, with or without modification,
00078   * are permitted provided that the following conditions are met:
00079   *   1. Redistributions of source code must retain the above copyright notice,
00080   *      this list of conditions and the following disclaimer.
00081   *   2. Redistributions in binary form must reproduce the above copyright notice,
00082   *      this list of conditions and the following disclaimer in the documentation
00083   *      and/or other materials provided with the distribution.
00084   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00085   *      may be used to endorse or promote products derived from this software
00086   *      without specific prior written permission.
00087   *
00088   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00089   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00090   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00091   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00092   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00093   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00094   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00095   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00096   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00097   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00098   *
00099   ******************************************************************************
00100   */
00101
00102 /* Includes ------------------------------------------------------------------*/
00103 #include "stm32l4xx_hal.h"
00104
00105 /** @addtogroup STM32L4xx_HAL_Driver
00106   * @{
00107   */
00108
00109 /** @defgroup DMA DMA
00110   * @brief DMA HAL module driver
00111   * @{
00112   */
00113
00114 #ifdef HAL_DMA_MODULE_ENABLED
00115
00116 /* Private typedef -----------------------------------------------------------*/
00117 /* Private define ------------------------------------------------------------*/
00118 /* Private macro -------------------------------------------------------------*/
00119 /* Private variables ---------------------------------------------------------*/
00120 /* Private function prototypes -----------------------------------------------*/
00121 /** @defgroup DMA_Private_Functions DMA Private Functions
00122   * @{
00123   */
00124 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00125 /**
00126   * @}
00127   */
00128
00129 /* Exported functions ---------------------------------------------------------*/
00130
00131 /** @defgroup DMA_Exported_Functions DMA Exported Functions
00132   * @{
00133   */
00134
00135 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
00136  *  @brief   Initialization and de-initialization functions
00137  *
00138 @verbatim
00139  ===============================================================================
00140              ##### Initialization and de-initialization functions  #####
00141  ===============================================================================
00142     [..]
00143     This section provides functions allowing to initialize the DMA Channel source
00144     and destination addresses, incrementation and data sizes, transfer direction,
00145     circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
00146     [..]
00147     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
00148     reference manual.
00149
00150 @endverbatim
00151   * @{
00152   */
00153
00154 /**
00155   * @brief  Initialize the DMA according to the specified
00156   *         parameters in the DMA_InitTypeDef and initialize the associated handle.
00157   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
00158   *               the configuration information for the specified DMA Channel.
00159   * @retval HAL status
00160   */
00161 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
00162 {
00163   uint32_t tmp = 0;
00164
00165   /* Check the DMA handle allocation */
00166   if(hdma == NULL)
00167   {
00168     return HAL_ERROR;
00169   }
00170
00171   /* Check the parameters */
00172   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00173   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
00174   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
00175   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
00176   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
00177   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
00178   assert_param(IS_DMA_MODE(hdma->Init.Mode));
00179   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
00180   if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
00181   {
00182     assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
00183   }
00184
00185   /* calculation of the channel index */
00186   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00187   {
00188     /* DMA1 */
00189     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
00190     hdma->DmaBaseAddress = DMA1;
00191   }
00192   else
00193   {
00194     /* DMA2 */
00195     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
00196     hdma->DmaBaseAddress = DMA2;
00197   }
00198
00199   /* Change DMA peripheral state */
00200   hdma->State = HAL_DMA_STATE_BUSY;
00201
00202   /* Get the CR register value */
00203   tmp = hdma->Instance->CCR;
00204
00205   /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
00206   tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
00207                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
00208                       DMA_CCR_DIR));
00209
00210   /* Prepare the DMA Channel configuration */
00211   tmp |=  hdma->Init.Direction        |
00212           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
00213           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
00214           hdma->Init.Mode                | hdma->Init.Priority;
00215
00216   /* Write to DMA Channel CR register */
00217   hdma->Instance->CCR = tmp;
00218
00219   /* Set request selection */
00220   if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
00221   {
00222     /* Write to DMA channel selection register */
00223     if (DMA1 == hdma->DmaBaseAddress)
00224     {
00225       /* Reset request selection for DMA1 Channelx */
00226       DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex);
00227
00228       /* Configure request selection for DMA1 Channelx */
00229       DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex));
00230     }
00231     else /* DMA2 */
00232     {
00233       /* Reset request selection for DMA2 Channelx */
00234       DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex);
00235
00236       /* Configure request selection for DMA2 Channelx */
00237       DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex));
00238     }
00239   }
00240
00241   /* Clean callbacks */
00242   hdma->XferCpltCallback = NULL;
00243   hdma->XferHalfCpltCallback = NULL;
00244   hdma->XferErrorCallback = NULL;
00245   hdma->XferAbortCallback = NULL;
00246
00247   /* Initialise the error code */
00248   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00249
00250   /* Initialize the DMA state*/
00251   hdma->State  = HAL_DMA_STATE_READY;
00252
00253   /* Allocate lock resource and initialize it */
00254   hdma->Lock = HAL_UNLOCKED;
00255
00256   return HAL_OK;
00257 }
00258
00259 /**
00260   * @brief  DeInitialize the DMA peripheral.
00261   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00262   *               the configuration information for the specified DMA Channel.
00263   * @retval HAL status
00264   */
00265 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
00266 {
00267   /* Check the DMA handle allocation */
00268   if(hdma == NULL)
00269   {
00270     return HAL_ERROR;
00271   }
00272
00273   /* Check the parameters */
00274   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00275
00276   /* Disable the selected DMA Channelx */
00277   __HAL_DMA_DISABLE(hdma);
00278
00279   /* Reset DMA Channel control register */
00280   hdma->Instance->CCR  = 0;
00281
00282   /* Calculation of the channel index */
00283   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00284   {
00285     /* DMA1 */
00286     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
00287     hdma->DmaBaseAddress = DMA1;
00288   }
00289   else
00290   {
00291     /* DMA2 */
00292     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
00293     hdma->DmaBaseAddress = DMA2;
00294   }
00295
00296
00297   /* Clear all flags */
00298   hdma->DmaBaseAddress->IFCR |= ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
00299
00300   /* Reset DMA channel selection register */
00301   if (DMA1 == hdma->DmaBaseAddress)
00302   {
00303     /* DMA1 */
00304     DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex));
00305   }
00306   else
00307   {
00308     /* DMA2 */
00309     DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex));
00310   }
00311
00312   /* Initialize the error code */
00313   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00314
00315   /* Initialize the DMA state */
00316   hdma->State = HAL_DMA_STATE_RESET;
00317
00318   /* Release Lock */
00319   __HAL_UNLOCK(hdma);
00320
00321   return HAL_OK;
00322 }
00323
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
00329  *  @brief   Input and Output operation functions
00330  *
00331 @verbatim
00332  ===============================================================================
00333                       #####  IO operation functions  #####
00334  ===============================================================================
00335     [..]  This section provides functions allowing to:
00336       (+) Configure the source, destination address and data length and Start DMA transfer
00337       (+) Configure the source, destination address and data length and
00338           Start DMA transfer with interrupt
00339       (+) Abort DMA transfer
00340       (+) Poll for transfer complete
00341       (+) Handle DMA interrupt request
00342
00343 @endverbatim
00344   * @{
00345   */
00346
00347 /**
00348   * @brief  Start the DMA Transfer.
00349   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00350   *               the configuration information for the specified DMA Channel.
00351   * @param  SrcAddress: The source memory Buffer address
00352   * @param  DstAddress: The destination memory Buffer address
00353   * @param  DataLength: The length of data to be transferred from source to destination
00354   * @retval HAL status
00355   */
00356 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00357 {
00358   HAL_StatusTypeDef status = HAL_OK;
00359
00360   /* Check the parameters */
00361   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00362
00363   /* Process locked */
00364   __HAL_LOCK(hdma);
00365
00366   if(HAL_DMA_STATE_READY == hdma->State)
00367   {
00368     /* Change DMA peripheral state */
00369     hdma->State = HAL_DMA_STATE_BUSY;
00370     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00371
00372     /* Disable the peripheral */
00373     __HAL_DMA_DISABLE(hdma);
00374
00375     /* Configure the source, destination address and the data length & clear flags*/
00376     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00377
00378     /* Enable the Peripheral */
00379     __HAL_DMA_ENABLE(hdma);
00380   }
00381   else
00382   {
00383    /* Process Unlocked */
00384    __HAL_UNLOCK(hdma);
00385    status = HAL_BUSY;
00386   }
00387   return status;
00388 }
00389
00390 /**
00391   * @brief  Start the DMA Transfer with interrupt enabled.
00392   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00393   *               the configuration information for the specified DMA Channel.
00394   * @param  SrcAddress: The source memory Buffer address
00395   * @param  DstAddress: The destination memory Buffer address
00396   * @param  DataLength: The length of data to be transferred from source to destination
00397   * @retval HAL status
00398   */
00399 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00400 {
00401   HAL_StatusTypeDef status = HAL_OK;
00402
00403   /* Check the parameters */
00404   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00405
00406   /* Process locked */
00407   __HAL_LOCK(hdma);
00408
00409   if(HAL_DMA_STATE_READY == hdma->State)
00410   {
00411     /* Change DMA peripheral state */
00412     hdma->State = HAL_DMA_STATE_BUSY;
00413     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00414
00415     /* Disable the peripheral */
00416     __HAL_DMA_DISABLE(hdma);
00417
00418     /* Configure the source, destination address and the data length & clear flags*/
00419     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00420
00421     /* Enable the transfer complete interrupt */
00422     /* Enable the transfer Error interrupt */
00423     if(NULL != hdma->XferHalfCpltCallback )
00424     {
00425       /* Enable the Half transfer complete interrupt as well */
00426       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00427     }
00428     else
00429     {
00430       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00431       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
00432     }
00433     /* Enable the Peripheral */
00434     __HAL_DMA_ENABLE(hdma);
00435   }
00436   else
00437   {
00438     /* Process Unlocked */
00439     __HAL_UNLOCK(hdma);
00440
00441     /* Remain BUSY */
00442     status = HAL_BUSY;
00443   }
00444   return status;
00445 }
00446
00447 /**
00448   * @brief  Abort the DMA Transfer.
00449   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00450   *               the configuration information for the specified DMA Channel.
00451     * @retval HAL status
00452   */
00453 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
00454 {
00455   HAL_StatusTypeDef status = HAL_OK;
00456
00457   if(HAL_DMA_STATE_BUSY != hdma->State)
00458   {
00459     /* no transfer ongoing */
00460     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00461
00462     status = HAL_ERROR;
00463   }
00464   else
00465   {
00466     /* Disable DMA IT */
00467     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00468
00469     /* Disable the channel */
00470     __HAL_DMA_DISABLE(hdma);
00471
00472     /* Clear all flags */
00473     hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
00474
00475     /* Change the DMA state */
00476     hdma->State = HAL_DMA_STATE_READY;
00477
00478     /* Process Unlocked */
00479     __HAL_UNLOCK(hdma);
00480   }
00481   return status;
00482 }
00483
00484 /**
00485   * @brief  Aborts the DMA Transfer in Interrupt mode.
00486   * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
00487   *                 the configuration information for the specified DMA Stream.
00488   * @retval HAL status
00489   */
00490 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
00491 {
00492   HAL_StatusTypeDef status = HAL_OK;
00493
00494   if(HAL_DMA_STATE_BUSY != hdma->State)
00495   {
00496     /* no transfer ongoing */
00497     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00498
00499     status = HAL_ERROR;
00500   }
00501   else
00502   {
00503     /* Disable DMA IT */
00504     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00505
00506     /* Disable the channel */
00507     __HAL_DMA_DISABLE(hdma);
00508
00509     /* Clear all flags */
00510     hdma->DmaBaseAddress->IFCR |= ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
00511
00512     /* Change the DMA state */
00513     hdma->State = HAL_DMA_STATE_READY;
00514
00515     /* Process Unlocked */
00516     __HAL_UNLOCK(hdma);
00517
00518     /* Call User Abort callback */
00519     if(hdma->XferAbortCallback != NULL)
00520     {
00521       hdma->XferAbortCallback(hdma);
00522     }
00523   }
00524   return status;
00525 }
00526
00527 /**
00528   * @brief  Polling for transfer complete.
00529   * @param  hdma:    pointer to a DMA_HandleTypeDef structure that contains
00530   *                  the configuration information for the specified DMA Channel.
00531   * @param  CompleteLevel: Specifies the DMA level complete.
00532   * @param  Timeout:       Timeout duration.
00533   * @retval HAL status
00534   */
00535 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
00536 {
00537   uint32_t temp;
00538   uint32_t tickstart = 0;
00539
00540   if(HAL_DMA_STATE_BUSY != hdma->State)
00541   {
00542     /* no transfer ongoing */
00543     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00544
00545     return HAL_ERROR;
00546   }
00547
00548   /* Polling mode not supported in circular mode */
00549   if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
00550   {
00551     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00552     return HAL_ERROR;
00553   }
00554
00555   /* Get the level transfer complete flag */
00556   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
00557   {
00558     /* Transfer Complete flag */
00559     temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
00560   }
00561   else
00562   {
00563     /* Half Transfer Complete flag */
00564     temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
00565   }
00566
00567   /* Get tick */
00568   tickstart = HAL_GetTick();
00569
00570   while(RESET == (hdma->DmaBaseAddress->ISR & temp))
00571   {
00572     if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))))
00573     {
00574       /* When a DMA transfer error occurs */
00575       /* A hardware clear of its EN bits is performed */
00576       /* Clear all flags */
00577       hdma->DmaBaseAddress->IFCR |= ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
00578
00579       /* Update error code */
00580       hdma->ErrorCode = HAL_DMA_ERROR_TE;
00581
00582       /* Change the DMA state */
00583       hdma->State= HAL_DMA_STATE_READY;
00584
00585       /* Process Unlocked */
00586       __HAL_UNLOCK(hdma);
00587
00588       return HAL_ERROR;
00589     }
00590     /* Check for the Timeout */
00591     if(Timeout != HAL_MAX_DELAY)
00592     {
00593       if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
00594       {
00595         /* Update error code */
00596         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
00597
00598         /* Change the DMA state */
00599         hdma->State = HAL_DMA_STATE_READY;
00600
00601         /* Process Unlocked */
00602         __HAL_UNLOCK(hdma);
00603
00604         return HAL_ERROR;
00605       }
00606     }
00607   }
00608
00609   if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
00610   {
00611     /* Clear the transfer complete flag */
00612     hdma->DmaBaseAddress->IFCR  |= (DMA_FLAG_TC1 << hdma->ChannelIndex);
00613
00614     /* The selected Channelx EN bit is cleared (DMA is disabled and
00615     all transfers are complete) */
00616     hdma->State = HAL_DMA_STATE_READY;
00617   }
00618   else
00619   {
00620     /* Clear the half transfer complete flag */
00621     hdma->DmaBaseAddress->IFCR |= (DMA_FLAG_HT1 << hdma->ChannelIndex);
00622   }
00623
00624   /* Process unlocked */
00625   __HAL_UNLOCK(hdma);
00626
00627   return HAL_OK;
00628 }
00629
00630 /**
00631   * @brief  Handle DMA interrupt request.
00632   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00633   *               the configuration information for the specified DMA Channel.
00634   * @retval None
00635   */
00636 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
00637 {
00638   uint32_t flag_it = hdma->DmaBaseAddress->ISR;
00639   uint32_t source_it = hdma->Instance->CCR;
00640
00641   /* Half Transfer Complete Interrupt management ******************************/
00642   if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
00643   {
00644       /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
00645       if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
00646       {
00647         /* Disable the half transfer interrupt */
00648         __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00649       }
00650       /* Clear the half transfer complete flag */
00651       hdma->DmaBaseAddress->IFCR  |= (DMA_ISR_HTIF1 << hdma->ChannelIndex);
00652
00653       /* DMA peripheral state is not updated in Half Transfer */
00654       /* but in Transfer Complete case */
00655
00656      if(hdma->XferHalfCpltCallback != NULL)
00657       {
00658         /* Half transfer callback */
00659         hdma->XferHalfCpltCallback(hdma);
00660       }
00661   }
00662
00663   /* Transfer Complete Interrupt management ***********************************/
00664   else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
00665   {
00666     if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
00667     {
00668       /* Disable the transfer complete and error interrupt */
00669       __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
00670
00671       /* Change the DMA state */
00672       hdma->State = HAL_DMA_STATE_READY;
00673     }
00674     /* Clear the transfer complete flag */
00675     hdma->DmaBaseAddress->IFCR |= (DMA_ISR_TCIF1 << hdma->ChannelIndex);
00676
00677     /* Process Unlocked */
00678     __HAL_UNLOCK(hdma);
00679
00680     if(hdma->XferCpltCallback != NULL)
00681     {
00682       /* Transfer complete callback */
00683       hdma->XferCpltCallback(hdma);
00684     }
00685   }
00686
00687   /* Transfer Error Interrupt management **************************************/
00688   else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
00689   {
00690     /* When a DMA transfer error occurs */
00691     /* A hardware clear of its EN bits is performed */
00692     /* Disable ALL DMA IT */
00693     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00694
00695     /* Clear all flags */
00696     hdma->DmaBaseAddress->IFCR  |= (DMA_ISR_GIF1 << hdma->ChannelIndex);
00697
00698     /* Update error code */
00699     hdma->ErrorCode = HAL_DMA_ERROR_TE;
00700
00701     /* Change the DMA state */
00702     hdma->State = HAL_DMA_STATE_READY;
00703
00704     /* Process Unlocked */
00705     __HAL_UNLOCK(hdma);
00706
00707     if (hdma->XferErrorCallback != NULL)
00708     {
00709       /* Transfer error callback */
00710       hdma->XferErrorCallback(hdma);
00711     }
00712   }
00713   return;
00714 }
00715
00716 /**
00717   * @brief  Register callbacks
00718   * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
00719   *                               the configuration information for the specified DMA Stream.
00720   * @param  CallbackID:           User Callback identifer
00721   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00722   * @param  pCallback:            pointer to private callbacsk function which has pointer to
00723   *                               a DMA_HandleTypeDef structure as parameter.
00724   * @retval HAL status
00725   */
00726 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
00727 {
00728   HAL_StatusTypeDef status = HAL_OK;
00729
00730   /* Process locked */
00731   __HAL_LOCK(hdma);
00732
00733   if(HAL_DMA_STATE_READY == hdma->State)
00734   {
00735     switch (CallbackID)
00736     {
00737      case  HAL_DMA_XFER_CPLT_CB_ID:
00738            hdma->XferCpltCallback = pCallback;
00739            break;
00740
00741      case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00742            hdma->XferHalfCpltCallback = pCallback;
00743            break;
00744
00745      case  HAL_DMA_XFER_ERROR_CB_ID:
00746            hdma->XferErrorCallback = pCallback;
00747            break;
00748
00749      case  HAL_DMA_XFER_ABORT_CB_ID:
00750            hdma->XferAbortCallback = pCallback;
00751            break;
00752
00753      default:
00754            status = HAL_ERROR;
00755            break;
00756     }
00757   }
00758   else
00759   {
00760     status = HAL_ERROR;
00761   }
00762
00763   /* Release Lock */
00764   __HAL_UNLOCK(hdma);
00765
00766   return status;
00767 }
00768
00769 /**
00770   * @brief  UnRegister callbacks
00771   * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
00772   *                               the configuration information for the specified DMA Stream.
00773   * @param  CallbackID:           User Callback identifer
00774   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00775   * @retval HAL status
00776   */
00777 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
00778 {
00779   HAL_StatusTypeDef status = HAL_OK;
00780
00781     /* Process locked */
00782   __HAL_LOCK(hdma);
00783
00784   if(HAL_DMA_STATE_READY == hdma->State)
00785   {
00786     switch (CallbackID)
00787     {
00788      case  HAL_DMA_XFER_CPLT_CB_ID:
00789            hdma->XferCpltCallback = NULL;
00790            break;
00791
00792      case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00793            hdma->XferHalfCpltCallback = NULL;
00794            break;
00795
00796      case  HAL_DMA_XFER_ERROR_CB_ID:
00797            hdma->XferErrorCallback = NULL;
00798            break;
00799
00800      case  HAL_DMA_XFER_ABORT_CB_ID:
00801            hdma->XferAbortCallback = NULL;
00802            break;
00803
00804     case   HAL_DMA_XFER_ALL_CB_ID:
00805            hdma->XferCpltCallback = NULL;
00806            hdma->XferHalfCpltCallback = NULL;
00807            hdma->XferErrorCallback = NULL;
00808            hdma->XferAbortCallback = NULL;
00809            break;
00810
00811     default:
00812            status = HAL_ERROR;
00813            break;
00814     }
00815   }
00816   else
00817   {
00818     status = HAL_ERROR;
00819   }
00820
00821   /* Release Lock */
00822   __HAL_UNLOCK(hdma);
00823
00824   return status;
00825 }
00826
00827 /**
00828   * @}
00829   */
00830
00831
00832
00833 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
00834  *  @brief    Peripheral State and Errors functions
00835  *
00836 @verbatim
00837  ===============================================================================
00838             ##### Peripheral State and Errors functions #####
00839  ===============================================================================
00840     [..]
00841     This subsection provides functions allowing to
00842       (+) Check the DMA state
00843       (+) Get error code
00844
00845 @endverbatim
00846   * @{
00847   */
00848
00849 /**
00850   * @brief  Return the DMA hande state.
00851   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00852   *               the configuration information for the specified DMA Channel.
00853   * @retval HAL state
00854   */
00855 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
00856 {
00857   /* Return DMA handle state */
00858   return hdma->State;
00859 }
00860
00861 /**
00862   * @brief  Return the DMA error code.
00863   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
00864   *              the configuration information for the specified DMA Channel.
00865   * @retval DMA Error Code
00866   */
00867 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
00868 {
00869   return hdma->ErrorCode;
00870 }
00871
00872 /**
00873   * @}
00874   */
00875
00876 /**
00877   * @}
00878   */
00879
00880 /** @addtogroup DMA_Private_Functions
00881   * @{
00882   */
00883
00884 /**
00885   * @brief  Sets the DMA Transfer parameter.
00886   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00887   *                     the configuration information for the specified DMA Channel.
00888   * @param  SrcAddress: The source memory Buffer address
00889   * @param  DstAddress: The destination memory Buffer address
00890   * @param  DataLength: The length of data to be transferred from source to destination
00891   * @retval HAL status
00892   */
00893 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00894 {
00895   /* Clear all flags */
00896   hdma->DmaBaseAddress->IFCR  |= (DMA_ISR_GIF1 << hdma->ChannelIndex);
00897
00898   /* Configure DMA Channel data length */
00899   hdma->Instance->CNDTR = DataLength;
00900
00901   /* Peripheral to Memory */
00902   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
00903   {
00904     /* Configure DMA Channel destination address */
00905     hdma->Instance->CPAR = DstAddress;
00906
00907     /* Configure DMA Channel source address */
00908     hdma->Instance->CMAR = SrcAddress;
00909   }
00910   /* Memory to Peripheral */
00911   else
00912   {
00913     /* Configure DMA Channel source address */
00914     hdma->Instance->CPAR = SrcAddress;
00915
00916     /* Configure DMA Channel destination address */
00917     hdma->Instance->CMAR = DstAddress;
00918   }
00919 }
00920
00921 /**
00922   * @}
00923   */
00924
00925 /**
00926   * @}
00927   */
00928
00929 #endif /* HAL_DMA_MODULE_ENABLED */
00930 /**
00931   * @}
00932   */
00933
00934 /**
00935   * @}
00936   */
00937
00938 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_dma.h Source File

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stm32l4xx_hal_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of DMA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_DMA_H
00040 #define __STM32L4xx_HAL_DMA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DMA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup DMA_Exported_Types DMA Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  DMA Configuration Structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
00069                                            This parameter can be a value of @ref DMA_request */
00070
00071   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
00072                                            from memory to memory or from peripheral to memory.
00073                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
00074
00075   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
00076                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
00077
00078   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
00079                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
00080
00081   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
00082                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
00083
00084   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
00085                                            This parameter can be a value of @ref DMA_Memory_data_size */
00086
00087   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
00088                                            This parameter can be a value of @ref DMA_mode
00089                                            @note The circular buffer mode cannot be used if the memory-to-memory
00090                                                  data transfer is configured on the selected Channel */
00091
00092   uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
00093                                            This parameter can be a value of @ref DMA_Priority_level */
00094 } DMA_InitTypeDef;
00095
00096 /**
00097   * @brief  HAL DMA State structures definition
00098   */
00099 typedef enum
00100 {
00101   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled    */
00102   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use      */
00103   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing                 */
00104   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                     */
00105 }HAL_DMA_StateTypeDef;
00106
00107 /**
00108   * @brief  HAL DMA Error Code structure definition
00109   */
00110 typedef enum
00111 {
00112   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
00113   HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */
00114 }HAL_DMA_LevelCompleteTypeDef;
00115
00116
00117 /**
00118   * @brief  HAL DMA Callback ID structure definition
00119   */
00120 typedef enum
00121 {
00122   HAL_DMA_XFER_CPLT_CB_ID          = 0x00,    /*!< Full transfer     */
00123   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01,    /*!< Half transfer     */
00124   HAL_DMA_XFER_ERROR_CB_ID         = 0x02,    /*!< Error             */
00125   HAL_DMA_XFER_ABORT_CB_ID         = 0x03,    /*!< Abort             */
00126   HAL_DMA_XFER_ALL_CB_ID           = 0x04     /*!< All               */
00127
00128 }HAL_DMA_CallbackIDTypeDef;
00129
00130 /**
00131   * @brief  DMA handle Structure definition
00132   */
00133 typedef struct __DMA_HandleTypeDef
00134 {
00135   DMA_Channel_TypeDef    *Instance;                                                  /*!< Register base address                */
00136
00137   DMA_InitTypeDef       Init;                                                        /*!< DMA communication parameters         */
00138
00139   HAL_LockTypeDef       Lock;                                                        /*!< DMA locking object                   */
00140
00141   __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                   */
00142
00143   void                  *Parent;                                                     /*!< Parent object state                  */
00144
00145   void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback       */
00146
00147   void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback  */
00148
00149   void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback          */
00150
00151   void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer abort callback          */
00152
00153   __IO uint32_t          ErrorCode;                                                  /*!< DMA Error code                       */
00154
00155   DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address             */
00156
00157   uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                    */
00158 }DMA_HandleTypeDef;
00159 /**
00160   * @}
00161   */
00162
00163 /* Exported constants --------------------------------------------------------*/
00164
00165 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00166   * @{
00167   */
00168
00169 /** @defgroup DMA_Error_Code DMA Error Code
00170   * @{
00171   */
00172 #define HAL_DMA_ERROR_NONE          ((uint32_t)0x00000000)    /*!< No error             */
00173 #define HAL_DMA_ERROR_TE            ((uint32_t)0x00000001)    /*!< Transfer error       */
00174 #define HAL_DMA_ERROR_NO_XFER       ((uint32_t)0x00000004)    /*!< no ongoing transfer  */
00175 #define HAL_DMA_ERROR_TIMEOUT       ((uint32_t)0x00000020)    /*!< Timeout error        */
00176 #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100)    /*!< Not supported mode   */
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup DMA_request DMA request
00182   * @{
00183   */
00184 #define DMA_REQUEST_0                     ((uint32_t)0x00000000)
00185 #define DMA_REQUEST_1                     ((uint32_t)0x00000001)
00186 #define DMA_REQUEST_2                     ((uint32_t)0x00000002)
00187 #define DMA_REQUEST_3                     ((uint32_t)0x00000003)
00188 #define DMA_REQUEST_4                     ((uint32_t)0x00000004)
00189 #define DMA_REQUEST_5                     ((uint32_t)0x00000005)
00190 #define DMA_REQUEST_6                     ((uint32_t)0x00000006)
00191 #define DMA_REQUEST_7                     ((uint32_t)0x00000007)
00192
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00198   * @{
00199   */
00200 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
00201 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
00202 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM)   /*!< Memory to memory direction     */
00203
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00209   * @{
00210   */
00211 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
00212 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)    /*!< Peripheral increment mode Disable */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00218   * @{
00219   */
00220 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
00221 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00227   * @{
00228   */
00229 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
00230 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
00231 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup DMA_Memory_data_size DMA Memory data size
00237   * @{
00238   */
00239 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
00240 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
00241 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup DMA_mode DMA mode
00247   * @{
00248   */
00249 #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
00250 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup DMA_Priority_level DMA Priority level
00256   * @{
00257   */
00258 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
00259 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
00260 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
00261 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
00262 /**
00263   * @}
00264   */
00265
00266
00267 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00268   * @{
00269   */
00270 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
00271 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
00272 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup DMA_flag_definitions DMA flag definitions
00278   * @{
00279   */
00280 #define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
00281 #define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
00282 #define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
00283 #define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
00284 #define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
00285 #define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
00286 #define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
00287 #define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
00288 #define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
00289 #define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
00290 #define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
00291 #define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
00292 #define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
00293 #define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
00294 #define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
00295 #define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
00296 #define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
00297 #define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
00298 #define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
00299 #define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
00300 #define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
00301 #define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
00302 #define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
00303 #define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
00304 #define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
00305 #define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
00306 #define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
00307 #define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
00308 /**
00309   * @}
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 /* Exported macros -----------------------------------------------------------*/
00317 /** @defgroup DMA_Exported_Macros DMA Exported Macros
00318   * @{
00319   */
00320
00321 /** @brief  Reset DMA handle state.
00322   * @param  __HANDLE__: DMA handle
00323   * @retval None
00324   */
00325 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00326
00327 /**
00328   * @brief  Enable the specified DMA Channel.
00329   * @param  __HANDLE__: DMA handle
00330   * @retval None
00331   */
00332 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
00333
00334 /**
00335   * @brief  Disable the specified DMA Channel.
00336   * @param  __HANDLE__: DMA handle
00337   * @retval None
00338   */
00339 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
00340
00341
00342 /* Interrupt & Flag management */
00343
00344 /**
00345   * @brief  Return the current DMA Channel transfer complete flag.
00346   * @param  __HANDLE__: DMA handle
00347   * @retval The specified transfer complete flag index.
00348   */
00349
00350 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00351 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00352  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
00353  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00354  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
00355  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00356  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
00357  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00358  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
00359  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00360  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
00361  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00362  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
00363    DMA_FLAG_TC7)
00364
00365 /**
00366   * @brief  Return the current DMA Channel half transfer complete flag.
00367   * @param  __HANDLE__: DMA handle
00368   * @retval The specified half transfer complete flag index.
00369   */
00370 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00371 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00372  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
00373  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00374  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
00375  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00376  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
00377  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00378  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
00379  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00380  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
00381  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00382  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
00383    DMA_FLAG_HT7)
00384
00385 /**
00386   * @brief  Return the current DMA Channel transfer error flag.
00387   * @param  __HANDLE__: DMA handle
00388   * @retval The specified transfer error flag index.
00389   */
00390 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00391 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00392  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
00393  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00394  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
00395  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00396  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
00397  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00398  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
00399  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00400  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
00401  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00402  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
00403    DMA_FLAG_TE7)
00404
00405 /**
00406   * @brief  Return the current DMA Channel Global interrupt flag.
00407   * @param  __HANDLE__: DMA handle
00408   * @retval The specified transfer error flag index.
00409   */
00410 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00411 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
00412  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
00413  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
00414  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
00415  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
00416  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
00417  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
00418  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
00419  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
00420  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
00421  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
00422  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
00423    DMA_ISR_GIF7)
00424
00425 /**
00426   * @brief  Get the DMA Channel pending flags.
00427   * @param  __HANDLE__: DMA handle
00428   * @param  __FLAG__: Get the specified flag.
00429   *          This parameter can be any combination of the following values:
00430   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00431   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00432   *            @arg DMA_FLAG_TEx:  Transfer error flag
00433   *            @arg DMA_FLAG_GLx:  Global interrupt flag
00434   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
00435   * @retval The state of FLAG (SET or RESET).
00436   */
00437 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
00438  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
00439
00440 /**
00441   * @brief  Clear the DMA Channel pending flags.
00442   * @param  __HANDLE__: DMA handle
00443   * @param  __FLAG__: specifies the flag to clear.
00444   *          This parameter can be any combination of the following values:
00445   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00446   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00447   *            @arg DMA_FLAG_TEx:  Transfer error flag
00448   *            @arg DMA_FLAG_GLx:  Global interrupt flag
00449   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
00450   * @retval None
00451   */
00452 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
00453  (DMA2->IFCR |= (__FLAG__)) : (DMA1->IFCR |= (__FLAG__)))
00454
00455 /**
00456   * @brief  Enable the specified DMA Channel interrupts.
00457   * @param  __HANDLE__: DMA handle
00458   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00459   *          This parameter can be any combination of the following values:
00460   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00461   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00462   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00463   * @retval None
00464   */
00465 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
00466
00467 /**
00468   * @brief  Disable the specified DMA Channel interrupts.
00469   * @param  __HANDLE__: DMA handle
00470   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00471   *          This parameter can be any combination of the following values:
00472   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00473   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00474   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00475   * @retval None
00476   */
00477 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
00478
00479 /**
00480   * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
00481   * @param  __HANDLE__: DMA handle
00482   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
00483   *          This parameter can be one of the following values:
00484   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00485   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00486   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00487   * @retval The state of DMA_IT (SET or RESET).
00488   */
00489 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
00490
00491 /**
00492   * @brief  Return the number of remaining data units in the current DMA Channel transfer.
00493   * @param  __HANDLE__: DMA handle
00494   * @retval The number of remaining data units in the current DMA Channel transfer.
00495   */
00496 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
00497
00498 /**
00499   * @}
00500   */
00501
00502 /* Exported functions --------------------------------------------------------*/
00503
00504 /** @addtogroup DMA_Exported_Functions
00505   * @{
00506   */
00507
00508 /** @addtogroup DMA_Exported_Functions_Group1
00509   * @{
00510   */
00511 /* Initialization and de-initialization functions *****************************/
00512 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00513 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
00514 /**
00515   * @}
00516   */
00517
00518 /** @addtogroup DMA_Exported_Functions_Group2
00519   * @{
00520   */
00521 /* IO operation functions *****************************************************/
00522 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00523 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00524 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
00525 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
00526 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
00527 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
00528 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
00529 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
00530
00531 /**
00532   * @}
00533   */
00534
00535 /** @addtogroup DMA_Exported_Functions_Group3
00536   * @{
00537   */
00538 /* Peripheral State and Error functions ***************************************/
00539 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
00540 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
00541 /**
00542   * @}
00543   */
00544
00545 /**
00546   * @}
00547   */
00548
00549 /* Private macros ------------------------------------------------------------*/
00550 /** @defgroup DMA_Private_Macros DMA Private Macros
00551   * @{
00552   */
00553
00554 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
00555                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
00556                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
00557
00558 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
00559
00560 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
00561                                             ((STATE) == DMA_PINC_DISABLE))
00562
00563 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
00564                                         ((STATE) == DMA_MINC_DISABLE))
00565
00566 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
00567                                      ((REQUEST) == DMA_REQUEST_1) || \
00568                                      ((REQUEST) == DMA_REQUEST_2) || \
00569                                      ((REQUEST) == DMA_REQUEST_3) || \
00570                                      ((REQUEST) == DMA_REQUEST_4) || \
00571                                      ((REQUEST) == DMA_REQUEST_5) || \
00572                                      ((REQUEST) == DMA_REQUEST_6) || \
00573                                      ((REQUEST) == DMA_REQUEST_7))
00574
00575 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
00576                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
00577                                            ((SIZE) == DMA_PDATAALIGN_WORD))
00578
00579 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
00580                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
00581                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
00582
00583 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
00584                            ((MODE) == DMA_CIRCULAR))
00585
00586 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
00587                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
00588                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
00589                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
00590
00591 /**
00592   * @}
00593   */
00594
00595 /* Private functions ---------------------------------------------------------*/
00596
00597 /**
00598   * @}
00599   */
00600
00601 /**
00602   * @}
00603   */
00604
00605 #ifdef __cplusplus
00606 }
00607 #endif
00608
00609 #endif /* __STM32L4xx_HAL_DMA_H */
00610
00611 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_firewall.c Source File

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stm32l4xx_hal_firewall.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_firewall.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   FIREWALL HAL module driver.
00008   *          This file provides firmware functions to manage the Firewall
00009   *          Peripheral initialization and enabling.
00010   *
00011   *
00012   @verbatim
00013  ===============================================================================
00014                         ##### How to use this driver #####
00015  ===============================================================================
00016   [..]
00017     The FIREWALL HAL driver can be used as follows:
00018
00019     (#) Declare a FIREWALL_InitTypeDef initialization structure.
00020
00021     (#) Resort to HAL_FIREWALL_Config() API to initialize the Firewall
00022
00023     (#) Enable the FIREWALL in calling HAL_FIREWALL_EnableFirewall() API
00024
00025     (#) To ensure that any code executed outside the protected segment closes the
00026         FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling
00027         __HAL_FIREWALL_PREARM_ENABLE() macro if called within a protected code segment
00028         or
00029         HAL_FIREWALL_EnablePreArmFlag() API if called outside of protected code segment
00030         after HAL_FIREWALL_Config() call.
00031
00032
00033   @endverbatim
00034   ******************************************************************************
00035   * @attention
00036   *
00037   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00038   *
00039   * Redistribution and use in source and binary forms, with or without modification,
00040   * are permitted provided that the following conditions are met:
00041   *   1. Redistributions of source code must retain the above copyright notice,
00042   *      this list of conditions and the following disclaimer.
00043   *   2. Redistributions in binary form must reproduce the above copyright notice,
00044   *      this list of conditions and the following disclaimer in the documentation
00045   *      and/or other materials provided with the distribution.
00046   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00047   *      may be used to endorse or promote products derived from this software
00048   *      without specific prior written permission.
00049   *
00050   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00051   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00052   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00053   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00054   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00055   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00056   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00057   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00058   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00059   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00060   *
00061   ******************************************************************************
00062   */
00063
00064 /* Includes ------------------------------------------------------------------*/
00065 #include "stm32l4xx_hal.h"
00066
00067 /** @addtogroup STM32L4xx_HAL_Driver
00068   * @{
00069   */
00070
00071 /** @defgroup FIREWALL FIREWALL
00072   * @brief HAL FIREWALL module driver
00073   * @{
00074   */
00075 #ifdef HAL_FIREWALL_MODULE_ENABLED
00076
00077 /* Private typedef -----------------------------------------------------------*/
00078 /* Private define ------------------------------------------------------------*/
00079 /* Private macro -------------------------------------------------------------*/
00080 /* Private variables ---------------------------------------------------------*/
00081 /* Private function prototypes -----------------------------------------------*/
00082 /* Private functions ---------------------------------------------------------*/
00083
00084
00085 /** @defgroup FIREWALL_Exported_Functions FIREWALL Exported Functions
00086   * @{
00087   */
00088
00089 /** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions
00090   * @brief    Initialization and Configuration Functions
00091   *
00092 @verbatim
00093 ===============================================================================
00094             ##### Initialization and Configuration functions #####
00095  ===============================================================================
00096     [..]
00097     This subsection provides the functions allowing to initialize the Firewall.
00098     Initialization is done by HAL_FIREWALL_Config():
00099
00100       (+) Enable the Firewall clock thru __HAL_RCC_FIREWALL_CLK_ENABLE() macro.
00101
00102       (+) Set the protected code segment address start and length.
00103
00104       (+) Set the protected non-volatile and/or volatile data segments
00105           address starts and lengths if applicable.
00106
00107       (+) Set the volatile data segment execution and sharing status.
00108
00109       (+) Length must be set to 0 for an unprotected segment.
00110
00111 @endverbatim
00112   * @{
00113   */
00114
00115 /**
00116   * @brief Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters.
00117   * @param fw_init: Firewall initialization structure
00118   * @note  The API returns HAL_ERROR if the Firewall is already enabled.
00119   * @retval HAL status
00120   */
00121 HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init)
00122 {
00123   /* Check the Firewall initialization structure allocation */
00124   if(fw_init == NULL)
00125   {
00126     return HAL_ERROR;
00127   }
00128
00129   /* Enable Firewall clock */
00130   __HAL_RCC_FIREWALL_CLK_ENABLE();
00131
00132   /* Make sure that Firewall is not enabled already */
00133   if (__HAL_FIREWALL_IS_ENABLED() != RESET)
00134   {
00135     return HAL_ERROR;
00136   }
00137
00138   /* Check Firewall configuration addresses and lengths when segment is protected */
00139   /* Code segment */
00140   if (fw_init->CodeSegmentLength != 0)
00141   {
00142     assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress));
00143     assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength));
00144   }
00145   /* Non volatile data segment */
00146   if (fw_init->NonVDataSegmentLength != 0)
00147   {
00148     assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress));
00149     assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength));
00150   }
00151   /* Volatile data segment */
00152   if (fw_init->VDataSegmentLength != 0)
00153   {
00154     assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress));
00155     assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength));
00156   }
00157
00158   /* Check Firewall Configuration Register parameters */
00159   assert_param(IS_FIREWALL_VOLATILEDATA_EXECUTE(fw_init->VolatileDataExecution));
00160   assert_param(IS_FIREWALL_VOLATILEDATA_SHARE(fw_init->VolatileDataShared));
00161
00162
00163    /* Configuration */
00164
00165   /* Protected code segment start address configuration */
00166   WRITE_REG(FIREWALL->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress));
00167         /* Protected code segment length configuration */
00168   WRITE_REG(FIREWALL->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength));
00169
00170   /* Protected non volatile data segment start address configuration */
00171   WRITE_REG(FIREWALL->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress));
00172         /* Protected non volatile data segment length configuration */
00173   WRITE_REG(FIREWALL->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength));
00174
00175   /* Protected volatile data segment start address configuration */
00176   WRITE_REG(FIREWALL->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress));
00177         /* Protected volatile data segment length configuration */
00178   WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength));
00179
00180   /* Set Firewall Configuration Register VDE and VDS bits
00181      (volatile data execution and shared configuration) */
00182   MODIFY_REG(FIREWALL->CR, FW_CR_VDS|FW_CR_VDE, fw_init->VolatileDataExecution|fw_init->VolatileDataShared);
00183
00184   return HAL_OK;
00185 }
00186
00187 /**
00188   * @brief Retrieve the Firewall configuration.
00189   * @param fw_config: Firewall configuration, type is same as initialization structure
00190   * @note This API can't be executed inside a code area protected by the Firewall
00191   *       when the Firewall is enabled
00192   * @note If NVDSL register is different from 0, that is, if the non volatile data segment
00193   *       is defined, this API can't be executed when the Firewall is enabled.
00194   * @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status
00195   * @retval None
00196   */
00197 void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config)
00198 {
00199
00200   /* Enable Firewall clock, in case no Firewall configuration has been carried
00201      out up to this point */
00202   __HAL_RCC_FIREWALL_CLK_ENABLE();
00203
00204   /* Retrieve code segment protection setting */
00205   fw_config->CodeSegmentStartAddress = (READ_REG(FIREWALL->CSSA) & FW_CSSA_ADD);
00206   fw_config->CodeSegmentLength = (READ_REG(FIREWALL->CSL) & FW_CSL_LENG);
00207
00208   /* Retrieve non volatile data segment protection setting */
00209   fw_config->NonVDataSegmentStartAddress = (READ_REG(FIREWALL->NVDSSA) & FW_NVDSSA_ADD);
00210   fw_config->NonVDataSegmentLength = (READ_REG(FIREWALL->NVDSL) & FW_NVDSL_LENG);
00211
00212   /* Retrieve volatile data segment protection setting */
00213   fw_config->VDataSegmentStartAddress = (READ_REG(FIREWALL->VDSSA) & FW_VDSSA_ADD);
00214   fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG);
00215
00216   /* Retrieve volatile data execution setting */
00217   fw_config->VolatileDataExecution = (READ_REG(FIREWALL->CR) & FW_CR_VDE);
00218
00219   /* Retrieve volatile data shared setting */
00220   fw_config->VolatileDataShared = (READ_REG(FIREWALL->CR) & FW_CR_VDS);
00221
00222   return;
00223 }
00224
00225
00226
00227 /**
00228   * @brief Enable FIREWALL.
00229   * @note Firewall is enabled in clearing FWDIS bit of SYSCFG CFGR1 register.
00230   *       Once enabled, the Firewall cannot be disabled by software. Only a
00231   *       system reset can set again FWDIS bit.
00232   * @retval None
00233   */
00234 void HAL_FIREWALL_EnableFirewall(void)
00235 {
00236   /* Clears FWDIS bit of SYSCFG CFGR1 register */
00237   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
00238
00239 }
00240
00241 /**
00242   * @brief Enable FIREWALL pre arm.
00243   * @note When FPA bit is set, any code executed outside the protected segment
00244   *       will close the Firewall.
00245   * @note This API provides the same service as __HAL_FIREWALL_PREARM_ENABLE() macro
00246   *       but can't be executed inside a code area protected by the Firewall.
00247   * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.
00248   * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is,
00249   *       when the non volatile data segment is not defined),
00250   *        **  this API can be executed when the Firewall is closed
00251   *        **  when the Firewall is opened, user should resort to
00252   *            __HAL_FIREWALL_PREARM_ENABLE() macro instead
00253   * @note When the Firewall is enabled and  NVDSL register is different from 0
00254   *       (that is, when the non volatile data segment is defined)
00255   *       **  FW_CR register can be accessed only when the Firewall is opened:
00256   *           user should resort to  __HAL_FIREWALL_PREARM_ENABLE() macro instead.
00257   * @retval None
00258   */
00259 void HAL_FIREWALL_EnablePreArmFlag(void)
00260 {
00261   /* Set FPA bit */
00262   SET_BIT(FIREWALL->CR, FW_CR_FPA);
00263 }
00264
00265
00266 /**
00267   * @brief Disable FIREWALL pre arm.
00268   * @note When FPA bit is reset, any code executed outside the protected segment
00269   *       when the Firewall is opened will generate a system reset.
00270   * @note This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro
00271   *       but can't be executed inside a code area protected by the Firewall.
00272   * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.
00273   * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is,
00274   *       when the non volatile data segment is not defined),
00275   *        **  this API can be executed when the Firewall is closed
00276   *        **  when the Firewall is opened, user should resort to
00277   *            __HAL_FIREWALL_PREARM_DISABLE() macro instead
00278   * @note When the Firewall is enabled and  NVDSL register is different from 0
00279   *       (that is, when the non volatile data segment is defined)
00280   *       **  FW_CR register can be accessed only when the Firewall is opened:
00281   *           user should resort to  __HAL_FIREWALL_PREARM_DISABLE() macro instead.
00282
00283   * @retval None
00284   */
00285 void HAL_FIREWALL_DisablePreArmFlag(void)
00286 {
00287   /* Clear FPA bit */
00288   CLEAR_BIT(FIREWALL->CR, FW_CR_FPA);
00289 }
00290
00291 /**
00292   * @}
00293   */
00294
00295 /**
00296   * @}
00297   */
00298
00299 #endif /* HAL_FIREWALL_MODULE_ENABLED */
00300 /**
00301   * @}
00302   */
00303
00304 /**
00305   * @}
00306   */
00307
00308 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_firewall.h Source File

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stm32l4xx_hal_firewall.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_firewall.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of FIREWALL HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_FIREWALL_H
00040 #define __STM32L4xx_HAL_FIREWALL_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FIREWALL  FIREWALL
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup FIREWALL_Exported_Types FIREWALL Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief FIREWALL Initialization Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t CodeSegmentStartAddress;        /*!< Protected code segment start address. This value is 24-bit long, the 8 LSB bits are
00068                                                 reserved and forced to 0 in order to allow a 256-byte granularity. */
00069
00070   uint32_t CodeSegmentLength;              /*!< Protected code segment length in bytes. This value is 22-bit long, the 8 LSB bits are
00071                                                 reserved and forced to 0 for the length to be a multiple of 256 bytes. */
00072
00073   uint32_t NonVDataSegmentStartAddress;    /*!< Protected non-volatile data segment start address. This value is 24-bit long, the 8 LSB
00074                                                 bits are reserved and forced to 0 in order to allow a 256-byte granularity. */
00075
00076   uint32_t NonVDataSegmentLength;          /*!< Protected non-volatile data segment length in bytes. This value is 22-bit long, the 8 LSB
00077                                                 bits are reserved and forced to 0 for the length to be a multiple of 256 bytes. */
00078
00079   uint32_t VDataSegmentStartAddress;       /*!< Protected volatile data segment start address. This value is 17-bit long, the 6 LSB bits
00080                                                 are reserved and forced to 0 in order to allow a 64-byte granularity. */
00081
00082   uint32_t VDataSegmentLength;             /*!< Protected volatile data segment length in bytes. This value is 17-bit long, the 6 LSB
00083                                                 bits are reserved and forced to 0 for the length to be a multiple of 64 bytes. */
00084
00085   uint32_t VolatileDataExecution;          /*!< Set VDE bit specifying whether or not the volatile data segment can be executed.
00086                                                  When VDS = 1 (set by parameter VolatileDataShared), VDE bit has no meaning.
00087                                                 This parameter can be a value of @ref FIREWALL_VolatileData_Executable */
00088
00089   uint32_t VolatileDataShared;             /*!< Set VDS bit in specifying whether or not the volatile data segment can be shared with a
00090                                                 non-protected application code.
00091                                                 This parameter can be a value of @ref FIREWALL_VolatileData_Shared */
00092
00093 }FIREWALL_InitTypeDef;
00094
00095
00096 /**
00097   * @}
00098   */
00099
00100
00101 /* Exported constants --------------------------------------------------------*/
00102 /** @defgroup FIREWALL_Exported_Constants FIREWALL Exported Constants
00103   * @{
00104   */
00105
00106 /** @defgroup FIREWALL_VolatileData_Executable   FIREWALL volatile data segment execution status
00107   * @{
00108   */
00109 #define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE                 ((uint32_t)0x0000)
00110 #define FIREWALL_VOLATILEDATA_EXECUTABLE                     ((uint32_t)FW_CR_VDE)
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup FIREWALL_VolatileData_Shared  FIREWALL volatile data segment share status
00116   * @{
00117   */
00118 #define FIREWALL_VOLATILEDATA_NOT_SHARED                ((uint32_t)0x0000)
00119 #define FIREWALL_VOLATILEDATA_SHARED                    ((uint32_t)FW_CR_VDS)
00120 /**
00121   * @}
00122   */
00123
00124 /** @defgroup FIREWALL_Pre_Arm FIREWALL pre arm status
00125   * @{
00126   */
00127 #define FIREWALL_PRE_ARM_RESET                 ((uint32_t)0x0000)
00128 #define FIREWALL_PRE_ARM_SET                   ((uint32_t)FW_CR_FPA)
00129
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @}
00136   */
00137
00138 /* Private macros --------------------------------------------------------*/
00139 /** @defgroup FIREWALL_Private_Macros   FIREWALL Private Macros
00140   * @{
00141   */
00142 #define IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
00143 #define IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
00144
00145 #define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
00146 #define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
00147
00148 #define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= SRAM1_BASE) && ((ADDRESS) < (SRAM1_BASE + SRAM1_SIZE_MAX)))
00149 #define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM1_BASE + SRAM1_SIZE_MAX))
00150
00151
00152 #define IS_FIREWALL_VOLATILEDATA_SHARE(SHARE) (((SHARE) == FIREWALL_VOLATILEDATA_NOT_SHARED) || \
00153                                                ((SHARE) == FIREWALL_VOLATILEDATA_SHARED))
00154
00155 #define IS_FIREWALL_VOLATILEDATA_EXECUTE(EXECUTE) (((EXECUTE) == FIREWALL_VOLATILEDATA_NOT_EXECUTABLE) || \
00156                                                    ((EXECUTE) == FIREWALL_VOLATILEDATA_EXECUTABLE))
00157 /**
00158   * @}
00159   */
00160
00161
00162 /* Exported macros -----------------------------------------------------------*/
00163 /** @defgroup FIREWALL_Exported_Macros FIREWALL Exported Macros
00164   * @{
00165   */
00166
00167 /** @brief  Check whether the FIREWALL is enabled or not.
00168   * @retval FIREWALL enabling status (TRUE or FALSE).
00169   */
00170 #define  __HAL_FIREWALL_IS_ENABLED()  HAL_IS_BIT_CLR(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS)
00171
00172
00173 /** @brief Enable FIREWALL pre arm.
00174   * @note When FPA bit is set, any code executed outside the protected segment
00175   *       closes the Firewall, otherwise it generates a system reset.
00176   * @note This macro provides the same service as HAL_FIREWALL_EnablePreArmFlag() API
00177   *       but can be executed inside a code area protected by the Firewall.
00178   * @note This macro can be executed whatever the Firewall state (opened or closed) when
00179   *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
00180   *       0, that is, when the non volatile data segment is defined), the macro can be
00181   *       executed only when the Firewall is opened.
00182   */
00183 #define __HAL_FIREWALL_PREARM_ENABLE()                                         \
00184              do {                                                              \
00185                   __IO uint32_t tmpreg;                                        \
00186                   SET_BIT(FIREWALL->CR, FW_CR_FPA) ;                           \
00187                   /* Read bit back to ensure it is taken into account by IP */ \
00188                   /* (introduce proper delay inside macro execution) */        \
00189                   tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                 \
00190                   UNUSED(tmpreg);                                              \
00191                 } while(0)
00192
00193
00194
00195 /** @brief Disable FIREWALL pre arm.
00196   * @note When FPA bit is set, any code executed outside the protected segment
00197   *       closes the Firewall, otherwise, it generates a system reset.
00198   * @note This macro provides the same service as HAL_FIREWALL_DisablePreArmFlag() API
00199   *       but can be executed inside a code area protected by the Firewall.
00200   * @note This macro can be executed whatever the Firewall state (opened or closed) when
00201   *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
00202   *       0, that is, when the non volatile data segment is defined), the macro can be
00203   *       executed only when the Firewall is opened.
00204   */
00205 #define __HAL_FIREWALL_PREARM_DISABLE()                                        \
00206              do {                                                              \
00207                   __IO uint32_t tmpreg;                                        \
00208                   CLEAR_BIT(FIREWALL->CR, FW_CR_FPA) ;                         \
00209                   /* Read bit back to ensure it is taken into account by IP */ \
00210                   /* (introduce proper delay inside macro execution) */        \
00211                   tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                 \
00212                   UNUSED(tmpreg);                                              \
00213                 } while(0)
00214
00215 /** @brief Enable volatile data sharing in setting VDS bit.
00216   * @note When VDS bit is set, the volatile data segment is shared with non-protected
00217   *       application code. It can be accessed whatever the Firewall state (opened or closed).
00218   * @note This macro can be executed inside a code area protected by the Firewall.
00219   * @note This macro can be executed whatever the Firewall state (opened or closed) when
00220   *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
00221   *       0, that is, when the non volatile data segment is defined), the macro can be
00222   *       executed only when the Firewall is opened.
00223   */
00224 #define __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE()                            \
00225              do {                                                              \
00226                   __IO uint32_t tmpreg;                                        \
00227                   SET_BIT(FIREWALL->CR, FW_CR_VDS) ;                           \
00228                   /* Read bit back to ensure it is taken into account by IP */ \
00229                   /* (introduce proper delay inside macro execution) */        \
00230                   tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                 \
00231                   UNUSED(tmpreg);                                              \
00232                 } while(0)
00233
00234 /** @brief Disable volatile data sharing in resetting VDS bit.
00235   * @note When VDS bit is reset, the volatile data segment is not shared and cannot be
00236   *       hit by a non protected executable code when the Firewall is closed. If it is
00237   *       accessed in such a condition, a system reset is generated by the Firewall.
00238   * @note This macro can be executed inside a code area protected by the Firewall.
00239   * @note This macro can be executed whatever the Firewall state (opened or closed) when
00240   *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
00241   *       0, that is, when the non volatile data segment is defined), the macro can be
00242   *       executed only when the Firewall is opened.
00243   */
00244 #define __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE()                           \
00245              do {                                                              \
00246                   __IO uint32_t tmpreg;                                        \
00247                   CLEAR_BIT(FIREWALL->CR, FW_CR_VDS) ;                         \
00248                   /* Read bit back to ensure it is taken into account by IP */ \
00249                   /* (introduce proper delay inside macro execution) */        \
00250                   tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                 \
00251                   UNUSED(tmpreg);                                              \
00252                 } while(0)
00253
00254 /** @brief Enable volatile data execution in setting VDE bit.
00255   * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be
00256   *       executed whatever the VDE bit value.
00257   * @note When VDE bit is set (with VDS = 0), the volatile data segment is executable. When
00258   *       the Firewall call is closed, a "call gate" entry procedure is required to open
00259   *       first the Firewall.
00260   * @note This macro can be executed inside a code area protected by the Firewall.
00261   * @note This macro can be executed whatever the Firewall state (opened or closed) when
00262   *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
00263   *       0, that is, when the non volatile data segment is defined), the macro can be
00264   *       executed only when the Firewall is opened.
00265   */
00266 #define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE()                         \
00267              do {                                                              \
00268                   __IO uint32_t tmpreg;                                        \
00269                   SET_BIT(FIREWALL->CR, FW_CR_VDE) ;                           \
00270                   /* Read bit back to ensure it is taken into account by IP */ \
00271                   /* (introduce proper delay inside macro execution) */        \
00272                   tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                 \
00273                   UNUSED(tmpreg);                                              \
00274                 } while(0)
00275
00276 /** @brief Disable volatile data execution in resetting VDE bit.
00277   * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be
00278   *       executed whatever the VDE bit value.
00279   * @note When VDE bit is reset (with VDS = 0), the volatile data segment cannot  be executed.
00280   * @note This macro can be executed inside a code area protected by the Firewall.
00281   * @note This macro can be executed whatever the Firewall state (opened or closed) when
00282   *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
00283   *       0, that is, when the non volatile data segment is defined), the macro can be
00284   *       executed only when the Firewall is opened.
00285   */
00286 #define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE()                           \
00287              do {                                                              \
00288                   __IO uint32_t tmpreg;                                        \
00289                   CLEAR_BIT(FIREWALL->CR, FW_CR_VDE) ;                         \
00290                   /* Read bit back to ensure it is taken into account by IP */ \
00291                   /* (introduce proper delay inside macro execution) */        \
00292                   tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                 \
00293                   UNUSED(tmpreg);                                              \
00294                 } while(0)
00295
00296
00297 /** @brief Check whether or not the volatile data segment is shared.
00298   * @note This macro can be executed inside a code area protected by the Firewall.
00299   * @note This macro can be executed whatever the Firewall state (opened or closed) when
00300   *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
00301   *       0, that is, when the non volatile data segment is defined), the macro can be
00302   *       executed only when the Firewall is opened.
00303   * @retval VDS bit setting status (TRUE or FALSE).
00304   */
00305 #define __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FIREWALL->CR & FW_CR_VDS) == FW_CR_VDS)
00306
00307 /** @brief Check whether or not the volatile data segment is declared executable.
00308   * @note This macro can be executed inside a code area protected by the Firewall.
00309   * @note This macro can be executed whatever the Firewall state (opened or closed) when
00310   *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
00311   *       0, that is, when the non volatile data segment is defined), the macro can be
00312   *       executed only when the Firewall is opened.
00313   * @retval VDE bit setting status (TRUE or FALSE).
00314   */
00315 #define __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FIREWALL->CR & FW_CR_VDE) == FW_CR_VDE)
00316
00317 /** @brief Check whether or not the Firewall pre arm bit is set.
00318   * @note This macro can be executed inside a code area protected by the Firewall.
00319   * @note This macro can be executed whatever the Firewall state (opened or closed) when
00320   *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
00321   *       0, that is, when the non volatile data segment is defined), the macro can be
00322   *       executed only when the Firewall is opened.
00323   * @retval FPA bit setting status (TRUE or FALSE).
00324   */
00325 #define __HAL_FIREWALL_GET_PREARM() ((FIREWALL->CR & FW_CR_FPA) == FW_CR_FPA)
00326
00327
00328 /**
00329   * @}
00330   */
00331
00332 /* Exported functions --------------------------------------------------------*/
00333
00334 /** @addtogroup FIREWALL_Exported_Functions FIREWALL Exported Functions
00335   * @{
00336   */
00337
00338 /** @addtogroup FIREWALL_Exported_Functions_Group1 Initialization Functions
00339   * @brief    Initialization and Configuration Functions
00340   * @{
00341   */
00342
00343 /* Initialization functions  ********************************/
00344 HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init);
00345 void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config);
00346 void HAL_FIREWALL_EnableFirewall(void);
00347 void HAL_FIREWALL_EnablePreArmFlag(void);
00348 void HAL_FIREWALL_DisablePreArmFlag(void);
00349
00350 /**
00351   * @}
00352   */
00353
00354 /**
00355   * @}
00356   */
00357
00358 /**
00359   * @}
00360   */
00361
00362 /**
00363   * @}
00364   */
00365
00366 #ifdef __cplusplus
00367 }
00368 #endif
00369
00370 #endif /* __STM32L4xx_HAL_FIREWALL_H */
00371
00372 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash.c Source File

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stm32l4xx_hal_flash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_flash.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   FLASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the internal FLASH memory:
00010   *           + Program operations functions
00011   *           + Memory Control functions
00012   *           + Peripheral Errors functions
00013   *
00014  @verbatim
00015   ==============================================================================
00016                         ##### FLASH peripheral features #####
00017   ==============================================================================
00018
00019   [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
00020        to the Flash memory. It implements the erase and program Flash memory operations
00021        and the read and write protection mechanisms.
00022
00023   [..] The Flash memory interface accelerates code execution with a system of instruction
00024        prefetch and cache lines.
00025
00026   [..] The FLASH main features are:
00027       (+) Flash memory read operations
00028       (+) Flash memory program/erase operations
00029       (+) Read / write protections
00030       (+) Option bytes programming
00031       (+) Prefetch on I-Code
00032       (+) 32 cache lines of 4*64 bits on I-Code
00033       (+) 8 cache lines of 4*64 bits on D-Code
00034       (+) Error code correction (ECC) : Data in flash are 72-bits word
00035           (8 bits added per double word)
00036
00037
00038                         ##### How to use this driver #####
00039  ==============================================================================
00040     [..]
00041       This driver provides functions and macros to configure and program the FLASH
00042       memory of all STM32L4xx devices.
00043
00044       (#) Flash Memory IO Programming functions:
00045            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00046                 HAL_FLASH_Lock() functions
00047            (++) Program functions: double word and fast program (full row programming)
00048            (++) There Two modes of programming :
00049             (+++) Polling mode using HAL_FLASH_Program() function
00050             (+++) Interrupt mode using HAL_FLASH_Program_IT() function
00051
00052       (#) Interrupts and flags management functions :
00053            (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
00054            (++) Callback functions are called when the flash operations are finished :
00055                 HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
00056                 HAL_FLASH_OperationErrorCallback()
00057            (++) Get error flag status by calling HAL_GetError()
00058
00059       (#) Option bytes management functions :
00060            (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
00061                 HAL_FLASH_OB_Lock() functions
00062            (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
00063                 In this case, a reset is generated
00064
00065     [..]
00066       In addition to these functions, this driver includes a set of macros allowing
00067       to handle the following operations:
00068        (+) Set the latency
00069        (+) Enable/Disable the prefetch buffer
00070        (+) Enable/Disable the Instruction cache and the Data cache
00071        (+) Reset the Instruction cache and the Data cache
00072        (+) Enable/Disable the Flash power-down during low-power run and sleep modes
00073        (+) Enable/Disable the Flash interrupts
00074        (+) Monitor the Flash flags status
00075
00076  @endverbatim
00077   ******************************************************************************
00078   * @attention
00079   *
00080   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00081   *
00082   * Redistribution and use in source and binary forms, with or without modification,
00083   * are permitted provided that the following conditions are met:
00084   *   1. Redistributions of source code must retain the above copyright notice,
00085   *      this list of conditions and the following disclaimer.
00086   *   2. Redistributions in binary form must reproduce the above copyright notice,
00087   *      this list of conditions and the following disclaimer in the documentation
00088   *      and/or other materials provided with the distribution.
00089   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00090   *      may be used to endorse or promote products derived from this software
00091   *      without specific prior written permission.
00092   *
00093   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00094   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00095   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00096   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00097   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00098   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00099   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00100   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00101   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00102   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00103   *
00104   ******************************************************************************
00105   */
00106
00107 /* Includes ------------------------------------------------------------------*/
00108 #include "stm32l4xx_hal.h"
00109
00110 /** @addtogroup STM32L4xx_HAL_Driver
00111   * @{
00112   */
00113
00114 /** @defgroup FLASH FLASH
00115   * @brief FLASH HAL module driver
00116   * @{
00117   */
00118
00119 #ifdef HAL_FLASH_MODULE_ENABLED
00120
00121 /* Private typedef -----------------------------------------------------------*/
00122 /* Private defines -----------------------------------------------------------*/
00123 /* Private macros ------------------------------------------------------------*/
00124 /* Private variables ---------------------------------------------------------*/
00125 /** @defgroup FLASH_Private_Variables FLASH Private Variables
00126  * @{
00127  */
00128 /**
00129   * @brief  Variable used for Program/Erase sectors under interruption
00130   */
00131 FLASH_ProcessTypeDef pFlash;
00132 /**
00133   * @}
00134   */
00135
00136 /* Private function prototypes -----------------------------------------------*/
00137 /** @defgroup FLASH_Private_Functions FLASH Private Functions
00138  * @{
00139  */
00140 HAL_StatusTypeDef    FLASH_WaitForLastOperation(uint32_t Timeout);
00141 extern void          FLASH_PageErase(uint32_t Page, uint32_t Banks);
00142 extern void          FLASH_FlushCaches(void);
00143 static void          FLASH_SetErrorCode(void);
00144 static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
00145 static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
00146 /**
00147   * @}
00148   */
00149
00150 /* Exported functions --------------------------------------------------------*/
00151 /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
00152   * @{
00153   */
00154
00155 /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
00156  *  @brief   Programming operation functions
00157  *
00158 @verbatim
00159  ===============================================================================
00160                   ##### Programming operation functions #####
00161  ===============================================================================
00162     [..]
00163     This subsection provides a set of functions allowing to manage the FLASH
00164     program operations.
00165
00166 @endverbatim
00167   * @{
00168   */
00169
00170 /**
00171   * @brief  Program double word or fast program of a row at a specified address.
00172   * @param  TypeProgram:  Indicate the way to program at a specified address.
00173   *                           This parameter can be a value of @ref FLASH_Type_Program
00174   * @param  Address:  specifies the address to be programmed.
00175   * @param  Data: specifies the data to be programmed
00176   *                This parameter is the data for the double word program and the address where
00177   *                are stored the data for the row fast program
00178   *
00179   * @retval HAL_StatusTypeDef HAL Status
00180   */
00181 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00182 {
00183   HAL_StatusTypeDef status = HAL_ERROR;
00184   uint32_t prog_bit = 0;
00185
00186   /* Process Locked */
00187   __HAL_LOCK(&pFlash);
00188
00189   /* Check the parameters */
00190   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00191
00192   /* Wait for last operation to be completed */
00193   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00194
00195   if(status == HAL_OK)
00196   {
00197     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00198
00199     if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
00200     {
00201       /* Program double-word (64-bit) at a specified address */
00202       FLASH_Program_DoubleWord(Address, Data);
00203       prog_bit = FLASH_CR_PG;
00204     }
00205     else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
00206     {
00207       /* Fast program a 32 row double-word (64-bit) at a specified address */
00208       FLASH_Program_Fast(Address, (uint32_t)Data);
00209
00210       /* If it is the last row, the bit will be cleared at the end of the operation */
00211       if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
00212       {
00213         prog_bit = FLASH_CR_FSTPG;
00214       }
00215     }
00216
00217     /* Wait for last operation to be completed */
00218     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00219
00220     /* If the program operation is completed, disable the PG or FSTPG Bit */
00221     if (prog_bit != 0)
00222     {
00223       CLEAR_BIT(FLASH->CR, prog_bit);
00224     }
00225   }
00226
00227   /* Process Unlocked */
00228   __HAL_UNLOCK(&pFlash);
00229
00230   return status;
00231 }
00232
00233 /**
00234   * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.
00235   * @param  TypeProgram:  Indicate the way to program at a specified address.
00236   *                           This parameter can be a value of @ref FLASH_Type_Program
00237   * @param  Address:  specifies the address to be programmed.
00238   * @param  Data: specifies the data to be programmed
00239   *                This parameter is the data for the double word program and the address where
00240   *                are stored the data for the row fast program
00241   *
00242   * @retval HAL Status
00243   */
00244 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00245 {
00246   HAL_StatusTypeDef status = HAL_OK;
00247
00248   /* Check the parameters */
00249   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00250
00251   /* Process Locked */
00252   __HAL_LOCK(&pFlash);
00253
00254   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00255
00256   /* Set internal variables used by the IRQ handler */
00257   if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
00258   {
00259     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
00260   }
00261   else
00262   {
00263     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
00264   }
00265   pFlash.Address = Address;
00266
00267   /* Enable End of Operation and Error interrupts */
00268   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
00269
00270   if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
00271   {
00272     /* Program double-word (64-bit) at a specified address */
00273     FLASH_Program_DoubleWord(Address, Data);
00274   }
00275     else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
00276   {
00277     /* Fast program a 32 row double-word (64-bit) at a specified address */
00278     FLASH_Program_Fast(Address, (uint32_t)Data);
00279   }
00280
00281   return status;
00282 }
00283
00284 /**
00285   * @brief Handle FLASH interrupt request.
00286   * @retval None
00287   */
00288 void HAL_FLASH_IRQHandler(void)
00289 {
00290   uint32_t tmp_page;
00291
00292   /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
00293   CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
00294 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00295   CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
00296 #endif
00297
00298   /* Disable the FSTPG Bit only if it is the last row programmed */
00299   if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
00300   {
00301     CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
00302   }
00303
00304   /* Check FLASH operation error flags */
00305   if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) ||
00306      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))  ||
00307      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))  ||
00308      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) ||
00309      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) ||
00310 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00311      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))   || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)))
00312 #else
00313      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)))
00314 #endif
00315   {
00316     /*Save the error code*/
00317     FLASH_SetErrorCode();
00318
00319     /* FLASH error interrupt user callback */
00320     if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
00321     {
00322        HAL_FLASH_EndOfOperationCallback(pFlash.Page);
00323     }
00324     else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE)
00325     {
00326         HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
00327     }
00328     else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) ||
00329             (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST))
00330     {
00331        HAL_FLASH_OperationErrorCallback(pFlash.Address);
00332     }
00333
00334     HAL_FLASH_OperationErrorCallback(pFlash.Address);
00335
00336     /*Stop the procedure ongoing*/
00337     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00338   }
00339
00340   /* Check FLASH End of Operation flag  */
00341   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
00342   {
00343     /* Clear FLASH End of Operation pending bit */
00344     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00345
00346     if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
00347     {
00348       /* Nb of pages to erased can be decreased */
00349       pFlash.NbPagesToErase--;
00350
00351       /* Check if there are still pages to erase*/
00352       if(pFlash.NbPagesToErase != 0)
00353       {
00354         /* Indicate user which page has been erased*/
00355         HAL_FLASH_EndOfOperationCallback(pFlash.Page);
00356
00357         /* Increment page number */
00358         pFlash.Page++;
00359         tmp_page = pFlash.Page;
00360         FLASH_PageErase(tmp_page, pFlash.Bank);
00361       }
00362       else
00363       {
00364         /* No more pages to Erase */
00365         /* Reset Address and stop Erase pages procedure */
00366         pFlash.Page = 0xFFFFFFFF;
00367         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00368
00369         /* Flush the caches to be sure of the data consistency */
00370         FLASH_FlushCaches() ;
00371
00372         /* FLASH EOP interrupt user callback */
00373         HAL_FLASH_EndOfOperationCallback(pFlash.Page);
00374       }
00375     }
00376     else
00377     {
00378       if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE)
00379       {
00380         /* MassErase ended. Return the selected bank */
00381         /* Flush the caches to be sure of the data consistency */
00382         FLASH_FlushCaches() ;
00383
00384         /* FLASH EOP interrupt user callback */
00385         HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
00386       }
00387       else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) ||
00388               (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST))
00389       {
00390         /* Program ended. Return the selected address */
00391         /* FLASH EOP interrupt user callback */
00392         HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00393       }
00394
00395       /*Clear the procedure ongoing*/
00396       pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00397     }
00398   }
00399
00400   if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
00401   {
00402     /* Disable End of Operation and Error interrupts */
00403     __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
00404
00405     /* Process Unlocked */
00406     __HAL_UNLOCK(&pFlash);
00407   }
00408 }
00409
00410 /**
00411   * @brief  FLASH end of operation interrupt callback.
00412   * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
00413   *                  Mass Erase: Bank number which has been requested to erase
00414   *                  Page Erase: Page which has been erased
00415   *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
00416   *                  Program: Address which was selected for data program
00417   * @retval None
00418   */
00419 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
00420 {
00421   /* Prevent unused argument(s) compilation warning */
00422   UNUSED(ReturnValue);
00423
00424   /* NOTE : This function should not be modified, when the callback is needed,
00425             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
00426    */
00427 }
00428
00429 /**
00430   * @brief  FLASH operation error interrupt callback.
00431   * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
00432   *                 Mass Erase: Bank number which has been requested to erase
00433   *                 Page Erase: Page number which returned an error
00434   *                 Program: Address which was selected for data program
00435   * @retval None
00436   */
00437 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
00438 {
00439   /* Prevent unused argument(s) compilation warning */
00440   UNUSED(ReturnValue);
00441
00442   /* NOTE : This function should not be modified, when the callback is needed,
00443             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
00444    */
00445 }
00446
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
00452  *  @brief   Management functions
00453  *
00454 @verbatim
00455  ===============================================================================
00456                       ##### Peripheral Control functions #####
00457  ===============================================================================
00458     [..]
00459     This subsection provides a set of functions allowing to control the FLASH
00460     memory operations.
00461
00462 @endverbatim
00463   * @{
00464   */
00465
00466 /**
00467   * @brief  Unlock the FLASH control register access.
00468   * @retval HAL Status
00469   */
00470 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
00471 {
00472   if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
00473   {
00474     /* Authorize the FLASH Registers access */
00475     WRITE_REG(FLASH->KEYR, FLASH_KEY1);
00476     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
00477   }
00478   else
00479   {
00480     return HAL_ERROR;
00481   }
00482
00483   return HAL_OK;
00484 }
00485
00486 /**
00487   * @brief  Lock the FLASH control register access.
00488   * @retval HAL Status
00489   */
00490 HAL_StatusTypeDef HAL_FLASH_Lock(void)
00491 {
00492   /* Set the LOCK Bit to lock the FLASH Registers access */
00493   SET_BIT(FLASH->CR, FLASH_CR_LOCK);
00494
00495   return HAL_OK;
00496 }
00497
00498 /**
00499   * @brief  Unlock the FLASH Option Bytes Registers access.
00500   * @retval HAL Status
00501   */
00502 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
00503 {
00504   if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != RESET)
00505   {
00506     /* Authorizes the Option Byte register programming */
00507     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
00508     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
00509   }
00510   else
00511   {
00512     return HAL_ERROR;
00513   }
00514
00515   return HAL_OK;
00516 }
00517
00518 /**
00519   * @brief  Lock the FLASH Option Bytes Registers access.
00520   * @retval HAL Status
00521   */
00522 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
00523 {
00524   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
00525   SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
00526
00527   return HAL_OK;
00528 }
00529
00530 /**
00531   * @brief  Launch the option byte loading.
00532   * @retval HAL Status
00533   */
00534 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
00535 {
00536   /* Set the bit to force the option byte reloading */
00537   SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
00538
00539   /* Wait for last operation to be completed */
00540   return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
00541 }
00542
00543 /**
00544   * @}
00545   */
00546
00547 /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
00548  *  @brief   Peripheral Errors functions
00549  *
00550 @verbatim
00551  ===============================================================================
00552                 ##### Peripheral Errors functions #####
00553  ===============================================================================
00554     [..]
00555     This subsection permits to get in run-time Errors of the FLASH peripheral.
00556
00557 @endverbatim
00558   * @{
00559   */
00560
00561 /**
00562   * @brief  Get the specific FLASH error flag.
00563   * @retval FLASH_ErrorCode: The returned value can be:
00564   *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
00565   *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
00566   *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
00567   *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
00568   *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
00569   *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
00570   *            @arg HAL_FLASH_ERROR_NONE: No error set
00571   *            @arg HAL_FLASH_ERROR_OP: FLASH Operation error
00572   *            @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
00573   *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
00574   *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
00575   *            @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
00576   *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
00577   *            @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
00578   *            @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
00579   *            @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
00580   *            @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
00581   *            @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
00582   *            @arg HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected
00583   */
00584 uint32_t HAL_FLASH_GetError(void)
00585 {
00586    return pFlash.ErrorCode;
00587 }
00588
00589 /**
00590   * @}
00591   */
00592
00593 /**
00594   * @}
00595   */
00596
00597 /* Private functions ---------------------------------------------------------*/
00598
00599 /** @addtogroup FLASH_Private_Functions
00600   * @{
00601   */
00602
00603 /**
00604   * @brief  Wait for a FLASH operation to complete.
00605   * @param  Timeout: maximum flash operation timeout
00606   * @retval HAL_StatusTypeDef HAL Status
00607   */
00608 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
00609 {
00610   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
00611      Even if the FLASH operation fails, the BUSY flag will be reset and an error
00612      flag will be set */
00613
00614   uint32_t timeout = HAL_GetTick() + Timeout;
00615
00616   while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
00617   {
00618     if(Timeout != HAL_MAX_DELAY)
00619     {
00620       if(HAL_GetTick() >= timeout)
00621       {
00622         return HAL_TIMEOUT;
00623       }
00624     }
00625   }
00626
00627   if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) ||
00628      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))  ||
00629      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))  ||
00630      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) ||
00631      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) ||
00632 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00633      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))   || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)))
00634 #else
00635      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)))
00636 #endif
00637   {
00638     /*Save the error code*/
00639     FLASH_SetErrorCode();
00640
00641     return HAL_ERROR;
00642   }
00643
00644   /* Check FLASH End of Operation flag  */
00645   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
00646   {
00647     /* Clear FLASH End of Operation pending bit */
00648     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00649   }
00650
00651   /* If there is an error flag set */
00652   return HAL_OK;
00653 }
00654
00655 /**
00656   * @brief  Set the specific FLASH error flag.
00657   * @retval None
00658   */
00659 static void FLASH_SetErrorCode(void)
00660 {
00661   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))
00662   {
00663     pFlash.ErrorCode |= HAL_FLASH_ERROR_OP;
00664   }
00665
00666   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR))
00667   {
00668     pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
00669   }
00670
00671   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
00672   {
00673     pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
00674   }
00675
00676   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
00677   {
00678     pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
00679   }
00680
00681   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
00682   {
00683     pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZ;
00684   }
00685
00686   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))
00687   {
00688     pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
00689   }
00690
00691   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR))
00692   {
00693    pFlash.ErrorCode |= HAL_FLASH_ERROR_MIS;
00694   }
00695
00696   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR))
00697   {
00698    pFlash.ErrorCode |= HAL_FLASH_ERROR_FAST;
00699   }
00700
00701   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
00702   {
00703    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
00704   }
00705
00706   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
00707   {
00708    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
00709   }
00710
00711   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))
00712   {
00713    pFlash.ErrorCode |= HAL_FLASH_ERROR_ECCD;
00714   }
00715
00716 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00717   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))
00718   {
00719     pFlash.ErrorCode |= HAL_FLASH_ERROR_PEMPTY;
00720     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PEMPTY);
00721   }
00722 #endif
00723
00724   /* Clear error programming flags */
00725   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
00726 }
00727
00728 /**
00729   * @brief  Program double-word (64-bit) at a specified address.
00730   * @param  Address: specifies the address to be programmed.
00731   * @param  Data: specifies the data to be programmed.
00732   * @retval None
00733   */
00734 static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
00735 {
00736   /* Check the parameters */
00737   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00738
00739   /* Set PG bit */
00740   SET_BIT(FLASH->CR, FLASH_CR_PG);
00741
00742   /* Program the double word */
00743   *(__IO uint32_t*)Address = (uint32_t)Data;
00744   *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
00745 }
00746
00747 /**
00748   * @brief  Fast program a 32 row double-word (64-bit) at a specified address.
00749   * @param  Address: specifies the address to be programmed.
00750   * @param  DataAddress: specifies the address where the data are stored.
00751   * @retval None
00752   */
00753 static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
00754 {
00755   uint8_t row_index = 32;
00756   __IO uint64_t *dest_addr = (__IO uint64_t*)Address;
00757   __IO uint64_t *src_addr = (__IO uint64_t*)DataAddress;
00758
00759   /* Check the parameters */
00760   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
00761
00762   /* Set FSTPG bit */
00763   SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
00764
00765   /* Disable interrupts to avoid any interruption during the loop */
00766   __disable_irq();
00767
00768   /* Program the 32 double word */
00769   do
00770   {
00771     *dest_addr++ = *src_addr++;
00772   } while (--row_index != 0);
00773
00774   /* Re-enable the interrupts */
00775   __enable_irq();
00776 }
00777
00778 /**
00779   * @}
00780   */
00781
00782 #endif /* HAL_FLASH_MODULE_ENABLED */
00783
00784 /**
00785   * @}
00786   */
00787
00788 /**
00789   * @}
00790   */
00791
00792 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash.h Source File

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stm32l4xx_hal_flash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_flash.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of FLASH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_FLASH_H
00040 #define __STM32L4xx_HAL_FLASH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASH
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup FLASH_Exported_Types FLASH Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  FLASH Erase structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t TypeErase;   /*!< Mass erase or page erase.
00068                              This parameter can be a value of @ref FLASH_Type_Erase */
00069   uint32_t Banks;       /*!< Select bank to erase.
00070                              This parameter must be a value of @ref FLASH_Banks
00071                              (FLASH_BANK_BOTH should be used only for mass erase) */
00072   uint32_t Page;        /*!< Initial Flash page to erase when page erase is disabled
00073                              This parameter must be a value between 0 and (max number of pages in the bank - 1)
00074                              (eg : 255 for 1MB dual bank) */
00075   uint32_t NbPages;     /*!< Number of pages to be erased.
00076                              This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
00077 } FLASH_EraseInitTypeDef;
00078
00079 /**
00080   * @brief  FLASH Option Bytes Program structure definition
00081   */
00082 typedef struct
00083 {
00084   uint32_t OptionType;     /*!< Option byte to be configured.
00085                                 This parameter can be a combination of the values of @ref FLASH_OB_Type */
00086   uint32_t WRPArea;        /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
00087                                 Only one WRP area could be programmed at the same time.
00088                                 This parameter can be value of @ref FLASH_OB_WRP_Area */
00089   uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
00090                                 This parameter must be a value between 0 and (max number of pages in the bank - 1)
00091                                 (eg : 25 for 1MB dual bank) */
00092   uint32_t WRPEndOffset;   /*!< Write protection end offset (used for OPTIONBYTE_WRP).
00093                                 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
00094   uint32_t RDPLevel;       /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
00095                                 This parameter can be a value of @ref FLASH_OB_Read_Protection */
00096   uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
00097                                 This parameter can be a combination of @ref FLASH_OB_USER_Type */
00098   uint32_t USERConfig;     /*!< Value of the user option byte (used for OPTIONBYTE_USER).
00099                                 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
00100                                 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
00101                                 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
00102                                 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
00103                                 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2,
00104                                 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1,
00105                                 @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */
00106   uint32_t PCROPConfig;    /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
00107                                 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
00108                                 and @ref FLASH_OB_PCROP_RDP */
00109   uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
00110                                 This parameter must be a value between begin and end of bank
00111                                 => Be careful of the bank swapping for the address */
00112   uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
00113                                 This parameter must be a value between PCROP Start address and end of bank */
00114 } FLASH_OBProgramInitTypeDef;
00115
00116 /**
00117   * @brief  FLASH Procedure structure definition
00118   */
00119 typedef enum
00120 {
00121   FLASH_PROC_NONE = 0,
00122   FLASH_PROC_PAGE_ERASE,
00123   FLASH_PROC_MASS_ERASE,
00124   FLASH_PROC_PROGRAM,
00125   FLASH_PROC_PROGRAM_LAST
00126 } FLASH_ProcedureTypeDef;
00127
00128 /**
00129   * @brief  FLASH handle Structure definition
00130   */
00131 typedef struct
00132 {
00133   HAL_LockTypeDef             Lock;              /* FLASH locking object */
00134   __IO uint32_t               ErrorCode;         /* FLASH error code */
00135   __IO FLASH_ProcedureTypeDef ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */
00136   __IO uint32_t               Address;           /* Internal variable to save address selected for program in IT context */
00137   __IO uint32_t               Bank;              /* Internal variable to save current bank selected during erase in IT context */
00138   __IO uint32_t               Page;              /* Internal variable to define the current page which is erasing in IT context */
00139   __IO uint32_t               NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */
00140 }FLASH_ProcessTypeDef;
00141
00142 /**
00143   * @}
00144   */
00145
00146 /* Exported constants --------------------------------------------------------*/
00147 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
00148   * @{
00149   */
00150
00151 /** @defgroup FLASH_Error FLASH Error
00152   * @{
00153   */
00154 #define HAL_FLASH_ERROR_NONE      ((uint32_t)0x00000000)
00155 #define HAL_FLASH_ERROR_OP        ((uint32_t)0x00000001)
00156 #define HAL_FLASH_ERROR_PROG      ((uint32_t)0x00000002)
00157 #define HAL_FLASH_ERROR_WRP       ((uint32_t)0x00000004)
00158 #define HAL_FLASH_ERROR_PGA       ((uint32_t)0x00000008)
00159 #define HAL_FLASH_ERROR_SIZ       ((uint32_t)0x00000010)
00160 #define HAL_FLASH_ERROR_PGS       ((uint32_t)0x00000020)
00161 #define HAL_FLASH_ERROR_MIS       ((uint32_t)0x00000040)
00162 #define HAL_FLASH_ERROR_FAST      ((uint32_t)0x00000080)
00163 #define HAL_FLASH_ERROR_RD        ((uint32_t)0x00000100)
00164 #define HAL_FLASH_ERROR_OPTV      ((uint32_t)0x00000200)
00165 #define HAL_FLASH_ERROR_ECCD      ((uint32_t)0x00000400)
00166 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00167 #define HAL_FLASH_ERROR_PEMPTY    ((uint32_t)0x00000800)
00168 #endif
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup FLASH_Type_Erase FLASH Erase Type
00174   * @{
00175   */
00176 #define FLASH_TYPEERASE_PAGES     ((uint32_t)0x00)  /*!<Pages erase only*/
00177 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)  /*!<Flash mass erase activation*/
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup FLASH_Banks FLASH Banks
00183   * @{
00184   */
00185 #define FLASH_BANK_1              ((uint32_t)0x01)                          /*!< Bank 1   */
00186 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00187 #define FLASH_BANK_2              ((uint32_t)0x02)                          /*!< Bank 2   */
00188 #define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */
00189 #else
00190 #define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1))                /*!< Bank 1   */
00191 #endif
00192 /**
00193   * @}
00194   */
00195
00196
00197 /** @defgroup FLASH_Type_Program FLASH Program Type
00198   * @{
00199   */
00200 #define FLASH_TYPEPROGRAM_DOUBLEWORD    ((uint32_t)0x00)  /*!<Program a double-word (64-bit) at a specified address.*/
00201 #define FLASH_TYPEPROGRAM_FAST          ((uint32_t)0x01)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.
00202                                                                  And another 32 row double-word (64-bit) will be programmed */
00203 #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.
00204                                                                  And this is the last 32 row double-word (64-bit) programmed */
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type
00210   * @{
00211   */
00212 #define OPTIONBYTE_WRP            ((uint32_t)0x01)  /*!< WRP option byte configuration */
00213 #define OPTIONBYTE_RDP            ((uint32_t)0x02)  /*!< RDP option byte configuration */
00214 #define OPTIONBYTE_USER           ((uint32_t)0x04)  /*!< USER option byte configuration */
00215 #define OPTIONBYTE_PCROP          ((uint32_t)0x08)  /*!< PCROP option byte configuration */
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
00221   * @{
00222   */
00223 #define OB_WRPAREA_BANK1_AREAA    ((uint32_t)0x00)  /*!< Flash Bank 1 Area A */
00224 #define OB_WRPAREA_BANK1_AREAB    ((uint32_t)0x01)  /*!< Flash Bank 1 Area B */
00225 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00226 #define OB_WRPAREA_BANK2_AREAA    ((uint32_t)0x02)  /*!< Flash Bank 2 Area A */
00227 #define OB_WRPAREA_BANK2_AREAB    ((uint32_t)0x04)  /*!< Flash Bank 2 Area B */
00228 #endif
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
00234   * @{
00235   */
00236 #define OB_RDP_LEVEL_0            ((uint32_t)0xAA)
00237 #define OB_RDP_LEVEL_1            ((uint32_t)0xBB)
00238 #define OB_RDP_LEVEL_2            ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2
00239                                                         it's no more possible to go back to level 1 or 0 */
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
00245   * @{
00246   */
00247 #define OB_USER_BOR_LEV           ((uint32_t)0x0001)                   /*!< BOR reset Level */
00248 #define OB_USER_nRST_STOP         ((uint32_t)0x0002)                   /*!< Reset generated when entering the stop mode */
00249 #define OB_USER_nRST_STDBY        ((uint32_t)0x0004)                   /*!< Reset generated when entering the standby mode */
00250 #define OB_USER_IWDG_SW           ((uint32_t)0x0008)                   /*!< Independent watchdog selection */
00251 #define OB_USER_IWDG_STOP         ((uint32_t)0x0010)                   /*!< Independent watchdog counter freeze in stop mode */
00252 #define OB_USER_IWDG_STDBY        ((uint32_t)0x0020)                   /*!< Independent watchdog counter freeze in standby mode */
00253 #define OB_USER_WWDG_SW           ((uint32_t)0x0040)                   /*!< Window watchdog selection */
00254 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00255 #define OB_USER_BFB2              ((uint32_t)0x0080)                   /*!< Dual-bank boot */
00256 #define OB_USER_DUALBANK          ((uint32_t)0x0100)                   /*!< Dual-Bank on 512KB or 256KB Flash memory devices */
00257 #endif
00258 #define OB_USER_nBOOT1            ((uint32_t)0x0200)                   /*!< Boot configuration */
00259 #define OB_USER_SRAM2_PE          ((uint32_t)0x0400)                   /*!< SRAM2 parity check enable */
00260 #define OB_USER_SRAM2_RST         ((uint32_t)0x0800)                   /*!< SRAM2 Erase when system reset */
00261 #define OB_USER_nRST_SHDW         ((uint32_t)0x1000)                   /*!< Reset generated when entering the shutdown mode */
00262 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00263 #define OB_USER_nSWBOOT0          ((uint32_t)0x2000)                   /*!< Software BOOT0 */
00264 #define OB_USER_nBOOT0            ((uint32_t)0x4000)                   /*!< nBOOT0 option bit */
00265 #endif
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
00271   * @{
00272   */
00273 #define OB_BOR_LEVEL_0            ((uint32_t)FLASH_OPTR_BOR_LEV_0)     /*!< Reset level threshold is around 1.7V */
00274 #define OB_BOR_LEVEL_1            ((uint32_t)FLASH_OPTR_BOR_LEV_1)     /*!< Reset level threshold is around 2.0V */
00275 #define OB_BOR_LEVEL_2            ((uint32_t)FLASH_OPTR_BOR_LEV_2)     /*!< Reset level threshold is around 2.2V */
00276 #define OB_BOR_LEVEL_3            ((uint32_t)FLASH_OPTR_BOR_LEV_3)     /*!< Reset level threshold is around 2.5V */
00277 #define OB_BOR_LEVEL_4            ((uint32_t)FLASH_OPTR_BOR_LEV_4)     /*!< Reset level threshold is around 2.8V */
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
00283   * @{
00284   */
00285 #define OB_STOP_RST               ((uint32_t)0x0000)                   /*!< Reset generated when entering the stop mode */
00286 #define OB_STOP_NORST             ((uint32_t)FLASH_OPTR_nRST_STOP)     /*!< No reset generated when entering the stop mode */
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
00292   * @{
00293   */
00294 #define OB_STANDBY_RST            ((uint32_t)0x0000)                   /*!< Reset generated when entering the standby mode */
00295 #define OB_STANDBY_NORST          ((uint32_t)FLASH_OPTR_nRST_STDBY)    /*!< No reset generated when entering the standby mode */
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
00301   * @{
00302   */
00303 #define OB_SHUTDOWN_RST           ((uint32_t)0x0000)                   /*!< Reset generated when entering the shutdown mode */
00304 #define OB_SHUTDOWN_NORST         ((uint32_t)FLASH_OPTR_nRST_SHDW)     /*!< No reset generated when entering the shutdown mode */
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
00310   * @{
00311   */
00312 #define OB_IWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware independent watchdog */
00313 #define OB_IWDG_SW                ((uint32_t)FLASH_OPTR_IWDG_SW)       /*!< Software independent watchdog */
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
00319   * @{
00320   */
00321 #define OB_IWDG_STOP_FREEZE       ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Stop mode */
00322 #define OB_IWDG_STOP_RUN          ((uint32_t)FLASH_OPTR_IWDG_STOP)     /*!< Independent watchdog counter is running in Stop mode */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
00328   * @{
00329   */
00330 #define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Standby mode */
00331 #define OB_IWDG_STDBY_RUN         ((uint32_t)FLASH_OPTR_IWDG_STDBY)    /*!< Independent watchdog counter is running in Standby mode */
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
00337   * @{
00338   */
00339 #define OB_WWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware window watchdog */
00340 #define OB_WWDG_SW                ((uint32_t)FLASH_OPTR_WWDG_SW)       /*!< Software window watchdog */
00341 /**
00342   * @}
00343   */
00344
00345 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00346 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
00347   * @{
00348   */
00349 #define OB_BFB2_DISABLE           ((uint32_t)0x000000)                 /*!< Dual-bank boot disable */
00350 #define OB_BFB2_ENABLE            ((uint32_t)FLASH_OPTR_BFB2)          /*!< Dual-bank boot enable */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
00356   * @{
00357   */
00358 #define OB_DUALBANK_SINGLE        ((uint32_t)0x000000)                 /*!< 256 KB/512 KB Single-bank Flash */
00359 #define OB_DUALBANK_DUAL          ((uint32_t)FLASH_OPTR_DUALBANK)      /*!< 256 KB/512 KB Dual-bank Flash */
00360 /**
00361   * @}
00362   */
00363 #endif
00364
00365 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
00366   * @{
00367   */
00368 #define OB_BOOT1_SRAM             ((uint32_t)0x000000)                 /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
00369 #define OB_BOOT1_SYSTEM           ((uint32_t)FLASH_OPTR_nBOOT1)        /*!< System memory is selected as boot space (if BOOT0=1) */
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type
00375   * @{
00376   */
00377 #define OB_SRAM2_PARITY_ENABLE    ((uint32_t)0x0000000)                /*!< SRAM2 parity check enable */
00378 #define OB_SRAM2_PARITY_DISABLE   ((uint32_t)FLASH_OPTR_SRAM2_PE)      /*!< SRAM2 parity check disable */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type
00384   * @{
00385   */
00386 #define OB_SRAM2_RST_ERASE        ((uint32_t)0x0000000)                /*!< SRAM2 erased when a system reset occurs */
00387 #define OB_SRAM2_RST_NOT_ERASE    ((uint32_t)FLASH_OPTR_SRAM2_RST)     /*!< SRAM2 is not erased when a system reset occurs */
00388 /**
00389   * @}
00390   */
00391
00392 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00393 /** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
00394   * @{
00395   */
00396 #define OB_BOOT0_FROM_OB          ((uint32_t)0x0000000)                /*!< BOOT0 taken from the option bit nBOOT0 */
00397 #define OB_BOOT0_FROM_PIN         ((uint32_t)FLASH_OPTR_nSWBOOT0)      /*!< BOOT0 taken from PH3/BOOT0 pin */
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
00403   * @{
00404   */
00405 #define OB_BOOT0_RESET            ((uint32_t)0x0000000)                /*!< nBOOT0 = 0 */
00406 #define OB_BOOT0_SET              ((uint32_t)FLASH_OPTR_nBOOT0)        /*!< nBOOT0 = 1 */
00407 /**
00408   * @}
00409   */
00410 #endif
00411
00412 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
00413   * @{
00414   */
00415 #define OB_PCROP_RDP_NOT_ERASE    ((uint32_t)0x00000000)               /*!< PCROP area is not erased when the RDP level
00416                                                                             is decreased from Level 1 to Level 0 */
00417 #define OB_PCROP_RDP_ERASE        ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is
00418                                                                             decreased from Level 1 to Level 0 (full mass erase) */
00419 /**
00420   * @}
00421   */
00422
00423 /** @defgroup FLASH_Latency FLASH Latency
00424   * @{
00425   */
00426 #define FLASH_LATENCY_0           FLASH_ACR_LATENCY_0WS                /*!< FLASH Zero wait state */
00427 #define FLASH_LATENCY_1           FLASH_ACR_LATENCY_1WS                /*!< FLASH One wait state */
00428 #define FLASH_LATENCY_2           FLASH_ACR_LATENCY_2WS                /*!< FLASH Two wait states */
00429 #define FLASH_LATENCY_3           FLASH_ACR_LATENCY_3WS                /*!< FLASH Three wait states */
00430 #define FLASH_LATENCY_4           FLASH_ACR_LATENCY_4WS                /*!< FLASH Four wait states */
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup FLASH_Keys FLASH Keys
00436   * @{
00437   */
00438 #define FLASH_KEY1                ((uint32_t)0x45670123U)               /*!< Flash key1 */
00439 #define FLASH_KEY2                ((uint32_t)0xCDEF89ABU)               /*!< Flash key2: used with FLASH_KEY1
00440                                                                             to unlock the FLASH registers access */
00441
00442 #define FLASH_PDKEY1              ((uint32_t)0x04152637U)               /*!< Flash power down key1 */
00443 #define FLASH_PDKEY2              ((uint32_t)0xFAFBFCFDU)               /*!< Flash power down key2: used with FLASH_PDKEY1
00444                                                                             to unlock the RUN_PD bit in FLASH_ACR */
00445
00446 #define FLASH_OPTKEY1             ((uint32_t)0x08192A3BU)               /*!< Flash option byte key1 */
00447 #define FLASH_OPTKEY2             ((uint32_t)0x4C5D6E7FU)               /*!< Flash option byte key2: used with FLASH_OPTKEY1
00448                                                                             to allow option bytes operations */
00449 /**
00450   * @}
00451   */
00452
00453 /** @defgroup FLASH_Flags FLASH Flags Definition
00454   * @{
00455   */
00456 #define FLASH_FLAG_EOP            FLASH_SR_EOP                         /*!< FLASH End of operation flag */
00457 #define FLASH_FLAG_OPERR          FLASH_SR_OPERR                       /*!< FLASH Operation error flag */
00458 #define FLASH_FLAG_PROGERR        FLASH_SR_PROGERR                     /*!< FLASH Programming error flag */
00459 #define FLASH_FLAG_WRPERR         FLASH_SR_WRPERR                      /*!< FLASH Write protection error flag */
00460 #define FLASH_FLAG_PGAERR         FLASH_SR_PGAERR                      /*!< FLASH Programming alignment error flag */
00461 #define FLASH_FLAG_SIZERR         FLASH_SR_SIZERR                      /*!< FLASH Size error flag  */
00462 #define FLASH_FLAG_PGSERR         FLASH_SR_PGSERR                      /*!< FLASH Programming sequence error flag */
00463 #define FLASH_FLAG_MISERR         FLASH_SR_MISERR                      /*!< FLASH Fast programming data miss error flag */
00464 #define FLASH_FLAG_FASTERR        FLASH_SR_FASTERR                     /*!< FLASH Fast programming error flag */
00465 #define FLASH_FLAG_RDERR          FLASH_SR_RDERR                       /*!< FLASH PCROP read error flag */
00466 #define FLASH_FLAG_OPTVERR        FLASH_SR_OPTVERR                     /*!< FLASH Option validity error flag  */
00467 #define FLASH_FLAG_BSY            FLASH_SR_BSY                         /*!< FLASH Busy flag */
00468 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00469 #define FLASH_FLAG_PEMPTY         FLASH_SR_PEMPTY                      /*!< FLASH Program empty */
00470 #endif
00471 #define FLASH_FLAG_ECCC           FLASH_ECCR_ECCC                      /*!< FLASH ECC correction */
00472 #define FLASH_FLAG_ECCD           FLASH_ECCR_ECCD                      /*!< FLASH ECC detection */
00473
00474 #define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
00475                                    FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
00476                                    FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
00477                                    FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)
00478 /**
00479   * @}
00480   */
00481
00482 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
00483   * @brief FLASH Interrupt definition
00484   * @{
00485   */
00486 #define FLASH_IT_EOP              FLASH_CR_EOPIE                       /*!< End of FLASH Operation Interrupt source */
00487 #define FLASH_IT_OPERR            FLASH_CR_ERRIE                       /*!< Error Interrupt source */
00488 #define FLASH_IT_RDERR            FLASH_CR_RDERRIE                     /*!< PCROP Read Error Interrupt source*/
00489 #define FLASH_IT_ECCC             (FLASH_ECCR_ECCIE >> 24)             /*!< ECC Correction Interrupt source */
00490 /**
00491   * @}
00492   */
00493
00494 /**
00495   * @}
00496   */
00497
00498 /* Exported macros -----------------------------------------------------------*/
00499 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00500  *  @brief macros to control FLASH features
00501  *  @{
00502  */
00503
00504 /**
00505   * @brief  Set the FLASH Latency.
00506   * @param  __LATENCY__: FLASH Latency
00507   *         This parameter can be one of the following values :
00508   *     @arg FLASH_LATENCY_0: FLASH Zero wait state
00509   *     @arg FLASH_LATENCY_1: FLASH One wait state
00510   *     @arg FLASH_LATENCY_2: FLASH Two wait states
00511   *     @arg FLASH_LATENCY_3: FLASH Three wait states
00512   *     @arg FLASH_LATENCY_4: FLASH Four wait states
00513   * @retval None
00514   */
00515 #define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
00516
00517 /**
00518   * @brief  Get the FLASH Latency.
00519   * @retval FLASH Latency
00520   *         This parameter can be one of the following values :
00521   *     @arg FLASH_LATENCY_0: FLASH Zero wait state
00522   *     @arg FLASH_LATENCY_1: FLASH One wait state
00523   *     @arg FLASH_LATENCY_2: FLASH Two wait states
00524   *     @arg FLASH_LATENCY_3: FLASH Three wait states
00525   *     @arg FLASH_LATENCY_4: FLASH Four wait states
00526   */
00527 #define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
00528
00529 /**
00530   * @brief  Enable the FLASH prefetch buffer.
00531   * @retval None
00532   */
00533 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
00534
00535 /**
00536   * @brief  Disable the FLASH prefetch buffer.
00537   * @retval None
00538   */
00539 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
00540
00541 /**
00542   * @brief  Enable the FLASH instruction cache.
00543   * @retval none
00544   */
00545 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
00546
00547 /**
00548   * @brief  Disable the FLASH instruction cache.
00549   * @retval none
00550   */
00551 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
00552
00553 /**
00554   * @brief  Enable the FLASH data cache.
00555   * @retval none
00556   */
00557 #define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
00558
00559 /**
00560   * @brief  Disable the FLASH data cache.
00561   * @retval none
00562   */
00563 #define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
00564
00565 /**
00566   * @brief  Reset the FLASH instruction Cache.
00567   * @note   This function must be used only when the Instruction Cache is disabled.
00568   * @retval None
00569   */
00570 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
00571                                                      CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
00572                                                    } while (0)
00573
00574 /**
00575   * @brief  Reset the FLASH data Cache.
00576   * @note   This function must be used only when the data Cache is disabled.
00577   * @retval None
00578   */
00579 #define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
00580                                                      CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
00581                                                    } while (0)
00582
00583 /**
00584   * @brief  Enable the FLASH power down during Low-power run mode.
00585   * @note   Writing this bit  to 0 this bit, automatically the keys are
00586   *         loss and a new unlock sequence is necessary to re-write it to 1.
00587   */
00588 #define __HAL_FLASH_POWER_DOWN_ENABLE()         do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
00589                                                      WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
00590                                                      SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);   \
00591                                                    } while (0)
00592
00593 /**
00594   * @brief  Disable the FLASH power down during Low-power run mode.
00595   * @note   Writing this bit  to 0 this bit, automatically the keys are
00596   *         loss and a new unlock sequence is necessary to re-write it to 1.
00597   */
00598 #define __HAL_FLASH_POWER_DOWN_DISABLE()        do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
00599                                                      WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
00600                                                      CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
00601                                                    } while (0)
00602
00603 /**
00604   * @brief  Enable the FLASH power down during Low-Power sleep mode
00605   * @retval none
00606   */
00607 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
00608
00609 /**
00610   * @brief  Disable the FLASH power down during Low-Power sleep mode
00611   * @retval none
00612   */
00613 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
00614
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros
00620  *  @brief macros to handle FLASH interrupts
00621  * @{
00622  */
00623
00624 /**
00625   * @brief  Enable the specified FLASH interrupt.
00626   * @param  __INTERRUPT__: FLASH interrupt
00627   *         This parameter can be any combination of the following values:
00628   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
00629   *     @arg FLASH_IT_OPERR: Error Interrupt
00630   *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
00631   *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
00632   * @retval none
00633   */
00634 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
00635                                                      if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
00636                                                    } while(0)
00637
00638 /**
00639   * @brief  Disable the specified FLASH interrupt.
00640   * @param  __INTERRUPT__: FLASH interrupt
00641   *         This parameter can be any combination of the following values:
00642   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
00643   *     @arg FLASH_IT_OPERR: Error Interrupt
00644   *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
00645   *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
00646   * @retval none
00647   */
00648 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
00649                                                      if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
00650                                                    } while(0)
00651
00652 /**
00653   * @brief  Check whether the specified FLASH flag is set or not.
00654   * @param  __FLAG__: specifies the FLASH flag to check.
00655   *   This parameter can be one of the following values:
00656   *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
00657   *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
00658   *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
00659   *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
00660   *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
00661   *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
00662   *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
00663   *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
00664   *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
00665   *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
00666   *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
00667   *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
00668   *     @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
00669   *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
00670   *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
00671   * @retval The new state of FLASH_FLAG (SET or RESET).
00672   */
00673 #define __HAL_FLASH_GET_FLAG(__FLAG__)          (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \
00674                                                  (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))  : \
00675                                                  (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))
00676
00677 /**
00678   * @brief  Clear the FLASH's pending flags.
00679   * @param  __FLAG__: specifies the FLASH flags to clear.
00680   *   This parameter can be any combination of the following values:
00681   *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
00682   *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
00683   *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
00684   *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
00685   *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
00686   *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
00687   *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
00688   *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
00689   *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
00690   *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
00691   *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
00692   *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
00693   *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
00694   *     @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
00695   * @retval None
00696   */
00697 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
00698                                                      if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
00699                                                    } while(0)
00700 /**
00701   * @}
00702   */
00703
00704 /* Include FLASH HAL Extended module */
00705 #include "stm32l4xx_hal_flash_ex.h"
00706 #include "stm32l4xx_hal_flash_ramfunc.h"
00707
00708 /* Exported functions --------------------------------------------------------*/
00709 /** @addtogroup FLASH_Exported_Functions
00710   * @{
00711   */
00712
00713 /* Program operation functions  ***********************************************/
00714 /** @addtogroup FLASH_Exported_Functions_Group1
00715   * @{
00716   */
00717 HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00718 HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00719 /* FLASH IRQ handler method */
00720 void               HAL_FLASH_IRQHandler(void);
00721 /* Callbacks in non blocking modes */
00722 void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
00723 void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
00724 /**
00725   * @}
00726   */
00727
00728 /* Peripheral Control functions  **********************************************/
00729 /** @addtogroup FLASH_Exported_Functions_Group2
00730   * @{
00731   */
00732 HAL_StatusTypeDef  HAL_FLASH_Unlock(void);
00733 HAL_StatusTypeDef  HAL_FLASH_Lock(void);
00734 /* Option bytes control */
00735 HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);
00736 HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);
00737 HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);
00738 /**
00739   * @}
00740   */
00741
00742 /* Peripheral State functions  ************************************************/
00743 /** @addtogroup FLASH_Exported_Functions_Group3
00744   * @{
00745   */
00746 uint32_t HAL_FLASH_GetError(void);
00747 /**
00748   * @}
00749   */
00750
00751 /**
00752   * @}
00753   */
00754
00755 /* Private constants --------------------------------------------------------*/
00756 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00757   * @{
00758   */
00759 #define FLASH_SIZE_DATA_REGISTER           ((uint32_t)0x1FFF75E0)
00760
00761 #define FLASH_SIZE                         ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
00762                                             (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
00763
00764 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00765 #define FLASH_BANK_SIZE                    (FLASH_SIZE >> 1)
00766 #else
00767 #define FLASH_BANK_SIZE                    (FLASH_SIZE)
00768 #endif
00769
00770 #define FLASH_PAGE_SIZE                    ((uint32_t)0x800)
00771
00772 #define FLASH_TIMEOUT_VALUE                ((uint32_t)50000)/* 50 s */
00773 /**
00774   * @}
00775   */
00776
00777 /* Private macros ------------------------------------------------------------*/
00778 /** @defgroup FLASH_Private_Macros FLASH Private Macros
00779  *  @{
00780  */
00781
00782 #define IS_FLASH_TYPEERASE(VALUE)          (((VALUE) == FLASH_TYPEERASE_PAGES) || \
00783                                             ((VALUE) == FLASH_TYPEERASE_MASSERASE))
00784
00785 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00786 #define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
00787                                             ((BANK) == FLASH_BANK_2)  || \
00788                                             ((BANK) == FLASH_BANK_BOTH))
00789
00790 #define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
00791                                             ((BANK) == FLASH_BANK_2))
00792 #else
00793 #define IS_FLASH_BANK(BANK)                ((BANK) == FLASH_BANK_1)
00794
00795 #define IS_FLASH_BANK_EXCLUSIVE(BANK)      ((BANK) == FLASH_BANK_1)
00796 #endif
00797
00798 #define IS_FLASH_TYPEPROGRAM(VALUE)        (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
00799                                             ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
00800                                             ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
00801
00802 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE)        && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
00803                                             ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
00804                                             ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
00805                                             ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \
00806                                             ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF))))))
00807
00808 #define IS_FLASH_OTP_ADDRESS(ADDRESS)      (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
00809
00810 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
00811
00812 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00813 #define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
00814                                             ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
00815                                             ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
00816                                             ((PAGE) < 256)))))
00817 #else
00818 #define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
00819                                             ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80)  ? ((PAGE) < 64) : \
00820                                             ((PAGE) < 128))))
00821 #endif
00822
00823 #define IS_OPTIONBYTE(VALUE)               (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
00824
00825 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00826 #define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
00827                                             ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
00828 #else
00829 #define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
00830 #endif
00831
00832 #define IS_OB_RDP_LEVEL(LEVEL)             (((LEVEL) == OB_RDP_LEVEL_0)   ||\
00833                                             ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
00834                                             ((LEVEL) == OB_RDP_LEVEL_2)*/)
00835
00836 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00837 #define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
00838 #else
00839 #define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0))
00840 #endif
00841
00842 #define IS_OB_USER_BOR_LEVEL(LEVEL)        (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
00843                                             ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
00844                                             ((LEVEL) == OB_BOR_LEVEL_4))
00845
00846 #define IS_OB_USER_STOP(VALUE)             (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
00847
00848 #define IS_OB_USER_STANDBY(VALUE)          (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
00849
00850 #define IS_OB_USER_SHUTDOWN(VALUE)         (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
00851
00852 #define IS_OB_USER_IWDG(VALUE)             (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
00853
00854 #define IS_OB_USER_IWDG_STOP(VALUE)        (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
00855
00856 #define IS_OB_USER_IWDG_STDBY(VALUE)       (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
00857
00858 #define IS_OB_USER_WWDG(VALUE)             (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
00859
00860 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00861 #define IS_OB_USER_BFB2(VALUE)             (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
00862
00863 #define IS_OB_USER_DUALBANK(VALUE)         (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
00864 #endif
00865
00866 #define IS_OB_USER_BOOT1(VALUE)            (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
00867
00868 #define IS_OB_USER_SRAM2_PARITY(VALUE)     (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
00869
00870 #define IS_OB_USER_SRAM2_RST(VALUE)        (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
00871
00872 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00873 #define IS_OB_USER_SWBOOT0(VALUE)          (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
00874
00875 #define IS_OB_USER_BOOT0(VALUE)            (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET))
00876 #endif
00877
00878 #define IS_OB_PCROP_RDP(VALUE)             (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
00879
00880 #define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || \
00881                                             ((LATENCY) == FLASH_LATENCY_1) || \
00882                                             ((LATENCY) == FLASH_LATENCY_2) || \
00883                                             ((LATENCY) == FLASH_LATENCY_3) || \
00884                                             ((LATENCY) == FLASH_LATENCY_4))
00885 /**
00886   * @}
00887   */
00888
00889 /**
00890   * @}
00891   */
00892
00893 /**
00894   * @}
00895   */
00896
00897 #ifdef __cplusplus
00898 }
00899 #endif
00900
00901 #endif /* __STM32L4xx_HAL_FLASH_H */
00902
00903 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash_ex.c Source File

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stm32l4xx_hal_flash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_flash_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Extended FLASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the FLASH extended peripheral:
00010   *           + Extended programming operations functions
00011   *
00012  @verbatim
00013  ==============================================================================
00014                    ##### Flash Extended features #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the FLASH interface for STM32L4xx
00018        devices contains the following additional features
00019
00020        (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
00021            capability (RWW)
00022        (+) Dual bank memory organization
00023        (+) PCROP protection for all banks
00024
00025                         ##### How to use this driver #####
00026  ==============================================================================
00027   [..] This driver provides functions to configure and program the FLASH memory
00028        of all STM32L4xx devices. It includes
00029       (#) Flash Memory Erase functions:
00030            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00031                 HAL_FLASH_Lock() functions
00032            (++) Erase function: Erase page, erase all sectors
00033            (++) There are two modes of erase :
00034              (+++) Polling Mode using HAL_FLASHEx_Erase()
00035              (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
00036
00037       (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
00038         (++) Set/Reset the write protection
00039         (++) Set the Read protection Level
00040         (++) Program the user Option Bytes
00041         (++) Configure the PCROP protection
00042
00043       (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
00044         (++) Get the value of a write protection area
00045         (++) Know if the read protection is activated
00046         (++) Get the value of the user Option Bytes
00047         (++) Get the value of a PCROP area
00048
00049  @endverbatim
00050   ******************************************************************************
00051   * @attention
00052   *
00053   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00054   *
00055   * Redistribution and use in source and binary forms, with or without modification,
00056   * are permitted provided that the following conditions are met:
00057   *   1. Redistributions of source code must retain the above copyright notice,
00058   *      this list of conditions and the following disclaimer.
00059   *   2. Redistributions in binary form must reproduce the above copyright notice,
00060   *      this list of conditions and the following disclaimer in the documentation
00061   *      and/or other materials provided with the distribution.
00062   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00063   *      may be used to endorse or promote products derived from this software
00064   *      without specific prior written permission.
00065   *
00066   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00067   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00068   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00069   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00070   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00071   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00072   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00073   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00074   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00075   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00076   *
00077   ******************************************************************************
00078   */
00079
00080 /* Includes ------------------------------------------------------------------*/
00081 #include "stm32l4xx_hal.h"
00082
00083 /** @addtogroup STM32L4xx_HAL_Driver
00084   * @{
00085   */
00086
00087 /** @defgroup FLASHEx FLASHEx
00088   * @brief FALSH Extended HAL module driver
00089   * @{
00090   */
00091
00092 #ifdef HAL_FLASH_MODULE_ENABLED
00093
00094 /* Private typedef -----------------------------------------------------------*/
00095 /* Private define ------------------------------------------------------------*/
00096 /* Private macro -------------------------------------------------------------*/
00097 /* Private variables ---------------------------------------------------------*/
00098 /** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables
00099  * @{
00100  */
00101 extern FLASH_ProcessTypeDef pFlash;
00102 /**
00103   * @}
00104   */
00105
00106 /* Private function prototypes -----------------------------------------------*/
00107 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
00108  * @{
00109  */
00110 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
00111 void                     FLASH_PageErase(uint32_t Page, uint32_t Banks);
00112 static void              FLASH_MassErase(uint32_t Banks);
00113 void                     FLASH_FlushCaches(void);
00114 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
00115 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
00116 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
00117 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
00118 static void              FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);
00119 static uint32_t          FLASH_OB_GetRDP(void);
00120 static uint32_t          FLASH_OB_GetUser(void);
00121 static void              FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported functions -------------------------------------------------------*/
00127 /** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
00128   * @{
00129   */
00130
00131 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
00132  *  @brief   Extended IO operation functions
00133  *
00134 @verbatim
00135  ===============================================================================
00136                 ##### Extended programming operation functions #####
00137  ===============================================================================
00138     [..]
00139     This subsection provides a set of functions allowing to manage the Extended FLASH
00140     programming operations Operations.
00141
00142 @endverbatim
00143   * @{
00144   */
00145 /**
00146   * @brief  Perform a mass erase or erase the specified FLASH memory pages.
00147   * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
00148   *         contains the configuration information for the erasing.
00149   *
00150   * @param[out]  PageError  : pointer to variable that contains the configuration
00151   *         information on faulty page in case of error (0xFFFFFFFF means that all
00152   *         the pages have been correctly erased)
00153   *
00154   * @retval HAL Status
00155   */
00156 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
00157 {
00158   HAL_StatusTypeDef status = HAL_ERROR;
00159   uint32_t page_index = 0;
00160
00161   /* Process Locked */
00162   __HAL_LOCK(&pFlash);
00163
00164   /* Check the parameters */
00165   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00166
00167   /* Wait for last operation to be completed */
00168   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00169
00170   if (status == HAL_OK)
00171   {
00172     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00173
00174     if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00175     {
00176       /* Mass erase to be done */
00177       FLASH_MassErase(pEraseInit->Banks);
00178
00179       /* Wait for last operation to be completed */
00180       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00181
00182 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00183       /* If the erase operation is completed, disable the MER1 and MER2 Bits */
00184       CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
00185 #else
00186       /* If the erase operation is completed, disable the MER1 Bit */
00187       CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
00188 #endif
00189     }
00190     else
00191     {
00192       /*Initialization of PageError variable*/
00193       *PageError = 0xFFFFFFFF;
00194
00195       for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
00196       {
00197         FLASH_PageErase(page_index, pEraseInit->Banks);
00198
00199         /* Wait for last operation to be completed */
00200         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00201
00202         /* If the erase operation is completed, disable the PER Bit */
00203         CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
00204
00205         if (status != HAL_OK)
00206         {
00207           /* In case of error, stop erase procedure and return the faulty address */
00208           *PageError = page_index;
00209           break;
00210         }
00211       }
00212     }
00213
00214     /* Flush the caches to be sure of the data consistency */
00215     FLASH_FlushCaches();
00216   }
00217
00218   /* Process Unlocked */
00219   __HAL_UNLOCK(&pFlash);
00220
00221   return status;
00222 }
00223
00224 /**
00225   * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
00226   * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
00227   *         contains the configuration information for the erasing.
00228   *
00229   * @retval HAL Status
00230   */
00231 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
00232 {
00233   HAL_StatusTypeDef status = HAL_OK;
00234
00235   /* Process Locked */
00236   __HAL_LOCK(&pFlash);
00237
00238   /* Check the parameters */
00239   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00240
00241   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00242
00243   /* Enable End of Operation and Error interrupts */
00244   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
00245
00246   pFlash.Bank = pEraseInit->Banks;
00247
00248   if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00249   {
00250     /* Mass erase to be done */
00251     pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
00252     FLASH_MassErase(pEraseInit->Banks);
00253   }
00254   else
00255   {
00256     /* Erase by page to be done */
00257     pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
00258     pFlash.NbPagesToErase = pEraseInit->NbPages;
00259     pFlash.Page = pEraseInit->Page;
00260
00261     /*Erase 1st page and wait for IT */
00262     FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
00263   }
00264
00265   return status;
00266 }
00267
00268 /**
00269   * @brief  Program Option bytes.
00270   * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
00271   *         contains the configuration information for the programming.
00272   *
00273   * @retval HAL Status
00274   */
00275 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
00276 {
00277   HAL_StatusTypeDef status = HAL_ERROR;
00278
00279   /* Process Locked */
00280   __HAL_LOCK(&pFlash);
00281
00282   /* Check the parameters */
00283   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
00284
00285   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00286
00287   /* Write protection configuration */
00288   if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET)
00289   {
00290     /* Configure of Write protection on the selected area */
00291     status = FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
00292   }
00293
00294   /* Read protection configuration */
00295   if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET)
00296   {
00297     /* Configure the Read protection level */
00298     status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
00299   }
00300
00301   /* User Configuration */
00302   if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET)
00303   {
00304     /* Configure the user option bytes */
00305     status = FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
00306   }
00307
00308   /* PCROP Configuration */
00309   if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET)
00310   {
00311     /* Configure the Proprietary code readout protection */
00312     status = FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr);
00313   }
00314
00315   /* Process Unlocked */
00316   __HAL_UNLOCK(&pFlash);
00317
00318   return status;
00319 }
00320
00321 /**
00322   * @brief  Get the Option bytes configuration.
00323   * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that contains the
00324   *                  configuration information. The fields pOBInit->WRPArea and
00325   *                  pOBInit->PCROPConfig should indicate which area is requested
00326   *                  for the WRP and PCROP
00327   *
00328   * @retval None
00329   */
00330 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
00331 {
00332   pOBInit->OptionType = (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP);
00333
00334   /* Get write protection on the selected area */
00335   FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
00336
00337   /* Get Read protection level */
00338   pOBInit->RDPLevel = FLASH_OB_GetRDP();
00339
00340   /* Get the user option bytes */
00341   pOBInit->USERConfig = FLASH_OB_GetUser();
00342
00343   /* Get the Proprietary code readout protection */
00344   FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
00345
00346 }
00347
00348 /**
00349   * @}
00350   */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /* Private functions ---------------------------------------------------------*/
00357
00358 /** @addtogroup FLASHEx_Private_Functions
00359   * @{
00360   */
00361 /**
00362   * @brief  Mass erase of FLASH memory.
00363   * @param  Banks: Banks to be erased
00364   *          This parameter can be one of the following values:
00365   *            @arg FLASH_BANK_1: Bank1 to be erased
00366   *            @arg FLASH_BANK_2: Bank2 to be erased
00367   *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
00368   * @retval None
00369   */
00370 static void FLASH_MassErase(uint32_t Banks)
00371 {
00372   /* Check the parameters */
00373   assert_param(IS_FLASH_BANK(Banks));
00374
00375   /* Set the Mass Erase Bit for the bank 1 if requested */
00376   if((Banks & FLASH_BANK_1) != RESET)
00377   {
00378     SET_BIT(FLASH->CR, FLASH_CR_MER1);
00379   }
00380
00381 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00382   /* Set the Mass Erase Bit for the bank 2 if requested */
00383   if((Banks & FLASH_BANK_2) != RESET)
00384   {
00385     SET_BIT(FLASH->CR, FLASH_CR_MER2);
00386   }
00387 #endif
00388
00389   /* Proceed to erase all sectors */
00390   SET_BIT(FLASH->CR, FLASH_CR_STRT);
00391 }
00392
00393 /**
00394   * @brief  Erase the specified FLASH memory page.
00395   * @param  Page: FLASH page to erase
00396   *         This parameter must be a value between 0 and (max number of pages in the bank - 1)
00397   * @param  Banks: Bank(s) where the page will be erased
00398   *          This parameter can be one or a combination of the following values:
00399   *            @arg FLASH_BANK_1: Page in bank 1 to be erased
00400   *            @arg FLASH_BANK_2: Page in bank 2 to be erased
00401   * @retval None
00402   */
00403 void FLASH_PageErase(uint32_t Page, uint32_t Banks)
00404 {
00405   /* Check the parameters */
00406   assert_param(IS_FLASH_PAGE(Page));
00407   assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
00408
00409 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00410   if((Banks & FLASH_BANK_1) != RESET)
00411   {
00412     CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
00413   }
00414   else
00415   {
00416     SET_BIT(FLASH->CR, FLASH_CR_BKER);
00417   }
00418 #endif
00419
00420   /* Proceed to erase the page */
00421   MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << 3));
00422   SET_BIT(FLASH->CR, FLASH_CR_PER);
00423   SET_BIT(FLASH->CR, FLASH_CR_STRT);
00424 }
00425
00426 /**
00427   * @brief  Flush the instruction and data caches.
00428   * @retval None
00429   */
00430 void FLASH_FlushCaches(void)
00431 {
00432   /* Flush instruction cache  */
00433   if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
00434   {
00435     /* Disable instruction cache  */
00436     __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
00437     /* Reset instruction cache */
00438     __HAL_FLASH_INSTRUCTION_CACHE_RESET();
00439     /* Enable instruction cache */
00440     __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
00441   }
00442
00443   /* Flush data cache */
00444   if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
00445   {
00446     /* Disable data cache  */
00447     __HAL_FLASH_DATA_CACHE_DISABLE();
00448     /* Reset data cache */
00449     __HAL_FLASH_DATA_CACHE_RESET();
00450     /* Enable data cache */
00451     __HAL_FLASH_DATA_CACHE_ENABLE();
00452   }
00453 }
00454
00455 /**
00456   * @brief  Configure the write protection of the desired pages.
00457   *
00458   * @note   When the memory read protection level is selected (RDP level = 1),
00459   *         it is not possible to program or erase Flash memory if the CPU debug
00460   *         features are connected (JTAG or single wire) or boot code is being
00461   *         executed from RAM or System flash, even if WRP is not activated.
00462   * @note   To configure the WRP options, the option lock bit OPTLOCK must be
00463   *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
00464   * @note   To validate the WRP options, the option bytes must be reloaded
00465   *         through the call of the HAL_FLASH_OB_Launch() function.
00466   *
00467   * @param  WRPArea: specifies the area to be configured.
00468   *          This parameter can be one of the following values:
00469   *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
00470   *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
00471   *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A  (don't apply for STM32L43x/STM32L44x devices)
00472   *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B  (don't apply for STM32L43x/STM32L44x devices)
00473   *
00474   * @param  WRPStartOffset: specifies the start page of the write protected area
00475   *          This parameter can be page number between 0 and (max number of pages in the bank - 1)
00476   *
00477   * @param  WRDPEndOffset: specifies the end page of the write protected area
00478   *          This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
00479   *
00480   * @retval HAL Status
00481   */
00482 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
00483 {
00484   HAL_StatusTypeDef status = HAL_OK;
00485
00486   /* Check the parameters */
00487   assert_param(IS_OB_WRPAREA(WRPArea));
00488   assert_param(IS_FLASH_PAGE(WRPStartOffset));
00489   assert_param(IS_FLASH_PAGE(WRDPEndOffset));
00490
00491   /* Wait for last operation to be completed */
00492   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00493
00494   if(status == HAL_OK)
00495   {
00496     /* Configure the write protected area */
00497     if(WRPArea == OB_WRPAREA_BANK1_AREAA)
00498     {
00499       MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),
00500                  (WRPStartOffset | (WRDPEndOffset << 16)));
00501     }
00502     else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
00503     {
00504       MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
00505                  (WRPStartOffset | (WRDPEndOffset << 16)));
00506     }
00507 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00508     else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
00509     {
00510       MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),
00511                  (WRPStartOffset | (WRDPEndOffset << 16)));
00512     }
00513     else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
00514     {
00515       MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END),
00516                  (WRPStartOffset | (WRDPEndOffset << 16)));
00517     }
00518 #endif
00519
00520     /* Set OPTSTRT Bit */
00521     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00522
00523     /* Wait for last operation to be completed */
00524     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00525
00526     /* If the option byte program operation is completed, disable the OPTSTRT Bit */
00527     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00528   }
00529
00530   return status;
00531 }
00532
00533 /**
00534   * @brief  Set the read protection level.
00535   *
00536   * @note   To configure the RDP level, the option lock bit OPTLOCK must be
00537   *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
00538   * @note   To validate the RDP level, the option bytes must be reloaded
00539   *         through the call of the HAL_FLASH_OB_Launch() function.
00540   * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
00541   *         to go back to level 1 or 0 !!!
00542   *
00543   * @param  RDPLevel: specifies the read protection level.
00544   *         This parameter can be one of the following values:
00545   *            @arg OB_RDP_LEVEL_0: No protection
00546   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
00547   *            @arg OB_RDP_LEVEL_2: Full chip protection
00548   *
00549   * @retval HAL status
00550   */
00551 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
00552 {
00553   HAL_StatusTypeDef status = HAL_OK;
00554
00555   /* Check the parameters */
00556   assert_param(IS_OB_RDP_LEVEL(RDPLevel));
00557
00558   /* Wait for last operation to be completed */
00559   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00560
00561   if(status == HAL_OK)
00562   {
00563     /* Configure the RDP level in the option bytes register */
00564     MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
00565
00566     /* Set OPTSTRT Bit */
00567     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00568
00569     /* Wait for last operation to be completed */
00570     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00571
00572     /* If the option byte program operation is completed, disable the OPTSTRT Bit */
00573     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00574   }
00575
00576   return status;
00577 }
00578
00579 /**
00580   * @brief  Program the FLASH User Option Byte.
00581   *
00582   * @note   To configure the user option bytes, the option lock bit OPTLOCK must
00583   *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
00584   * @note   To validate the user option bytes, the option bytes must be reloaded
00585   *         through the call of the HAL_FLASH_OB_Launch() function.
00586   *
00587   * @param  UserType: The FLASH User Option Bytes to be modified
00588   * @param  UserConfig: The FLASH User Option Bytes values:
00589   *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),
00590   *         IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20),
00591   *         DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
00592   *
00593   * @retval HAL status
00594   */
00595 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
00596 {
00597   uint32_t optr_reg_val = 0;
00598   uint32_t optr_reg_mask = 0;
00599   HAL_StatusTypeDef status = HAL_OK;
00600
00601   /* Check the parameters */
00602   assert_param(IS_OB_USER_TYPE(UserType));
00603
00604   /* Wait for last operation to be completed */
00605   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00606
00607   if(status == HAL_OK)
00608   {
00609     if((UserType & OB_USER_BOR_LEV) != RESET)
00610     {
00611       /* BOR level option byte should be modified */
00612       assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
00613
00614       /* Set value and mask for BOR level option byte */
00615       optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
00616       optr_reg_mask |= FLASH_OPTR_BOR_LEV;
00617     }
00618
00619     if((UserType & OB_USER_nRST_STOP) != RESET)
00620     {
00621       /* nRST_STOP option byte should be modified */
00622       assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
00623
00624       /* Set value and mask for nRST_STOP option byte */
00625       optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
00626       optr_reg_mask |= FLASH_OPTR_nRST_STOP;
00627     }
00628
00629     if((UserType & OB_USER_nRST_STDBY) != RESET)
00630     {
00631       /* nRST_STDBY option byte should be modified */
00632       assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
00633
00634       /* Set value and mask for nRST_STDBY option byte */
00635       optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
00636       optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
00637     }
00638
00639     if((UserType & OB_USER_nRST_SHDW) != RESET)
00640     {
00641       /* nRST_SHDW option byte should be modified */
00642       assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
00643
00644       /* Set value and mask for nRST_SHDW option byte */
00645       optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
00646       optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
00647     }
00648
00649     if((UserType & OB_USER_IWDG_SW) != RESET)
00650     {
00651       /* IWDG_SW option byte should be modified */
00652       assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
00653
00654       /* Set value and mask for IWDG_SW option byte */
00655       optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
00656       optr_reg_mask |= FLASH_OPTR_IWDG_SW;
00657     }
00658
00659     if((UserType & OB_USER_IWDG_STOP) != RESET)
00660     {
00661       /* IWDG_STOP option byte should be modified */
00662       assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
00663
00664       /* Set value and mask for IWDG_STOP option byte */
00665       optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
00666       optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
00667     }
00668
00669     if((UserType & OB_USER_IWDG_STDBY) != RESET)
00670     {
00671       /* IWDG_STDBY option byte should be modified */
00672       assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
00673
00674       /* Set value and mask for IWDG_STDBY option byte */
00675       optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
00676       optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
00677     }
00678
00679     if((UserType & OB_USER_WWDG_SW) != RESET)
00680     {
00681       /* WWDG_SW option byte should be modified */
00682       assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
00683
00684       /* Set value and mask for WWDG_SW option byte */
00685       optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
00686       optr_reg_mask |= FLASH_OPTR_WWDG_SW;
00687     }
00688
00689 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00690     if((UserType & OB_USER_BFB2) != RESET)
00691     {
00692       /* BFB2 option byte should be modified */
00693       assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
00694
00695       /* Set value and mask for BFB2 option byte */
00696       optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
00697       optr_reg_mask |= FLASH_OPTR_BFB2;
00698     }
00699
00700     if((UserType & OB_USER_DUALBANK) != RESET)
00701     {
00702       /* DUALBANK option byte should be modified */
00703       assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
00704
00705       /* Set value and mask for DUALBANK option byte */
00706       optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
00707       optr_reg_mask |= FLASH_OPTR_DUALBANK;
00708     }
00709 #endif
00710
00711     if((UserType & OB_USER_nBOOT1) != RESET)
00712     {
00713       /* nBOOT1 option byte should be modified */
00714       assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
00715
00716       /* Set value and mask for nBOOT1 option byte */
00717       optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
00718       optr_reg_mask |= FLASH_OPTR_nBOOT1;
00719     }
00720
00721     if((UserType & OB_USER_SRAM2_PE) != RESET)
00722     {
00723       /* SRAM2_PE option byte should be modified */
00724       assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));
00725
00726       /* Set value and mask for SRAM2_PE option byte */
00727       optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);
00728       optr_reg_mask |= FLASH_OPTR_SRAM2_PE;
00729     }
00730
00731     if((UserType & OB_USER_SRAM2_RST) != RESET)
00732     {
00733       /* SRAM2_RST option byte should be modified */
00734       assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
00735
00736       /* Set value and mask for SRAM2_RST option byte */
00737       optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
00738       optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
00739     }
00740
00741 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00742     if((UserType & OB_USER_nSWBOOT0) != RESET)
00743     {
00744       /* nSWBOOT0 option byte should be modified */
00745       assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
00746
00747       /* Set value and mask for nSWBOOT0 option byte */
00748       optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
00749       optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
00750     }
00751
00752     if((UserType & OB_USER_nBOOT0) != RESET)
00753     {
00754       /* nBOOT0 option byte should be modified */
00755       assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
00756
00757       /* Set value and mask for nBOOT0 option byte */
00758       optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
00759       optr_reg_mask |= FLASH_OPTR_nBOOT0;
00760     }
00761 #endif
00762
00763     /* Configure the option bytes register */
00764     MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
00765
00766     /* Set OPTSTRT Bit */
00767     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00768
00769     /* Wait for last operation to be completed */
00770     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00771
00772     /* If the option byte program operation is completed, disable the OPTSTRT Bit */
00773     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00774   }
00775
00776   return status;
00777 }
00778
00779 /**
00780   * @brief  Configure the Proprietary code readout protection of the desired addresses.
00781   *
00782   * @note   To configure the PCROP options, the option lock bit OPTLOCK must be
00783   *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
00784   * @note   To validate the PCROP options, the option bytes must be reloaded
00785   *         through the call of the HAL_FLASH_OB_Launch() function.
00786   *
00787   * @param  PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option).
00788   *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
00789   *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
00790   *
00791   * @param  PCROPStartAddr: specifies the start address of the Proprietary code readout protection
00792   *          This parameter can be an address between begin and end of the bank
00793   *
00794   * @param  PCROPEndAddr: specifies the end address of the Proprietary code readout protection
00795   *          This parameter can be an address between PCROPStartAddr and end of the bank
00796   *
00797   * @retval HAL Status
00798   */
00799 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
00800 {
00801   HAL_StatusTypeDef status = HAL_OK;
00802   uint32_t reg_value = 0;
00803   uint32_t bank1_addr;
00804 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00805   uint32_t bank2_addr;
00806 #endif
00807
00808   /* Check the parameters */
00809   assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
00810   assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
00811   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
00812   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
00813
00814   /* Wait for last operation to be completed */
00815   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00816
00817   if(status == HAL_OK)
00818   {
00819 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00820     /* Get the information about the bank swapping */
00821     if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
00822     {
00823       bank1_addr = FLASH_BASE;
00824       bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
00825     }
00826     else
00827     {
00828       bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
00829       bank2_addr = FLASH_BASE;
00830     }
00831 #else
00832     bank1_addr = FLASH_BASE;
00833 #endif
00834
00835     /* Configure the Proprietary code readout protection */
00836     if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
00837     {
00838       reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
00839       MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
00840
00841       reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
00842       MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
00843     }
00844 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00845     else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
00846     {
00847       reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
00848       MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
00849
00850       reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
00851       MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
00852     }
00853 #endif
00854
00855     MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
00856
00857     /* Set OPTSTRT Bit */
00858     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00859
00860     /* Wait for last operation to be completed */
00861     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00862
00863     /* If the option byte program operation is completed, disable the OPTSTRT Bit */
00864     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
00865   }
00866
00867   return status;
00868 }
00869
00870 /**
00871   * @brief  Return the FLASH Write Protection Option Bytes value.
00872   *
00873   * @param[in]  WRPArea: specifies the area to be returned.
00874   *          This parameter can be one of the following values:
00875   *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
00876   *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
00877   *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices)
00878   *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices)
00879   *
00880   * @param[out]  WRPStartOffset: specifies the address where to copied the start page
00881   *                         of the write protected area
00882   *
00883   * @param[out]  WRDPEndOffset: specifies the address where to copied the end page of
00884   *                        the write protected area
00885   *
00886   * @retval None
00887   */
00888 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)
00889 {
00890   /* Check the parameters */
00891   assert_param(IS_OB_WRPAREA(WRPArea));
00892
00893   /* Get the configuration of the write protected area */
00894   if(WRPArea == OB_WRPAREA_BANK1_AREAA)
00895   {
00896     *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
00897     *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);
00898   }
00899   else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
00900   {
00901     *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
00902     *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);
00903   }
00904 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00905   else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
00906   {
00907     *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
00908     *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);
00909   }
00910   else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
00911   {
00912     *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
00913     *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);
00914   }
00915 #endif
00916 }
00917
00918 /**
00919   * @brief  Return the FLASH Read Protection level.
00920   * @retval FLASH ReadOut Protection Status:
00921   *         This return value can be one of the following values:
00922   *            @arg OB_RDP_LEVEL_0: No protection
00923   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
00924   *            @arg OB_RDP_LEVEL_2: Full chip protection
00925   */
00926 static uint32_t FLASH_OB_GetRDP(void)
00927 {
00928   if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) &&
00929       (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2))
00930   {
00931     return (OB_RDP_LEVEL_1);
00932   }
00933   else
00934   {
00935     return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));
00936   }
00937 }
00938
00939 /**
00940   * @brief  Return the FLASH User Option Byte value.
00941   * @retval The FLASH User Option Bytes values:
00942   *      For STM32L47x/STM32L48x devices :
00943   *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
00944   *         IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
00945   *         BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
00946   *      For STM32L43x/STM32L44x devices :
00947   *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
00948   *         IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
00949   *         nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27).
00950   */
00951 static uint32_t FLASH_OB_GetUser(void)
00952 {
00953   uint32_t user_config = READ_REG(FLASH->OPTR);
00954   CLEAR_BIT(user_config, FLASH_OPTR_RDP);
00955
00956   return user_config;
00957 }
00958
00959 /**
00960   * @brief  Return the FLASH Write Protection Option Bytes value.
00961   *
00962   * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).
00963   *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
00964   *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
00965   *
00966   * @param PCROPStartAddr [out]: specifies the address where to copied the start address
00967   *                         of the Proprietary code readout protection
00968   *
00969   * @param PCROPEndAddr [out]: specifies the address where to copied the end address of
00970   *                       the Proprietary code readout protection
00971   *
00972   * @retval None
00973   */
00974 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)
00975 {
00976   uint32_t reg_value = 0;
00977   uint32_t bank1_addr;
00978 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00979   uint32_t bank2_addr;
00980 #endif
00981
00982   /* Check the parameters */
00983   assert_param(IS_FLASH_BANK_EXCLUSIVE((*PCROPConfig) & FLASH_BANK_BOTH));
00984
00985 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00986   /* Get the information about the bank swapping */
00987   if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
00988   {
00989     bank1_addr = FLASH_BASE;
00990     bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
00991   }
00992   else
00993   {
00994     bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
00995     bank2_addr = FLASH_BASE;
00996   }
00997 #else
00998   bank1_addr = FLASH_BASE;
00999 #endif
01000
01001   if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
01002   {
01003     reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
01004     *PCROPStartAddr = (reg_value << 3) + bank1_addr;
01005
01006     reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
01007     *PCROPEndAddr = (reg_value << 3) + bank1_addr;
01008   }
01009 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
01010   else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
01011   {
01012     reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
01013     *PCROPStartAddr = (reg_value << 3) + bank2_addr;
01014
01015     reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
01016     *PCROPEndAddr = (reg_value << 3) + bank2_addr;
01017   }
01018 #endif
01019
01020   *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
01021 }
01022 /**
01023   * @}
01024   */
01025
01026 /**
01027   * @}
01028   */
01029
01030 #endif /* HAL_FLASH_MODULE_ENABLED */
01031
01032 /**
01033   * @}
01034   */
01035
01036 /**
01037   * @}
01038   */
01039
01040 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash_ex.h Source File

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stm32l4xx_hal_flash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_flash_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of FLASH HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_FLASH_EX_H
00040 #define __STM32L4xx_HAL_FLASH_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASHEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /* Exported constants --------------------------------------------------------*/
00060
00061 /* Exported macro ------------------------------------------------------------*/
00062
00063 /* Exported functions --------------------------------------------------------*/
00064 /** @addtogroup FLASHEx_Exported_Functions
00065   * @{
00066   */
00067
00068 /* Extended Program operation functions  *************************************/
00069 /** @addtogroup FLASHEx_Exported_Functions_Group1
00070   * @{
00071   */
00072 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
00073 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
00074 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
00075 void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
00076 /**
00077   * @}
00078   */
00079
00080 /**
00081   * @}
00082   */
00083
00084 /**
00085   * @}
00086   */
00087
00088 /**
00089   * @}
00090   */
00091
00092 #ifdef __cplusplus
00093 }
00094 #endif
00095
00096 #endif /* __STM32L4xx_HAL_FLASH_EX_H */
00097
00098 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash_ramfunc.c Source File

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stm32l4xx_hal_flash_ramfunc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_flash_ramfunc.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   FLASH RAMFUNC driver.
00008   *          This file provides a Flash firmware functions which should be
00009   *          executed from internal SRAM
00010   *            + FLASH HalfPage Programming
00011   *            + FLASH Power Down in Run mode
00012   *
00013   *  @verbatim
00014   ==============================================================================
00015                    ##### Flash RAM functions #####
00016   ==============================================================================
00017
00018     *** ARM Compiler ***
00019     --------------------
00020     [..] RAM functions are defined using the toolchain options.
00021          Functions that are executed in RAM should reside in a separate
00022          source module. Using the 'Options for File' dialog you can simply change
00023          the 'Code / Const' area of a module to a memory space in physical RAM.
00024          Available memory areas are declared in the 'Target' tab of the
00025          Options for Target' dialog.
00026
00027     *** ICCARM Compiler ***
00028     -----------------------
00029     [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
00030
00031     *** GNU Compiler ***
00032     --------------------
00033     [..] RAM functions are defined using a specific toolchain attribute
00034          "__attribute__((section(".RamFunc")))".
00035
00036   @endverbatim
00037   ******************************************************************************
00038   * @attention
00039   *
00040   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00041   *
00042   * Redistribution and use in source and binary forms, with or without modification,
00043   * are permitted provided that the following conditions are met:
00044   *   1. Redistributions of source code must retain the above copyright notice,
00045   *      this list of conditions and the following disclaimer.
00046   *   2. Redistributions in binary form must reproduce the above copyright notice,
00047   *      this list of conditions and the following disclaimer in the documentation
00048   *      and/or other materials provided with the distribution.
00049   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00050   *      may be used to endorse or promote products derived from this software
00051   *      without specific prior written permission.
00052   *
00053   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00054   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00055   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00056   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00057   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00058   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00059   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00060   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00061   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00062   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00063   *
00064   ******************************************************************************
00065   */
00066
00067 /* Includes ------------------------------------------------------------------*/
00068 #include "stm32l4xx_hal.h"
00069
00070 /** @addtogroup STM32L4xx_HAL_Driver
00071   * @{
00072   */
00073
00074 /** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
00075   * @brief FLASH functions executed from RAM
00076   * @{
00077   */
00078
00079 #ifdef HAL_FLASH_MODULE_ENABLED
00080
00081 /* Private typedef -----------------------------------------------------------*/
00082 /* Private define ------------------------------------------------------------*/
00083 /* Private macro -------------------------------------------------------------*/
00084 /* Private variables ---------------------------------------------------------*/
00085 /* Private function prototypes -----------------------------------------------*/
00086 /* Exported functions -------------------------------------------------------*/
00087
00088 /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions
00089   * @{
00090   */
00091
00092 /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
00093  *  @brief   Data transfers functions
00094  *
00095 @verbatim
00096  ===============================================================================
00097                       ##### ramfunc functions #####
00098  ===============================================================================
00099     [..]
00100     This subsection provides a set of functions that should be executed from RAM.
00101
00102 @endverbatim
00103   * @{
00104   */
00105
00106 /**
00107   * @brief   Enable the Power down in Run Mode
00108   * @note    This function should be called and executed from SRAM memory
00109   * @retval None
00110   */
00111 __RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
00112 {
00113   /* Enable the Power Down in Run mode*/
00114   __HAL_FLASH_POWER_DOWN_ENABLE();
00115
00116   return HAL_OK;
00117
00118 }
00119
00120 /**
00121   * @brief   Disable the Power down in Run Mode
00122   * @note    This function should be called and executed from SRAM memory
00123   * @retval None
00124   */
00125 __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
00126 {
00127   /* Disable the Power Down in Run mode*/
00128   __HAL_FLASH_POWER_DOWN_DISABLE();
00129
00130   return HAL_OK;
00131 }
00132
00133 /**
00134   * @}
00135   */
00136
00137 /**
00138   * @}
00139   */
00140 #endif /* HAL_FLASH_MODULE_ENABLED */
00141
00142
00143
00144 /**
00145   * @}
00146   */
00147
00148 /**
00149   * @}
00150   */
00151
00152
00153 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00154
00155
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_flash_ramfunc.h Source File

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stm32l4xx_hal_flash_ramfunc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_flash_ramfunc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of FLASH RAMFUNC driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_FLASH_RAMFUNC_H
00040 #define __STM32L4xx_FLASH_RAMFUNC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASH_RAMFUNC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported macro ------------------------------------------------------------*/
00059 /**
00060   * @brief  __RAM_FUNC definition
00061   */
00062 #if defined ( __CC_ARM   )
00063 /* ARM Compiler
00064    ------------
00065    RAM functions are defined using the toolchain options.
00066    Functions that are executed in RAM should reside in a separate source module.
00067    Using the 'Options for File' dialog you can simply change the 'Code / Const'
00068    area of a module to a memory space in physical RAM.
00069    Available memory areas are declared in the 'Target' tab of the 'Options for Target'
00070    dialog.
00071 */
00072 #define __RAM_FUNC HAL_StatusTypeDef
00073
00074 #elif defined ( __ICCARM__ )
00075 /* ICCARM Compiler
00076    ---------------
00077    RAM functions are defined using a specific toolchain keyword "__ramfunc".
00078 */
00079 #define __RAM_FUNC __ramfunc HAL_StatusTypeDef
00080
00081 #elif defined   (  __GNUC__  )
00082 /* GNU Compiler
00083    ------------
00084   RAM functions are defined using a specific toolchain attribute
00085    "__attribute__((section(".RamFunc")))".
00086 */
00087 #define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
00088
00089 #endif
00090
00091
00092 /* Exported functions --------------------------------------------------------*/
00093 /** @addtogroup FLASH_RAMFUNC_Exported_Functions
00094   * @{
00095   */
00096
00097 /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
00098   * @{
00099   */
00100 /* Peripheral Control functions  ************************************************/
00101 __RAM_FUNC  HAL_FLASHEx_EnableRunPowerDown(void);
00102 __RAM_FUNC  HAL_FLASHEx_DisableRunPowerDown(void);
00103 /**
00104   * @}
00105   */
00106
00107 /**
00108   * @}
00109   */
00110
00111 /**
00112   * @}
00113   */
00114
00115 /**
00116   * @}
00117   */
00118
00119 #ifdef __cplusplus
00120 }
00121 #endif
00122
00123 #endif /* __STM32L4xx_FLASH_RAMFUNC_H */
00124
00125 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_gpio.c Source File

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stm32l4xx_hal_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   GPIO HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### GPIO Peripheral features #####
00016   ==============================================================================
00017   [..]
00018     (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
00019         configured by software in several modes:
00020         (++) Input mode
00021         (++) Analog mode
00022         (++) Output mode
00023         (++) Alternate function mode
00024         (++) External interrupt/event lines
00025
00026     (+) During and just after reset, the alternate functions and external interrupt
00027         lines are not active and the I/O ports are configured in input floating mode.
00028
00029     (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
00030         activated or not.
00031
00032     (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00033         type and the IO speed can be selected depending on the VDD value.
00034
00035     (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
00036         multiplexer that allows only one peripheral alternate function (AF) connected
00037        to an IO pin at a time. In this way, there can be no conflict between peripherals
00038        sharing the same IO pin.
00039
00040     (+) All ports have external interrupt/event capability. To use external interrupt
00041         lines, the port must be configured in input mode. All available GPIO pins are
00042         connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00043
00044     (+) The external interrupt/event controller consists of up to 39 edge detectors
00045         (16 lines are connected to GPIO) for generating event/interrupt requests (each
00046         input line can be independently configured to select the type (interrupt or event)
00047         and the corresponding trigger event (rising or falling or both). Each line can
00048         also be masked independently.
00049
00050                      ##### How to use this driver #####
00051   ==============================================================================
00052   [..]
00053     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
00054
00055     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00056         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00057         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
00058              structure.
00059         (++) In case of Output or alternate function mode selection: the speed is
00060              configured through "Speed" member from GPIO_InitTypeDef structure.
00061         (++) In alternate mode is selection, the alternate function connected to the IO
00062              is configured through "Alternate" member from GPIO_InitTypeDef structure.
00063         (++) Analog mode is required when a pin is to be used as ADC channel
00064              or DAC output.
00065         (++) In case of external interrupt/event selection the "Mode" member from
00066              GPIO_InitTypeDef structure select the type (interrupt or event) and
00067              the corresponding trigger event (rising or falling or both).
00068
00069     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
00070         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00071         HAL_NVIC_EnableIRQ().
00072
00073     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00074
00075     (#) To set/reset the level of a pin configured in output mode use
00076         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00077
00078    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00079
00080     (#) During and just after reset, the alternate functions are not
00081         active and the GPIO pins are configured in input floating mode (except JTAG
00082         pins).
00083
00084     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
00085         (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
00086         priority over the GPIO function.
00087
00088     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00089         general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
00090         The HSE has priority over the GPIO function.
00091
00092   @endverbatim
00093   ******************************************************************************
00094   * @attention
00095   *
00096   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00097   *
00098   * Redistribution and use in source and binary forms, with or without modification,
00099   * are permitted provided that the following conditions are met:
00100   *   1. Redistributions of source code must retain the above copyright notice,
00101   *      this list of conditions and the following disclaimer.
00102   *   2. Redistributions in binary form must reproduce the above copyright notice,
00103   *      this list of conditions and the following disclaimer in the documentation
00104   *      and/or other materials provided with the distribution.
00105   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00106   *      may be used to endorse or promote products derived from this software
00107   *      without specific prior written permission.
00108   *
00109   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00110   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00111   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00112   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00113   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00114   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00115   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00116   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00117   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00118   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00119   *
00120   ******************************************************************************
00121   */
00122
00123 /* Includes ------------------------------------------------------------------*/
00124 #include "stm32l4xx_hal.h"
00125
00126 /** @addtogroup STM32L4xx_HAL_Driver
00127   * @{
00128   */
00129
00130 /** @defgroup GPIO GPIO
00131   * @brief GPIO HAL module driver
00132   * @{
00133   */
00134
00135 #ifdef HAL_GPIO_MODULE_ENABLED
00136
00137 /* Private typedef -----------------------------------------------------------*/
00138 /* Private defines -----------------------------------------------------------*/
00139 /** @defgroup GPIO_Private_Defines GPIO Private Defines
00140   * @{
00141   */
00142 #define GPIO_MODE             ((uint32_t)0x00000003)
00143 #define ANALOG_MODE           ((uint32_t)0x00000008)
00144 #define EXTI_MODE             ((uint32_t)0x10000000)
00145 #define GPIO_MODE_IT          ((uint32_t)0x00010000)
00146 #define GPIO_MODE_EVT         ((uint32_t)0x00020000)
00147 #define RISING_EDGE           ((uint32_t)0x00100000)
00148 #define FALLING_EDGE          ((uint32_t)0x00200000)
00149 #define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
00150
00151 #define GPIO_NUMBER           ((uint32_t)16)
00152 /**
00153   * @}
00154   */
00155
00156 /* Private macros ------------------------------------------------------------*/
00157 /* Private macros ------------------------------------------------------------*/
00158 /** @defgroup GPIO_Private_Macros GPIO Private Macros
00159   * @{
00160   */
00161 /**
00162   * @}
00163   */
00164 /* Private variables ---------------------------------------------------------*/
00165 /* Private function prototypes -----------------------------------------------*/
00166 /* Exported functions --------------------------------------------------------*/
00167
00168 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00169   * @{
00170   */
00171
00172 /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
00173  *  @brief    Initialization and Configuration functions
00174  *
00175 @verbatim
00176  ===============================================================================
00177               ##### Initialization and de-initialization functions #####
00178  ===============================================================================
00179
00180 @endverbatim
00181   * @{
00182   */
00183
00184 /**
00185   * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00186   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
00187   * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
00188   *         the configuration information for the specified GPIO peripheral.
00189   * @retval None
00190   */
00191 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00192 {
00193   uint32_t position = 0x00;
00194   uint32_t iocurrent = 0x00;
00195   uint32_t temp = 0x00;
00196
00197   /* Check the parameters */
00198   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00199   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00200   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00201   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00202
00203   /* Configure the port pins */
00204   while (((GPIO_Init->Pin) >> position) != RESET)
00205   {
00206     /* Get current io position */
00207     iocurrent = (GPIO_Init->Pin) & (1U << position);
00208
00209     if(iocurrent)
00210     {
00211       /*--------------------- GPIO Mode Configuration ------------------------*/
00212       /* In case of Alternate function mode selection */
00213       if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00214       {
00215         /* Check the Alternate function parameters */
00216         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
00217         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
00218
00219         /* Configure Alternate function mapped with the current IO */
00220         temp = GPIOx->AFR[position >> 3];
00221         temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
00222         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
00223         GPIOx->AFR[position >> 3] = temp;
00224       }
00225
00226       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
00227       temp = GPIOx->MODER;
00228       temp &= ~(GPIO_MODER_MODE0 << (position * 2));
00229       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
00230       GPIOx->MODER = temp;
00231
00232       /* In case of Output or Alternate function mode selection */
00233       if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
00234          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00235       {
00236         /* Check the Speed parameter */
00237         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00238         /* Configure the IO Speed */
00239         temp = GPIOx->OSPEEDR;
00240         temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2));
00241         temp |= (GPIO_Init->Speed << (position * 2));
00242         GPIOx->OSPEEDR = temp;
00243
00244         /* Configure the IO Output Type */
00245         temp = GPIOx->OTYPER;
00246         temp &= ~(GPIO_OTYPER_OT0 << position) ;
00247         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
00248         GPIOx->OTYPER = temp;
00249       }
00250
00251 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00252
00253       /* In case of Analog mode, check if ADC control mode is selected */
00254       if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
00255       {
00256         /* Configure the IO Output Type */
00257         temp = GPIOx->ASCR;
00258         temp &= ~(GPIO_ASCR_ASC0 << position) ;
00259         temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position);
00260         GPIOx->ASCR = temp;
00261       }
00262
00263 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00264
00265       /* Activate the Pull-up or Pull down resistor for the current IO */
00266       temp = GPIOx->PUPDR;
00267       temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
00268       temp |= ((GPIO_Init->Pull) << (position * 2));
00269       GPIOx->PUPDR = temp;
00270
00271       /*--------------------- EXTI Mode Configuration ------------------------*/
00272       /* Configure the External Interrupt or event for the current IO */
00273       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
00274       {
00275         /* Enable SYSCFG Clock */
00276         __HAL_RCC_SYSCFG_CLK_ENABLE();
00277
00278         temp = SYSCFG->EXTICR[position >> 2];
00279         temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
00280         temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)));
00281         SYSCFG->EXTICR[position >> 2] = temp;
00282
00283         /* Clear EXTI line configuration */
00284         temp = EXTI->IMR1;
00285         temp &= ~((uint32_t)iocurrent);
00286         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
00287         {
00288           temp |= iocurrent;
00289         }
00290         EXTI->IMR1 = temp;
00291
00292         temp = EXTI->EMR1;
00293         temp &= ~((uint32_t)iocurrent);
00294         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
00295         {
00296           temp |= iocurrent;
00297         }
00298         EXTI->EMR1 = temp;
00299
00300         /* Clear Rising Falling edge configuration */
00301         temp = EXTI->RTSR1;
00302         temp &= ~((uint32_t)iocurrent);
00303         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
00304         {
00305           temp |= iocurrent;
00306         }
00307         EXTI->RTSR1 = temp;
00308
00309         temp = EXTI->FTSR1;
00310         temp &= ~((uint32_t)iocurrent);
00311         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
00312         {
00313           temp |= iocurrent;
00314         }
00315         EXTI->FTSR1 = temp;
00316       }
00317     }
00318
00319     position++;
00320   }
00321 }
00322
00323 /**
00324   * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
00325   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
00326   * @param  GPIO_Pin: specifies the port bit to be written.
00327   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
00328   * @retval None
00329   */
00330 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00331 {
00332   uint32_t position = 0x00;
00333   uint32_t iocurrent = 0x00;
00334   uint32_t tmp = 0x00;
00335
00336   /* Check the parameters */
00337   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00338   assert_param(IS_GPIO_PIN(GPIO_Pin));
00339
00340   /* Configure the port pins */
00341   while ((GPIO_Pin >> position) != RESET)
00342   {
00343     /* Get current io position */
00344     iocurrent = (GPIO_Pin) & (1U << position);
00345
00346     if (iocurrent)
00347     {
00348       /*------------------------- GPIO Mode Configuration --------------------*/
00349       /* Configure IO in Analog Mode */
00350       GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2));
00351
00352       /* Configure the default Alternate Function in current IO */
00353       GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
00354
00355       /* Configure the default value for IO Speed */
00356       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2));
00357
00358       /* Configure the default value IO Output Type */
00359       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
00360
00361       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
00362       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
00363
00364 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00365
00366       /* Deactivate the Control bit of Analog mode for the current IO */
00367       GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);
00368
00369 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00370
00371       /*------------------------- EXTI Mode Configuration --------------------*/
00372       /* Clear the External Interrupt or Event for the current IO */
00373
00374       tmp = SYSCFG->EXTICR[position >> 2];
00375       tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
00376       if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
00377       {
00378         tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
00379         SYSCFG->EXTICR[position >> 2] &= ~tmp;
00380
00381         /* Clear EXTI line configuration */
00382         EXTI->IMR1 &= ~((uint32_t)iocurrent);
00383         EXTI->EMR1 &= ~((uint32_t)iocurrent);
00384
00385         /* Clear Rising Falling edge configuration */
00386         EXTI->RTSR1 &= ~((uint32_t)iocurrent);
00387         EXTI->FTSR1 &= ~((uint32_t)iocurrent);
00388       }
00389     }
00390
00391     position++;
00392   }
00393 }
00394
00395 /**
00396   * @}
00397   */
00398
00399 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
00400  *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
00401  *
00402 @verbatim
00403  ===============================================================================
00404                        ##### IO operation functions #####
00405  ===============================================================================
00406
00407 @endverbatim
00408   * @{
00409   */
00410
00411 /**
00412   * @brief  Read the specified input port pin.
00413   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
00414   * @param  GPIO_Pin: specifies the port bit to read.
00415   *         This parameter can be GPIO_PIN_x where x can be (0..15).
00416   * @retval The input port pin value.
00417   */
00418 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00419 {
00420   GPIO_PinState bitstatus;
00421
00422   /* Check the parameters */
00423   assert_param(IS_GPIO_PIN(GPIO_Pin));
00424
00425   if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
00426   {
00427     bitstatus = GPIO_PIN_SET;
00428   }
00429   else
00430   {
00431     bitstatus = GPIO_PIN_RESET;
00432   }
00433   return bitstatus;
00434 }
00435
00436 /**
00437   * @brief  Set or clear the selected data port bit.
00438   *
00439   * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
00440   *         accesses. In this way, there is no risk of an IRQ occurring between
00441   *         the read and the modify access.
00442   *
00443   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
00444   * @param  GPIO_Pin: specifies the port bit to be written.
00445   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
00446   * @param  PinState: specifies the value to be written to the selected bit.
00447   *         This parameter can be one of the GPIO_PinState enum values:
00448   *            @arg GPIO_PIN_RESET: to clear the port pin
00449   *            @arg GPIO_PIN_SET: to set the port pin
00450   * @retval None
00451   */
00452 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00453 {
00454   /* Check the parameters */
00455   assert_param(IS_GPIO_PIN(GPIO_Pin));
00456   assert_param(IS_GPIO_PIN_ACTION(PinState));
00457
00458   if(PinState != GPIO_PIN_RESET)
00459   {
00460     GPIOx->BSRR = (uint32_t)GPIO_Pin;
00461   }
00462   else
00463   {
00464     GPIOx->BRR = (uint32_t)GPIO_Pin;
00465   }
00466 }
00467
00468 /**
00469   * @brief  Toggle the specified GPIO pin.
00470   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
00471   * @param  GPIO_Pin: specifies the pin to be toggled.
00472   * @retval None
00473   */
00474 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00475 {
00476   /* Check the parameters */
00477   assert_param(IS_GPIO_PIN(GPIO_Pin));
00478
00479   GPIOx->ODR ^= GPIO_Pin;
00480 }
00481
00482 /**
00483 * @brief  Lock GPIO Pins configuration registers.
00484   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
00485   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
00486   * @note   The configuration of the locked GPIO pins can no longer be modified
00487   *         until the next reset.
00488   * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
00489   * @param  GPIO_Pin: specifies the port bits to be locked.
00490   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00491   * @retval None
00492   */
00493 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00494 {
00495   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00496
00497   /* Check the parameters */
00498   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
00499   assert_param(IS_GPIO_PIN(GPIO_Pin));
00500
00501   /* Apply lock key write sequence */
00502   tmp |= GPIO_Pin;
00503   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00504   GPIOx->LCKR = tmp;
00505   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
00506   GPIOx->LCKR = GPIO_Pin;
00507   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00508   GPIOx->LCKR = tmp;
00509   /* Read LCKK bit*/
00510   tmp = GPIOx->LCKR;
00511
00512   if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
00513   {
00514     return HAL_OK;
00515   }
00516   else
00517   {
00518     return HAL_ERROR;
00519   }
00520 }
00521
00522 /**
00523   * @brief  Handle EXTI interrupt request.
00524   * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
00525   * @retval None
00526   */
00527 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00528 {
00529   /* EXTI line interrupt detected */
00530   if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
00531   {
00532     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
00533     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00534   }
00535 }
00536
00537 /**
00538   * @brief  EXTI line detection callback.
00539   * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
00540   * @retval None
00541   */
00542 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
00543 {
00544   /* Prevent unused argument(s) compilation warning */
00545   UNUSED(GPIO_Pin);
00546
00547   /* NOTE: This function should not be modified, when the callback is needed,
00548            the HAL_GPIO_EXTI_Callback could be implemented in the user file
00549    */
00550 }
00551
00552 /**
00553   * @}
00554   */
00555
00556
00557 /**
00558   * @}
00559   */
00560
00561 #endif /* HAL_GPIO_MODULE_ENABLED */
00562 /**
00563   * @}
00564   */
00565
00566 /**
00567   * @}
00568   */
00569
00570 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_gpio.h Source File

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stm32l4xx_hal_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_gpio.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of GPIO HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_GPIO_H
00040 #define __STM32L4xx_HAL_GPIO_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup GPIO
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup GPIO_Exported_Types GPIO Exported Types
00060   * @{
00061   */
00062 /**
00063   * @brief   GPIO Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
00068                            This parameter can be any value of @ref GPIO_pins */
00069
00070   uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
00071                            This parameter can be a value of @ref GPIO_mode */
00072
00073   uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
00074                            This parameter can be a value of @ref GPIO_pull */
00075
00076   uint32_t Speed;      /*!< Specifies the speed for the selected pins.
00077                            This parameter can be a value of @ref GPIO_speed */
00078
00079   uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
00080                             This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
00081 }GPIO_InitTypeDef;
00082
00083 /**
00084   * @brief  GPIO Bit SET and Bit RESET enumeration
00085   */
00086 typedef enum
00087 {
00088   GPIO_PIN_RESET = 0,
00089   GPIO_PIN_SET
00090 }GPIO_PinState;
00091 /**
00092   * @}
00093   */
00094
00095 /* Exported constants --------------------------------------------------------*/
00096 /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
00097   * @{
00098   */
00099 /** @defgroup GPIO_pins GPIO pins
00100   * @{
00101   */
00102 #define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
00103 #define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
00104 #define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
00105 #define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
00106 #define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
00107 #define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
00108 #define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
00109 #define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
00110 #define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
00111 #define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
00112 #define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
00113 #define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
00114 #define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
00115 #define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
00116 #define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
00117 #define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
00118 #define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
00119
00120 #define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup GPIO_mode GPIO mode
00126   * @brief GPIO Configuration Mode
00127   *        Elements values convention: 0xX0yz00YZ
00128   *           - X  : GPIO mode or EXTI Mode
00129   *           - y  : External IT or Event trigger detection
00130   *           - z  : IO configuration on External IT or Event
00131   *           - Y  : Output type (Push Pull or Open Drain)
00132   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
00133   * @{
00134   */
00135 #define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
00136 #define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
00137 #define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
00138 #define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
00139 #define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
00140 #define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
00141 #define  GPIO_MODE_ANALOG_ADC_CONTROL           ((uint32_t)0x0000000B)   /*!< Analog Mode for ADC conversion */
00142 #define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
00143 #define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
00144 #define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
00145 #define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
00146 #define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
00147 #define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup GPIO_speed GPIO speed
00153   * @brief GPIO Output Maximum frequency
00154   * @{
00155   */
00156 #define  GPIO_SPEED_FREQ_LOW        ((uint32_t)0x00000000)   /*!< range up to 5 MHz, please refer to the product datasheet */
00157 #define  GPIO_SPEED_FREQ_MEDIUM     ((uint32_t)0x00000001)   /*!< range  5 MHz to 25 MHz, please refer to the product datasheet */
00158 #define  GPIO_SPEED_FREQ_HIGH       ((uint32_t)0x00000002)   /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */
00159 #define  GPIO_SPEED_FREQ_VERY_HIGH  ((uint32_t)0x00000003)   /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */
00160 /**
00161   * @}
00162   */
00163
00164  /** @defgroup GPIO_pull GPIO pull
00165    * @brief GPIO Pull-Up or Pull-Down Activation
00166    * @{
00167    */
00168 #define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
00169 #define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
00170 #define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
00171 /**
00172   * @}
00173   */
00174
00175 /**
00176   * @}
00177   */
00178
00179 /* Exported macro ------------------------------------------------------------*/
00180 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
00181   * @{
00182   */
00183
00184 /**
00185   * @brief  Check whether the specified EXTI line flag is set or not.
00186   * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
00187   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00188   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00189   */
00190 #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR1 & (__EXTI_LINE__))
00191
00192 /**
00193   * @brief  Clear the EXTI's line pending flags.
00194   * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
00195   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00196   * @retval None
00197   */
00198 #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR1 = (__EXTI_LINE__))
00199
00200 /**
00201   * @brief  Check whether the specified EXTI line is asserted or not.
00202   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00203   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00204   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00205   */
00206 #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR1 & (__EXTI_LINE__))
00207
00208 /**
00209   * @brief  Clear the EXTI's line pending bits.
00210   * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
00211   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00212   * @retval None
00213   */
00214 #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR1 = (__EXTI_LINE__))
00215
00216 /**
00217   * @brief  Generate a Software interrupt on selected EXTI line.
00218   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00219   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00220   * @retval None
00221   */
00222 #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
00223
00224 /**
00225   * @}
00226   */
00227
00228 /* Private macros ------------------------------------------------------------*/
00229 /** @addtogroup GPIO_Private_Macros GPIO Private Macros
00230   * @{
00231   */
00232 #define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
00233
00234 #define IS_GPIO_PIN(__PIN__)        (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
00235
00236 #define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
00237                                      ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
00238                                      ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
00239                                      ((__MODE__) == GPIO_MODE_AF_PP)              ||\
00240                                      ((__MODE__) == GPIO_MODE_AF_OD)              ||\
00241                                      ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
00242                                      ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
00243                                      ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
00244                                      ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
00245                                      ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
00246                                      ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
00247                                      ((__MODE__) == GPIO_MODE_ANALOG)             ||\
00248                                      ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL))
00249
00250 #define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
00251                                      ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
00252                                      ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
00253                                      ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
00254
00255 #define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
00256                                      ((__PULL__) == GPIO_PULLUP)   || \
00257                                      ((__PULL__) == GPIO_PULLDOWN))
00258 /**
00259   * @}
00260   */
00261
00262 /* Include GPIO HAL Extended module */
00263 #include "stm32l4xx_hal_gpio_ex.h"
00264
00265 /* Exported functions --------------------------------------------------------*/
00266 /** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
00267   * @{
00268   */
00269
00270 /** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
00271  *  @brief    Initialization and Configuration functions
00272  * @{
00273  */
00274
00275 /* Initialization and de-initialization functions *****************************/
00276 void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
00277 void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
00278
00279 /**
00280   * @}
00281   */
00282
00283 /** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
00284  * @{
00285  */
00286
00287 /* IO operation functions *****************************************************/
00288 GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00289 void              HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
00290 void              HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00291 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00292 void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
00293 void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
00294
00295 /**
00296   * @}
00297   */
00298
00299 /**
00300   * @}
00301   */
00302
00303 /**
00304   * @}
00305   */
00306
00307 /**
00308   * @}
00309   */
00310
00311 #ifdef __cplusplus
00312 }
00313 #endif
00314
00315 #endif /* __STM32L4xx_HAL_GPIO_H */
00316
00317 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_gpio_ex.h Source File

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stm32l4xx_hal_gpio_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of GPIO HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_GPIO_EX_H
00040 #define __STM32L4xx_HAL_GPIO_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup GPIOEx GPIOEx
00054   * @brief GPIO Extended HAL module driver
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
00065   * @{
00066   */
00067
00068 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00069 /*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx---*/
00070 /**
00071   * @brief   AF 0 selection
00072   */
00073 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
00074 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00075 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00076 #if defined(STM32L476xx) || defined(STM32L486xx)
00077 #define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                        */
00078 #endif /* STM32L476xx || STM32L486xx */
00079 #define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
00080
00081 /**
00082   * @brief   AF 1 selection
00083   */
00084 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
00085 #define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
00086 #define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */
00087 #define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */
00088 #define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
00089 #define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
00090
00091 /**
00092   * @brief   AF 2 selection
00093   */
00094 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
00095 #define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
00096 #define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
00097 #define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
00098 #define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
00099
00100 /**
00101   * @brief   AF 3 selection
00102   */
00103 #define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
00104 #define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
00105 #define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
00106
00107 /**
00108   * @brief   AF 4 selection
00109   */
00110 #define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
00111 #define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
00112 #define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
00113
00114 /**
00115   * @brief   AF 5 selection
00116   */
00117 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
00118 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
00119
00120 /**
00121   * @brief   AF 6 selection
00122   */
00123 #define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
00124 #define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */
00125
00126 /**
00127   * @brief   AF 7 selection
00128   */
00129 #define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
00130 #define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
00131 #define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
00132
00133 /**
00134   * @brief   AF 8 selection
00135   */
00136 #define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */
00137 #define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */
00138 #define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
00139
00140
00141 /**
00142   * @brief   AF 9 selection
00143   */
00144 #define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
00145 #define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
00146
00147 /**
00148   * @brief   AF 10 selection
00149   */
00150 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00151 #define GPIO_AF10_OTG_FS       ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
00152 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00153 #define GPIO_AF10_QUADSPI      ((uint8_t)0xA)  /* QUADSPI Alternate Function mapping */
00154
00155 #if defined(STM32L476xx) || defined(STM32L486xx)
00156 /**
00157   * @brief   AF 11 selection
00158   */
00159 #define GPIO_AF11_LCD           ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
00160 #endif /* STM32L476xx || STM32L486xx */
00161
00162 /**
00163   * @brief   AF 12 selection
00164   */
00165 #define GPIO_AF12_FMC           ((uint8_t)0xC)  /* FMC Alternate Function mapping     */
00166 #define GPIO_AF12_SWPMI1        ((uint8_t)0xC)  /* SWPMI1 Alternate Function mapping  */
00167 #define GPIO_AF12_COMP1         ((uint8_t)0xC)  /* COMP1 Alternate Function mapping   */
00168 #define GPIO_AF12_COMP2         ((uint8_t)0xC)  /* COMP2 Alternate Function mapping   */
00169 #define GPIO_AF12_SDMMC1        ((uint8_t)0xC)  /* SDMMC1 Alternate Function mapping  */
00170
00171 /**
00172   * @brief   AF 13 selection
00173   */
00174 #define GPIO_AF13_SAI1          ((uint8_t)0x0D)   /* SAI1 Alternate Function mapping */
00175 #define GPIO_AF13_SAI2          ((uint8_t)0x0D)   /* SAI2 Alternate Function mapping */
00176 #define GPIO_AF13_TIM8_COMP2    ((uint8_t)0x0D)   /* TIM8/COMP2 Break in Alternate Function mapping  */
00177 #define GPIO_AF13_TIM8_COMP1    ((uint8_t)0x0D)   /* TIM8/COMP1 Break in Alternate Function mapping  */
00178
00179 /**
00180   * @brief   AF 14 selection
00181   */
00182 #define GPIO_AF14_TIM2          ((uint8_t)0x0E)   /* TIM2 Alternate Function mapping */
00183 #define GPIO_AF14_TIM15         ((uint8_t)0x0E)   /* TIM15 Alternate Function mapping */
00184 #define GPIO_AF14_TIM16         ((uint8_t)0x0E)   /* TIM16 Alternate Function mapping */
00185 #define GPIO_AF14_TIM17         ((uint8_t)0x0E)   /* TIM17 Alternate Function mapping */
00186 #define GPIO_AF14_LPTIM2        ((uint8_t)0x0E)   /* LPTIM2 Alternate Function mapping */
00187 #define GPIO_AF14_TIM8_COMP1    ((uint8_t)0x0E)   /* TIM8/COMP1 Break in Alternate Function mapping  */
00188
00189 /**
00190   * @brief   AF 15 selection
00191   */
00192 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
00193
00194 #define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
00195
00196 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00197
00198 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00199 /*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/
00200 /**
00201   * @brief   AF 0 selection
00202   */
00203 #define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
00204 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
00205 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
00206 #if defined(STM32L433xx) || defined(STM32L443xx)
00207 #define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                          */
00208 #endif /* STM32L433xx || STM32L443xx */
00209 #define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
00210
00211 /**
00212   * @brief   AF 1 selection
00213   */
00214 #define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
00215 #define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
00216 #define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
00217 #define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
00218
00219 /**
00220   * @brief   AF 2 selection
00221   */
00222 #define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
00223 #define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
00224
00225 /**
00226   * @brief   AF 3 selection
00227   */
00228 #define GPIO_AF3_USART2        ((uint8_t)0x03)  /* USART1 Alternate Function mapping */
00229 #define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
00230 #define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
00231
00232 /**
00233   * @brief   AF 4 selection
00234   */
00235 #define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
00236 #define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
00237 #define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
00238
00239 /**
00240   * @brief   AF 5 selection
00241   */
00242 #define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
00243 #define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
00244
00245 /**
00246   * @brief   AF 6 selection
00247   */
00248 #define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
00249 #define GPIO_AF6_COMP1         ((uint8_t)0x06)  /* COMP1 Alternate Function mapping   */
00250
00251 /**
00252   * @brief   AF 7 selection
00253   */
00254 #define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
00255 #define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
00256 #define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
00257
00258 /**
00259   * @brief   AF 8 selection
00260   */
00261 #define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
00262
00263 /**
00264   * @brief   AF 9 selection
00265   */
00266 #define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
00267 #define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
00268
00269 /**
00270   * @brief   AF 10 selection
00271   */
00272 #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00273 #define GPIO_AF10_USB_FS        ((uint8_t)0xA)  /* USB_FS Alternate Function mapping */
00274 #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
00275 #define GPIO_AF10_QUADSPI       ((uint8_t)0xA)  /* QUADSPI Alternate Function mapping */
00276
00277 #if defined(STM32L433xx) || defined(STM32L443xx)
00278 /**
00279   * @brief   AF 11 selection
00280   */
00281 #define GPIO_AF11_LCD           ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
00282 #endif /* STM32L433xx || STM32L443xx */
00283
00284 /**
00285   * @brief   AF 12 selection
00286   */
00287 #define GPIO_AF12_SWPMI1        ((uint8_t)0xC)  /* SWPMI1 Alternate Function mapping  */
00288 #define GPIO_AF12_COMP1         ((uint8_t)0xC)  /* COMP1 Alternate Function mapping   */
00289 #define GPIO_AF12_COMP2         ((uint8_t)0xC)  /* COMP2 Alternate Function mapping   */
00290 #define GPIO_AF12_SDMMC1        ((uint8_t)0xC)  /* SDMMC1 Alternate Function mapping  */
00291
00292 /**
00293   * @brief   AF 13 selection
00294   */
00295 #define GPIO_AF13_SAI1          ((uint8_t)0x0D)   /* SAI1 Alternate Function mapping */
00296
00297 /**
00298   * @brief   AF 14 selection
00299   */
00300 #define GPIO_AF14_TIM2          ((uint8_t)0x0E)   /* TIM2 Alternate Function mapping */
00301 #define GPIO_AF14_TIM15         ((uint8_t)0x0E)   /* TIM15 Alternate Function mapping */
00302 #define GPIO_AF14_TIM16         ((uint8_t)0x0E)   /* TIM16 Alternate Function mapping */
00303 #define GPIO_AF14_LPTIM2        ((uint8_t)0x0E)   /* LPTIM2 Alternate Function mapping */
00304
00305 /**
00306   * @brief   AF 15 selection
00307   */
00308 #define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
00309
00310 #define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
00311
00312 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
00313
00314 /**
00315   * @}
00316   */
00317
00318 /**
00319   * @}
00320   */
00321
00322 /* Exported macro ------------------------------------------------------------*/
00323 /** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
00324   * @{
00325   */
00326
00327 /** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
00328 * @{
00329   */
00330 #if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)
00331
00332 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
00333                                       ((__GPIOx__) == (GPIOB))? 1U :\
00334                                       ((__GPIOx__) == (GPIOC))? 2U :\
00335                                       ((__GPIOx__) == (GPIOD))? 3U :\
00336                                       ((__GPIOx__) == (GPIOE))? 4U : 7U)
00337
00338 #endif /* STM32L431xx || STM32L433xx || STM32L443xx */
00339
00340 #if defined(STM32L432xx) || defined(STM32L442xx)
00341
00342 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
00343                                       ((__GPIOx__) == (GPIOB))? 1U :\
00344                                       ((__GPIOx__) == (GPIOC))? 2U : 7U)
00345
00346 #endif /* STM32L432xx || STM32L442xx */
00347
00348 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00349
00350 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
00351                                       ((__GPIOx__) == (GPIOB))? 1U :\
00352                                       ((__GPIOx__) == (GPIOC))? 2U :\
00353                                       ((__GPIOx__) == (GPIOD))? 3U :\
00354                                       ((__GPIOx__) == (GPIOE))? 4U :\
00355                                       ((__GPIOx__) == (GPIOF))? 5U :\
00356                                       ((__GPIOx__) == (GPIOG))? 6U : 7U)
00357
00358 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00359
00360 /**
00361   * @}
00362   */
00363
00364 /**
00365   * @}
00366   */
00367
00368 /* Exported functions --------------------------------------------------------*/
00369 /**
00370   * @}
00371   */
00372
00373 /**
00374   * @}
00375   */
00376
00377 #ifdef __cplusplus
00378 }
00379 #endif
00380
00381 #endif /* __STM32L4xx_HAL_GPIO_EX_H */
00382
00383 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_hcd.c Source File

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stm32l4xx_hal_hcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_hcd.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   HCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     (#)Declare a HCD_HandleTypeDef handle structure, for example:
00021        HCD_HandleTypeDef  hhcd;
00022
00023     (#)Fill parameters of Init structure in HCD handle
00024
00025     (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
00026
00027     (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
00028         (##) Enable the HCD/USB Low Level interface clock using the following macro
00029              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
00030
00031         (##) Initialize the related GPIO clocks
00032         (##) Configure HCD pin-out
00033         (##) Configure HCD NVIC interrupt
00034
00035     (#)Associate the Upper USB Host stack to the HAL HCD Driver:
00036         (##) hhcd.pData = phost;
00037
00038     (#)Enable HCD transmission and reception:
00039         (##) HAL_HCD_Start();
00040
00041   @endverbatim
00042   ******************************************************************************
00043   * @attention
00044   *
00045   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00046   *
00047   * Redistribution and use in source and binary forms, with or without modification,
00048   * are permitted provided that the following conditions are met:
00049   *   1. Redistributions of source code must retain the above copyright notice,
00050   *      this list of conditions and the following disclaimer.
00051   *   2. Redistributions in binary form must reproduce the above copyright notice,
00052   *      this list of conditions and the following disclaimer in the documentation
00053   *      and/or other materials provided with the distribution.
00054   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00055   *      may be used to endorse or promote products derived from this software
00056   *      without specific prior written permission.
00057   *
00058   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00059   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00060   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00061   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00062   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00063   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00064   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00065   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00066   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00067   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00068   *
00069   ******************************************************************************
00070   */
00071
00072 /* Includes ------------------------------------------------------------------*/
00073 #include "stm32l4xx_hal.h"
00074
00075 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00076
00077 /** @addtogroup STM32L4xx_HAL_Driver
00078   * @{
00079   */
00080
00081 /** @defgroup HCD HCD
00082   * @brief HCD HAL module driver
00083   * @{
00084   */
00085
00086 #ifdef HAL_HCD_MODULE_ENABLED
00087
00088 /* Private typedef -----------------------------------------------------------*/
00089 /* Private define ------------------------------------------------------------*/
00090 /* Private macro -------------------------------------------------------------*/
00091 /* Private variables ---------------------------------------------------------*/
00092 /* Private function prototypes -----------------------------------------------*/
00093 /** @defgroup HCD_Private_Functions HCD Private Functions
00094   * @{
00095   */
00096 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00097 static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00098 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
00099 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported functions --------------------------------------------------------*/
00105 /** @defgroup HCD_Exported_Functions HCD Exported Functions
00106   * @{
00107   */
00108
00109 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00110  *  @brief    Initialization and Configuration functions
00111  *
00112 @verbatim
00113  ===============================================================================
00114           ##### Initialization and de-initialization functions #####
00115  ===============================================================================
00116     [..]  This section provides functions allowing to:
00117
00118 @endverbatim
00119   * @{
00120   */
00121
00122 /**
00123   * @brief  Initialize the Host driver.
00124   * @param  hhcd: HCD handle
00125   * @retval HAL status
00126   */
00127 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
00128 {
00129   /* Check the HCD handle allocation */
00130   if(hhcd == NULL)
00131   {
00132     return HAL_ERROR;
00133   }
00134
00135   /* Check the parameters */
00136   assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
00137
00138   if(hhcd->State == HAL_HCD_STATE_RESET)
00139   {
00140     /* Allocate lock resource and initialize it */
00141     hhcd->Lock = HAL_UNLOCKED;
00142
00143     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00144     HAL_HCD_MspInit(hhcd);
00145   }
00146
00147   hhcd->State = HAL_HCD_STATE_BUSY;
00148
00149   /* Disable the Interrupts */
00150  __HAL_HCD_DISABLE(hhcd);
00151
00152  /*Init the Core (common init.) */
00153  USB_CoreInit(hhcd->Instance, hhcd->Init);
00154
00155  /* Force Host Mode*/
00156  USB_SetCurrentMode(hhcd->Instance , USB_HOST_MODE);
00157
00158  /* Init Host */
00159  USB_HostInit(hhcd->Instance, hhcd->Init);
00160
00161  hhcd->State= HAL_HCD_STATE_READY;
00162
00163  return HAL_OK;
00164 }
00165
00166 /**
00167   * @brief  Initialize a Host channel.
00168   * @param  hhcd: HCD handle
00169   * @param  ch_num: Channel number.
00170   *         This parameter can be a value from 1 to 15
00171   * @param  epnum: Endpoint number.
00172   *          This parameter can be a value from 1 to 15
00173   * @param  dev_address : Current device address
00174   *          This parameter can be a value from 0 to 255
00175   * @param  speed: Current device speed.
00176   *          This parameter can be one of these values:
00177   *            HCD_SPEED_HIGH: High speed mode,
00178   *            HCD_SPEED_FULL: Full speed mode,
00179   *            HCD_SPEED_LOW: Low speed mode
00180   * @param  ep_type: Endpoint Type.
00181   *          This parameter can be one of these values:
00182   *            EP_TYPE_CTRL: Control type,
00183   *            EP_TYPE_ISOC: Isochronous type,
00184   *            EP_TYPE_BULK: Bulk type,
00185   *            EP_TYPE_INTR: Interrupt type
00186   * @param  mps: Max Packet Size.
00187   *          This parameter can be a value from 0 to32K
00188   * @retval HAL status
00189   */
00190 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00191                                   uint8_t ch_num,
00192                                   uint8_t epnum,
00193                                   uint8_t dev_address,
00194                                   uint8_t speed,
00195                                   uint8_t ep_type,
00196                                   uint16_t mps)
00197 {
00198   HAL_StatusTypeDef status = HAL_OK;
00199
00200   __HAL_LOCK(hhcd);
00201
00202   hhcd->hc[ch_num].dev_addr = dev_address;
00203   hhcd->hc[ch_num].max_packet = mps;
00204   hhcd->hc[ch_num].ch_num = ch_num;
00205   hhcd->hc[ch_num].ep_type = ep_type;
00206   hhcd->hc[ch_num].ep_num = epnum & 0x7F;
00207   hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
00208   hhcd->hc[ch_num].speed = speed;
00209
00210   status =  USB_HC_Init(hhcd->Instance,
00211                         ch_num,
00212                         epnum,
00213                         dev_address,
00214                         speed,
00215                         ep_type,
00216                         mps);
00217   __HAL_UNLOCK(hhcd);
00218
00219   return status;
00220 }
00221
00222 /**
00223   * @brief  Halt a Host channel.
00224   * @param  hhcd: HCD handle
00225   * @param  ch_num: Channel number.
00226   *         This parameter can be a value from 1 to 15
00227   * @retval HAL status
00228   */
00229 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
00230 {
00231   HAL_StatusTypeDef status = HAL_OK;
00232
00233   __HAL_LOCK(hhcd);
00234   USB_HC_Halt(hhcd->Instance, ch_num);
00235   __HAL_UNLOCK(hhcd);
00236
00237   return status;
00238 }
00239
00240 /**
00241   * @brief  DeInitialize the Host driver.
00242   * @param  hhcd: HCD handle
00243   * @retval HAL status
00244   */
00245 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
00246 {
00247   /* Check the HCD handle allocation */
00248   if(hhcd == NULL)
00249   {
00250     return HAL_ERROR;
00251   }
00252
00253   hhcd->State = HAL_HCD_STATE_BUSY;
00254
00255   /* DeInit the low level hardware */
00256   HAL_HCD_MspDeInit(hhcd);
00257
00258    __HAL_HCD_DISABLE(hhcd);
00259
00260   hhcd->State = HAL_HCD_STATE_RESET;
00261
00262   return HAL_OK;
00263 }
00264
00265 /**
00266   * @brief  Initialize the HCD MSP.
00267   * @param  hhcd: HCD handle
00268   * @retval None
00269   */
00270 __weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
00271 {
00272   /* Prevent unused argument(s) compilation warning */
00273   UNUSED(hhcd);
00274
00275   /* NOTE : This function should not be modified, when the callback is needed,
00276             the HAL_PCD_MspInit could be implemented in the user file
00277    */
00278 }
00279
00280 /**
00281   * @brief  DeInitialize the HCD MSP.
00282   * @param  hhcd: HCD handle
00283   * @retval None
00284   */
00285 __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
00286 {
00287   /* Prevent unused argument(s) compilation warning */
00288   UNUSED(hhcd);
00289
00290   /* NOTE : This function should not be modified, when the callback is needed,
00291             the HAL_PCD_MspDeInit could be implemented in the user file
00292    */
00293 }
00294
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
00300   *  @brief   HCD IO operation functions
00301   *
00302 @verbatim
00303  ===============================================================================
00304                       ##### IO operation functions #####
00305  ===============================================================================
00306  [..] This subsection provides a set of functions allowing to manage the USB Host Data
00307     Transfer
00308
00309 @endverbatim
00310   * @{
00311   */
00312
00313 /**
00314   * @brief  Submit a new URB for processing.
00315   * @param  hhcd: HCD handle
00316   * @param  ch_num: Channel number.
00317   *         This parameter can be a value from 1 to 15
00318   * @param  direction: Channel number.
00319   *          This parameter can be one of these values:
00320   *           0 : Output / 1 : Input
00321   * @param  ep_type: Endpoint Type.
00322   *          This parameter can be one of these values:
00323   *            EP_TYPE_CTRL: Control type/
00324   *            EP_TYPE_ISOC: Isochronous type/
00325   *            EP_TYPE_BULK: Bulk type/
00326   *            EP_TYPE_INTR: Interrupt type/
00327   * @param  token: Endpoint Type.
00328   *          This parameter can be one of these values:
00329   *            0: HC_PID_SETUP / 1: HC_PID_DATA1
00330   * @param  pbuff: pointer to URB data
00331   * @param  length: Length of URB data
00332   * @param  do_ping: activate do ping protocol (for high speed only).
00333   *          This parameter can be one of these values:
00334   *           0 : do ping inactive / 1 : do ping active
00335   * @retval HAL status
00336   */
00337 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00338                                             uint8_t ch_num,
00339                                             uint8_t direction ,
00340                                             uint8_t ep_type,
00341                                             uint8_t token,
00342                                             uint8_t* pbuff,
00343                                             uint16_t length,
00344                                             uint8_t do_ping)
00345 {
00346   hhcd->hc[ch_num].ep_is_in = direction;
00347   hhcd->hc[ch_num].ep_type  = ep_type;
00348
00349   if(token == 0)
00350   {
00351     hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
00352   }
00353   else
00354   {
00355     hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00356   }
00357
00358   /* Manage Data Toggle */
00359   switch(ep_type)
00360   {
00361   case EP_TYPE_CTRL:
00362     if((token == 1) && (direction == 0)) /*send data */
00363     {
00364       if ( length == 0 )
00365       { /* For Status OUT stage, Length==0, Status Out PID = 1 */
00366         hhcd->hc[ch_num].toggle_out = 1;
00367       }
00368
00369       /* Set the Data Toggle bit as per the Flag */
00370       if ( hhcd->hc[ch_num].toggle_out == 0)
00371       { /* Put the PID 0 */
00372         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00373       }
00374       else
00375       { /* Put the PID 1 */
00376         hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
00377       }
00378       if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
00379       {
00380         hhcd->hc[ch_num].do_ping = do_ping;
00381       }
00382     }
00383     break;
00384
00385   case EP_TYPE_BULK:
00386     if(direction == 0)
00387     {
00388       /* Set the Data Toggle bit as per the Flag */
00389       if ( hhcd->hc[ch_num].toggle_out == 0)
00390       { /* Put the PID 0 */
00391         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00392       }
00393       else
00394       { /* Put the PID 1 */
00395         hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
00396       }
00397       if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
00398       {
00399         hhcd->hc[ch_num].do_ping = do_ping;
00400       }
00401     }
00402     else
00403     {
00404       if( hhcd->hc[ch_num].toggle_in == 0)
00405       {
00406         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00407       }
00408       else
00409       {
00410         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00411       }
00412     }
00413
00414     break;
00415   case EP_TYPE_INTR:
00416     if(direction == 0)
00417     {
00418       /* Set the Data Toggle bit as per the Flag */
00419       if ( hhcd->hc[ch_num].toggle_out == 0)
00420       { /* Put the PID 0 */
00421         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00422       }
00423       else
00424       { /* Put the PID 1 */
00425         hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
00426       }
00427     }
00428     else
00429     {
00430       if( hhcd->hc[ch_num].toggle_in == 0)
00431       {
00432         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00433       }
00434       else
00435       {
00436         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00437       }
00438     }
00439     break;
00440
00441   case EP_TYPE_ISOC:
00442     hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00443     break;
00444   }
00445
00446   hhcd->hc[ch_num].xfer_buff = pbuff;
00447   hhcd->hc[ch_num].xfer_len  = length;
00448   hhcd->hc[ch_num].urb_state =   URB_IDLE;
00449   hhcd->hc[ch_num].xfer_count = 0 ;
00450   hhcd->hc[ch_num].ch_num = ch_num;
00451   hhcd->hc[ch_num].state = HC_IDLE;
00452
00453   return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
00454 }
00455
00456 /**
00457   * @brief  Handle HCD interrupt request.
00458   * @param  hhcd: HCD handle
00459   * @retval None
00460   */
00461 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
00462 {
00463   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00464   uint32_t i = 0 , interrupt = 0;
00465
00466   /* ensure that we are in device mode */
00467   if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
00468   {
00469     /* avoid spurious interrupt */
00470     if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
00471     {
00472       return;
00473     }
00474
00475     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00476     {
00477      /* incorrect mode, acknowledge the interrupt */
00478       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00479     }
00480
00481     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
00482     {
00483      /* incorrect mode, acknowledge the interrupt */
00484       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
00485     }
00486
00487     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
00488     {
00489      /* incorrect mode, acknowledge the interrupt */
00490       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
00491     }
00492
00493     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
00494     {
00495      /* incorrect mode, acknowledge the interrupt */
00496       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
00497     }
00498
00499     /* Handle Host Disconnect Interrupts */
00500     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
00501     {
00502
00503       /* Cleanup HPRT */
00504       USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
00505         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
00506
00507       /* Handle Host Port Interrupts */
00508       HAL_HCD_Disconnect_Callback(hhcd);
00509        USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
00510       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
00511     }
00512
00513     /* Handle Host Port Interrupts */
00514     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
00515     {
00516       HCD_Port_IRQHandler (hhcd);
00517     }
00518
00519     /* Handle Host SOF Interrupts */
00520     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
00521     {
00522       HAL_HCD_SOF_Callback(hhcd);
00523       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
00524     }
00525
00526     /* Handle Host channel Interrupts */
00527     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
00528     {
00529       interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
00530       for (i = 0; i < hhcd->Init.Host_channels ; i++)
00531       {
00532         if (interrupt & (1 << i))
00533         {
00534           if ((USBx_HC(i)->HCCHAR) &  USB_OTG_HCCHAR_EPDIR)
00535           {
00536             HCD_HC_IN_IRQHandler (hhcd, i);
00537           }
00538           else
00539           {
00540             HCD_HC_OUT_IRQHandler (hhcd, i);
00541           }
00542         }
00543       }
00544       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
00545     }
00546
00547     /* Handle Rx Queue Level Interrupts */
00548     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
00549     {
00550       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00551
00552       HCD_RXQLVL_IRQHandler (hhcd);
00553
00554       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00555     }
00556   }
00557 }
00558
00559 /**
00560   * @brief  SOF callback.
00561   * @param  hhcd: HCD handle
00562   * @retval None
00563   */
00564 __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
00565 {
00566   /* Prevent unused argument(s) compilation warning */
00567   UNUSED(hhcd);
00568
00569   /* NOTE : This function should not be modified, when the callback is needed,
00570             the HAL_HCD_SOF_Callback could be implemented in the user file
00571    */
00572 }
00573
00574 /**
00575   * @brief Connection Event callback.
00576   * @param  hhcd: HCD handle
00577   * @retval None
00578   */
00579 __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
00580 {
00581   /* Prevent unused argument(s) compilation warning */
00582   UNUSED(hhcd);
00583
00584   /* NOTE : This function should not be modified, when the callback is needed,
00585             the HAL_HCD_Connect_Callback could be implemented in the user file
00586    */
00587 }
00588
00589 /**
00590   * @brief  Disconnection Event callback.
00591   * @param  hhcd: HCD handle
00592   * @retval None
00593   */
00594 __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
00595 {
00596   /* Prevent unused argument(s) compilation warning */
00597   UNUSED(hhcd);
00598
00599   /* NOTE : This function should not be modified, when the callback is needed,
00600             the HAL_HCD_Disconnect_Callback could be implemented in the user file
00601    */
00602 }
00603
00604 /**
00605   * @brief  Notify URB state change callback.
00606   * @param  hhcd: HCD handle
00607   * @param  chnum: Channel number.
00608   *         This parameter can be a value from 1 to 15
00609   * @param  urb_state:
00610   *          This parameter can be one of these values:
00611   *            URB_IDLE/
00612   *            URB_DONE/
00613   *            URB_NOTREADY/
00614   *            URB_NYET/
00615   *            URB_ERROR/
00616   *            URB_STALL/
00617   * @retval None
00618   */
00619 __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
00620 {
00621   /* Prevent unused argument(s) compilation warning */
00622   UNUSED(hhcd);
00623   UNUSED(chnum);
00624   UNUSED(urb_state);
00625
00626   /* NOTE : This function should not be modified, when the callback is needed,
00627             the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
00628    */
00629 }
00630
00631 /**
00632   * @}
00633   */
00634
00635 /** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
00636  *  @brief   Management functions
00637  *
00638 @verbatim
00639  ===============================================================================
00640                       ##### Peripheral Control functions #####
00641  ===============================================================================
00642     [..]
00643     This subsection provides a set of functions allowing to control the HCD data
00644     transfers.
00645
00646 @endverbatim
00647   * @{
00648   */
00649
00650 /**
00651   * @brief  Start the Host driver.
00652   * @param  hhcd: HCD handle
00653   * @retval HAL status
00654   */
00655 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
00656 {
00657   __HAL_LOCK(hhcd);
00658   __HAL_HCD_ENABLE(hhcd);
00659   USB_DriveVbus(hhcd->Instance, 1);
00660   __HAL_UNLOCK(hhcd);
00661   return HAL_OK;
00662 }
00663
00664 /**
00665   * @brief  Stop the Host driver.
00666   * @param  hhcd: HCD handle
00667   * @retval HAL status
00668   */
00669
00670 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
00671 {
00672   __HAL_LOCK(hhcd);
00673   USB_StopHost(hhcd->Instance);
00674   __HAL_UNLOCK(hhcd);
00675   return HAL_OK;
00676 }
00677
00678 /**
00679   * @brief  Reset the Host port.
00680   * @param  hhcd: HCD handle
00681   * @retval HAL status
00682   */
00683 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
00684 {
00685   return (USB_ResetPort(hhcd->Instance));
00686 }
00687
00688 /**
00689   * @}
00690   */
00691
00692 /** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
00693  *  @brief   Peripheral State functions
00694  *
00695 @verbatim
00696  ===============================================================================
00697                       ##### Peripheral State functions #####
00698  ===============================================================================
00699     [..]
00700     This subsection permits to get in run-time the status of the peripheral
00701     and the data flow.
00702
00703 @endverbatim
00704   * @{
00705   */
00706
00707 /**
00708   * @brief  Return the HCD handle state.
00709   * @param  hhcd: HCD handle
00710   * @retval HAL state
00711   */
00712 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
00713 {
00714   return hhcd->State;
00715 }
00716
00717 /**
00718   * @brief  Return  URB state for a channel.
00719   * @param  hhcd: HCD handle
00720   * @param  chnum: Channel number.
00721   *         This parameter can be a value from 1 to 15
00722   * @retval URB state.
00723   *          This parameter can be one of these values:
00724   *            URB_IDLE/
00725   *            URB_DONE/
00726   *            URB_NOTREADY/
00727   *            URB_NYET/
00728   *            URB_ERROR/
00729   *            URB_STALL
00730   */
00731 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00732 {
00733   return hhcd->hc[chnum].urb_state;
00734 }
00735
00736
00737 /**
00738   * @brief  Return the last Host transfer size.
00739   * @param  hhcd: HCD handle
00740   * @param  chnum: Channel number.
00741   *         This parameter can be a value from 1 to 15
00742   * @retval last transfer size in byte
00743   */
00744 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00745 {
00746   return hhcd->hc[chnum].xfer_count;
00747 }
00748
00749 /**
00750   * @brief  Return the Host Channel state.
00751   * @param  hhcd: HCD handle
00752   * @param  chnum: Channel number.
00753   *         This parameter can be a value from 1 to 15
00754   * @retval Host channel state
00755   *          This parameter can be one of these values:
00756   *            HC_IDLE/
00757   *            HC_XFRC/
00758   *            HC_HALTED/
00759   *            HC_NYET/
00760   *            HC_NAK/
00761   *            HC_STALL/
00762   *            HC_XACTERR/
00763   *            HC_BBLERR/
00764   *            HC_DATATGLERR
00765   */
00766 HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00767 {
00768   return hhcd->hc[chnum].state;
00769 }
00770
00771 /**
00772   * @brief  Return the current Host frame number.
00773   * @param  hhcd: HCD handle
00774   * @retval Current Host frame number
00775   */
00776 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
00777 {
00778   return (USB_GetCurrentFrame(hhcd->Instance));
00779 }
00780
00781 /**
00782   * @brief  Return the Host enumeration speed.
00783   * @param  hhcd: HCD handle
00784   * @retval Enumeration speed
00785   */
00786 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
00787 {
00788   return (USB_GetHostSpeed(hhcd->Instance));
00789 }
00790
00791 /**
00792   * @}
00793   */
00794
00795 /**
00796   * @}
00797   */
00798
00799 /** @addtogroup HCD_Private_Functions
00800   * @{
00801   */
00802 /**
00803   * @brief  Handle Host Channel IN interrupt requests.
00804   * @param  hhcd: HCD handle
00805   * @param  chnum: Channel number.
00806   *         This parameter can be a value from 1 to 15
00807   * @retval none
00808   */
00809 static void HCD_HC_IN_IRQHandler   (HCD_HandleTypeDef *hhcd, uint8_t chnum)
00810 {
00811   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00812   uint32_t tmpreg = 0;
00813
00814   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
00815   {
00816     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
00817     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00818   }
00819   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
00820   {
00821     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
00822   }
00823
00824   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)
00825   {
00826     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00827     hhcd->hc[chnum].state = HC_STALL;
00828     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00829     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
00830     USB_HC_Halt(hhcd->Instance, chnum);
00831   }
00832   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
00833   {
00834     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00835     USB_HC_Halt(hhcd->Instance, chnum);
00836     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00837     hhcd->hc[chnum].state = HC_DATATGLERR;
00838     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
00839   }
00840
00841   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
00842   {
00843     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00844     USB_HC_Halt(hhcd->Instance, chnum);
00845     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
00846   }
00847
00848   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
00849   {
00850
00851     if (hhcd->Init.dma_enable)
00852     {
00853       hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
00854                                (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
00855     }
00856
00857     hhcd->hc[chnum].state = HC_XFRC;
00858     hhcd->hc[chnum].ErrCnt = 0;
00859     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
00860
00861
00862     if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
00863         (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
00864     {
00865       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00866       USB_HC_Halt(hhcd->Instance, chnum);
00867       __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00868
00869     }
00870     else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
00871     {
00872       USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
00873       hhcd->hc[chnum].urb_state = URB_DONE;
00874       HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
00875     }
00876     hhcd->hc[chnum].toggle_in ^= 1;
00877
00878   }
00879   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
00880   {
00881     __HAL_HCD_MASK_HALT_HC_INT(chnum);
00882
00883     if(hhcd->hc[chnum].state == HC_XFRC)
00884     {
00885       hhcd->hc[chnum].urb_state  = URB_DONE;
00886     }
00887
00888     else if (hhcd->hc[chnum].state == HC_STALL)
00889     {
00890       hhcd->hc[chnum].urb_state  = URB_STALL;
00891     }
00892
00893     else if((hhcd->hc[chnum].state == HC_XACTERR) ||
00894             (hhcd->hc[chnum].state == HC_DATATGLERR))
00895     {
00896       if(hhcd->hc[chnum].ErrCnt++ > 3)
00897       {
00898         hhcd->hc[chnum].ErrCnt = 0;
00899         hhcd->hc[chnum].urb_state = URB_ERROR;
00900       }
00901       else
00902       {
00903         hhcd->hc[chnum].urb_state = URB_NOTREADY;
00904       }
00905
00906       /* re-activate the channel  */
00907       tmpreg = USBx_HC(chnum)->HCCHAR;
00908       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
00909       tmpreg |= USB_OTG_HCCHAR_CHENA;
00910       USBx_HC(chnum)->HCCHAR = tmpreg;
00911     }
00912     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
00913     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
00914   }
00915
00916   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
00917   {
00918     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00919      hhcd->hc[chnum].ErrCnt++;
00920      hhcd->hc[chnum].state = HC_XACTERR;
00921      USB_HC_Halt(hhcd->Instance, chnum);
00922      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
00923   }
00924   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
00925   {
00926     if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
00927     {
00928       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00929       USB_HC_Halt(hhcd->Instance, chnum);
00930     }
00931
00932    /* Clear the NAK flag before re-enabling the channel for new IN request */
00933     hhcd->hc[chnum].state = HC_NAK;
00934     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00935
00936     if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
00937          (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
00938     {
00939       /* re-activate the channel  */
00940       USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
00941       USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
00942
00943     }
00944   }
00945 }
00946
00947 /**
00948   * @brief  Handle Host Channel OUT interrupt requests.
00949   * @param  hhcd: HCD handle
00950   * @param  chnum: Channel number.
00951   *         This parameter can be a value from 1 to 15
00952   * @retval none
00953   */
00954 static void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)
00955 {
00956   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00957   uint32_t tmpreg = 0;
00958
00959   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
00960   {
00961     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
00962     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00963   }
00964   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
00965   {
00966     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
00967
00968     if( hhcd->hc[chnum].do_ping == 1)
00969     {
00970       hhcd->hc[chnum].state = HC_NYET;
00971       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00972       USB_HC_Halt(hhcd->Instance, chnum);
00973       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
00974     }
00975   }
00976
00977   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NYET)
00978   {
00979     hhcd->hc[chnum].state = HC_NYET;
00980     hhcd->hc[chnum].ErrCnt= 0;
00981     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00982     USB_HC_Halt(hhcd->Instance, chnum);
00983     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
00984
00985   }
00986
00987   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
00988   {
00989     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00990     USB_HC_Halt(hhcd->Instance, chnum);
00991     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
00992   }
00993
00994   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
00995   {
00996       hhcd->hc[chnum].ErrCnt = 0;
00997     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00998     USB_HC_Halt(hhcd->Instance, chnum);
00999     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
01000     hhcd->hc[chnum].state = HC_XFRC;
01001
01002   }
01003
01004   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)
01005   {
01006     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
01007     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01008     USB_HC_Halt(hhcd->Instance, chnum);
01009     hhcd->hc[chnum].state = HC_STALL;
01010   }
01011
01012   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
01013   {
01014     hhcd->hc[chnum].ErrCnt = 0;
01015     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01016     USB_HC_Halt(hhcd->Instance, chnum);
01017     hhcd->hc[chnum].state = HC_NAK;
01018     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
01019   }
01020
01021   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
01022   {
01023     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01024     USB_HC_Halt(hhcd->Instance, chnum);
01025     hhcd->hc[chnum].state = HC_XACTERR;
01026      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
01027   }
01028
01029   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
01030   {
01031     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01032     USB_HC_Halt(hhcd->Instance, chnum);
01033     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
01034     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
01035     hhcd->hc[chnum].state = HC_DATATGLERR;
01036   }
01037
01038
01039   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
01040   {
01041     __HAL_HCD_MASK_HALT_HC_INT(chnum);
01042
01043     if(hhcd->hc[chnum].state == HC_XFRC)
01044     {
01045       hhcd->hc[chnum].urb_state  = URB_DONE;
01046       if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
01047       {
01048         hhcd->hc[chnum].toggle_out ^= 1;
01049       }
01050     }
01051     else if (hhcd->hc[chnum].state == HC_NAK)
01052     {
01053       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
01054     }
01055
01056     else if (hhcd->hc[chnum].state == HC_NYET)
01057     {
01058       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
01059       hhcd->hc[chnum].do_ping = 0;
01060     }
01061
01062     else if (hhcd->hc[chnum].state == HC_STALL)
01063     {
01064       hhcd->hc[chnum].urb_state  = URB_STALL;
01065     }
01066
01067     else if((hhcd->hc[chnum].state == HC_XACTERR) ||
01068             (hhcd->hc[chnum].state == HC_DATATGLERR))
01069     {
01070       if(hhcd->hc[chnum].ErrCnt++ > 3)
01071       {
01072         hhcd->hc[chnum].ErrCnt = 0;
01073         hhcd->hc[chnum].urb_state = URB_ERROR;
01074       }
01075       else
01076       {
01077         hhcd->hc[chnum].urb_state = URB_NOTREADY;
01078       }
01079
01080       /* re-activate the channel  */
01081       tmpreg = USBx_HC(chnum)->HCCHAR;
01082       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01083       tmpreg |= USB_OTG_HCCHAR_CHENA;
01084       USBx_HC(chnum)->HCCHAR = tmpreg;
01085     }
01086
01087     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
01088     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
01089   }
01090 }
01091
01092 /**
01093   * @brief  Handle Rx Queue Level interrupt requests.
01094   * @param  hhcd: HCD handle
01095   * @retval none
01096   */
01097 static void HCD_RXQLVL_IRQHandler  (HCD_HandleTypeDef *hhcd)
01098 {
01099   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01100   uint8_t channelnum =0;
01101   uint32_t pktsts;
01102   uint32_t pktcnt;
01103   uint32_t temp = 0;
01104   uint32_t tmpreg = 0;
01105
01106   temp = hhcd->Instance->GRXSTSP ;
01107   channelnum = temp &  USB_OTG_GRXSTSP_EPNUM;
01108   pktsts = (temp &  USB_OTG_GRXSTSP_PKTSTS) >> 17;
01109   pktcnt = (temp &  USB_OTG_GRXSTSP_BCNT) >> 4;
01110
01111   switch (pktsts)
01112   {
01113   case GRXSTS_PKTSTS_IN:
01114     /* Read the data into the Host buffer. */
01115     if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void  *)0))
01116     {
01117
01118       USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
01119
01120       /*manage multiple Xfer */
01121       hhcd->hc[channelnum].xfer_buff += pktcnt;
01122       hhcd->hc[channelnum].xfer_count  += pktcnt;
01123
01124       if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
01125       {
01126         /* re-activate the channel when more packets are expected */
01127         tmpreg = USBx_HC(channelnum)->HCCHAR;
01128         tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01129         tmpreg |= USB_OTG_HCCHAR_CHENA;
01130         USBx_HC(channelnum)->HCCHAR = tmpreg;
01131         hhcd->hc[channelnum].toggle_in ^= 1;
01132       }
01133     }
01134     break;
01135
01136   case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
01137     break;
01138   case GRXSTS_PKTSTS_IN_XFER_COMP:
01139   case GRXSTS_PKTSTS_CH_HALTED:
01140   default:
01141     break;
01142   }
01143 }
01144
01145 /**
01146   * @brief  Handle Host Port interrupt requests.
01147   * @param  hhcd: HCD handle
01148   * @retval None
01149   */
01150 static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
01151 {
01152   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01153   __IO uint32_t hprt0, hprt0_dup;
01154
01155   /* Handle Host Port Interrupts */
01156   hprt0 = USBx_HPRT0;
01157   hprt0_dup = USBx_HPRT0;
01158
01159   hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
01160                  USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
01161
01162   /* Check whether Port Connect Detected */
01163   if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
01164   {
01165     if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
01166     {
01167       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01168       HAL_HCD_Connect_Callback(hhcd);
01169     }
01170     hprt0_dup  |= USB_OTG_HPRT_PCDET;
01171
01172   }
01173
01174   /* Check whether Port Enable Changed */
01175   if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
01176   {
01177     hprt0_dup |= USB_OTG_HPRT_PENCHNG;
01178
01179     if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
01180     {
01181       if(hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
01182       {
01183         if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
01184         {
01185           USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
01186         }
01187         else
01188         {
01189           USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
01190         }
01191       }
01192       else
01193       {
01194         if(hhcd->Init.speed == HCD_SPEED_FULL)
01195         {
01196           USBx_HOST->HFIR = (uint32_t)60000;
01197         }
01198       }
01199       HAL_HCD_Connect_Callback(hhcd);
01200
01201       if(hhcd->Init.speed == HCD_SPEED_HIGH)
01202       {
01203         USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01204       }
01205     }
01206     else
01207     {
01208       /* Cleanup HPRT */
01209       USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
01210         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
01211
01212       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01213     }
01214   }
01215
01216   /* Check For an overcurrent */
01217   if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
01218   {
01219     hprt0_dup |= USB_OTG_HPRT_POCCHNG;
01220   }
01221
01222   /* Clear Port Interrupts */
01223   USBx_HPRT0 = hprt0_dup;
01224 }
01225
01226 /**
01227   * @}
01228   */
01229
01230 /**
01231   * @}
01232   */
01233
01234 #endif /* HAL_HCD_MODULE_ENABLED */
01235 /**
01236   * @}
01237   */
01238
01239 /**
01240   * @}
01241   */
01242
01243 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01244
01245 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_hcd.h Source File

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stm32l4xx_hal_hcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_hcd.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of HCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_HCD_H
00040 #define __STM32L4xx_HAL_HCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32l4xx_ll_usb.h"
00050
00051 /** @addtogroup STM32L4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup HCD
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup HCD_Exported_Types HCD Exported Types
00061   * @{
00062   */
00063
00064 /** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
00065   * @{
00066   */
00067 typedef enum
00068 {
00069   HAL_HCD_STATE_RESET    = 0x00,
00070   HAL_HCD_STATE_READY    = 0x01,
00071   HAL_HCD_STATE_ERROR    = 0x02,
00072   HAL_HCD_STATE_BUSY     = 0x03,
00073   HAL_HCD_STATE_TIMEOUT  = 0x04
00074 } HCD_StateTypeDef;
00075
00076 typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
00077 typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
00078 typedef USB_OTG_HCTypeDef       HCD_HCTypeDef ;
00079 typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
00080 typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef ;
00081 /**
00082   * @}
00083   */
00084
00085 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
00086   * @{
00087   */
00088 typedef struct
00089 {
00090   HCD_TypeDef               *Instance;  /*!< Register base address    */
00091   HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
00092   HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */
00093   HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
00094   __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
00095   void                      *pData;     /*!< Pointer Stack Handler    */
00096
00097 } HCD_HandleTypeDef;
00098 /**
00099   * @}
00100   */
00101
00102 /**
00103   * @}
00104   */
00105
00106 /* Exported constants --------------------------------------------------------*/
00107 /** @defgroup HCD_Exported_Constants HCD Exported Constants
00108   * @{
00109   */
00110
00111 /** @defgroup HCD_Speed HCD Speed
00112   * @{
00113   */
00114 #define HCD_SPEED_HIGH               0
00115 #define HCD_SPEED_LOW                2
00116 #define HCD_SPEED_FULL               3
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup HCD_PHY_Module HCD PHY Module
00122   * @{
00123   */
00124 #define HCD_PHY_EMBEDDED             1
00125 /**
00126   * @}
00127   */
00128
00129 /**
00130   * @}
00131   */
00132
00133 /* Exported macro ------------------------------------------------------------*/
00134 /** @defgroup HCD_Exported_Macros HCD Exported Macros
00135  *  @brief macros to handle interrupts and specific clock configurations
00136  * @{
00137  */
00138 #define __HAL_HCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
00139 #define __HAL_HCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
00140
00141 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00142 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
00143 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
00144
00145 #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
00146 #define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
00147 #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
00148 #define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
00149 #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
00150 /**
00151   * @}
00152   */
00153
00154 /* Exported functions --------------------------------------------------------*/
00155 /** @addtogroup HCD_Exported_Functions HCD Exported Functions
00156   * @{
00157   */
00158
00159 /* Initialization/de-initialization functions  ********************************/
00160 /** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00161   * @{
00162   */
00163 HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
00164 HAL_StatusTypeDef      HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
00165 HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00166                                   uint8_t ch_num,
00167                                   uint8_t epnum,
00168                                   uint8_t dev_address,
00169                                   uint8_t speed,
00170                                   uint8_t ep_type,
00171                                   uint16_t mps);
00172
00173 HAL_StatusTypeDef       HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
00174                                   uint8_t ch_num);
00175
00176 void            HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
00177 void            HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
00178 /**
00179   * @}
00180   */
00181
00182 /* I/O operation functions  ***************************************************/
00183 /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
00184   * @{
00185   */
00186 HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00187                                                  uint8_t pipe,
00188                                                  uint8_t direction ,
00189                                                  uint8_t ep_type,
00190                                                  uint8_t token,
00191                                                  uint8_t* pbuff,
00192                                                  uint16_t length,
00193                                                  uint8_t do_ping);
00194
00195  /* Non-Blocking mode: Interrupt */
00196 void             HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
00197 void             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
00198 void             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
00199 void             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
00200 void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
00201                                                             uint8_t chnum,
00202                                                             HCD_URBStateTypeDef urb_state);
00203 /**
00204   * @}
00205   */
00206
00207 /* Peripheral Control functions  **********************************************/
00208 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
00209   * @{
00210   */
00211 HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
00212 HAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
00213 HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
00214 /**
00215   * @}
00216   */
00217
00218 /* Peripheral State functions  ************************************************/
00219 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
00220   * @{
00221   */
00222 HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
00223 HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00224 uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00225 HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00226 uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
00227 uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
00228 /**
00229   * @}
00230   */
00231
00232 /**
00233   * @}
00234   */
00235
00236 /* Private macros ------------------------------------------------------------*/
00237 /** @defgroup HCD_Private_Macros HCD Private Macros
00238  * @{
00239  */
00240
00241 /**
00242   * @}
00243   */
00244
00245 /**
00246   * @}
00247   */
00248
00249 /**
00250   * @}
00251   */
00252
00253 #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00254
00255 #ifdef __cplusplus
00256 }
00257 #endif
00258
00259 #endif /* __STM32L4xx_HAL_HCD_H */
00260
00261 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_i2c.c Source File

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stm32l4xx_hal_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   I2C HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and Errors functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019     The I2C HAL driver can be used as follows:
00020
00021     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00022         I2C_HandleTypeDef  hi2c;
00023
00024     (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
00025         (##) Enable the I2Cx interface clock
00026         (##) I2C pins configuration
00027             (+++) Enable the clock for the I2C GPIOs
00028             (+++) Configure I2C pins as alternate function open-drain
00029         (##) NVIC configuration if you need to use interrupt process
00030             (+++) Configure the I2Cx interrupt priority
00031             (+++) Enable the NVIC I2C IRQ Channel
00032         (##) DMA Configuration if you need to use DMA process
00033             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
00034             (+++) Enable the DMAx interface clock using
00035             (+++) Configure the DMA handle parameters
00036             (+++) Configure the DMA Tx or Rx channel
00037             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00039                   the DMA Tx or Rx channel
00040
00041     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
00042         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
00043
00044     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
00045         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
00046
00047     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
00048
00049     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00050
00051     *** Polling mode IO operation ***
00052     =================================
00053     [..]
00054       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
00055       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
00056       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
00057       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
00058
00059     *** Polling mode IO MEM operation ***
00060     =====================================
00061     [..]
00062       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
00063       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
00064
00065
00066     *** Interrupt mode IO operation ***
00067     ===================================
00068     [..]
00069       (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
00070       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00071            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00072       (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
00073       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00074            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00075       (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
00076       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00077            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00078       (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
00079       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00080            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00081       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00082            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00083       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00084       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00085            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00086       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00087            This action will inform Master to generate a Stop condition to discard the communication.
00088
00089
00090     *** Interrupt mode IO sequential operation ***
00091     ===================================
00092     [..]
00093       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
00094           when a direction change during transfer
00095     [..]
00096       (+) A specific option field manage the different steps of a sequential transfer
00097       (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
00098       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
00099       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
00100                             and data to transfer without a final stop condition
00101       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
00102                             and with new data to transfer if the direction change or manage only the new data to transfer
00103                             if no direction change and without a final stop condition in both cases
00104       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
00105                             and with new data to transfer if the direction change or manage only the new data to transfer
00106                             if no direction change and with a final stop condition in both cases
00107
00108       (+) Differents sequential I2C interfaces are listed below:
00109       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
00110       (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00111            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00112       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
00113       (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00114            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00115       (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00116       (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00117            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00118       (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
00119       (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
00120       (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
00121       (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
00122            add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
00123       (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
00124            add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
00125       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
00126       (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00127            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00128       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
00129       (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00130            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00131       (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00132            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00133       (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00134       (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00135            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00136       (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00137            This action will inform Master to generate a Stop condition to discard the communication.
00138
00139     *** Interrupt mode IO MEM operation ***
00140     =======================================
00141     [..]
00142       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
00143           HAL_I2C_Mem_Write_IT()
00144       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
00145            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00146       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
00147           HAL_I2C_Mem_Read_IT()
00148       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
00149            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00150       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00151            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00152
00153     *** DMA mode IO operation ***
00154     ==============================
00155     [..]
00156       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
00157           HAL_I2C_Master_Transmit_DMA()
00158       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00159            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00160       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
00161           HAL_I2C_Master_Receive_DMA()
00162       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00163            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00164       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
00165           HAL_I2C_Slave_Transmit_DMA()
00166       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00167            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00168       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
00169           HAL_I2C_Slave_Receive_DMA()
00170       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00171            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00172       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00173            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00174       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00175       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00176            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00177       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00178            This action will inform Master to generate a Stop condition to discard the communication.
00179
00180     *** DMA mode IO MEM operation ***
00181     =================================
00182     [..]
00183       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
00184           HAL_I2C_Mem_Write_DMA()
00185       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
00186            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00187       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
00188           HAL_I2C_Mem_Read_DMA()
00189       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
00190            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00191       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00192            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00193
00194
00195      *** I2C HAL driver macros list ***
00196      ==================================
00197      [..]
00198        Below the list of most used macros in I2C HAL driver.
00199
00200       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
00201       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
00202       (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
00203       (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
00204       (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
00205       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00206       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00207
00208      [..]
00209        (@) You can refer to the I2C HAL driver header file for more useful macros
00210
00211   @endverbatim
00212   ******************************************************************************
00213   * @attention
00214   *
00215   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00216   *
00217   * Redistribution and use in source and binary forms, with or without modification,
00218   * are permitted provided that the following conditions are met:
00219   *   1. Redistributions of source code must retain the above copyright notice,
00220   *      this list of conditions and the following disclaimer.
00221   *   2. Redistributions in binary form must reproduce the above copyright notice,
00222   *      this list of conditions and the following disclaimer in the documentation
00223   *      and/or other materials provided with the distribution.
00224   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00225   *      may be used to endorse or promote products derived from this software
00226   *      without specific prior written permission.
00227   *
00228   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00229   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00230   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00231   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00232   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00233   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00234   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00235   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00236   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00237   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00238   *
00239   ******************************************************************************
00240   */
00241
00242 /* Includes ------------------------------------------------------------------*/
00243 #include "stm32l4xx_hal.h"
00244
00245 /** @addtogroup STM32L4xx_HAL_Driver
00246   * @{
00247   */
00248
00249 /** @defgroup I2C I2C
00250   * @brief I2C HAL module driver
00251   * @{
00252   */
00253
00254 #ifdef HAL_I2C_MODULE_ENABLED
00255
00256 /* Private typedef -----------------------------------------------------------*/
00257 /* Private define ------------------------------------------------------------*/
00258
00259 /** @defgroup I2C_Private_Define I2C Private Define
00260   * @{
00261   */
00262 #define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
00263 #define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
00264 #define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
00265 #define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
00266 #define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
00267 #define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
00268 #define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
00269 #define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
00270 #define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
00271 #define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
00272
00273 #define MAX_NBYTE_SIZE      255U
00274 #define SlaveAddr_SHIFT     7U
00275 #define SlaveAddr_MSK       0x06U
00276
00277 /* Private define for @ref PreviousState usage */
00278 #define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits            */
00279 #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
00280 #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00281 #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00282 #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
00283 #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00284 #define I2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
00285 #define I2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
00286
00287
00288 /* Private define to centralize the enable/disable of Interrupts */
00289 #define I2C_XFER_TX_IT          (0x00000001U)
00290 #define I2C_XFER_RX_IT          (0x00000002U)
00291 #define I2C_XFER_LISTEN_IT      (0x00000004U)
00292
00293 #define I2C_XFER_ERROR_IT       (0x00000011U)
00294 #define I2C_XFER_CPLT_IT        (0x00000012U)
00295 #define I2C_XFER_RELOAD_IT      (0x00000012U)
00296 /**
00297   * @}
00298   */
00299
00300 /* Private macro -------------------------------------------------------------*/
00301 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX)   ? \
00302                                             ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \
00303                                             ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR)))
00304
00305 /* Private variables ---------------------------------------------------------*/
00306 /* Private function prototypes -----------------------------------------------*/
00307
00308 /** @defgroup I2C_Private_Functions I2C Private Functions
00309   * @{
00310   */
00311 /* Private functions to handle DMA transfer */
00312 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00313 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00314 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00315 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00316 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00317 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
00318
00319 /* Private functions to handle IT transfer */
00320 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00321 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
00322 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
00323 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00324 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00325 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00326 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
00327
00328 /* Private functions to handle IT transfer */
00329 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00330 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00331
00332 /* Private functions for I2C transfer IRQ handler */
00333 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00334 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00335 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00336 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00337
00338 /* Private functions to handle flags during polling transfer */
00339 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
00340 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00341 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00342 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00343 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00344
00345 /* Private functions to centralize the enable/disable of Interrupts */
00346 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00347 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00348
00349 /* Private functions to flush TXDR register */
00350 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
00351
00352 /* Private functions to handle  start, restart or stop a transfer */
00353 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00354 /**
00355   * @}
00356   */
00357
00358 /* Exported functions --------------------------------------------------------*/
00359
00360 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00361   * @{
00362   */
00363
00364 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00365  *  @brief    Initialization and Configuration functions
00366  *
00367 @verbatim
00368  ===============================================================================
00369               ##### Initialization and de-initialization functions #####
00370  ===============================================================================
00371     [..]  This subsection provides a set of functions allowing to initialize and
00372           deinitialize the I2Cx peripheral:
00373
00374       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00375           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00376
00377       (+) Call the function HAL_I2C_Init() to configure the selected device with
00378           the selected configuration:
00379         (++) Clock Timing
00380         (++) Own Address 1
00381         (++) Addressing mode (Master, Slave)
00382         (++) Dual Addressing mode
00383         (++) Own Address 2
00384         (++) Own Address 2 Mask
00385         (++) General call mode
00386         (++) Nostretch mode
00387
00388       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00389           of the selected I2Cx peripheral.
00390
00391 @endverbatim
00392   * @{
00393   */
00394
00395 /**
00396   * @brief  Initializes the I2C according to the specified parameters
00397   *         in the I2C_InitTypeDef and initialize the associated handle.
00398   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00399   *                the configuration information for the specified I2C.
00400   * @retval HAL status
00401   */
00402 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00403 {
00404   /* Check the I2C handle allocation */
00405   if(hi2c == NULL)
00406   {
00407     return HAL_ERROR;
00408   }
00409
00410   /* Check the parameters */
00411   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00412   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00413   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00414   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00415   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00416   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
00417   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00418   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00419
00420   if(hi2c->State == HAL_I2C_STATE_RESET)
00421   {
00422     /* Allocate lock resource and initialize it */
00423     hi2c->Lock = HAL_UNLOCKED;
00424
00425     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00426     HAL_I2C_MspInit(hi2c);
00427   }
00428
00429   hi2c->State = HAL_I2C_STATE_BUSY;
00430
00431   /* Disable the selected I2C peripheral */
00432   __HAL_I2C_DISABLE(hi2c);
00433
00434   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
00435   /* Configure I2Cx: Frequency range */
00436   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
00437
00438   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00439   /* Configure I2Cx: Own Address1 and ack own address1 mode */
00440   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00441   if(hi2c->Init.OwnAddress1 != 0U)
00442   {
00443     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
00444     {
00445       hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
00446     }
00447     else /* I2C_ADDRESSINGMODE_10BIT */
00448     {
00449       hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
00450     }
00451   }
00452
00453   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00454   /* Configure I2Cx: Addressing Master mode */
00455   if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00456   {
00457     hi2c->Instance->CR2 = (I2C_CR2_ADD10);
00458   }
00459   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
00460   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00461
00462   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00463   /* Configure I2Cx: Dual mode and Own Address2 */
00464   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
00465
00466   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00467   /* Configure I2Cx: Generalcall and NoStretch mode */
00468   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00469
00470   /* Enable the selected I2C peripheral */
00471   __HAL_I2C_ENABLE(hi2c);
00472
00473   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00474   hi2c->State = HAL_I2C_STATE_READY;
00475   hi2c->PreviousState = I2C_STATE_NONE;
00476   hi2c->Mode = HAL_I2C_MODE_NONE;
00477
00478   return HAL_OK;
00479 }
00480
00481 /**
00482   * @brief  DeInitialize the I2C peripheral.
00483   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00484   *                the configuration information for the specified I2C.
00485   * @retval HAL status
00486   */
00487 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00488 {
00489   /* Check the I2C handle allocation */
00490   if(hi2c == NULL)
00491   {
00492     return HAL_ERROR;
00493   }
00494
00495   /* Check the parameters */
00496   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00497
00498   hi2c->State = HAL_I2C_STATE_BUSY;
00499
00500   /* Disable the I2C Peripheral Clock */
00501   __HAL_I2C_DISABLE(hi2c);
00502
00503   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00504   HAL_I2C_MspDeInit(hi2c);
00505
00506   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00507   hi2c->State = HAL_I2C_STATE_RESET;
00508   hi2c->PreviousState = I2C_STATE_NONE;
00509   hi2c->Mode = HAL_I2C_MODE_NONE;
00510
00511   /* Release Lock */
00512   __HAL_UNLOCK(hi2c);
00513
00514   return HAL_OK;
00515 }
00516
00517 /**
00518   * @brief Initialize the I2C MSP.
00519   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00520   *                the configuration information for the specified I2C.
00521   * @retval None
00522   */
00523 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00524 {
00525   /* Prevent unused argument(s) compilation warning */
00526   UNUSED(hi2c);
00527
00528   /* NOTE : This function should not be modified, when the callback is needed,
00529             the HAL_I2C_MspInit could be implemented in the user file
00530    */
00531 }
00532
00533 /**
00534   * @brief DeInitialize the I2C MSP.
00535   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00536   *                the configuration information for the specified I2C.
00537   * @retval None
00538   */
00539 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00540 {
00541   /* Prevent unused argument(s) compilation warning */
00542   UNUSED(hi2c);
00543
00544   /* NOTE : This function should not be modified, when the callback is needed,
00545             the HAL_I2C_MspDeInit could be implemented in the user file
00546    */
00547 }
00548
00549 /**
00550   * @}
00551   */
00552
00553 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
00554  *  @brief   Data transfers functions
00555  *
00556 @verbatim
00557  ===============================================================================
00558                       ##### IO operation functions #####
00559  ===============================================================================
00560     [..]
00561     This subsection provides a set of functions allowing to manage the I2C data
00562     transfers.
00563
00564     (#) There are two modes of transfer:
00565        (++) Blocking mode : The communication is performed in the polling mode.
00566             The status of all data processing is returned by the same function
00567             after finishing transfer.
00568        (++) No-Blocking mode : The communication is performed using Interrupts
00569             or DMA. These functions return the status of the transfer startup.
00570             The end of the data processing will be indicated through the
00571             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
00572             using DMA mode.
00573
00574     (#) Blocking mode functions are :
00575         (++) HAL_I2C_Master_Transmit()
00576         (++) HAL_I2C_Master_Receive()
00577         (++) HAL_I2C_Slave_Transmit()
00578         (++) HAL_I2C_Slave_Receive()
00579         (++) HAL_I2C_Mem_Write()
00580         (++) HAL_I2C_Mem_Read()
00581         (++) HAL_I2C_IsDeviceReady()
00582
00583     (#) No-Blocking mode functions with Interrupt are :
00584         (++) HAL_I2C_Master_Transmit_IT()
00585         (++) HAL_I2C_Master_Receive_IT()
00586         (++) HAL_I2C_Slave_Transmit_IT()
00587         (++) HAL_I2C_Slave_Receive_IT()
00588         (++) HAL_I2C_Mem_Write_IT()
00589         (++) HAL_I2C_Mem_Read_IT()
00590
00591     (#) No-Blocking mode functions with DMA are :
00592         (++) HAL_I2C_Master_Transmit_DMA()
00593         (++) HAL_I2C_Master_Receive_DMA()
00594         (++) HAL_I2C_Slave_Transmit_DMA()
00595         (++) HAL_I2C_Slave_Receive_DMA()
00596         (++) HAL_I2C_Mem_Write_DMA()
00597         (++) HAL_I2C_Mem_Read_DMA()
00598
00599     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00600         (++) HAL_I2C_MemTxCpltCallback()
00601         (++) HAL_I2C_MemRxCpltCallback()
00602         (++) HAL_I2C_MasterTxCpltCallback()
00603         (++) HAL_I2C_MasterRxCpltCallback()
00604         (++) HAL_I2C_SlaveTxCpltCallback()
00605         (++) HAL_I2C_SlaveRxCpltCallback()
00606         (++) HAL_I2C_ErrorCallback()
00607
00608 @endverbatim
00609   * @{
00610   */
00611
00612 /**
00613   * @brief  Transmits in master mode an amount of data in blocking mode.
00614   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00615   *                the configuration information for the specified I2C.
00616   * @param  DevAddress Target device address
00617   * @param  pData Pointer to data buffer
00618   * @param  Size Amount of data to be sent
00619   * @param  Timeout Timeout duration
00620   * @retval HAL status
00621   */
00622 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00623 {
00624   uint32_t tickstart = 0U;
00625
00626   if(hi2c->State == HAL_I2C_STATE_READY)
00627   {
00628     /* Process Locked */
00629     __HAL_LOCK(hi2c);
00630
00631     /* Init tickstart for timeout management*/
00632     tickstart = HAL_GetTick();
00633
00634     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
00635     {
00636       return HAL_TIMEOUT;
00637     }
00638
00639     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
00640     hi2c->Mode      = HAL_I2C_MODE_MASTER;
00641     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00642
00643     /* Prepare transfer parameters */
00644     hi2c->pBuffPtr  = pData;
00645     hi2c->XferCount = Size;
00646     hi2c->XferISR   = NULL;
00647
00648     /* Send Slave Address */
00649     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
00650     if(hi2c->XferCount > MAX_NBYTE_SIZE)
00651     {
00652       hi2c->XferSize = MAX_NBYTE_SIZE;
00653       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
00654     }
00655     else
00656     {
00657       hi2c->XferSize = hi2c->XferCount;
00658       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
00659     }
00660
00661     while(hi2c->XferCount > 0U)
00662     {
00663       /* Wait until TXIS flag is set */
00664       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00665       {
00666         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00667         {
00668           return HAL_ERROR;
00669         }
00670         else
00671         {
00672           return HAL_TIMEOUT;
00673         }
00674       }
00675       /* Write data to TXDR */
00676       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
00677       hi2c->XferCount--;
00678       hi2c->XferSize--;
00679
00680       if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
00681       {
00682         /* Wait until TCR flag is set */
00683         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
00684         {
00685           return HAL_TIMEOUT;
00686         }
00687
00688         if(hi2c->XferCount > MAX_NBYTE_SIZE)
00689         {
00690           hi2c->XferSize = MAX_NBYTE_SIZE;
00691           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
00692         }
00693         else
00694         {
00695           hi2c->XferSize = hi2c->XferCount;
00696           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
00697         }
00698       }
00699     }
00700
00701     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00702     /* Wait until STOPF flag is set */
00703     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00704     {
00705       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00706       {
00707         return HAL_ERROR;
00708       }
00709       else
00710       {
00711         return HAL_TIMEOUT;
00712       }
00713     }
00714
00715     /* Clear STOP Flag */
00716     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00717
00718     /* Clear Configuration Register 2 */
00719     I2C_RESET_CR2(hi2c);
00720
00721     hi2c->State = HAL_I2C_STATE_READY;
00722     hi2c->Mode  = HAL_I2C_MODE_NONE;
00723
00724     /* Process Unlocked */
00725     __HAL_UNLOCK(hi2c);
00726
00727     return HAL_OK;
00728   }
00729   else
00730   {
00731     return HAL_BUSY;
00732   }
00733 }
00734
00735 /**
00736   * @brief  Receives in master mode an amount of data in blocking mode.
00737   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00738   *                the configuration information for the specified I2C.
00739   * @param  DevAddress Target device address
00740   * @param  pData Pointer to data buffer
00741   * @param  Size Amount of data to be sent
00742   * @param  Timeout Timeout duration
00743   * @retval HAL status
00744   */
00745 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00746 {
00747   uint32_t tickstart = 0U;
00748
00749   if(hi2c->State == HAL_I2C_STATE_READY)
00750   {
00751     /* Process Locked */
00752     __HAL_LOCK(hi2c);
00753
00754     /* Init tickstart for timeout management*/
00755     tickstart = HAL_GetTick();
00756
00757     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
00758     {
00759       return HAL_TIMEOUT;
00760     }
00761
00762     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
00763     hi2c->Mode      = HAL_I2C_MODE_MASTER;
00764     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00765
00766     /* Prepare transfer parameters */
00767     hi2c->pBuffPtr  = pData;
00768     hi2c->XferCount = Size;
00769     hi2c->XferISR   = NULL;
00770
00771     /* Send Slave Address */
00772     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
00773     if(hi2c->XferCount > MAX_NBYTE_SIZE)
00774     {
00775       hi2c->XferSize = MAX_NBYTE_SIZE;
00776       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
00777     }
00778     else
00779     {
00780       hi2c->XferSize = hi2c->XferCount;
00781       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
00782     }
00783
00784     while(hi2c->XferCount > 0U)
00785     {
00786       /* Wait until RXNE flag is set */
00787       if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00788       {
00789         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00790         {
00791           return HAL_ERROR;
00792         }
00793         else
00794         {
00795           return HAL_TIMEOUT;
00796         }
00797       }
00798
00799       /* Read data from RXDR */
00800       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
00801       hi2c->XferSize--;
00802       hi2c->XferCount--;
00803
00804       if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
00805       {
00806         /* Wait until TCR flag is set */
00807         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
00808         {
00809           return HAL_TIMEOUT;
00810         }
00811
00812         if(hi2c->XferCount > MAX_NBYTE_SIZE)
00813         {
00814           hi2c->XferSize = MAX_NBYTE_SIZE;
00815           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
00816         }
00817         else
00818         {
00819           hi2c->XferSize = hi2c->XferCount;
00820           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
00821         }
00822       }
00823     }
00824
00825     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00826     /* Wait until STOPF flag is set */
00827     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00828     {
00829       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00830       {
00831         return HAL_ERROR;
00832       }
00833       else
00834       {
00835         return HAL_TIMEOUT;
00836       }
00837     }
00838
00839     /* Clear STOP Flag */
00840     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00841
00842     /* Clear Configuration Register 2 */
00843     I2C_RESET_CR2(hi2c);
00844
00845     hi2c->State = HAL_I2C_STATE_READY;
00846     hi2c->Mode  = HAL_I2C_MODE_NONE;
00847
00848     /* Process Unlocked */
00849     __HAL_UNLOCK(hi2c);
00850
00851     return HAL_OK;
00852   }
00853   else
00854   {
00855     return HAL_BUSY;
00856   }
00857 }
00858
00859 /**
00860   * @brief  Transmits in slave mode an amount of data in blocking mode.
00861   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00862   *                the configuration information for the specified I2C.
00863   * @param  pData Pointer to data buffer
00864   * @param  Size Amount of data to be sent
00865   * @param  Timeout Timeout duration
00866   * @retval HAL status
00867   */
00868 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00869 {
00870   uint32_t tickstart = 0U;
00871
00872   if(hi2c->State == HAL_I2C_STATE_READY)
00873   {
00874     if((pData == NULL) || (Size == 0U))
00875     {
00876       return  HAL_ERROR;
00877     }
00878     /* Process Locked */
00879     __HAL_LOCK(hi2c);
00880
00881     /* Init tickstart for timeout management*/
00882     tickstart = HAL_GetTick();
00883
00884     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
00885     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
00886     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00887
00888     /* Prepare transfer parameters */
00889     hi2c->pBuffPtr  = pData;
00890     hi2c->XferCount = Size;
00891     hi2c->XferISR   = NULL;
00892
00893     /* Enable Address Acknowledge */
00894     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
00895
00896     /* Wait until ADDR flag is set */
00897     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
00898     {
00899       /* Disable Address Acknowledge */
00900       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00901       return HAL_TIMEOUT;
00902     }
00903
00904     /* Clear ADDR flag */
00905     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
00906
00907     /* If 10bit addressing mode is selected */
00908     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00909     {
00910       /* Wait until ADDR flag is set */
00911       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
00912       {
00913         /* Disable Address Acknowledge */
00914         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00915         return HAL_TIMEOUT;
00916       }
00917
00918       /* Clear ADDR flag */
00919       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
00920     }
00921
00922     /* Wait until DIR flag is set Transmitter mode */
00923     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
00924     {
00925       /* Disable Address Acknowledge */
00926       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00927       return HAL_TIMEOUT;
00928     }
00929
00930     while(hi2c->XferCount > 0U)
00931     {
00932       /* Wait until TXIS flag is set */
00933       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00934       {
00935         /* Disable Address Acknowledge */
00936         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00937
00938         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00939         {
00940           return HAL_ERROR;
00941         }
00942         else
00943         {
00944           return HAL_TIMEOUT;
00945         }
00946       }
00947
00948       /* Write data to TXDR */
00949       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
00950       hi2c->XferCount--;
00951     }
00952
00953     /* Wait until STOP flag is set */
00954     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00955     {
00956       /* Disable Address Acknowledge */
00957       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00958
00959       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00960       {
00961         /* Normal use case for Transmitter mode */
00962         /* A NACK is generated to confirm the end of transfer */
00963         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00964       }
00965       else
00966       {
00967         return HAL_TIMEOUT;
00968       }
00969     }
00970
00971     /* Clear STOP flag */
00972     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
00973
00974     /* Wait until BUSY flag is reset */
00975     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
00976     {
00977       /* Disable Address Acknowledge */
00978       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00979       return HAL_TIMEOUT;
00980     }
00981
00982     /* Disable Address Acknowledge */
00983     hi2c->Instance->CR2 |= I2C_CR2_NACK;
00984
00985     hi2c->State = HAL_I2C_STATE_READY;
00986     hi2c->Mode  = HAL_I2C_MODE_NONE;
00987
00988     /* Process Unlocked */
00989     __HAL_UNLOCK(hi2c);
00990
00991     return HAL_OK;
00992   }
00993   else
00994   {
00995     return HAL_BUSY;
00996   }
00997 }
00998
00999 /**
01000   * @brief  Receive in slave mode an amount of data in blocking mode
01001   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01002   *                the configuration information for the specified I2C.
01003   * @param  pData Pointer to data buffer
01004   * @param  Size Amount of data to be sent
01005   * @param  Timeout Timeout duration
01006   * @retval HAL status
01007   */
01008 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01009 {
01010   uint32_t tickstart = 0U;
01011
01012   if(hi2c->State == HAL_I2C_STATE_READY)
01013   {
01014     if((pData == NULL) || (Size == 0U))
01015     {
01016       return  HAL_ERROR;
01017     }
01018     /* Process Locked */
01019     __HAL_LOCK(hi2c);
01020
01021     /* Init tickstart for timeout management*/
01022     tickstart = HAL_GetTick();
01023
01024     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01025     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01026     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01027
01028     /* Prepare transfer parameters */
01029     hi2c->pBuffPtr  = pData;
01030     hi2c->XferCount = Size;
01031     hi2c->XferISR   = NULL;
01032
01033     /* Enable Address Acknowledge */
01034     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01035
01036     /* Wait until ADDR flag is set */
01037     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01038     {
01039       /* Disable Address Acknowledge */
01040       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01041       return HAL_TIMEOUT;
01042     }
01043
01044     /* Clear ADDR flag */
01045     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
01046
01047     /* Wait until DIR flag is reset Receiver mode */
01048     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
01049     {
01050       /* Disable Address Acknowledge */
01051       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01052       return HAL_TIMEOUT;
01053     }
01054
01055     while(hi2c->XferCount > 0U)
01056     {
01057       /* Wait until RXNE flag is set */
01058       if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01059       {
01060         /* Disable Address Acknowledge */
01061         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01062
01063         /* Store Last receive data if any */
01064         if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
01065         {
01066           /* Read data from RXDR */
01067           (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01068           hi2c->XferCount--;
01069         }
01070
01071         if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
01072         {
01073           return HAL_TIMEOUT;
01074         }
01075         else
01076         {
01077           return HAL_ERROR;
01078         }
01079       }
01080
01081       /* Read data from RXDR */
01082       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01083       hi2c->XferCount--;
01084     }
01085
01086     /* Wait until STOP flag is set */
01087     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01088     {
01089       /* Disable Address Acknowledge */
01090       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01091
01092       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01093       {
01094         return HAL_ERROR;
01095       }
01096       else
01097       {
01098         return HAL_TIMEOUT;
01099       }
01100     }
01101
01102     /* Clear STOP flag */
01103     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
01104
01105     /* Wait until BUSY flag is reset */
01106     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01107     {
01108       /* Disable Address Acknowledge */
01109       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01110       return HAL_TIMEOUT;
01111     }
01112
01113     /* Disable Address Acknowledge */
01114     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01115
01116     hi2c->State = HAL_I2C_STATE_READY;
01117     hi2c->Mode  = HAL_I2C_MODE_NONE;
01118
01119     /* Process Unlocked */
01120     __HAL_UNLOCK(hi2c);
01121
01122     return HAL_OK;
01123   }
01124   else
01125   {
01126     return HAL_BUSY;
01127   }
01128 }
01129
01130 /**
01131   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
01132   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01133   *                the configuration information for the specified I2C.
01134   * @param  DevAddress Target device address
01135   * @param  pData Pointer to data buffer
01136   * @param  Size Amount of data to be sent
01137   * @retval HAL status
01138   */
01139 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01140 {
01141   uint32_t xfermode = 0U;
01142
01143   if(hi2c->State == HAL_I2C_STATE_READY)
01144   {
01145     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01146     {
01147       return HAL_BUSY;
01148     }
01149
01150     /* Process Locked */
01151     __HAL_LOCK(hi2c);
01152
01153     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01154     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01155     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01156
01157     /* Prepare transfer parameters */
01158     hi2c->pBuffPtr    = pData;
01159     hi2c->XferCount   = Size;
01160     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01161     hi2c->XferISR     = I2C_Master_ISR_IT;
01162
01163     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01164     {
01165       hi2c->XferSize = MAX_NBYTE_SIZE;
01166       xfermode = I2C_RELOAD_MODE;
01167     }
01168     else
01169     {
01170       hi2c->XferSize = hi2c->XferCount;
01171       xfermode = I2C_AUTOEND_MODE;
01172     }
01173
01174     /* Send Slave Address */
01175     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01176     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01177
01178     /* Process Unlocked */
01179     __HAL_UNLOCK(hi2c);
01180
01181     /* Note : The I2C interrupts must be enabled after unlocking current process
01182               to avoid the risk of I2C interrupt handle execution before current
01183               process unlock */
01184
01185     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01186     /* possible to enable all of these */
01187     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01188     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01189
01190     return HAL_OK;
01191   }
01192   else
01193   {
01194     return HAL_BUSY;
01195   }
01196 }
01197
01198 /**
01199   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
01200   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01201   *                the configuration information for the specified I2C.
01202   * @param  DevAddress Target device address
01203   * @param  pData Pointer to data buffer
01204   * @param  Size Amount of data to be sent
01205   * @retval HAL status
01206   */
01207 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01208 {
01209   uint32_t xfermode = 0U;
01210
01211   if(hi2c->State == HAL_I2C_STATE_READY)
01212   {
01213     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01214     {
01215       return HAL_BUSY;
01216     }
01217
01218     /* Process Locked */
01219     __HAL_LOCK(hi2c);
01220
01221     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01222     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01223     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01224
01225     /* Prepare transfer parameters */
01226     hi2c->pBuffPtr    = pData;
01227     hi2c->XferCount   = Size;
01228     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01229     hi2c->XferISR     = I2C_Master_ISR_IT;
01230
01231     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01232     {
01233       hi2c->XferSize = MAX_NBYTE_SIZE;
01234       xfermode = I2C_RELOAD_MODE;
01235     }
01236     else
01237     {
01238       hi2c->XferSize = hi2c->XferCount;
01239       xfermode = I2C_AUTOEND_MODE;
01240     }
01241
01242     /* Send Slave Address */
01243     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01244     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01245
01246     /* Process Unlocked */
01247     __HAL_UNLOCK(hi2c);
01248
01249     /* Note : The I2C interrupts must be enabled after unlocking current process
01250               to avoid the risk of I2C interrupt handle execution before current
01251               process unlock */
01252
01253     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01254     /* possible to enable all of these */
01255     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01256     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
01257
01258     return HAL_OK;
01259   }
01260   else
01261   {
01262     return HAL_BUSY;
01263   }
01264 }
01265
01266 /**
01267   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
01268   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01269   *                the configuration information for the specified I2C.
01270   * @param  pData Pointer to data buffer
01271   * @param  Size Amount of data to be sent
01272   * @retval HAL status
01273   */
01274 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01275 {
01276   if(hi2c->State == HAL_I2C_STATE_READY)
01277   {
01278     /* Process Locked */
01279     __HAL_LOCK(hi2c);
01280
01281     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01282     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01283     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01284
01285     /* Enable Address Acknowledge */
01286     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01287
01288     /* Prepare transfer parameters */
01289     hi2c->pBuffPtr    = pData;
01290     hi2c->XferCount   = Size;
01291     hi2c->XferSize    = hi2c->XferCount;
01292     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01293     hi2c->XferISR     = I2C_Slave_ISR_IT;
01294
01295     /* Process Unlocked */
01296     __HAL_UNLOCK(hi2c);
01297
01298     /* Note : The I2C interrupts must be enabled after unlocking current process
01299               to avoid the risk of I2C interrupt handle execution before current
01300               process unlock */
01301
01302     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01303     /* possible to enable all of these */
01304     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01305     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
01306
01307     return HAL_OK;
01308   }
01309   else
01310   {
01311     return HAL_BUSY;
01312   }
01313 }
01314
01315 /**
01316   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
01317   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01318   *                the configuration information for the specified I2C.
01319   * @param  pData Pointer to data buffer
01320   * @param  Size Amount of data to be sent
01321   * @retval HAL status
01322   */
01323 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01324 {
01325   if(hi2c->State == HAL_I2C_STATE_READY)
01326   {
01327     /* Process Locked */
01328     __HAL_LOCK(hi2c);
01329
01330     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01331     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01332     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01333
01334     /* Enable Address Acknowledge */
01335     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01336
01337     /* Prepare transfer parameters */
01338     hi2c->pBuffPtr    = pData;
01339     hi2c->XferCount   = Size;
01340     hi2c->XferSize    = hi2c->XferCount;
01341     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01342     hi2c->XferISR     = I2C_Slave_ISR_IT;
01343
01344     /* Process Unlocked */
01345     __HAL_UNLOCK(hi2c);
01346
01347     /* Note : The I2C interrupts must be enabled after unlocking current process
01348               to avoid the risk of I2C interrupt handle execution before current
01349               process unlock */
01350
01351     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01352     /* possible to enable all of these */
01353     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01354     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
01355
01356     return HAL_OK;
01357   }
01358   else
01359   {
01360     return HAL_BUSY;
01361   }
01362 }
01363
01364 /**
01365   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
01366   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01367   *                the configuration information for the specified I2C.
01368   * @param  DevAddress Target device address
01369   * @param  pData Pointer to data buffer
01370   * @param  Size Amount of data to be sent
01371   * @retval HAL status
01372   */
01373 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01374 {
01375   uint32_t xfermode = 0U;
01376
01377   if(hi2c->State == HAL_I2C_STATE_READY)
01378   {
01379     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01380     {
01381       return HAL_BUSY;
01382     }
01383
01384     /* Process Locked */
01385     __HAL_LOCK(hi2c);
01386
01387     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01388     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01389     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01390
01391     /* Prepare transfer parameters */
01392     hi2c->pBuffPtr    = pData;
01393     hi2c->XferCount   = Size;
01394     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01395     hi2c->XferISR     = I2C_Master_ISR_DMA;
01396
01397     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01398     {
01399       hi2c->XferSize = MAX_NBYTE_SIZE;
01400       xfermode = I2C_RELOAD_MODE;
01401     }
01402     else
01403     {
01404       hi2c->XferSize = hi2c->XferCount;
01405       xfermode = I2C_AUTOEND_MODE;
01406     }
01407
01408     if(hi2c->XferSize > 0U)
01409     {
01410       /* Set the I2C DMA transfer complete callback */
01411       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
01412
01413       /* Set the DMA error callback */
01414       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01415
01416       /* Set the unused DMA callbacks to NULL */
01417       hi2c->hdmatx->XferHalfCpltCallback = NULL;
01418       hi2c->hdmatx->XferAbortCallback = NULL;
01419
01420       /* Enable the DMA channel */
01421       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01422
01423       /* Send Slave Address */
01424       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01425       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01426
01427       /* Update XferCount value */
01428       hi2c->XferCount -= hi2c->XferSize;
01429
01430       /* Process Unlocked */
01431       __HAL_UNLOCK(hi2c);
01432
01433       /* Note : The I2C interrupts must be enabled after unlocking current process
01434                 to avoid the risk of I2C interrupt handle execution before current
01435                 process unlock */
01436       /* Enable ERR and NACK interrupts */
01437       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01438
01439       /* Enable DMA Request */
01440       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01441     }
01442     else
01443     {
01444       /* Update Transfer ISR function pointer */
01445       hi2c->XferISR = I2C_Master_ISR_IT;
01446
01447       /* Send Slave Address */
01448       /* Set NBYTES to write and generate START condition */
01449       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
01450
01451       /* Process Unlocked */
01452       __HAL_UNLOCK(hi2c);
01453
01454       /* Note : The I2C interrupts must be enabled after unlocking current process
01455                 to avoid the risk of I2C interrupt handle execution before current
01456                 process unlock */
01457       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01458       /* possible to enable all of these */
01459       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01460       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01461     }
01462
01463     return HAL_OK;
01464   }
01465   else
01466   {
01467     return HAL_BUSY;
01468   }
01469 }
01470
01471 /**
01472   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
01473   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01474   *                the configuration information for the specified I2C.
01475   * @param  DevAddress Target device address
01476   * @param  pData Pointer to data buffer
01477   * @param  Size Amount of data to be sent
01478   * @retval HAL status
01479   */
01480 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01481 {
01482   uint32_t xfermode = 0U;
01483
01484   if(hi2c->State == HAL_I2C_STATE_READY)
01485   {
01486     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01487     {
01488       return HAL_BUSY;
01489     }
01490
01491     /* Process Locked */
01492     __HAL_LOCK(hi2c);
01493
01494     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01495     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01496     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01497
01498     /* Prepare transfer parameters */
01499     hi2c->pBuffPtr    = pData;
01500     hi2c->XferCount   = Size;
01501     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01502     hi2c->XferISR     = I2C_Master_ISR_DMA;
01503
01504     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01505     {
01506       hi2c->XferSize = MAX_NBYTE_SIZE;
01507       xfermode = I2C_RELOAD_MODE;
01508     }
01509     else
01510     {
01511       hi2c->XferSize = hi2c->XferCount;
01512       xfermode = I2C_AUTOEND_MODE;
01513     }
01514
01515     if(hi2c->XferSize > 0U)
01516     {
01517       /* Set the I2C DMA transfer complete callback */
01518       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
01519
01520       /* Set the DMA error callback */
01521       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01522
01523       /* Set the unused DMA callbacks to NULL */
01524       hi2c->hdmarx->XferHalfCpltCallback = NULL;
01525       hi2c->hdmarx->XferAbortCallback = NULL;
01526
01527       /* Enable the DMA channel */
01528       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01529
01530       /* Send Slave Address */
01531       /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01532       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01533
01534       /* Update XferCount value */
01535       hi2c->XferCount -= hi2c->XferSize;
01536
01537       /* Process Unlocked */
01538       __HAL_UNLOCK(hi2c);
01539
01540       /* Note : The I2C interrupts must be enabled after unlocking current process
01541                 to avoid the risk of I2C interrupt handle execution before current
01542                 process unlock */
01543       /* Enable ERR and NACK interrupts */
01544       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01545
01546       /* Enable DMA Request */
01547       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
01548     }
01549     else
01550     {
01551       /* Update Transfer ISR function pointer */
01552       hi2c->XferISR = I2C_Master_ISR_IT;
01553
01554       /* Send Slave Address */
01555       /* Set NBYTES to read and generate START condition */
01556       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01557
01558       /* Process Unlocked */
01559       __HAL_UNLOCK(hi2c);
01560
01561       /* Note : The I2C interrupts must be enabled after unlocking current process
01562                 to avoid the risk of I2C interrupt handle execution before current
01563                 process unlock */
01564       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01565       /* possible to enable all of these */
01566       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01567       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01568     }
01569     return HAL_OK;
01570   }
01571   else
01572   {
01573     return HAL_BUSY;
01574   }
01575 }
01576
01577 /**
01578   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
01579   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01580   *                the configuration information for the specified I2C.
01581   * @param  pData Pointer to data buffer
01582   * @param  Size Amount of data to be sent
01583   * @retval HAL status
01584   */
01585 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01586 {
01587   if(hi2c->State == HAL_I2C_STATE_READY)
01588   {
01589     if((pData == NULL) || (Size == 0U))
01590     {
01591       return  HAL_ERROR;
01592     }
01593     /* Process Locked */
01594     __HAL_LOCK(hi2c);
01595
01596     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01597     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01598     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01599
01600     /* Prepare transfer parameters */
01601     hi2c->pBuffPtr    = pData;
01602     hi2c->XferCount   = Size;
01603     hi2c->XferSize    = hi2c->XferCount;
01604     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01605     hi2c->XferISR     = I2C_Slave_ISR_DMA;
01606
01607     /* Set the I2C DMA transfer complete callback */
01608     hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
01609
01610     /* Set the DMA error callback */
01611     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01612
01613     /* Set the unused DMA callbacks to NULL */
01614     hi2c->hdmatx->XferHalfCpltCallback = NULL;
01615     hi2c->hdmatx->XferAbortCallback = NULL;
01616
01617     /* Enable the DMA channel */
01618     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01619
01620     /* Enable Address Acknowledge */
01621     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01622
01623     /* Process Unlocked */
01624     __HAL_UNLOCK(hi2c);
01625
01626     /* Note : The I2C interrupts must be enabled after unlocking current process
01627               to avoid the risk of I2C interrupt handle execution before current
01628               process unlock */
01629     /* Enable ERR, STOP, NACK, ADDR interrupts */
01630     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
01631
01632     /* Enable DMA Request */
01633     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01634
01635     return HAL_OK;
01636   }
01637   else
01638   {
01639     return HAL_BUSY;
01640   }
01641 }
01642
01643 /**
01644   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
01645   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01646   *                the configuration information for the specified I2C.
01647   * @param  pData Pointer to data buffer
01648   * @param  Size Amount of data to be sent
01649   * @retval HAL status
01650   */
01651 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01652 {
01653   if(hi2c->State == HAL_I2C_STATE_READY)
01654   {
01655     if((pData == NULL) || (Size == 0U))
01656     {
01657       return  HAL_ERROR;
01658     }
01659     /* Process Locked */
01660     __HAL_LOCK(hi2c);
01661
01662     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01663     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01664     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01665
01666     /* Prepare transfer parameters */
01667     hi2c->pBuffPtr    = pData;
01668     hi2c->XferCount   = Size;
01669     hi2c->XferSize    = hi2c->XferCount;
01670     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01671     hi2c->XferISR     = I2C_Slave_ISR_DMA;
01672
01673     /* Set the I2C DMA transfer complete callback */
01674     hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
01675
01676     /* Set the DMA error callback */
01677     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01678
01679     /* Set the unused DMA callbacks to NULL */
01680     hi2c->hdmarx->XferHalfCpltCallback = NULL;
01681     hi2c->hdmarx->XferAbortCallback = NULL;
01682
01683     /* Enable the DMA channel */
01684     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01685
01686     /* Enable Address Acknowledge */
01687     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01688
01689     /* Process Unlocked */
01690     __HAL_UNLOCK(hi2c);
01691
01692     /* Note : The I2C interrupts must be enabled after unlocking current process
01693               to avoid the risk of I2C interrupt handle execution before current
01694               process unlock */
01695     /* Enable ERR, STOP, NACK, ADDR interrupts */
01696     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
01697
01698     /* Enable DMA Request */
01699     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
01700
01701     return HAL_OK;
01702   }
01703   else
01704   {
01705     return HAL_BUSY;
01706   }
01707 }
01708 /**
01709   * @brief  Write an amount of data in blocking mode to a specific memory address
01710   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01711   *                the configuration information for the specified I2C.
01712   * @param  DevAddress Target device address
01713   * @param  MemAddress Internal memory address
01714   * @param  MemAddSize Size of internal memory address
01715   * @param  pData Pointer to data buffer
01716   * @param  Size Amount of data to be sent
01717   * @param  Timeout Timeout duration
01718   * @retval HAL status
01719   */
01720 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01721 {
01722   uint32_t tickstart = 0U;
01723
01724   /* Check the parameters */
01725   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01726
01727   if(hi2c->State == HAL_I2C_STATE_READY)
01728   {
01729     if((pData == NULL) || (Size == 0U))
01730     {
01731       return  HAL_ERROR;
01732     }
01733
01734     /* Process Locked */
01735     __HAL_LOCK(hi2c);
01736
01737     /* Init tickstart for timeout management*/
01738     tickstart = HAL_GetTick();
01739
01740     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01741     {
01742       return HAL_TIMEOUT;
01743     }
01744
01745     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01746     hi2c->Mode      = HAL_I2C_MODE_MEM;
01747     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01748
01749     /* Prepare transfer parameters */
01750     hi2c->pBuffPtr  = pData;
01751     hi2c->XferCount = Size;
01752     hi2c->XferISR   = NULL;
01753
01754     /* Send Slave Address and Memory Address */
01755     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
01756     {
01757       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01758       {
01759         /* Process Unlocked */
01760         __HAL_UNLOCK(hi2c);
01761         return HAL_ERROR;
01762       }
01763       else
01764       {
01765         /* Process Unlocked */
01766         __HAL_UNLOCK(hi2c);
01767         return HAL_TIMEOUT;
01768       }
01769     }
01770
01771     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01772     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01773     {
01774       hi2c->XferSize = MAX_NBYTE_SIZE;
01775       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01776     }
01777     else
01778     {
01779       hi2c->XferSize = hi2c->XferCount;
01780       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01781     }
01782
01783     do
01784     {
01785       /* Wait until TXIS flag is set */
01786       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01787       {
01788         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01789         {
01790           return HAL_ERROR;
01791         }
01792         else
01793         {
01794           return HAL_TIMEOUT;
01795         }
01796       }
01797
01798       /* Write data to TXDR */
01799       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
01800       hi2c->XferCount--;
01801       hi2c->XferSize--;
01802
01803       if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
01804       {
01805         /* Wait until TCR flag is set */
01806         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01807         {
01808           return HAL_TIMEOUT;
01809         }
01810
01811         if(hi2c->XferCount > MAX_NBYTE_SIZE)
01812         {
01813           hi2c->XferSize = MAX_NBYTE_SIZE;
01814           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01815         }
01816         else
01817         {
01818           hi2c->XferSize = hi2c->XferCount;
01819           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01820         }
01821       }
01822
01823     }while(hi2c->XferCount > 0U);
01824
01825     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01826     /* Wait until STOPF flag is reset */
01827     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01828     {
01829       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01830       {
01831         return HAL_ERROR;
01832       }
01833       else
01834       {
01835         return HAL_TIMEOUT;
01836       }
01837     }
01838
01839     /* Clear STOP Flag */
01840     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01841
01842     /* Clear Configuration Register 2 */
01843     I2C_RESET_CR2(hi2c);
01844
01845     hi2c->State = HAL_I2C_STATE_READY;
01846     hi2c->Mode  = HAL_I2C_MODE_NONE;
01847
01848     /* Process Unlocked */
01849     __HAL_UNLOCK(hi2c);
01850
01851     return HAL_OK;
01852   }
01853   else
01854   {
01855     return HAL_BUSY;
01856   }
01857 }
01858
01859 /**
01860   * @brief  Read an amount of data in blocking mode from a specific memory address
01861   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01862   *                the configuration information for the specified I2C.
01863   * @param  DevAddress Target device address
01864   * @param  MemAddress Internal memory address
01865   * @param  MemAddSize Size of internal memory address
01866   * @param  pData Pointer to data buffer
01867   * @param  Size Amount of data to be sent
01868   * @param  Timeout Timeout duration
01869   * @retval HAL status
01870   */
01871 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01872 {
01873   uint32_t tickstart = 0U;
01874
01875   /* Check the parameters */
01876   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01877
01878   if(hi2c->State == HAL_I2C_STATE_READY)
01879   {
01880     if((pData == NULL) || (Size == 0U))
01881     {
01882       return  HAL_ERROR;
01883     }
01884
01885     /* Process Locked */
01886     __HAL_LOCK(hi2c);
01887
01888     /* Init tickstart for timeout management*/
01889     tickstart = HAL_GetTick();
01890
01891     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01892     {
01893       return HAL_TIMEOUT;
01894     }
01895
01896     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01897     hi2c->Mode      = HAL_I2C_MODE_MEM;
01898     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01899
01900     /* Prepare transfer parameters */
01901     hi2c->pBuffPtr  = pData;
01902     hi2c->XferCount = Size;
01903     hi2c->XferISR   = NULL;
01904
01905     /* Send Slave Address and Memory Address */
01906     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
01907     {
01908       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01909       {
01910         /* Process Unlocked */
01911         __HAL_UNLOCK(hi2c);
01912         return HAL_ERROR;
01913       }
01914       else
01915       {
01916         /* Process Unlocked */
01917         __HAL_UNLOCK(hi2c);
01918         return HAL_TIMEOUT;
01919       }
01920     }
01921
01922     /* Send Slave Address */
01923     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01924     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01925     {
01926       hi2c->XferSize = MAX_NBYTE_SIZE;
01927       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
01928     }
01929     else
01930     {
01931       hi2c->XferSize = hi2c->XferCount;
01932       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01933     }
01934
01935     do
01936     {
01937       /* Wait until RXNE flag is set */
01938       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
01939       {
01940         return HAL_TIMEOUT;
01941       }
01942
01943       /* Read data from RXDR */
01944       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01945       hi2c->XferSize--;
01946       hi2c->XferCount--;
01947
01948       if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
01949       {
01950         /* Wait until TCR flag is set */
01951         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01952         {
01953           return HAL_TIMEOUT;
01954         }
01955
01956         if(hi2c->XferCount > MAX_NBYTE_SIZE)
01957         {
01958           hi2c->XferSize = MAX_NBYTE_SIZE;
01959           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01960         }
01961         else
01962         {
01963           hi2c->XferSize = hi2c->XferCount;
01964           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01965         }
01966       }
01967     }while(hi2c->XferCount > 0U);
01968
01969     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01970     /* Wait until STOPF flag is reset */
01971     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01972     {
01973       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01974       {
01975         return HAL_ERROR;
01976       }
01977       else
01978       {
01979         return HAL_TIMEOUT;
01980       }
01981     }
01982
01983     /* Clear STOP Flag */
01984     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01985
01986     /* Clear Configuration Register 2 */
01987     I2C_RESET_CR2(hi2c);
01988
01989     hi2c->State = HAL_I2C_STATE_READY;
01990     hi2c->Mode  = HAL_I2C_MODE_NONE;
01991
01992     /* Process Unlocked */
01993     __HAL_UNLOCK(hi2c);
01994
01995     return HAL_OK;
01996   }
01997   else
01998   {
01999     return HAL_BUSY;
02000   }
02001 }
02002 /**
02003   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
02004   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02005   *                the configuration information for the specified I2C.
02006   * @param  DevAddress Target device address
02007   * @param  MemAddress Internal memory address
02008   * @param  MemAddSize Size of internal memory address
02009   * @param  pData Pointer to data buffer
02010   * @param  Size Amount of data to be sent
02011   * @retval HAL status
02012   */
02013 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02014 {
02015   uint32_t tickstart = 0U;
02016   uint32_t xfermode = 0U;
02017
02018   /* Check the parameters */
02019   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02020
02021   if(hi2c->State == HAL_I2C_STATE_READY)
02022   {
02023     if((pData == NULL) || (Size == 0U))
02024     {
02025       return  HAL_ERROR;
02026     }
02027
02028     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02029     {
02030       return HAL_BUSY;
02031     }
02032
02033     /* Process Locked */
02034     __HAL_LOCK(hi2c);
02035
02036     /* Init tickstart for timeout management*/
02037     tickstart = HAL_GetTick();
02038
02039     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02040     hi2c->Mode        = HAL_I2C_MODE_MEM;
02041     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02042
02043     /* Prepare transfer parameters */
02044     hi2c->pBuffPtr    = pData;
02045     hi2c->XferCount   = Size;
02046     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02047     hi2c->XferISR     = I2C_Master_ISR_IT;
02048
02049     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02050     {
02051       hi2c->XferSize = MAX_NBYTE_SIZE;
02052       xfermode = I2C_RELOAD_MODE;
02053     }
02054     else
02055     {
02056       hi2c->XferSize = hi2c->XferCount;
02057       xfermode = I2C_AUTOEND_MODE;
02058     }
02059
02060     /* Send Slave Address and Memory Address */
02061     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02062     {
02063       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02064       {
02065         /* Process Unlocked */
02066         __HAL_UNLOCK(hi2c);
02067         return HAL_ERROR;
02068       }
02069       else
02070       {
02071         /* Process Unlocked */
02072         __HAL_UNLOCK(hi2c);
02073         return HAL_TIMEOUT;
02074       }
02075     }
02076
02077     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02078     I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02079
02080     /* Process Unlocked */
02081     __HAL_UNLOCK(hi2c);
02082
02083     /* Note : The I2C interrupts must be enabled after unlocking current process
02084               to avoid the risk of I2C interrupt handle execution before current
02085               process unlock */
02086
02087     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02088     /* possible to enable all of these */
02089     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02090     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02091
02092     return HAL_OK;
02093   }
02094   else
02095   {
02096     return HAL_BUSY;
02097   }
02098 }
02099
02100 /**
02101   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
02102   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02103   *                the configuration information for the specified I2C.
02104   * @param  DevAddress Target device address
02105   * @param  MemAddress Internal memory address
02106   * @param  MemAddSize Size of internal memory address
02107   * @param  pData Pointer to data buffer
02108   * @param  Size Amount of data to be sent
02109   * @retval HAL status
02110   */
02111 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02112 {
02113   uint32_t tickstart = 0U;
02114   uint32_t xfermode = 0U;
02115
02116   /* Check the parameters */
02117   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02118
02119   if(hi2c->State == HAL_I2C_STATE_READY)
02120   {
02121     if((pData == NULL) || (Size == 0U))
02122     {
02123       return  HAL_ERROR;
02124     }
02125
02126     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02127     {
02128       return HAL_BUSY;
02129     }
02130
02131     /* Process Locked */
02132     __HAL_LOCK(hi2c);
02133
02134     /* Init tickstart for timeout management*/
02135     tickstart = HAL_GetTick();
02136
02137     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02138     hi2c->Mode        = HAL_I2C_MODE_MEM;
02139     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02140
02141     /* Prepare transfer parameters */
02142     hi2c->pBuffPtr    = pData;
02143     hi2c->XferCount   = Size;
02144     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02145     hi2c->XferISR     = I2C_Master_ISR_IT;
02146
02147     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02148     {
02149       hi2c->XferSize = MAX_NBYTE_SIZE;
02150       xfermode = I2C_RELOAD_MODE;
02151     }
02152     else
02153     {
02154       hi2c->XferSize = hi2c->XferCount;
02155       xfermode = I2C_AUTOEND_MODE;
02156     }
02157
02158     /* Send Slave Address and Memory Address */
02159     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02160     {
02161       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02162       {
02163         /* Process Unlocked */
02164         __HAL_UNLOCK(hi2c);
02165         return HAL_ERROR;
02166       }
02167       else
02168       {
02169         /* Process Unlocked */
02170         __HAL_UNLOCK(hi2c);
02171         return HAL_TIMEOUT;
02172       }
02173     }
02174
02175     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02176     I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02177
02178     /* Process Unlocked */
02179     __HAL_UNLOCK(hi2c);
02180
02181     /* Note : The I2C interrupts must be enabled after unlocking current process
02182               to avoid the risk of I2C interrupt handle execution before current
02183               process unlock */
02184
02185     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02186     /* possible to enable all of these */
02187     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02188     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02189
02190     return HAL_OK;
02191   }
02192   else
02193   {
02194     return HAL_BUSY;
02195   }
02196 }
02197 /**
02198   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
02199   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02200   *                the configuration information for the specified I2C.
02201   * @param  DevAddress Target device address
02202   * @param  MemAddress Internal memory address
02203   * @param  MemAddSize Size of internal memory address
02204   * @param  pData Pointer to data buffer
02205   * @param  Size Amount of data to be sent
02206   * @retval HAL status
02207   */
02208 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02209 {
02210   uint32_t tickstart = 0U;
02211   uint32_t xfermode = 0U;
02212
02213   /* Check the parameters */
02214   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02215
02216   if(hi2c->State == HAL_I2C_STATE_READY)
02217   {
02218     if((pData == NULL) || (Size == 0U))
02219     {
02220       return  HAL_ERROR;
02221     }
02222
02223     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02224     {
02225       return HAL_BUSY;
02226     }
02227
02228     /* Process Locked */
02229     __HAL_LOCK(hi2c);
02230
02231     /* Init tickstart for timeout management*/
02232     tickstart = HAL_GetTick();
02233
02234     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02235     hi2c->Mode        = HAL_I2C_MODE_MEM;
02236     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02237
02238     /* Prepare transfer parameters */
02239     hi2c->pBuffPtr    = pData;
02240     hi2c->XferCount   = Size;
02241     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02242     hi2c->XferISR     = I2C_Master_ISR_DMA;
02243
02244     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02245     {
02246       hi2c->XferSize = MAX_NBYTE_SIZE;
02247       xfermode = I2C_RELOAD_MODE;
02248     }
02249     else
02250     {
02251       hi2c->XferSize = hi2c->XferCount;
02252       xfermode = I2C_AUTOEND_MODE;
02253     }
02254
02255     /* Send Slave Address and Memory Address */
02256     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02257     {
02258       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02259       {
02260         /* Process Unlocked */
02261         __HAL_UNLOCK(hi2c);
02262         return HAL_ERROR;
02263       }
02264       else
02265       {
02266         /* Process Unlocked */
02267         __HAL_UNLOCK(hi2c);
02268         return HAL_TIMEOUT;
02269       }
02270     }
02271
02272     /* Set the I2C DMA transfer complete callback */
02273     hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
02274
02275     /* Set the DMA error callback */
02276     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02277
02278     /* Set the unused DMA callbacks to NULL */
02279     hi2c->hdmatx->XferHalfCpltCallback = NULL;
02280     hi2c->hdmatx->XferAbortCallback = NULL;
02281
02282     /* Enable the DMA channel */
02283     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
02284
02285     /* Send Slave Address */
02286     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02287     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02288
02289     /* Update XferCount value */
02290     hi2c->XferCount -= hi2c->XferSize;
02291
02292     /* Process Unlocked */
02293     __HAL_UNLOCK(hi2c);
02294
02295     /* Note : The I2C interrupts must be enabled after unlocking current process
02296               to avoid the risk of I2C interrupt handle execution before current
02297               process unlock */
02298     /* Enable ERR and NACK interrupts */
02299     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02300
02301     /* Enable DMA Request */
02302     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02303
02304     return HAL_OK;
02305   }
02306   else
02307   {
02308     return HAL_BUSY;
02309   }
02310 }
02311
02312 /**
02313   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
02314   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02315   *                the configuration information for the specified I2C.
02316   * @param  DevAddress Target device address
02317   * @param  MemAddress Internal memory address
02318   * @param  MemAddSize Size of internal memory address
02319   * @param  pData Pointer to data buffer
02320   * @param  Size Amount of data to be read
02321   * @retval HAL status
02322   */
02323 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02324 {
02325   uint32_t tickstart = 0U;
02326   uint32_t xfermode = 0U;
02327
02328   /* Check the parameters */
02329   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02330
02331   if(hi2c->State == HAL_I2C_STATE_READY)
02332   {
02333     if((pData == NULL) || (Size == 0U))
02334     {
02335       return  HAL_ERROR;
02336     }
02337
02338     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02339     {
02340       return HAL_BUSY;
02341     }
02342
02343     /* Process Locked */
02344     __HAL_LOCK(hi2c);
02345
02346     /* Init tickstart for timeout management*/
02347     tickstart = HAL_GetTick();
02348
02349     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02350     hi2c->Mode        = HAL_I2C_MODE_MEM;
02351     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02352
02353     /* Prepare transfer parameters */
02354     hi2c->pBuffPtr    = pData;
02355     hi2c->XferCount   = Size;
02356     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02357     hi2c->XferISR     = I2C_Master_ISR_DMA;
02358
02359     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02360     {
02361       hi2c->XferSize = MAX_NBYTE_SIZE;
02362       xfermode = I2C_RELOAD_MODE;
02363     }
02364     else
02365     {
02366       hi2c->XferSize = hi2c->XferCount;
02367       xfermode = I2C_AUTOEND_MODE;
02368     }
02369
02370     /* Send Slave Address and Memory Address */
02371     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02372     {
02373       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02374       {
02375         /* Process Unlocked */
02376         __HAL_UNLOCK(hi2c);
02377         return HAL_ERROR;
02378       }
02379       else
02380       {
02381         /* Process Unlocked */
02382         __HAL_UNLOCK(hi2c);
02383         return HAL_TIMEOUT;
02384       }
02385     }
02386
02387     /* Set the I2C DMA transfer complete callback */
02388     hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
02389
02390     /* Set the DMA error callback */
02391     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02392
02393     /* Set the unused DMA callbacks to NULL */
02394     hi2c->hdmarx->XferHalfCpltCallback = NULL;
02395     hi2c->hdmarx->XferAbortCallback = NULL;
02396
02397     /* Enable the DMA channel */
02398     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
02399
02400     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02401     I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02402
02403     /* Update XferCount value */
02404     hi2c->XferCount -= hi2c->XferSize;
02405
02406     /* Process Unlocked */
02407     __HAL_UNLOCK(hi2c);
02408
02409     /* Enable DMA Request */
02410     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02411
02412     /* Note : The I2C interrupts must be enabled after unlocking current process
02413               to avoid the risk of I2C interrupt handle execution before current
02414               process unlock */
02415     /* Enable ERR and NACK interrupts */
02416     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02417
02418     return HAL_OK;
02419   }
02420   else
02421   {
02422     return HAL_BUSY;
02423   }
02424 }
02425
02426 /**
02427   * @brief  Checks if target device is ready for communication.
02428   * @note   This function is used with Memory devices
02429   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02430   *                the configuration information for the specified I2C.
02431   * @param  DevAddress Target device address
02432   * @param  Trials Number of trials
02433   * @param  Timeout Timeout duration
02434   * @retval HAL status
02435   */
02436 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
02437 {
02438   uint32_t tickstart = 0U;
02439
02440   __IO uint32_t I2C_Trials = 0U;
02441
02442   if(hi2c->State == HAL_I2C_STATE_READY)
02443   {
02444     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02445     {
02446       return HAL_BUSY;
02447     }
02448
02449     /* Process Locked */
02450     __HAL_LOCK(hi2c);
02451
02452     hi2c->State = HAL_I2C_STATE_BUSY;
02453     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02454
02455     do
02456     {
02457       /* Generate Start */
02458       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
02459
02460       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02461       /* Wait until STOPF flag is set or a NACK flag is set*/
02462       tickstart = HAL_GetTick();
02463       while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
02464       {
02465         if(Timeout != HAL_MAX_DELAY)
02466         {
02467           if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
02468           {
02469             /* Device is ready */
02470             hi2c->State = HAL_I2C_STATE_READY;
02471             /* Process Unlocked */
02472             __HAL_UNLOCK(hi2c);
02473             return HAL_TIMEOUT;
02474           }
02475         }
02476       }
02477
02478       /* Check if the NACKF flag has not been set */
02479       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
02480       {
02481         /* Wait until STOPF flag is reset */
02482         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02483         {
02484           return HAL_TIMEOUT;
02485         }
02486
02487         /* Clear STOP Flag */
02488         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02489
02490         /* Device is ready */
02491         hi2c->State = HAL_I2C_STATE_READY;
02492
02493         /* Process Unlocked */
02494         __HAL_UNLOCK(hi2c);
02495
02496         return HAL_OK;
02497       }
02498       else
02499       {
02500         /* Wait until STOPF flag is reset */
02501         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02502         {
02503           return HAL_TIMEOUT;
02504         }
02505
02506         /* Clear NACK Flag */
02507         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02508
02509         /* Clear STOP Flag, auto generated with autoend*/
02510         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02511       }
02512
02513       /* Check if the maximum allowed number of trials has been reached */
02514       if (I2C_Trials++ == Trials)
02515       {
02516         /* Generate Stop */
02517         hi2c->Instance->CR2 |= I2C_CR2_STOP;
02518
02519         /* Wait until STOPF flag is reset */
02520         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02521         {
02522           return HAL_TIMEOUT;
02523         }
02524
02525         /* Clear STOP Flag */
02526         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02527       }
02528     }while(I2C_Trials < Trials);
02529
02530     hi2c->State = HAL_I2C_STATE_READY;
02531
02532     /* Process Unlocked */
02533     __HAL_UNLOCK(hi2c);
02534
02535     return HAL_TIMEOUT;
02536   }
02537   else
02538   {
02539     return HAL_BUSY;
02540   }
02541 }
02542
02543 /**
02544   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
02545   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02546   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02547   *                the configuration information for the specified I2C.
02548   * @param  DevAddress Target device address
02549   * @param  pData Pointer to data buffer
02550   * @param  Size Amount of data to be sent
02551   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02552   * @retval HAL status
02553   */
02554 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02555 {
02556   uint32_t xfermode = 0U;
02557   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
02558
02559   /* Check the parameters */
02560   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02561
02562   if(hi2c->State == HAL_I2C_STATE_READY)
02563   {
02564     /* Process Locked */
02565     __HAL_LOCK(hi2c);
02566
02567     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02568     hi2c->Mode      = HAL_I2C_MODE_MASTER;
02569     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02570
02571     /* Prepare transfer parameters */
02572     hi2c->pBuffPtr    = pData;
02573     hi2c->XferCount   = Size;
02574     hi2c->XferOptions = XferOptions;
02575     hi2c->XferISR     = I2C_Master_ISR_IT;
02576
02577     /* If size > MAX_NBYTE_SIZE, use reload mode */
02578     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02579     {
02580       hi2c->XferSize = MAX_NBYTE_SIZE;
02581       xfermode = I2C_RELOAD_MODE;
02582     }
02583     else
02584     {
02585       hi2c->XferSize = hi2c->XferCount;
02586       xfermode = hi2c->XferOptions;
02587
02588       /* If transfer direction not change, do not generate Restart Condition */
02589       /* Mean Previous state is same as current state */
02590       if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX)
02591       {
02592         xferrequest = I2C_NO_STARTSTOP;
02593       }
02594     }
02595
02596
02597     /* Send Slave Address and set NBYTES to write */
02598     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
02599
02600     /* Process Unlocked */
02601     __HAL_UNLOCK(hi2c);
02602
02603     /* Note : The I2C interrupts must be enabled after unlocking current process
02604               to avoid the risk of I2C interrupt handle execution before current
02605               process unlock */
02606     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02607
02608     return HAL_OK;
02609   }
02610   else
02611   {
02612     return HAL_BUSY;
02613   }
02614 }
02615
02616 /**
02617   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
02618   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02619   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02620   *                the configuration information for the specified I2C.
02621   * @param  DevAddress Target device address
02622   * @param  pData Pointer to data buffer
02623   * @param  Size Amount of data to be sent
02624   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02625   * @retval HAL status
02626   */
02627 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02628 {
02629   uint32_t xfermode = 0U;
02630   uint32_t xferrequest = I2C_GENERATE_START_READ;
02631
02632   /* Check the parameters */
02633   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02634
02635   if(hi2c->State == HAL_I2C_STATE_READY)
02636   {
02637     /* Process Locked */
02638     __HAL_LOCK(hi2c);
02639
02640     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02641     hi2c->Mode      = HAL_I2C_MODE_MASTER;
02642     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02643
02644     /* Prepare transfer parameters */
02645     hi2c->pBuffPtr    = pData;
02646     hi2c->XferCount   = Size;
02647     hi2c->XferOptions = XferOptions;
02648     hi2c->XferISR     = I2C_Master_ISR_IT;
02649
02650     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
02651     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02652     {
02653       hi2c->XferSize = MAX_NBYTE_SIZE;
02654       xfermode = I2C_RELOAD_MODE;
02655     }
02656     else
02657     {
02658       hi2c->XferSize = hi2c->XferCount;
02659       xfermode = hi2c->XferOptions;
02660
02661       /* If transfer direction not change, do not generate Restart Condition */
02662       /* Mean Previous state is same as current state */
02663       if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
02664       {
02665         xferrequest = I2C_NO_STARTSTOP;
02666       }
02667     }
02668
02669     /* Send Slave Address and set NBYTES to read */
02670     I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
02671
02672     /* Process Unlocked */
02673     __HAL_UNLOCK(hi2c);
02674
02675     /* Note : The I2C interrupts must be enabled after unlocking current process
02676               to avoid the risk of I2C interrupt handle execution before current
02677               process unlock */
02678     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02679
02680     return HAL_OK;
02681   }
02682   else
02683   {
02684     return HAL_BUSY;
02685   }
02686 }
02687
02688 /**
02689   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
02690   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02691   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02692   *                the configuration information for the specified I2C.
02693   * @param  pData Pointer to data buffer
02694   * @param  Size Amount of data to be sent
02695   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02696   * @retval HAL status
02697   */
02698 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02699 {
02700   /* Check the parameters */
02701   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02702
02703   if(hi2c->State == HAL_I2C_STATE_LISTEN)
02704   {
02705     if((pData == NULL) || (Size == 0U))
02706     {
02707       return  HAL_ERROR;
02708     }
02709
02710     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
02711     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
02712
02713     /* Process Locked */
02714     __HAL_LOCK(hi2c);
02715
02716     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
02717     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
02718     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02719
02720     /* Enable Address Acknowledge */
02721     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02722
02723     /* Prepare transfer parameters */
02724     hi2c->pBuffPtr    = pData;
02725     hi2c->XferCount   = Size;
02726     hi2c->XferSize    = hi2c->XferCount;
02727     hi2c->XferOptions = XferOptions;
02728     hi2c->XferISR     = I2C_Slave_ISR_IT;
02729
02730     if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
02731     {
02732       /* Clear ADDR flag after prepare the transfer parameters */
02733       /* This action will generate an acknowledge to the Master */
02734       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
02735     }
02736
02737     /* Process Unlocked */
02738     __HAL_UNLOCK(hi2c);
02739
02740     /* Note : The I2C interrupts must be enabled after unlocking current process
02741     to avoid the risk of I2C interrupt handle execution before current
02742     process unlock */
02743     /* REnable ADDR interrupt */
02744     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
02745
02746     return HAL_OK;
02747   }
02748   else
02749   {
02750     return HAL_ERROR;
02751   }
02752 }
02753
02754 /**
02755   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
02756   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02757   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02758   *                the configuration information for the specified I2C.
02759   * @param  pData Pointer to data buffer
02760   * @param  Size Amount of data to be sent
02761   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02762   * @retval HAL status
02763   */
02764 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02765 {
02766   /* Check the parameters */
02767   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02768
02769   if(hi2c->State == HAL_I2C_STATE_LISTEN)
02770   {
02771     if((pData == NULL) || (Size == 0U))
02772     {
02773       return  HAL_ERROR;
02774     }
02775
02776     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
02777     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
02778
02779     /* Process Locked */
02780     __HAL_LOCK(hi2c);
02781
02782     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
02783     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
02784     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02785
02786     /* Enable Address Acknowledge */
02787     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02788
02789     /* Prepare transfer parameters */
02790     hi2c->pBuffPtr    = pData;
02791     hi2c->XferCount   = Size;
02792     hi2c->XferSize    = hi2c->XferCount;
02793     hi2c->XferOptions = XferOptions;
02794     hi2c->XferISR     = I2C_Slave_ISR_IT;
02795
02796     if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
02797     {
02798       /* Clear ADDR flag after prepare the transfer parameters */
02799       /* This action will generate an acknowledge to the Master */
02800       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
02801     }
02802
02803     /* Process Unlocked */
02804     __HAL_UNLOCK(hi2c);
02805
02806     /* Note : The I2C interrupts must be enabled after unlocking current process
02807     to avoid the risk of I2C interrupt handle execution before current
02808     process unlock */
02809     /* REnable ADDR interrupt */
02810     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
02811
02812     return HAL_OK;
02813   }
02814   else
02815   {
02816     return HAL_ERROR;
02817   }
02818 }
02819
02820 /**
02821   * @brief  Enable the Address listen mode with Interrupt.
02822   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02823   *                the configuration information for the specified I2C.
02824   * @retval HAL status
02825   */
02826 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
02827 {
02828   if(hi2c->State == HAL_I2C_STATE_READY)
02829   {
02830     hi2c->State = HAL_I2C_STATE_LISTEN;
02831     hi2c->XferISR = I2C_Slave_ISR_IT;
02832
02833     /* Enable the Address Match interrupt */
02834     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02835
02836     return HAL_OK;
02837   }
02838   else
02839   {
02840     return HAL_BUSY;
02841   }
02842 }
02843
02844 /**
02845   * @brief  Disable the Address listen mode with Interrupt.
02846   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02847   *                the configuration information for the specified I2C
02848   * @retval HAL status
02849   */
02850 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
02851 {
02852   /* Declaration of tmp to prevent undefined behavior of volatile usage */
02853   uint32_t tmp;
02854
02855   /* Disable Address listen mode only if a transfer is not ongoing */
02856   if(hi2c->State == HAL_I2C_STATE_LISTEN)
02857   {
02858     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
02859     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
02860     hi2c->State = HAL_I2C_STATE_READY;
02861     hi2c->Mode = HAL_I2C_MODE_NONE;
02862     hi2c->XferISR = NULL;
02863
02864     /* Disable the Address Match interrupt */
02865     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02866
02867     return HAL_OK;
02868   }
02869   else
02870   {
02871     return HAL_BUSY;
02872   }
02873 }
02874
02875 /**
02876   * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
02877   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02878   *                the configuration information for the specified I2C.
02879   * @param  DevAddress Target device address
02880   * @retval HAL status
02881   */
02882 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
02883 {
02884   if(hi2c->Mode == HAL_I2C_MODE_MASTER)
02885   {
02886     /* Process Locked */
02887     __HAL_LOCK(hi2c);
02888
02889     /* Disable Interrupts */
02890     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
02891     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
02892
02893     /* Set State at HAL_I2C_STATE_ABORT */
02894     hi2c->State = HAL_I2C_STATE_ABORT;
02895
02896     /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
02897     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
02898     I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
02899
02900     /* Process Unlocked */
02901     __HAL_UNLOCK(hi2c);
02902
02903     /* Note : The I2C interrupts must be enabled after unlocking current process
02904               to avoid the risk of I2C interrupt handle execution before current
02905               process unlock */
02906     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
02907
02908     return HAL_OK;
02909   }
02910   else
02911   {
02912     /* Wrong usage of abort function */
02913     /* This function should be used only in case of abort monitored by master device */
02914     return HAL_ERROR;
02915   }
02916 }
02917
02918 /**
02919   * @}
02920   */
02921
02922 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
02923  * @{
02924  */
02925
02926 /**
02927   * @brief  This function handles I2C event interrupt request.
02928   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02929   *                the configuration information for the specified I2C.
02930   * @retval None
02931   */
02932 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
02933 {
02934   /* Get current IT Flags and IT sources value */
02935   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
02936   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
02937
02938   /* I2C events treatment -------------------------------------*/
02939   if(hi2c->XferISR != NULL)
02940   {
02941     hi2c->XferISR(hi2c, itflags, itsources);
02942   }
02943 }
02944
02945 /**
02946   * @brief  This function handles I2C error interrupt request.
02947   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02948   *                the configuration information for the specified I2C.
02949   * @retval None
02950   */
02951 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
02952 {
02953   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
02954   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
02955
02956   /* I2C Bus error interrupt occurred ------------------------------------*/
02957   if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
02958   {
02959     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
02960
02961     /* Clear BERR flag */
02962     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
02963   }
02964
02965   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
02966   if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
02967   {
02968     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
02969
02970     /* Clear OVR flag */
02971     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
02972   }
02973
02974   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
02975   if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
02976   {
02977     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
02978
02979     /* Clear ARLO flag */
02980     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
02981   }
02982
02983   /* Call the Error Callback in case of Error detected */
02984   if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
02985   {
02986     I2C_ITError(hi2c, hi2c->ErrorCode);
02987   }
02988 }
02989
02990 /**
02991   * @brief  Master Tx Transfer completed callback.
02992   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02993   *                the configuration information for the specified I2C.
02994   * @retval None
02995   */
02996 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
02997 {
02998   /* Prevent unused argument(s) compilation warning */
02999   UNUSED(hi2c);
03000
03001   /* NOTE : This function should not be modified, when the callback is needed,
03002             the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
03003    */
03004 }
03005
03006 /**
03007   * @brief  Master Rx Transfer completed callback.
03008   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03009   *                the configuration information for the specified I2C.
03010   * @retval None
03011   */
03012 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
03013 {
03014   /* Prevent unused argument(s) compilation warning */
03015   UNUSED(hi2c);
03016
03017   /* NOTE : This function should not be modified, when the callback is needed,
03018             the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
03019    */
03020 }
03021
03022 /** @brief  Slave Tx Transfer completed callback.
03023   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03024   *                the configuration information for the specified I2C.
03025   * @retval None
03026   */
03027 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
03028 {
03029   /* Prevent unused argument(s) compilation warning */
03030   UNUSED(hi2c);
03031
03032   /* NOTE : This function should not be modified, when the callback is needed,
03033             the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
03034    */
03035 }
03036
03037 /**
03038   * @brief  Slave Rx Transfer completed callback.
03039   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03040   *                the configuration information for the specified I2C.
03041   * @retval None
03042   */
03043 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
03044 {
03045   /* Prevent unused argument(s) compilation warning */
03046   UNUSED(hi2c);
03047
03048   /* NOTE : This function should not be modified, when the callback is needed,
03049             the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
03050    */
03051 }
03052
03053 /**
03054   * @brief  Slave Address Match callback.
03055   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03056   *                the configuration information for the specified I2C.
03057   * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS
03058   * @param  AddrMatchCode: Address Match Code
03059   * @retval None
03060   */
03061 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
03062 {
03063   /* Prevent unused argument(s) compilation warning */
03064   UNUSED(hi2c);
03065   UNUSED(TransferDirection);
03066   UNUSED(AddrMatchCode);
03067
03068   /* NOTE : This function should not be modified, when the callback is needed,
03069             the HAL_I2C_AddrCallback() could be implemented in the user file
03070    */
03071 }
03072
03073 /**
03074   * @brief  Listen Complete callback.
03075   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03076   *                the configuration information for the specified I2C.
03077   * @retval None
03078   */
03079 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
03080 {
03081   /* Prevent unused argument(s) compilation warning */
03082   UNUSED(hi2c);
03083
03084   /* NOTE : This function should not be modified, when the callback is needed,
03085             the HAL_I2C_ListenCpltCallback() could be implemented in the user file
03086    */
03087 }
03088
03089 /**
03090   * @brief  Memory Tx Transfer completed callback.
03091   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03092   *                the configuration information for the specified I2C.
03093   * @retval None
03094   */
03095 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
03096 {
03097   /* Prevent unused argument(s) compilation warning */
03098   UNUSED(hi2c);
03099
03100   /* NOTE : This function should not be modified, when the callback is needed,
03101             the HAL_I2C_MemTxCpltCallback could be implemented in the user file
03102    */
03103 }
03104
03105 /**
03106   * @brief  Memory Rx Transfer completed callback.
03107   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03108   *                the configuration information for the specified I2C.
03109   * @retval None
03110   */
03111 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
03112 {
03113   /* Prevent unused argument(s) compilation warning */
03114   UNUSED(hi2c);
03115
03116   /* NOTE : This function should not be modified, when the callback is needed,
03117             the HAL_I2C_MemRxCpltCallback could be implemented in the user file
03118    */
03119 }
03120
03121 /**
03122   * @brief  I2C error callback.
03123   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03124   *                the configuration information for the specified I2C.
03125   * @retval None
03126   */
03127 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
03128 {
03129   /* Prevent unused argument(s) compilation warning */
03130   UNUSED(hi2c);
03131
03132   /* NOTE : This function should not be modified, when the callback is needed,
03133             the HAL_I2C_ErrorCallback could be implemented in the user file
03134    */
03135 }
03136
03137 /**
03138   * @brief  I2C abort callback.
03139   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03140   *                the configuration information for the specified I2C.
03141   * @retval None
03142   */
03143 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
03144 {
03145   /* Prevent unused argument(s) compilation warning */
03146   UNUSED(hi2c);
03147
03148   /* NOTE : This function should not be modified, when the callback is needed,
03149             the HAL_I2C_AbortCpltCallback could be implemented in the user file
03150    */
03151 }
03152
03153 /**
03154   * @}
03155   */
03156
03157 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
03158  *  @brief   Peripheral State, Mode and Error functions
03159  *
03160 @verbatim
03161  ===============================================================================
03162             ##### Peripheral State, Mode and Error functions #####
03163  ===============================================================================
03164     [..]
03165     This subsection permit to get in run-time the status of the peripheral
03166     and the data flow.
03167
03168 @endverbatim
03169   * @{
03170   */
03171
03172 /**
03173   * @brief  Return the I2C handle state.
03174   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03175   *                the configuration information for the specified I2C.
03176   * @retval HAL state
03177   */
03178 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
03179 {
03180   /* Return I2C handle state */
03181   return hi2c->State;
03182 }
03183
03184 /**
03185   * @brief  Returns the I2C Master, Slave, Memory or no mode.
03186   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03187   *         the configuration information for I2C module
03188   * @retval HAL mode
03189   */
03190 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
03191 {
03192   return hi2c->Mode;
03193 }
03194
03195 /**
03196 * @brief  Return the I2C error code.
03197   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03198   *              the configuration information for the specified I2C.
03199 * @retval I2C Error Code
03200 */
03201 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
03202 {
03203   return hi2c->ErrorCode;
03204 }
03205
03206 /**
03207   * @}
03208   */
03209
03210 /**
03211   * @}
03212   */
03213
03214 /** @addtogroup I2C_Private_Functions
03215   * @{
03216   */
03217
03218 /**
03219   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
03220   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03221   *                the configuration information for the specified I2C.
03222   * @param  ITFlags Interrupt flags to handle.
03223   * @param  ITSources Interrupt sources enabled.
03224   * @retval HAL status
03225   */
03226 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03227 {
03228   uint16_t devaddress = 0U;
03229
03230   /* Process Locked */
03231   __HAL_LOCK(hi2c);
03232
03233   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03234   {
03235     /* Clear NACK Flag */
03236     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03237
03238     /* Set corresponding Error Code */
03239     /* No need to generate STOP, it is automatically done */
03240     /* Error callback will be send during stop flag treatment */
03241     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03242
03243     /* Flush TX register */
03244     I2C_Flush_TXDR(hi2c);
03245   }
03246   else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
03247   {
03248     /* Read data from RXDR */
03249     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
03250     hi2c->XferSize--;
03251     hi2c->XferCount--;
03252   }
03253   else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
03254   {
03255     /* Write data to TXDR */
03256     hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
03257     hi2c->XferSize--;
03258     hi2c->XferCount--;
03259   }
03260   else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03261   {
03262     if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
03263     {
03264       devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03265
03266       if(hi2c->XferCount > MAX_NBYTE_SIZE)
03267       {
03268         hi2c->XferSize = MAX_NBYTE_SIZE;
03269         I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
03270       }
03271       else
03272       {
03273         hi2c->XferSize = hi2c->XferCount;
03274         if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
03275         {
03276           I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
03277         }
03278         else
03279         {
03280           I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
03281         }
03282       }
03283     }
03284     else
03285     {
03286       /* Call TxCpltCallback() if no stop mode is set */
03287       if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
03288       {
03289         /* Call I2C Master Sequential complete process */
03290         I2C_ITMasterSequentialCplt(hi2c);
03291       }
03292       else
03293       {
03294         /* Wrong size Status regarding TCR flag event */
03295         /* Call the corresponding callback to inform upper layer of End of Transfer */
03296         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03297       }
03298     }
03299   }
03300   else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03301   {
03302     if(hi2c->XferCount == 0U)
03303     {
03304       if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
03305       {
03306         /* Generate a stop condition in case of no transfer option */
03307         if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
03308         {
03309           /* Generate Stop */
03310           hi2c->Instance->CR2 |= I2C_CR2_STOP;
03311         }
03312         else
03313         {
03314           /* Call I2C Master Sequential complete process */
03315           I2C_ITMasterSequentialCplt(hi2c);
03316         }
03317       }
03318     }
03319     else
03320     {
03321       /* Wrong size Status regarding TC flag event */
03322       /* Call the corresponding callback to inform upper layer of End of Transfer */
03323       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03324     }
03325   }
03326
03327   if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03328   {
03329     /* Call I2C Master complete process */
03330     I2C_ITMasterCplt(hi2c, ITFlags);
03331   }
03332
03333   /* Process Unlocked */
03334   __HAL_UNLOCK(hi2c);
03335
03336   return HAL_OK;
03337 }
03338
03339 /**
03340   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
03341   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03342   *                the configuration information for the specified I2C.
03343   * @param  ITFlags Interrupt flags to handle.
03344   * @param  ITSources Interrupt sources enabled.
03345   * @retval HAL status
03346   */
03347 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03348 {
03349   /* Process locked */
03350   __HAL_LOCK(hi2c);
03351
03352   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03353   {
03354     /* Check that I2C transfer finished */
03355     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
03356     /* Mean XferCount == 0*/
03357     /* So clear Flag NACKF only */
03358     if(hi2c->XferCount == 0U)
03359     {
03360       if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
03361         (hi2c->State == HAL_I2C_STATE_LISTEN))
03362       {
03363         /* Call I2C Listen complete process */
03364         I2C_ITListenCplt(hi2c, ITFlags);
03365       }
03366       else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
03367       {
03368         /* Clear NACK Flag */
03369         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03370
03371         /* Flush TX register */
03372         I2C_Flush_TXDR(hi2c);
03373
03374         /* Last Byte is Transmitted */
03375         /* Call I2C Slave Sequential complete process */
03376         I2C_ITSlaveSequentialCplt(hi2c);
03377       }
03378       else
03379       {
03380         /* Clear NACK Flag */
03381         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03382       }
03383     }
03384     else
03385     {
03386       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
03387       /* Clear NACK Flag */
03388       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03389
03390       /* Set ErrorCode corresponding to a Non-Acknowledge */
03391       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03392     }
03393   }
03394   else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
03395   {
03396     if(hi2c->XferCount > 0U)
03397     {
03398       /* Read data from RXDR */
03399       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
03400       hi2c->XferSize--;
03401       hi2c->XferCount--;
03402     }
03403
03404     if((hi2c->XferCount == 0U) && \
03405        (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
03406     {
03407       /* Call I2C Slave Sequential complete process */
03408       I2C_ITSlaveSequentialCplt(hi2c);
03409    }
03410   }
03411   else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
03412   {
03413     I2C_ITAddrCplt(hi2c, ITFlags);
03414   }
03415   else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
03416   {
03417     /* Write data to TXDR only if XferCount not reach "0" */
03418     /* A TXIS flag can be set, during STOP treatment      */
03419     /* Check if all Datas have already been sent */
03420     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
03421     if(hi2c->XferCount > 0U)
03422     {
03423       /* Write data to TXDR */
03424       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
03425       hi2c->XferCount--;
03426       hi2c->XferSize--;
03427     }
03428     else
03429     {
03430       if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
03431       {
03432         /* Last Byte is Transmitted */
03433         /* Call I2C Slave Sequential complete process */
03434         I2C_ITSlaveSequentialCplt(hi2c);
03435       }
03436     }
03437   }
03438
03439   /* Check if STOPF is set */
03440   if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03441   {
03442     /* Call I2C Slave complete process */
03443     I2C_ITSlaveCplt(hi2c, ITFlags);
03444   }
03445
03446   /* Process Unlocked */
03447   __HAL_UNLOCK(hi2c);
03448
03449   return HAL_OK;
03450 }
03451
03452 /**
03453   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
03454   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03455   *                the configuration information for the specified I2C.
03456   * @param  ITFlags Interrupt flags to handle.
03457   * @param  ITSources Interrupt sources enabled.
03458   * @retval HAL status
03459   */
03460 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03461 {
03462   uint16_t devaddress = 0U;
03463   uint32_t xfermode = 0U;
03464
03465   /* Process Locked */
03466   __HAL_LOCK(hi2c);
03467
03468   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03469   {
03470     /* Clear NACK Flag */
03471     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03472
03473     /* Set corresponding Error Code */
03474     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03475
03476     /* No need to generate STOP, it is automatically done */
03477     /* But enable STOP interrupt, to treat it */
03478     /* Error callback will be send during stop flag treatment */
03479     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
03480
03481     /* Flush TX register */
03482     I2C_Flush_TXDR(hi2c);
03483   }
03484   else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03485   {
03486     /* Disable TC interrupt */
03487     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
03488
03489     if(hi2c->XferCount != 0U)
03490     {
03491       /* Recover Slave address */
03492       devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03493
03494       /* Prepare the new XferSize to transfer */
03495       if(hi2c->XferCount > MAX_NBYTE_SIZE)
03496       {
03497         hi2c->XferSize = MAX_NBYTE_SIZE;
03498         xfermode = I2C_RELOAD_MODE;
03499       }
03500       else
03501       {
03502         hi2c->XferSize = hi2c->XferCount;
03503         xfermode = I2C_AUTOEND_MODE;
03504       }
03505
03506       /* Set the new XferSize in Nbytes register */
03507       I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
03508
03509       /* Update XferCount value */
03510       hi2c->XferCount -= hi2c->XferSize;
03511
03512       /* Enable DMA Request */
03513       if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
03514       {
03515         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
03516       }
03517       else
03518       {
03519         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03520       }
03521     }
03522     else
03523     {
03524       /* Wrong size Status regarding TCR flag event */
03525       /* Call the corresponding callback to inform upper layer of End of Transfer */
03526       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03527     }
03528   }
03529   else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03530   {
03531     /* Call I2C Master complete process */
03532     I2C_ITMasterCplt(hi2c, ITFlags);
03533   }
03534
03535   /* Process Unlocked */
03536   __HAL_UNLOCK(hi2c);
03537
03538   return HAL_OK;
03539 }
03540
03541 /**
03542   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
03543   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03544   *                the configuration information for the specified I2C.
03545   * @param  ITFlags Interrupt flags to handle.
03546   * @param  ITSources Interrupt sources enabled.
03547   * @retval HAL status
03548   */
03549 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
03550 {
03551   /* Process locked */
03552   __HAL_LOCK(hi2c);
03553
03554   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03555   {
03556     /* Check that I2C transfer finished */
03557     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
03558     /* Mean XferCount == 0 */
03559     /* So clear Flag NACKF only */
03560     if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
03561     {
03562       /* Clear NACK Flag */
03563       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03564     }
03565     else
03566     {
03567       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
03568       /* Clear NACK Flag */
03569       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03570
03571       /* Set ErrorCode corresponding to a Non-Acknowledge */
03572       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03573     }
03574   }
03575   else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
03576   {
03577     /* Clear ADDR flag */
03578     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03579   }
03580   else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03581   {
03582     /* Call I2C Slave complete process */
03583     I2C_ITSlaveCplt(hi2c, ITFlags);
03584   }
03585
03586   /* Process Unlocked */
03587   __HAL_UNLOCK(hi2c);
03588
03589   return HAL_OK;
03590 }
03591
03592 /**
03593   * @brief  Master sends target device address followed by internal memory address for write request.
03594   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03595   *                the configuration information for the specified I2C.
03596   * @param  DevAddress Target device address
03597   * @param  MemAddress Internal memory address
03598   * @param  MemAddSize Size of internal memory address
03599   * @param  Timeout Timeout duration
03600   * @param  Tickstart Tick start value
03601   * @retval HAL status
03602   */
03603 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
03604 {
03605   I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
03606
03607   /* Wait until TXIS flag is set */
03608   if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03609   {
03610     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03611     {
03612       return HAL_ERROR;
03613     }
03614     else
03615     {
03616       return HAL_TIMEOUT;
03617     }
03618   }
03619
03620   /* If Memory address size is 8Bit */
03621   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
03622   {
03623     /* Send Memory Address */
03624     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03625   }
03626   /* If Memory address size is 16Bit */
03627   else
03628   {
03629     /* Send MSB of Memory Address */
03630     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03631
03632     /* Wait until TXIS flag is set */
03633     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03634     {
03635       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03636       {
03637         return HAL_ERROR;
03638       }
03639       else
03640       {
03641         return HAL_TIMEOUT;
03642       }
03643     }
03644
03645     /* Send LSB of Memory Address */
03646     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03647   }
03648
03649   /* Wait until TCR flag is set */
03650   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
03651   {
03652     return HAL_TIMEOUT;
03653   }
03654
03655 return HAL_OK;
03656 }
03657
03658 /**
03659   * @brief  Master sends target device address followed by internal memory address for read request.
03660   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03661   *                the configuration information for the specified I2C.
03662   * @param  DevAddress Target device address
03663   * @param  MemAddress Internal memory address
03664   * @param  MemAddSize Size of internal memory address
03665   * @param  Timeout Timeout duration
03666   * @param  Tickstart Tick start value
03667   * @retval HAL status
03668   */
03669 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
03670 {
03671   I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
03672
03673   /* Wait until TXIS flag is set */
03674   if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03675   {
03676     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03677     {
03678       return HAL_ERROR;
03679     }
03680     else
03681     {
03682       return HAL_TIMEOUT;
03683     }
03684   }
03685
03686   /* If Memory address size is 8Bit */
03687   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
03688   {
03689     /* Send Memory Address */
03690     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03691   }
03692   /* If Memory address size is 16Bit */
03693   else
03694   {
03695     /* Send MSB of Memory Address */
03696     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03697
03698     /* Wait until TXIS flag is set */
03699     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03700     {
03701       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03702       {
03703         return HAL_ERROR;
03704       }
03705       else
03706       {
03707         return HAL_TIMEOUT;
03708       }
03709     }
03710
03711     /* Send LSB of Memory Address */
03712     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03713   }
03714
03715   /* Wait until TC flag is set */
03716   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
03717   {
03718     return HAL_TIMEOUT;
03719   }
03720
03721   return HAL_OK;
03722 }
03723
03724 /**
03725   * @brief  I2C Address complete process callback.
03726   * @param  hi2c I2C handle.
03727   * @param  ITFlags Interrupt flags to handle.
03728   * @retval None
03729   */
03730 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
03731 {
03732   uint8_t transferdirection = 0U;
03733   uint16_t slaveaddrcode = 0U;
03734   uint16_t ownadd1code = 0U;
03735   uint16_t ownadd2code = 0U;
03736
03737   /* In case of Listen state, need to inform upper layer of address match code event */
03738   if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
03739   {
03740     transferdirection = I2C_GET_DIR(hi2c);
03741     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
03742     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
03743     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
03744
03745     /* If 10bits addressing mode is selected */
03746     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
03747     {
03748       if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
03749       {
03750         slaveaddrcode = ownadd1code;
03751         hi2c->AddrEventCount++;
03752         if(hi2c->AddrEventCount == 2U)
03753         {
03754           /* Reset Address Event counter */
03755           hi2c->AddrEventCount = 0U;
03756
03757           /* Clear ADDR flag */
03758           __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
03759
03760           /* Process Unlocked */
03761           __HAL_UNLOCK(hi2c);
03762
03763           /* Call Slave Addr callback */
03764           HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03765         }
03766       }
03767       else
03768       {
03769         slaveaddrcode = ownadd2code;
03770
03771         /* Disable ADDR Interrupts */
03772         I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
03773
03774         /* Process Unlocked */
03775         __HAL_UNLOCK(hi2c);
03776
03777         /* Call Slave Addr callback */
03778         HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03779       }
03780     }
03781     /* else 7 bits addressing mode is selected */
03782     else
03783     {
03784       /* Disable ADDR Interrupts */
03785       I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
03786
03787       /* Process Unlocked */
03788       __HAL_UNLOCK(hi2c);
03789
03790       /* Call Slave Addr callback */
03791       HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03792     }
03793   }
03794   /* Else clear address flag only */
03795   else
03796   {
03797     /* Clear ADDR flag */
03798     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03799
03800     /* Process Unlocked */
03801     __HAL_UNLOCK(hi2c);
03802   }
03803 }
03804
03805 /**
03806   * @brief  I2C Master sequential complete process.
03807   * @param  hi2c I2C handle.
03808   * @retval None
03809   */
03810 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
03811 {
03812   /* Reset I2C handle mode */
03813   hi2c->Mode = HAL_I2C_MODE_NONE;
03814
03815   /* No Generate Stop, to permit restart mode */
03816   /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
03817   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
03818   {
03819     hi2c->State         = HAL_I2C_STATE_READY;
03820     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
03821     hi2c->XferISR       = NULL;
03822
03823     /* Disable Interrupts */
03824     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
03825
03826     /* Process Unlocked */
03827     __HAL_UNLOCK(hi2c);
03828
03829     /* Call the corresponding callback to inform upper layer of End of Transfer */
03830     HAL_I2C_MasterTxCpltCallback(hi2c);
03831   }
03832   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
03833   else
03834   {
03835     hi2c->State         = HAL_I2C_STATE_READY;
03836     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
03837     hi2c->XferISR       = NULL;
03838
03839     /* Disable Interrupts */
03840     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03841
03842     /* Process Unlocked */
03843     __HAL_UNLOCK(hi2c);
03844
03845     /* Call the corresponding callback to inform upper layer of End of Transfer */
03846     HAL_I2C_MasterRxCpltCallback(hi2c);
03847   }
03848 }
03849
03850 /**
03851   * @brief  I2C Slave sequential complete process.
03852   * @param  hi2c I2C handle.
03853   * @retval None
03854   */
03855 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
03856 {
03857   /* Reset I2C handle mode */
03858   hi2c->Mode = HAL_I2C_MODE_NONE;
03859
03860   if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
03861   {
03862     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
03863     hi2c->State         = HAL_I2C_STATE_LISTEN;
03864     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
03865
03866     /* Disable Interrupts */
03867     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
03868
03869     /* Process Unlocked */
03870     __HAL_UNLOCK(hi2c);
03871
03872     /* Call the Tx complete callback to inform upper layer of the end of transmit process */
03873     HAL_I2C_SlaveTxCpltCallback(hi2c);
03874   }
03875
03876   else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03877   {
03878     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
03879     hi2c->State         = HAL_I2C_STATE_LISTEN;
03880     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
03881
03882     /* Disable Interrupts */
03883     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03884
03885     /* Process Unlocked */
03886     __HAL_UNLOCK(hi2c);
03887
03888     /* Call the Rx complete callback to inform upper layer of the end of receive process */
03889     HAL_I2C_SlaveRxCpltCallback(hi2c);
03890   }
03891 }
03892
03893 /**
03894   * @brief  I2C Master complete process.
03895   * @param  hi2c I2C handle.
03896   * @param  ITFlags Interrupt flags to handle.
03897   * @retval None
03898   */
03899 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
03900 {
03901   /* Clear STOP Flag */
03902   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03903
03904   /* Clear Configuration Register 2 */
03905   I2C_RESET_CR2(hi2c);
03906
03907   /* Reset handle parameters */
03908   hi2c->PreviousState = I2C_STATE_NONE;
03909   hi2c->XferISR       = NULL;
03910   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
03911
03912   if((ITFlags & I2C_FLAG_AF) != RESET)
03913   {
03914     /* Clear NACK Flag */
03915     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03916
03917     /* Set acknowledge error code */
03918     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03919   }
03920
03921   /* Flush TX register */
03922   I2C_Flush_TXDR(hi2c);
03923
03924   /* Disable Interrupts */
03925   I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
03926
03927   /* Call the corresponding callback to inform upper layer of End of Transfer */
03928   if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
03929   {
03930     /* Call the corresponding callback to inform upper layer of End of Transfer */
03931     I2C_ITError(hi2c, hi2c->ErrorCode);
03932   }
03933   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
03934   else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
03935   {
03936     hi2c->State = HAL_I2C_STATE_READY;
03937
03938     if (hi2c->Mode == HAL_I2C_MODE_MEM)
03939     {
03940       hi2c->Mode = HAL_I2C_MODE_NONE;
03941
03942       /* Process Unlocked */
03943       __HAL_UNLOCK(hi2c);
03944
03945       /* Call the corresponding callback to inform upper layer of End of Transfer */
03946       HAL_I2C_MemTxCpltCallback(hi2c);
03947     }
03948     else
03949     {
03950       hi2c->Mode = HAL_I2C_MODE_NONE;
03951
03952       /* Process Unlocked */
03953       __HAL_UNLOCK(hi2c);
03954
03955       /* Call the corresponding callback to inform upper layer of End of Transfer */
03956       HAL_I2C_MasterTxCpltCallback(hi2c);
03957     }
03958   }
03959   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
03960   else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
03961   {
03962     hi2c->State = HAL_I2C_STATE_READY;
03963
03964     if (hi2c->Mode == HAL_I2C_MODE_MEM)
03965     {
03966       hi2c->Mode = HAL_I2C_MODE_NONE;
03967
03968       /* Process Unlocked */
03969       __HAL_UNLOCK(hi2c);
03970
03971       HAL_I2C_MemRxCpltCallback(hi2c);
03972     }
03973     else
03974     {
03975       hi2c->Mode = HAL_I2C_MODE_NONE;
03976
03977       /* Process Unlocked */
03978       __HAL_UNLOCK(hi2c);
03979
03980       HAL_I2C_MasterRxCpltCallback(hi2c);
03981     }
03982   }
03983 }
03984
03985 /**
03986   * @brief  I2C Slave complete process.
03987   * @param  hi2c I2C handle.
03988   * @param  ITFlags Interrupt flags to handle.
03989   * @retval None
03990   */
03991 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
03992 {
03993   /* Clear STOP Flag */
03994   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03995
03996   /* Clear ADDR flag */
03997   __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
03998
03999   /* Disable all interrupts */
04000   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
04001
04002   /* Disable Address Acknowledge */
04003   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04004
04005   /* Clear Configuration Register 2 */
04006   I2C_RESET_CR2(hi2c);
04007
04008   /* Flush TX register */
04009   I2C_Flush_TXDR(hi2c);
04010
04011   /* If a DMA is ongoing, Update handle size context */
04012   if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
04013      ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
04014   {
04015     hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
04016   }
04017
04018   /* All data are not transferred, so set error code accordingly */
04019   if(hi2c->XferCount != 0U)
04020   {
04021     /* Set ErrorCode corresponding to a Non-Acknowledge */
04022     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04023   }
04024
04025   /* Store Last receive data if any */
04026   if(((ITFlags & I2C_FLAG_RXNE) != RESET))
04027   {
04028     /* Read data from RXDR */
04029     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
04030
04031     if((hi2c->XferSize > 0U))
04032     {
04033       hi2c->XferSize--;
04034       hi2c->XferCount--;
04035
04036       /* Set ErrorCode corresponding to a Non-Acknowledge */
04037       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04038     }
04039   }
04040
04041   hi2c->PreviousState = I2C_STATE_NONE;
04042   hi2c->Mode = HAL_I2C_MODE_NONE;
04043   hi2c->XferISR = NULL;
04044
04045   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04046   {
04047     /* Call the corresponding callback to inform upper layer of End of Transfer */
04048     I2C_ITError(hi2c, hi2c->ErrorCode);
04049
04050     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04051     if(hi2c->State == HAL_I2C_STATE_LISTEN)
04052     {
04053       /* Call I2C Listen complete process */
04054       I2C_ITListenCplt(hi2c, ITFlags);
04055     }
04056   }
04057   else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
04058   {
04059     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04060     hi2c->State = HAL_I2C_STATE_READY;
04061
04062     /* Process Unlocked */
04063     __HAL_UNLOCK(hi2c);
04064
04065     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04066     HAL_I2C_ListenCpltCallback(hi2c);
04067   }
04068   /* Call the corresponding callback to inform upper layer of End of Transfer */
04069   else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
04070   {
04071     hi2c->State = HAL_I2C_STATE_READY;
04072
04073     /* Process Unlocked */
04074     __HAL_UNLOCK(hi2c);
04075
04076     /* Call the Slave Rx Complete callback */
04077     HAL_I2C_SlaveRxCpltCallback(hi2c);
04078   }
04079   else
04080   {
04081     hi2c->State = HAL_I2C_STATE_READY;
04082
04083     /* Process Unlocked */
04084     __HAL_UNLOCK(hi2c);
04085
04086     /* Call the Slave Tx Complete callback */
04087     HAL_I2C_SlaveTxCpltCallback(hi2c);
04088   }
04089 }
04090
04091 /**
04092   * @brief  I2C Listen complete process.
04093   * @param  hi2c I2C handle.
04094   * @param  ITFlags Interrupt flags to handle.
04095   * @retval None
04096   */
04097 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
04098 {
04099   /* Reset handle parameters */
04100   hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04101   hi2c->PreviousState = I2C_STATE_NONE;
04102   hi2c->State = HAL_I2C_STATE_READY;
04103   hi2c->Mode = HAL_I2C_MODE_NONE;
04104   hi2c->XferISR = NULL;
04105
04106   /* Store Last receive data if any */
04107   if(((ITFlags & I2C_FLAG_RXNE) != RESET))
04108   {
04109     /* Read data from RXDR */
04110     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
04111
04112     if((hi2c->XferSize > 0U))
04113     {
04114       hi2c->XferSize--;
04115       hi2c->XferCount--;
04116
04117       /* Set ErrorCode corresponding to a Non-Acknowledge */
04118       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04119     }
04120   }
04121
04122   /* Disable all Interrupts*/
04123   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04124
04125   /* Clear NACK Flag */
04126   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04127
04128   /* Process Unlocked */
04129   __HAL_UNLOCK(hi2c);
04130
04131   /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04132   HAL_I2C_ListenCpltCallback(hi2c);
04133 }
04134
04135 /**
04136   * @brief  I2C interrupts error process.
04137   * @param  hi2c I2C handle.
04138   * @param  ErrorCode Error code to handle.
04139   * @retval None
04140   */
04141 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
04142 {
04143   /* Reset handle parameters */
04144   hi2c->Mode          = HAL_I2C_MODE_NONE;
04145   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
04146   hi2c->XferCount     = 0U;
04147
04148   /* Set new error code */
04149   hi2c->ErrorCode |= ErrorCode;
04150
04151   /* Disable Interrupts */
04152   if((hi2c->State == HAL_I2C_STATE_LISTEN)         ||
04153      (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
04154      (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
04155   {
04156     /* Disable all interrupts, except interrupts related to LISTEN state */
04157     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04158
04159     /* keep HAL_I2C_STATE_LISTEN if set */
04160     hi2c->State         = HAL_I2C_STATE_LISTEN;
04161     hi2c->PreviousState = I2C_STATE_NONE;
04162     hi2c->XferISR       = I2C_Slave_ISR_IT;
04163   }
04164   else
04165   {
04166     /* Disable all interrupts */
04167     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04168
04169     /* If state is an abort treatment on goind, don't change state */
04170     /* This change will be do later */
04171     if(hi2c->State != HAL_I2C_STATE_ABORT)
04172     {
04173       /* Set HAL_I2C_STATE_READY */
04174       hi2c->State         = HAL_I2C_STATE_READY;
04175     }
04176     hi2c->PreviousState = I2C_STATE_NONE;
04177     hi2c->XferISR       = NULL;
04178   }
04179
04180   /* Abort DMA TX transfer if any */
04181   if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04182   {
04183     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04184
04185     /* Set the I2C DMA Abort callback :
04186        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04187     hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04188
04189     /* Process Unlocked */
04190     __HAL_UNLOCK(hi2c);
04191
04192     /* Abort DMA TX */
04193     if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04194     {
04195       /* Call Directly XferAbortCallback function in case of error */
04196       hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04197     }
04198   }
04199   /* Abort DMA RX transfer if any */
04200   else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
04201   {
04202     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04203
04204     /* Set the I2C DMA Abort callback :
04205        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04206     hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
04207
04208     /* Process Unlocked */
04209     __HAL_UNLOCK(hi2c);
04210
04211     /* Abort DMA RX */
04212     if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
04213     {
04214       /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
04215       hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
04216     }
04217   }
04218   else if(hi2c->State == HAL_I2C_STATE_ABORT)
04219   {
04220     hi2c->State = HAL_I2C_STATE_READY;
04221
04222     /* Process Unlocked */
04223     __HAL_UNLOCK(hi2c);
04224
04225     /* Call the corresponding callback to inform upper layer of End of Transfer */
04226     HAL_I2C_AbortCpltCallback(hi2c);
04227   }
04228   else
04229   {
04230     /* Process Unlocked */
04231     __HAL_UNLOCK(hi2c);
04232
04233     /* Call the corresponding callback to inform upper layer of End of Transfer */
04234     HAL_I2C_ErrorCallback(hi2c);
04235   }
04236 }
04237
04238 /**
04239   * @brief  I2C Tx data register flush process.
04240   * @param  hi2c I2C handle.
04241   * @retval None
04242   */
04243 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
04244 {
04245   /* If a pending TXIS flag is set */
04246   /* Write a dummy data in TXDR to clear it */
04247   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
04248   {
04249      hi2c->Instance->TXDR = 0x00U;
04250   }
04251
04252   /* Flush TX register if not empty */
04253   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
04254   {
04255     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
04256   }
04257 }
04258
04259 /**
04260   * @brief  DMA I2C master transmit process complete callback.
04261   * @param  hdma DMA handle
04262   * @retval None
04263   */
04264 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
04265 {
04266   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04267
04268   /* Disable DMA Request */
04269   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04270
04271   /* If last transfer, enable STOP interrupt */
04272   if(hi2c->XferCount == 0U)
04273   {
04274     /* Enable STOP interrupt */
04275     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04276   }
04277   /* else prepare a new DMA transfer and enable TCReload interrupt */
04278   else
04279   {
04280     /* Update Buffer pointer */
04281     hi2c->pBuffPtr += hi2c->XferSize;
04282
04283     /* Set the XferSize to transfer */
04284     if(hi2c->XferCount > MAX_NBYTE_SIZE)
04285     {
04286       hi2c->XferSize = MAX_NBYTE_SIZE;
04287     }
04288     else
04289     {
04290       hi2c->XferSize = hi2c->XferCount;
04291     }
04292
04293     /* Enable the DMA channel */
04294     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
04295
04296     /* Enable TC interrupts */
04297     I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
04298   }
04299 }
04300
04301 /**
04302   * @brief  DMA I2C slave transmit process complete callback.
04303   * @param  hdma DMA handle
04304   * @retval None
04305   */
04306 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
04307 {
04308   /* No specific action, Master fully manage the generation of STOP condition */
04309   /* Mean that this generation can arrive at any time, at the end or during DMA process */
04310   /* So STOP condition should be manage through Interrupt treatment */
04311 }
04312
04313 /**
04314   * @brief DMA I2C master receive process complete callback.
04315   * @param  hdma DMA handle
04316   * @retval None
04317   */
04318 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
04319 {
04320   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04321
04322   /* Disable DMA Request */
04323   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04324
04325   /* If last transfer, enable STOP interrupt */
04326   if(hi2c->XferCount == 0U)
04327   {
04328     /* Enable STOP interrupt */
04329     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04330   }
04331   /* else prepare a new DMA transfer and enable TCReload interrupt */
04332   else
04333   {
04334     /* Update Buffer pointer */
04335     hi2c->pBuffPtr += hi2c->XferSize;
04336
04337     /* Set the XferSize to transfer */
04338     if(hi2c->XferCount > MAX_NBYTE_SIZE)
04339     {
04340       hi2c->XferSize = MAX_NBYTE_SIZE;
04341     }
04342     else
04343     {
04344       hi2c->XferSize = hi2c->XferCount;
04345     }
04346
04347     /* Enable the DMA channel */
04348     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
04349
04350     /* Enable TC interrupts */
04351     I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
04352   }
04353 }
04354
04355 /**
04356   * @brief  DMA I2C slave receive process complete callback.
04357   * @param  hdma DMA handle
04358   * @retval None
04359   */
04360 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
04361 {
04362   /* No specific action, Master fully manage the generation of STOP condition */
04363   /* Mean that this generation can arrive at any time, at the end or during DMA process */
04364   /* So STOP condition should be manage through Interrupt treatment */
04365 }
04366
04367 /**
04368   * @brief  DMA I2C communication error callback.
04369   * @param hdma DMA handle
04370   * @retval None
04371   */
04372 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
04373 {
04374   I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04375
04376   /* Disable Acknowledge */
04377   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04378
04379   /* Call the corresponding callback to inform upper layer of End of Transfer */
04380   I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
04381 }
04382
04383 /**
04384   * @brief DMA I2C communication abort callback
04385   *        (To be called at end of DMA Abort procedure).
04386   * @param hdma: DMA handle.
04387   * @retval None
04388   */
04389 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
04390 {
04391   I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04392
04393   /* Disable Acknowledge */
04394   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04395
04396   /* Reset AbortCpltCallback */
04397   hi2c->hdmatx->XferAbortCallback = NULL;
04398   hi2c->hdmarx->XferAbortCallback = NULL;
04399
04400   /* Check if come from abort from user */
04401   if(hi2c->State == HAL_I2C_STATE_ABORT)
04402   {
04403     hi2c->State = HAL_I2C_STATE_READY;
04404
04405     /* Call the corresponding callback to inform upper layer of End of Transfer */
04406     HAL_I2C_AbortCpltCallback(hi2c);
04407   }
04408   else
04409   {
04410     /* Call the corresponding callback to inform upper layer of End of Transfer */
04411     HAL_I2C_ErrorCallback(hi2c);
04412   }
04413 }
04414
04415 /**
04416   * @brief  This function handles I2C Communication Timeout.
04417   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04418   *                the configuration information for the specified I2C.
04419   * @param  Flag Specifies the I2C flag to check.
04420   * @param  Status The new Flag status (SET or RESET).
04421   * @param  Timeout Timeout duration
04422   * @param  Tickstart Tick start value
04423   * @retval HAL status
04424   */
04425 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
04426 {
04427   while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
04428   {
04429     /* Check for the Timeout */
04430     if(Timeout != HAL_MAX_DELAY)
04431     {
04432       if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
04433       {
04434         hi2c->State= HAL_I2C_STATE_READY;
04435         hi2c->Mode = HAL_I2C_MODE_NONE;
04436
04437         /* Process Unlocked */
04438         __HAL_UNLOCK(hi2c);
04439         return HAL_TIMEOUT;
04440       }
04441     }
04442   }
04443   return HAL_OK;
04444 }
04445
04446 /**
04447   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
04448   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04449   *                the configuration information for the specified I2C.
04450   * @param  Timeout Timeout duration
04451   * @param  Tickstart Tick start value
04452   * @retval HAL status
04453   */
04454 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04455 {
04456   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
04457   {
04458     /* Check if a NACK is detected */
04459     if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04460     {
04461       return HAL_ERROR;
04462     }
04463
04464     /* Check for the Timeout */
04465     if(Timeout != HAL_MAX_DELAY)
04466     {
04467       if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04468       {
04469         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04470         hi2c->State= HAL_I2C_STATE_READY;
04471         hi2c->Mode = HAL_I2C_MODE_NONE;
04472
04473         /* Process Unlocked */
04474         __HAL_UNLOCK(hi2c);
04475
04476         return HAL_TIMEOUT;
04477       }
04478     }
04479   }
04480   return HAL_OK;
04481 }
04482
04483 /**
04484   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
04485   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04486   *                the configuration information for the specified I2C.
04487   * @param  Timeout Timeout duration
04488   * @param  Tickstart Tick start value
04489   * @retval HAL status
04490   */
04491 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04492 {
04493   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04494   {
04495     /* Check if a NACK is detected */
04496     if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04497     {
04498       return HAL_ERROR;
04499     }
04500
04501     /* Check for the Timeout */
04502     if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04503     {
04504       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04505       hi2c->State= HAL_I2C_STATE_READY;
04506       hi2c->Mode = HAL_I2C_MODE_NONE;
04507
04508       /* Process Unlocked */
04509       __HAL_UNLOCK(hi2c);
04510
04511       return HAL_TIMEOUT;
04512     }
04513   }
04514   return HAL_OK;
04515 }
04516
04517 /**
04518   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
04519   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04520   *                the configuration information for the specified I2C.
04521   * @param  Timeout Timeout duration
04522   * @param  Tickstart Tick start value
04523   * @retval HAL status
04524   */
04525 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04526 {
04527   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
04528   {
04529     /* Check if a NACK is detected */
04530     if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04531     {
04532       return HAL_ERROR;
04533     }
04534
04535     /* Check if a STOPF is detected */
04536     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
04537     {
04538       /* Clear STOP Flag */
04539       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04540
04541       /* Clear Configuration Register 2 */
04542       I2C_RESET_CR2(hi2c);
04543
04544       hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04545       hi2c->State= HAL_I2C_STATE_READY;
04546       hi2c->Mode = HAL_I2C_MODE_NONE;
04547
04548       /* Process Unlocked */
04549       __HAL_UNLOCK(hi2c);
04550
04551       return HAL_ERROR;
04552     }
04553
04554     /* Check for the Timeout */
04555     if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04556     {
04557       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04558       hi2c->State= HAL_I2C_STATE_READY;
04559
04560       /* Process Unlocked */
04561       __HAL_UNLOCK(hi2c);
04562
04563       return HAL_TIMEOUT;
04564     }
04565   }
04566   return HAL_OK;
04567 }
04568
04569 /**
04570   * @brief  This function handles Acknowledge failed detection during an I2C Communication.
04571   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04572   *                the configuration information for the specified I2C.
04573   * @param  Timeout Timeout duration
04574   * @param  Tickstart Tick start value
04575   * @retval HAL status
04576   */
04577 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04578 {
04579   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
04580   {
04581     /* Wait until STOP Flag is reset */
04582     /* AutoEnd should be initiate after AF */
04583     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04584     {
04585       /* Check for the Timeout */
04586       if(Timeout != HAL_MAX_DELAY)
04587       {
04588       if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04589         {
04590           hi2c->State= HAL_I2C_STATE_READY;
04591           hi2c->Mode = HAL_I2C_MODE_NONE;
04592
04593           /* Process Unlocked */
04594           __HAL_UNLOCK(hi2c);
04595           return HAL_TIMEOUT;
04596         }
04597       }
04598     }
04599
04600     /* Clear NACKF Flag */
04601     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04602
04603     /* Clear STOP Flag */
04604     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04605
04606     /* Flush TX register */
04607     I2C_Flush_TXDR(hi2c);
04608
04609     /* Clear Configuration Register 2 */
04610     I2C_RESET_CR2(hi2c);
04611
04612     hi2c->ErrorCode = HAL_I2C_ERROR_AF;
04613     hi2c->State= HAL_I2C_STATE_READY;
04614     hi2c->Mode = HAL_I2C_MODE_NONE;
04615
04616     /* Process Unlocked */
04617     __HAL_UNLOCK(hi2c);
04618
04619     return HAL_ERROR;
04620   }
04621   return HAL_OK;
04622 }
04623
04624 /**
04625   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
04626   * @param  hi2c I2C handle.
04627   * @param  DevAddress Specifies the slave address to be programmed.
04628   * @param  Size Specifies the number of bytes to be programmed.
04629   *   This parameter must be a value between 0 and 255.
04630   * @param  Mode New state of the I2C START condition generation.
04631   *   This parameter can be one of the following values:
04632   *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
04633   *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
04634   *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
04635   * @param  Request New state of the I2C START condition generation.
04636   *   This parameter can be one of the following values:
04637   *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
04638   *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
04639   *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
04640   *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
04641   * @retval None
04642   */
04643 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
04644 {
04645   uint32_t tmpreg = 0U;
04646
04647   /* Check the parameters */
04648   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
04649   assert_param(IS_TRANSFER_MODE(Mode));
04650   assert_param(IS_TRANSFER_REQUEST(Request));
04651
04652   /* Get the CR2 register value */
04653   tmpreg = hi2c->Instance->CR2;
04654
04655   /* clear tmpreg specific bits */
04656   tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
04657
04658   /* update tmpreg */
04659   tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
04660             (uint32_t)Mode | (uint32_t)Request);
04661
04662   /* update CR2 register */
04663   hi2c->Instance->CR2 = tmpreg;
04664 }
04665
04666 /**
04667   * @brief  Manage the enabling of Interrupts.
04668   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04669   *                the configuration information for the specified I2C.
04670   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
04671   * @retval HAL status
04672   */
04673 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
04674 {
04675   uint32_t tmpisr = 0U;
04676
04677   if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
04678      (hi2c->XferISR == I2C_Slave_ISR_DMA))
04679   {
04680     if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04681     {
04682       /* Enable ERR, STOP, NACK and ADDR interrupts */
04683       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04684     }
04685
04686     if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
04687     {
04688       /* Enable ERR and NACK interrupts */
04689       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
04690     }
04691
04692     if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04693     {
04694       /* Enable STOP interrupts */
04695       tmpisr |= I2C_IT_STOPI;
04696     }
04697
04698     if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
04699     {
04700       /* Enable TC interrupts */
04701       tmpisr |= I2C_IT_TCI;
04702     }
04703   }
04704   else
04705   {
04706     if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04707     {
04708       /* Enable ERR, STOP, NACK, and ADDR interrupts */
04709       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04710     }
04711
04712     if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
04713     {
04714       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
04715       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
04716     }
04717
04718     if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
04719     {
04720       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
04721       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
04722     }
04723
04724     if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04725     {
04726       /* Enable STOP interrupts */
04727       tmpisr |= I2C_IT_STOPI;
04728     }
04729   }
04730
04731   /* Enable interrupts only at the end */
04732   /* to avoid the risk of I2C interrupt handle execution before */
04733   /* all interrupts requested done */
04734   __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
04735
04736   return HAL_OK;
04737 }
04738
04739 /**
04740   * @brief  Manage the disabling of Interrupts.
04741   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04742   *                the configuration information for the specified I2C.
04743   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
04744   * @retval HAL status
04745   */
04746 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
04747 {
04748   uint32_t tmpisr = 0U;
04749
04750   if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
04751   {
04752     /* Disable TC and TXI interrupts */
04753     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
04754
04755     if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
04756     {
04757       /* Disable NACK and STOP interrupts */
04758       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04759     }
04760   }
04761
04762   if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
04763   {
04764     /* Disable TC and RXI interrupts */
04765     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
04766
04767     if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
04768     {
04769       /* Disable NACK and STOP interrupts */
04770       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04771     }
04772   }
04773
04774   if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04775   {
04776     /* Disable ADDR, NACK and STOP interrupts */
04777     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04778   }
04779
04780   if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
04781   {
04782     /* Enable ERR and NACK interrupts */
04783     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
04784   }
04785
04786   if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04787   {
04788     /* Enable STOP interrupts */
04789     tmpisr |= I2C_IT_STOPI;
04790   }
04791
04792   if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
04793   {
04794     /* Enable TC interrupts */
04795     tmpisr |= I2C_IT_TCI;
04796   }
04797
04798   /* Disable interrupts only at the end */
04799   /* to avoid a breaking situation like at "t" time */
04800   /* all disable interrupts request are not done */
04801   __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
04802
04803   return HAL_OK;
04804 }
04805
04806 /**
04807   * @}
04808   */
04809
04810 #endif /* HAL_I2C_MODULE_ENABLED */
04811 /**
04812   * @}
04813   */
04814
04815 /**
04816   * @}
04817   */
04818
04819 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_i2c.h Source File

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stm32l4xx_hal_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_i2c.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of I2C HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_I2C_H
00040 #define __STM32L4xx_HAL_I2C_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2C
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup I2C_Exported_Types I2C Exported Types
00059   * @{
00060   */
00061
00062 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
00063   * @brief  I2C Configuration Structure definition
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
00069                                   This parameter calculated by referring to I2C initialization
00070                                          section in Reference manual */
00071
00072   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
00073                                   This parameter can be a 7-bit or 10-bit address. */
00074
00075   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00076                                   This parameter can be a value of @ref I2C_ADDRESSING_MODE */
00077
00078   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
00079                                   This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
00080
00081   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
00082                                   This parameter can be a 7-bit address. */
00083
00084   uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
00085                                   This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
00086
00087   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
00088                                   This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
00089
00090   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
00091                                   This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
00092
00093 }I2C_InitTypeDef;
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup HAL_state_structure_definition HAL state structure definition
00100   * @brief  HAL State structure definition
00101   * @note  HAL I2C State value coding follow below described bitmap :\n
00102   *          b7-b6  Error information\n
00103   *             00 : No Error\n
00104   *             01 : Abort (Abort user request on going)\n
00105   *             10 : Timeout\n
00106   *             11 : Error\n
00107   *          b5     IP initilisation status\n
00108   *             0  : Reset (IP not initialized)\n
00109   *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
00110   *          b4     (not used)\n
00111   *             x  : Should be set to 0\n
00112   *          b3\n
00113   *             0  : Ready or Busy (No Listen mode ongoing)\n
00114   *             1  : Listen (IP in Address Listen Mode)\n
00115   *          b2     Intrinsic process state\n
00116   *             0  : Ready\n
00117   *             1  : Busy (IP busy with some configuration or internal operations)\n
00118   *          b1     Rx state\n
00119   *             0  : Ready (no Rx operation ongoing)\n
00120   *             1  : Busy (Rx operation ongoing)\n
00121   *          b0     Tx state\n
00122   *             0  : Ready (no Tx operation ongoing)\n
00123   *             1  : Busy (Tx operation ongoing)
00124   * @{
00125   */
00126 typedef enum
00127 {
00128   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
00129   HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
00130   HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
00131   HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
00132   HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
00133   HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
00134   HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
00135                                                  process is ongoing                         */
00136   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
00137                                                  process is ongoing                         */
00138   HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
00139   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
00140   HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
00141
00142 }HAL_I2C_StateTypeDef;
00143
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
00149   * @brief  HAL Mode structure definition
00150   * @note  HAL I2C Mode value coding follow below described bitmap :\n
00151   *          b7     (not used)\n
00152   *             x  : Should be set to 0\n
00153   *          b6\n
00154   *             0  : None\n
00155   *             1  : Memory (HAL I2C communication is in Memory Mode)\n
00156   *          b5\n
00157   *             0  : None\n
00158   *             1  : Slave (HAL I2C communication is in Slave Mode)\n
00159   *          b4\n
00160   *             0  : None\n
00161   *             1  : Master (HAL I2C communication is in Master Mode)\n
00162   *          b3-b2-b1-b0  (not used)\n
00163   *             xxxx : Should be set to 0000
00164   * @{
00165   */
00166 typedef enum
00167 {
00168   HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
00169   HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
00170   HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
00171   HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
00172
00173 }HAL_I2C_ModeTypeDef;
00174
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
00180   * @brief  I2C Error Code definition
00181   * @{
00182   */
00183 #define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
00184 #define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
00185 #define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
00186 #define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
00187 #define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
00188 #define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
00189 #define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
00190 #define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
00191 /**
00192   * @}
00193   */
00194
00195 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
00196   * @brief  I2C handle Structure definition
00197   * @{
00198   */
00199 typedef struct __I2C_HandleTypeDef
00200 {
00201   I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
00202
00203   I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
00204
00205   uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
00206
00207   uint16_t                   XferSize;       /*!< I2C transfer size                         */
00208
00209   __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
00210
00211   __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
00212                                                   be a value of @ref I2C_XFEROPTIONS */
00213
00214   __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
00215
00216   HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
00217
00218   DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
00219
00220   DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
00221
00222   HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
00223
00224   __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
00225
00226   __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
00227
00228   __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
00229
00230   __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
00231 }I2C_HandleTypeDef;
00232 /**
00233   * @}
00234   */
00235
00236 /**
00237   * @}
00238   */
00239 /* Exported constants --------------------------------------------------------*/
00240
00241 /** @defgroup I2C_Exported_Constants I2C Exported Constants
00242   * @{
00243   */
00244
00245 /** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
00246   * @{
00247   */
00248 #define I2C_NO_OPTION_FRAME             (0xFFFF0000U)
00249 #define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
00250 #define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00251 #define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
00252 #define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
00258   * @{
00259   */
00260 #define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
00261 #define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
00267   * @{
00268   */
00269 #define I2C_DUALADDRESS_DISABLE         (0x00000000U)
00270 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
00276   * @{
00277   */
00278 #define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
00279 #define I2C_OA2_MASK01                  ((uint8_t)0x01U)
00280 #define I2C_OA2_MASK02                  ((uint8_t)0x02U)
00281 #define I2C_OA2_MASK03                  ((uint8_t)0x03U)
00282 #define I2C_OA2_MASK04                  ((uint8_t)0x04U)
00283 #define I2C_OA2_MASK05                  ((uint8_t)0x05U)
00284 #define I2C_OA2_MASK06                  ((uint8_t)0x06U)
00285 #define I2C_OA2_MASK07                  ((uint8_t)0x07U)
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
00291   * @{
00292   */
00293 #define I2C_GENERALCALL_DISABLE         (0x00000000U)
00294 #define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
00300   * @{
00301   */
00302 #define I2C_NOSTRETCH_DISABLE           (0x00000000U)
00303 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
00309   * @{
00310   */
00311 #define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
00312 #define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup I2C_XferDirection I2C Transfer Direction
00318   * @{
00319   */
00320 #define I2C_DIRECTION_TRANSMIT          (0x00000000U)
00321 #define I2C_DIRECTION_RECEIVE           (0x00000001U)
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
00327   * @{
00328   */
00329 #define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
00330 #define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
00331 #define  I2C_SOFTEND_MODE               (0x00000000U)
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
00337   * @{
00338   */
00339 #define  I2C_NO_STARTSTOP               (0x00000000U)
00340 #define  I2C_GENERATE_STOP              I2C_CR2_STOP
00341 #define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
00342 #define  I2C_GENERATE_START_WRITE       I2C_CR2_START
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
00348   * @brief I2C Interrupt definition
00349   *        Elements values convention: 0xXXXXXXXX
00350   *           - XXXXXXXX  : Interrupt control mask
00351   * @{
00352   */
00353 #define I2C_IT_ERRI                     I2C_CR1_ERRIE
00354 #define I2C_IT_TCI                      I2C_CR1_TCIE
00355 #define I2C_IT_STOPI                    I2C_CR1_STOPIE
00356 #define I2C_IT_NACKI                    I2C_CR1_NACKIE
00357 #define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
00358 #define I2C_IT_RXI                      I2C_CR1_RXIE
00359 #define I2C_IT_TXI                      I2C_CR1_TXIE
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup I2C_Flag_definition I2C Flag definition
00365   * @{
00366   */
00367 #define I2C_FLAG_TXE                    I2C_ISR_TXE
00368 #define I2C_FLAG_TXIS                   I2C_ISR_TXIS
00369 #define I2C_FLAG_RXNE                   I2C_ISR_RXNE
00370 #define I2C_FLAG_ADDR                   I2C_ISR_ADDR
00371 #define I2C_FLAG_AF                     I2C_ISR_NACKF
00372 #define I2C_FLAG_STOPF                  I2C_ISR_STOPF
00373 #define I2C_FLAG_TC                     I2C_ISR_TC
00374 #define I2C_FLAG_TCR                    I2C_ISR_TCR
00375 #define I2C_FLAG_BERR                   I2C_ISR_BERR
00376 #define I2C_FLAG_ARLO                   I2C_ISR_ARLO
00377 #define I2C_FLAG_OVR                    I2C_ISR_OVR
00378 #define I2C_FLAG_PECERR                 I2C_ISR_PECERR
00379 #define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
00380 #define I2C_FLAG_ALERT                  I2C_ISR_ALERT
00381 #define I2C_FLAG_BUSY                   I2C_ISR_BUSY
00382 #define I2C_FLAG_DIR                    I2C_ISR_DIR
00383 /**
00384   * @}
00385   */
00386
00387 /**
00388   * @}
00389   */
00390
00391 /* Exported macros -----------------------------------------------------------*/
00392
00393 /** @defgroup I2C_Exported_Macros I2C Exported Macros
00394   * @{
00395   */
00396
00397 /** @brief Reset I2C handle state.
00398   * @param  __HANDLE__ specifies the I2C Handle.
00399   * @retval None
00400   */
00401 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
00402
00403 /** @brief  Enable the specified I2C interrupt.
00404   * @param  __HANDLE__ specifies the I2C Handle.
00405   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00406   *        This parameter can be one of the following values:
00407   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00408   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00409   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00410   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00411   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00412   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00413   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00414   *
00415   * @retval None
00416   */
00417 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00418
00419 /** @brief  Disable the specified I2C interrupt.
00420   * @param  __HANDLE__ specifies the I2C Handle.
00421   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00422   *        This parameter can be one of the following values:
00423   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00424   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00425   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00426   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00427   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00428   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00429   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00430   *
00431   * @retval None
00432   */
00433 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00434
00435 /** @brief  Check whether the specified I2C interrupt source is enabled or not.
00436   * @param  __HANDLE__ specifies the I2C Handle.
00437   * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
00438   *          This parameter can be one of the following values:
00439   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00440   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00441   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00442   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00443   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00444   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00445   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00446   *
00447   * @retval The new state of __INTERRUPT__ (SET or RESET).
00448   */
00449 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00450
00451 /** @brief  Check whether the specified I2C flag is set or not.
00452   * @param  __HANDLE__ specifies the I2C Handle.
00453   * @param  __FLAG__ specifies the flag to check.
00454   *        This parameter can be one of the following values:
00455   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00456   *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
00457   *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
00458   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00459   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00460   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00461   *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
00462   *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
00463   *            @arg @ref I2C_FLAG_BERR    Bus error
00464   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00465   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00466   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00467   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00468   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00469   *            @arg @ref I2C_FLAG_BUSY    Bus busy
00470   *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
00471   *
00472   * @retval The new state of __FLAG__ (SET or RESET).
00473   */
00474 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00475
00476 /** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
00477   * @param  __HANDLE__ specifies the I2C Handle.
00478   * @param  __FLAG__ specifies the flag to clear.
00479   *          This parameter can be any combination of the following values:
00480   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00481   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00482   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00483   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00484   *            @arg @ref I2C_FLAG_BERR    Bus error
00485   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00486   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00487   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00488   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00489   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00490   *
00491   * @retval None
00492   */
00493 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
00494                                                                                  : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
00495
00496 /** @brief  Enable the specified I2C peripheral.
00497   * @param  __HANDLE__ specifies the I2C Handle.
00498   * @retval None
00499   */
00500 #define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
00501
00502 /** @brief  Disable the specified I2C peripheral.
00503   * @param  __HANDLE__ specifies the I2C Handle.
00504   * @retval None
00505   */
00506 #define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00507
00508 /** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
00509   * @param  __HANDLE__: specifies the I2C Handle.
00510   * @retval None
00511   */
00512 #define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00513 /**
00514   * @}
00515   */
00516
00517 /* Include I2C HAL Extended module */
00518 #include "stm32l4xx_hal_i2c_ex.h"
00519
00520 /* Exported functions --------------------------------------------------------*/
00521 /** @addtogroup I2C_Exported_Functions
00522   * @{
00523   */
00524
00525 /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00526   * @{
00527   */
00528 /* Initialization and de-initialization functions******************************/
00529 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
00530 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
00531 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
00532 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
00533 /**
00534   * @}
00535   */
00536
00537 /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
00538   * @{
00539   */
00540 /* IO operation functions  ****************************************************/
00541  /******* Blocking mode: Polling */
00542 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00543 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00544 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00545 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00546 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00547 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00548 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00549
00550  /******* Non-Blocking mode: Interrupt */
00551 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00552 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00553 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00554 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00555 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00556 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00557
00558 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00559 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00560 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00561 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00562 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
00563 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
00564 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
00565
00566  /******* Non-Blocking mode: DMA */
00567 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00568 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00569 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00570 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00571 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00572 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00573 /**
00574   * @}
00575   */
00576
00577 /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00578  * @{
00579  */
00580 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00581 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
00582 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
00583 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
00584 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
00585 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
00586 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
00587 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00588 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
00589 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
00590 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
00591 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
00592 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
00593 /**
00594   * @}
00595   */
00596
00597 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
00598   * @{
00599   */
00600 /* Peripheral State, Mode and Error functions  *********************************/
00601 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
00602 HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
00603 uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
00604
00605 /**
00606   * @}
00607   */
00608
00609 /**
00610   * @}
00611   */
00612
00613 /* Private constants ---------------------------------------------------------*/
00614 /** @defgroup I2C_Private_Constants I2C Private Constants
00615   * @{
00616   */
00617
00618 /**
00619   * @}
00620   */
00621
00622 /* Private macros ------------------------------------------------------------*/
00623 /** @defgroup I2C_Private_Macro I2C Private Macros
00624   * @{
00625   */
00626
00627 #define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
00628                                          ((MODE) == I2C_ADDRESSINGMODE_10BIT))
00629
00630 #define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
00631                                          ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
00632
00633 #define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
00634                                          ((MASK) == I2C_OA2_MASK01) || \
00635                                          ((MASK) == I2C_OA2_MASK02) || \
00636                                          ((MASK) == I2C_OA2_MASK03) || \
00637                                          ((MASK) == I2C_OA2_MASK04) || \
00638                                          ((MASK) == I2C_OA2_MASK05) || \
00639                                          ((MASK) == I2C_OA2_MASK06) || \
00640                                          ((MASK) == I2C_OA2_MASK07))
00641
00642 #define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
00643                                          ((CALL) == I2C_GENERALCALL_ENABLE))
00644
00645 #define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
00646                                          ((STRETCH) == I2C_NOSTRETCH_ENABLE))
00647
00648 #define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
00649                                          ((SIZE) == I2C_MEMADD_SIZE_16BIT))
00650
00651 #define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
00652                                          ((MODE) == I2C_AUTOEND_MODE) || \
00653                                          ((MODE) == I2C_SOFTEND_MODE))
00654
00655 #define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
00656                                          ((REQUEST) == I2C_GENERATE_START_READ)  || \
00657                                          ((REQUEST) == I2C_GENERATE_START_WRITE) || \
00658                                          ((REQUEST) == I2C_NO_STARTSTOP))
00659
00660 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
00661                                                    ((REQUEST) == I2C_NEXT_FRAME)           || \
00662                                                    ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
00663                                                    ((REQUEST) == I2C_LAST_FRAME))
00664
00665 #define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00666
00667 #define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
00668 #define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
00669 #define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00670 #define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
00671 #define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
00672
00673 #define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
00674 #define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
00675
00676 #define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
00677 #define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00678
00679 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00680                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00681 /**
00682   * @}
00683   */
00684
00685 /* Private Functions ---------------------------------------------------------*/
00686 /** @defgroup I2C_Private_Functions I2C Private Functions
00687   * @{
00688   */
00689 /* Private functions are defined in stm32l4xx_hal_i2c.c file */
00690 /**
00691   * @}
00692   */
00693
00694 /**
00695   * @}
00696   */
00697
00698 /**
00699   * @}
00700   */
00701
00702 #ifdef __cplusplus
00703 }
00704 #endif
00705
00706
00707 #endif /* __STM32L4xx_HAL_I2C_H */
00708
00709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_i2c_ex.c Source File

  • File List
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  • STM32L4xx_HAL_Driver
  • Src
stm32l4xx_hal_i2c_ex.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_i2c_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   I2C Extended HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of I2C Extended peripheral:
00010   *           + Extended features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### I2C peripheral Extended features  #####
00015   ==============================================================================
00016
00017   [..] Comparing to other previous devices, the I2C interface for STM32L4xx
00018        devices contains the following additional features
00019
00020        (+) Possibility to disable or enable Analog Noise Filter
00021        (+) Use of a configured Digital Noise Filter
00022        (+) Disable or enable wakeup from Stop modes
00023
00024                      ##### How to use this driver #####
00025   ==============================================================================
00026   [..] This driver provides functions to configure Noise Filter and Wake Up Feature
00027     (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
00028     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
00029     (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
00030           (++) HAL_I2CEx_EnableWakeUp()
00031           (++) HAL_I2CEx_DisableWakeUp()
00032     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
00033           (++) HAL_I2CEx_EnableFastModePlus()
00034           (++) HAL_I2CEx_DisbleFastModePlus()
00035   @endverbatim
00036   ******************************************************************************
00037   * @attention
00038   *
00039   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00040   *
00041   * Redistribution and use in source and binary forms, with or without modification,
00042   * are permitted provided that the following conditions are met:
00043   *   1. Redistributions of source code must retain the above copyright notice,
00044   *      this list of conditions and the following disclaimer.
00045   *   2. Redistributions in binary form must reproduce the above copyright notice,
00046   *      this list of conditions and the following disclaimer in the documentation
00047   *      and/or other materials provided with the distribution.
00048   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00049   *      may be used to endorse or promote products derived from this software
00050   *      without specific prior written permission.
00051   *
00052   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00053   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00054   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00055   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00056   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00057   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00058   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00059   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00060   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00061   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00062   *
00063   ******************************************************************************
00064   */
00065
00066 /* Includes ------------------------------------------------------------------*/
00067 #include "stm32l4xx_hal.h"
00068
00069 /** @addtogroup STM32L4xx_HAL_Driver
00070   * @{
00071   */
00072
00073 /** @defgroup I2CEx I2CEx
00074   * @brief I2C Extended HAL module driver
00075   * @{
00076   */
00077
00078 #ifdef HAL_I2C_MODULE_ENABLED
00079
00080 /* Private typedef -----------------------------------------------------------*/
00081 /* Private define ------------------------------------------------------------*/
00082 /* Private macro -------------------------------------------------------------*/
00083 /* Private variables ---------------------------------------------------------*/
00084 /* Private function prototypes -----------------------------------------------*/
00085 /* Private functions ---------------------------------------------------------*/
00086
00087 /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
00088   * @{
00089   */
00090
00091 /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
00092   * @brief    Extended features functions
00093  *
00094 @verbatim
00095  ===============================================================================
00096                       ##### Extended features functions #####
00097  ===============================================================================
00098     [..] This section provides functions allowing to:
00099       (+) Configure Noise Filters
00100       (+) Configure Wake Up Feature
00101
00102 @endverbatim
00103   * @{
00104   */
00105
00106 /**
00107   * @brief  Configure I2C Analog noise filter.
00108   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00109   *                the configuration information for the specified I2Cx peripheral.
00110   * @param  AnalogFilter New state of the Analog filter.
00111   * @retval HAL status
00112   */
00113 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
00114 {
00115   /* Check the parameters */
00116   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00117   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
00118
00119   if(hi2c->State == HAL_I2C_STATE_READY)
00120   {
00121     /* Process Locked */
00122     __HAL_LOCK(hi2c);
00123
00124     hi2c->State = HAL_I2C_STATE_BUSY;
00125
00126     /* Disable the selected I2C peripheral */
00127     __HAL_I2C_DISABLE(hi2c);
00128
00129     /* Reset I2Cx ANOFF bit */
00130     hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00131
00132     /* Set analog filter bit*/
00133     hi2c->Instance->CR1 |= AnalogFilter;
00134
00135     __HAL_I2C_ENABLE(hi2c);
00136
00137     hi2c->State = HAL_I2C_STATE_READY;
00138
00139     /* Process Unlocked */
00140     __HAL_UNLOCK(hi2c);
00141
00142     return HAL_OK;
00143   }
00144   else
00145   {
00146     return HAL_BUSY;
00147   }
00148 }
00149
00150 /**
00151   * @brief  Configure I2C Digital noise filter.
00152   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00153   *                the configuration information for the specified I2Cx peripheral.
00154   * @param  DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
00155   * @retval HAL status
00156   */
00157 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
00158 {
00159   uint32_t tmpreg = 0U;
00160
00161   /* Check the parameters */
00162   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00163   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
00164
00165   if(hi2c->State == HAL_I2C_STATE_READY)
00166   {
00167     /* Process Locked */
00168     __HAL_LOCK(hi2c);
00169
00170     hi2c->State = HAL_I2C_STATE_BUSY;
00171
00172     /* Disable the selected I2C peripheral */
00173     __HAL_I2C_DISABLE(hi2c);
00174
00175     /* Get the old register value */
00176     tmpreg = hi2c->Instance->CR1;
00177
00178     /* Reset I2Cx DNF bits [11:8] */
00179     tmpreg &= ~(I2C_CR1_DNF);
00180
00181     /* Set I2Cx DNF coefficient */
00182     tmpreg |= DigitalFilter << 8U;
00183
00184     /* Store the new register value */
00185     hi2c->Instance->CR1 = tmpreg;
00186
00187     __HAL_I2C_ENABLE(hi2c);
00188
00189     hi2c->State = HAL_I2C_STATE_READY;
00190
00191     /* Process Unlocked */
00192     __HAL_UNLOCK(hi2c);
00193
00194     return HAL_OK;
00195   }
00196   else
00197   {
00198     return HAL_BUSY;
00199   }
00200 }
00201
00202 /**
00203   * @brief  Enable I2C wakeup from stop mode.
00204   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00205   *                the configuration information for the specified I2Cx peripheral.
00206   * @retval HAL status
00207   */
00208 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
00209 {
00210   /* Check the parameters */
00211   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00212
00213   if(hi2c->State == HAL_I2C_STATE_READY)
00214   {
00215     /* Process Locked */
00216     __HAL_LOCK(hi2c);
00217
00218     hi2c->State = HAL_I2C_STATE_BUSY;
00219
00220     /* Disable the selected I2C peripheral */
00221     __HAL_I2C_DISABLE(hi2c);
00222
00223     /* Enable wakeup from stop mode */
00224     hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
00225
00226     __HAL_I2C_ENABLE(hi2c);
00227
00228     hi2c->State = HAL_I2C_STATE_READY;
00229
00230     /* Process Unlocked */
00231     __HAL_UNLOCK(hi2c);
00232
00233     return HAL_OK;
00234   }
00235   else
00236   {
00237     return HAL_BUSY;
00238   }
00239 }
00240
00241
00242 /**
00243   * @brief  Disable I2C wakeup from stop mode.
00244   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00245   *                the configuration information for the specified I2Cx peripheral.
00246   * @retval HAL status
00247   */
00248 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
00249 {
00250   /* Check the parameters */
00251   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00252
00253   if(hi2c->State == HAL_I2C_STATE_READY)
00254   {
00255     /* Process Locked */
00256     __HAL_LOCK(hi2c);
00257
00258     hi2c->State = HAL_I2C_STATE_BUSY;
00259
00260     /* Disable the selected I2C peripheral */
00261     __HAL_I2C_DISABLE(hi2c);
00262
00263     /* Enable wakeup from stop mode */
00264     hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
00265
00266     __HAL_I2C_ENABLE(hi2c);
00267
00268     hi2c->State = HAL_I2C_STATE_READY;
00269
00270     /* Process Unlocked */
00271     __HAL_UNLOCK(hi2c);
00272
00273     return HAL_OK;
00274   }
00275   else
00276   {
00277     return HAL_BUSY;
00278   }
00279 }
00280
00281 /**
00282   * @brief Enable the I2C fast mode plus driving capability.
00283   * @param ConfigFastModePlus Selects the pin.
00284   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00285   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
00286   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00287   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00288   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00289   *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00290   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
00291   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
00292   * @note  For all I2C3 pins fast mode plus driving capability can be enabled
00293   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00294   * @retval None
00295   */
00296 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
00297 {
00298   /* Check the parameter */
00299   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00300
00301   /* Enable SYSCFG clock */
00302   __HAL_RCC_SYSCFG_CLK_ENABLE();
00303
00304   /* Enable fast mode plus driving capability for selected pin */
00305   SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00306 }
00307
00308 /**
00309   * @brief Disable the I2C fast mode plus driving capability.
00310   * @param ConfigFastModePlus Selects the pin.
00311   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00312   * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
00313   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00314   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00315   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00316   *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00317   * @note  For all I2C2 pins fast mode plus driving capability can be disabled
00318   *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
00319   * @note  For all I2C3 pins fast mode plus driving capability can be disabled
00320   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00321   * @retval None
00322   */
00323 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
00324 {
00325   /* Check the parameter */
00326   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00327
00328   /* Enable SYSCFG clock */
00329   __HAL_RCC_SYSCFG_CLK_ENABLE();
00330
00331   /* Disable fast mode plus driving capability for selected pin */
00332   CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00333 }
00334
00335 /**
00336   * @}
00337   */
00338
00339 /**
00340   * @}
00341   */
00342
00343 #endif /* HAL_I2C_MODULE_ENABLED */
00344 /**
00345   * @}
00346   */
00347
00348 /**
00349   * @}
00350   */
00351
00352 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_i2c_ex.h Source File

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stm32l4xx_hal_i2c_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_i2c_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of I2C HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_I2C_EX_H
00040 #define __STM32L4xx_HAL_I2C_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2CEx I2CEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059
00060 /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
00065   * @{
00066   */
00067 #define I2C_ANALOGFILTER_ENABLE         ((uint32_t)0x00000000)
00068 #define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
00069 /**
00070   * @}
00071   */
00072
00073 /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
00074   * @{
00075   */
00076 #define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
00077 #define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
00078 #define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
00079 #define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
00080 #define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
00081 #define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
00082 #define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
00083 /**
00084   * @}
00085   */
00086
00087 /**
00088   * @}
00089   */
00090
00091 /* Exported macro ------------------------------------------------------------*/
00092 /* Exported functions --------------------------------------------------------*/
00093
00094 /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
00095   * @{
00096   */
00097
00098 /** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
00099   * @brief    Extended features functions
00100   * @{
00101   */
00102
00103 /* Peripheral Control functions  ************************************************/
00104 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
00105 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
00106 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
00107 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
00108 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
00109 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
00110
00111 /* Private constants ---------------------------------------------------------*/
00112 /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
00113   * @{
00114   */
00115
00116 /**
00117   * @}
00118   */
00119
00120 /* Private macros ------------------------------------------------------------*/
00121 /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
00122   * @{
00123   */
00124 #define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
00125                                           ((FILTER) == I2C_ANALOGFILTER_DISABLE))
00126
00127 #define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
00128
00129 #if defined (STM32L432xx) || defined (STM32L442xx)
00130 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6)    || \
00131                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7)   || \
00132                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
00133                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
00134 #else
00135 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6)    || \
00136                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7)   || \
00137                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8)   || \
00138                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9)   || \
00139                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
00140                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
00141                                           (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
00142 #endif /* STM32L432xx || STM32L442xx */
00143 /**
00144   * @}
00145   */
00146
00147 /* Private Functions ---------------------------------------------------------*/
00148 /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
00149   * @{
00150   */
00151 /* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */
00152 /**
00153   * @}
00154   */
00155
00156 /**
00157   * @}
00158   */
00159
00160 /**
00161   * @}
00162   */
00163
00164 /**
00165   * @}
00166   */
00167
00168 /**
00169   * @}
00170   */
00171
00172 #ifdef __cplusplus
00173 }
00174 #endif
00175
00176 #endif /* __STM32L4xx_HAL_I2C_EX_H */
00177
00178 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_irda.c Source File

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stm32l4xx_hal_irda.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_irda.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   IRDA HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the IrDA (Infrared Data Association) Peripheral
00010   *          (IRDA)
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral State and Errors functions
00014   *           + Peripheral Control functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                         ##### How to use this driver #####
00019   ==============================================================================
00020   [..]
00021     The IRDA HAL driver can be used as follows:
00022
00023     (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
00024     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
00025         in setting the associated USART or UART in IRDA mode:
00026         (++) Enable the USARTx/UARTx interface clock.
00027         (++) USARTx/UARTx pins configuration:
00028             (+++) Enable the clock for the USARTx/UARTx GPIOs.
00029             (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
00030         (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
00031              and HAL_IRDA_Receive_IT() APIs):
00032             (+++) Configure the USARTx/UARTx interrupt priority.
00033             (+++) Enable the NVIC USARTx/UARTx IRQ handle.
00034             (+++) The specific IRDA interrupts (Transmission complete interrupt,
00035                   RXNE interrupt and Error Interrupts) will be managed using the macros
00036                   __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00037
00038         (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
00039              and HAL_IRDA_Receive_DMA() APIs):
00040             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00041             (+++) Enable the DMAx interface clock.
00042             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00043             (+++) Configure the DMA Tx/Rx channel.
00044             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
00045             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00046
00047     (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
00048         the normal or low power mode and the clock prescaler in the hirda handle Init structure.
00049
00050     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
00051         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00052              by calling the customized HAL_IRDA_MspInit() API.
00053
00054          -@@- The specific IRDA interrupts (Transmission complete interrupt,
00055              RXNE interrupt and Error Interrupts) will be managed using the macros
00056              __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00057
00058     (#) Three operation modes are available within this driver :
00059
00060      *** Polling mode IO operation ***
00061      =================================
00062      [..]
00063        (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
00064        (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
00065
00066      *** Interrupt mode IO operation ***
00067      ===================================
00068      [..]
00069        (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
00070        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00071             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00072        (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
00073        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00074             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00075        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00076             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00077
00078      *** DMA mode IO operation ***
00079      ==============================
00080      [..]
00081        (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
00082        (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
00083             add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
00084        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00085             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00086        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
00087        (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
00088             add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
00089        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00090             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00091        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00092             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00093
00094      *** IRDA HAL driver macros list ***
00095      ====================================
00096      [..]
00097        Below the list of most used macros in IRDA HAL driver.
00098
00099        (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
00100        (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
00101        (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
00102        (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
00103        (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
00104        (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
00105        (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
00106
00107      [..]
00108        (@) You can refer to the IRDA HAL driver header file for more useful macros
00109
00110   @endverbatim
00111   ******************************************************************************
00112   * @attention
00113   *
00114   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00115   *
00116   * Redistribution and use in source and binary forms, with or without modification,
00117   * are permitted provided that the following conditions are met:
00118   *   1. Redistributions of source code must retain the above copyright notice,
00119   *      this list of conditions and the following disclaimer.
00120   *   2. Redistributions in binary form must reproduce the above copyright notice,
00121   *      this list of conditions and the following disclaimer in the documentation
00122   *      and/or other materials provided with the distribution.
00123   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00124   *      may be used to endorse or promote products derived from this software
00125   *      without specific prior written permission.
00126   *
00127   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00128   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00129   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00130   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00131   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00132   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00133   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00134   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00135   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00136   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00137   *
00138   ******************************************************************************
00139   */
00140
00141 /* Includes ------------------------------------------------------------------*/
00142 #include "stm32l4xx_hal.h"
00143
00144 /** @addtogroup STM32L4xx_HAL_Driver
00145   * @{
00146   */
00147
00148 /** @defgroup IRDA IRDA
00149   * @brief HAL IRDA module driver
00150   * @{
00151   */
00152
00153 #ifdef HAL_IRDA_MODULE_ENABLED
00154
00155 /* Private typedef -----------------------------------------------------------*/
00156 /* Private define ------------------------------------------------------------*/
00157 /** @defgroup IRDA_Private_Constants IRDA Private Constants
00158   * @{
00159   */
00160 #define IRDA_TEACK_REACK_TIMEOUT            1000                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
00161 #define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
00162                                    | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
00163 /**
00164   * @}
00165   */
00166
00167 /* Private macros ------------------------------------------------------------*/
00168 /* Private variables ---------------------------------------------------------*/
00169 /* Private function prototypes -----------------------------------------------*/
00170 /** @addtogroup IRDA_Private_Functions
00171   * @{
00172   */
00173 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
00174 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
00175 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
00176 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
00177 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
00178 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00179 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
00180 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00181 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
00182 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
00183 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00184 /**
00185   * @}
00186   */
00187
00188 /* Exported functions --------------------------------------------------------*/
00189
00190 /** @defgroup IRDA_Exported_Functions IRDA Exported Functions
00191   * @{
00192   */
00193
00194 /** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00195   *  @brief    Initialization and Configuration functions
00196   *
00197 @verbatim
00198   ==============================================================================
00199               ##### Initialization and Configuration functions #####
00200   ==============================================================================
00201   [..]
00202   This subsection provides a set of functions allowing to initialize the USARTx
00203   in asynchronous IRDA mode.
00204   (+) For the asynchronous mode only these parameters can be configured:
00205       (++) Baud Rate
00206       (++) Word Length
00207       (++) Parity: If the parity is enabled, then the MSB bit of the data written
00208            in the data register is transmitted but is changed by the parity bit.
00209       (++) Power mode
00210       (++) Prescaler setting
00211       (++) Receiver/transmitter modes
00212
00213   [..]
00214   The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
00215   (details for the procedures are available in reference manual).
00216
00217 @endverbatim
00218
00219   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00220   8-bit or 9-bit), the possible IRDA frame formats are listed in the
00221   following table.
00222
00223     Table 1. IRDA frame format.
00224     +-----------------------------------------------------------------------+
00225     |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
00226     |---------|---------|-----------|---------------------------------------|
00227     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00228     |---------|---------|-----------|---------------------------------------|
00229     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00230     |---------|---------|-----------|---------------------------------------|
00231     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00232     |---------|---------|-----------|---------------------------------------|
00233     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00234     |---------|---------|-----------|---------------------------------------|
00235     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00236     |---------|---------|-----------|---------------------------------------|
00237     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00238     +-----------------------------------------------------------------------+
00239
00240   * @{
00241   */
00242
00243 /**
00244   * @brief Initialize the IRDA mode according to the specified
00245   *        parameters in the IRDA_InitTypeDef and initialize the associated handle.
00246   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00247   *               the configuration information for the specified IRDA module.
00248   * @retval HAL status
00249   */
00250 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
00251 {
00252   /* Check the IRDA handle allocation */
00253   if(hirda == NULL)
00254   {
00255     return HAL_ERROR;
00256   }
00257
00258   /* Check the USART/UART associated to the IRDA handle */
00259   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00260
00261   if(hirda->gState == HAL_IRDA_STATE_RESET)
00262   {
00263     /* Allocate lock resource and initialize it */
00264     hirda->Lock = HAL_UNLOCKED;
00265
00266     /* Init the low level hardware : GPIO, CLOCK */
00267     HAL_IRDA_MspInit(hirda);
00268   }
00269
00270   hirda->gState = HAL_IRDA_STATE_BUSY;
00271
00272   /* Disable the Peripheral to update the configuration registers */
00273   __HAL_IRDA_DISABLE(hirda);
00274
00275   /* Set the IRDA Communication parameters */
00276   if (IRDA_SetConfig(hirda) == HAL_ERROR)
00277   {
00278     return HAL_ERROR;
00279   }
00280
00281   /* In IRDA mode, the following bits must be kept cleared:
00282   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
00283   - SCEN and HDSEL bits in the USART_CR3 register.*/
00284   hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP);
00285   hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
00286
00287   /* set the UART/USART in IRDA mode */
00288   hirda->Instance->CR3 |= USART_CR3_IREN;
00289
00290   /* Enable the Peripheral */
00291   __HAL_IRDA_ENABLE(hirda);
00292
00293   /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
00294   return (IRDA_CheckIdleState(hirda));
00295 }
00296
00297 /**
00298   * @brief DeInitialize the IRDA peripheral.
00299   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00300   *               the configuration information for the specified IRDA module.
00301   * @retval HAL status
00302   */
00303 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
00304 {
00305   /* Check the IRDA handle allocation */
00306   if(hirda == NULL)
00307   {
00308     return HAL_ERROR;
00309   }
00310
00311   /* Check the USART/UART associated to the IRDA handle */
00312   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00313
00314   hirda->gState = HAL_IRDA_STATE_BUSY;
00315
00316   /* DeInit the low level hardware */
00317   HAL_IRDA_MspDeInit(hirda);
00318   /* Disable the Peripheral */
00319   __HAL_IRDA_DISABLE(hirda);
00320
00321   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00322   hirda->gState    = HAL_IRDA_STATE_RESET;
00323   hirda->RxState   = HAL_IRDA_STATE_RESET;
00324
00325   /* Process Unlock */
00326   __HAL_UNLOCK(hirda);
00327
00328   return HAL_OK;
00329 }
00330
00331 /**
00332   * @brief Initialize the IRDA MSP.
00333   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00334   *               the configuration information for the specified IRDA module.
00335   * @retval None
00336   */
00337 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
00338 {
00339   /* Prevent unused argument(s) compilation warning */
00340   UNUSED(hirda);
00341
00342   /* NOTE: This function should not be modified, when the callback is needed,
00343            the HAL_IRDA_MspInit can be implemented in the user file
00344    */
00345 }
00346
00347 /**
00348   * @brief DeInitialize the IRDA MSP.
00349   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00350   *               the configuration information for the specified IRDA module.
00351   * @retval None
00352   */
00353 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
00354 {
00355   /* Prevent unused argument(s) compilation warning */
00356   UNUSED(hirda);
00357
00358   /* NOTE: This function should not be modified, when the callback is needed,
00359            the HAL_IRDA_MspDeInit can be implemented in the user file
00360    */
00361 }
00362
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
00368   *  @brief   IRDA Transmit and Receive functions
00369   *
00370 @verbatim
00371   ==============================================================================
00372                          ##### IO operation functions #####
00373   ==============================================================================
00374   [..]
00375     This subsection provides a set of functions allowing to manage the IRDA data transfers.
00376
00377   [..]
00378     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
00379     on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
00380     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
00381     While receiving data, transmission should be avoided as the data to be transmitted
00382     could be corrupted.
00383
00384     (#) There are two modes of transfer:
00385         (++) Blocking mode: the communication is performed in polling mode.
00386              The HAL status of all data processing is returned by the same function
00387              after finishing transfer.
00388         (++) No-Blocking mode: the communication is performed using Interrupts
00389              or DMA, these API's return the HAL status.
00390              The end of the data processing will be indicated through the
00391              dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
00392              using DMA mode.
00393              The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
00394              will be executed respectively at the end of the Transmit or Receive process
00395              The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
00396
00397     (#) Blocking mode APIs are :
00398         (++) HAL_IRDA_Transmit()
00399         (++) HAL_IRDA_Receive()
00400
00401     (#) Non Blocking mode APIs with Interrupt are :
00402         (++) HAL_IRDA_Transmit_IT()
00403         (++) HAL_IRDA_Receive_IT()
00404         (++) HAL_IRDA_IRQHandler()
00405
00406     (#) Non Blocking mode functions with DMA are :
00407         (++) HAL_IRDA_Transmit_DMA()
00408         (++) HAL_IRDA_Receive_DMA()
00409         (++) HAL_IRDA_DMAPause()
00410         (++) HAL_IRDA_DMAResume()
00411         (++) HAL_IRDA_DMAStop()
00412
00413     (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
00414         (++) HAL_IRDA_TxHalfCpltCallback()
00415         (++) HAL_IRDA_TxCpltCallback()
00416         (++) HAL_IRDA_RxHalfCpltCallback()
00417         (++) HAL_IRDA_RxCpltCallback()
00418         (++) HAL_IRDA_ErrorCallback()
00419
00420 @endverbatim
00421   * @{
00422   */
00423
00424 /**
00425   * @brief Send an amount of data in blocking mode.
00426   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00427   *               the configuration information for the specified IRDA module.
00428   * @param pData: Pointer to data buffer.
00429   * @param Size: Amount of data to be sent.
00430   * @param  Timeout: Specify timeout value.
00431   * @retval HAL status
00432   */
00433 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00434 {
00435   uint16_t* tmp;
00436   uint32_t tickstart = 0;
00437
00438   /* Check that a Tx process is not already ongoing */
00439   if(hirda->gState == HAL_IRDA_STATE_READY)
00440   {
00441     if((pData == NULL) || (Size == 0))
00442     {
00443       return  HAL_ERROR;
00444     }
00445
00446     /* Process Locked */
00447     __HAL_LOCK(hirda);
00448
00449     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00450
00451     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00452
00453     /* Init tickstart for timeout managment*/
00454     tickstart = HAL_GetTick();
00455
00456     hirda->TxXferSize = Size;
00457     hirda->TxXferCount = Size;
00458     while(hirda->TxXferCount > 0)
00459     {
00460       hirda->TxXferCount--;
00461
00462       if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00463       {
00464         return HAL_TIMEOUT;
00465       }
00466       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00467       {
00468         tmp = (uint16_t*) pData;
00469         hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
00470         pData +=2;
00471       }
00472       else
00473       {
00474         hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
00475       }
00476     }
00477
00478     if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00479     {
00480       return HAL_TIMEOUT;
00481     }
00482
00483     /* At end of Tx process, restore hirda->gState to Ready */
00484     hirda->gState = HAL_IRDA_STATE_READY;
00485
00486     /* Process Unlocked */
00487     __HAL_UNLOCK(hirda);
00488
00489     return HAL_OK;
00490   }
00491   else
00492   {
00493     return HAL_BUSY;
00494   }
00495 }
00496
00497 /**
00498   * @brief Receive an amount of data in blocking mode.
00499   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00500   *                the configuration information for the specified IRDA module.
00501   * @param pData: Pointer to data buffer.
00502   * @param Size: Amount of data to be received.
00503   * @param  Timeout: Specify timeout value.
00504   * @retval HAL status
00505   */
00506 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00507 {
00508   uint16_t* tmp;
00509   uint16_t uhMask;
00510   uint32_t tickstart = 0;
00511
00512   /* Check that a Rx process is not already ongoing */
00513   if(hirda->RxState == HAL_IRDA_STATE_READY)
00514   {
00515     if((pData == NULL) || (Size == 0))
00516     {
00517       return  HAL_ERROR;
00518     }
00519
00520     /* Process Locked */
00521     __HAL_LOCK(hirda);
00522
00523     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00524
00525     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00526
00527     /* Init tickstart for timeout managment*/
00528     tickstart = HAL_GetTick();
00529
00530     hirda->RxXferSize = Size;
00531     hirda->RxXferCount = Size;
00532
00533     /* Computation of the mask to apply to the RDR register
00534        of the UART associated to the IRDA */
00535     IRDA_MASK_COMPUTATION(hirda);
00536     uhMask = hirda->Mask;
00537
00538     /* Check data remaining to be received */
00539     while(hirda->RxXferCount > 0)
00540     {
00541       hirda->RxXferCount--;
00542
00543       if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00544       {
00545         return HAL_TIMEOUT;
00546       }
00547       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00548       {
00549         tmp = (uint16_t*) pData ;
00550         *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
00551         pData +=2;
00552       }
00553       else
00554       {
00555         *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
00556       }
00557     }
00558
00559     /* At end of Rx process, restore hirda->RxState to Ready */
00560     hirda->RxState = HAL_IRDA_STATE_READY;
00561
00562     /* Process Unlocked */
00563     __HAL_UNLOCK(hirda);
00564
00565     return HAL_OK;
00566   }
00567   else
00568   {
00569     return HAL_BUSY;
00570   }
00571 }
00572
00573 /**
00574   * @brief Send an amount of data in interrupt mode.
00575   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00576   *                the configuration information for the specified IRDA module.
00577   * @param pData: Pointer to data buffer.
00578   * @param Size: Amount of data to be sent.
00579   * @retval HAL status
00580   */
00581 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00582 {
00583   /* Check that a Tx process is not already ongoing */
00584   if(hirda->gState == HAL_IRDA_STATE_READY)
00585   {
00586     if((pData == NULL) || (Size == 0))
00587     {
00588       return HAL_ERROR;
00589     }
00590
00591     /* Process Locked */
00592     __HAL_LOCK(hirda);
00593
00594     hirda->pTxBuffPtr = pData;
00595     hirda->TxXferSize = Size;
00596     hirda->TxXferCount = Size;
00597
00598     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00599
00600     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00601
00602     /* Process Unlocked */
00603     __HAL_UNLOCK(hirda);
00604
00605     /* Enable the IRDA Transmit Data Register Empty Interrupt */
00606     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
00607
00608     return HAL_OK;
00609   }
00610   else
00611   {
00612     return HAL_BUSY;
00613   }
00614 }
00615
00616 /**
00617   * @brief Receive an amount of data in interrupt mode.
00618   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00619   *                the configuration information for the specified IRDA module.
00620   * @param pData: Pointer to data buffer.
00621   * @param Size: Amount of data to be received.
00622   * @retval HAL status
00623   */
00624 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00625 {
00626   /* Check that a Rx process is not already ongoing */
00627   if(hirda->RxState == HAL_IRDA_STATE_READY)
00628   {
00629     if((pData == NULL) || (Size == 0))
00630     {
00631       return HAL_ERROR;
00632     }
00633
00634     /* Process Locked */
00635   __HAL_LOCK(hirda);
00636
00637     hirda->pRxBuffPtr = pData;
00638     hirda->RxXferSize = Size;
00639     hirda->RxXferCount = Size;
00640
00641     /* Computation of the mask to apply to the RDR register
00642        of the UART associated to the IRDA */
00643     IRDA_MASK_COMPUTATION(hirda);
00644
00645     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00646
00647     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00648
00649     /* Process Unlocked */
00650     __HAL_UNLOCK(hirda);
00651
00652     /* Enable the IRDA Data Register not empty Interrupt */
00653     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
00654
00655     /* Enable the IRDA Parity Error Interrupt */
00656     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
00657
00658     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00659     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
00660
00661     return HAL_OK;
00662   }
00663   else
00664   {
00665     return HAL_BUSY;
00666   }
00667 }
00668
00669 /**
00670   * @brief Send an amount of data in DMA mode.
00671   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00672   *               the configuration information for the specified IRDA module.
00673   * @param pData: pointer to data buffer.
00674   * @param Size: amount of data to be sent.
00675   * @retval HAL status
00676   */
00677 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00678 {
00679   uint32_t *tmp;
00680
00681   /* Check that a Tx process is not already ongoing */
00682   if(hirda->gState == HAL_IRDA_STATE_READY)
00683   {
00684     if((pData == NULL) || (Size == 0))
00685     {
00686       return HAL_ERROR;
00687     }
00688
00689     /* Process Locked */
00690     __HAL_LOCK(hirda);
00691
00692     hirda->pTxBuffPtr = pData;
00693     hirda->TxXferSize = Size;
00694     hirda->TxXferCount = Size;
00695
00696     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00697
00698     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00699
00700     /* Set the IRDA DMA transfer complete callback */
00701     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
00702
00703     /* Set the IRDA DMA half transfer complete callback */
00704     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
00705
00706     /* Set the DMA error callback */
00707     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
00708
00709     /* Enable the IRDA transmit DMA channel */
00710     tmp = (uint32_t*)&pData;
00711     HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
00712
00713     /* Clear the TC flag in the ICR register */
00714     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
00715
00716     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00717        in the USART CR3 register */
00718     hirda->Instance->CR3 |= USART_CR3_DMAT;
00719
00720     /* Process Unlocked */
00721     __HAL_UNLOCK(hirda);
00722
00723     return HAL_OK;
00724   }
00725   else
00726   {
00727     return HAL_BUSY;
00728   }
00729 }
00730
00731 /**
00732   * @brief Receive an amount of data in DMA mode.
00733   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00734   *               the configuration information for the specified IRDA module.
00735   * @param pData: Pointer to data buffer.
00736   * @param Size: Amount of data to be received.
00737   * @note   When the IRDA parity is enabled (PCE = 1) the received data contains
00738   *         the parity bit (MSB position).
00739   * @retval HAL status
00740   */
00741 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00742 {
00743   uint32_t *tmp;
00744
00745   /* Check that a Rx process is not already ongoing */
00746   if(hirda->RxState == HAL_IRDA_STATE_READY)
00747   {
00748     if((pData == NULL) || (Size == 0))
00749     {
00750       return HAL_ERROR;
00751     }
00752
00753     /* Process Locked */
00754     __HAL_LOCK(hirda);
00755
00756     hirda->pRxBuffPtr = pData;
00757     hirda->RxXferSize = Size;
00758
00759     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00760
00761     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00762
00763     /* Set the IRDA DMA transfer complete callback */
00764     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
00765
00766     /* Set the IRDA DMA half transfer complete callback */
00767     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
00768
00769     /* Set the DMA error callback */
00770     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
00771
00772     /* Enable the DMA channel */
00773     tmp = (uint32_t*)&pData;
00774     HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);
00775
00776     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00777        in the USART CR3 register */
00778      hirda->Instance->CR3 |= USART_CR3_DMAR;
00779
00780      /* Process Unlocked */
00781      __HAL_UNLOCK(hirda);
00782
00783     return HAL_OK;
00784   }
00785   else
00786   {
00787     return HAL_BUSY;
00788   }
00789 }
00790
00791
00792 /**
00793   * @brief Pause the DMA Transfer.
00794   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00795   *                the configuration information for the specified IRDA module.
00796   * @retval HAL status
00797   */
00798 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
00799 {
00800   /* Process Locked */
00801   __HAL_LOCK(hirda);
00802
00803   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
00804   {
00805     /* Disable the IRDA DMA Tx request */
00806     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00807   }
00808   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
00809   {
00810     /* Disable the IRDA DMA Rx request */
00811     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00812   }
00813
00814   /* Process Unlocked */
00815   __HAL_UNLOCK(hirda);
00816
00817   return HAL_OK;
00818 }
00819
00820 /**
00821   * @brief Resume the DMA Transfer.
00822   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00823   *                the configuration information for the specified UART module.
00824   * @retval HAL status
00825   */
00826 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
00827 {
00828   /* Process Locked */
00829   __HAL_LOCK(hirda);
00830
00831   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
00832   {
00833     /* Enable the IRDA DMA Tx request */
00834     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00835   }
00836   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
00837   {
00838     /* Clear the Overrun flag before resuming the Rx transfer*/
00839     __HAL_IRDA_CLEAR_OREFLAG(hirda);
00840     /* Enable the IRDA DMA Rx request */
00841     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00842   }
00843
00844   /* Process Unlocked */
00845   __HAL_UNLOCK(hirda);
00846
00847   return HAL_OK;
00848 }
00849
00850 /**
00851   * @brief Stop the DMA Transfer.
00852   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00853   *                the configuration information for the specified UART module.
00854   * @retval HAL status
00855   */
00856 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
00857 {
00858   /* The Lock is not implemented on this API to allow the user application
00859      to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
00860      HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
00861      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
00862      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
00863      the stream and the corresponding call back is executed. */
00864
00865   /* Disable the IRDA Tx/Rx DMA requests */
00866   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00867   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00868
00869   /* Abort the IRDA DMA tx channel */
00870   if(hirda->hdmatx != NULL)
00871   {
00872     HAL_DMA_Abort(hirda->hdmatx);
00873   }
00874   /* Abort the IRDA DMA rx channel */
00875   if(hirda->hdmarx != NULL)
00876   {
00877     HAL_DMA_Abort(hirda->hdmarx);
00878   }
00879
00880   hirda->gState = HAL_IRDA_STATE_READY;
00881   hirda->RxState = HAL_IRDA_STATE_READY;
00882
00883   return HAL_OK;
00884 }
00885
00886
00887 /**
00888   * @brief Handle IRDA interrupt request.
00889   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00890   *               the configuration information for the specified IRDA module.
00891   * @retval None
00892   */
00893 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
00894 {
00895   /* IRDA parity error interrupt occurred -------------------------------------*/
00896   if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET))
00897   {
00898     __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
00899
00900     hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
00901     /* Set the IRDA Rx state ready to be able to start again the process */
00902     hirda->RxState = HAL_IRDA_STATE_READY;
00903   }
00904
00905   /* IRDA frame error interrupt occurred --------------------------------------*/
00906   if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
00907   {
00908     __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
00909
00910     hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
00911     /* Set the IRDA Rx state ready to be able to start again the process */
00912     hirda->RxState = HAL_IRDA_STATE_READY;
00913   }
00914
00915   /* IRDA noise error interrupt occurred --------------------------------------*/
00916   if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
00917   {
00918     __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
00919
00920     hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
00921     /* Set the IRDA Rx state ready to be able to start again the process */
00922     hirda->RxState = HAL_IRDA_STATE_READY;
00923   }
00924
00925   /* IRDA Over-Run interrupt occurred -----------------------------------------*/
00926   if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
00927   {
00928     __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
00929
00930     hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
00931     /* Set the IRDA Rx state ready to be able to start again the process */
00932     hirda->RxState = HAL_IRDA_STATE_READY;
00933   }
00934
00935   /* Call IRDA Error Call back function if need be --------------------------*/
00936   if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
00937   {
00938     HAL_IRDA_ErrorCallback(hirda);
00939   }
00940
00941   /* IRDA in mode Receiver ---------------------------------------------------*/
00942   if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET))
00943   {
00944     IRDA_Receive_IT(hirda);
00945   }
00946
00947
00948   /* IRDA in mode Transmitter ------------------------------------------------*/
00949  if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))
00950   {
00951     IRDA_Transmit_IT(hirda);
00952   }
00953
00954   /* IRDA in mode Transmitter (transmission end) -----------------------------*/
00955  if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))
00956   {
00957     IRDA_EndTransmit_IT(hirda);
00958   }
00959
00960 }
00961
00962 /**
00963   * @brief  Tx Transfer completed callback.
00964   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00965   *                the configuration information for the specified IRDA module.
00966   * @retval None
00967   */
00968 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
00969 {
00970   /* Prevent unused argument(s) compilation warning */
00971   UNUSED(hirda);
00972
00973   /* NOTE: This function should not be modified, when the callback is needed,
00974            the HAL_IRDA_TxCpltCallback can be implemented in the user file.
00975    */
00976 }
00977
00978 /**
00979   * @brief  Tx Half Transfer completed callback.
00980   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00981   *                the configuration information for the specified USART module.
00982   * @retval None
00983   */
00984 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
00985 {
00986   /* Prevent unused argument(s) compilation warning */
00987   UNUSED(hirda);
00988
00989   /* NOTE: This function should not be modified, when the callback is needed,
00990            the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
00991    */
00992 }
00993
00994 /**
00995   * @brief  Rx Transfer completed callback.
00996   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00997   *                the configuration information for the specified IRDA module.
00998   * @retval None
00999   */
01000 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
01001 {
01002   /* Prevent unused argument(s) compilation warning */
01003   UNUSED(hirda);
01004
01005   /* NOTE: This function should not be modified, when the callback is needed,
01006            the HAL_IRDA_RxCpltCallback can be implemented in the user file.
01007    */
01008 }
01009
01010 /**
01011   * @brief  Rx Half Transfer complete callback.
01012   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01013   *                the configuration information for the specified IRDA module.
01014   * @retval None
01015   */
01016 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
01017 {
01018   /* Prevent unused argument(s) compilation warning */
01019   UNUSED(hirda);
01020
01021   /* NOTE : This function should not be modified, when the callback is needed,
01022             the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
01023    */
01024 }
01025
01026 /**
01027   * @brief  IRDA error callback.
01028   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01029   *                the configuration information for the specified IRDA module.
01030   * @retval None
01031   */
01032  __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
01033 {
01034   /* Prevent unused argument(s) compilation warning */
01035   UNUSED(hirda);
01036
01037   /* NOTE: This function should not be modified, when the callback is needed,
01038            the HAL_IRDA_ErrorCallback can be implemented in the user file.
01039    */
01040 }
01041
01042 /**
01043   * @}
01044   */
01045
01046 /** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
01047   *  @brief   IRDA State and Errors functions
01048   *
01049 @verbatim
01050   ==============================================================================
01051                   ##### Peripheral State and Errors functions #####
01052   ==============================================================================
01053   [..]
01054     This subsection provides a set of functions allowing to return the State of IrDA
01055     communication process and also return Peripheral Errors occurred during communication process
01056      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
01057          of the IRDA peripheral handle.
01058      (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
01059          communication.
01060
01061 @endverbatim
01062   * @{
01063   */
01064
01065 /**
01066   * @brief  Return the IRDA handle state.
01067   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01068   *                the configuration information for the specified IRDA module.
01069   * @retval HAL state
01070   */
01071 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
01072 {
01073   /* Return IRDA handle state */
01074   uint32_t temp1= 0x00, temp2 = 0x00;
01075   temp1 = hirda->gState;
01076   temp2 = hirda->RxState;
01077
01078   return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
01079 }
01080
01081 /**
01082   * @brief Return the IRDA handle error code.
01083   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01084   *               the configuration information for the specified IRDA module.
01085   * @retval IRDA Error Code
01086   */
01087 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
01088 {
01089   return hirda->ErrorCode;
01090 }
01091
01092 /**
01093   * @}
01094   */
01095
01096 /**
01097   * @}
01098   */
01099
01100 /** @defgroup IRDA_Private_Functions IRDA Private Functions
01101   * @{
01102   */
01103
01104 /**
01105   * @brief  DMA IRDA transmit process complete callback.
01106   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01107   *               the configuration information for the specified DMA module.
01108   * @retval None
01109   */
01110 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01111 {
01112   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01113
01114   /* DMA Normal mode */
01115   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
01116   {
01117     hirda->TxXferCount = 0;
01118
01119     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01120        in the IRDA CR3 register */
01121     hirda->Instance->CR3 &= ~(USART_CR3_DMAT);
01122
01123     /* Enable the IRDA Transmit Complete Interrupt */
01124     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
01125   }
01126   /* DMA Circular mode */
01127   else
01128   {
01129     HAL_IRDA_TxCpltCallback(hirda);
01130   }
01131 }
01132
01133 /**
01134   * @brief DMA IRDA receive process half complete callback.
01135   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01136   *               the configuration information for the specified DMA module.
01137   * @retval None
01138   */
01139 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
01140 {
01141   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01142
01143   HAL_IRDA_TxHalfCpltCallback(hirda);
01144 }
01145
01146 /**
01147   * @brief  DMA IRDA receive process complete callback.
01148   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01149   *               the configuration information for the specified DMA module.
01150   * @retval None
01151   */
01152 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01153 {
01154   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01155
01156   /* DMA Normal mode */
01157   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
01158   {
01159     hirda->RxXferCount = 0;
01160
01161     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
01162        in the IRDA CR3 register */
01163     hirda->Instance->CR3 &= ~(USART_CR3_DMAR);
01164
01165     /* At end of Rx process, restore hirda->RxState to Ready */
01166     hirda->RxState = HAL_IRDA_STATE_READY;
01167   }
01168
01169   HAL_IRDA_RxCpltCallback(hirda);
01170 }
01171
01172 /**
01173   * @brief DMA IRDA receive process half complete callback.
01174   * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
01175   *              the configuration information for the specified DMA module.
01176   * @retval None
01177   */
01178 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
01179 {
01180   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01181
01182   HAL_IRDA_RxHalfCpltCallback(hirda);
01183 }
01184
01185 /**
01186   * @brief DMA IRDA communication error callback.
01187   * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
01188   *              the configuration information for the specified DMA module.
01189   * @retval None
01190   */
01191 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
01192 {
01193   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01194
01195   hirda->RxXferCount = 0;
01196   hirda->TxXferCount = 0;
01197   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
01198   hirda->gState     = HAL_IRDA_STATE_READY;
01199   hirda->RxState    = HAL_IRDA_STATE_READY;
01200
01201   HAL_IRDA_ErrorCallback(hirda);
01202 }
01203
01204 /**
01205   * @brief  Handle IRDA Communication Timeout.
01206   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01207   *               the configuration information for the specified IRDA module.
01208   * @param  Flag Specifies the IRDA flag to check.
01209   * @param  Status the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
01210   * @param  Tickstart Tick start value
01211   * @param  Timeout Timeout duration
01212   * @retval HAL status
01213   */
01214 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01215 {
01216   /* Wait until flag is set */
01217   while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
01218   {
01219     /* Check for the Timeout */
01220     if(Timeout != HAL_MAX_DELAY)
01221     {
01222       if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
01223       {
01224         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01225         CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
01226         CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01227
01228         hirda->gState= HAL_IRDA_STATE_READY;
01229         hirda->RxState= HAL_IRDA_STATE_READY;
01230
01231         /* Process Unlocked */
01232         __HAL_UNLOCK(hirda);
01233
01234         return HAL_TIMEOUT;
01235       }
01236     }
01237   }
01238   return HAL_OK;
01239 }
01240
01241 /**
01242   * @brief  Send an amount of data in non-blocking mode.
01243   * @note   Function is called under interruption only, once
01244   *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
01245   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01246   *                the configuration information for the specified IRDA module.
01247   * @retval HAL status
01248   */
01249 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
01250 {
01251   uint16_t* tmp;
01252
01253   /* Check that a Tx process is ongoing */
01254   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01255   {
01256     if(hirda->TxXferCount == 0)
01257     {
01258       /* Disable the IRDA Transmit Data Register Empty Interrupt */
01259       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
01260
01261       /* Enable the IRDA Transmit Complete Interrupt */
01262       __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
01263
01264       return HAL_OK;
01265     }
01266     else
01267     {
01268       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
01269       {
01270         tmp = (uint16_t*) hirda->pTxBuffPtr;
01271         hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
01272         hirda->pTxBuffPtr += 2;
01273       }
01274       else
01275       {
01276         hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
01277       }
01278       hirda->TxXferCount--;
01279
01280       return HAL_OK;
01281     }
01282   }
01283   else
01284   {
01285     return HAL_BUSY;
01286   }
01287 }
01288
01289 /**
01290   * @brief  Wrap up transmission in non-blocking mode.
01291   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01292   *                the configuration information for the specified IRDA module.
01293   * @retval HAL status
01294   */
01295 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
01296 {
01297   /* Disable the IRDA Transmit Complete Interrupt */
01298   __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
01299
01300   /* Tx process is ended, restore hirda->gState to Ready */
01301   hirda->gState = HAL_IRDA_STATE_READY;
01302
01303   HAL_IRDA_TxCpltCallback(hirda);
01304
01305   return HAL_OK;
01306 }
01307
01308
01309 /**
01310   * @brief  Receive an amount of data in non-blocking mode.
01311   *         Function is called under interruption only, once
01312   *         interruptions have been enabled by HAL_IRDA_Receive_IT().
01313   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01314   *                the configuration information for the specified IRDA module.
01315   * @retval HAL status
01316   */
01317 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
01318 {
01319   uint16_t* tmp;
01320   uint16_t uhMask = hirda->Mask;
01321
01322   /* Check that a Rx process is ongoing */
01323   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01324   {
01325
01326     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
01327     {
01328       tmp = (uint16_t*) hirda->pRxBuffPtr ;
01329       *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
01330       hirda->pRxBuffPtr  +=2;
01331     }
01332     else
01333     {
01334       *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
01335     }
01336
01337     if(--hirda->RxXferCount == 0)
01338     {
01339       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
01340
01341       /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
01342       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
01343
01344       /* Disable the IRDA Parity Error Interrupt */
01345       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
01346
01347       /* Rx process is completed, restore hirda->RxState to Ready */
01348       hirda->RxState = HAL_IRDA_STATE_READY;
01349
01350       HAL_IRDA_RxCpltCallback(hirda);
01351
01352       return HAL_OK;
01353     }
01354
01355     return HAL_OK;
01356   }
01357   else
01358   {
01359     /* Clear RXNE interrupt flag */
01360     __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
01361
01362     return HAL_BUSY;
01363   }
01364 }
01365
01366 /**
01367   * @brief Configure the IRDA peripheral.
01368   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01369   *               the configuration information for the specified IRDA module.
01370   * @retval None
01371   */
01372 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
01373 {
01374   uint32_t tmpreg                     = 0x00000000;
01375   IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
01376   HAL_StatusTypeDef ret               = HAL_OK;
01377
01378   /* Check the communication parameters */
01379   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
01380   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
01381   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
01382   assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
01383   assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
01384   assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
01385
01386   /*-------------------------- USART CR1 Configuration -----------------------*/
01387   /* Configure the IRDA Word Length, Parity and transfer Mode:
01388      Set the M bits according to hirda->Init.WordLength value
01389      Set PCE and PS bits according to hirda->Init.Parity value
01390      Set TE and RE bits according to hirda->Init.Mode value */
01391   tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
01392
01393   MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
01394
01395   /*-------------------------- USART CR3 Configuration -----------------------*/
01396   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
01397
01398   /*-------------------------- USART GTPR Configuration ----------------------*/
01399   MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
01400
01401   /*-------------------------- USART BRR Configuration -----------------------*/
01402   IRDA_GETCLOCKSOURCE(hirda, clocksource);
01403   switch (clocksource)
01404   {
01405     case IRDA_CLOCKSOURCE_PCLK1:
01406       hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01407       break;
01408     case IRDA_CLOCKSOURCE_PCLK2:
01409       hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01410       break;
01411     case IRDA_CLOCKSOURCE_HSI:
01412       hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01413       break;
01414     case IRDA_CLOCKSOURCE_SYSCLK:
01415       hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01416       break;
01417     case IRDA_CLOCKSOURCE_LSE:
01418       hirda->Instance->BRR = (uint16_t)((LSE_VALUE  + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
01419       break;
01420     case IRDA_CLOCKSOURCE_UNDEFINED:
01421     default:
01422       ret = HAL_ERROR;
01423       break;
01424   }
01425
01426   return ret;
01427 }
01428
01429 /**
01430   * @brief Check the IRDA Idle State.
01431   * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01432   *               the configuration information for the specified IRDA module.
01433   * @retval HAL status
01434   */
01435 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
01436 {
01437   uint32_t tickstart = 0;
01438
01439   /* Initialize the IRDA ErrorCode */
01440   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01441
01442   /* Init tickstart for timeout managment*/
01443   tickstart = HAL_GetTick();
01444
01445   /* Check if the Transmitter is enabled */
01446   if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01447   {
01448     /* Wait until TEACK flag is set */
01449     if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
01450     {
01451       /* Timeout occurred */
01452       return HAL_TIMEOUT;
01453     }
01454   }
01455   /* Check if the Receiver is enabled */
01456   if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01457   {
01458     if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
01459     {
01460       /* Timeout occurred */
01461       return HAL_TIMEOUT;
01462     }
01463   }
01464
01465   /* Initialize the IRDA state*/
01466   hirda->gState= HAL_IRDA_STATE_READY;
01467   hirda->RxState= HAL_IRDA_STATE_READY;
01468
01469   /* Process Unlocked */
01470   __HAL_UNLOCK(hirda);
01471
01472   return HAL_OK;
01473 }
01474
01475 /**
01476   * @}
01477   */
01478
01479 #endif /* HAL_IRDA_MODULE_ENABLED */
01480 /**
01481   * @}
01482   */
01483
01484 /**
01485   * @}
01486   */
01487
01488 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_irda.h Source File

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stm32l4xx_hal_irda.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_irda.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of IRDA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_IRDA_H
00040 #define __STM32L4xx_HAL_IRDA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IRDA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup IRDA_Exported_Types IRDA Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief IRDA Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
00068                                            The baud rate register is computed using the following formula:
00069                                               Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
00070
00071   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00072                                            This parameter can be a value of @ref IRDA_Word_Length */
00073
00074   uint32_t Parity;                    /*!< Specifies the parity mode.
00075                                            This parameter can be a value of @ref IRDA_Parity
00076                                            @note When parity is enabled, the computed parity is inserted
00077                                                  at the MSB position of the transmitted data (9th bit when
00078                                                  the word length is set to 9 data bits; 8th bit when the
00079                                                  word length is set to 8 data bits). */
00080
00081   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00082                                            This parameter can be a value of @ref IRDA_Transfer_Mode */
00083
00084   uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
00085                                            to achieve low-power frequency.
00086                                            @note Prescaler value 0 is forbidden */
00087
00088   uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
00089                                            This parameter can be a value of @ref IRDA_Low_Power */
00090 }IRDA_InitTypeDef;
00091
00092 /**
00093   * @brief HAL IRDA State structures definition
00094   * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
00095   *        - gState contains IRDA state information related to global Handle management
00096   *          and also information related to Tx operations.
00097   *          gState value coding follow below described bitmap :
00098   *          b7-b6  Error information
00099   *             00 : No Error
00100   *             01 : (Not Used)
00101   *             10 : Timeout
00102   *             11 : Error
00103   *          b5     IP initilisation status
00104   *             0  : Reset (IP not initialized)
00105   *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
00106   *          b4-b3  (not used)
00107   *             xx : Should be set to 00
00108   *          b2     Intrinsic process state
00109   *             0  : Ready
00110   *             1  : Busy (IP busy with some configuration or internal operations)
00111   *          b1     (not used)
00112   *             x  : Should be set to 0
00113   *          b0     Tx state
00114   *             0  : Ready (no Tx operation ongoing)
00115   *             1  : Busy (Tx operation ongoing)
00116   *        - RxState contains information related to Rx operations.
00117   *          RxState value coding follow below described bitmap :
00118   *          b7-b6  (not used)
00119   *             xx : Should be set to 00
00120   *          b5     IP initilisation status
00121   *             0  : Reset (IP not initialized)
00122   *             1  : Init done (IP not initialized)
00123   *          b4-b2  (not used)
00124   *            xxx : Should be set to 000
00125   *          b1     Rx state
00126   *             0  : Ready (no Rx operation ongoing)
00127   *             1  : Busy (Rx operation ongoing)
00128   *          b0     (not used)
00129   *             x  : Should be set to 0.
00130   */
00131 typedef enum
00132 {
00133   HAL_IRDA_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
00134                                                    Value is allowed for gState and RxState */
00135   HAL_IRDA_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
00136                                                    Value is allowed for gState and RxState */
00137   HAL_IRDA_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
00138                                                    Value is allowed for gState only */
00139   HAL_IRDA_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
00140                                                    Value is allowed for gState only */
00141   HAL_IRDA_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
00142                                                    Value is allowed for RxState only */
00143   HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
00144                                                    Not to be used for neither gState nor RxState.
00145                                                    Value is result of combination (Or) between gState and RxState values */
00146   HAL_IRDA_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
00147                                                    Value is allowed for gState only */
00148   HAL_IRDA_STATE_ERROR             = 0xE0U    /*!< Error
00149                                                    Value is allowed for gState only */
00150 }HAL_IRDA_StateTypeDef;
00151
00152 /**
00153   * @brief  HAL IRDA Error Code structure definition
00154   */
00155 typedef enum
00156 {
00157   HAL_IRDA_ERROR_NONE      = 0x00,    /*!< No error            */
00158   HAL_IRDA_ERROR_PE        = 0x01,    /*!< Parity error        */
00159   HAL_IRDA_ERROR_NE        = 0x02,    /*!< Noise error         */
00160   HAL_IRDA_ERROR_FE        = 0x04,    /*!< frame error         */
00161   HAL_IRDA_ERROR_ORE       = 0x08,    /*!< Overrun error       */
00162   HAL_IRDA_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
00163 }HAL_IRDA_ErrorTypeDef;
00164
00165 /**
00166   * @brief IRDA clock sources definition
00167   */
00168 typedef enum
00169 {
00170   IRDA_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source     */
00171   IRDA_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source     */
00172   IRDA_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source       */
00173   IRDA_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source    */
00174   IRDA_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
00175   IRDA_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
00176 }IRDA_ClockSourceTypeDef;
00177
00178 /**
00179   * @brief  IRDA handle Structure definition
00180   */
00181 typedef struct
00182 {
00183   USART_TypeDef            *Instance;        /*!< USART registers base address       */
00184
00185   IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
00186
00187   uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
00188
00189   uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
00190
00191   uint16_t                 TxXferCount;      /* !<IRDA Tx Transfer Counter           */
00192
00193   uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
00194
00195   uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
00196
00197   uint16_t                 RxXferCount;      /*!< IRDA Rx Transfer Counter           */
00198
00199   uint16_t                 Mask;             /*!< USART RX RDR register mask         */
00200
00201   DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
00202
00203   DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
00204
00205   HAL_LockTypeDef          Lock;             /*!< Locking object                     */
00206
00207   __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
00208                                                   and also related to Tx operations.
00209                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00210
00211   __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
00212                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00213
00214   uint32_t                 ErrorCode;        /*!< IRDA Error code                    */
00215
00216 }IRDA_HandleTypeDef;
00217
00218 /**
00219   * @brief  IRDA Configuration enumeration values definition
00220   */
00221 typedef enum
00222 {
00223   IRDA_BAUDRATE        = 0x00,     /*!< IRDA Baud rate          */
00224   IRDA_PARITY          = 0x01,     /*!< IRDA frame parity       */
00225   IRDA_WORDLENGTH      = 0x02,     /*!< IRDA frame length       */
00226   IRDA_MODE            = 0x03,     /*!< IRDA communication mode */
00227   IRDA_PRESCALER       = 0x04,     /*!< IRDA prescaling         */
00228   IRDA_POWERMODE       = 0x05      /*!< IRDA power mode         */
00229 }IRDA_ControlTypeDef;
00230
00231 /**
00232   * @}
00233   */
00234
00235 /* Exported constants --------------------------------------------------------*/
00236 /** @defgroup IRDA_Exported_Constants IRDA Exported Constants
00237   * @{
00238   */
00239
00240 /** @defgroup IRDA_Word_Length IRDA Word Length
00241   * @{
00242   */
00243 #define IRDA_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long frame */
00244 #define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long frame */
00245 #define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long frame */
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup IRDA_Parity IRDA Parity
00251   * @{
00252   */
00253 #define IRDA_PARITY_NONE                    ((uint32_t)0x00000000)                      /*!< No parity   */
00254 #define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
00255 #define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
00261   * @{
00262   */
00263 #define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
00264 #define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
00265 #define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup IRDA_Low_Power IRDA Low Power
00271   * @{
00272   */
00273 #define IRDA_POWERMODE_NORMAL               ((uint32_t)0x00000000)       /*!< IRDA normal power mode */
00274 #define IRDA_POWERMODE_LOWPOWER             ((uint32_t)USART_CR3_IRLP)   /*!< IRDA low power mode    */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup IRDA_State IRDA State
00280   * @{
00281   */
00282 #define IRDA_STATE_DISABLE                  ((uint32_t)0x00000000)     /*!< IRDA disabled  */
00283 #define IRDA_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)   /*!< IRDA enabled   */
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup IRDA_Mode  IRDA Mode
00289   * @{
00290   */
00291 #define IRDA_MODE_DISABLE                   ((uint32_t)0x00000000)      /*!< Associated UART disabled in IRDA mode */
00292 #define IRDA_MODE_ENABLE                    ((uint32_t)USART_CR3_IREN)  /*!< Associated UART enabled in IRDA mode  */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup IRDA_One_Bit  IRDA One Bit Sampling
00298   * @{
00299   */
00300 #define IRDA_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000)       /*!< One-bit sampling disabled */
00301 #define IRDA_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled  */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup IRDA_DMA_Tx IRDA DMA Tx
00307   * @{
00308   */
00309 #define IRDA_DMA_TX_DISABLE                 ((uint32_t)0x00000000)       /*!< IRDA DMA TX disabled */
00310 #define IRDA_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)   /*!< IRDA DMA TX enabled  */
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup IRDA_DMA_Rx  IRDA DMA Rx
00316   * @{
00317   */
00318 #define IRDA_DMA_RX_DISABLE                 ((uint32_t)0x00000000)       /*!< IRDA DMA RX disabled */
00319 #define IRDA_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)   /*!< IRDA DMA RX enabled  */
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup IRDA_Request_Parameters IRDA Request Parameters
00325   * @{
00326   */
00327 #define IRDA_AUTOBAUD_REQUEST            ((uint16_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
00328 #define IRDA_RXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
00329 #define IRDA_TXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup IRDA_Flags IRDA Flags
00335   *        Elements values convention: 0xXXXX
00336   *           - 0xXXXX  : Flag mask in the ISR register
00337   * @{
00338   */
00339 #define IRDA_FLAG_REACK                     ((uint32_t)0x00400000)    /*!< IRDA Receive enable acknowledge flag  */
00340 #define IRDA_FLAG_TEACK                     ((uint32_t)0x00200000)    /*!< IRDA Transmit enable acknowledge flag */
00341 #define IRDA_FLAG_BUSY                      ((uint32_t)0x00010000)    /*!< IRDA Busy flag                        */
00342 #define IRDA_FLAG_ABRF                      ((uint32_t)0x00008000)    /*!< IRDA Auto baud rate flag              */
00343 #define IRDA_FLAG_ABRE                      ((uint32_t)0x00004000)    /*!< IRDA Auto baud rate error             */
00344 #define IRDA_FLAG_TXE                       ((uint32_t)0x00000080)    /*!< IRDA Transmit data register empty     */
00345 #define IRDA_FLAG_TC                        ((uint32_t)0x00000040)    /*!< IRDA Transmission complete            */
00346 #define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020)    /*!< IRDA Read data register not empty     */
00347 #define IRDA_FLAG_ORE                       ((uint32_t)0x00000008)    /*!< IRDA Overrun error                    */
00348 #define IRDA_FLAG_NE                        ((uint32_t)0x00000004)    /*!< IRDA Noise error                      */
00349 #define IRDA_FLAG_FE                        ((uint32_t)0x00000002)    /*!< IRDA Noise error                      */
00350 #define IRDA_FLAG_PE                        ((uint32_t)0x00000001)    /*!< IRDA Parity error                     */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
00356   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00357   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00358   *           - XX  : Interrupt source register (2bits)
00359   *                 - 01: CR1 register
00360   *                 - 10: CR2 register
00361   *                 - 11: CR3 register
00362   *           - ZZZZ  : Flag position in the ISR register(4bits)
00363   * @{
00364   */
00365 #define IRDA_IT_PE                          ((uint16_t)0x0028)     /*!< IRDA Parity error interruption                 */
00366 #define IRDA_IT_TXE                         ((uint16_t)0x0727)     /*!< IRDA Transmit data register empty interruption */
00367 #define IRDA_IT_TC                          ((uint16_t)0x0626)     /*!< IRDA Transmission complete interruption        */
00368 #define IRDA_IT_RXNE                        ((uint16_t)0x0525)     /*!< IRDA Read data register not empty interruption */
00369 #define IRDA_IT_IDLE                        ((uint16_t)0x0424)     /*!< IRDA Idle interruption                         */
00370
00371 /*       Elements values convention: 000000000XXYYYYYb
00372              - YYYYY  : Interrupt source position in the XX register (5bits)
00373              - XX  : Interrupt source register (2bits)
00374                    - 01: CR1 register
00375                    - 10: CR2 register
00376                    - 11: CR3 register */
00377 #define IRDA_IT_ERR                         ((uint16_t)0x0060)       /*!< IRDA Error interruption        */
00378
00379 /*       Elements values convention: 0000ZZZZ00000000b
00380              - ZZZZ  : Flag position in the ISR register(4bits) */
00381 #define IRDA_IT_ORE                         ((uint16_t)0x0300)      /*!< IRDA Overrun error interruption */
00382 #define IRDA_IT_NE                          ((uint16_t)0x0200)      /*!< IRDA Noise error interruption   */
00383 #define IRDA_IT_FE                          ((uint16_t)0x0100)      /*!< IRDA Frame error interruption   */
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup IRDA_IT_CLEAR_Flags   IRDA Interruption Clear Flags
00389   * @{
00390   */
00391 #define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
00392 #define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
00393 #define IRDA_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
00394 #define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
00395 #define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
00396 #define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup IRDA_Interruption_Mask    IRDA interruptions flags mask
00402   * @{
00403   */
00404 #define IRDA_IT_MASK  ((uint16_t)0x001F)                             /*!< IRDA Interruptions flags mask */
00405 /**
00406   * @}
00407   */
00408
00409 /**
00410  * @}
00411  */
00412
00413
00414 /* Exported macros -----------------------------------------------------------*/
00415 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
00416   * @{
00417   */
00418
00419 /** @brief  Reset IRDA handle state.
00420   * @param  __HANDLE__: IRDA handle.
00421   * @retval None
00422   */
00423 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00424                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00425                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00426                                                      } while(0)
00427
00428 /** @brief  Flush the IRDA DR register.
00429   * @param  __HANDLE__: specifies the IRDA Handle.
00430   * @retval None
00431   */
00432 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
00433     do{                                                                    \
00434          SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
00435          SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
00436       } while(0)
00437
00438 /** @brief  Clear the specified IRDA pending flag.
00439   * @param  __HANDLE__: specifies the IRDA Handle.
00440   * @param  __FLAG__: specifies the flag to check.
00441   *          This parameter can be any combination of the following values:
00442   *            @arg @ref IRDA_CLEAR_PEF
00443   *            @arg @ref IRDA_CLEAR_FEF
00444   *            @arg @ref IRDA_CLEAR_NEF
00445   *            @arg @ref IRDA_CLEAR_OREF
00446   *            @arg @ref IRDA_CLEAR_TCF
00447   *            @arg @ref IRDA_CLEAR_IDLEF
00448   * @retval None
00449   */
00450 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00451
00452 /** @brief  Clear the IRDA PE pending flag.
00453   * @param  __HANDLE__: specifies the IRDA Handle.
00454   * @retval None
00455   */
00456 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
00457
00458
00459 /** @brief  Clear the IRDA FE pending flag.
00460   * @param  __HANDLE__: specifies the IRDA Handle.
00461   * @retval None
00462   */
00463 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
00464
00465 /** @brief  Clear the IRDA NE pending flag.
00466   * @param  __HANDLE__: specifies the IRDA Handle.
00467   * @retval None
00468   */
00469 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
00470
00471 /** @brief  Clear the IRDA ORE pending flag.
00472   * @param  __HANDLE__: specifies the IRDA Handle.
00473   * @retval None
00474   */
00475 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
00476
00477 /** @brief  Clear the IRDA IDLE pending flag.
00478   * @param  __HANDLE__: specifies the IRDA Handle.
00479   * @retval None
00480   */
00481 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
00482
00483 /** @brief  Check whether the specified IRDA flag is set or not.
00484   * @param  __HANDLE__: specifies the IRDA Handle.
00485   * @param  __FLAG__: specifies the flag to check.
00486   *        This parameter can be one of the following values:
00487   *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
00488   *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
00489   *            @arg @ref IRDA_FLAG_BUSY  Busy flag
00490   *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
00491   *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
00492   *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
00493   *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
00494   *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
00495   *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
00496   *            @arg @ref IRDA_FLAG_NE    Noise Error flag
00497   *            @arg @ref IRDA_FLAG_FE    Framing Error flag
00498   *            @arg @ref IRDA_FLAG_PE    Parity Error flag
00499   * @retval The new state of __FLAG__ (TRUE or FALSE).
00500   */
00501 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00502
00503
00504 /** @brief  Enable the specified IRDA interrupt.
00505   * @param  __HANDLE__: specifies the IRDA Handle.
00506   * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
00507   *          This parameter can be one of the following values:
00508   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00509   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00510   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00511   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00512   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00513   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00514   * @retval None
00515   */
00516 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00517                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00518                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
00519
00520 /** @brief  Disable the specified IRDA interrupt.
00521   * @param  __HANDLE__: specifies the IRDA Handle.
00522   * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
00523   *          This parameter can be one of the following values:
00524   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00525   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00526   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00527   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00528   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00529   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00530   * @retval None
00531   */
00532 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00533                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00534                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
00535
00536
00537 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
00538   * @param  __HANDLE__: specifies the IRDA Handle.
00539   * @param  __IT__: specifies the IRDA interrupt source to check.
00540   *          This parameter can be one of the following values:
00541   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00542   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00543   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00544   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00545   *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
00546   *            @arg @ref IRDA_IT_NE Noise Error interrupt
00547   *            @arg @ref IRDA_IT_FE Framing Error interrupt
00548   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00549   * @retval The new state of __IT__ (TRUE or FALSE).
00550   */
00551 #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
00552
00553 /** @brief  Check whether the specified IRDA interrupt source is enabled or not.
00554   * @param  __HANDLE__: specifies the IRDA Handle.
00555   * @param  __IT__: specifies the IRDA interrupt source to check.
00556   *          This parameter can be one of the following values:
00557   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00558   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00559   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00560   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00561   *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
00562   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00563   * @retval The new state of __IT__ (TRUE or FALSE).
00564   */
00565 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
00566                                                        (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
00567
00568
00569 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
00570   * @param  __HANDLE__: specifies the IRDA Handle.
00571   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00572   *                       to clear the corresponding interrupt
00573   *          This parameter can be one of the following values:
00574   *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
00575   *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
00576   *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
00577   *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
00578   *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
00579   * @retval None
00580   */
00581 #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00582
00583
00584 /** @brief  Set a specific IRDA request flag.
00585   * @param  __HANDLE__: specifies the IRDA Handle.
00586   * @param  __REQ__: specifies the request flag to set
00587   *          This parameter can be one of the following values:
00588   *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
00589   *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
00590   *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
00591   *
00592   * @retval None
00593   */
00594 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00595
00596 /** @brief  Enable the IRDA one bit sample method.
00597   * @param  __HANDLE__: specifies the IRDA Handle.
00598   * @retval None
00599   */
00600 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00601
00602 /** @brief  Disable the IRDA one bit sample method.
00603   * @param  __HANDLE__: specifies the IRDA Handle.
00604   * @retval None
00605   */
00606 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00607
00608 /** @brief  Enable UART/USART associated to IRDA Handle.
00609   * @param  __HANDLE__: specifies the IRDA Handle.
00610   * @retval None
00611   */
00612 #define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00613
00614 /** @brief  Disable UART/USART associated to IRDA Handle.
00615   * @param  __HANDLE__: specifies the IRDA Handle.
00616   * @retval None
00617   */
00618 #define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00619
00620 /**
00621   * @}
00622   */
00623
00624 /* Private macros --------------------------------------------------------*/
00625 /** @defgroup IRDA_Private_Macros   IRDA Private Macros
00626   * @{
00627   */
00628
00629 /** @brief  Compute the mask to apply to retrieve the received data
00630   *         according to the word length and to the parity bits activation.
00631   * @param  __HANDLE__: specifies the IRDA Handle.
00632   * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
00633   */
00634 #define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
00635   do {                                                                \
00636   if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
00637   {                                                                   \
00638      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00639      {                                                                \
00640         (__HANDLE__)->Mask = 0x01FF ;                                 \
00641      }                                                                \
00642      else                                                             \
00643      {                                                                \
00644         (__HANDLE__)->Mask = 0x00FF ;                                 \
00645      }                                                                \
00646   }                                                                   \
00647   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
00648   {                                                                   \
00649      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00650      {                                                                \
00651         (__HANDLE__)->Mask = 0x00FF ;                                 \
00652      }                                                                \
00653      else                                                             \
00654      {                                                                \
00655         (__HANDLE__)->Mask = 0x007F ;                                 \
00656      }                                                                \
00657   }                                                                   \
00658   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \
00659   {                                                                   \
00660      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00661      {                                                                \
00662         (__HANDLE__)->Mask = 0x007F ;                                 \
00663      }                                                                \
00664      else                                                             \
00665      {                                                                \
00666         (__HANDLE__)->Mask = 0x003F ;                                 \
00667      }                                                                \
00668   }                                                                   \
00669 } while(0)
00670
00671 /** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
00672   * @param  __BAUDRATE__: specifies the IRDA Baudrate set by the user.
00673   * @retval True or False
00674   */
00675 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
00676
00677 /** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
00678   * @param  __PRESCALER__: specifies the IRDA prescaler value set by the user.
00679   * @retval True or False
00680   */
00681 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
00682
00683 /**
00684   * @brief Ensure that IRDA frame length is valid.
00685   * @param __LENGTH__: IRDA frame length.
00686   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00687   */
00688 #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
00689                                          ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
00690                                          ((__LENGTH__) == IRDA_WORDLENGTH_9B))
00691
00692 /**
00693   * @brief Ensure that IRDA frame parity is valid.
00694   * @param __PARITY__: IRDA frame parity.
00695   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00696   */
00697 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
00698                                     ((__PARITY__) == IRDA_PARITY_EVEN) || \
00699                                     ((__PARITY__) == IRDA_PARITY_ODD))
00700
00701 /**
00702   * @brief Ensure that IRDA communication mode is valid.
00703   * @param __MODE__: IRDA communication mode.
00704   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00705   */
00706 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
00707
00708 /**
00709   * @brief Ensure that IRDA power mode is valid.
00710   * @param __MODE__: IRDA power mode.
00711   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00712   */
00713 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
00714                                      ((__MODE__) == IRDA_POWERMODE_NORMAL))
00715
00716 /**
00717   * @brief Ensure that IRDA state is valid.
00718   * @param __STATE__: IRDA state mode.
00719   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00720   */
00721 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
00722                                   ((__STATE__) == IRDA_STATE_ENABLE))
00723
00724 /**
00725   * @brief Ensure that IRDA associated UART/USART mode is valid.
00726   * @param __MODE__: IRDA associated UART/USART mode.
00727   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00728   */
00729 #define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
00730                                  ((__MODE__) == IRDA_MODE_ENABLE))
00731
00732 /**
00733   * @brief Ensure that IRDA sampling rate is valid.
00734   * @param __ONEBIT__: IRDA sampling rate.
00735   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00736   */
00737 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
00738                                                  ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
00739
00740 /**
00741   * @brief Ensure that IRDA DMA TX mode is valid.
00742   * @param __DMATX__: IRDA DMA TX mode.
00743   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
00744   */
00745 #define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
00746                                        ((__DMATX__) == IRDA_DMA_TX_ENABLE))
00747
00748 /**
00749   * @brief Ensure that IRDA DMA RX mode is valid.
00750   * @param __DMARX__: IRDA DMA RX mode.
00751   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
00752   */
00753 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
00754                                    ((__DMARX__) == IRDA_DMA_RX_ENABLE))
00755
00756 /**
00757   * @brief Ensure that IRDA request is valid.
00758   * @param __PARAM__: IRDA request.
00759   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00760   */
00761 #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
00762                                               ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
00763                                               ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
00764 /**
00765  * @}
00766  */
00767
00768 /* Include IRDA HAL Extended module */
00769 #include "stm32l4xx_hal_irda_ex.h"
00770
00771 /* Exported functions --------------------------------------------------------*/
00772 /** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
00773   * @{
00774   */
00775
00776 /** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00777   * @{
00778   */
00779
00780 /* Initialization and de-initialization functions  ****************************/
00781 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
00782 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
00783 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
00784 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
00785
00786 /**
00787   * @}
00788   */
00789
00790 /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
00791   * @{
00792   */
00793
00794 /* IO operation functions *****************************************************/
00795 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00796 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00797 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00798 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00799 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00800 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00801 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
00802 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
00803 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
00804 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
00805 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
00806 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
00807 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00808 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00809 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
00810
00811 /**
00812   * @}
00813   */
00814
00815 /* Peripheral Control functions  ************************************************/
00816
00817 /** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
00818   * @{
00819   */
00820
00821 /* Peripheral State and Error functions ***************************************/
00822 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
00823 uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
00824
00825 /**
00826   * @}
00827   */
00828
00829 /**
00830   * @}
00831   */
00832
00833 /**
00834   * @}
00835   */
00836
00837 /**
00838   * @}
00839   */
00840
00841 #ifdef __cplusplus
00842 }
00843 #endif
00844
00845 #endif /* __STM32L4xx_HAL_IRDA_H */
00846
00847 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_irda_ex.h Source File

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stm32l4xx_hal_irda_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_irda_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of IRDA HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_IRDA_EX_H
00040 #define __STM32L4xx_HAL_IRDA_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IRDAEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /* Exported macros -----------------------------------------------------------*/
00060 /* Exported functions --------------------------------------------------------*/
00061
00062 /* Private macros ------------------------------------------------------------*/
00063
00064 /** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
00065   * @{
00066   */
00067
00068 /** @brief  Report the IRDA clock source.
00069   * @param  __HANDLE__: specifies the IRDA Handle.
00070   * @param  __CLOCKSOURCE__: output variable.
00071   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
00072   */
00073 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00074 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00075   do {                                                        \
00076     if((__HANDLE__)->Instance == USART1)                      \
00077     {                                                         \
00078        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00079        {                                                      \
00080         case RCC_USART1CLKSOURCE_PCLK2:                       \
00081           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
00082           break;                                              \
00083         case RCC_USART1CLKSOURCE_HSI:                         \
00084           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00085           break;                                              \
00086         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00087           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00088           break;                                              \
00089         case RCC_USART1CLKSOURCE_LSE:                         \
00090           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00091           break;                                              \
00092         default:                                              \
00093           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00094           break;                                              \
00095        }                                                      \
00096     }                                                         \
00097     else if((__HANDLE__)->Instance == USART2)                 \
00098     {                                                         \
00099        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00100        {                                                      \
00101         case RCC_USART2CLKSOURCE_PCLK1:                       \
00102           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00103           break;                                              \
00104         case RCC_USART2CLKSOURCE_HSI:                         \
00105           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00106           break;                                              \
00107         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00108           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00109           break;                                              \
00110         case RCC_USART2CLKSOURCE_LSE:                         \
00111           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00112           break;                                              \
00113         default:                                              \
00114           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00115           break;                                              \
00116        }                                                      \
00117     }                                                         \
00118     else if((__HANDLE__)->Instance == USART3)                 \
00119     {                                                         \
00120        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00121        {                                                      \
00122         case RCC_USART3CLKSOURCE_PCLK1:                       \
00123           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00124           break;                                              \
00125         case RCC_USART3CLKSOURCE_HSI:                         \
00126           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00127           break;                                              \
00128         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00129           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00130           break;                                              \
00131         case RCC_USART3CLKSOURCE_LSE:                         \
00132           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00133           break;                                              \
00134         default:                                              \
00135           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00136           break;                                              \
00137        }                                                      \
00138     }                                                         \
00139     else if((__HANDLE__)->Instance == UART4)                  \
00140     {                                                         \
00141        switch(__HAL_RCC_GET_UART4_SOURCE())                   \
00142        {                                                      \
00143         case RCC_UART4CLKSOURCE_PCLK1:                        \
00144           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00145           break;                                              \
00146         case RCC_UART4CLKSOURCE_HSI:                          \
00147           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00148           break;                                              \
00149         case RCC_UART4CLKSOURCE_SYSCLK:                       \
00150           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00151           break;                                              \
00152         case RCC_UART4CLKSOURCE_LSE:                          \
00153           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00154           break;                                              \
00155         default:                                              \
00156           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00157           break;                                              \
00158        }                                                      \
00159     }                                                         \
00160     else if ((__HANDLE__)->Instance == UART5)                 \
00161     {                                                         \
00162        switch(__HAL_RCC_GET_UART5_SOURCE())                   \
00163        {                                                      \
00164         case RCC_UART5CLKSOURCE_PCLK1:                        \
00165           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00166           break;                                              \
00167         case RCC_UART5CLKSOURCE_HSI:                          \
00168           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00169           break;                                              \
00170         case RCC_UART5CLKSOURCE_SYSCLK:                       \
00171           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00172           break;                                              \
00173         case RCC_UART5CLKSOURCE_LSE:                          \
00174           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00175           break;                                              \
00176         default:                                              \
00177           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00178           break;                                              \
00179        }                                                      \
00180     }                                                         \
00181   } while(0)
00182 #elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
00183 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00184   do {                                                        \
00185     if((__HANDLE__)->Instance == USART1)                      \
00186     {                                                         \
00187        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00188        {                                                      \
00189         case RCC_USART1CLKSOURCE_PCLK2:                       \
00190           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
00191           break;                                              \
00192         case RCC_USART1CLKSOURCE_HSI:                         \
00193           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00194           break;                                              \
00195         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00196           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00197           break;                                              \
00198         case RCC_USART1CLKSOURCE_LSE:                         \
00199           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00200           break;                                              \
00201         default:                                              \
00202           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00203           break;                                              \
00204        }                                                      \
00205     }                                                         \
00206     else if((__HANDLE__)->Instance == USART2)                 \
00207     {                                                         \
00208        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00209        {                                                      \
00210         case RCC_USART2CLKSOURCE_PCLK1:                       \
00211           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00212           break;                                              \
00213         case RCC_USART2CLKSOURCE_HSI:                         \
00214           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00215           break;                                              \
00216         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00217           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00218           break;                                              \
00219         case RCC_USART2CLKSOURCE_LSE:                         \
00220           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00221           break;                                              \
00222         default:                                              \
00223           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00224           break;                                              \
00225        }                                                      \
00226     }                                                         \
00227     else if((__HANDLE__)->Instance == USART3)                 \
00228     {                                                         \
00229        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00230        {                                                      \
00231         case RCC_USART3CLKSOURCE_PCLK1:                       \
00232           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00233           break;                                              \
00234         case RCC_USART3CLKSOURCE_HSI:                         \
00235           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00236           break;                                              \
00237         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00238           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00239           break;                                              \
00240         case RCC_USART3CLKSOURCE_LSE:                         \
00241           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00242           break;                                              \
00243         default:                                              \
00244           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00245           break;                                              \
00246        }                                                      \
00247     }                                                         \
00248   } while(0)
00249 #elif defined (STM32L432xx) || defined (STM32L442xx)
00250 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00251   do {                                                        \
00252     if((__HANDLE__)->Instance == USART1)                      \
00253     {                                                         \
00254        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00255        {                                                      \
00256         case RCC_USART1CLKSOURCE_PCLK2:                       \
00257           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
00258           break;                                              \
00259         case RCC_USART1CLKSOURCE_HSI:                         \
00260           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00261           break;                                              \
00262         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00263           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00264           break;                                              \
00265         case RCC_USART1CLKSOURCE_LSE:                         \
00266           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00267           break;                                              \
00268         default:                                              \
00269           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00270           break;                                              \
00271        }                                                      \
00272     }                                                         \
00273     else if((__HANDLE__)->Instance == USART2)                 \
00274     {                                                         \
00275        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00276        {                                                      \
00277         case RCC_USART2CLKSOURCE_PCLK1:                       \
00278           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
00279           break;                                              \
00280         case RCC_USART2CLKSOURCE_HSI:                         \
00281           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
00282           break;                                              \
00283         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00284           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
00285           break;                                              \
00286         case RCC_USART2CLKSOURCE_LSE:                         \
00287           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
00288           break;                                              \
00289         default:                                              \
00290           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
00291           break;                                              \
00292        }                                                      \
00293     }                                                         \
00294   } while(0)
00295 #endif
00296
00297 /**
00298   * @}
00299   */
00300
00301 /* Exported functions --------------------------------------------------------*/
00302
00303 /**
00304   * @}
00305   */
00306
00307 /**
00308   * @}
00309   */
00310
00311 #ifdef __cplusplus
00312 }
00313 #endif
00314
00315 #endif /* __STM32L4xx_HAL_IRDA_EX_H */
00316
00317 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_iwdg.c Source File

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stm32l4xx_hal_iwdg.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_iwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   IWDG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Independent Watchdog (IWDG) peripheral:
00010   *           + Initialization and Start functions
00011   *           + IO operation functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### IWDG Generic features #####
00016   ==============================================================================
00017   [..]
00018     (+) The IWDG can be started by either software or hardware (configurable
00019         through option byte).
00020
00021     (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
00022         if the main clock fails.
00023
00024     (+) Once the IWDG is started, the LSI is forced ON and both can not be
00025         disabled. The counter starts counting down from the reset value (0xFFF).
00026         When it reaches the end of count value (0x000) a reset signal is
00027         generated (IWDG reset).
00028
00029     (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
00030         the IWDG_RLR value is reloaded in the counter and the watchdog reset is
00031         prevented.
00032
00033     (+) The IWDG is implemented in the VDD voltage domain that is still functional
00034         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
00035         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
00036         reset occurs.
00037
00038     (+) Debug mode : When the microcontroller enters debug mode (core halted),
00039         the IWDG counter either continues to work normally or stops, depending
00040         on DBG_IWDG_STOP configuration bit in DBG module, accessible through
00041         __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
00042
00043     [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
00044          The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx
00045          devices provide the capability to measure the LSI frequency (LSI clock
00046          connected internally to TIM16 CH1 input capture). The measured value
00047          can be used to have an IWDG timeout with an acceptable accuracy.
00048
00049                      ##### How to use this driver #####
00050   ==============================================================================
00051   [..]
00052     (#) Use IWDG using HAL_IWDG_Init() function to :
00053       (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
00054            clock is forced ON and IWDG counter starts downcounting.
00055       (+) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
00056            IWDG_WINR.
00057       (+) Configure the IWDG prescaler and counter reload value. This reload
00058            value will be loaded in the IWDG counter each time the watchdog is
00059            reloaded, then the IWDG will start counting down from this value.
00060       (+) wait for status flags to be reset"
00061       (+) Depending on window parameter:
00062         (++) If Window Init parameter is same as Window register value,
00063              nothing more is done but reload counter value in order to exit
00064              function withy exact time base.
00065         (++) Else modify Window register. This will automatically reload
00066              watchdog counter.
00067
00068     (#) Then the application program must refresh the IWDG counter at regular
00069         intervals during normal operation to prevent an MCU reset, using
00070         HAL_IWDG_Refresh() function.
00071
00072      *** IWDG HAL driver macros list ***
00073      ====================================
00074      [..]
00075        Below the list of most used macros in IWDG HAL driver:
00076       (+) __HAL_IWDG_START: Enable the IWDG peripheral
00077       (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
00078           the reload register
00079
00080   @endverbatim
00081   ******************************************************************************
00082   * @attention
00083   *
00084   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00085   *
00086   * Redistribution and use in source and binary forms, with or without modification,
00087   * are permitted provided that the following conditions are met:
00088   *   1. Redistributions of source code must retain the above copyright notice,
00089   *      this list of conditions and the following disclaimer.
00090   *   2. Redistributions in binary form must reproduce the above copyright notice,
00091   *      this list of conditions and the following disclaimer in the documentation
00092   *      and/or other materials provided with the distribution.
00093   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00094   *      may be used to endorse or promote products derived from this software
00095   *      without specific prior written permission.
00096   *
00097   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00098   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00099   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00100   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00101   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00102   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00103   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00104   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00105   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00106   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00107   *
00108   ******************************************************************************
00109   */
00110
00111 /* Includes ------------------------------------------------------------------*/
00112 #include "stm32l4xx_hal.h"
00113
00114 /** @addtogroup STM32L4xx_HAL_Driver
00115   * @{
00116   */
00117
00118 #ifdef HAL_IWDG_MODULE_ENABLED
00119 /** @addtogroup IWDG
00120   * @brief IWDG HAL module driver.
00121   * @{
00122   */
00123
00124 /* Private typedef -----------------------------------------------------------*/
00125 /* Private define ------------------------------------------------------------*/
00126 /** @defgroup IWDG_Private_Defines IWDG Private Defines
00127   * @{
00128   */
00129 /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
00130    higher prescaler (256), and according to HSI variation, we need to wait at
00131    least 6 cycles so 48 ms. */
00132 #define HAL_IWDG_DEFAULT_TIMEOUT            48u
00133 /**
00134   * @}
00135   */
00136
00137 /* Private macro -------------------------------------------------------------*/
00138 /* Private variables ---------------------------------------------------------*/
00139 /* Private function prototypes -----------------------------------------------*/
00140 /* Exported functions --------------------------------------------------------*/
00141
00142 /** @addtogroup IWDG_Exported_Functions
00143   * @{
00144   */
00145
00146 /** @addtogroup IWDG_Exported_Functions_Group1
00147  *  @brief    Initialization and Start functions.
00148  *
00149 @verbatim
00150  ===============================================================================
00151           ##### Initialization and Start functions #####
00152  ===============================================================================
00153  [..]  This section provides functions allowing to:
00154       (+) Initialize the IWDG according to the specified parameters in the
00155           IWDG_InitTypeDef of associated handle.
00156       (+) Manage Window option.
00157       (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
00158           is reloaded in order to exit function with correct time base.
00159
00160 @endverbatim
00161   * @{
00162   */
00163
00164 /**
00165   * @brief  Initialize the IWDG according to the specified parameters in the
00166   *         IWDG_InitTypeDef and start watchdog. Before exiting function,
00167   *         watchdog is refreshed in order to have correct time base.
00168   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00169   *                the configuration information for the specified IWDG module.
00170   * @retval HAL status
00171   */
00172 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
00173 {
00174   uint32_t tickstart;
00175
00176   /* Check the IWDG handle allocation */
00177   if(hiwdg == NULL)
00178   {
00179     return HAL_ERROR;
00180   }
00181
00182   /* Check the parameters */
00183   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
00184   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
00185   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
00186   assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
00187
00188   /* Enable IWDG. LSI is turned on automaticaly */
00189   __HAL_IWDG_START(hiwdg);
00190
00191   /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
00192   0x5555 in KR */
00193   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
00194
00195   /* Write to IWDG registers the Prescaler & Reload values to work with */
00196   hiwdg->Instance->PR = hiwdg->Init.Prescaler;
00197   hiwdg->Instance->RLR = hiwdg->Init.Reload;
00198
00199   /* Check pending flag, if previous update not done, return timeout */
00200   tickstart = HAL_GetTick();
00201
00202    /* Wait for register to be updated */
00203   while(hiwdg->Instance->SR != RESET)
00204   {
00205     if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
00206     {
00207       return HAL_TIMEOUT;
00208     }
00209   }
00210
00211   /* If window parameter is different than current value, modify window
00212   register */
00213   if(hiwdg->Instance->WINR != hiwdg->Init.Window)
00214   {
00215     /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
00216     even if window feature is disabled, Watchdog will be reloaded by writing
00217     windows register */
00218     hiwdg->Instance->WINR = hiwdg->Init.Window;
00219   }
00220   else
00221   {
00222     /* Reload IWDG counter with value defined in the reload register */
00223     __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00224   }
00225
00226   /* Return function status */
00227   return HAL_OK;
00228 }
00229
00230 /**
00231   * @}
00232   */
00233
00234
00235 /** @addtogroup IWDG_Exported_Functions_Group2
00236  *  @brief   IO operation functions
00237  *
00238 @verbatim
00239  ===============================================================================
00240                       ##### IO operation functions #####
00241  ===============================================================================
00242  [..]  This section provides functions allowing to:
00243       (+) Refresh the IWDG.
00244
00245 @endverbatim
00246   * @{
00247   */
00248
00249
00250 /**
00251   * @brief  Refresh the IWDG.
00252   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00253   *                the configuration information for the specified IWDG module.
00254   * @retval HAL status
00255   */
00256 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
00257 {
00258   /* Reload IWDG counter with value defined in the reload register */
00259   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00260
00261   /* Return function status */
00262   return HAL_OK;
00263 }
00264
00265 /**
00266   * @}
00267   */
00268
00269 /**
00270   * @}
00271   */
00272
00273 #endif /* HAL_IWDG_MODULE_ENABLED */
00274 /**
00275   * @}
00276   */
00277
00278 /**
00279   * @}
00280   */
00281
00282 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_iwdg.h Source File

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stm32l4xx_hal_iwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_iwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of IWDG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_IWDG_H
00040 #define __STM32L4xx_HAL_IWDG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup IWDG IWDG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup IWDG_Exported_Types IWDG Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  IWDG Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
00068                             This parameter can be a value of @ref IWDG_Prescaler */
00069
00070   uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
00071                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00072
00073   uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
00074                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00075
00076 } IWDG_InitTypeDef;
00077
00078 /**
00079   * @brief  IWDG Handle Structure definition
00080   */
00081 typedef struct
00082 {
00083   IWDG_TypeDef                 *Instance;  /*!< Register base address    */
00084
00085   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
00086
00087 }IWDG_HandleTypeDef;
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported constants --------------------------------------------------------*/
00094 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
00095   * @{
00096   */
00097
00098 /** @defgroup IWDG_Prescaler IWDG Prescaler
00099   * @{
00100   */
00101 #define IWDG_PRESCALER_4                0x00000000u                   /*!< IWDG prescaler set to 4   */
00102 #define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
00103 #define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
00104 #define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
00105 #define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
00106 #define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)   /*!< IWDG prescaler set to 128 */
00107 #define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)   /*!< IWDG prescaler set to 256 */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup IWDG_Window_option IWDG Window option
00113   * @{
00114   */
00115 #define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123
00124 /* Exported macros -----------------------------------------------------------*/
00125 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
00126   * @{
00127   */
00128
00129 /**
00130   * @brief  Enable the IWDG peripheral.
00131   * @param  __HANDLE__  IWDG handle
00132   * @retval None
00133   */
00134 #define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
00135
00136 /**
00137   * @brief  Reload IWDG counter with value defined in the reload register
00138   *         (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
00139   * @param  __HANDLE__  IWDG handle
00140   * @retval None
00141   */
00142 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
00143
00144 /**
00145   * @}
00146   */
00147
00148 /* Exported functions --------------------------------------------------------*/
00149 /** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
00150   * @{
00151   */
00152
00153 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
00154   * @{
00155   */
00156 /* Initialization/Start functions  ********************************************/
00157 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
00163   * @{
00164   */
00165 /* I/O operation functions ****************************************************/
00166 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
00167 /**
00168   * @}
00169   */
00170
00171 /**
00172   * @}
00173   */
00174
00175 /* Private constants ---------------------------------------------------------*/
00176 /** @defgroup IWDG_Private_Constants IWDG Private Constants
00177   * @{
00178   */
00179
00180 /**
00181   * @brief  IWDG Key Register BitMask
00182   */
00183 #define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
00184 #define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
00185 #define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
00186 #define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
00187
00188 /**
00189   * @}
00190   */
00191
00192 /* Private macros ------------------------------------------------------------*/
00193 /** @defgroup IWDG_Private_Macros IWDG Private Macros
00194   * @{
00195   */
00196
00197 /**
00198   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00199   * @param  __HANDLE__  IWDG handle
00200   * @retval None
00201   */
00202 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
00203
00204 /**
00205   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00206   * @param  __HANDLE__  IWDG handle
00207   * @retval None
00208   */
00209 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
00210
00211 /**
00212   * @brief  Check IWDG prescaler value.
00213   * @param  __PRESCALER__  IWDG prescaler value
00214   * @retval None
00215   */
00216 #define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
00217                                                ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
00218                                                ((__PRESCALER__) == IWDG_PRESCALER_16) || \
00219                                                ((__PRESCALER__) == IWDG_PRESCALER_32) || \
00220                                                ((__PRESCALER__) == IWDG_PRESCALER_64) || \
00221                                                ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
00222                                                ((__PRESCALER__) == IWDG_PRESCALER_256))
00223
00224 /**
00225   * @brief  Check IWDG reload value.
00226   * @param  __RELOAD__  IWDG reload value
00227   * @retval None
00228   */
00229 #define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
00230
00231 /**
00232   * @brief  Check IWDG window value.
00233   * @param  __WINDOW__  IWDG window value
00234   * @retval None
00235   */
00236 #define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
00237
00238 /**
00239   * @}
00240   */
00241
00242 /**
00243   * @}
00244   */
00245
00246 /**
00247   * @}
00248   */
00249
00250
00251 #ifdef __cplusplus
00252 }
00253 #endif
00254
00255 #endif /* __STM32L4xx_HAL_IWDG_H */
00256
00257 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_lcd.c Source File

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  • STM32L4xx_HAL_Driver
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stm32l4xx_hal_lcd.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_lcd.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   LCD Controller HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the LCD Controller (LCD) peripheral:
00010   *           + Initialization/de-initialization methods
00011   *           + I/O operation methods
00012   *           + Peripheral State methods
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018       [..] The LCD HAL driver can be used as follows:
00019
00020       (#) Declare a LCD_HandleTypeDef handle structure.
00021
00022       -@- The frequency generator allows you to achieve various LCD frame rates
00023           starting from an LCD input clock frequency (LCDCLK) which can vary
00024           from 32 kHz up to 1 MHz.
00025
00026       (#) Initialize the LCD low level resources by implementing the HAL_LCD_MspInit() API:
00027
00028           (++) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows:
00029                (+++) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and
00030                   selected clock source (HSE, LSI or LSE)
00031
00032           (++) LCD pins configuration:
00033               (+++) Enable the clock for the LCD GPIOs.
00034               (+++) Configure these LCD pins as alternate function no-pull.
00035           (++) Enable the LCD interface clock.
00036
00037
00038       (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias,
00039           Voltage Source, Dead Time, Pulse On Duration, Contrast, High drive and Multiplexer
00040           Segment in the Init structure of the LCD handle.
00041
00042       (#) Initialize the LCD registers by calling the HAL_LCD_Init() API.
00043
00044       -@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc)
00045           by calling the customized HAL_LCD_MspInit() API.
00046       -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared
00047
00048       (#) Optionally you can update the LCD configuration using these macros:
00049               (++) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
00050               (++) Voltage output buffer using __HAL_LCD_VOLTAGE_BUFFER_ENABLE() and __HAL_LCD_VOLTAGE_BUFFER_DISABLE() macros
00051               (++) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
00052               (++) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro
00053               (++) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
00054               (++) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro
00055
00056       (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
00057           more time to update the different LCD RAM registers before calling
00058           HAL_LCD_UpdateDisplayRequest() API.
00059
00060       (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.
00061
00062       (#) When LCD RAM memory is updated enable the update display request using
00063           the HAL_LCD_UpdateDisplayRequest() API.
00064
00065       [..] LCD and low power modes:
00066            (#) The LCD remain active during Sleep, Low Power run, Low Power Sleep and
00067                STOP modes.
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32l4xx_hal.h"
00102
00103 #if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx)
00104
00105 /** @addtogroup STM32L4xx_HAL_Driver
00106   * @{
00107   */
00108
00109 #ifdef HAL_LCD_MODULE_ENABLED
00110
00111 /** @defgroup LCD LCD
00112   * @brief LCD HAL module driver
00113   * @{
00114   */
00115
00116 /* Private typedef -----------------------------------------------------------*/
00117 /* Private define ------------------------------------------------------------*/
00118 /** @defgroup LCD_Private_Defines LCD Private Defines
00119   * @{
00120   */
00121
00122 #define LCD_TIMEOUT_VALUE             1000
00123
00124 /**
00125   * @}
00126   */
00127
00128 /* Private macro -------------------------------------------------------------*/
00129 /* Private variables ---------------------------------------------------------*/
00130 /* Private function prototypes -----------------------------------------------*/
00131 /* Exported functions --------------------------------------------------------*/
00132
00133 /** @defgroup LCD_Exported_Functions LCD Exported Functions
00134   * @{
00135   */
00136
00137 /** @defgroup LCD_Exported_Functions_Group1 Initialization/de-initialization methods
00138   *  @brief    Initialization and Configuration functions
00139   *
00140 @verbatim
00141 ===============================================================================
00142             ##### Initialization and Configuration functions #####
00143  ===============================================================================
00144     [..]
00145
00146 @endverbatim
00147   * @{
00148   */
00149
00150 /**
00151   * @brief  Initialize the LCD peripheral according to the specified parameters
00152   *         in the LCD_InitStruct and initialize the associated handle.
00153   * @note   This function can be used only when the LCD is disabled.
00154   * @param  hlcd: LCD handle
00155   * @retval None
00156   */
00157 HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
00158 {
00159   uint32_t tickstart = 0x00;
00160   uint32_t counter = 0;
00161
00162   /* Check the LCD handle allocation */
00163   if(hlcd == NULL)
00164   {
00165     return HAL_ERROR;
00166   }
00167
00168   /* Check function parameters */
00169   assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
00170   assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler));
00171   assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider));
00172   assert_param(IS_LCD_DUTY(hlcd->Init.Duty));
00173   assert_param(IS_LCD_BIAS(hlcd->Init.Bias));
00174   assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource));
00175   assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration));
00176   assert_param(IS_LCD_HIGH_DRIVE(hlcd->Init.HighDrive));
00177   assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime));
00178   assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast));
00179   assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency));
00180   assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode));
00181   assert_param(IS_LCD_MUX_SEGMENT(hlcd->Init.MuxSegment));
00182
00183   if(hlcd->State == HAL_LCD_STATE_RESET)
00184   {
00185     /* Allocate lock resource and initialize it */
00186     hlcd->Lock = HAL_UNLOCKED;
00187
00188     /* Initialize the low level hardware (MSP) */
00189     HAL_LCD_MspInit(hlcd);
00190   }
00191
00192   hlcd->State = HAL_LCD_STATE_BUSY;
00193
00194   /* Disable the peripheral */
00195   __HAL_LCD_DISABLE(hlcd);
00196
00197   /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit
00198      in the LCD_SR register */
00199   for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
00200   {
00201     hlcd->Instance->RAM[counter] = 0;
00202   }
00203   /* Enable the display request */
00204   hlcd->Instance->SR |= LCD_SR_UDR;
00205
00206   /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency:
00207      Set PS[3:0] bits according to hlcd->Init.Prescaler value
00208      Set DIV[3:0] bits according to hlcd->Init.Divider value
00209      Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value
00210      Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value
00211      Set DEAD[2:0] bits according to hlcd->Init.DeadTime value
00212      Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value
00213      Set CC[2:0] bits according to hlcd->Init.Contrast value
00214      Set HD bit according to hlcd->Init.HighDrive value */
00215    MODIFY_REG(hlcd->Instance->FCR, \
00216       (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \
00217        LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC | LCD_FCR_HD), \
00218       (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \
00219        hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive));
00220
00221   /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register
00222      This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK
00223      domain. It is cleared by hardware when writing to the LCD_FCR register.*/
00224   LCD_WaitForSynchro(hlcd);
00225
00226   /* Configure the LCD Duty, Bias, Voltage Source, Dead Time, Pulse On Duration and Contrast:
00227      Set DUTY[2:0] bits according to hlcd->Init.Duty value
00228      Set BIAS[1:0] bits according to hlcd->Init.Bias value
00229      Set VSEL bit according to hlcd->Init.VoltageSource value
00230      Set MUX_SEG bit according to hlcd->Init.MuxSegment value */
00231   MODIFY_REG(hlcd->Instance->CR, \
00232     (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \
00233     (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment));
00234
00235   /* Enable the peripheral */
00236   __HAL_LCD_ENABLE(hlcd);
00237
00238   /* Get timeout */
00239   tickstart = HAL_GetTick();
00240
00241   /* Wait Until the LCD is enabled */
00242   while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET)
00243   {
00244     if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
00245     {
00246       hlcd->ErrorCode = HAL_LCD_ERROR_ENS;
00247       return HAL_TIMEOUT;
00248     }
00249   }
00250
00251   /* Get timeout */
00252   tickstart = HAL_GetTick();
00253
00254   /*!< Wait Until the LCD Booster is ready */
00255   while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET)
00256   {
00257     if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
00258     {
00259       hlcd->ErrorCode = HAL_LCD_ERROR_RDY;
00260       return HAL_TIMEOUT;
00261     }
00262   }
00263
00264   /* Initialize the LCD state */
00265   hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
00266   hlcd->State= HAL_LCD_STATE_READY;
00267
00268   return HAL_OK;
00269 }
00270
00271 /**
00272   * @brief  DeInitialize the LCD peripheral.
00273   * @param  hlcd: LCD handle
00274   * @retval HAL status
00275   */
00276 HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd)
00277 {
00278   /* Check the LCD handle allocation */
00279   if(hlcd == NULL)
00280   {
00281     return HAL_ERROR;
00282   }
00283
00284   /* Check the parameters */
00285   assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
00286
00287   hlcd->State = HAL_LCD_STATE_BUSY;
00288
00289   /* DeInit the low level hardware */
00290   HAL_LCD_MspDeInit(hlcd);
00291
00292   hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
00293   hlcd->State = HAL_LCD_STATE_RESET;
00294
00295   /* Release Lock */
00296   __HAL_UNLOCK(hlcd);
00297
00298   return HAL_OK;
00299 }
00300
00301 /**
00302   * @brief  DeInitialize the LCD MSP.
00303   * @param  hlcd: LCD handle
00304   * @retval None
00305   */
00306 __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd)
00307 {
00308   /* Prevent unused argument(s) compilation warning */
00309   UNUSED(hlcd);
00310
00311   /* NOTE: This function should not be modified, when the callback is needed,
00312            the HAL_LCD_MspDeInit it to be implemented in the user file
00313    */
00314 }
00315
00316 /**
00317   * @brief  Initialize the LCD MSP.
00318   * @param  hlcd: LCD handle
00319   * @retval None
00320   */
00321 __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd)
00322 {
00323   /* Prevent unused argument(s) compilation warning */
00324   UNUSED(hlcd);
00325
00326   /* NOTE: This function should not be modified, when the callback is needed,
00327            the HAL_LCD_MspInit is to be implemented in the user file
00328    */
00329 }
00330
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup LCD_Exported_Functions_Group2 IO operation methods
00336   *  @brief LCD RAM functions
00337   *
00338 @verbatim
00339  ===============================================================================
00340                       ##### IO operation functions #####
00341  ===============================================================================
00342  [..] Using its double buffer memory the LCD controller ensures the coherency of the
00343  displayed information without having to use interrupts to control LCD_RAM
00344  modification.
00345  The application software can access the first buffer level (LCD_RAM) through
00346  the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API,
00347  it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API.
00348  This UDR flag (update display request) requests the updated information to be
00349  moved into the second buffer level (LCD_DISPLAY).
00350  This operation is done synchronously with the frame (at the beginning of the
00351  next frame), until the update is completed, the LCD_RAM is write protected and
00352  the UDR flag stays high.
00353  Once the update is completed another flag (UDD - Update Display Done) is set and
00354  generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
00355  The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one
00356  even frame.
00357  The update will not occur (UDR = 1 and UDD = 0) until the display is
00358  enabled (LCDEN = 1).
00359
00360 @endverbatim
00361   * @{
00362   */
00363
00364 /**
00365   * @brief  Write a word in the specific LCD RAM.
00366   * @param  hlcd: LCD handle
00367   * @param  RAMRegisterIndex: specifies the LCD RAM Register.
00368   *   This parameter can be one of the following values:
00369   *     @arg LCD_RAM_REGISTER0: LCD RAM Register 0
00370   *     @arg LCD_RAM_REGISTER1: LCD RAM Register 1
00371   *     @arg LCD_RAM_REGISTER2: LCD RAM Register 2
00372   *     @arg LCD_RAM_REGISTER3: LCD RAM Register 3
00373   *     @arg LCD_RAM_REGISTER4: LCD RAM Register 4
00374   *     @arg LCD_RAM_REGISTER5: LCD RAM Register 5
00375   *     @arg LCD_RAM_REGISTER6: LCD RAM Register 6
00376   *     @arg LCD_RAM_REGISTER7: LCD RAM Register 7
00377   *     @arg LCD_RAM_REGISTER8: LCD RAM Register 8
00378   *     @arg LCD_RAM_REGISTER9: LCD RAM Register 9
00379   *     @arg LCD_RAM_REGISTER10: LCD RAM Register 10
00380   *     @arg LCD_RAM_REGISTER11: LCD RAM Register 11
00381   *     @arg LCD_RAM_REGISTER12: LCD RAM Register 12
00382   *     @arg LCD_RAM_REGISTER13: LCD RAM Register 13
00383   *     @arg LCD_RAM_REGISTER14: LCD RAM Register 14
00384   *     @arg LCD_RAM_REGISTER15: LCD RAM Register 15
00385   * @param  RAMRegisterMask: specifies the LCD RAM Register Data Mask.
00386   * @param  Data: specifies LCD Data Value to be written.
00387   * @retval None
00388   */
00389 HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
00390 {
00391   uint32_t tickstart = 0x00;
00392
00393   if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
00394   {
00395     /* Check the parameters */
00396     assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex));
00397
00398     if(hlcd->State == HAL_LCD_STATE_READY)
00399     {
00400       /* Process Locked */
00401       __HAL_LOCK(hlcd);
00402       hlcd->State = HAL_LCD_STATE_BUSY;
00403
00404       /* Get timeout */
00405       tickstart = HAL_GetTick();
00406
00407       /*!< Wait Until the LCD is ready */
00408       while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
00409       {
00410         if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
00411         {
00412           hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
00413
00414           /* Process Unlocked */
00415           __HAL_UNLOCK(hlcd);
00416
00417           return HAL_TIMEOUT;
00418         }
00419       }
00420     }
00421
00422     /* Copy the new Data bytes to LCD RAM register */
00423     MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data);
00424
00425     return HAL_OK;
00426   }
00427   else
00428   {
00429     return HAL_ERROR;
00430   }
00431 }
00432
00433 /**
00434   * @brief Clear the LCD RAM registers.
00435   * @param hlcd: LCD handle
00436   * @retval None
00437   */
00438 HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
00439 {
00440   uint32_t tickstart = 0x00;
00441   uint32_t counter = 0;
00442
00443   if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
00444   {
00445     /* Process Locked */
00446     __HAL_LOCK(hlcd);
00447
00448     hlcd->State = HAL_LCD_STATE_BUSY;
00449
00450     /* Get timeout */
00451     tickstart = HAL_GetTick();
00452
00453     /*!< Wait Until the LCD is ready */
00454     while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
00455     {
00456       if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
00457       {
00458         hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
00459
00460         /* Process Unlocked */
00461         __HAL_UNLOCK(hlcd);
00462
00463         return HAL_TIMEOUT;
00464       }
00465     }
00466     /* Clear the LCD_RAM registers */
00467     for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
00468     {
00469       hlcd->Instance->RAM[counter] = 0;
00470     }
00471
00472     /* Update the LCD display */
00473     HAL_LCD_UpdateDisplayRequest(hlcd);
00474
00475     return HAL_OK;
00476   }
00477   else
00478   {
00479     return HAL_ERROR;
00480   }
00481 }
00482
00483 /**
00484   * @brief  Enable the Update Display Request.
00485   * @param  hlcd: LCD handle
00486   * @note   Each time software modifies the LCD_RAM it must set the UDR bit to
00487   *         transfer the updated data to the second level buffer.
00488   *         The UDR bit stays set until the end of the update and during this
00489   *         time the LCD_RAM is write protected.
00490   * @note   When the display is disabled, the update is performed for all
00491   *         LCD_DISPLAY locations.
00492   *         When the display is enabled, the update is performed only for locations
00493   *         for which commons are active (depending on DUTY). For example if
00494   *         DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
00495   * @retval None
00496   */
00497 HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd)
00498 {
00499   uint32_t tickstart = 0x00;
00500
00501   /* Clear the Update Display Done flag before starting the update display request */
00502   __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD);
00503
00504   /* Enable the display request */
00505   hlcd->Instance->SR |= LCD_SR_UDR;
00506
00507   /* Get timeout */
00508   tickstart = HAL_GetTick();
00509
00510   /*!< Wait Until the LCD display is done */
00511   while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET)
00512   {
00513     if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
00514     {
00515       hlcd->ErrorCode = HAL_LCD_ERROR_UDD;
00516
00517       /* Process Unlocked */
00518       __HAL_UNLOCK(hlcd);
00519
00520       return HAL_TIMEOUT;
00521     }
00522   }
00523
00524   hlcd->State = HAL_LCD_STATE_READY;
00525
00526   /* Process Unlocked */
00527   __HAL_UNLOCK(hlcd);
00528
00529   return HAL_OK;
00530 }
00531
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods
00537   *  @brief   LCD State functions
00538   *
00539 @verbatim
00540  ===============================================================================
00541                       ##### Peripheral State functions #####
00542  ===============================================================================
00543     [..]
00544      This subsection provides a set of functions allowing to control the LCD:
00545       (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State.
00546       (+) HAL_LCD_GetError() API to return the LCD error code.
00547 @endverbatim
00548   * @{
00549   */
00550
00551 /**
00552   * @brief Return the LCD handle state.
00553   * @param hlcd: LCD handle
00554   * @retval HAL state
00555   */
00556 HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd)
00557 {
00558   /* Return LCD handle state */
00559   return hlcd->State;
00560 }
00561
00562 /**
00563   * @brief Return the LCD error code.
00564   * @param hlcd: LCD handle
00565   * @retval LCD Error Code
00566   */
00567 uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd)
00568 {
00569   return hlcd->ErrorCode;
00570 }
00571
00572 /**
00573   * @}
00574   */
00575
00576 /**
00577   * @}
00578   */
00579
00580 /** @defgroup LCD_Private_Functions LCD Private Functions
00581   * @{
00582   */
00583
00584 /**
00585   * @brief  Wait until the LCD FCR register is synchronized in the LCDCLK domain.
00586   *   This function must be called after any write operation to LCD_FCR register.
00587   * @retval None
00588   */
00589 HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
00590 {
00591   uint32_t tickstart = 0x00;
00592
00593   /* Get timeout */
00594   tickstart = HAL_GetTick();
00595
00596   /* Loop until FCRSF flag is set */
00597   while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET)
00598   {
00599     if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
00600     {
00601       hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF;
00602       return HAL_TIMEOUT;
00603     }
00604   }
00605
00606   return HAL_OK;
00607 }
00608
00609 /**
00610   * @}
00611   */
00612
00613 /**
00614   * @}
00615   */
00616
00617 #endif /* HAL_LCD_MODULE_ENABLED */
00618
00619 /**
00620   * @}
00621   */
00622
00623 #endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx */
00624
00625 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00626
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_lcd.h Source File

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stm32l4xx_hal_lcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_lcd.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of LCD Controller HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_LCD_H
00040 #define __STM32L4xx_HAL_LCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32l4xx_hal_def.h"
00050
00051 /** @addtogroup STM32L4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup LCD
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup LCD_Exported_Types LCD Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief LCD Init structure definition
00066   */
00067
00068 typedef struct
00069 {
00070   uint32_t Prescaler;       /*!< Configures the LCD Prescaler.
00071                                  This parameter can be one value of @ref LCD_Prescaler */
00072   uint32_t Divider;         /*!< Configures the LCD Divider.
00073                                  This parameter can be one value of @ref LCD_Divider */
00074   uint32_t Duty;            /*!< Configures the LCD Duty.
00075                                  This parameter can be one value of @ref LCD_Duty */
00076   uint32_t Bias;            /*!< Configures the LCD Bias.
00077                                  This parameter can be one value of @ref LCD_Bias */
00078   uint32_t VoltageSource;   /*!< Selects the LCD Voltage source.
00079                                  This parameter can be one value of @ref LCD_Voltage_Source */
00080   uint32_t Contrast;        /*!< Configures the LCD Contrast.
00081                                  This parameter can be one value of @ref LCD_Contrast */
00082   uint32_t DeadTime;        /*!< Configures the LCD Dead Time.
00083                                  This parameter can be one value of @ref LCD_DeadTime */
00084   uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
00085                                  This parameter can be one value of @ref LCD_PulseOnDuration */
00086   uint32_t HighDrive;       /*!< Enable or disable the low resistance divider.
00087                                  This parameter can be one value of @ref LCD_HighDrive */
00088   uint32_t BlinkMode;       /*!< Configures the LCD Blink Mode.
00089                                  This parameter can be one value of @ref LCD_BlinkMode */
00090   uint32_t BlinkFrequency;  /*!< Configures the LCD Blink frequency.
00091                                  This parameter can be one value of @ref LCD_BlinkFrequency */
00092   uint32_t MuxSegment;      /*!< Enable or disable mux segment.
00093                                  This parameter can be one value of @ref LCD_MuxSegment */
00094 } LCD_InitTypeDef;
00095
00096 /**
00097   * @brief HAL LCD State structures definition
00098   */
00099 typedef enum
00100 {
00101   HAL_LCD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
00102   HAL_LCD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
00103   HAL_LCD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
00104   HAL_LCD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
00105   HAL_LCD_STATE_ERROR             = 0x04     /*!< Error */
00106 } HAL_LCD_StateTypeDef;
00107
00108 /**
00109   * @brief  UART handle Structure definition
00110   */
00111 typedef struct
00112 {
00113   LCD_TypeDef                   *Instance;  /* LCD registers base address */
00114
00115   LCD_InitTypeDef               Init;       /* LCD communication parameters */
00116
00117   HAL_LockTypeDef               Lock;       /* Locking object */
00118
00119   __IO HAL_LCD_StateTypeDef     State;      /* LCD communication state */
00120
00121   __IO uint32_t                 ErrorCode;  /* LCD Error code */
00122
00123 }LCD_HandleTypeDef;
00124 /**
00125   * @}
00126   */
00127
00128 /* Exported constants --------------------------------------------------------*/
00129 /** @defgroup LCD_Exported_Constants LCD Exported Constants
00130   * @{
00131   */
00132
00133 /** @defgroup  LCD_ErrorCode LCD Error Code
00134   * @{
00135   */
00136 #define HAL_LCD_ERROR_NONE       ((uint32_t)0x00)    /*!< No error */
00137 #define HAL_LCD_ERROR_FCRSF      ((uint32_t)0x01)    /*!< Synchro flag timeout error */
00138 #define HAL_LCD_ERROR_UDR        ((uint32_t)0x02)    /*!< Update display request flag timeout error */
00139 #define HAL_LCD_ERROR_UDD        ((uint32_t)0x04)    /*!< Update display done flag timeout error */
00140 #define HAL_LCD_ERROR_ENS        ((uint32_t)0x08)    /*!< LCD enabled status flag timeout error */
00141 #define HAL_LCD_ERROR_RDY        ((uint32_t)0x10)    /*!< LCD Booster ready timeout error */
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup LCD_Prescaler LCD Prescaler
00147   * @{
00148   */
00149 #define LCD_PRESCALER_1        ((uint32_t)0x00000000)  /*!< CLKPS = LCDCLK        */
00150 #define LCD_PRESCALER_2        ((uint32_t)0x00400000)  /*!< CLKPS = LCDCLK/2      */
00151 #define LCD_PRESCALER_4        ((uint32_t)0x00800000)  /*!< CLKPS = LCDCLK/4      */
00152 #define LCD_PRESCALER_8        ((uint32_t)0x00C00000)  /*!< CLKPS = LCDCLK/8      */
00153 #define LCD_PRESCALER_16       ((uint32_t)0x01000000)  /*!< CLKPS = LCDCLK/16     */
00154 #define LCD_PRESCALER_32       ((uint32_t)0x01400000)  /*!< CLKPS = LCDCLK/32     */
00155 #define LCD_PRESCALER_64       ((uint32_t)0x01800000)  /*!< CLKPS = LCDCLK/64     */
00156 #define LCD_PRESCALER_128      ((uint32_t)0x01C00000)  /*!< CLKPS = LCDCLK/128    */
00157 #define LCD_PRESCALER_256      ((uint32_t)0x02000000)  /*!< CLKPS = LCDCLK/256    */
00158 #define LCD_PRESCALER_512      ((uint32_t)0x02400000)  /*!< CLKPS = LCDCLK/512    */
00159 #define LCD_PRESCALER_1024     ((uint32_t)0x02800000)  /*!< CLKPS = LCDCLK/1024   */
00160 #define LCD_PRESCALER_2048     ((uint32_t)0x02C00000)  /*!< CLKPS = LCDCLK/2048   */
00161 #define LCD_PRESCALER_4096     ((uint32_t)0x03000000)  /*!< CLKPS = LCDCLK/4096   */
00162 #define LCD_PRESCALER_8192     ((uint32_t)0x03400000)  /*!< CLKPS = LCDCLK/8192   */
00163 #define LCD_PRESCALER_16384    ((uint32_t)0x03800000)  /*!< CLKPS = LCDCLK/16384  */
00164 #define LCD_PRESCALER_32768    ((uint32_t)0x03C00000)  /*!< CLKPS = LCDCLK/32768  */
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup LCD_Divider LCD Divider
00170   * @{
00171   */
00172 #define LCD_DIVIDER_16    ((uint32_t)0x00000000)  /*!< LCD frequency = CLKPS/16 */
00173 #define LCD_DIVIDER_17    ((uint32_t)0x00040000)  /*!< LCD frequency = CLKPS/17 */
00174 #define LCD_DIVIDER_18    ((uint32_t)0x00080000)  /*!< LCD frequency = CLKPS/18 */
00175 #define LCD_DIVIDER_19    ((uint32_t)0x000C0000)  /*!< LCD frequency = CLKPS/19 */
00176 #define LCD_DIVIDER_20    ((uint32_t)0x00100000)  /*!< LCD frequency = CLKPS/20 */
00177 #define LCD_DIVIDER_21    ((uint32_t)0x00140000)  /*!< LCD frequency = CLKPS/21 */
00178 #define LCD_DIVIDER_22    ((uint32_t)0x00180000)  /*!< LCD frequency = CLKPS/22 */
00179 #define LCD_DIVIDER_23    ((uint32_t)0x001C0000)  /*!< LCD frequency = CLKPS/23 */
00180 #define LCD_DIVIDER_24    ((uint32_t)0x00200000)  /*!< LCD frequency = CLKPS/24 */
00181 #define LCD_DIVIDER_25    ((uint32_t)0x00240000)  /*!< LCD frequency = CLKPS/25 */
00182 #define LCD_DIVIDER_26    ((uint32_t)0x00280000)  /*!< LCD frequency = CLKPS/26 */
00183 #define LCD_DIVIDER_27    ((uint32_t)0x002C0000)  /*!< LCD frequency = CLKPS/27 */
00184 #define LCD_DIVIDER_28    ((uint32_t)0x00300000)  /*!< LCD frequency = CLKPS/28 */
00185 #define LCD_DIVIDER_29    ((uint32_t)0x00340000)  /*!< LCD frequency = CLKPS/29 */
00186 #define LCD_DIVIDER_30    ((uint32_t)0x00380000)  /*!< LCD frequency = CLKPS/30 */
00187 #define LCD_DIVIDER_31    ((uint32_t)0x003C0000)  /*!< LCD frequency = CLKPS/31 */
00188 /**
00189   * @}
00190   */
00191
00192
00193 /** @defgroup LCD_Duty LCD Duty
00194   * @{
00195   */
00196 #define LCD_DUTY_STATIC                 ((uint32_t)0x00000000)            /*!< Static duty */
00197 #define LCD_DUTY_1_2                    (LCD_CR_DUTY_0)                   /*!< 1/2 duty    */
00198 #define LCD_DUTY_1_3                    (LCD_CR_DUTY_1)                   /*!< 1/3 duty    */
00199 #define LCD_DUTY_1_4                    ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty    */
00200 #define LCD_DUTY_1_8                    (LCD_CR_DUTY_2)                   /*!< 1/8 duty    */
00201 /**
00202   * @}
00203   */
00204
00205
00206 /** @defgroup LCD_Bias LCD Bias
00207   * @{
00208   */
00209 #define LCD_BIAS_1_4                    ((uint32_t)0x00000000)  /*!< 1/4 Bias */
00210 #define LCD_BIAS_1_2                    LCD_CR_BIAS_0           /*!< 1/2 Bias */
00211 #define LCD_BIAS_1_3                    LCD_CR_BIAS_1           /*!< 1/3 Bias */
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup LCD_Voltage_Source LCD Voltage Source
00217   * @{
00218   */
00219 #define LCD_VOLTAGESOURCE_INTERNAL      ((uint32_t)0x00000000)  /*!< Internal voltage source for the LCD */
00220 #define LCD_VOLTAGESOURCE_EXTERNAL      LCD_CR_VSEL             /*!< External voltage source for the LCD */
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup LCD_Interrupts LCD Interrupts
00226   * @{
00227   */
00228 #define LCD_IT_SOF                      LCD_FCR_SOFIE
00229 #define LCD_IT_UDD                      LCD_FCR_UDDIE
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
00235   * @{
00236   */
00237 #define LCD_PULSEONDURATION_0           ((uint32_t)0x00000000)          /*!< Pulse ON duration = 0 pulse   */
00238 #define LCD_PULSEONDURATION_1           (LCD_FCR_PON_0)                 /*!< Pulse ON duration = 1/CK_PS  */
00239 #define LCD_PULSEONDURATION_2           (LCD_FCR_PON_1)                 /*!< Pulse ON duration = 2/CK_PS  */
00240 #define LCD_PULSEONDURATION_3           (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS  */
00241 #define LCD_PULSEONDURATION_4           (LCD_FCR_PON_2)                 /*!< Pulse ON duration = 4/CK_PS  */
00242 #define LCD_PULSEONDURATION_5           (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS  */
00243 #define LCD_PULSEONDURATION_6           (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS  */
00244 #define LCD_PULSEONDURATION_7           (LCD_FCR_PON)                   /*!< Pulse ON duration = 7/CK_PS  */
00245 /**
00246   * @}
00247   */
00248
00249
00250 /** @defgroup LCD_DeadTime LCD Dead Time
00251   * @{
00252   */
00253 #define LCD_DEADTIME_0                  ((uint32_t)0x00000000)            /*!< No dead Time  */
00254 #define LCD_DEADTIME_1                  (LCD_FCR_DEAD_0)                  /*!< One Phase between different couple of Frame   */
00255 #define LCD_DEADTIME_2                  (LCD_FCR_DEAD_1)                  /*!< Two Phase between different couple of Frame   */
00256 #define LCD_DEADTIME_3                  (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
00257 #define LCD_DEADTIME_4                  (LCD_FCR_DEAD_2)                  /*!< Four Phase between different couple of Frame  */
00258 #define LCD_DEADTIME_5                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame  */
00259 #define LCD_DEADTIME_6                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame   */
00260 #define LCD_DEADTIME_7                  (LCD_FCR_DEAD)                    /*!< Seven Phase between different couple of Frame */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup LCD_BlinkMode LCD Blink Mode
00266   * @{
00267   */
00268 #define LCD_BLINKMODE_OFF               ((uint32_t)0x00000000)  /*!< Blink disabled            */
00269 #define LCD_BLINKMODE_SEG0_COM0         (LCD_FCR_BLINK_0)       /*!< Blink enabled on SEG[0], COM[0] (1 pixel)   */
00270 #define LCD_BLINKMODE_SEG0_ALLCOM       (LCD_FCR_BLINK_1)       /*!< Blink enabled on SEG[0], all COM (up to
00271                                                                     8 pixels according to the programmed duty)  */
00272 #define LCD_BLINKMODE_ALLSEG_ALLCOM     (LCD_FCR_BLINK)         /*!< Blink enabled on all SEG and all COM (all pixels)  */
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup LCD_BlinkFrequency LCD Blink Frequency
00278   * @{
00279   */
00280 #define LCD_BLINKFREQUENCY_DIV8         ((uint32_t)0x00000000)                /*!< The Blink frequency = fLCD/8    */
00281 #define LCD_BLINKFREQUENCY_DIV16        (LCD_FCR_BLINKF_0)                    /*!< The Blink frequency = fLCD/16   */
00282 #define LCD_BLINKFREQUENCY_DIV32        (LCD_FCR_BLINKF_1)                    /*!< The Blink frequency = fLCD/32   */
00283 #define LCD_BLINKFREQUENCY_DIV64        (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64   */
00284 #define LCD_BLINKFREQUENCY_DIV128       (LCD_FCR_BLINKF_2)                    /*!< The Blink frequency = fLCD/128  */
00285 #define LCD_BLINKFREQUENCY_DIV256       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)  /*!< The Blink frequency = fLCD/256  */
00286 #define LCD_BLINKFREQUENCY_DIV512       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)  /*!< The Blink frequency = fLCD/512  */
00287 #define LCD_BLINKFREQUENCY_DIV1024      (LCD_FCR_BLINKF)                      /*!< The Blink frequency = fLCD/1024 */
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup LCD_Contrast LCD Contrast
00293   * @{
00294   */
00295 #define LCD_CONTRASTLEVEL_0               ((uint32_t)0x00000000)        /*!< Maximum Voltage = 2.60V    */
00296 #define LCD_CONTRASTLEVEL_1               (LCD_FCR_CC_0)                /*!< Maximum Voltage = 2.73V    */
00297 #define LCD_CONTRASTLEVEL_2               (LCD_FCR_CC_1)                /*!< Maximum Voltage = 2.86V    */
00298 #define LCD_CONTRASTLEVEL_3               (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V    */
00299 #define LCD_CONTRASTLEVEL_4               (LCD_FCR_CC_2)                /*!< Maximum Voltage = 3.12V    */
00300 #define LCD_CONTRASTLEVEL_5               (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.26V    */
00301 #define LCD_CONTRASTLEVEL_6               (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.40V    */
00302 #define LCD_CONTRASTLEVEL_7               (LCD_FCR_CC)                  /*!< Maximum Voltage = 3.55V    */
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup LCD_RAMRegister LCD RAMRegister
00308   * @{
00309   */
00310 #define LCD_RAM_REGISTER0               ((uint32_t)0x00000000) /*!< LCD RAM Register 0  */
00311 #define LCD_RAM_REGISTER1               ((uint32_t)0x00000001) /*!< LCD RAM Register 1  */
00312 #define LCD_RAM_REGISTER2               ((uint32_t)0x00000002) /*!< LCD RAM Register 2  */
00313 #define LCD_RAM_REGISTER3               ((uint32_t)0x00000003) /*!< LCD RAM Register 3  */
00314 #define LCD_RAM_REGISTER4               ((uint32_t)0x00000004) /*!< LCD RAM Register 4  */
00315 #define LCD_RAM_REGISTER5               ((uint32_t)0x00000005) /*!< LCD RAM Register 5  */
00316 #define LCD_RAM_REGISTER6               ((uint32_t)0x00000006) /*!< LCD RAM Register 6  */
00317 #define LCD_RAM_REGISTER7               ((uint32_t)0x00000007) /*!< LCD RAM Register 7  */
00318 #define LCD_RAM_REGISTER8               ((uint32_t)0x00000008) /*!< LCD RAM Register 8  */
00319 #define LCD_RAM_REGISTER9               ((uint32_t)0x00000009) /*!< LCD RAM Register 9  */
00320 #define LCD_RAM_REGISTER10              ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
00321 #define LCD_RAM_REGISTER11              ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
00322 #define LCD_RAM_REGISTER12              ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
00323 #define LCD_RAM_REGISTER13              ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
00324 #define LCD_RAM_REGISTER14              ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
00325 #define LCD_RAM_REGISTER15              ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup LCD_HighDrive LCD High Drive
00331   * @{
00332   */
00333
00334 #define LCD_HIGHDRIVE_DISABLE             ((uint32_t)0x00000000)        /*!< High drive disabled */
00335 #define LCD_HIGHDRIVE_ENABLE              (LCD_FCR_HD)                  /*!< High drive enabled  */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup LCD_MuxSegment LCD Mux Segment
00341   * @{
00342   */
00343
00344 #define LCD_MUXSEGMENT_DISABLE            ((uint32_t)0x00000000)        /*!< SEG pin multiplexing disabled */
00345 #define LCD_MUXSEGMENT_ENABLE             (LCD_CR_MUX_SEG)              /*!< SEG[31:28] are multiplexed with SEG[43:40]    */
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup LCD_Flag_Definition LCD Flags Definition
00351   * @{
00352   */
00353 #define LCD_FLAG_ENS                    LCD_SR_ENS   /*!< LCD enabled status */
00354 #define LCD_FLAG_SOF                    LCD_SR_SOF   /*!< Start of frame flag */
00355 #define LCD_FLAG_UDR                    LCD_SR_UDR   /*!< Update display request */
00356 #define LCD_FLAG_UDD                    LCD_SR_UDD   /*!< Update display done */
00357 #define LCD_FLAG_RDY                    LCD_SR_RDY   /*!< Ready flag */
00358 #define LCD_FLAG_FCRSF                  LCD_SR_FCRSR /*!< LCD Frame Control Register Synchronization flag */
00359 /**
00360   * @}
00361   */
00362
00363 /**
00364   * @}
00365   */
00366
00367 /* Exported macros -----------------------------------------------------------*/
00368 /** @defgroup LCD_Exported_Macros LCD Exported Macros
00369   * @{
00370   */
00371
00372 /** @brief Reset LCD handle state.
00373   * @param  __HANDLE__: specifies the LCD Handle.
00374   * @retval None
00375   */
00376 #define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
00377
00378 /** @brief  Enable the LCD peripheral.
00379   * @param  __HANDLE__: specifies the LCD Handle.
00380   * @retval None
00381   */
00382 #define __HAL_LCD_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
00383
00384 /** @brief  Disable the LCD peripheral.
00385   * @param  __HANDLE__: specifies the LCD Handle.
00386   * @retval None
00387   */
00388 #define __HAL_LCD_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
00389
00390 /** @brief  Enable the low resistance divider.
00391   * @param  __HANDLE__: specifies the LCD Handle.
00392   * @note   Displays with high internal resistance may need a longer drive time to
00393   *         achieve satisfactory contrast. This function is useful in this case if
00394   *         some additional power consumption can be tolerated.
00395   * @note   When this mode is enabled, the PulseOn Duration (PON) have to be
00396   *         programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
00397   * @retval None
00398   */
00399 #define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)                       \
00400                   do {                                                \
00401                     SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
00402                     LCD_WaitForSynchro(__HANDLE__);                   \
00403                   } while(0)
00404
00405 /** @brief  Disable the low resistance divider.
00406   * @param  __HANDLE__: specifies the LCD Handle.
00407   * @retval None
00408   */
00409 #define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)                        \
00410                   do {                                                  \
00411                     CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
00412                     LCD_WaitForSynchro(__HANDLE__);                     \
00413                   } while(0)
00414
00415 /** @brief  Enable the voltage output buffer for higher driving capability.
00416   * @param  __HANDLE__: specifies the LCD Handle.
00417   * @retval None
00418   */
00419 #define __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
00420
00421 /** @brief  Disable the voltage output buffer for higher driving capability.
00422   * @param  __HANDLE__: specifies the LCD Handle.
00423   * @retval None
00424   */
00425 #define __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
00426
00427 /**
00428   * @brief  Configure the LCD pulse on duration.
00429   * @param  __HANDLE__: specifies the LCD Handle.
00430   * @param  __DURATION__: specifies the LCD pulse on duration in terms of
00431   *         CK_PS (prescaled LCD clock period) pulses.
00432   *   This parameter can be one of the following values:
00433   *     @arg LCD_PULSEONDURATION_0: 0 pulse
00434   *     @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
00435   *     @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
00436   *     @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
00437   *     @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
00438   *     @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
00439   *     @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
00440   *     @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
00441   * @retval None
00442   */
00443 #define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)                        \
00444                   do {                                                                    \
00445                     MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
00446                     LCD_WaitForSynchro(__HANDLE__);                                       \
00447                   } while(0)
00448
00449 /**
00450   * @brief  Configure the LCD dead time.
00451   * @param  __HANDLE__: specifies the LCD Handle.
00452   * @param  __DEADTIME__: specifies the LCD dead time.
00453   *   This parameter can be one of the following values:
00454   *     @arg LCD_DEADTIME_0: No dead Time
00455   *     @arg LCD_DEADTIME_1: One Phase between different couple of Frame
00456   *     @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
00457   *     @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
00458   *     @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
00459   *     @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
00460   *     @arg LCD_DEADTIME_6: Six Phase between different couple of Frame
00461   *     @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
00462   * @retval None
00463   */
00464 #define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)                                \
00465                   do {                                                                     \
00466                     MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
00467                     LCD_WaitForSynchro(__HANDLE__);                                        \
00468                   } while(0)
00469
00470 /**
00471   * @brief  Configure the LCD contrast.
00472   * @param  __HANDLE__: specifies the LCD Handle.
00473   * @param  __CONTRAST__: specifies the LCD Contrast.
00474   *   This parameter can be one of the following values:
00475   *     @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
00476   *     @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
00477   *     @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
00478   *     @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
00479   *     @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
00480   *     @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
00481   *     @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
00482   *     @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
00483   * @retval None
00484   */
00485 #define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)                           \
00486               do {                                                                    \
00487                 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__));  \
00488                 LCD_WaitForSynchro(__HANDLE__);                                       \
00489               } while(0)
00490
00491 /**
00492   * @brief  Configure the LCD Blink mode and Blink frequency.
00493   * @param  __HANDLE__: specifies the LCD Handle.
00494   * @param  __BLINKMODE__: specifies the LCD blink mode.
00495   *   This parameter can be one of the following values:
00496   *     @arg LCD_BLINKMODE_OFF:           Blink disabled
00497   *     @arg LCD_BLINKMODE_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
00498   *     @arg LCD_BLINKMODE_SEG0_ALLCOM:   Blink enabled on SEG[0], all COM (up to 8
00499   *                                       pixels according to the programmed duty)
00500   *     @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM
00501   *                                       (all pixels)
00502   * @param  __BLINKFREQUENCY__: specifies the LCD blink frequency.
00503   *     @arg LCD_BLINKFREQUENCY_DIV8:    The Blink frequency = fLcd/8
00504   *     @arg LCD_BLINKFREQUENCY_DIV16:   The Blink frequency = fLcd/16
00505   *     @arg LCD_BLINKFREQUENCY_DIV32:   The Blink frequency = fLcd/32
00506   *     @arg LCD_BLINKFREQUENCY_DIV64:   The Blink frequency = fLcd/64
00507   *     @arg LCD_BLINKFREQUENCY_DIV128:  The Blink frequency = fLcd/128
00508   *     @arg LCD_BLINKFREQUENCY_DIV256:  The Blink frequency = fLcd/256
00509   *     @arg LCD_BLINKFREQUENCY_DIV512:  The Blink frequency = fLcd/512
00510   *     @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
00511   * @retval None
00512   */
00513 #define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)         \
00514               do {                                                                    \
00515                 MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
00516                 LCD_WaitForSynchro(__HANDLE__);                                       \
00517               } while(0)
00518
00519 /** @brief  Enable the specified LCD interrupt.
00520   * @param  __HANDLE__: specifies the LCD Handle.
00521   * @param  __INTERRUPT__: specifies the LCD interrupt source to be enabled.
00522   *          This parameter can be one of the following values:
00523   *     @arg LCD_IT_SOF: Start of Frame Interrupt
00524   *     @arg LCD_IT_UDD: Update Display Done Interrupt
00525   * @retval None
00526   */
00527 #define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)                      \
00528                   do {                                                      \
00529                     SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__));  \
00530                     LCD_WaitForSynchro(__HANDLE__);                         \
00531                   } while(0)
00532
00533 /** @brief  Disable the specified LCD interrupt.
00534   * @param  __HANDLE__: specifies the LCD Handle.
00535   * @param  __INTERRUPT__: specifies the LCD interrupt source to be disabled.
00536   *          This parameter can be one of the following values:
00537   *     @arg LCD_IT_SOF: Start of Frame Interrupt
00538   *     @arg LCD_IT_UDD: Update Display Done Interrupt
00539   * @retval None
00540   */
00541 #define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)                      \
00542                   do {                                                       \
00543                     CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
00544                     LCD_WaitForSynchro(__HANDLE__);                          \
00545                   } while(0)
00546
00547 /** @brief  Check whether the specified LCD interrupt source is enabled or not.
00548   * @param  __HANDLE__: specifies the LCD Handle.
00549   * @param  __IT__: specifies the LCD interrupt source to check.
00550   *        This parameter can be one of the following values:
00551   *        @arg LCD_IT_SOF: Start of Frame Interrupt
00552   *        @arg LCD_IT_UDD: Update Display Done Interrupt.
00553   * @note If the device is in STOP mode (PCLK not provided) UDD will not
00554   *          generate an interrupt even if UDDIE = 1.
00555   *          If the display is not enabled the UDD interrupt will never occur.
00556   * @retval The state of __IT__ (TRUE or FALSE).
00557   */
00558 #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
00559
00560 /** @brief  Check whether the specified LCD flag is set or not.
00561   * @param  __HANDLE__: specifies the LCD Handle.
00562   * @param  __FLAG__: specifies the flag to check.
00563   *        This parameter can be one of the following values:
00564   *        @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
00565   * @note  The ENS bit is set immediately when the LCDEN bit in the LCD_CR
00566   *             goes from 0 to 1. On deactivation it reflects the real status of
00567   *             LCD so it becomes 0 at the end of the last displayed frame.
00568   *        @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
00569   *             the beginning of a new frame, at the same time as the display data is
00570   *             updated.
00571   *        @arg LCD_FLAG_UDR: Update Display Request flag.
00572   *        @arg LCD_FLAG_UDD: Update Display Done flag.
00573   *        @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
00574   *             of the step-up converter.
00575   *        @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
00576   *             This flag is set by hardware each time the LCD_FCR register is updated
00577   *             in the LCDCLK domain.
00578   * @retval The new state of __FLAG__ (TRUE or FALSE).
00579   */
00580 #define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00581
00582 /** @brief  Clear the specified LCD pending flag.
00583   * @param  __HANDLE__: specifies the LCD Handle.
00584   * @param  __FLAG__: specifies the flag to clear.
00585   *        This parameter can be any combination of the following values:
00586   *        @arg LCD_FLAG_SOF: Start of Frame Interrupt
00587   *        @arg LCD_FLAG_UDD: Update Display Done Interrupt
00588   * @retval None
00589   */
00590 #define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__)  WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))
00591
00592 /**
00593   * @}
00594   */
00595
00596 /* Exported functions ------------------------------------------------------- */
00597 /** @addtogroup LCD_Exported_Functions
00598   * @{
00599   */
00600
00601 /* Initialization/de-initialization methods  **********************************/
00602 /** @addtogroup LCD_Exported_Functions_Group1
00603   * @{
00604   */
00605 HAL_StatusTypeDef    HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
00606 HAL_StatusTypeDef    HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
00607 void                 HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
00608 void                 HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
00609 /**
00610   * @}
00611   */
00612
00613 /* IO operation methods *******************************************************/
00614 /** @addtogroup LCD_Exported_Functions_Group2
00615   * @{
00616   */
00617 HAL_StatusTypeDef    HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
00618 HAL_StatusTypeDef    HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
00619 HAL_StatusTypeDef    HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
00620 /**
00621   * @}
00622   */
00623
00624 /* Peripheral State methods  **************************************************/
00625 /** @addtogroup LCD_Exported_Functions_Group3
00626   * @{
00627   */
00628 HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
00629 uint32_t             HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
00630 /**
00631   * @}
00632   */
00633
00634 /**
00635   * @}
00636   */
00637
00638 /* Private types -------------------------------------------------------------*/
00639 /* Private variables ---------------------------------------------------------*/
00640 /* Private constants ---------------------------------------------------------*/
00641 /* Private macros ------------------------------------------------------------*/
00642 /** @defgroup LCD_Private_Macros LCD Private Macros
00643   * @{
00644   */
00645
00646 #define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1)     || \
00647                                          ((__PRESCALER__) == LCD_PRESCALER_2)     || \
00648                                          ((__PRESCALER__) == LCD_PRESCALER_4)     || \
00649                                          ((__PRESCALER__) == LCD_PRESCALER_8)     || \
00650                                          ((__PRESCALER__) == LCD_PRESCALER_16)    || \
00651                                          ((__PRESCALER__) == LCD_PRESCALER_32)    || \
00652                                          ((__PRESCALER__) == LCD_PRESCALER_64)    || \
00653                                          ((__PRESCALER__) == LCD_PRESCALER_128)   || \
00654                                          ((__PRESCALER__) == LCD_PRESCALER_256)   || \
00655                                          ((__PRESCALER__) == LCD_PRESCALER_512)   || \
00656                                          ((__PRESCALER__) == LCD_PRESCALER_1024)  || \
00657                                          ((__PRESCALER__) == LCD_PRESCALER_2048)  || \
00658                                          ((__PRESCALER__) == LCD_PRESCALER_4096)  || \
00659                                          ((__PRESCALER__) == LCD_PRESCALER_8192)  || \
00660                                          ((__PRESCALER__) == LCD_PRESCALER_16384) || \
00661                                          ((__PRESCALER__) == LCD_PRESCALER_32768))
00662
00663 #define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
00664                                      ((__DIVIDER__) == LCD_DIVIDER_17) || \
00665                                      ((__DIVIDER__) == LCD_DIVIDER_18) || \
00666                                      ((__DIVIDER__) == LCD_DIVIDER_19) || \
00667                                      ((__DIVIDER__) == LCD_DIVIDER_20) || \
00668                                      ((__DIVIDER__) == LCD_DIVIDER_21) || \
00669                                      ((__DIVIDER__) == LCD_DIVIDER_22) || \
00670                                      ((__DIVIDER__) == LCD_DIVIDER_23) || \
00671                                      ((__DIVIDER__) == LCD_DIVIDER_24) || \
00672                                      ((__DIVIDER__) == LCD_DIVIDER_25) || \
00673                                      ((__DIVIDER__) == LCD_DIVIDER_26) || \
00674                                      ((__DIVIDER__) == LCD_DIVIDER_27) || \
00675                                      ((__DIVIDER__) == LCD_DIVIDER_28) || \
00676                                      ((__DIVIDER__) == LCD_DIVIDER_29) || \
00677                                      ((__DIVIDER__) == LCD_DIVIDER_30) || \
00678                                      ((__DIVIDER__) == LCD_DIVIDER_31))
00679
00680 #define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC)  || \
00681                                ((__DUTY__) == LCD_DUTY_1_2)     || \
00682                                ((__DUTY__) == LCD_DUTY_1_3)     || \
00683                                ((__DUTY__) == LCD_DUTY_1_4)     || \
00684                                ((__DUTY__) == LCD_DUTY_1_8))
00685
00686 #define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
00687                                ((__BIAS__) == LCD_BIAS_1_2) || \
00688                                ((__BIAS__) == LCD_BIAS_1_3))
00689
00690 #define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
00691                                        ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
00692
00693
00694 #define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
00695                                                 ((__DURATION__) == LCD_PULSEONDURATION_1) || \
00696                                                 ((__DURATION__) == LCD_PULSEONDURATION_2) || \
00697                                                 ((__DURATION__) == LCD_PULSEONDURATION_3) || \
00698                                                 ((__DURATION__) == LCD_PULSEONDURATION_4) || \
00699                                                 ((__DURATION__) == LCD_PULSEONDURATION_5) || \
00700                                                 ((__DURATION__) == LCD_PULSEONDURATION_6) || \
00701                                                 ((__DURATION__) == LCD_PULSEONDURATION_7))
00702
00703 #define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
00704                                     ((__TIME__) == LCD_DEADTIME_1) || \
00705                                     ((__TIME__) == LCD_DEADTIME_2) || \
00706                                     ((__TIME__) == LCD_DEADTIME_3) || \
00707                                     ((__TIME__) == LCD_DEADTIME_4) || \
00708                                     ((__TIME__) == LCD_DEADTIME_5) || \
00709                                     ((__TIME__) == LCD_DEADTIME_6) || \
00710                                     ((__TIME__) == LCD_DEADTIME_7))
00711
00712 #define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF)            || \
00713                                      ((__MODE__) == LCD_BLINKMODE_SEG0_COM0)      || \
00714                                      ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM)    || \
00715                                      ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
00716
00717 #define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8)   || \
00718                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16)  || \
00719                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32)  || \
00720                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64)  || \
00721                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
00722                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
00723                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
00724                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
00725
00726 #define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
00727                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
00728                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
00729                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
00730                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
00731                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
00732                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
00733                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
00734
00735 #define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0)  || \
00736                                            ((__REGISTER__) == LCD_RAM_REGISTER1)  || \
00737                                            ((__REGISTER__) == LCD_RAM_REGISTER2)  || \
00738                                            ((__REGISTER__) == LCD_RAM_REGISTER3)  || \
00739                                            ((__REGISTER__) == LCD_RAM_REGISTER4)  || \
00740                                            ((__REGISTER__) == LCD_RAM_REGISTER5)  || \
00741                                            ((__REGISTER__) == LCD_RAM_REGISTER6)  || \
00742                                            ((__REGISTER__) == LCD_RAM_REGISTER7)  || \
00743                                            ((__REGISTER__) == LCD_RAM_REGISTER8)  || \
00744                                            ((__REGISTER__) == LCD_RAM_REGISTER9)  || \
00745                                            ((__REGISTER__) == LCD_RAM_REGISTER10) || \
00746                                            ((__REGISTER__) == LCD_RAM_REGISTER11) || \
00747                                            ((__REGISTER__) == LCD_RAM_REGISTER12) || \
00748                                            ((__REGISTER__) == LCD_RAM_REGISTER13) || \
00749                                            ((__REGISTER__) == LCD_RAM_REGISTER14) || \
00750                                            ((__REGISTER__) == LCD_RAM_REGISTER15))
00751
00752 #define IS_LCD_HIGH_DRIVE(__VALUE__) (((__VALUE__) == LCD_HIGHDRIVE_DISABLE) || \
00753                                       ((__VALUE__) == LCD_HIGHDRIVE_ENABLE))
00754
00755 #define IS_LCD_MUX_SEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
00756                                        ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
00757
00758 /**
00759   * @}
00760   */
00761
00762 /* Private functions ---------------------------------------------------------*/
00763 /** @addtogroup LCD_Private_Functions
00764   * @{
00765   */
00766
00767 HAL_StatusTypeDef     LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
00768
00769 /**
00770   * @}
00771   */
00772
00773 /**
00774   * @}
00775   */
00776
00777 /**
00778   * @}
00779   */
00780
00781 #endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx */
00782
00783 #ifdef __cplusplus
00784 }
00785 #endif
00786
00787 #endif /* __STM32L4xx_HAL_LCD_H */
00788
00789 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_lptim.c Source File

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stm32l4xx_hal_lptim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_lptim.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   LPTIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Low Power Timer (LPTIM) peripheral:
00010   *           + Initialization and de-initialization functions.
00011   *           + Start/Stop operation functions in polling mode.
00012   *           + Start/Stop operation functions in interrupt mode.
00013   *           + Reading operation functions.
00014   *           + Peripheral State functions.
00015   *
00016   @verbatim
00017   ==============================================================================
00018                      ##### How to use this driver #####
00019   ==============================================================================
00020     [..]
00021       The LPTIM HAL driver can be used as follows:
00022
00023       (#)Initialize the LPTIM low level resources by implementing the
00024         HAL_LPTIM_MspInit():
00025          (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
00026          (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
00027              (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
00028              (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
00029              (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
00030
00031       (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
00032          configures mainly:
00033          (++) The instance: LPTIM1 or LPTIM2.
00034          (++) Clock: the counter clock.
00035              (+++) Source   : it can be either the ULPTIM input (IN1) or one of
00036                               the internal clock; (APB, LSE, LSI or MSI).
00037              (+++) Prescaler: select the clock divider.
00038          (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
00039                as counter clock source.
00040              (+++) Polarity:   polarity of the active edge for the counter unit
00041                                if the ULPTIM input is selected.
00042              (+++) SampleTime: clock sampling time to configure the clock glitch
00043                                filter.
00044          (++) Trigger: How the counter start.
00045              (+++) Source: trigger can be software or one of the hardware triggers.
00046              (+++) ActiveEdge : only for hardware trigger.
00047              (+++) SampleTime : trigger sampling time to configure the trigger
00048                                 glitch filter.
00049          (++) OutputPolarity : 2 opposite polarities are possible.
00050          (++) UpdateMode: specifies whether the update of the autoreload and
00051               the compare values is done immediately or after the end of current
00052               period.
00053          (++) Input1Source: Source selected for input1 (GPIO or comparator output).
00054          (++) Input2Source: Source selected for input2 (GPIO or comparator output).
00055               Input2 is used only for encoder feature so is used only for LPTIM1 instance.
00056
00057       (#)Six modes are available:
00058
00059          (++) PWM Mode: To generate a PWM signal with specified period and pulse,
00060          call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
00061          mode.
00062
00063          (++) One Pulse Mode: To generate pulse with specified width in response
00064          to a stimulus, call HAL_LPTIM_OnePulse_Start() or
00065          HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
00066
00067          (++) Set once Mode: In this mode, the output changes the level (from
00068          low level to high level if the output polarity is configured high, else
00069          the opposite) when a compare match occurs. To start this mode, call
00070          HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
00071          interruption mode.
00072
00073          (++) Encoder Mode: To use the encoder interface call
00074          HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
00075          interruption mode. Only available for LPTIM1 instance.
00076
00077          (++) Time out Mode: an active edge on one selected trigger input rests
00078          the counter. The first trigger event will start the timer, any
00079          successive trigger event will reset the counter and the timer will
00080          restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
00081          HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
00082
00083          (++) Counter Mode: counter can be used to count external events on
00084          the LPTIM Input1 or it can be used to count internal clock cycles.
00085          To start this mode, call HAL_LPTIM_Counter_Start() or
00086          HAL_LPTIM_Counter_Start_IT() for interruption mode.
00087
00088
00089       (#) User can stop any process by calling the corresponding API:
00090           HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
00091           already started in interruption mode.
00092
00093       (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
00094
00095   @endverbatim
00096   ******************************************************************************
00097   * @attention
00098   *
00099   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00100   *
00101   * Redistribution and use in source and binary forms, with or without modification,
00102   * are permitted provided that the following conditions are met:
00103   *   1. Redistributions of source code must retain the above copyright notice,
00104   *      this list of conditions and the following disclaimer.
00105   *   2. Redistributions in binary form must reproduce the above copyright notice,
00106   *      this list of conditions and the following disclaimer in the documentation
00107   *      and/or other materials provided with the distribution.
00108   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00109   *      may be used to endorse or promote products derived from this software
00110   *      without specific prior written permission.
00111   *
00112   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00113   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00114   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00115   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00116   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00117   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00118   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00119   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00120   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00121   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00122   *
00123   ******************************************************************************
00124   */
00125
00126 /* Includes ------------------------------------------------------------------*/
00127 #include "stm32l4xx_hal.h"
00128
00129 /** @addtogroup STM32L4xx_HAL_Driver
00130   * @{
00131   */
00132
00133 /** @defgroup LPTIM LPTIM
00134   * @brief LPTIM HAL module driver.
00135   * @{
00136   */
00137
00138 #ifdef HAL_LPTIM_MODULE_ENABLED
00139 /* Private typedef -----------------------------------------------------------*/
00140 /* Private define ------------------------------------------------------------*/
00141 /* Private macro -------------------------------------------------------------*/
00142 /* Private variables ---------------------------------------------------------*/
00143 /* Private function prototypes -----------------------------------------------*/
00144 /* Exported functions --------------------------------------------------------*/
00145
00146 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
00151  *  @brief    Initialization and Configuration functions.
00152  *
00153 @verbatim
00154   ==============================================================================
00155               ##### Initialization and de-initialization functions #####
00156   ==============================================================================
00157     [..]  This section provides functions allowing to:
00158       (+) Initialize the LPTIM according to the specified parameters in the
00159           LPTIM_InitTypeDef and initialize the associated handle.
00160       (+) DeInitialize the LPTIM peripheral.
00161       (+) Initialize the LPTIM MSP.
00162       (+) DeInitialize the LPTIM MSP.
00163
00164 @endverbatim
00165   * @{
00166   */
00167
00168 /**
00169   * @brief  Initialize the LPTIM according to the specified parameters in the
00170   *         LPTIM_InitTypeDef and initialize the associated handle.
00171   * @param  hlptim: LPTIM handle
00172   * @retval HAL status
00173   */
00174 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
00175 {
00176   uint32_t tmpcfgr = 0;
00177
00178   /* Check the LPTIM handle allocation */
00179   if(hlptim == NULL)
00180   {
00181     return HAL_ERROR;
00182   }
00183
00184   /* Check the parameters */
00185   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00186
00187   assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
00188   assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
00189   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00190   {
00191     assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00192     assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
00193   }
00194   assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
00195   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00196   {
00197     assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
00198     assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
00199   }
00200   assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
00201   assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
00202   assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
00203
00204   if(hlptim->State == HAL_LPTIM_STATE_RESET)
00205   {
00206     /* Allocate lock resource and initialize it */
00207     hlptim->Lock = HAL_UNLOCKED;
00208
00209     /* Init the low level hardware */
00210     HAL_LPTIM_MspInit(hlptim);
00211   }
00212
00213   /* Change the LPTIM state */
00214   hlptim->State = HAL_LPTIM_STATE_BUSY;
00215
00216   /* Get the LPTIMx CFGR value */
00217   tmpcfgr = hlptim->Instance->CFGR;
00218
00219   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00220   {
00221     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
00222   }
00223   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00224   {
00225     tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
00226   }
00227
00228   /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
00229   tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
00230                           LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
00231
00232   /* Set initialization parameters */
00233   tmpcfgr |= (hlptim->Init.Clock.Source    |
00234               hlptim->Init.Clock.Prescaler |
00235               hlptim->Init.OutputPolarity  |
00236               hlptim->Init.UpdateMode      |
00237               hlptim->Init.CounterSource);
00238
00239   if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
00240   {
00241     tmpcfgr |=  (hlptim->Init.UltraLowPowerClock.Polarity |
00242                 hlptim->Init.UltraLowPowerClock.SampleTime);
00243   }
00244
00245   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00246   {
00247     /* Enable External trigger and set the trigger source */
00248     tmpcfgr |= (hlptim->Init.Trigger.Source     |
00249                 hlptim->Init.Trigger.ActiveEdge |
00250                 hlptim->Init.Trigger.SampleTime);
00251   }
00252
00253   /* Write to LPTIMx CFGR */
00254   hlptim->Instance->CFGR = tmpcfgr;
00255
00256   /* Configure LPTIM input sources */
00257   if(hlptim->Instance == LPTIM1)
00258   {
00259     /* Check LPTIM1 Input1 and Input2 sources */
00260     assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source));
00261     assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance,hlptim->Init.Input2Source));
00262
00263     /* Configure LPTIM1 Input1 and Input2 sources */
00264     hlptim->Instance->OR = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
00265   }
00266   else
00267   {
00268     /* Check LPTIM2 Input1 source */
00269     assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source));
00270
00271     /* Configure LPTIM2 Input1 source */
00272     hlptim->Instance->OR = hlptim->Init.Input1Source;
00273   }
00274
00275   /* Change the LPTIM state */
00276   hlptim->State = HAL_LPTIM_STATE_READY;
00277
00278   /* Return function status */
00279   return HAL_OK;
00280 }
00281
00282 /**
00283   * @brief  DeInitialize the LPTIM peripheral.
00284   * @param  hlptim: LPTIM handle
00285   * @retval HAL status
00286   */
00287 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
00288 {
00289   /* Check the LPTIM handle allocation */
00290   if(hlptim == NULL)
00291   {
00292     return HAL_ERROR;
00293   }
00294
00295   /* Change the LPTIM state */
00296   hlptim->State = HAL_LPTIM_STATE_BUSY;
00297
00298   /* Disable the LPTIM Peripheral Clock */
00299   __HAL_LPTIM_DISABLE(hlptim);
00300
00301   /* DeInit the low level hardware: CLOCK, NVIC.*/
00302   HAL_LPTIM_MspDeInit(hlptim);
00303
00304   /* Change the LPTIM state */
00305   hlptim->State = HAL_LPTIM_STATE_RESET;
00306
00307   /* Release Lock */
00308   __HAL_UNLOCK(hlptim);
00309
00310   /* Return function status */
00311   return HAL_OK;
00312 }
00313
00314 /**
00315   * @brief  Initialize the LPTIM MSP.
00316   * @param  hlptim: LPTIM handle
00317   * @retval None
00318   */
00319 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
00320 {
00321   /* Prevent unused argument(s) compilation warning */
00322   UNUSED(hlptim);
00323
00324   /* NOTE : This function should not be modified, when the callback is needed,
00325             the HAL_LPTIM_MspInit could be implemented in the user file
00326    */
00327 }
00328
00329 /**
00330   * @brief  DeInitialize LPTIM MSP.
00331   * @param  hlptim: LPTIM handle
00332   * @retval None
00333   */
00334 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
00335 {
00336   /* Prevent unused argument(s) compilation warning */
00337   UNUSED(hlptim);
00338
00339   /* NOTE : This function should not be modified, when the callback is needed,
00340             the HAL_LPTIM_MspDeInit could be implemented in the user file
00341    */
00342 }
00343
00344 /**
00345   * @}
00346   */
00347
00348 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
00349  *  @brief   Start-Stop operation functions.
00350  *
00351 @verbatim
00352   ==============================================================================
00353                 ##### LPTIM Start Stop operation functions #####
00354   ==============================================================================
00355     [..]  This section provides functions allowing to:
00356       (+) Start the PWM mode.
00357       (+) Stop the PWM mode.
00358       (+) Start the One pulse mode.
00359       (+) Stop the One pulse mode.
00360       (+) Start the Set once mode.
00361       (+) Stop the Set once mode.
00362       (+) Start the Encoder mode.
00363       (+) Stop the Encoder mode.
00364       (+) Start the Timeout mode.
00365       (+) Stop the Timeout mode.
00366       (+) Start the Counter mode.
00367       (+) Stop the Counter mode.
00368
00369
00370 @endverbatim
00371   * @{
00372   */
00373
00374 /**
00375   * @brief  Start the LPTIM PWM generation.
00376   * @param  hlptim : LPTIM handle
00377   * @param  Period : Specifies the Autoreload value.
00378   *         This parameter must be a value between 0x0000 and 0xFFFF.
00379   * @param  Pulse : Specifies the compare value.
00380   *         This parameter must be a value between 0x0000 and 0xFFFF.
00381   * @retval HAL status
00382   */
00383 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00384 {
00385   /* Check the parameters */
00386   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00387   assert_param(IS_LPTIM_PERIOD(Period));
00388   assert_param(IS_LPTIM_PULSE(Pulse));
00389
00390   /* Set the LPTIM state */
00391   hlptim->State= HAL_LPTIM_STATE_BUSY;
00392
00393   /* Reset WAVE bit to set PWM mode */
00394   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00395
00396   /* Enable the Peripheral */
00397   __HAL_LPTIM_ENABLE(hlptim);
00398
00399   /* Load the period value in the autoreload register */
00400   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00401
00402   /* Load the pulse value in the compare register */
00403   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00404
00405   /* Start timer in continuous mode */
00406   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00407
00408   /* Change the TIM state*/
00409   hlptim->State= HAL_LPTIM_STATE_READY;
00410
00411   /* Return function status */
00412   return HAL_OK;
00413 }
00414
00415 /**
00416   * @brief  Stop the LPTIM PWM generation.
00417   * @param  hlptim : LPTIM handle
00418   * @retval HAL status
00419   */
00420 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
00421 {
00422   /* Check the parameters */
00423   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00424
00425   /* Set the LPTIM state */
00426   hlptim->State= HAL_LPTIM_STATE_BUSY;
00427
00428   /* Disable the Peripheral */
00429   __HAL_LPTIM_DISABLE(hlptim);
00430
00431   /* Change the TIM state*/
00432   hlptim->State= HAL_LPTIM_STATE_READY;
00433
00434   /* Return function status */
00435   return HAL_OK;
00436 }
00437
00438 /**
00439   * @brief  Start the LPTIM PWM generation in interrupt mode.
00440   * @param  hlptim : LPTIM handle
00441   * @param  Period : Specifies the Autoreload value.
00442   *         This parameter must be a value between 0x0000 and 0xFFFF
00443   * @param  Pulse : Specifies the compare value.
00444   *         This parameter must be a value between 0x0000 and 0xFFFF
00445   * @retval HAL status
00446   */
00447 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00448 {
00449   /* Check the parameters */
00450   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00451   assert_param(IS_LPTIM_PERIOD(Period));
00452   assert_param(IS_LPTIM_PULSE(Pulse));
00453
00454   /* Set the LPTIM state */
00455   hlptim->State= HAL_LPTIM_STATE_BUSY;
00456
00457   /* Reset WAVE bit to set PWM mode */
00458   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00459
00460   /* Enable Autoreload write complete interrupt */
00461   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00462
00463   /* Enable Compare write complete interrupt */
00464   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00465
00466   /* Enable Autoreload match interrupt */
00467   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00468
00469   /* Enable Compare match interrupt */
00470   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00471
00472   /* If external trigger source is used, then enable external trigger interrupt */
00473   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00474   {
00475     /* Enable external trigger interrupt */
00476     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00477   }
00478
00479   /* Enable the Peripheral */
00480   __HAL_LPTIM_ENABLE(hlptim);
00481
00482   /* Load the period value in the autoreload register */
00483   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00484
00485   /* Load the pulse value in the compare register */
00486   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00487
00488   /* Start timer in continuous mode */
00489   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00490
00491   /* Change the TIM state*/
00492   hlptim->State= HAL_LPTIM_STATE_READY;
00493
00494   /* Return function status */
00495   return HAL_OK;
00496 }
00497
00498 /**
00499   * @brief  Stop the LPTIM PWM generation in interrupt mode.
00500   * @param  hlptim : LPTIM handle
00501   * @retval HAL status
00502   */
00503 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00504 {
00505   /* Check the parameters */
00506   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00507
00508   /* Set the LPTIM state */
00509   hlptim->State= HAL_LPTIM_STATE_BUSY;
00510
00511   /* Disable the Peripheral */
00512   __HAL_LPTIM_DISABLE(hlptim);
00513
00514     /* Disable Autoreload write complete interrupt */
00515   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00516
00517   /* Disable Compare write complete interrupt */
00518   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00519
00520   /* Disable Autoreload match interrupt */
00521   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00522
00523   /* Disable Compare match interrupt */
00524   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00525
00526   /* If external trigger source is used, then disable external trigger interrupt */
00527   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00528   {
00529     /* Disable external trigger interrupt */
00530     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00531   }
00532
00533   /* Change the TIM state*/
00534   hlptim->State= HAL_LPTIM_STATE_READY;
00535
00536   /* Return function status */
00537   return HAL_OK;
00538 }
00539
00540 /**
00541   * @brief  Start the LPTIM One pulse generation.
00542   * @param  hlptim : LPTIM handle
00543   * @param  Period : Specifies the Autoreload value.
00544   *         This parameter must be a value between 0x0000 and 0xFFFF.
00545   * @param  Pulse : Specifies the compare value.
00546   *         This parameter must be a value between 0x0000 and 0xFFFF.
00547   * @retval HAL status
00548   */
00549 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00550 {
00551   /* Check the parameters */
00552   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00553   assert_param(IS_LPTIM_PERIOD(Period));
00554   assert_param(IS_LPTIM_PULSE(Pulse));
00555
00556   /* Set the LPTIM state */
00557   hlptim->State= HAL_LPTIM_STATE_BUSY;
00558
00559   /* Reset WAVE bit to set one pulse mode */
00560   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00561
00562   /* Enable the Peripheral */
00563   __HAL_LPTIM_ENABLE(hlptim);
00564
00565   /* Load the period value in the autoreload register */
00566   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00567
00568   /* Load the pulse value in the compare register */
00569   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00570
00571   /* Start timer in continuous mode */
00572   __HAL_LPTIM_START_SINGLE(hlptim);
00573
00574   /* Change the TIM state*/
00575   hlptim->State= HAL_LPTIM_STATE_READY;
00576
00577   /* Return function status */
00578   return HAL_OK;
00579 }
00580
00581 /**
00582   * @brief  Stop the LPTIM One pulse generation.
00583   * @param  hlptim : LPTIM handle
00584   * @retval HAL status
00585   */
00586 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
00587 {
00588   /* Check the parameters */
00589   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00590
00591   /* Set the LPTIM state */
00592   hlptim->State= HAL_LPTIM_STATE_BUSY;
00593
00594   /* Disable the Peripheral */
00595   __HAL_LPTIM_DISABLE(hlptim);
00596
00597   /* Change the TIM state*/
00598   hlptim->State= HAL_LPTIM_STATE_READY;
00599
00600   /* Return function status */
00601   return HAL_OK;
00602 }
00603
00604 /**
00605   * @brief  Start the LPTIM One pulse generation in interrupt mode.
00606   * @param  hlptim : LPTIM handle
00607   * @param  Period : Specifies the Autoreload value.
00608   *         This parameter must be a value between 0x0000 and 0xFFFF.
00609   * @param  Pulse : Specifies the compare value.
00610   *         This parameter must be a value between 0x0000 and 0xFFFF.
00611   * @retval HAL status
00612   */
00613 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00614 {
00615   /* Check the parameters */
00616   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00617   assert_param(IS_LPTIM_PERIOD(Period));
00618   assert_param(IS_LPTIM_PULSE(Pulse));
00619
00620   /* Set the LPTIM state */
00621   hlptim->State= HAL_LPTIM_STATE_BUSY;
00622
00623   /* Reset WAVE bit to set one pulse mode */
00624   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00625
00626   /* Enable Autoreload write complete interrupt */
00627   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00628
00629   /* Enable Compare write complete interrupt */
00630   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00631
00632   /* Enable Autoreload match interrupt */
00633   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00634
00635   /* Enable Compare match interrupt */
00636   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00637
00638   /* If external trigger source is used, then enable external trigger interrupt */
00639   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00640   {
00641     /* Enable external trigger interrupt */
00642     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00643   }
00644
00645   /* Enable the Peripheral */
00646   __HAL_LPTIM_ENABLE(hlptim);
00647
00648   /* Load the period value in the autoreload register */
00649   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00650
00651   /* Load the pulse value in the compare register */
00652   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00653
00654   /* Start timer in continuous mode */
00655   __HAL_LPTIM_START_SINGLE(hlptim);
00656
00657   /* Change the TIM state*/
00658   hlptim->State= HAL_LPTIM_STATE_READY;
00659
00660   /* Return function status */
00661   return HAL_OK;
00662 }
00663
00664 /**
00665   * @brief  Stop the LPTIM One pulse generation in interrupt mode.
00666   * @param  hlptim : LPTIM handle
00667   * @retval HAL status
00668   */
00669 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00670 {
00671   /* Check the parameters */
00672   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00673
00674   /* Set the LPTIM state */
00675   hlptim->State= HAL_LPTIM_STATE_BUSY;
00676
00677   /* Disable the Peripheral */
00678   __HAL_LPTIM_DISABLE(hlptim);
00679
00680   /* Disable Autoreload write complete interrupt */
00681   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00682
00683   /* Disable Compare write complete interrupt */
00684   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00685
00686   /* Disable Autoreload match interrupt */
00687   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00688
00689   /* Disable Compare match interrupt */
00690   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00691
00692   /* If external trigger source is used, then disable external trigger interrupt */
00693   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00694   {
00695     /* Disable external trigger interrupt */
00696     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00697   }
00698
00699   /* Change the TIM state*/
00700   hlptim->State= HAL_LPTIM_STATE_READY;
00701
00702   /* Return function status */
00703   return HAL_OK;
00704 }
00705
00706 /**
00707   * @brief  Start the LPTIM in Set once mode.
00708   * @param  hlptim : LPTIM handle
00709   * @param  Period : Specifies the Autoreload value.
00710   *         This parameter must be a value between 0x0000 and 0xFFFF.
00711   * @param  Pulse : Specifies the compare value.
00712   *         This parameter must be a value between 0x0000 and 0xFFFF.
00713   * @retval HAL status
00714   */
00715 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00716 {
00717   /* Check the parameters */
00718   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00719   assert_param(IS_LPTIM_PERIOD(Period));
00720   assert_param(IS_LPTIM_PULSE(Pulse));
00721
00722   /* Set the LPTIM state */
00723   hlptim->State= HAL_LPTIM_STATE_BUSY;
00724
00725   /* Set WAVE bit to enable the set once mode */
00726   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00727
00728   /* Enable the Peripheral */
00729   __HAL_LPTIM_ENABLE(hlptim);
00730
00731   /* Load the period value in the autoreload register */
00732   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00733
00734   /* Load the pulse value in the compare register */
00735   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00736
00737   /* Start timer in continuous mode */
00738   __HAL_LPTIM_START_SINGLE(hlptim);
00739
00740   /* Change the TIM state*/
00741   hlptim->State= HAL_LPTIM_STATE_READY;
00742
00743   /* Return function status */
00744   return HAL_OK;
00745 }
00746
00747 /**
00748   * @brief  Stop the LPTIM Set once mode.
00749   * @param  hlptim : LPTIM handle
00750   * @retval HAL status
00751   */
00752 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
00753 {
00754   /* Check the parameters */
00755   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00756
00757   /* Set the LPTIM state */
00758   hlptim->State= HAL_LPTIM_STATE_BUSY;
00759
00760   /* Disable the Peripheral */
00761   __HAL_LPTIM_DISABLE(hlptim);
00762
00763   /* Change the TIM state*/
00764   hlptim->State= HAL_LPTIM_STATE_READY;
00765
00766   /* Return function status */
00767   return HAL_OK;
00768 }
00769
00770 /**
00771   * @brief  Start the LPTIM Set once mode in interrupt mode.
00772   * @param  hlptim : LPTIM handle
00773   * @param  Period : Specifies the Autoreload value.
00774   *         This parameter must be a value between 0x0000 and 0xFFFF.
00775   * @param  Pulse : Specifies the compare value.
00776   *         This parameter must be a value between 0x0000 and 0xFFFF.
00777   * @retval HAL status
00778   */
00779 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00780 {
00781   /* Check the parameters */
00782   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00783   assert_param(IS_LPTIM_PERIOD(Period));
00784   assert_param(IS_LPTIM_PULSE(Pulse));
00785
00786   /* Set the LPTIM state */
00787   hlptim->State= HAL_LPTIM_STATE_BUSY;
00788
00789   /* Set WAVE bit to enable the set once mode */
00790   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00791
00792   /* Enable Autoreload write complete interrupt */
00793   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00794
00795   /* Enable Compare write complete interrupt */
00796   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00797
00798   /* Enable Autoreload match interrupt */
00799   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00800
00801   /* Enable Compare match interrupt */
00802   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00803
00804   /* If external trigger source is used, then enable external trigger interrupt */
00805   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00806   {
00807     /* Enable external trigger interrupt */
00808     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00809   }
00810
00811   /* Enable the Peripheral */
00812   __HAL_LPTIM_ENABLE(hlptim);
00813
00814   /* Load the period value in the autoreload register */
00815   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00816
00817   /* Load the pulse value in the compare register */
00818   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00819
00820   /* Start timer in continuous mode */
00821   __HAL_LPTIM_START_SINGLE(hlptim);
00822
00823   /* Change the TIM state*/
00824   hlptim->State= HAL_LPTIM_STATE_READY;
00825
00826   /* Return function status */
00827   return HAL_OK;
00828 }
00829
00830 /**
00831   * @brief  Stop the LPTIM Set once mode in interrupt mode.
00832   * @param  hlptim : LPTIM handle
00833   * @retval HAL status
00834   */
00835 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00836 {
00837   /* Check the parameters */
00838   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00839
00840   /* Set the LPTIM state */
00841   hlptim->State= HAL_LPTIM_STATE_BUSY;
00842
00843   /* Disable the Peripheral */
00844   __HAL_LPTIM_DISABLE(hlptim);
00845
00846   /* Disable Autoreload write complete interrupt */
00847   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00848
00849   /* Disable Compare write complete interrupt */
00850   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00851
00852   /* Disable Autoreload match interrupt */
00853   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00854
00855   /* Disable Compare match interrupt */
00856   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00857
00858   /* If external trigger source is used, then disable external trigger interrupt */
00859   if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
00860   {
00861     /* Disable external trigger interrupt */
00862     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00863   }
00864
00865   /* Change the TIM state*/
00866   hlptim->State= HAL_LPTIM_STATE_READY;
00867
00868   /* Return function status */
00869   return HAL_OK;
00870 }
00871
00872 /**
00873   * @brief  Start the Encoder interface.
00874   * @param  hlptim : LPTIM handle
00875   * @param  Period : Specifies the Autoreload value.
00876   *         This parameter must be a value between 0x0000 and 0xFFFF.
00877   * @retval HAL status
00878   */
00879 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
00880 {
00881   HAL_StatusTypeDef status = HAL_OK;
00882   uint32_t          tmpcfgr;
00883
00884   /* Check the parameters */
00885   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00886   assert_param(IS_LPTIM_PERIOD(Period));
00887   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
00888   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
00889   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00890
00891   /* Encoder feature is only available for LPTIM1 instance */
00892   if (hlptim->Instance == LPTIM1)
00893   {
00894     /* Set the LPTIM state */
00895     hlptim->State= HAL_LPTIM_STATE_BUSY;
00896
00897     /* Get the LPTIMx CFGR value */
00898     tmpcfgr = hlptim->Instance->CFGR;
00899
00900     /* Clear CKPOL bits */
00901     tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
00902
00903     /* Set Input polarity */
00904     tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
00905
00906     /* Write to LPTIMx CFGR */
00907     hlptim->Instance->CFGR = tmpcfgr;
00908
00909     /* Set ENC bit to enable the encoder interface */
00910     hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
00911
00912     /* Enable the Peripheral */
00913     __HAL_LPTIM_ENABLE(hlptim);
00914
00915     /* Load the period value in the autoreload register */
00916     __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00917
00918     /* Start timer in continuous mode */
00919     __HAL_LPTIM_START_CONTINUOUS(hlptim);
00920
00921     /* Change the TIM state*/
00922     hlptim->State= HAL_LPTIM_STATE_READY;
00923   }
00924   else
00925   {
00926     status = HAL_ERROR;
00927   }
00928
00929   /* Return function status */
00930   return status;
00931 }
00932
00933 /**
00934   * @brief  Stop the Encoder interface.
00935   * @param  hlptim : LPTIM handle
00936   * @retval HAL status
00937   */
00938 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
00939 {
00940   /* Check the parameters */
00941   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00942
00943   /* Set the LPTIM state */
00944   hlptim->State= HAL_LPTIM_STATE_BUSY;
00945
00946   /* Disable the Peripheral */
00947   __HAL_LPTIM_DISABLE(hlptim);
00948
00949   /* Reset ENC bit to disable the encoder interface */
00950   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
00951
00952   /* Change the TIM state*/
00953   hlptim->State= HAL_LPTIM_STATE_READY;
00954
00955   /* Return function status */
00956   return HAL_OK;
00957 }
00958
00959 /**
00960   * @brief  Start the Encoder interface in interrupt mode.
00961   * @param  hlptim : LPTIM handle
00962   * @param  Period : Specifies the Autoreload value.
00963   *         This parameter must be a value between 0x0000 and 0xFFFF.
00964   * @retval HAL status
00965   */
00966 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
00967 {
00968   HAL_StatusTypeDef status = HAL_OK;
00969   uint32_t          tmpcfgr;
00970
00971   /* Check the parameters */
00972   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00973   assert_param(IS_LPTIM_PERIOD(Period));
00974   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
00975   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
00976   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00977
00978   /* Encoder feature is only available for LPTIM1 instance */
00979   if (hlptim->Instance == LPTIM1)
00980   {
00981     /* Set the LPTIM state */
00982     hlptim->State= HAL_LPTIM_STATE_BUSY;
00983
00984     /* Configure edge sensitivity for encoder mode */
00985     /* Get the LPTIMx CFGR value */
00986     tmpcfgr = hlptim->Instance->CFGR;
00987
00988     /* Clear CKPOL bits */
00989     tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
00990
00991     /* Set Input polarity */
00992     tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
00993
00994     /* Write to LPTIMx CFGR */
00995     hlptim->Instance->CFGR = tmpcfgr;
00996
00997     /* Set ENC bit to enable the encoder interface */
00998     hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
00999
01000     /* Enable "switch to down direction" interrupt */
01001     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
01002
01003     /* Enable "switch to up direction" interrupt */
01004     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
01005
01006     /* Enable the Peripheral */
01007     __HAL_LPTIM_ENABLE(hlptim);
01008
01009     /* Load the period value in the autoreload register */
01010     __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01011
01012     /* Start timer in continuous mode */
01013     __HAL_LPTIM_START_CONTINUOUS(hlptim);
01014
01015     /* Change the TIM state*/
01016     hlptim->State= HAL_LPTIM_STATE_READY;
01017   }
01018   else
01019   {
01020     status = HAL_ERROR;
01021   }
01022
01023   /* Return function status */
01024   return status;
01025 }
01026
01027 /**
01028   * @brief  Stop the Encoder interface in interrupt mode.
01029   * @param  hlptim : LPTIM handle
01030   * @retval HAL status
01031   */
01032 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01033 {
01034   /* Check the parameters */
01035   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01036
01037   /* Set the LPTIM state */
01038   hlptim->State= HAL_LPTIM_STATE_BUSY;
01039
01040   /* Disable the Peripheral */
01041   __HAL_LPTIM_DISABLE(hlptim);
01042
01043   /* Reset ENC bit to disable the encoder interface */
01044   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01045
01046   /* Disable "switch to down direction" interrupt */
01047   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
01048
01049   /* Disable "switch to up direction" interrupt */
01050   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
01051
01052   /* Change the TIM state*/
01053   hlptim->State= HAL_LPTIM_STATE_READY;
01054
01055   /* Return function status */
01056   return HAL_OK;
01057 }
01058
01059 /**
01060   * @brief  Start the Timeout function.
01061   * @note   The first trigger event will start the timer, any successive
01062   *         trigger event will reset the counter and the timer restarts.
01063   * @param  hlptim : LPTIM handle
01064   * @param  Period : Specifies the Autoreload value.
01065   *         This parameter must be a value between 0x0000 and 0xFFFF.
01066   * @param  Timeout : Specifies the TimeOut value to rest the counter.
01067   *         This parameter must be a value between 0x0000 and 0xFFFF.
01068   * @retval HAL status
01069   */
01070 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01071 {
01072   /* Check the parameters */
01073   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01074   assert_param(IS_LPTIM_PERIOD(Period));
01075   assert_param(IS_LPTIM_PULSE(Timeout));
01076
01077   /* Set the LPTIM state */
01078   hlptim->State= HAL_LPTIM_STATE_BUSY;
01079
01080   /* Set TIMOUT bit to enable the timeout function */
01081   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01082
01083   /* Enable the Peripheral */
01084   __HAL_LPTIM_ENABLE(hlptim);
01085
01086   /* Load the period value in the autoreload register */
01087   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01088
01089   /* Load the Timeout value in the compare register */
01090   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01091
01092   /* Start timer in continuous mode */
01093   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01094
01095   /* Change the TIM state*/
01096   hlptim->State= HAL_LPTIM_STATE_READY;
01097
01098   /* Return function status */
01099   return HAL_OK;
01100 }
01101
01102 /**
01103   * @brief  Stop the Timeout function.
01104   * @param  hlptim : LPTIM handle
01105   * @retval HAL status
01106   */
01107 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
01108 {
01109   /* Check the parameters */
01110   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01111
01112   /* Set the LPTIM state */
01113   hlptim->State= HAL_LPTIM_STATE_BUSY;
01114
01115   /* Disable the Peripheral */
01116   __HAL_LPTIM_DISABLE(hlptim);
01117
01118   /* Reset TIMOUT bit to enable the timeout function */
01119   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01120
01121   /* Change the TIM state*/
01122   hlptim->State= HAL_LPTIM_STATE_READY;
01123
01124   /* Return function status */
01125   return HAL_OK;
01126 }
01127
01128 /**
01129   * @brief  Start the Timeout function in interrupt mode.
01130   * @note   The first trigger event will start the timer, any successive
01131   *         trigger event will reset the counter and the timer restarts.
01132   * @param  hlptim : LPTIM handle
01133   * @param  Period : Specifies the Autoreload value.
01134   *         This parameter must be a value between 0x0000 and 0xFFFF.
01135   * @param  Timeout : Specifies the TimeOut value to rest the counter.
01136   *         This parameter must be a value between 0x0000 and 0xFFFF.
01137   * @retval HAL status
01138   */
01139 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01140 {
01141   /* Check the parameters */
01142   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01143   assert_param(IS_LPTIM_PERIOD(Period));
01144   assert_param(IS_LPTIM_PULSE(Timeout));
01145
01146   /* Set the LPTIM state */
01147   hlptim->State= HAL_LPTIM_STATE_BUSY;
01148
01149   /* Set TIMOUT bit to enable the timeout function */
01150   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01151
01152   /* Enable Compare match interrupt */
01153   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01154
01155   /* Enable the Peripheral */
01156   __HAL_LPTIM_ENABLE(hlptim);
01157
01158   /* Load the period value in the autoreload register */
01159   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01160
01161   /* Load the Timeout value in the compare register */
01162   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01163
01164   /* Start timer in continuous mode */
01165   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01166
01167   /* Change the TIM state*/
01168   hlptim->State= HAL_LPTIM_STATE_READY;
01169
01170   /* Return function status */
01171   return HAL_OK;
01172 }
01173
01174 /**
01175   * @brief  Stop the Timeout function in interrupt mode.
01176   * @param  hlptim : LPTIM handle
01177   * @retval HAL status
01178   */
01179 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01180 {
01181   /* Check the parameters */
01182   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01183
01184   /* Set the LPTIM state */
01185   hlptim->State= HAL_LPTIM_STATE_BUSY;
01186
01187   /* Disable the Peripheral */
01188   __HAL_LPTIM_DISABLE(hlptim);
01189
01190   /* Reset TIMOUT bit to enable the timeout function */
01191   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01192
01193   /* Disable Compare match interrupt */
01194   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01195
01196   /* Change the TIM state*/
01197   hlptim->State= HAL_LPTIM_STATE_READY;
01198
01199   /* Return function status */
01200   return HAL_OK;
01201 }
01202
01203 /**
01204   * @brief  Start the Counter mode.
01205   * @param  hlptim : LPTIM handle
01206   * @param  Period : Specifies the Autoreload value.
01207   *         This parameter must be a value between 0x0000 and 0xFFFF.
01208   * @retval HAL status
01209   */
01210 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01211 {
01212   /* Check the parameters */
01213   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01214   assert_param(IS_LPTIM_PERIOD(Period));
01215
01216   /* Set the LPTIM state */
01217   hlptim->State= HAL_LPTIM_STATE_BUSY;
01218
01219   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01220   if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01221   {
01222     /* Check if clock is prescaled */
01223     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01224     /* Set clock prescaler to 0 */
01225     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01226   }
01227
01228   /* Enable the Peripheral */
01229   __HAL_LPTIM_ENABLE(hlptim);
01230
01231   /* Load the period value in the autoreload register */
01232   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01233
01234   /* Start timer in continuous mode */
01235   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01236
01237   /* Change the TIM state*/
01238   hlptim->State= HAL_LPTIM_STATE_READY;
01239
01240   /* Return function status */
01241   return HAL_OK;
01242 }
01243
01244 /**
01245   * @brief  Stop the Counter mode.
01246   * @param  hlptim : LPTIM handle
01247   * @retval HAL status
01248   */
01249 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
01250 {
01251   /* Check the parameters */
01252   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01253
01254   /* Set the LPTIM state */
01255   hlptim->State= HAL_LPTIM_STATE_BUSY;
01256
01257   /* Disable the Peripheral */
01258   __HAL_LPTIM_DISABLE(hlptim);
01259
01260   /* Change the TIM state*/
01261   hlptim->State= HAL_LPTIM_STATE_READY;
01262
01263   /* Return function status */
01264   return HAL_OK;
01265 }
01266
01267 /**
01268   * @brief  Start the Counter mode in interrupt mode.
01269   * @param  hlptim : LPTIM handle
01270   * @param  Period : Specifies the Autoreload value.
01271   *         This parameter must be a value between 0x0000 and 0xFFFF.
01272   * @retval HAL status
01273   */
01274 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01275 {
01276   /* Check the parameters */
01277   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01278   assert_param(IS_LPTIM_PERIOD(Period));
01279
01280   /* Set the LPTIM state */
01281   hlptim->State= HAL_LPTIM_STATE_BUSY;
01282
01283   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01284   if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01285   {
01286     /* Check if clock is prescaled */
01287     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01288     /* Set clock prescaler to 0 */
01289     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01290   }
01291
01292   /* Enable Autoreload write complete interrupt */
01293   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01294
01295   /* Enable Autoreload match interrupt */
01296   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01297
01298   /* Enable the Peripheral */
01299   __HAL_LPTIM_ENABLE(hlptim);
01300
01301   /* Load the period value in the autoreload register */
01302   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01303
01304   /* Start timer in continuous mode */
01305   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01306
01307   /* Change the TIM state*/
01308   hlptim->State= HAL_LPTIM_STATE_READY;
01309
01310   /* Return function status */
01311   return HAL_OK;
01312 }
01313
01314 /**
01315   * @brief  Stop the Counter mode in interrupt mode.
01316   * @param  hlptim : LPTIM handle
01317   * @retval HAL status
01318   */
01319 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01320 {
01321   /* Check the parameters */
01322   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01323
01324   /* Set the LPTIM state */
01325   hlptim->State= HAL_LPTIM_STATE_BUSY;
01326
01327   /* Disable the Peripheral */
01328   __HAL_LPTIM_DISABLE(hlptim);
01329
01330   /* Disable Autoreload write complete interrupt */
01331   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01332
01333   /* Disable Autoreload match interrupt */
01334   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01335
01336   /* Change the TIM state*/
01337   hlptim->State= HAL_LPTIM_STATE_READY;
01338
01339   /* Return function status */
01340   return HAL_OK;
01341 }
01342
01343 /**
01344   * @}
01345   */
01346
01347 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
01348  *  @brief  Read operation functions.
01349  *
01350 @verbatim
01351   ==============================================================================
01352                   ##### LPTIM Read operation functions #####
01353   ==============================================================================
01354 [..]  This section provides LPTIM Reading functions.
01355       (+) Read the counter value.
01356       (+) Read the period (Auto-reload) value.
01357       (+) Read the pulse (Compare)value.
01358 @endverbatim
01359   * @{
01360   */
01361
01362 /**
01363   * @brief  Return the current counter value.
01364   * @param  hlptim: LPTIM handle
01365   * @retval Counter value.
01366   */
01367 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
01368 {
01369     /* Check the parameters */
01370   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01371
01372   return (hlptim->Instance->CNT);
01373 }
01374
01375 /**
01376   * @brief  Return the current Autoreload (Period) value.
01377   * @param  hlptim: LPTIM handle
01378   * @retval Autoreload value.
01379   */
01380 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
01381 {
01382     /* Check the parameters */
01383   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01384
01385   return (hlptim->Instance->ARR);
01386 }
01387
01388 /**
01389   * @brief  Return the current Compare (Pulse) value.
01390   * @param  hlptim: LPTIM handle
01391   * @retval Compare value.
01392   */
01393 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
01394 {
01395     /* Check the parameters */
01396   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01397
01398   return (hlptim->Instance->CMP);
01399 }
01400
01401 /**
01402   * @}
01403   */
01404
01405
01406
01407 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
01408  *  @brief  LPTIM  IRQ handler.
01409  *
01410 @verbatim
01411   ==============================================================================
01412                       ##### LPTIM IRQ handler and callbacks  #####
01413   ==============================================================================
01414 [..]  This section provides LPTIM IRQ handler and callback functions called within
01415       the IRQ handler.
01416
01417 @endverbatim
01418   * @{
01419   */
01420
01421 /**
01422   * @brief  Handle LPTIM interrupt request.
01423   * @param  hlptim: LPTIM handle
01424   * @retval None
01425   */
01426 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
01427 {
01428   /* Compare match interrupt */
01429   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
01430   {
01431     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
01432     {
01433       /* Clear Compare match flag */
01434       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
01435
01436       /* Compare match Callback */
01437       HAL_LPTIM_CompareMatchCallback(hlptim);
01438     }
01439   }
01440
01441   /* Autoreload match interrupt */
01442   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
01443   {
01444     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
01445     {
01446       /* Clear Autoreload match flag */
01447       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
01448
01449       /* Autoreload match Callback */
01450       HAL_LPTIM_AutoReloadMatchCallback(hlptim);
01451     }
01452   }
01453
01454   /* Trigger detected interrupt */
01455   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
01456   {
01457     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
01458     {
01459       /* Clear Trigger detected flag */
01460       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
01461
01462       /* Trigger detected callback */
01463       HAL_LPTIM_TriggerCallback(hlptim);
01464     }
01465   }
01466
01467   /* Compare write interrupt */
01468   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
01469   {
01470     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
01471     {
01472       /* Clear Compare write flag */
01473       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01474
01475       /* Compare write Callback */
01476       HAL_LPTIM_CompareWriteCallback(hlptim);
01477     }
01478   }
01479
01480   /* Autoreload write interrupt */
01481   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
01482   {
01483     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
01484     {
01485       /* Clear Autoreload write flag */
01486       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01487
01488       /* Autoreload write Callback */
01489       HAL_LPTIM_AutoReloadWriteCallback(hlptim);
01490     }
01491   }
01492
01493   /* Direction counter changed from Down to Up interrupt */
01494   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
01495   {
01496     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
01497     {
01498       /* Clear Direction counter changed from Down to Up flag */
01499       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
01500
01501       /* Direction counter changed from Down to Up Callback */
01502       HAL_LPTIM_DirectionUpCallback(hlptim);
01503     }
01504   }
01505
01506   /* Direction counter changed from Up to Down interrupt */
01507   if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
01508   {
01509     if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
01510     {
01511       /* Clear Direction counter changed from Up to Down flag */
01512       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
01513
01514       /* Direction counter changed from Up to Down Callback */
01515       HAL_LPTIM_DirectionDownCallback(hlptim);
01516     }
01517   }
01518 }
01519
01520 /**
01521   * @brief  Compare match callback in non-blocking mode.
01522   * @param  hlptim : LPTIM handle
01523   * @retval None
01524   */
01525 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
01526 {
01527   /* Prevent unused argument(s) compilation warning */
01528   UNUSED(hlptim);
01529
01530   /* NOTE : This function should not be modified, when the callback is needed,
01531             the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
01532    */
01533 }
01534
01535 /**
01536   * @brief  Autoreload match callback in non-blocking mode.
01537   * @param  hlptim : LPTIM handle
01538   * @retval None
01539   */
01540 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
01541 {
01542   /* Prevent unused argument(s) compilation warning */
01543   UNUSED(hlptim);
01544
01545   /* NOTE : This function should not be modified, when the callback is needed,
01546             the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
01547    */
01548 }
01549
01550 /**
01551   * @brief  Trigger detected callback in non-blocking mode.
01552   * @param  hlptim : LPTIM handle
01553   * @retval None
01554   */
01555 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
01556 {
01557   /* Prevent unused argument(s) compilation warning */
01558   UNUSED(hlptim);
01559
01560   /* NOTE : This function should not be modified, when the callback is needed,
01561             the HAL_LPTIM_TriggerCallback could be implemented in the user file
01562    */
01563 }
01564
01565 /**
01566   * @brief  Compare write callback in non-blocking mode.
01567   * @param  hlptim : LPTIM handle
01568   * @retval None
01569   */
01570 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
01571 {
01572   /* Prevent unused argument(s) compilation warning */
01573   UNUSED(hlptim);
01574
01575   /* NOTE : This function should not be modified, when the callback is needed,
01576             the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
01577    */
01578 }
01579
01580 /**
01581   * @brief  Autoreload write callback in non-blocking mode.
01582   * @param  hlptim : LPTIM handle
01583   * @retval None
01584   */
01585 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
01586 {
01587   /* Prevent unused argument(s) compilation warning */
01588   UNUSED(hlptim);
01589
01590   /* NOTE : This function should not be modified, when the callback is needed,
01591             the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
01592    */
01593 }
01594
01595 /**
01596   * @brief  Direction counter changed from Down to Up callback in non-blocking mode.
01597   * @param  hlptim : LPTIM handle
01598   * @retval None
01599   */
01600 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
01601 {
01602   /* Prevent unused argument(s) compilation warning */
01603   UNUSED(hlptim);
01604
01605   /* NOTE : This function should not be modified, when the callback is needed,
01606             the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
01607    */
01608 }
01609
01610 /**
01611   * @brief  Direction counter changed from Up to Down callback in non-blocking mode.
01612   * @param  hlptim : LPTIM handle
01613   * @retval None
01614   */
01615 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
01616 {
01617   /* Prevent unused argument(s) compilation warning */
01618   UNUSED(hlptim);
01619
01620   /* NOTE : This function should not be modified, when the callback is needed,
01621             the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
01622    */
01623 }
01624
01625 /**
01626   * @}
01627   */
01628
01629 /** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions
01630  *  @brief   Peripheral State functions.
01631  *
01632 @verbatim
01633   ==============================================================================
01634                       ##### Peripheral State functions #####
01635   ==============================================================================
01636     [..]
01637     This subsection permits to get in run-time the status of the peripheral.
01638
01639 @endverbatim
01640   * @{
01641   */
01642
01643 /**
01644   * @brief  Return the LPTIM handle state.
01645   * @param  hlptim: LPTIM handle
01646   * @retval HAL state
01647   */
01648 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
01649 {
01650   /* Return LPTIM handle state */
01651   return hlptim->State;
01652 }
01653
01654 /**
01655   * @}
01656   */
01657
01658
01659 /**
01660   * @}
01661   */
01662
01663 #endif /* HAL_LPTIM_MODULE_ENABLED */
01664 /**
01665   * @}
01666   */
01667
01668 /**
01669   * @}
01670   */
01671
01672 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_lptim.h Source File

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stm32l4xx_hal_lptim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_lptim.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of LPTIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_LPTIM_H
00040 #define __STM32L4xx_HAL_LPTIM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup LPTIM
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  LPTIM Clock configuration definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Source;         /*!< Selects the clock source.
00068                            This parameter can be a value of @ref LPTIM_Clock_Source   */
00069
00070   uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
00071                            This parameter can be a value of @ref LPTIM_Clock_Prescaler */
00072
00073 }LPTIM_ClockConfigTypeDef;
00074
00075 /**
00076   * @brief  LPTIM Clock configuration definition
00077   */
00078 typedef struct
00079 {
00080   uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
00081                            if the ULPTIM input is selected.
00082                            Note: This parameter is used only when Ultra low power clock source is used.
00083                            Note: If the polarity is configured on 'both edges', an auxiliary clock
00084                            (one of the Low power oscillator) must be active.
00085                            This parameter can be a value of @ref LPTIM_Clock_Polarity */
00086
00087   uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
00088                            Note: This parameter is used only when Ultra low power clock source is used.
00089                            This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
00090
00091 }LPTIM_ULPClockConfigTypeDef;
00092
00093 /**
00094   * @brief  LPTIM Trigger configuration definition
00095   */
00096 typedef struct
00097 {
00098   uint32_t Source;        /*!< Selects the Trigger source.
00099                           This parameter can be a value of @ref LPTIM_Trigger_Source */
00100
00101   uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
00102                           Note: This parameter is used only when an external trigger is used.
00103                           This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
00104
00105   uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
00106                           Note: This parameter is used only when an external trigger is used.
00107                           This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
00108 }LPTIM_TriggerConfigTypeDef;
00109
00110 /**
00111   * @brief  LPTIM Initialization Structure definition
00112   */
00113 typedef struct
00114 {
00115   LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
00116
00117   LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
00118
00119   LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
00120
00121   uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
00122                                                     This parameter can be a value of @ref LPTIM_Output_Polarity */
00123
00124   uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autoreload and the compare
00125                                                     values is done immediately or after the end of current period.
00126                                                     This parameter can be a value of @ref LPTIM_Updating_Mode */
00127
00128   uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
00129                                                     or each external event.
00130                                                     This parameter can be a value of @ref LPTIM_Counter_Source */
00131
00132   uint32_t                     Input1Source;        /*!< Specifies source selected for input1 (GPIO or comparator output).
00133                                                     This parameter can be a value of @ref LPTIM_Input1_Source */
00134
00135   uint32_t                     Input2Source;        /*!< Specifies source selected for input2 (GPIO or comparator output).
00136                                                     Note: This parameter is used only for encoder feature so is used only
00137                                                     for LPTIM1 instance.
00138                                                     This parameter can be a value of @ref LPTIM_Input2_Source */
00139
00140 }LPTIM_InitTypeDef;
00141
00142 /**
00143   * @brief  HAL LPTIM State structure definition
00144   */
00145 typedef enum __HAL_LPTIM_StateTypeDef
00146 {
00147   HAL_LPTIM_STATE_RESET            = 0x00,    /*!< Peripheral not yet initialized or disabled  */
00148   HAL_LPTIM_STATE_READY            = 0x01,    /*!< Peripheral Initialized and ready for use    */
00149   HAL_LPTIM_STATE_BUSY             = 0x02,    /*!< An internal process is ongoing              */
00150   HAL_LPTIM_STATE_TIMEOUT          = 0x03,    /*!< Timeout state                               */
00151   HAL_LPTIM_STATE_ERROR            = 0x04     /*!< Internal Process is ongoing                */
00152 }HAL_LPTIM_StateTypeDef;
00153
00154 /**
00155   * @brief  LPTIM handle Structure definition
00156   */
00157 typedef struct
00158 {
00159       LPTIM_TypeDef              *Instance;         /*!< Register base address     */
00160
00161       LPTIM_InitTypeDef           Init;             /*!< LPTIM required parameters */
00162
00163       HAL_StatusTypeDef           Status;           /*!< LPTIM peripheral status   */
00164
00165       HAL_LockTypeDef             Lock;             /*!< LPTIM locking object      */
00166
00167    __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
00168
00169 }LPTIM_HandleTypeDef;
00170
00171 /**
00172   * @}
00173   */
00174
00175 /* Exported constants --------------------------------------------------------*/
00176 /** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
00177   * @{
00178   */
00179
00180 /** @defgroup LPTIM_Clock_Source LPTIM Clock Source
00181   * @{
00182   */
00183 #define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        ((uint32_t)0x00)
00184 #define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
00190   * @{
00191   */
00192 #define LPTIM_PRESCALER_DIV1                    ((uint32_t)0x000000)
00193 #define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
00194 #define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
00195 #define LPTIM_PRESCALER_DIV8                    ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
00196 #define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
00197 #define LPTIM_PRESCALER_DIV32                   ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
00198 #define LPTIM_PRESCALER_DIV64                   ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
00199 #define LPTIM_PRESCALER_DIV128                  ((uint32_t)LPTIM_CFGR_PRESC)
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
00205   * @{
00206   */
00207
00208 #define LPTIM_OUTPUTPOLARITY_HIGH               ((uint32_t)0x00000000)
00209 #define LPTIM_OUTPUTPOLARITY_LOW                (LPTIM_CFGR_WAVPOL)
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
00215   * @{
00216   */
00217 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000)
00218 #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
00219 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
00220 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
00226   * @{
00227   */
00228 #define LPTIM_CLOCKPOLARITY_RISING              ((uint32_t)0x00000000)
00229 #define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
00230 #define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
00236   * @{
00237   */
00238 #define LPTIM_TRIGSOURCE_SOFTWARE               ((uint32_t)0x0000FFFF)
00239 #define LPTIM_TRIGSOURCE_0                      ((uint32_t)0x00000000)
00240 #define LPTIM_TRIGSOURCE_1                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
00241 #define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
00242 #define LPTIM_TRIGSOURCE_3                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
00243 #define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
00244 #define LPTIM_TRIGSOURCE_5                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
00245 #define LPTIM_TRIGSOURCE_6                      ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
00246 #define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
00252   * @{
00253   */
00254 #define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
00255 #define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
00256 #define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
00257 /**
00258   * @}
00259   */
00260
00261 /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
00262   * @{
00263   */
00264 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000)
00265 #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
00266 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
00267 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
00273   * @{
00274   */
00275
00276 #define LPTIM_UPDATE_IMMEDIATE                  ((uint32_t)0x00000000)
00277 #define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup LPTIM_Counter_Source LPTIM Counter Source
00283   * @{
00284   */
00285
00286 #define LPTIM_COUNTERSOURCE_INTERNAL            ((uint32_t)0x00000000)
00287 #define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
00293   * @{
00294   */
00295
00296 #define LPTIM_INPUT1SOURCE_GPIO         ((uint32_t)0x00000000) /*!< For LPTIM1 and LPTIM2 */
00297 #define LPTIM_INPUT1SOURCE_COMP1        LPTIM_OR_OR_0          /*!< For LPTIM1 and LPTIM2 */
00298 #define LPTIM_INPUT1SOURCE_COMP2        LPTIM_OR_OR_1          /*!< For LPTIM2 */
00299 #define LPTIM_INPUT1SOURCE_COMP1_COMP2  LPTIM_OR_OR            /*!< For LPTIM2 */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
00305   * @{
00306   */
00307
00308 #define LPTIM_INPUT2SOURCE_GPIO         ((uint32_t)0x00000000) /*!< For LPTIM1 */
00309 #define LPTIM_INPUT2SOURCE_COMP2        LPTIM_OR_OR_1          /*!< For LPTIM1 */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
00315   * @{
00316   */
00317
00318 #define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
00319 #define LPTIM_FLAG_UP                            LPTIM_ISR_UP
00320 #define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
00321 #define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
00322 #define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
00323 #define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
00324 #define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
00330   * @{
00331   */
00332
00333 #define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
00334 #define LPTIM_IT_UP                              LPTIM_IER_UPIE
00335 #define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
00336 #define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
00337 #define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
00338 #define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
00339 #define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
00340 /**
00341   * @}
00342   */
00343
00344 /**
00345   * @}
00346   */
00347
00348 /* Exported macros -----------------------------------------------------------*/
00349 /** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
00350   * @{
00351   */
00352
00353 /** @brief Reset LPTIM handle state.
00354   * @param  __HANDLE__: LPTIM handle
00355   * @retval None
00356   */
00357 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
00358
00359 /**
00360   * @brief  Enable the LPTIM peripheral.
00361   * @param  __HANDLE__: LPTIM handle
00362   * @retval None
00363   */
00364 #define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |=  (LPTIM_CR_ENABLE))
00365
00366 /**
00367   * @brief  Disable the LPTIM peripheral.
00368   * @param  __HANDLE__: LPTIM handle
00369   * @retval None
00370   */
00371 #define __HAL_LPTIM_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &=  ~(LPTIM_CR_ENABLE))
00372
00373 /**
00374   * @brief  Start the LPTIM peripheral in Continuous or in single mode.
00375   * @param  __HANDLE__: DMA handle
00376   * @retval None
00377   */
00378 #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
00379 #define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
00380
00381
00382 /**
00383   * @brief  Write the passed parameter in the Autoreload register.
00384   * @param  __HANDLE__: LPTIM handle
00385   * @param  __VALUE__: Autoreload value
00386   * @retval None
00387   */
00388 #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
00389
00390 /**
00391   * @brief  Write the passed parameter in the Compare register.
00392   * @param  __HANDLE__: LPTIM handle
00393   * @param  __VALUE__: Compare value
00394   * @retval None
00395   */
00396 #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
00397
00398 /**
00399   * @brief  Check whether the specified LPTIM flag is set or not.
00400   * @param  __HANDLE__: LPTIM handle
00401   * @param  __FLAG__: LPTIM flag to check
00402   *            This parameter can be a value of:
00403   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00404   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00405   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00406   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00407   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00408   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00409   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00410   * @retval The state of the specified flag (SET or RESET).
00411   */
00412 #define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
00413
00414 /**
00415   * @brief  Clear the specified LPTIM flag.
00416   * @param  __HANDLE__: LPTIM handle.
00417   * @param  __FLAG__: LPTIM flag to clear.
00418   *            This parameter can be a value of:
00419   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00420   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00421   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00422   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00423   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00424   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00425   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00426   * @retval None
00427   */
00428 #define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
00429
00430 /**
00431   * @brief  Enable the specified LPTIM interrupt.
00432   * @param  __HANDLE__: LPTIM handle.
00433   * @param  __INTERRUPT__: LPTIM interrupt to set.
00434   *            This parameter can be a value of:
00435   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00436   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00437   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00438   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00439   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00440   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00441   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00442   * @retval None
00443   */
00444 #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
00445
00446  /**
00447   * @brief  Disable the specified LPTIM interrupt.
00448   * @param  __HANDLE__: LPTIM handle.
00449   * @param  __INTERRUPT__: LPTIM interrupt to set.
00450   *            This parameter can be a value of:
00451   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00452   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00453   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00454   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00455   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00456   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00457   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00458   * @retval None
00459   */
00460 #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
00461
00462     /**
00463   * @brief  Check whether the specified LPTIM interrupt source is enabled or not.
00464   * @param  __HANDLE__: LPTIM handle.
00465   * @param  __INTERRUPT__: LPTIM interrupt to check.
00466   *            This parameter can be a value of:
00467   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00468   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00469   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00470   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00471   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00472   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00473   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00474   * @retval Interrupt status.
00475   */
00476
00477 #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00478
00479 /**
00480   * @}
00481   */
00482
00483 /* Exported functions --------------------------------------------------------*/
00484 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00485   * @{
00486   */
00487
00488 /* Initialization/de-initialization functions  ********************************/
00489 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
00490 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
00491
00492 /* MSP functions  *************************************************************/
00493 void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
00494 void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
00495
00496 /* Start/Stop operation functions  *********************************************/
00497 /* ################################# PWM Mode ################################*/
00498 /* Blocking mode: Polling */
00499 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00500 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
00501 /* Non-Blocking mode: Interrupt */
00502 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00503 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00504
00505 /* ############################# One Pulse Mode ##############################*/
00506 /* Blocking mode: Polling */
00507 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00508 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
00509 /* Non-Blocking mode: Interrupt */
00510 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00511 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00512
00513 /* ############################## Set once Mode ##############################*/
00514 /* Blocking mode: Polling */
00515 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00516 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
00517 /* Non-Blocking mode: Interrupt */
00518 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00519 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00520
00521 /* ############################### Encoder Mode ##############################*/
00522 /* Blocking mode: Polling */
00523 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00524 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
00525 /* Non-Blocking mode: Interrupt */
00526 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00527 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00528
00529 /* ############################# Time out  Mode ##############################*/
00530 /* Blocking mode: Polling */
00531 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00532 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
00533 /* Non-Blocking mode: Interrupt */
00534 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00535 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00536
00537 /* ############################## Counter Mode ###############################*/
00538 /* Blocking mode: Polling */
00539 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00540 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
00541 /* Non-Blocking mode: Interrupt */
00542 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00543 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00544
00545 /* Reading operation functions ************************************************/
00546 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
00547 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
00548 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
00549
00550 /* LPTIM IRQ functions  *******************************************************/
00551 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
00552
00553 /* CallBack functions  ********************************************************/
00554 void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
00555 void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
00556 void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
00557 void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
00558 void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
00559 void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
00560 void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
00561
00562 /* Peripheral State functions  ************************************************/
00563 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
00564
00565 /**
00566   * @}
00567   */
00568
00569 /* Private types -------------------------------------------------------------*/
00570 /** @defgroup LPTIM_Private_Types LPTIM Private Types
00571   * @{
00572   */
00573
00574 /**
00575   * @}
00576   */
00577
00578 /* Private variables ---------------------------------------------------------*/
00579 /** @defgroup LPTIM_Private_Variables LPTIM Private Variables
00580   * @{
00581   */
00582
00583 /**
00584   * @}
00585   */
00586
00587 /* Private constants ---------------------------------------------------------*/
00588 /** @defgroup LPTIM_Private_Constants LPTIM Private Constants
00589   * @{
00590   */
00591
00592 /**
00593   * @}
00594   */
00595
00596 /* Private macros ------------------------------------------------------------*/
00597 /** @defgroup LPTIM_Private_Macros LPTIM Private Macros
00598   * @{
00599   */
00600
00601 #define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
00602                                                  ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
00603
00604
00605 #define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
00606                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
00607                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
00608                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
00609                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
00610                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
00611                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
00612                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
00613
00614 #define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
00615
00616 #define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
00617                                                  ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
00618
00619 #define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
00620                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
00621                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
00622                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
00623
00624 #define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
00625                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
00626                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
00627
00628 #define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
00629                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
00630                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
00631                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
00632                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
00633                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
00634                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
00635                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
00636                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_7))
00637
00638 #define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
00639                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
00640                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
00641
00642 #define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
00643                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
00644                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
00645                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
00646
00647 #define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
00648                                                  ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
00649
00650 #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
00651                                                  ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
00652
00653 #define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFF)
00654
00655 #define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFF)
00656
00657 #define IS_LPTIM_PERIOD(__PERIOD__)             ((__PERIOD__) <= 0x0000FFFF)
00658
00659 #define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFF)
00660
00661 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)  \
00662     ((((__INSTANCE__) == LPTIM1) &&                       \
00663      (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00664       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))        \
00665      ||                                                   \
00666      (((__INSTANCE__) == LPTIM2) &&                       \
00667      (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00668       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||       \
00669       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||       \
00670       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
00671
00672 #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
00673      (((__INSTANCE__) == LPTIM1) &&                       \
00674      (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
00675       ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
00676
00677 /**
00678   * @}
00679   */
00680
00681 /* Private functions ---------------------------------------------------------*/
00682 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00683   * @{
00684   */
00685
00686 /**
00687   * @}
00688   */
00689
00690 /**
00691   * @}
00692   */
00693
00694 /**
00695   * @}
00696   */
00697
00698 #ifdef __cplusplus
00699 }
00700 #endif
00701
00702 #endif /* __STM32L4xx_HAL_LPTIM_H */
00703
00704 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_nand.c Source File

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stm32l4xx_hal_nand.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_nand.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   NAND HAL module driver.
00008   *          This file provides a generic firmware to drive NAND memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                          ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016       This driver is a generic layered driver which contains a set of APIs used to
00017       control NAND flash memories. It uses the FMC layer functions to interface
00018       with NAND devices. This driver is used as follows:
00019
00020       (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
00021           with control and timing parameters for both common and attribute spaces.
00022
00023       (+) Read NAND flash memory maker and device IDs using the function
00024           HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
00025           structure declared by the function caller.
00026
00027       (+) Access NAND flash memory by read/write operations using the functions
00028           HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
00029           to read/write page(s)/spare area(s). These functions use specific device
00030           information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
00031           structure. The read/write address information is contained by the Nand_Address_Typedef
00032           structure passed as parameter.
00033
00034       (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
00035
00036       (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
00037           The erase block address information is contained in the Nand_Address_Typedef
00038           structure passed as parameter.
00039
00040       (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
00041
00042       (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
00043           HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
00044           feature or the function HAL_NAND_GetECC() to get the ECC correction code.
00045
00046       (+) You can monitor the NAND device HAL state by calling the function
00047           HAL_NAND_GetState()
00048
00049     [..]
00050       (@) This driver is a set of generic APIs which handle standard NAND flash operations.
00051           If a NAND flash device contains different operations and/or implementations,
00052           it should be implemented separately.
00053
00054   @endverbatim
00055   ******************************************************************************
00056   * @attention
00057   *
00058   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00059   *
00060   * Redistribution and use in source and binary forms, with or without modification,
00061   * are permitted provided that the following conditions are met:
00062   *   1. Redistributions of source code must retain the above copyright notice,
00063   *      this list of conditions and the following disclaimer.
00064   *   2. Redistributions in binary form must reproduce the above copyright notice,
00065   *      this list of conditions and the following disclaimer in the documentation
00066   *      and/or other materials provided with the distribution.
00067   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00068   *      may be used to endorse or promote products derived from this software
00069   *      without specific prior written permission.
00070   *
00071   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00072   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00073   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00074   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00075   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00076   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00077   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00078   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00079   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00080   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00081   *
00082   ******************************************************************************
00083   */
00084
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32l4xx_hal.h"
00087
00088 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00089
00090 /** @addtogroup STM32L4xx_HAL_Driver
00091   * @{
00092   */
00093
00094 #ifdef HAL_NAND_MODULE_ENABLED
00095
00096 /** @defgroup NAND NAND
00097   * @brief NAND HAL module driver
00098   * @{
00099   */
00100
00101 /* Private typedef -----------------------------------------------------------*/
00102 /* Private define ------------------------------------------------------------*/
00103 /** @defgroup NAND_Private_Constants NAND Private Constants
00104   * @{
00105   */
00106
00107 /**
00108   * @}
00109   */
00110
00111 /* Private macro -------------------------------------------------------------*/
00112 /** @defgroup NAND_Private_Macros NAND Private Macros
00113   * @{
00114   */
00115
00116 /**
00117   * @}
00118   */
00119
00120 /* Private variables ---------------------------------------------------------*/
00121 /* Private function prototypes -----------------------------------------------*/
00122 /** @defgroup NAND_Private_Functions NAND Private Functions
00123   * @{
00124   */
00125 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
00126 /**
00127   * @}
00128   */
00129
00130 /* Exported functions ---------------------------------------------------------*/
00131
00132 /** @defgroup NAND_Exported_Functions NAND Exported Functions
00133   * @{
00134   */
00135
00136 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00137   * @brief    Initialization and Configuration functions
00138   *
00139   @verbatim
00140   ==============================================================================
00141             ##### NAND Initialization and de-initialization functions #####
00142   ==============================================================================
00143   [..]
00144     This section provides functions allowing to initialize/de-initialize
00145     the NAND memory
00146
00147 @endverbatim
00148   * @{
00149   */
00150
00151 /**
00152   * @brief  Perform NAND memory Initialization sequence.
00153   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00154   *                the configuration information for NAND module.
00155   * @param  ComSpace_Timing: pointer to Common space timing structure
00156   * @param  AttSpace_Timing: pointer to Attribute space timing structure
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
00160 {
00161   /* Check the NAND handle state */
00162   if(hnand == NULL)
00163   {
00164      return HAL_ERROR;
00165   }
00166
00167   if(hnand->State == HAL_NAND_STATE_RESET)
00168   {
00169     /* Allocate lock resource and initialize it */
00170     hnand->Lock = HAL_UNLOCKED;
00171
00172     /* Initialize the low level hardware (MSP) */
00173     HAL_NAND_MspInit(hnand);
00174   }
00175
00176   /* Initialize NAND control Interface */
00177   FMC_NAND_Init(hnand->Instance, &(hnand->Init));
00178
00179   /* Initialize NAND common space timing Interface */
00180   FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
00181
00182   /* Initialize NAND attribute space timing Interface */
00183   FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
00184
00185   /* Enable the NAND device */
00186   __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
00187
00188   /* Update the NAND controller state */
00189   hnand->State = HAL_NAND_STATE_READY;
00190
00191   return HAL_OK;
00192 }
00193
00194 /**
00195   * @brief  Perform NAND memory De-Initialization sequence.
00196   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00197   *                the configuration information for NAND module.
00198   * @retval HAL status
00199   */
00200 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
00201 {
00202   /* Initialize the low level hardware (MSP) */
00203   HAL_NAND_MspDeInit(hnand);
00204
00205   /* Configure the NAND registers with their reset values */
00206   FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
00207
00208   /* Reset the NAND controller state */
00209   hnand->State = HAL_NAND_STATE_RESET;
00210
00211   /* Release Lock */
00212   __HAL_UNLOCK(hnand);
00213
00214   return HAL_OK;
00215 }
00216
00217 /**
00218   * @brief  Initialize the NAND MSP.
00219   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00220   *                the configuration information for NAND module.
00221   * @retval None
00222   */
00223 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
00224 {
00225   /* Prevent unused argument(s) compilation warning */
00226   UNUSED(hnand);
00227
00228   /* NOTE : This function should not be modified, when the callback is needed,
00229             the HAL_NAND_MspInit could be implemented in the user file
00230    */
00231 }
00232
00233 /**
00234   * @brief  DeInitialize the NAND MSP.
00235   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00236   *                the configuration information for NAND module.
00237   * @retval None
00238   */
00239 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
00240 {
00241   /* Prevent unused argument(s) compilation warning */
00242   UNUSED(hnand);
00243
00244   /* NOTE : This function should not be modified, when the callback is needed,
00245             the HAL_NAND_MspDeInit could be implemented in the user file
00246    */
00247 }
00248
00249
00250 /**
00251   * @brief  This function handles NAND device interrupt request.
00252   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00253   *                the configuration information for NAND module.
00254   * @retval HAL status
00255 */
00256 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
00257 {
00258   /* Check NAND interrupt Rising edge flag */
00259   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
00260   {
00261     /* NAND interrupt callback*/
00262     HAL_NAND_ITCallback(hnand);
00263
00264     /* Clear NAND interrupt Rising edge pending bit */
00265     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
00266   }
00267
00268   /* Check NAND interrupt Level flag */
00269   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
00270   {
00271     /* NAND interrupt callback*/
00272     HAL_NAND_ITCallback(hnand);
00273
00274     /* Clear NAND interrupt Level pending bit */
00275     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
00276   }
00277
00278   /* Check NAND interrupt Falling edge flag */
00279   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
00280   {
00281     /* NAND interrupt callback*/
00282     HAL_NAND_ITCallback(hnand);
00283
00284     /* Clear NAND interrupt Falling edge pending bit */
00285     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
00286   }
00287
00288   /* Check NAND interrupt FIFO empty flag */
00289   if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
00290   {
00291     /* NAND interrupt callback*/
00292     HAL_NAND_ITCallback(hnand);
00293
00294     /* Clear NAND interrupt FIFO empty pending bit */
00295     __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
00296   }
00297 }
00298
00299 /**
00300   * @brief  NAND interrupt feature callback.
00301   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00302   *                the configuration information for NAND module.
00303   * @retval None
00304   */
00305 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
00306 {
00307   /* Prevent unused argument(s) compilation warning */
00308   UNUSED(hnand);
00309
00310   /* NOTE : This function should not be modified, when the callback is needed,
00311             the HAL_NAND_ITCallback could be implemented in the user file
00312    */
00313 }
00314
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
00320   * @brief    Input Output and memory control functions
00321   *
00322   @verbatim
00323   ==============================================================================
00324                     ##### NAND Input and Output functions #####
00325   ==============================================================================
00326   [..]
00327     This section provides functions allowing to use and control the NAND
00328     memory
00329
00330 @endverbatim
00331   * @{
00332   */
00333
00334 /**
00335   * @brief  Read the NAND memory electronic signature.
00336   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00337   *                the configuration information for NAND module.
00338   * @param  pNAND_ID: NAND ID structure
00339   * @retval HAL status
00340   */
00341 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
00342 {
00343   __IO uint32_t data = 0;
00344   uint32_t deviceaddress = 0;
00345
00346   /* Process Locked */
00347   __HAL_LOCK(hnand);
00348
00349   /* Check the NAND controller state */
00350   if(hnand->State == HAL_NAND_STATE_BUSY)
00351   {
00352      return HAL_BUSY;
00353   }
00354
00355   /* Identify the device address */
00356   deviceaddress = NAND_DEVICE;
00357
00358   /* Update the NAND controller state */
00359   hnand->State = HAL_NAND_STATE_BUSY;
00360
00361   /* Send Read ID command sequence */
00362   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
00363   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00364
00365   /* Read the electronic signature from NAND flash */
00366   data = *(__IO uint32_t *)deviceaddress;
00367
00368   /* Return the data read */
00369   pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00370   pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
00371   pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
00372   pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
00373
00374   /* Update the NAND controller state */
00375   hnand->State = HAL_NAND_STATE_READY;
00376
00377   /* Process unlocked */
00378   __HAL_UNLOCK(hnand);
00379
00380   return HAL_OK;
00381 }
00382
00383 /**
00384   * @brief  NAND memory reset.
00385   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00386   *                the configuration information for NAND module.
00387   * @retval HAL status
00388   */
00389 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
00390 {
00391   uint32_t deviceaddress = 0;
00392
00393   /* Process Locked */
00394   __HAL_LOCK(hnand);
00395
00396   /* Check the NAND controller state */
00397   if(hnand->State == HAL_NAND_STATE_BUSY)
00398   {
00399      return HAL_BUSY;
00400   }
00401
00402   /* Identify the device address */
00403   deviceaddress = NAND_DEVICE;
00404
00405   /* Update the NAND controller state */
00406   hnand->State = HAL_NAND_STATE_BUSY;
00407
00408   /* Send NAND reset command */
00409   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
00410
00411
00412   /* Update the NAND controller state */
00413   hnand->State = HAL_NAND_STATE_READY;
00414
00415   /* Process unlocked */
00416   __HAL_UNLOCK(hnand);
00417
00418   return HAL_OK;
00419
00420 }
00421
00422 /**
00423   * @brief  Read Page(s) from NAND memory block.
00424   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00425   *                the configuration information for NAND module.
00426   * @param  pAddress: pointer to NAND address structure
00427   * @param  pBuffer: pointer to destination read buffer
00428   * @param  NumPageToRead: number of pages to read from block
00429   * @retval HAL status
00430   */
00431 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
00432 {
00433   __IO uint32_t index  = 0;
00434   uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
00435   NAND_AddressTypeDef nandaddress;
00436   uint32_t addressoffset = 0;
00437
00438   /* Process Locked */
00439   __HAL_LOCK(hnand);
00440
00441   /* Check the NAND controller state */
00442   if(hnand->State == HAL_NAND_STATE_BUSY)
00443   {
00444      return HAL_BUSY;
00445   }
00446
00447   /* Identify the device address */
00448   deviceaddress = NAND_DEVICE;
00449
00450   /* Update the NAND controller state */
00451   hnand->State = HAL_NAND_STATE_BUSY;
00452
00453   /* Save the content of pAddress as it will be modified */
00454   nandaddress.Block     = pAddress->Block;
00455   nandaddress.Page      = pAddress->Page;
00456   nandaddress.Zone      = pAddress->Zone;
00457
00458   /* Page(s) read loop */
00459   while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
00460   {
00461     /* update the buffer size */
00462     size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
00463
00464     /* Get the address offset */
00465     addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
00466
00467     /* Send read page command sequence */
00468     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00469
00470     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00471     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
00472     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
00473     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
00474
00475     /* for 512 and 1 GB devices, 4th cycle is required */
00476     if(hnand->Info.BlockNbr >= 1024)
00477     {
00478       *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
00479     }
00480
00481     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00482
00483     /* Get Data into Buffer */
00484     for(; index < size; index++)
00485     {
00486       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
00487     }
00488
00489     /* Increment read pages number */
00490     numpagesread++;
00491
00492     /* Decrement pages to read */
00493     NumPageToRead--;
00494
00495     /* Increment the NAND address */
00496     addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
00497   }
00498
00499   /* Update the NAND controller state */
00500   hnand->State = HAL_NAND_STATE_READY;
00501
00502   /* Process unlocked */
00503   __HAL_UNLOCK(hnand);
00504
00505   return HAL_OK;
00506
00507 }
00508
00509 /**
00510   * @brief  Write Page(s) to NAND memory block.
00511   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00512   *                the configuration information for NAND module.
00513   * @param  pAddress: pointer to NAND address structure
00514   * @param  pBuffer: pointer to source buffer to write
00515   * @param  NumPageToWrite: number of pages to write to block
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
00519 {
00520   __IO uint32_t index = 0;
00521   uint32_t tickstart = 0;
00522   uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
00523   NAND_AddressTypeDef nandaddress;
00524   uint32_t addressoffset = 0;
00525
00526   /* Process Locked */
00527   __HAL_LOCK(hnand);
00528
00529   /* Check the NAND controller state */
00530   if(hnand->State == HAL_NAND_STATE_BUSY)
00531   {
00532      return HAL_BUSY;
00533   }
00534
00535   /* Identify the device address */
00536   deviceaddress = NAND_DEVICE;
00537
00538   /* Update the NAND controller state */
00539   hnand->State = HAL_NAND_STATE_BUSY;
00540
00541   /* Save the content of pAddress as it will be modified */
00542   nandaddress.Block     = pAddress->Block;
00543   nandaddress.Page      = pAddress->Page;
00544   nandaddress.Zone      = pAddress->Zone;
00545
00546   /* Page(s) write loop */
00547   while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
00548   {
00549     /* update the buffer size */
00550     size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
00551
00552     /* Get the address offset */
00553     addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
00554
00555     /* Send write page command sequence */
00556     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00557     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
00558
00559     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00560     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
00561     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
00562     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
00563
00564     /* for 512 and 1 GB devices, 4th cycle is required */
00565     if(hnand->Info.BlockNbr >= 1024)
00566     {
00567       *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
00568     }
00569
00570     /* Write data to memory */
00571     for(; index < size; index++)
00572     {
00573       *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
00574     }
00575
00576     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00577
00578     /* Get tick */
00579     tickstart = HAL_GetTick();
00580
00581     /* Read status until NAND is ready */
00582     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00583     {
00584       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00585       {
00586         return HAL_TIMEOUT;
00587       }
00588     }
00589
00590     /* Increment written pages number */
00591     numpageswritten++;
00592
00593     /* Decrement pages to write */
00594     NumPageToWrite--;
00595
00596     /* Increment the NAND address */
00597     addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
00598   }
00599
00600   /* Update the NAND controller state */
00601   hnand->State = HAL_NAND_STATE_READY;
00602
00603   /* Process unlocked */
00604   __HAL_UNLOCK(hnand);
00605
00606   return HAL_OK;
00607 }
00608
00609 /**
00610   * @brief  Read Spare area(s) from NAND memory.
00611   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00612   *                the configuration information for NAND module.
00613   * @param  pAddress: pointer to NAND address structure
00614   * @param  pBuffer: pointer to source buffer to write
00615   * @param  NumSpareAreaToRead: Number of spare area to read
00616   * @retval HAL status
00617 */
00618 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
00619 {
00620   __IO uint32_t index   = 0;
00621   uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
00622   NAND_AddressTypeDef nandaddress;
00623   uint32_t addressoffset = 0;
00624
00625   /* Process Locked */
00626   __HAL_LOCK(hnand);
00627
00628   /* Check the NAND controller state */
00629   if(hnand->State == HAL_NAND_STATE_BUSY)
00630   {
00631      return HAL_BUSY;
00632   }
00633
00634   /* Identify the device address */
00635   deviceaddress = NAND_DEVICE;
00636
00637   /* Update the NAND controller state */
00638   hnand->State = HAL_NAND_STATE_BUSY;
00639
00640   /* Save the content of pAddress as it will be modified */
00641   nandaddress.Block     = pAddress->Block;
00642   nandaddress.Page      = pAddress->Page;
00643   nandaddress.Zone      = pAddress->Zone;
00644
00645   /* Spare area(s) read loop */
00646   while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
00647   {
00648     /* update the buffer size */
00649     size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
00650
00651     /* Get the address offset */
00652     addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
00653
00654     /* Send read spare area command sequence */
00655     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
00656
00657     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00658     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
00659     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
00660     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
00661
00662     /* for 512 and 1 GB devices, 4th cycle is required */
00663     if(hnand->Info.BlockNbr >= 1024)
00664     {
00665       *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
00666     }
00667
00668     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
00669
00670     /* Get Data into Buffer */
00671     for ( ;index < size; index++)
00672     {
00673       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
00674     }
00675
00676     /* Increment read spare areas number */
00677     num_spare_area_read++;
00678
00679     /* Decrement spare areas to read */
00680     NumSpareAreaToRead--;
00681
00682     /* Increment the NAND address */
00683     addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
00684   }
00685
00686   /* Update the NAND controller state */
00687   hnand->State = HAL_NAND_STATE_READY;
00688
00689   /* Process unlocked */
00690   __HAL_UNLOCK(hnand);
00691
00692   return HAL_OK;
00693 }
00694
00695 /**
00696   * @brief  Write Spare area(s) to NAND memory.
00697   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00698   *                the configuration information for NAND module.
00699   * @param  pAddress: pointer to NAND address structure
00700   * @param  pBuffer: pointer to source buffer to write
00701   * @param  NumSpareAreaTowrite: number of spare areas to write to block
00702   * @retval HAL status
00703   */
00704 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
00705 {
00706   __IO uint32_t index = 0;
00707   uint32_t tickstart = 0;
00708   uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
00709   NAND_AddressTypeDef nandaddress;
00710   uint32_t addressoffset = 0;
00711
00712   /* Process Locked */
00713   __HAL_LOCK(hnand);
00714
00715   /* Check the NAND controller state */
00716   if(hnand->State == HAL_NAND_STATE_BUSY)
00717   {
00718      return HAL_BUSY;
00719   }
00720
00721   /* Identify the device address */
00722   deviceaddress = NAND_DEVICE;
00723
00724   /* Update the FMC_NAND controller state */
00725   hnand->State = HAL_NAND_STATE_BUSY;
00726
00727   /* Save the content of pAddress as it will be modified */
00728   nandaddress.Block     = pAddress->Block;
00729   nandaddress.Page      = pAddress->Page;
00730   nandaddress.Zone      = pAddress->Zone;
00731
00732   /* Spare area(s) write loop */
00733   while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
00734   {
00735     /* update the buffer size */
00736     size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
00737
00738     /* Get the address offset */
00739     addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
00740
00741     /* Send write Spare area command sequence */
00742     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
00743     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
00744
00745     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00746     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
00747     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
00748     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
00749
00750     /* for 512 and 1 GB devices, 4th cycle is required */
00751     if(hnand->Info.BlockNbr >= 1024)
00752     {
00753       *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
00754     }
00755
00756     /* Write data to memory */
00757     for(; index < size; index++)
00758     {
00759       *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
00760     }
00761
00762     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00763
00764     /* Get tick */
00765     tickstart = HAL_GetTick();
00766
00767     /* Read status until NAND is ready */
00768     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00769     {
00770       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00771       {
00772         return HAL_TIMEOUT;
00773       }
00774     }
00775
00776     /* Increment written spare areas number */
00777     num_spare_area_written++;
00778
00779     /* Decrement spare areas to write */
00780     NumSpareAreaTowrite--;
00781
00782     /* Increment the NAND address */
00783     addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
00784   }
00785
00786   /* Update the NAND controller state */
00787   hnand->State = HAL_NAND_STATE_READY;
00788
00789   /* Process unlocked */
00790   __HAL_UNLOCK(hnand);
00791
00792   return HAL_OK;
00793 }
00794
00795 /**
00796   * @brief  NAND memory Block erase.
00797   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00798   *                the configuration information for NAND module.
00799   * @param  pAddress: pointer to NAND address structure
00800   * @retval HAL status
00801   */
00802 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
00803 {
00804   uint32_t deviceaddress = 0;
00805   uint32_t tickstart = 0;
00806
00807   /* Process Locked */
00808   __HAL_LOCK(hnand);
00809
00810   /* Check the NAND controller state */
00811   if(hnand->State == HAL_NAND_STATE_BUSY)
00812   {
00813      return HAL_BUSY;
00814   }
00815
00816   /* Identify the device address */
00817   deviceaddress = NAND_DEVICE;
00818
00819   /* Update the NAND controller state */
00820   hnand->State = HAL_NAND_STATE_BUSY;
00821
00822   /* Send Erase block command sequence */
00823   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
00824
00825   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00826   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00827   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00828
00829   /* for 512 and 1 GB devices, 4th cycle is required */
00830   if(hnand->Info.BlockNbr >= 1024)
00831   {
00832     *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
00833   }
00834
00835   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
00836
00837   /* Update the NAND controller state */
00838   hnand->State = HAL_NAND_STATE_READY;
00839
00840   /* Get tick */
00841   tickstart = HAL_GetTick();
00842
00843   /* Read status until NAND is ready */
00844   while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00845   {
00846     if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00847     {
00848       /* Process unlocked */
00849       __HAL_UNLOCK(hnand);
00850
00851       return HAL_TIMEOUT;
00852     }
00853   }
00854
00855   /* Process unlocked */
00856   __HAL_UNLOCK(hnand);
00857
00858   return HAL_OK;
00859 }
00860
00861 /**
00862   * @brief  NAND memory read status.
00863   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00864   *                the configuration information for NAND module.
00865   * @retval NAND status
00866   */
00867 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
00868 {
00869   uint32_t data = 0;
00870   uint32_t deviceaddress = 0;
00871
00872   /* Prevent unused argument(s) compilation warning */
00873   UNUSED(hnand);
00874
00875   /* Identify the device address */
00876    deviceaddress = NAND_DEVICE;
00877
00878   /* Send Read status operation command */
00879   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
00880
00881   /* Read status register data */
00882   data = *(__IO uint8_t *)deviceaddress;
00883
00884   /* Return the status */
00885   if((data & NAND_ERROR) == NAND_ERROR)
00886   {
00887     return NAND_ERROR;
00888   }
00889   else if((data & NAND_READY) == NAND_READY)
00890   {
00891     return NAND_READY;
00892   }
00893
00894   return NAND_BUSY;
00895 }
00896
00897 /**
00898   * @brief  Increment the NAND memory address.
00899   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00900   *                the configuration information for NAND module.
00901   * @param pAddress: pointer to NAND address structure
00902   * @retval The new status of the increment address operation. It can be:
00903   *           - NAND_VALID_ADDRESS: When the new address is valid address
00904   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
00905   */
00906 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
00907 {
00908   uint32_t status = NAND_VALID_ADDRESS;
00909
00910   /* Increment page address */
00911   pAddress->Page++;
00912
00913   /* Check NAND address is valid */
00914   if(pAddress->Page == hnand->Info.BlockSize)
00915   {
00916     pAddress->Page = 0;
00917     pAddress->Block++;
00918
00919     if(pAddress->Block == hnand->Info.ZoneSize)
00920     {
00921       pAddress->Block = 0;
00922       pAddress->Zone++;
00923
00924       if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
00925       {
00926         status = NAND_INVALID_ADDRESS;
00927       }
00928     }
00929   }
00930
00931   return (status);
00932 }
00933 /**
00934   * @}
00935   */
00936
00937 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
00938  *  @brief   management functions
00939  *
00940 @verbatim
00941   ==============================================================================
00942                          ##### NAND Control functions #####
00943   ==============================================================================
00944   [..]
00945     This subsection provides a set of functions allowing to control dynamically
00946     the NAND interface.
00947
00948 @endverbatim
00949   * @{
00950   */
00951
00952
00953 /**
00954   * @brief  Enable dynamically NAND ECC feature.
00955   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00956   *                the configuration information for NAND module.
00957   * @retval HAL status
00958   */
00959 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
00960 {
00961   /* Check the NAND controller state */
00962   if(hnand->State == HAL_NAND_STATE_BUSY)
00963   {
00964      return HAL_BUSY;
00965   }
00966
00967   /* Update the NAND state */
00968   hnand->State = HAL_NAND_STATE_BUSY;
00969
00970   /* Enable ECC feature */
00971   FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
00972
00973   /* Update the NAND state */
00974   hnand->State = HAL_NAND_STATE_READY;
00975
00976   return HAL_OK;
00977 }
00978
00979 /**
00980   * @brief  Disable dynamically NAND ECC feature.
00981   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00982   *                the configuration information for NAND module.
00983   * @retval HAL status
00984   */
00985 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
00986 {
00987   /* Check the NAND controller state */
00988   if(hnand->State == HAL_NAND_STATE_BUSY)
00989   {
00990      return HAL_BUSY;
00991   }
00992
00993   /* Update the NAND state */
00994   hnand->State = HAL_NAND_STATE_BUSY;
00995
00996   /* Disable ECC feature */
00997   FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
00998
00999   /* Update the NAND state */
01000   hnand->State = HAL_NAND_STATE_READY;
01001
01002   return HAL_OK;
01003 }
01004
01005 /**
01006   * @brief  Disable dynamically NAND ECC feature.
01007   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01008   *                the configuration information for NAND module.
01009   * @param  ECCval: pointer to ECC value
01010   * @param  Timeout: maximum timeout to wait
01011   * @retval HAL status
01012   */
01013 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
01014 {
01015   HAL_StatusTypeDef status = HAL_OK;
01016
01017   /* Check the NAND controller state */
01018   if(hnand->State == HAL_NAND_STATE_BUSY)
01019   {
01020      return HAL_BUSY;
01021   }
01022
01023   /* Update the NAND state */
01024   hnand->State = HAL_NAND_STATE_BUSY;
01025
01026   /* Get NAND ECC value */
01027   status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
01028
01029   /* Update the NAND state */
01030   hnand->State = HAL_NAND_STATE_READY;
01031
01032   return status;
01033 }
01034
01035 /**
01036   * @}
01037   */
01038
01039
01040 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
01041  *  @brief   Peripheral State functions
01042  *
01043 @verbatim
01044   ==============================================================================
01045                          ##### NAND State functions #####
01046   ==============================================================================
01047   [..]
01048     This subsection permits to get in run-time the status of the NAND controller
01049     and the data flow.
01050
01051 @endverbatim
01052   * @{
01053   */
01054
01055 /**
01056   * @brief  Return the NAND handle state.
01057   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01058   *                the configuration information for NAND module.
01059   * @retval HAL state
01060   */
01061 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
01062 {
01063   /* Return NAND handle state */
01064   return hnand->State;
01065 }
01066
01067 /**
01068   * @}
01069   */
01070
01071 /**
01072   * @}
01073   */
01074
01075 /** @addtogroup NAND_Private_Functions
01076   * @{
01077   */
01078
01079 /**
01080   * @brief  Increment the NAND memory address.
01081   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01082   *                the configuration information for NAND module.
01083   * @param  Address: address to be incremented.
01084   * @retval The new status of the increment address operation. It can be:
01085   *              - NAND_VALID_ADDRESS: When the new address is valid address
01086   *              - NAND_INVALID_ADDRESS: When the new address is invalid address
01087   */
01088 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
01089 {
01090   uint32_t status = NAND_VALID_ADDRESS;
01091
01092   Address->Page++;
01093
01094   if(Address->Page == hnand->Info.BlockSize)
01095   {
01096     Address->Page = 0;
01097     Address->Block++;
01098
01099     if(Address->Block == hnand->Info.ZoneSize)
01100     {
01101       Address->Block = 0;
01102       Address->Zone++;
01103
01104       if(Address->Zone == hnand->Info.BlockNbr)
01105       {
01106         status = NAND_INVALID_ADDRESS;
01107       }
01108     }
01109   }
01110
01111   return (status);
01112 }
01113
01114 /**
01115   * @}
01116   */
01117
01118 /**
01119   * @}
01120   */
01121
01122 #endif /* HAL_NAND_MODULE_ENABLED  */
01123
01124 /**
01125   * @}
01126   */
01127
01128 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01129
01130 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_nand.h Source File

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stm32l4xx_hal_nand.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_nand.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of NAND HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_NAND_H
00040 #define __STM32L4xx_HAL_NAND_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32l4xx_ll_fmc.h"
00050
00051 /** @addtogroup STM32L4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup NAND
00056   * @{
00057   */
00058
00059 /** @addtogroup NAND_Private_Constants
00060   * @{
00061   */
00062
00063 #define NAND_DEVICE                FMC_BANK3
00064 #define NAND_WRITE_TIMEOUT         ((uint32_t)1000)
00065
00066 #define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
00067 #define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
00068
00069 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
00070 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
00071 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
00072 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
00073
00074 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
00075 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
00076 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
00077 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
00078 #define NAND_CMD_READID            ((uint8_t)0x90)
00079 #define NAND_CMD_STATUS            ((uint8_t)0x70)
00080 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
00081 #define NAND_CMD_RESET             ((uint8_t)0xFF)
00082
00083 /* NAND memory status */
00084 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
00085 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
00086 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
00087 #define NAND_BUSY                  ((uint32_t)0x00000000)
00088 #define NAND_ERROR                 ((uint32_t)0x00000001)
00089 #define NAND_READY                 ((uint32_t)0x00000040)
00090
00091 /**
00092   * @}
00093   */
00094
00095 /** @addtogroup NAND_Private_Macros
00096   * @{
00097   */
00098
00099 /**
00100   * @brief  NAND memory address computation.
00101   * @param  __ADDRESS__: NAND memory address.
00102   * @param  __HANDLE__: NAND handle.
00103   * @retval NAND Raw address value
00104   */
00105 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
00106                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
00107
00108 /**
00109   * @brief  NAND memory address cycling.
00110   * @param  __ADDRESS__: NAND memory address.
00111   * @retval NAND address cycling value.
00112   */
00113 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
00114 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
00115 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
00116 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
00117
00118 /**
00119   * @}
00120   */
00121
00122 /* Exported typedef ----------------------------------------------------------*/
00123 /* Exported types ------------------------------------------------------------*/
00124 /** @defgroup NAND_Exported_Types NAND Exported Types
00125   * @{
00126   */
00127
00128 /**
00129   * @brief  HAL NAND State structures definition
00130   */
00131 typedef enum
00132 {
00133   HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
00134   HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
00135   HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
00136   HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
00137 }HAL_NAND_StateTypeDef;
00138
00139 /**
00140   * @brief  NAND Memory electronic signature Structure definition
00141   */
00142 typedef struct
00143 {
00144   /*<! NAND memory electronic signature maker and device IDs */
00145
00146   uint8_t Maker_Id;
00147
00148   uint8_t Device_Id;
00149
00150   uint8_t Third_Id;
00151
00152   uint8_t Fourth_Id;
00153 }NAND_IDTypeDef;
00154
00155 /**
00156   * @brief  NAND Memory address Structure definition
00157   */
00158 typedef struct
00159 {
00160   uint16_t Page;   /*!< NAND memory Page address  */
00161
00162   uint16_t Zone;   /*!< NAND memory Zone address  */
00163
00164   uint16_t Block;  /*!< NAND memory Block address */
00165
00166 }NAND_AddressTypeDef;
00167
00168 /**
00169   * @brief  NAND Memory info Structure definition
00170   */
00171 typedef struct
00172 {
00173   uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
00174
00175   uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
00176
00177   uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
00178
00179   uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
00180
00181   uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
00182 }NAND_InfoTypeDef;
00183
00184 /**
00185   * @brief  NAND handle Structure definition
00186   */
00187 typedef struct
00188 {
00189   FMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
00190
00191   FMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
00192
00193   HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
00194
00195   __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
00196
00197   NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
00198 }NAND_HandleTypeDef;
00199
00200 /**
00201   * @}
00202   */
00203
00204 /* Exported constants --------------------------------------------------------*/
00205 /* Exported macro ------------------------------------------------------------*/
00206 /** @defgroup NAND_Exported_Macros NAND Exported Macros
00207  * @{
00208  */
00209
00210 /** @brief Reset NAND handle state.
00211   * @param  __HANDLE__: specifies the NAND handle.
00212   * @retval None
00213   */
00214 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
00215
00216 /**
00217   * @}
00218   */
00219
00220 /* Exported functions --------------------------------------------------------*/
00221 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
00222   * @{
00223   */
00224
00225 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00226   * @{
00227   */
00228
00229 /* Initialization/de-initialization functions  ********************************/
00230 HAL_StatusTypeDef   HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
00231 HAL_StatusTypeDef   HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
00232 void                HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
00233 void                HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
00234 void                HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
00235 void                HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
00236
00237 /**
00238   * @}
00239   */
00240
00241 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
00242   * @{
00243   */
00244
00245 /* IO operation functions  ****************************************************/
00246 HAL_StatusTypeDef   HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
00247 HAL_StatusTypeDef   HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
00248 HAL_StatusTypeDef   HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
00249 HAL_StatusTypeDef   HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
00250 HAL_StatusTypeDef   HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
00251 HAL_StatusTypeDef   HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
00252 HAL_StatusTypeDef   HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00253 uint32_t            HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00254 uint32_t            HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00255
00256 /**
00257   * @}
00258   */
00259
00260 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
00261   * @{
00262   */
00263
00264 /* NAND Control functions  ****************************************************/
00265 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
00266 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
00267 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
00268
00269 /**
00270   * @}
00271   */
00272
00273 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
00274   * @{
00275   */
00276
00277 /* NAND State functions *******************************************************/
00278 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
00279 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 /**
00294   * @}
00295   */
00296
00297 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00298
00299 #ifdef __cplusplus
00300 }
00301 #endif
00302
00303 #endif /* __STM32L4xx_HAL_NAND_H */
00304
00305 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_nor.c Source File

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stm32l4xx_hal_nor.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_nor.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   NOR HAL module driver.
00008   *          This file provides a generic firmware to drive NOR memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                      ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016       This driver is a generic layered driver which contains a set of APIs used to
00017       control NOR flash memories. It uses the FMC layer functions to interface
00018       with NOR devices. This driver is used as follows:
00019
00020       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
00021           with control and timing parameters for both normal and extended mode.
00022
00023       (+) Read NOR flash memory manufacturer code and device IDs using the function
00024           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
00025           structure declared by the function caller.
00026
00027       (+) Access NOR flash memory by read/write data unit operations using the functions
00028           HAL_NOR_Read(), HAL_NOR_Program().
00029
00030       (+) Perform NOR flash erase block/chip operations using the functions
00031           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
00032
00033       (+) Read the NOR flash CFI (common flash interface) IDs using the function
00034           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
00035           structure declared by the function caller.
00036
00037       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
00038           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
00039
00040       (+) You can monitor the NOR device HAL state by calling the function
00041           HAL_NOR_GetState()
00042     [..]
00043      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
00044          If a NOR flash device contains different operations and/or implementations,
00045          it should be implemented separately.
00046
00047      *** NOR HAL driver macros list ***
00048      =============================================
00049      [..]
00050        Below the list of most used macros in NOR HAL driver.
00051
00052       (+) NOR_WRITE : NOR memory write data to specified address
00053
00054   @endverbatim
00055   ******************************************************************************
00056   * @attention
00057   *
00058   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00059   *
00060   * Redistribution and use in source and binary forms, with or without modification,
00061   * are permitted provided that the following conditions are met:
00062   *   1. Redistributions of source code must retain the above copyright notice,
00063   *      this list of conditions and the following disclaimer.
00064   *   2. Redistributions in binary form must reproduce the above copyright notice,
00065   *      this list of conditions and the following disclaimer in the documentation
00066   *      and/or other materials provided with the distribution.
00067   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00068   *      may be used to endorse or promote products derived from this software
00069   *      without specific prior written permission.
00070   *
00071   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00072   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00073   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00074   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00075   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00076   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00077   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00078   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00079   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00080   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00081   *
00082   ******************************************************************************
00083   */
00084
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32l4xx_hal.h"
00087
00088 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00089
00090 /** @addtogroup STM32L4xx_HAL_Driver
00091   * @{
00092   */
00093
00094 #ifdef HAL_NOR_MODULE_ENABLED
00095
00096 /** @defgroup NOR NOR
00097   * @brief NOR HAL module driver
00098   * @{
00099   */
00100 /* Private typedef -----------------------------------------------------------*/
00101 /* Private define ------------------------------------------------------------*/
00102 /** @defgroup NOR_Private_Constants NOR Private Constants
00103   * @{
00104   */
00105
00106 /* Constants to define address to set to write a command */
00107 #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
00108 #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
00109 #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
00110 #define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
00111 #define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
00112 #define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
00113 #define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
00114
00115 /* Constants to define data to program a command */
00116 #define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
00117 #define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
00118 #define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
00119 #define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
00120 #define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
00121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
00122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
00123 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
00124 #define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
00125 #define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
00126
00127 #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
00128 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
00129 #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
00130
00131 /* Mask on NOR STATUS REGISTER */
00132 #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
00133 #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
00134
00135 /**
00136   * @}
00137   */
00138
00139 /* Private macro -------------------------------------------------------------*/
00140 /** @defgroup NOR_Private_Macros NOR Private Macros
00141   * @{
00142   */
00143
00144 /**
00145   * @}
00146   */
00147
00148 /* Private variables ---------------------------------------------------------*/
00149
00150 /** @defgroup NOR_Private_Variables NOR Private Variables
00151   * @{
00152   */
00153
00154 static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
00155
00156 /**
00157   * @}
00158   */
00159
00160 /* Exported functions ---------------------------------------------------------*/
00161
00162 /** @defgroup NOR_Exported_Functions NOR Exported Functions
00163   * @{
00164   */
00165
00166 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00167   * @brief    Initialization and Configuration functions
00168   *
00169   @verbatim
00170   ==============================================================================
00171            ##### NOR Initialization and de-initialization functions #####
00172   ==============================================================================
00173   [..]
00174     This section provides functions allowing to initialize/de-initialize
00175     the NOR memory
00176
00177 @endverbatim
00178   * @{
00179   */
00180
00181 /**
00182   * @brief  Perform the NOR memory Initialization sequence.
00183   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00184   *                the configuration information for NOR module.
00185   * @param  Timing: pointer to NOR control timing structure
00186   * @param  ExtTiming: pointer to NOR extended mode timing structure
00187   * @retval HAL status
00188   */
00189 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00190 {
00191   /* Check the NOR handle parameter */
00192   if(hnor == NULL)
00193   {
00194      return HAL_ERROR;
00195   }
00196
00197   if(hnor->State == HAL_NOR_STATE_RESET)
00198   {
00199     /* Allocate lock resource and initialize it */
00200     hnor->Lock = HAL_UNLOCKED;
00201
00202     /* Initialize the low level hardware (MSP) */
00203     HAL_NOR_MspInit(hnor);
00204   }
00205
00206   /* Initialize NOR control Interface */
00207   FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
00208
00209   /* Initialize NOR timing Interface */
00210   FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
00211
00212   /* Initialize NOR extended mode timing Interface */
00213   FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
00214
00215   /* Enable the NORSRAM device */
00216   __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
00217
00218   /* Initialize NOR Memory Data Width*/
00219   if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
00220   {
00221     uwNORMemoryDataWidth = NOR_MEMORY_8B;
00222   }
00223   else
00224   {
00225     uwNORMemoryDataWidth = NOR_MEMORY_16B;
00226   }
00227
00228   /* Check the NOR controller state */
00229   hnor->State = HAL_NOR_STATE_READY;
00230
00231   return HAL_OK;
00232 }
00233
00234 /**
00235   * @brief  Perform NOR memory De-Initialization sequence.
00236   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00237   *                the configuration information for NOR module.
00238   * @retval HAL status
00239   */
00240 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
00241 {
00242   /* De-Initialize the low level hardware (MSP) */
00243   HAL_NOR_MspDeInit(hnor);
00244
00245   /* Configure the NOR registers with their reset values */
00246   FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
00247
00248   /* Update the NOR controller state */
00249   hnor->State = HAL_NOR_STATE_RESET;
00250
00251   /* Release Lock */
00252   __HAL_UNLOCK(hnor);
00253
00254   return HAL_OK;
00255 }
00256
00257 /**
00258   * @brief  Initialize the NOR MSP.
00259   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00260   *                the configuration information for NOR module.
00261   * @retval None
00262   */
00263 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
00264 {
00265   /* Prevent unused argument(s) compilation warning */
00266   UNUSED(hnor);
00267
00268   /* NOTE : This function should not be modified, when the callback is needed,
00269             the HAL_NOR_MspInit could be implemented in the user file
00270    */
00271 }
00272
00273 /**
00274   * @brief  DeInitialize the NOR MSP.
00275   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00276   *                the configuration information for NOR module.
00277   * @retval None
00278   */
00279 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
00280 {
00281   /* Prevent unused argument(s) compilation warning */
00282   UNUSED(hnor);
00283
00284   /* NOTE : This function should not be modified, when the callback is needed,
00285             the HAL_NOR_MspDeInit could be implemented in the user file
00286    */
00287 }
00288
00289 /**
00290   * @brief  NOR MSP Wait for Ready/Busy signal.
00291   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00292   *                the configuration information for NOR module.
00293   * @param  Timeout: Maximum timeout value
00294   * @retval None
00295   */
00296 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
00297 {
00298   /* Prevent unused argument(s) compilation warning */
00299   UNUSED(hnor);
00300   UNUSED(Timeout);
00301
00302   /* NOTE : This function should not be modified, when the callback is needed,
00303             the HAL_NOR_MspWait could be implemented in the user file
00304    */
00305 }
00306
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
00312   * @brief    Input Output and memory control functions
00313   *
00314   @verbatim
00315   ==============================================================================
00316                 ##### NOR Input and Output functions #####
00317   ==============================================================================
00318   [..]
00319     This section provides functions allowing to use and control the NOR memory
00320
00321 @endverbatim
00322   * @{
00323   */
00324
00325 /**
00326   * @brief  Read NOR flash IDs.
00327   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00328   *                the configuration information for NOR module.
00329   * @param  pNOR_ID : pointer to NOR ID structure
00330   * @retval HAL status
00331   */
00332 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
00333 {
00334   uint32_t deviceaddress = 0;
00335
00336   /* Process Locked */
00337   __HAL_LOCK(hnor);
00338
00339   /* Check the NOR controller state */
00340   if(hnor->State == HAL_NOR_STATE_BUSY)
00341   {
00342      return HAL_BUSY;
00343   }
00344
00345   /* Select the NOR device address */
00346   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00347   {
00348     deviceaddress = NOR_MEMORY_ADRESS1;
00349   }
00350   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00351   {
00352     deviceaddress = NOR_MEMORY_ADRESS2;
00353   }
00354   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00355   {
00356     deviceaddress = NOR_MEMORY_ADRESS3;
00357   }
00358   else /* FMC_NORSRAM_BANK4 */
00359   {
00360     deviceaddress = NOR_MEMORY_ADRESS4;
00361   }
00362
00363   /* Update the NOR controller state */
00364   hnor->State = HAL_NOR_STATE_BUSY;
00365
00366   /* Send read ID command */
00367   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00368   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00369   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
00370
00371   /* Read the NOR IDs */
00372   pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
00373   pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
00374   pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
00375   pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
00376
00377   /* Check the NOR controller state */
00378   hnor->State = HAL_NOR_STATE_READY;
00379
00380   /* Process unlocked */
00381   __HAL_UNLOCK(hnor);
00382
00383   return HAL_OK;
00384 }
00385
00386 /**
00387   * @brief  Return the NOR memory to Read mode.
00388   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00389   *                the configuration information for NOR module.
00390   * @retval HAL status
00391   */
00392 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
00393 {
00394   uint32_t deviceaddress = 0;
00395
00396   /* Process Locked */
00397   __HAL_LOCK(hnor);
00398
00399   /* Check the NOR controller state */
00400   if(hnor->State == HAL_NOR_STATE_BUSY)
00401   {
00402      return HAL_BUSY;
00403   }
00404
00405   /* Select the NOR device address */
00406   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00407   {
00408     deviceaddress = NOR_MEMORY_ADRESS1;
00409   }
00410   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00411   {
00412     deviceaddress = NOR_MEMORY_ADRESS2;
00413   }
00414   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00415   {
00416     deviceaddress = NOR_MEMORY_ADRESS3;
00417   }
00418   else /* FMC_NORSRAM_BANK4 */
00419   {
00420     deviceaddress = NOR_MEMORY_ADRESS4;
00421   }
00422
00423   NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
00424
00425   /* Check the NOR controller state */
00426   hnor->State = HAL_NOR_STATE_READY;
00427
00428   /* Process unlocked */
00429   __HAL_UNLOCK(hnor);
00430
00431   return HAL_OK;
00432 }
00433
00434 /**
00435   * @brief  Read data from NOR memory.
00436   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00437   *                the configuration information for NOR module.
00438   * @param  pAddress: pointer to Device address
00439   * @param  pData : pointer to read data
00440   * @retval HAL status
00441   */
00442 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00443 {
00444   uint32_t deviceaddress = 0;
00445
00446   /* Process Locked */
00447   __HAL_LOCK(hnor);
00448
00449   /* Check the NOR controller state */
00450   if(hnor->State == HAL_NOR_STATE_BUSY)
00451   {
00452      return HAL_BUSY;
00453   }
00454
00455   /* Select the NOR device address */
00456   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00457   {
00458     deviceaddress = NOR_MEMORY_ADRESS1;
00459   }
00460   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00461   {
00462     deviceaddress = NOR_MEMORY_ADRESS2;
00463   }
00464   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00465   {
00466     deviceaddress = NOR_MEMORY_ADRESS3;
00467   }
00468   else /* FMC_NORSRAM_BANK4 */
00469   {
00470     deviceaddress = NOR_MEMORY_ADRESS4;
00471   }
00472
00473   /* Update the NOR controller state */
00474   hnor->State = HAL_NOR_STATE_BUSY;
00475
00476   /* Send read data command */
00477   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00478   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00479   NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
00480
00481   /* Read the data */
00482   *pData = *(__IO uint32_t *)(uint32_t)pAddress;
00483
00484   /* Check the NOR controller state */
00485   hnor->State = HAL_NOR_STATE_READY;
00486
00487   /* Process unlocked */
00488   __HAL_UNLOCK(hnor);
00489
00490   return HAL_OK;
00491 }
00492
00493 /**
00494   * @brief  Program data to NOR memory.
00495   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00496   *                the configuration information for NOR module.
00497   * @param  pAddress: Device address
00498   * @param  pData : pointer to the data to write
00499   * @retval HAL status
00500   */
00501 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00502 {
00503   uint32_t deviceaddress = 0;
00504
00505   /* Process Locked */
00506   __HAL_LOCK(hnor);
00507
00508   /* Check the NOR controller state */
00509   if(hnor->State == HAL_NOR_STATE_BUSY)
00510   {
00511      return HAL_BUSY;
00512   }
00513
00514   /* Select the NOR device address */
00515   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00516   {
00517     deviceaddress = NOR_MEMORY_ADRESS1;
00518   }
00519   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00520   {
00521     deviceaddress = NOR_MEMORY_ADRESS2;
00522   }
00523   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00524   {
00525     deviceaddress = NOR_MEMORY_ADRESS3;
00526   }
00527   else /* FMC_NORSRAM_BANK4 */
00528   {
00529     deviceaddress = NOR_MEMORY_ADRESS4;
00530   }
00531
00532   /* Update the NOR controller state */
00533   hnor->State = HAL_NOR_STATE_BUSY;
00534
00535   /* Send program data command */
00536   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00537   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00538   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
00539
00540   /* Write the data */
00541   NOR_WRITE(pAddress, *pData);
00542
00543   /* Check the NOR controller state */
00544   hnor->State = HAL_NOR_STATE_READY;
00545
00546   /* Process unlocked */
00547   __HAL_UNLOCK(hnor);
00548
00549   return HAL_OK;
00550 }
00551
00552 /**
00553   * @brief  Read a block of data from the FMC NOR memory.
00554   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00555   *                the configuration information for NOR module.
00556   * @param  uwAddress: NOR memory internal address to read from.
00557   * @param  pData: pointer to the buffer that receives the data read from the
00558   *         NOR memory.
00559   * @param  uwBufferSize : number of Half word to read.
00560   * @retval HAL status
00561   */
00562 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00563 {
00564   uint32_t deviceaddress = 0;
00565
00566   /* Process Locked */
00567   __HAL_LOCK(hnor);
00568
00569   /* Check the NOR controller state */
00570   if(hnor->State == HAL_NOR_STATE_BUSY)
00571   {
00572      return HAL_BUSY;
00573   }
00574
00575   /* Select the NOR device address */
00576   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00577   {
00578     deviceaddress = NOR_MEMORY_ADRESS1;
00579   }
00580   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00581   {
00582     deviceaddress = NOR_MEMORY_ADRESS2;
00583   }
00584   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00585   {
00586     deviceaddress = NOR_MEMORY_ADRESS3;
00587   }
00588   else /* FMC_NORSRAM_BANK4 */
00589   {
00590     deviceaddress = NOR_MEMORY_ADRESS4;
00591   }
00592
00593   /* Update the NOR controller state */
00594   hnor->State = HAL_NOR_STATE_BUSY;
00595
00596   /* Send read data command */
00597   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00598   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00599   NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
00600
00601   /* Read buffer */
00602   while( uwBufferSize > 0)
00603   {
00604     *pData++ = *(__IO uint16_t *)uwAddress;
00605     uwAddress += 2;
00606     uwBufferSize--;
00607   }
00608
00609   /* Check the NOR controller state */
00610   hnor->State = HAL_NOR_STATE_READY;
00611
00612   /* Process unlocked */
00613   __HAL_UNLOCK(hnor);
00614
00615   return HAL_OK;
00616 }
00617
00618 /**
00619   * @brief  Write a half-word buffer to the FMC NOR memory. This function
00620   *         must be used only with S29GL128P NOR memory.
00621   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00622   *                the configuration information for NOR module.
00623   * @param  uwAddress: NOR memory internal address from which the data
00624   * @note   Some NOR memory need Address aligned to xx bytes (can be aligned to
00625   *          64 bytes boundary for example).
00626   * @param  pData: pointer to source data buffer.
00627   * @param  uwBufferSize: number of Half words to write.
00628   * @note   The maximum buffer size allowed is NOR memory dependent
00629   *         (can be 64 Bytes max for example).
00630   * @retval HAL status
00631   */
00632 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00633 {
00634   uint16_t * p_currentaddress = (uint16_t *)NULL;
00635   uint16_t * p_endaddress = (uint16_t *)NULL;
00636   uint32_t lastloadedaddress = 0, deviceaddress = 0;
00637
00638   /* Process Locked */
00639   __HAL_LOCK(hnor);
00640
00641   /* Check the NOR controller state */
00642   if(hnor->State == HAL_NOR_STATE_BUSY)
00643   {
00644      return HAL_BUSY;
00645   }
00646
00647   /* Select the NOR device address */
00648   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00649   {
00650     deviceaddress = NOR_MEMORY_ADRESS1;
00651   }
00652   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00653   {
00654     deviceaddress = NOR_MEMORY_ADRESS2;
00655   }
00656   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00657   {
00658     deviceaddress = NOR_MEMORY_ADRESS3;
00659   }
00660   else /* FMC_NORSRAM_BANK4 */
00661   {
00662     deviceaddress = NOR_MEMORY_ADRESS4;
00663   }
00664
00665   /* Update the NOR controller state */
00666   hnor->State = HAL_NOR_STATE_BUSY;
00667
00668   /* Initialize variables */
00669   p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
00670   p_endaddress      = p_currentaddress + (uwBufferSize-1);
00671   lastloadedaddress = (uint32_t)(uwAddress);
00672
00673   /* Issue unlock command sequence */
00674   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00675   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00676
00677   /* Write Buffer Load Command */
00678   NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
00679   NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
00680
00681   /* Load Data into NOR Buffer */
00682   while(p_currentaddress <= p_endaddress)
00683   {
00684     /* Store last loaded address & data value (for polling) */
00685     lastloadedaddress = (uint32_t)p_currentaddress;
00686
00687     NOR_WRITE(p_currentaddress, *pData++);
00688
00689     p_currentaddress++;
00690   }
00691
00692   NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
00693
00694   /* Check the NOR controller state */
00695   hnor->State = HAL_NOR_STATE_READY;
00696
00697   /* Process unlocked */
00698   __HAL_UNLOCK(hnor);
00699
00700   return HAL_OK;
00701
00702 }
00703
00704 /**
00705   * @brief  Erase the specified block of the NOR memory.
00706   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00707   *                the configuration information for NOR module.
00708   * @param  BlockAddress : Block to erase address
00709   * @param  Address: Device address
00710   * @retval HAL status
00711   */
00712 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
00713 {
00714   uint32_t deviceaddress = 0;
00715
00716   /* Process Locked */
00717   __HAL_LOCK(hnor);
00718
00719   /* Check the NOR controller state */
00720   if(hnor->State == HAL_NOR_STATE_BUSY)
00721   {
00722      return HAL_BUSY;
00723   }
00724
00725   /* Select the NOR device address */
00726   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00727   {
00728     deviceaddress = NOR_MEMORY_ADRESS1;
00729   }
00730   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00731   {
00732     deviceaddress = NOR_MEMORY_ADRESS2;
00733   }
00734   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00735   {
00736     deviceaddress = NOR_MEMORY_ADRESS3;
00737   }
00738   else /* FMC_NORSRAM_BANK4 */
00739   {
00740     deviceaddress = NOR_MEMORY_ADRESS4;
00741   }
00742
00743   /* Update the NOR controller state */
00744   hnor->State = HAL_NOR_STATE_BUSY;
00745
00746   /* Send block erase command sequence */
00747   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00748   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00749   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00750   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00751   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00752   NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
00753
00754   /* Check the NOR memory status and update the controller state */
00755   hnor->State = HAL_NOR_STATE_READY;
00756
00757   /* Process unlocked */
00758   __HAL_UNLOCK(hnor);
00759
00760   return HAL_OK;
00761
00762 }
00763
00764 /**
00765   * @brief  Erase the entire NOR chip.
00766   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00767   *                the configuration information for NOR module.
00768   * @param  Address : Device address
00769   * @retval HAL status
00770   */
00771 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
00772 {
00773   uint32_t deviceaddress = 0;
00774
00775   /* Prevent unused argument(s) compilation warning */
00776   UNUSED(Address);
00777
00778   /* Process Locked */
00779   __HAL_LOCK(hnor);
00780
00781   /* Check the NOR controller state */
00782   if(hnor->State == HAL_NOR_STATE_BUSY)
00783   {
00784      return HAL_BUSY;
00785   }
00786
00787   /* Select the NOR device address */
00788   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00789   {
00790     deviceaddress = NOR_MEMORY_ADRESS1;
00791   }
00792   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00793   {
00794     deviceaddress = NOR_MEMORY_ADRESS2;
00795   }
00796   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00797   {
00798     deviceaddress = NOR_MEMORY_ADRESS3;
00799   }
00800   else /* FMC_NORSRAM_BANK4 */
00801   {
00802     deviceaddress = NOR_MEMORY_ADRESS4;
00803   }
00804
00805   /* Update the NOR controller state */
00806   hnor->State = HAL_NOR_STATE_BUSY;
00807
00808   /* Send NOR chip erase command sequence */
00809   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00810   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00811   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00812   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00813   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00814   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
00815
00816   /* Check the NOR memory status and update the controller state */
00817   hnor->State = HAL_NOR_STATE_READY;
00818
00819   /* Process unlocked */
00820   __HAL_UNLOCK(hnor);
00821
00822   return HAL_OK;
00823 }
00824
00825 /**
00826   * @brief  Read NOR flash CFI IDs.
00827   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00828   *                the configuration information for NOR module.
00829   * @param  pNOR_CFI : pointer to NOR CFI IDs structure
00830   * @retval HAL status
00831   */
00832 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
00833 {
00834   uint32_t deviceaddress = 0;
00835
00836   /* Process Locked */
00837   __HAL_LOCK(hnor);
00838
00839   /* Check the NOR controller state */
00840   if(hnor->State == HAL_NOR_STATE_BUSY)
00841   {
00842      return HAL_BUSY;
00843   }
00844
00845   /* Select the NOR device address */
00846   if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
00847   {
00848     deviceaddress = NOR_MEMORY_ADRESS1;
00849   }
00850   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
00851   {
00852     deviceaddress = NOR_MEMORY_ADRESS2;
00853   }
00854   else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
00855   {
00856     deviceaddress = NOR_MEMORY_ADRESS3;
00857   }
00858   else /* FMC_NORSRAM_BANK4 */
00859   {
00860     deviceaddress = NOR_MEMORY_ADRESS4;
00861   }
00862
00863   /* Update the NOR controller state */
00864   hnor->State = HAL_NOR_STATE_BUSY;
00865
00866   /* Send read CFI query command */
00867   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
00868
00869   /* read the NOR CFI information */
00870   pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
00871   pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
00872   pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
00873   pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
00874
00875   /* Check the NOR controller state */
00876   hnor->State = HAL_NOR_STATE_READY;
00877
00878   /* Process unlocked */
00879   __HAL_UNLOCK(hnor);
00880
00881   return HAL_OK;
00882 }
00883
00884 /**
00885   * @}
00886   */
00887
00888 /** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions
00889  *  @brief   management functions
00890  *
00891 @verbatim
00892   ==============================================================================
00893                         ##### NOR Control functions #####
00894   ==============================================================================
00895   [..]
00896     This subsection provides a set of functions allowing to control dynamically
00897     the NOR interface.
00898
00899 @endverbatim
00900   * @{
00901   */
00902
00903 /**
00904   * @brief  Enable dynamically NOR write operation.
00905   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00906   *                the configuration information for NOR module.
00907   * @retval HAL status
00908   */
00909 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
00910 {
00911   /* Process Locked */
00912   __HAL_LOCK(hnor);
00913
00914   /* Enable write operation */
00915   FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
00916
00917   /* Update the NOR controller state */
00918   hnor->State = HAL_NOR_STATE_READY;
00919
00920   /* Process unlocked */
00921   __HAL_UNLOCK(hnor);
00922
00923   return HAL_OK;
00924 }
00925
00926 /**
00927   * @brief  Disable dynamically NOR write operation.
00928   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00929   *                the configuration information for NOR module.
00930   * @retval HAL status
00931   */
00932 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
00933 {
00934   /* Process Locked */
00935   __HAL_LOCK(hnor);
00936
00937   /* Update the SRAM controller state */
00938   hnor->State = HAL_NOR_STATE_BUSY;
00939
00940   /* Disable write operation */
00941   FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
00942
00943   /* Update the NOR controller state */
00944   hnor->State = HAL_NOR_STATE_PROTECTED;
00945
00946   /* Process unlocked */
00947   __HAL_UNLOCK(hnor);
00948
00949   return HAL_OK;
00950 }
00951
00952 /**
00953   * @}
00954   */
00955
00956 /** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions
00957  *  @brief   Peripheral State functions
00958  *
00959 @verbatim
00960   ==============================================================================
00961                       ##### NOR State functions #####
00962   ==============================================================================
00963   [..]
00964     This subsection permits to get in run-time the status of the NOR controller
00965     and the data flow.
00966
00967 @endverbatim
00968   * @{
00969   */
00970
00971 /**
00972   * @brief  Return the NOR controller handle state.
00973   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00974   *                the configuration information for NOR module.
00975   * @retval NOR controller state
00976   */
00977 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
00978 {
00979   /* Return NOR handle state */
00980   return hnor->State;
00981 }
00982
00983 /**
00984   * @brief  Return the NOR operation status.
00985   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00986   *                the configuration information for NOR module.
00987   * @param  Address: Device address
00988   * @param  Timeout: NOR programming Timeout
00989   * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
00990   *         or HAL_NOR_STATUS_TIMEOUT
00991   */
00992 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
00993 {
00994   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
00995   uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
00996   uint32_t tickstart = 0;
00997
00998   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
00999   HAL_NOR_MspWait(hnor, Timeout);
01000
01001   /* Get tick */
01002   tickstart = HAL_GetTick();
01003   while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
01004   {
01005     /* Check for the Timeout */
01006     if(Timeout != HAL_MAX_DELAY)
01007     {
01008       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01009       {
01010         status = HAL_NOR_STATUS_TIMEOUT;
01011       }
01012     }
01013
01014     /* Read NOR status register (DQ6 and DQ5) */
01015     tmp_sr1 = *(__IO uint16_t *)Address;
01016     tmp_sr2 = *(__IO uint16_t *)Address;
01017
01018     /* If DQ6 did not toggle between the two reads then return NOR_Success */
01019     if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
01020     {
01021       return HAL_NOR_STATUS_SUCCESS;
01022     }
01023
01024     if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
01025     {
01026       status = HAL_NOR_STATUS_ONGOING;
01027     }
01028
01029     tmp_sr1 = *(__IO uint16_t *)Address;
01030     tmp_sr2 = *(__IO uint16_t *)Address;
01031
01032     /* If DQ6 did not toggle between the two reads then return NOR_Success */
01033     if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
01034     {
01035       return HAL_NOR_STATUS_SUCCESS;
01036     }
01037     else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
01038     {
01039       return HAL_NOR_STATUS_ERROR;
01040     }
01041   }
01042
01043   /* Return the operation status */
01044   return status;
01045 }
01046
01047 /**
01048   * @}
01049   */
01050
01051 /**
01052   * @}
01053   */
01054 /**
01055   * @}
01056   */
01057 #endif /* HAL_NOR_MODULE_ENABLED */
01058
01059 /**
01060   * @}
01061   */
01062
01063 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01064
01065 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_nor.h Source File

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stm32l4xx_hal_nor.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_nor.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of NOR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_NOR_H
00040 #define __STM32L4xx_HAL_NOR_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32l4xx_ll_fmc.h"
00050
00051
00052 /** @addtogroup STM32L4xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup NOR
00057   * @{
00058   */
00059
00060 /** @addtogroup NOR_Private_Constants
00061   * @{
00062   */
00063
00064 /* NOR device IDs addresses */
00065 #define MC_ADDRESS               ((uint16_t)0x0000)
00066 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
00067 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
00068 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
00069
00070 /* NOR CFI IDs addresses */
00071 #define CFI1_ADDRESS             ((uint16_t)0x10)
00072 #define CFI2_ADDRESS             ((uint16_t)0x11)
00073 #define CFI3_ADDRESS             ((uint16_t)0x12)
00074 #define CFI4_ADDRESS             ((uint16_t)0x13)
00075
00076 /* NOR memory data width */
00077 #define NOR_MEMORY_8B            ((uint8_t)0x0)
00078 #define NOR_MEMORY_16B           ((uint8_t)0x1)
00079
00080 /* NOR memory device read/write start address */
00081 #define NOR_MEMORY_ADRESS1       FMC_BANK1_1
00082 #define NOR_MEMORY_ADRESS2       FMC_BANK1_2
00083 #define NOR_MEMORY_ADRESS3       FMC_BANK1_3
00084 #define NOR_MEMORY_ADRESS4       FMC_BANK1_4
00085
00086 /**
00087   * @}
00088   */
00089
00090 /** @addtogroup NOR_Private_Macros
00091   * @{
00092   */
00093
00094 /**
00095   * @brief  NOR memory address shifting.
00096   * @param  __NOR_ADDRESS: NOR base address
00097   * @param  __NOR_MEMORY_WIDTH_: NOR memory width
00098   * @param  __ADDRESS__: NOR memory address
00099   * @retval NOR shifted address value
00100   */
00101 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
00102             ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
00103               ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
00104               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
00105
00106 /**
00107   * @brief  NOR memory write data to specified address.
00108   * @param  __ADDRESS__: NOR memory address
00109   * @param  __DATA__: Data to write
00110   * @retval None
00111   */
00112 #define NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
00113
00114 /**
00115   * @}
00116   */
00117
00118 /* Exported typedef ----------------------------------------------------------*/
00119 /** @defgroup NOR_Exported_Types NOR Exported Types
00120   * @{
00121   */
00122
00123 /**
00124   * @brief  HAL SRAM State structures definition
00125   */
00126 typedef enum
00127 {
00128   HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
00129   HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
00130   HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
00131   HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
00132   HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected   */
00133 }HAL_NOR_StateTypeDef;
00134
00135 /**
00136   * @brief  FMC NOR Status typedef
00137   */
00138 typedef enum
00139 {
00140   HAL_NOR_STATUS_SUCCESS = 0,
00141   HAL_NOR_STATUS_ONGOING,
00142   HAL_NOR_STATUS_ERROR,
00143   HAL_NOR_STATUS_TIMEOUT
00144 }HAL_NOR_StatusTypeDef;
00145
00146 /**
00147   * @brief  FMC NOR ID typedef
00148   */
00149 typedef struct
00150 {
00151   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
00152
00153   uint16_t Device_Code1;
00154
00155   uint16_t Device_Code2;
00156
00157   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
00158                                     These codes can be accessed by performing read operations with specific
00159                                     control signals and addresses set.They can also be accessed by issuing
00160                                     an Auto Select command.                                                   */
00161 }NOR_IDTypeDef;
00162
00163 /**
00164   * @brief  FMC NOR CFI typedef
00165   */
00166 typedef struct
00167 {
00168   uint16_t CFI_1;
00169
00170   uint16_t CFI_2;
00171
00172   uint16_t CFI_3;
00173
00174   uint16_t CFI_4;  /*!< Defines the information stored in the memory's Common flash interface
00175                         which contains a description of various electrical and timing parameters,
00176                         density information and functions supported by the memory.                   */
00177 }NOR_CFITypeDef;
00178
00179 /**
00180   * @brief  NOR handle Structure definition
00181   */
00182 typedef struct
00183 {
00184   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
00185
00186   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
00187
00188   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
00189
00190   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
00191
00192   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
00193
00194 }NOR_HandleTypeDef;
00195
00196 /**
00197   * @}
00198   */
00199
00200 /* Exported constants --------------------------------------------------------*/
00201 /* Exported macro ------------------------------------------------------------*/
00202 /** @defgroup NOR_Exported_Macros NOR Exported Macros
00203   * @{
00204   */
00205
00206 /** @brief Reset NOR handle state.
00207   * @param  __HANDLE__: NOR handle
00208   * @retval None
00209   */
00210 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
00211
00212 /**
00213   * @}
00214   */
00215
00216 /* Exported functions --------------------------------------------------------*/
00217 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
00218   * @{
00219   */
00220
00221 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00222   * @{
00223   */
00224
00225 /* Initialization/de-initialization functions  ********************************/
00226 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00227 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
00228 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
00229 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
00230 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
00231
00232 /**
00233   * @}
00234   */
00235
00236 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
00237   * @{
00238   */
00239
00240 /* I/O operation functions  ***************************************************/
00241 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
00242 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
00243 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00244 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00245
00246 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00247 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00248
00249 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
00250 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
00251 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
00252
00253 /**
00254   * @}
00255   */
00256
00257 /** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions
00258   * @{
00259   */
00260
00261 /* NOR Control functions  *****************************************************/
00262 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
00263 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
00264
00265 /**
00266   * @}
00267   */
00268
00269 /** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions
00270   * @{
00271   */
00272
00273 /* NOR State functions ********************************************************/
00274 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
00275 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
00276
00277 /**
00278   * @}
00279   */
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00294
00295 #ifdef __cplusplus
00296 }
00297 #endif
00298
00299 #endif /* __STM32L4xx_HAL_NOR_H */
00300
00301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_opamp.c Source File

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stm32l4xx_hal_opamp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_opamp.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   OPAMP HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the operational amplifier(s) peripheral:
00010   *           + OPAMP configuration
00011   *           + OPAMP calibration
00012   *          Thanks to
00013   *           + Initialization and de-initialization functions
00014   *           + IO operation functions
00015   *           + Peripheral Control functions
00016   *           + Peripheral State functions
00017   *
00018   @verbatim
00019 ================================================================================
00020           ##### OPAMP Peripheral Features #####
00021 ================================================================================
00022
00023   [..] The device integrates 1 or 2 operational amplifiers OPAMP1 & OPAMP2
00024
00025        (#) The OPAMP(s) provide(s) several exclusive running modes.
00026        (++) 1 OPAMP: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx
00027        (++) 2 OPAMP: STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx
00028
00029        (#) The OPAMP(s) provide(s) several exclusive running modes.
00030        (++) Standalone mode
00031        (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
00032        (++) Follower mode
00033
00034        (#) All OPAMP (same for all OPAMPs) can operate in
00035        (++) Either Low range (VDDA < 2.4V) power supply
00036        (++) Or High range (VDDA > 2.4V) power supply
00037
00038        (#) Each OPAMP(s) can be configured in normal and low power mode.
00039
00040        (#) The OPAMP(s) provide(s) calibration capabilities.
00041        (++) Calibration aims at correcting some offset for running mode.
00042        (++) The OPAMP uses either factory calibration settings OR user defined
00043            calibration (trimming) settings (i.e. trimming mode).
00044        (++) The user defined settings can be figured out using self calibration
00045            handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
00046        (++) HAL_OPAMP_SelfCalibrate:
00047        (+++) Runs automatically the calibration.
00048        (+++) Enables the user trimming mode
00049        (+++) Updates the init structure with trimming values with fresh calibration
00050             results.
00051             The user may store the calibration results for larger
00052             (ex monitoring the trimming as a function of temperature
00053             for instance)
00054        (+++) HAL_OPAMPEx_SelfCalibrateAll
00055             runs calibration of all OPAMPs in parallel to save search time.
00056
00057        (#) Running mode: Standalone mode
00058        (++) Gain is set externally (gain depends on external loads).
00059        (++) Follower mode also possible externally by connecting the inverting input to
00060            the output.
00061
00062        (#) Running mode: Follower mode
00063        (++) No Inverting Input is connected.
00064
00065        (#) Running mode: Programmable Gain Amplifier (PGA) mode
00066            (Resistor feedback output)
00067        (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
00068            output.
00069        (++) OPAMP gain is either 2, 4, 8 or 16.
00070
00071        (#) The OPAMPs inverting input can be selected according to the Reference Manual
00072            "OPAMP function description" chapter.
00073
00074        (#) The OPAMPs non inverting input can be selected according to the Reference Manual
00075            "OPAMP function description" chapter.
00076
00077
00078             ##### How to use this driver #####
00079 ================================================================================
00080   [..]
00081
00082     *** Power supply range ***
00083     ============================================
00084     [..] To run in low power mode:
00085
00086       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00087       (++) Select OPAMP_POWERSUPPLY_LOW (VDDA lower than 2.4V)
00088       (++) Otherwise select OPAMP_POWERSUPPLY_HIGH (VDDA higher than 2.4V)
00089
00090     *** Low / normal power mode ***
00091     ============================================
00092     [..] To run in low power mode:
00093
00094       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00095       (++) Select OPAMP_POWERMODE_LOWPOWER
00096       (++) Otherwise select OPAMP_POWERMODE_NORMAL
00097
00098     *** Calibration ***
00099     ============================================
00100     [..] To run the OPAMP calibration self calibration:
00101
00102       (#) Start calibration using HAL_OPAMP_SelfCalibrate.
00103            Store the calibration results.
00104
00105     *** Running mode ***
00106     ============================================
00107
00108     [..] To use the OPAMP, perform the following steps:
00109
00110       (#) Fill in the HAL_OPAMP_MspInit() to
00111       (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
00112       (++) Configure the OPAMP input AND output in analog mode using
00113            HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
00114
00115       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00116       (++) Select the mode
00117       (++) Select the inverting input
00118       (++) Select the non-inverting input
00119       (++) If PGA mode is enabled, Select if inverting input is connected.
00120       (++) Select either factory or user defined trimming mode.
00121       (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
00122           (typically values set by HAL_OPAMP_SelfCalibrate function).
00123
00124       (#) Enable the OPAMP using HAL_OPAMP_Start() function.
00125
00126       (#) Disable the OPAMP using HAL_OPAMP_Stop() function.
00127
00128       (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
00129           Caution: On STM32L4, HAL OPAMP lock is software lock only (not
00130           hardware lock as on some other STM32 devices)
00131
00132       (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.
00133
00134     *** Running mode: change of configuration while OPAMP ON  ***
00135     ============================================
00136     [..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
00137       (#) If needed, fill in the HAL_OPAMP_MspInit()
00138       (++) This is the case for instance if you wish to use new OPAMP I/O
00139
00140       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
00141       (++) As in configure case, select first the parameters you wish to modify.
00142
00143       (#) Change from low power mode to normal power mode (& vice versa) requires
00144           first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
00145           In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
00146           alone.
00147
00148   @endverbatim
00149   ******************************************************************************
00150
00151       Table 1.  OPAMPs inverting/non-inverting inputs for the STM32L4 devices:
00152       +------------------------------------------------------------------------|
00153       |                 |         | OPAMP1               | OPAMP2              |
00154       |-----------------|---------|----------------------|---------------------|
00155       | Inverting Input | VM_SEL  |                      |                     |
00156       |                 |         |  IO0-> PA1           | IO0-> PA7           |
00157       |                 |         |  LOW LEAKAGE IO (2)  | LOW LEAKAGE IO (2)  |
00158       |                 |         |  Not connected       | Not connected       |
00159       | (1)             |         |    PGA mode only     |   PGA mode only     |
00160       |-----------------|---------|----------------------|---------------------|
00161       |  Non Inverting  | VP_SEL  |                      |                     |
00162       |                 |         |  IO0-> PA0 (GPIO)    | IO0-> PA6  (GPIO)   |
00163       |    Input        |         |  DAC1_OUT1 internal  | DAC1_OUT2 internal  |
00164       +------------------------------------------------------------------------|
00165        (1): NA in follower mode.
00166        (2): Available on some package only (ex. BGA132).
00167
00168
00169       Table 2.  OPAMPs outputs for the STM32L4 devices:
00170
00171       +-------------------------------------------------------------------------
00172       |                 |        | OPAMP1                | OPAMP2              |
00173       |-----------------|--------|-----------------------|---------------------|
00174       | Output          |  VOUT  |  PA3                  |  PB0                |
00175       |                 |        |  & (1) ADC12_IN if    | & (1) ADC12_IN if   |
00176       |                 |        |  connected internally | connected internally|
00177       |-----------------|--------|-----------------------|---------------------|
00178        (1): ADC1 or ADC2 shall select IN15.
00179
00180   ******************************************************************************
00181   * @attention
00182   *
00183   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00184   *
00185   * Redistribution and use in source and binary forms, with or without modification,
00186   * are permitted provided that the following conditions are met:
00187   *   1. Redistributions of source code must retain the above copyright notice,
00188   *      this list of conditions and the following disclaimer.
00189   *   2. Redistributions in binary form must reproduce the above copyright notice,
00190   *      this list of conditions and the following disclaimer in the documentation
00191   *      and/or other materials provided with the distribution.
00192   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00193   *      may be used to endorse or promote products derived from this software
00194   *      without specific prior written permission.
00195   *
00196   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00197   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00198   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00199   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00200   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00201   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00202   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00203   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00204   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00205   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00206   *
00207   ******************************************************************************
00208   */
00209
00210 /* Includes ------------------------------------------------------------------*/
00211 #include "stm32l4xx_hal.h"
00212
00213 /** @addtogroup STM32L4xx_HAL_Driver
00214   * @{
00215   */
00216
00217 /** @defgroup OPAMP OPAMP
00218   * @brief OPAMP module driver
00219   * @{
00220   */
00221
00222 #ifdef HAL_OPAMP_MODULE_ENABLED
00223
00224 /* Private types -------------------------------------------------------------*/
00225 /* Private variables ---------------------------------------------------------*/
00226 /* Private constants ---------------------------------------------------------*/
00227 /** @addtogroup OPAMP_Private_Constants
00228   * @{
00229   */
00230
00231 /* CSR register reset value */
00232 #define OPAMP_CSR_RESET_VALUE             ((uint32_t)0x00000000)
00233
00234 #define OPAMP_CSR_RESET_BITS    (OPAMP_CSR_OPAMPxEN | OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE \
00235                                | OPAMP_CSR_PGGAIN | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL \
00236                                | OPAMP_CSR_CALON | OPAMP_CSR_USERTRIM)
00237
00238 /* CSR Init masks */
00239 #define OPAMP_CSR_INIT_MASK_PGA (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_PGGAIN \
00240                                | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL | OPAMP_CSR_USERTRIM)
00241
00242 #define OPAMP_CSR_INIT_MASK_FOLLOWER (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_VPSEL \
00243                                     | OPAMP_CSR_USERTRIM)
00244
00245 #define OPAMP_CSR_INIT_MASK_STANDALONE (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_VPSEL \
00246                                       | OPAMP_CSR_VMSEL | OPAMP_CSR_USERTRIM)
00247
00248
00249 /**
00250   * @}
00251   */
00252
00253 /* Private macros ------------------------------------------------------------*/
00254 /* Private functions ---------------------------------------------------------*/
00255 /* Exported functions --------------------------------------------------------*/
00256
00257 /** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
00258   * @{
00259   */
00260
00261 /** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
00262  *  @brief    Initialization and Configuration functions
00263  *
00264 @verbatim
00265   ==============================================================================
00266               ##### Initialization and de-initialization functions #####
00267   ==============================================================================
00268
00269 @endverbatim
00270   * @{
00271   */
00272
00273 /**
00274   * @brief  Initializes the OPAMP according to the specified
00275   *         parameters in the OPAMP_InitTypeDef and initialize the associated handle.
00276   * @note   If the selected opamp is locked, initialization can't be performed.
00277   *         To unlock the configuration, perform a system reset.
00278   * @param  hopamp: OPAMP handle
00279   * @retval HAL status
00280   */
00281 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
00282 {
00283   HAL_StatusTypeDef status = HAL_OK;
00284   uint32_t updateotrlpotr = 0;
00285
00286   /* Check the OPAMP handle allocation and lock status */
00287   /* Init not allowed if calibration is ongoing */
00288   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
00289                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
00290   {
00291     return HAL_ERROR;
00292   }
00293   else
00294   {
00295     /* Check the parameter */
00296     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00297
00298     /* Set OPAMP parameters */
00299     assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange));
00300     assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
00301     assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
00302     assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
00303
00304     if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
00305     {
00306       assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput));
00307     }
00308
00309     if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
00310     {
00311       assert_param(IS_OPAMP_INVERTING_INPUT_PGA(hopamp->Init.InvertingInput));
00312     }
00313
00314     if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
00315     {
00316       assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
00317     }
00318
00319     assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
00320     if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
00321     {
00322       if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00323       {
00324         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
00325         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
00326       }
00327     else
00328       {
00329         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePLowPower));
00330         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower));
00331       }
00332     }
00333
00334     if(hopamp->State == HAL_OPAMP_STATE_RESET)
00335     {
00336       /* Allocate lock resource and initialize it */
00337       hopamp->Lock = HAL_UNLOCKED;
00338     }
00339
00340     /* Call MSP init function */
00341     HAL_OPAMP_MspInit(hopamp);
00342
00343     /* Set operating mode */
00344     CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
00345
00346     if (hopamp->Init.Mode == OPAMP_PGA_MODE)
00347     {
00348       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \
00349                                         hopamp->Init.PowerMode | \
00350                                         hopamp->Init.Mode | \
00351                                         hopamp->Init.PgaGain | \
00352                                         hopamp->Init.InvertingInput    | \
00353                                         hopamp->Init.NonInvertingInput | \
00354                                         hopamp->Init.UserTrimming);
00355     }
00356
00357     if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
00358     {
00359     /* In Follower mode InvertingInput is Not Applicable  */
00360     MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_FOLLOWER, \
00361                                         hopamp->Init.PowerMode | \
00362                                         hopamp->Init.Mode | \
00363                                         hopamp->Init.NonInvertingInput | \
00364                                         hopamp->Init.UserTrimming);
00365     }
00366
00367     if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE)
00368     {
00369       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \
00370                                         hopamp->Init.PowerMode | \
00371                                         hopamp->Init.Mode | \
00372                                         hopamp->Init.InvertingInput    | \
00373                                         hopamp->Init.NonInvertingInput | \
00374                                         hopamp->Init.UserTrimming);
00375     }
00376
00377     if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
00378     {
00379       /* Set power mode and associated calibration parameters */
00380       if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
00381       {
00382         /* OPAMP_POWERMODE_NORMAL */
00383         /* Set calibration mode (factory or user) and values for            */
00384         /* transistors differential pair high (PMOS) and low (NMOS) for     */
00385         /* normal mode.                                                     */
00386         updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \
00387                          | (hopamp->Init.TrimmingValueN));
00388         MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
00389       }
00390       else
00391       {
00392         /* OPAMP_POWERMODE_LOWPOWER */
00393         /* transistors differential pair high (PMOS) and low (NMOS) for     */
00394         /* low power mode.                                                     */
00395         updateotrlpotr = (((hopamp->Init.TrimmingValuePLowPower) << (OPAMP_INPUT_NONINVERTING)) \
00396                          | (hopamp->Init.TrimmingValueNLowPower));
00397         MODIFY_REG(hopamp->Instance->LPOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
00398       }
00399     }
00400
00401     /* Configure the power supply range */
00402     /* The OPAMP_CSR_OPARANGE is common configuration for all OPAMPs */
00403     /* bit OPAMP1_CSR_OPARANGE is used for both OPAMPs */
00404     MODIFY_REG(OPAMP1->CSR, OPAMP1_CSR_OPARANGE, hopamp->Init.PowerSupplyRange);
00405
00406     /* Update the OPAMP state*/
00407     if (hopamp->State == HAL_OPAMP_STATE_RESET)
00408     {
00409       /* From RESET state to READY State */
00410       hopamp->State = HAL_OPAMP_STATE_READY;
00411     }
00412     /* else: remain in READY or BUSY state (no update) */
00413     return status;
00414   }
00415 }
00416
00417 /**
00418   * @brief  DeInitialize the OPAMP peripheral.
00419   * @note   Deinitialization can be performed if the OPAMP configuration is locked.
00420   *         (the lock is SW in L4)
00421   * @param  hopamp: OPAMP handle
00422   * @retval HAL status
00423   */
00424 HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
00425 {
00426   HAL_StatusTypeDef status = HAL_OK;
00427
00428   /* Check the OPAMP handle allocation */
00429   /* DeInit not allowed if calibration is ongoing */
00430   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
00431   {
00432     status = HAL_ERROR;
00433   }
00434   else
00435   {
00436     /* Check the parameter */
00437     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00438
00439     /* Set OPAMP_CSR register to reset value */
00440     /* Mind that OPAMP1_CSR_OPARANGE of CSR of OPAMP1 remains unchanged (applies to both OPAMPs) */
00441     /* OPAMP shall be disabled first separately */
00442     CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00443     MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE);
00444
00445     /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
00446     HAL_OPAMP_MspDeInit(hopamp);
00447
00448     /* Update the OPAMP state*/
00449     hopamp->State = HAL_OPAMP_STATE_RESET;
00450   }
00451
00452   /* Process unlocked */
00453   __HAL_UNLOCK(hopamp);
00454
00455   return status;
00456 }
00457
00458
00459 /**
00460   * @brief  Initialize the OPAMP MSP.
00461   * @param  hopamp: OPAMP handle
00462   * @retval None
00463   */
00464 __weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
00465 {
00466   /* Prevent unused argument(s) compilation warning */
00467   UNUSED(hopamp);
00468
00469   /* NOTE : This function should not be modified, when the callback is needed,
00470             the function "HAL_OPAMP_MspInit()" must be implemented in the user file.
00471    */
00472 }
00473
00474 /**
00475   * @brief  DeInitialize OPAMP MSP.
00476   * @param  hopamp: OPAMP handle
00477   * @retval None
00478   */
00479 __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
00480 {
00481   /* Prevent unused argument(s) compilation warning */
00482   UNUSED(hopamp);
00483
00484   /* NOTE : This function should not be modified, when the callback is needed,
00485             the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file.
00486    */
00487 }
00488
00489 /**
00490   * @}
00491   */
00492
00493
00494 /** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions
00495  *  @brief   IO operation functions
00496  *
00497 @verbatim
00498  ===============================================================================
00499                         ##### IO operation functions #####
00500  ===============================================================================
00501     [..]
00502     This subsection provides a set of functions allowing to manage the OPAMP
00503     start, stop and calibration actions.
00504
00505 @endverbatim
00506   * @{
00507   */
00508
00509 /**
00510   * @brief  Start the OPAMP.
00511   * @param  hopamp: OPAMP handle
00512   * @retval HAL status
00513   */
00514
00515 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
00516 {
00517   HAL_StatusTypeDef status = HAL_OK;
00518
00519   /* Check the OPAMP handle allocation */
00520   /* Check if OPAMP locked */
00521   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00522   {
00523     status = HAL_ERROR;
00524   }
00525   else
00526   {
00527     /* Check the parameter */
00528     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00529
00530     if(hopamp->State == HAL_OPAMP_STATE_READY)
00531     {
00532       /* Enable the selected opamp */
00533       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00534
00535       /* Update the OPAMP state*/
00536       /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
00537       hopamp->State = HAL_OPAMP_STATE_BUSY;
00538     }
00539     else
00540     {
00541       status = HAL_ERROR;
00542     }
00543
00544    }
00545   return status;
00546 }
00547
00548 /**
00549   * @brief  Stop the OPAMP.
00550   * @param  hopamp: OPAMP handle
00551   * @retval HAL status
00552   */
00553 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
00554 {
00555   HAL_StatusTypeDef status = HAL_OK;
00556
00557   /* Check the OPAMP handle allocation */
00558   /* Check if OPAMP locked */
00559   /* Check if OPAMP calibration ongoing */
00560   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
00561                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
00562   {
00563     status = HAL_ERROR;
00564   }
00565   else
00566   {
00567     /* Check the parameter */
00568     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00569
00570     if(hopamp->State == HAL_OPAMP_STATE_BUSY)
00571     {
00572       /* Disable the selected opamp */
00573       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00574
00575       /* Update the OPAMP state*/
00576       /* From  HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
00577       hopamp->State = HAL_OPAMP_STATE_READY;
00578     }
00579     else
00580     {
00581       status = HAL_ERROR;
00582     }
00583   }
00584   return status;
00585 }
00586
00587 /**
00588   * @brief  Run the self calibration of one OPAMP.
00589   * @note   Calibration is performed in the mode specified in OPAMP init
00590   *         structure (mode normal or low-power). To perform calibration for
00591   *         both modes, repeat this function twice after OPAMP init structure
00592   *         accordingly updated.
00593   * @note   Calibration runs about 10 ms.
00594   * @param  hopamp handle
00595   * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
00596   * @retval HAL status
00597
00598   */
00599
00600 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
00601 {
00602
00603   HAL_StatusTypeDef status = HAL_OK;
00604
00605   uint32_t trimmingvaluen = 0;
00606   uint32_t trimmingvaluep = 0;
00607   uint32_t delta;
00608   uint32_t opampmode;
00609
00610   __IO uint32_t* tmp_opamp_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or LPOTR */
00611
00612   /* Check the OPAMP handle allocation */
00613   /* Check if OPAMP locked */
00614   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00615   {
00616     status = HAL_ERROR;
00617   }
00618   else
00619   {
00620     /* Check if OPAMP in calibration mode and calibration not yet enable */
00621     if(hopamp->State ==  HAL_OPAMP_STATE_READY)
00622     {
00623       /* Check the parameter */
00624       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00625       assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
00626
00627       /* Save OPAMP mode as in                                       */
00628       /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */
00629       /* the calibration is not working in PGA mode                  */
00630       opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_OPAMODE);
00631
00632       /* Use of standalone mode */
00633       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE);
00634
00635       /*  user trimming values are used for offset calibration */
00636       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
00637
00638       /* Select trimming settings depending on power mode */
00639       if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00640       {
00641         tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
00642       }
00643       else
00644       {
00645         tmp_opamp_reg_trimming = &hopamp->Instance->LPOTR;
00646       }
00647
00648       /* Enable calibration */
00649       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
00650
00651       /* 1st calibration - N */
00652       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALSEL);
00653
00654       /* Enable the selected opamp */
00655       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00656
00657       /* Init trimming counter */
00658       /* Medium value */
00659       trimmingvaluen = 16;
00660       delta = 8;
00661
00662       while (delta != 0)
00663       {
00664         /* Set candidate trimming */
00665         /* OPAMP_POWERMODE_NORMAL */
00666         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
00667
00668         /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
00669         /* Offset trim time: during calibration, minimum time needed between */
00670         /* two steps to have 1 mV accuracy */
00671         HAL_Delay(OPAMP_TRIMMING_DELAY);
00672
00673         if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00674         {
00675           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
00676           trimmingvaluen -= delta;
00677         }
00678         else
00679         {
00680           /* OPAMP_CSR_CALOUT is LOW try lower trimming */
00681           trimmingvaluen += delta;
00682         }
00683         /* Divide range by 2 to continue dichotomy sweep */
00684         delta >>= 1;
00685       }
00686
00687       /* Still need to check if right calibration is current value or one step below */
00688       /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1  */
00689       /* Set candidate trimming */
00690       MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
00691
00692       /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
00693       /* Offset trim time: during calibration, minimum time needed between */
00694       /* two steps to have 1 mV accuracy */
00695       HAL_Delay(OPAMP_TRIMMING_DELAY);
00696
00697       if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) == 0)
00698       {
00699         /* Trimming value is actually one value more */
00700         trimmingvaluen++;
00701         /* Set right trimming */
00702         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
00703       }
00704
00705       /* 2nd calibration - P */
00706       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALSEL);
00707
00708       /* Init trimming counter */
00709       /* Medium value */
00710       trimmingvaluep = 16;
00711       delta = 8;
00712
00713       while (delta != 0)
00714       {
00715         /* Set candidate trimming */
00716         /* OPAMP_POWERMODE_NORMAL */
00717         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
00718
00719         /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
00720         /* Offset trim time: during calibration, minimum time needed between */
00721         /* two steps to have 1 mV accuracy */
00722         HAL_Delay(OPAMP_TRIMMING_DELAY);
00723
00724         if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00725         {
00726           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
00727           trimmingvaluep += delta;
00728         }
00729         else
00730         {
00731           /* OPAMP_CSR_CALOUT  is LOW try lower trimming */
00732           trimmingvaluep -= delta;
00733         }
00734
00735         /* Divide range by 2 to continue dichotomy sweep */
00736         delta >>= 1;
00737       }
00738
00739       /* Still need to check if right calibration is current value or one step below */
00740       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
00741       /* Set candidate trimming */
00742       MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
00743
00744       /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
00745       /* Offset trim time: during calibration, minimum time needed between */
00746       /* two steps to have 1 mV accuracy */
00747       HAL_Delay(OPAMP_TRIMMING_DELAY);
00748
00749       if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00750       {
00751         /* Trimming value is actually one value more */
00752         trimmingvaluep++;
00753         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
00754       }
00755
00756       /* Disable the OPAMP */
00757       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00758
00759       /* Disable calibration & set normal mode (operating mode) */
00760       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
00761
00762       /* Self calibration is successful  */
00763       /* Store calibration(user trimming) results in init structure. */
00764
00765       /* Set user trimming mode */
00766       hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
00767
00768       /* Affect calibration parameters depending on mode normal/low power */
00769       if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
00770       {
00771         /* Write calibration result N */
00772         hopamp->Init.TrimmingValueN = trimmingvaluen;
00773         /* Write calibration result P */
00774         hopamp->Init.TrimmingValueP = trimmingvaluep;
00775       }
00776       else
00777       {
00778         /* Write calibration result N */
00779         hopamp->Init.TrimmingValueNLowPower = trimmingvaluen;
00780         /* Write calibration result P */
00781         hopamp->Init.TrimmingValuePLowPower = trimmingvaluep;
00782       }
00783
00784     /* Restore OPAMP mode after calibration */
00785     MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode);
00786     }
00787     else
00788     {
00789       /* OPAMP can not be calibrated from this mode */
00790       status = HAL_ERROR;
00791     }
00792   }
00793   return status;
00794 }
00795
00796 /**
00797   * @}
00798   */
00799
00800 /** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
00801  *  @brief   Peripheral Control functions
00802  *
00803 @verbatim
00804  ===============================================================================
00805                       ##### Peripheral Control functions #####
00806  ===============================================================================
00807     [..]
00808     This subsection provides a set of functions allowing to control the OPAMP data
00809     transfers.
00810
00811
00812
00813 @endverbatim
00814   * @{
00815   */
00816
00817 /**
00818   * @brief  Lock the selected OPAMP configuration.
00819   * @note   On STM32L4, HAL OPAMP lock is software lock only (in
00820   *         contrast of hardware lock available on some other STM32
00821   *         devices).
00822   * @param  hopamp: OPAMP handle
00823   * @retval HAL status
00824   */
00825 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
00826 {
00827   HAL_StatusTypeDef status = HAL_OK;
00828
00829   /* Check the OPAMP handle allocation */
00830   /* Check if OPAMP locked */
00831   /* OPAMP can be locked when enabled and running in normal mode */
00832   /*   It is meaningless otherwise */
00833   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
00834                       || (hopamp->State == HAL_OPAMP_STATE_READY) \
00835                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
00836                       || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00837
00838   {
00839     status = HAL_ERROR;
00840   }
00841
00842   else
00843   {
00844     /* Check the parameter */
00845     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00846
00847    /* OPAMP state changed to locked */
00848     hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
00849   }
00850   return status;
00851 }
00852
00853 /**
00854   * @brief  Return the OPAMP factory trimming value.
00855   * @note            On STM32L4 OPAMP, user can retrieve factory trimming if
00856   *                  OPAMP has never been set to user trimming before.
00857   *                  Therefore, this function must be called when OPAMP init
00858   *                  parameter "UserTrimming" is set to trimming factory,
00859   *                  and before OPAMP  calibration (function
00860   *                  "HAL_OPAMP_SelfCalibrate()").
00861   *                  Otherwise, factory trimming value cannot be retrieved and
00862   *                  error status is returned.
00863   * @param  hopamp : OPAMP handle
00864   * @param  trimmingoffset : Trimming offset (P or N)
00865   *         This parameter must be a value of @ref OPAMP_FactoryTrimming
00866   * @note   Calibration parameter retrieved is corresponding to the mode
00867   *         specified in OPAMP init structure (mode normal or low-power).
00868   *         To retrieve calibration parameters for both modes, repeat this
00869   *         function after OPAMP init structure accordingly updated.
00870   * @retval Trimming value (P or N): range: 0->31
00871   *         or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
00872   *
00873   */
00874
00875 HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
00876 {
00877   HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
00878   __IO uint32_t* tmp_opamp_reg_trimming;  /* Selection of register of trimming depending on power mode: OTR or LPOTR */
00879
00880   /* Check the OPAMP handle allocation */
00881   /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
00882   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
00883                       || (hopamp->State == HAL_OPAMP_STATE_BUSY) \
00884                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
00885                       || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
00886   {
00887     return OPAMP_FACTORYTRIMMING_DUMMY;
00888   }
00889   else
00890   {
00891     /* Check the parameter */
00892     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00893     assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
00894     assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
00895
00896     /* Check the trimming mode */
00897     if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM) != RESET)
00898     {
00899       /* This function must called when OPAMP init parameter "UserTrimming"   */
00900       /* is set to trimming factory, and before OPAMP calibration (function   */
00901       /* "HAL_OPAMP_SelfCalibrate()").                                        */
00902       /* Otherwise, factory trimming value cannot be retrieved and error       */
00903       /* status is returned.                                                  */
00904       trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY;
00905     }
00906     else
00907     {
00908       /* Select trimming settings depending on power mode */
00909       if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00910       {
00911         tmp_opamp_reg_trimming = &OPAMP->OTR;
00912       }
00913       else
00914       {
00915         tmp_opamp_reg_trimming = &OPAMP->LPOTR;
00916       }
00917
00918       /* Get factory trimming  */
00919       if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
00920       {
00921         /* OPAMP_FACTORYTRIMMING_P */
00922         trimmingvalue = ((*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
00923       }
00924       else
00925       {
00926         /* OPAMP_FACTORYTRIMMING_N */
00927         trimmingvalue = (*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETN;
00928       }
00929     }
00930   }
00931   return trimmingvalue;
00932 }
00933
00934 /**
00935   * @}
00936   */
00937
00938
00939 /** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
00940  *  @brief   Peripheral State functions
00941  *
00942 @verbatim
00943  ===============================================================================
00944                       ##### Peripheral State functions #####
00945  ===============================================================================
00946     [..]
00947     This subsection permits to get in run-time the status of the peripheral.
00948
00949 @endverbatim
00950   * @{
00951   */
00952
00953 /**
00954   * @brief  Return the OPAMP handle state.
00955   * @param  hopamp : OPAMP handle
00956   * @retval HAL state
00957   */
00958 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
00959 {
00960   /* Check the OPAMP handle allocation */
00961   if(hopamp == NULL)
00962   {
00963     return HAL_OPAMP_STATE_RESET;
00964   }
00965
00966   /* Check the parameter */
00967   assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00968
00969   /* Return OPAMP handle state */
00970   return hopamp->State;
00971 }
00972
00973 /**
00974   * @}
00975   */
00976
00977 /**
00978   * @}
00979   */
00980
00981   /**
00982   * @}
00983   */
00984
00985 #endif /* HAL_OPAMP_MODULE_ENABLED */
00986 /**
00987   * @}
00988   */
00989
00990 /**
00991   * @}
00992   */
00993
00994 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_opamp.h Source File

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stm32l4xx_hal_opamp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_opamp.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of OPAMP HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_OPAMP_H
00040 #define __STM32L4xx_HAL_OPAMP_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup OPAMP
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup OPAMP_Exported_Types OPAMP Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  OPAMP Init structure definition
00065   */
00066
00067 typedef struct
00068 {
00069   uint32_t PowerSupplyRange;            /*!< Specifies the power supply range: above or under 2.4V.
00070                                              This parameter must be a value of @ref OPAMP_PowerSupplyRange
00071                                              Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */
00072
00073   uint32_t PowerMode;                   /*!< Specifies the power mode Normal or Low-Power.
00074                                              This parameter must be a value of @ref OPAMP_PowerMode */
00075
00076   uint32_t Mode;                        /*!< Specifies the OPAMP mode
00077                                              This parameter must be a value of @ref OPAMP_Mode
00078                                              mode is either Standalone, - Follower or PGA */
00079
00080   uint32_t InvertingInput;              /*!< Specifies the inverting input in Standalone & PGA modes
00081                                                - In Standalone mode:   i.e. when mode is OPAMP_STANDALONE_MODE
00082                                                  & PGA mode:           i.e. when mode is OPAMP_PGA_MODE
00083                                                  This parameter must be a value of @ref OPAMP_InvertingInput
00084                                                - In Follower mode    i.e. when mode is OPAMP_FOLLOWER_MODE
00085                                                  This parameter is Not Applicable */
00086
00087   uint32_t NonInvertingInput;           /*!< Specifies the non inverting input of the opamp:
00088                                              This parameter must be a value of @ref OPAMP_NonInvertingInput */
00089
00090   uint32_t PgaGain;                     /*!< Specifies the gain in PGA mode
00091                                              i.e. when mode is OPAMP_PGA_MODE.
00092                                              This parameter must be a value of @ref OPAMP_PgaGain (2, 4, 8 or 16 ) */
00093
00094   uint32_t UserTrimming;                /*!< Specifies the trimming mode
00095                                              This parameter must be a value of @ref OPAMP_UserTrimming
00096                                              UserTrimming is either factory or user trimming.*/
00097
00098   uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS)
00099                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00100                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31
00101                                              16 is typical default value */
00102
00103   uint32_t TrimmingValueN;              /*!< Specifies the offset trimming value (NMOS)
00104                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00105                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31
00106                                              16 is typical default value */
00107
00108   uint32_t TrimmingValuePLowPower;      /*!< Specifies the offset trimming value (PMOS)
00109                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00110                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31
00111                                              16 is typical default value */
00112
00113   uint32_t TrimmingValueNLowPower;      /*!< Specifies the offset trimming value (NMOS)
00114                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
00115                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31
00116                                              16 is typical default value */
00117
00118 }OPAMP_InitTypeDef;
00119
00120 /**
00121   * @brief  HAL State structures definition
00122   */
00123
00124 typedef enum
00125 {
00126   HAL_OPAMP_STATE_RESET               = 0x00000000, /*!< OPAMP is not yet Initialized          */
00127
00128   HAL_OPAMP_STATE_READY               = 0x00000001, /*!< OPAMP is initialized and ready for use */
00129   HAL_OPAMP_STATE_CALIBBUSY           = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
00130
00131   HAL_OPAMP_STATE_BUSY                = 0x00000004, /*!< OPAMP is enabled and running in normal mode */
00132   HAL_OPAMP_STATE_BUSYLOCKED          = 0x00000005  /*!< OPAMP is locked
00133                                                          only system reset allows reconfiguring the opamp. */
00134
00135 }HAL_OPAMP_StateTypeDef;
00136
00137 /**
00138   * @brief OPAMP Handle Structure definition
00139   */
00140 typedef struct
00141 {
00142   OPAMP_TypeDef       *Instance;                    /*!< OPAMP instance's registers base address   */
00143   OPAMP_InitTypeDef   Init;                         /*!< OPAMP required parameters */
00144   HAL_StatusTypeDef Status;                         /*!< OPAMP peripheral status   */
00145   HAL_LockTypeDef   Lock;                           /*!< Locking object          */
00146   __IO HAL_OPAMP_StateTypeDef  State;               /*!< OPAMP communication state */
00147
00148 } OPAMP_HandleTypeDef;
00149
00150 /**
00151   * @brief HAl_OPAMP_TrimmingValueTypeDef definition
00152   */
00153
00154 typedef  uint32_t HAL_OPAMP_TrimmingValueTypeDef;
00155
00156 /**
00157   * @}
00158   */
00159
00160 /* Exported constants --------------------------------------------------------*/
00161
00162 /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
00163   * @{
00164   */
00165
00166 /** @defgroup OPAMP_Mode OPAMP Mode
00167   * @{
00168   */
00169 #define OPAMP_STANDALONE_MODE            ((uint32_t)0x00000000) /*!< standalone mode */
00170 #define OPAMP_PGA_MODE                   OPAMP_CSR_OPAMODE_1    /*!< PGA mode */
00171 #define OPAMP_FOLLOWER_MODE              OPAMP_CSR_OPAMODE      /*!< follower mode */
00172
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
00178   * @{
00179   */
00180
00181 #define OPAMP_NONINVERTINGINPUT_IO0        ((uint32_t)0x00000000)  /*!< OPAMP non-inverting input connected to dedicated IO pin */
00182 #define OPAMP_NONINVERTINGINPUT_DAC_CH      OPAMP_CSR_VPSEL        /*!< OPAMP non-inverting input connected internally to DAC channel */
00183
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
00189   * @{
00190   */
00191
00192 #define OPAMP_INVERTINGINPUT_IO0              ((uint32_t)0x00000000)  /*!< OPAMP inverting input connected to dedicated IO pin low-leakage */
00193 #define OPAMP_INVERTINGINPUT_IO1              OPAMP_CSR_VMSEL_0       /*!< OPAMP inverting input connected to alternative IO pin available on some device packages */
00194 #define OPAMP_INVERTINGINPUT_CONNECT_NO       OPAMP_CSR_VMSEL_1       /*!< OPAMP inverting input not connected externally (PGA mode only) */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup OPAMP_PgaGain OPAMP Pga Gain
00201   * @{
00202   */
00203
00204 #define OPAMP_PGA_GAIN_2                ((uint32_t)0x00000000)                        /*!< PGA gain =  2 */
00205 #define OPAMP_PGA_GAIN_4                OPAMP_CSR_PGGAIN_0                            /*!< PGA gain =  4 */
00206 #define OPAMP_PGA_GAIN_8                OPAMP_CSR_PGGAIN_1                            /*!< PGA gain =  8 */
00207 #define OPAMP_PGA_GAIN_16              (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)      /*!< PGA gain = 16 */
00208
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup OPAMP_PowerMode OPAMP PowerMode
00214   * @{
00215   */
00216 #define OPAMP_POWERMODE_NORMAL        ((uint32_t)0x00000000)
00217 #define OPAMP_POWERMODE_LOWPOWER      OPAMP_CSR_OPALPM
00218
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange
00224   * @{
00225   */
00226 #define OPAMP_POWERSUPPLY_LOW          ((uint32_t)0x00000000)  /*!< Power supply range low (VDDA lower than 2.4V) */
00227 #define OPAMP_POWERSUPPLY_HIGH         OPAMP1_CSR_OPARANGE     /*!< Power supply range high (VDDA higher than 2.4V) */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup OPAMP_UserTrimming OPAMP User Trimming
00234   * @{
00235   */
00236 #define OPAMP_TRIMMING_FACTORY        ((uint32_t)0x00000000)                          /*!< Factory trimming */
00237 #define OPAMP_TRIMMING_USER           OPAMP_CSR_USERTRIM                              /*!< User trimming */
00238
00239 #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
00240                                      ((TRIMMING) == OPAMP_TRIMMING_USER))
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
00246   * @{
00247   */
00248 #define OPAMP_FACTORYTRIMMING_DUMMY    ((uint32_t)0xFFFFFFFF)                           /*!< Dummy value if trimming value could not be retrieved */
00249
00250 #define OPAMP_FACTORYTRIMMING_N        ((uint32_t)0x00000000)                          /*!< Offset trimming N */
00251 #define OPAMP_FACTORYTRIMMING_P        ((uint32_t)0x00000001)                          /*!< Offset trimming P */
00252
00253 /**
00254   * @}
00255   */
00256
00257  /**
00258   * @}
00259   */
00260
00261 /* Private constants ---------------------------------------------------------*/
00262 /** @defgroup OPAMP_Private_Constants OPAMP Private Constants
00263   * @brief   OPAMP Private constants and defines
00264   * @{
00265   */
00266
00267 /* NONINVERTING bit position in OTR & LPOTR */
00268 #define OPAMP_INPUT_NONINVERTING              ((uint32_t) 8) /*!< Non inverting input */
00269
00270 /* Offset trimming time: during calibration, minimum time needed between two  */
00271 /* steps to have 1 mV accuracy.                                               */
00272 /* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=1ms.*/
00273 /* Unit: ms.                                                                  */
00274 #define OPAMP_TRIMMING_DELAY               ((uint32_t) 1)
00275
00276 /**
00277   * @}
00278   */
00279
00280 /* Exported macros -----------------------------------------------------------*/
00281 /** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
00282   * @{
00283   */
00284
00285 /** @brief Reset OPAMP handle state.
00286   * @param  __HANDLE__: OPAMP handle.
00287   * @retval None
00288   */
00289 #define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
00290
00291 /**
00292   * @}
00293   */
00294
00295 /* Private macro -------------------------------------------------------------*/
00296
00297 /** @defgroup OPAMP_Private_Macros OPAMP Private Macros
00298   * @{
00299   */
00300
00301 #define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
00302                                                ((INPUT) == OPAMP_PGA_MODE) || \
00303                                                ((INPUT) == OPAMP_FOLLOWER_MODE))
00304
00305 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00306 #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
00307                                                     ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
00308 #endif
00309 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx)  || defined (STM32L442xx)  || defined (STM32L443xx)
00310 #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) ((INPUT) == OPAMP_INVERTINGINPUT_IO0)
00311 #endif
00312
00313 #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
00314                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))
00315
00316 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00317 #define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
00318                                              ((INPUT) == OPAMP_INVERTINGINPUT_IO1)|| \
00319                                              ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO))
00320 #endif
00321 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx)  || defined (STM32L442xx)  || defined (STM32L443xx)
00322 #define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
00323                                              ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO))
00324 #endif
00325
00326 #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
00327                                  ((GAIN) == OPAMP_PGA_GAIN_4) || \
00328                                  ((GAIN) == OPAMP_PGA_GAIN_8) || \
00329                                  ((GAIN) == OPAMP_PGA_GAIN_16))
00330
00331 #define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
00332                                       ((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) )
00333
00334 #define IS_OPAMP_POWER_SUPPLY_RANGE(RANGE) (((RANGE) == OPAMP_POWERSUPPLY_LOW) || \
00335                                             ((RANGE) == OPAMP_POWERSUPPLY_HIGH)  )
00336
00337 #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
00338                                      ((TRIMMING) == OPAMP_TRIMMING_USER))
00339
00340
00341 #define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
00342
00343 #define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
00344                                              ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
00345
00346 /**
00347   * @}
00348   */
00349
00350 /* Include OPAMP HAL Extended module */
00351 #include "stm32l4xx_hal_opamp_ex.h"
00352
00353 /* Exported functions --------------------------------------------------------*/
00354 /** @addtogroup OPAMP_Exported_Functions
00355   * @{
00356   */
00357
00358 /** @addtogroup OPAMP_Exported_Functions_Group1
00359   * @{
00360   */
00361 /* Initialization/de-initialization functions  **********************************/
00362 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
00363 HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
00364 void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
00365 void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
00366 /**
00367   * @}
00368   */
00369
00370 /** @addtogroup OPAMP_Exported_Functions_Group2
00371   * @{
00372   */
00373
00374 /* I/O operation functions  *****************************************************/
00375 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
00376 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
00377 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
00378
00379 /**
00380   * @}
00381   */
00382
00383 /** @addtogroup OPAMP_Exported_Functions_Group3
00384   * @{
00385   */
00386
00387 /* Peripheral Control functions  ************************************************/
00388 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
00389 HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
00390
00391 /**
00392   * @}
00393   */
00394
00395 /** @addtogroup OPAMP_Exported_Functions_Group4
00396   * @{
00397   */
00398
00399 /* Peripheral State functions  **************************************************/
00400 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
00401
00402 /**
00403   * @}
00404   */
00405
00406 /**
00407   * @}
00408   */
00409
00410 /**
00411   * @}
00412   */
00413
00414 /**
00415   * @}
00416   */
00417
00418 #ifdef __cplusplus
00419 }
00420 #endif
00421
00422 #endif /* __STM32L4xx_HAL_OPAMP_H */
00423
00424 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_opamp_ex.c Source File

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stm32l4xx_hal_opamp_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_opamp_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Extended OPAMP HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
00010   *          peripheral:
00011   *           + Extended Initialization and de-initialization functions
00012   *           + Extended Peripheral Control functions
00013   *
00014   @verbatim
00015   ******************************************************************************
00016   * @attention
00017   *
00018   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00019   *
00020   * Redistribution and use in source and binary forms, with or without modification,
00021   * are permitted provided that the following conditions are met:
00022   *   1. Redistributions of source code must retain the above copyright notice,
00023   *      this list of conditions and the following disclaimer.
00024   *   2. Redistributions in binary form must reproduce the above copyright notice,
00025   *      this list of conditions and the following disclaimer in the documentation
00026   *      and/or other materials provided with the distribution.
00027   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00028   *      may be used to endorse or promote products derived from this software
00029   *      without specific prior written permission.
00030   *
00031   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00032   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00033   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00034   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00035   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00036   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00037   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00038   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00039   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00040   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00041   *
00042   ******************************************************************************
00043   */
00044
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32l4xx_hal.h"
00047
00048 /** @addtogroup STM32L4xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @defgroup OPAMPEx OPAMPEx
00053   * @brief OPAMP Extended HAL module driver
00054   * @{
00055   */
00056
00057 #ifdef HAL_OPAMP_MODULE_ENABLED
00058
00059 /* Private typedef -----------------------------------------------------------*/
00060 /* Private define ------------------------------------------------------------*/
00061 /* Private macro -------------------------------------------------------------*/
00062 /* Private variables ---------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064 /* Exported functions --------------------------------------------------------*/
00065
00066 /** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
00067   * @{
00068   */
00069
00070 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00071
00072 /** @addtogroup OPAMPEx_Exported_Functions_Group1
00073   * @brief    Extended operation functions
00074   *
00075 @verbatim
00076  ===============================================================================
00077               ##### Extended IO operation functions #####
00078  ===============================================================================
00079   [..]
00080       (+) OPAMP Self calibration.
00081
00082 @endverbatim
00083   * @{
00084   */
00085
00086 /*  2 OPAMPS available */
00087 /*  2 OPAMPS can be calibrated in parallel */
00088 /*  Not available on STM32L43x/STM32L44x where only one OPAMP available */
00089
00090 /**
00091   * @brief  Run the self calibration of the 2 OPAMPs in parallel.
00092   * @note   Trimming values (PMOS & NMOS) are updated and user trimming is
00093   *         enabled is calibration is successful.
00094   * @note   Calibration is performed in the mode specified in OPAMP init
00095   *         structure (mode normal or low-power). To perform calibration for
00096   *         both modes, repeat this function twice after OPAMP init structure
00097   *         accordingly updated.
00098   * @note   Calibration runs about 10 ms (5 dichotomy steps, repeated for P
00099   *         and N transistors: 10 steps with 1 ms for each step).
00100   * @param  hopamp1 handle
00101   * @param  hopamp2 handle
00102   * @retval HAL status
00103   */
00104
00105 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
00106 {
00107   HAL_StatusTypeDef status = HAL_OK;
00108
00109   uint32_t trimmingvaluen1 = 0;
00110   uint32_t trimmingvaluep1 = 0;
00111   uint32_t trimmingvaluen2 = 0;
00112   uint32_t trimmingvaluep2 = 0;
00113
00114 /* Selection of register of trimming depending on power mode: OTR or LPOTR */
00115   __IO uint32_t* tmp_opamp1_reg_trimming;
00116   __IO uint32_t* tmp_opamp2_reg_trimming;
00117
00118   uint32_t delta;
00119   uint32_t opampmode1;
00120   uint32_t opampmode2;
00121
00122   if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
00123      (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED))
00124   {
00125     status = HAL_ERROR;
00126   }
00127   else
00128   {
00129     /* Check if OPAMP in calibration mode and calibration not yet enable */
00130     if((hopamp1->State ==  HAL_OPAMP_STATE_READY) && (hopamp2->State ==  HAL_OPAMP_STATE_READY))
00131     {
00132       /* Check the parameter */
00133       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
00134       assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
00135
00136       assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
00137       assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
00138
00139       /* Save OPAMP mode as in                                       */
00140       /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */
00141       /* the calibration is not working in PGA mode                  */
00142       opampmode1 = READ_BIT(hopamp1->Instance->CSR,OPAMP_CSR_OPAMODE);
00143       opampmode2 = READ_BIT(hopamp2->Instance->CSR,OPAMP_CSR_OPAMODE);
00144
00145       /* Use of standalone mode */
00146       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE);
00147       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE);
00148
00149       /*  user trimming values are used for offset calibration */
00150       SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
00151       SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
00152
00153       /* Select trimming settings depending on power mode */
00154       if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00155       {
00156         tmp_opamp1_reg_trimming = &OPAMP1->OTR;
00157       }
00158       else
00159       {
00160         tmp_opamp1_reg_trimming = &OPAMP1->LPOTR;
00161       }
00162
00163       if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
00164       {
00165         tmp_opamp2_reg_trimming = &OPAMP2->OTR;
00166       }
00167       else
00168       {
00169         tmp_opamp2_reg_trimming = &OPAMP2->LPOTR;
00170       }
00171
00172       /* Enable calibration */
00173       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00174       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00175
00176       /* 1st calibration - N */
00177       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL);
00178       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL);
00179
00180       /* Enable the selected opamp */
00181       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00182       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00183
00184       /* Init trimming counter */
00185       /* Medium value */
00186       trimmingvaluen1 = 16;
00187       trimmingvaluen2 = 16;
00188       delta = 8;
00189
00190       while (delta != 0)
00191       {
00192         /* Set candidate trimming */
00193         /* OPAMP_POWERMODE_NORMAL */
00194         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
00195         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
00196
00197         /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
00198         /* Offset trim time: during calibration, minimum time needed between */
00199         /* two steps to have 1 mV accuracy */
00200         HAL_Delay(OPAMP_TRIMMING_DELAY);
00201
00202         if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00203         {
00204           /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
00205           trimmingvaluen1 -= delta;
00206         }
00207         else
00208         {
00209           /* OPAMP_CSR_CALOUT is LOW try higher trimming */
00210           trimmingvaluen1 += delta;
00211         }
00212
00213         if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00214         {
00215           /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
00216           trimmingvaluen2 -= delta;
00217         }
00218         else
00219         {
00220           /* OPAMP_CSR_CALOUT is LOW try higher trimming */
00221           trimmingvaluen2 += delta;
00222         }
00223         /* Divide range by 2 to continue dichotomy sweep */
00224         delta >>= 1;
00225       }
00226
00227       /* Still need to check if right calibration is current value or one step below */
00228       /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1  */
00229       /* Set candidate trimming */
00230       MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
00231       MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
00232
00233       /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
00234       /* Offset trim time: during calibration, minimum time needed between */
00235       /* two steps to have 1 mV accuracy */
00236       HAL_Delay(OPAMP_TRIMMING_DELAY);
00237
00238       if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) == 0)
00239       {
00240         /* Trimming value is actually one value more */
00241         trimmingvaluen1++;
00242         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
00243       }
00244
00245       if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) == 0)
00246       {
00247         /* Trimming value is actually one value more */
00248         trimmingvaluen2++;
00249         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
00250       }
00251
00252       /* 2nd calibration - P */
00253       SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL);
00254       SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL);
00255
00256       /* Init trimming counter */
00257       /* Medium value */
00258       trimmingvaluep1 = 16;
00259       trimmingvaluep2 = 16;
00260       delta = 8;
00261
00262       while (delta != 0)
00263       {
00264         /* Set candidate trimming */
00265         /* OPAMP_POWERMODE_NORMAL */
00266         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
00267         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
00268
00269         /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
00270         /* Offset trim time: during calibration, minimum time needed between */
00271         /* two steps to have 1 mV accuracy */
00272         HAL_Delay(OPAMP_TRIMMING_DELAY);
00273
00274         if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00275         {
00276           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
00277           trimmingvaluep1 += delta;
00278         }
00279         else
00280         {
00281           /* OPAMP_CSR_CALOUT is HIGH try lower trimming */
00282           trimmingvaluep1 -= delta;
00283         }
00284
00285         if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00286         {
00287           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
00288           trimmingvaluep2 += delta;
00289         }
00290         else
00291         {
00292           /* OPAMP_CSR_CALOUT is LOW try lower trimming */
00293           trimmingvaluep2 -= delta;
00294         }
00295         /* Divide range by 2 to continue dichotomy sweep */
00296         delta >>= 1;
00297       }
00298
00299       /* Still need to check if right calibration is current value or one step below */
00300       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
00301       /* Set candidate trimming */
00302       MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
00303       MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
00304
00305       /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
00306       /* Offset trim time: during calibration, minimum time needed between */
00307       /* two steps to have 1 mV accuracy */
00308       HAL_Delay(OPAMP_TRIMMING_DELAY);
00309
00310       if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00311       {
00312         /* Trimming value is actually one value more */
00313         trimmingvaluep1++;
00314         MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
00315       }
00316
00317       if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)
00318       {
00319         /* Trimming value is actually one value more */
00320         trimmingvaluep2++;
00321         MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
00322       }
00323
00324       /* Disable the OPAMPs */
00325       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00326       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
00327
00328       /* Disable calibration & set normal mode (operating mode) */
00329       CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
00330       CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
00331
00332       /* Self calibration is successful */
00333       /* Store calibration (user trimming) results in init structure. */
00334
00335       /* Set user trimming mode */
00336       hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
00337       hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
00338
00339       /* Affect calibration parameters depending on mode normal/low power */
00340       if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
00341       {
00342         /* Write calibration result N */
00343         hopamp1->Init.TrimmingValueN = trimmingvaluen1;
00344         /* Write calibration result P */
00345         hopamp1->Init.TrimmingValueP = trimmingvaluep1;
00346       }
00347       else
00348       {
00349         /* Write calibration result N */
00350         hopamp1->Init.TrimmingValueNLowPower = trimmingvaluen1;
00351         /* Write calibration result P */
00352         hopamp1->Init.TrimmingValuePLowPower = trimmingvaluep1;
00353       }
00354
00355       if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
00356       {
00357         /* Write calibration result N */
00358         hopamp2->Init.TrimmingValueN = trimmingvaluen2;
00359         /* Write calibration result P */
00360         hopamp2->Init.TrimmingValueP = trimmingvaluep2;
00361       }
00362       else
00363       {
00364         /* Write calibration result N */
00365         hopamp2->Init.TrimmingValueNLowPower = trimmingvaluen2;
00366         /* Write calibration result P */
00367         hopamp2->Init.TrimmingValuePLowPower = trimmingvaluep2;
00368       }
00369
00370       /* Update OPAMP state */
00371       hopamp1->State = HAL_OPAMP_STATE_READY;
00372       hopamp2->State = HAL_OPAMP_STATE_READY;
00373
00374       /* Restore OPAMP mode after calibration */
00375       MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode1);
00376       MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode2);
00377     }
00378     else
00379     {
00380       /* At least one OPAMP can not be calibrated */
00381       status = HAL_ERROR;
00382     }
00383   }
00384   return status;
00385 }
00386
00387 /**
00388   * @}
00389   */
00390
00391 #endif
00392
00393 /** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions
00394  *  @brief   Peripheral Control functions
00395  *
00396 @verbatim
00397  ===============================================================================
00398              ##### Peripheral Control functions #####
00399  ===============================================================================
00400     [..]
00401       (+) OPAMP unlock.
00402
00403 @endverbatim
00404   * @{
00405   */
00406
00407 /**
00408   * @brief  Unlock the selected OPAMP configuration.
00409   * @note   This function must be called only when OPAMP is in state "locked".
00410   * @param  hopamp: OPAMP handle
00411   * @retval HAL status
00412   */
00413 HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp)
00414 {
00415   HAL_StatusTypeDef status = HAL_OK;
00416
00417   /* Check the OPAMP handle allocation */
00418   /* Check if OPAMP locked */
00419   if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET)
00420                       || (hopamp->State == HAL_OPAMP_STATE_READY)
00421                       || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
00422                       || (hopamp->State == HAL_OPAMP_STATE_BUSY))
00423
00424   {
00425     status = HAL_ERROR;
00426   }
00427   else
00428   {
00429     /* Check the parameter */
00430     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
00431
00432    /* OPAMP state changed to locked */
00433     hopamp->State = HAL_OPAMP_STATE_BUSY;
00434   }
00435   return status;
00436 }
00437
00438 /**
00439   * @}
00440   */
00441
00442 /**
00443   * @}
00444   */
00445
00446 #endif /* HAL_OPAMP_MODULE_ENABLED */
00447 /**
00448   * @}
00449   */
00450
00451 /**
00452   * @}
00453   */
00454
00455 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_opamp_ex.h Source File

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stm32l4xx_hal_opamp_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_opamp_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of OPAMP HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_OPAMP_EX_H
00040 #define __STM32L4xx_HAL_OPAMP_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup OPAMPEx
00054   * @{
00055   */
00056 /* Exported types ------------------------------------------------------------*/
00057 /* Exported constants --------------------------------------------------------*/
00058 /* Exported macro ------------------------------------------------------------*/
00059 /* Exported functions --------------------------------------------------------*/
00060 /** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
00061   * @{
00062   */
00063
00064 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00065
00066 /* I/O operation functions  *****************************************************/
00067 /** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
00068   * @{
00069   */
00070
00071 HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
00072
00073 /**
00074   * @}
00075   */
00076 #endif
00077
00078 /* Peripheral Control functions  ************************************************/
00079 /** @addtogroup OPAMPEx_Exported_Functions_Group2
00080   * @{
00081   */
00082 HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp);
00083 /**
00084   * @}
00085   */
00086
00087 /**
00088   * @}
00089   */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /**
00096   * @}
00097   */
00098
00099 #ifdef __cplusplus
00100 }
00101 #endif
00102
00103
00104 #endif /* __STM32L4xx_HAL_OPAMP_EX_H */
00105
00106 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pcd.c Source File

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stm32l4xx_hal_pcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pcd.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   PCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       The PCD HAL driver can be used as follows:
00021
00022      (#) Declare a PCD_HandleTypeDef handle structure, for example:
00023          PCD_HandleTypeDef  hpcd;
00024
00025      (#) Fill parameters of Init structure in HCD handle
00026
00027      (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
00028
00029      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
00030          (##) Enable the PCD/USB Low Level interface clock using
00031               (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
00032          (##) Initialize the related GPIO clocks
00033          (##) Configure PCD pin-out
00034          (##) Configure PCD NVIC interrupt
00035
00036      (#)Associate the Upper USB device stack to the HAL PCD Driver:
00037          (##) hpcd.pData = pdev;
00038
00039      (#)Enable PCD transmission and reception:
00040          (##) HAL_PCD_Start();
00041
00042   @endverbatim
00043   ******************************************************************************
00044   * @attention
00045   *
00046   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00047   *
00048   * Redistribution and use in source and binary forms, with or without modification,
00049   * are permitted provided that the following conditions are met:
00050   *   1. Redistributions of source code must retain the above copyright notice,
00051   *      this list of conditions and the following disclaimer.
00052   *   2. Redistributions in binary form must reproduce the above copyright notice,
00053   *      this list of conditions and the following disclaimer in the documentation
00054   *      and/or other materials provided with the distribution.
00055   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00056   *      may be used to endorse or promote products derived from this software
00057   *      without specific prior written permission.
00058   *
00059   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00060   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00061   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00062   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00063   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00064   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00065   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00066   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00067   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00068   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00069   *
00070   ******************************************************************************
00071   */
00072
00073 /* Includes ------------------------------------------------------------------*/
00074 #include "stm32l4xx_hal.h"
00075
00076 /** @addtogroup STM32L4xx_HAL_Driver
00077   * @{
00078   */
00079
00080 /** @defgroup PCD PCD
00081   * @brief PCD HAL module driver
00082   * @{
00083   */
00084
00085 #ifdef HAL_PCD_MODULE_ENABLED
00086
00087 #if defined(STM32L475xx) || defined(STM32L476xx) || \
00088     defined(STM32L485xx) || defined(STM32L486xx) || \
00089     defined(STM32L432xx) || defined(STM32L433xx) || \
00090     defined(STM32L442xx) || defined(STM32L443xx)
00091
00092 /* Private types -------------------------------------------------------------*/
00093 /* Private variables ---------------------------------------------------------*/
00094 /* Private constants ---------------------------------------------------------*/
00095 /* Private macros ------------------------------------------------------------*/
00096 /** @defgroup PCD_Private_Macros PCD Private Macros
00097   * @{
00098   */
00099 #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
00100 #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
00101 /**
00102   * @}
00103   */
00104
00105 /* Private functions prototypes ----------------------------------------------*/
00106 /** @defgroup PCD_Private_Functions PCD Private Functions
00107   * @{
00108   */
00109 #if defined (USB_OTG_FS)
00110 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
00111 #endif /* USB_OTG_FS */
00112 #if defined (USB)
00113 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
00114 #endif /* USB */
00115 /**
00116   * @}
00117   */
00118
00119 /* Exported functions --------------------------------------------------------*/
00120 /** @defgroup PCD_Exported_Functions PCD Exported Functions
00121   * @{
00122   */
00123
00124 /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00125  *  @brief    Initialization and Configuration functions
00126  *
00127 @verbatim
00128  ===============================================================================
00129             ##### Initialization and de-initialization functions #####
00130  ===============================================================================
00131     [..]  This section provides functions allowing to:
00132
00133 @endverbatim
00134   * @{
00135   */
00136
00137 /**
00138   * @brief  Initializes the PCD according to the specified
00139   *         parameters in the PCD_InitTypeDef and initialize the associated handle.
00140   * @param  hpcd: PCD handle
00141   * @retval HAL status
00142   */
00143 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
00144 {
00145   uint32_t index = 0;
00146
00147   /* Check the PCD handle allocation */
00148   if(hpcd == NULL)
00149   {
00150     return HAL_ERROR;
00151   }
00152
00153   /* Check the parameters */
00154   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
00155
00156   if(hpcd->State == HAL_PCD_STATE_RESET)
00157   {
00158     /* Allocate lock resource and initialize it */
00159     hpcd->Lock = HAL_UNLOCKED;
00160
00161     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00162     HAL_PCD_MspInit(hpcd);
00163   }
00164
00165   hpcd->State = HAL_PCD_STATE_BUSY;
00166
00167   /* Disable the Interrupts */
00168   __HAL_PCD_DISABLE(hpcd);
00169
00170   /*Init the Core (common init.) */
00171   USB_CoreInit(hpcd->Instance, hpcd->Init);
00172
00173   /* Force Device Mode*/
00174   USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE);
00175
00176   /* Init endpoints structures */
00177   for (index = 0; index < hpcd->Init.dev_endpoints ; index++)
00178   {
00179     /* Init ep structure */
00180     hpcd->IN_ep[index].is_in = 1;
00181     hpcd->IN_ep[index].num = index;
00182     hpcd->IN_ep[index].tx_fifo_num = index;
00183     /* Control until ep is activated */
00184     hpcd->IN_ep[index].type = EP_TYPE_CTRL;
00185     hpcd->IN_ep[index].maxpacket =  0;
00186     hpcd->IN_ep[index].xfer_buff = 0;
00187     hpcd->IN_ep[index].xfer_len = 0;
00188   }
00189
00190   for (index = 0; index < 15 ; index++)
00191   {
00192     hpcd->OUT_ep[index].is_in = 0;
00193     hpcd->OUT_ep[index].num = index;
00194     hpcd->IN_ep[index].tx_fifo_num = index;
00195     /* Control until ep is activated */
00196     hpcd->OUT_ep[index].type = EP_TYPE_CTRL;
00197     hpcd->OUT_ep[index].maxpacket = 0;
00198     hpcd->OUT_ep[index].xfer_buff = 0;
00199     hpcd->OUT_ep[index].xfer_len = 0;
00200   }
00201
00202   /* Init Device */
00203   USB_DevInit(hpcd->Instance, hpcd->Init);
00204
00205   hpcd->USB_Address = 0;
00206
00207   hpcd->State= HAL_PCD_STATE_READY;
00208
00209    /* Activate LPM */
00210   if (hpcd->Init.lpm_enable ==1)
00211   {
00212     HAL_PCDEx_ActivateLPM(hpcd);
00213   }
00214   /* Activate Battery charging */
00215   if (hpcd->Init.battery_charging_enable ==1)
00216   {
00217     HAL_PCDEx_ActivateBCD(hpcd);
00218   }
00219   USB_DevDisconnect (hpcd->Instance);
00220   return HAL_OK;
00221 }
00222
00223 /**
00224   * @brief  DeInitializes the PCD peripheral.
00225   * @param  hpcd: PCD handle
00226   * @retval HAL status
00227   */
00228 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
00229 {
00230   /* Check the PCD handle allocation */
00231   if(hpcd == NULL)
00232   {
00233     return HAL_ERROR;
00234   }
00235
00236   hpcd->State = HAL_PCD_STATE_BUSY;
00237
00238   /* Stop Device */
00239   HAL_PCD_Stop(hpcd);
00240
00241   /* DeInit the low level hardware */
00242   HAL_PCD_MspDeInit(hpcd);
00243
00244   hpcd->State = HAL_PCD_STATE_RESET;
00245
00246   return HAL_OK;
00247 }
00248
00249 /**
00250   * @brief  Initializes the PCD MSP.
00251   * @param  hpcd: PCD handle
00252   * @retval None
00253   */
00254 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
00255 {
00256   /* Prevent unused argument(s) compilation warning */
00257   UNUSED(hpcd);
00258
00259   /* NOTE : This function should not be modified, when the callback is needed,
00260             the HAL_PCD_MspInit could be implemented in the user file
00261    */
00262 }
00263
00264 /**
00265   * @brief  DeInitializes PCD MSP.
00266   * @param  hpcd: PCD handle
00267   * @retval None
00268   */
00269 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
00270 {
00271   /* Prevent unused argument(s) compilation warning */
00272   UNUSED(hpcd);
00273
00274   /* NOTE : This function should not be modified, when the callback is needed,
00275             the HAL_PCD_MspDeInit could be implemented in the user file
00276    */
00277 }
00278
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
00284  *  @brief   Data transfers functions
00285  *
00286 @verbatim
00287  ===============================================================================
00288                       ##### IO operation functions #####
00289  ===============================================================================
00290     [..]
00291     This subsection provides a set of functions allowing to manage the PCD data
00292     transfers.
00293
00294 @endverbatim
00295   * @{
00296   */
00297
00298 /**
00299   * @brief  Start The USB OTG Device.
00300   * @param  hpcd: PCD handle
00301   * @retval HAL status
00302   */
00303 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
00304 {
00305   __HAL_LOCK(hpcd);
00306   USB_DevConnect (hpcd->Instance);
00307   __HAL_PCD_ENABLE(hpcd);
00308   __HAL_UNLOCK(hpcd);
00309   return HAL_OK;
00310 }
00311
00312 /**
00313   * @brief  Stop The USB OTG Device.
00314   * @param  hpcd: PCD handle
00315   * @retval HAL status
00316   */
00317 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
00318 {
00319   __HAL_LOCK(hpcd);
00320   __HAL_PCD_DISABLE(hpcd);
00321   USB_StopDevice(hpcd->Instance);
00322   USB_DevDisconnect (hpcd->Instance);
00323   __HAL_UNLOCK(hpcd);
00324   return HAL_OK;
00325 }
00326 #if defined (USB_OTG_FS)
00327 /**
00328   * @brief  Handles PCD interrupt request.
00329   * @param  hpcd: PCD handle
00330   * @retval HAL status
00331   */
00332 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
00333 {
00334   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00335   uint32_t index = 0, ep_intr = 0, epint = 0, epnum = 0;
00336   uint32_t fifoemptymsk = 0, temp = 0;
00337   USB_OTG_EPTypeDef *ep = NULL;
00338   uint32_t hclk = 80000000;
00339
00340   /* ensure that we are in device mode */
00341   if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
00342   {
00343     /* avoid spurious interrupt */
00344     if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
00345     {
00346       return;
00347     }
00348
00349     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
00350     {
00351       /* incorrect mode, acknowledge the interrupt */
00352       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
00353     }
00354
00355     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
00356     {
00357       epnum = 0;
00358
00359       /* Read in the device interrupt bits */
00360       ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
00361
00362       while ( ep_intr )
00363       {
00364         if (ep_intr & 0x1)
00365         {
00366           epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
00367
00368           if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
00369           {
00370             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
00371
00372             if ((( (USBx_OUTEP(0)->DOEPINT & 0x8000) == 0)) )
00373             {
00374
00375               if(hpcd->Init.dma_enable == 1)
00376               {
00377                 hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
00378                 hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
00379               }
00380
00381               HAL_PCD_DataOutStageCallback(hpcd, epnum);
00382
00383               if(hpcd->Init.dma_enable == 1)
00384               {
00385                 if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))
00386                 {
00387                   /* this is ZLP, so prepare EP0 for next setup */
00388                   USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
00389                 }
00390               }
00391             }
00392             /* Clear the SetPktRcvd flag*/
00393             USBx_OUTEP(0)->DOEPINT |= 0x8020;
00394           }
00395
00396           if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
00397           {
00398             /* Inform the upper layer that a setup packet is available */
00399             HAL_PCD_SetupStageCallback(hpcd);
00400             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
00401           }
00402
00403           if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
00404           {
00405             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
00406           }
00407         }
00408         epnum++;
00409         ep_intr >>= 1;
00410       }
00411     }
00412
00413     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
00414     {
00415       /* Read in the device interrupt bits */
00416       ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
00417
00418       epnum = 0;
00419
00420       while ( ep_intr )
00421       {
00422         if (ep_intr & 0x1) /* In ITR */
00423         {
00424           epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
00425
00426           if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
00427           {
00428             fifoemptymsk = 0x1 << epnum;
00429             USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
00430
00431             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
00432
00433             if (hpcd->Init.dma_enable == 1)
00434             {
00435               hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
00436             }
00437
00438             HAL_PCD_DataInStageCallback(hpcd, epnum);
00439
00440             if (hpcd->Init.dma_enable == 1)
00441             {
00442               /* this is ZLP, so prepare EP0 for next setup */
00443               if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))
00444               {
00445                 /* prepare to rx more setup packets */
00446                 USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
00447               }
00448             }
00449           }
00450           if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
00451           {
00452             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
00453           }
00454           if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
00455           {
00456             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
00457           }
00458           if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
00459           {
00460             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
00461           }
00462           if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
00463           {
00464             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
00465           }
00466           if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
00467           {
00468             PCD_WriteEmptyTxFifo(hpcd , epnum);
00469           }
00470         }
00471         epnum++;
00472         ep_intr >>= 1;
00473       }
00474     }
00475
00476     /* Handle Resume Interrupt */
00477     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
00478     {
00479       /* Clear the Remote Wake-up Signaling */
00480       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
00481
00482       if(hpcd->LPM_State == LPM_L1)
00483       {
00484         hpcd->LPM_State = LPM_L0;
00485         HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
00486       }
00487       else
00488       {
00489         HAL_PCD_ResumeCallback(hpcd);
00490       }
00491
00492       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
00493     }
00494
00495     /* Handle Suspend Interrupt */
00496     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
00497     {
00498       if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
00499       {
00500
00501         HAL_PCD_SuspendCallback(hpcd);
00502       }
00503       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
00504     }
00505
00506     /* Handle LPM Interrupt */
00507     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
00508     {
00509       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
00510       if( hpcd->LPM_State == LPM_L0)
00511       {
00512         hpcd->LPM_State = LPM_L1;
00513         hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;
00514         HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
00515       }
00516       else
00517       {
00518         HAL_PCD_SuspendCallback(hpcd);
00519       }
00520     }
00521
00522     /* Handle Reset Interrupt */
00523     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
00524     {
00525       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
00526       USB_FlushTxFifo(hpcd->Instance ,  0 );
00527
00528       for (index = 0; index < hpcd->Init.dev_endpoints ; index++)
00529       {
00530         USBx_INEP(index)->DIEPINT = 0xFF;
00531         USBx_OUTEP(index)->DOEPINT = 0xFF;
00532       }
00533       USBx_DEVICE->DAINT = 0xFFFFFFFF;
00534       USBx_DEVICE->DAINTMSK |= 0x10001;
00535
00536       if(hpcd->Init.use_dedicated_ep1)
00537       {
00538         USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
00539         USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
00540       }
00541       else
00542       {
00543         USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
00544         USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
00545       }
00546
00547       /* Set Default Address to 0 */
00548       USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
00549
00550       /* setup EP0 to receive SETUP packets */
00551       USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
00552
00553       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
00554     }
00555
00556     /* Handle Enumeration done Interrupt */
00557     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
00558     {
00559       USB_ActivateSetup(hpcd->Instance);
00560       hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
00561
00562       hpcd->Init.speed            = USB_OTG_SPEED_FULL;
00563       hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;
00564
00565         /* The USBTRD is configured according to the tables below, depending on AHB frequency
00566         used by application. In the low AHB frequency range it is used to stretch enough the USB response
00567         time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
00568         latency to the Data FIFO */
00569
00570       /* Get hclk frequency value */
00571       hclk = HAL_RCC_GetHCLKFreq();
00572
00573       if((hclk >= 14200000)&&(hclk < 15000000))
00574       {
00575         /* hclk Clock Range between 14.2-15 MHz */
00576         hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);
00577       }
00578
00579       else if((hclk >= 15000000)&&(hclk < 16000000))
00580       {
00581         /* hclk Clock Range between 15-16 MHz */
00582         hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);
00583       }
00584
00585       else if((hclk >= 16000000)&&(hclk < 17200000))
00586       {
00587         /* hclk Clock Range between 16-17.2 MHz */
00588         hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);
00589       }
00590
00591       else if((hclk >= 17200000)&&(hclk < 18500000))
00592       {
00593         /* hclk Clock Range between 17.2-18.5 MHz */
00594         hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);
00595       }
00596
00597       else if((hclk >= 18500000)&&(hclk < 20000000))
00598       {
00599         /* hclk Clock Range between 18.5-20 MHz */
00600         hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);
00601       }
00602
00603       else if((hclk >= 20000000)&&(hclk < 21800000))
00604       {
00605         /* hclk Clock Range between 20-21.8 MHz */
00606         hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);
00607       }
00608
00609       else if((hclk >= 21800000)&&(hclk < 24000000))
00610       {
00611         /* hclk Clock Range between 21.8-24 MHz */
00612         hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);
00613       }
00614
00615       else if((hclk >= 24000000)&&(hclk < 27700000))
00616       {
00617         /* hclk Clock Range between 24-27.7 MHz */
00618         hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);
00619       }
00620
00621       else if((hclk >= 27700000)&&(hclk < 32000000))
00622       {
00623         /* hclk Clock Range between 27.7-32 MHz */
00624         hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);
00625       }
00626
00627       else /* if(hclk >= 32000000) */
00628       {
00629         /* hclk Clock Range between 32-80 MHz */
00630         hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);
00631       }
00632
00633       HAL_PCD_ResetCallback(hpcd);
00634
00635       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
00636     }
00637
00638     /* Handle RxQLevel Interrupt */
00639     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
00640     {
00641       USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00642
00643       temp = USBx->GRXSTSP;
00644
00645       ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
00646
00647       if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
00648       {
00649         if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
00650         {
00651           USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
00652           ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
00653           ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
00654         }
00655       }
00656       else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
00657       {
00658         USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
00659         ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
00660       }
00661       USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00662     }
00663
00664     /* Handle SOF Interrupt */
00665     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
00666     {
00667       HAL_PCD_SOFCallback(hpcd);
00668       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
00669     }
00670
00671     /* Handle Incomplete ISO IN Interrupt */
00672     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
00673     {
00674       HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
00675       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
00676     }
00677
00678     /* Handle Incomplete ISO OUT Interrupt */
00679     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00680     {
00681       HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
00682       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00683     }
00684
00685     /* Handle Connection event Interrupt */
00686     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
00687     {
00688       HAL_PCD_ConnectCallback(hpcd);
00689       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
00690     }
00691
00692     /* Handle Disconnection event Interrupt */
00693     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
00694     {
00695       temp = hpcd->Instance->GOTGINT;
00696
00697       if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
00698       {
00699         HAL_PCD_DisconnectCallback(hpcd);
00700       }
00701       hpcd->Instance->GOTGINT |= temp;
00702     }
00703   }
00704 }
00705
00706 #endif /* USB_OTG_FS */
00707
00708 #if defined (USB)
00709 /**
00710   * @brief  This function handles PCD interrupt request.
00711   * @param  hpcd: PCD handle
00712   * @retval HAL status
00713   */
00714 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
00715 {
00716   uint32_t wInterrupt_Mask = 0;
00717
00718   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
00719   {
00720     /* servicing of the endpoint correct transfer interrupt */
00721     /* clear of the CTR flag into the sub */
00722     PCD_EP_ISR_Handler(hpcd);
00723   }
00724
00725   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
00726   {
00727     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
00728     HAL_PCD_ResetCallback(hpcd);
00729     HAL_PCD_SetAddress(hpcd, 0);
00730   }
00731
00732   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
00733   {
00734     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
00735   }
00736
00737   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
00738   {
00739     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
00740   }
00741
00742   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
00743   {
00744
00745     hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE);
00746
00747     /*set wInterrupt_Mask global variable*/
00748     wInterrupt_Mask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
00749       | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
00750
00751     /*Set interrupt mask*/
00752     hpcd->Instance->CNTR = wInterrupt_Mask;
00753
00754     /* enable L1REQ interrupt */
00755     if (hpcd->Init.lpm_enable ==1)
00756     {
00757       wInterrupt_Mask |= USB_CNTR_L1REQM;
00758
00759       /* Enable LPM support and enable ACK answer to LPM request*/
00760       USB_TypeDef *USBx = hpcd->Instance;
00761       hpcd->lpm_active = ENABLE;
00762       hpcd->LPM_State = LPM_L0;
00763
00764       USBx->LPMCSR |= (USB_LPMCSR_LMPEN);
00765       USBx->LPMCSR |= (USB_LPMCSR_LPMACK);
00766     }
00767
00768     if(hpcd->LPM_State == LPM_L1)
00769     {
00770       hpcd->LPM_State = LPM_L0;
00771       HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
00772     }
00773
00774     HAL_PCD_ResumeCallback(hpcd);
00775
00776     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
00777   }
00778
00779   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
00780   {
00781     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
00782     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
00783
00784     /* Force low-power mode in the macrocell */
00785     hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
00786     hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
00787
00788     if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0)
00789     {
00790       HAL_PCD_SuspendCallback(hpcd);
00791     }
00792   }
00793
00794   /* Handle LPM Interrupt */
00795   if(__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ))
00796   {
00797     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
00798     if( hpcd->LPM_State == LPM_L0)
00799     {
00800       /* Force suspend and low-power mode before going to L1 state*/
00801       hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
00802       hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
00803
00804       hpcd->LPM_State = LPM_L1;
00805       hpcd->BESL = (hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >>2 ;
00806       HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
00807     }
00808     else
00809     {
00810       HAL_PCD_SuspendCallback(hpcd);
00811     }
00812   }
00813
00814   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
00815   {
00816     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
00817     HAL_PCD_SOFCallback(hpcd);
00818   }
00819
00820   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
00821   {
00822     /* clear ESOF flag in ISTR */
00823     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
00824   }
00825 }
00826 #endif /* USB */
00827
00828 /**
00829   * @brief  Data OUT stage callback.
00830   * @param  hpcd: PCD handle
00831   * @param  epnum: endpoint number
00832   * @retval None
00833   */
00834 __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00835 {
00836   /* Prevent unused argument(s) compilation warning */
00837   UNUSED(hpcd);
00838   UNUSED(epnum);
00839
00840   /* NOTE : This function should not be modified, when the callback is needed,
00841             the HAL_PCD_DataOutStageCallback could be implemented in the user file
00842    */
00843 }
00844
00845 /**
00846   * @brief  Data IN stage callback.
00847   * @param  hpcd: PCD handle
00848   * @param  epnum: endpoint number
00849   * @retval None
00850   */
00851 __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00852 {
00853   /* Prevent unused argument(s) compilation warning */
00854   UNUSED(hpcd);
00855   UNUSED(epnum);
00856
00857   /* NOTE : This function should not be modified, when the callback is needed,
00858             the HAL_PCD_DataInStageCallback could be implemented in the user file
00859    */
00860 }
00861 /**
00862   * @brief  Setup stage callback.
00863   * @param  hpcd: PCD handle
00864   * @retval None
00865   */
00866 __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
00867 {
00868   /* Prevent unused argument(s) compilation warning */
00869   UNUSED(hpcd);
00870
00871   /* NOTE : This function should not be modified, when the callback is needed,
00872             the HAL_PCD_SetupStageCallback could be implemented in the user file
00873    */
00874 }
00875
00876 /**
00877   * @brief  USB Start Of Frame callback.
00878   * @param  hpcd: PCD handle
00879   * @retval None
00880   */
00881 __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
00882 {
00883   /* Prevent unused argument(s) compilation warning */
00884   UNUSED(hpcd);
00885
00886   /* NOTE : This function should not be modified, when the callback is needed,
00887             the HAL_PCD_SOFCallback could be implemented in the user file
00888    */
00889 }
00890
00891 /**
00892   * @brief  USB Reset callback.
00893   * @param  hpcd: PCD handle
00894   * @retval None
00895   */
00896 __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
00897 {
00898   /* Prevent unused argument(s) compilation warning */
00899   UNUSED(hpcd);
00900
00901   /* NOTE : This function should not be modified, when the callback is needed,
00902             the HAL_PCD_ResetCallback could be implemented in the user file
00903    */
00904 }
00905
00906 /**
00907   * @brief  Suspend event callback.
00908   * @param  hpcd: PCD handle
00909   * @retval None
00910   */
00911 __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
00912 {
00913   /* Prevent unused argument(s) compilation warning */
00914   UNUSED(hpcd);
00915
00916   /* NOTE : This function should not be modified, when the callback is needed,
00917             the HAL_PCD_SuspendCallback could be implemented in the user file
00918    */
00919 }
00920
00921 /**
00922   * @brief  Resume event callback.
00923   * @param  hpcd: PCD handle
00924   * @retval None
00925   */
00926 __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
00927 {
00928   /* Prevent unused argument(s) compilation warning */
00929   UNUSED(hpcd);
00930
00931   /* NOTE : This function should not be modified, when the callback is needed,
00932             the HAL_PCD_ResumeCallback could be implemented in the user file
00933    */
00934 }
00935
00936 /**
00937   * @brief  Incomplete ISO OUT callback.
00938   * @param  hpcd: PCD handle
00939   * @param  epnum: endpoint number
00940   * @retval None
00941   */
00942 __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00943 {
00944   /* Prevent unused argument(s) compilation warning */
00945   UNUSED(hpcd);
00946   UNUSED(epnum);
00947
00948   /* NOTE : This function should not be modified, when the callback is needed,
00949             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
00950    */
00951 }
00952
00953 /**
00954   * @brief  Incomplete ISO IN callback.
00955   * @param  hpcd: PCD handle
00956   * @param  epnum: endpoint number
00957   * @retval None
00958   */
00959 __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00960 {
00961   /* Prevent unused argument(s) compilation warning */
00962   UNUSED(hpcd);
00963   UNUSED(epnum);
00964
00965   /* NOTE : This function should not be modified, when the callback is needed,
00966             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
00967    */
00968 }
00969
00970 /**
00971   * @brief  Connection event callback.
00972   * @param  hpcd: PCD handle
00973   * @retval None
00974   */
00975 __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
00976 {
00977   /* Prevent unused argument(s) compilation warning */
00978   UNUSED(hpcd);
00979
00980   /* NOTE : This function should not be modified, when the callback is needed,
00981             the HAL_PCD_ConnectCallback could be implemented in the user file
00982    */
00983 }
00984
00985 /**
00986   * @brief  Disconnection event callback.
00987   * @param  hpcd: PCD handle
00988   * @retval None
00989   */
00990 __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
00991 {
00992   /* Prevent unused argument(s) compilation warning */
00993   UNUSED(hpcd);
00994
00995   /* NOTE : This function should not be modified, when the callback is needed,
00996             the HAL_PCD_DisconnectCallback could be implemented in the user file
00997    */
00998 }
00999
01000 /**
01001   * @}
01002   */
01003
01004 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
01005  *  @brief   management functions
01006  *
01007 @verbatim
01008  ===============================================================================
01009                       ##### Peripheral Control functions #####
01010  ===============================================================================
01011     [..]
01012     This subsection provides a set of functions allowing to control the PCD data
01013     transfers.
01014
01015 @endverbatim
01016   * @{
01017   */
01018
01019 /**
01020   * @brief  Connect the USB device.
01021   * @param  hpcd: PCD handle
01022   * @retval HAL status
01023   */
01024 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
01025 {
01026   __HAL_LOCK(hpcd);
01027   USB_DevConnect(hpcd->Instance);
01028   __HAL_UNLOCK(hpcd);
01029   return HAL_OK;
01030 }
01031
01032 /**
01033   * @brief  Disconnect the USB device.
01034   * @param  hpcd: PCD handle
01035   * @retval HAL status
01036   */
01037 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
01038 {
01039   __HAL_LOCK(hpcd);
01040   USB_DevDisconnect(hpcd->Instance);
01041   __HAL_UNLOCK(hpcd);
01042   return HAL_OK;
01043 }
01044
01045 /**
01046   * @brief  Set the USB Device address.
01047   * @param  hpcd: PCD handle
01048   * @param  address: new device address
01049   * @retval HAL status
01050   */
01051 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
01052 {
01053   __HAL_LOCK(hpcd);
01054   hpcd->USB_Address = address;
01055   USB_SetDevAddress(hpcd->Instance, address);
01056   __HAL_UNLOCK(hpcd);
01057   return HAL_OK;
01058 }
01059 /**
01060   * @brief  Open and configure an endpoint.
01061   * @param  hpcd: PCD handle
01062   * @param  ep_addr: endpoint address
01063   * @param  ep_mps: endpoint max packet size
01064   * @param  ep_type: endpoint type
01065   * @retval HAL status
01066   */
01067 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
01068 {
01069   HAL_StatusTypeDef  ret = HAL_OK;
01070   PCD_EPTypeDef *ep = NULL;
01071
01072   if ((ep_addr & 0x80) == 0x80)
01073   {
01074     ep = &hpcd->IN_ep[ep_addr & 0x7F];
01075   }
01076   else
01077   {
01078     ep = &hpcd->OUT_ep[ep_addr & 0x7F];
01079   }
01080   ep->num   = ep_addr & 0x7F;
01081
01082   ep->is_in = (0x80 & ep_addr) != 0;
01083   ep->maxpacket = ep_mps;
01084   ep->type = ep_type;
01085
01086   __HAL_LOCK(hpcd);
01087   USB_ActivateEndpoint(hpcd->Instance , ep);
01088   __HAL_UNLOCK(hpcd);
01089   return ret;
01090
01091 }
01092
01093
01094 /**
01095   * @brief  Deactivate an endpoint.
01096   * @param  hpcd: PCD handle
01097   * @param  ep_addr: endpoint address
01098   * @retval HAL status
01099   */
01100 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01101 {
01102   PCD_EPTypeDef *ep = NULL;
01103
01104   if ((ep_addr & 0x80) == 0x80)
01105   {
01106     ep = &hpcd->IN_ep[ep_addr & 0x7F];
01107   }
01108   else
01109   {
01110     ep = &hpcd->OUT_ep[ep_addr & 0x7F];
01111   }
01112   ep->num   = ep_addr & 0x7F;
01113
01114   ep->is_in = (0x80 & ep_addr) != 0;
01115
01116   __HAL_LOCK(hpcd);
01117   USB_DeactivateEndpoint(hpcd->Instance , ep);
01118   __HAL_UNLOCK(hpcd);
01119   return HAL_OK;
01120 }
01121
01122
01123 /**
01124   * @brief  Receive an amount of data.
01125   * @param  hpcd: PCD handle
01126   * @param  ep_addr: endpoint address
01127   * @param  pBuf: pointer to the reception buffer
01128   * @param  len: amount of data to be received
01129   * @retval HAL status
01130   */
01131 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01132 {
01133   PCD_EPTypeDef *ep = NULL;
01134
01135   ep = &hpcd->OUT_ep[ep_addr & 0x7F];
01136
01137   /*setup and start the Xfer */
01138   ep->xfer_buff = pBuf;
01139   ep->xfer_len = len;
01140   ep->xfer_count = 0;
01141   ep->is_in = 0;
01142   ep->num = ep_addr & 0x7F;
01143
01144   __HAL_LOCK(hpcd);
01145
01146   if ((ep_addr & 0x7F) == 0 )
01147   {
01148     USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable);
01149   }
01150   else
01151   {
01152     USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable);
01153   }
01154   __HAL_UNLOCK(hpcd);
01155
01156   return HAL_OK;
01157 }
01158
01159 /**
01160   * @brief  Get Received Data Size.
01161   * @param  hpcd: PCD handle
01162   * @param  ep_addr: endpoint address
01163   * @retval Data Size
01164   */
01165 uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01166 {
01167   return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
01168 }
01169 /**
01170   * @brief  Send an amount of data.
01171   * @param  hpcd: PCD handle
01172   * @param  ep_addr: endpoint address
01173   * @param  pBuf: pointer to the transmission buffer
01174   * @param  len: amount of data to be sent
01175   * @retval HAL status
01176   */
01177 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01178 {
01179   PCD_EPTypeDef *ep = NULL;
01180
01181   ep = &hpcd->IN_ep[ep_addr & 0x7F];
01182
01183   /*setup and start the Xfer */
01184   ep->xfer_buff = pBuf;
01185   ep->xfer_len = len;
01186   ep->xfer_count = 0;
01187   ep->is_in = 1;
01188   ep->num = ep_addr & 0x7F;
01189
01190   __HAL_LOCK(hpcd);
01191
01192   if ((ep_addr & 0x7F) == 0 )
01193   {
01194     USB_EP0StartXfer(hpcd->Instance,ep,  hpcd->Init.dma_enable);
01195   }
01196   else
01197   {
01198     USB_EPStartXfer(hpcd->Instance, ep,  hpcd->Init.dma_enable);
01199   }
01200
01201   __HAL_UNLOCK(hpcd);
01202
01203   return HAL_OK;
01204 }
01205
01206 /**
01207   * @brief  Set a STALL condition over an endpoint.
01208   * @param  hpcd: PCD handle
01209   * @param  ep_addr: endpoint address
01210   * @retval HAL status
01211   */
01212 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01213 {
01214   PCD_EPTypeDef *ep = NULL;
01215
01216   if ((0x80 & ep_addr) == 0x80)
01217   {
01218     ep = &hpcd->IN_ep[ep_addr & 0x7F];
01219   }
01220   else
01221   {
01222     ep = &hpcd->OUT_ep[ep_addr];
01223   }
01224
01225   ep->is_stall = 1;
01226   ep->num   = ep_addr & 0x7F;
01227   ep->is_in = ((ep_addr & 0x80) == 0x80);
01228
01229   __HAL_LOCK(hpcd);
01230   USB_EPSetStall(hpcd->Instance , ep);
01231   if((ep_addr & 0x7F) == 0)
01232   {
01233     USB_EP0_OutStart(hpcd->Instance,  hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
01234   }
01235   __HAL_UNLOCK(hpcd);
01236
01237   return HAL_OK;
01238 }
01239
01240 /**
01241   * @brief  Clear a STALL condition over in an endpoint.
01242   * @param  hpcd: PCD handle
01243   * @param  ep_addr: endpoint address
01244   * @retval HAL status
01245   */
01246 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01247 {
01248   PCD_EPTypeDef *ep = NULL;
01249
01250   if ((0x80 & ep_addr) == 0x80)
01251   {
01252     ep = &hpcd->IN_ep[ep_addr & 0x7F];
01253   }
01254   else
01255   {
01256     ep = &hpcd->OUT_ep[ep_addr];
01257   }
01258
01259   ep->is_stall = 0;
01260   ep->num   = ep_addr & 0x7F;
01261   ep->is_in = ((ep_addr & 0x80) == 0x80);
01262
01263   __HAL_LOCK(hpcd);
01264   USB_EPClearStall(hpcd->Instance , ep);
01265   __HAL_UNLOCK(hpcd);
01266
01267   return HAL_OK;
01268 }
01269
01270 /**
01271   * @brief  Flush an endpoint.
01272   * @param  hpcd: PCD handle
01273   * @param  ep_addr: endpoint address
01274   * @retval HAL status
01275   */
01276 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01277 {
01278   __HAL_LOCK(hpcd);
01279
01280   if ((ep_addr & 0x80) == 0x80)
01281   {
01282     USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
01283   }
01284   else
01285   {
01286     USB_FlushRxFifo(hpcd->Instance);
01287   }
01288
01289   __HAL_UNLOCK(hpcd);
01290
01291   return HAL_OK;
01292 }
01293
01294 /**
01295   * @brief  Activate remote wakeup signalling.
01296   * @param  hpcd: PCD handle
01297   * @retval HAL status
01298   */
01299 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01300 {
01301   return(USB_ActivateRemoteWakeup(hpcd->Instance));
01302 }
01303
01304 /**
01305   * @brief  De-activate remote wakeup signalling.
01306   * @param  hpcd: PCD handle
01307   * @retval HAL status
01308   */
01309 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01310 {
01311   return(USB_DeActivateRemoteWakeup(hpcd->Instance));
01312 }
01313 /**
01314   * @}
01315   */
01316
01317 /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
01318  *  @brief   Peripheral State functions
01319  *
01320 @verbatim
01321  ===============================================================================
01322                       ##### Peripheral State functions #####
01323  ===============================================================================
01324     [..]
01325     This subsection permits to get in run-time the status of the peripheral
01326     and the data flow.
01327
01328 @endverbatim
01329   * @{
01330   */
01331
01332 /**
01333   * @brief  Return the PCD handle state.
01334   * @param  hpcd: PCD handle
01335   * @retval HAL state
01336   */
01337 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
01338 {
01339   return hpcd->State;
01340 }
01341 /**
01342   * @}
01343   */
01344
01345 /**
01346   * @}
01347   */
01348
01349 /* Private functions ---------------------------------------------------------*/
01350 /** @addtogroup PCD_Private_Functions
01351   * @{
01352   */
01353 #if defined (USB_OTG_FS)
01354 /**
01355   * @brief  Check FIFO for the next packet to be loaded.
01356   * @param  hpcd: PCD handle
01357   * @param  epnum: endpoint number
01358   * @retval HAL status
01359   */
01360 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
01361 {
01362   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01363   USB_OTG_EPTypeDef *ep = NULL;
01364   int32_t len = 0;
01365   uint32_t len32b = 0;
01366   uint32_t fifoemptymsk = 0;
01367
01368   ep = &hpcd->IN_ep[epnum];
01369   len = ep->xfer_len - ep->xfer_count;
01370
01371   if (len > ep->maxpacket)
01372   {
01373     len = ep->maxpacket;
01374   }
01375
01376
01377   len32b = (len + 3) / 4;
01378
01379   while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
01380           ep->xfer_count < ep->xfer_len &&
01381             ep->xfer_len != 0)
01382   {
01383     /* Write the FIFO */
01384     len = ep->xfer_len - ep->xfer_count;
01385
01386     if (len > ep->maxpacket)
01387     {
01388       len = ep->maxpacket;
01389     }
01390     len32b = (len + 3) / 4;
01391
01392     USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable);
01393
01394     ep->xfer_buff  += len;
01395     ep->xfer_count += len;
01396   }
01397
01398   if(len <= 0)
01399   {
01400     fifoemptymsk = 0x1 << epnum;
01401     USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
01402
01403   }
01404
01405   return HAL_OK;
01406 }
01407 #endif /* USB_OTG_FS */
01408
01409 #if defined (USB)
01410 /**
01411   * @brief  This function handles PCD Endpoint interrupt request.
01412   * @param  hpcd: PCD handle
01413   * @retval HAL status
01414   */
01415 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
01416 {
01417   PCD_EPTypeDef *ep = NULL;
01418   uint16_t count = 0;
01419   uint8_t epindex = 0;
01420   __IO uint16_t wIstr = 0;
01421   __IO uint16_t wEPVal = 0;
01422
01423   /* stay in loop while pending interrupts */
01424   while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
01425   {
01426     /* extract highest priority endpoint number */
01427     epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
01428
01429     if (epindex == 0)
01430     {
01431       /* Decode and service control endpoint interrupt */
01432
01433       /* DIR bit = origin of the interrupt */
01434       if ((wIstr & USB_ISTR_DIR) == 0)
01435       {
01436         /* DIR = 0 */
01437
01438         /* DIR = 0      => IN  int */
01439         /* DIR = 0 implies that (EP_CTR_TX = 1) always  */
01440         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01441         ep = &hpcd->IN_ep[0];
01442
01443         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01444         ep->xfer_buff += ep->xfer_count;
01445
01446         /* TX COMPLETE */
01447         HAL_PCD_DataInStageCallback(hpcd, 0);
01448
01449
01450         if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
01451         {
01452           hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
01453           hpcd->USB_Address = 0;
01454         }
01455
01456       }
01457       else
01458       {
01459         /* DIR = 1 */
01460
01461         /* DIR = 1 & CTR_RX       => SETUP or OUT int */
01462         /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
01463         ep = &hpcd->OUT_ep[0];
01464         wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
01465
01466         if ((wEPVal & USB_EP_SETUP) != 0)
01467         {
01468           /* Get SETUP Packet*/
01469           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01470           USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
01471           /* SETUP bit kept frozen while CTR_RX = 1*/
01472           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01473
01474           /* Process SETUP Packet*/
01475           HAL_PCD_SetupStageCallback(hpcd);
01476         }
01477
01478         else if ((wEPVal & USB_EP_CTR_RX) != 0)
01479         {
01480           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01481           /* Get Control Data OUT Packet*/
01482           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01483
01484           if (ep->xfer_count != 0)
01485           {
01486             USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
01487             ep->xfer_buff+=ep->xfer_count;
01488           }
01489
01490           /* Process Control Data OUT Packet*/
01491            HAL_PCD_DataOutStageCallback(hpcd, 0);
01492
01493           PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
01494           PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
01495         }
01496       }
01497     }
01498     else
01499     {
01500       /* Decode and service non control endpoints interrupt  */
01501
01502       /* process related endpoint register */
01503       wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
01504       if ((wEPVal & USB_EP_CTR_RX) != 0)
01505       {
01506         /* clear int flag */
01507         PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
01508         ep = &hpcd->OUT_ep[epindex];
01509
01510         /* OUT double Buffering*/
01511         if (ep->doublebuffer == 0)
01512         {
01513           count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01514           if (count != 0)
01515           {
01516             USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
01517           }
01518         }
01519         else
01520         {
01521           if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
01522           {
01523             /*read from endpoint BUF0Addr buffer*/
01524             count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
01525             if (count != 0)
01526             {
01527               USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
01528             }
01529           }
01530           else
01531           {
01532             /*read from endpoint BUF1Addr buffer*/
01533             count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
01534             if (count != 0)
01535             {
01536               USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
01537             }
01538           }
01539           PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
01540         }
01541         /*multi-packet on the NON control OUT endpoint*/
01542         ep->xfer_count+=count;
01543         ep->xfer_buff+=count;
01544
01545         if ((ep->xfer_len == 0) || (count < ep->maxpacket))
01546         {
01547           /* RX COMPLETE */
01548           HAL_PCD_DataOutStageCallback(hpcd, ep->num);
01549         }
01550         else
01551         {
01552           HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
01553         }
01554
01555       } /* if((wEPVal & EP_CTR_RX) */
01556
01557       if ((wEPVal & USB_EP_CTR_TX) != 0)
01558       {
01559         ep = &hpcd->IN_ep[epindex];
01560
01561         /* clear int flag */
01562         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
01563
01564         /* IN double Buffering*/
01565         if (ep->doublebuffer == 0)
01566         {
01567           ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01568           if (ep->xfer_count != 0)
01569           {
01570             USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
01571           }
01572         }
01573         else
01574         {
01575           if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
01576           {
01577             /*read from endpoint BUF0Addr buffer*/
01578             ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
01579             if (ep->xfer_count != 0)
01580             {
01581               USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
01582             }
01583           }
01584           else
01585           {
01586             /*read from endpoint BUF1Addr buffer*/
01587             ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
01588             if (ep->xfer_count != 0)
01589             {
01590               USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
01591             }
01592           }
01593           PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
01594         }
01595         /*multi-packet on the NON control IN endpoint*/
01596         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01597         ep->xfer_buff+=ep->xfer_count;
01598
01599         /* Zero Length Packet? */
01600         if (ep->xfer_len == 0)
01601         {
01602           /* TX COMPLETE */
01603           HAL_PCD_DataInStageCallback(hpcd, ep->num);
01604         }
01605         else
01606         {
01607           HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
01608         }
01609       }
01610     }
01611   }
01612   return HAL_OK;
01613 }
01614 #endif /* USB */
01615
01616 /**
01617   * @}
01618   */
01619
01620 /**
01621   * @}
01622   */
01623
01624 #endif /* STM32L475xx || STM32L476xx || */
01625        /* STM32L485xx || STM32L486xx || */
01626        /* STM32L432xx || STM32L433xx || */
01627        /* STM32L442xx || STM32L443xx    */
01628
01629 #endif /* HAL_PCD_MODULE_ENABLED */
01630
01631
01632 /**
01633   * @}
01634   */
01635
01636 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pcd.h Source File

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stm32l4xx_hal_pcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pcd.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of PCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_PCD_H
00040 #define __STM32L4xx_HAL_PCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32L475xx) || defined(STM32L476xx) || \
00047     defined(STM32L485xx) || defined(STM32L486xx) || \
00048     defined(STM32L432xx) || defined(STM32L433xx) || \
00049     defined(STM32L442xx) || defined(STM32L443xx)
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32l4xx_ll_usb.h"
00053
00054 /** @addtogroup STM32L4xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @addtogroup PCD
00059   * @{
00060   */
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 /** @defgroup PCD_Exported_Types PCD Exported Types
00064   * @{
00065   */
00066
00067    /**
00068   * @brief  PCD State structure definition
00069   */
00070 typedef enum
00071 {
00072   HAL_PCD_STATE_RESET   = 0x00,
00073   HAL_PCD_STATE_READY   = 0x01,
00074   HAL_PCD_STATE_ERROR   = 0x02,
00075   HAL_PCD_STATE_BUSY    = 0x03,
00076   HAL_PCD_STATE_TIMEOUT = 0x04
00077 } PCD_StateTypeDef;
00078
00079 /* Device LPM suspend state */
00080 typedef enum
00081 {
00082   LPM_L0 = 0x00, /* on */
00083   LPM_L1 = 0x01, /* LPM L1 sleep */
00084   LPM_L2 = 0x02, /* suspend */
00085   LPM_L3 = 0x03, /* off */
00086 }PCD_LPM_StateTypeDef;
00087
00088 #if defined (USB)
00089 /**
00090   * @brief  PCD double buffered endpoint direction
00091   */
00092 typedef enum
00093 {
00094   PCD_EP_DBUF_OUT,
00095   PCD_EP_DBUF_IN,
00096   PCD_EP_DBUF_ERR,
00097 }PCD_EP_DBUF_DIR;
00098
00099 /**
00100   * @brief  PCD endpoint buffer number
00101   */
00102 typedef enum
00103 {
00104   PCD_EP_NOBUF,
00105   PCD_EP_BUF0,
00106   PCD_EP_BUF1
00107 }PCD_EP_BUF_NUM;
00108 #endif /* USB */
00109
00110 #if defined (USB_OTG_FS)
00111 typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
00112 typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
00113 typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
00114 #endif /* USB_OTG_FS */
00115
00116 #if defined (USB)
00117 typedef USB_TypeDef        PCD_TypeDef;
00118 typedef USB_CfgTypeDef     PCD_InitTypeDef;
00119 typedef USB_EPTypeDef      PCD_EPTypeDef;
00120 #endif /* USB */
00121
00122 /**
00123   * @brief  PCD Handle Structure definition
00124   */
00125 typedef struct
00126 {
00127   PCD_TypeDef             *Instance;   /*!< Register base address              */
00128   PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
00129   __IO uint8_t            USB_Address; /*!< USB Address: not used by USB OTG FS */
00130   PCD_EPTypeDef           IN_ep[15];    /*!< IN endpoint parameters             */
00131   PCD_EPTypeDef           OUT_ep[15];   /*!< OUT endpoint parameters            */
00132   HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
00133   __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
00134   uint32_t                Setup[12];   /*!< Setup packet buffer                */
00135   PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
00136   uint32_t                BESL;
00137
00138
00139   uint32_t lpm_active;                  /*!< Enable or disable the Link Power Management .
00140                                         This parameter can be set to ENABLE or DISABLE                      */
00141
00142   uint32_t battery_charging_active;     /*!< Enable or disable Battery charging.
00143                                         This parameter can be set to ENABLE or DISABLE                      */
00144   void                    *pData;      /*!< Pointer to upper stack Handler     */
00145
00146 } PCD_HandleTypeDef;
00147
00148 /**
00149   * @}
00150   */
00151
00152 /* Include PCD HAL Extended module */
00153 #include "stm32l4xx_hal_pcd_ex.h"
00154
00155 /* Exported constants --------------------------------------------------------*/
00156 /** @defgroup PCD_Exported_Constants PCD Exported Constants
00157   * @{
00158   */
00159
00160 /** @defgroup PCD_Speed PCD Speed
00161   * @{
00162   */
00163 #define PCD_SPEED_FULL               1
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup PCD_PHY_Module PCD PHY Module
00169   * @{
00170   */
00171 #define PCD_PHY_EMBEDDED             1
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
00177   * @{
00178   */
00179 #ifndef USBD_FS_TRDT_VALUE
00180  #define USBD_FS_TRDT_VALUE           5
00181 #endif /* USBD_FS_TRDT_VALUE */
00182 /**
00183   * @}
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /* Exported macros -----------------------------------------------------------*/
00191 /** @defgroup PCD_Exported_Macros PCD Exported Macros
00192  *  @brief macros to handle interrupts and specific clock configurations
00193  * @{
00194  */
00195 #if defined (USB_OTG_FS)
00196 #define __HAL_PCD_ENABLE(__HANDLE__)                       USB_EnableGlobalInt ((__HANDLE__)->Instance)
00197 #define __HAL_PCD_DISABLE(__HANDLE__)                      USB_DisableGlobalInt ((__HANDLE__)->Instance)
00198
00199 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00200 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
00201 #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
00202
00203
00204 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
00205                                                           ~(USB_OTG_PCGCCTL_STOPCLK)
00206
00207 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
00208
00209 #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
00210
00211 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE
00212 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
00213 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
00214 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE
00215
00216 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()  do {\
00217                                                              EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00218                                                              EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
00219                                                            } while(0)
00220
00221 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\
00222                                                              EXTI->FTSR1 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
00223                                                              EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00224                                                            } while(0)
00225
00226 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\
00227                                                                    EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00228                                                                    EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
00229                                                                    EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
00230                                                                    EXTI->FTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
00231                                                                   } while(0)
00232
00233 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE)
00234
00235 #endif /* USB_OTG_FS */
00236
00237 #if defined (USB)
00238 #define __HAL_PCD_ENABLE(__HANDLE__)                                  USB_EnableGlobalInt ((__HANDLE__)->Instance)
00239 #define __HAL_PCD_DISABLE(__HANDLE__)                                 USB_DisableGlobalInt ((__HANDLE__)->Instance)
00240 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00241 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
00242
00243 #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                             EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
00244 #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                            EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
00245 #define __HAL_USB_WAKEUP_EXTI_GET_FLAG()                              EXTI->PR1 & (USB_WAKEUP_EXTI_LINE)
00246 #define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG()                            EXTI->PR1 = USB_WAKEUP_EXTI_LINE
00247
00248 #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE()                    do {\
00249                                                                         EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
00250                                                                         EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\
00251                                                                       } while(0)
00252
00253 #define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE()                   do {\
00254                                                                         EXTI->FTSR1 |= (USB_WAKEUP_EXTI_LINE);\
00255                                                                         EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
00256                                                                       } while(0)
00257
00258 #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()            do {\
00259                                                                         EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
00260                                                                         EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\
00261                                                                         EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\
00262                                                                         EXTI->FTSR1 |= USB_WAKEUP_EXTI_LINE;\
00263                                                                       } while(0)
00264
00265 #define __HAL_USB_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER1 |= USB_WAKEUP_EXTI_LINE)
00266
00267 #endif /* USB */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
00274   * @{
00275   */
00276
00277 /* Initialization/de-initialization functions  ********************************/
00278 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00279   * @{
00280   */
00281 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
00282 HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
00283 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
00284 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
00285 /**
00286   * @}
00287   */
00288
00289 /* I/O operation functions  ***************************************************/
00290 /* Non-Blocking mode: Interrupt */
00291 /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
00292   * @{
00293   */
00294  /* Non-Blocking mode: Interrupt */
00295 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
00296 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
00297 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
00298
00299 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00300 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00301 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
00302 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
00303 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
00304 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
00305 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
00306 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00307 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00308 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
00309 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
00310 /**
00311   * @}
00312   */
00313
00314 /* Peripheral Control functions  **********************************************/
00315 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00316   * @{
00317   */
00318 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00319 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00320 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00321 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00322 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00323 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00324 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00325 uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00326 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00327 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00328 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00329 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00330 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00331 /**
00332   * @}
00333   */
00334
00335 /* Peripheral State functions  ************************************************/
00336 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00337   * @{
00338   */
00339 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
00340 /**
00341   * @}
00342   */
00343
00344 /**
00345   * @}
00346   */
00347
00348 /* Private constants ---------------------------------------------------------*/
00349 /** @defgroup PCD_Private_Constants PCD Private Constants
00350   * @{
00351   */
00352 /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
00353   * @{
00354   */
00355 #if defined (USB_OTG_FS)
00356 #define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            ((uint32_t)0x08)
00357 #define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           ((uint32_t)0x0C)
00358 #define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    ((uint32_t)0x10)
00359
00360 #define USB_OTG_FS_WAKEUP_EXTI_LINE                                   ((uint32_t)0x00020000)  /*!< External interrupt line 17 Connected to the USB EXTI Line */
00361 #endif /* USB_OTG_FS */
00362
00363 #if defined (USB)
00364 #define  USB_WAKEUP_EXTI_LINE                                         ((uint32_t)0x00020000)  /*!< External interrupt line 17Connected to the USB EXTI Line */
00365 #endif /* USB */
00366
00367 /**
00368   * @}
00369   */
00370
00371 #if defined (USB)
00372 /** @defgroup PCD_EP0_MPS PCD EP0 MPS
00373   * @{
00374   */
00375 #define PCD_EP0MPS_64                                                 DEP0CTL_MPS_64
00376 #define PCD_EP0MPS_32                                                 DEP0CTL_MPS_32
00377 #define PCD_EP0MPS_16                                                 DEP0CTL_MPS_16
00378 #define PCD_EP0MPS_08                                                 DEP0CTL_MPS_8
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup PCD_ENDP PCD ENDP
00384   * @{
00385   */
00386 #define PCD_ENDP0                                                     ((uint8_t)0)
00387 #define PCD_ENDP1                                                     ((uint8_t)1)
00388 #define PCD_ENDP2                                                     ((uint8_t)2)
00389 #define PCD_ENDP3                                                     ((uint8_t)3)
00390 #define PCD_ENDP4                                                     ((uint8_t)4)
00391 #define PCD_ENDP5                                                     ((uint8_t)5)
00392 #define PCD_ENDP6                                                     ((uint8_t)6)
00393 #define PCD_ENDP7                                                     ((uint8_t)7)
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
00399   * @{
00400   */
00401 #define PCD_SNG_BUF                                                   0
00402 #define PCD_DBL_BUF                                                   1
00403 /**
00404   * @}
00405   */
00406 #endif /* USB */
00407 /**
00408   * @}
00409   */
00410
00411 /* Private macros ------------------------------------------------------------*/
00412 /** @addtogroup PCD_Private_Macros PCD Private Macros
00413  * @{
00414  */
00415 #if defined (USB)
00416 /* SetENDPOINT */
00417 #define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue)  (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
00418
00419 /* GetENDPOINT */
00420 #define PCD_GET_ENDPOINT(USBx, bEpNum)            (*(&(USBx)->EP0R + (bEpNum) * 2))
00421
00422 /* ENDPOINT transfer */
00423 #define USB_EP0StartXfer                          USB_EPStartXfer
00424
00425 /**
00426   * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
00427   * @param  USBx: USB peripheral instance register address.
00428   * @param  bEpNum: Endpoint Number.
00429   * @param  wType: Endpoint Type.
00430   * @retval None
00431   */
00432 #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
00433                                   ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
00434
00435 /**
00436   * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
00437   * @param  USBx: USB peripheral instance register address.
00438   * @param  bEpNum: Endpoint Number.
00439   * @retval Endpoint Type
00440   */
00441 #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
00442
00443 /**
00444   * @brief free buffer used from the application realizing it to the line
00445           toggles bit SW_BUF in the double buffered endpoint register
00446   * @param  USBx: USB peripheral instance register address.
00447   * @param  bEpNum: Endpoint Number.
00448   * @param  bDir: Direction
00449   * @retval None
00450   */
00451 #define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
00452 {\
00453   if ((bDir) == PCD_EP_DBUF_OUT)\
00454   { /* OUT double buffered endpoint */\
00455     PCD_TX_DTOG((USBx), (bEpNum));\
00456   }\
00457   else if ((bDir) == PCD_EP_DBUF_IN)\
00458   { /* IN double buffered endpoint */\
00459     PCD_RX_DTOG((USBx), (bEpNum));\
00460   }\
00461 }
00462
00463 /**
00464   * @brief gets direction of the double buffered endpoint
00465   * @param   USBx: USB peripheral instance register address.
00466   * @param   bEpNum: Endpoint Number.
00467   * @retval EP_DBUF_OUT, EP_DBUF_IN,
00468   *         EP_DBUF_ERR if the endpoint counter not yet programmed.
00469   */
00470 #define PCD_GET_DB_DIR(USBx, bEpNum)\
00471 {\
00472   if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
00473     return(PCD_EP_DBUF_OUT);\
00474   else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
00475     return(PCD_EP_DBUF_IN);\
00476   else\
00477     return(PCD_EP_DBUF_ERR);\
00478 }
00479
00480 /**
00481   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
00482   * @param  USBx: USB peripheral instance register address.
00483   * @param  bEpNum: Endpoint Number.
00484   * @param  wState: new state
00485   * @retval None
00486   */
00487 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
00488    \
00489     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
00490    /* toggle first bit ? */     \
00491    if((USB_EPTX_DTOG1 & (wState))!= 0)\
00492    {                                                                            \
00493      _wRegVal ^= USB_EPTX_DTOG1;        \
00494    }                                                                            \
00495    /* toggle second bit ?  */         \
00496    if((USB_EPTX_DTOG2 & (wState))!= 0)      \
00497    {                                                                            \
00498      _wRegVal ^= USB_EPTX_DTOG2;        \
00499    }                                                                            \
00500    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\
00501   } /* PCD_SET_EP_TX_STATUS */
00502
00503 /**
00504   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
00505   * @param  USBx: USB peripheral instance register address.
00506   * @param  bEpNum: Endpoint Number.
00507   * @param  wState: new state
00508   * @retval None
00509   */
00510 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
00511     register uint16_t _wRegVal;   \
00512     \
00513     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
00514     /* toggle first bit ? */  \
00515     if((USB_EPRX_DTOG1 & (wState))!= 0) \
00516     {                                                                             \
00517       _wRegVal ^= USB_EPRX_DTOG1;  \
00518     }                                                                             \
00519     /* toggle second bit ? */  \
00520     if((USB_EPRX_DTOG2 & (wState))!= 0) \
00521     {                                                                             \
00522       _wRegVal ^= USB_EPRX_DTOG2;  \
00523     }                                                                             \
00524     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
00525   } /* PCD_SET_EP_RX_STATUS */
00526
00527 /**
00528   * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
00529   * @param  USBx: USB peripheral instance register address.
00530   * @param  bEpNum: Endpoint Number.
00531   * @param  wStaterx: new state.
00532   * @param  wStatetx: new state.
00533   * @retval None
00534   */
00535 #define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
00536     register uint32_t _wRegVal;   \
00537     \
00538     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
00539     /* toggle first bit ? */  \
00540     if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
00541     {                                                                                    \
00542       _wRegVal ^= USB_EPRX_DTOG1;  \
00543     }                                                                                    \
00544     /* toggle second bit ? */  \
00545     if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
00546     {                                                                                    \
00547       _wRegVal ^= USB_EPRX_DTOG2;  \
00548     }                                                                                    \
00549     /* toggle first bit ? */     \
00550     if((USB_EPTX_DTOG1 & (wStatetx))!= 0)      \
00551     {                                                                                    \
00552       _wRegVal ^= USB_EPTX_DTOG1;        \
00553     }                                                                                    \
00554     /* toggle second bit ?  */         \
00555     if((USB_EPTX_DTOG2 & (wStatetx))!= 0)      \
00556     {                                                                                    \
00557       _wRegVal ^= USB_EPTX_DTOG2;        \
00558     }                                                                                    \
00559     PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX);    \
00560   } /* PCD_SET_EP_TXRX_STATUS */
00561
00562 /**
00563   * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
00564   *         /STAT_RX[1:0])
00565   * @param  USBx: USB peripheral instance register address.
00566   * @param  bEpNum: Endpoint Number.
00567   * @retval status
00568   */
00569 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
00570 #define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
00571
00572 /**
00573   * @brief  sets directly the VALID tx/rx-status into the endpoint register
00574   * @param  USBx: USB peripheral instance register address.
00575   * @param  bEpNum: Endpoint Number.
00576   * @retval None
00577   */
00578 #define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
00579 #define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
00580
00581 /**
00582   * @brief  checks stall condition in an endpoint.
00583   * @param  USBx: USB peripheral instance register address.
00584   * @param  bEpNum: Endpoint Number.
00585   * @retval TRUE = endpoint in stall condition.
00586   */
00587 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
00588                                    == USB_EP_TX_STALL)
00589 #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
00590                                    == USB_EP_RX_STALL)
00591
00592 /**
00593   * @brief  set & clear EP_KIND bit.
00594   * @param  USBx: USB peripheral instance register address.
00595   * @param  bEpNum: Endpoint Number.
00596   * @retval None
00597   */
00598 #define PCD_SET_EP_KIND(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00599                                 (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
00600 #define PCD_CLEAR_EP_KIND(USBx, bEpNum)  (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00601                                 (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
00602
00603 /**
00604   * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
00605   * @param  USBx: USB peripheral instance register address.
00606   * @param  bEpNum: Endpoint Number.
00607   * @retval None
00608   */
00609 #define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))
00610 #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))
00611
00612 /**
00613   * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
00614   * @param  USBx: USB peripheral instance register address.
00615   * @param  bEpNum: Endpoint Number.
00616   * @retval None
00617   */
00618 #define PCD_SET_EP_DBUF(USBx, bEpNum)          PCD_SET_EP_KIND((USBx), (bEpNum))
00619 #define PCD_CLEAR_EP_DBUF(USBx, bEpNum)        PCD_CLEAR_EP_KIND((USBx), (bEpNum))
00620
00621 /**
00622   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
00623   * @param  USBx: USB peripheral instance register address.
00624   * @param  bEpNum: Endpoint Number.
00625   * @retval None
00626   */
00627 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
00628                                    PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
00629 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
00630                                    PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
00631
00632 /**
00633   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
00634   * @param  USBx: USB peripheral instance register address.
00635   * @param  bEpNum: Endpoint Number.
00636   * @retval None
00637   */
00638 #define PCD_RX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00639                                    USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
00640 #define PCD_TX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00641                                    USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
00642
00643 /**
00644   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
00645   * @param  USBx: USB peripheral instance register address.
00646   * @param  bEpNum: Endpoint Number.
00647   * @retval None
00648   */
00649 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
00650                                          {                                                              \
00651                                            PCD_RX_DTOG((USBx), (bEpNum));                               \
00652                                          }
00653 #define PCD_CLEAR_TX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
00654                                          {                                                              \
00655                                             PCD_TX_DTOG((USBx), (bEpNum));                              \
00656                                          }
00657
00658 /**
00659   * @brief  Sets address in an endpoint register.
00660   * @param  USBx: USB peripheral instance register address.
00661   * @param  bEpNum: Endpoint Number.
00662   * @param  bAddr: Address.
00663   * @retval None
00664   */
00665 #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
00666     USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
00667
00668 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
00669
00670 #define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+     ((uint32_t)(USBx) + 0x400)))
00671 #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+  ((uint32_t)(USBx) + 0x400)))
00672 #define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+  ((uint32_t)(USBx) + 0x400)))
00673 #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+  ((uint32_t)(USBx) + 0x400)))
00674
00675 #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
00676     uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
00677     PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
00678   }
00679
00680 /**
00681   * @brief  sets address of the tx/rx buffer.
00682   * @param  USBx: USB peripheral instance register address.
00683   * @param  bEpNum: Endpoint Number.
00684   * @param  wAddr: address to be set (must be word aligned).
00685   * @retval None
00686   */
00687 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
00688 #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
00689
00690 /**
00691   * @brief  Gets address of the tx/rx buffer.
00692   * @param  USBx: USB peripheral instance register address.
00693   * @param  bEpNum: Endpoint Number.
00694   * @retval address of the buffer.
00695   */
00696 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
00697 #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
00698
00699 /**
00700   * @brief  Sets counter of rx buffer with no. of blocks.
00701   * @param  dwReg: Register
00702   * @param  wCount: Counter.
00703   * @param  wNBlocks: no. of Blocks.
00704   * @retval None
00705   */
00706 #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
00707     (wNBlocks) = (wCount) >> 5;\
00708     if(((wCount) & 0x1f) == 0)\
00709     {                                                  \
00710       (wNBlocks)--;\
00711     }                                                  \
00712     *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \
00713   }/* PCD_CALC_BLK32 */
00714
00715 #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
00716     (wNBlocks) = (wCount) >> 1;\
00717     if(((wCount) & 0x1) != 0)\
00718     {                                                  \
00719       (wNBlocks)++;\
00720     }                                                  \
00721     *pdwReg = (uint16_t)((wNBlocks) << 10);\
00722   }/* PCD_CALC_BLK2 */
00723
00724 #define PCD_SET_EP_CNT_RX_REG(dwReg,wCount)  {\
00725     uint16_t wNBlocks;\
00726     if((wCount) > 62)                                \
00727     {                                                \
00728       PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);     \
00729     }                                                \
00730     else                                             \
00731     {                                                \
00732       PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);      \
00733     }                                                \
00734   }/* PCD_SET_EP_CNT_RX_REG */
00735
00736 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
00737     uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
00738     PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
00739   }
00740
00741 /**
00742   * @brief  sets counter for the tx/rx buffer.
00743   * @param  USBx: USB peripheral instance register address.
00744   * @param  bEpNum: Endpoint Number.
00745   * @param  wCount: Counter value.
00746   * @retval None
00747   */
00748 #define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
00749
00750
00751 /**
00752   * @brief  gets counter of the tx buffer.
00753   * @param  USBx: USB peripheral instance register address.
00754   * @param  bEpNum: Endpoint Number.
00755   * @retval Counter value
00756   */
00757 #define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
00758 #define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
00759
00760 /**
00761   * @brief  Sets buffer 0/1 address in a double buffer endpoint.
00762   * @param  USBx: USB peripheral instance register address.
00763   * @param  bEpNum: Endpoint Number.
00764   * @param  wBuf0Addr: buffer 0 address.
00765   * @retval Counter value
00766   */
00767 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
00768 #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
00769
00770 /**
00771   * @brief  Sets addresses in a double buffer endpoint.
00772   * @param  USBx: USB peripheral instance register address.
00773   * @param  bEpNum: Endpoint Number.
00774   * @param  wBuf0Addr: buffer 0 address.
00775   * @param  wBuf1Addr = buffer 1 address.
00776   * @retval None
00777   */
00778 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
00779     PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
00780     PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
00781   } /* PCD_SET_EP_DBUF_ADDR */
00782
00783 /**
00784   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00785   * @param  USBx: USB peripheral instance register address.
00786   * @param  bEpNum: Endpoint Number.
00787   * @retval None
00788   */
00789 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
00790 #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
00791
00792 /**
00793   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00794   * @param  USBx: USB peripheral instance register address.
00795   * @param  bEpNum: Endpoint Number.
00796   * @param  bDir: endpoint dir  EP_DBUF_OUT = OUT
00797   *         EP_DBUF_IN  = IN
00798   * @param  wCount: Counter value
00799   * @retval None
00800   */
00801 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)  { \
00802     if((bDir) == PCD_EP_DBUF_OUT)\
00803       /* OUT endpoint */ \
00804     {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
00805     else if((bDir) == PCD_EP_DBUF_IN)\
00806       /* IN endpoint */ \
00807       *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount);  \
00808   } /* SetEPDblBuf0Count*/
00809
00810 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)  { \
00811     if((bDir) == PCD_EP_DBUF_OUT)\
00812     {/* OUT endpoint */                                       \
00813       PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));           \
00814     }                                                         \
00815     else if((bDir) == PCD_EP_DBUF_IN)\
00816     {/* IN endpoint */                                        \
00817       *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
00818     }                                                         \
00819   } /* SetEPDblBuf1Count */
00820
00821 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
00822     PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
00823     PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
00824   } /* PCD_SET_EP_DBUF_CNT  */
00825
00826 /**
00827   * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
00828   * @param  USBx: USB peripheral instance register address.
00829   * @param  bEpNum: Endpoint Number.
00830   * @retval None
00831   */
00832 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
00833 #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
00834
00835 #endif /* USB */
00836
00837 #if defined(STM32L432xx) || defined(STM32L433xx) || \
00838     defined(STM32L442xx) || defined(STM32L443xx)
00839 /** @defgroup PCD_Instance_definition PCD Instance definition
00840   * @{
00841   */
00842 #define IS_PCD_ALL_INSTANCE                                        IS_USB_ALL_INSTANCE
00843 /**
00844   * @}
00845   */
00846 #endif /* STM32L432xx || STM32L433xx || */
00847        /* STM32L442xx || STM32L443xx    */
00848
00849 /**
00850   * @}
00851   */
00852
00853 /**
00854   * @}
00855   */
00856
00857 /**
00858   * @}
00859   */
00860
00861 #endif /* STM32L475xx || STM32L476xx || */
00862        /* STM32L485xx || STM32L486xx || */
00863        /* STM32L432xx || STM32L433xx || */
00864        /* STM32L442xx || STM32L443xx    */
00865
00866 #ifdef __cplusplus
00867 }
00868 #endif
00869
00870
00871 #endif /* __STM32L4xx_HAL_PCD_H */
00872
00873 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pcd_ex.c Source File

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stm32l4xx_hal_pcd_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pcd_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   PCD Extended HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Extended features functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32l4xx_hal.h"
00044
00045 /** @addtogroup STM32L4xx_HAL_Driver
00046   * @{
00047   */
00048 #ifdef HAL_PCD_MODULE_ENABLED
00049
00050 #if defined(STM32L475xx) || defined(STM32L476xx) || \
00051     defined(STM32L485xx) || defined(STM32L486xx) || \
00052     defined(STM32L432xx) || defined(STM32L433xx) || \
00053     defined(STM32L442xx) || defined(STM32L443xx)
00054
00055
00056 /** @defgroup PCDEx PCDEx
00057   * @brief PCD Extended HAL module driver
00058   * @{
00059   */
00060
00061 /* Private types -------------------------------------------------------------*/
00062 /* Private variables ---------------------------------------------------------*/
00063 /* Private constants ---------------------------------------------------------*/
00064 /* Private macros ------------------------------------------------------------*/
00065 /* Private functions ---------------------------------------------------------*/
00066 /* Exported functions --------------------------------------------------------*/
00067
00068 /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
00069   * @{
00070   */
00071
00072 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00073   * @brief    PCDEx control functions
00074  *
00075 @verbatim
00076  ===============================================================================
00077                  ##### Extended features functions #####
00078  ===============================================================================
00079     [..]  This section provides functions allowing to:
00080       (+) Update FIFO configuration
00081
00082 @endverbatim
00083   * @{
00084   */
00085 #if defined (USB_OTG_FS)
00086 /**
00087   * @brief  Set Tx FIFO
00088   * @param  hpcd: PCD handle
00089   * @param  fifo: The number of Tx fifo
00090   * @param  size: Fifo size
00091   * @retval HAL status
00092   */
00093 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
00094 {
00095   uint8_t index = 0;
00096   uint32_t Tx_Offset = 0;
00097
00098   /*  TXn min size = 16 words. (n  : Transmit FIFO index)
00099       When a TxFIFO is not used, the Configuration should be as follows:
00100           case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00101          --> Txm can use the space allocated for Txn.
00102          case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00103          --> Txn should be configured with the minimum space of 16 words
00104      The FIFO is used optimally when used TxFIFOs are allocated in the top
00105          of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
00106      When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
00107
00108   Tx_Offset = hpcd->Instance->GRXFSIZ;
00109
00110   if(fifo == 0)
00111   {
00112     hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
00113   }
00114   else
00115   {
00116     Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
00117     for (index = 0; index < (fifo - 1); index++)
00118     {
00119       Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16);
00120     }
00121
00122     /* Multiply Tx_Size by 2 to get higher performance */
00123     hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
00124   }
00125
00126   return HAL_OK;
00127 }
00128
00129 /**
00130   * @brief  Set Rx FIFO
00131   * @param  hpcd: PCD handle
00132   * @param  size: Size of Rx fifo
00133   * @retval HAL status
00134   */
00135 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
00136 {
00137   hpcd->Instance->GRXFSIZ = size;
00138
00139   return HAL_OK;
00140 }
00141
00142 /**
00143   * @brief  Activate LPM feature.
00144   * @param  hpcd: PCD handle
00145   * @retval HAL status
00146   */
00147 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
00148 {
00149   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00150
00151   hpcd->lpm_active = ENABLE;
00152   hpcd->LPM_State = LPM_L0;
00153   USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
00154   USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
00155
00156   return HAL_OK;
00157 }
00158
00159 /**
00160   * @brief  Deactivate LPM feature.
00161   * @param  hpcd: PCD handle
00162   * @retval HAL status
00163   */
00164 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
00165 {
00166   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00167
00168   hpcd->lpm_active = DISABLE;
00169   USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
00170   USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
00171
00172   return HAL_OK;
00173 }
00174
00175 /**
00176   * @brief  Handle BatteryCharging Process.
00177   * @param  hpcd: PCD handle
00178   * @retval HAL status
00179   */
00180 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
00181 {
00182   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00183   uint32_t tickstart = HAL_GetTick();
00184
00185   /* Start BCD When device is connected */
00186   if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
00187   {
00188     /* Enable DCD : Data Contact Detect */
00189     USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
00190
00191     /* Wait Detect flag or a timeout is happen*/
00192     while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0)
00193     {
00194       /* Check for the Timeout */
00195       if((HAL_GetTick() - tickstart ) > 1000)
00196       {
00197         HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
00198         return;
00199       }
00200     }
00201
00202     /* Right response got */
00203     HAL_Delay(100);
00204
00205     /* Check Detect flag*/
00206     if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
00207     {
00208       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
00209     }
00210
00211     /*Primary detection: checks if connected to Standard Downstream Port
00212     (without charging capability) */
00213     USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
00214     USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
00215     HAL_Delay(100);
00216
00217     if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
00218     {
00219       /* Case of Standard Downstream Port */
00220       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00221     }
00222     else
00223     {
00224       /* start secondary detection to check connection to Charging Downstream
00225       Port or Dedicated Charging Port */
00226       USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
00227       USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
00228       HAL_Delay(100);
00229
00230       if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
00231       {
00232         /* case Dedicated Charging Port  */
00233         HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00234       }
00235       else
00236       {
00237         /* case Charging Downstream Port  */
00238         HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00239       }
00240     }
00241     /* Battery Charging capability discovery finished */
00242     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00243   }
00244 }
00245
00246 /**
00247   * @brief  Activate BatteryCharging feature.
00248   * @param  hpcd: PCD handle
00249   * @retval HAL status
00250   */
00251 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
00252 {
00253   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00254
00255   hpcd->battery_charging_active = ENABLE;
00256   USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
00257
00258   return HAL_OK;
00259 }
00260
00261 /**
00262   * @brief  Deactivate BatteryCharging feature.
00263   * @param  hpcd: PCD handle
00264   * @retval HAL status
00265   */
00266 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
00267 {
00268   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00269   hpcd->battery_charging_active = DISABLE;
00270   USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
00271   return HAL_OK;
00272 }
00273 #endif /* USB_OTG_FS */
00274
00275 #if defined (USB)
00276 /**
00277   * @brief  Configure PMA for EP
00278   * @param  hpcd : Device instance
00279   * @param  ep_addr: endpoint address
00280   * @param  ep_kind: endpoint Kind
00281   *                  USB_SNG_BUF: Single Buffer used
00282   *                  USB_DBL_BUF: Double Buffer used
00283   * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
00284   *                   this parameter is 16-bit value providing the address
00285   *                   in PMA allocated to endpoint.
00286   *                   In case of double buffer endpoint this parameter
00287   *                   is a 32-bit value providing the endpoint buffer 0 address
00288   *                   in the LSB part of 32-bit value and endpoint buffer 1 address
00289   *                   in the MSB part of 32-bit value.
00290   * @retval HAL status
00291   */
00292
00293 HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
00294                                        uint16_t ep_addr,
00295                                        uint16_t ep_kind,
00296                                        uint32_t pmaadress)
00297
00298 {
00299   PCD_EPTypeDef *ep = NULL;
00300
00301   /* initialize ep structure*/
00302   if ((0x80 & ep_addr) == 0x80)
00303   {
00304     ep = &hpcd->IN_ep[ep_addr & 0x7F];
00305   }
00306   else
00307   {
00308     ep = &hpcd->OUT_ep[ep_addr];
00309   }
00310
00311   /* Here we check if the endpoint is single or double Buffer*/
00312   if (ep_kind == PCD_SNG_BUF)
00313   {
00314     /*Single Buffer*/
00315     ep->doublebuffer = 0;
00316     /*Configure te PMA*/
00317     ep->pmaadress = (uint16_t)pmaadress;
00318   }
00319   else /*USB_DBL_BUF*/
00320   {
00321     /*Double Buffer Endpoint*/
00322     ep->doublebuffer = 1;
00323     /*Configure the PMA*/
00324     ep->pmaaddr0 =  pmaadress & 0xFFFF;
00325     ep->pmaaddr1 =  (pmaadress & 0xFFFF0000) >> 16;
00326   }
00327
00328   return HAL_OK;
00329 }
00330
00331 /**
00332   * @brief  Activate BatteryCharging feature.
00333   * @param  hpcd: PCD handle
00334   * @retval HAL status
00335   */
00336 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
00337 {
00338   USB_TypeDef *USBx = hpcd->Instance;
00339   hpcd->battery_charging_active = ENABLE;
00340
00341   USBx->BCDR |= (USB_BCDR_BCDEN);
00342   /* Enable DCD : Data Contact Detect */
00343   USBx->BCDR |= (USB_BCDR_DCDEN);
00344
00345   return HAL_OK;
00346 }
00347
00348 /**
00349   * @brief  Deactivate BatteryCharging feature.
00350   * @param  hpcd: PCD handle
00351   * @retval HAL status
00352   */
00353 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
00354 {
00355   USB_TypeDef *USBx = hpcd->Instance;
00356   hpcd->battery_charging_active = DISABLE;
00357
00358   USBx->BCDR &= ~(USB_BCDR_BCDEN);
00359   return HAL_OK;
00360 }
00361
00362 /**
00363   * @brief  Handle BatteryCharging Process.
00364   * @param  hpcd: PCD handle
00365   * @retval HAL status
00366   */
00367 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
00368 {
00369   USB_TypeDef *USBx = hpcd->Instance;
00370   uint32_t tickstart = HAL_GetTick();
00371
00372   /* Wait Detect flag or a timeout is happen*/
00373   while ((USBx->BCDR & USB_BCDR_DCDET) == 0)
00374   {
00375     /* Check for the Timeout */
00376     if((HAL_GetTick() - tickstart ) > 1000)
00377     {
00378       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
00379       return;
00380     }
00381   }
00382
00383   HAL_Delay(300);
00384
00385   /* Data Pin Contact ? Check Detect flag */
00386   if (USBx->BCDR & USB_BCDR_DCDET)
00387   {
00388     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
00389   }
00390   /* Primary detection: checks if connected to Standard Downstream Port
00391   (without charging capability) */
00392   USBx->BCDR &= ~(USB_BCDR_DCDEN);
00393   USBx->BCDR |= (USB_BCDR_PDEN);
00394   HAL_Delay(300);
00395
00396   /* If Charger detect ? */
00397   if (USBx->BCDR & USB_BCDR_PDET)
00398   {
00399     /* Start secondary detection to check connection to Charging Downstream
00400     Port or Dedicated Charging Port */
00401     USBx->BCDR &= ~(USB_BCDR_PDEN);
00402     USBx->BCDR |= (USB_BCDR_SDEN);
00403     HAL_Delay(300);
00404
00405     /* If CDP ? */
00406     if (USBx->BCDR & USB_BCDR_SDET)
00407     {
00408       /* Dedicated Downstream Port DCP */
00409       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00410     }
00411     else
00412     {
00413       /* Charging Downstream Port CDP */
00414       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00415
00416       /* Battery Charging capability discovery finished
00417       Start Enumeration*/
00418       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00419     }
00420   }
00421   else /* NO */
00422   {
00423     /* Standard Downstream Port */
00424     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00425   }
00426 }
00427
00428 /**
00429   * @brief  Activate LPM feature.
00430   * @param  hpcd: PCD handle
00431   * @retval HAL status
00432   */
00433 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
00434 {
00435
00436   USB_TypeDef *USBx = hpcd->Instance;
00437   hpcd->lpm_active = ENABLE;
00438   hpcd->LPM_State = LPM_L0;
00439
00440   USBx->LPMCSR |= (USB_LPMCSR_LMPEN);
00441   USBx->LPMCSR |= (USB_LPMCSR_LPMACK);
00442
00443
00444   return HAL_OK;
00445 }
00446
00447 /**
00448   * @brief  Deactivate LPM feature.
00449   * @param  hpcd: PCD handle
00450   * @retval HAL status
00451   */
00452 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
00453 {
00454   USB_TypeDef *USBx = hpcd->Instance;
00455
00456   hpcd->lpm_active = DISABLE;
00457
00458   USBx->LPMCSR &= ~ (USB_LPMCSR_LMPEN);
00459   USBx->LPMCSR &= ~ (USB_LPMCSR_LPMACK);
00460
00461   return HAL_OK;
00462 }
00463
00464 #endif /* USB_FS */
00465
00466 /**
00467   * @brief  Send LPM message to user layer callback.
00468   * @param  hpcd: PCD handle
00469   * @param  msg: LPM message
00470   * @retval HAL status
00471   */
00472 __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
00473 {
00474   /* Prevent unused argument(s) compilation warning */
00475   UNUSED(hpcd);
00476   UNUSED(msg);
00477
00478   /* NOTE : This function should not be modified, when the callback is needed,
00479             the HAL_PCDEx_LPM_Callback could be implemented in the user file
00480    */
00481 }
00482
00483 /**
00484   * @brief  Send BatteryCharging message to user layer callback.
00485   * @param  hpcd: PCD handle
00486   * @param  msg: LPM message
00487   * @retval HAL status
00488   */
00489 __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
00490 {
00491   /* Prevent unused argument(s) compilation warning */
00492   UNUSED(hpcd);
00493   UNUSED(msg);
00494
00495   /* NOTE : This function should not be modified, when the callback is needed,
00496             the HAL_PCDEx_BCD_Callback could be implemented in the user file
00497    */
00498 }
00499
00500 /**
00501   * @}
00502   */
00503
00504 /**
00505   * @}
00506   */
00507 /**
00508   * @}
00509   */
00510
00511 /**
00512   * @}
00513   */
00514
00515 #endif /* STM32L475xx || STM32L476xx || */
00516        /* STM32L485xx || STM32L486xx || */
00517        /* STM32L432xx || STM32L433xx || */
00518        /* STM32L442xx || STM32L443xx    */
00519
00520 #endif /* HAL_PCD_MODULE_ENABLED */
00521
00522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pcd_ex.h Source File

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stm32l4xx_hal_pcd_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pcd_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of PCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_PCD_EX_H
00040 #define __STM32L4xx_HAL_PCD_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32L475xx) || defined(STM32L476xx) || \
00047     defined(STM32L485xx) || defined(STM32L486xx) || \
00048     defined(STM32L432xx) || defined(STM32L433xx) || \
00049     defined(STM32L442xx) || defined(STM32L443xx)
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32l4xx_hal_def.h"
00053
00054 /** @addtogroup STM32L4xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @addtogroup PCDEx
00059   * @{
00060   */
00061 /* Exported types ------------------------------------------------------------*/
00062 typedef enum
00063 {
00064   PCD_LPM_L0_ACTIVE = 0x00, /* on */
00065   PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
00066 }PCD_LPM_MsgTypeDef;
00067
00068 typedef enum
00069 {
00070   PCD_BCD_ERROR                     = 0xFF,
00071   PCD_BCD_CONTACT_DETECTION         = 0xFE,
00072   PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
00073   PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
00074   PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
00075   PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
00076
00077 }PCD_BCD_MsgTypeDef;
00078
00079 /* Exported constants --------------------------------------------------------*/
00080 /* Exported macros -----------------------------------------------------------*/
00081 /* Exported functions --------------------------------------------------------*/
00082 /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
00083   * @{
00084   */
00085 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00086   * @{
00087   */
00088
00089 #if defined(USB_OTG_FS)
00090 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
00091 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
00092 #endif /* USB_OTG_FS */
00093
00094 #if defined (USB)
00095 HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
00096                                        uint16_t ep_addr,
00097                                        uint16_t ep_kind,
00098                                        uint32_t pmaadress);
00099 #endif /* USB_FS */
00100 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
00101 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
00102 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
00103 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
00104 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
00105 void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
00106 void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
00107
00108 /**
00109   * @}
00110   */
00111
00112 /**
00113   * @}
00114   */
00115
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123
00124 #endif /* STM32L475xx || STM32L476xx || */
00125        /* STM32L485xx || STM32L486xx || */
00126        /* STM32L432xx || STM32L433xx || */
00127        /* STM32L442xx || STM32L443xx    */
00128
00129 #ifdef __cplusplus
00130 }
00131 #endif
00132
00133
00134 #endif /* __STM32L4xx_HAL_PCD_EX_H */
00135
00136 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pwr.c Source File

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stm32l4xx_hal_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   PWR HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Power Controller (PWR) peripheral:
00010   *           + Initialization/de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00017   *
00018   * Redistribution and use in source and binary forms, with or without modification,
00019   * are permitted provided that the following conditions are met:
00020   *   1. Redistributions of source code must retain the above copyright notice,
00021   *      this list of conditions and the following disclaimer.
00022   *   2. Redistributions in binary form must reproduce the above copyright notice,
00023   *      this list of conditions and the following disclaimer in the documentation
00024   *      and/or other materials provided with the distribution.
00025   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00026   *      may be used to endorse or promote products derived from this software
00027   *      without specific prior written permission.
00028   *
00029   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00031   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00032   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00033   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00034   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00035   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00036   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00037   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00038   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32l4xx_hal.h"
00045
00046 /** @addtogroup STM32L4xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup PWR PWR
00051   * @brief PWR HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_PWR_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059
00060 /** @defgroup PWR_Private_Defines PWR Private Defines
00061   * @{
00062   */
00063
00064 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00065   * @{
00066   */
00067 #define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD threshold crossing */
00068 #define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD threshold crossing        */
00069 #define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trigger                 */
00070 #define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD trigger                */
00071 /**
00072   * @}
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Private macro -------------------------------------------------------------*/
00080 /* Private variables ---------------------------------------------------------*/
00081 /* Private function prototypes -----------------------------------------------*/
00082 /* Exported functions --------------------------------------------------------*/
00083
00084 /** @defgroup PWR_Exported_Functions PWR Exported Functions
00085   * @{
00086   */
00087
00088 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00089   *  @brief    Initialization and de-initialization functions
00090   *
00091 @verbatim
00092  ===============================================================================
00093               ##### Initialization and de-initialization functions #####
00094  ===============================================================================
00095     [..]
00096
00097 @endverbatim
00098   * @{
00099   */
00100
00101 /**
00102   * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
00103   * @retval None
00104   */
00105 void HAL_PWR_DeInit(void)
00106 {
00107   __HAL_RCC_PWR_FORCE_RESET();
00108   __HAL_RCC_PWR_RELEASE_RESET();
00109 }
00110
00111 /**
00112   * @brief Enable access to the backup domain
00113   *        (RTC registers, RTC backup data registers).
00114   * @note  After reset, the backup domain is protected against
00115   *        possible unwanted write accesses.
00116   * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
00117   *        In order to set or modify the RTC clock, the backup domain access must be
00118   *        disabled.
00119   * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
00120   *        back-up domain.
00121   * @retval None
00122   */
00123 void HAL_PWR_EnableBkUpAccess(void)
00124 {
00125   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00126 }
00127
00128 /**
00129   * @brief Disable access to the backup domain
00130   *        (RTC registers, RTC backup data registers).
00131   * @retval None
00132   */
00133 void HAL_PWR_DisableBkUpAccess(void)
00134 {
00135   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00136 }
00137
00138
00139
00140
00141 /**
00142   * @}
00143   */
00144
00145
00146
00147 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
00148   *  @brief Low Power modes configuration functions
00149   *
00150 @verbatim
00151
00152  ===============================================================================
00153                  ##### Peripheral Control functions #####
00154  ===============================================================================
00155
00156      [..]
00157      *** PVD configuration ***
00158     =========================
00159     [..]
00160       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00161           threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
00162
00163       (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
00164           than the PVD threshold. This event is internally connected to the EXTI
00165           line16 and can generate an interrupt if enabled. This is done through
00166           __HAL_PVD_EXTI_ENABLE_IT() macro.
00167       (+) The PVD is stopped in Standby mode.
00168
00169
00170     *** WakeUp pin configuration ***
00171     ================================
00172     [..]
00173       (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
00174           The polarity of these pins can be set to configure event detection on high
00175           level (rising edge) or low level (falling edge).
00176
00177
00178
00179     *** Low Power modes configuration ***
00180     =====================================
00181     [..]
00182       The devices feature 8 low-power modes:
00183       (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
00184       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
00185       (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
00186       (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
00187       (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
00188       (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
00189       (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
00190       (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
00191       (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
00192
00193
00194    *** Low-power run mode ***
00195    ==========================
00196     [..]
00197       (+) Entry: (from main run mode)
00198         (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
00199
00200       (+) Exit:
00201         (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
00202              then can the system clock frequency be increased above 2 MHz.
00203
00204
00205    *** Sleep mode / Low-power sleep mode ***
00206    =========================================
00207     [..]
00208       (+) Entry:
00209           The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
00210           in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
00211           (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
00212           (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
00213           In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
00214           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00215           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00216
00217       (+) WFI Exit:
00218         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
00219              controller (NVIC) or any wake-up event.
00220
00221       (+) WFE Exit:
00222         (++) Any wake-up event such as an EXTI line configured in event mode.
00223
00224          [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
00225              the MCU is in Low-power Run mode.
00226
00227    *** Stop 0, Stop 1 and Stop 2 modes ***
00228    ===============================
00229     [..]
00230       (+) Entry:
00231           The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
00232           (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
00233           (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
00234       (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
00235           (++) PWR_MAINREGULATOR_ON
00236           (++) PWR_LOWPOWERREGULATOR_ON
00237       (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
00238           (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
00239           (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
00240
00241       (+) WFI Exit:
00242           (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
00243           (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
00244                when programmed in wakeup mode.
00245       (+) WFE Exit:
00246           (++) Any EXTI Line (Internal or External) configured in Event mode.
00247
00248        [..]
00249           When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
00250           depending on the LPR bit setting.
00251           When exiting Stop 2 mode, the MCU is in Run mode.
00252
00253    *** Standby mode ***
00254    ====================
00255      [..]
00256       The Standby mode offers two options:
00257       (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
00258         SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
00259         and Standby circuitry.
00260       (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
00261         SRAM and register contents are lost except for the RTC registers, RTC backup registers
00262         and Standby circuitry.
00263
00264       (++) Entry:
00265           (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
00266                 SRAM1 and register contents are lost except for registers in the Backup domain and
00267                 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
00268                 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
00269                 to set RRS bit.
00270
00271       (++) Exit:
00272           (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
00273                 external reset in NRST pin, IWDG reset.
00274
00275       [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.
00276
00277
00278     *** Shutdown mode ***
00279    ======================
00280      [..]
00281       In Shutdown mode,
00282         voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
00283         SRAM and registers contents are lost except for backup domain registers.
00284
00285       (+) Entry:
00286           The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
00287
00288       (+) Exit:
00289           (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
00290                external reset in NRST pin.
00291
00292          [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
00293
00294
00295    *** Auto-wakeup (AWU) from low-power mode ***
00296    =============================================
00297     [..]
00298       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
00299       Wakeup event, a tamper event or a time-stamp event, without depending on
00300       an external interrupt (Auto-wakeup mode).
00301
00302       (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
00303
00304
00305         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
00306              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
00307
00308         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
00309              is necessary to configure the RTC to detect the tamper or time stamp event using the
00310              HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
00311
00312         (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
00313               configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00314
00315 @endverbatim
00316   * @{
00317   */
00318
00319
00320
00321 /**
00322   * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
00323   * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
00324   *        configuration information.
00325   * @note Refer to the electrical characteristics of your device datasheet for
00326   *         more details about the voltage thresholds corresponding to each
00327   *         detection level.
00328   * @retval None
00329   */
00330 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00331 {
00332   /* Check the parameters */
00333   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00334   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00335
00336   /* Set PLS bits according to PVDLevel value */
00337   MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
00338
00339   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00340   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
00341   __HAL_PWR_PVD_EXTI_DISABLE_IT();
00342   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00343   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
00344
00345   /* Configure interrupt mode */
00346   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00347   {
00348     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00349   }
00350
00351   /* Configure event mode */
00352   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00353   {
00354     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
00355   }
00356
00357   /* Configure the edge */
00358   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00359   {
00360     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00361   }
00362
00363   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00364   {
00365     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00366   }
00367
00368   return HAL_OK;
00369 }
00370
00371
00372 /**
00373   * @brief Enable the Power Voltage Detector (PVD).
00374   * @retval None
00375   */
00376 void HAL_PWR_EnablePVD(void)
00377 {
00378   SET_BIT(PWR->CR2, PWR_CR2_PVDE);
00379 }
00380
00381 /**
00382   * @brief Disable the Power Voltage Detector (PVD).
00383   * @retval None
00384   */
00385 void HAL_PWR_DisablePVD(void)
00386 {
00387   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
00388 }
00389
00390
00391
00392
00393 /**
00394   * @brief Enable the WakeUp PINx functionality.
00395   * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
00396   *         This parameter can be one of the following legacy values which set the default polarity
00397   *         i.e. detection on high level (rising edge):
00398   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
00399   *
00400   *         or one of the following value where the user can explicitly specify the enabled pin and
00401   *         the chosen polarity:
00402   *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
00403   *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
00404   *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
00405   *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
00406   *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
00407   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
00408   * @retval None
00409   */
00410 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
00411 {
00412   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
00413
00414   /* Specifies the Wake-Up pin polarity for the event detection
00415     (rising or falling edge) */
00416   MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
00417
00418   /* Enable wake-up pin */
00419   SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
00420
00421
00422 }
00423
00424 /**
00425   * @brief Disable the WakeUp PINx functionality.
00426   * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
00427   *         This parameter can be one of the following values:
00428   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
00429   * @retval None
00430   */
00431 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00432 {
00433   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00434
00435   CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
00436 }
00437
00438
00439 /**
00440   * @brief Enter Sleep or Low-power Sleep mode.
00441   * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
00442   * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
00443   *          This parameter can be one of the following values:
00444   *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
00445   *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
00446   * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
00447   *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
00448   *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
00449   *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
00450   *        Additionally, the clock frequency must be reduced below 2 MHz.
00451   *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
00452   *        be done before calling HAL_PWR_EnterSLEEPMode() API.
00453   * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
00454   *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
00455   * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
00456   *           This parameter can be one of the following values:
00457   *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
00458   *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
00459   * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as
00460   *        the interrupt wake up source.
00461   * @retval None
00462   */
00463 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00464 {
00465   /* Check the parameters */
00466   assert_param(IS_PWR_REGULATOR(Regulator));
00467   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00468
00469   /* Set Regulator parameter */
00470   if (Regulator == PWR_MAINREGULATOR_ON)
00471   {
00472     /* If in low-power run mode at this point, exit it */
00473     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
00474     {
00475       HAL_PWREx_DisableLowPowerRunMode();
00476     }
00477     /* Regulator now in main mode. */
00478   }
00479   else
00480   {
00481     /* If in run mode, first move to low-power run mode.
00482        The system clock frequency must be below 2 MHz at this point. */
00483     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
00484     {
00485       HAL_PWREx_EnableLowPowerRunMode();
00486     }
00487   }
00488
00489   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00490   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00491
00492   /* Select SLEEP mode entry -------------------------------------------------*/
00493   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
00494   {
00495     /* Request Wait For Interrupt */
00496     __WFI();
00497   }
00498   else
00499   {
00500     /* Request Wait For Event */
00501     __SEV();
00502     __WFE();
00503     __WFE();
00504   }
00505
00506 }
00507
00508
00509 /**
00510   * @brief Enter Stop mode
00511   * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
00512   *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.
00513   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
00514   * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,
00515   *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
00516   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
00517   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
00518   *        only to the peripheral requesting it.
00519   *        SRAM1, SRAM2 and register contents are preserved.
00520   *        The BOR is available.
00521   *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
00522   * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
00523   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
00524   *         is set; the MSI oscillator is selected if STOPWUCK is cleared.
00525   * @note  When the voltage regulator operates in low power mode (Stop 1), an additional
00526   *         startup delay is incurred when waking up.
00527   *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
00528   *         is higher although the startup time is reduced.
00529   * @param Regulator: Specifies the regulator state in Stop mode.
00530   *          This parameter can be one of the following values:
00531   *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
00532   *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON)
00533   * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
00534   *          This parameter can be one of the following values:
00535   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.
00536   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.
00537   * @retval None
00538   */
00539 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00540 {
00541   /* Check the parameters */
00542   assert_param(IS_PWR_REGULATOR(Regulator));
00543
00544   if(Regulator == PWR_LOWPOWERREGULATOR_ON)
00545   {
00546     HAL_PWREx_EnterSTOP1Mode(STOPEntry);
00547   }
00548   else
00549   {
00550     HAL_PWREx_EnterSTOP0Mode(STOPEntry);
00551   }
00552 }
00553
00554 /**
00555   * @brief Enter Standby mode.
00556   * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
00557   *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
00558   *        in which case the regulator is in low-power mode.
00559   *        SRAM1 and register contents are lost except for registers in the Backup domain and
00560   *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
00561   *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
00562   *        to set RRS bit.
00563   *        The BOR is available.
00564   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
00565   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
00566   *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
00567   *        same.
00568   *        These states are effective in Standby mode only if APC bit is set through
00569   *        HAL_PWREx_EnablePullUpPullDownConfig() API.
00570   * @retval None
00571   */
00572 void HAL_PWR_EnterSTANDBYMode(void)
00573 {
00574   /* Set Stand-by mode */
00575   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
00576
00577   /* Set SLEEPDEEP bit of Cortex System Control Register */
00578   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00579
00580 /* This option is used to ensure that store operations are completed */
00581 #if defined ( __CC_ARM)
00582   __force_stores();
00583 #endif
00584   /* Request Wait For Interrupt */
00585   __WFI();
00586 }
00587
00588
00589
00590 /**
00591   * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
00592   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00593   *       re-enters SLEEP mode when an interruption handling is over.
00594   *       Setting this bit is useful when the processor is expected to run only on
00595   *       interruptions handling.
00596   * @retval None
00597   */
00598 void HAL_PWR_EnableSleepOnExit(void)
00599 {
00600   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00601   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00602 }
00603
00604
00605 /**
00606   * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
00607   * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00608   *       re-enters SLEEP mode when an interruption handling is over.
00609   * @retval None
00610   */
00611 void HAL_PWR_DisableSleepOnExit(void)
00612 {
00613   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00614   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00615 }
00616
00617
00618
00619 /**
00620   * @brief Enable CORTEX M4 SEVONPEND bit.
00621   * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
00622   *       WFE to wake up when an interrupt moves from inactive to pended.
00623   * @retval None
00624   */
00625 void HAL_PWR_EnableSEVOnPend(void)
00626 {
00627   /* Set SEVONPEND bit of Cortex System Control Register */
00628   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00629 }
00630
00631
00632 /**
00633   * @brief Disable CORTEX M4 SEVONPEND bit.
00634   * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
00635   *       WFE to wake up when an interrupt moves from inactive to pended.
00636   * @retval None
00637   */
00638 void HAL_PWR_DisableSEVOnPend(void)
00639 {
00640   /* Clear SEVONPEND bit of Cortex System Control Register */
00641   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00642 }
00643
00644
00645
00646
00647
00648 /**
00649   * @brief PWR PVD interrupt callback
00650   * @retval None
00651   */
00652 __weak void HAL_PWR_PVDCallback(void)
00653 {
00654   /* NOTE : This function should not be modified; when the callback is needed,
00655             the HAL_PWR_PVDCallback can be implemented in the user file
00656    */
00657 }
00658
00659 /**
00660   * @}
00661   */
00662
00663 /**
00664   * @}
00665   */
00666
00667 #endif /* HAL_PWR_MODULE_ENABLED */
00668 /**
00669   * @}
00670   */
00671
00672 /**
00673   * @}
00674   */
00675
00676 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pwr.h Source File

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stm32l4xx_hal_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pwr.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of PWR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_PWR_H
00040 #define __STM32L4xx_HAL_PWR_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PWR
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup PWR_Exported_Types PWR Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  PWR PVD configuration structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
00069                             This parameter can be a value of @ref PWR_PVD_detection_level. */
00070
00071   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00072                            This parameter can be a value of @ref PWR_PVD_Mode. */
00073 }PWR_PVDTypeDef;
00074
00075
00076 /**
00077   * @}
00078   */
00079
00080 /* Exported constants --------------------------------------------------------*/
00081
00082 /** @defgroup PWR_Exported_Constants PWR Exported Constants
00083   * @{
00084   */
00085
00086
00087 /** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
00088   * @{
00089   */
00090 #define PWR_PVDLEVEL_0                  PWR_CR2_PLS_LEV0  /*!< PVD threshold around 2.0 V */
00091 #define PWR_PVDLEVEL_1                  PWR_CR2_PLS_LEV1  /*!< PVD threshold around 2.2 V */
00092 #define PWR_PVDLEVEL_2                  PWR_CR2_PLS_LEV2  /*!< PVD threshold around 2.4 V */
00093 #define PWR_PVDLEVEL_3                  PWR_CR2_PLS_LEV3  /*!< PVD threshold around 2.5 V */
00094 #define PWR_PVDLEVEL_4                  PWR_CR2_PLS_LEV4  /*!< PVD threshold around 2.6 V */
00095 #define PWR_PVDLEVEL_5                  PWR_CR2_PLS_LEV5  /*!< PVD threshold around 2.8 V */
00096 #define PWR_PVDLEVEL_6                  PWR_CR2_PLS_LEV6  /*!< PVD threshold around 2.9 V */
00097 #define PWR_PVDLEVEL_7                  PWR_CR2_PLS_LEV7  /*!< External input analog voltage (compared internally to VREFINT) */
00098 /**
00099   * @}
00100   */
00101
00102 /** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode
00103   * @{
00104   */
00105 #define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< Basic mode is used */
00106 #define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
00107 #define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
00108 #define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00109 #define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
00110 #define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
00111 #define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
00112 /**
00113   * @}
00114   */
00115
00116
00117
00118
00119 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
00120   * @{
00121   */
00122 #define PWR_MAINREGULATOR_ON            ((uint32_t)0x00000000) /*!< Regulator in main mode      */
00123 #define PWR_LOWPOWERREGULATOR_ON        PWR_CR1_LPR            /*!< Regulator in low-power mode */
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry
00129   * @{
00130   */
00131 #define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)        /*!< Wait For Interruption instruction to enter Sleep mode */
00132 #define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)        /*!< Wait For Event instruction to enter Sleep mode        */
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry
00138   * @{
00139   */
00140 #define PWR_STOPENTRY_WFI               ((uint8_t)0x01)       /*!< Wait For Interruption instruction to enter Stop mode */
00141 #define PWR_STOPENTRY_WFE               ((uint8_t)0x02)       /*!< Wait For Event instruction to enter Stop mode        */
00142 /**
00143   * @}
00144   */
00145
00146
00147 /** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
00148   * @{
00149   */
00150 #define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)   /*!< External interrupt line 16 Connected to the PVD EXTI Line */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line
00156   * @{
00157   */
00158 #define PWR_EVENT_LINE_PVD  ((uint32_t)0x00010000)  /*!< Event line 16 Connected to the PVD Event Line */
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /* Exported macros -----------------------------------------------------------*/
00168 /** @defgroup PWR_Exported_Macros  PWR Exported Macros
00169   * @{
00170   */
00171
00172 /** @brief  Check whether or not a specific PWR flag is set.
00173   * @param  __FLAG__: specifies the flag to check.
00174   *           This parameter can be one of the following values:
00175   *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
00176   *                  was received from the WKUP pin 1.
00177   *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
00178   *                  was received from the WKUP pin 2.
00179   *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
00180   *                  was received from the WKUP pin 3.
00181   *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
00182   *                  was received from the WKUP pin 4.
00183   *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
00184   *                  was received from the WKUP pin 5.
00185   *            @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
00186   *                  entered StandBy mode.
00187   *            @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
00188   *                 the internal wakeup line.
00189   *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
00190   *                 low-power regulator is ready.
00191   *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
00192   *                 regulator is ready in main mode or is in low-power mode.
00193   *            @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
00194   *                 in the selected voltage range or is still changing to the required voltage level.
00195   *            @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
00196   *                  below or above the selected PVD threshold.
00197   *            @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
00198   *                  is below or above PVM1 threshold (applicable when USB feature is supported).
00199   @if STM32L486xx
00200   *            @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
00201   *                  is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
00202   @endif
00203   *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
00204   *                  is below or above PVM3 threshold.
00205   *            @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
00206   *                  is below or above PVM4 threshold.
00207   *
00208   * @retval The new state of __FLAG__ (TRUE or FALSE).
00209   */
00210 #define __HAL_PWR_GET_FLAG(__FLAG__)  ( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\
00211                                       (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
00212                                       (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
00213
00214 /** @brief  Clear a specific PWR flag.
00215   * @param  __FLAG__: specifies the flag to clear.
00216   *          This parameter can be one of the following values:
00217   *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
00218   *                  was received from the WKUP pin 1.
00219   *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
00220   *                  was received from the WKUP pin 2.
00221   *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
00222   *                  was received from the WKUP pin 3.
00223   *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
00224   *                  was received from the WKUP pin 4.
00225   *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
00226   *                  was received from the WKUP pin 5.
00227   *            @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
00228   *            @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
00229   *                  entered Standby mode.
00230   * @retval None
00231   */
00232 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
00233                                          (PWR->SCR  = (__FLAG__)) :\
00234                                          (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
00235 /**
00236   * @brief Enable the PVD Extended Interrupt Line.
00237   * @retval None
00238   */
00239 #define __HAL_PWR_PVD_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
00240
00241 /**
00242   * @brief Disable the PVD Extended Interrupt Line.
00243   * @retval None
00244   */
00245 #define __HAL_PWR_PVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
00246
00247 /**
00248   * @brief Enable the PVD Event Line.
00249   * @retval None
00250   */
00251 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
00252
00253 /**
00254   * @brief Disable the PVD Event Line.
00255   * @retval None
00256   */
00257 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
00258
00259 /**
00260   * @brief Enable the PVD Extended Interrupt Rising Trigger.
00261   * @retval None
00262   */
00263 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
00264
00265 /**
00266   * @brief Disable the PVD Extended Interrupt Rising Trigger.
00267   * @retval None
00268   */
00269 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
00270
00271 /**
00272   * @brief Enable the PVD Extended Interrupt Falling Trigger.
00273   * @retval None
00274   */
00275 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
00276
00277
00278 /**
00279   * @brief Disable the PVD Extended Interrupt Falling Trigger.
00280   * @retval None
00281   */
00282 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
00283
00284
00285 /**
00286   * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
00287   * @retval None
00288   */
00289 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00290   do {                                                   \
00291     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
00292     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
00293   } while(0)
00294
00295 /**
00296   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
00297   * @retval None
00298   */
00299 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00300   do {                                                    \
00301     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
00302     __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
00303   } while(0)
00304
00305 /**
00306   * @brief  Generate a Software interrupt on selected EXTI line.
00307   * @retval None
00308   */
00309 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
00310
00311 /**
00312   * @brief Check whether or not the PVD EXTI interrupt flag is set.
00313   * @retval EXTI PVD Line Status.
00314   */
00315 #define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR1 & PWR_EXTI_LINE_PVD)
00316
00317 /**
00318   * @brief Clear the PVD EXTI interrupt flag.
00319   * @retval None
00320   */
00321 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
00322
00323 /**
00324   * @}
00325   */
00326
00327
00328 /* Private macros --------------------------------------------------------*/
00329 /** @addtogroup  PWR_Private_Macros   PWR Private Macros
00330   * @{
00331   */
00332
00333 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
00334                                  ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
00335                                  ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
00336                                  ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
00337
00338 #define IS_PWR_PVD_MODE(MODE)  (((MODE) == PWR_PVD_MODE_NORMAL)              ||\
00339                                 ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
00340                                 ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
00341                                 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\
00342                                 ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\
00343                                 ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\
00344                                 ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
00345
00346 #define IS_PWR_REGULATOR(REGULATOR)      (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
00347                                           ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
00348
00349 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
00350
00351 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
00352
00353 /**
00354   * @}
00355   */
00356
00357 /* Include PWR HAL Extended module */
00358 #include "stm32l4xx_hal_pwr_ex.h"
00359
00360 /* Exported functions --------------------------------------------------------*/
00361
00362 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
00363   * @{
00364   */
00365
00366 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00367   * @{
00368   */
00369
00370 /* Initialization and de-initialization functions *******************************/
00371 void HAL_PWR_DeInit(void);
00372 void HAL_PWR_EnableBkUpAccess(void);
00373 void HAL_PWR_DisableBkUpAccess(void);
00374
00375 /**
00376   * @}
00377   */
00378
00379 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
00380   * @{
00381   */
00382
00383 /* Peripheral Control functions  ************************************************/
00384 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
00385 void HAL_PWR_EnablePVD(void);
00386 void HAL_PWR_DisablePVD(void);
00387
00388
00389 /* WakeUp pins configuration functions ****************************************/
00390 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
00391 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
00392
00393 /* Low Power modes configuration functions ************************************/
00394 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
00395 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00396 void HAL_PWR_EnterSTANDBYMode(void);
00397
00398 void HAL_PWR_EnableSleepOnExit(void);
00399 void HAL_PWR_DisableSleepOnExit(void);
00400 void HAL_PWR_EnableSEVOnPend(void);
00401 void HAL_PWR_DisableSEVOnPend(void);
00402
00403 void HAL_PWR_PVDCallback(void);
00404
00405
00406 /**
00407   * @}
00408   */
00409
00410 /**
00411   * @}
00412   */
00413
00414 /**
00415   * @}
00416   */
00417
00418 /**
00419   * @}
00420   */
00421
00422 #ifdef __cplusplus
00423 }
00424 #endif
00425
00426
00427 #endif /* __STM32L4xx_HAL_PWR_H */
00428
00429 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pwr_ex.c Source File

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stm32l4xx_hal_pwr_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pwr_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Extended PWR HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Power Controller (PWR) peripheral:
00010   *           + Extended Initialization and de-initialization functions
00011   *           + Extended Peripheral Control functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00017   *
00018   * Redistribution and use in source and binary forms, with or without modification,
00019   * are permitted provided that the following conditions are met:
00020   *   1. Redistributions of source code must retain the above copyright notice,
00021   *      this list of conditions and the following disclaimer.
00022   *   2. Redistributions in binary form must reproduce the above copyright notice,
00023   *      this list of conditions and the following disclaimer in the documentation
00024   *      and/or other materials provided with the distribution.
00025   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00026   *      may be used to endorse or promote products derived from this software
00027   *      without specific prior written permission.
00028   *
00029   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00031   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00032   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00033   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00034   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00035   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00036   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00037   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00038   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32l4xx_hal.h"
00045
00046 /** @addtogroup STM32L4xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup PWREx PWREx
00051   * @brief PWR Extended HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_PWR_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059
00060 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00061 #define PWR_PORTH_AVAILABLE_PINS   (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1)
00062 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00063 #define PWR_PORTH_AVAILABLE_PINS   (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1|PWR_GPIO_BIT_3)
00064 #endif
00065
00066 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
00067   * @{
00068   */
00069
00070 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
00071   * @{
00072   */
00073 #define PVM_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVM threshold crossing */
00074 #define PVM_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVM threshold crossing        */
00075 #define PVM_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVM trigger                 */
00076 #define PVM_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVM trigger                */
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
00082   * @{
00083   */
00084 #define PWR_FLAG_SETTING_DELAY_US                      50   /*!< Time out value for REGLPF and VOSF flags setting */
00085 /**
00086   * @}
00087   */
00088
00089
00090
00091 /**
00092   * @}
00093   */
00094
00095
00096
00097 /* Private macro -------------------------------------------------------------*/
00098 /* Private variables ---------------------------------------------------------*/
00099 /* Private function prototypes -----------------------------------------------*/
00100 /* Exported functions --------------------------------------------------------*/
00101
00102 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
00103   * @{
00104   */
00105
00106 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
00107   *  @brief   Extended Peripheral Control functions
00108   *
00109 @verbatim
00110  ===============================================================================
00111               ##### Extended Peripheral Initialization and de-initialization functions #####
00112  ===============================================================================
00113     [..]
00114
00115 @endverbatim
00116   * @{
00117   */
00118
00119
00120 /**
00121   * @brief Return Voltage Scaling Range.
00122   * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
00123   */
00124 uint32_t HAL_PWREx_GetVoltageRange(void)
00125 {
00126   return  (PWR->CR1 & PWR_CR1_VOS);
00127 }
00128
00129
00130
00131 /**
00132   * @brief Configure the main internal regulator output voltage.
00133   * @param  VoltageScaling: specifies the regulator output voltage to achieve
00134   *         a tradeoff between performance and power consumption.
00135   *          This parameter can be one of the following values:
00136   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
00137   *                                                typical output voltage at 1.2 V,
00138   *                                                system frequency up to 80 MHz.
00139   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
00140   *                                                typical output voltage at 1.0 V,
00141   *                                                system frequency up to 26 MHz.
00142   * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
00143   *        a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
00144   *        When moving from Range 2 to Range 1, the system frequency can be increased to
00145   *        a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
00146   * @note  When moving from Range 2 to Range 1, the API waits for VOSF flag to be
00147   *        cleared before returning the status. If the flag is not cleared within
00148   *        50 microseconds, HAL_TIMEOUT status is reported.
00149   * @retval HAL Status
00150   */
00151 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
00152 {
00153   uint32_t wait_loop_index = 0;
00154
00155   assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
00156
00157   /* If Set Range 1 */
00158   if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
00159   {
00160     if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
00161     {
00162       /* Set Range 1 */
00163       MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
00164
00165       /* Wait until VOSF is cleared */
00166       wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
00167       while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)))
00168       {
00169         wait_loop_index--;
00170       }
00171       if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
00172       {
00173         return HAL_TIMEOUT;
00174       }
00175     }
00176   }
00177   else
00178   {
00179     if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
00180     {
00181       /* Set Range 2 */
00182       MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
00183       /* No need to wait for VOSF to be cleared for this transition */
00184     }
00185   }
00186
00187   return HAL_OK;
00188 }
00189
00190
00191 /**
00192   * @brief Enable battery charging.
00193   *        When VDD is present, charge the external battery on VBAT thru an internal resistor.
00194   * @param  ResistorSelection: specifies the resistor impedance.
00195   *          This parameter can be one of the following values:
00196   *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5     5 kOhms resistor
00197   *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
00198   * @retval None
00199   */
00200 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
00201 {
00202   assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
00203
00204   /* Specify resistor selection */
00205   MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
00206
00207   /* Enable battery charging */
00208   SET_BIT(PWR->CR4, PWR_CR4_VBE);
00209 }
00210
00211
00212 /**
00213   * @brief Disable battery charging.
00214   * @retval None
00215   */
00216 void HAL_PWREx_DisableBatteryCharging(void)
00217 {
00218   CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
00219 }
00220
00221
00222 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00223 /**
00224   * @brief Enable VDDUSB supply.
00225   * @note  Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
00226   * @retval None
00227   */
00228 void HAL_PWREx_EnableVddUSB(void)
00229 {
00230   SET_BIT(PWR->CR2, PWR_CR2_USV);
00231 }
00232
00233
00234 /**
00235   * @brief Disable VDDUSB supply.
00236   * @retval None
00237   */
00238 void HAL_PWREx_DisableVddUSB(void)
00239 {
00240   CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
00241 }
00242 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00243
00244 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00245 /**
00246   * @brief Enable VDDIO2 supply.
00247   * @note  Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
00248   * @retval None
00249   */
00250 void HAL_PWREx_EnableVddIO2(void)
00251 {
00252   SET_BIT(PWR->CR2, PWR_CR2_IOSV);
00253 }
00254
00255
00256 /**
00257   * @brief Disable VDDIO2 supply.
00258   * @retval None
00259   */
00260 void HAL_PWREx_DisableVddIO2(void)
00261 {
00262   CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
00263 }
00264 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00265
00266
00267 /**
00268   * @brief Enable Internal Wake-up Line.
00269   * @retval None
00270   */
00271 void HAL_PWREx_EnableInternalWakeUpLine(void)
00272 {
00273   SET_BIT(PWR->CR3, PWR_CR3_EIWF);
00274 }
00275
00276
00277 /**
00278   * @brief Disable Internal Wake-up Line.
00279   * @retval None
00280   */
00281 void HAL_PWREx_DisableInternalWakeUpLine(void)
00282 {
00283   CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
00284 }
00285
00286
00287
00288 /**
00289   * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
00290   * @note  Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
00291   *        pull-up state in Standby and Shutdown modes.
00292   * @note  This state is effective in Standby and Shutdown modes only if APC bit
00293   *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
00294   * @note  The configuration is lost when exiting the Shutdown mode due to the
00295   *        power-on reset, maintained when exiting the Standby mode.
00296   * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
00297   *        PDy bit of PWR_PDCRx register is cleared unless it is reserved.
00298   * @note  Even if a PUy bit to set is reserved, the other PUy bits entered as input
00299   *        parameter at the same time are set.
00300   * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
00301   *         to select the GPIO peripheral.
00302   * @param  GPIONumber: Specify the I/O pins numbers.
00303   *         This parameter can be one of the following values:
00304   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
00305   *         I/O pins are available) or the logical OR of several of them to set
00306   *         several bits for a given port in a single API call.
00307   * @retval HAL Status
00308   */
00309 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00310 {
00311   assert_param(IS_PWR_GPIO(GPIO));
00312   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00313
00314   switch (GPIO)
00315   {
00316     case PWR_GPIO_A:
00317        SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
00318        CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
00319        break;
00320     case PWR_GPIO_B:
00321        SET_BIT(PWR->PUCRB, GPIONumber);
00322        CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
00323        break;
00324     case PWR_GPIO_C:
00325        SET_BIT(PWR->PUCRC, GPIONumber);
00326        CLEAR_BIT(PWR->PDCRC, GPIONumber);
00327        break;
00328 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00329     case PWR_GPIO_D:
00330        SET_BIT(PWR->PUCRD, GPIONumber);
00331        CLEAR_BIT(PWR->PDCRD, GPIONumber);
00332        break;
00333     case PWR_GPIO_E:
00334        SET_BIT(PWR->PUCRE, GPIONumber);
00335        CLEAR_BIT(PWR->PDCRE, GPIONumber);
00336        break;
00337 #endif
00338 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00339     case PWR_GPIO_F:
00340        SET_BIT(PWR->PUCRF, GPIONumber);
00341        CLEAR_BIT(PWR->PDCRF, GPIONumber);
00342        break;
00343     case PWR_GPIO_G:
00344        SET_BIT(PWR->PUCRG, GPIONumber);
00345        CLEAR_BIT(PWR->PDCRG, GPIONumber);
00346        break;
00347 #endif
00348     case PWR_GPIO_H:
00349        SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00350        CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00351        break;
00352     default:
00353         return HAL_ERROR;
00354   }
00355
00356   return HAL_OK;
00357 }
00358
00359
00360 /**
00361   * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
00362   * @note  Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
00363   *        in pull-up state in Standby and Shutdown modes.
00364   * @note  Even if a PUy bit to reset is reserved, the other PUy bits entered as input
00365   *        parameter at the same time are reset.
00366   * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
00367   *         to select the GPIO peripheral.
00368   * @param  GPIONumber: Specify the I/O pins numbers.
00369   *         This parameter can be one of the following values:
00370   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
00371   *         I/O pins are available) or the logical OR of several of them to reset
00372   *         several bits for a given port in a single API call.
00373   * @retval HAL Status
00374   */
00375 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00376 {
00377   assert_param(IS_PWR_GPIO(GPIO));
00378   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00379
00380   switch (GPIO)
00381   {
00382     case PWR_GPIO_A:
00383        CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
00384        break;
00385     case PWR_GPIO_B:
00386        CLEAR_BIT(PWR->PUCRB, GPIONumber);
00387        break;
00388     case PWR_GPIO_C:
00389        CLEAR_BIT(PWR->PUCRC, GPIONumber);
00390        break;
00391 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00392     case PWR_GPIO_D:
00393        CLEAR_BIT(PWR->PUCRD, GPIONumber);
00394        break;
00395     case PWR_GPIO_E:
00396        CLEAR_BIT(PWR->PUCRE, GPIONumber);
00397        break;
00398 #endif
00399 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00400     case PWR_GPIO_F:
00401        CLEAR_BIT(PWR->PUCRF, GPIONumber);
00402        break;
00403     case PWR_GPIO_G:
00404        CLEAR_BIT(PWR->PUCRG, GPIONumber);
00405        break;
00406 #endif
00407     case PWR_GPIO_H:
00408        CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00409        break;
00410     default:
00411         return HAL_ERROR;
00412   }
00413
00414   return HAL_OK;
00415 }
00416
00417
00418
00419 /**
00420   * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
00421   * @note  Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
00422   *        pull-down state in Standby and Shutdown modes.
00423   * @note  This state is effective in Standby and Shutdown modes only if APC bit
00424   *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
00425   * @note  The configuration is lost when exiting the Shutdown mode due to the
00426   *        power-on reset, maintained when exiting the Standby mode.
00427   * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
00428   *        PUy bit of PWR_PUCRx register is cleared unless it is reserved.
00429   * @note  Even if a PDy bit to set is reserved, the other PDy bits entered as input
00430   *        parameter at the same time are set.
00431   * @param  GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
00432   *         to select the GPIO peripheral.
00433   * @param  GPIONumber: Specify the I/O pins numbers.
00434   *         This parameter can be one of the following values:
00435   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
00436   *         I/O pins are available) or the logical OR of several of them to set
00437   *         several bits for a given port in a single API call.
00438   * @retval HAL Status
00439   */
00440 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
00441 {
00442   assert_param(IS_PWR_GPIO(GPIO));
00443   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00444
00445   switch (GPIO)
00446   {
00447     case PWR_GPIO_A:
00448        SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
00449        CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
00450        break;
00451     case PWR_GPIO_B:
00452        SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
00453        CLEAR_BIT(PWR->PUCRB, GPIONumber);
00454        break;
00455     case PWR_GPIO_C:
00456        SET_BIT(PWR->PDCRC, GPIONumber);
00457        CLEAR_BIT(PWR->PUCRC, GPIONumber);
00458        break;
00459 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00460     case PWR_GPIO_D:
00461        SET_BIT(PWR->PDCRD, GPIONumber);
00462        CLEAR_BIT(PWR->PUCRD, GPIONumber);
00463        break;
00464     case PWR_GPIO_E:
00465        SET_BIT(PWR->PDCRE, GPIONumber);
00466        CLEAR_BIT(PWR->PUCRE, GPIONumber);
00467        break;
00468 #endif
00469 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00470     case PWR_GPIO_F:
00471        SET_BIT(PWR->PDCRF, GPIONumber);
00472        CLEAR_BIT(PWR->PUCRF, GPIONumber);
00473        break;
00474     case PWR_GPIO_G:
00475        SET_BIT(PWR->PDCRG, GPIONumber);
00476        CLEAR_BIT(PWR->PUCRG, GPIONumber);
00477        break;
00478 #endif
00479     case PWR_GPIO_H:
00480        SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00481        CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00482        break;
00483     default:
00484         return HAL_ERROR;
00485   }
00486
00487   return HAL_OK;
00488 }
00489
00490
00491 /**
00492   * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
00493   * @note  Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
00494   *        in pull-down state in Standby and Shutdown modes.
00495   * @note  Even if a PDy bit to reset is reserved, the other PDy bits entered as input
00496   *        parameter at the same time are reset.
00497   * @param  GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
00498   *         to select the GPIO peripheral.
00499   * @param  GPIONumber: Specify the I/O pins numbers.
00500   *         This parameter can be one of the following values:
00501   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
00502   *         I/O pins are available) or the logical OR of several of them to reset
00503   *         several bits for a given port in a single API call.
00504   * @retval HAL Status
00505   */
00506 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
00507 {
00508   assert_param(IS_PWR_GPIO(GPIO));
00509   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00510
00511   switch (GPIO)
00512   {
00513     case PWR_GPIO_A:
00514        CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
00515        break;
00516     case PWR_GPIO_B:
00517        CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
00518        break;
00519     case PWR_GPIO_C:
00520        CLEAR_BIT(PWR->PDCRC, GPIONumber);
00521        break;
00522 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00523     case PWR_GPIO_D:
00524        CLEAR_BIT(PWR->PDCRD, GPIONumber);
00525        break;
00526     case PWR_GPIO_E:
00527        CLEAR_BIT(PWR->PDCRE, GPIONumber);
00528        break;
00529 #endif
00530 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00531     case PWR_GPIO_F:
00532        CLEAR_BIT(PWR->PDCRF, GPIONumber);
00533        break;
00534     case PWR_GPIO_G:
00535        CLEAR_BIT(PWR->PDCRG, GPIONumber);
00536        break;
00537 #endif
00538     case PWR_GPIO_H:
00539       CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00540        break;
00541     default:
00542         return HAL_ERROR;
00543   }
00544
00545   return HAL_OK;
00546 }
00547
00548
00549
00550 /**
00551   * @brief Enable pull-up and pull-down configuration.
00552   * @note  When APC bit is set, the I/O pull-up and pull-down configurations defined in
00553   *        PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
00554   * @note  Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
00555   *        PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
00556   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
00557   *        is no conflict when setting PUy or PDy bit.
00558   * @retval None
00559   */
00560 void HAL_PWREx_EnablePullUpPullDownConfig(void)
00561 {
00562   SET_BIT(PWR->CR3, PWR_CR3_APC);
00563 }
00564
00565
00566 /**
00567   * @brief Disable pull-up and pull-down configuration.
00568   * @note  When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
00569   *        PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
00570   * @retval None
00571   */
00572 void HAL_PWREx_DisablePullUpPullDownConfig(void)
00573 {
00574   CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
00575 }
00576
00577
00578
00579 /**
00580   * @brief Enable SRAM2 content retention in Standby mode.
00581   * @note  When RRS bit is set, SRAM2 is powered by the low-power regulator in
00582   *         Standby mode and its content is kept.
00583   * @retval None
00584   */
00585 void HAL_PWREx_EnableSRAM2ContentRetention(void)
00586 {
00587   SET_BIT(PWR->CR3, PWR_CR3_RRS);
00588 }
00589
00590
00591 /**
00592   * @brief Disable SRAM2 content retention in Standby mode.
00593   * @note  When RRS bit is reset, SRAM2 is powered off in Standby mode
00594   *        and its content is lost.
00595   * @retval None
00596   */
00597 void HAL_PWREx_DisableSRAM2ContentRetention(void)
00598 {
00599   CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
00600 }
00601
00602
00603
00604
00605 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00606 /**
00607   * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
00608   * @retval None
00609   */
00610 void HAL_PWREx_EnablePVM1(void)
00611 {
00612   SET_BIT(PWR->CR2, PWR_PVM_1);
00613 }
00614
00615 /**
00616   * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
00617   * @retval None
00618   */
00619 void HAL_PWREx_DisablePVM1(void)
00620 {
00621   CLEAR_BIT(PWR->CR2, PWR_PVM_1);
00622 }
00623 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00624
00625
00626 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00627 /**
00628   * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
00629   * @retval None
00630   */
00631 void HAL_PWREx_EnablePVM2(void)
00632 {
00633   SET_BIT(PWR->CR2, PWR_PVM_2);
00634 }
00635
00636 /**
00637   * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
00638   * @retval None
00639   */
00640 void HAL_PWREx_DisablePVM2(void)
00641 {
00642   CLEAR_BIT(PWR->CR2, PWR_PVM_2);
00643 }
00644 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00645
00646
00647 /**
00648   * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
00649   * @retval None
00650   */
00651 void HAL_PWREx_EnablePVM3(void)
00652 {
00653   SET_BIT(PWR->CR2, PWR_PVM_3);
00654 }
00655
00656 /**
00657   * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
00658   * @retval None
00659   */
00660 void HAL_PWREx_DisablePVM3(void)
00661 {
00662   CLEAR_BIT(PWR->CR2, PWR_PVM_3);
00663 }
00664
00665
00666 /**
00667   * @brief Enable the Power Voltage Monitoring 4:  VDDA versus 2.2V.
00668   * @retval None
00669   */
00670 void HAL_PWREx_EnablePVM4(void)
00671 {
00672   SET_BIT(PWR->CR2, PWR_PVM_4);
00673 }
00674
00675 /**
00676   * @brief Disable the Power Voltage Monitoring 4:  VDDA versus 2.2V.
00677   * @retval None
00678   */
00679 void HAL_PWREx_DisablePVM4(void)
00680 {
00681   CLEAR_BIT(PWR->CR2, PWR_PVM_4);
00682 }
00683
00684
00685
00686
00687 /**
00688   * @brief Configure the Peripheral Voltage Monitoring (PVM).
00689   * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
00690   *        PVM configuration information.
00691   * @note The API configures a single PVM according to the information contained
00692   *       in the input structure. To configure several PVMs, the API must be singly
00693   *       called for each PVM used.
00694   * @note Refer to the electrical characteristics of your device datasheet for
00695   *         more details about the voltage thresholds corresponding to each
00696   *         detection level and to each monitored supply.
00697   * @retval HAL status
00698   */
00699 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
00700 {
00701   /* Check the parameters */
00702   assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
00703   assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
00704
00705
00706   /* Configure EXTI 35 to 38 interrupts if so required:
00707      scan thru PVMType to detect which PVMx is set and
00708      configure the corresponding EXTI line accordingly. */
00709   switch (sConfigPVM->PVMType)
00710   {
00711 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00712     case PWR_PVM_1:
00713       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00714       __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
00715       __HAL_PWR_PVM1_EXTI_DISABLE_IT();
00716       __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
00717       __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
00718
00719       /* Configure interrupt mode */
00720       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00721       {
00722         __HAL_PWR_PVM1_EXTI_ENABLE_IT();
00723       }
00724
00725       /* Configure event mode */
00726       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00727       {
00728         __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
00729       }
00730
00731       /* Configure the edge */
00732       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00733       {
00734         __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
00735       }
00736
00737       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00738       {
00739         __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
00740       }
00741       break;
00742 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00743
00744 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00745     case PWR_PVM_2:
00746       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00747       __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
00748       __HAL_PWR_PVM2_EXTI_DISABLE_IT();
00749       __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
00750       __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
00751
00752       /* Configure interrupt mode */
00753       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00754       {
00755         __HAL_PWR_PVM2_EXTI_ENABLE_IT();
00756       }
00757
00758       /* Configure event mode */
00759       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00760       {
00761         __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
00762       }
00763
00764       /* Configure the edge */
00765       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00766       {
00767         __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
00768       }
00769
00770       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00771       {
00772         __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
00773       }
00774       break;
00775 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00776
00777     case PWR_PVM_3:
00778       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00779       __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
00780       __HAL_PWR_PVM3_EXTI_DISABLE_IT();
00781       __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
00782       __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
00783
00784       /* Configure interrupt mode */
00785       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00786       {
00787         __HAL_PWR_PVM3_EXTI_ENABLE_IT();
00788       }
00789
00790       /* Configure event mode */
00791       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00792       {
00793         __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
00794       }
00795
00796       /* Configure the edge */
00797       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00798       {
00799         __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
00800       }
00801
00802       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00803       {
00804         __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
00805       }
00806       break;
00807
00808     case PWR_PVM_4:
00809       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00810       __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
00811       __HAL_PWR_PVM4_EXTI_DISABLE_IT();
00812       __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
00813       __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
00814
00815       /* Configure interrupt mode */
00816       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00817       {
00818         __HAL_PWR_PVM4_EXTI_ENABLE_IT();
00819       }
00820
00821       /* Configure event mode */
00822       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00823       {
00824         __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
00825       }
00826
00827       /* Configure the edge */
00828       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00829       {
00830         __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
00831       }
00832
00833       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00834       {
00835         __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
00836       }
00837       break;
00838
00839     default:
00840       return HAL_ERROR;
00841
00842   }
00843
00844
00845   return HAL_OK;
00846 }
00847
00848
00849
00850 /**
00851   * @brief Enter Low-power Run mode
00852   * @note  In Low-power Run mode, all I/O pins keep the same state as in Run mode.
00853   * @note  When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
00854   *        Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
00855   *        Additionally, the clock frequency must be reduced below 2 MHz.
00856   *        Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
00857   *        be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
00858   * @retval None
00859   */
00860 void HAL_PWREx_EnableLowPowerRunMode(void)
00861 {
00862   /* Set Regulator parameter */
00863   SET_BIT(PWR->CR1, PWR_CR1_LPR);
00864 }
00865
00866
00867 /**
00868   * @brief Exit Low-power Run mode.
00869   * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
00870   *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
00871   *        returns HAL_TIMEOUT status). The system clock frequency can then be
00872   *        increased above 2 MHz.
00873   * @retval HAL Status
00874   */
00875 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
00876 {
00877   uint32_t wait_loop_index = 0;
00878
00879   /* Clear LPR bit */
00880   CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
00881
00882   /* Wait until REGLPF is reset */
00883   wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
00884   while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)))
00885   {
00886     wait_loop_index--;
00887   }
00888   if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
00889   {
00890     return HAL_TIMEOUT;
00891   }
00892
00893   return HAL_OK;
00894 }
00895
00896
00897 /**
00898   * @brief Enter Stop 0 mode.
00899   * @note  In Stop 0 mode, main and low voltage regulators are ON.
00900   * @note  In Stop 0 mode, all I/O pins keep the same state as in Run mode.
00901   * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,
00902   *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
00903   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
00904   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
00905   *        only to the peripheral requesting it.
00906   *        SRAM1, SRAM2 and register contents are preserved.
00907   *        The BOR is available.
00908   * @note  When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
00909   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
00910   *         is set; the MSI oscillator is selected if STOPWUCK is cleared.
00911   * @note  By keeping the internal regulator ON during Stop 0 mode, the consumption
00912   *         is higher although the startup time is reduced.
00913   * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
00914   *          This parameter can be one of the following values:
00915   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
00916   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
00917   * @retval None
00918   */
00919 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
00920 {
00921   /* Check the parameters */
00922   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00923
00924   /* Stop 0 mode with Main Regulator */
00925   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
00926
00927   /* Set SLEEPDEEP bit of Cortex System Control Register */
00928   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00929
00930   /* Select Stop mode entry --------------------------------------------------*/
00931   if(STOPEntry == PWR_STOPENTRY_WFI)
00932   {
00933     /* Request Wait For Interrupt */
00934     __WFI();
00935   }
00936   else
00937   {
00938     /* Request Wait For Event */
00939     __SEV();
00940     __WFE();
00941     __WFE();
00942   }
00943
00944   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00945   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00946 }
00947
00948
00949 /**
00950   * @brief Enter Stop 1 mode.
00951   * @note  In Stop 1 mode, only low power voltage regulator is ON.
00952   * @note  In Stop 1 mode, all I/O pins keep the same state as in Run mode.
00953   * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,
00954   *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
00955   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
00956   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
00957   *        only to the peripheral requesting it.
00958   *        SRAM1, SRAM2 and register contents are preserved.
00959   *        The BOR is available.
00960   * @note  When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
00961   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
00962   *         is set; the MSI oscillator is selected if STOPWUCK is cleared.
00963   * @note  Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
00964   * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
00965   *          This parameter can be one of the following values:
00966   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
00967   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
00968   * @retval None
00969   */
00970 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
00971 {
00972   /* Check the parameters */
00973   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00974
00975   /* Stop 1 mode with Low-Power Regulator */
00976   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
00977
00978   /* Set SLEEPDEEP bit of Cortex System Control Register */
00979   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00980
00981   /* Select Stop mode entry --------------------------------------------------*/
00982   if(STOPEntry == PWR_STOPENTRY_WFI)
00983   {
00984     /* Request Wait For Interrupt */
00985     __WFI();
00986   }
00987   else
00988   {
00989     /* Request Wait For Event */
00990     __SEV();
00991     __WFE();
00992     __WFE();
00993   }
00994
00995   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00996   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00997 }
00998
00999
01000 /**
01001   * @brief Enter Stop 2 mode.
01002   * @note  In Stop 2 mode, only low power voltage regulator is ON.
01003   * @note  In Stop 2 mode, all I/O pins keep the same state as in Run mode.
01004   * @note  All clocks in the VCORE domain are stopped, the PLL, the MSI,
01005   *        the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
01006   *        (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
01007   *        receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
01008   *        to the peripheral requesting it.
01009   *        SRAM1, SRAM2 and register contents are preserved.
01010   *        The BOR is available.
01011   *        The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
01012   *        Otherwise, Stop 1 mode is entered.
01013   * @note  When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
01014   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
01015   *         is set; the MSI oscillator is selected if STOPWUCK is cleared.
01016   * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
01017   *          This parameter can be one of the following values:
01018   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
01019   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
01020   * @retval None
01021   */
01022 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
01023 {
01024   /* Check the parameter */
01025   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
01026
01027   /* Set Stop mode 2 */
01028   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
01029
01030   /* Set SLEEPDEEP bit of Cortex System Control Register */
01031   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01032
01033   /* Select Stop mode entry --------------------------------------------------*/
01034   if(STOPEntry == PWR_STOPENTRY_WFI)
01035   {
01036     /* Request Wait For Interrupt */
01037     __WFI();
01038   }
01039   else
01040   {
01041     /* Request Wait For Event */
01042     __SEV();
01043     __WFE();
01044     __WFE();
01045   }
01046
01047   /* Reset SLEEPDEEP bit of Cortex System Control Register */
01048   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01049 }
01050
01051
01052
01053
01054
01055 /**
01056   * @brief Enter Shutdown mode.
01057   * @note  In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
01058   *        off. The voltage regulator is disabled and Vcore domain is powered off.
01059   *        SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
01060   *        The BOR is not available.
01061   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
01062   * @retval None
01063   */
01064 void HAL_PWREx_EnterSHUTDOWNMode(void)
01065 {
01066
01067   /* Set Shutdown mode */
01068   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
01069
01070   /* Set SLEEPDEEP bit of Cortex System Control Register */
01071   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01072
01073 /* This option is used to ensure that store operations are completed */
01074 #if defined ( __CC_ARM)
01075   __force_stores();
01076 #endif
01077   /* Request Wait For Interrupt */
01078   __WFI();
01079 }
01080
01081
01082
01083
01084 /**
01085   * @brief This function handles the PWR PVD/PVMx interrupt request.
01086   * @note This API should be called under the PVD_PVM_IRQHandler().
01087   * @retval None
01088   */
01089 void HAL_PWREx_PVD_PVM_IRQHandler(void)
01090 {
01091   /* Check PWR exti flag */
01092   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
01093   {
01094     /* PWR PVD interrupt user callback */
01095     HAL_PWR_PVDCallback();
01096
01097     /* Clear PVD exti pending bit */
01098     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
01099   }
01100   /* Next, successively check PVMx exti flags */
01101 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01102   if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET)
01103   {
01104     /* PWR PVM1 interrupt user callback */
01105     HAL_PWREx_PVM1Callback();
01106
01107     /* Clear PVM1 exti pending bit */
01108     __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
01109   }
01110 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01111 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01112   if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET)
01113   {
01114     /* PWR PVM2 interrupt user callback */
01115     HAL_PWREx_PVM2Callback();
01116
01117     /* Clear PVM2 exti pending bit */
01118     __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
01119   }
01120 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01121   if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET)
01122   {
01123     /* PWR PVM3 interrupt user callback */
01124     HAL_PWREx_PVM3Callback();
01125
01126     /* Clear PVM3 exti pending bit */
01127     __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
01128   }
01129   if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET)
01130   {
01131     /* PWR PVM4 interrupt user callback */
01132     HAL_PWREx_PVM4Callback();
01133
01134     /* Clear PVM4 exti pending bit */
01135     __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
01136   }
01137 }
01138
01139
01140 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01141 /**
01142   * @brief PWR PVM1 interrupt callback
01143   * @retval None
01144   */
01145 __weak void HAL_PWREx_PVM1Callback(void)
01146 {
01147   /* NOTE : This function should not be modified; when the callback is needed,
01148             HAL_PWREx_PVM1Callback() API can be implemented in the user file
01149    */
01150 }
01151 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01152
01153 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
01154 /**
01155   * @brief PWR PVM2 interrupt callback
01156   * @retval None
01157   */
01158 __weak void HAL_PWREx_PVM2Callback(void)
01159 {
01160   /* NOTE : This function should not be modified; when the callback is needed,
01161             HAL_PWREx_PVM2Callback() API can be implemented in the user file
01162    */
01163 }
01164 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01165
01166 /**
01167   * @brief PWR PVM3 interrupt callback
01168   * @retval None
01169   */
01170 __weak void HAL_PWREx_PVM3Callback(void)
01171 {
01172   /* NOTE : This function should not be modified; when the callback is needed,
01173             HAL_PWREx_PVM3Callback() API can be implemented in the user file
01174    */
01175 }
01176
01177 /**
01178   * @brief PWR PVM4 interrupt callback
01179   * @retval None
01180   */
01181 __weak void HAL_PWREx_PVM4Callback(void)
01182 {
01183   /* NOTE : This function should not be modified; when the callback is needed,
01184             HAL_PWREx_PVM4Callback() API can be implemented in the user file
01185    */
01186 }
01187
01188
01189 /**
01190   * @}
01191   */
01192
01193 /**
01194   * @}
01195   */
01196
01197 #endif /* HAL_PWR_MODULE_ENABLED */
01198 /**
01199   * @}
01200   */
01201
01202 /**
01203   * @}
01204   */
01205
01206 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_pwr_ex.h Source File

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stm32l4xx_hal_pwr_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pwr_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of PWR HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_PWR_EX_H
00040 #define __STM32L4xx_HAL_PWR_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PWREx
00054   * @{
00055   */
00056
00057
00058 /* Exported types ------------------------------------------------------------*/
00059
00060 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
00061   * @{
00062   */
00063
00064
00065 /**
00066   * @brief  PWR PVM configuration structure definition
00067   */
00068 typedef struct
00069 {
00070   uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold.
00071                            This parameter can be a value of @ref PWREx_PVM_Type.
00072                            @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
00073 @if STM32L486xx
00074                            @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
00075 @endif
00076                            @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
00077                            @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
00078
00079   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00080                            This parameter can be a value of @ref PWREx_PVM_Mode. */
00081 }PWR_PVMTypeDef;
00082
00083 /**
00084   * @}
00085   */
00086
00087 /* Exported constants --------------------------------------------------------*/
00088
00089 /** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
00090   * @{
00091   */
00092
00093 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
00094   * @{
00095   */
00096 #define PWR_WUP_POLARITY_SHIFT                  0x05   /*!< Internal constant used to retrieve wakeup pin polariry */
00097 /**
00098   * @}
00099   */
00100
00101
00102 /** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins
00103   * @{
00104   */
00105 #define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
00106 #define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
00107 #define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
00108 #define PWR_WAKEUP_PIN4                 PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
00109 #define PWR_WAKEUP_PIN5                 PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
00110 #define PWR_WAKEUP_PIN1_HIGH            PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
00111 #define PWR_WAKEUP_PIN2_HIGH            PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
00112 #define PWR_WAKEUP_PIN3_HIGH            PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
00113 #define PWR_WAKEUP_PIN4_HIGH            PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
00114 #define PWR_WAKEUP_PIN5_HIGH            PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
00115 #define PWR_WAKEUP_PIN1_LOW             (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
00116 #define PWR_WAKEUP_PIN2_LOW             (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
00117 #define PWR_WAKEUP_PIN3_LOW             (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
00118 #define PWR_WAKEUP_PIN4_LOW             (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
00119 #define PWR_WAKEUP_PIN5_LOW             (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
00120 /**
00121   * @}
00122   */
00123
00124 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
00125   * @{
00126   */
00127 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
00128     defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00129 #define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
00130 #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00131 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00132 #define PWR_PVM_2                  PWR_CR2_PVME2  /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
00133 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00134 #define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
00135 #define PWR_PVM_4                  PWR_CR2_PVME4  /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V  */
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
00141   * @{
00142   */
00143 #define PWR_PVM_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
00144 #define PWR_PVM_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
00145 #define PWR_PVM_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
00146 #define PWR_PVM_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00147 #define PWR_PVM_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
00148 #define PWR_PVM_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
00149 #define PWR_PVM_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
00150 /**
00151   * @}
00152   */
00153
00154
00155
00156 /** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
00157   * @{
00158   */
00159 #define PWR_REGULATOR_VOLTAGE_SCALE1       PWR_CR1_VOS_0     /*!< Voltage scaling range 1 */
00160 #define PWR_REGULATOR_VOLTAGE_SCALE2       PWR_CR1_VOS_1     /*!< Voltage scaling range 2 */
00161 /**
00162   * @}
00163   */
00164
00165
00166 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
00167   * @{
00168   */
00169 #define PWR_BATTERY_CHARGING_RESISTOR_5          ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor   */
00170 #define PWR_BATTERY_CHARGING_RESISTOR_1_5         PWR_CR4_VBRS          /*!< VBAT charging through a 1.5 kOhms resistor */
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
00176   * @{
00177   */
00178 #define PWR_BATTERY_CHARGING_DISABLE        ((uint32_t)0x00000000)
00179 #define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
00185   * @{
00186   */
00187 #define PWR_GPIO_BIT_0   PWR_PUCRA_PA0    /*!< GPIO port I/O pin 0  */
00188 #define PWR_GPIO_BIT_1   PWR_PUCRA_PA1    /*!< GPIO port I/O pin 1  */
00189 #define PWR_GPIO_BIT_2   PWR_PUCRA_PA2    /*!< GPIO port I/O pin 2  */
00190 #define PWR_GPIO_BIT_3   PWR_PUCRA_PA3    /*!< GPIO port I/O pin 3  */
00191 #define PWR_GPIO_BIT_4   PWR_PUCRA_PA4    /*!< GPIO port I/O pin 4  */
00192 #define PWR_GPIO_BIT_5   PWR_PUCRA_PA5    /*!< GPIO port I/O pin 5  */
00193 #define PWR_GPIO_BIT_6   PWR_PUCRA_PA6    /*!< GPIO port I/O pin 6  */
00194 #define PWR_GPIO_BIT_7   PWR_PUCRA_PA7    /*!< GPIO port I/O pin 7  */
00195 #define PWR_GPIO_BIT_8   PWR_PUCRA_PA8    /*!< GPIO port I/O pin 8  */
00196 #define PWR_GPIO_BIT_9   PWR_PUCRA_PA9    /*!< GPIO port I/O pin 9  */
00197 #define PWR_GPIO_BIT_10  PWR_PUCRA_PA10   /*!< GPIO port I/O pin 10 */
00198 #define PWR_GPIO_BIT_11  PWR_PUCRA_PA11   /*!< GPIO port I/O pin 11 */
00199 #define PWR_GPIO_BIT_12  PWR_PUCRA_PA12   /*!< GPIO port I/O pin 12 */
00200 #define PWR_GPIO_BIT_13  PWR_PUCRA_PA13   /*!< GPIO port I/O pin 13 */
00201 #define PWR_GPIO_BIT_14  PWR_PDCRA_PA14   /*!< GPIO port I/O pin 14 */
00202 #define PWR_GPIO_BIT_15  PWR_PUCRA_PA15   /*!< GPIO port I/O pin 15 */
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup PWREx_GPIO GPIO port
00208   * @{
00209   */
00210 #define PWR_GPIO_A   0x00000000      /*!< GPIO port A */
00211 #define PWR_GPIO_B   0x00000001      /*!< GPIO port B */
00212 #define PWR_GPIO_C   0x00000002      /*!< GPIO port C */
00213 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) ||                                                   \
00214     defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00215 #define PWR_GPIO_D   0x00000003      /*!< GPIO port D */
00216 #define PWR_GPIO_E   0x00000004      /*!< GPIO port E */
00217 #endif
00218 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00219 #define PWR_GPIO_F   0x00000005      /*!< GPIO port F */
00220 #define PWR_GPIO_G   0x00000006      /*!< GPIO port G */
00221 #endif
00222 #define PWR_GPIO_H   0x00000007      /*!< GPIO port H */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
00228   * @{
00229   */
00230 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00231 #define PWR_EXTI_LINE_PVM1  ((uint32_t)0x00000008)  /*!< External interrupt line 35 Connected to the PVM1 EXTI Line   */
00232 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00233 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00234 #define PWR_EXTI_LINE_PVM2  ((uint32_t)0x00000010)  /*!< External interrupt line 36 Connected to the PVM2 EXTI Line   */
00235 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00236 #define PWR_EXTI_LINE_PVM3  ((uint32_t)0x00000020)  /*!< External interrupt line 37 Connected to the PVM3 EXTI Line   */
00237 #define PWR_EXTI_LINE_PVM4  ((uint32_t)0x00000040)  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
00243   * @{
00244   */
00245 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00246 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)  /*!< Event line 35 Connected to the PVM1 EXTI Line */
00247 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00248 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00249 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)  /*!< Event line 36 Connected to the PVM2 EXTI Line */
00250 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00251 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)  /*!< Event line 37 Connected to the PVM3 EXTI Line */
00252 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)  /*!< Event line 38 Connected to the PVM4 EXTI Line */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup PWREx_Flag  PWR Status Flags
00258   *        Elements values convention: 0000 0000 0XXY YYYYb
00259   *           - Y YYYY  : Flag position in the XX register (5 bits)
00260   *           - XX  : Status register (2 bits)
00261   *                 - 01: SR1 register
00262   *                 - 10: SR2 register
00263   *        The only exception is PWR_FLAG_WU, encompassing all
00264   *        wake-up flags and set to PWR_SR1_WUF.
00265   * @{
00266   */
00267 #define PWR_FLAG_WUF1                       ((uint32_t)0x0020)   /*!< Wakeup event on wakeup pin 1 */
00268 #define PWR_FLAG_WUF2                       ((uint32_t)0x0021)   /*!< Wakeup event on wakeup pin 2 */
00269 #define PWR_FLAG_WUF3                       ((uint32_t)0x0022)   /*!< Wakeup event on wakeup pin 3 */
00270 #define PWR_FLAG_WUF4                       ((uint32_t)0x0023)   /*!< Wakeup event on wakeup pin 4 */
00271 #define PWR_FLAG_WUF5                       ((uint32_t)0x0024)   /*!< Wakeup event on wakeup pin 5 */
00272 #define PWR_FLAG_WU                         PWR_SR1_WUF          /*!< Encompass wakeup event on all wakeup pins */
00273 #define PWR_FLAG_SB                         ((uint32_t)0x0028)   /*!< Standby flag */
00274 #define PWR_FLAG_WUFI                       ((uint32_t)0x002F)   /*!< Wakeup on internal wakeup line */
00275
00276 #define PWR_FLAG_REGLPS                     ((uint32_t)0x0048)   /*!< Low-power regulator start flag */
00277 #define PWR_FLAG_REGLPF                     ((uint32_t)0x0049)   /*!< Low-power regulator flag */
00278 #define PWR_FLAG_VOSF                       ((uint32_t)0x004A)   /*!< Voltage scaling flag */
00279 #define PWR_FLAG_PVDO                       ((uint32_t)0x004B)   /*!< Power Voltage Detector output flag */
00280 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00281 #define PWR_FLAG_PVMO1                      ((uint32_t)0x004C)   /*!< Power Voltage Monitoring 1 output flag */
00282 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00283 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00284 #define PWR_FLAG_PVMO2                      ((uint32_t)0x004D)   /*!< Power Voltage Monitoring 2 output flag */
00285 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00286 #define PWR_FLAG_PVMO3                      ((uint32_t)0x004E)   /*!< Power Voltage Monitoring 3 output flag */
00287 #define PWR_FLAG_PVMO4                      ((uint32_t)0x004F)   /*!< Power Voltage Monitoring 4 output flag */
00288 /**
00289   * @}
00290   */
00291
00292 /**
00293   * @}
00294   */
00295
00296 /* Exported macros -----------------------------------------------------------*/
00297 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
00298  * @{
00299  */
00300
00301 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00302 /**
00303   * @brief Enable the PVM1 Extended Interrupt Line.
00304   * @retval None
00305   */
00306 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
00307
00308 /**
00309   * @brief Disable the PVM1 Extended Interrupt Line.
00310   * @retval None
00311   */
00312 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
00313
00314 /**
00315   * @brief Enable the PVM1 Event Line.
00316   * @retval None
00317   */
00318 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
00319
00320 /**
00321   * @brief Disable the PVM1 Event Line.
00322   * @retval None
00323   */
00324 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
00325
00326 /**
00327   * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
00328   * @retval None
00329   */
00330 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
00331
00332 /**
00333   * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
00334   * @retval None
00335   */
00336 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
00337
00338 /**
00339   * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
00340   * @retval None
00341   */
00342 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
00343
00344
00345 /**
00346   * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
00347   * @retval None
00348   */
00349 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
00350
00351
00352 /**
00353   * @brief  PVM1 EXTI line configuration: set rising & falling edge trigger.
00354   * @retval None
00355   */
00356 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00357   do {                                                    \
00358     __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
00359     __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
00360   } while(0)
00361
00362 /**
00363   * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
00364   * @retval None
00365   */
00366 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00367   do {                                                     \
00368     __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
00369     __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
00370   } while(0)
00371
00372 /**
00373   * @brief  Generate a Software interrupt on selected EXTI line.
00374   * @retval None
00375   */
00376 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
00377
00378 /**
00379   * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
00380   * @retval EXTI PVM1 Line Status.
00381   */
00382 #define __HAL_PWR_PVM1_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
00383
00384 /**
00385   * @brief Clear the PVM1 EXTI flag.
00386   * @retval None
00387   */
00388 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
00389
00390 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00391
00392
00393 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00394 /**
00395   * @brief Enable the PVM2 Extended Interrupt Line.
00396   * @retval None
00397   */
00398 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
00399
00400 /**
00401   * @brief Disable the PVM2 Extended Interrupt Line.
00402   * @retval None
00403   */
00404 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
00405
00406 /**
00407   * @brief Enable the PVM2 Event Line.
00408   * @retval None
00409   */
00410 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
00411
00412 /**
00413   * @brief Disable the PVM2 Event Line.
00414   * @retval None
00415   */
00416 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
00417
00418 /**
00419   * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
00420   * @retval None
00421   */
00422 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
00423
00424 /**
00425   * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
00426   * @retval None
00427   */
00428 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
00429
00430 /**
00431   * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
00432   * @retval None
00433   */
00434 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
00435
00436
00437 /**
00438   * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
00439   * @retval None
00440   */
00441 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
00442
00443
00444 /**
00445   * @brief  PVM2 EXTI line configuration: set rising & falling edge trigger.
00446   * @retval None
00447   */
00448 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00449   do {                                                    \
00450     __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \
00451     __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \
00452   } while(0)
00453
00454 /**
00455   * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
00456   * @retval None
00457   */
00458 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00459   do {                                                     \
00460     __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \
00461     __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \
00462   } while(0)
00463
00464 /**
00465   * @brief  Generate a Software interrupt on selected EXTI line.
00466   * @retval None
00467   */
00468 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
00469
00470 /**
00471   * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
00472   * @retval EXTI PVM2 Line Status.
00473   */
00474 #define __HAL_PWR_PVM2_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
00475
00476 /**
00477   * @brief Clear the PVM2 EXTI flag.
00478   * @retval None
00479   */
00480 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
00481
00482 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00483
00484
00485 /**
00486   * @brief Enable the PVM3 Extended Interrupt Line.
00487   * @retval None
00488   */
00489 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
00490
00491 /**
00492   * @brief Disable the PVM3 Extended Interrupt Line.
00493   * @retval None
00494   */
00495 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
00496
00497 /**
00498   * @brief Enable the PVM3 Event Line.
00499   * @retval None
00500   */
00501 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
00502
00503 /**
00504   * @brief Disable the PVM3 Event Line.
00505   * @retval None
00506   */
00507 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
00508
00509 /**
00510   * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
00511   * @retval None
00512   */
00513 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
00514
00515 /**
00516   * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
00517   * @retval None
00518   */
00519 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
00520
00521 /**
00522   * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
00523   * @retval None
00524   */
00525 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
00526
00527
00528 /**
00529   * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
00530   * @retval None
00531   */
00532 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
00533
00534
00535 /**
00536   * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.
00537   * @retval None
00538   */
00539 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00540   do {                                                    \
00541     __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
00542     __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
00543   } while(0)
00544
00545 /**
00546   * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
00547   * @retval None
00548   */
00549 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00550   do {                                                     \
00551     __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
00552     __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
00553   } while(0)
00554
00555 /**
00556   * @brief  Generate a Software interrupt on selected EXTI line.
00557   * @retval None
00558   */
00559 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
00560
00561 /**
00562   * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
00563   * @retval EXTI PVM3 Line Status.
00564   */
00565 #define __HAL_PWR_PVM3_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
00566
00567 /**
00568   * @brief Clear the PVM3 EXTI flag.
00569   * @retval None
00570   */
00571 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
00572
00573
00574
00575
00576 /**
00577   * @brief Enable the PVM4 Extended Interrupt Line.
00578   * @retval None
00579   */
00580 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
00581
00582 /**
00583   * @brief Disable the PVM4 Extended Interrupt Line.
00584   * @retval None
00585   */
00586 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
00587
00588 /**
00589   * @brief Enable the PVM4 Event Line.
00590   * @retval None
00591   */
00592 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
00593
00594 /**
00595   * @brief Disable the PVM4 Event Line.
00596   * @retval None
00597   */
00598 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
00599
00600 /**
00601   * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
00602   * @retval None
00603   */
00604 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
00605
00606 /**
00607   * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
00608   * @retval None
00609   */
00610 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
00611
00612 /**
00613   * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
00614   * @retval None
00615   */
00616 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
00617
00618
00619 /**
00620   * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
00621   * @retval None
00622   */
00623 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
00624
00625
00626 /**
00627   * @brief  PVM4 EXTI line configuration: set rising & falling edge trigger.
00628   * @retval None
00629   */
00630 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00631   do {                                                    \
00632     __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \
00633     __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \
00634   } while(0)
00635
00636 /**
00637   * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
00638   * @retval None
00639   */
00640 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00641   do {                                                     \
00642     __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \
00643     __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \
00644   } while(0)
00645
00646 /**
00647   * @brief  Generate a Software interrupt on selected EXTI line.
00648   * @retval None
00649   */
00650 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
00651
00652 /**
00653   * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
00654   * @retval EXTI PVM4 Line Status.
00655   */
00656 #define __HAL_PWR_PVM4_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
00657
00658 /**
00659   * @brief Clear the PVM4 EXTI flag.
00660   * @retval None
00661   */
00662 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
00663
00664
00665 /**
00666   * @brief Configure the main internal regulator output voltage.
00667   * @param  __REGULATOR__: specifies the regulator output voltage to achieve
00668   *         a tradeoff between performance and power consumption.
00669   *          This parameter can be one of the following values:
00670   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,
00671   *                                                typical output voltage at 1.2 V,
00672   *                                                system frequency up to 80 MHz.
00673   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,
00674   *                                                typical output voltage at 1.0 V,
00675   *                                                system frequency up to 26 MHz.
00676   * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
00677   *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User
00678   *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
00679   * @retval None
00680   */
00681 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
00682                                                             __IO uint32_t tmpreg;                               \
00683                                                             MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
00684                                                             /* Delay after an RCC peripheral clock enabling */  \
00685                                                             tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
00686                                                             UNUSED(tmpreg);                                     \
00687                                                           } while(0)
00688
00689 /**
00690   * @}
00691   */
00692
00693 /* Private macros --------------------------------------------------------*/
00694 /** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
00695   * @{
00696   */
00697
00698 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
00699                                 ((PIN) == PWR_WAKEUP_PIN2) || \
00700                                 ((PIN) == PWR_WAKEUP_PIN3) || \
00701                                 ((PIN) == PWR_WAKEUP_PIN4) || \
00702                                 ((PIN) == PWR_WAKEUP_PIN5) || \
00703                                 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
00704                                 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
00705                                 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
00706                                 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
00707                                 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
00708                                 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
00709                                 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
00710                                 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
00711                                 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
00712                                 ((PIN) == PWR_WAKEUP_PIN5_LOW))
00713
00714 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00715 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
00716                                ((TYPE) == PWR_PVM_2) ||\
00717                                ((TYPE) == PWR_PVM_3) ||\
00718                                ((TYPE) == PWR_PVM_4))
00719 #elif defined (STM32L471xx)
00720 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
00721                                ((TYPE) == PWR_PVM_3) ||\
00722                                ((TYPE) == PWR_PVM_4))
00723 #endif
00724
00725 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00726 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
00727                                ((TYPE) == PWR_PVM_3) ||\
00728                                ((TYPE) == PWR_PVM_4))
00729 #elif defined (STM32L431xx)
00730 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
00731                                ((TYPE) == PWR_PVM_4))
00732 #endif
00733
00734 #define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
00735                                 ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
00736                                 ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
00737                                 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
00738                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
00739                                 ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
00740                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
00741
00742 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
00743                                              ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
00744
00745 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
00746                                                   ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
00747
00748 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
00749                                            ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
00750
00751 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
00752
00753
00754 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00755 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
00756                            ((GPIO) == PWR_GPIO_B) ||\
00757                            ((GPIO) == PWR_GPIO_C) ||\
00758                            ((GPIO) == PWR_GPIO_D) ||\
00759                            ((GPIO) == PWR_GPIO_E) ||\
00760                            ((GPIO) == PWR_GPIO_F) ||\
00761                            ((GPIO) == PWR_GPIO_G) ||\
00762                            ((GPIO) == PWR_GPIO_H))
00763 #endif
00764 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
00765 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
00766                            ((GPIO) == PWR_GPIO_B) ||\
00767                            ((GPIO) == PWR_GPIO_C) ||\
00768                            ((GPIO) == PWR_GPIO_D) ||\
00769                            ((GPIO) == PWR_GPIO_E) ||\
00770                            ((GPIO) == PWR_GPIO_H))
00771 #elif defined (STM32L432xx) || defined (STM32L442xx)
00772 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
00773                            ((GPIO) == PWR_GPIO_B) ||\
00774                            ((GPIO) == PWR_GPIO_C) ||\
00775                            ((GPIO) == PWR_GPIO_H))
00776 #endif
00777
00778
00779 /**
00780   * @}
00781   */
00782
00783
00784 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
00785   * @{
00786   */
00787
00788 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
00789   * @{
00790   */
00791
00792
00793 /* Peripheral Control functions  **********************************************/
00794 uint32_t HAL_PWREx_GetVoltageRange(void);
00795 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
00796 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
00797 void HAL_PWREx_DisableBatteryCharging(void);
00798 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00799 void HAL_PWREx_EnableVddUSB(void);
00800 void HAL_PWREx_DisableVddUSB(void);
00801 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00802 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00803 void HAL_PWREx_EnableVddIO2(void);
00804 void HAL_PWREx_DisableVddIO2(void);
00805 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00806 void HAL_PWREx_EnableInternalWakeUpLine(void);
00807 void HAL_PWREx_DisableInternalWakeUpLine(void);
00808 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
00809 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
00810 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
00811 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
00812 void HAL_PWREx_EnablePullUpPullDownConfig(void);
00813 void HAL_PWREx_DisablePullUpPullDownConfig(void);
00814 void HAL_PWREx_EnableSRAM2ContentRetention(void);
00815 void HAL_PWREx_DisableSRAM2ContentRetention(void);
00816 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00817 void HAL_PWREx_EnablePVM1(void);
00818 void HAL_PWREx_DisablePVM1(void);
00819 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00820 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00821 void HAL_PWREx_EnablePVM2(void);
00822 void HAL_PWREx_DisablePVM2(void);
00823 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00824 void HAL_PWREx_EnablePVM3(void);
00825 void HAL_PWREx_DisablePVM3(void);
00826 void HAL_PWREx_EnablePVM4(void);
00827 void HAL_PWREx_DisablePVM4(void);
00828 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
00829
00830
00831 /* Low Power modes configuration functions ************************************/
00832 void HAL_PWREx_EnableLowPowerRunMode(void);
00833 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
00834 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
00835 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
00836 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
00837 void HAL_PWREx_EnterSHUTDOWNMode(void);
00838
00839 void HAL_PWREx_PVD_PVM_IRQHandler(void);
00840 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00841 void HAL_PWREx_PVM1Callback(void);
00842 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00843 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00844 void HAL_PWREx_PVM2Callback(void);
00845 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00846 void HAL_PWREx_PVM3Callback(void);
00847 void HAL_PWREx_PVM4Callback(void);
00848
00849
00850 /**
00851   * @}
00852   */
00853
00854 /**
00855   * @}
00856   */
00857
00858 /**
00859   * @}
00860   */
00861
00862 /**
00863   * @}
00864   */
00865
00866 #ifdef __cplusplus
00867 }
00868 #endif
00869
00870
00871 #endif /* __STM32L4xx_HAL_PWR_EX_H */
00872
00873 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_qspi.c Source File

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stm32l4xx_hal_qspi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_qspi.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   QSPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the QuadSPI interface (QSPI).
00010   *           + Initialization and de-initialization functions
00011   *           + Indirect functional mode management
00012   *           + Memory-mapped functional mode management
00013   *           + Auto-polling functional mode management
00014   *           + Interrupts and flags management
00015   *           + DMA channel configuration for indirect functional mode
00016   *           + Errors management and abort functionality
00017   *
00018   *
00019   @verbatim
00020  ===============================================================================
00021                         ##### How to use this driver #####
00022  ===============================================================================
00023   [..]
00024     *** Initialization ***
00025     ======================
00026     [..]
00027       (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
00028         (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
00029         (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
00030         (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00031         (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
00032         (++) If interrupt mode is used, enable and configure QuadSPI global
00033             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00034         (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
00035             with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
00036             link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
00037             DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00038       (#) Configure the flash size, the clock prescaler, the fifo threshold, the
00039           clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
00040
00041     *** Indirect functional mode ***
00042     ================================
00043     [..]
00044       (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
00045           functions :
00046          (++) Instruction phase : the mode used and if present the instruction opcode.
00047          (++) Address phase : the mode used and if present the size and the address value.
00048          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00049              bytes values.
00050          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00051          (++) Data phase : the mode used and if present the number of bytes.
00052          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00053              if activated.
00054          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00055       (#) If no data is required for the command, it is sent directly to the memory :
00056          (++) In polling mode, the output of the function is done when the transfer is complete.
00057          (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
00058       (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
00059           HAL_QSPI_Transmit_IT() after the command configuration :
00060          (++) In polling mode, the output of the function is done when the transfer is complete.
00061          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00062              is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00063          (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
00064              HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00065       (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
00066           HAL_QSPI_Receive_IT() after the command configuration :
00067          (++) In polling mode, the output of the function is done when the transfer is complete.
00068          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00069              is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00070          (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
00071              HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00072
00073     *** Auto-polling functional mode ***
00074     ====================================
00075     [..]
00076       (#) Configure the command sequence and the auto-polling functional mode using the
00077           HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
00078          (++) Instruction phase : the mode used and if present the instruction opcode.
00079          (++) Address phase : the mode used and if present the size and the address value.
00080          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00081              bytes values.
00082          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00083          (++) Data phase : the mode used.
00084          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00085              if activated.
00086          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00087          (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
00088              the polling interval and the automatic stop activation.
00089       (#) After the configuration :
00090          (++) In polling mode, the output of the function is done when the status match is reached. The
00091              automatic stop is activated to avoid an infinite loop.
00092          (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
00093
00094     *** Memory-mapped functional mode ***
00095     =====================================
00096     [..]
00097       (#) Configure the command sequence and the memory-mapped functional mode using the
00098           HAL_QSPI_MemoryMapped() functions :
00099          (++) Instruction phase : the mode used and if present the instruction opcode.
00100          (++) Address phase : the mode used and the size.
00101          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00102              bytes values.
00103          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00104          (++) Data phase : the mode used.
00105          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00106              if activated.
00107          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00108          (++) The timeout activation and the timeout period.
00109       (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
00110           the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
00111
00112     *** Errors management and abort functionality ***
00113     =================================================
00114     [..]
00115       (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
00116       (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
00117           flushes the fifo :
00118          (++) In polling mode, the output of the function is done when the transfer
00119               complete bit is set and the busy bit cleared.
00120          (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
00121               the transfer complete bi is set.
00122
00123     *** Control functions ***
00124     =========================
00125     [..]
00126       (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
00127       (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
00128       (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
00129       (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
00130
00131     *** Workarounds linked to Silicon Limitation ***
00132     ====================================================
00133     [..]
00134       (#) Workarounds Implemented inside HAL Driver
00135          (++) Extra data written in the FIFO at the end of a read transfer
00136
00137   @endverbatim
00138   ******************************************************************************
00139   * @attention
00140   *
00141   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00142   *
00143   * Redistribution and use in source and binary forms, with or without modification,
00144   * are permitted provided that the following conditions are met:
00145   *   1. Redistributions of source code must retain the above copyright notice,
00146   *      this list of conditions and the following disclaimer.
00147   *   2. Redistributions in binary form must reproduce the above copyright notice,
00148   *      this list of conditions and the following disclaimer in the documentation
00149   *      and/or other materials provided with the distribution.
00150   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00151   *      may be used to endorse or promote products derived from this software
00152   *      without specific prior written permission.
00153   *
00154   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00155   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00156   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00157   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00158   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00159   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00160   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00161   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00162   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00163   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00164   *
00165   ******************************************************************************
00166   */
00167
00168 /* Includes ------------------------------------------------------------------*/
00169 #include "stm32l4xx_hal.h"
00170
00171 /** @addtogroup STM32L4xx_HAL_Driver
00172   * @{
00173   */
00174
00175 /** @defgroup QSPI QSPI
00176   * @brief QSPI HAL module driver
00177   * @{
00178   */
00179 #ifdef HAL_QSPI_MODULE_ENABLED
00180
00181 /* Private typedef -----------------------------------------------------------*/
00182
00183 /* Private define ------------------------------------------------------------*/
00184 /** @defgroup QSPI_Private_Constants QSPI Private Constants
00185   * @{
00186   */
00187 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)          /*!<Indirect write mode*/
00188 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
00189 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
00190 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
00191 /**
00192   * @}
00193   */
00194
00195 /* Private macro -------------------------------------------------------------*/
00196 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00197   * @{
00198   */
00199 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
00200                                        ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
00201                                        ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
00202                                        ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
00203 /**
00204   * @}
00205   */
00206
00207 /* Private variables ---------------------------------------------------------*/
00208
00209 /* Private function prototypes -----------------------------------------------*/
00210 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
00211 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
00212 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00213 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00214 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
00215 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
00216 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
00217 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
00218
00219 /* Exported functions --------------------------------------------------------*/
00220
00221 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
00222   * @{
00223   */
00224
00225 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
00226   *  @brief    Initialization and Configuration functions
00227   *
00228 @verbatim
00229 ===============================================================================
00230             ##### Initialization and Configuration functions #####
00231  ===============================================================================
00232     [..]
00233     This subsection provides a set of functions allowing to :
00234       (+) Initialize the QuadSPI.
00235       (+) De-initialize the QuadSPI.
00236
00237 @endverbatim
00238   * @{
00239   */
00240
00241 /**
00242   * @brief Initialize the QSPI mode according to the specified parameters
00243   *        in the QSPI_InitTypeDef and initialize the associated handle.
00244   * @param hqspi: QSPI handle
00245   * @retval HAL status
00246   */
00247 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
00248 {
00249   HAL_StatusTypeDef status = HAL_ERROR;
00250   uint32_t tickstart = HAL_GetTick();
00251
00252   /* Check the QSPI handle allocation */
00253   if(hqspi == NULL)
00254   {
00255     return HAL_ERROR;
00256   }
00257
00258   /* Check the parameters */
00259   assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
00260   assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
00261   assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
00262   assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
00263   assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
00264   assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
00265   assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
00266 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00267   assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
00268
00269   if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
00270   {
00271     assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
00272   }
00273 #endif
00274
00275   /* Process locked */
00276   __HAL_LOCK(hqspi);
00277
00278   if(hqspi->State == HAL_QSPI_STATE_RESET)
00279   {
00280     /* Allocate lock resource and initialize it */
00281     hqspi->Lock = HAL_UNLOCKED;
00282
00283     /* Init the low level hardware : GPIO, CLOCK */
00284     HAL_QSPI_MspInit(hqspi);
00285
00286     /* Configure the default timeout for the QSPI memory access */
00287     HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
00288   }
00289
00290   /* Configure QSPI FIFO Threshold */
00291   MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
00292              ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
00293
00294   /* Wait till BUSY flag reset */
00295   status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
00296
00297   if(status == HAL_OK)
00298   {
00299     /* Configure QSPI Clock Prescaler and Sample Shift */
00300 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00301     MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
00302                ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) |
00303                 hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
00304 #else
00305     MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),
00306                ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) |
00307                 hqspi->Init.SampleShifting));
00308 #endif
00309
00310     /* Configure QSPI Flash Size, CS High Time and Clock Mode */
00311     MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
00312                ((hqspi->Init.FlashSize << POSITION_VAL(QUADSPI_DCR_FSIZE)) |
00313                 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
00314
00315     /* Enable the QSPI peripheral */
00316     __HAL_QSPI_ENABLE(hqspi);
00317
00318     /* Set QSPI error code to none */
00319     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00320
00321     /* Initialize the QSPI state */
00322     hqspi->State = HAL_QSPI_STATE_READY;
00323   }
00324
00325   /* Release Lock */
00326   __HAL_UNLOCK(hqspi);
00327
00328   /* Return function status */
00329   return status;
00330 }
00331
00332 /**
00333   * @brief De-Initialize the QSPI peripheral.
00334   * @param hqspi: QSPI handle
00335   * @retval HAL status
00336   */
00337 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
00338 {
00339   /* Check the QSPI handle allocation */
00340   if(hqspi == NULL)
00341   {
00342     return HAL_ERROR;
00343   }
00344
00345   /* Process locked */
00346   __HAL_LOCK(hqspi);
00347
00348   /* Disable the QSPI Peripheral Clock */
00349   __HAL_QSPI_DISABLE(hqspi);
00350
00351   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00352   HAL_QSPI_MspDeInit(hqspi);
00353
00354   /* Set QSPI error code to none */
00355   hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00356
00357   /* Initialize the QSPI state */
00358   hqspi->State = HAL_QSPI_STATE_RESET;
00359
00360   /* Release Lock */
00361   __HAL_UNLOCK(hqspi);
00362
00363   return HAL_OK;
00364 }
00365
00366 /**
00367   * @brief Initialize the QSPI MSP.
00368   * @param hqspi: QSPI handle
00369   * @retval None
00370   */
00371 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
00372 {
00373   /* Prevent unused argument(s) compilation warning */
00374   UNUSED(hqspi);
00375
00376   /* NOTE : This function should not be modified, when the callback is needed,
00377             the HAL_QSPI_MspInit can be implemented in the user file
00378    */
00379 }
00380
00381 /**
00382   * @brief DeInitialize the QSPI MSP.
00383   * @param hqspi: QSPI handle
00384   * @retval None
00385   */
00386 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
00387 {
00388   /* Prevent unused argument(s) compilation warning */
00389   UNUSED(hqspi);
00390
00391   /* NOTE : This function should not be modified, when the callback is needed,
00392             the HAL_QSPI_MspDeInit can be implemented in the user file
00393    */
00394 }
00395
00396 /**
00397   * @}
00398   */
00399
00400 /** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
00401   *  @brief QSPI Transmit/Receive functions
00402   *
00403 @verbatim
00404  ===============================================================================
00405                       ##### IO operation functions #####
00406  ===============================================================================
00407     [..]
00408     This subsection provides a set of functions allowing to :
00409       (+) Handle the interrupts.
00410       (+) Handle the command sequence.
00411       (+) Transmit data in blocking, interrupt or DMA mode.
00412       (+) Receive data in blocking, interrupt or DMA mode.
00413       (+) Manage the auto-polling functional mode.
00414       (+) Manage the memory-mapped functional mode.
00415
00416 @endverbatim
00417   * @{
00418   */
00419
00420 /**
00421   * @brief Handle QSPI interrupt request.
00422   * @param hqspi: QSPI handle
00423   * @retval None
00424   */
00425 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
00426 {
00427   __IO uint32_t *data_reg;
00428   uint32_t flag = READ_REG(hqspi->Instance->SR);
00429   uint32_t itsource = READ_REG(hqspi->Instance->CR);
00430
00431   /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
00432   if((flag & QSPI_FLAG_FT) && (itsource & QSPI_IT_FT))
00433   {
00434     data_reg = &hqspi->Instance->DR;
00435
00436     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00437     {
00438       /* Transmission process */
00439       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
00440       {
00441         if (hqspi->TxXferCount > 0)
00442         {
00443           /* Fill the FIFO until the threshold is reached */
00444           *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
00445           hqspi->TxXferCount--;
00446         }
00447         else
00448         {
00449           /* No more data available for the transfer */
00450           /* Disable the QSPI FIFO Threshold Interrupt */
00451           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
00452           break;
00453         }
00454       }
00455     }
00456     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00457     {
00458       /* Receiving Process */
00459       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
00460       {
00461         if (hqspi->RxXferCount > 0)
00462         {
00463           /* Read the FIFO until the threshold is reached */
00464           *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00465           hqspi->RxXferCount--;
00466         }
00467         else
00468         {
00469           /* All data have been received for the transfer */
00470           /* Disable the QSPI FIFO Threshold Interrupt */
00471           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
00472           break;
00473         }
00474       }
00475     }
00476
00477     /* FIFO Threshold callback */
00478     HAL_QSPI_FifoThresholdCallback(hqspi);
00479   }
00480
00481   /* QSPI Transfer Complete interrupt occurred -------------------------------*/
00482   else if((flag & QSPI_FLAG_TC) && (itsource & QSPI_IT_TC))
00483   {
00484     /* Clear interrupt */
00485     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
00486
00487     /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
00488     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00489
00490     /* Transfer complete callback */
00491     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00492     {
00493       if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
00494       {
00495         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00496         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00497
00498         /* Disable the DMA channel */
00499         __HAL_DMA_DISABLE(hqspi->hdma);
00500       }
00501
00502 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00503       /* Clear Busy bit */
00504       HAL_QSPI_Abort_IT(hqspi);
00505 #endif
00506
00507       /* Change state of QSPI */
00508       hqspi->State = HAL_QSPI_STATE_READY;
00509
00510       /* TX Complete callback */
00511       HAL_QSPI_TxCpltCallback(hqspi);
00512     }
00513     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00514     {
00515       if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
00516       {
00517         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00518         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00519
00520         /* Disable the DMA channel */
00521         __HAL_DMA_DISABLE(hqspi->hdma);
00522       }
00523       else
00524       {
00525         data_reg = &hqspi->Instance->DR;
00526         while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
00527         {
00528           if (hqspi->RxXferCount > 0)
00529           {
00530             /* Read the last data received in the FIFO until it is empty */
00531             *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00532             hqspi->RxXferCount--;
00533           }
00534           else
00535           {
00536             /* All data have been received for the transfer */
00537             break;
00538           }
00539         }
00540       }
00541
00542 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00543       /* Workaround - Extra data written in the FIFO at the end of a read transfer */
00544       HAL_QSPI_Abort_IT(hqspi);
00545 #endif
00546
00547       /* Change state of QSPI */
00548       hqspi->State = HAL_QSPI_STATE_READY;
00549
00550       /* RX Complete callback */
00551       HAL_QSPI_RxCpltCallback(hqspi);
00552     }
00553     else if(hqspi->State == HAL_QSPI_STATE_BUSY)
00554     {
00555       /* Change state of QSPI */
00556       hqspi->State = HAL_QSPI_STATE_READY;
00557
00558       /* Command Complete callback */
00559       HAL_QSPI_CmdCpltCallback(hqspi);
00560     }
00561     else if(hqspi->State == HAL_QSPI_STATE_ABORT)
00562     {
00563       /* Change state of QSPI */
00564       hqspi->State = HAL_QSPI_STATE_READY;
00565
00566       if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
00567       {
00568         /* Abort called by the user */
00569
00570         /* Abort Complete callback */
00571         HAL_QSPI_AbortCpltCallback(hqspi);
00572       }
00573       else
00574       {
00575         /* Abort due to an error (eg :  DMA error) */
00576
00577         /* Error callback */
00578         HAL_QSPI_ErrorCallback(hqspi);
00579       }
00580     }
00581   }
00582
00583   /* QSPI Status Match interrupt occurred ------------------------------------*/
00584   else if((flag & QSPI_FLAG_SM) && (itsource & QSPI_IT_SM))
00585   {
00586     /* Clear interrupt */
00587     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
00588
00589     /* Check if the automatic poll mode stop is activated */
00590     if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
00591     {
00592       /* Disable the QSPI Transfer Error and Status Match Interrupts */
00593       __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
00594
00595       /* Change state of QSPI */
00596       hqspi->State = HAL_QSPI_STATE_READY;
00597     }
00598
00599     /* Status match callback */
00600     HAL_QSPI_StatusMatchCallback(hqspi);
00601   }
00602
00603   /* QSPI Transfer Error interrupt occurred ----------------------------------*/
00604   else if((flag & QSPI_FLAG_TE) && (itsource & QSPI_IT_TE))
00605   {
00606     /* Clear interrupt */
00607     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
00608
00609     /* Disable all the QSPI Interrupts */
00610     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00611
00612     /* Set error code */
00613     hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
00614
00615     if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
00616     {
00617       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00618       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00619
00620       /* Disable the DMA channel */
00621       hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
00622       HAL_DMA_Abort_IT(hqspi->hdma);
00623     }
00624     else
00625     {
00626       /* Change state of QSPI */
00627       hqspi->State = HAL_QSPI_STATE_READY;
00628
00629       /* Error callback */
00630       HAL_QSPI_ErrorCallback(hqspi);
00631     }
00632   }
00633
00634   /* QSPI Timeout interrupt occurred -----------------------------------------*/
00635   else if((flag & QSPI_FLAG_TO) && (itsource & QSPI_IT_TO))
00636   {
00637     /* Clear interrupt */
00638     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
00639
00640     /* Timeout callback */
00641     HAL_QSPI_TimeOutCallback(hqspi);
00642   }
00643 }
00644
00645 /**
00646   * @brief Set the command configuration.
00647   * @param hqspi: QSPI handle
00648   * @param cmd : structure that contains the command configuration information
00649   * @param Timeout : Timeout duration
00650   * @note   This function is used only in Indirect Read or Write Modes
00651   * @retval HAL status
00652   */
00653 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
00654 {
00655   HAL_StatusTypeDef status = HAL_ERROR;
00656   uint32_t tickstart = HAL_GetTick();
00657
00658   /* Check the parameters */
00659   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00660   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00661   {
00662     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00663   }
00664
00665   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00666   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00667   {
00668     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00669   }
00670
00671   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00672   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00673   {
00674     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00675   }
00676
00677   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00678   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00679
00680   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00681   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00682   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00683
00684   /* Process locked */
00685   __HAL_LOCK(hqspi);
00686
00687   if(hqspi->State == HAL_QSPI_STATE_READY)
00688   {
00689     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00690
00691     /* Update QSPI state */
00692     hqspi->State = HAL_QSPI_STATE_BUSY;
00693
00694     /* Wait till BUSY flag reset */
00695     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
00696
00697     if (status == HAL_OK)
00698     {
00699       /* Call the configuration function */
00700       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00701
00702       if (cmd->DataMode == QSPI_DATA_NONE)
00703       {
00704         /* When there is no data phase, the transfer start as soon as the configuration is done
00705         so wait until TC flag is set to go back in idle state */
00706         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
00707
00708         if (status == HAL_OK)
00709         {
00710           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00711
00712           /* Update QSPI state */
00713           hqspi->State = HAL_QSPI_STATE_READY;
00714         }
00715       }
00716       else
00717       {
00718         /* Update QSPI state */
00719         hqspi->State = HAL_QSPI_STATE_READY;
00720       }
00721     }
00722   }
00723   else
00724   {
00725     status = HAL_BUSY;
00726   }
00727
00728   /* Process unlocked */
00729   __HAL_UNLOCK(hqspi);
00730
00731   /* Return function status */
00732   return status;
00733 }
00734
00735 /**
00736   * @brief Set the command configuration in interrupt mode.
00737   * @param hqspi: QSPI handle
00738   * @param cmd : structure that contains the command configuration information
00739   * @note   This function is used only in Indirect Read or Write Modes
00740   * @retval HAL status
00741   */
00742 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
00743 {
00744   HAL_StatusTypeDef status = HAL_ERROR;
00745   uint32_t tickstart = HAL_GetTick();
00746
00747   /* Check the parameters */
00748   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00749   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00750   {
00751     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00752   }
00753
00754   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00755   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00756   {
00757     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00758   }
00759
00760   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00761   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00762   {
00763     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00764   }
00765
00766   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00767   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00768
00769   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00770   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
00771   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00772
00773   /* Process locked */
00774   __HAL_LOCK(hqspi);
00775
00776   if(hqspi->State == HAL_QSPI_STATE_READY)
00777   {
00778     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00779
00780     /* Update QSPI state */
00781     hqspi->State = HAL_QSPI_STATE_BUSY;
00782
00783     /* Wait till BUSY flag reset */
00784     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
00785
00786     if (status == HAL_OK)
00787     {
00788       if (cmd->DataMode == QSPI_DATA_NONE)
00789       {
00790         /* Clear interrupt */
00791         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
00792       }
00793
00794       /* Call the configuration function */
00795       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00796
00797       if (cmd->DataMode == QSPI_DATA_NONE)
00798       {
00799         /* When there is no data phase, the transfer start as soon as the configuration is done
00800         so activate TC and TE interrupts */
00801         /* Process unlocked */
00802         __HAL_UNLOCK(hqspi);
00803
00804         /* Enable the QSPI Transfer Error Interrupt */
00805         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
00806       }
00807       else
00808       {
00809         /* Update QSPI state */
00810         hqspi->State = HAL_QSPI_STATE_READY;
00811
00812         /* Process unlocked */
00813         __HAL_UNLOCK(hqspi);
00814       }
00815     }
00816     else
00817     {
00818       /* Process unlocked */
00819       __HAL_UNLOCK(hqspi);
00820     }
00821   }
00822   else
00823   {
00824     status = HAL_BUSY;
00825
00826     /* Process unlocked */
00827     __HAL_UNLOCK(hqspi);
00828   }
00829
00830   /* Return function status */
00831   return status;
00832 }
00833
00834 /**
00835   * @brief Transmit an amount of data in blocking mode.
00836   * @param hqspi: QSPI handle
00837   * @param pData: pointer to data buffer
00838   * @param Timeout : Timeout duration
00839   * @note   This function is used only in Indirect Write Mode
00840   * @retval HAL status
00841   */
00842 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00843 {
00844   HAL_StatusTypeDef status = HAL_OK;
00845   uint32_t tickstart = HAL_GetTick();
00846   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00847
00848   /* Process locked */
00849   __HAL_LOCK(hqspi);
00850
00851   if(hqspi->State == HAL_QSPI_STATE_READY)
00852   {
00853     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00854
00855     if(pData != NULL )
00856     {
00857       /* Update state */
00858       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
00859
00860       /* Configure counters and size of the handle */
00861       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
00862       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
00863       hqspi->pTxBuffPtr = pData;
00864
00865       /* Configure QSPI: CCR register with functional as indirect write */
00866       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00867
00868       while(hqspi->TxXferCount > 0)
00869       {
00870         /* Wait until FT flag is set to send data */
00871         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
00872
00873         if (status != HAL_OK)
00874         {
00875           break;
00876         }
00877
00878         *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
00879         hqspi->TxXferCount--;
00880       }
00881
00882       if (status == HAL_OK)
00883       {
00884         /* Wait until TC flag is set to go back in idle state */
00885         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
00886
00887         if (status == HAL_OK)
00888         {
00889           /* Clear Transfer Complete bit */
00890           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00891
00892 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00893           /* Clear Busy bit */
00894           status = HAL_QSPI_Abort(hqspi);
00895 #endif
00896         }
00897       }
00898
00899       /* Update QSPI state */
00900       hqspi->State = HAL_QSPI_STATE_READY;
00901     }
00902     else
00903     {
00904       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
00905       status = HAL_ERROR;
00906     }
00907   }
00908   else
00909   {
00910     status = HAL_BUSY;
00911   }
00912
00913   /* Process unlocked */
00914   __HAL_UNLOCK(hqspi);
00915
00916   return status;
00917 }
00918
00919
00920 /**
00921   * @brief Receive an amount of data in blocking mode.
00922   * @param hqspi: QSPI handle
00923   * @param pData: pointer to data buffer
00924   * @param Timeout : Timeout duration
00925   * @note   This function is used only in Indirect Read Mode
00926   * @retval HAL status
00927   */
00928 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00929 {
00930   HAL_StatusTypeDef status = HAL_OK;
00931   uint32_t tickstart = HAL_GetTick();
00932   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
00933   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00934
00935   /* Process locked */
00936   __HAL_LOCK(hqspi);
00937
00938   if(hqspi->State == HAL_QSPI_STATE_READY)
00939   {
00940     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00941
00942     if(pData != NULL )
00943     {
00944       /* Update state */
00945       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
00946
00947       /* Configure counters and size of the handle */
00948       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
00949       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
00950       hqspi->pRxBuffPtr = pData;
00951
00952       /* Configure QSPI: CCR register with functional as indirect read */
00953       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
00954
00955       /* Start the transfer by re-writing the address in AR register */
00956       WRITE_REG(hqspi->Instance->AR, addr_reg);
00957
00958       while(hqspi->RxXferCount > 0)
00959       {
00960         /* Wait until FT or TC flag is set to read received data */
00961         status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
00962
00963         if  (status != HAL_OK)
00964         {
00965           break;
00966         }
00967
00968         *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
00969         hqspi->RxXferCount--;
00970       }
00971
00972       if (status == HAL_OK)
00973       {
00974         /* Wait until TC flag is set to go back in idle state */
00975         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
00976
00977         if  (status == HAL_OK)
00978         {
00979           /* Clear Transfer Complete bit */
00980           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00981
00982 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00983           /* Workaround - Extra data written in the FIFO at the end of a read transfer */
00984           status = HAL_QSPI_Abort(hqspi);
00985 #endif
00986         }
00987       }
00988
00989       /* Update QSPI state */
00990       hqspi->State = HAL_QSPI_STATE_READY;
00991     }
00992     else
00993     {
00994       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
00995       status = HAL_ERROR;
00996     }
00997   }
00998   else
00999   {
01000     status = HAL_BUSY;
01001   }
01002
01003   /* Process unlocked */
01004   __HAL_UNLOCK(hqspi);
01005
01006   return status;
01007 }
01008
01009 /**
01010   * @brief  Send an amount of data in non-blocking mode with interrupt.
01011   * @param  hqspi: QSPI handle
01012   * @param  pData: pointer to data buffer
01013   * @note   This function is used only in Indirect Write Mode
01014   * @retval HAL status
01015   */
01016 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01017 {
01018   HAL_StatusTypeDef status = HAL_OK;
01019
01020   /* Process locked */
01021   __HAL_LOCK(hqspi);
01022
01023   if(hqspi->State == HAL_QSPI_STATE_READY)
01024   {
01025     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01026
01027     if(pData != NULL )
01028     {
01029       /* Update state */
01030       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01031
01032       /* Configure counters and size of the handle */
01033       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
01034       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
01035       hqspi->pTxBuffPtr = pData;
01036
01037       /* Configure QSPI: CCR register with functional as indirect write */
01038       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01039
01040       /* Clear interrupt */
01041       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
01042
01043       /* Process unlocked */
01044       __HAL_UNLOCK(hqspi);
01045
01046       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01047       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01048     }
01049     else
01050     {
01051       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01052       status = HAL_ERROR;
01053
01054       /* Process unlocked */
01055       __HAL_UNLOCK(hqspi);
01056     }
01057   }
01058   else
01059   {
01060     status = HAL_BUSY;
01061
01062     /* Process unlocked */
01063     __HAL_UNLOCK(hqspi);
01064   }
01065
01066   return status;
01067 }
01068
01069 /**
01070   * @brief  Receive an amount of data in non-blocking mode with interrupt.
01071   * @param  hqspi: QSPI handle
01072   * @param  pData: pointer to data buffer
01073   * @note   This function is used only in Indirect Read Mode
01074   * @retval HAL status
01075   */
01076 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01077 {
01078   HAL_StatusTypeDef status = HAL_OK;
01079   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01080
01081   /* Process locked */
01082   __HAL_LOCK(hqspi);
01083
01084   if(hqspi->State == HAL_QSPI_STATE_READY)
01085   {
01086     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01087
01088     if(pData != NULL )
01089     {
01090       /* Update state */
01091       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01092
01093       /* Configure counters and size of the handle */
01094       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
01095       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
01096       hqspi->pRxBuffPtr = pData;
01097
01098       /* Configure QSPI: CCR register with functional as indirect read */
01099       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01100
01101       /* Start the transfer by re-writing the address in AR register */
01102       WRITE_REG(hqspi->Instance->AR, addr_reg);
01103
01104       /* Clear interrupt */
01105       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
01106
01107       /* Process unlocked */
01108       __HAL_UNLOCK(hqspi);
01109
01110       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01111       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01112     }
01113     else
01114     {
01115       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01116       status = HAL_ERROR;
01117
01118       /* Process unlocked */
01119       __HAL_UNLOCK(hqspi);
01120     }
01121   }
01122   else
01123   {
01124     status = HAL_BUSY;
01125
01126     /* Process unlocked */
01127     __HAL_UNLOCK(hqspi);
01128   }
01129
01130   return status;
01131 }
01132
01133 /**
01134   * @brief  Send an amount of data in non-blocking mode with DMA.
01135   * @param  hqspi: QSPI handle
01136   * @param  pData: pointer to data buffer
01137   * @note   This function is used only in Indirect Write Mode
01138   * @note   If DMA peripheral access is configured as halfword, the number
01139   *         of data and the fifo threshold should be aligned on halfword
01140   * @note   If DMA peripheral access is configured as word, the number
01141   *         of data and the fifo threshold should be aligned on word
01142   * @retval HAL status
01143   */
01144 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01145 {
01146   HAL_StatusTypeDef status = HAL_OK;
01147   uint32_t *tmp;
01148   uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
01149
01150   /* Process locked */
01151   __HAL_LOCK(hqspi);
01152
01153   if(hqspi->State == HAL_QSPI_STATE_READY)
01154   {
01155     /* Clear the error code */
01156     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01157
01158     if(pData != NULL )
01159     {
01160       /* Configure counters of the handle */
01161       if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
01162       {
01163         hqspi->TxXferCount = data_size;
01164       }
01165       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
01166       {
01167         if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
01168         {
01169           /* The number of data or the fifo threshold is not aligned on halfword
01170           => no transfer possible with DMA peripheral access configured as halfword */
01171           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01172           status = HAL_ERROR;
01173
01174           /* Process unlocked */
01175           __HAL_UNLOCK(hqspi);
01176         }
01177         else
01178         {
01179           hqspi->TxXferCount = (data_size >> 1);
01180         }
01181       }
01182       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
01183       {
01184         if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
01185         {
01186           /* The number of data or the fifo threshold is not aligned on word
01187           => no transfer possible with DMA peripheral access configured as word */
01188           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01189           status = HAL_ERROR;
01190
01191           /* Process unlocked */
01192           __HAL_UNLOCK(hqspi);
01193         }
01194         else
01195         {
01196           hqspi->TxXferCount = (data_size >> 2);
01197         }
01198       }
01199
01200       if (status == HAL_OK)
01201       {
01202         /* Update state */
01203         hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01204
01205         /* Clear interrupt */
01206         __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
01207
01208         /* Configure size and pointer of the handle */
01209         hqspi->TxXferSize = hqspi->TxXferCount;
01210         hqspi->pTxBuffPtr = pData;
01211
01212         /* Configure QSPI: CCR register with functional mode as indirect write */
01213         MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01214
01215         /* Set the QSPI DMA transfer complete callback */
01216         hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
01217
01218         /* Set the QSPI DMA Half transfer complete callback */
01219         hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
01220
01221         /* Set the DMA error callback */
01222         hqspi->hdma->XferErrorCallback = QSPI_DMAError;
01223
01224         /* Clear the DMA abort callback */
01225         hqspi->hdma->XferAbortCallback = NULL;
01226
01227         /* Configure the direction of the DMA */
01228         hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
01229         MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
01230
01231         /* Enable the QSPI transmit DMA Channel */
01232         tmp = (uint32_t*)&pData;
01233         HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
01234
01235         /* Process unlocked */
01236         __HAL_UNLOCK(hqspi);
01237
01238         /* Enable the QSPI transfer error Interrupt */
01239         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
01240
01241         /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
01242         SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01243       }
01244     }
01245     else
01246     {
01247       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01248       status = HAL_ERROR;
01249
01250       /* Process unlocked */
01251       __HAL_UNLOCK(hqspi);
01252     }
01253   }
01254   else
01255   {
01256     status = HAL_BUSY;
01257
01258     /* Process unlocked */
01259     __HAL_UNLOCK(hqspi);
01260   }
01261
01262   return status;
01263 }
01264
01265 /**
01266   * @brief  Receive an amount of data in non-blocking mode with DMA.
01267   * @param  hqspi: QSPI handle
01268   * @param  pData: pointer to data buffer.
01269   * @note   This function is used only in Indirect Read Mode
01270   * @note   If DMA peripheral access is configured as halfword, the number
01271   *         of data and the fifo threshold should be aligned on halfword
01272   * @note   If DMA peripheral access is configured as word, the number
01273   *         of data and the fifo threshold should be aligned on word
01274   * @retval HAL status
01275   */
01276 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01277 {
01278   HAL_StatusTypeDef status = HAL_OK;
01279   uint32_t *tmp;
01280   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01281   uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
01282
01283   /* Process locked */
01284   __HAL_LOCK(hqspi);
01285
01286   if(hqspi->State == HAL_QSPI_STATE_READY)
01287   {
01288     /* Clear the error code */
01289     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01290
01291     if(pData != NULL)
01292     {
01293       /* Configure counters of the handle */
01294       if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
01295       {
01296         hqspi->RxXferCount = data_size;
01297       }
01298       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
01299       {
01300         if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
01301         {
01302           /* The number of data or the fifo threshold is not aligned on halfword
01303              => no transfer possible with DMA peripheral access configured as halfword */
01304           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01305           status = HAL_ERROR;
01306
01307           /* Process unlocked */
01308           __HAL_UNLOCK(hqspi);
01309         }
01310         else
01311         {
01312           hqspi->RxXferCount = (data_size >> 1);
01313         }
01314       }
01315       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
01316       {
01317         if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
01318         {
01319           /* The number of data or the fifo threshold is not aligned on word
01320              => no transfer possible with DMA peripheral access configured as word */
01321           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01322           status = HAL_ERROR;
01323
01324           /* Process unlocked */
01325           __HAL_UNLOCK(hqspi);
01326         }
01327         else
01328         {
01329           hqspi->RxXferCount = (data_size >> 2);
01330         }
01331       }
01332
01333       if (status == HAL_OK)
01334       {
01335         /* Update state */
01336         hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01337
01338         /* Clear interrupt */
01339         __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
01340
01341         /* Configure size and pointer of the handle */
01342         hqspi->RxXferSize = hqspi->RxXferCount;
01343         hqspi->pRxBuffPtr = pData;
01344
01345         /* Set the QSPI DMA transfer complete callback */
01346         hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
01347
01348         /* Set the QSPI DMA Half transfer complete callback */
01349         hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
01350
01351         /* Set the DMA error callback */
01352         hqspi->hdma->XferErrorCallback = QSPI_DMAError;
01353
01354         /* Clear the DMA abort callback */
01355         hqspi->hdma->XferAbortCallback = NULL;
01356
01357         /* Configure the direction of the DMA */
01358         hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
01359         MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
01360
01361         /* Enable the DMA Channel */
01362         tmp = (uint32_t*)&pData;
01363         HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
01364
01365         /* Configure QSPI: CCR register with functional as indirect read */
01366         MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01367
01368         /* Start the transfer by re-writing the address in AR register */
01369         WRITE_REG(hqspi->Instance->AR, addr_reg);
01370
01371         /* Process unlocked */
01372         __HAL_UNLOCK(hqspi);
01373
01374         /* Enable the QSPI transfer error Interrupt */
01375         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
01376
01377         /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
01378         SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01379       }
01380     }
01381     else
01382     {
01383       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01384       status = HAL_ERROR;
01385
01386       /* Process unlocked */
01387       __HAL_UNLOCK(hqspi);
01388     }
01389   }
01390   else
01391   {
01392     status = HAL_BUSY;
01393
01394     /* Process unlocked */
01395     __HAL_UNLOCK(hqspi);
01396   }
01397
01398   return status;
01399 }
01400
01401 /**
01402   * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
01403   * @param  hqspi: QSPI handle
01404   * @param  cmd: structure that contains the command configuration information.
01405   * @param  cfg: structure that contains the polling configuration information.
01406   * @param  Timeout : Timeout duration
01407   * @note   This function is used only in Automatic Polling Mode
01408   * @retval HAL status
01409   */
01410 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
01411 {
01412   HAL_StatusTypeDef status = HAL_ERROR;
01413   uint32_t tickstart = HAL_GetTick();
01414
01415   /* Check the parameters */
01416   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01417   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01418   {
01419     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01420   }
01421
01422   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01423   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01424   {
01425     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01426   }
01427
01428   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01429   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01430   {
01431     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01432   }
01433
01434   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01435   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01436
01437   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01438   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01439   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01440
01441   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01442   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01443   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01444
01445   /* Process locked */
01446   __HAL_LOCK(hqspi);
01447
01448   if(hqspi->State == HAL_QSPI_STATE_READY)
01449   {
01450     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01451
01452     /* Update state */
01453     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01454
01455     /* Wait till BUSY flag reset */
01456     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
01457
01458     if (status == HAL_OK)
01459     {
01460       /* Configure QSPI: PSMAR register with the status match value */
01461       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01462
01463       /* Configure QSPI: PSMKR register with the status mask value */
01464       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01465
01466       /* Configure QSPI: PIR register with the interval value */
01467       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01468
01469       /* Configure QSPI: CR register with Match mode and Automatic stop enabled
01470       (otherwise there will be an infinite loop in blocking mode) */
01471       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01472                (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
01473
01474       /* Call the configuration function */
01475       cmd->NbData = cfg->StatusBytesSize;
01476       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01477
01478       /* Wait until SM flag is set to go back in idle state */
01479       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
01480
01481       if (status == HAL_OK)
01482       {
01483         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
01484
01485         /* Update state */
01486         hqspi->State = HAL_QSPI_STATE_READY;
01487       }
01488     }
01489   }
01490   else
01491   {
01492     status = HAL_BUSY;
01493   }
01494
01495   /* Process unlocked */
01496   __HAL_UNLOCK(hqspi);
01497
01498   /* Return function status */
01499   return status;
01500 }
01501
01502 /**
01503   * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
01504   * @param  hqspi: QSPI handle
01505   * @param  cmd: structure that contains the command configuration information.
01506   * @param  cfg: structure that contains the polling configuration information.
01507   * @note   This function is used only in Automatic Polling Mode
01508   * @retval HAL status
01509   */
01510 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
01511 {
01512   HAL_StatusTypeDef status = HAL_ERROR;
01513   uint32_t tickstart = HAL_GetTick();
01514
01515   /* Check the parameters */
01516   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01517   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01518   {
01519     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01520   }
01521
01522   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01523   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01524   {
01525     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01526   }
01527
01528   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01529   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01530   {
01531     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01532   }
01533
01534   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01535   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01536
01537   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01538   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01539   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01540
01541   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01542   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01543   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01544   assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
01545
01546   /* Process locked */
01547   __HAL_LOCK(hqspi);
01548
01549   if(hqspi->State == HAL_QSPI_STATE_READY)
01550   {
01551     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01552
01553     /* Update state */
01554     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01555
01556     /* Wait till BUSY flag reset */
01557     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01558
01559     if (status == HAL_OK)
01560     {
01561       /* Configure QSPI: PSMAR register with the status match value */
01562       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01563
01564       /* Configure QSPI: PSMKR register with the status mask value */
01565       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01566
01567       /* Configure QSPI: PIR register with the interval value */
01568       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01569
01570       /* Configure QSPI: CR register with Match mode and Automatic stop mode */
01571       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01572                (cfg->MatchMode | cfg->AutomaticStop));
01573
01574       /* Clear interrupt */
01575       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
01576
01577       /* Call the configuration function */
01578       cmd->NbData = cfg->StatusBytesSize;
01579       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01580
01581       /* Process unlocked */
01582       __HAL_UNLOCK(hqspi);
01583
01584       /* Enable the QSPI Transfer Error and status match Interrupt */
01585       __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
01586
01587     }
01588     else
01589     {
01590       /* Process unlocked */
01591       __HAL_UNLOCK(hqspi);
01592     }
01593   }
01594   else
01595   {
01596     status = HAL_BUSY;
01597
01598     /* Process unlocked */
01599     __HAL_UNLOCK(hqspi);
01600   }
01601
01602   /* Return function status */
01603   return status;
01604 }
01605
01606 /**
01607   * @brief  Configure the Memory Mapped mode.
01608   * @param  hqspi: QSPI handle
01609   * @param  cmd: structure that contains the command configuration information.
01610   * @param  cfg: structure that contains the memory mapped configuration information.
01611   * @note   This function is used only in Memory mapped Mode
01612   * @retval HAL status
01613   */
01614 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
01615 {
01616   HAL_StatusTypeDef status = HAL_ERROR;
01617   uint32_t tickstart = HAL_GetTick();
01618
01619   /* Check the parameters */
01620   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01621   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01622   {
01623   assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01624   }
01625
01626   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01627   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01628   {
01629     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01630   }
01631
01632   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01633   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01634   {
01635     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01636   }
01637
01638   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01639   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01640
01641   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01642   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
01643   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01644
01645   assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
01646
01647   /* Process locked */
01648   __HAL_LOCK(hqspi);
01649
01650   if(hqspi->State == HAL_QSPI_STATE_READY)
01651   {
01652     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01653
01654     /* Update state */
01655     hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
01656
01657     /* Wait till BUSY flag reset */
01658     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01659
01660     if (status == HAL_OK)
01661     {
01662       /* Configure QSPI: CR register with timeout counter enable */
01663       MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
01664
01665       if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
01666       {
01667         assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
01668
01669         /* Configure QSPI: LPTR register with the low-power timeout value */
01670         WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
01671
01672         /* Clear interrupt */
01673         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
01674
01675         /* Enable the QSPI TimeOut Interrupt */
01676         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
01677       }
01678
01679       /* Call the configuration function */
01680       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
01681     }
01682   }
01683   else
01684   {
01685     status = HAL_BUSY;
01686   }
01687
01688   /* Process unlocked */
01689   __HAL_UNLOCK(hqspi);
01690
01691   /* Return function status */
01692   return status;
01693 }
01694
01695 /**
01696   * @brief  Transfer Error callback.
01697   * @param  hqspi: QSPI handle
01698   * @retval None
01699   */
01700 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
01701 {
01702   /* Prevent unused argument(s) compilation warning */
01703   UNUSED(hqspi);
01704
01705   /* NOTE : This function should not be modified, when the callback is needed,
01706             the HAL_QSPI_ErrorCallback could be implemented in the user file
01707    */
01708 }
01709
01710 /**
01711   * @brief  Abort completed callback.
01712   * @param  hqspi: QSPI handle
01713   * @retval None
01714   */
01715 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
01716 {
01717   /* Prevent unused argument(s) compilation warning */
01718   UNUSED(hqspi);
01719
01720   /* NOTE: This function should not be modified, when the callback is needed,
01721            the HAL_QSPI_AbortCpltCallback could be implemented in the user file
01722    */
01723 }
01724
01725 /**
01726   * @brief  Command completed callback.
01727   * @param  hqspi: QSPI handle
01728   * @retval None
01729   */
01730 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
01731 {
01732   /* Prevent unused argument(s) compilation warning */
01733   UNUSED(hqspi);
01734
01735   /* NOTE: This function should not be modified, when the callback is needed,
01736            the HAL_QSPI_CmdCpltCallback could be implemented in the user file
01737    */
01738 }
01739
01740 /**
01741   * @brief  Rx Transfer completed callback.
01742   * @param  hqspi: QSPI handle
01743   * @retval None
01744   */
01745 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
01746 {
01747   /* Prevent unused argument(s) compilation warning */
01748   UNUSED(hqspi);
01749
01750   /* NOTE: This function should not be modified, when the callback is needed,
01751            the HAL_QSPI_RxCpltCallback could be implemented in the user file
01752    */
01753 }
01754
01755 /**
01756   * @brief  Tx Transfer completed callback.
01757   * @param  hqspi: QSPI handle
01758   * @retval None
01759   */
01760  __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
01761 {
01762   /* Prevent unused argument(s) compilation warning */
01763   UNUSED(hqspi);
01764
01765   /* NOTE: This function should not be modified, when the callback is needed,
01766            the HAL_QSPI_TxCpltCallback could be implemented in the user file
01767    */
01768 }
01769
01770 /**
01771   * @brief  Rx Half Transfer completed callback.
01772   * @param  hqspi: QSPI handle
01773   * @retval None
01774   */
01775 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01776 {
01777   /* Prevent unused argument(s) compilation warning */
01778   UNUSED(hqspi);
01779
01780   /* NOTE: This function should not be modified, when the callback is needed,
01781            the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
01782    */
01783 }
01784
01785 /**
01786   * @brief  Tx Half Transfer completed callback.
01787   * @param  hqspi: QSPI handle
01788   * @retval None
01789   */
01790 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01791 {
01792   /* Prevent unused argument(s) compilation warning */
01793   UNUSED(hqspi);
01794
01795   /* NOTE: This function should not be modified, when the callback is needed,
01796            the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
01797    */
01798 }
01799
01800 /**
01801   * @brief  FIFO Threshold callback.
01802   * @param  hqspi: QSPI handle
01803   * @retval None
01804   */
01805 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
01806 {
01807   /* Prevent unused argument(s) compilation warning */
01808   UNUSED(hqspi);
01809
01810   /* NOTE : This function should not be modified, when the callback is needed,
01811             the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
01812    */
01813 }
01814
01815 /**
01816   * @brief  Status Match callback.
01817   * @param  hqspi: QSPI handle
01818   * @retval None
01819   */
01820 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
01821 {
01822   /* Prevent unused argument(s) compilation warning */
01823   UNUSED(hqspi);
01824
01825   /* NOTE : This function should not be modified, when the callback is needed,
01826             the HAL_QSPI_StatusMatchCallback could be implemented in the user file
01827    */
01828 }
01829
01830 /**
01831   * @brief  Timeout callback.
01832   * @param  hqspi: QSPI handle
01833   * @retval None
01834   */
01835 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
01836 {
01837   /* Prevent unused argument(s) compilation warning */
01838   UNUSED(hqspi);
01839
01840   /* NOTE : This function should not be modified, when the callback is needed,
01841             the HAL_QSPI_TimeOutCallback could be implemented in the user file
01842    */
01843 }
01844
01845 /**
01846   * @}
01847   */
01848
01849 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
01850   *  @brief   QSPI control and State functions
01851   *
01852 @verbatim
01853  ===============================================================================
01854                   ##### Peripheral Control and State functions #####
01855  ===============================================================================
01856     [..]
01857     This subsection provides a set of functions allowing to :
01858       (+) Check in run-time the state of the driver.
01859       (+) Check the error code set during last operation.
01860       (+) Abort any operation.
01861
01862
01863 @endverbatim
01864   * @{
01865   */
01866
01867 /**
01868   * @brief  Return the QSPI handle state.
01869   * @param  hqspi: QSPI handle
01870   * @retval HAL state
01871   */
01872 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
01873 {
01874   /* Return QSPI handle state */
01875   return hqspi->State;
01876 }
01877
01878 /**
01879 * @brief  Return the QSPI error code.
01880 * @param  hqspi: QSPI handle
01881 * @retval QSPI Error Code
01882 */
01883 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
01884 {
01885   return hqspi->ErrorCode;
01886 }
01887
01888 /**
01889 * @brief  Abort the current transmission.
01890 * @param  hqspi: QSPI handle
01891 * @retval HAL status
01892 */
01893 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
01894 {
01895   HAL_StatusTypeDef status = HAL_OK;
01896   uint32_t tickstart = HAL_GetTick();
01897
01898   /* Check if the state is in one of the busy states */
01899   if ((hqspi->State & 0x2) != 0)
01900   {
01901     /* Process unlocked */
01902     __HAL_UNLOCK(hqspi);
01903
01904     if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
01905     {
01906       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
01907       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01908
01909       /* Abort DMA channel */
01910       status = HAL_DMA_Abort(hqspi->hdma);
01911       if(status != HAL_OK)
01912       {
01913         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
01914       }
01915     }
01916
01917     /* Configure QSPI: CR register with Abort request */
01918     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
01919
01920     /* Wait until TC flag is set to go back in idle state */
01921     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
01922
01923     if(status == HAL_OK)
01924     {
01925       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01926
01927       /* Wait until BUSY flag is reset */
01928       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01929     }
01930
01931     if (status == HAL_OK)
01932     {
01933       /* Update state */
01934       hqspi->State = HAL_QSPI_STATE_READY;
01935     }
01936   }
01937
01938   return status;
01939 }
01940
01941 /**
01942 * @brief  Abort the current transmission (non-blocking function)
01943 * @param  hqspi: QSPI handle
01944 * @retval HAL status
01945 */
01946 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
01947 {
01948   HAL_StatusTypeDef status = HAL_OK;
01949
01950   /* Check if the state is in one of the busy states */
01951   if ((hqspi->State & 0x2) != 0)
01952   {
01953     /* Process unlocked */
01954     __HAL_UNLOCK(hqspi);
01955
01956     /* Update QSPI state */
01957     hqspi->State = HAL_QSPI_STATE_ABORT;
01958
01959     /* Disable all interrupts */
01960     __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
01961
01962     if (hqspi->Instance->CR & QUADSPI_CR_DMAEN)
01963     {
01964       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
01965       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01966
01967       /* Abort DMA channel */
01968       hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
01969       HAL_DMA_Abort_IT(hqspi->hdma);
01970     }
01971     else
01972     {
01973       /* Clear interrupt */
01974       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01975
01976       /* Enable the QSPI Transfer Complete Interrupt */
01977       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
01978
01979       /* Configure QSPI: CR register with Abort request */
01980       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
01981     }
01982   }
01983   return status;
01984 }
01985
01986 /** @brief Set QSPI timeout.
01987   * @param  hqspi: QSPI handle.
01988   * @param  Timeout: Timeout for the QSPI memory access.
01989   * @retval None
01990   */
01991 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
01992 {
01993   hqspi->Timeout = Timeout;
01994 }
01995
01996 /** @brief Set QSPI Fifo threshold.
01997   * @param  hqspi: QSPI handle.
01998   * @param  Threshold: Threshold of the Fifo (value between 1 and 16).
01999   * @retval HAL status
02000   */
02001 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
02002 {
02003   HAL_StatusTypeDef status = HAL_OK;
02004
02005   /* Process locked */
02006   __HAL_LOCK(hqspi);
02007
02008   if(hqspi->State == HAL_QSPI_STATE_READY)
02009   {
02010     /* Synchronize init structure with new FIFO threshold value */
02011     hqspi->Init.FifoThreshold = Threshold;
02012
02013     /* Configure QSPI FIFO Threshold */
02014     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
02015                ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
02016   }
02017   else
02018   {
02019     status = HAL_BUSY;
02020   }
02021
02022   /* Process unlocked */
02023   __HAL_UNLOCK(hqspi);
02024
02025   /* Return function status */
02026   return status;
02027 }
02028
02029 /** @brief Get QSPI Fifo threshold.
02030   * @param  hqspi: QSPI handle.
02031   * @retval Fifo threshold (value between 1 and 16)
02032   */
02033 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
02034 {
02035   return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
02036 }
02037
02038 /**
02039   * @}
02040   */
02041
02042 /**
02043   * @brief  DMA QSPI receive process complete callback.
02044   * @param  hdma: DMA handle
02045   * @retval None
02046   */
02047 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
02048 {
02049   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02050   hqspi->RxXferCount = 0;
02051
02052   /* Enable the QSPI transfer complete Interrupt */
02053   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02054 }
02055
02056 /**
02057   * @brief  DMA QSPI transmit process complete callback.
02058   * @param  hdma: DMA handle
02059   * @retval None
02060   */
02061 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
02062 {
02063   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02064   hqspi->TxXferCount = 0;
02065
02066   /* Enable the QSPI transfer complete Interrupt */
02067   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02068 }
02069
02070 /**
02071   * @brief  DMA QSPI receive process half complete callback.
02072   * @param  hdma : DMA handle
02073   * @retval None
02074   */
02075 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02076 {
02077   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02078
02079   HAL_QSPI_RxHalfCpltCallback(hqspi);
02080 }
02081
02082 /**
02083   * @brief  DMA QSPI transmit process half complete callback.
02084   * @param  hdma : DMA handle
02085   * @retval None
02086   */
02087 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02088 {
02089   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02090
02091   HAL_QSPI_TxHalfCpltCallback(hqspi);
02092 }
02093
02094 /**
02095   * @brief  DMA QSPI communication error callback.
02096   * @param  hdma: DMA handle
02097   * @retval None
02098   */
02099 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
02100 {
02101   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02102
02103   hqspi->RxXferCount = 0;
02104   hqspi->TxXferCount = 0;
02105   hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
02106
02107   /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
02108   CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
02109
02110   /* Abort the QSPI */
02111   HAL_QSPI_Abort_IT(hqspi);
02112 }
02113
02114 /**
02115   * @brief  DMA QSPI abort complete callback.
02116   * @param  hdma: DMA handle
02117   * @retval None
02118   */
02119 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
02120 {
02121   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02122
02123   hqspi->RxXferCount = 0;
02124   hqspi->TxXferCount = 0;
02125
02126   if(hqspi->State == HAL_QSPI_STATE_ABORT)
02127   {
02128     /* DMA Abort called by QSPI abort */
02129     /* Clear interrupt */
02130     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
02131
02132     /* Enable the QSPI Transfer Complete Interrupt */
02133     __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02134
02135     /* Configure QSPI: CR register with Abort request */
02136     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02137   }
02138   else
02139   {
02140     /* DMA Abort called due to a transfer error interrupt */
02141     /* Change state of QSPI */
02142     hqspi->State = HAL_QSPI_STATE_READY;
02143
02144     /* Error callback */
02145     HAL_QSPI_ErrorCallback(hqspi);
02146   }
02147 }
02148 /**
02149   * @brief  Wait for a flag state until timeout.
02150   * @param  hqspi: QSPI handle
02151   * @param  Flag: Flag checked
02152   * @param  State: Value of the flag expected
02153   * @param  Timeout: Duration of the timeout
02154   * @param  Tickstart Tick start value
02155   * @retval HAL status
02156   */
02157 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
02158                                                         FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
02159 {
02160   /* Wait until flag is in expected state */
02161   while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
02162   {
02163     /* Check for the Timeout */
02164     if (Timeout != HAL_MAX_DELAY)
02165     {
02166       if((Timeout == 0) || ((HAL_GetTick() - Tickstart) > Timeout))
02167       {
02168         hqspi->State     = HAL_QSPI_STATE_ERROR;
02169         hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
02170
02171         return HAL_ERROR;
02172       }
02173     }
02174   }
02175   return HAL_OK;
02176 }
02177
02178 /**
02179   * @brief  Configure the communication registers.
02180   * @param  hqspi: QSPI handle
02181   * @param  cmd: structure that contains the command configuration information
02182   * @param  FunctionalMode: functional mode to configured
02183   *           This parameter can be one of the following values:
02184   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
02185   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
02186   *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
02187   *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
02188   * @retval None
02189   */
02190 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
02191 {
02192   assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
02193
02194   if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
02195   {
02196     /* Configure QSPI: DLR register with the number of data to read or write */
02197     WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
02198   }
02199
02200   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
02201   {
02202     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
02203     {
02204       /* Configure QSPI: ABR register with alternate bytes value */
02205       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
02206
02207       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02208       {
02209         /*---- Command with instruction, address and alternate bytes ----*/
02210         /* Configure QSPI: CCR register with all communications parameters */
02211         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02212                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02213                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02214                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
02215                                          cmd->Instruction | FunctionalMode));
02216
02217         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02218         {
02219           /* Configure QSPI: AR register with address value */
02220           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02221         }
02222       }
02223       else
02224       {
02225         /*---- Command with instruction and alternate bytes ----*/
02226         /* Configure QSPI: CCR register with all communications parameters */
02227         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02228                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02229                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02230                                          cmd->AddressMode | cmd->InstructionMode |
02231                                          cmd->Instruction | FunctionalMode));
02232       }
02233     }
02234     else
02235     {
02236       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02237       {
02238         /*---- Command with instruction and address ----*/
02239         /* Configure QSPI: CCR register with all communications parameters */
02240         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02241                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02242                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
02243                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
02244
02245         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02246         {
02247           /* Configure QSPI: AR register with address value */
02248           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02249         }
02250       }
02251       else
02252       {
02253         /*---- Command with only instruction ----*/
02254         /* Configure QSPI: CCR register with all communications parameters */
02255         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02256                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02257                                          cmd->AlternateByteMode | cmd->AddressMode |
02258                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
02259       }
02260     }
02261   }
02262   else
02263   {
02264     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
02265     {
02266       /* Configure QSPI: ABR register with alternate bytes value */
02267       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
02268
02269       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02270       {
02271         /*---- Command with address and alternate bytes ----*/
02272         /* Configure QSPI: CCR register with all communications parameters */
02273         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02274                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02275                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02276                                          cmd->AddressSize | cmd->AddressMode |
02277                                          cmd->InstructionMode | FunctionalMode));
02278
02279         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02280         {
02281           /* Configure QSPI: AR register with address value */
02282           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02283         }
02284       }
02285       else
02286       {
02287         /*---- Command with only alternate bytes ----*/
02288         /* Configure QSPI: CCR register with all communications parameters */
02289         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02290                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02291                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02292                                          cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
02293       }
02294     }
02295     else
02296     {
02297       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02298       {
02299         /*---- Command with only address ----*/
02300         /* Configure QSPI: CCR register with all communications parameters */
02301         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02302                                          cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02303                                          cmd->AlternateByteMode | cmd->AddressSize |
02304                                          cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
02305
02306         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02307         {
02308           /* Configure QSPI: AR register with address value */
02309           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02310         }
02311       }
02312       else
02313       {
02314         /*---- Command with only data phase ----*/
02315         if (cmd->DataMode != QSPI_DATA_NONE)
02316         {
02317           /* Configure QSPI: CCR register with all communications parameters */
02318           WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
02319                                            cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) |
02320                                            cmd->AlternateByteMode | cmd->AddressMode |
02321                                            cmd->InstructionMode | FunctionalMode));
02322         }
02323       }
02324     }
02325   }
02326 }
02327
02328 /**
02329   * @}
02330   */
02331
02332 #endif /* HAL_QSPI_MODULE_ENABLED */
02333 /**
02334   * @}
02335   */
02336
02337 /**
02338   * @}
02339   */
02340
02341 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_qspi.h Source File

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stm32l4xx_hal_qspi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_qspi.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of QSPI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_QSPI_H
00040 #define __STM32L4xx_HAL_QSPI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup QSPI
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup QSPI_Exported_Types QSPI Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  QSPI Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
00068                                   This parameter can be a number between 0 and 255 */
00069   uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
00070                                   This parameter can be a value between 1 and 16 */
00071   uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
00072                                   take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
00073                                   This parameter can be a value of @ref QSPI_SampleShifting */
00074   uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
00075                                   required to address the flash memory. The flash capacity can be up to 4GB
00076                                   (addressed using 32 bits) in indirect mode, but the addressable space in
00077                                   memory-mapped mode is limited to 256MB
00078                                   This parameter can be a number between 0 and 31 */
00079   uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
00080                                   of clock cycles which the chip select must remain high between commands.
00081                                   This parameter can be a value of @ref QSPI_ChipSelectHighTime */
00082   uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
00083                                   This parameter can be a value of @ref QSPI_ClockMode */
00084 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00085   uint32_t FlashID;            /* Specifies the Flash which will be used,
00086                                   This parameter can be a value of @ref QSPI_Flash_Select */
00087   uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
00088                                   This parameter can be a value of @ref QSPI_DualFlash_Mode */
00089 #endif
00090 }QSPI_InitTypeDef;
00091
00092 /**
00093   * @brief HAL QSPI State structures definition
00094   */
00095 typedef enum
00096 {
00097   HAL_QSPI_STATE_RESET             = 0x00,    /*!< Peripheral not initialized                            */
00098   HAL_QSPI_STATE_READY             = 0x01,    /*!< Peripheral initialized and ready for use              */
00099   HAL_QSPI_STATE_BUSY              = 0x02,    /*!< Peripheral in indirect mode and busy                  */
00100   HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12,    /*!< Peripheral in indirect mode with transmission ongoing */
00101   HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22,    /*!< Peripheral in indirect mode with reception ongoing    */
00102   HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42,    /*!< Peripheral in auto polling mode ongoing               */
00103   HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82,    /*!< Peripheral in memory mapped mode ongoing              */
00104   HAL_QSPI_STATE_ABORT             = 0x08,    /*!< Peripheral with abort request ongoing                 */
00105   HAL_QSPI_STATE_ERROR             = 0x04     /*!< Peripheral in error                                   */
00106 }HAL_QSPI_StateTypeDef;
00107
00108 /**
00109   * @brief  QSPI Handle Structure definition
00110   */
00111 typedef struct
00112 {
00113   QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
00114   QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
00115   uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
00116   __IO uint16_t              TxXferSize;       /* QSPI Tx Transfer size              */
00117   __IO uint16_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
00118   uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
00119   __IO uint16_t              RxXferSize;       /* QSPI Rx Transfer size              */
00120   __IO uint16_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
00121   DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
00122   __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
00123   __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
00124   __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
00125   uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
00126 }QSPI_HandleTypeDef;
00127
00128 /**
00129   * @brief  QSPI Command structure definition
00130   */
00131 typedef struct
00132 {
00133   uint32_t Instruction;        /* Specifies the Instruction to be sent
00134                                   This parameter can be a value (8-bit) between 0x00 and 0xFF */
00135   uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
00136                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00137   uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
00138                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00139   uint32_t AddressSize;        /* Specifies the Address Size
00140                                   This parameter can be a value of @ref QSPI_AddressSize */
00141   uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
00142                                   This parameter can be a value of @ref QSPI_AlternateBytesSize */
00143   uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
00144                                   This parameter can be a number between 0 and 31 */
00145   uint32_t InstructionMode;    /* Specifies the Instruction Mode
00146                                   This parameter can be a value of @ref QSPI_InstructionMode */
00147   uint32_t AddressMode;        /* Specifies the Address Mode
00148                                   This parameter can be a value of @ref QSPI_AddressMode */
00149   uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
00150                                   This parameter can be a value of @ref QSPI_AlternateBytesMode */
00151   uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
00152                                   This parameter can be a value of @ref QSPI_DataMode */
00153   uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)
00154                                   This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
00155                                   until end of memory)*/
00156   uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
00157                                   This parameter can be a value of @ref QSPI_DdrMode */
00158   uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of
00159                                   system clock in DDR mode. Not available on STM32L4x6 devices but in future devices.
00160                                   This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
00161   uint32_t SIOOMode;           /* Specifies the send instruction only once mode
00162                                   This parameter can be a value of @ref QSPI_SIOOMode */
00163 }QSPI_CommandTypeDef;
00164
00165 /**
00166   * @brief  QSPI Auto Polling mode configuration structure definition
00167   */
00168 typedef struct
00169 {
00170   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
00171                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00172   uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
00173                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00174   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
00175                                   This parameter can be any value between 0 and 0xFFFF */
00176   uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
00177                                   This parameter can be any value between 1 and 4 */
00178   uint32_t MatchMode;          /* Specifies the method used for determining a match.
00179                                   This parameter can be a value of @ref QSPI_MatchMode */
00180   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
00181                                   This parameter can be a value of @ref QSPI_AutomaticStop */
00182 }QSPI_AutoPollingTypeDef;
00183
00184 /**
00185   * @brief  QSPI Memory Mapped mode configuration structure definition
00186   */
00187 typedef struct
00188 {
00189   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
00190                                   This parameter can be any value between 0 and 0xFFFF */
00191   uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.
00192                                   This parameter can be a value of @ref QSPI_TimeOutActivation */
00193 }QSPI_MemoryMappedTypeDef;
00194
00195 /**
00196   * @}
00197   */
00198
00199 /* Exported constants --------------------------------------------------------*/
00200 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
00201   * @{
00202   */
00203
00204 /** @defgroup QSPI_ErrorCode QSPI Error Code
00205   * @{
00206   */
00207 #define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000) /*!< No error                 */
00208 #define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001) /*!< Timeout error            */
00209 #define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002) /*!< Transfer error           */
00210 #define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004) /*!< DMA transfer error       */
00211 #define HAL_QSPI_ERROR_INVALID_PARAM   ((uint32_t)0x00000008) /*!< Invalid parameters error */
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
00217   * @{
00218   */
00219 #define QSPI_SAMPLE_SHIFTING_NONE      ((uint32_t)0x00000000)        /*!<No clock cycle shift to sample data*/
00220 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
00226   * @{
00227   */
00228 #define QSPI_CS_HIGH_TIME_1_CYCLE      ((uint32_t)0x00000000)                              /*!<nCS stay high for at least 1 clock cycle between commands*/
00229 #define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
00230 #define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
00231 #define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
00232 #define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
00233 #define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
00234 #define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
00235 #define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup QSPI_ClockMode QSPI Clock Mode
00241   * @{
00242   */
00243 #define QSPI_CLOCK_MODE_0              ((uint32_t)0x00000000)         /*!<Clk stays low while nCS is released*/
00244 #define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
00245 /**
00246   * @}
00247   */
00248
00249 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00250 /** @defgroup QSPI_Flash_Select QSPI Flash Select
00251   * @{
00252   */
00253 #define QSPI_FLASH_ID_1                ((uint32_t)0x00000000)      /*!<FLASH 1 selected*/
00254 #define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
00255 /**
00256   * @}
00257   */
00258
00259   /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
00260   * @{
00261   */
00262 #define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
00263 #define QSPI_DUALFLASH_DISABLE         ((uint32_t)0x00000000)     /*!<Dual-flash mode disabled*/
00264 /**
00265   * @}
00266   */
00267 #endif
00268
00269 /** @defgroup QSPI_AddressSize QSPI Address Size
00270   * @{
00271   */
00272 #define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000)           /*!<8-bit address*/
00273 #define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
00274 #define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
00275 #define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
00281   * @{
00282   */
00283 #define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000)           /*!<8-bit alternate bytes*/
00284 #define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
00285 #define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
00286 #define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
00292 * @{
00293 */
00294 #define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000)          /*!<No instruction*/
00295 #define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
00296 #define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
00297 #define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup QSPI_AddressMode QSPI Address Mode
00303 * @{
00304 */
00305 #define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000)           /*!<No address*/
00306 #define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
00307 #define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
00308 #define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
00314 * @{
00315 */
00316 #define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000)           /*!<No alternate bytes*/
00317 #define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
00318 #define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
00319 #define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup QSPI_DataMode QSPI Data Mode
00325   * @{
00326   */
00327 #define QSPI_DATA_NONE                 ((uint32_t)0X00000000)           /*!<No data*/
00328 #define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
00329 #define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
00330 #define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup QSPI_DdrMode QSPI DDR Mode
00336   * @{
00337   */
00338 #define QSPI_DDR_MODE_DISABLE          ((uint32_t)0x00000000)       /*!<Double data rate mode disabled*/
00339 #define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
00345   * @{
00346   */
00347 #define QSPI_DDR_HHC_ANALOG_DELAY      ((uint32_t)0x00000000)       /*!<Delay the data output using analog delay in DDR mode*/
00348 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00349 #define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
00350 #endif
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
00356   * @{
00357   */
00358 #define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000)       /*!<Send instruction on every transaction*/
00359 #define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup QSPI_MatchMode QSPI Match Mode
00365   * @{
00366   */
00367 #define QSPI_MATCH_MODE_AND            ((uint32_t)0x00000000)     /*!<AND match mode between unmasked bits*/
00368 #define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
00374   * @{
00375   */
00376 #define QSPI_AUTOMATIC_STOP_DISABLE    ((uint32_t)0x00000000)      /*!<AutoPolling stops only with abort or QSPI disabling*/
00377 #define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
00383   * @{
00384   */
00385 #define QSPI_TIMEOUT_COUNTER_DISABLE   ((uint32_t)0x00000000)      /*!<Timeout counter disabled, nCS remains active*/
00386 #define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup QSPI_Flags QSPI Flags
00392   * @{
00393   */
00394 #define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
00395 #define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
00396 #define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
00397 #define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
00398 #define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
00399 #define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup QSPI_Interrupts QSPI Interrupts
00405   * @{
00406   */
00407 #define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
00408 #define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
00409 #define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
00410 #define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
00411 #define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
00417   * @brief QSPI Timeout definition
00418   * @{
00419   */
00420 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
00421 /**
00422   * @}
00423   */
00424
00425 /**
00426   * @}
00427   */
00428
00429 /* Exported macros -----------------------------------------------------------*/
00430 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
00431   * @{
00432   */
00433 /** @brief Reset QSPI handle state.
00434   * @param  __HANDLE__: QSPI handle.
00435   * @retval None
00436   */
00437 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
00438
00439 /** @brief  Enable the QSPI peripheral.
00440   * @param  __HANDLE__: specifies the QSPI Handle.
00441   * @retval None
00442   */
00443 #define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00444
00445 /** @brief  Disable the QSPI peripheral.
00446   * @param  __HANDLE__: specifies the QSPI Handle.
00447   * @retval None
00448   */
00449 #define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00450
00451 /** @brief  Enable the specified QSPI interrupt.
00452   * @param  __HANDLE__: specifies the QSPI Handle.
00453   * @param  __INTERRUPT__: specifies the QSPI interrupt source to enable.
00454   *          This parameter can be one of the following values:
00455   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00456   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00457   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00458   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00459   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00460   * @retval None
00461   */
00462 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00463
00464
00465 /** @brief  Disable the specified QSPI interrupt.
00466   * @param  __HANDLE__: specifies the QSPI Handle.
00467   * @param  __INTERRUPT__: specifies the QSPI interrupt source to disable.
00468   *          This parameter can be one of the following values:
00469   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00470   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00471   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00472   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00473   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00474   * @retval None
00475   */
00476 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00477
00478 /** @brief  Check whether the specified QSPI interrupt source is enabled or not.
00479   * @param  __HANDLE__: specifies the QSPI Handle.
00480   * @param  __INTERRUPT__: specifies the QSPI interrupt source to check.
00481   *          This parameter can be one of the following values:
00482   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00483   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00484   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00485   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00486   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00487   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00488   */
00489 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
00490
00491 /**
00492   * @brief  Check whether the selected QSPI flag is set or not.
00493   * @param  __HANDLE__: specifies the QSPI Handle.
00494   * @param  __FLAG__: specifies the QSPI flag to check.
00495   *          This parameter can be one of the following values:
00496   *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
00497   *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
00498   *            @arg QSPI_FLAG_SM:   QSPI Status match flag
00499   *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
00500   *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
00501   *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
00502   * @retval None
00503   */
00504 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
00505
00506 /** @brief  Clears the specified QSPI's flag status.
00507   * @param  __HANDLE__: specifies the QSPI Handle.
00508   * @param  __FLAG__: specifies the QSPI clear register flag that needs to be set
00509   *          This parameter can be one of the following values:
00510   *            @arg QSPI_FLAG_TO: QSPI Timeout flag
00511   *            @arg QSPI_FLAG_SM: QSPI Status match flag
00512   *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
00513   *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
00514   * @retval None
00515   */
00516 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
00517 /**
00518   * @}
00519   */
00520
00521 /* Exported functions --------------------------------------------------------*/
00522 /** @addtogroup QSPI_Exported_Functions
00523   * @{
00524   */
00525 /* Initialization/de-initialization functions  ********************************/
00526 HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
00527 HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
00528 void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
00529 void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
00530
00531 /* IO operation functions *****************************************************/
00532 /* QSPI IRQ handler method */
00533 void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
00534
00535 /* QSPI indirect mode */
00536 HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
00537 HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00538 HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00539 HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
00540 HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00541 HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00542 HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00543 HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00544
00545 /* QSPI status flag polling mode */
00546 HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
00547 HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
00548
00549 /* QSPI memory-mapped mode */
00550 HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
00551
00552 /* Callback functions in non-blocking modes ***********************************/
00553 void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
00554 void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
00555 void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
00556
00557 /* QSPI indirect mode */
00558 void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
00559 void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00560 void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00561 void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00562 void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00563
00564 /* QSPI status flag polling mode */
00565 void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
00566
00567 /* QSPI memory-mapped mode */
00568 void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
00569
00570 /* Peripheral Control and State functions  ************************************/
00571 HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
00572 uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
00573 HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
00574 HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
00575 void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
00576 HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
00577 uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
00578 /**
00579   * @}
00580   */
00581 /* End of exported functions -------------------------------------------------*/
00582
00583 /* Private macros ------------------------------------------------------------*/
00584 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00585 * @{
00586 */
00587 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
00588
00589 #define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0) && ((THR) <= 16))
00590
00591 #define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
00592                                             ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
00593
00594 #define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31))
00595
00596 #define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
00597                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
00598                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
00599                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
00600                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
00601                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
00602                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
00603                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
00604
00605 #define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
00606                                             ((CLKMODE) == QSPI_CLOCK_MODE_3))
00607
00608 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00609 #define IS_QSPI_FLASH_ID(FLASH)            (((FLASH) == QSPI_FLASH_ID_1) || \
00610                                             ((FLASH) == QSPI_FLASH_ID_2))
00611
00612 #define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \
00613                                             ((MODE) == QSPI_DUALFLASH_DISABLE))
00614 #endif
00615
00616 #define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFF)
00617
00618 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
00619                                             ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
00620                                             ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
00621                                             ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
00622
00623 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
00624                                             ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
00625                                             ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
00626                                             ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
00627
00628 #define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31)
00629
00630 #define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
00631                                             ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
00632                                             ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
00633                                             ((MODE) == QSPI_INSTRUCTION_4_LINES))
00634
00635 #define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
00636                                             ((MODE) == QSPI_ADDRESS_1_LINE)  || \
00637                                             ((MODE) == QSPI_ADDRESS_2_LINES) || \
00638                                             ((MODE) == QSPI_ADDRESS_4_LINES))
00639
00640 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
00641                                             ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
00642                                             ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
00643                                             ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
00644
00645 #define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
00646                                             ((MODE) == QSPI_DATA_1_LINE)  || \
00647                                             ((MODE) == QSPI_DATA_2_LINES) || \
00648                                             ((MODE) == QSPI_DATA_4_LINES))
00649
00650 #define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
00651                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
00652
00653 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00654 #define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
00655                                             ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
00656 #else
00657 #define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
00658 #endif
00659
00660 #define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
00661                                             ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
00662
00663 #define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
00664
00665 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1) && ((SIZE) <= 4))
00666
00667 #define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
00668                                             ((MODE) == QSPI_MATCH_MODE_OR))
00669
00670 #define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
00671                                             ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
00672
00673 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
00674                                             ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
00675
00676 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFF)
00677 /**
00678 * @}
00679 */
00680 /* End of private macros -----------------------------------------------------*/
00681
00682 /**
00683   * @}
00684   */
00685
00686 /**
00687   * @}
00688   */
00689
00690 #ifdef __cplusplus
00691 }
00692 #endif
00693
00694 #endif /* __STM32L4xx_HAL_QSPI_H */
00695
00696 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:13 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rcc.c Source File

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stm32l4xx_hal_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   RCC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                       ##### RCC specific features #####
00016   ==============================================================================
00017     [..]
00018       After reset the device is running from Multiple Speed Internal oscillator
00019       (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
00020       and I-Cache are disabled, and all peripherals are off except internal
00021       SRAM, Flash and JTAG.
00022
00023       (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
00024           all peripherals mapped on these busses are running at MSI speed.
00025       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00026       (+) All GPIOs are in analog mode, except the JTAG pins which
00027           are assigned to be used for debug purpose.
00028
00029     [..]
00030       Once the device started from reset, the user application has to:
00031       (+) Configure the clock source to be used to drive the System clock
00032           (if the application needs higher frequency/performance)
00033       (+) Configure the System clock frequency and Flash settings
00034       (+) Configure the AHB and APB busses prescalers
00035       (+) Enable the clock for the peripheral(s) to be used
00036       (+) Configure the clock source(s) for peripherals which clocks are not
00037           derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG)
00038
00039   @endverbatim
00040   ******************************************************************************
00041   * @attention
00042   *
00043   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00044   *
00045   * Redistribution and use in source and binary forms, with or without modification,
00046   * are permitted provided that the following conditions are met:
00047   *   1. Redistributions of source code must retain the above copyright notice,
00048   *      this list of conditions and the following disclaimer.
00049   *   2. Redistributions in binary form must reproduce the above copyright notice,
00050   *      this list of conditions and the following disclaimer in the documentation
00051   *      and/or other materials provided with the distribution.
00052   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00053   *      may be used to endorse or promote products derived from this software
00054   *      without specific prior written permission.
00055   *
00056   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00057   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00058   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00059   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00060   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00061   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00062   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00063   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00064   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00065   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00066   *
00067   ******************************************************************************
00068   */
00069
00070 /* Includes ------------------------------------------------------------------*/
00071 #include "stm32l4xx_hal.h"
00072
00073 /** @addtogroup STM32L4xx_HAL_Driver
00074   * @{
00075   */
00076
00077 /** @defgroup RCC RCC
00078   * @brief RCC HAL module driver
00079   * @{
00080   */
00081
00082 #ifdef HAL_RCC_MODULE_ENABLED
00083
00084 /* Private typedef -----------------------------------------------------------*/
00085 /* Private define ------------------------------------------------------------*/
00086 /** @defgroup RCC_Private_Constants RCC Private Constants
00087  * @{
00088  */
00089 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
00090 #define HSI_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
00091 #define MSI_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
00092 #define LSI_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
00093 #define HSI48_TIMEOUT_VALUE        ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
00094 #define PLL_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
00095 #define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000U) /* 5 s    */
00096 /**
00097   * @}
00098   */
00099
00100 /* Private macro -------------------------------------------------------------*/
00101 /** @defgroup RCC_Private_Macros RCC Private Macros
00102   * @{
00103   */
00104 #define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
00105 #define MCO1_GPIO_PORT        GPIOA
00106 #define MCO1_PIN              GPIO_PIN_8
00107
00108 #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
00109             (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
00110 /**
00111   * @}
00112   */
00113
00114 /* Private variables ---------------------------------------------------------*/
00115 /** @defgroup RCC_Private_Variables RCC Private Variables
00116   * @{
00117   */
00118
00119 /**
00120   * @}
00121   */
00122
00123 /* Private function prototypes -----------------------------------------------*/
00124 /** @defgroup RCC_Private_Functions RCC Private Functions
00125   * @{
00126   */
00127 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
00128 /**
00129   * @}
00130   */
00131
00132 /* Exported functions --------------------------------------------------------*/
00133
00134 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00135   * @{
00136   */
00137
00138 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00139   *  @brief    Initialization and Configuration functions
00140   *
00141   @verbatim
00142  ===============================================================================
00143            ##### Initialization and de-initialization functions #####
00144  ===============================================================================
00145     [..]
00146       This section provides functions allowing to configure the internal and external oscillators
00147       (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
00148        and APB2).
00149
00150     [..] Internal/external clock and PLL configuration
00151          (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
00152              the PLL as System clock source.
00153
00154          (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
00155              It can be used to generate the clock for the USB OTG FS (48 MHz).
00156              The number of flash wait states is automatically adjusted when MSI range is updated with
00157              HAL_RCC_OscConfig() and the MSI is used as System clock source.
00158
00159          (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
00160              clock source.
00161
00162          (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
00163              through the PLL as System clock source. Can be used also optionally as RTC clock source.
00164
00165          (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
00166
00167          (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
00168            (++) The first output is used to generate the high speed system clock (up to 80MHz).
00169            (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
00170                 the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
00171            (++) The third output is used to generate an accurate clock to achieve
00172                 high-quality audio performance on SAI interface.
00173
00174          (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
00175            (++) The first output is used to generate SAR ADC1 clock.
00176            (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
00177                 the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
00178            (++) The Third output is used to generate an accurate clock to achieve
00179                 high-quality audio performance on SAI interface.
00180
00181          (+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks:
00182            (++) The first output is used to generate SAR ADC2 clock.
00183            (++) The second  output is used to generate an accurate clock to achieve
00184                 high-quality audio performance on SAI interface.
00185
00186          (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
00187             (HSE used directly or through PLL as System clock source), the System clock
00188              is automatically switched to HSI and an interrupt is generated if enabled.
00189              The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
00190              exception vector.
00191
00192          (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
00193              main PLL clock (through a configurable prescaler) on PA8 pin.
00194
00195     [..] System, AHB and APB busses clocks configuration
00196          (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
00197              HSE and main PLL.
00198              The AHB clock (HCLK) is derived from System clock through configurable
00199              prescaler and used to clock the CPU, memory and peripherals mapped
00200              on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
00201              from AHB clock through configurable prescalers and used to clock
00202              the peripherals mapped on these busses. You can use
00203              "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
00204
00205          -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
00206
00207            (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or
00208                 from an external clock mapped on the SAI_CKIN pin.
00209                 You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
00210            (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
00211                 divided by 2 to 31.
00212                 You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
00213                 to configure this clock.
00214            (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
00215                 to work correctly, while the SDMMC1 and RNG peripherals require a frequency
00216                 equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1
00217                 through PLLQ divider. You have to enable the peripheral clock and use
00218                 HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
00219            (+@) IWDG clock which is always the LSI clock.
00220
00221
00222          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.
00223              The clock source frequency should be adapted depending on the device voltage range
00224              as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
00225
00226   @endverbatim
00227
00228            Table 1. HCLK clock frequency.
00229            +-------------------------------------------------------+
00230            | Latency         |    HCLK clock frequency (MHz)       |
00231            |                 |-------------------------------------|
00232            |                 | voltage range 1  | voltage range 2  |
00233            |                 |      1.2 V       |     1.0 V        |
00234            |-----------------|------------------|------------------|
00235            |0WS(1 CPU cycles)|  0 < HCLK <= 16  |  0 < HCLK <= 6   |
00236            |-----------------|------------------|------------------|
00237            |1WS(2 CPU cycles)| 16 < HCLK <= 32  |  6 < HCLK <= 12  |
00238            |-----------------|------------------|------------------|
00239            |2WS(3 CPU cycles)| 32 < HCLK <= 48  | 12 < HCLK <= 18  |
00240            |-----------------|------------------|------------------|
00241            |3WS(4 CPU cycles)| 48 < HCLK <= 64  | 18 < HCLK <= 26  |
00242            |-----------------|------------------|------------------|
00243            |4WS(5 CPU cycles)| 64 < HCLK <= 80  | 18 < HCLK <= 26  |
00244            +-------------------------------------------------------+
00245   * @{
00246   */
00247
00248 /**
00249   * @brief  Reset the RCC clock configuration to the default reset state.
00250   * @note   The default reset state of the clock configuration is given below:
00251   *            - MSI ON and used as system clock source
00252   *            - HSE, HSI, PLL, PLLSAI1 and PLLISAI2 OFF
00253   *            - AHB, APB1 and APB2 prescaler set to 1.
00254   *            - CSS, MCO1 OFF
00255   *            - All interrupts disabled
00256   * @note   This function doesn't modify the configuration of the
00257   *            - Peripheral clocks
00258   *            - LSI, LSE and RTC clocks
00259   * @retval None
00260   */
00261 void HAL_RCC_DeInit(void)
00262 {
00263   /* Set MSION bit */
00264   SET_BIT(RCC->CR, RCC_CR_MSION);
00265
00266   /* Insure MSIRDY bit is set before writing default MSIRANGE value */
00267   while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) { __NOP(); }
00268
00269   /* Set MSIRANGE default value */
00270   MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6);
00271
00272   /* Reset CFGR register (MSI is selected as system clock source) */
00273   CLEAR_REG(RCC->CFGR);
00274
00275   /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */
00276 #if defined(RCC_PLLSAI2_SUPPORT)
00277
00278   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON);
00279
00280 #else
00281
00282   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON);
00283
00284 #endif /* RCC_PLLSAI2_SUPPORT */
00285
00286   /* Reset PLLCFGR register */
00287   CLEAR_REG(RCC->PLLCFGR);
00288   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 );
00289
00290   /* Reset PLLSAI1CFGR register */
00291   CLEAR_REG(RCC->PLLSAI1CFGR);
00292   SET_BIT(RCC->PLLSAI1CFGR,  RCC_PLLSAI1CFGR_PLLSAI1N_4 );
00293
00294 #if defined(RCC_PLLSAI2_SUPPORT)
00295
00296   /* Reset PLLSAI2CFGR register */
00297   CLEAR_REG(RCC->PLLSAI2CFGR);
00298   SET_BIT(RCC->PLLSAI2CFGR,  RCC_PLLSAI2CFGR_PLLSAI2N_4 );
00299
00300 #endif /* RCC_PLLSAI2_SUPPORT */
00301
00302   /* Reset HSEBYP bit */
00303   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00304
00305   /* Disable all interrupts */
00306   CLEAR_REG(RCC->CIER);
00307
00308   /* Update the SystemCoreClock global variable */
00309   SystemCoreClock = MSI_VALUE;
00310 }
00311
00312 /**
00313   * @brief  Initialize the RCC Oscillators according to the specified parameters in the
00314   *         RCC_OscInitTypeDef.
00315   * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
00316   *         contains the configuration information for the RCC Oscillators.
00317   * @note   The PLL is not disabled when used as system clock.
00318   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
00319   *         supported by this macro. User should request a transition to LSE Off
00320   *         first and then LSE On or LSE Bypass.
00321   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
00322   *         supported by this macro. User should request a transition to HSE Off
00323   *         first and then HSE On or HSE Bypass.
00324   * @retval HAL status
00325   */
00326 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00327 {
00328   uint32_t tickstart = 0;
00329
00330   /* Check the parameters */
00331   assert_param(RCC_OscInitStruct != NULL);
00332   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00333
00334   /*----------------------------- MSI Configuration --------------------------*/
00335   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
00336   {
00337     /* Check the parameters */
00338     assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
00339     assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
00340     assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
00341
00342     /* When the MSI is used as system clock it will not be disabled */
00343     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) )
00344     {
00345       if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
00346       {
00347         return HAL_ERROR;
00348       }
00349
00350        /* Otherwise, just the calibration and MSI range change are allowed */
00351       else
00352       {
00353         /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00354            must be correctly programmed according to the frequency of the CPU clock
00355            (HCLK) and the supply voltage of the device. */
00356         if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
00357         {
00358           /* First increase number of wait states update if necessary */
00359           if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
00360           {
00361             return HAL_ERROR;
00362           }
00363
00364           /* Selects the Multiple Speed oscillator (MSI) clock range .*/
00365           __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
00366           /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
00367           __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
00368         }
00369         else
00370         {
00371           /* Else, keep current flash latency while decreasing applies */
00372           /* Selects the Multiple Speed oscillator (MSI) clock range .*/
00373           __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
00374           /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
00375           __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
00376
00377           /* Decrease number of wait states update if necessary */
00378           if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
00379           {
00380             return HAL_ERROR;
00381           }
00382         }
00383
00384         /* Update the SystemCoreClock global variable */
00385         SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
00386
00387         /* Configure the source of time base considering new system clocks settings*/
00388         HAL_InitTick (TICK_INT_PRIORITY);
00389       }
00390     }
00391     else
00392     {
00393       /* Check the MSI State */
00394       if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
00395       {
00396         /* Enable the Internal High Speed oscillator (MSI). */
00397         __HAL_RCC_MSI_ENABLE();
00398
00399         /* Get timeout */
00400         tickstart = HAL_GetTick();
00401
00402         /* Wait till MSI is ready */
00403         while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET)
00404         {
00405           if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
00406           {
00407             return HAL_TIMEOUT;
00408           }
00409         }
00410          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
00411         __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
00412          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
00413         __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
00414
00415       }
00416       else
00417       {
00418         /* Disable the Internal High Speed oscillator (MSI). */
00419         __HAL_RCC_MSI_DISABLE();
00420
00421         /* Get timeout */
00422         tickstart = HAL_GetTick();
00423
00424         /* Wait till MSI is ready */
00425         while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET)
00426         {
00427           if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
00428           {
00429             return HAL_TIMEOUT;
00430           }
00431         }
00432       }
00433     }
00434   }
00435   /*------------------------------- HSE Configuration ------------------------*/
00436   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00437   {
00438     /* Check the parameters */
00439     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00440
00441     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
00442     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||
00443        ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
00444     {
00445       if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00446       {
00447         return HAL_ERROR;
00448       }
00449     }
00450     else
00451     {
00452       /* Set the new HSE configuration ---------------------------------------*/
00453       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00454
00455       /* Check the HSE State */
00456       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
00457       {
00458         /* Get Start Tick*/
00459         tickstart = HAL_GetTick();
00460
00461         /* Wait till HSE is ready */
00462         while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET)
00463         {
00464           if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
00465           {
00466             return HAL_TIMEOUT;
00467           }
00468         }
00469       }
00470       else
00471       {
00472         /* Get Start Tick*/
00473         tickstart = HAL_GetTick();
00474
00475         /* Wait till HSE is disabled */
00476         while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
00477         {
00478           if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
00479           {
00480             return HAL_TIMEOUT;
00481           }
00482         }
00483       }
00484     }
00485   }
00486   /*----------------------------- HSI Configuration --------------------------*/
00487   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00488   {
00489     /* Check the parameters */
00490     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00491     assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00492
00493     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
00494     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||
00495        ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
00496     {
00497       /* When HSI is used as system clock it will not be disabled */
00498       if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
00499       {
00500         return HAL_ERROR;
00501       }
00502       /* Otherwise, just the calibration is allowed */
00503       else
00504       {
00505         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00506         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00507       }
00508     }
00509     else
00510     {
00511       /* Check the HSI State */
00512       if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
00513       {
00514         /* Enable the Internal High Speed oscillator (HSI). */
00515         __HAL_RCC_HSI_ENABLE();
00516
00517         /* Get Start Tick*/
00518         tickstart = HAL_GetTick();
00519
00520         /* Wait till HSI is ready */
00521         while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
00522         {
00523           if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00524           {
00525             return HAL_TIMEOUT;
00526           }
00527         }
00528
00529         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00530         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00531       }
00532       else
00533       {
00534         /* Disable the Internal High Speed oscillator (HSI). */
00535         __HAL_RCC_HSI_DISABLE();
00536
00537         /* Get Start Tick*/
00538         tickstart = HAL_GetTick();
00539
00540         /* Wait till HSI is disabled */
00541         while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET)
00542         {
00543           if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00544           {
00545             return HAL_TIMEOUT;
00546           }
00547         }
00548       }
00549     }
00550   }
00551   /*------------------------------ LSI Configuration -------------------------*/
00552   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
00553   {
00554     /* Check the parameters */
00555     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00556
00557     /* Check the LSI State */
00558     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
00559     {
00560       /* Enable the Internal Low Speed oscillator (LSI). */
00561       __HAL_RCC_LSI_ENABLE();
00562
00563       /* Get Start Tick*/
00564       tickstart = HAL_GetTick();
00565
00566       /* Wait till LSI is ready */
00567       while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RESET)
00568       {
00569         if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
00570         {
00571           return HAL_TIMEOUT;
00572         }
00573       }
00574     }
00575     else
00576     {
00577       /* Disable the Internal Low Speed oscillator (LSI). */
00578       __HAL_RCC_LSI_DISABLE();
00579
00580       /* Get Start Tick*/
00581       tickstart = HAL_GetTick();
00582
00583       /* Wait till LSI is disabled */
00584       while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != RESET)
00585       {
00586         if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
00587         {
00588           return HAL_TIMEOUT;
00589         }
00590       }
00591     }
00592   }
00593   /*------------------------------ LSE Configuration -------------------------*/
00594   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00595   {
00596     FlagStatus       pwrclkchanged = RESET;
00597
00598     /* Check the parameters */
00599     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00600
00601     /* Update LSE configuration in Backup Domain control register    */
00602     /* Requires to enable write access to Backup Domain of necessary */
00603     if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
00604     {
00605       __HAL_RCC_PWR_CLK_ENABLE();
00606       pwrclkchanged = SET;
00607     }
00608
00609     if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
00610     {
00611       /* Enable write access to Backup domain */
00612       SET_BIT(PWR->CR1, PWR_CR1_DBP);
00613
00614       /* Wait for Backup domain Write protection disable */
00615       tickstart = HAL_GetTick();
00616
00617       while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
00618       {
00619         if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00620         {
00621           return HAL_TIMEOUT;
00622         }
00623       }
00624     }
00625
00626     /* Set the new LSE configuration -----------------------------------------*/
00627     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00628
00629     /* Check the LSE State */
00630     if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
00631     {
00632       /* Get Start Tick*/
00633       tickstart = HAL_GetTick();
00634
00635       /* Wait till LSE is ready */
00636       while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET)
00637       {
00638         if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00639         {
00640           return HAL_TIMEOUT;
00641         }
00642       }
00643     }
00644     else
00645     {
00646       /* Get Start Tick*/
00647       tickstart = HAL_GetTick();
00648
00649       /* Wait till LSE is disabled */
00650       while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != RESET)
00651       {
00652         if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00653         {
00654           return HAL_TIMEOUT;
00655         }
00656       }
00657     }
00658
00659     /* Restore clock configuration if changed */
00660     if(pwrclkchanged == SET)
00661     {
00662       __HAL_RCC_PWR_CLK_DISABLE();
00663     }
00664   }
00665 #if defined(RCC_HSI48_SUPPORT)
00666   /*------------------------------ HSI48 Configuration -----------------------*/
00667   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
00668   {
00669     /* Check the parameters */
00670     assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
00671
00672     /* Check the LSI State */
00673     if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
00674     {
00675       /* Enable the Internal Low Speed oscillator (HSI48). */
00676       __HAL_RCC_HSI48_ENABLE();
00677
00678       /* Get Start Tick*/
00679       tickstart = HAL_GetTick();
00680
00681       /* Wait till HSI48 is ready */
00682       while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RESET)
00683       {
00684         if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
00685         {
00686           return HAL_TIMEOUT;
00687         }
00688       }
00689     }
00690     else
00691     {
00692       /* Disable the Internal Low Speed oscillator (HSI48). */
00693       __HAL_RCC_HSI48_DISABLE();
00694
00695       /* Get Start Tick*/
00696       tickstart = HAL_GetTick();
00697
00698       /* Wait till HSI48 is disabled */
00699       while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != RESET)
00700       {
00701         if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
00702         {
00703           return HAL_TIMEOUT;
00704         }
00705       }
00706     }
00707   }
00708 #endif /* RCC_HSI48_SUPPORT */
00709   /*-------------------------------- PLL Configuration -----------------------*/
00710   /* Check the parameters */
00711   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00712
00713   if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
00714   {
00715     /* Check if the PLL is used as system clock or not */
00716     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
00717     {
00718       if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
00719       {
00720         /* Check the parameters */
00721         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00722         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
00723         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
00724         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
00725         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
00726         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
00727
00728         /* Disable the main PLL. */
00729         __HAL_RCC_PLL_DISABLE();
00730
00731         /* Get Start Tick*/
00732         tickstart = HAL_GetTick();
00733
00734         /* Wait till PLL is ready */
00735         while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
00736         {
00737           if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00738           {
00739             return HAL_TIMEOUT;
00740           }
00741         }
00742
00743         /* Configure the main PLL clock source, multiplication and division factors. */
00744         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
00745                              RCC_OscInitStruct->PLL.PLLM,
00746                              RCC_OscInitStruct->PLL.PLLN,
00747                              RCC_OscInitStruct->PLL.PLLP,
00748                              RCC_OscInitStruct->PLL.PLLQ,
00749                              RCC_OscInitStruct->PLL.PLLR);
00750
00751         /* Enable the main PLL. */
00752         __HAL_RCC_PLL_ENABLE();
00753
00754         /* Enable PLL System Clock output. */
00755          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
00756
00757         /* Get Start Tick*/
00758         tickstart = HAL_GetTick();
00759
00760         /* Wait till PLL is ready */
00761         while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
00762         {
00763           if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00764           {
00765             return HAL_TIMEOUT;
00766           }
00767         }
00768       }
00769       else
00770       {
00771         /* Disable the main PLL. */
00772         __HAL_RCC_PLL_DISABLE();
00773
00774         /* Disable all PLL outputs to save power if no PLLs on */
00775         if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
00776 #if defined(RCC_PLLSAI2_SUPPORT)
00777            &&
00778            (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
00779 #endif /* RCC_PLLSAI2_SUPPORT */
00780           )
00781         {
00782           MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
00783         }
00784
00785 #if defined(RCC_PLLSAI2_SUPPORT)
00786         __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
00787 #else
00788         __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);
00789 #endif /* RCC_PLLSAI2_SUPPORT */
00790
00791         /* Get Start Tick*/
00792         tickstart = HAL_GetTick();
00793
00794         /* Wait till PLL is disabled */
00795         while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
00796         {
00797           if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00798           {
00799             return HAL_TIMEOUT;
00800           }
00801         }
00802       }
00803     }
00804     else
00805     {
00806       return HAL_ERROR;
00807     }
00808   }
00809   return HAL_OK;
00810 }
00811
00812 /**
00813   * @brief  Initialize the CPU, AHB and APB busses clocks according to the specified
00814   *         parameters in the RCC_ClkInitStruct.
00815   * @param  RCC_ClkInitStruct  pointer to an RCC_OscInitTypeDef structure that
00816   *         contains the configuration information for the RCC peripheral.
00817   * @param  FLatency  FLASH Latency
00818   *          This parameter can be one of the following values:
00819   *            @arg FLASH_LATENCY_0   FLASH 0 Latency cycle
00820   *            @arg FLASH_LATENCY_1   FLASH 1 Latency cycle
00821   *            @arg FLASH_LATENCY_2   FLASH 2 Latency cycle
00822   *            @arg FLASH_LATENCY_3   FLASH 3 Latency cycle
00823   *            @arg FLASH_LATENCY_4   FLASH 4 Latency cycle
00824   *
00825   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00826   *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
00827   *
00828   * @note   The MSI is used by default as system clock source after
00829   *         startup from Reset, wake-up from STANDBY mode. After restart from Reset,
00830   *         the MSI frequency is set to its default value 4 MHz.
00831   *
00832   * @note   The HSI can be selected as system clock source after
00833   *         from STOP modes or in case of failure of the HSE used directly or indirectly
00834   *         as system clock (if the Clock Security System CSS is enabled).
00835   *
00836   * @note   A switch from one clock source to another occurs only if the target
00837   *         clock source is ready (clock stable after startup delay or PLL locked).
00838   *         If a clock source which is not yet ready is selected, the switch will
00839   *         occur when the clock source is ready.
00840   *
00841   * @note   You can use HAL_RCC_GetClockConfig() function to know which clock is
00842   *         currently used as system clock source.
00843   *
00844   * @note   Depending on the device voltage range, the software has to set correctly
00845   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
00846   *         (for more details refer to section above "Initialization/de-initialization functions")
00847   * @retval None
00848   */
00849 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
00850 {
00851   uint32_t tickstart = 0;
00852
00853   /* Check the parameters */
00854   assert_param(RCC_ClkInitStruct != NULL);
00855   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
00856   assert_param(IS_FLASH_LATENCY(FLatency));
00857
00858   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00859     must be correctly programmed according to the frequency of the CPU clock
00860     (HCLK) and the supply voltage of the device. */
00861
00862   /* Increasing the number of wait states because of higher CPU frequency */
00863   if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
00864   {
00865     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00866     __HAL_FLASH_SET_LATENCY(FLatency);
00867
00868     /* Check that the new number of wait states is taken into account to access the Flash
00869     memory by reading the FLASH_ACR register */
00870     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00871     {
00872       return HAL_ERROR;
00873     }
00874   }
00875
00876   /*-------------------------- HCLK Configuration --------------------------*/
00877   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00878   {
00879     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00880     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00881   }
00882
00883   /*------------------------- SYSCLK Configuration ---------------------------*/
00884   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
00885   {
00886     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
00887
00888     /* HSE is selected as System Clock Source */
00889     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00890     {
00891       /* Check the HSE ready flag */
00892       if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET)
00893       {
00894         return HAL_ERROR;
00895       }
00896     }
00897     /* PLL is selected as System Clock Source */
00898     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00899     {
00900       /* Check the PLL ready flag */
00901       if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
00902       {
00903         return HAL_ERROR;
00904       }
00905     }
00906     /* MSI is selected as System Clock Source */
00907     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
00908     {
00909       /* Check the MSI ready flag */
00910       if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET)
00911       {
00912         return HAL_ERROR;
00913       }
00914     }
00915     /* HSI is selected as System Clock Source */
00916     else
00917     {
00918       /* Check the HSI ready flag */
00919       if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
00920       {
00921         return HAL_ERROR;
00922       }
00923     }
00924     MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
00925
00926     /* Get Start Tick*/
00927     tickstart = HAL_GetTick();
00928
00929     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00930     {
00931       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
00932       {
00933         if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00934         {
00935           return HAL_TIMEOUT;
00936         }
00937       }
00938     }
00939     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00940     {
00941       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
00942       {
00943         if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00944         {
00945           return HAL_TIMEOUT;
00946         }
00947       }
00948     }
00949     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
00950     {
00951       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
00952       {
00953         if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00954         {
00955           return HAL_TIMEOUT;
00956         }
00957       }
00958     }
00959     else
00960     {
00961       while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
00962       {
00963         if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00964         {
00965           return HAL_TIMEOUT;
00966         }
00967       }
00968     }
00969   }
00970
00971   /* Decreasing the number of wait states because of lower CPU frequency */
00972   if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
00973   {
00974     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00975     __HAL_FLASH_SET_LATENCY(FLatency);
00976
00977     /* Check that the new number of wait states is taken into account to access the Flash
00978     memory by reading the FLASH_ACR register */
00979     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00980     {
00981       return HAL_ERROR;
00982     }
00983   }
00984
00985   /*-------------------------- PCLK1 Configuration ---------------------------*/
00986   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00987   {
00988     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
00989     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
00990   }
00991
00992   /*-------------------------- PCLK2 Configuration ---------------------------*/
00993   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00994   {
00995     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
00996     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
00997   }
00998
00999   /* Update the SystemCoreClock global variable */
01000   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
01001
01002   /* Configure the source of time base considering new system clocks settings*/
01003   HAL_InitTick (TICK_INT_PRIORITY);
01004
01005   return HAL_OK;
01006 }
01007
01008 /**
01009   * @}
01010   */
01011
01012 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
01013  *  @brief   RCC clocks control functions
01014  *
01015 @verbatim
01016  ===============================================================================
01017                       ##### Peripheral Control functions #####
01018  ===============================================================================
01019     [..]
01020     This subsection provides a set of functions allowing to:
01021
01022     (+) Ouput clock to MCO pin.
01023     (+) Retrieve current clock frequencies.
01024     (+) Enable the Clock Security System.
01025
01026 @endverbatim
01027   * @{
01028   */
01029
01030 /**
01031   * @brief  Select the clock source to output on MCO pin(PA8).
01032   * @note   PA8 should be configured in alternate function mode.
01033   * @param  RCC_MCOx  specifies the output direction for the clock source.
01034   *          For STM32L4xx family this parameter can have only one value:
01035   *            @arg @ref RCC_MCO1  Clock source to output on MCO1 pin(PA8).
01036   * @param  RCC_MCOSource  specifies the clock source to output.
01037   *          This parameter can be one of the following values:
01038   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled, no clock on MCO
01039   *            @arg @ref RCC_MCO1SOURCE_SYSCLK  system  clock selected as MCO source
01040   *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source
01041   *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
01042   *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee
01043   *            @arg @ref RCC_MCO1SOURCE_PLLCLK  main PLL clock selected as MCO source
01044   *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
01045   *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
01046   @if STM32L443xx
01047   *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
01048   @endif
01049   * @param  RCC_MCODiv  specifies the MCO prescaler.
01050   *          This parameter can be one of the following values:
01051   *            @arg @ref RCC_MCODIV_1  no division applied to MCO clock
01052   *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock
01053   *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock
01054   *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock
01055   *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock
01056   * @retval None
01057   */
01058 void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
01059 {
01060   GPIO_InitTypeDef GPIO_InitStruct;
01061   /* Check the parameters */
01062   assert_param(IS_RCC_MCO(RCC_MCOx));
01063   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
01064   assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
01065
01066   /* MCO Clock Enable */
01067   __MCO1_CLK_ENABLE();
01068
01069   /* Configue the MCO1 pin in alternate function mode */
01070   GPIO_InitStruct.Pin = MCO1_PIN;
01071   GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
01072   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
01073   GPIO_InitStruct.Pull = GPIO_NOPULL;
01074   GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
01075   HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
01076
01077   /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */
01078   MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv ));
01079 }
01080
01081 /**
01082   * @brief  Return the SYSCLK frequency.
01083   *
01084   * @note   The system frequency computed by this function is not the real
01085   *         frequency in the chip. It is calculated based on the predefined
01086   *         constant and the selected clock source:
01087   * @note     If SYSCLK source is MSI, function returns values based on MSI
01088   *             Value as defined by the MSI range.
01089   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
01090   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
01091   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
01092   *           HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
01093   * @note     (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
01094   *               16 MHz) but the real value may vary depending on the variations
01095   *               in voltage and temperature.
01096   * @note     (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
01097   *                8 MHz), user has to ensure that HSE_VALUE is same as the real
01098   *                frequency of the crystal used. Otherwise, this function may
01099   *                have wrong result.
01100   *
01101   * @note   The result of this function could be not correct when using fractional
01102   *         value for HSE crystal.
01103   *
01104   * @note   This function can be used by the user application to compute the
01105   *         baudrate for the communication peripherals or configure other parameters.
01106   *
01107   * @note   Each time SYSCLK changes, this function must be called to update the
01108   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
01109   *
01110   *
01111   * @retval SYSCLK frequency
01112   */
01113 uint32_t HAL_RCC_GetSysClockFreq(void)
01114 {
01115   uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U;
01116   uint32_t sysclockfreq = 0U;
01117
01118   if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ||
01119      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)))
01120   {
01121     /* MSI or PLL with MSI source used as system clock source */
01122
01123     /* Get SYSCLK source */
01124     if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET)
01125     { /* MSISRANGE from RCC_CSR applies */
01126       msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> POSITION_VAL(RCC_CSR_MSISRANGE);
01127     }
01128     else
01129     { /* MSIRANGE from RCC_CR applies */
01130       msirange = (RCC->CR & RCC_CR_MSIRANGE) >> POSITION_VAL(RCC_CR_MSIRANGE);
01131     }
01132     /*MSI frequency range in HZ*/
01133     msirange = MSIRangeTable[msirange];
01134
01135     if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI)
01136     {
01137       /* MSI used as system clock source */
01138       sysclockfreq = msirange;
01139     }
01140   }
01141   else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
01142   {
01143     /* HSI used as system clock source */
01144     sysclockfreq = HSI_VALUE;
01145   }
01146   else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
01147   {
01148     /* HSE used as system clock source */
01149     sysclockfreq = HSE_VALUE;
01150   }
01151
01152   if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
01153   {
01154     /* PLL used as system clock  source */
01155
01156     /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
01157     SYSCLK = PLL_VCO / PLLR
01158     */
01159     pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
01160     pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U ;
01161
01162     switch (pllsource)
01163     {
01164     case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01165       pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
01166       break;
01167
01168     case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01169       pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
01170       break;
01171
01172     case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
01173     default:
01174       pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
01175       break;
01176     }
01177     pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U ) * 2U;
01178     sysclockfreq = pllvco/pllr;
01179   }
01180
01181   return sysclockfreq;
01182 }
01183
01184 /**
01185   * @brief  Return the HCLK frequency.
01186   * @note   Each time HCLK changes, this function must be called to update the
01187   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
01188   *
01189   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
01190   * @retval HCLK frequency in Hz
01191   */
01192 uint32_t HAL_RCC_GetHCLKFreq(void)
01193 {
01194   return SystemCoreClock;
01195 }
01196
01197 /**
01198   * @brief  Return the PCLK1 frequency.
01199   * @note   Each time PCLK1 changes, this function must be called to update the
01200   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
01201   * @retval PCLK1 frequency in Hz
01202   */
01203 uint32_t HAL_RCC_GetPCLK1Freq(void)
01204 {
01205   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01206   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
01207 }
01208
01209 /**
01210   * @brief  Return the PCLK2 frequency.
01211   * @note   Each time PCLK2 changes, this function must be called to update the
01212   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
01213   * @retval PCLK2 frequency in Hz
01214   */
01215 uint32_t HAL_RCC_GetPCLK2Freq(void)
01216 {
01217   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
01218   return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
01219 }
01220
01221 /**
01222   * @brief  Configure the RCC_OscInitStruct according to the internal
01223   *         RCC configuration registers.
01224   * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
01225   *         will be configured.
01226   * @retval None
01227   */
01228 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
01229 {
01230   /* Check the parameters */
01231   assert_param(RCC_OscInitStruct != NULL);
01232
01233   /* Set all possible values for the Oscillator type parameter ---------------*/
01234 #if defined(RCC_HSI48_SUPPORT)
01235   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
01236                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
01237 #else
01238   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
01239                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
01240 #endif /* RCC_HSI48_SUPPORT */
01241
01242   /* Get the HSE configuration -----------------------------------------------*/
01243   if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
01244   {
01245     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
01246   }
01247   else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
01248   {
01249     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
01250   }
01251   else
01252   {
01253     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
01254   }
01255
01256    /* Get the MSI configuration -----------------------------------------------*/
01257   if((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION)
01258   {
01259     RCC_OscInitStruct->MSIState = RCC_MSI_ON;
01260   }
01261   else
01262   {
01263     RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
01264   }
01265
01266   RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM));
01267   RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_CR_MSIRANGE) );
01268
01269   /* Get the HSI configuration -----------------------------------------------*/
01270   if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
01271   {
01272     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
01273   }
01274   else
01275   {
01276     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
01277   }
01278
01279   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM));
01280
01281   /* Get the LSE configuration -----------------------------------------------*/
01282   if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
01283   {
01284     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01285   }
01286   else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01287   {
01288     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01289   }
01290   else
01291   {
01292     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01293   }
01294
01295   /* Get the LSI configuration -----------------------------------------------*/
01296   if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
01297   {
01298     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01299   }
01300   else
01301   {
01302     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01303   }
01304
01305 #if defined(RCC_HSI48_SUPPORT)
01306   /* Get the HSI48 configuration ---------------------------------------------*/
01307   if((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
01308   {
01309     RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
01310   }
01311   else
01312   {
01313     RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
01314   }
01315 #else
01316   RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
01317 #endif /* RCC_HSI48_SUPPORT */
01318
01319   /* Get the PLL configuration -----------------------------------------------*/
01320   if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
01321   {
01322     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01323   }
01324   else
01325   {
01326     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01327   }
01328   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
01329   RCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U);
01330   RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
01331   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
01332   RCC_OscInitStruct->PLL.PLLR = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U) << 1U);
01333 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
01334   RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV));
01335 #else
01336   if((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) != RESET)
01337   {
01338     RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17;
01339   }
01340   else
01341   {
01342     RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7;
01343   }
01344 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
01345 }
01346
01347 /**
01348   * @brief  Configure the RCC_ClkInitStruct according to the internal
01349   *         RCC configuration registers.
01350   * @param  RCC_ClkInitStruct  pointer to an RCC_ClkInitTypeDef structure that
01351   *         will be configured.
01352   * @param  pFLatency  Pointer on the Flash Latency.
01353   * @retval None
01354   */
01355 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01356 {
01357   /* Check the parameters */
01358   assert_param(RCC_ClkInitStruct != NULL);
01359   assert_param(pFLatency != NULL);
01360
01361   /* Set all possible values for the Clock type parameter --------------------*/
01362   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
01363
01364   /* Get the SYSCLK configuration --------------------------------------------*/
01365   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
01366
01367   /* Get the HCLK configuration ----------------------------------------------*/
01368   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
01369
01370   /* Get the APB1 configuration ----------------------------------------------*/
01371   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
01372
01373   /* Get the APB2 configuration ----------------------------------------------*/
01374   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
01375
01376   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01377   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
01378 }
01379
01380 /**
01381   * @brief  Enable the Clock Security System.
01382   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
01383   *         is automatically disabled and an interrupt is generated to inform the
01384   *         software about the failure (Clock Security System Interrupt, CSSI),
01385   *         allowing the MCU to perform rescue operations. The CSSI is linked to
01386   *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
01387   * @note   The Clock Security System can only be cleared by reset.
01388   * @retval None
01389   */
01390 void HAL_RCC_EnableCSS(void)
01391 {
01392   SET_BIT(RCC->CR, RCC_CR_CSSON) ;
01393 }
01394
01395 /**
01396   * @brief Handle the RCC Clock Security System interrupt request.
01397   * @note This API should be called under the NMI_Handler().
01398   * @retval None
01399   */
01400 void HAL_RCC_NMI_IRQHandler(void)
01401 {
01402   /* Check RCC CSSF interrupt flag  */
01403   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
01404   {
01405     /* RCC Clock Security System interrupt user callback */
01406     HAL_RCC_CSSCallback();
01407
01408     /* Clear RCC CSS pending bit */
01409     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
01410   }
01411 }
01412
01413 /**
01414   * @brief  RCC Clock Security System interrupt callback.
01415   * @retval none
01416   */
01417 __weak void HAL_RCC_CSSCallback(void)
01418 {
01419   /* NOTE : This function should not be modified, when the callback is needed,
01420             the HAL_RCC_CSSCallback should be implemented in the user file
01421    */
01422 }
01423
01424 /**
01425   * @}
01426   */
01427
01428 /**
01429   * @}
01430   */
01431
01432 /* Private function prototypes -----------------------------------------------*/
01433 /** @addtogroup RCC_Private_Functions
01434   * @{
01435   */
01436 /**
01437   * @brief  Update number of Flash wait states in line with MSI range and current
01438             voltage range.
01439   * @param  msirange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
01440   * @retval HAL status
01441   */
01442 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
01443 {
01444   uint32_t vos = 0;
01445   uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
01446
01447   if(__HAL_RCC_PWR_IS_CLK_ENABLED())
01448   {
01449     vos = HAL_PWREx_GetVoltageRange();
01450   }
01451   else
01452   {
01453     __HAL_RCC_PWR_CLK_ENABLE();
01454     vos = HAL_PWREx_GetVoltageRange();
01455     __HAL_RCC_PWR_CLK_DISABLE();
01456   }
01457
01458   if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
01459   {
01460     if(msirange > RCC_MSIRANGE_8)
01461     {
01462       /* MSI > 16Mhz */
01463       if(msirange > RCC_MSIRANGE_10)
01464       {
01465         /* MSI 48Mhz */
01466         latency = FLASH_LATENCY_2; /* 2WS */
01467       }
01468       else
01469       {
01470         /* MSI 24Mhz or 32Mhz */
01471         latency = FLASH_LATENCY_1; /* 1WS */
01472       }
01473     }
01474     /* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */
01475   }
01476   else
01477   {
01478     if(msirange > RCC_MSIRANGE_8)
01479     {
01480       /* MSI > 16Mhz */
01481       latency = FLASH_LATENCY_3; /* 3WS */
01482     }
01483     else
01484     {
01485       if(msirange == RCC_MSIRANGE_8)
01486       {
01487         /* MSI 16Mhz */
01488         latency = FLASH_LATENCY_2; /* 2WS */
01489       }
01490       else if(msirange == RCC_MSIRANGE_7)
01491       {
01492         /* MSI 8Mhz */
01493         latency = FLASH_LATENCY_1; /* 1WS */
01494       }
01495       /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
01496     }
01497   }
01498
01499   __HAL_FLASH_SET_LATENCY(latency);
01500
01501   /* Check that the new number of wait states is taken into account to access the Flash
01502      memory by reading the FLASH_ACR register */
01503   if((FLASH->ACR & FLASH_ACR_LATENCY) != latency)
01504   {
01505     return HAL_ERROR;
01506   }
01507
01508   return HAL_OK;
01509 }
01510
01511 /**
01512   * @}
01513   */
01514
01515 #endif /* HAL_RCC_MODULE_ENABLED */
01516 /**
01517   * @}
01518   */
01519
01520 /**
01521   * @}
01522   */
01523
01524 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rcc.h Source File

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stm32l4xx_hal_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rcc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of RCC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_RCC_H
00040 #define __STM32L4xx_HAL_RCC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RCC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RCC_Exported_Types RCC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  RCC PLL configuration structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t PLLState;   /*!< The new state of the PLL.
00068                             This parameter can be a value of @ref RCC_PLL_Config                      */
00069
00070   uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
00071                             This parameter must be a value of @ref RCC_PLL_Clock_Source               */
00072
00073   uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
00074                             This parameter must be a number between Min_Data = 1 and Max_Data = 8     */
00075
00076   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
00077                             This parameter must be a number between Min_Data = 8 and Max_Data = 86    */
00078
00079   uint32_t PLLP;       /*!< PLLP: Division factor for SAI clock.
00080                             This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
00081
00082   uint32_t PLLQ;       /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
00083                             This parameter must be a value of @ref RCC_PLLQ_Clock_Divider             */
00084
00085   uint32_t PLLR;       /*!< PLLR: Division for the main system clock.
00086                             User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
00087                             This parameter must be a value of @ref RCC_PLLR_Clock_Divider             */
00088
00089 }RCC_PLLInitTypeDef;
00090
00091 /**
00092   * @brief  RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
00093   */
00094 typedef struct
00095 {
00096   uint32_t OscillatorType;       /*!< The oscillators to be configured.
00097                                       This parameter can be a value of @ref RCC_Oscillator_Type                   */
00098
00099   uint32_t HSEState;             /*!< The new state of the HSE.
00100                                       This parameter can be a value of @ref RCC_HSE_Config                        */
00101
00102   uint32_t LSEState;             /*!< The new state of the LSE.
00103                                       This parameter can be a value of @ref RCC_LSE_Config                        */
00104
00105   uint32_t HSIState;             /*!< The new state of the HSI.
00106                                       This parameter can be a value of @ref RCC_HSI_Config                        */
00107
00108   uint32_t HSICalibrationValue;  /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
00109                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L47x/STM32L48x devices.
00110                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on STM32L43x/STM32L44x/STM32L49x/STM32L4Ax/ devices */
00111
00112   uint32_t LSIState;             /*!< The new state of the LSI.
00113                                       This parameter can be a value of @ref RCC_LSI_Config                        */
00114
00115   uint32_t MSIState;             /*!< The new state of the MSI.
00116                                       This parameter can be a value of @ref RCC_MSI_Config */
00117
00118   uint32_t MSICalibrationValue;  /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
00119                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00120
00121   uint32_t MSIClockRange;        /*!< The MSI frequency range.
00122                                       This parameter can be a value of @ref RCC_MSI_Clock_Range  */
00123
00124   uint32_t HSI48State;             /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices).
00125                                         This parameter can be a value of @ref RCC_HSI48_Config */
00126
00127   RCC_PLLInitTypeDef PLL;        /*!< Main PLL structure parameters                                               */
00128
00129 }RCC_OscInitTypeDef;
00130
00131 /**
00132   * @brief  RCC System, AHB and APB busses clock configuration structure definition
00133   */
00134 typedef struct
00135 {
00136   uint32_t ClockType;             /*!< The clock to be configured.
00137                                        This parameter can be a value of @ref RCC_System_Clock_Type      */
00138
00139   uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).
00140                                        This parameter can be a value of @ref RCC_System_Clock_Source    */
00141
00142   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00143                                        This parameter can be a value of @ref RCC_AHB_Clock_Source       */
00144
00145   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00146                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00147
00148   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00149                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00150
00151 }RCC_ClkInitTypeDef;
00152
00153 /**
00154   * @}
00155   */
00156
00157 /* Exported constants --------------------------------------------------------*/
00158 /** @defgroup RCC_Exported_Constants RCC Exported Constants
00159   * @{
00160   */
00161
00162 /** @defgroup RCC_Timeout_Value Timeout Values
00163   * @{
00164   */
00165 #define RCC_DBP_TIMEOUT_VALUE          ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
00166 #define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup RCC_Oscillator_Type Oscillator Type
00172   * @{
00173   */
00174 #define RCC_OSCILLATORTYPE_NONE        ((uint32_t)0x00000000U)   /*!< Oscillator configuration unchanged */
00175 #define RCC_OSCILLATORTYPE_HSE         ((uint32_t)0x00000001U)   /*!< HSE to configure */
00176 #define RCC_OSCILLATORTYPE_HSI         ((uint32_t)0x00000002U)   /*!< HSI to configure */
00177 #define RCC_OSCILLATORTYPE_LSE         ((uint32_t)0x00000004U)   /*!< LSE to configure */
00178 #define RCC_OSCILLATORTYPE_LSI         ((uint32_t)0x00000008U)   /*!< LSI to configure */
00179 #define RCC_OSCILLATORTYPE_MSI         ((uint32_t)0x00000010U)   /*!< MSI to configure */
00180 #if defined(RCC_HSI48_SUPPORT)
00181 #define RCC_OSCILLATORTYPE_HSI48       ((uint32_t)0x00000020U)   /*!< HSI48 to configure */
00182 #endif /* RCC_HSI48_SUPPORT */
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup RCC_HSE_Config HSE Config
00188   * @{
00189   */
00190 #define RCC_HSE_OFF                    ((uint32_t)0x00000000U)                     /*!< HSE clock deactivation */
00191 #define RCC_HSE_ON                     RCC_CR_HSEON                               /*!< HSE clock activation */
00192 #define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup RCC_LSE_Config LSE Config
00198   * @{
00199   */
00200 #define RCC_LSE_OFF                    ((uint32_t)0x00000000U)                         /*!< LSE clock deactivation */
00201 #define RCC_LSE_ON                     RCC_BDCR_LSEON                                 /*!< LSE clock activation */
00202 #define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup RCC_HSI_Config HSI Config
00208   * @{
00209   */
00210 #define RCC_HSI_OFF                    ((uint32_t)0x00000000U) /*!< HSI clock deactivation */
00211 #define RCC_HSI_ON                     RCC_CR_HSION           /*!< HSI clock activation */
00212
00213 #define RCC_HSICALIBRATION_DEFAULT     ((uint32_t)16)   /*!< Default HSI calibration trimming value */
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup RCC_LSI_Config LSI Config
00219   * @{
00220   */
00221 #define RCC_LSI_OFF                    ((uint32_t)0x00000000U) /*!< LSI clock deactivation */
00222 #define RCC_LSI_ON                     RCC_CSR_LSION          /*!< LSI clock activation */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup RCC_MSI_Config MSI Config
00228   * @{
00229   */
00230 #define RCC_MSI_OFF                    ((uint32_t)0x00000000U) /*!< MSI clock deactivation */
00231 #define RCC_MSI_ON                     RCC_CR_MSION           /*!< MSI clock activation */
00232
00233 #define RCC_MSICALIBRATION_DEFAULT     ((uint32_t)0)   /*!< Default MSI calibration trimming value */
00234 /**
00235   * @}
00236   */
00237
00238 #if defined(RCC_HSI48_SUPPORT)
00239 /** @defgroup RCC_HSI48_Config HSI48 Config
00240   * @{
00241   */
00242 #define RCC_HSI48_OFF                  ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
00243 #define RCC_HSI48_ON                   RCC_CRRCR_HSI48ON      /*!< HSI48 clock activation */
00244 /**
00245   * @}
00246   */
00247 #else
00248 /** @defgroup RCC_HSI48_Config HSI48 Config
00249   * @{
00250   */
00251 #define RCC_HSI48_OFF                  ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
00252 /**
00253   * @}
00254   */
00255 #endif /* RCC_HSI48_SUPPORT */
00256
00257 /** @defgroup RCC_PLL_Config PLL Config
00258   * @{
00259   */
00260 #define RCC_PLL_NONE                   ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */
00261 #define RCC_PLL_OFF                    ((uint32_t)0x00000001U) /*!< PLL deactivation */
00262 #define RCC_PLL_ON                     ((uint32_t)0x00000002U) /*!< PLL activation */
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
00268   * @{
00269   */
00270 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
00271 #define RCC_PLLP_DIV2                  ((uint32_t)0x00000002U) /*!< PLLP division factor = 2  */
00272 #define RCC_PLLP_DIV3                  ((uint32_t)0x00000003U) /*!< PLLP division factor = 3  */
00273 #define RCC_PLLP_DIV4                  ((uint32_t)0x00000004U) /*!< PLLP division factor = 4  */
00274 #define RCC_PLLP_DIV5                  ((uint32_t)0x00000005U) /*!< PLLP division factor = 5  */
00275 #define RCC_PLLP_DIV6                  ((uint32_t)0x00000006U) /*!< PLLP division factor = 6  */
00276 #define RCC_PLLP_DIV7                  ((uint32_t)0x00000007U) /*!< PLLP division factor = 7  */
00277 #define RCC_PLLP_DIV8                  ((uint32_t)0x00000008U) /*!< PLLP division factor = 8  */
00278 #define RCC_PLLP_DIV9                  ((uint32_t)0x00000009U) /*!< PLLP division factor = 9  */
00279 #define RCC_PLLP_DIV10                 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */
00280 #define RCC_PLLP_DIV11                 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */
00281 #define RCC_PLLP_DIV12                 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */
00282 #define RCC_PLLP_DIV13                 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */
00283 #define RCC_PLLP_DIV14                 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */
00284 #define RCC_PLLP_DIV15                 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */
00285 #define RCC_PLLP_DIV16                 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */
00286 #define RCC_PLLP_DIV17                 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
00287 #define RCC_PLLP_DIV18                 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */
00288 #define RCC_PLLP_DIV19                 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */
00289 #define RCC_PLLP_DIV20                 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */
00290 #define RCC_PLLP_DIV21                 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */
00291 #define RCC_PLLP_DIV22                 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */
00292 #define RCC_PLLP_DIV23                 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */
00293 #define RCC_PLLP_DIV24                 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */
00294 #define RCC_PLLP_DIV25                 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */
00295 #define RCC_PLLP_DIV26                 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */
00296 #define RCC_PLLP_DIV27                 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */
00297 #define RCC_PLLP_DIV28                 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */
00298 #define RCC_PLLP_DIV29                 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */
00299 #define RCC_PLLP_DIV30                 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */
00300 #define RCC_PLLP_DIV31                 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */
00301 #else
00302 #define RCC_PLLP_DIV7                  ((uint32_t)0x00000007U) /*!< PLLP division factor = 7  */
00303 #define RCC_PLLP_DIV17                 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
00304 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
00310   * @{
00311   */
00312 #define RCC_PLLQ_DIV2                  ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */
00313 #define RCC_PLLQ_DIV4                  ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */
00314 #define RCC_PLLQ_DIV6                  ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */
00315 #define RCC_PLLQ_DIV8                  ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
00321   * @{
00322   */
00323 #define RCC_PLLR_DIV2                  ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */
00324 #define RCC_PLLR_DIV4                  ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */
00325 #define RCC_PLLR_DIV6                  ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */
00326 #define RCC_PLLR_DIV8                  ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
00332   * @{
00333   */
00334 #define RCC_PLLSOURCE_NONE             ((uint32_t)0x00000000U)  /*!< No clock selected as PLL entry clock source  */
00335 #define RCC_PLLSOURCE_MSI              RCC_PLLCFGR_PLLSRC_MSI  /*!< MSI clock selected as PLL entry clock source */
00336 #define RCC_PLLSOURCE_HSI              RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI clock selected as PLL entry clock source */
00337 #define RCC_PLLSOURCE_HSE              RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output
00343   * @{
00344   */
00345 #if defined(RCC_PLLSAI2_SUPPORT)
00346 #define RCC_PLL_SAI3CLK                RCC_PLLCFGR_PLLPEN      /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */
00347 #else
00348 #define RCC_PLL_SAI2CLK                RCC_PLLCFGR_PLLPEN      /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */
00349 #endif /* RCC_PLLSAI2_SUPPORT */
00350 #define RCC_PLL_48M1CLK                RCC_PLLCFGR_PLLQEN      /*!< PLL48M1CLK selection from main PLL */
00351 #define RCC_PLL_SYSCLK                 RCC_PLLCFGR_PLLREN      /*!< PLLCLK selection from main PLL */
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
00357   * @{
00358   */
00359 #define RCC_PLLSAI1_SAI1CLK            RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */
00360 #define RCC_PLLSAI1_48M2CLK            RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */
00361 #define RCC_PLLSAI1_ADC1CLK            RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */
00362 /**
00363   * @}
00364   */
00365
00366 #if defined(RCC_PLLSAI2_SUPPORT)
00367
00368 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
00369   * @{
00370   */
00371 #define RCC_PLLSAI2_SAI2CLK            RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */
00372 #define RCC_PLLSAI2_ADC2CLK            RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */
00373 /**
00374   * @}
00375   */
00376
00377 #endif /* RCC_PLLSAI2_SUPPORT */
00378
00379 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range
00380   * @{
00381   */
00382 #define RCC_MSIRANGE_0                 RCC_CR_MSIRANGE_0  /*!< MSI = 100 KHz  */
00383 #define RCC_MSIRANGE_1                 RCC_CR_MSIRANGE_1  /*!< MSI = 200 KHz  */
00384 #define RCC_MSIRANGE_2                 RCC_CR_MSIRANGE_2  /*!< MSI = 400 KHz  */
00385 #define RCC_MSIRANGE_3                 RCC_CR_MSIRANGE_3  /*!< MSI = 800 KHz  */
00386 #define RCC_MSIRANGE_4                 RCC_CR_MSIRANGE_4  /*!< MSI = 1 MHz    */
00387 #define RCC_MSIRANGE_5                 RCC_CR_MSIRANGE_5  /*!< MSI = 2 MHz    */
00388 #define RCC_MSIRANGE_6                 RCC_CR_MSIRANGE_6  /*!< MSI = 4 MHz    */
00389 #define RCC_MSIRANGE_7                 RCC_CR_MSIRANGE_7  /*!< MSI = 8 MHz    */
00390 #define RCC_MSIRANGE_8                 RCC_CR_MSIRANGE_8  /*!< MSI = 16 MHz   */
00391 #define RCC_MSIRANGE_9                 RCC_CR_MSIRANGE_9  /*!< MSI = 24 MHz   */
00392 #define RCC_MSIRANGE_10                RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz   */
00393 #define RCC_MSIRANGE_11                RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz   */
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup RCC_System_Clock_Type System Clock Type
00399   * @{
00400   */
00401 #define RCC_CLOCKTYPE_SYSCLK           ((uint32_t)0x00000001U)  /*!< SYSCLK to configure */
00402 #define RCC_CLOCKTYPE_HCLK             ((uint32_t)0x00000002U)  /*!< HCLK to configure */
00403 #define RCC_CLOCKTYPE_PCLK1            ((uint32_t)0x00000004U)  /*!< PCLK1 to configure */
00404 #define RCC_CLOCKTYPE_PCLK2            ((uint32_t)0x00000008U)  /*!< PCLK2 to configure */
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup RCC_System_Clock_Source System Clock Source
00410   * @{
00411   */
00412 #define RCC_SYSCLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
00413 #define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
00414 #define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
00415 #define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
00421   * @{
00422   */
00423 #define RCC_SYSCLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
00424 #define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00425 #define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00426 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
00427 /**
00428   * @}
00429   */
00430
00431 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
00432   * @{
00433   */
00434 #define RCC_SYSCLK_DIV1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
00435 #define RCC_SYSCLK_DIV2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
00436 #define RCC_SYSCLK_DIV4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
00437 #define RCC_SYSCLK_DIV8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
00438 #define RCC_SYSCLK_DIV16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
00439 #define RCC_SYSCLK_DIV64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
00440 #define RCC_SYSCLK_DIV128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
00441 #define RCC_SYSCLK_DIV256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
00442 #define RCC_SYSCLK_DIV512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
00443 /**
00444   * @}
00445   */
00446
00447 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
00448   * @{
00449   */
00450 #define RCC_HCLK_DIV1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
00451 #define RCC_HCLK_DIV2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
00452 #define RCC_HCLK_DIV4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
00453 #define RCC_HCLK_DIV8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
00454 #define RCC_HCLK_DIV16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
00460   * @{
00461   */
00462 #define RCC_RTCCLKSOURCE_NO_CLK        ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */
00463 #define RCC_RTCCLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
00464 #define RCC_RTCCLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
00465 #define RCC_RTCCLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup RCC_MCO_Index MCO Index
00471   * @{
00472   */
00473 #define RCC_MCO1                       ((uint32_t)0x00000000U)
00474 #define RCC_MCO                        RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
00475 /**
00476   * @}
00477   */
00478
00479 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
00480   * @{
00481   */
00482 #define RCC_MCO1SOURCE_NOCLOCK         ((uint32_t)0x00000000U)                 /*!< MCO1 output disabled, no clock on MCO1 */
00483 #define RCC_MCO1SOURCE_SYSCLK          RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
00484 #define RCC_MCO1SOURCE_MSI             RCC_CFGR_MCOSEL_1                      /*!< MSI selection as MCO1 source */
00485 #define RCC_MCO1SOURCE_HSI             (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
00486 #define RCC_MCO1SOURCE_HSE             RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
00487 #define RCC_MCO1SOURCE_PLLCLK          (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< PLLCLK selection as MCO1 source */
00488 #define RCC_MCO1SOURCE_LSI             (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
00489 #define RCC_MCO1SOURCE_LSE             (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
00490 #if defined(RCC_HSI48_SUPPORT)
00491 #define RCC_MCO1SOURCE_HSI48           RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */
00492 #endif /* RCC_HSI48_SUPPORT */
00493 /**
00494   * @}
00495   */
00496
00497 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
00498   * @{
00499   */
00500 #define RCC_MCODIV_1                   RCC_CFGR_MCOPRE_DIV1     /*!< MCO not divided  */
00501 #define RCC_MCODIV_2                   RCC_CFGR_MCOPRE_DIV2     /*!< MCO divided by 2 */
00502 #define RCC_MCODIV_4                   RCC_CFGR_MCOPRE_DIV4     /*!< MCO divided by 4 */
00503 #define RCC_MCODIV_8                   RCC_CFGR_MCOPRE_DIV8     /*!< MCO divided by 8 */
00504 #define RCC_MCODIV_16                  RCC_CFGR_MCOPRE_DIV16    /*!< MCO divided by 16 */
00505 /**
00506   * @}
00507   */
00508
00509 /** @defgroup RCC_Interrupt Interrupts
00510   * @{
00511   */
00512 #define RCC_IT_LSIRDY                  RCC_CIFR_LSIRDYF      /*!< LSI Ready Interrupt flag */
00513 #define RCC_IT_LSERDY                  RCC_CIFR_LSERDYF      /*!< LSE Ready Interrupt flag */
00514 #define RCC_IT_MSIRDY                  RCC_CIFR_MSIRDYF      /*!< MSI Ready Interrupt flag */
00515 #define RCC_IT_HSIRDY                  RCC_CIFR_HSIRDYF      /*!< HSI16 Ready Interrupt flag */
00516 #define RCC_IT_HSERDY                  RCC_CIFR_HSERDYF      /*!< HSE Ready Interrupt flag */
00517 #define RCC_IT_PLLRDY                  RCC_CIFR_PLLRDYF      /*!< PLL Ready Interrupt flag */
00518 #define RCC_IT_PLLSAI1RDY              RCC_CIFR_PLLSAI1RDYF  /*!< PLLSAI1 Ready Interrupt flag */
00519 #if defined(RCC_PLLSAI2_SUPPORT)
00520 #define RCC_IT_PLLSAI2RDY              RCC_CIFR_PLLSAI2RDYF  /*!< PLLSAI2 Ready Interrupt flag */
00521 #endif /* RCC_PLLSAI2_SUPPORT */
00522 #define RCC_IT_CSS                     RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
00523 #define RCC_IT_LSECSS                  RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
00524 #if defined(RCC_HSI48_SUPPORT)
00525 #define RCC_IT_HSI48RDY                RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
00526 #endif /* RCC_HSI48_SUPPORT */
00527 /**
00528   * @}
00529   */
00530
00531 /** @defgroup RCC_Flag Flags
00532   *        Elements values convention: XXXYYYYYb
00533   *           - YYYYY  : Flag position in the register
00534   *           - XXX  : Register index
00535   *                 - 001: CR register
00536   *                 - 010: BDCR register
00537   *                 - 011: CSR register
00538   *                 - 100: CRRCR register
00539   * @{
00540   */
00541 /* Flags in the CR register */
00542 #define RCC_FLAG_MSIRDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */
00543 #define RCC_FLAG_HSIRDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */
00544 #define RCC_FLAG_HSERDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */
00545 #define RCC_FLAG_PLLRDY                ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */
00546 #define RCC_FLAG_PLLSAI1RDY            ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */
00547 #if defined(RCC_PLLSAI2_SUPPORT)
00548 #define RCC_FLAG_PLLSAI2RDY            ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */
00549 #endif /* RCC_PLLSAI2_SUPPORT */
00550
00551 /* Flags in the BDCR register */
00552 #define RCC_FLAG_LSERDY                ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */
00553 #define RCC_FLAG_LSECSSD               ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */
00554
00555 /* Flags in the CSR register */
00556 #define RCC_FLAG_LSIRDY                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< LSI Ready flag */
00557 #define RCC_FLAG_RMVF                  ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF)))     /*!< Remove reset flag */
00558 #define RCC_FLAG_FWRST                 ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF)))   /*!< Firewall reset flag */
00559 #define RCC_FLAG_OBLRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))  /*!< Option Byte Loader reset flag */
00560 #define RCC_FLAG_PINRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
00561 #define RCC_FLAG_BORRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF)))  /*!< BOR reset flag */
00562 #define RCC_FLAG_SFTRST                ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
00563 #define RCC_FLAG_IWDGRST               ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
00564 #define RCC_FLAG_WWDGRST               ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
00565 #define RCC_FLAG_LPWRRST               ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
00566
00567 #if defined(RCC_HSI48_SUPPORT)
00568 /* Flags in the CRRCR register */
00569 #define RCC_FLAG_HSI48RDY              ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */
00570 #endif /* RCC_HSI48_SUPPORT */
00571 /**
00572   * @}
00573   */
00574
00575 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
00576   * @{
00577   */
00578 #define RCC_LSEDRIVE_LOW                 ((uint32_t)0x00000000U) /*!< LSE low drive capability */
00579 #define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
00580 #define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */
00581 #define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
00582 /**
00583   * @}
00584   */
00585
00586 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
00587   * @{
00588   */
00589 #define RCC_STOP_WAKEUPCLOCK_MSI       ((uint32_t)0x00000000U)  /*!< MSI selection after wake-up from STOP */
00590 #define RCC_STOP_WAKEUPCLOCK_HSI       RCC_CFGR_STOPWUCK       /*!< HSI selection after wake-up from STOP */
00591 /**
00592   * @}
00593   */
00594
00595 /**
00596   * @}
00597   */
00598
00599 /* Exported macros -----------------------------------------------------------*/
00600
00601 /** @defgroup RCC_Exported_Macros RCC Exported Macros
00602   * @{
00603   */
00604
00605 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
00606   * @brief  Enable or disable the AHB1 peripheral clock.
00607   * @note   After reset, the peripheral clock (used for registers read/write access)
00608   *         is disabled and the application software has to enable this clock before
00609   *         using it.
00610   * @{
00611   */
00612
00613 #define __HAL_RCC_DMA1_CLK_ENABLE()            do { \
00614                                                  __IO uint32_t tmpreg; \
00615                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
00616                                                  /* Delay after an RCC peripheral clock enabling */ \
00617                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
00618                                                  UNUSED(tmpreg); \
00619                                                } while(0)
00620
00621 #define __HAL_RCC_DMA2_CLK_ENABLE()            do { \
00622                                                  __IO uint32_t tmpreg; \
00623                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
00624                                                  /* Delay after an RCC peripheral clock enabling */ \
00625                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
00626                                                  UNUSED(tmpreg); \
00627                                                } while(0)
00628
00629 #define __HAL_RCC_FLASH_CLK_ENABLE()           do { \
00630                                                  __IO uint32_t tmpreg; \
00631                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
00632                                                  /* Delay after an RCC peripheral clock enabling */ \
00633                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
00634                                                  UNUSED(tmpreg); \
00635                                                } while(0)
00636
00637 #define __HAL_RCC_CRC_CLK_ENABLE()             do { \
00638                                                  __IO uint32_t tmpreg; \
00639                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
00640                                                  /* Delay after an RCC peripheral clock enabling */ \
00641                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
00642                                                  UNUSED(tmpreg); \
00643                                                } while(0)
00644
00645 #define __HAL_RCC_TSC_CLK_ENABLE()             do { \
00646                                                  __IO uint32_t tmpreg; \
00647                                                  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
00648                                                  /* Delay after an RCC peripheral clock enabling */ \
00649                                                  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
00650                                                  UNUSED(tmpreg); \
00651                                                } while(0)
00652
00653
00654 #define __HAL_RCC_DMA1_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
00655
00656 #define __HAL_RCC_DMA2_CLK_DISABLE()           CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
00657
00658 #define __HAL_RCC_FLASH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
00659
00660 #define __HAL_RCC_CRC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
00661
00662 #define __HAL_RCC_TSC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
00663
00664 /**
00665   * @}
00666   */
00667
00668 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
00669   * @brief  Enable or disable the AHB2 peripheral clock.
00670   * @note   After reset, the peripheral clock (used for registers read/write access)
00671   *         is disabled and the application software has to enable this clock before
00672   *         using it.
00673   * @{
00674   */
00675
00676 #define __HAL_RCC_GPIOA_CLK_ENABLE()           do { \
00677                                                  __IO uint32_t tmpreg; \
00678                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
00679                                                  /* Delay after an RCC peripheral clock enabling */ \
00680                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
00681                                                  UNUSED(tmpreg); \
00682                                                } while(0)
00683
00684 #define __HAL_RCC_GPIOB_CLK_ENABLE()           do { \
00685                                                  __IO uint32_t tmpreg; \
00686                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
00687                                                  /* Delay after an RCC peripheral clock enabling */ \
00688                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
00689                                                  UNUSED(tmpreg); \
00690                                                } while(0)
00691
00692 #define __HAL_RCC_GPIOC_CLK_ENABLE()           do { \
00693                                                  __IO uint32_t tmpreg; \
00694                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
00695                                                  /* Delay after an RCC peripheral clock enabling */ \
00696                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
00697                                                  UNUSED(tmpreg); \
00698                                                } while(0)
00699
00700 #if defined(GPIOD)
00701 #define __HAL_RCC_GPIOD_CLK_ENABLE()           do { \
00702                                                  __IO uint32_t tmpreg; \
00703                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
00704                                                  /* Delay after an RCC peripheral clock enabling */ \
00705                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
00706                                                  UNUSED(tmpreg); \
00707                                                } while(0)
00708 #endif /* GPIOD */
00709
00710 #if defined(GPIOE)
00711 #define __HAL_RCC_GPIOE_CLK_ENABLE()           do { \
00712                                                  __IO uint32_t tmpreg; \
00713                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
00714                                                  /* Delay after an RCC peripheral clock enabling */ \
00715                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
00716                                                  UNUSED(tmpreg); \
00717                                                } while(0)
00718 #endif /* GPIOE */
00719
00720 #if defined(GPIOF)
00721 #define __HAL_RCC_GPIOF_CLK_ENABLE()           do { \
00722                                                  __IO uint32_t tmpreg; \
00723                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
00724                                                  /* Delay after an RCC peripheral clock enabling */ \
00725                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
00726                                                  UNUSED(tmpreg); \
00727                                                } while(0)
00728 #endif /* GPIOF */
00729
00730 #if defined(GPIOG)
00731 #define __HAL_RCC_GPIOG_CLK_ENABLE()           do { \
00732                                                  __IO uint32_t tmpreg; \
00733                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
00734                                                  /* Delay after an RCC peripheral clock enabling */ \
00735                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
00736                                                  UNUSED(tmpreg); \
00737                                                } while(0)
00738 #endif /* GPIOG */
00739
00740 #define __HAL_RCC_GPIOH_CLK_ENABLE()           do { \
00741                                                  __IO uint32_t tmpreg; \
00742                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
00743                                                  /* Delay after an RCC peripheral clock enabling */ \
00744                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
00745                                                  UNUSED(tmpreg); \
00746                                                } while(0)
00747
00748 #if defined(USB_OTG_FS)
00749 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()      do { \
00750                                                  __IO uint32_t tmpreg; \
00751                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
00752                                                  /* Delay after an RCC peripheral clock enabling */ \
00753                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
00754                                                  UNUSED(tmpreg); \
00755                                                } while(0)
00756 #endif /* USB_OTG_FS */
00757
00758 #define __HAL_RCC_ADC_CLK_ENABLE()             do { \
00759                                                  __IO uint32_t tmpreg; \
00760                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
00761                                                  /* Delay after an RCC peripheral clock enabling */ \
00762                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
00763                                                  UNUSED(tmpreg); \
00764                                                } while(0)
00765
00766 #if defined(AES)
00767 #define __HAL_RCC_AES_CLK_ENABLE()             do { \
00768                                                  __IO uint32_t tmpreg; \
00769                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
00770                                                  /* Delay after an RCC peripheral clock enabling */ \
00771                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
00772                                                  UNUSED(tmpreg); \
00773                                                } while(0)
00774 #endif /* AES */
00775
00776 #define __HAL_RCC_RNG_CLK_ENABLE()             do { \
00777                                                  __IO uint32_t tmpreg; \
00778                                                  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
00779                                                  /* Delay after an RCC peripheral clock enabling */ \
00780                                                  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
00781                                                  UNUSED(tmpreg); \
00782                                                } while(0)
00783
00784
00785 #define __HAL_RCC_GPIOA_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
00786
00787 #define __HAL_RCC_GPIOB_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
00788
00789 #define __HAL_RCC_GPIOC_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
00790
00791 #if defined(GPIOD)
00792 #define __HAL_RCC_GPIOD_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
00793 #endif /* GPIOD */
00794
00795 #if defined(GPIOE)
00796 #define __HAL_RCC_GPIOE_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
00797 #endif /* GPIOE */
00798
00799 #if defined(GPIOF)
00800 #define __HAL_RCC_GPIOF_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
00801 #endif /* GPIOF */
00802
00803 #if defined(GPIOG)
00804 #define __HAL_RCC_GPIOG_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
00805 #endif /* GPIOG */
00806
00807 #define __HAL_RCC_GPIOH_CLK_DISABLE()          CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
00808
00809 #if defined(USB_OTG_FS)
00810 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()     CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
00811 #endif /* USB_OTG_FS */
00812
00813 #define __HAL_RCC_ADC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
00814
00815 #if defined(AES)
00816 #define __HAL_RCC_AES_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
00817 #endif /* AES */
00818
00819 #define __HAL_RCC_RNG_CLK_DISABLE()            CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
00820
00821 /**
00822   * @}
00823   */
00824
00825 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
00826   * @brief  Enable or disable the AHB3 peripheral clock.
00827   * @note   After reset, the peripheral clock (used for registers read/write access)
00828   *         is disabled and the application software has to enable this clock before
00829   *         using it.
00830   * @{
00831   */
00832
00833 #if defined(FMC_BANK1)
00834 #define __HAL_RCC_FMC_CLK_ENABLE()             do { \
00835                                                  __IO uint32_t tmpreg; \
00836                                                  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
00837                                                  /* Delay after an RCC peripheral clock enabling */ \
00838                                                  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
00839                                                  UNUSED(tmpreg); \
00840                                                } while(0)
00841 #endif /* FMC_BANK1 */
00842
00843 #if defined(QUADSPI)
00844 #define __HAL_RCC_QSPI_CLK_ENABLE()            do { \
00845                                                  __IO uint32_t tmpreg; \
00846                                                  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
00847                                                  /* Delay after an RCC peripheral clock enabling */ \
00848                                                  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
00849                                                  UNUSED(tmpreg); \
00850                                                } while(0)
00851 #endif /* QUADSPI */
00852
00853
00854 #if defined(FMC_BANK1)
00855 #define __HAL_RCC_FMC_CLK_DISABLE()            CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
00856 #endif /* FMC_BANK1 */
00857
00858 #if defined(QUADSPI)
00859 #define __HAL_RCC_QSPI_CLK_DISABLE()           CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
00860 #endif /* QUADSPI */
00861
00862 /**
00863   * @}
00864   */
00865
00866 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
00867   * @brief  Enable or disable the APB1 peripheral clock.
00868   * @note   After reset, the peripheral clock (used for registers read/write access)
00869   *         is disabled and the application software has to enable this clock before
00870   *         using it.
00871   * @{
00872   */
00873
00874 #define __HAL_RCC_TIM2_CLK_ENABLE()            do { \
00875                                                  __IO uint32_t tmpreg; \
00876                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
00877                                                  /* Delay after an RCC peripheral clock enabling */ \
00878                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
00879                                                  UNUSED(tmpreg); \
00880                                                } while(0)
00881
00882 #if defined(TIM3)
00883 #define __HAL_RCC_TIM3_CLK_ENABLE()            do { \
00884                                                  __IO uint32_t tmpreg; \
00885                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
00886                                                  /* Delay after an RCC peripheral clock enabling */ \
00887                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
00888                                                  UNUSED(tmpreg); \
00889                                                } while(0)
00890 #endif /* TIM3 */
00891
00892 #if defined(TIM4)
00893 #define __HAL_RCC_TIM4_CLK_ENABLE()            do { \
00894                                                  __IO uint32_t tmpreg; \
00895                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
00896                                                  /* Delay after an RCC peripheral clock enabling */ \
00897                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
00898                                                  UNUSED(tmpreg); \
00899                                                } while(0)
00900 #endif /* TIM4 */
00901
00902 #if defined(TIM5)
00903 #define __HAL_RCC_TIM5_CLK_ENABLE()            do { \
00904                                                  __IO uint32_t tmpreg; \
00905                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
00906                                                  /* Delay after an RCC peripheral clock enabling */ \
00907                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
00908                                                  UNUSED(tmpreg); \
00909                                                } while(0)
00910 #endif /* TIM5 */
00911
00912 #define __HAL_RCC_TIM6_CLK_ENABLE()            do { \
00913                                                  __IO uint32_t tmpreg; \
00914                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
00915                                                  /* Delay after an RCC peripheral clock enabling */ \
00916                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
00917                                                  UNUSED(tmpreg); \
00918                                                } while(0)
00919
00920 #define __HAL_RCC_TIM7_CLK_ENABLE()            do { \
00921                                                  __IO uint32_t tmpreg; \
00922                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
00923                                                  /* Delay after an RCC peripheral clock enabling */ \
00924                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
00925                                                  UNUSED(tmpreg); \
00926                                                } while(0)
00927
00928 #if defined(LCD)
00929 #define __HAL_RCC_LCD_CLK_ENABLE()             do { \
00930                                                  __IO uint32_t tmpreg; \
00931                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
00932                                                  /* Delay after an RCC peripheral clock enabling */ \
00933                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
00934                                                  UNUSED(tmpreg); \
00935                                                } while(0)
00936 #endif /* LCD */
00937
00938 #if defined(RCC_APB1ENR1_RTCAPBEN)
00939 #define __HAL_RCC_RTCAPB_CLK_ENABLE()          do { \
00940                                                  __IO uint32_t tmpreg; \
00941                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
00942                                                  /* Delay after an RCC peripheral clock enabling */ \
00943                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
00944                                                  UNUSED(tmpreg); \
00945                                                } while(0)
00946 #endif /* RCC_APB1ENR1_RTCAPBEN */
00947
00948 #define __HAL_RCC_WWDG_CLK_ENABLE()            do { \
00949                                                  __IO uint32_t tmpreg; \
00950                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
00951                                                  /* Delay after an RCC peripheral clock enabling */ \
00952                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
00953                                                  UNUSED(tmpreg); \
00954                                                } while(0)
00955
00956 #if defined(SPI2)
00957 #define __HAL_RCC_SPI2_CLK_ENABLE()            do { \
00958                                                  __IO uint32_t tmpreg; \
00959                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
00960                                                  /* Delay after an RCC peripheral clock enabling */ \
00961                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
00962                                                  UNUSED(tmpreg); \
00963                                                } while(0)
00964 #endif /* SPI2 */
00965
00966 #define __HAL_RCC_SPI3_CLK_ENABLE()            do { \
00967                                                  __IO uint32_t tmpreg; \
00968                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
00969                                                  /* Delay after an RCC peripheral clock enabling */ \
00970                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
00971                                                  UNUSED(tmpreg); \
00972                                                } while(0)
00973
00974 #define __HAL_RCC_USART2_CLK_ENABLE()          do { \
00975                                                  __IO uint32_t tmpreg; \
00976                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
00977                                                  /* Delay after an RCC peripheral clock enabling */ \
00978                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
00979                                                  UNUSED(tmpreg); \
00980                                                } while(0)
00981
00982 #if defined(USART3)
00983 #define __HAL_RCC_USART3_CLK_ENABLE()          do { \
00984                                                  __IO uint32_t tmpreg; \
00985                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
00986                                                  /* Delay after an RCC peripheral clock enabling */ \
00987                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
00988                                                  UNUSED(tmpreg); \
00989                                                } while(0)
00990 #endif /* USART3 */
00991
00992 #if defined(UART4)
00993 #define __HAL_RCC_UART4_CLK_ENABLE()           do { \
00994                                                  __IO uint32_t tmpreg; \
00995                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
00996                                                  /* Delay after an RCC peripheral clock enabling */ \
00997                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
00998                                                  UNUSED(tmpreg); \
00999                                                } while(0)
01000 #endif /* UART4 */
01001
01002 #if defined(UART5)
01003 #define __HAL_RCC_UART5_CLK_ENABLE()           do { \
01004                                                  __IO uint32_t tmpreg; \
01005                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
01006                                                  /* Delay after an RCC peripheral clock enabling */ \
01007                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
01008                                                  UNUSED(tmpreg); \
01009                                                } while(0)
01010 #endif /* UART5 */
01011
01012 #define __HAL_RCC_I2C1_CLK_ENABLE()            do { \
01013                                                  __IO uint32_t tmpreg; \
01014                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
01015                                                  /* Delay after an RCC peripheral clock enabling */ \
01016                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
01017                                                  UNUSED(tmpreg); \
01018                                                } while(0)
01019
01020 #if defined(I2C2)
01021 #define __HAL_RCC_I2C2_CLK_ENABLE()            do { \
01022                                                  __IO uint32_t tmpreg; \
01023                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
01024                                                  /* Delay after an RCC peripheral clock enabling */ \
01025                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
01026                                                  UNUSED(tmpreg); \
01027                                                } while(0)
01028 #endif /* I2C2 */
01029
01030 #define __HAL_RCC_I2C3_CLK_ENABLE()            do { \
01031                                                  __IO uint32_t tmpreg; \
01032                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
01033                                                  /* Delay after an RCC peripheral clock enabling */ \
01034                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
01035                                                  UNUSED(tmpreg); \
01036                                                } while(0)
01037
01038 #if defined(CRS)
01039 #define __HAL_RCC_CRS_CLK_ENABLE()             do { \
01040                                                  __IO uint32_t tmpreg; \
01041                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
01042                                                  /* Delay after an RCC peripheral clock enabling */ \
01043                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
01044                                                  UNUSED(tmpreg); \
01045                                                } while(0)
01046 #endif /* CRS */
01047
01048 #define __HAL_RCC_CAN1_CLK_ENABLE()            do { \
01049                                                  __IO uint32_t tmpreg; \
01050                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
01051                                                  /* Delay after an RCC peripheral clock enabling */ \
01052                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
01053                                                  UNUSED(tmpreg); \
01054                                                } while(0)
01055
01056 #if defined(USB)
01057 #define __HAL_RCC_USB_CLK_ENABLE()             do { \
01058                                                  __IO uint32_t tmpreg; \
01059                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
01060                                                  /* Delay after an RCC peripheral clock enabling */ \
01061                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
01062                                                  UNUSED(tmpreg); \
01063                                                } while(0)
01064 #endif /* USB */
01065
01066 #define __HAL_RCC_PWR_CLK_ENABLE()             do { \
01067                                                  __IO uint32_t tmpreg; \
01068                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
01069                                                  /* Delay after an RCC peripheral clock enabling */ \
01070                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
01071                                                  UNUSED(tmpreg); \
01072                                                } while(0)
01073
01074 #define __HAL_RCC_DAC1_CLK_ENABLE()            do { \
01075                                                  __IO uint32_t tmpreg; \
01076                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
01077                                                  /* Delay after an RCC peripheral clock enabling */ \
01078                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
01079                                                  UNUSED(tmpreg); \
01080                                                } while(0)
01081
01082 #define __HAL_RCC_OPAMP_CLK_ENABLE()           do { \
01083                                                  __IO uint32_t tmpreg; \
01084                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
01085                                                  /* Delay after an RCC peripheral clock enabling */ \
01086                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
01087                                                  UNUSED(tmpreg); \
01088                                                } while(0)
01089
01090 #define __HAL_RCC_LPTIM1_CLK_ENABLE()          do { \
01091                                                  __IO uint32_t tmpreg; \
01092                                                  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
01093                                                  /* Delay after an RCC peripheral clock enabling */ \
01094                                                  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
01095                                                  UNUSED(tmpreg); \
01096                                                } while(0)
01097
01098 #define __HAL_RCC_LPUART1_CLK_ENABLE()         do { \
01099                                                  __IO uint32_t tmpreg; \
01100                                                  SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
01101                                                  /* Delay after an RCC peripheral clock enabling */ \
01102                                                  tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
01103                                                  UNUSED(tmpreg); \
01104                                                } while(0)
01105
01106 #define __HAL_RCC_SWPMI1_CLK_ENABLE()          do { \
01107                                                  __IO uint32_t tmpreg; \
01108                                                  SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
01109                                                  /* Delay after an RCC peripheral clock enabling */ \
01110                                                  tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
01111                                                  UNUSED(tmpreg); \
01112                                                } while(0)
01113
01114 #define __HAL_RCC_LPTIM2_CLK_ENABLE()          do { \
01115                                                  __IO uint32_t tmpreg; \
01116                                                  SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
01117                                                  /* Delay after an RCC peripheral clock enabling */ \
01118                                                  tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
01119                                                  UNUSED(tmpreg); \
01120                                                } while(0)
01121
01122
01123 #define __HAL_RCC_TIM2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
01124
01125 #if defined(TIM3)
01126 #define __HAL_RCC_TIM3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
01127 #endif /* TIM3 */
01128
01129 #if defined(TIM4)
01130 #define __HAL_RCC_TIM4_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
01131 #endif /* TIM4 */
01132
01133 #if defined(TIM5)
01134 #define __HAL_RCC_TIM5_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
01135 #endif /* TIM5 */
01136
01137 #define __HAL_RCC_TIM6_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
01138
01139 #define __HAL_RCC_TIM7_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
01140
01141 #if defined(LCD)
01142 #define __HAL_RCC_LCD_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
01143 #endif /* LCD */
01144
01145 #if defined(RCC_APB1ENR1_RTCAPBEN)
01146 #define __HAL_RCC_RTCAPB_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
01147 #endif /* RCC_APB1ENR1_RTCAPBEN */
01148
01149 #if defined(SPI2)
01150 #define __HAL_RCC_SPI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
01151 #endif /* SPI2 */
01152
01153 #define __HAL_RCC_SPI3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
01154
01155 #define __HAL_RCC_USART2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
01156
01157 #if defined(USART3)
01158 #define __HAL_RCC_USART3_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
01159 #endif /* USART3 */
01160
01161 #if defined(UART4)
01162 #define __HAL_RCC_UART4_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
01163 #endif /* UART4 */
01164
01165 #if defined(UART5)
01166 #define __HAL_RCC_UART5_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
01167 #endif /* UART5 */
01168
01169 #define __HAL_RCC_I2C1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
01170
01171 #if defined(I2C2)
01172 #define __HAL_RCC_I2C2_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
01173 #endif /* I2C2 */
01174
01175 #define __HAL_RCC_I2C3_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
01176
01177 #if defined(CRS)
01178 #define __HAL_RCC_CRS_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
01179 #endif /* CRS */
01180
01181 #define __HAL_RCC_CAN1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
01182
01183 #if defined(USB)
01184 #define __HAL_RCC_USB_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
01185 #endif /* USB */
01186
01187 #define __HAL_RCC_PWR_CLK_DISABLE()            CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
01188
01189 #define __HAL_RCC_DAC1_CLK_DISABLE()           CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
01190
01191 #define __HAL_RCC_OPAMP_CLK_DISABLE()          CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
01192
01193 #define __HAL_RCC_LPTIM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
01194
01195 #define __HAL_RCC_LPUART1_CLK_DISABLE()        CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
01196
01197 #define __HAL_RCC_SWPMI1_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
01198
01199 #define __HAL_RCC_LPTIM2_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
01200
01201 /**
01202   * @}
01203   */
01204
01205 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
01206   * @brief  Enable or disable the APB2 peripheral clock.
01207   * @note   After reset, the peripheral clock (used for registers read/write access)
01208   *         is disabled and the application software has to enable this clock before
01209   *         using it.
01210   * @{
01211   */
01212
01213 #define __HAL_RCC_SYSCFG_CLK_ENABLE()          do { \
01214                                                  __IO uint32_t tmpreg; \
01215                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
01216                                                  /* Delay after an RCC peripheral clock enabling */ \
01217                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
01218                                                  UNUSED(tmpreg); \
01219                                                } while(0)
01220
01221 #define __HAL_RCC_FIREWALL_CLK_ENABLE()        do { \
01222                                                  __IO uint32_t tmpreg; \
01223                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
01224                                                  /* Delay after an RCC peripheral clock enabling */ \
01225                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
01226                                                  UNUSED(tmpreg); \
01227                                                } while(0)
01228
01229 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
01230 #define __HAL_RCC_SDMMC1_CLK_ENABLE()          do { \
01231                                                  __IO uint32_t tmpreg; \
01232                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
01233                                                  /* Delay after an RCC peripheral clock enabling */ \
01234                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
01235                                                  UNUSED(tmpreg); \
01236                                                } while(0)
01237 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
01238
01239 #define __HAL_RCC_TIM1_CLK_ENABLE()            do { \
01240                                                  __IO uint32_t tmpreg; \
01241                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
01242                                                  /* Delay after an RCC peripheral clock enabling */ \
01243                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
01244                                                  UNUSED(tmpreg); \
01245                                                } while(0)
01246
01247 #define __HAL_RCC_SPI1_CLK_ENABLE()            do { \
01248                                                  __IO uint32_t tmpreg; \
01249                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
01250                                                  /* Delay after an RCC peripheral clock enabling */ \
01251                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
01252                                                  UNUSED(tmpreg); \
01253                                                } while(0)
01254
01255 #if defined(TIM8)
01256 #define __HAL_RCC_TIM8_CLK_ENABLE()            do { \
01257                                                  __IO uint32_t tmpreg; \
01258                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
01259                                                  /* Delay after an RCC peripheral clock enabling */ \
01260                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
01261                                                  UNUSED(tmpreg); \
01262                                                } while(0)
01263 #endif /* TIM8 */
01264
01265 #define __HAL_RCC_USART1_CLK_ENABLE()          do { \
01266                                                  __IO uint32_t tmpreg; \
01267                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
01268                                                  /* Delay after an RCC peripheral clock enabling */ \
01269                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
01270                                                  UNUSED(tmpreg); \
01271                                                } while(0)
01272
01273
01274 #define __HAL_RCC_TIM15_CLK_ENABLE()           do { \
01275                                                  __IO uint32_t tmpreg; \
01276                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
01277                                                  /* Delay after an RCC peripheral clock enabling */ \
01278                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
01279                                                  UNUSED(tmpreg); \
01280                                                } while(0)
01281
01282 #define __HAL_RCC_TIM16_CLK_ENABLE()           do { \
01283                                                  __IO uint32_t tmpreg; \
01284                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
01285                                                  /* Delay after an RCC peripheral clock enabling */ \
01286                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
01287                                                  UNUSED(tmpreg); \
01288                                                } while(0)
01289
01290 #if defined(TIM17)
01291 #define __HAL_RCC_TIM17_CLK_ENABLE()           do { \
01292                                                  __IO uint32_t tmpreg; \
01293                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
01294                                                  /* Delay after an RCC peripheral clock enabling */ \
01295                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
01296                                                  UNUSED(tmpreg); \
01297                                                } while(0)
01298 #endif /* TIM17 */
01299
01300 #define __HAL_RCC_SAI1_CLK_ENABLE()            do { \
01301                                                  __IO uint32_t tmpreg; \
01302                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
01303                                                  /* Delay after an RCC peripheral clock enabling */ \
01304                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
01305                                                  UNUSED(tmpreg); \
01306                                                } while(0)
01307
01308 #if defined(SAI2)
01309 #define __HAL_RCC_SAI2_CLK_ENABLE()            do { \
01310                                                  __IO uint32_t tmpreg; \
01311                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
01312                                                  /* Delay after an RCC peripheral clock enabling */ \
01313                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
01314                                                  UNUSED(tmpreg); \
01315                                                } while(0)
01316 #endif /* SAI2 */
01317
01318 #if defined(DFSDM1_Filter0)
01319 #define __HAL_RCC_DFSDM1_CLK_ENABLE()          do { \
01320                                                  __IO uint32_t tmpreg; \
01321                                                  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
01322                                                  /* Delay after an RCC peripheral clock enabling */ \
01323                                                  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
01324                                                  UNUSED(tmpreg); \
01325                                                } while(0)
01326 #endif /* DFSDM1_Filter0 */
01327
01328
01329 #define __HAL_RCC_SYSCFG_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
01330
01331 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
01332 #define __HAL_RCC_SDMMC1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
01333 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
01334
01335 #define __HAL_RCC_TIM1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
01336
01337 #define __HAL_RCC_SPI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
01338
01339 #if defined(TIM8)
01340 #define __HAL_RCC_TIM8_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
01341 #endif /* TIM8 */
01342
01343 #define __HAL_RCC_USART1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
01344
01345 #define __HAL_RCC_TIM15_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
01346
01347 #define __HAL_RCC_TIM16_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
01348
01349 #if defined(TIM17)
01350 #define __HAL_RCC_TIM17_CLK_DISABLE()          CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
01351 #endif /* TIM17 */
01352
01353 #define __HAL_RCC_SAI1_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
01354
01355 #if defined(SAI2)
01356 #define __HAL_RCC_SAI2_CLK_DISABLE()           CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
01357 #endif /* SAI2 */
01358
01359 #if defined(DFSDM1_Filter0)
01360 #define __HAL_RCC_DFSDM1_CLK_DISABLE()         CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
01361 #endif /* DFSDM1_Filter0 */
01362
01363 /**
01364   * @}
01365   */
01366
01367 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
01368   * @brief  Check whether the AHB1 peripheral clock is enabled or not.
01369   * @note   After reset, the peripheral clock (used for registers read/write access)
01370   *         is disabled and the application software has to enable this clock before
01371   *         using it.
01372   * @{
01373   */
01374
01375 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
01376
01377 #define __HAL_RCC_DMA2_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
01378
01379 #define __HAL_RCC_FLASH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
01380
01381 #define __HAL_RCC_CRC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
01382
01383 #define __HAL_RCC_TSC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
01384
01385
01386 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
01387
01388 #define __HAL_RCC_DMA2_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
01389
01390 #define __HAL_RCC_FLASH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
01391
01392 #define __HAL_RCC_CRC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
01393
01394 #define __HAL_RCC_TSC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
01395
01396 /**
01397   * @}
01398   */
01399
01400 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
01401   * @brief  Check whether the AHB2 peripheral clock is enabled or not.
01402   * @note   After reset, the peripheral clock (used for registers read/write access)
01403   *         is disabled and the application software has to enable this clock before
01404   *         using it.
01405   * @{
01406   */
01407
01408 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
01409
01410 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
01411
01412 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
01413
01414 #if defined(GPIOD)
01415 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
01416 #endif /* GPIOD */
01417
01418 #if defined(GPIOE)
01419 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
01420 #endif /* GPIOE */
01421
01422 #if defined(GPIOF)
01423 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
01424 #endif /* GPIOF */
01425
01426 #if defined(GPIOG)
01427 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
01428 #endif /* GPIOG */
01429
01430 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED()       (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
01431
01432 #if defined(USB_OTG_FS)
01433 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
01434 #endif /* USB_OTG_FS */
01435
01436 #define __HAL_RCC_ADC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
01437
01438 #if defined(AES)
01439 #define __HAL_RCC_AES_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
01440 #endif /* AES */
01441
01442 #define __HAL_RCC_RNG_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
01443
01444
01445 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
01446
01447 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
01448
01449 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
01450
01451 #if defined(GPIOD)
01452 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
01453 #endif /* GPIOD */
01454
01455 #if defined(GPIOE)
01456 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
01457 #endif /* GPIOE */
01458
01459 #if defined(GPIOF)
01460 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
01461 #endif /* GPIOF */
01462
01463 #if defined(GPIOG)
01464 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
01465 #endif /* GPIOG */
01466
01467 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED()      (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
01468
01469 #if defined(USB_OTG_FS)
01470 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
01471 #endif /* USB_OTG_FS */
01472
01473 #define __HAL_RCC_ADC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
01474
01475 #if defined(AES)
01476 #define __HAL_RCC_AES_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
01477 #endif /* AES */
01478
01479 #define __HAL_RCC_RNG_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
01480
01481 /**
01482   * @}
01483   */
01484
01485 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
01486   * @brief  Check whether the AHB3 peripheral clock is enabled or not.
01487   * @note   After reset, the peripheral clock (used for registers read/write access)
01488   *         is disabled and the application software has to enable this clock before
01489   *         using it.
01490   * @{
01491   */
01492
01493 #if defined(FMC_BANK1)
01494 #define __HAL_RCC_FMC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
01495 #endif /* FMC_BANK1 */
01496
01497 #if defined(QUADSPI)
01498 #define __HAL_RCC_QSPI_IS_CLK_ENABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
01499 #endif /* QUADSPI */
01500
01501 #if defined(FMC_BANK1)
01502 #define __HAL_RCC_FMC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
01503 #endif /* FMC_BANK1 */
01504
01505 #if defined(QUADSPI)
01506 #define __HAL_RCC_QSPI_IS_CLK_DISABLED()       (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
01507 #endif /* QUADSPI */
01508
01509 /**
01510   * @}
01511   */
01512
01513 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
01514   * @brief  Check whether the APB1 peripheral clock is enabled or not.
01515   * @note   After reset, the peripheral clock (used for registers read/write access)
01516   *         is disabled and the application software has to enable this clock before
01517   *         using it.
01518   * @{
01519   */
01520
01521 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
01522
01523 #if defined(TIM3)
01524 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
01525 #endif /* TIM3 */
01526
01527 #if defined(TIM4)
01528 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
01529 #endif /* TIM4 */
01530
01531 #if defined(TIM5)
01532 #define __HAL_RCC_TIM5_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
01533 #endif /* TIM5 */
01534
01535 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
01536
01537 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
01538
01539 #if defined(LCD)
01540 #define __HAL_RCC_LCD_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
01541 #endif /* LCD */
01542
01543 #if defined(RCC_APB1ENR1_RTCAPBEN)
01544 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET)
01545 #endif /* RCC_APB1ENR1_RTCAPBEN */
01546
01547 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
01548
01549 #if defined(SPI2)
01550 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
01551 #endif /* SPI2 */
01552
01553 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
01554
01555 #define __HAL_RCC_USART2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
01556
01557 #if defined(USART3)
01558 #define __HAL_RCC_USART3_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
01559 #endif /* USART3 */
01560
01561 #if defined(UART4)
01562 #define __HAL_RCC_UART4_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
01563 #endif /* UART4 */
01564
01565 #if defined(UART5)
01566 #define __HAL_RCC_UART5_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
01567 #endif /* UART5 */
01568
01569 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
01570
01571 #if defined(I2C2)
01572 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
01573 #endif /* I2C2 */
01574
01575 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
01576
01577 #if defined(CRS)
01578 #define __HAL_RCC_CRS_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET)
01579 #endif /* CRS */
01580
01581 #define __HAL_RCC_CAN1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
01582
01583 #if defined(USB)
01584 #define __HAL_RCC_USB_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET)
01585 #endif /* USB */
01586
01587 #define __HAL_RCC_PWR_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
01588
01589 #define __HAL_RCC_DAC1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
01590
01591 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
01592
01593 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
01594
01595 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
01596
01597 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
01598
01599 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()      (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
01600
01601
01602 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
01603
01604 #if defined(TIM3)
01605 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
01606 #endif /* TIM3 */
01607
01608 #if defined(TIM4)
01609 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
01610 #endif /* TIM4 */
01611
01612 #if defined(TIM5)
01613 #define __HAL_RCC_TIM5_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
01614 #endif /* TIM5 */
01615
01616 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
01617
01618 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
01619
01620 #if defined(LCD)
01621 #define __HAL_RCC_LCD_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
01622 #endif /* LCD */
01623
01624 #if defined(RCC_APB1ENR1_RTCAPBEN)
01625 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET)
01626 #endif /* RCC_APB1ENR1_RTCAPBEN */
01627
01628 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
01629
01630 #if defined(SPI2)
01631 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
01632 #endif /* SPI2 */
01633
01634 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
01635
01636 #define __HAL_RCC_USART2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
01637
01638 #if defined(USART3)
01639 #define __HAL_RCC_USART3_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
01640 #endif /* USART3 */
01641
01642 #if defined(UART4)
01643 #define __HAL_RCC_UART4_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
01644 #endif /* UART4 */
01645
01646 #if defined(UART5)
01647 #define __HAL_RCC_UART5_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
01648 #endif /* UART5 */
01649
01650 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
01651
01652 #if defined(I2C2)
01653 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
01654 #endif /* I2C2 */
01655
01656 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
01657
01658 #if defined(CRS)
01659 #define __HAL_RCC_CRS_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET)
01660 #endif /* CRS */
01661
01662 #define __HAL_RCC_CAN1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
01663
01664 #if defined(USB)
01665 #define __HAL_RCC_USB_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET)
01666 #endif /* USB */
01667
01668 #define __HAL_RCC_PWR_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
01669
01670 #define __HAL_RCC_DAC1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
01671
01672 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED()      (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
01673
01674 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
01675
01676 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED()    (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
01677
01678 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
01679
01680 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
01681
01682 /**
01683   * @}
01684   */
01685
01686 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
01687   * @brief  Check whether the APB2 peripheral clock is enabled or not.
01688   * @note   After reset, the peripheral clock (used for registers read/write access)
01689   *         is disabled and the application software has to enable this clock before
01690   *         using it.
01691   * @{
01692   */
01693
01694 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
01695
01696 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
01697
01698 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
01699 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
01700 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
01701
01702 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
01703
01704 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
01705
01706 #if defined(TIM8)
01707 #define __HAL_RCC_TIM8_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
01708 #endif /* TIM8 */
01709
01710 #define __HAL_RCC_USART1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
01711
01712 #define __HAL_RCC_TIM15_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
01713
01714 #define __HAL_RCC_TIM16_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
01715
01716 #if defined(TIM17)
01717 #define __HAL_RCC_TIM17_IS_CLK_ENABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
01718 #endif /* TIM17 */
01719
01720 #define __HAL_RCC_SAI1_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
01721
01722 #if defined(SAI2)
01723 #define __HAL_RCC_SAI2_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
01724 #endif /* SAI2 */
01725
01726 #if defined(DFSDM1_Filter0)
01727 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
01728 #endif /* DFSDM1_Filter0 */
01729
01730
01731 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
01732
01733 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
01734 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
01735 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
01736
01737 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
01738
01739 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
01740
01741 #if defined(TIM8)
01742 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
01743 #endif /* TIM8 */
01744
01745 #define __HAL_RCC_USART1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
01746
01747 #define __HAL_RCC_TIM15_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
01748
01749 #define __HAL_RCC_TIM16_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
01750
01751 #if defined(TIM17)
01752 #define __HAL_RCC_TIM17_IS_CLK_DISABLED()      (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
01753 #endif /* TIM17 */
01754
01755 #define __HAL_RCC_SAI1_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
01756
01757 #if defined(SAI2)
01758 #define __HAL_RCC_SAI2_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
01759 #endif /* SAI2 */
01760
01761 #if defined(DFSDM1_Filter0)
01762 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()     (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)
01763 #endif /* DFSDM1_Filter0 */
01764
01765 /**
01766   * @}
01767   */
01768
01769 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
01770   * @brief  Force or release AHB1 peripheral reset.
01771   * @{
01772   */
01773 #define __HAL_RCC_AHB1_FORCE_RESET()           WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
01774
01775 #define __HAL_RCC_DMA1_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
01776
01777 #define __HAL_RCC_DMA2_FORCE_RESET()           SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
01778
01779 #define __HAL_RCC_FLASH_FORCE_RESET()          SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
01780
01781 #define __HAL_RCC_CRC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
01782
01783 #define __HAL_RCC_TSC_FORCE_RESET()            SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
01784
01785
01786 #define __HAL_RCC_AHB1_RELEASE_RESET()         WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
01787
01788 #define __HAL_RCC_DMA1_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
01789
01790 #define __HAL_RCC_DMA2_RELEASE_RESET()         CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
01791
01792 #define __HAL_RCC_FLASH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
01793
01794 #define __HAL_RCC_CRC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
01795
01796 #define __HAL_RCC_TSC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
01797
01798 /**
01799   * @}
01800   */
01801
01802 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
01803   * @brief  Force or release AHB2 peripheral reset.
01804   * @{
01805   */
01806 #define __HAL_RCC_AHB2_FORCE_RESET()           WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
01807
01808 #define __HAL_RCC_GPIOA_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
01809
01810 #define __HAL_RCC_GPIOB_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
01811
01812 #define __HAL_RCC_GPIOC_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
01813
01814 #if defined(GPIOD)
01815 #define __HAL_RCC_GPIOD_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
01816 #endif /* GPIOD */
01817
01818 #if defined(GPIOE)
01819 #define __HAL_RCC_GPIOE_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
01820 #endif /* GPIOE */
01821
01822 #if defined(GPIOF)
01823 #define __HAL_RCC_GPIOF_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
01824 #endif /* GPIOF */
01825
01826 #if defined(GPIOG)
01827 #define __HAL_RCC_GPIOG_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
01828 #endif /* GPIOG */
01829
01830 #define __HAL_RCC_GPIOH_FORCE_RESET()          SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
01831
01832 #if defined(USB_OTG_FS)
01833 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()     SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
01834 #endif /* USB_OTG_FS */
01835
01836 #define __HAL_RCC_ADC_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
01837
01838 #if defined(AES)
01839 #define __HAL_RCC_AES_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
01840 #endif /* AES */
01841
01842 #define __HAL_RCC_RNG_FORCE_RESET()            SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
01843
01844
01845 #define __HAL_RCC_AHB2_RELEASE_RESET()         WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
01846
01847 #define __HAL_RCC_GPIOA_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
01848
01849 #define __HAL_RCC_GPIOB_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
01850
01851 #define __HAL_RCC_GPIOC_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
01852
01853 #if defined(GPIOD)
01854 #define __HAL_RCC_GPIOD_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
01855 #endif /* GPIOD */
01856
01857 #if defined(GPIOE)
01858 #define __HAL_RCC_GPIOE_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
01859 #endif /* GPIOE */
01860
01861 #if defined(GPIOF)
01862 #define __HAL_RCC_GPIOF_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
01863 #endif /* GPIOF */
01864
01865 #if defined(GPIOG)
01866 #define __HAL_RCC_GPIOG_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
01867 #endif /* GPIOG */
01868
01869 #define __HAL_RCC_GPIOH_RELEASE_RESET()        CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
01870
01871 #if defined(USB_OTG_FS)
01872 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()   CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
01873 #endif /* USB_OTG_FS */
01874
01875 #define __HAL_RCC_ADC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
01876
01877 #if defined(AES)
01878 #define __HAL_RCC_AES_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
01879 #endif /* AES */
01880
01881 #define __HAL_RCC_RNG_RELEASE_RESET()          CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
01882
01883 /**
01884   * @}
01885   */
01886
01887 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
01888   * @brief  Force or release AHB3 peripheral reset.
01889   * @{
01890   */
01891 #define __HAL_RCC_AHB3_FORCE_RESET()           WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
01892
01893 #if defined(FMC_BANK1)
01894 #define __HAL_RCC_FMC_FORCE_RESET()            SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
01895 #endif /* FMC_BANK1 */
01896
01897 #if defined(QUADSPI)
01898 #define __HAL_RCC_QSPI_FORCE_RESET()           SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
01899 #endif /* QUADSPI */
01900
01901
01902 #define __HAL_RCC_AHB3_RELEASE_RESET()         WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
01903
01904 #if defined(FMC_BANK1)
01905 #define __HAL_RCC_FMC_RELEASE_RESET()          CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
01906 #endif /* FMC_BANK1 */
01907
01908 #if defined(QUADSPI)
01909 #define __HAL_RCC_QSPI_RELEASE_RESET()         CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
01910 #endif /* QUADSPI */
01911
01912 /**
01913   * @}
01914   */
01915
01916 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
01917   * @brief  Force or release APB1 peripheral reset.
01918   * @{
01919   */
01920 #define __HAL_RCC_APB1_FORCE_RESET()           WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
01921
01922 #define __HAL_RCC_TIM2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
01923
01924 #if defined(TIM3)
01925 #define __HAL_RCC_TIM3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
01926 #endif /* TIM3 */
01927
01928 #if defined(TIM4)
01929 #define __HAL_RCC_TIM4_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
01930 #endif /* TIM4 */
01931
01932 #if defined(TIM5)
01933 #define __HAL_RCC_TIM5_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
01934 #endif /* TIM5 */
01935
01936 #define __HAL_RCC_TIM6_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
01937
01938 #define __HAL_RCC_TIM7_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
01939
01940 #if defined(LCD)
01941 #define __HAL_RCC_LCD_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
01942 #endif /* LCD */
01943
01944 #if defined(SPI2)
01945 #define __HAL_RCC_SPI2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
01946 #endif /* SPI2 */
01947
01948 #define __HAL_RCC_SPI3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
01949
01950 #define __HAL_RCC_USART2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
01951
01952 #if defined(USART3)
01953 #define __HAL_RCC_USART3_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
01954 #endif /* USART3 */
01955
01956 #if defined(UART4)
01957 #define __HAL_RCC_UART4_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
01958 #endif /* UART4 */
01959
01960 #if defined(UART5)
01961 #define __HAL_RCC_UART5_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
01962 #endif /* UART5 */
01963
01964 #define __HAL_RCC_I2C1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
01965
01966 #if defined(I2C2)
01967 #define __HAL_RCC_I2C2_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
01968 #endif /* I2C2 */
01969
01970 #define __HAL_RCC_I2C3_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
01971
01972 #if defined(CRS)
01973 #define __HAL_RCC_CRS_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
01974 #endif /* CRS */
01975
01976 #define __HAL_RCC_CAN1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
01977
01978 #if defined(USB)
01979 #define __HAL_RCC_USB_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
01980 #endif /* USB */
01981
01982 #define __HAL_RCC_PWR_FORCE_RESET()            SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
01983
01984 #define __HAL_RCC_DAC1_FORCE_RESET()           SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
01985
01986 #define __HAL_RCC_OPAMP_FORCE_RESET()          SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
01987
01988 #define __HAL_RCC_LPTIM1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
01989
01990 #define __HAL_RCC_LPUART1_FORCE_RESET()        SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
01991
01992 #define __HAL_RCC_SWPMI1_FORCE_RESET()         SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
01993
01994 #define __HAL_RCC_LPTIM2_FORCE_RESET()         SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
01995
01996
01997 #define __HAL_RCC_APB1_RELEASE_RESET()         WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
01998
01999 #define __HAL_RCC_TIM2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
02000
02001 #if defined(TIM3)
02002 #define __HAL_RCC_TIM3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
02003 #endif /* TIM3 */
02004
02005 #if defined(TIM4)
02006 #define __HAL_RCC_TIM4_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
02007 #endif /* TIM4 */
02008
02009 #if defined(TIM5)
02010 #define __HAL_RCC_TIM5_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
02011 #endif /* TIM5 */
02012
02013 #define __HAL_RCC_TIM6_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
02014
02015 #define __HAL_RCC_TIM7_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
02016
02017 #if defined(LCD)
02018 #define __HAL_RCC_LCD_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
02019 #endif /* LCD */
02020
02021 #if defined(SPI2)
02022 #define __HAL_RCC_SPI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
02023 #endif /* SPI2 */
02024
02025 #define __HAL_RCC_SPI3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
02026
02027 #define __HAL_RCC_USART2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
02028
02029 #if defined(USART3)
02030 #define __HAL_RCC_USART3_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
02031 #endif /* USART3 */
02032
02033 #if defined(UART4)
02034 #define __HAL_RCC_UART4_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
02035 #endif /* UART4 */
02036
02037 #if defined(UART5)
02038 #define __HAL_RCC_UART5_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
02039 #endif /* UART5 */
02040
02041 #define __HAL_RCC_I2C1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
02042
02043 #if defined(I2C2)
02044 #define __HAL_RCC_I2C2_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
02045 #endif /* I2C2 */
02046
02047 #define __HAL_RCC_I2C3_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
02048
02049 #if defined(CRS)
02050 #define __HAL_RCC_CRS_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
02051 #endif /* CRS */
02052
02053 #define __HAL_RCC_CAN1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
02054
02055 #if defined(USB)
02056 #define __HAL_RCC_USB_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
02057 #endif /* USB */
02058
02059 #define __HAL_RCC_PWR_RELEASE_RESET()          CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
02060
02061 #define __HAL_RCC_DAC1_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
02062
02063 #define __HAL_RCC_OPAMP_RELEASE_RESET()        CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
02064
02065 #define __HAL_RCC_LPTIM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
02066
02067 #define __HAL_RCC_LPUART1_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
02068
02069 #define __HAL_RCC_SWPMI1_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
02070
02071 #define __HAL_RCC_LPTIM2_RELEASE_RESET()       CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
02072
02073 /**
02074   * @}
02075   */
02076
02077 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
02078   * @brief  Force or release APB2 peripheral reset.
02079   * @{
02080   */
02081 #define __HAL_RCC_APB2_FORCE_RESET()           WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
02082
02083 #define __HAL_RCC_SYSCFG_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
02084
02085 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
02086 #define __HAL_RCC_SDMMC1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
02087 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
02088
02089 #define __HAL_RCC_TIM1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
02090
02091 #define __HAL_RCC_SPI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
02092
02093 #if defined(TIM8)
02094 #define __HAL_RCC_TIM8_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
02095 #endif /* TIM8 */
02096
02097 #define __HAL_RCC_USART1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
02098
02099 #define __HAL_RCC_TIM15_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
02100
02101 #define __HAL_RCC_TIM16_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
02102
02103 #if defined(TIM17)
02104 #define __HAL_RCC_TIM17_FORCE_RESET()          SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
02105 #endif /* TIM17 */
02106
02107 #define __HAL_RCC_SAI1_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
02108
02109 #if defined(SAI2)
02110 #define __HAL_RCC_SAI2_FORCE_RESET()           SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
02111 #endif /* SAI2 */
02112
02113 #if defined(DFSDM1_Filter0)
02114 #define __HAL_RCC_DFSDM1_FORCE_RESET()         SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
02115 #endif /* DFSDM1_Filter0 */
02116
02117
02118 #define __HAL_RCC_APB2_RELEASE_RESET()         WRITE_REG(RCC->APB2RSTR, 0x00000000U)
02119
02120 #define __HAL_RCC_SYSCFG_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
02121
02122 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
02123 #define __HAL_RCC_SDMMC1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
02124 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
02125
02126 #define __HAL_RCC_TIM1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
02127
02128 #define __HAL_RCC_SPI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
02129
02130 #if defined(TIM8)
02131 #define __HAL_RCC_TIM8_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
02132 #endif /* TIM8 */
02133
02134 #define __HAL_RCC_USART1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
02135
02136 #define __HAL_RCC_TIM15_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
02137
02138 #define __HAL_RCC_TIM16_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
02139
02140 #if defined(TIM17)
02141 #define __HAL_RCC_TIM17_RELEASE_RESET()        CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
02142 #endif /* TIM17 */
02143
02144 #define __HAL_RCC_SAI1_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
02145
02146 #if defined(SAI2)
02147 #define __HAL_RCC_SAI2_RELEASE_RESET()         CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
02148 #endif /* SAI2 */
02149
02150 #if defined(DFSDM1_Filter0)
02151 #define __HAL_RCC_DFSDM1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
02152 #endif /* DFSDM1_Filter0 */
02153
02154 /**
02155   * @}
02156   */
02157
02158 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
02159   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
02160   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02161   *         power consumption.
02162   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02163   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02164   * @{
02165   */
02166
02167 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
02168
02169 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
02170
02171 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
02172
02173 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
02174
02175 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
02176
02177 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
02178
02179
02180 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
02181
02182 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
02183
02184 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
02185
02186 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
02187
02188 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
02189
02190 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
02191
02192 /**
02193   * @}
02194   */
02195
02196 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
02197   * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
02198   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02199   *         power consumption.
02200   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02201   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02202   * @{
02203   */
02204
02205 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
02206
02207 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
02208
02209 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
02210
02211 #if defined(GPIOD)
02212 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
02213 #endif /* GPIOD */
02214
02215 #if defined(GPIOE)
02216 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
02217 #endif /* GPIOE */
02218
02219 #if defined(GPIOF)
02220 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
02221 #endif /* GPIOF */
02222
02223 #if defined(GPIOG)
02224 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
02225 #endif /* GPIOG */
02226
02227 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
02228
02229 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
02230
02231 #if defined(USB_OTG_FS)
02232 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
02233 #endif /* USB_OTG_FS */
02234
02235 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
02236
02237 #if defined(AES)
02238 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
02239 #endif /* AES */
02240
02241 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
02242
02243
02244 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
02245
02246 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
02247
02248 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
02249
02250 #if defined(GPIOD)
02251 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
02252 #endif /* GPIOD */
02253
02254 #if defined(GPIOE)
02255 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
02256 #endif /* GPIOE */
02257
02258 #if defined(GPIOF)
02259 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
02260 #endif /* GPIOF */
02261
02262 #if defined(GPIOG)
02263 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
02264 #endif /* GPIOG */
02265
02266 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
02267
02268 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
02269
02270 #if defined(USB_OTG_FS)
02271 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
02272 #endif /* USB_OTG_FS */
02273
02274 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
02275
02276 #if defined(AES)
02277 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
02278 #endif /* AES */
02279
02280 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
02281
02282 /**
02283   * @}
02284   */
02285
02286 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
02287   * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
02288   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02289   *         power consumption.
02290   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02291   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02292   * @{
02293   */
02294
02295 #if defined(QUADSPI)
02296 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
02297 #endif /* QUADSPI */
02298
02299 #if defined(FMC_BANK1)
02300 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()       SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
02301 #endif /* FMC_BANK1 */
02302
02303
02304 #if defined(QUADSPI)
02305 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
02306 #endif /* QUADSPI */
02307
02308 #if defined(FMC_BANK1)
02309 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
02310 #endif /* FMC_BANK1 */
02311
02312 /**
02313   * @}
02314   */
02315
02316 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
02317   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
02318   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02319   *         power consumption.
02320   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02321   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02322   * @{
02323   */
02324
02325 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
02326
02327 #if defined(TIM3)
02328 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
02329 #endif /* TIM3 */
02330
02331 #if defined(TIM4)
02332 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
02333 #endif /* TIM4 */
02334
02335 #if defined(TIM5)
02336 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
02337 #endif /* TIM5 */
02338
02339 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
02340
02341 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
02342
02343 #if defined(LCD)
02344 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
02345 #endif /* LCD */
02346
02347 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
02348 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
02349 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
02350
02351 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
02352
02353 #if defined(SPI2)
02354 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
02355 #endif /* SPI2 */
02356
02357 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
02358
02359 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
02360
02361 #if defined(USART3)
02362 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
02363 #endif /* USART3 */
02364
02365 #if defined(UART4)
02366 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
02367 #endif /* UART4 */
02368
02369 #if defined(UART5)
02370 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
02371 #endif /* UART5 */
02372
02373 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
02374
02375 #if defined(I2C2)
02376 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
02377 #endif /* I2C2 */
02378
02379 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
02380
02381 #if defined(CRS)
02382 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
02383 #endif /* CRS */
02384
02385 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
02386
02387 #if defined(USB)
02388 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
02389 #endif /* USB */
02390
02391 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()       SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
02392
02393 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
02394
02395 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
02396
02397 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
02398
02399 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
02400
02401 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
02402
02403 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
02404
02405
02406 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
02407
02408 #if defined(TIM3)
02409 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
02410 #endif /* TIM3 */
02411
02412 #if defined(TIM4)
02413 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
02414 #endif /* TIM4 */
02415
02416 #if defined(TIM5)
02417 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
02418 #endif /* TIM5 */
02419
02420 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
02421
02422 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
02423
02424 #if defined(LCD)
02425 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
02426 #endif /* LCD */
02427
02428 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
02429 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
02430 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
02431
02432 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
02433
02434 #if defined(SPI2)
02435 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
02436 #endif /* SPI2 */
02437
02438 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
02439
02440 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
02441
02442 #if defined(USART3)
02443 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
02444 #endif /* USART3 */
02445
02446 #if defined(UART4)
02447 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
02448 #endif /* UART4 */
02449
02450 #if defined(UART5)
02451 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
02452 #endif /* UART5 */
02453
02454 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
02455
02456 #if defined(I2C2)
02457 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
02458 #endif /* I2C2 */
02459
02460 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
02461
02462 #if defined(CRS)
02463 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
02464 #endif /* CRS */
02465
02466 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
02467
02468 #if defined(USB)
02469 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
02470 #endif /* USB */
02471
02472 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()      CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
02473
02474 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
02475
02476 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
02477
02478 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
02479
02480 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
02481
02482 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
02483
02484 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
02485
02486 /**
02487   * @}
02488   */
02489
02490 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
02491   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
02492   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02493   *         power consumption.
02494   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02495   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02496   * @{
02497   */
02498
02499 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
02500
02501 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
02502 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
02503 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
02504
02505 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
02506
02507 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
02508
02509 #if defined(TIM8)
02510 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
02511 #endif /* TIM8 */
02512
02513 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
02514
02515 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
02516
02517 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
02518
02519 #if defined(TIM17)
02520 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
02521 #endif /* TIM17 */
02522
02523 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
02524
02525 #if defined(SAI2)
02526 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
02527 #endif /* SAI2 */
02528
02529 #if defined(DFSDM1_Filter0)
02530 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
02531 #endif /* DFSDM1_Filter0 */
02532
02533
02534 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
02535
02536 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
02537 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
02538 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
02539
02540 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
02541
02542 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
02543
02544 #if defined(TIM8)
02545 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
02546 #endif /* TIM8 */
02547
02548 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
02549
02550 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
02551
02552 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
02553
02554 #if defined(TIM17)
02555 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
02556 #endif /* TIM17 */
02557
02558 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
02559
02560 #if defined(SAI2)
02561 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
02562 #endif /* SAI2 */
02563
02564 #if defined(DFSDM1_Filter0)
02565 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
02566 #endif /* DFSDM1_Filter0 */
02567
02568 /**
02569   * @}
02570   */
02571
02572 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
02573   * @brief  Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
02574   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02575   *         power consumption.
02576   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02577   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02578   * @{
02579   */
02580
02581 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
02582
02583 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
02584
02585 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
02586
02587 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
02588
02589 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
02590
02591 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
02592
02593
02594 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
02595
02596 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
02597
02598 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
02599
02600 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
02601
02602 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
02603
02604 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
02605
02606 /**
02607   * @}
02608   */
02609
02610 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
02611   * @brief  Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
02612   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02613   *         power consumption.
02614   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02615   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02616   * @{
02617   */
02618
02619 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
02620
02621 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
02622
02623 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
02624
02625 #if defined(GPIOD)
02626 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
02627 #endif /* GPIOD */
02628
02629 #if defined(GPIOE)
02630 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
02631 #endif /* GPIOE */
02632
02633 #if defined(GPIOF)
02634 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
02635 #endif /* GPIOF */
02636
02637 #if defined(GPIOG)
02638 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
02639 #endif /* GPIOG */
02640
02641 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
02642
02643 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
02644
02645 #if defined(USB_OTG_FS)
02646 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
02647 #endif /* USB_OTG_FS */
02648
02649 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
02650
02651 #if defined(AES)
02652 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
02653 #endif /* AES */
02654
02655 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
02656
02657
02658 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
02659
02660 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
02661
02662 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
02663
02664 #if defined(GPIOD)
02665 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
02666 #endif /* GPIOD */
02667
02668 #if defined(GPIOE)
02669 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
02670 #endif /* GPIOE */
02671
02672 #if defined(GPIOF)
02673 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
02674 #endif /* GPIOF */
02675
02676 #if defined(GPIOG)
02677 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
02678 #endif /* GPIOG */
02679
02680 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
02681
02682 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
02683
02684 #if defined(USB_OTG_FS)
02685 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
02686 #endif /* USB_OTG_FS */
02687
02688 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
02689
02690 #if defined(AES)
02691 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
02692 #endif /* AES */
02693
02694 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
02695
02696 /**
02697   * @}
02698   */
02699
02700 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
02701   * @brief  Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
02702   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02703   *         power consumption.
02704   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02705   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02706   * @{
02707   */
02708
02709 #if defined(QUADSPI)
02710 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
02711 #endif /* QUADSPI */
02712
02713 #if defined(FMC_BANK1)
02714 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
02715 #endif /* FMC_BANK1 */
02716
02717 #if defined(QUADSPI)
02718 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
02719 #endif /* QUADSPI */
02720
02721 #if defined(FMC_BANK1)
02722 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
02723 #endif /* FMC_BANK1 */
02724
02725 /**
02726   * @}
02727   */
02728
02729 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
02730   * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
02731   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02732   *         power consumption.
02733   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02734   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02735   * @{
02736   */
02737
02738 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
02739
02740 #if defined(TIM3)
02741 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
02742 #endif /* TIM3 */
02743
02744 #if defined(TIM4)
02745 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
02746 #endif /* TIM4 */
02747
02748 #if defined(TIM5)
02749 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
02750 #endif /* TIM5 */
02751
02752 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
02753
02754 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
02755
02756 #if defined(LCD)
02757 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
02758 #endif /* LCD */
02759
02760 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
02761 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
02762 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
02763
02764 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
02765
02766 #if defined(SPI2)
02767 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
02768 #endif /* SPI2 */
02769
02770 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
02771
02772 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
02773
02774 #if defined(USART3)
02775 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
02776 #endif /* USART3 */
02777
02778 #if defined(UART4)
02779 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
02780 #endif /* UART4 */
02781
02782 #if defined(UART5)
02783 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
02784 #endif /* UART5 */
02785
02786 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
02787
02788 #if defined(I2C2)
02789 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
02790 #endif /* I2C2 */
02791
02792 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
02793
02794 #if defined(CRS)
02795 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
02796 #endif /* CRS */
02797
02798 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
02799
02800 #if defined(USB)
02801 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET)
02802 #endif /* USB */
02803
02804 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
02805
02806 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
02807
02808 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
02809
02810 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
02811
02812 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
02813
02814 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
02815
02816 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
02817
02818
02819 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
02820
02821 #if defined(TIM3)
02822 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
02823 #endif /* TIM3 */
02824
02825 #if defined(TIM4)
02826 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
02827 #endif /* TIM4 */
02828
02829 #if defined(TIM5)
02830 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
02831 #endif /* TIM5 */
02832
02833 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
02834
02835 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
02836
02837 #if defined(LCD)
02838 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
02839 #endif /* LCD */
02840
02841 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
02842 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
02843 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
02844
02845 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
02846
02847 #if defined(SPI2)
02848 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
02849 #endif /* SPI2 */
02850
02851 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
02852
02853 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
02854
02855 #if defined(USART3)
02856 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
02857 #endif /* USART3 */
02858
02859 #if defined(UART4)
02860 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
02861 #endif /* UART4 */
02862
02863 #if defined(UART5)
02864 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
02865 #endif /* UART5 */
02866
02867 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
02868
02869 #if defined(I2C2)
02870 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
02871 #endif /* I2C2 */
02872
02873 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
02874
02875 #if defined(CRS)
02876 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
02877 #endif /* CRS */
02878
02879 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
02880
02881 #if defined(USB)
02882 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET)
02883 #endif /* USB */
02884
02885 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
02886
02887 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
02888
02889 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
02890
02891 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
02892
02893 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
02894
02895 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
02896
02897 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
02898
02899 /**
02900   * @}
02901   */
02902
02903 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
02904   * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
02905   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02906   *         power consumption.
02907   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02908   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02909   * @{
02910   */
02911
02912 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
02913
02914 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
02915 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
02916 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
02917
02918 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
02919
02920 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
02921
02922 #if defined(TIM8)
02923 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
02924 #endif /* TIM8 */
02925
02926 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
02927
02928 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
02929
02930 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
02931
02932 #if defined(TIM17)
02933 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
02934 #endif /* TIM17 */
02935
02936 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
02937
02938 #if defined(SAI2)
02939 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
02940 #endif /* SAI2 */
02941
02942 #if defined(DFSDM1_Filter0)
02943 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
02944 #endif /* DFSDM1_Filter0 */
02945
02946
02947 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
02948
02949 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
02950 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
02951 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
02952
02953 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
02954
02955 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
02956
02957 #if defined(TIM8)
02958 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
02959 #endif /* TIM8 */
02960
02961 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
02962
02963 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
02964
02965 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
02966
02967 #if defined(TIM17)
02968 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
02969 #endif /* TIM17 */
02970
02971 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
02972
02973 #if defined(SAI2)
02974 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
02975 #endif /* SAI2 */
02976
02977 #if defined(DFSDM1_Filter0)
02978 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)
02979 #endif /* DFSDM1_Filter0 */
02980
02981 /**
02982   * @}
02983   */
02984
02985 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
02986   * @{
02987   */
02988
02989 /** @brief  Macros to force or release the Backup domain reset.
02990   * @note   This function resets the RTC peripheral (including the backup registers)
02991   *         and the RTC clock source selection in RCC_CSR register.
02992   * @note   The BKPSRAM is not affected by this reset.
02993   * @retval None
02994   */
02995 #define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
02996
02997 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
02998
02999 /**
03000   * @}
03001   */
03002
03003 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
03004   * @{
03005   */
03006
03007 /** @brief  Macros to enable or disable the RTC clock.
03008   * @note   As the RTC is in the Backup domain and write access is denied to
03009   *         this domain after reset, you have to enable write access using
03010   *         HAL_PWR_EnableBkUpAccess() function before to configure the RTC
03011   *         (to be done once after reset).
03012   * @note   These macros must be used after the RTC clock source was selected.
03013   * @retval None
03014   */
03015 #define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
03016
03017 #define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
03018
03019 /**
03020   * @}
03021   */
03022
03023 /** @brief  Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
03024   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
03025   *         It is used (enabled by hardware) as system clock source after startup
03026   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
03027   *         of the HSE used directly or indirectly as system clock (if the Clock
03028   *         Security System CSS is enabled).
03029   * @note   HSI can not be stopped if it is used as system clock source. In this case,
03030   *         you have to select another source of the system clock then stop the HSI.
03031   * @note   After enabling the HSI, the application software should wait on HSIRDY
03032   *         flag to be set indicating that HSI clock is stable and can be used as
03033   *         system clock source.
03034   *         This parameter can be: ENABLE or DISABLE.
03035   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
03036   *         clock cycles.
03037   * @retval None
03038   */
03039 #define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
03040
03041 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
03042
03043 /** @brief  Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
03044   * @note   The calibration is used to compensate for the variations in voltage
03045   *         and temperature that influence the frequency of the internal HSI RC.
03046   * @param  __HSICALIBRATIONVALUE__: specifies the calibration trimming value
03047   *         (default is RCC_HSICALIBRATION_DEFAULT).
03048   *         This parameter must be a number between 0 and 31.
03049   * @retval None
03050   */
03051 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
03052                   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
03053
03054 /**
03055   * @brief    Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
03056   *           in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
03057   * @note     The enable of this function has not effect on the HSION bit.
03058   *           This parameter can be: ENABLE or DISABLE.
03059   * @retval None
03060   */
03061 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE()   SET_BIT(RCC->CR, RCC_CR_HSIASFS)
03062
03063 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE()  CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
03064
03065 /**
03066   * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
03067   *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
03068   * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
03069   *           speed because of the HSI startup time.
03070   * @note     The enable of this function has not effect on the HSION bit.
03071   *           This parameter can be: ENABLE or DISABLE.
03072   * @retval None
03073   */
03074 #define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
03075
03076 #define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
03077
03078 /**
03079   * @brief  Macros to enable or disable the Internal Multi Speed oscillator (MSI).
03080   * @note     The MSI is stopped by hardware when entering STOP and STANDBY modes.
03081   *           It is used (enabled by hardware) as system clock source after
03082   *           startup from Reset, wakeup from STOP and STANDBY mode, or in case
03083   *           of failure of the HSE used directly or indirectly as system clock
03084   *           (if the Clock Security System CSS is enabled).
03085   * @note     MSI can not be stopped if it is used as system clock source.
03086   *           In this case, you have to select another source of the system
03087   *           clock then stop the MSI.
03088   * @note     After enabling the MSI, the application software should wait on
03089   *           MSIRDY flag to be set indicating that MSI clock is stable and can
03090   *           be used as system clock source.
03091   * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
03092   *         clock cycles.
03093   * @retval None
03094   */
03095 #define __HAL_RCC_MSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_MSION)
03096
03097 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
03098
03099 /** @brief  Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
03100   * @note   The calibration is used to compensate for the variations in voltage
03101   *         and temperature that influence the frequency of the internal MSI RC.
03102   *         Refer to the Application Note AN3300 for more details on how to
03103   *         calibrate the MSI.
03104   * @param  __MSICALIBRATIONVALUE__: specifies the calibration trimming value
03105   *         (default is RCC_MSICALIBRATION_DEFAULT).
03106   *         This parameter must be a number between 0 and 255.
03107   * @retval None
03108   */
03109 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
03110                   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
03111
03112 /**
03113   * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
03114   * @note     After restart from Reset , the MSI clock is around 4 MHz.
03115   *           After stop the startup clock can be MSI (at any of its possible
03116   *           frequencies, the one that was used before entering stop mode) or HSI.
03117   *          After Standby its frequency can be selected between 4 possible values
03118   *          (1, 2, 4 or 8 MHz).
03119   * @note     MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
03120   *          (MSIRDY=1).
03121   * @note    The MSI clock range after reset can be modified on the fly.
03122   * @param  __MSIRANGEVALUE__: specifies the MSI clock range.
03123   *         This parameter must be one of the following values:
03124   *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz
03125   *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz
03126   *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz
03127   *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz
03128   *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
03129   *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2MHz
03130   *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4MHz (default after Reset)
03131   *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8  MHz
03132   *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz
03133   *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz
03134   *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz
03135   *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz
03136   * @retval None
03137   */
03138 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
03139                   do {                                                         \
03140                     SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);                         \
03141                     MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
03142                   } while(0)
03143
03144 /**
03145   * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
03146   *         After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
03147   * @param  __MSIRANGEVALUE__: specifies the MSI clock range.
03148   *         This parameter must be one of the following values:
03149   *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
03150   *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2MHz
03151   *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4MHz (default after Reset)
03152   *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8  MHz
03153   * @retval None
03154   */
03155 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
03156                   MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
03157
03158 /** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
03159   * @retval MSI clock range.
03160   *         This parameter must be one of the following values:
03161   *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz
03162   *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz
03163   *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz
03164   *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz
03165   *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
03166   *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2MHz
03167   *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4MHz (default after Reset)
03168   *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8  MHz
03169   *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz
03170   *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz
03171   *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz
03172   *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz
03173   */
03174 #define __HAL_RCC_GET_MSI_RANGE()                                              \
03175                   ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ?             \
03176                    (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) :            \
03177                    (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
03178
03179 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
03180   * @note   After enabling the LSI, the application software should wait on
03181   *         LSIRDY flag to be set indicating that LSI clock is stable and can
03182   *         be used to clock the IWDG and/or the RTC.
03183   * @note   LSI can not be disabled if the IWDG is running.
03184   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
03185   *         clock cycles.
03186   * @retval None
03187   */
03188 #define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
03189
03190 #define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
03191
03192 /**
03193   * @brief  Macro to configure the External High Speed oscillator (HSE).
03194   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
03195   *         supported by this macro. User should request a transition to HSE Off
03196   *         first and then HSE On or HSE Bypass.
03197   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
03198   *         software should wait on HSERDY flag to be set indicating that HSE clock
03199   *         is stable and can be used to clock the PLL and/or system clock.
03200   * @note   HSE state can not be changed if it is used directly or through the
03201   *         PLL as system clock. In this case, you have to select another source
03202   *         of the system clock then change the HSE state (ex. disable it).
03203   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
03204   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
03205   *         was previously enabled you have to enable it again after calling this
03206   *         function.
03207   * @param  __STATE__: specifies the new state of the HSE.
03208   *         This parameter can be one of the following values:
03209   *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator, HSERDY flag goes low after
03210   *                              6 HSE oscillator clock cycles.
03211   *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.
03212   *            @arg @ref RCC_HSE_BYPASS  HSE oscillator bypassed with external clock.
03213   * @retval None
03214   */
03215 #define __HAL_RCC_HSE_CONFIG(__STATE__)                      \
03216                     do {                                     \
03217                       if((__STATE__) == RCC_HSE_ON)          \
03218                       {                                      \
03219                         SET_BIT(RCC->CR, RCC_CR_HSEON);      \
03220                       }                                      \
03221                       else if((__STATE__) == RCC_HSE_BYPASS) \
03222                       {                                      \
03223                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);     \
03224                         SET_BIT(RCC->CR, RCC_CR_HSEON);      \
03225                       }                                      \
03226                       else                                   \
03227                       {                                      \
03228                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);    \
03229                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);   \
03230                       }                                      \
03231                     } while(0)
03232
03233 /**
03234   * @brief  Macro to configure the External Low Speed oscillator (LSE).
03235   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
03236   *         supported by this macro. User should request a transition to LSE Off
03237   *         first and then LSE On or LSE Bypass.
03238   * @note   As the LSE is in the Backup domain and write access is denied to
03239   *         this domain after reset, you have to enable write access using
03240   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
03241   *         (to be done once after reset).
03242   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
03243   *         software should wait on LSERDY flag to be set indicating that LSE clock
03244   *         is stable and can be used to clock the RTC.
03245   * @param  __STATE__: specifies the new state of the LSE.
03246   *         This parameter can be one of the following values:
03247   *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator, LSERDY flag goes low after
03248   *                              6 LSE oscillator clock cycles.
03249   *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.
03250   *            @arg @ref RCC_LSE_BYPASS  LSE oscillator bypassed with external clock.
03251   * @retval None
03252   */
03253 #define __HAL_RCC_LSE_CONFIG(__STATE__)                        \
03254                     do {                                       \
03255                       if((__STATE__) == RCC_LSE_ON)            \
03256                       {                                        \
03257                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
03258                       }                                        \
03259                       else if((__STATE__) == RCC_LSE_BYPASS)   \
03260                       {                                        \
03261                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
03262                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
03263                       }                                        \
03264                       else                                     \
03265                       {                                        \
03266                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
03267                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
03268                       }                                        \
03269                     } while(0)
03270
03271 #if defined(RCC_HSI48_SUPPORT)
03272
03273 /** @brief  Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
03274   * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
03275   * @note   After enabling the HSI48, the application software should wait on HSI48RDY
03276   *         flag to be set indicating that HSI48 clock is stable.
03277   *         This parameter can be: ENABLE or DISABLE.
03278   * @retval None
03279   */
03280 #define __HAL_RCC_HSI48_ENABLE()  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
03281
03282 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
03283
03284 #endif /* RCC_HSI48_SUPPORT */
03285
03286 /** @brief  Macros to configure the RTC clock (RTCCLK).
03287   * @note   As the RTC clock configuration bits are in the Backup domain and write
03288   *         access is denied to this domain after reset, you have to enable write
03289   *         access using the Power Backup Access macro before to configure
03290   *         the RTC clock source (to be done once after reset).
03291   * @note   Once the RTC clock is configured it cannot be changed unless the
03292   *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
03293   *         a Power On Reset (POR).
03294   *
03295   * @param  __RTC_CLKSOURCE__: specifies the RTC clock source.
03296   *         This parameter can be one of the following values:
03297   *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK  No clock selected as RTC clock.
03298   *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
03299   *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
03300   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
03301   *
03302   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
03303   *         work in STOP and STANDBY modes, and can be used as wakeup source.
03304   *         However, when the HSE clock is used as RTC clock source, the RTC
03305   *         cannot be used in STOP and STANDBY modes.
03306   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
03307   *         RTC clock source).
03308   * @retval None
03309   */
03310 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)  \
03311                   MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
03312
03313
03314 /** @brief  Macro to get the RTC clock source.
03315   * @retval The returned value can be one of the following:
03316   *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK  No clock selected as RTC clock.
03317   *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
03318   *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
03319   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
03320   */
03321 #define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
03322
03323 /** @brief  Macros to enable or disable the main PLL.
03324   * @note   After enabling the main PLL, the application software should wait on
03325   *         PLLRDY flag to be set indicating that PLL clock is stable and can
03326   *         be used as system clock source.
03327   * @note   The main PLL can not be disabled if it is used as system clock source
03328   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
03329   * @retval None
03330   */
03331 #define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLLON)
03332
03333 #define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
03334
03335 /** @brief  Macro to configure the PLL clock source.
03336   * @note   This function must be used only when the main PLL is disabled.
03337   * @param  __PLLSOURCE__: specifies the PLL entry clock source.
03338   *         This parameter can be one of the following values:
03339   *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
03340   *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
03341   *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
03342   *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
03343   * @note   This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
03344   * @retval None
03345   *
03346   */
03347 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
03348                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
03349
03350 /** @brief  Macro to configure the PLL source division factor M.
03351   * @note   This function must be used only when the main PLL is disabled.
03352   * @param  __PLLM__: specifies the division factor for PLL VCO input clock
03353   *         This parameter must be a number between Min_Data = 1 and Max_Data = 8.
03354   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
03355   *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
03356   *         of 16 MHz to limit PLL jitter.
03357   * @retval None
03358   *
03359   */
03360 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
03361                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
03362
03363 /**
03364   * @brief  Macro to configure the main PLL clock source, multiplication and division factors.
03365   * @note   This function must be used only when the main PLL is disabled.
03366   *
03367   * @param  __PLLSOURCE__: specifies the PLL entry clock source.
03368   *          This parameter can be one of the following values:
03369   *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
03370   *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
03371   *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
03372   *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
03373   * @note   This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
03374   *
03375   * @param  __PLLM__: specifies the division factor for PLL VCO input clock.
03376   *          This parameter must be a number between 1 and 8.
03377   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
03378   *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
03379   *         of 16 MHz to limit PLL jitter.
03380   *
03381   * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock.
03382   *          This parameter must be a number between 8 and 86.
03383   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
03384   *         output frequency is between 64 and 344 MHz.
03385   *
03386   * @param  __PLLP__: specifies the division factor for SAI clock.
03387   *          This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
03388   *          else (2 to 31).
03389   *
03390   * @param  __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
03391   *          This parameter must be in the range (2, 4, 6 or 8).
03392   * @note   If the USB OTG FS is used in your application, you have to set the
03393   *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
03394   *         the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
03395   *         correctly.
03396   * @param  __PLLR__: specifies the division factor for the main system clock.
03397   * @note   You have to set the PLLR parameter correctly to not exceed 80MHZ.
03398   *          This parameter must be in the range (2, 4, 6 or 8).
03399   * @retval None
03400   */
03401 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
03402
03403 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
03404                   (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \
03405                    (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \
03406                    (uint32_t)((__PLLP__) << 27U))
03407
03408 #else
03409
03410 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
03411                   (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \
03412                    (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
03413
03414 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
03415
03416 /** @brief  Macro to get the oscillator used as PLL clock source.
03417   * @retval The oscillator used as PLL clock source. The returned value can be one
03418   *         of the following:
03419   *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
03420   *              - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
03421   *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
03422   *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
03423   */
03424 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
03425
03426 /**
03427   * @brief  Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
03428   * @note   Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
03429   *         without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
03430   *         be stopped if used as System Clock.
03431   * @param  __PLLCLOCKOUT__: specifies the PLL clock to be output.
03432   *          This parameter can be one or a combination of the following values:
03433   *            @arg @ref RCC_PLL_SAI3CLK  This clock is used to generate an accurate clock to achieve
03434   *                                   high-quality audio performance on SAI interface in case.
03435   *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB OTG FS (48 MHz),
03436   *                                   the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
03437   *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 80MHz)
03438   * @retval None
03439   */
03440 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
03441
03442 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
03443
03444 /**
03445   * @brief  Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
03446   * @param  __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
03447   *          This parameter can be one of the following values:
03448   *            @arg @ref RCC_PLL_SAI3CLK  This clock is used to generate an accurate clock to achieve
03449   *                                   high-quality audio performance on SAI interface in case.
03450   *            @arg @ref RCC_PLL_48M1CLK  This Clock is used to generate the clock for the USB OTG FS (48 MHz),
03451   *                                   the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
03452   *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 80MHz)
03453   * @retval SET / RESET
03454   */
03455 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)  READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
03456
03457 /**
03458   * @brief  Macro to configure the system clock source.
03459   * @param  __SYSCLKSOURCE__: specifies the system clock source.
03460   *          This parameter can be one of the following values:
03461   *              - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
03462   *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
03463   *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
03464   *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
03465   * @retval None
03466   */
03467 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
03468                   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
03469
03470 /** @brief  Macro to get the clock source used as system clock.
03471   * @retval The clock source used as system clock. The returned value can be one
03472   *         of the following:
03473   *              - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
03474   *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
03475   *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
03476   *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
03477   */
03478 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
03479
03480 /**
03481   * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
03482   * @note   As the LSE is in the Backup domain and write access is denied to
03483   *         this domain after reset, you have to enable write access using
03484   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
03485   *         (to be done once after reset).
03486   * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.
03487   *          This parameter can be one of the following values:
03488   *            @arg @ref RCC_LSEDRIVE_LOW  LSE oscillator low drive capability.
03489   *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.
03490   *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH  LSE oscillator medium high drive capability.
03491   *            @arg @ref RCC_LSEDRIVE_HIGH  LSE oscillator high drive capability.
03492   * @retval None
03493   */
03494 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
03495                   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
03496
03497 /**
03498   * @brief  Macro to configure the wake up from stop clock.
03499   * @param  __STOPWUCLK__: specifies the clock source used after wake up from stop.
03500   *         This parameter can be one of the following values:
03501   *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI selected as system clock source
03502   *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI selected as system clock source
03503   * @retval None
03504   */
03505 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
03506                   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
03507
03508
03509 /** @brief  Macro to configure the MCO clock.
03510   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
03511   *          This parameter can be one of the following values:
03512   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled
03513   *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System  clock selected as MCO source
03514   *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source
03515   *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
03516   *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee
03517   *            @arg @ref RCC_MCO1SOURCE_PLLCLK  Main PLL clock selected as MCO source
03518   *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
03519   *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
03520   @if STM32L443xx
03521   *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
03522   @endif
03523   * @param  __MCODIV__ specifies the MCO clock prescaler.
03524   *          This parameter can be one of the following values:
03525   *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
03526   *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
03527   *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
03528   *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
03529   *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
03530   */
03531 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
03532                  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
03533
03534 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
03535   * @brief macros to manage the specified RCC Flags and interrupts.
03536   * @{
03537   */
03538
03539 /** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
03540   *         the selected interrupts).
03541   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
03542   *         This parameter can be any combination of the following values:
03543   *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
03544   *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
03545   *            @arg @ref RCC_IT_MSIRDY  HSI ready interrupt
03546   *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
03547   *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
03548   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
03549   *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
03550   *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2
03551   *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
03552   @if STM32L443xx
03553   *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
03554   @endif
03555   * @retval None
03556   */
03557 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
03558
03559 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
03560   *        the selected interrupts).
03561   * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
03562   *         This parameter can be any combination of the following values:
03563   *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
03564   *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
03565   *            @arg @ref RCC_IT_MSIRDY  HSI ready interrupt
03566   *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
03567   *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
03568   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
03569   *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
03570   *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2
03571   *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
03572   @if STM32L443xx
03573   *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
03574   @endif
03575   * @retval None
03576   */
03577 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
03578
03579 /** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
03580   *         bits to clear the selected interrupt pending bits.
03581   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
03582   *         This parameter can be any combination of the following values:
03583   *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
03584   *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
03585   *            @arg @ref RCC_IT_MSIRDY  MSI ready interrupt
03586   *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
03587   *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
03588   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
03589   *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
03590   *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2
03591   *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt
03592   *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
03593   @if STM32L443xx
03594   *            @arg @ref RCC_IT_HSI48RDY  HSI48 ready interrupt for devices with HSI48
03595   @endif
03596   * @retval None
03597   */
03598 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
03599
03600 /** @brief  Check whether the RCC interrupt has occurred or not.
03601   * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
03602   *         This parameter can be one of the following values:
03603   *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt
03604   *            @arg @ref RCC_IT_LSERDY  LSE ready interrupt
03605   *            @arg @ref RCC_IT_MSIRDY  MSI ready interrupt
03606   *            @arg @ref RCC_IT_HSIRDY  HSI ready interrupt
03607   *            @arg @ref RCC_IT_HSERDY  HSE ready interrupt
03608   *            @arg @ref RCC_IT_PLLRDY  Main PLL ready interrupt
03609   *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt
03610   *            @arg @ref RCC_IT_PLLSAI2RDY  PLLSAI2 ready interrupt for devices with PLLSAI2
03611   *            @arg @ref RCC_IT_CSS  HSE Clock security system interrupt
03612   *            @arg @ref RCC_IT_LSECSS  LSE Clock security system interrupt
03613   @if STM32L443xx
03614   *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
03615   @endif
03616   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
03617   */
03618 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
03619
03620 /** @brief Set RMVF bit to clear the reset flags.
03621   *        The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
03622   *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
03623   * @retval None
03624  */
03625 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
03626
03627 /** @brief  Check whether the selected RCC flag is set or not.
03628   * @param  __FLAG__: specifies the flag to check.
03629   *         This parameter can be one of the following values:
03630   *            @arg @ref RCC_FLAG_MSIRDY  MSI oscillator clock ready
03631   *            @arg @ref RCC_FLAG_HSIRDY  HSI oscillator clock ready
03632   *            @arg @ref RCC_FLAG_HSERDY  HSE oscillator clock ready
03633   *            @arg @ref RCC_FLAG_PLLRDY  Main PLL clock ready
03634   *            @arg @ref RCC_FLAG_PLLSAI1RDY  PLLSAI1 clock ready
03635   *            @arg @ref RCC_FLAG_PLLSAI2RDY  PLLSAI2 clock ready for devices with PLLSAI2
03636   @if STM32L443xx
03637   *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48
03638   @endif
03639   *            @arg @ref RCC_FLAG_LSERDY  LSE oscillator clock ready
03640   *            @arg @ref RCC_FLAG_LSECSSD  Clock security system failure on LSE oscillator detection
03641   *            @arg @ref RCC_FLAG_LSIRDY  LSI oscillator clock ready
03642   *            @arg @ref RCC_FLAG_BORRST  BOR reset
03643   *            @arg @ref RCC_FLAG_OBLRST  OBLRST reset
03644   *            @arg @ref RCC_FLAG_PINRST  Pin reset
03645   *            @arg @ref RCC_FLAG_FWRST  FIREWALL reset
03646   *            @arg @ref RCC_FLAG_RMVF  Remove reset Flag
03647   *            @arg @ref RCC_FLAG_SFTRST  Software reset
03648   *            @arg @ref RCC_FLAG_IWDGRST  Independent Watchdog reset
03649   *            @arg @ref RCC_FLAG_WWDGRST  Window Watchdog reset
03650   *            @arg @ref RCC_FLAG_LPWRRST  Low Power reset
03651   * @retval The new state of __FLAG__ (TRUE or FALSE).
03652   */
03653 #if defined(RCC_HSI48_SUPPORT)
03654 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                     \
03655                                         ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR :                  \
03656                                         ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                   \
03657                                         ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) &    \
03658                                           ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
03659                                             ? 1U : 0U)
03660 #else
03661 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR :                    \
03662                                         ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :                  \
03663                                         ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) &    \
03664                                           ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
03665                                             ? 1U : 0U)
03666 #endif /* RCC_HSI48_SUPPORT */
03667
03668 /**
03669   * @}
03670   */
03671
03672 /**
03673   * @}
03674   */
03675
03676 /* Private constants ---------------------------------------------------------*/
03677 /** @defgroup RCC_Private_Constants RCC Private Constants
03678   * @{
03679   */
03680 /* Defines used for Flags */
03681 #define CR_REG_INDEX              ((uint32_t)1U)
03682 #define BDCR_REG_INDEX            ((uint32_t)2U)
03683 #define CSR_REG_INDEX             ((uint32_t)3U)
03684 #if defined(RCC_HSI48_SUPPORT)
03685 #define CRRCR_REG_INDEX           ((uint32_t)4U)
03686 #endif /* RCC_HSI48_SUPPORT */
03687
03688 #define RCC_FLAG_MASK             ((uint32_t)0x1FU)
03689 /**
03690   * @}
03691   */
03692
03693 /* Private macros ------------------------------------------------------------*/
03694 /** @addtogroup RCC_Private_Macros
03695   * @{
03696   */
03697
03698 #if defined(RCC_HSI48_SUPPORT)
03699 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \
03700                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)   == RCC_OSCILLATORTYPE_HSE)   || \
03701                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)   == RCC_OSCILLATORTYPE_HSI)   || \
03702                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
03703                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI)   == RCC_OSCILLATORTYPE_MSI)   || \
03704                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI)   == RCC_OSCILLATORTYPE_LSI)   || \
03705                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)   == RCC_OSCILLATORTYPE_LSE))
03706 #else
03707 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
03708                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
03709                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
03710                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
03711                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
03712                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
03713 #endif /* RCC_HSI48_SUPPORT */
03714
03715 #define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
03716                               ((__HSE__) == RCC_HSE_BYPASS))
03717
03718 #define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
03719                               ((__LSE__) == RCC_LSE_BYPASS))
03720
03721 #define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
03722
03723 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31U)
03724
03725 #define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
03726
03727 #define IS_RCC_MSI(__MSI__)  (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
03728
03729 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
03730
03731 #if defined(RCC_HSI48_SUPPORT)
03732 #define IS_RCC_HSI48(__HSI48__)  (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
03733 #endif /* RCC_HSI48_SUPPORT */
03734
03735 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
03736                              ((__PLL__) == RCC_PLL_ON))
03737
03738 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
03739                                       ((__SOURCE__) == RCC_PLLSOURCE_MSI)  || \
03740                                       ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
03741                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
03742
03743 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
03744
03745 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
03746
03747 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
03748 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
03749 #else
03750 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
03751 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */
03752
03753 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
03754                                       ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
03755
03756 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
03757                                       ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
03758
03759 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK)  || \
03760                                                   (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK)  || \
03761                                                   (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
03762                                                  (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))
03763
03764 #if defined(RCC_PLLSAI2_SUPPORT)
03765 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK)  || \
03766                                                   (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
03767                                                  (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))
03768 #endif /* RCC_PLLSAI2_SUPPORT */
03769
03770 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0)  || \
03771                                            ((__RANGE__) == RCC_MSIRANGE_1)  || \
03772                                            ((__RANGE__) == RCC_MSIRANGE_2)  || \
03773                                            ((__RANGE__) == RCC_MSIRANGE_3)  || \
03774                                            ((__RANGE__) == RCC_MSIRANGE_4)  || \
03775                                            ((__RANGE__) == RCC_MSIRANGE_5)  || \
03776                                            ((__RANGE__) == RCC_MSIRANGE_6)  || \
03777                                            ((__RANGE__) == RCC_MSIRANGE_7)  || \
03778                                            ((__RANGE__) == RCC_MSIRANGE_8)  || \
03779                                            ((__RANGE__) == RCC_MSIRANGE_9)  || \
03780                                            ((__RANGE__) == RCC_MSIRANGE_10) || \
03781                                            ((__RANGE__) == RCC_MSIRANGE_11))
03782
03783 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4)  || \
03784                                                    ((__RANGE__) == RCC_MSIRANGE_5)  || \
03785                                                    ((__RANGE__) == RCC_MSIRANGE_6)  || \
03786                                                    ((__RANGE__) == RCC_MSIRANGE_7))
03787
03788 #define IS_RCC_CLOCKTYPE(__CLK__)  ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
03789
03790 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
03791                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
03792                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
03793                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
03794
03795 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
03796                                ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV8)   || \
03797                                ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || \
03798                                ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
03799                                ((__HCLK__) == RCC_SYSCLK_DIV512))
03800
03801 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
03802                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
03803                                ((__PCLK__) == RCC_HCLK_DIV16))
03804
03805 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
03806                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)    || \
03807                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)    || \
03808                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
03809
03810 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
03811
03812 #if defined(RCC_HSI48_SUPPORT)
03813 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
03814                                        ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
03815                                        ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
03816                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
03817                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
03818                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
03819                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
03820                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
03821                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
03822 #else
03823 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
03824                                        ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
03825                                        ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
03826                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
03827                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
03828                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
03829                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
03830                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
03831 #endif /* RCC_HSI48_SUPPORT */
03832
03833 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
03834                                 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
03835                                 ((__DIV__) == RCC_MCODIV_16))
03836
03837 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
03838                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
03839                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
03840                                      ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
03841
03842 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
03843                                              ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
03844 /**
03845   * @}
03846   */
03847
03848 /* Include RCC HAL Extended module */
03849 #include "stm32l4xx_hal_rcc_ex.h"
03850
03851 /* Exported functions --------------------------------------------------------*/
03852 /** @addtogroup RCC_Exported_Functions
03853   * @{
03854   */
03855
03856
03857 /** @addtogroup RCC_Exported_Functions_Group1
03858   * @{
03859   */
03860
03861 /* Initialization and de-initialization functions  ******************************/
03862 void              HAL_RCC_DeInit(void);
03863 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
03864 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
03865
03866 /**
03867   * @}
03868   */
03869
03870 /** @addtogroup RCC_Exported_Functions_Group2
03871   * @{
03872   */
03873
03874 /* Peripheral Control functions  ************************************************/
03875 void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
03876 void              HAL_RCC_EnableCSS(void);
03877 uint32_t          HAL_RCC_GetSysClockFreq(void);
03878 uint32_t          HAL_RCC_GetHCLKFreq(void);
03879 uint32_t          HAL_RCC_GetPCLK1Freq(void);
03880 uint32_t          HAL_RCC_GetPCLK2Freq(void);
03881 void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
03882 void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
03883 /* CSS NMI IRQ handler */
03884 void              HAL_RCC_NMI_IRQHandler(void);
03885 /* User Callbacks in non blocking mode (IT mode) */
03886 void              HAL_RCC_CSSCallback(void);
03887
03888 /**
03889   * @}
03890   */
03891
03892 /**
03893   * @}
03894   */
03895
03896 /**
03897   * @}
03898   */
03899
03900 /**
03901   * @}
03902   */
03903
03904 #ifdef __cplusplus
03905 }
03906 #endif
03907
03908 #endif /* __STM32L4xx_HAL_RCC_H */
03909
03910 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rcc_ex.c Source File

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stm32l4xx_hal_rcc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rcc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Extended RCC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities RCC extended peripheral:
00010   *           + Extended Peripheral Control functions
00011   *           + Extended Clock management functions
00012   *           + Extended Clock Recovery System Control functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00018   *
00019   * Redistribution and use in source and binary forms, with or without modification,
00020   * are permitted provided that the following conditions are met:
00021   *   1. Redistributions of source code must retain the above copyright notice,
00022   *      this list of conditions and the following disclaimer.
00023   *   2. Redistributions in binary form must reproduce the above copyright notice,
00024   *      this list of conditions and the following disclaimer in the documentation
00025   *      and/or other materials provided with the distribution.
00026   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00027   *      may be used to endorse or promote products derived from this software
00028   *      without specific prior written permission.
00029   *
00030   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00031   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00032   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00033   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00034   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00035   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00036   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00037   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00038   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00039   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00040   *
00041   ******************************************************************************
00042   */
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32l4xx_hal.h"
00046
00047 /** @addtogroup STM32L4xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @defgroup RCCEx RCCEx
00052   * @brief RCC Extended HAL module driver
00053   * @{
00054   */
00055
00056 #ifdef HAL_RCC_MODULE_ENABLED
00057
00058 /* Private typedef -----------------------------------------------------------*/
00059 /* Private defines -----------------------------------------------------------*/
00060 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
00061  * @{
00062  */
00063 #define PLLSAI1_TIMEOUT_VALUE    ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
00064 #define PLLSAI2_TIMEOUT_VALUE    ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
00065 #define PLL_TIMEOUT_VALUE        ((uint32_t)2U)    /* 2 ms (minimum Tick + 1) */
00066
00067 #define DIVIDER_P_UPDATE          0U
00068 #define DIVIDER_Q_UPDATE          1U
00069 #define DIVIDER_R_UPDATE          2U
00070
00071 #define __LSCO_CLK_ENABLE()       __HAL_RCC_GPIOA_CLK_ENABLE()
00072 #define LSCO_GPIO_PORT            GPIOA
00073 #define LSCO_PIN                  GPIO_PIN_2
00074 /**
00075   * @}
00076   */
00077
00078 /* Private macros ------------------------------------------------------------*/
00079 /* Private variables ---------------------------------------------------------*/
00080 /* Private function prototypes -----------------------------------------------*/
00081 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
00082  * @{
00083  */
00084 static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider);
00085
00086 #if defined(RCC_PLLSAI2_SUPPORT)
00087
00088 static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider);
00089
00090 #endif /* RCC_PLLSAI2_SUPPORT */
00091
00092 /**
00093   * @}
00094   */
00095
00096 /* Exported functions --------------------------------------------------------*/
00097
00098 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
00099   * @{
00100   */
00101
00102 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
00103  *  @brief  Extended Peripheral Control functions
00104  *
00105 @verbatim
00106  ===============================================================================
00107                 ##### Extended Peripheral Control functions  #####
00108  ===============================================================================
00109     [..]
00110     This subsection provides a set of functions allowing to control the RCC Clocks
00111     frequencies.
00112     [..]
00113     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
00114         select the RTC clock source; in this case the Backup domain will be reset in
00115         order to modify the RTC Clock source, as consequence RTC registers (including
00116         the backup registers) are set to their reset values.
00117
00118 @endverbatim
00119   * @{
00120   */
00121 /**
00122   * @brief  Initialize the RCC extended peripherals clocks according to the specified
00123   *         parameters in the RCC_PeriphCLKInitTypeDef.
00124   * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
00125   *         contains a field PeriphClockSelection which can be a combination of the following values:
00126   *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
00127   *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
00128   @if STM32L486xx
00129   *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM1)
00130   @endif
00131   *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
00132   *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
00133   *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
00134   *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
00135   *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock
00136   *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
00137   *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
00138   *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
00139   @if STM32L486xx
00140   *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)
00141   @endif
00142   *            @arg @ref RCC_PERIPHCLK_SDMMC1  SDMMC1 peripheral clock
00143   @if STM32L443xx
00144   *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)
00145   @endif
00146   @if STM32L486xx
00147   *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock (only for devices with SWPMI1)
00148   @endif
00149   *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
00150   *            @arg @ref RCC_PERIPHCLK_USART2  USART1 peripheral clock
00151   *            @arg @ref RCC_PERIPHCLK_USART3  USART1 peripheral clock
00152   @if STM32L486xx
00153   *            @arg @ref RCC_PERIPHCLK_UART4  USART1 peripheral clock (only for devices with UART4)
00154   *            @arg @ref RCC_PERIPHCLK_UART5  USART1 peripheral clock (only for devices with UART5)
00155   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
00156   @endif
00157   *
00158   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
00159   *         the RTC clock source: in this case the access to Backup domain is enabled.
00160   *
00161   * @retval HAL status
00162   */
00163 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00164 {
00165   uint32_t tmpregister = 0;
00166   uint32_t tickstart = 0U;
00167   HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
00168   HAL_StatusTypeDef status = HAL_OK;   /* Final status */
00169
00170   /* Check the parameters */
00171   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
00172
00173   /*-------------------------- SAI1 clock source configuration ---------------------*/
00174   if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
00175   {
00176     /* Check the parameters */
00177     assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
00178
00179     switch(PeriphClkInit->Sai1ClockSelection)
00180     {
00181     case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
00182       /* Enable SAI Clock output generated form System PLL . */
00183 #if defined(RCC_PLLSAI2_SUPPORT)
00184       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
00185 #else
00186       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
00187 #endif /* RCC_PLLSAI2_SUPPORT */
00188       /* SAI1 clock source config set later after clock selection check */
00189       break;
00190
00191     case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
00192       /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
00193       ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
00194       /* SAI1 clock source config set later after clock selection check */
00195       break;
00196
00197 #if defined(RCC_PLLSAI2_SUPPORT)
00198
00199     case RCC_SAI1CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI1*/
00200       /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
00201       ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
00202       /* SAI1 clock source config set later after clock selection check */
00203       break;
00204
00205 #endif /* RCC_PLLSAI2_SUPPORT */
00206
00207     case RCC_SAI1CLKSOURCE_PIN:      /* External clock is used as source of SAI1 clock*/
00208       /* SAI1 clock source config set later after clock selection check */
00209       break;
00210
00211     default:
00212       ret = HAL_ERROR;
00213       break;
00214     }
00215
00216     if(ret == HAL_OK)
00217     {
00218       /* Set the source of SAI1 clock*/
00219       __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
00220     }
00221     else
00222     {
00223       /* set overall return value */
00224       status = ret;
00225     }
00226   }
00227
00228 #if defined(SAI2)
00229
00230   /*-------------------------- SAI2 clock source configuration ---------------------*/
00231   if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
00232   {
00233     /* Check the parameters */
00234     assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
00235
00236     switch(PeriphClkInit->Sai2ClockSelection)
00237     {
00238     case RCC_SAI2CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
00239       /* Enable SAI Clock output generated form System PLL . */
00240       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
00241       /* SAI2 clock source config set later after clock selection check */
00242       break;
00243
00244     case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
00245       /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
00246       ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
00247       /* SAI2 clock source config set later after clock selection check */
00248       break;
00249
00250     case RCC_SAI2CLKSOURCE_PLLSAI2:  /* PLLSAI2 is used as clock source for SAI2*/
00251       /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
00252       ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
00253       /* SAI2 clock source config set later after clock selection check */
00254       break;
00255
00256     case RCC_SAI2CLKSOURCE_PIN:      /* External clock is used as source of SAI2 clock*/
00257       /* SAI2 clock source config set later after clock selection check */
00258       break;
00259
00260     default:
00261       ret = HAL_ERROR;
00262       break;
00263     }
00264
00265     if(ret == HAL_OK)
00266     {
00267       /* Set the source of SAI2 clock*/
00268       __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
00269     }
00270     else
00271     {
00272       /* set overall return value */
00273       status = ret;
00274     }
00275   }
00276 #endif /* SAI2 */
00277
00278   /*-------------------------- RTC clock source configuration ----------------------*/
00279   if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
00280   {
00281     FlagStatus       pwrclkchanged = RESET;
00282
00283     /* Check for RTC Parameters used to output RTCCLK */
00284     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
00285
00286     /* Enable Power Clock */
00287     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
00288     {
00289       __HAL_RCC_PWR_CLK_ENABLE();
00290       pwrclkchanged = SET;
00291     }
00292
00293     /* Enable write access to Backup domain */
00294     SET_BIT(PWR->CR1, PWR_CR1_DBP);
00295
00296     /* Wait for Backup domain Write protection disable */
00297     tickstart = HAL_GetTick();
00298
00299     while((PWR->CR1 & PWR_CR1_DBP) == RESET)
00300     {
00301       if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00302       {
00303         ret = HAL_TIMEOUT;
00304         break;
00305       }
00306     }
00307
00308     if(ret == HAL_OK)
00309     {
00310       /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
00311       tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
00312
00313       if((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != PeriphClkInit->RTCClockSelection))
00314       {
00315         /* Store the content of BDCR register before the reset of Backup Domain */
00316         tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
00317         /* RTC Clock selection can be changed only if the Backup Domain is reset */
00318         __HAL_RCC_BACKUPRESET_FORCE();
00319         __HAL_RCC_BACKUPRESET_RELEASE();
00320         /* Restore the Content of BDCR register */
00321         RCC->BDCR = tmpregister;
00322       }
00323
00324       /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
00325       if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
00326       {
00327         /* Get Start Tick*/
00328         tickstart = HAL_GetTick();
00329
00330         /* Wait till LSE is ready */
00331         while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET)
00332         {
00333           if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00334           {
00335             ret = HAL_TIMEOUT;
00336             break;
00337           }
00338         }
00339       }
00340
00341       if(ret == HAL_OK)
00342       {
00343         /* Apply new RTC clock source selection */
00344         __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
00345       }
00346       else
00347       {
00348         /* set overall return value */
00349         status = ret;
00350       }
00351     }
00352     else
00353     {
00354       /* set overall return value */
00355       status = ret;
00356     }
00357
00358     /* Restore clock configuration if changed */
00359     if(pwrclkchanged == SET)
00360     {
00361       __HAL_RCC_PWR_CLK_DISABLE();
00362     }
00363   }
00364
00365   /*-------------------------- USART1 clock source configuration -------------------*/
00366   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
00367   {
00368     /* Check the parameters */
00369     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
00370
00371     /* Configure the USART1 clock source */
00372     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
00373   }
00374
00375   /*-------------------------- USART2 clock source configuration -------------------*/
00376   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
00377   {
00378     /* Check the parameters */
00379     assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
00380
00381     /* Configure the USART2 clock source */
00382     __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
00383   }
00384
00385 #if defined(USART3)
00386
00387   /*-------------------------- USART3 clock source configuration -------------------*/
00388   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
00389   {
00390     /* Check the parameters */
00391     assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
00392
00393     /* Configure the USART3 clock source */
00394     __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
00395   }
00396
00397 #endif /* USART3 */
00398
00399 #if defined(UART4)
00400
00401   /*-------------------------- UART4 clock source configuration --------------------*/
00402   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
00403   {
00404     /* Check the parameters */
00405     assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
00406
00407     /* Configure the UART4 clock source */
00408     __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
00409   }
00410
00411 #endif /* UART4 */
00412
00413 #if defined(UART5)
00414
00415   /*-------------------------- UART5 clock source configuration --------------------*/
00416   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
00417   {
00418     /* Check the parameters */
00419     assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
00420
00421     /* Configure the UART5 clock source */
00422     __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
00423   }
00424
00425 #endif /* UART5 */
00426
00427   /*-------------------------- LPUART1 clock source configuration ------------------*/
00428   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
00429   {
00430     /* Check the parameters */
00431     assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
00432
00433     /* Configure the LPUAR1 clock source */
00434     __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
00435   }
00436
00437   /*-------------------------- LPTIM1 clock source configuration -------------------*/
00438   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
00439   {
00440     assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
00441     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
00442   }
00443
00444   /*-------------------------- LPTIM2 clock source configuration -------------------*/
00445   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
00446   {
00447     assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
00448     __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
00449   }
00450
00451   /*-------------------------- I2C1 clock source configuration ---------------------*/
00452   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
00453   {
00454     /* Check the parameters */
00455     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
00456
00457     /* Configure the I2C1 clock source */
00458     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
00459   }
00460
00461 #if defined(I2C2)
00462
00463   /*-------------------------- I2C2 clock source configuration ---------------------*/
00464   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
00465   {
00466     /* Check the parameters */
00467     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
00468
00469     /* Configure the I2C2 clock source */
00470     __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
00471   }
00472
00473 #endif /* I2C2 */
00474
00475   /*-------------------------- I2C3 clock source configuration ---------------------*/
00476   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
00477   {
00478     /* Check the parameters */
00479     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
00480
00481     /* Configure the I2C3 clock source */
00482     __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
00483   }
00484
00485 #if defined(USB_OTG_FS) || defined(USB)
00486
00487   /*-------------------------- USB clock source configuration ----------------------*/
00488   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
00489   {
00490     assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
00491     __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
00492
00493     if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
00494     {
00495       /* Enable PLL48M1CLK output */
00496       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
00497     }
00498     else if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
00499     {
00500       /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
00501       ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
00502
00503       if(ret != HAL_OK)
00504       {
00505         /* set overall return value */
00506         status = ret;
00507       }
00508     }
00509   }
00510
00511 #endif /* USB_OTG_FS || USB */
00512
00513 #if defined(SDMMC1)
00514
00515   /*-------------------------- SDMMC1 clock source configuration -------------------*/
00516   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
00517   {
00518     assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
00519     __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
00520
00521     if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)
00522     {
00523       /* Enable PLL48M1CLK output */
00524       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
00525     }
00526     else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
00527     {
00528       /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
00529       ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
00530
00531       if(ret != HAL_OK)
00532       {
00533         /* set overall return value */
00534         status = ret;
00535       }
00536     }
00537   }
00538
00539 #endif /* SDMMC1 */
00540
00541   /*-------------------------- RNG clock source configuration ----------------------*/
00542   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
00543   {
00544     assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
00545     __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
00546
00547     if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
00548     {
00549       /* Enable PLL48M1CLK output */
00550       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
00551     }
00552     else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
00553     {
00554       /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
00555       ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
00556
00557       if(ret != HAL_OK)
00558       {
00559         /* set overall return value */
00560         status = ret;
00561       }
00562     }
00563   }
00564
00565   /*-------------------------- ADC clock source configuration ----------------------*/
00566   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
00567   {
00568     /* Check the parameters */
00569     assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
00570
00571     /* Configure the ADC interface clock source */
00572     __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
00573
00574     if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
00575     {
00576       /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
00577       ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
00578
00579       if(ret != HAL_OK)
00580       {
00581         /* set overall return value */
00582         status = ret;
00583       }
00584     }
00585
00586 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00587
00588     else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
00589     {
00590       /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
00591       ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
00592
00593       if(ret != HAL_OK)
00594       {
00595         /* set overall return value */
00596         status = ret;
00597       }
00598     }
00599
00600 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00601
00602   }
00603
00604 #if defined(SWPMI1)
00605
00606   /*-------------------------- SWPMI1 clock source configuration -------------------*/
00607   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
00608   {
00609     /* Check the parameters */
00610     assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
00611
00612     /* Configure the SWPMI1 clock source */
00613     __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
00614   }
00615
00616 #endif /* SWPMI1 */
00617
00618 #if defined(DFSDM1_Filter0)
00619
00620   /*-------------------------- DFSDM1 clock source configuration -------------------*/
00621   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
00622   {
00623     /* Check the parameters */
00624     assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
00625
00626     /* Configure the DFSDM1 interface clock source */
00627     __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
00628   }
00629
00630 #endif /* DFSDM1_Filter0 */
00631
00632   return status;
00633 }
00634
00635 /**
00636   * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
00637   * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
00638   *         returns the configuration information for the Extended Peripherals
00639   *         clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, LPUART,
00640   *         USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG).
00641   * @retval None
00642   */
00643 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00644 {
00645   /* Set all possible values for the extended clock type parameter------------*/
00646
00647 #if defined(STM32L431xx)
00648
00649   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |                                               \
00650                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \
00651                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                                               \
00652                                         RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \
00653                                         RCC_PERIPHCLK_RTC ;
00654
00655 #elif defined(STM32L432xx) || defined(STM32L442xx)
00656
00657   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 |                                                                      \
00658                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   |                        RCC_PERIPHCLK_I2C3   |                        \
00659                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \
00660                                                                 RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \
00661                                         RCC_PERIPHCLK_RTC ;
00662
00663 #elif defined(STM32L433xx) || defined(STM32L443xx)
00664
00665   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |                                               \
00666                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \
00667                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   |                        RCC_PERIPHCLK_USB    | \
00668                                         RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 |                        \
00669                                         RCC_PERIPHCLK_RTC ;
00670 #elif defined(STM32L471xx)
00671
00672   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
00673                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3                          | \
00674                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2                          | \
00675                                         RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
00676                                         RCC_PERIPHCLK_RTC ;
00677
00678 #elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00679
00680   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1  | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4  | RCC_PERIPHCLK_UART5  | \
00681                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2   | RCC_PERIPHCLK_I2C3   |                        \
00682                                         RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1   | RCC_PERIPHCLK_SAI2   | RCC_PERIPHCLK_USB    | \
00683                                         RCC_PERIPHCLK_SDMMC1  | RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
00684                                         RCC_PERIPHCLK_RTC ;
00685
00686 #endif /* STM32L431xx */
00687
00688   /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
00689
00690   PeriphClkInit->PLLSAI1.PLLSAI1Source = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC));
00691   PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U;
00692   PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N));
00693   PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) << 4U) + 7U;
00694   PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))+1U) * 2U;
00695   PeriphClkInit->PLLSAI1.PLLSAI1R = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))+1U) * 2U;
00696
00697 #if defined(RCC_PLLSAI2_SUPPORT)
00698
00699   /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/
00700
00701   PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source;
00702   PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M;
00703   PeriphClkInit->PLLSAI2.PLLSAI2N = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N));
00704   PeriphClkInit->PLLSAI2.PLLSAI2P = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2P) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) << 4U) + 7U;
00705   PeriphClkInit->PLLSAI2.PLLSAI2R = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2R)>> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))+1U) * 2U;
00706
00707 #endif /* RCC_PLLSAI2_SUPPORT */
00708
00709   /* Get the USART1 clock source ---------------------------------------------*/
00710   PeriphClkInit->Usart1ClockSelection  = __HAL_RCC_GET_USART1_SOURCE();
00711   /* Get the USART2 clock source ---------------------------------------------*/
00712   PeriphClkInit->Usart2ClockSelection  = __HAL_RCC_GET_USART2_SOURCE();
00713
00714 #if defined(USART3)
00715   /* Get the USART3 clock source ---------------------------------------------*/
00716   PeriphClkInit->Usart3ClockSelection  = __HAL_RCC_GET_USART3_SOURCE();
00717 #endif /* USART3 */
00718
00719 #if defined(UART4)
00720   /* Get the UART4 clock source ----------------------------------------------*/
00721   PeriphClkInit->Uart4ClockSelection   = __HAL_RCC_GET_UART4_SOURCE();
00722 #endif /* UART4 */
00723
00724 #if defined(UART5)
00725   /* Get the UART5 clock source ----------------------------------------------*/
00726   PeriphClkInit->Uart5ClockSelection   = __HAL_RCC_GET_UART5_SOURCE();
00727 #endif /* UART5 */
00728
00729   /* Get the LPUART1 clock source --------------------------------------------*/
00730   PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
00731
00732   /* Get the I2C1 clock source -----------------------------------------------*/
00733   PeriphClkInit->I2c1ClockSelection    = __HAL_RCC_GET_I2C1_SOURCE();
00734
00735 #if defined(I2C2)
00736    /* Get the I2C2 clock source ----------------------------------------------*/
00737   PeriphClkInit->I2c2ClockSelection    = __HAL_RCC_GET_I2C2_SOURCE();
00738 #endif /* I2C2 */
00739
00740   /* Get the I2C3 clock source -----------------------------------------------*/
00741   PeriphClkInit->I2c3ClockSelection    = __HAL_RCC_GET_I2C3_SOURCE();
00742
00743   /* Get the LPTIM1 clock source ---------------------------------------------*/
00744   PeriphClkInit->Lptim1ClockSelection  = __HAL_RCC_GET_LPTIM1_SOURCE();
00745
00746   /* Get the LPTIM2 clock source ---------------------------------------------*/
00747   PeriphClkInit->Lptim2ClockSelection  = __HAL_RCC_GET_LPTIM2_SOURCE();
00748
00749   /* Get the SAI1 clock source -----------------------------------------------*/
00750   PeriphClkInit->Sai1ClockSelection    = __HAL_RCC_GET_SAI1_SOURCE();
00751
00752 #if defined(SAI2)
00753   /* Get the SAI2 clock source -----------------------------------------------*/
00754   PeriphClkInit->Sai2ClockSelection    = __HAL_RCC_GET_SAI2_SOURCE();
00755 #endif /* SAI2 */
00756
00757   /* Get the RTC clock source ------------------------------------------------*/
00758   PeriphClkInit->RTCClockSelection     = __HAL_RCC_GET_RTC_SOURCE();
00759
00760 #if defined(USB_OTG_FS) || defined(USB)
00761   /* Get the USB clock source ------------------------------------------------*/
00762   PeriphClkInit->UsbClockSelection   = __HAL_RCC_GET_USB_SOURCE();
00763 #endif /* USB_OTG_FS || USB */
00764
00765 #if defined(SDMMC1)
00766   /* Get the SDMMC1 clock source ---------------------------------------------*/
00767   PeriphClkInit->Sdmmc1ClockSelection   = __HAL_RCC_GET_SDMMC1_SOURCE();
00768 #endif /* SDMMC1 */
00769
00770   /* Get the RNG clock source ------------------------------------------------*/
00771   PeriphClkInit->RngClockSelection   = __HAL_RCC_GET_RNG_SOURCE();
00772
00773   /* Get the ADC clock source ------------------------------------------------*/
00774   PeriphClkInit->AdcClockSelection     = __HAL_RCC_GET_ADC_SOURCE();
00775
00776 #if defined(SWPMI1)
00777   /* Get the SWPMI1 clock source ---------------------------------------------*/
00778   PeriphClkInit->Swpmi1ClockSelection  = __HAL_RCC_GET_SWPMI1_SOURCE();
00779 #endif /* SWPMI1 */
00780
00781 #if defined(DFSDM1_Filter0)
00782   /* Get the DFSDM1 clock source ---------------------------------------------*/
00783   PeriphClkInit->Dfsdm1ClockSelection  = __HAL_RCC_GET_DFSDM1_SOURCE();
00784 #endif /* DFSDM1_Filter0 */
00785 }
00786
00787 /**
00788   * @brief  Return the peripheral clock frequency for peripherals with clock source from PLLSAIs
00789   * @note   Return 0 if peripheral clock identifier not managed by this API
00790   * @param  PeriphClk  Peripheral clock identifier
00791   *         This parameter can be one of the following values:
00792   *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
00793   *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
00794   @if STM32L486xx
00795   *            @arg @ref RCC_PERIPHCLK_DFSDM1  DFSDM1 peripheral clock (only for devices with DFSDM)
00796   @endif
00797   *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
00798   *            @arg @ref RCC_PERIPHCLK_I2C2  I2C2 peripheral clock
00799   *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
00800   *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
00801   *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock
00802   *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
00803   *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
00804   *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
00805   @if STM32L486xx
00806   *            @arg @ref RCC_PERIPHCLK_SAI2  SAI2 peripheral clock (only for devices with SAI2)
00807   @endif
00808   *            @arg @ref RCC_PERIPHCLK_SDMMC1  SDMMC1 peripheral clock
00809   *            @arg @ref RCC_PERIPHCLK_SWPMI1  SWPMI1 peripheral clock
00810   *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
00811   *            @arg @ref RCC_PERIPHCLK_USART2  USART1 peripheral clock
00812   *            @arg @ref RCC_PERIPHCLK_USART3  USART1 peripheral clock
00813   @if STM32L486xx
00814   *            @arg @ref RCC_PERIPHCLK_UART4  UART4 peripheral clock (only for devices with UART4)
00815   *            @arg @ref RCC_PERIPHCLK_UART5  UART5 peripheral clock (only for devices with UART5)
00816   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock (only for devices with USB)
00817   @endif
00818   * @retval Frequency in Hz
00819   */
00820 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
00821 {
00822   uint32_t frequency = 0U;
00823   uint32_t srcclk = 0U;
00824   uint32_t pllvco = 0U, plln = 0U, pllp = 0U;
00825
00826   /* Check the parameters */
00827   assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
00828
00829   if(PeriphClk == RCC_PERIPHCLK_RTC)
00830   {
00831     /* Get the current RTC source */
00832     srcclk = __HAL_RCC_GET_RTC_SOURCE();
00833
00834     /* Check if LSE is ready and if RTC clock selection is LSE */
00835     if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
00836     {
00837       frequency = LSE_VALUE;
00838     }
00839     /* Check if LSI is ready and if RTC clock selection is LSI */
00840     else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
00841     {
00842       frequency = LSI_VALUE;
00843     }
00844     /* Check if HSE is ready  and if RTC clock selection is HSI_DIV32*/
00845     else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
00846     {
00847       frequency = HSE_VALUE / 32;
00848     }
00849     /* Clock not enabled for RTC*/
00850     else
00851     {
00852       frequency = 0U;
00853     }
00854   }
00855   else
00856   {
00857     /* Other external peripheral clock source than RTC */
00858
00859     /* Compute PLL clock input */
00860     if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)        /* MSI ? */
00861     {
00862       if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
00863       {
00864         pllvco = (1U << ((__HAL_RCC_GET_MSI_RANGE() >> 4U) - 4U)) * 1000000U;
00865       }
00866       else
00867       {
00868         pllvco = 0U;
00869       }
00870     }
00871     else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)   /* HSI ? */
00872     {
00873       if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
00874       {
00875         pllvco = HSI_VALUE;
00876       }
00877       else
00878       {
00879         pllvco = 0U;
00880       }
00881     }
00882     else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)   /* HSE ? */
00883     {
00884       if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
00885       {
00886         pllvco = HSE_VALUE;
00887       }
00888       else
00889       {
00890         pllvco = 0U;
00891       }
00892     }
00893     else /* No source */
00894     {
00895       pllvco = 0U;
00896     }
00897
00898     /* f(PLL Source) / PLLM */
00899     pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U));
00900
00901     switch(PeriphClk)
00902     {
00903 #if defined(SAI2)
00904
00905     case RCC_PERIPHCLK_SAI1:
00906     case RCC_PERIPHCLK_SAI2:
00907
00908       if(PeriphClk == RCC_PERIPHCLK_SAI1)
00909       {
00910         srcclk = __HAL_RCC_GET_SAI1_SOURCE();
00911
00912         if(srcclk == RCC_SAI1CLKSOURCE_PIN)
00913         {
00914           frequency = EXTERNAL_SAI1_CLOCK_VALUE;
00915         }
00916         /* Else, PLL clock output to check below */
00917       }
00918       else /* RCC_PERIPHCLK_SAI2 */
00919       {
00920         srcclk = __HAL_RCC_GET_SAI2_SOURCE();
00921
00922         if(srcclk == RCC_SAI2CLKSOURCE_PIN)
00923         {
00924           frequency = EXTERNAL_SAI2_CLOCK_VALUE;
00925         }
00926         /* Else, PLL clock output to check below */
00927       }
00928
00929 #else
00930
00931     case RCC_PERIPHCLK_SAI1:
00932
00933       if(PeriphClk == RCC_PERIPHCLK_SAI1)
00934       {
00935         srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL);
00936
00937         if(srcclk == RCC_SAI1CLKSOURCE_PIN)
00938         {
00939           frequency = EXTERNAL_SAI1_CLOCK_VALUE;
00940         }
00941         /* Else, PLL clock output to check below */
00942       }
00943
00944 #endif /* SAI2 */
00945
00946       if(frequency == 0U)
00947       {
00948 #if defined(SAI2)
00949         if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL))
00950         {
00951           if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET)
00952           {
00953             /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */
00954             plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
00955 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
00956             pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV);
00957 #endif
00958             if(pllp == 0U)
00959             {
00960               if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET)
00961               {
00962                 pllp = 17U;
00963               }
00964               else
00965               {
00966                 pllp = 7U;
00967               }
00968             }
00969             frequency = (pllvco * plln) / pllp;
00970           }
00971         }
00972         else if(srcclk == 0U)  /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */
00973         {
00974           if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
00975           {
00976             /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
00977             plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
00978 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
00979             pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV);
00980 #endif
00981             if(pllp == 0U)
00982             {
00983               if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET)
00984               {
00985                 pllp = 17U;
00986               }
00987               else
00988               {
00989                 pllp = 7U;
00990               }
00991             }
00992             frequency = (pllvco * plln) / pllp;
00993           }
00994         }
00995 #else
00996         if(srcclk == RCC_SAI1CLKSOURCE_PLL)
00997         {
00998           if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET)
00999           {
01000             /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */
01001             plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
01002 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
01003             pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV);
01004 #endif
01005             if(pllp == 0U)
01006             {
01007               if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET)
01008               {
01009                 pllp = 17U;
01010               }
01011               else
01012               {
01013                 pllp = 7U;
01014               }
01015             }
01016
01017             frequency = (pllvco * plln) / pllp;
01018           }
01019           else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
01020           {
01021             /* HSI automatically selected as clock source if PLLs not enabled */
01022             frequency = HSI_VALUE;
01023           }
01024           else
01025           {
01026             /* No clock source */
01027             frequency = 0U;
01028           }
01029         }
01030         else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1)
01031         {
01032           if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
01033           {
01034             /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
01035             plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
01036 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
01037             pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV);
01038 #endif
01039             if(pllp == 0U)
01040             {
01041               if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET)
01042               {
01043                 pllp = 17U;
01044               }
01045               else
01046               {
01047                 pllp = 7U;
01048               }
01049             }
01050
01051            frequency = (pllvco * plln) / pllp;
01052           }
01053           else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
01054           {
01055             /* HSI automatically selected as clock source if PLLs not enabled */
01056             frequency = HSI_VALUE;
01057           }
01058           else
01059           {
01060             /* No clock source */
01061             frequency = 0U;
01062           }
01063         }
01064 #endif /* SAI2 */
01065
01066 #if defined(RCC_PLLSAI2_SUPPORT)
01067
01068         else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2))
01069         {
01070           if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET)
01071           {
01072             /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */
01073             plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
01074 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
01075             pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV);
01076 #endif
01077             if(pllp == 0U)
01078             {
01079               if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET)
01080               {
01081                 pllp = 17U;
01082               }
01083               else
01084               {
01085                 pllp = 7U;
01086               }
01087             }
01088             frequency = (pllvco * plln) / pllp;
01089           }
01090         }
01091
01092 #endif /* RCC_PLLSAI2_SUPPORT */
01093
01094         else
01095         {
01096           /* No clock source */
01097           frequency = 0U;
01098         }
01099       }
01100       break;
01101
01102 #if defined(USB_OTG_FS) || defined(USB)
01103
01104     case RCC_PERIPHCLK_USB:
01105
01106 #endif /* USB_OTG_FS || USB */
01107
01108     case RCC_PERIPHCLK_RNG:
01109
01110 #if defined(SDMMC1)
01111
01112     case RCC_PERIPHCLK_SDMMC1:
01113
01114 #endif /* SDMMC1 */
01115
01116       srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
01117
01118       if(srcclk == RCC_CCIPR_CLK48SEL)   /* MSI ? */
01119       {
01120         if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
01121         {
01122           frequency = (1U << ((__HAL_RCC_GET_MSI_RANGE() >> 4U) - 4U)) * 1000000U;
01123         }
01124         else
01125         {
01126           frequency = 0U;
01127         }
01128       }
01129       else if(srcclk == RCC_CCIPR_CLK48SEL_1)  /* PLL ? */
01130       {
01131         if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
01132         {
01133           /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */
01134           plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
01135           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
01136         }
01137         else
01138         {
01139           frequency = 0U;
01140         }
01141       }
01142       else if(srcclk == RCC_CCIPR_CLK48SEL_0)  /* PLLSAI1 ? */
01143       {
01144         if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
01145         {
01146           /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */
01147           plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
01148           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) + 1U) << 1U);
01149         }
01150         else
01151         {
01152           frequency = 0U;
01153         }
01154       }
01155 #if defined(RCC_HSI48_SUPPORT)
01156       else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */
01157       {
01158         frequency = HSI48_VALUE;
01159       }
01160       else /* No clock source */
01161       {
01162         frequency = 0U;
01163       }
01164 #else
01165       else /* No clock source */
01166       {
01167         frequency = 0U;
01168       }
01169 #endif /* RCC_HSI48_SUPPORT */
01170       break;
01171
01172     case RCC_PERIPHCLK_USART1:
01173       /* Get the current USART1 source */
01174       srcclk = __HAL_RCC_GET_USART1_SOURCE();
01175
01176       if(srcclk == RCC_USART1CLKSOURCE_PCLK2)
01177       {
01178         frequency = HAL_RCC_GetPCLK2Freq();
01179       }
01180       else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK)
01181       {
01182         frequency = HAL_RCC_GetSysClockFreq();
01183       }
01184       else if((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01185       {
01186         frequency = HSI_VALUE;
01187       }
01188       else if((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01189       {
01190         frequency = LSE_VALUE;
01191       }
01192       /* Clock not enabled for USART1 */
01193       else
01194       {
01195         frequency = 0U;
01196       }
01197       break;
01198
01199     case RCC_PERIPHCLK_USART2:
01200       /* Get the current USART2 source */
01201       srcclk = __HAL_RCC_GET_USART2_SOURCE();
01202
01203       if(srcclk == RCC_USART2CLKSOURCE_PCLK1)
01204       {
01205         frequency = HAL_RCC_GetPCLK1Freq();
01206       }
01207       else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK)
01208       {
01209         frequency = HAL_RCC_GetSysClockFreq();
01210       }
01211       else if((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01212       {
01213         frequency = HSI_VALUE;
01214       }
01215       else if((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01216       {
01217         frequency = LSE_VALUE;
01218       }
01219       /* Clock not enabled for USART2 */
01220       else
01221       {
01222         frequency = 0U;
01223       }
01224       break;
01225
01226 #if defined(USART3)
01227
01228     case RCC_PERIPHCLK_USART3:
01229       /* Get the current USART3 source */
01230       srcclk = __HAL_RCC_GET_USART3_SOURCE();
01231
01232       if(srcclk == RCC_USART3CLKSOURCE_PCLK1)
01233       {
01234         frequency = HAL_RCC_GetPCLK1Freq();
01235       }
01236       else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK)
01237       {
01238         frequency = HAL_RCC_GetSysClockFreq();
01239       }
01240       else if((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01241       {
01242         frequency = HSI_VALUE;
01243       }
01244       else if((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01245       {
01246         frequency = LSE_VALUE;
01247       }
01248       /* Clock not enabled for USART3 */
01249       else
01250       {
01251         frequency = 0U;
01252       }
01253       break;
01254
01255 #endif /* USART3 */
01256
01257 #if defined(UART4)
01258
01259     case RCC_PERIPHCLK_UART4:
01260       /* Get the current UART4 source */
01261       srcclk = __HAL_RCC_GET_UART4_SOURCE();
01262
01263       if(srcclk == RCC_UART4CLKSOURCE_PCLK1)
01264       {
01265         frequency = HAL_RCC_GetPCLK1Freq();
01266       }
01267       else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK)
01268       {
01269         frequency = HAL_RCC_GetSysClockFreq();
01270       }
01271       else if((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01272       {
01273         frequency = HSI_VALUE;
01274       }
01275       else if((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01276       {
01277         frequency = LSE_VALUE;
01278       }
01279       /* Clock not enabled for UART4 */
01280       else
01281       {
01282         frequency = 0U;
01283       }
01284       break;
01285
01286 #endif /* UART4 */
01287
01288 #if defined(UART5)
01289
01290     case RCC_PERIPHCLK_UART5:
01291       /* Get the current UART5 source */
01292       srcclk = __HAL_RCC_GET_UART5_SOURCE();
01293
01294       if(srcclk == RCC_UART5CLKSOURCE_PCLK1)
01295       {
01296         frequency = HAL_RCC_GetPCLK1Freq();
01297       }
01298       else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK)
01299       {
01300         frequency = HAL_RCC_GetSysClockFreq();
01301       }
01302       else if((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01303       {
01304         frequency = HSI_VALUE;
01305       }
01306       else if((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01307       {
01308         frequency = LSE_VALUE;
01309       }
01310       /* Clock not enabled for UART5 */
01311       else
01312       {
01313         frequency = 0U;
01314       }
01315       break;
01316
01317 #endif /* UART5 */
01318
01319     case RCC_PERIPHCLK_LPUART1:
01320       /* Get the current LPUART1 source */
01321       srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
01322
01323       if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
01324       {
01325         frequency = HAL_RCC_GetPCLK1Freq();
01326       }
01327       else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
01328       {
01329         frequency = HAL_RCC_GetSysClockFreq();
01330       }
01331       else if((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01332       {
01333         frequency = HSI_VALUE;
01334       }
01335       else if((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01336       {
01337         frequency = LSE_VALUE;
01338       }
01339       /* Clock not enabled for LPUART1 */
01340       else
01341       {
01342         frequency = 0U;
01343       }
01344       break;
01345
01346     case RCC_PERIPHCLK_ADC:
01347
01348       srcclk = __HAL_RCC_GET_ADC_SOURCE();
01349
01350       if(srcclk == RCC_ADCCLKSOURCE_SYSCLK)
01351       {
01352         frequency = HAL_RCC_GetSysClockFreq();
01353       }
01354       else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI1)
01355       {
01356         if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET)
01357         {
01358           /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */
01359           plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
01360           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) + 1U) << 1U);
01361         }
01362       }
01363 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
01364       else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI2)
01365       {
01366         if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET)
01367         {
01368           /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */
01369           plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
01370           frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) + 1U) << 1U);
01371         }
01372       }
01373 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01374       /* Clock not enabled for ADC */
01375       else
01376       {
01377         frequency = 0U;
01378       }
01379       break;
01380
01381 #if defined(DFSDM1_Filter0)
01382
01383     case RCC_PERIPHCLK_DFSDM1:
01384       /* Get the current DFSDM1 source */
01385       srcclk = __HAL_RCC_GET_DFSDM1_SOURCE();
01386
01387       if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK)
01388       {
01389         frequency = HAL_RCC_GetPCLK1Freq();
01390       }
01391       else
01392       {
01393         frequency = HAL_RCC_GetSysClockFreq();
01394       }
01395       break;
01396
01397 #endif /* DFSDM1_Filter0 */
01398
01399     case RCC_PERIPHCLK_I2C1:
01400       /* Get the current I2C1 source */
01401       srcclk = __HAL_RCC_GET_I2C1_SOURCE();
01402
01403       if(srcclk == RCC_I2C1CLKSOURCE_PCLK1)
01404       {
01405         frequency = HAL_RCC_GetPCLK1Freq();
01406       }
01407       else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
01408       {
01409         frequency = HAL_RCC_GetSysClockFreq();
01410       }
01411       else if((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01412       {
01413         frequency = HSI_VALUE;
01414       }
01415       /* Clock not enabled for I2C1 */
01416       else
01417       {
01418         frequency = 0U;
01419       }
01420       break;
01421
01422 #if defined(I2C2)
01423
01424     case RCC_PERIPHCLK_I2C2:
01425       /* Get the current I2C2 source */
01426       srcclk = __HAL_RCC_GET_I2C2_SOURCE();
01427
01428       if(srcclk == RCC_I2C2CLKSOURCE_PCLK1)
01429       {
01430         frequency = HAL_RCC_GetPCLK1Freq();
01431       }
01432       else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
01433       {
01434         frequency = HAL_RCC_GetSysClockFreq();
01435       }
01436       else if((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01437       {
01438         frequency = HSI_VALUE;
01439       }
01440       /* Clock not enabled for I2C2 */
01441       else
01442       {
01443         frequency = 0U;
01444       }
01445       break;
01446
01447 #endif /* I2C2 */
01448
01449     case RCC_PERIPHCLK_I2C3:
01450       /* Get the current I2C3 source */
01451       srcclk = __HAL_RCC_GET_I2C3_SOURCE();
01452
01453       if(srcclk == RCC_I2C3CLKSOURCE_PCLK1)
01454       {
01455         frequency = HAL_RCC_GetPCLK1Freq();
01456       }
01457       else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
01458       {
01459         frequency = HAL_RCC_GetSysClockFreq();
01460       }
01461       else if((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01462       {
01463         frequency = HSI_VALUE;
01464       }
01465       /* Clock not enabled for I2C3 */
01466       else
01467       {
01468         frequency = 0U;
01469       }
01470       break;
01471
01472     case RCC_PERIPHCLK_LPTIM1:
01473       /* Get the current LPTIM1 source */
01474       srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
01475
01476       if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK)
01477       {
01478         frequency = HAL_RCC_GetPCLK1Freq();
01479       }
01480       else if((srcclk == RCC_LPTIM1CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
01481       {
01482         frequency = LSI_VALUE;
01483       }
01484       else if((srcclk == RCC_LPTIM1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01485       {
01486         frequency = HSI_VALUE;
01487       }
01488       else if ((srcclk == RCC_LPTIM1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01489       {
01490         frequency = LSE_VALUE;
01491       }
01492       /* Clock not enabled for LPTIM1 */
01493       else
01494       {
01495         frequency = 0U;
01496       }
01497       break;
01498
01499     case RCC_PERIPHCLK_LPTIM2:
01500       /* Get the current LPTIM2 source */
01501       srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
01502
01503       if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK)
01504       {
01505         frequency = HAL_RCC_GetPCLK1Freq();
01506       }
01507       else if((srcclk == RCC_LPTIM2CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
01508       {
01509         frequency = LSI_VALUE;
01510       }
01511       else if((srcclk == RCC_LPTIM2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01512       {
01513         frequency = HSI_VALUE;
01514       }
01515       else if ((srcclk == RCC_LPTIM2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
01516       {
01517         frequency = LSE_VALUE;
01518       }
01519       /* Clock not enabled for LPTIM2 */
01520       else
01521       {
01522         frequency = 0U;
01523       }
01524       break;
01525
01526 #if defined(SWPMI1)
01527
01528     case RCC_PERIPHCLK_SWPMI1:
01529       /* Get the current SWPMI1 source */
01530       srcclk = __HAL_RCC_GET_SWPMI1_SOURCE();
01531
01532       if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK)
01533       {
01534         frequency = HAL_RCC_GetPCLK1Freq();
01535       }
01536       else if((srcclk == RCC_SWPMI1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
01537       {
01538         frequency = HSI_VALUE;
01539       }
01540       /* Clock not enabled for SWPMI1 */
01541       else
01542       {
01543         frequency = 0U;
01544       }
01545       break;
01546
01547 #endif /* SWPMI1 */
01548
01549     default:
01550       break;
01551     }
01552   }
01553
01554   return(frequency);
01555 }
01556
01557 /**
01558   * @}
01559   */
01560
01561 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
01562  *  @brief  Extended Clock management functions
01563  *
01564 @verbatim
01565  ===============================================================================
01566                 ##### Extended clock management functions  #####
01567  ===============================================================================
01568     [..]
01569     This subsection provides a set of functions allowing to control the
01570     activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS,
01571     Low speed clock output and clock after wake-up from STOP mode.
01572 @endverbatim
01573   * @{
01574   */
01575
01576 /**
01577   * @brief  Enable PLLSAI1.
01578   * @param  PLLSAI1Init  pointer to an RCC_PLLSAI1InitTypeDef structure that
01579   *         contains the configuration information for the PLLSAI1
01580   * @retval HAL status
01581   */
01582 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init)
01583 {
01584   uint32_t tickstart = 0U;
01585   HAL_StatusTypeDef status = HAL_OK;
01586
01587   /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
01588   assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source));
01589   assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M));
01590   assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N));
01591   assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P));
01592   assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q));
01593   assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R));
01594   assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut));
01595
01596   /* Disable the PLLSAI1 */
01597   __HAL_RCC_PLLSAI1_DISABLE();
01598
01599   /* Get Start Tick*/
01600   tickstart = HAL_GetTick();
01601
01602   /* Wait till PLLSAI1 is ready to be updated */
01603   while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
01604   {
01605     if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
01606     {
01607       status = HAL_TIMEOUT;
01608       break;
01609     }
01610   }
01611
01612   if(status == HAL_OK)
01613   {
01614     /* Configure the PLLSAI1 Multiplication factor N */
01615     /* Configure the PLLSAI1 Division factors P, Q and R */
01616     __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);
01617     /* Configure the PLLSAI1 Clock output(s) */
01618     __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut);
01619
01620     /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
01621     __HAL_RCC_PLLSAI1_ENABLE();
01622
01623     /* Get Start Tick*/
01624     tickstart = HAL_GetTick();
01625
01626     /* Wait till PLLSAI1 is ready */
01627     while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
01628     {
01629       if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
01630       {
01631         status = HAL_TIMEOUT;
01632         break;
01633       }
01634     }
01635   }
01636
01637   return status;
01638 }
01639
01640 /**
01641   * @brief  Disable PLLSAI1.
01642   * @retval HAL status
01643   */
01644 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
01645 {
01646   uint32_t tickstart = 0U;
01647   HAL_StatusTypeDef status = HAL_OK;
01648
01649   /* Disable the PLLSAI1 */
01650   __HAL_RCC_PLLSAI1_DISABLE();
01651
01652   /* Get Start Tick*/
01653   tickstart = HAL_GetTick();
01654
01655   /* Wait till PLLSAI1 is ready */
01656   while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
01657   {
01658     if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
01659     {
01660       status = HAL_TIMEOUT;
01661       break;
01662     }
01663   }
01664
01665   /* Disable the PLLSAI1 Clock outputs */
01666   __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN);
01667
01668   /* Reset PLL source to save power if no PLLs on */
01669   if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
01670 #if defined(RCC_PLLSAI2_SUPPORT)
01671       &&
01672      (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
01673 #endif /* RCC_PLLSAI2_SUPPORT */
01674     )
01675   {
01676     MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
01677   }
01678
01679   return status;
01680 }
01681
01682 #if defined(RCC_PLLSAI2_SUPPORT)
01683
01684 /**
01685   * @brief  Enable PLLSAI2.
01686   * @param  PLLSAI2Init  pointer to an RCC_PLLSAI2InitTypeDef structure that
01687   *         contains the configuration information for the PLLSAI2
01688   * @retval HAL status
01689   */
01690 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init)
01691 {
01692   uint32_t tickstart = 0U;
01693   HAL_StatusTypeDef status = HAL_OK;
01694
01695   /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
01696   assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source));
01697   assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M));
01698   assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N));
01699   assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P));
01700   assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R));
01701   assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut));
01702
01703   /* Disable the PLLSAI2 */
01704   __HAL_RCC_PLLSAI2_DISABLE();
01705
01706   /* Get Start Tick*/
01707   tickstart = HAL_GetTick();
01708
01709   /* Wait till PLLSAI2 is ready to be updated */
01710   while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
01711   {
01712     if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
01713     {
01714       status = HAL_TIMEOUT;
01715       break;
01716     }
01717   }
01718
01719   if(status == HAL_OK)
01720   {
01721     /* Configure the PLLSAI2 Multiplication factor N */
01722     /* Configure the PLLSAI2 Division factors P and R */
01723     __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);
01724     /* Configure the PLLSAI2 Clock output(s) */
01725     __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut);
01726
01727     /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
01728     __HAL_RCC_PLLSAI2_ENABLE();
01729
01730     /* Get Start Tick*/
01731     tickstart = HAL_GetTick();
01732
01733     /* Wait till PLLSAI2 is ready */
01734     while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
01735     {
01736       if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
01737       {
01738         status = HAL_TIMEOUT;
01739         break;
01740       }
01741     }
01742   }
01743
01744   return status;
01745 }
01746
01747 /**
01748   * @brief  Disable PLLISAI2.
01749   * @retval HAL status
01750   */
01751 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)
01752 {
01753   uint32_t tickstart = 0U;
01754   HAL_StatusTypeDef status = HAL_OK;
01755
01756   /* Disable the PLLSAI2 */
01757   __HAL_RCC_PLLSAI2_DISABLE();
01758
01759   /* Get Start Tick*/
01760   tickstart = HAL_GetTick();
01761
01762   /* Wait till PLLSAI2 is ready */
01763   while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
01764   {
01765     if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
01766     {
01767       status = HAL_TIMEOUT;
01768       break;
01769     }
01770   }
01771
01772   /* Disable the PLLSAI2 Clock outputs */
01773   __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN);
01774
01775   /* Reset PLL source to save power if no PLLs on */
01776   if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
01777       &&
01778      (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
01779     )
01780   {
01781     MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
01782   }
01783
01784   return status;
01785 }
01786
01787 #endif /* RCC_PLLSAI2_SUPPORT */
01788
01789 /**
01790   * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
01791   * @param  WakeUpClk  Wakeup clock
01792   *         This parameter can be one of the following values:
01793   *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI oscillator selection
01794   *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI oscillator selection
01795   * @note   This function shall not be called after the Clock Security System on HSE has been
01796   *         enabled.
01797   * @retval None
01798   */
01799 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
01800 {
01801   assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
01802
01803   __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
01804 }
01805
01806 /**
01807   * @brief  Configure the MSI range after standby mode.
01808   * @note   After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
01809   * @param  MSIRange  MSI range
01810   *         This parameter can be one of the following values:
01811   *            @arg @ref RCC_MSIRANGE_4  Range 4 around 1 MHz
01812   *            @arg @ref RCC_MSIRANGE_5  Range 5 around 2 MHz
01813   *            @arg @ref RCC_MSIRANGE_6  Range 6 around 4 MHz (reset value)
01814   *            @arg @ref RCC_MSIRANGE_7  Range 7 around 8 MHz
01815   * @retval None
01816   */
01817 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
01818 {
01819   assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
01820
01821   __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
01822 }
01823
01824 /**
01825   * @brief  Enable the LSE Clock Security System.
01826   * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
01827   *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
01828   *         clock with HAL_RCCEx_PeriphCLKConfig().
01829   * @retval None
01830   */
01831 void HAL_RCCEx_EnableLSECSS(void)
01832 {
01833   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
01834 }
01835
01836 /**
01837   * @brief  Disable the LSE Clock Security System.
01838   * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
01839   * @retval None
01840   */
01841 void HAL_RCCEx_DisableLSECSS(void)
01842 {
01843   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
01844
01845   /* Disable LSE CSS IT if any */
01846   __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
01847 }
01848
01849 /**
01850   * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
01851   * @note   LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
01852   * @retval None
01853   */
01854 void HAL_RCCEx_EnableLSECSS_IT(void)
01855 {
01856   /* Enable LSE CSS */
01857   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
01858
01859   /* Enable LSE CSS IT */
01860   __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
01861
01862   /* Enable IT on EXTI Line 19 */
01863   __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
01864   __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
01865 }
01866
01867 /**
01868   * @brief Handle the RCC LSE Clock Security System interrupt request.
01869   * @retval None
01870   */
01871 void HAL_RCCEx_LSECSS_IRQHandler(void)
01872 {
01873   /* Check RCC LSE CSSF flag  */
01874   if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
01875   {
01876     /* RCC LSE Clock Security System interrupt user callback */
01877     HAL_RCCEx_LSECSS_Callback();
01878
01879     /* Clear RCC LSE CSS pending bit */
01880     __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
01881   }
01882 }
01883
01884 /**
01885   * @brief  RCCEx LSE Clock Security System interrupt callback.
01886   * @retval none
01887   */
01888 __weak void HAL_RCCEx_LSECSS_Callback(void)
01889 {
01890   /* NOTE : This function should not be modified, when the callback is needed,
01891             the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
01892    */
01893 }
01894
01895 /**
01896   * @brief  Select the Low Speed clock source to output on LSCO pin (PA2).
01897   * @param  LSCOSource  specifies the Low Speed clock source to output.
01898   *          This parameter can be one of the following values:
01899   *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source
01900   *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source
01901   * @retval None
01902   */
01903 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
01904 {
01905   GPIO_InitTypeDef GPIO_InitStruct;
01906   FlagStatus       pwrclkchanged = RESET;
01907   FlagStatus       backupchanged = RESET;
01908
01909   /* Check the parameters */
01910   assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
01911
01912   /* LSCO Pin Clock Enable */
01913   __LSCO_CLK_ENABLE();
01914
01915   /* Configue the LSCO pin in analog mode */
01916   GPIO_InitStruct.Pin = LSCO_PIN;
01917   GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
01918   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
01919   GPIO_InitStruct.Pull = GPIO_NOPULL;
01920   HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
01921
01922   /* Update LSCOSEL clock source in Backup Domain control register */
01923   if(__HAL_RCC_PWR_IS_CLK_DISABLED())
01924   {
01925     __HAL_RCC_PWR_CLK_ENABLE();
01926     pwrclkchanged = SET;
01927   }
01928   if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
01929   {
01930     HAL_PWR_EnableBkUpAccess();
01931     backupchanged = SET;
01932   }
01933
01934   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
01935
01936   if(backupchanged == SET)
01937   {
01938     HAL_PWR_DisableBkUpAccess();
01939   }
01940   if(pwrclkchanged == SET)
01941   {
01942     __HAL_RCC_PWR_CLK_DISABLE();
01943   }
01944 }
01945
01946 /**
01947   * @brief  Disable the Low Speed clock output.
01948   * @retval None
01949   */
01950 void HAL_RCCEx_DisableLSCO(void)
01951 {
01952   FlagStatus       pwrclkchanged = RESET;
01953   FlagStatus       backupchanged = RESET;
01954
01955   /* Update LSCOEN bit in Backup Domain control register */
01956   if(__HAL_RCC_PWR_IS_CLK_DISABLED())
01957   {
01958     __HAL_RCC_PWR_CLK_ENABLE();
01959     pwrclkchanged = SET;
01960   }
01961   if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
01962   {
01963     /* Enable access to the backup domain */
01964     HAL_PWR_EnableBkUpAccess();
01965     backupchanged = SET;
01966   }
01967
01968   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01969
01970   /* Restore previous configuration */
01971   if(backupchanged == SET)
01972   {
01973     /* Disable access to the backup domain */
01974     HAL_PWR_DisableBkUpAccess();
01975   }
01976   if(pwrclkchanged == SET)
01977   {
01978     __HAL_RCC_PWR_CLK_DISABLE();
01979   }
01980 }
01981
01982 /**
01983   * @brief  Enable the PLL-mode of the MSI.
01984   * @note   Prior to enable the PLL-mode of the MSI for automatic hardware
01985   *         calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
01986   * @retval None
01987   */
01988 void HAL_RCCEx_EnableMSIPLLMode(void)
01989 {
01990   SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
01991 }
01992
01993 /**
01994   * @brief  Disable the PLL-mode of the MSI.
01995   * @note   PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
01996   * @retval None
01997   */
01998 void HAL_RCCEx_DisableMSIPLLMode(void)
01999 {
02000   CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
02001 }
02002
02003 /**
02004   * @}
02005   */
02006
02007 #if defined(CRS)
02008
02009 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
02010  *  @brief  Extended Clock Recovery System Control functions
02011  *
02012 @verbatim
02013  ===============================================================================
02014                 ##### Extended Clock Recovery System Control functions  #####
02015  ===============================================================================
02016     [..]
02017       For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
02018
02019       (#) In System clock config, HSI48 needs to be enabled
02020
02021       (#) Enable CRS clock in IP MSP init which will use CRS functions
02022
02023       (#) Call CRS functions as follows:
02024           (##) Prepare synchronization configuration necessary for HSI48 calibration
02025               (+++) Default values can be set for frequency Error Measurement (reload and error limit)
02026                         and also HSI48 oscillator smooth trimming.
02027               (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
02028                         directly reload value with target and sychronization frequencies values
02029           (##) Call function HAL_RCCEx_CRSConfig which
02030               (+++) Resets CRS registers to their default values.
02031               (+++) Configures CRS registers with synchronization configuration
02032               (+++) Enables automatic calibration and frequency error counter feature
02033            Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
02034            periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
02035            provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
02036            precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
02037            should be used as SYNC signal.
02038
02039           (##) A polling function is provided to wait for complete synchronization
02040               (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
02041               (+++) According to CRS status, user can decide to adjust again the calibration or continue
02042                         application if synchronization is OK
02043
02044       (#) User can retrieve information related to synchronization in calling function
02045             HAL_RCCEx_CRSGetSynchronizationInfo()
02046
02047       (#) Regarding synchronization status and synchronization information, user can try a new calibration
02048            in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
02049            Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
02050            it means that the actual frequency is lower than the target (and so, that the TRIM value should be
02051            incremented), while when it is detected during the upcounting phase it means that the actual frequency
02052            is higher (and that the TRIM value should be decremented).
02053
02054       (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
02055           through CRS Handler (CRS_IRQn/CRS_IRQHandler)
02056               (++) Call function HAL_RCCEx_CRSConfig()
02057               (++) Enable CRS_IRQn (thanks to NVIC functions)
02058               (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
02059               (++) Implement CRS status management in the following user callbacks called from
02060                    HAL_RCCEx_CRS_IRQHandler():
02061                    (+++) HAL_RCCEx_CRS_SyncOkCallback()
02062                    (+++) HAL_RCCEx_CRS_SyncWarnCallback()
02063                    (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
02064                    (+++) HAL_RCCEx_CRS_ErrorCallback()
02065
02066       (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
02067           This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
02068
02069 @endverbatim
02070  * @{
02071  */
02072
02073 /**
02074   * @brief  Start automatic synchronization for polling mode
02075   * @param  pInit Pointer on RCC_CRSInitTypeDef structure
02076   * @retval None
02077   */
02078 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
02079 {
02080   uint32_t value = 0;
02081
02082   /* Check the parameters */
02083   assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
02084   assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
02085   assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
02086   assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
02087   assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
02088   assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
02089
02090   /* CONFIGURATION */
02091
02092   /* Before configuration, reset CRS registers to their default values*/
02093   __HAL_RCC_CRS_FORCE_RESET();
02094   __HAL_RCC_CRS_RELEASE_RESET();
02095
02096   /* Set the SYNCDIV[2:0] bits according to Prescaler value */
02097   /* Set the SYNCSRC[1:0] bits according to Source value */
02098   /* Set the SYNCSPOL bit according to Polarity value */
02099   value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
02100   /* Set the RELOAD[15:0] bits according to ReloadValue value */
02101   value |= pInit->ReloadValue;
02102   /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
02103   value |= (pInit->ErrorLimitValue << POSITION_VAL(CRS_CFGR_FELIM));
02104   WRITE_REG(CRS->CFGR, value);
02105
02106   /* Adjust HSI48 oscillator smooth trimming */
02107   /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
02108   MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << POSITION_VAL(CRS_CR_TRIM)));
02109
02110   /* START AUTOMATIC SYNCHRONIZATION*/
02111
02112   /* Enable Automatic trimming & Frequency error counter */
02113   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
02114 }
02115
02116 /**
02117   * @brief  Generate the software synchronization event
02118   * @retval None
02119   */
02120 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
02121 {
02122   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
02123 }
02124
02125 /**
02126   * @brief  Return synchronization info
02127   * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
02128   * @retval None
02129   */
02130 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
02131 {
02132   /* Check the parameter */
02133   assert_param(pSynchroInfo != NULL);
02134
02135   /* Get the reload value */
02136   pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
02137
02138   /* Get HSI48 oscillator smooth trimming */
02139   pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> POSITION_VAL(CRS_CR_TRIM));
02140
02141   /* Get Frequency error capture */
02142   pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> POSITION_VAL(CRS_ISR_FECAP));
02143
02144   /* Get Frequency error direction */
02145   pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
02146 }
02147
02148 /**
02149 * @brief Wait for CRS Synchronization status.
02150 * @param Timeout  Duration of the timeout
02151 * @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
02152 *        frequency.
02153 * @note    If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
02154 * @retval Combination of Synchronization status
02155 *          This parameter can be a combination of the following values:
02156 *            @arg @ref RCC_CRS_TIMEOUT
02157 *            @arg @ref RCC_CRS_SYNCOK
02158 *            @arg @ref RCC_CRS_SYNCWARN
02159 *            @arg @ref RCC_CRS_SYNCERR
02160 *            @arg @ref RCC_CRS_SYNCMISS
02161 *            @arg @ref RCC_CRS_TRIMOVF
02162 */
02163 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
02164 {
02165   uint32_t crsstatus = RCC_CRS_NONE;
02166   uint32_t tickstart = 0U;
02167
02168   /* Get timeout */
02169   tickstart = HAL_GetTick();
02170
02171   /* Wait for CRS flag or timeout detection */
02172   do
02173   {
02174     if(Timeout != HAL_MAX_DELAY)
02175     {
02176       if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
02177       {
02178         crsstatus = RCC_CRS_TIMEOUT;
02179       }
02180     }
02181     /* Check CRS SYNCOK flag  */
02182     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
02183     {
02184       /* CRS SYNC event OK */
02185       crsstatus |= RCC_CRS_SYNCOK;
02186
02187       /* Clear CRS SYNC event OK bit */
02188       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
02189     }
02190
02191     /* Check CRS SYNCWARN flag  */
02192     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
02193     {
02194       /* CRS SYNC warning */
02195       crsstatus |= RCC_CRS_SYNCWARN;
02196
02197       /* Clear CRS SYNCWARN bit */
02198       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
02199     }
02200
02201     /* Check CRS TRIM overflow flag  */
02202     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
02203     {
02204       /* CRS SYNC Error */
02205       crsstatus |= RCC_CRS_TRIMOVF;
02206
02207       /* Clear CRS Error bit */
02208       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
02209     }
02210
02211     /* Check CRS Error flag  */
02212     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
02213     {
02214       /* CRS SYNC Error */
02215       crsstatus |= RCC_CRS_SYNCERR;
02216
02217       /* Clear CRS Error bit */
02218       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
02219     }
02220
02221     /* Check CRS SYNC Missed flag  */
02222     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
02223     {
02224       /* CRS SYNC Missed */
02225       crsstatus |= RCC_CRS_SYNCMISS;
02226
02227       /* Clear CRS SYNC Missed bit */
02228       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
02229     }
02230
02231     /* Check CRS Expected SYNC flag  */
02232     if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
02233     {
02234       /* frequency error counter reached a zero value */
02235       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
02236     }
02237   } while(RCC_CRS_NONE == crsstatus);
02238
02239   return crsstatus;
02240 }
02241
02242 /**
02243   * @brief Handle the Clock Recovery System interrupt request.
02244   * @retval None
02245   */
02246 void HAL_RCCEx_CRS_IRQHandler(void)
02247 {
02248   uint32_t crserror = RCC_CRS_NONE;
02249   /* Get current IT flags and IT sources values */
02250   uint32_t itflags = READ_REG(CRS->ISR);
02251   uint32_t itsources = READ_REG(CRS->CR);
02252
02253   /* Check CRS SYNCOK flag  */
02254   if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET))
02255   {
02256     /* Clear CRS SYNC event OK flag */
02257     WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
02258
02259     /* user callback */
02260     HAL_RCCEx_CRS_SyncOkCallback();
02261   }
02262   /* Check CRS SYNCWARN flag  */
02263   else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET))
02264   {
02265     /* Clear CRS SYNCWARN flag */
02266     WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
02267
02268     /* user callback */
02269     HAL_RCCEx_CRS_SyncWarnCallback();
02270   }
02271   /* Check CRS Expected SYNC flag  */
02272   else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET))
02273   {
02274     /* frequency error counter reached a zero value */
02275     WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
02276
02277     /* user callback */
02278     HAL_RCCEx_CRS_ExpectedSyncCallback();
02279   }
02280   /* Check CRS Error flags  */
02281   else
02282   {
02283     if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET))
02284     {
02285       if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET)
02286       {
02287         crserror |= RCC_CRS_SYNCERR;
02288       }
02289       if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET)
02290       {
02291         crserror |= RCC_CRS_SYNCMISS;
02292       }
02293       if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET)
02294       {
02295         crserror |= RCC_CRS_TRIMOVF;
02296       }
02297
02298       /* Clear CRS Error flags */
02299       WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
02300
02301       /* user error callback */
02302       HAL_RCCEx_CRS_ErrorCallback(crserror);
02303     }
02304   }
02305 }
02306
02307 /**
02308   * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
02309   * @retval none
02310   */
02311 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
02312 {
02313   /* NOTE : This function should not be modified, when the callback is needed,
02314             the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
02315    */
02316 }
02317
02318 /**
02319   * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
02320   * @retval none
02321   */
02322 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
02323 {
02324   /* NOTE : This function should not be modified, when the callback is needed,
02325             the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
02326    */
02327 }
02328
02329 /**
02330   * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
02331   * @retval none
02332   */
02333 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
02334 {
02335   /* NOTE : This function should not be modified, when the callback is needed,
02336             the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
02337    */
02338 }
02339
02340 /**
02341   * @brief  RCCEx Clock Recovery System Error interrupt callback.
02342   * @param  Error Combination of Error status.
02343   *         This parameter can be a combination of the following values:
02344   *           @arg @ref RCC_CRS_SYNCERR
02345   *           @arg @ref RCC_CRS_SYNCMISS
02346   *           @arg @ref RCC_CRS_TRIMOVF
02347   * @retval none
02348   */
02349 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
02350 {
02351   /* Prevent unused argument(s) compilation warning */
02352   UNUSED(Error);
02353
02354   /* NOTE : This function should not be modified, when the callback is needed,
02355             the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
02356    */
02357 }
02358
02359 /**
02360   * @}
02361   */
02362
02363 #endif /* CRS */
02364
02365 /**
02366   * @}
02367   */
02368
02369 /** @addtogroup RCCEx_Private_Functions
02370  * @{
02371  */
02372
02373 /**
02374   * @brief  Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s).
02375   * @param  PllSai1  pointer to an RCC_PLLSAI1InitTypeDef structure that
02376   *         contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s)
02377   * @param  Divider  divider parameter to be updated
02378   *
02379   * @note   PLLSAI1 is temporary disable to apply new parameters
02380   *
02381   * @retval HAL status
02382   */
02383 static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
02384 {
02385   uint32_t tickstart = 0U;
02386   HAL_StatusTypeDef status = HAL_OK;
02387
02388   /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
02389   /* P, Q and R dividers are verified in each specific divider case below */
02390   assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source));
02391   assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
02392   assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
02393   assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
02394
02395   /* Check that PLLSAI1 clock source and divider M can be applied */
02396   if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
02397   {
02398     /* PLL clock source and divider M already set, check that no request for change  */
02399     if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
02400        ||
02401        (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
02402        ||
02403        (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai1->PLLSAI1M)
02404       )
02405     {
02406       status = HAL_ERROR;
02407     }
02408   }
02409   else
02410   {
02411     /* Check PLLSAI1 clock source availability */
02412     switch(PllSai1->PLLSAI1Source)
02413     {
02414     case RCC_PLLSOURCE_MSI:
02415       if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
02416       {
02417         status = HAL_ERROR;
02418       }
02419       break;
02420     case RCC_PLLSOURCE_HSI:
02421       if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
02422       {
02423         status = HAL_ERROR;
02424       }
02425       break;
02426     case RCC_PLLSOURCE_HSE:
02427       if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
02428       {
02429         status = HAL_ERROR;
02430       }
02431       break;
02432     default:
02433       status = HAL_ERROR;
02434       break;
02435     }
02436
02437     if(status == HAL_OK)
02438     {
02439       /* Set PLLSAI1 clock source and divider M */
02440       MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM));
02441     }
02442   }
02443
02444   if(status == HAL_OK)
02445   {
02446     /* Disable the PLLSAI1 */
02447     __HAL_RCC_PLLSAI1_DISABLE();
02448
02449     /* Get Start Tick*/
02450     tickstart = HAL_GetTick();
02451
02452     /* Wait till PLLSAI1 is ready to be updated */
02453     while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET)
02454     {
02455       if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
02456       {
02457         status = HAL_TIMEOUT;
02458         break;
02459       }
02460     }
02461
02462     if(status == HAL_OK)
02463     {
02464       if(Divider == DIVIDER_P_UPDATE)
02465       {
02466         assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P));
02467         /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/
02468 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
02469         MODIFY_REG(RCC->PLLSAI1CFGR,
02470                    RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
02471                    (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
02472                    (PllSai1->PLLSAI1P << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)));
02473 #else
02474         MODIFY_REG(RCC->PLLSAI1CFGR,
02475                    RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P,
02476                    (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
02477                    ((PllSai1->PLLSAI1P >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)));
02478 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
02479       }
02480       else if(Divider == DIVIDER_Q_UPDATE)
02481       {
02482         assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q));
02483         /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
02484         MODIFY_REG(RCC->PLLSAI1CFGR,
02485                    RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
02486                    (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
02487                    (((PllSai1->PLLSAI1Q >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)));
02488       }
02489       else
02490       {
02491         assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R));
02492         /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
02493         MODIFY_REG(RCC->PLLSAI1CFGR,
02494                    RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
02495                    (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
02496                    (((PllSai1->PLLSAI1R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)));
02497       }
02498
02499       /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
02500       __HAL_RCC_PLLSAI1_ENABLE();
02501
02502       /* Get Start Tick*/
02503       tickstart = HAL_GetTick();
02504
02505       /* Wait till PLLSAI1 is ready */
02506       while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
02507       {
02508         if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
02509         {
02510           status = HAL_TIMEOUT;
02511           break;
02512         }
02513       }
02514
02515       if(status == HAL_OK)
02516       {
02517         /* Configure the PLLSAI1 Clock output(s) */
02518         __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
02519       }
02520     }
02521   }
02522
02523   return status;
02524 }
02525
02526 #if defined(RCC_PLLSAI2_SUPPORT)
02527
02528 /**
02529   * @brief  Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s).
02530   * @param  PllSai2  pointer to an RCC_PLLSAI2InitTypeDef structure that
02531   *         contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s)
02532   * @param  Divider  divider parameter to be updated
02533   *
02534   * @note   PLLSAI2 is temporary disable to apply new parameters
02535   *
02536   * @retval HAL status
02537   */
02538 static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
02539 {
02540   uint32_t tickstart = 0U;
02541   HAL_StatusTypeDef status = HAL_OK;
02542
02543   /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
02544   /* P, Q and R dividers are verified in each specific divider case below */
02545   assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source));
02546   assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
02547   assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
02548   assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
02549
02550   /* Check that PLLSAI2 clock source and divider M can be applied */
02551   if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
02552   {
02553     /* PLL clock source and divider M already set, check that no request for change  */
02554     if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
02555        ||
02556        (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
02557        ||
02558        (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai2->PLLSAI2M)
02559       )
02560     {
02561       status = HAL_ERROR;
02562     }
02563   }
02564   else
02565   {
02566     /* Check PLLSAI2 clock source availability */
02567     switch(PllSai2->PLLSAI2Source)
02568     {
02569     case RCC_PLLSOURCE_MSI:
02570       if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
02571       {
02572         status = HAL_ERROR;
02573       }
02574       break;
02575     case RCC_PLLSOURCE_HSI:
02576       if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
02577       {
02578         status = HAL_ERROR;
02579       }
02580       break;
02581     case RCC_PLLSOURCE_HSE:
02582       if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
02583       {
02584         status = HAL_ERROR;
02585       }
02586       break;
02587     default:
02588       status = HAL_ERROR;
02589       break;
02590     }
02591
02592     if(status == HAL_OK)
02593     {
02594       /* Set PLLSAI2 clock source and divider M */
02595       MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM));
02596     }
02597   }
02598
02599   if(status == HAL_OK)
02600   {
02601     /* Disable the PLLSAI2 */
02602     __HAL_RCC_PLLSAI2_DISABLE();
02603
02604     /* Get Start Tick*/
02605     tickstart = HAL_GetTick();
02606
02607     /* Wait till PLLSAI2 is ready to be updated */
02608     while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET)
02609     {
02610       if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
02611       {
02612         status = HAL_TIMEOUT;
02613         break;
02614       }
02615     }
02616
02617     if(status == HAL_OK)
02618     {
02619       if(Divider == DIVIDER_P_UPDATE)
02620       {
02621         assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P));
02622         /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/
02623 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
02624         MODIFY_REG(RCC->PLLSAI2CFGR,
02625                    RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
02626                    (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) |
02627                    (PllSai2->PLLSAI2P << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)));
02628 #else
02629         MODIFY_REG(RCC->PLLSAI2CFGR,
02630                    RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P,
02631                    (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) |
02632                    ((PllSai2->PLLSAI2P >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)));
02633 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
02634       }
02635       else
02636       {
02637         assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R));
02638         /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
02639         MODIFY_REG(RCC->PLLSAI2CFGR,
02640                    RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,
02641                    (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) |
02642                    (((PllSai2->PLLSAI2R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)));
02643       }
02644
02645       /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
02646       __HAL_RCC_PLLSAI2_ENABLE();
02647
02648       /* Get Start Tick*/
02649       tickstart = HAL_GetTick();
02650
02651       /* Wait till PLLSAI2 is ready */
02652       while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
02653       {
02654         if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
02655         {
02656           status = HAL_TIMEOUT;
02657           break;
02658         }
02659       }
02660
02661       if(status == HAL_OK)
02662       {
02663         /* Configure the PLLSAI2 Clock output(s) */
02664         __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
02665       }
02666     }
02667   }
02668
02669   return status;
02670 }
02671
02672 #endif /* RCC_PLLSAI2_SUPPORT */
02673
02674 /**
02675   * @}
02676   */
02677
02678 /**
02679   * @}
02680   */
02681
02682 #endif /* HAL_RCC_MODULE_ENABLED */
02683 /**
02684   * @}
02685   */
02686
02687 /**
02688   * @}
02689   */
02690
02691 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
02692
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rcc_ex.h Source File

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stm32l4xx_hal_rcc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of RCC HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_RCC_EX_H
00040 #define __STM32L4xx_HAL_RCC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RCCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  PLLSAI1 Clock structure definition
00065   */
00066 typedef struct
00067 {
00068
00069   uint32_t PLLSAI1Source;    /*!< PLLSAI1Source: PLLSAI1 entry clock source.
00070                                   This parameter must be a value of @ref RCC_PLL_Clock_Source */
00071
00072   uint32_t PLLSAI1M;         /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
00073                                   This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
00074
00075   uint32_t PLLSAI1N;         /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
00076                                   This parameter must be a number between 8 and 86 or 127 depending on devices. */
00077
00078   uint32_t PLLSAI1P;         /*!< PLLSAI1P: specifies the division factor for SAI clock.
00079                                   This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
00080
00081   uint32_t PLLSAI1Q;         /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
00082                                   This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
00083
00084   uint32_t PLLSAI1R;         /*!< PLLSAI1R: specifies the division factor for ADC clock.
00085                                   This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
00086
00087   uint32_t PLLSAI1ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
00088                                   This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
00089 }RCC_PLLSAI1InitTypeDef;
00090
00091 #if defined(RCC_PLLSAI2_SUPPORT)
00092
00093 /**
00094   * @brief  PLLSAI2 Clock structure definition
00095   */
00096 typedef struct
00097 {
00098
00099   uint32_t PLLSAI2Source;    /*!< PLLSAI2Source: PLLSAI2 entry clock source.
00100                                   This parameter must be a value of @ref RCC_PLL_Clock_Source */
00101
00102   uint32_t PLLSAI2M;         /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
00103                                   This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
00104
00105   uint32_t PLLSAI2N;         /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
00106                                   This parameter must be a number between 8 and 86 or 127 depending on devices. */
00107
00108   uint32_t PLLSAI2P;         /*!< PLLSAI2P: specifies the division factor for SAI clock.
00109                                   This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
00110
00111   uint32_t PLLSAI2R;         /*!< PLLSAI2R: specifies the division factor for ADC clock.
00112                                   This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
00113
00114   uint32_t PLLSAI2ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
00115                                   This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
00116 }RCC_PLLSAI2InitTypeDef;
00117
00118 #endif /* RCC_PLLSAI2_SUPPORT */
00119
00120 /**
00121   * @brief  RCC extended clocks structure definition
00122   */
00123 typedef struct
00124 {
00125   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
00126                                         This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00127
00128   RCC_PLLSAI1InitTypeDef PLLSAI1;  /*!< PLLSAI1 structure parameters.
00129                                         This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
00130
00131 #if defined(RCC_PLLSAI2_SUPPORT)
00132
00133   RCC_PLLSAI2InitTypeDef PLLSAI2;  /*!< PLLSAI2 structure parameters.
00134                                         This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
00135
00136 #endif /* RCC_PLLSAI2_SUPPORT */
00137
00138   uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.
00139                                         This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00140
00141   uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.
00142                                         This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
00143
00144 #if defined(USART3)
00145
00146   uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source.
00147                                         This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
00148
00149 #endif /* USART3 */
00150
00151 #if defined(UART4)
00152
00153   uint32_t Uart4ClockSelection;    /*!< Specifies UART4 clock source.
00154                                         This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
00155
00156 #endif /* UART4 */
00157
00158 #if defined(UART5)
00159
00160   uint32_t Uart5ClockSelection;    /*!< Specifies UART5 clock source.
00161                                         This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
00162
00163 #endif /* UART5 */
00164
00165   uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.
00166                                         This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
00167
00168   uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.
00169                                         This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
00170
00171 #if defined(I2C2)
00172
00173   uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source.
00174                                         This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00175
00176 #endif /* I2C2 */
00177
00178   uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.
00179                                         This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
00180
00181   uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.
00182                                         This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
00183
00184   uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source.
00185                                         This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
00186
00187   uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source.
00188                                         This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
00189
00190 #if defined(SAI2)
00191
00192   uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 clock source.
00193                                         This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
00194
00195 #endif /* SAI2 */
00196
00197 #if defined(USB_OTG_FS) || defined(USB)
00198
00199   uint32_t UsbClockSelection;      /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
00200                                         This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00201
00202 #endif /* USB_OTG_FS || USB */
00203
00204 #if defined(SDMMC1)
00205
00206   uint32_t Sdmmc1ClockSelection;   /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
00207                                         This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
00208
00209 #endif /* SDMMC1 */
00210
00211   uint32_t RngClockSelection;      /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
00212                                         This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
00213
00214   uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source.
00215                                         This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
00216
00217 #if defined(SWPMI1)
00218
00219   uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 clock source.
00220                                         This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
00221
00222 #endif /* SWPMI1 */
00223
00224 #if defined(DFSDM1_Filter0)
00225
00226   uint32_t Dfsdm1ClockSelection;   /*!< Specifies DFSDM1 clock source.
00227                                         This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
00228
00229 #endif /* DFSDM1_Filter0 */
00230
00231   uint32_t RTCClockSelection;      /*!< Specifies RTC clock source.
00232                                         This parameter can be a value of @ref RCC_RTC_Clock_Source */
00233 }RCC_PeriphCLKInitTypeDef;
00234
00235 #if defined(CRS)
00236
00237 /**
00238   * @brief RCC_CRS Init structure definition
00239   */
00240 typedef struct
00241 {
00242   uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
00243                                      This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
00244
00245   uint32_t Source;                /*!< Specifies the SYNC signal source.
00246                                      This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
00247
00248   uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
00249                                      This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
00250
00251   uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
00252                                       It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
00253                                      This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
00254
00255   uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
00256                                      This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
00257
00258   uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
00259                                      This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
00260
00261 }RCC_CRSInitTypeDef;
00262
00263 /**
00264   * @brief RCC_CRS Synchronization structure definition
00265   */
00266 typedef struct
00267 {
00268   uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
00269                                      This parameter must be a number between 0 and 0xFFFF */
00270
00271   uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
00272                                      This parameter must be a number between 0 and 0x3F */
00273
00274   uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
00275                                                                     value latched in the time of the last SYNC event.
00276                                     This parameter must be a number between 0 and 0xFFFF */
00277
00278   uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
00279                                                                     frequency error counter latched in the time of the last SYNC event.
00280                                                                     It shows whether the actual frequency is below or above the target.
00281                                     This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
00282
00283 }RCC_CRSSynchroInfoTypeDef;
00284
00285 #endif /* CRS */
00286 /**
00287   * @}
00288   */
00289
00290 /* Exported constants --------------------------------------------------------*/
00291 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
00292   * @{
00293   */
00294
00295 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
00296   * @{
00297   */
00298 #define RCC_LSCOSOURCE_LSI             (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */
00299 #define RCC_LSCOSOURCE_LSE             RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock output */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
00305   * @{
00306   */
00307 #define RCC_PERIPHCLK_USART1           ((uint32_t)0x00000001U)
00308 #define RCC_PERIPHCLK_USART2           ((uint32_t)0x00000002U)
00309 #if defined(USART3)
00310 #define RCC_PERIPHCLK_USART3           ((uint32_t)0x00000004U)
00311 #endif
00312 #if defined(UART4)
00313 #define RCC_PERIPHCLK_UART4            ((uint32_t)0x00000008U)
00314 #endif
00315 #if defined(UART5)
00316 #define RCC_PERIPHCLK_UART5            ((uint32_t)0x00000010U)
00317 #endif
00318 #define RCC_PERIPHCLK_LPUART1          ((uint32_t)0x00000020U)
00319 #define RCC_PERIPHCLK_I2C1             ((uint32_t)0x00000040U)
00320 #if defined(I2C2)
00321 #define RCC_PERIPHCLK_I2C2             ((uint32_t)0x00000080U)
00322 #endif
00323 #define RCC_PERIPHCLK_I2C3             ((uint32_t)0x00000100U)
00324 #define RCC_PERIPHCLK_LPTIM1           ((uint32_t)0x00000200U)
00325 #define RCC_PERIPHCLK_LPTIM2           ((uint32_t)0x00000400U)
00326 #define RCC_PERIPHCLK_SAI1             ((uint32_t)0x00000800U)
00327 #if defined(SAI2)
00328 #define RCC_PERIPHCLK_SAI2             ((uint32_t)0x00001000U)
00329 #endif
00330 #if defined(USB_OTG_FS) || defined(USB)
00331 #define RCC_PERIPHCLK_USB              ((uint32_t)0x00002000U)
00332 #endif
00333 #define RCC_PERIPHCLK_ADC              ((uint32_t)0x00004000U)
00334 #define RCC_PERIPHCLK_SWPMI1           ((uint32_t)0x00008000U)
00335 #if defined(DFSDM1_Filter0)
00336 #define RCC_PERIPHCLK_DFSDM1           ((uint32_t)0x00010000U)
00337 #endif
00338 #define RCC_PERIPHCLK_RTC              ((uint32_t)0x00020000U)
00339 #define RCC_PERIPHCLK_RNG              ((uint32_t)0x00040000U)
00340 #if defined(SDMMC1)
00341 #define RCC_PERIPHCLK_SDMMC1           ((uint32_t)0x00080000U)
00342 #endif
00343 /**
00344   * @}
00345   */
00346
00347
00348 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
00349   * @{
00350   */
00351 #define RCC_USART1CLKSOURCE_PCLK2      ((uint32_t)0x00000000U)
00352 #define RCC_USART1CLKSOURCE_SYSCLK     RCC_CCIPR_USART1SEL_0
00353 #define RCC_USART1CLKSOURCE_HSI        RCC_CCIPR_USART1SEL_1
00354 #define RCC_USART1CLKSOURCE_LSE        (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
00360   * @{
00361   */
00362 #define RCC_USART2CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
00363 #define RCC_USART2CLKSOURCE_SYSCLK     RCC_CCIPR_USART2SEL_0
00364 #define RCC_USART2CLKSOURCE_HSI        RCC_CCIPR_USART2SEL_1
00365 #define RCC_USART2CLKSOURCE_LSE        (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
00366 /**
00367   * @}
00368   */
00369
00370 #if defined(USART3)
00371 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
00372   * @{
00373   */
00374 #define RCC_USART3CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
00375 #define RCC_USART3CLKSOURCE_SYSCLK     RCC_CCIPR_USART3SEL_0
00376 #define RCC_USART3CLKSOURCE_HSI        RCC_CCIPR_USART3SEL_1
00377 #define RCC_USART3CLKSOURCE_LSE        (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
00378 /**
00379   * @}
00380   */
00381 #endif /* USART3 */
00382
00383 #if defined(UART4)
00384 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
00385   * @{
00386   */
00387 #define RCC_UART4CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
00388 #define RCC_UART4CLKSOURCE_SYSCLK      RCC_CCIPR_UART4SEL_0
00389 #define RCC_UART4CLKSOURCE_HSI         RCC_CCIPR_UART4SEL_1
00390 #define RCC_UART4CLKSOURCE_LSE         (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
00391 /**
00392   * @}
00393   */
00394 #endif /* UART4 */
00395
00396 #if defined(UART5)
00397 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
00398   * @{
00399   */
00400 #define RCC_UART5CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
00401 #define RCC_UART5CLKSOURCE_SYSCLK      RCC_CCIPR_UART5SEL_0
00402 #define RCC_UART5CLKSOURCE_HSI         RCC_CCIPR_UART5SEL_1
00403 #define RCC_UART5CLKSOURCE_LSE         (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
00404 /**
00405   * @}
00406   */
00407 #endif /* UART5 */
00408
00409 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
00410   * @{
00411   */
00412 #define RCC_LPUART1CLKSOURCE_PCLK1     ((uint32_t)0x00000000U)
00413 #define RCC_LPUART1CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0
00414 #define RCC_LPUART1CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1
00415 #define RCC_LPUART1CLKSOURCE_LSE       (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
00421   * @{
00422   */
00423 #define RCC_I2C1CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
00424 #define RCC_I2C1CLKSOURCE_SYSCLK       RCC_CCIPR_I2C1SEL_0
00425 #define RCC_I2C1CLKSOURCE_HSI          RCC_CCIPR_I2C1SEL_1
00426 /**
00427   * @}
00428   */
00429
00430 #if defined(I2C2)
00431 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
00432   * @{
00433   */
00434 #define RCC_I2C2CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
00435 #define RCC_I2C2CLKSOURCE_SYSCLK       RCC_CCIPR_I2C2SEL_0
00436 #define RCC_I2C2CLKSOURCE_HSI          RCC_CCIPR_I2C2SEL_1
00437 /**
00438   * @}
00439   */
00440 #endif /* I2C2 */
00441
00442 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
00443   * @{
00444   */
00445 #define RCC_I2C3CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
00446 #define RCC_I2C3CLKSOURCE_SYSCLK       RCC_CCIPR_I2C3SEL_0
00447 #define RCC_I2C3CLKSOURCE_HSI          RCC_CCIPR_I2C3SEL_1
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
00453   * @{
00454   */
00455 #define RCC_SAI1CLKSOURCE_PLLSAI1      ((uint32_t)0x00000000U)
00456 #if defined(RCC_PLLSAI2_SUPPORT)
00457 #define RCC_SAI1CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI1SEL_0
00458 #endif /* RCC_PLLSAI2_SUPPORT */
00459 #define RCC_SAI1CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_1
00460 #define RCC_SAI1CLKSOURCE_PIN          RCC_CCIPR_SAI1SEL
00461 /**
00462   * @}
00463   */
00464
00465 #if defined(SAI2)
00466 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
00467   * @{
00468   */
00469 #define RCC_SAI2CLKSOURCE_PLLSAI1      ((uint32_t)0x00000000U)
00470 #define RCC_SAI2CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI2SEL_0
00471 #define RCC_SAI2CLKSOURCE_PLL          RCC_CCIPR_SAI2SEL_1
00472 #define RCC_SAI2CLKSOURCE_PIN          RCC_CCIPR_SAI2SEL
00473 /**
00474   * @}
00475   */
00476 #endif /* SAI2 */
00477
00478 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
00479   * @{
00480   */
00481 #define RCC_LPTIM1CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
00482 #define RCC_LPTIM1CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0
00483 #define RCC_LPTIM1CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1
00484 #define RCC_LPTIM1CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
00490   * @{
00491   */
00492 #define RCC_LPTIM2CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
00493 #define RCC_LPTIM2CLKSOURCE_LSI        RCC_CCIPR_LPTIM2SEL_0
00494 #define RCC_LPTIM2CLKSOURCE_HSI        RCC_CCIPR_LPTIM2SEL_1
00495 #define RCC_LPTIM2CLKSOURCE_LSE        RCC_CCIPR_LPTIM2SEL
00496 /**
00497   * @}
00498   */
00499
00500 #if defined(SDMMC1)
00501 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
00502   * @{
00503   */
00504 #if defined(RCC_HSI48_SUPPORT)
00505 #define RCC_SDMMC1CLKSOURCE_HSI48      ((uint32_t)0x00000000U)
00506 #else
00507 #define RCC_SDMMC1CLKSOURCE_NONE       ((uint32_t)0x00000000U)
00508 #endif /* RCC_HSI48_SUPPORT */
00509 #define RCC_SDMMC1CLKSOURCE_PLLSAI1    RCC_CCIPR_CLK48SEL_0
00510 #define RCC_SDMMC1CLKSOURCE_PLL        RCC_CCIPR_CLK48SEL_1
00511 #define RCC_SDMMC1CLKSOURCE_MSI        RCC_CCIPR_CLK48SEL
00512 /**
00513   * @}
00514   */
00515 #endif /* SDMMC1 */
00516
00517 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
00518   * @{
00519   */
00520 #if defined(RCC_HSI48_SUPPORT)
00521 #define RCC_RNGCLKSOURCE_HSI48         ((uint32_t)0x00000000U)
00522 #else
00523 #define RCC_RNGCLKSOURCE_NONE          ((uint32_t)0x00000000U)
00524 #endif /* RCC_HSI48_SUPPORT */
00525 #define RCC_RNGCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0
00526 #define RCC_RNGCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
00527 #define RCC_RNGCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL
00528 /**
00529   * @}
00530   */
00531
00532 #if defined(USB_OTG_FS) || defined(USB)
00533 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
00534   * @{
00535   */
00536 #if defined(RCC_HSI48_SUPPORT)
00537 #define RCC_USBCLKSOURCE_HSI48         ((uint32_t)0x00000000U)
00538 #else
00539 #define RCC_USBCLKSOURCE_NONE          ((uint32_t)0x00000000U)
00540 #endif /* RCC_HSI48_SUPPORT */
00541 #define RCC_USBCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0
00542 #define RCC_USBCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
00543 #define RCC_USBCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL
00544 /**
00545   * @}
00546   */
00547 #endif /* USB_OTG_FS || USB */
00548
00549 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
00550   * @{
00551   */
00552 #define RCC_ADCCLKSOURCE_NONE        ((uint32_t)0x00000000U)
00553 #define RCC_ADCCLKSOURCE_PLLSAI1      RCC_CCIPR_ADCSEL_0
00554 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00555 #define RCC_ADCCLKSOURCE_PLLSAI2      RCC_CCIPR_ADCSEL_1
00556 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00557 #define RCC_ADCCLKSOURCE_SYSCLK       RCC_CCIPR_ADCSEL
00558 /**
00559   * @}
00560   */
00561
00562 #if defined(SWPMI1)
00563 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
00564   * @{
00565   */
00566 #define RCC_SWPMI1CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
00567 #define RCC_SWPMI1CLKSOURCE_HSI        RCC_CCIPR_SWPMI1SEL
00568 /**
00569   * @}
00570   */
00571 #endif /* SWPMI1 */
00572
00573 #if defined(DFSDM1_Filter0)
00574 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
00575   * @{
00576   */
00577 #define RCC_DFSDM1CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
00578 #define RCC_DFSDM1CLKSOURCE_SYSCLK     RCC_CCIPR_DFSDM1SEL
00579 /**
00580   * @}
00581   */
00582 #endif /* DFSDM1_Filter0 */
00583
00584 /** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
00585   * @{
00586   */
00587 #define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM19        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
00588 /**
00589   * @}
00590   */
00591
00592 #if defined(CRS)
00593
00594 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
00595   * @{
00596   */
00597 #define RCC_CRS_NONE                   ((uint32_t)0x00000000U)
00598 #define RCC_CRS_TIMEOUT                ((uint32_t)0x00000001U)
00599 #define RCC_CRS_SYNCOK                 ((uint32_t)0x00000002U)
00600 #define RCC_CRS_SYNCWARN               ((uint32_t)0x00000004U)
00601 #define RCC_CRS_SYNCERR                ((uint32_t)0x00000008U)
00602 #define RCC_CRS_SYNCMISS               ((uint32_t)0x00000010U)
00603 #define RCC_CRS_TRIMOVF                ((uint32_t)0x00000020U)
00604 /**
00605   * @}
00606   */
00607
00608 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
00609   * @{
00610   */
00611 #define RCC_CRS_SYNC_SOURCE_GPIO       ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
00612 #define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
00613 #define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
00614 /**
00615   * @}
00616   */
00617
00618 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
00619   * @{
00620   */
00621 #define RCC_CRS_SYNC_DIV1        ((uint32_t)0x00000000U)                   /*!< Synchro Signal not divided (default) */
00622 #define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
00623 #define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
00624 #define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
00625 #define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
00626 #define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
00627 #define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
00628 #define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
00634   * @{
00635   */
00636 #define RCC_CRS_SYNC_POLARITY_RISING   ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
00637 #define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
00638 /**
00639   * @}
00640   */
00641
00642 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
00643   * @{
00644   */
00645 #define RCC_CRS_RELOADVALUE_DEFAULT    ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
00646                                                                     to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
00647 /**
00648   * @}
00649   */
00650
00651 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
00652   * @{
00653   */
00654 #define RCC_CRS_ERRORLIMIT_DEFAULT     ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
00655 /**
00656   * @}
00657   */
00658
00659 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
00660   * @{
00661   */
00662 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
00663                                                                       The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
00664                                                                       corresponds to a higher output frequency */
00665 /**
00666   * @}
00667   */
00668
00669 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
00670   * @{
00671   */
00672 #define RCC_CRS_FREQERRORDIR_UP        ((uint32_t)0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
00673 #define RCC_CRS_FREQERRORDIR_DOWN      ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
00674 /**
00675   * @}
00676   */
00677
00678 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
00679   * @{
00680   */
00681 #define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
00682 #define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
00683 #define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
00684 #define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
00685 #define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
00686 #define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
00687 #define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE           /*!< Trimming overflow or underflow */
00688
00689 /**
00690   * @}
00691   */
00692
00693 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
00694   * @{
00695   */
00696 #define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
00697 #define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
00698 #define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
00699 #define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
00700 #define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
00701 #define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
00702 #define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
00703
00704 /**
00705   * @}
00706   */
00707
00708 #endif /* CRS */
00709
00710 /**
00711   * @}
00712   */
00713
00714 /* Exported macros -----------------------------------------------------------*/
00715 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
00716  * @{
00717  */
00718
00719
00720 /**
00721   * @brief  Macro to configure the PLLSAI1 clock multiplication and division factors.
00722   *
00723   * @note   This function must be used only when the PLLSAI1 is disabled.
00724   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00725   *         __HAL_RCC_PLL_CONFIG() macro)
00726   *
00727   * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
00728   *         This parameter must be a number between 8 and 86.
00729   * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO
00730   *         output frequency is between 64 and 344 MHz.
00731   *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
00732   *
00733   * @param  __PLLSAI1P__ specifies the division factor for SAI clock.
00734   *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
00735   *         else (2 to 31).
00736   *         SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
00737   *
00738   * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
00739   *         This parameter must be in the range (2, 4, 6 or 8).
00740   *         USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
00741   *
00742   * @param  __PLLSAI1R__ specifies the division factor for SAR ADC clock.
00743   *         This parameter must be in the range (2, 4, 6 or 8).
00744   *         ADC clock frequency = f(PLLSAI1) / PLLSAI1R
00745   *
00746   * @retval None
00747   */
00748 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
00749
00750 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
00751                   WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
00752                    ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
00753                    ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \
00754                    ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)))
00755
00756 #else
00757
00758 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
00759                   WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
00760                    (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
00761                    ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
00762                    ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
00763
00764 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
00765
00766 /**
00767   * @brief  Macro to configure the PLLSAI1 clock multiplication factor N.
00768   *
00769   * @note   This function must be used only when the PLLSAI1 is disabled.
00770   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00771   *         __HAL_RCC_PLL_CONFIG() macro)
00772   *
00773   * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
00774   *          This parameter must be a number between 8 and 86.
00775   * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO
00776   *         output frequency is between 64 and 344 MHz.
00777   *         Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
00778   *
00779   * @retval None
00780   */
00781 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
00782                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
00783
00784 /** @brief  Macro to configure the PLLSAI1 clock division factor P.
00785   *
00786   * @note   This function must be used only when the PLLSAI1 is disabled.
00787   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00788   *         __HAL_RCC_PLL_CONFIG() macro)
00789   *
00790   * @param  __PLLSAI1P__ specifies the division factor for SAI clock.
00791   *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
00792   *         else (2 to 31).
00793   *         Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
00794   *
00795   * @retval None
00796   */
00797 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
00798
00799 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
00800                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))
00801
00802 #else
00803
00804 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
00805                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
00806
00807 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
00808
00809 /** @brief  Macro to configure the PLLSAI1 clock division factor Q.
00810   *
00811   * @note   This function must be used only when the PLLSAI1 is disabled.
00812   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00813   *         __HAL_RCC_PLL_CONFIG() macro)
00814   *
00815   * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
00816   *         This parameter must be in the range (2, 4, 6 or 8).
00817   *         Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
00818   *
00819   * @retval None
00820   */
00821 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
00822                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
00823
00824 /** @brief  Macro to configure the PLLSAI1 clock division factor R.
00825   *
00826   * @note   This function must be used only when the PLLSAI1 is disabled.
00827   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00828   *         __HAL_RCC_PLL_CONFIG() macro)
00829   *
00830   * @param  __PLLSAI1R__ specifies the division factor for ADC clock.
00831   *         This parameter must be in the range (2, 4, 6 or 8)
00832   *         Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
00833   *
00834   * @retval None
00835   */
00836 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
00837                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
00838
00839 /**
00840   * @brief  Macros to enable or disable the PLLSAI1.
00841   * @note   The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
00842   * @retval None
00843   */
00844
00845 #define __HAL_RCC_PLLSAI1_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
00846
00847 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
00848
00849 /**
00850   * @brief  Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
00851   * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.
00852   *         This is mainly used to save Power.
00853   * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
00854   *         This parameter can be one or a combination of the following values:
00855   *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve
00856   *                                   high-quality audio performance on SAI interface in case.
00857   *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),
00858   *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
00859   *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.
00860   * @retval None
00861   */
00862
00863 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__)   SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
00864
00865 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__)  CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
00866
00867 /**
00868   * @brief  Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
00869   * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
00870   *         This parameter can be one of the following values:
00871   *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve
00872   *                                   high-quality audio performance on SAI interface in case.
00873   *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),
00874   *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
00875   *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.
00876   * @retval SET / RESET
00877   */
00878 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__)  READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
00879
00880 #if defined(RCC_PLLSAI2_SUPPORT)
00881
00882 /**
00883   * @brief  Macro to configure the PLLSAI2 clock multiplication and division factors.
00884   *
00885   * @note   This function must be used only when the PLLSAI2 is disabled.
00886   * @note   PLLSAI2 clock source is common with the main PLL (configured through
00887   *         __HAL_RCC_PLL_CONFIG() macro)
00888   *
00889   * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
00890   *          This parameter must be a number between 8 and 86.
00891   * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO
00892   *         output frequency is between 64 and 344 MHz.
00893   *
00894   * @param  __PLLSAI2P__ specifies the division factor for SAI clock.
00895   *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
00896   *         else (2 to 31).
00897   *         SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
00898   *
00899   * @param  __PLLSAI2R__ specifies the division factor for SAR ADC clock.
00900   *         This parameter must be in the range (2, 4, 6 or 8).
00901   *
00902   * @retval None
00903   */
00904
00905 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
00906
00907 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
00908                   WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
00909                    ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \
00910                    ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)))
00911
00912 #else
00913
00914 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
00915                   WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
00916                     (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
00917                     ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
00918
00919 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
00920
00921
00922 /**
00923   * @brief  Macro to configure the PLLSAI2 clock multiplication factor N.
00924   *
00925   * @note   This function must be used only when the PLLSAI2 is disabled.
00926   * @note   PLLSAI2 clock source is common with the main PLL (configured through
00927   *         __HAL_RCC_PLL_CONFIG() macro)
00928   *
00929   * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
00930   *          This parameter must be a number between 8 and 86.
00931   * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO
00932   *         output frequency is between 64 and 344 MHz.
00933   *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
00934   *
00935   * @retval None
00936   */
00937 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
00938                   MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
00939
00940 /** @brief  Macro to configure the PLLSAI2 clock division factor P.
00941   *
00942   * @note   This function must be used only when the PLLSAI2 is disabled.
00943   * @note   PLLSAI2 clock source is common with the main PLL (configured through
00944   *         __HAL_RCC_PLL_CONFIG() macro)
00945   *
00946   * @param  __PLLSAI2P__ specifies the division factor.
00947   *         This parameter must be a number in the range (7 or 17).
00948   *         Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
00949   *
00950   * @retval None
00951   */
00952 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
00953                   MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
00954
00955 /** @brief  Macro to configure the PLLSAI2 clock division factor R.
00956   *
00957   * @note   This function must be used only when the PLLSAI2 is disabled.
00958   * @note   PLLSAI2 clock source is common with the main PLL (configured through
00959   *         __HAL_RCC_PLL_CONFIG() macro)
00960   *
00961   * @param  __PLLSAI2R__ specifies the division factor.
00962   *         This parameter must be in the range (2, 4, 6 or 8).
00963   *         Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
00964   *
00965   * @retval None
00966   */
00967 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
00968                   MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
00969
00970 /**
00971   * @brief  Macros to enable or disable the PLLSAI2.
00972   * @note   The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
00973   * @retval None
00974   */
00975
00976 #define __HAL_RCC_PLLSAI2_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
00977
00978 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
00979
00980 /**
00981   * @brief  Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
00982   * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.
00983   *         This is mainly used to save Power.
00984   * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
00985   *         This parameter can be one or a combination of the following values:
00986   *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve
00987   *                                   high-quality audio performance on SAI interface in case.
00988   *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.
00989   * @retval None
00990   */
00991
00992 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__)  SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
00993
00994 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
00995
00996 /**
00997   * @brief  Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
00998   * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
00999   *          This parameter can be one of the following values:
01000   *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve
01001   *                                   high-quality audio performance on SAI interface in case.
01002   *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.
01003   * @retval SET / RESET
01004   */
01005 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__)  READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
01006
01007 #endif /* RCC_PLLSAI2_SUPPORT */
01008
01009 /**
01010   * @brief  Macro to configure the SAI1 clock source.
01011   * @param  __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
01012   *         from the PLLSAI1, system PLL or external clock (through a dedicated pin).
01013   *          This parameter can be one of the following values:
01014   *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
01015   @if STM32L486xx
01016   *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
01017   @endif
01018   *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
01019   *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)
01020   *
01021   @if STM32L443xx
01022   * @note  HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
01023   @endif
01024   *
01025   * @retval None
01026   */
01027 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
01028                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
01029
01030 /** @brief  Macro to get the SAI1 clock source.
01031   * @retval The clock source can be one of the following values:
01032   *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
01033   @if STM32L486xx
01034   *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
01035   @endif
01036   *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
01037   *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)
01038   *
01039   * @note  Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
01040   *        clock source when PLLs are disabled for devices without PLLSAI2.
01041   *
01042   */
01043 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
01044
01045 #if defined(SAI2)
01046
01047 /**
01048   * @brief  Macro to configure the SAI2 clock source.
01049   * @param  __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
01050   *         from the PLLSAI2, system PLL or external clock (through a dedicated pin).
01051   *          This parameter can be one of the following values:
01052   *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
01053   *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
01054   *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)
01055   *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)
01056   *
01057   * @retval None
01058   */
01059 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
01060                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
01061
01062 /** @brief  Macro to get the SAI2 clock source.
01063   * @retval The clock source can be one of the following values:
01064   *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
01065   *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
01066   *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)
01067   *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)
01068   */
01069 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
01070
01071 #endif /* SAI2 */
01072
01073 /** @brief  Macro to configure the I2C1 clock (I2C1CLK).
01074   *
01075   * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
01076   *          This parameter can be one of the following values:
01077   *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
01078   *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
01079   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
01080   * @retval None
01081   */
01082 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
01083                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
01084
01085 /** @brief  Macro to get the I2C1 clock source.
01086   * @retval The clock source can be one of the following values:
01087   *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
01088   *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
01089   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
01090   */
01091 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
01092
01093 #if defined(I2C2)
01094
01095 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
01096   *
01097   * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
01098   *          This parameter can be one of the following values:
01099   *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
01100   *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
01101   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
01102   * @retval None
01103   */
01104 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
01105                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
01106
01107 /** @brief  Macro to get the I2C2 clock source.
01108   * @retval The clock source can be one of the following values:
01109   *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
01110   *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
01111   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
01112   */
01113 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
01114
01115 #endif /* I2C2 */
01116
01117 /** @brief  Macro to configure the I2C3 clock (I2C3CLK).
01118   *
01119   * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
01120   *          This parameter can be one of the following values:
01121   *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
01122   *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
01123   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
01124   * @retval None
01125   */
01126 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
01127                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
01128
01129 /** @brief  Macro to get the I2C3 clock source.
01130   * @retval The clock source can be one of the following values:
01131   *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
01132   *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
01133   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
01134   */
01135 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
01136
01137 /** @brief  Macro to configure the USART1 clock (USART1CLK).
01138   *
01139   * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
01140   *          This parameter can be one of the following values:
01141   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
01142   *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
01143   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
01144   *            @arg @ref RCC_USART1CLKSOURCE_LSE  SE selected as USART1 clock
01145   * @retval None
01146   */
01147 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
01148                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
01149
01150 /** @brief  Macro to get the USART1 clock source.
01151   * @retval The clock source can be one of the following values:
01152   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
01153   *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
01154   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
01155   *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock
01156   */
01157 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
01158
01159 /** @brief  Macro to configure the USART2 clock (USART2CLK).
01160   *
01161   * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
01162   *          This parameter can be one of the following values:
01163   *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
01164   *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
01165   *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
01166   *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
01167   * @retval None
01168   */
01169 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
01170                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
01171
01172 /** @brief  Macro to get the USART2 clock source.
01173   * @retval The clock source can be one of the following values:
01174   *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
01175   *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
01176   *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
01177   *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
01178   */
01179 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
01180
01181 #if defined(USART3)
01182
01183 /** @brief  Macro to configure the USART3 clock (USART3CLK).
01184   *
01185   * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.
01186   *          This parameter can be one of the following values:
01187   *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
01188   *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
01189   *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
01190   *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
01191   * @retval None
01192   */
01193 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
01194                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
01195
01196 /** @brief  Macro to get the USART3 clock source.
01197   * @retval The clock source can be one of the following values:
01198   *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
01199   *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
01200   *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
01201   *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
01202   */
01203 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
01204
01205 #endif /* USART3 */
01206
01207 #if defined(UART4)
01208
01209 /** @brief  Macro to configure the UART4 clock (UART4CLK).
01210   *
01211   * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.
01212   *          This parameter can be one of the following values:
01213   *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
01214   *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
01215   *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
01216   *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
01217   * @retval None
01218   */
01219 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
01220                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
01221
01222 /** @brief  Macro to get the UART4 clock source.
01223   * @retval The clock source can be one of the following values:
01224   *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
01225   *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
01226   *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
01227   *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
01228   */
01229 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
01230
01231 #endif /* UART4 */
01232
01233 #if defined(UART5)
01234
01235 /** @brief  Macro to configure the UART5 clock (UART5CLK).
01236   *
01237   * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.
01238   *          This parameter can be one of the following values:
01239   *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
01240   *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
01241   *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
01242   *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
01243   * @retval None
01244   */
01245 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
01246                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
01247
01248 /** @brief  Macro to get the UART5 clock source.
01249   * @retval The clock source can be one of the following values:
01250   *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
01251   *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
01252   *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
01253   *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
01254   */
01255 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
01256
01257 #endif /* UART5 */
01258
01259 /** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).
01260   *
01261   * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
01262   *          This parameter can be one of the following values:
01263   *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
01264   *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
01265   *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
01266   *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
01267   * @retval None
01268   */
01269 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
01270                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
01271
01272 /** @brief  Macro to get the LPUART1 clock source.
01273   * @retval The clock source can be one of the following values:
01274   *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
01275   *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
01276   *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
01277   *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
01278   */
01279 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
01280
01281 /** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
01282   *
01283   * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
01284   *          This parameter can be one of the following values:
01285   *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK  PCLK selected as LPTIM1 clock
01286   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPTIM1 clock
01287   *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  LSI selected as LPTIM1 clock
01288   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPTIM1 clock
01289   * @retval None
01290   */
01291 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
01292                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
01293
01294 /** @brief  Macro to get the LPTIM1 clock source.
01295   * @retval The clock source can be one of the following values:
01296   *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK  PCLK selected as LPUART1 clock
01297   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPUART1 clock
01298   *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  System Clock selected as LPUART1 clock
01299   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPUART1 clock
01300   */
01301 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
01302
01303 /** @brief  Macro to configure the LPTIM2 clock (LPTIM2CLK).
01304   *
01305   * @param  __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
01306   *          This parameter can be one of the following values:
01307   *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK  PCLK selected as LPTIM2 clock
01308   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPTIM2 clock
01309   *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  LSI selected as LPTIM2 clock
01310   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPTIM2 clock
01311   * @retval None
01312   */
01313 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
01314                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
01315
01316 /** @brief  Macro to get the LPTIM2 clock source.
01317   * @retval The clock source can be one of the following values:
01318   *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK  PCLK selected as LPUART1 clock
01319   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPUART1 clock
01320   *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  System Clock selected as LPUART1 clock
01321   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPUART1 clock
01322   */
01323 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
01324
01325 #if defined(SDMMC1)
01326
01327 /** @brief  Macro to configure the SDMMC1 clock.
01328   *
01329   @if STM32L486xx
01330   * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
01331   @endif
01332   *
01333   @if STM32L443xx
01334   * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
01335   @endif
01336   *
01337   * @param  __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
01338   *         This parameter can be one of the following values:
01339   @if STM32L486xx
01340   *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock for devices without HSI48
01341   *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
01342   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as SDMMC1 clock
01343   @endif
01344   @if STM32L443xx
01345   *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48
01346   *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
01347   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as SDMMC1 clock
01348   @endif
01349   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL Clock selected as SDMMC1 clock
01350   * @retval None
01351   */
01352 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
01353                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
01354
01355 /** @brief  Macro to get the SDMMC1 clock.
01356   * @retval The clock source can be one of the following values:
01357   @if STM32L486xx
01358   *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock for devices without HSI48
01359   *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
01360   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
01361   @endif
01362   @if STM32L443xx
01363   *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48
01364   *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
01365   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
01366   @endif
01367   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
01368   */
01369 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
01370
01371 #endif /* SDMMC1 */
01372
01373 /** @brief  Macro to configure the RNG clock.
01374   *
01375   * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
01376   *
01377   * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.
01378   *         This parameter can be one of the following values:
01379   @if STM32L486xx
01380   *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock for devices without HSI48
01381   @endif
01382   @if STM32L443xx
01383   *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48
01384   @endif
01385   *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock
01386   *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as RNG clock
01387   *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL Clock selected as RNG clock
01388   * @retval None
01389   */
01390 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
01391                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
01392
01393 /** @brief  Macro to get the RNG clock.
01394   * @retval The clock source can be one of the following values:
01395   @if STM32L486xx
01396   *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock for devices without HSI48
01397   @endif
01398   @if STM32L443xx
01399   *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48
01400   @endif
01401   *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock
01402   *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
01403   *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as RNG clock
01404   */
01405 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
01406
01407 #if defined(USB_OTG_FS) || defined(USB)
01408
01409 /** @brief  Macro to configure the USB clock (USBCLK).
01410   *
01411   * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
01412   *
01413   * @param  __USB_CLKSOURCE__ specifies the USB clock source.
01414   *         This parameter can be one of the following values:
01415   @if STM32L486xx
01416   *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock for devices without HSI48
01417   @endif
01418   @if STM32L443xx
01419   *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
01420   @endif
01421   *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock
01422   *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
01423   *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
01424   * @retval None
01425   */
01426 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
01427                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
01428
01429 /** @brief  Macro to get the USB clock source.
01430   * @retval The clock source can be one of the following values:
01431   @if STM32L486xx
01432   *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock for devices without HSI48
01433   @endif
01434   @if STM32L443xx
01435   *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
01436   @endif
01437   *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock
01438   *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
01439   *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
01440   */
01441 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
01442
01443 #endif /* USB_OTG_FS || USB */
01444
01445 /** @brief  Macro to configure the ADC interface clock.
01446   * @param  __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
01447   *         This parameter can be one of the following values:
01448   *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock
01449   *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock
01450   @if STM32L486xx
01451   *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
01452   @endif
01453   *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
01454   * @retval None
01455   */
01456 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
01457                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
01458
01459 /** @brief  Macro to get the ADC clock source.
01460   * @retval The clock source can be one of the following values:
01461   *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock
01462   *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock
01463   @if STM32L486xx
01464   *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
01465   @endif
01466   *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
01467   */
01468 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
01469
01470 #if defined(SWPMI1)
01471
01472 /** @brief  Macro to configure the SWPMI1 clock.
01473   * @param  __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
01474   *         This parameter can be one of the following values:
01475   *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK  PCLK Clock selected as SWPMI1 clock
01476   *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock
01477   * @retval None
01478   */
01479 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
01480                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
01481
01482 /** @brief  Macro to get the SWPMI1 clock source.
01483   * @retval The clock source can be one of the following values:
01484   *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK  PCLK Clock selected as SWPMI1 clock
01485   *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock
01486   */
01487 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
01488
01489 #endif /* SWPMI1 */
01490
01491 #if defined(DFSDM1_Filter0)
01492 /** @brief  Macro to configure the DFSDM1 clock.
01493   * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
01494   *         This parameter can be one of the following values:
01495   *            @arg @ref RCC_DFSDM1CLKSOURCE_PCLK  PCLK Clock selected as DFSDM1 clock
01496   *            @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK  System Clock selected as DFSDM1 clock
01497   * @retval None
01498   */
01499 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
01500                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
01501
01502 /** @brief  Macro to get the DFSDM1 clock source.
01503   * @retval The clock source can be one of the following values:
01504   *            @arg @ref RCC_DFSDM1CLKSOURCE_PCLK  PCLK Clock selected as DFSDM1 clock
01505   *            @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK  System Clock selected as DFSDM1 clock
01506   */
01507 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))
01508
01509 #endif /* DFSDM1_Filter0 */
01510
01511
01512 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
01513   * @brief macros to manage the specified RCC Flags and interrupts.
01514   * @{
01515   */
01516
01517 /** @brief Enable PLLSAI1RDY interrupt.
01518   * @retval None
01519   */
01520 #define __HAL_RCC_PLLSAI1_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
01521
01522 /** @brief Disable PLLSAI1RDY interrupt.
01523   * @retval None
01524   */
01525 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
01526
01527 /** @brief Clear the PLLSAI1RDY interrupt pending bit.
01528   * @retval None
01529   */
01530 #define __HAL_RCC_PLLSAI1_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
01531
01532 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
01533   * @retval TRUE or FALSE.
01534   */
01535 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
01536
01537 /** @brief  Check whether the PLLSAI1RDY flag is set or not.
01538   * @retval TRUE or FALSE.
01539   */
01540 #define __HAL_RCC_PLLSAI1_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
01541
01542 #if defined(RCC_PLLSAI2_SUPPORT)
01543
01544 /** @brief Enable PLLSAI2RDY interrupt.
01545   * @retval None
01546   */
01547 #define __HAL_RCC_PLLSAI2_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
01548
01549 /** @brief Disable PLLSAI2RDY interrupt.
01550   * @retval None
01551   */
01552 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
01553
01554 /** @brief Clear the PLLSAI2RDY interrupt pending bit.
01555   * @retval None
01556   */
01557 #define __HAL_RCC_PLLSAI2_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
01558
01559 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
01560   * @retval TRUE or FALSE.
01561   */
01562 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
01563
01564 /** @brief  Check whether the PLLSAI2RDY flag is set or not.
01565   * @retval TRUE or FALSE.
01566   */
01567 #define __HAL_RCC_PLLSAI2_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
01568
01569 #endif /* RCC_PLLSAI2_SUPPORT */
01570
01571
01572 /**
01573   * @brief Enable the RCC LSE CSS Extended Interrupt Line.
01574   * @retval None
01575   */
01576 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
01577
01578 /**
01579   * @brief Disable the RCC LSE CSS Extended Interrupt Line.
01580   * @retval None
01581   */
01582 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
01583
01584 /**
01585   * @brief Enable the RCC LSE CSS Event Line.
01586   * @retval None.
01587   */
01588 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
01589
01590 /**
01591   * @brief Disable the RCC LSE CSS Event Line.
01592   * @retval None.
01593   */
01594 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
01595
01596
01597 /**
01598   * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
01599   * @retval None.
01600   */
01601 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
01602
01603
01604 /**
01605   * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
01606   * @retval None.
01607   */
01608 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
01609
01610
01611 /**
01612   * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
01613   * @retval None.
01614   */
01615 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
01616
01617 /**
01618   * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
01619   * @retval None.
01620   */
01621 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
01622
01623 /**
01624   * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
01625   * @retval None.
01626   */
01627 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
01628   do {                                                      \
01629     __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
01630     __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
01631   } while(0)
01632
01633 /**
01634   * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
01635   * @retval None.
01636   */
01637 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
01638   do {                                                       \
01639     __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
01640     __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
01641   } while(0)
01642
01643 /**
01644   * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
01645   * @retval EXTI RCC LSE CSS Line Status.
01646   */
01647 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
01648
01649 /**
01650   * @brief Clear the RCC LSE CSS EXTI flag.
01651   * @retval None.
01652   */
01653 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
01654
01655 /**
01656   * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
01657   * @retval None.
01658   */
01659 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
01660
01661
01662 #if defined(CRS)
01663
01664 /**
01665   * @brief  Enable the specified CRS interrupts.
01666   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
01667   *          This parameter can be any combination of the following values:
01668   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01669   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01670   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01671   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01672   * @retval None
01673   */
01674 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
01675
01676 /**
01677   * @brief  Disable the specified CRS interrupts.
01678   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
01679   *          This parameter can be any combination of the following values:
01680   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01681   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01682   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01683   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01684   * @retval None
01685   */
01686 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
01687
01688 /** @brief  Check whether the CRS interrupt has occurred or not.
01689   * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
01690   *         This parameter can be one of the following values:
01691   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01692   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01693   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01694   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01695   * @retval The new state of __INTERRUPT__ (SET or RESET).
01696   */
01697 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
01698
01699 /** @brief  Clear the CRS interrupt pending bits
01700   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01701   *         This parameter can be any combination of the following values:
01702   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01703   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01704   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01705   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01706   *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
01707   *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
01708   *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
01709   */
01710 /* CRS IT Error Mask */
01711 #define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
01712
01713 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
01714                                                  if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
01715                                                  { \
01716                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
01717                                                  } \
01718                                                  else \
01719                                                  { \
01720                                                    WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
01721                                                  } \
01722                                                } while(0)
01723
01724 /**
01725   * @brief  Check whether the specified CRS flag is set or not.
01726   * @param  __FLAG__ specifies the flag to check.
01727   *          This parameter can be one of the following values:
01728   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
01729   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
01730   *              @arg @ref RCC_CRS_FLAG_ERR  Error
01731   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
01732   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
01733   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
01734   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
01735   * @retval The new state of _FLAG_ (TRUE or FALSE).
01736   */
01737 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
01738
01739 /**
01740   * @brief  Clear the CRS specified FLAG.
01741   * @param __FLAG__ specifies the flag to clear.
01742   *          This parameter can be one of the following values:
01743   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
01744   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
01745   *              @arg @ref RCC_CRS_FLAG_ERR  Error
01746   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
01747   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
01748   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
01749   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
01750   * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
01751   * @retval None
01752   */
01753
01754 /* CRS Flag Error Mask */
01755 #define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
01756
01757 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
01758                                                  if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
01759                                                  { \
01760                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
01761                                                  } \
01762                                                  else \
01763                                                  { \
01764                                                    WRITE_REG(CRS->ICR, (__FLAG__)); \
01765                                                  } \
01766                                                } while(0)
01767
01768 #endif /* CRS */
01769
01770 /**
01771   * @}
01772   */
01773
01774 #if defined(CRS)
01775
01776 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
01777   * @{
01778   */
01779 /**
01780   * @brief  Enable the oscillator clock for frequency error counter.
01781   * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
01782   * @retval None
01783   */
01784 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
01785
01786 /**
01787   * @brief  Disable the oscillator clock for frequency error counter.
01788   * @retval None
01789   */
01790 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
01791
01792 /**
01793   * @brief  Enable the automatic hardware adjustement of TRIM bits.
01794   * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
01795   * @retval None
01796   */
01797 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
01798
01799 /**
01800   * @brief  Enable or disable the automatic hardware adjustement of TRIM bits.
01801   * @retval None
01802   */
01803 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
01804
01805 /**
01806   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
01807   * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
01808   *             of the synchronization source after prescaling. It is then decreased by one in order to
01809   *             reach the expected synchronization on the zero value. The formula is the following:
01810   *             RELOAD = (fTARGET / fSYNC) -1
01811   * @param  __FTARGET__ Target frequency (value in Hz)
01812   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
01813   * @retval None
01814   */
01815 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
01816
01817 /**
01818   * @}
01819   */
01820
01821 #endif /* CRS */
01822
01823 /**
01824   * @}
01825   */
01826
01827 /* Exported functions --------------------------------------------------------*/
01828 /** @addtogroup RCCEx_Exported_Functions
01829   * @{
01830   */
01831
01832 /** @addtogroup RCCEx_Exported_Functions_Group1
01833   * @{
01834   */
01835
01836 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01837 void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01838 uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
01839
01840 /**
01841   * @}
01842   */
01843
01844 /** @addtogroup RCCEx_Exported_Functions_Group2
01845   * @{
01846   */
01847
01848 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init);
01849 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
01850
01851 #if defined(RCC_PLLSAI2_SUPPORT)
01852
01853 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init);
01854 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
01855
01856 #endif /* RCC_PLLSAI2_SUPPORT */
01857
01858 void              HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
01859 void              HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
01860 void              HAL_RCCEx_EnableLSECSS(void);
01861 void              HAL_RCCEx_DisableLSECSS(void);
01862 void              HAL_RCCEx_EnableLSECSS_IT(void);
01863 void              HAL_RCCEx_LSECSS_IRQHandler(void);
01864 void              HAL_RCCEx_LSECSS_Callback(void);
01865 void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
01866 void              HAL_RCCEx_DisableLSCO(void);
01867 void              HAL_RCCEx_EnableMSIPLLMode(void);
01868 void              HAL_RCCEx_DisableMSIPLLMode(void);
01869
01870 /**
01871   * @}
01872   */
01873
01874 #if defined(CRS)
01875
01876 /** @addtogroup RCCEx_Exported_Functions_Group3
01877   * @{
01878   */
01879
01880 void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
01881 void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
01882 void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
01883 uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
01884 void              HAL_RCCEx_CRS_IRQHandler(void);
01885 void              HAL_RCCEx_CRS_SyncOkCallback(void);
01886 void              HAL_RCCEx_CRS_SyncWarnCallback(void);
01887 void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);
01888 void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
01889
01890 /**
01891   * @}
01892   */
01893
01894 #endif /* CRS */
01895
01896 /**
01897   * @}
01898   */
01899
01900 /* Private macros ------------------------------------------------------------*/
01901 /** @addtogroup RCCEx_Private_Macros
01902   * @{
01903   */
01904
01905 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
01906                                        ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
01907
01908 #if defined(STM32L431xx)
01909
01910 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01911                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01912                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01913                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01914                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01915                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01916                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01917                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
01918                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01919                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01920                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
01921                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01922                 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
01923                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01924                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
01925                 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
01926
01927 #elif defined(STM32L432xx) || defined(STM32L442xx)
01928
01929 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01930                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01931                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01932                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01933                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01934                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
01935                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01936                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01937                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
01938                 (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
01939                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01940                 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
01941                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01942                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG))
01943
01944 #elif defined(STM32L433xx) || defined(STM32L443xx)
01945
01946 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01947                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01948                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01949                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01950                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01951                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01952                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01953                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
01954                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01955                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01956                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
01957                 (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
01958                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01959                 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
01960                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01961                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
01962                 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
01963
01964 #elif defined(STM32L471xx)
01965
01966 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01967                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01968                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01969                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01970                 (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
01971                 (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \
01972                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01973                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01974                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01975                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
01976                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01977                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01978                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
01979                 (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \
01980                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01981                 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
01982                 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \
01983                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01984                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
01985                 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
01986
01987 #else
01988
01989 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01990                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01991                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01992                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01993                 (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
01994                 (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \
01995                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01996                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01997                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01998                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
01999                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
02000                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
02001                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
02002                 (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \
02003                 (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
02004                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
02005                 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
02006                 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \
02007                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
02008                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
02009                 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
02010
02011 #endif /* STM32L431xx */
02012
02013 #define IS_RCC_USART1CLKSOURCE(__SOURCE__)  \
02014                (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
02015                 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
02016                 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
02017                 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
02018
02019 #define IS_RCC_USART2CLKSOURCE(__SOURCE__)  \
02020                (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
02021                 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
02022                 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
02023                 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
02024
02025 #if defined(USART3)
02026
02027 #define IS_RCC_USART3CLKSOURCE(__SOURCE__)  \
02028                (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
02029                 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
02030                 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
02031                 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
02032
02033 #endif /* USART3 */
02034
02035 #if defined(UART4)
02036
02037 #define IS_RCC_UART4CLKSOURCE(__SOURCE__)  \
02038                (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1)  || \
02039                 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
02040                 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)    || \
02041                 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
02042
02043 #endif /* UART4 */
02044
02045 #if defined(UART5)
02046
02047 #define IS_RCC_UART5CLKSOURCE(__SOURCE__)  \
02048                (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1)  || \
02049                 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
02050                 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)    || \
02051                 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
02052
02053 #endif /* UART5 */
02054
02055 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  \
02056                (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
02057                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
02058                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
02059                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
02060
02061 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__)   \
02062                (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
02063                 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
02064                 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
02065
02066 #if defined(I2C2)
02067
02068 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__)   \
02069                (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
02070                 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
02071                 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
02072
02073 #endif /* I2C2 */
02074
02075 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__)   \
02076                (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
02077                 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
02078                 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
02079
02080 #if defined(RCC_PLLSAI2_SUPPORT)
02081
02082 #define IS_RCC_SAI1CLK(__SOURCE__)   \
02083                (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
02084                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
02085                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
02086                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
02087
02088 #else
02089
02090 #define IS_RCC_SAI1CLK(__SOURCE__)   \
02091                (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
02092                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
02093                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
02094
02095 #endif /* RCC_PLLSAI2_SUPPORT */
02096
02097 #if defined(RCC_PLLSAI2_SUPPORT)
02098
02099 #define IS_RCC_SAI2CLK(__SOURCE__)   \
02100                (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
02101                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
02102                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)     || \
02103                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
02104
02105 #endif /* RCC_PLLSAI2_SUPPORT */
02106
02107 #define IS_RCC_LPTIM1CLK(__SOURCE__)  \
02108                (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) || \
02109                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)  || \
02110                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)  || \
02111                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
02112
02113 #define IS_RCC_LPTIM2CLK(__SOURCE__)  \
02114                (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) || \
02115                 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)  || \
02116                 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)  || \
02117                 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
02118
02119 #if defined(SDMMC1)
02120 #if defined(RCC_HSI48_SUPPORT)
02121
02122 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \
02123                (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48)   || \
02124                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
02125                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \
02126                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
02127
02128 #else
02129
02130 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \
02131                (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE)    || \
02132                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
02133                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \
02134                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
02135
02136 #endif /* RCC_HSI48_SUPPORT */
02137 #endif /* SDMMC1 */
02138
02139 #if defined(RCC_HSI48_SUPPORT)
02140
02141 #define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
02142                (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \
02143                 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
02144                 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
02145                 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
02146
02147 #else
02148
02149 #define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
02150                (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE)    || \
02151                 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
02152                 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
02153                 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
02154
02155 #endif /* RCC_HSI48_SUPPORT */
02156
02157 #if defined(USB_OTG_FS) || defined(USB)
02158 #if defined(RCC_HSI48_SUPPORT)
02159
02160 #define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
02161                (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \
02162                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
02163                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
02164                 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
02165
02166 #else
02167
02168 #define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
02169                (((__SOURCE__) == RCC_USBCLKSOURCE_NONE)    || \
02170                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
02171                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
02172                 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
02173
02174 #endif /* RCC_HSI48_SUPPORT */
02175 #endif /* USB_OTG_FS || USB */
02176
02177 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
02178
02179 #define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \
02180                (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \
02181                 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
02182                 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
02183                 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
02184
02185 #else
02186
02187 #define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \
02188                (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \
02189                 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
02190                 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
02191
02192 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
02193
02194 #if defined(SWPMI1)
02195
02196 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__)  \
02197                (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) || \
02198                 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
02199
02200 #endif /* SWPMI1 */
02201
02202 #if defined(DFSDM1_Filter0)
02203
02204 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__)  \
02205                (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK) || \
02206                 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
02207
02208 #endif /* DFSDM1_Filter0 */
02209
02210 #define IS_RCC_PLLSAI1SOURCE(__VALUE__)    IS_RCC_PLLSOURCE(__VALUE__)
02211
02212 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
02213
02214 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
02215
02216 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
02217 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
02218 #else
02219 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
02220 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
02221
02222 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
02223                                             ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
02224
02225 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
02226                                             ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
02227
02228 #if defined(RCC_PLLSAI2_SUPPORT)
02229
02230 #define IS_RCC_PLLSAI2SOURCE(__VALUE__)    IS_RCC_PLLSOURCE(__VALUE__)
02231
02232 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
02233
02234 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
02235
02236 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
02237 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
02238 #else
02239 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
02240 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
02241
02242 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
02243                                             ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
02244
02245 #endif /* RCC_PLLSAI2_SUPPORT */
02246
02247 #if defined(CRS)
02248
02249 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
02250                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
02251                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
02252
02253 #define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
02254                                             ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
02255                                             ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
02256                                             ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
02257
02258 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
02259                                                 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
02260
02261 #define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
02262
02263 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
02264
02265 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
02266
02267 #define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
02268                                             ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
02269
02270 #endif /* CRS */
02271
02272 /**
02273   * @}
02274   */
02275
02276 /**
02277   * @}
02278   */
02279
02280 /**
02281   * @}
02282   */
02283
02284 #ifdef __cplusplus
02285 }
02286 #endif
02287
02288 #endif /* __STM32L4xx_HAL_RCC_EX_H */
02289
02290 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rng.c Source File

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  • Src
stm32l4xx_hal_rng.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rng.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   RNG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Random Number Generator (RNG) peripheral:
00010   *           + Initialization/de-initialization functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019       The RNG HAL driver can be used as follows:
00020
00021       (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
00022           in HAL_RNG_MspInit().
00023       (#) Activate the RNG peripheral using HAL_RNG_Init() function.
00024       (#) Wait until the 32-bit Random Number Generator contains a valid
00025           random data using (polling/interrupt) mode.
00026       (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
00027
00028   @endverbatim
00029   ******************************************************************************
00030   * @attention
00031   *
00032   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00033   *
00034   * Redistribution and use in source and binary forms, with or without modification,
00035   * are permitted provided that the following conditions are met:
00036   *   1. Redistributions of source code must retain the above copyright notice,
00037   *      this list of conditions and the following disclaimer.
00038   *   2. Redistributions in binary form must reproduce the above copyright notice,
00039   *      this list of conditions and the following disclaimer in the documentation
00040   *      and/or other materials provided with the distribution.
00041   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00042   *      may be used to endorse or promote products derived from this software
00043   *      without specific prior written permission.
00044   *
00045   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00046   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00047   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00048   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00049   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00050   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00051   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00052   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00053   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00054   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00055   *
00056   ******************************************************************************
00057   */
00058
00059 /* Includes ------------------------------------------------------------------*/
00060 #include "stm32l4xx_hal.h"
00061
00062 /** @addtogroup STM32L4xx_HAL_Driver
00063   * @{
00064   */
00065
00066 /** @defgroup RNG RNG
00067   * @brief RNG HAL module driver.
00068   * @{
00069   */
00070
00071 #ifdef HAL_RNG_MODULE_ENABLED
00072
00073
00074
00075 /* Private types -------------------------------------------------------------*/
00076 /* Private defines -----------------------------------------------------------*/
00077 /** @defgroup RNG_Private_Constants RNG_Private_Constants
00078   * @{
00079   */
00080 #define RNG_TIMEOUT_VALUE     2
00081 /**
00082   * @}
00083   */
00084
00085 /* Private macros ------------------------------------------------------------*/
00086 /* Private variables ---------------------------------------------------------*/
00087 /* Private function prototypes -----------------------------------------------*/
00088 /* Private functions ---------------------------------------------------------*/
00089 /* Exported functions --------------------------------------------------------*/
00090
00091 /** @addtogroup RNG_Exported_Functions
00092   * @{
00093   */
00094
00095 /** @addtogroup RNG_Exported_Functions_Group1
00096  *  @brief   Initialization and de-initialization functions
00097  *
00098 @verbatim
00099  ===============================================================================
00100           ##### Initialization and de-initialization functions #####
00101  ===============================================================================
00102     [..]  This section provides functions allowing to:
00103       (+) Initialize the RNG according to the specified parameters
00104           in the RNG_InitTypeDef and create the associated handle
00105       (+) DeInitialize the RNG peripheral
00106       (+) Initialize the RNG MSP (MCU Specific Package)
00107       (+) DeInitialize the RNG MSP
00108
00109 @endverbatim
00110   * @{
00111   */
00112
00113 /**
00114   * @brief  Initialize the RNG peripheral and initialize the associated handle.
00115   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00116   * @retval HAL status
00117   */
00118 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
00119 {
00120   /* Check the RNG handle allocation */
00121   if(hrng == NULL)
00122   {
00123     return HAL_ERROR;
00124   }
00125
00126   assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
00127
00128   __HAL_LOCK(hrng);
00129
00130   if(hrng->State == HAL_RNG_STATE_RESET)
00131   {
00132     /* Allocate lock resource and initialize it */
00133     hrng->Lock = HAL_UNLOCKED;
00134
00135     /* Init the low level hardware */
00136     HAL_RNG_MspInit(hrng);
00137   }
00138
00139   /* Change RNG peripheral state */
00140   hrng->State = HAL_RNG_STATE_BUSY;
00141
00142   /* Enable the RNG Peripheral */
00143   __HAL_RNG_ENABLE(hrng);
00144
00145   /* Initialize the RNG state */
00146   hrng->State = HAL_RNG_STATE_READY;
00147
00148   __HAL_UNLOCK(hrng);
00149
00150   /* Return function status */
00151   return HAL_OK;
00152 }
00153
00154 /**
00155   * @brief  DeInitialize the RNG peripheral.
00156   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
00160 {
00161   /* Check the RNG handle allocation */
00162   if(hrng == NULL)
00163   {
00164     return HAL_ERROR;
00165   }
00166   /* Disable the RNG Peripheral */
00167   CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
00168
00169   /* Clear RNG interrupt status flags */
00170   CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
00171
00172   /* DeInit the low level hardware */
00173   HAL_RNG_MspDeInit(hrng);
00174
00175   /* Update the RNG state */
00176   hrng->State = HAL_RNG_STATE_RESET;
00177
00178   /* Release Lock */
00179   __HAL_UNLOCK(hrng);
00180
00181   /* Return the function status */
00182   return HAL_OK;
00183 }
00184
00185 /**
00186   * @brief  Initialize the RNG MSP.
00187   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00188   * @retval None
00189   */
00190 __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
00191 {
00192   /* Prevent unused argument(s) compilation warning */
00193   UNUSED(hrng);
00194
00195   /* NOTE : This function should not be modified. When the callback is needed,
00196             function HAL_RNG_MspInit must be implemented in the user file.
00197    */
00198 }
00199
00200 /**
00201   * @brief  DeInitialize the RNG MSP.
00202   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00203   * @retval None
00204   */
00205 __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
00206 {
00207   /* Prevent unused argument(s) compilation warning */
00208   UNUSED(hrng);
00209
00210   /* NOTE : This function should not be modified. When the callback is needed,
00211             function HAL_RNG_MspDeInit must be implemented in the user file.
00212    */
00213 }
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @addtogroup RNG_Exported_Functions_Group2
00220  *  @brief    Management functions.
00221  *
00222 @verbatim
00223  ===============================================================================
00224                       ##### Peripheral Control functions #####
00225  ===============================================================================
00226     [..]  This section provides functions allowing to:
00227       (+) Get the 32 bit Random number
00228       (+) Get the 32 bit Random number with interrupt enabled
00229       (+) Handle RNG interrupt request
00230
00231 @endverbatim
00232   * @{
00233   */
00234
00235 /**
00236   * @brief  Generate a 32-bit random number.
00237   * @note   Each time the random number data is read the RNG_FLAG_DRDY flag
00238   *         is automatically cleared.
00239   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00240   * @param  random32bit: pointer to generated random number variable if successful.
00241   * @retval HAL status
00242   */
00243
00244 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
00245 {
00246   uint32_t tickstart = 0;
00247   HAL_StatusTypeDef status = HAL_OK;
00248
00249   /* Process Locked */
00250   __HAL_LOCK(hrng);
00251
00252   /* Check RNS peripheral state */
00253   if(hrng->State == HAL_RNG_STATE_READY)
00254   {
00255     /* Change RNG peripheral state */
00256     hrng->State = HAL_RNG_STATE_BUSY;
00257
00258     /* Get tick */
00259     tickstart = HAL_GetTick();
00260
00261     /* Check if data register contains valid random data */
00262     while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
00263     {
00264       if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
00265       {
00266         hrng->State = HAL_RNG_STATE_ERROR;
00267
00268         /* Process Unlocked */
00269         __HAL_UNLOCK(hrng);
00270
00271         return HAL_TIMEOUT;
00272       }
00273     }
00274
00275     /* Get a 32bit Random number */
00276     hrng->RandomNumber = hrng->Instance->DR;
00277     *random32bit = hrng->RandomNumber;
00278
00279     hrng->State = HAL_RNG_STATE_READY;
00280   }
00281   else
00282   {
00283     status = HAL_ERROR;
00284   }
00285
00286   /* Process Unlocked */
00287   __HAL_UNLOCK(hrng);
00288
00289   return status;
00290 }
00291
00292 /**
00293   * @brief  Generate a 32-bit random number in interrupt mode.
00294   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00295   * @retval HAL status
00296   */
00297 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
00298 {
00299   HAL_StatusTypeDef status = HAL_OK;
00300
00301   /* Process Locked */
00302   __HAL_LOCK(hrng);
00303
00304   /* Check RNG peripheral state */
00305   if(hrng->State == HAL_RNG_STATE_READY)
00306   {
00307     /* Change RNG peripheral state */
00308     hrng->State = HAL_RNG_STATE_BUSY;
00309
00310     /* Process Unlocked */
00311     __HAL_UNLOCK(hrng);
00312
00313     /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00314     __HAL_RNG_ENABLE_IT(hrng);
00315   }
00316   else
00317   {
00318     /* Process Unlocked */
00319     __HAL_UNLOCK(hrng);
00320
00321     status = HAL_ERROR;
00322   }
00323
00324   return status;
00325 }
00326
00327 /**
00328   * @brief  Handle RNG interrupt request.
00329   * @note   In the case of a clock error, the RNG is no more able to generate
00330   *         random numbers because the PLL48CLK clock is not correct. User has
00331   *         to check that the clock controller is correctly configured to provide
00332   *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
00333   *         The clock error has no impact on the previously generated
00334   *         random numbers, and the RNG_DR register contents can be used.
00335   * @note   In the case of a seed error, the generation of random numbers is
00336   *         interrupted as long as the SECS bit is '1'. If a number is
00337   *         available in the RNG_DR register, it must not be used because it may
00338   *         not have enough entropy. In this case, it is recommended to clear the
00339   *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
00340   *         the RNG peripheral to reinitialize and restart the RNG.
00341   * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
00342   *         or CEIS are set.
00343   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00344   * @retval None
00345
00346   */
00347 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
00348 {
00349   /* RNG clock error interrupt occurred */
00350   if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
00351   {
00352     /* Change RNG peripheral state */
00353     hrng->State = HAL_RNG_STATE_ERROR;
00354
00355     HAL_RNG_ErrorCallback(hrng);
00356
00357     /* Clear the clock error flag */
00358     __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
00359
00360   }
00361
00362   /* Check RNG data ready interrupt occurred */
00363   if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
00364   {
00365     /* Generate random number once, so disable the IT */
00366     __HAL_RNG_DISABLE_IT(hrng);
00367
00368     /* Get the 32bit Random number (DRDY flag automatically cleared) */
00369     hrng->RandomNumber = hrng->Instance->DR;
00370
00371     if(hrng->State != HAL_RNG_STATE_ERROR)
00372     {
00373       /* Change RNG peripheral state */
00374       hrng->State = HAL_RNG_STATE_READY;
00375
00376       /* Data Ready callback */
00377       HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
00378     }
00379   }
00380 }
00381
00382 /**
00383   * @brief  Return generated random number in polling mode (Obsolete).
00384   * @note   Use HAL_RNG_GenerateRandomNumber() API instead.
00385   * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
00386   *                the configuration information for RNG.
00387   * @retval random value
00388   */
00389 uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
00390 {
00391   if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
00392   {
00393     return hrng->RandomNumber;
00394   }
00395   else
00396   {
00397     return 0;
00398   }
00399 }
00400
00401
00402 /**
00403   * @brief  Return a 32-bit random number with interrupt enabled (Obsolete).
00404   * @note   Use HAL_RNG_GenerateRandomNumber_IT() API instead.
00405   * @param  hrng: RNG handle
00406   * @retval 32-bit random number
00407   */
00408 uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
00409 {
00410   uint32_t random32bit = 0;
00411
00412   /* Process locked */
00413   __HAL_LOCK(hrng);
00414
00415   /* Change RNG peripheral state */
00416   hrng->State = HAL_RNG_STATE_BUSY;
00417
00418   /* Get a 32bit Random number */
00419   random32bit = hrng->Instance->DR;
00420
00421   /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00422   __HAL_RNG_ENABLE_IT(hrng);
00423
00424   /* Return the 32 bit random number */
00425   return random32bit;
00426 }
00427
00428
00429
00430 /**
00431   * @brief  Read latest generated random number.
00432   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00433   * @retval random value
00434   */
00435 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
00436 {
00437   return(hrng->RandomNumber);
00438 }
00439
00440 /**
00441   * @brief  Data Ready callback in non-blocking mode.
00442   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00443   * @param  random32bit: generated random value
00444   * @retval None
00445   */
00446 __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
00447 {
00448   /* Prevent unused argument(s) compilation warning */
00449   UNUSED(hrng);
00450   UNUSED(random32bit);
00451
00452   /* NOTE : This function should not be modified. When the callback is needed,
00453             function HAL_RNG_ReadyDataCallback must be implemented in the user file.
00454    */
00455 }
00456
00457 /**
00458   * @brief  RNG error callback.
00459   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00460   * @retval None
00461   */
00462 __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
00463 {
00464   /* Prevent unused argument(s) compilation warning */
00465   UNUSED(hrng);
00466
00467   /* NOTE : This function should not be modified. When the callback is needed,
00468             function HAL_RNG_ErrorCallback must be implemented in the user file.
00469    */
00470 }
00471
00472 /**
00473   * @}
00474   */
00475
00476 /** @addtogroup RNG_Exported_Functions_Group3
00477  *  @brief    Peripheral State functions.
00478  *
00479 @verbatim
00480  ===============================================================================
00481                       ##### Peripheral State functions #####
00482  ===============================================================================
00483     [..]
00484     This subsection permits to get in run-time the status of the peripheral.
00485
00486 @endverbatim
00487   * @{
00488   */
00489
00490 /**
00491   * @brief  Return the RNG handle state.
00492   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00493   * @retval HAL state
00494   */
00495 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
00496 {
00497   /* Return RNG handle state */
00498   return hrng->State;
00499 }
00500
00501 /**
00502   * @}
00503   */
00504
00505 /**
00506   * @}
00507   */
00508
00509
00510 #endif /* HAL_RNG_MODULE_ENABLED */
00511 /**
00512   * @}
00513   */
00514
00515 /**
00516   * @}
00517   */
00518
00519 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rng.h Source File

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stm32l4xx_hal_rng.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rng.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of RNG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_RNG_H
00040 #define __STM32L4xx_HAL_RNG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RNG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RNG_Exported_Types RNG Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  RNG HAL State Structure definition
00064   */
00065 typedef enum
00066 {
00067   HAL_RNG_STATE_RESET     = 0x00,  /*!< RNG not yet initialized or disabled */
00068   HAL_RNG_STATE_READY     = 0x01,  /*!< RNG initialized and ready for use   */
00069   HAL_RNG_STATE_BUSY      = 0x02,  /*!< RNG internal process is ongoing     */
00070   HAL_RNG_STATE_TIMEOUT   = 0x03,  /*!< RNG timeout state                   */
00071   HAL_RNG_STATE_ERROR     = 0x04   /*!< RNG error state                     */
00072
00073 }HAL_RNG_StateTypeDef;
00074
00075 /**
00076   * @brief  RNG Handle Structure definition
00077   */
00078 typedef struct
00079 {
00080   RNG_TypeDef                 *Instance;  /*!< Register base address   */
00081
00082   HAL_LockTypeDef             Lock;       /*!< RNG locking object      */
00083
00084   __IO HAL_RNG_StateTypeDef   State;      /*!< RNG communication state */
00085
00086   uint32_t               RandomNumber;    /*!< Last Generated RNG Data */
00087
00088 }RNG_HandleTypeDef;
00089
00090 /**
00091   * @}
00092   */
00093
00094 /* Exported constants --------------------------------------------------------*/
00095 /** @defgroup RNG_Exported_Constants RNG Exported Constants
00096   * @{
00097   */
00098
00099 /** @defgroup RNG_Interrupt_definition  RNG Interrupts Definition
00100   * @{
00101   */
00102 #define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
00103 #define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
00104 #define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup RNG_Flag_definition  RNG Flags Definition
00110   * @{
00111   */
00112 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
00113 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
00114 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
00115 /**
00116   * @}
00117   */
00118
00119 /**
00120   * @}
00121   */
00122
00123 /* Exported macros -----------------------------------------------------------*/
00124 /** @defgroup RNG_Exported_Macros RNG Exported Macros
00125   * @{
00126   */
00127
00128 /** @brief Reset RNG handle state.
00129   * @param  __HANDLE__: RNG Handle
00130   * @retval None
00131   */
00132 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
00133
00134 /**
00135   * @brief  Enable the RNG peripheral.
00136   * @param  __HANDLE__: RNG Handle
00137   * @retval None
00138   */
00139 #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
00140
00141 /**
00142   * @brief  Disable the RNG peripheral.
00143   * @param  __HANDLE__: RNG Handle
00144   * @retval None
00145   */
00146 #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
00147
00148 /**
00149   * @brief  Check whether the specified RNG flag is set or not.
00150   * @param  __HANDLE__: RNG Handle
00151   * @param  __FLAG__: RNG flag
00152   *          This parameter can be one of the following values:
00153   *            @arg RNG_FLAG_DRDY:  Data ready
00154   *            @arg RNG_FLAG_CECS:  Clock error current status
00155   *            @arg RNG_FLAG_SECS:  Seed error current status
00156   * @retval The new state of __FLAG__ (SET or RESET).
00157   */
00158 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00159
00160
00161 /**
00162   * @brief  Clear the selected RNG flag status.
00163   * @param  __HANDLE__: RNG handle
00164   * @param  __FLAG__: RNG flag to clear
00165   * @note   WARNING: This is a dummy macro for HAL code alignment,
00166   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
00167   * @retval None
00168   */
00169 #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
00170
00171
00172
00173 /**
00174   * @brief  Enable the RNG interrupt.
00175   * @param  __HANDLE__: RNG Handle
00176   * @retval None
00177   */
00178 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
00179
00180 /**
00181   * @brief  Disable the RNG interrupt.
00182   * @param  __HANDLE__: RNG Handle
00183   * @retval None
00184   */
00185 #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
00186
00187 /**
00188   * @brief  Check whether the specified RNG interrupt has occurred or not.
00189   * @param  __HANDLE__: RNG Handle
00190   * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
00191   *         This parameter can be one of the following values:
00192   *            @arg RNG_IT_DRDY: Data ready interrupt
00193   *            @arg RNG_IT_CEI: Clock error interrupt
00194   *            @arg RNG_IT_SEI: Seed error interrupt
00195   * @retval The new state of __INTERRUPT__ (SET or RESET).
00196   */
00197 #define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00198
00199 /**
00200   * @brief  Clear the RNG interrupt status flags.
00201   * @param  __HANDLE__: RNG Handle
00202   * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
00203   *          This parameter can be one of the following values:
00204   *            @arg RNG_IT_CEI: Clock error interrupt
00205   *            @arg RNG_IT_SEI: Seed error interrupt
00206   * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
00207   * @retval None
00208   */
00209 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
00210
00211 /**
00212   * @}
00213   */
00214
00215
00216 /* Exported functions --------------------------------------------------------*/
00217 /** @defgroup RNG_Exported_Functions RNG Exported Functions
00218   * @{
00219   */
00220
00221 /* Initialization and de-initialization functions  ******************************/
00222 /** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
00223   * @{
00224   */
00225 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
00226 HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
00227 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
00228 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
00229 /**
00230   * @}
00231   */
00232
00233 /* Peripheral Control functions  ************************************************/
00234 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
00235   * @{
00236   */
00237 uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
00238 uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
00239
00240 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
00241 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
00242 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
00243
00244 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
00245 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
00246 void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
00247 /**
00248   * @}
00249   */
00250
00251 /* Peripheral State functions  **************************************************/
00252 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
00253   * @{
00254   */
00255 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
00256 /**
00257   * @}
00258   */
00259
00260 /**
00261   * @}
00262   */
00263
00264 /* Private types -------------------------------------------------------------*/
00265 /* Private defines -----------------------------------------------------------*/
00266 /* Private variables ---------------------------------------------------------*/
00267 /* Private constants ---------------------------------------------------------*/
00268 /* Private macros ------------------------------------------------------------*/
00269 /* Private functions prototypes ----------------------------------------------*/
00270
00271 /**
00272   * @}
00273   */
00274
00275 /**
00276   * @}
00277   */
00278
00279 #ifdef __cplusplus
00280 }
00281 #endif
00282
00283 #endif /* __STM32L4xx_HAL_RNG_H */
00284
00285 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rtc.c Source File

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stm32l4xx_hal_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rtc.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   RTC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Real-Time Clock (RTC) peripheral:
00010   *           + Initialization
00011   *           + Calendar (Time and Date) configuration
00012   *           + Alarms (Alarm A and Alarm B) configuration
00013   *           + WakeUp Timer configuration
00014   *           + TimeStamp configuration
00015   *           + Tampers configuration
00016   *           + Backup Data Registers configuration
00017   *           + RTC Tamper and TimeStamp Pins Selection
00018   *           + Interrupts and flags management
00019   *
00020   @verbatim
00021  ===============================================================================
00022                           ##### RTC Operating Condition #####
00023  ===============================================================================
00024   [..] The real-time clock (RTC) and the RTC backup registers can be powered
00025        from the VBAT voltage when the main VDD supply is powered off.
00026        To retain the content of the RTC backup registers and supply the RTC
00027        when VDD is turned off, VBAT pin can be connected to an optional
00028        standby voltage supplied by a battery or by another source.
00029
00030                    ##### Backup Domain Reset #####
00031  ===============================================================================
00032   [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
00033        to their reset values.
00034        A backup domain reset is generated when one of the following events occurs:
00035     (#) Software reset, triggered by setting the BDRST bit in the
00036         RCC Backup domain control register (RCC_BDCR).
00037     (#) VDD or VBAT power on, if both supplies have previously been powered off.
00038     (#) Tamper detection event resets all data backup registers.
00039
00040                    ##### Backup Domain Access #####
00041  ===================================================================
00042   [..] After reset, the backup domain (RTC registers, RTC backup data
00043        registers and backup SRAM) is protected against possible unwanted write
00044        accesses.
00045
00046   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00047     (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
00048         PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
00049     (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
00050
00051                   ##### How to use RTC Driver #####
00052  ===================================================================
00053   [..]
00054     (#) Enable the RTC domain access (see description in the section above).
00055     (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00056         format using the HAL_RTC_Init() function.
00057
00058   *** Time and Date configuration ***
00059   ===================================
00060   [..]
00061     (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
00062         and HAL_RTC_SetDate() functions.
00063     (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
00064
00065   *** Alarm configuration ***
00066   ===========================
00067   [..]
00068     (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
00069             You can also configure the RTC Alarm with interrupt mode using the
00070             HAL_RTC_SetAlarm_IT() function.
00071     (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
00072
00073                   ##### RTC and low power modes #####
00074  ===================================================================
00075   [..] The MCU can be woken up from a low power mode by an RTC alternate
00076        function.
00077   [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
00078        RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
00079        These RTC alternate functions can wake up the system from the Stop and
00080        Standby low power modes.
00081   [..] The system can also wake up from low power modes without depending
00082        on an external interrupt (Auto-wakeup mode), by using the RTC alarm
00083        or the RTC wakeup events.
00084   [..] The RTC provides a programmable time base for waking up from the
00085        Stop or Standby mode at regular intervals.
00086        Wakeup from STOP and Standby modes is possible only when the RTC clock source
00087        is LSE or LSI.
00088
00089    @endverbatim
00090
00091   ******************************************************************************
00092   * @attention
00093   *
00094   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00095   *
00096   * Redistribution and use in source and binary forms, with or without modification,
00097   * are permitted provided that the following conditions are met:
00098   *   1. Redistributions of source code must retain the above copyright notice,
00099   *      this list of conditions and the following disclaimer.
00100   *   2. Redistributions in binary form must reproduce the above copyright notice,
00101   *      this list of conditions and the following disclaimer in the documentation
00102   *      and/or other materials provided with the distribution.
00103   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00104   *      may be used to endorse or promote products derived from this software
00105   *      without specific prior written permission.
00106   *
00107   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00108   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00109   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00110   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00111   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00112   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00113   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00114   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00115   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00116   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00117   *
00118   ******************************************************************************
00119   */
00120
00121 /* Includes ------------------------------------------------------------------*/
00122 #include "stm32l4xx_hal.h"
00123
00124 /** @addtogroup STM32L4xx_HAL_Driver
00125   * @{
00126   */
00127
00128 /** @defgroup RTC RTC
00129   * @brief RTC HAL module driver
00130   * @{
00131   */
00132
00133 #ifdef HAL_RTC_MODULE_ENABLED
00134
00135 /* Private typedef -----------------------------------------------------------*/
00136 /* Private define ------------------------------------------------------------*/
00137 /* Private macro -------------------------------------------------------------*/
00138 /* Private variables ---------------------------------------------------------*/
00139 /* Private function prototypes -----------------------------------------------*/
00140 /* Exported functions --------------------------------------------------------*/
00141
00142 /** @defgroup RTC_Exported_Functions RTC Exported Functions
00143   * @{
00144   */
00145
00146 /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
00147  *  @brief    Initialization and Configuration functions
00148  *
00149 @verbatim
00150  ===============================================================================
00151               ##### Initialization and de-initialization functions #####
00152  ===============================================================================
00153    [..] This section provide functions allowing to initialize and configure the
00154          RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
00155          RTC registers Write protection, enter and exit the RTC initialization mode,
00156          RTC registers synchronization check and reference clock detection enable.
00157          (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
00158              It is split into 2 programmable prescalers to minimize power consumption.
00159              (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
00160              (++) When both prescalers are used, it is recommended to configure the
00161                  asynchronous prescaler to a high value to minimize power consumption.
00162          (#) All RTC registers are Write protected. Writing to the RTC registers
00163              is enabled by writing a key into the Write Protection register, RTC_WPR.
00164          (#) To configure the RTC Calendar, user application should enter
00165              initialization mode. In this mode, the calendar counter is stopped
00166              and its value can be updated. When the initialization sequence is
00167              complete, the calendar restarts counting after 4 RTCCLK cycles.
00168          (#) To read the calendar through the shadow registers after Calendar
00169              initialization, calendar update or after wakeup from low power modes
00170              the software must first clear the RSF flag. The software must then
00171              wait until it is set again before reading the calendar, which means
00172              that the calendar registers have been correctly copied into the
00173              RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function
00174              implements the above software sequence (RSF clear and RSF check).
00175
00176 @endverbatim
00177   * @{
00178   */
00179
00180 /**
00181   * @brief  Initialize the RTC according to the specified parameters
00182   *         in the RTC_InitTypeDef structure and initialize the associated handle.
00183   * @param  hrtc: RTC handle
00184   * @retval HAL status
00185   */
00186 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
00187 {
00188   /* Check the RTC peripheral state */
00189   if(hrtc == NULL)
00190   {
00191      return HAL_ERROR;
00192   }
00193
00194   /* Check the parameters */
00195   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00196   assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
00197   assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
00198   assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
00199   assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
00200   assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
00201   assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
00202   assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
00203
00204   if(hrtc->State == HAL_RTC_STATE_RESET)
00205   {
00206     /* Allocate lock resource and initialize it */
00207     hrtc->Lock = HAL_UNLOCKED;
00208
00209     /* Initialize RTC MSP */
00210     HAL_RTC_MspInit(hrtc);
00211   }
00212
00213   /* Set RTC state */
00214   hrtc->State = HAL_RTC_STATE_BUSY;
00215
00216   /* Disable the write protection for RTC registers */
00217   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00218
00219   /* Set Initialization mode */
00220   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00221   {
00222     /* Enable the write protection for RTC registers */
00223     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00224
00225     /* Set RTC state */
00226     hrtc->State = HAL_RTC_STATE_ERROR;
00227
00228     return HAL_ERROR;
00229   }
00230   else
00231   {
00232     /* Clear RTC_CR FMT, OSEL and POL Bits */
00233     hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
00234     /* Set RTC_CR register */
00235     hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
00236
00237     /* Configure the RTC PRER */
00238     hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
00239     hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
00240
00241     /* Exit Initialization mode */
00242     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00243
00244     hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
00245     hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
00246
00247     /* Enable the write protection for RTC registers */
00248     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00249
00250     /* Set RTC state */
00251     hrtc->State = HAL_RTC_STATE_READY;
00252
00253     return HAL_OK;
00254   }
00255 }
00256
00257 /**
00258   * @brief  DeInitialize the RTC peripheral.
00259   * @param  hrtc: RTC handle
00260   * @note   This function doesn't reset the RTC Backup Data registers.
00261   * @retval HAL status
00262   */
00263 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
00264 {
00265   uint32_t tickstart = 0;
00266
00267   /* Check the parameters */
00268   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00269
00270   /* Set RTC state */
00271   hrtc->State = HAL_RTC_STATE_BUSY;
00272
00273   /* Disable the write protection for RTC registers */
00274   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00275
00276   /* Set Initialization mode */
00277   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00278   {
00279     /* Enable the write protection for RTC registers */
00280     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00281
00282     /* Set RTC state */
00283     hrtc->State = HAL_RTC_STATE_ERROR;
00284
00285     return HAL_ERROR;
00286   }
00287   else
00288   {
00289     /* Reset TR, DR and CR registers */
00290     hrtc->Instance->TR = (uint32_t)0x00000000;
00291     hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00292     /* Reset All CR bits except CR[2:0] */
00293     hrtc->Instance->CR &= RTC_CR_WUCKSEL;
00294
00295     tickstart = HAL_GetTick();
00296
00297     /* Wait till WUTWF flag is set and if Time out is reached exit */
00298     while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
00299     {
00300       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00301       {
00302         /* Enable the write protection for RTC registers */
00303         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00304
00305         /* Set RTC state */
00306         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00307
00308         return HAL_TIMEOUT;
00309       }
00310     }
00311
00312     /* Reset all RTC CR register bits */
00313     hrtc->Instance->CR &= (uint32_t)0x00000000;
00314     hrtc->Instance->WUTR = RTC_WUTR_WUT;
00315     hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF));
00316     hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
00317     hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
00318     hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
00319     hrtc->Instance->CALR = (uint32_t)0x00000000;
00320     hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
00321     hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
00322
00323     /* Reset ISR register and exit initialization mode */
00324     hrtc->Instance->ISR = (uint32_t)0x00000000;
00325
00326     /* Reset Tamper configuration register */
00327     hrtc->Instance->TAMPCR = 0x00000000;
00328
00329     /* Reset Option register */
00330     hrtc->Instance->OR = 0x00000000;
00331
00332     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00333     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00334     {
00335       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00336       {
00337         /* Enable the write protection for RTC registers */
00338         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00339
00340         hrtc->State = HAL_RTC_STATE_ERROR;
00341
00342         return HAL_ERROR;
00343       }
00344     }
00345   }
00346
00347   /* Enable the write protection for RTC registers */
00348   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00349
00350   /* De-Initialize RTC MSP */
00351   HAL_RTC_MspDeInit(hrtc);
00352
00353   hrtc->State = HAL_RTC_STATE_RESET;
00354
00355   /* Release Lock */
00356   __HAL_UNLOCK(hrtc);
00357
00358   return HAL_OK;
00359 }
00360
00361 /**
00362   * @brief  Initialize the RTC MSP.
00363   * @param  hrtc: RTC handle
00364   * @retval None
00365   */
00366 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
00367 {
00368   /* Prevent unused argument(s) compilation warning */
00369   UNUSED(hrtc);
00370
00371   /* NOTE : This function should not be modified, when the callback is needed,
00372             the HAL_RTC_MspInit could be implemented in the user file
00373    */
00374 }
00375
00376 /**
00377   * @brief  DeInitialize the RTC MSP.
00378   * @param  hrtc: RTC handle
00379   * @retval None
00380   */
00381 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
00382 {
00383   /* Prevent unused argument(s) compilation warning */
00384   UNUSED(hrtc);
00385
00386   /* NOTE : This function should not be modified, when the callback is needed,
00387             the HAL_RTC_MspDeInit could be implemented in the user file
00388    */
00389 }
00390
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
00396  *  @brief   RTC Time and Date functions
00397  *
00398 @verbatim
00399  ===============================================================================
00400                  ##### RTC Time and Date functions #####
00401  ===============================================================================
00402
00403  [..] This section provides functions allowing to configure Time and Date features
00404
00405 @endverbatim
00406   * @{
00407   */
00408
00409 /**
00410   * @brief  Set RTC current time.
00411   * @param  hrtc: RTC handle
00412   * @param  sTime: Pointer to Time structure
00413   * @param  Format: Specifies the format of the entered parameters.
00414   *          This parameter can be one of the following values:
00415   *            @arg RTC_FORMAT_BIN: Binary data format
00416   *            @arg RTC_FORMAT_BCD: BCD data format
00417   * @retval HAL status
00418   */
00419 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00420 {
00421   uint32_t tmpreg = 0;
00422
00423  /* Check the parameters */
00424   assert_param(IS_RTC_FORMAT(Format));
00425   assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
00426   assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
00427
00428   /* Process Locked */
00429   __HAL_LOCK(hrtc);
00430
00431   hrtc->State = HAL_RTC_STATE_BUSY;
00432
00433   if(Format == RTC_FORMAT_BIN)
00434   {
00435     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00436     {
00437       assert_param(IS_RTC_HOUR12(sTime->Hours));
00438       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00439     }
00440     else
00441     {
00442       sTime->TimeFormat = 0x00;
00443       assert_param(IS_RTC_HOUR24(sTime->Hours));
00444     }
00445     assert_param(IS_RTC_MINUTES(sTime->Minutes));
00446     assert_param(IS_RTC_SECONDS(sTime->Seconds));
00447
00448     tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
00449                         ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
00450                         ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
00451                         (((uint32_t)sTime->TimeFormat) << 16));
00452   }
00453   else
00454   {
00455     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00456     {
00457       tmpreg = RTC_Bcd2ToByte(sTime->Hours);
00458       assert_param(IS_RTC_HOUR12(tmpreg));
00459       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00460     }
00461     else
00462     {
00463       sTime->TimeFormat = 0x00;
00464       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
00465     }
00466     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
00467     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
00468     tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
00469               ((uint32_t)(sTime->Minutes) << 8) | \
00470               ((uint32_t)sTime->Seconds) | \
00471               ((uint32_t)(sTime->TimeFormat) << 16));
00472   }
00473
00474   /* Disable the write protection for RTC registers */
00475   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00476
00477   /* Set Initialization mode */
00478   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00479   {
00480     /* Enable the write protection for RTC registers */
00481     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00482
00483     /* Set RTC state */
00484     hrtc->State = HAL_RTC_STATE_ERROR;
00485
00486     /* Process Unlocked */
00487     __HAL_UNLOCK(hrtc);
00488
00489     return HAL_ERROR;
00490   }
00491   else
00492   {
00493     /* Set the RTC_TR register */
00494     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
00495
00496     /* Clear the bits to be configured */
00497     hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
00498
00499     /* Configure the RTC_CR register */
00500     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
00501
00502     /* Exit Initialization mode */
00503     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00504
00505     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00506     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00507     {
00508       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00509       {
00510         /* Enable the write protection for RTC registers */
00511         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00512
00513         hrtc->State = HAL_RTC_STATE_ERROR;
00514
00515         /* Process Unlocked */
00516         __HAL_UNLOCK(hrtc);
00517
00518         return HAL_ERROR;
00519       }
00520     }
00521
00522     /* Enable the write protection for RTC registers */
00523     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00524
00525    hrtc->State = HAL_RTC_STATE_READY;
00526
00527    __HAL_UNLOCK(hrtc);
00528
00529    return HAL_OK;
00530   }
00531 }
00532
00533 /**
00534   * @brief  Get RTC current time.
00535   * @param  hrtc: RTC handle
00536   * @param  sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned
00537   *                with input format (BIN or BCD), also SubSeconds field returning the
00538   *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
00539   *                factor to be used for second fraction ratio computation.
00540   * @param  Format: Specifies the format of the entered parameters.
00541   *          This parameter can be one of the following values:
00542   *            @arg RTC_FORMAT_BIN: Binary data format
00543   *            @arg RTC_FORMAT_BCD: BCD data format
00544   * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
00545   *        value in second fraction ratio with time unit following generic formula:
00546   *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
00547   *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
00548   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00549   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00550   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
00551   *        to ensure consistency between the time and date values.
00552   * @retval HAL status
00553   */
00554 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00555 {
00556   uint32_t tmpreg = 0;
00557
00558   /* Check the parameters */
00559   assert_param(IS_RTC_FORMAT(Format));
00560
00561   /* Get subseconds structure field from the corresponding register*/
00562   sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
00563
00564   /* Get SecondFraction structure field from the corresponding register field*/
00565   sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
00566
00567   /* Get the TR register */
00568   tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
00569
00570   /* Fill the structure fields with the read parameters */
00571   sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
00572   sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
00573   sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
00574   sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
00575
00576   /* Check the input parameters format */
00577   if(Format == RTC_FORMAT_BIN)
00578   {
00579     /* Convert the time structure parameters to Binary format */
00580     sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
00581     sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
00582     sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
00583   }
00584
00585   return HAL_OK;
00586 }
00587
00588 /**
00589   * @brief  Set RTC current date.
00590   * @param  hrtc: RTC handle
00591   * @param  sDate: Pointer to date structure
00592   * @param  Format: specifies the format of the entered parameters.
00593   *          This parameter can be one of the following values:
00594   *            @arg RTC_FORMAT_BIN: Binary data format
00595   *            @arg RTC_FORMAT_BCD: BCD data format
00596   * @retval HAL status
00597   */
00598 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00599 {
00600   uint32_t datetmpreg = 0;
00601
00602  /* Check the parameters */
00603   assert_param(IS_RTC_FORMAT(Format));
00604
00605  /* Process Locked */
00606  __HAL_LOCK(hrtc);
00607
00608   hrtc->State = HAL_RTC_STATE_BUSY;
00609
00610   if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
00611   {
00612     sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
00613   }
00614
00615   assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
00616
00617   if(Format == RTC_FORMAT_BIN)
00618   {
00619     assert_param(IS_RTC_YEAR(sDate->Year));
00620     assert_param(IS_RTC_MONTH(sDate->Month));
00621     assert_param(IS_RTC_DATE(sDate->Date));
00622
00623    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
00624                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
00625                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
00626                  ((uint32_t)sDate->WeekDay << 13));
00627   }
00628   else
00629   {
00630     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
00631     datetmpreg = RTC_Bcd2ToByte(sDate->Month);
00632     assert_param(IS_RTC_MONTH(datetmpreg));
00633     datetmpreg = RTC_Bcd2ToByte(sDate->Date);
00634     assert_param(IS_RTC_DATE(datetmpreg));
00635
00636     datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
00637                   (((uint32_t)sDate->Month) << 8) | \
00638                   ((uint32_t)sDate->Date) | \
00639                   (((uint32_t)sDate->WeekDay) << 13));
00640   }
00641
00642   /* Disable the write protection for RTC registers */
00643   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00644
00645   /* Set Initialization mode */
00646   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00647   {
00648     /* Enable the write protection for RTC registers */
00649     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00650
00651     /* Set RTC state*/
00652     hrtc->State = HAL_RTC_STATE_ERROR;
00653
00654     /* Process Unlocked */
00655     __HAL_UNLOCK(hrtc);
00656
00657     return HAL_ERROR;
00658   }
00659   else
00660   {
00661     /* Set the RTC_DR register */
00662     hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
00663
00664     /* Exit Initialization mode */
00665     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00666
00667     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00668     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
00669     {
00670       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00671       {
00672         /* Enable the write protection for RTC registers */
00673         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00674
00675         hrtc->State = HAL_RTC_STATE_ERROR;
00676
00677         /* Process Unlocked */
00678         __HAL_UNLOCK(hrtc);
00679
00680         return HAL_ERROR;
00681       }
00682     }
00683
00684     /* Enable the write protection for RTC registers */
00685     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00686
00687     hrtc->State = HAL_RTC_STATE_READY ;
00688
00689     /* Process Unlocked */
00690     __HAL_UNLOCK(hrtc);
00691
00692     return HAL_OK;
00693   }
00694 }
00695
00696 /**
00697   * @brief  Get RTC current date.
00698   * @param  hrtc: RTC handle
00699   * @param  sDate: Pointer to Date structure
00700   * @param  Format: Specifies the format of the entered parameters.
00701   *          This parameter can be one of the following values:
00702   *            @arg RTC_FORMAT_BIN:  Binary data format
00703   *            @arg RTC_FORMAT_BCD:  BCD data format
00704   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00705   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00706   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read.
00707   * @retval HAL status
00708   */
00709 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00710 {
00711   uint32_t datetmpreg = 0;
00712
00713   /* Check the parameters */
00714   assert_param(IS_RTC_FORMAT(Format));
00715
00716   /* Get the DR register */
00717   datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
00718
00719   /* Fill the structure fields with the read parameters */
00720   sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
00721   sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
00722   sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
00723   sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
00724
00725   /* Check the input parameters format */
00726   if(Format == RTC_FORMAT_BIN)
00727   {
00728     /* Convert the date structure parameters to Binary format */
00729     sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
00730     sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
00731     sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
00732   }
00733   return HAL_OK;
00734 }
00735
00736 /**
00737   * @}
00738   */
00739
00740 /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
00741  *  @brief   RTC Alarm functions
00742  *
00743 @verbatim
00744  ===============================================================================
00745                  ##### RTC Alarm functions #####
00746  ===============================================================================
00747
00748  [..] This section provides functions allowing to configure Alarm feature
00749
00750 @endverbatim
00751   * @{
00752   */
00753 /**
00754   * @brief  Set the specified RTC Alarm.
00755   * @param  hrtc: RTC handle
00756   * @param  sAlarm: Pointer to Alarm structure
00757   * @param  Format: Specifies the format of the entered parameters.
00758   *          This parameter can be one of the following values:
00759   *             @arg RTC_FORMAT_BIN: Binary data format
00760   *             @arg RTC_FORMAT_BCD: BCD data format
00761   * @retval HAL status
00762   */
00763 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00764 {
00765   uint32_t tickstart = 0;
00766   uint32_t tmpreg = 0, subsecondtmpreg = 0;
00767
00768   /* Check the parameters */
00769   assert_param(IS_RTC_FORMAT(Format));
00770   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00771   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
00772   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
00773   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
00774   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
00775
00776   /* Process Locked */
00777   __HAL_LOCK(hrtc);
00778
00779   hrtc->State = HAL_RTC_STATE_BUSY;
00780
00781   if(Format == RTC_FORMAT_BIN)
00782   {
00783     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00784     {
00785       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
00786       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00787     }
00788     else
00789     {
00790       sAlarm->AlarmTime.TimeFormat = 0x00;
00791       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
00792     }
00793     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
00794     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
00795
00796     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00797     {
00798       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
00799     }
00800     else
00801     {
00802       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
00803     }
00804
00805     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
00806               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
00807               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
00808               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
00809               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
00810               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00811               ((uint32_t)sAlarm->AlarmMask));
00812   }
00813   else
00814   {
00815     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00816     {
00817       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
00818       assert_param(IS_RTC_HOUR12(tmpreg));
00819       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00820     }
00821     else
00822     {
00823       sAlarm->AlarmTime.TimeFormat = 0x00;
00824       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
00825     }
00826
00827     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
00828     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
00829
00830     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00831     {
00832       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
00833       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
00834     }
00835     else
00836     {
00837       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
00838       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
00839     }
00840
00841     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
00842               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
00843               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
00844               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
00845               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
00846               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00847               ((uint32_t)sAlarm->AlarmMask));
00848   }
00849
00850   /* Configure the Alarm A or Alarm B Sub Second registers */
00851   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
00852
00853   /* Disable the write protection for RTC registers */
00854   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00855
00856   /* Configure the Alarm register */
00857   if(sAlarm->Alarm == RTC_ALARM_A)
00858   {
00859     /* Disable the Alarm A interrupt */
00860     __HAL_RTC_ALARMA_DISABLE(hrtc);
00861
00862     /* In case of interrupt mode is used, the interrupt source must disabled */
00863     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
00864
00865     tickstart = HAL_GetTick();
00866     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
00867     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
00868     {
00869       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00870       {
00871         /* Enable the write protection for RTC registers */
00872         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00873
00874         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00875
00876         /* Process Unlocked */
00877         __HAL_UNLOCK(hrtc);
00878
00879         return HAL_TIMEOUT;
00880       }
00881     }
00882
00883     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
00884     /* Configure the Alarm A Sub Second register */
00885     hrtc->Instance->ALRMASSR = subsecondtmpreg;
00886     /* Configure the Alarm state: Enable Alarm */
00887     __HAL_RTC_ALARMA_ENABLE(hrtc);
00888   }
00889   else
00890   {
00891     /* Disable the Alarm B interrupt */
00892     __HAL_RTC_ALARMB_DISABLE(hrtc);
00893
00894     /* In case of interrupt mode is used, the interrupt source must disabled */
00895     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
00896
00897     tickstart = HAL_GetTick();
00898     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
00899     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
00900     {
00901       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00902       {
00903         /* Enable the write protection for RTC registers */
00904         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00905
00906         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00907
00908         /* Process Unlocked */
00909         __HAL_UNLOCK(hrtc);
00910
00911         return HAL_TIMEOUT;
00912       }
00913     }
00914
00915     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
00916     /* Configure the Alarm B Sub Second register */
00917     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
00918     /* Configure the Alarm state: Enable Alarm */
00919     __HAL_RTC_ALARMB_ENABLE(hrtc);
00920   }
00921
00922   /* Enable the write protection for RTC registers */
00923   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00924
00925   /* Change RTC state */
00926   hrtc->State = HAL_RTC_STATE_READY;
00927
00928   /* Process Unlocked */
00929   __HAL_UNLOCK(hrtc);
00930
00931   return HAL_OK;
00932 }
00933
00934 /**
00935   * @brief  Set the specified RTC Alarm with Interrupt.
00936   * @param  hrtc: RTC handle
00937   * @param  sAlarm: Pointer to Alarm structure
00938   * @param  Format: Specifies the format of the entered parameters.
00939   *          This parameter can be one of the following values:
00940   *             @arg RTC_FORMAT_BIN: Binary data format
00941   *             @arg RTC_FORMAT_BCD: BCD data format
00942   * @note   The Alarm register can only be written when the corresponding Alarm
00943   *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
00944   * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
00945   * @retval HAL status
00946   */
00947 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00948 {
00949   uint32_t tickstart = 0;
00950   uint32_t tmpreg = 0, subsecondtmpreg = 0;
00951
00952   /* Check the parameters */
00953   assert_param(IS_RTC_FORMAT(Format));
00954   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00955   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
00956   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
00957   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
00958   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
00959
00960   /* Process Locked */
00961   __HAL_LOCK(hrtc);
00962
00963   hrtc->State = HAL_RTC_STATE_BUSY;
00964
00965   if(Format == RTC_FORMAT_BIN)
00966   {
00967     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00968     {
00969       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
00970       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
00971     }
00972     else
00973     {
00974       sAlarm->AlarmTime.TimeFormat = 0x00;
00975       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
00976     }
00977     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
00978     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
00979
00980     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
00981     {
00982       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
00983     }
00984     else
00985     {
00986       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
00987     }
00988     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
00989               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
00990               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
00991               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
00992               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
00993               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
00994               ((uint32_t)sAlarm->AlarmMask));
00995   }
00996   else
00997   {
00998     if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
00999     {
01000       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01001       assert_param(IS_RTC_HOUR12(tmpreg));
01002       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01003     }
01004     else
01005     {
01006       sAlarm->AlarmTime.TimeFormat = 0x00;
01007       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01008     }
01009
01010     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01011     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01012
01013     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01014     {
01015       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01016       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
01017     }
01018     else
01019     {
01020       tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01021       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
01022     }
01023     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
01024               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
01025               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
01026               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
01027               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
01028               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01029               ((uint32_t)sAlarm->AlarmMask));
01030   }
01031   /* Configure the Alarm A or Alarm B Sub Second registers */
01032   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01033
01034   /* Disable the write protection for RTC registers */
01035   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01036
01037   /* Configure the Alarm register */
01038   if(sAlarm->Alarm == RTC_ALARM_A)
01039   {
01040     /* Disable the Alarm A interrupt */
01041     __HAL_RTC_ALARMA_DISABLE(hrtc);
01042
01043     /* Clear flag alarm A */
01044     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01045
01046     tickstart = HAL_GetTick();
01047     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01048     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
01049     {
01050       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01051       {
01052         /* Enable the write protection for RTC registers */
01053         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01054
01055         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01056
01057         /* Process Unlocked */
01058         __HAL_UNLOCK(hrtc);
01059
01060         return HAL_TIMEOUT;
01061       }
01062     }
01063
01064     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01065     /* Configure the Alarm A Sub Second register */
01066     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01067     /* Configure the Alarm state: Enable Alarm */
01068     __HAL_RTC_ALARMA_ENABLE(hrtc);
01069     /* Configure the Alarm interrupt */
01070     __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
01071   }
01072   else
01073   {
01074     /* Disable the Alarm B interrupt */
01075     __HAL_RTC_ALARMB_DISABLE(hrtc);
01076
01077     /* Clear flag alarm B */
01078     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01079
01080     tickstart = HAL_GetTick();
01081     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01082     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
01083     {
01084       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01085       {
01086         /* Enable the write protection for RTC registers */
01087         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01088
01089         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01090
01091         /* Process Unlocked */
01092         __HAL_UNLOCK(hrtc);
01093
01094         return HAL_TIMEOUT;
01095       }
01096     }
01097
01098     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01099     /* Configure the Alarm B Sub Second register */
01100     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01101     /* Configure the Alarm state: Enable Alarm */
01102     __HAL_RTC_ALARMB_ENABLE(hrtc);
01103     /* Configure the Alarm interrupt */
01104     __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
01105   }
01106
01107   /* RTC Alarm Interrupt Configuration: EXTI configuration */
01108   __HAL_RTC_ALARM_EXTI_ENABLE_IT();
01109
01110   __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
01111
01112   /* Enable the write protection for RTC registers */
01113   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01114
01115   hrtc->State = HAL_RTC_STATE_READY;
01116
01117   /* Process Unlocked */
01118   __HAL_UNLOCK(hrtc);
01119
01120   return HAL_OK;
01121 }
01122
01123 /**
01124   * @brief  Deactivate the specified RTC Alarm.
01125   * @param  hrtc: RTC handle
01126   * @param  Alarm: Specifies the Alarm.
01127   *          This parameter can be one of the following values:
01128   *            @arg RTC_ALARM_A:  AlarmA
01129   *            @arg RTC_ALARM_B:  AlarmB
01130   * @retval HAL status
01131   */
01132 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
01133 {
01134   uint32_t tickstart = 0;
01135
01136   /* Check the parameters */
01137   assert_param(IS_RTC_ALARM(Alarm));
01138
01139   /* Process Locked */
01140   __HAL_LOCK(hrtc);
01141
01142   hrtc->State = HAL_RTC_STATE_BUSY;
01143
01144   /* Disable the write protection for RTC registers */
01145   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01146
01147   if(Alarm == RTC_ALARM_A)
01148   {
01149     /* AlarmA */
01150     __HAL_RTC_ALARMA_DISABLE(hrtc);
01151
01152     /* In case of interrupt mode is used, the interrupt source must disabled */
01153     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01154
01155     tickstart = HAL_GetTick();
01156
01157     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01158     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
01159     {
01160       if( (HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
01161       {
01162         /* Enable the write protection for RTC registers */
01163         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01164
01165         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01166
01167         /* Process Unlocked */
01168         __HAL_UNLOCK(hrtc);
01169
01170         return HAL_TIMEOUT;
01171       }
01172     }
01173   }
01174   else
01175   {
01176     /* AlarmB */
01177     __HAL_RTC_ALARMB_DISABLE(hrtc);
01178
01179     /* In case of interrupt mode is used, the interrupt source must disabled */
01180     __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
01181
01182     tickstart = HAL_GetTick();
01183
01184     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01185     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
01186     {
01187       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01188       {
01189         /* Enable the write protection for RTC registers */
01190         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01191
01192         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01193
01194         /* Process Unlocked */
01195         __HAL_UNLOCK(hrtc);
01196
01197         return HAL_TIMEOUT;
01198       }
01199     }
01200   }
01201   /* Enable the write protection for RTC registers */
01202   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01203
01204   hrtc->State = HAL_RTC_STATE_READY;
01205
01206   /* Process Unlocked */
01207   __HAL_UNLOCK(hrtc);
01208
01209   return HAL_OK;
01210 }
01211
01212 /**
01213   * @brief  Get the RTC Alarm value and masks.
01214   * @param  hrtc: RTC handle
01215   * @param  sAlarm: Pointer to Date structure
01216   * @param  Alarm: Specifies the Alarm.
01217   *          This parameter can be one of the following values:
01218   *             @arg RTC_ALARM_A: AlarmA
01219   *             @arg RTC_ALARM_B: AlarmB
01220   * @param  Format: Specifies the format of the entered parameters.
01221   *          This parameter can be one of the following values:
01222   *             @arg RTC_FORMAT_BIN: Binary data format
01223   *             @arg RTC_FORMAT_BCD: BCD data format
01224   * @retval HAL status
01225   */
01226 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
01227 {
01228   uint32_t tmpreg = 0, subsecondtmpreg = 0;
01229
01230   /* Check the parameters */
01231   assert_param(IS_RTC_FORMAT(Format));
01232   assert_param(IS_RTC_ALARM(Alarm));
01233
01234   if(Alarm == RTC_ALARM_A)
01235   {
01236     /* AlarmA */
01237     sAlarm->Alarm = RTC_ALARM_A;
01238
01239     tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
01240     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
01241   }
01242   else
01243   {
01244     sAlarm->Alarm = RTC_ALARM_B;
01245
01246     tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
01247     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
01248   }
01249
01250   /* Fill the structure with the read parameters */
01251   /* ALRMAR/ALRMBR registers have same mapping)  */
01252   sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
01253   sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
01254   sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
01255   sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
01256   sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01257   sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
01258   sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
01259   sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01260
01261   if(Format == RTC_FORMAT_BIN)
01262   {
01263     sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01264     sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
01265     sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
01266     sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01267   }
01268
01269   return HAL_OK;
01270 }
01271
01272 /**
01273   * @brief  Handle Alarm interrupt request.
01274   * @param  hrtc: RTC handle
01275   * @retval None
01276   */
01277 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
01278 {
01279   /* Get the AlarmA interrupt source enable status */
01280   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
01281   {
01282     /* Get the pending status of the AlarmA Interrupt */
01283     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
01284     {
01285       /* AlarmA callback */
01286       HAL_RTC_AlarmAEventCallback(hrtc);
01287
01288       /* Clear the AlarmA interrupt pending bit */
01289       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01290     }
01291   }
01292
01293   /* Get the AlarmB interrupt source enable status */
01294   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET)
01295   {
01296     /* Get the pending status of the AlarmB Interrupt */
01297     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)
01298     {
01299       /* AlarmB callback */
01300       HAL_RTCEx_AlarmBEventCallback(hrtc);
01301
01302       /* Clear the AlarmB interrupt pending bit */
01303       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01304     }
01305   }
01306
01307   /* Clear the EXTI's line Flag for RTC Alarm */
01308   __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
01309
01310   /* Change RTC state */
01311   hrtc->State = HAL_RTC_STATE_READY;
01312 }
01313
01314 /**
01315   * @brief  Alarm A callback.
01316   * @param  hrtc: RTC handle
01317   * @retval None
01318   */
01319 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
01320 {
01321   /* Prevent unused argument(s) compilation warning */
01322   UNUSED(hrtc);
01323
01324   /* NOTE : This function should not be modified, when the callback is needed,
01325             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
01326    */
01327 }
01328
01329 /**
01330   * @brief  Handle AlarmA Polling request.
01331   * @param  hrtc: RTC handle
01332   * @param  Timeout: Timeout duration
01333   * @retval HAL status
01334   */
01335 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01336 {
01337
01338   uint32_t tickstart = HAL_GetTick();
01339
01340   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
01341   {
01342     if(Timeout != HAL_MAX_DELAY)
01343     {
01344       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01345       {
01346         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01347         return HAL_TIMEOUT;
01348       }
01349     }
01350   }
01351
01352   /* Clear the Alarm interrupt pending bit */
01353   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01354
01355   /* Change RTC state */
01356   hrtc->State = HAL_RTC_STATE_READY;
01357
01358   return HAL_OK;
01359 }
01360
01361 /**
01362   * @}
01363   */
01364
01365 /** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
01366  *  @brief   Peripheral Control functions
01367  *
01368 @verbatim
01369  ===============================================================================
01370                      ##### Peripheral Control functions #####
01371  ===============================================================================
01372     [..]
01373     This subsection provides functions allowing to
01374       (+) Wait for RTC Time and Date Synchronization
01375
01376 @endverbatim
01377   * @{
01378   */
01379
01380 /**
01381   * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
01382   *         synchronized with RTC APB clock.
01383   * @note   The RTC Resynchronization mode is write protected, use the
01384   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01385   * @note   To read the calendar through the shadow registers after Calendar
01386   *         initialization, calendar update or after wakeup from low power modes
01387   *         the software must first clear the RSF flag.
01388   *         The software must then wait until it is set again before reading
01389   *         the calendar, which means that the calendar registers have been
01390   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
01391   * @param  hrtc: RTC handle
01392   * @retval HAL status
01393   */
01394 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
01395 {
01396   uint32_t tickstart = 0;
01397
01398   /* Clear RSF flag */
01399   hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
01400
01401   tickstart = HAL_GetTick();
01402
01403   /* Wait the registers to be synchronised */
01404   while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
01405   {
01406     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01407     {
01408       return HAL_TIMEOUT;
01409     }
01410   }
01411
01412   return HAL_OK;
01413 }
01414
01415 /**
01416   * @}
01417   */
01418
01419 /** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
01420  *  @brief   Peripheral State functions
01421  *
01422 @verbatim
01423  ===============================================================================
01424                      ##### Peripheral State functions #####
01425  ===============================================================================
01426     [..]
01427     This subsection provides functions allowing to
01428       (+) Get RTC state
01429
01430 @endverbatim
01431   * @{
01432   */
01433 /**
01434   * @brief  Return the RTC handle state.
01435   * @param  hrtc: RTC handle
01436   * @retval HAL state
01437   */
01438 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
01439 {
01440   /* Return RTC handle state */
01441   return hrtc->State;
01442 }
01443
01444 /**
01445   * @}
01446   */
01447
01448 /**
01449   * @}
01450   */
01451
01452 /** @defgroup RTC_Private_Functions RTC Private functions
01453   * @{
01454   */
01455 /**
01456   * @brief  Enter the RTC Initialization mode.
01457   * @note   The RTC Initialization mode is write protected, use the
01458   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01459   * @param  hrtc: RTC handle
01460   * @retval HAL status
01461   */
01462 HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
01463 {
01464   uint32_t tickstart = 0;
01465
01466   /* Check if the Initialization mode is set */
01467   if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
01468   {
01469     /* Set the Initialization mode */
01470     hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
01471
01472     tickstart = HAL_GetTick();
01473     /* Wait till RTC is in INIT state and if Time out is reached exit */
01474     while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
01475     {
01476       if((HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
01477       {
01478         return HAL_TIMEOUT;
01479       }
01480     }
01481   }
01482
01483   return HAL_OK;
01484 }
01485
01486
01487 /**
01488   * @brief  Convert a 2 digit decimal to BCD format.
01489   * @param  Value: Byte to be converted
01490   * @retval Converted byte
01491   */
01492 uint8_t RTC_ByteToBcd2(uint8_t Value)
01493 {
01494   uint32_t bcdhigh = 0;
01495
01496   while(Value >= 10)
01497   {
01498     bcdhigh++;
01499     Value -= 10;
01500   }
01501
01502   return  ((uint8_t)(bcdhigh << 4) | Value);
01503 }
01504
01505 /**
01506   * @brief  Convert from 2 digit BCD to Binary.
01507   * @param  Value: BCD value to be converted
01508   * @retval Converted word
01509   */
01510 uint8_t RTC_Bcd2ToByte(uint8_t Value)
01511 {
01512   uint32_t tmp = 0;
01513   tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
01514   return (tmp + (Value & (uint8_t)0x0F));
01515 }
01516
01517 /**
01518   * @}
01519   */
01520
01521 #endif /* HAL_RTC_MODULE_ENABLED */
01522 /**
01523   * @}
01524   */
01525
01526 /**
01527   * @}
01528   */
01529
01530 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rtc.h Source File

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stm32l4xx_hal_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rtc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of RTC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_RTC_H
00040 #define __STM32L4xx_HAL_RTC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RTC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RTC_Exported_Types RTC Exported Types
00059   * @{
00060   */
00061 /**
00062   * @brief  HAL State structures definition
00063   */
00064 typedef enum
00065 {
00066   HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
00067   HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
00068   HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */
00069   HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */
00070   HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */
00071
00072 }HAL_RTCStateTypeDef;
00073
00074 /**
00075   * @brief  RTC Configuration Structure definition
00076   */
00077 typedef struct
00078 {
00079   uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
00080                                  This parameter can be a value of @ref RTC_Hour_Formats */
00081
00082   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
00083                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
00084
00085   uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
00086                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
00087
00088   uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
00089                                  This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
00090
00091   uint32_t OutPutRemap;    /*!< Specifies the remap for RTC output.
00092                                  This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
00093
00094   uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
00095                                  This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
00096
00097   uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
00098                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
00099 }RTC_InitTypeDef;
00100
00101 /**
00102   * @brief  RTC Time structure definition
00103   */
00104 typedef struct
00105 {
00106   uint8_t Hours;            /*!< Specifies the RTC Time Hour.
00107                                  This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
00108                                  This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
00109
00110   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
00111                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00112
00113   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
00114                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00115
00116   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
00117                                  This parameter can be a value of @ref RTC_AM_PM_Definitions */
00118
00119   uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
00120                                  This parameter corresponds to a time unit range between [0-1] Second
00121                                  with [1 Sec / SecondFraction +1] granularity */
00122
00123   uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
00124                                  corresponding to Synchronous pre-scaler factor value (PREDIV_S)
00125                                  This parameter corresponds to a time unit range between [0-1] Second
00126                                  with [1 Sec / SecondFraction +1] granularity.
00127                                  This field will be used only by HAL_RTC_GetTime function */
00128
00129   uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
00130                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
00131
00132   uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
00133                                  in CR register to store the operation.
00134                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
00135 }RTC_TimeTypeDef;
00136
00137 /**
00138   * @brief  RTC Date structure definition
00139   */
00140 typedef struct
00141 {
00142   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00143                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
00144
00145   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
00146                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
00147
00148   uint8_t Date;     /*!< Specifies the RTC Date.
00149                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00150
00151   uint8_t Year;     /*!< Specifies the RTC Date Year.
00152                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
00153
00154 }RTC_DateTypeDef;
00155
00156 /**
00157   * @brief  RTC Alarm structure definition
00158   */
00159 typedef struct
00160 {
00161   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
00162
00163   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00164                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
00165
00166   uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
00167                                       This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
00168
00169   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
00170                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
00171
00172   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
00173                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
00174                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
00175
00176   uint32_t Alarm;                /*!< Specifies the alarm .
00177                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
00178 }RTC_AlarmTypeDef;
00179
00180 /**
00181   * @brief  Time Handle Structure definition
00182   */
00183 typedef struct
00184 {
00185   RTC_TypeDef               *Instance;  /*!< Register base address    */
00186
00187   RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
00188
00189   HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
00190
00191   __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
00192
00193 }RTC_HandleTypeDef;
00194
00195 /**
00196   * @}
00197   */
00198
00199 /* Exported constants --------------------------------------------------------*/
00200 /** @defgroup RTC_Exported_Constants RTC Exported Constants
00201   * @{
00202   */
00203
00204 /** @defgroup RTC_Hour_Formats RTC Hour Formats
00205   * @{
00206   */
00207 #define RTC_HOURFORMAT_24              ((uint32_t)0x00000000)
00208 #define RTC_HOURFORMAT_12              ((uint32_t)0x00000040)
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
00214   * @{
00215   */
00216 #define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000)
00217 #define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000)
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
00223   * @{
00224   */
00225 #define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000)
00226 #define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)RTC_OR_ALARMOUTTYPE)
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
00232   * @{
00233   */
00234 #define RTC_OUTPUT_REMAP_NONE          ((uint32_t)0x00000000)
00235 #define RTC_OUTPUT_REMAP_POS1          ((uint32_t)RTC_OR_OUT_RMP)
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
00241   * @{
00242   */
00243 #define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
00244 #define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
00250   * @{
00251   */
00252 #define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000)
00253 #define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000)
00254 #define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000)
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
00260   * @{
00261   */
00262 #define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000)
00263 #define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000)
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
00269   * @{
00270   */
00271 #define RTC_FORMAT_BIN                  ((uint32_t)0x000000000)
00272 #define RTC_FORMAT_BCD                  ((uint32_t)0x000000001)
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
00278   * @{
00279   */
00280
00281 /* Coded in BCD format */
00282 #define RTC_MONTH_JANUARY              ((uint8_t)0x01)
00283 #define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
00284 #define RTC_MONTH_MARCH                ((uint8_t)0x03)
00285 #define RTC_MONTH_APRIL                ((uint8_t)0x04)
00286 #define RTC_MONTH_MAY                  ((uint8_t)0x05)
00287 #define RTC_MONTH_JUNE                 ((uint8_t)0x06)
00288 #define RTC_MONTH_JULY                 ((uint8_t)0x07)
00289 #define RTC_MONTH_AUGUST               ((uint8_t)0x08)
00290 #define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
00291 #define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
00292 #define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
00293 #define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
00299   * @{
00300   */
00301 #define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
00302 #define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
00303 #define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
00304 #define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
00305 #define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
00306 #define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
00307 #define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
00313   * @{
00314   */
00315 #define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000)
00316 #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000)
00317 /**
00318   * @}
00319   */
00320
00321
00322 /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
00323   * @{
00324   */
00325 #define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000)
00326 #define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
00327 #define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
00328 #define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
00329 #define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
00330 #define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080)
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
00336   * @{
00337   */
00338 #define RTC_ALARM_A                       RTC_CR_ALRAE
00339 #define RTC_ALARM_B                       RTC_CR_ALRBE
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
00345   * @{
00346   */
00347 #define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000)  /*!< All Alarm SS fields are masked.
00348                                                                         There is no comparison on sub seconds
00349                                                                         for Alarm */
00350 #define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000)  /*!< SS[14:1] are don't care in Alarm
00351                                                                         comparison. Only SS[0] is compared.    */
00352 #define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000)  /*!< SS[14:2] are don't care in Alarm
00353                                                                         comparison. Only SS[1:0] are compared  */
00354 #define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000)  /*!< SS[14:3] are don't care in Alarm
00355                                                                         comparison. Only SS[2:0] are compared  */
00356 #define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000)  /*!< SS[14:4] are don't care in Alarm
00357                                                                         comparison. Only SS[3:0] are compared  */
00358 #define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000)  /*!< SS[14:5] are don't care in Alarm
00359                                                                         comparison. Only SS[4:0] are compared  */
00360 #define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000)  /*!< SS[14:6] are don't care in Alarm
00361                                                                         comparison. Only SS[5:0] are compared  */
00362 #define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000)  /*!< SS[14:7] are don't care in Alarm
00363                                                                         comparison. Only SS[6:0] are compared  */
00364 #define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000)  /*!< SS[14:8] are don't care in Alarm
00365                                                                         comparison. Only SS[7:0] are compared  */
00366 #define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000)  /*!< SS[14:9] are don't care in Alarm
00367                                                                         comparison. Only SS[8:0] are compared  */
00368 #define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000)  /*!< SS[14:10] are don't care in Alarm
00369                                                                         comparison. Only SS[9:0] are compared  */
00370 #define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000)  /*!< SS[14:11] are don't care in Alarm
00371                                                                         comparison. Only SS[10:0] are compared */
00372 #define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000)  /*!< SS[14:12] are don't care in Alarm
00373                                                                         comparison. Only SS[11:0] are compared */
00374 #define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000)  /*!< SS[14:13] are don't care in Alarm
00375                                                                         comparison. Only SS[12:0] are compared */
00376 #define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000)  /*!< SS[14] is don't care in Alarm
00377                                                                         comparison. Only SS[13:0] are compared */
00378 #define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000)  /*!< SS[14:0] are compared and must match
00379                                                                         to activate alarm. */
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
00385   * @{
00386   */
00387 #define RTC_IT_TS                         ((uint32_t)RTC_CR_TSIE)        /*!< Enable Timestamp Interrupt    */
00388 #define RTC_IT_WUT                        ((uint32_t)RTC_CR_WUTIE)       /*!< Enable Wakeup timer Interrupt */
00389 #define RTC_IT_ALRA                       ((uint32_t)RTC_CR_ALRAIE)      /*!< Enable Alarm A Interrupt      */
00390 #define RTC_IT_ALRB                       ((uint32_t)RTC_CR_ALRBIE)      /*!< Enable Alarm B Interrupt      */
00391 #define RTC_IT_TAMP                       ((uint32_t)RTC_TAMPCR_TAMPIE)  /*!< Enable all Tamper Interrupt   */
00392 #define RTC_IT_TAMP1                      ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt     */
00393 #define RTC_IT_TAMP2                      ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt     */
00394 #define RTC_IT_TAMP3                      ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt     */
00395 /**
00396   * @}
00397   */
00398
00399 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
00400   * @{
00401   */
00402 #define RTC_FLAG_RECALPF                  ((uint32_t)RTC_ISR_RECALPF)
00403 #define RTC_FLAG_TAMP3F                   ((uint32_t)RTC_ISR_TAMP3F)
00404 #define RTC_FLAG_TAMP2F                   ((uint32_t)RTC_ISR_TAMP2F)
00405 #define RTC_FLAG_TAMP1F                   ((uint32_t)RTC_ISR_TAMP1F)
00406 #define RTC_FLAG_TSOVF                    ((uint32_t)RTC_ISR_TSOVF)
00407 #define RTC_FLAG_TSF                      ((uint32_t)RTC_ISR_TSF)
00408 #define RTC_FLAG_ITSF                     ((uint32_t)RTC_ISR_ITSF)
00409 #define RTC_FLAG_WUTF                     ((uint32_t)RTC_ISR_WUTF)
00410 #define RTC_FLAG_ALRBF                    ((uint32_t)RTC_ISR_ALRBF)
00411 #define RTC_FLAG_ALRAF                    ((uint32_t)RTC_ISR_ALRAF)
00412 #define RTC_FLAG_INITF                    ((uint32_t)RTC_ISR_INITF)
00413 #define RTC_FLAG_RSF                      ((uint32_t)RTC_ISR_RSF)
00414 #define RTC_FLAG_INITS                    ((uint32_t)RTC_ISR_INITS)
00415 #define RTC_FLAG_SHPF                     ((uint32_t)RTC_ISR_SHPF)
00416 #define RTC_FLAG_WUTWF                    ((uint32_t)RTC_ISR_WUTWF)
00417 #define RTC_FLAG_ALRBWF                   ((uint32_t)RTC_ISR_ALRBWF)
00418 #define RTC_FLAG_ALRAWF                   ((uint32_t)RTC_ISR_ALRAWF)
00419 /**
00420   * @}
00421   */
00422
00423 /**
00424   * @}
00425   */
00426
00427 /* Exported macros -----------------------------------------------------------*/
00428 /** @defgroup RTC_Exported_Macros RTC Exported Macros
00429   * @{
00430   */
00431
00432 /** @brief Reset RTC handle state.
00433   * @param  __HANDLE__: RTC handle.
00434   * @retval None
00435   */
00436 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
00437
00438 /**
00439   * @brief  Disable the write protection for RTC registers.
00440   * @param  __HANDLE__: specifies the RTC handle.
00441   * @retval None
00442   */
00443 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
00444                         do{                                       \
00445                             (__HANDLE__)->Instance->WPR = 0xCA;   \
00446                             (__HANDLE__)->Instance->WPR = 0x53;   \
00447                           } while(0)
00448
00449 /**
00450   * @brief  Enable the write protection for RTC registers.
00451   * @param  __HANDLE__: specifies the RTC handle.
00452   * @retval None
00453   */
00454 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
00455                         do{                                       \
00456                             (__HANDLE__)->Instance->WPR = 0xFF;   \
00457                           } while(0)
00458
00459
00460 /**
00461   * @brief  Enable the RTC ALARMA peripheral.
00462   * @param  __HANDLE__: specifies the RTC handle.
00463   * @retval None
00464   */
00465 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
00466
00467 /**
00468   * @brief  Disable the RTC ALARMA peripheral.
00469   * @param  __HANDLE__: specifies the RTC handle.
00470   * @retval None
00471   */
00472 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
00473
00474 /**
00475   * @brief  Enable the RTC ALARMB peripheral.
00476   * @param  __HANDLE__: specifies the RTC handle.
00477   * @retval None
00478   */
00479 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
00480
00481 /**
00482   * @brief  Disable the RTC ALARMB peripheral.
00483   * @param  __HANDLE__: specifies the RTC handle.
00484   * @retval None
00485   */
00486 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
00487
00488 /**
00489   * @brief  Enable the RTC Alarm interrupt.
00490   * @param  __HANDLE__: specifies the RTC handle.
00491   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
00492   *          This parameter can be any combination of the following values:
00493   *             @arg RTC_IT_ALRA: Alarm A interrupt
00494   *             @arg RTC_IT_ALRB: Alarm B interrupt
00495   * @retval None
00496   */
00497 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00498
00499 /**
00500   * @brief  Disable the RTC Alarm interrupt.
00501   * @param  __HANDLE__: specifies the RTC handle.
00502   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
00503   *         This parameter can be any combination of the following values:
00504   *            @arg RTC_IT_ALRA: Alarm A interrupt
00505   *            @arg RTC_IT_ALRB: Alarm B interrupt
00506   * @retval None
00507   */
00508 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00509
00510 /**
00511   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
00512   * @param  __HANDLE__: specifies the RTC handle.
00513   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
00514   *         This parameter can be:
00515   *            @arg RTC_IT_ALRA: Alarm A interrupt
00516   *            @arg RTC_IT_ALRB: Alarm B interrupt
00517   * @retval None
00518   */
00519 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
00520
00521 /**
00522   * @brief  Get the selected RTC Alarm's flag status.
00523   * @param  __HANDLE__: specifies the RTC handle.
00524   * @param  __FLAG__: specifies the RTC Alarm Flag sources to check.
00525   *         This parameter can be:
00526   *            @arg RTC_FLAG_ALRAF
00527   *            @arg RTC_FLAG_ALRBF
00528   *            @arg RTC_FLAG_ALRAWF
00529   *            @arg RTC_FLAG_ALRBWF
00530   * @retval None
00531   */
00532 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00533
00534 /**
00535   * @brief  Clear the RTC Alarm's pending flags.
00536   * @param  __HANDLE__: specifies the RTC handle.
00537   * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
00538   *          This parameter can be:
00539   *             @arg RTC_FLAG_ALRAF
00540   *             @arg RTC_FLAG_ALRBF
00541   * @retval None
00542   */
00543 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00544
00545 /**
00546   * @brief  Check whether the specified RTC Alarm interrupt is enabled or not.
00547   * @param  __HANDLE__: specifies the RTC handle.
00548   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
00549   *         This parameter can be:
00550   *            @arg RTC_IT_ALRA: Alarm A interrupt
00551   *            @arg RTC_IT_ALRB: Alarm B interrupt
00552   * @retval None
00553   */
00554 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00555
00556 /**
00557   * @brief  Enable interrupt on the RTC Alarm associated Exti line.
00558   * @retval None
00559   */
00560 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00561
00562 /**
00563   * @brief  Disable interrupt on the RTC Alarm associated Exti line.
00564   * @retval None
00565   */
00566 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00567
00568 /**
00569   * @brief  Enable event on the RTC Alarm associated Exti line.
00570   * @retval None
00571   */
00572 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00573
00574 /**
00575   * @brief  Disable event on the RTC Alarm associated Exti line.
00576   * @retval None
00577   */
00578 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00579
00580 /**
00581   * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
00582   * @retval None
00583   */
00584 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00585
00586 /**
00587   * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
00588   * @retval None
00589   */
00590 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00591
00592 /**
00593   * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
00594   * @retval None
00595   */
00596 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00597
00598 /**
00599   * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
00600   * @retval None
00601   */
00602 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00603
00604 /**
00605   * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
00606   * @retval None
00607   */
00608 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00609                                                              __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
00610                                                              __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
00611                                                            } while(0)
00612
00613 /**
00614   * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
00615   * @retval None
00616   */
00617 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
00618                                                              __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
00619                                                              __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
00620                                                            } while(0)
00621
00622 /**
00623   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
00624   * @retval Line Status.
00625   */
00626 #define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
00627
00628 /**
00629   * @brief Clear the RTC Alarm associated Exti line flag.
00630   * @retval None
00631   */
00632 #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
00633
00634 /**
00635   * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
00636   * @retval None
00637   */
00638 #define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
00639
00640 /**
00641   * @}
00642   */
00643
00644 /* Include RTC HAL Extended module */
00645 #include "stm32l4xx_hal_rtc_ex.h"
00646
00647 /* Exported functions --------------------------------------------------------*/
00648 /** @addtogroup RTC_Exported_Functions
00649   * @{
00650   */
00651
00652 /** @addtogroup RTC_Exported_Functions_Group1
00653   * @{
00654   */
00655 /* Initialization and de-initialization functions  ****************************/
00656 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
00657 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
00658 void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
00659 void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
00660 /**
00661   * @}
00662   */
00663
00664 /** @addtogroup RTC_Exported_Functions_Group2
00665   * @{
00666   */
00667 /* RTC Time and Date functions ************************************************/
00668 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00669 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00670 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00671 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00672 /**
00673   * @}
00674   */
00675
00676 /** @addtogroup RTC_Exported_Functions_Group3
00677   * @{
00678   */
00679 /* RTC Alarm functions ********************************************************/
00680 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00681 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00682 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
00683 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
00684 void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
00685 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00686 void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
00687 /**
00688   * @}
00689   */
00690
00691 /** @addtogroup RTC_Exported_Functions_Group4
00692   * @{
00693   */
00694 /* Peripheral Control functions ***********************************************/
00695 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
00696 /**
00697   * @}
00698   */
00699
00700 /** @addtogroup RTC_Exported_Functions_Group5
00701   * @{
00702   */
00703 /* Peripheral State functions *************************************************/
00704 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
00705
00706 /**
00707   * @}
00708   */
00709
00710 /**
00711   * @}
00712   */
00713
00714 /* Private types -------------------------------------------------------------*/
00715 /* Private variables ---------------------------------------------------------*/
00716 /* Private constants ---------------------------------------------------------*/
00717 /** @defgroup RTC_Private_Constants RTC Private Constants
00718   * @{
00719   */
00720 /* Masks Definition */
00721 #define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
00722 #define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F)
00723 #define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)
00724 #define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)
00725
00726 #define RTC_TIMEOUT_VALUE  1000
00727
00728 #define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the RTC Alarm event */
00729
00730 /**
00731   * @}
00732   */
00733
00734 /* Private macros ------------------------------------------------------------*/
00735 /** @defgroup RTC_Private_Macros RTC Private Macros
00736   * @{
00737   */
00738
00739 /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
00740   * @{
00741   */
00742
00743 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
00744                                         ((FORMAT) == RTC_HOURFORMAT_24))
00745
00746 #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
00747                                 ((POL) == RTC_OUTPUT_POLARITY_LOW))
00748
00749 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
00750                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
00751
00752 #define IS_RTC_OUTPUT_REMAP(REMAP)   (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
00753                                       ((REMAP) == RTC_OUTPUT_REMAP_POS1))
00754
00755 #define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
00756
00757 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
00758                                       ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
00759                                       ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
00760
00761 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
00762                                            ((OPERATION) == RTC_STOREOPERATION_SET))
00763
00764 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
00765
00766 #define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99)
00767
00768 #define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
00769
00770 #define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
00771
00772 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00773                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00774                                  ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00775                                  ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00776                                  ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00777                                  ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00778                                  ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00779
00780 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
00781
00782 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00783                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00784                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00785                                                     ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00786                                                     ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00787                                                     ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00788                                                     ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00789
00790 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
00791                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
00792
00793 #define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
00794
00795 #define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
00796
00797 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
00798
00799 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
00800                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
00801                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
00802                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
00803                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
00804                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
00805                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
00806                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
00807                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
00808                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
00809                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
00810                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
00811                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
00812                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
00813                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
00814                                               ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
00815
00816 #define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7F)
00817
00818 #define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFF)
00819
00820 #define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
00821
00822 #define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23)
00823
00824 #define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59)
00825
00826 #define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59)
00827
00828 /**
00829   * @}
00830   */
00831
00832 /**
00833   * @}
00834   */
00835
00836 /* Private functions ---------------------------------------------------------*/
00837 /** @addtogroup RTC_Private_Functions
00838   * @{
00839   */
00840
00841 HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
00842 uint8_t            RTC_ByteToBcd2(uint8_t Value);
00843 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
00844
00845 /**
00846   * @}
00847   */
00848
00849 /**
00850   * @}
00851   */
00852
00853 /**
00854   * @}
00855   */
00856
00857 #ifdef __cplusplus
00858 }
00859 #endif
00860
00861 #endif /* __STM32L4xx_HAL_RTC_H */
00862
00863 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rtc_ex.c Source File

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stm32l4xx_hal_rtc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rtc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Extended RTC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Real Time Clock (RTC) Extended peripheral:
00010   *           + RTC Time Stamp functions
00011   *           + RTC Tamper functions
00012   *           + RTC Wake-up functions
00013   *           + Extended Control functions
00014   *           + Extended RTC features functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                   ##### How to use this driver #####
00019   ==============================================================================
00020   [..]
00021     (+) Enable the RTC domain access.
00022     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00023         format using the HAL_RTC_Init() function.
00024
00025   *** RTC Wakeup configuration ***
00026   ================================
00027   [..]
00028     (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
00029         function. You can also configure the RTC Wakeup timer with interrupt mode
00030         using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00031     (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
00032         function.
00033
00034   *** Outputs configuration ***
00035   =============================
00036   [..]  The RTC has 2 different outputs:
00037     (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
00038         and WaKeUp signals.
00039         To output the selected RTC signal, use the HAL_RTC_Init() function.
00040     (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
00041         To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
00042     (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
00043         the RTC_OR register.
00044     (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
00045         automatically configured in output alternate function.
00046
00047   *** Smooth digital Calibration configuration ***
00048   ================================================
00049   [..]
00050     (+) Configure the RTC Original Digital Calibration Value and the corresponding
00051         calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
00052         function.
00053
00054   *** TimeStamp configuration ***
00055   ===============================
00056   [..]
00057     (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
00058         You can also configure the RTC TimeStamp with interrupt mode using the
00059         HAL_RTCEx_SetTimeStamp_IT() function.
00060     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00061         function.
00062
00063   *** Internal TimeStamp configuration ***
00064   ===============================
00065   [..]
00066     (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
00067         User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
00068     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00069         function.
00070
00071   *** Tamper configuration ***
00072   ============================
00073   [..]
00074     (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
00075         or Level according to the Tamper filter (if equal to 0 Edge else Level)
00076         value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
00077         Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
00078         with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
00079     (+) The default configuration of the Tamper erases the backup registers. To avoid
00080         erase, enable the NoErase field on the RTC_TAMPCR register.
00081
00082   *** Backup Data Registers configuration ***
00083   ===========================================
00084   [..]
00085     (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
00086         function.
00087     (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
00088         function.
00089
00090    @endverbatim
00091   ******************************************************************************
00092   * @attention
00093   *
00094   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00095   *
00096   * Redistribution and use in source and binary forms, with or without modification,
00097   * are permitted provided that the following conditions are met:
00098   *   1. Redistributions of source code must retain the above copyright notice,
00099   *      this list of conditions and the following disclaimer.
00100   *   2. Redistributions in binary form must reproduce the above copyright notice,
00101   *      this list of conditions and the following disclaimer in the documentation
00102   *      and/or other materials provided with the distribution.
00103   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00104   *      may be used to endorse or promote products derived from this software
00105   *      without specific prior written permission.
00106   *
00107   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00108   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00109   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00110   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00111   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00112   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00113   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00114   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00115   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00116   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00117   *
00118   ******************************************************************************
00119   */
00120
00121 /* Includes ------------------------------------------------------------------*/
00122 #include "stm32l4xx_hal.h"
00123
00124 /** @addtogroup STM32L4xx_HAL_Driver
00125   * @{
00126   */
00127
00128 /** @defgroup RTCEx RTCEx
00129   * @brief RTC Extended HAL module driver
00130   * @{
00131   */
00132
00133 #ifdef HAL_RTC_MODULE_ENABLED
00134
00135 /* Private typedef -----------------------------------------------------------*/
00136 /* Private define ------------------------------------------------------------*/
00137 #if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
00138 #define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
00139                                        (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00140                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
00141                                        (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
00142                                        (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
00143                                        (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
00144 #elif defined(RTC_TAMPER1_SUPPORT)
00145 #define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
00146                                        (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00147                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
00148                                        (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
00149                                        (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
00150 #elif defined(RTC_TAMPER3_SUPPORT)
00151 #define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
00152                                        (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00153                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
00154                                        (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
00155                                        (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
00156 #else
00157 #define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
00158                                        (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00159                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
00160                                        (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
00161 #endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */
00162
00163 /* Private macro -------------------------------------------------------------*/
00164 /* Private variables ---------------------------------------------------------*/
00165 /* Private function prototypes -----------------------------------------------*/
00166 /* Exported functions --------------------------------------------------------*/
00167
00168 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
00169   * @{
00170   */
00171
00172
00173 /** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
00174  *  @brief   RTC TimeStamp and Tamper functions
00175   *
00176 @verbatim
00177  ===============================================================================
00178                  ##### RTC TimeStamp and Tamper functions #####
00179  ===============================================================================
00180
00181  [..] This section provide functions allowing to configure TimeStamp feature
00182
00183 @endverbatim
00184   * @{
00185   */
00186
00187 /**
00188   * @brief  Set TimeStamp.
00189   * @note   This API must be called before enabling the TimeStamp feature.
00190   * @param  hrtc: RTC handle
00191   * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
00192   *         activated.
00193   *          This parameter can be one of the following values:
00194   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00195   *                                        rising edge of the related pin.
00196   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00197   *                                         falling edge of the related pin.
00198   * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
00199   *          This parameter can be one of the following values:
00200   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00201   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00202   *               compatibility, this parameter is required.
00203   * @retval HAL status
00204   */
00205 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00206 {
00207   uint32_t tmpreg = 0;
00208
00209   /* Check the parameters */
00210   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00211   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00212
00213   /* Process Locked */
00214   __HAL_LOCK(hrtc);
00215
00216   hrtc->State = HAL_RTC_STATE_BUSY;
00217
00218   /* Get the RTC_CR register and clear the bits to be configured */
00219   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00220
00221   tmpreg|= TimeStampEdge;
00222
00223   /* Disable the write protection for RTC registers */
00224   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00225
00226   /* Configure the Time Stamp TSEDGE and Enable bits */
00227   hrtc->Instance->CR = (uint32_t)tmpreg;
00228
00229   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00230
00231   /* Enable the write protection for RTC registers */
00232   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00233
00234   /* Change RTC state */
00235   hrtc->State = HAL_RTC_STATE_READY;
00236
00237   /* Process Unlocked */
00238   __HAL_UNLOCK(hrtc);
00239
00240   return HAL_OK;
00241 }
00242
00243 /**
00244   * @brief  Set TimeStamp with Interrupt.
00245   * @param  hrtc: RTC handle
00246   * @note   This API must be called before enabling the TimeStamp feature.
00247   * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is
00248   *         activated.
00249   *          This parameter can be one of the following values:
00250   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00251   *                                        rising edge of the related pin.
00252   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00253   *                                         falling edge of the related pin.
00254   * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
00255   *          This parameter can be one of the following values:
00256   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00257   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00258   *               compatibility, this parameter is required.
00259   * @retval HAL status
00260   */
00261 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00262 {
00263   uint32_t tmpreg = 0;
00264
00265   /* Check the parameters */
00266   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00267   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00268
00269   /* Process Locked */
00270   __HAL_LOCK(hrtc);
00271
00272   hrtc->State = HAL_RTC_STATE_BUSY;
00273
00274   /* Get the RTC_CR register and clear the bits to be configured */
00275   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00276
00277   tmpreg |= TimeStampEdge;
00278
00279   /* Disable the write protection for RTC registers */
00280   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00281
00282   /* Configure the Time Stamp TSEDGE and Enable bits */
00283   hrtc->Instance->CR = (uint32_t)tmpreg;
00284
00285   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00286
00287   /* Enable IT timestamp */
00288   __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
00289
00290   /* RTC timestamp Interrupt Configuration: EXTI configuration */
00291   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00292
00293   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
00294
00295   /* Enable the write protection for RTC registers */
00296   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00297
00298   hrtc->State = HAL_RTC_STATE_READY;
00299
00300   /* Process Unlocked */
00301   __HAL_UNLOCK(hrtc);
00302
00303   return HAL_OK;
00304 }
00305
00306 /**
00307   * @brief  Deactivate TimeStamp.
00308   * @param  hrtc: RTC handle
00309   * @retval HAL status
00310   */
00311 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
00312 {
00313   uint32_t tmpreg = 0;
00314
00315   /* Process Locked */
00316   __HAL_LOCK(hrtc);
00317
00318   hrtc->State = HAL_RTC_STATE_BUSY;
00319
00320   /* Disable the write protection for RTC registers */
00321   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00322
00323   /* In case of interrupt mode is used, the interrupt source must disabled */
00324   __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
00325
00326   /* Get the RTC_CR register and clear the bits to be configured */
00327   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00328
00329   /* Configure the Time Stamp TSEDGE and Enable bits */
00330   hrtc->Instance->CR = (uint32_t)tmpreg;
00331
00332   /* Enable the write protection for RTC registers */
00333   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00334
00335   hrtc->State = HAL_RTC_STATE_READY;
00336
00337   /* Process Unlocked */
00338   __HAL_UNLOCK(hrtc);
00339
00340   return HAL_OK;
00341 }
00342
00343 /**
00344   * @brief  Set Internal TimeStamp.
00345   * @note   This API must be called before enabling the internal TimeStamp feature.
00346   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00347   *                the configuration information for RTC.
00348   * @retval HAL status
00349   */
00350 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00351 {
00352   /* Process Locked */
00353   __HAL_LOCK(hrtc);
00354
00355   hrtc->State = HAL_RTC_STATE_BUSY;
00356
00357   /* Disable the write protection for RTC registers */
00358   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00359
00360   /* Configure the internal Time Stamp Enable bits */
00361   __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);
00362
00363   /* Enable the write protection for RTC registers */
00364   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00365
00366   /* Change RTC state */
00367   hrtc->State = HAL_RTC_STATE_READY;
00368
00369   /* Process Unlocked */
00370   __HAL_UNLOCK(hrtc);
00371
00372   return HAL_OK;
00373 }
00374
00375 /**
00376   * @brief  Deactivate Internal TimeStamp.
00377   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00378   *                the configuration information for RTC.
00379   * @retval HAL status
00380   */
00381 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00382 {
00383   /* Process Locked */
00384   __HAL_LOCK(hrtc);
00385
00386   hrtc->State = HAL_RTC_STATE_BUSY;
00387
00388   /* Disable the write protection for RTC registers */
00389   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00390
00391   /* Configure the internal Time Stamp Enable bits */
00392   __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);
00393
00394   /* Enable the write protection for RTC registers */
00395   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00396
00397   hrtc->State = HAL_RTC_STATE_READY;
00398
00399   /* Process Unlocked */
00400   __HAL_UNLOCK(hrtc);
00401
00402   return HAL_OK;
00403 }
00404
00405 /**
00406   * @brief  Get the RTC TimeStamp value.
00407   * @param  hrtc: RTC handle
00408   * @param  sTimeStamp: Pointer to Time structure
00409   * @param  sTimeStampDate: Pointer to Date structure
00410   * @param  Format: specifies the format of the entered parameters.
00411   *          This parameter can be one of the following values:
00412   *             @arg RTC_FORMAT_BIN: Binary data format
00413   *             @arg RTC_FORMAT_BCD: BCD data format
00414   * @retval HAL status
00415   */
00416 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
00417 {
00418   uint32_t tmptime = 0, tmpdate = 0;
00419
00420   /* Check the parameters */
00421   assert_param(IS_RTC_FORMAT(Format));
00422
00423   /* Get the TimeStamp time and date registers values */
00424   tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
00425   tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
00426
00427   /* Fill the Time structure fields with the read parameters */
00428   sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
00429   sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
00430   sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
00431   sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
00432   sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
00433
00434   /* Fill the Date structure fields with the read parameters */
00435   sTimeStampDate->Year = 0;
00436   sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
00437   sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
00438   sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
00439
00440   /* Check the input parameters format */
00441   if(Format == RTC_FORMAT_BIN)
00442   {
00443     /* Convert the TimeStamp structure parameters to Binary format */
00444     sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
00445     sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
00446     sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
00447
00448     /* Convert the DateTimeStamp structure parameters to Binary format */
00449     sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
00450     sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
00451     sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
00452   }
00453
00454   /* Clear the TIMESTAMP Flags */
00455   __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF);
00456   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00457
00458   return HAL_OK;
00459 }
00460
00461 /**
00462   * @brief  Set Tamper.
00463   * @note   By calling this API we disable the tamper interrupt for all tampers.
00464   * @param  hrtc: RTC handle
00465   * @param  sTamper: Pointer to Tamper Structure.
00466   * @retval HAL status
00467   */
00468 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00469 {
00470   uint32_t tmpreg = 0;
00471
00472   /* Check the parameters */
00473   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00474   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00475   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00476   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00477   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00478   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00479   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00480   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00481   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00482
00483   /* Process Locked */
00484   __HAL_LOCK(hrtc);
00485
00486   hrtc->State = HAL_RTC_STATE_BUSY;
00487
00488   /* Configure the tamper trigger */
00489   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00490   {
00491     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
00492   }
00493
00494   if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00495   {
00496     sTamper->NoErase = 0;
00497 #if defined(RTC_TAMPER1_SUPPORT)
00498     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00499     {
00500       sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
00501     }
00502 #endif /* RTC_TAMPER1_SUPPORT */
00503     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00504     {
00505       sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
00506     }
00507 #if defined(RTC_TAMPER3_SUPPORT)
00508     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00509     {
00510       sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
00511     }
00512 #endif /* RTC_TAMPER3_SUPPORT */
00513   }
00514
00515   if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00516   {
00517     sTamper->MaskFlag = 0;
00518 #if defined(RTC_TAMPER1_SUPPORT)
00519     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00520     {
00521       sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
00522     }
00523 #endif /* RTC_TAMPER1_SUPPORT */
00524     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00525     {
00526       sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
00527     }
00528 #if defined(RTC_TAMPER3_SUPPORT)
00529     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00530     {
00531       sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
00532     }
00533 #endif /* RTC_TAMPER3_SUPPORT */
00534   }
00535
00536   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
00537             (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
00538             (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
00539
00540   hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
00541
00542   hrtc->Instance->TAMPCR |= tmpreg;
00543
00544   hrtc->State = HAL_RTC_STATE_READY;
00545
00546   /* Process Unlocked */
00547   __HAL_UNLOCK(hrtc);
00548
00549   return HAL_OK;
00550 }
00551
00552 /**
00553   * @brief  Set Tamper with interrupt.
00554   * @note   By calling this API we force the tamper interrupt for all tampers.
00555   * @param  hrtc: RTC handle
00556   * @param  sTamper: Pointer to RTC Tamper.
00557   * @retval HAL status
00558   */
00559 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00560 {
00561   uint32_t tmpreg = 0;
00562
00563   /* Check the parameters */
00564   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00565   assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));
00566   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00567   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00568   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00569   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00570   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00571   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00572   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00573   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00574
00575   /* Process Locked */
00576   __HAL_LOCK(hrtc);
00577
00578   hrtc->State = HAL_RTC_STATE_BUSY;
00579
00580   /* Configure the tamper trigger */
00581   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00582   {
00583     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
00584   }
00585
00586   if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00587   {
00588     sTamper->NoErase = 0;
00589 #if defined(RTC_TAMPER1_SUPPORT)
00590     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00591     {
00592       sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
00593     }
00594 #endif /* RTC_TAMPER1_SUPPORT */
00595     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00596     {
00597       sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
00598     }
00599 #if defined(RTC_TAMPER3_SUPPORT)
00600     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00601     {
00602       sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
00603     }
00604 #endif /* RTC_TAMPER3_SUPPORT */
00605   }
00606
00607   if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00608   {
00609     sTamper->MaskFlag = 0;
00610 #if defined(RTC_TAMPER1_SUPPORT)
00611     if((sTamper->Tamper & RTC_TAMPER_1) != 0)
00612     {
00613       sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
00614     }
00615 #endif /* RTC_TAMPER1_SUPPORT */
00616     if((sTamper->Tamper & RTC_TAMPER_2) != 0)
00617     {
00618       sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
00619     }
00620 #if defined(RTC_TAMPER3_SUPPORT)
00621     if((sTamper->Tamper & RTC_TAMPER_3) != 0)
00622     {
00623       sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
00624     }
00625 #endif /* RTC_TAMPER3_SUPPORT */
00626   }
00627
00628   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
00629             (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
00630             (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
00631
00632   hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
00633
00634   hrtc->Instance->TAMPCR |= tmpreg;
00635
00636   /* RTC Tamper Interrupt Configuration: EXTI configuration */
00637   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00638
00639   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
00640
00641   hrtc->State = HAL_RTC_STATE_READY;
00642
00643   /* Process Unlocked */
00644   __HAL_UNLOCK(hrtc);
00645
00646   return HAL_OK;
00647 }
00648
00649 /**
00650   * @brief  Deactivate Tamper.
00651   * @param  hrtc: RTC handle
00652   * @param  Tamper: Selected tamper pin.
00653   *          This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
00654   * @retval HAL status
00655   */
00656 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
00657 {
00658   assert_param(IS_RTC_TAMPER(Tamper));
00659
00660   /* Process Locked */
00661   __HAL_LOCK(hrtc);
00662
00663   hrtc->State = HAL_RTC_STATE_BUSY;
00664
00665   /* Disable the selected Tamper pin */
00666   hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper);
00667
00668 #if defined(RTC_TAMPER1_SUPPORT)
00669   if ((Tamper & RTC_TAMPER_1) != 0)
00670   {
00671     /* Disable the Tamper1 interrupt */
00672     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
00673   }
00674 #endif /* RTC_TAMPER1_SUPPORT */
00675   if ((Tamper & RTC_TAMPER_2) != 0)
00676   {
00677     /* Disable the Tamper2 interrupt */
00678     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2));
00679   }
00680 #if defined(RTC_TAMPER3_SUPPORT)
00681   if ((Tamper & RTC_TAMPER_3) != 0)
00682   {
00683     /* Disable the Tamper3 interrupt */
00684     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
00685   }
00686 #endif /* RTC_TAMPER3_SUPPORT */
00687
00688   hrtc->State = HAL_RTC_STATE_READY;
00689
00690   /* Process Unlocked */
00691   __HAL_UNLOCK(hrtc);
00692
00693   return HAL_OK;
00694 }
00695
00696 /**
00697   * @brief  Handle TimeStamp interrupt request.
00698   * @param  hrtc: RTC handle
00699   * @retval None
00700   */
00701 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
00702 {
00703   /* Get the TimeStamp interrupt source enable status */
00704   if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
00705   {
00706     /* Get the pending status of the TIMESTAMP Interrupt */
00707     if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
00708     {
00709       /* TIMESTAMP callback */
00710       HAL_RTCEx_TimeStampEventCallback(hrtc);
00711
00712       /* Clear the TIMESTAMP interrupt pending bit */
00713       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00714     }
00715   }
00716
00717 #if defined(RTC_TAMPER1_SUPPORT)
00718   /* Get the Tamper1 interrupts source enable status */
00719   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET)
00720   {
00721     /* Get the pending status of the Tamper1 Interrupt */
00722     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
00723     {
00724       /* Tamper1 callback */
00725       HAL_RTCEx_Tamper1EventCallback(hrtc);
00726
00727       /* Clear the Tamper1 interrupt pending bit */
00728       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
00729     }
00730   }
00731 #endif /* RTC_TAMPER1_SUPPORT */
00732
00733   /* Get the Tamper2 interrupts source enable status */
00734   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET)
00735   {
00736     /* Get the pending status of the Tamper2 Interrupt */
00737     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
00738     {
00739       /* Tamper2 callback */
00740       HAL_RTCEx_Tamper2EventCallback(hrtc);
00741
00742       /* Clear the Tamper2 interrupt pending bit */
00743       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
00744     }
00745   }
00746
00747 #if defined(RTC_TAMPER3_SUPPORT)
00748   /* Get the Tamper3 interrupts source enable status */
00749   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET)
00750   {
00751     /* Get the pending status of the Tamper3 Interrupt */
00752     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
00753     {
00754       /* Tamper3 callback */
00755       HAL_RTCEx_Tamper3EventCallback(hrtc);
00756
00757       /* Clear the Tamper3 interrupt pending bit */
00758       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
00759     }
00760   }
00761 #endif /* RTC_TAMPER3_SUPPORT */
00762
00763   /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
00764   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
00765
00766   /* Change RTC state */
00767   hrtc->State = HAL_RTC_STATE_READY;
00768 }
00769
00770 /**
00771   * @brief  TimeStamp callback.
00772   * @param  hrtc: RTC handle
00773   * @retval None
00774   */
00775 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
00776 {
00777   /* Prevent unused argument(s) compilation warning */
00778   UNUSED(hrtc);
00779
00780   /* NOTE : This function should not be modified, when the callback is needed,
00781             the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
00782   */
00783 }
00784
00785 #if defined(RTC_TAMPER1_SUPPORT)
00786 /**
00787   * @brief  Tamper 1 callback.
00788   * @param  hrtc: RTC handle
00789   * @retval None
00790   */
00791 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
00792 {
00793   /* Prevent unused argument(s) compilation warning */
00794   UNUSED(hrtc);
00795
00796   /* NOTE : This function should not be modified, when the callback is needed,
00797             the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
00798    */
00799 }
00800 #endif /* RTC_TAMPER1_SUPPORT */
00801
00802 /**
00803   * @brief  Tamper 2 callback.
00804   * @param  hrtc: RTC handle
00805   * @retval None
00806   */
00807 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
00808 {
00809   /* Prevent unused argument(s) compilation warning */
00810   UNUSED(hrtc);
00811
00812   /* NOTE : This function should not be modified, when the callback is needed,
00813             the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
00814    */
00815 }
00816
00817 #if defined(RTC_TAMPER3_SUPPORT)
00818 /**
00819   * @brief  Tamper 3 callback.
00820   * @param  hrtc: RTC handle
00821   * @retval None
00822   */
00823 __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
00824 {
00825   /* Prevent unused argument(s) compilation warning */
00826   UNUSED(hrtc);
00827
00828   /* NOTE : This function should not be modified, when the callback is needed,
00829             the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
00830    */
00831 }
00832 #endif /* RTC_TAMPER3_SUPPORT */
00833
00834 /**
00835   * @brief  Handle TimeStamp polling request.
00836   * @param  hrtc: RTC handle
00837   * @param  Timeout: Timeout duration
00838   * @retval HAL status
00839   */
00840 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00841 {
00842   uint32_t tickstart = HAL_GetTick();
00843
00844   while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
00845   {
00846     if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
00847     {
00848       /* Clear the TIMESTAMP OverRun Flag */
00849       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
00850
00851       /* Change TIMESTAMP state */
00852       hrtc->State = HAL_RTC_STATE_ERROR;
00853
00854       return HAL_ERROR;
00855     }
00856
00857     if(Timeout != HAL_MAX_DELAY)
00858     {
00859       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00860       {
00861         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00862         return HAL_TIMEOUT;
00863       }
00864     }
00865   }
00866
00867   /* Change RTC state */
00868   hrtc->State = HAL_RTC_STATE_READY;
00869
00870   return HAL_OK;
00871 }
00872
00873 #if defined(RTC_TAMPER1_SUPPORT)
00874 /**
00875   * @brief  Handle Tamper 1 Polling.
00876   * @param  hrtc: RTC handle
00877   * @param  Timeout: Timeout duration
00878   * @retval HAL status
00879   */
00880 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00881 {
00882   uint32_t tickstart = HAL_GetTick();
00883
00884   /* Get the status of the Interrupt */
00885   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
00886   {
00887     if(Timeout != HAL_MAX_DELAY)
00888     {
00889       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00890       {
00891         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00892         return HAL_TIMEOUT;
00893       }
00894     }
00895   }
00896
00897   /* Clear the Tamper Flag */
00898   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
00899
00900   /* Change RTC state */
00901   hrtc->State = HAL_RTC_STATE_READY;
00902
00903   return HAL_OK;
00904 }
00905 #endif /* RTC_TAMPER1_SUPPORT */
00906
00907 /**
00908   * @brief  Handle Tamper 2 Polling.
00909   * @param  hrtc: RTC handle
00910   * @param  Timeout: Timeout duration
00911   * @retval HAL status
00912   */
00913 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00914 {
00915   uint32_t tickstart = HAL_GetTick();
00916
00917   /* Get the status of the Interrupt */
00918   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
00919   {
00920     if(Timeout != HAL_MAX_DELAY)
00921     {
00922       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00923       {
00924         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00925         return HAL_TIMEOUT;
00926       }
00927     }
00928   }
00929
00930   /* Clear the Tamper Flag */
00931   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
00932
00933   /* Change RTC state */
00934   hrtc->State = HAL_RTC_STATE_READY;
00935
00936   return HAL_OK;
00937 }
00938
00939 #if defined(RTC_TAMPER3_SUPPORT)
00940 /**
00941   * @brief  Handle Tamper 3 Polling.
00942   * @param  hrtc: RTC handle
00943   * @param  Timeout: Timeout duration
00944   * @retval HAL status
00945   */
00946 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00947 {
00948   uint32_t tickstart = HAL_GetTick();
00949
00950   /* Get the status of the Interrupt */
00951   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)
00952   {
00953     if(Timeout != HAL_MAX_DELAY)
00954     {
00955       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00956       {
00957         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00958         return HAL_TIMEOUT;
00959       }
00960     }
00961   }
00962
00963   /* Clear the Tamper Flag */
00964   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
00965
00966   /* Change RTC state */
00967   hrtc->State = HAL_RTC_STATE_READY;
00968
00969   return HAL_OK;
00970 }
00971 #endif /* RTC_TAMPER3_SUPPORT */
00972
00973 /**
00974   * @}
00975   */
00976
00977 /** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
00978   * @brief    RTC Wake-up functions
00979   *
00980 @verbatim
00981  ===============================================================================
00982                         ##### RTC Wake-up functions #####
00983  ===============================================================================
00984
00985  [..] This section provide functions allowing to configure Wake-up feature
00986
00987 @endverbatim
00988   * @{
00989   */
00990
00991 /**
00992   * @brief  Set wake up timer.
00993   * @param  hrtc: RTC handle
00994   * @param  WakeUpCounter: Wake up counter
00995   * @param  WakeUpClock: Wake up clock
00996   * @retval HAL status
00997   */
00998 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
00999 {
01000   uint32_t tickstart = 0;
01001
01002   /* Check the parameters */
01003   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
01004   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
01005
01006   /* Process Locked */
01007   __HAL_LOCK(hrtc);
01008
01009   hrtc->State = HAL_RTC_STATE_BUSY;
01010
01011   /* Disable the write protection for RTC registers */
01012   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01013
01014   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
01015   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
01016   {
01017     tickstart = HAL_GetTick();
01018
01019     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
01020     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
01021     {
01022       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01023       {
01024         /* Enable the write protection for RTC registers */
01025         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01026
01027         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01028
01029         /* Process Unlocked */
01030         __HAL_UNLOCK(hrtc);
01031
01032         return HAL_TIMEOUT;
01033       }
01034     }
01035   }
01036
01037   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
01038
01039   tickstart = HAL_GetTick();
01040
01041   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01042   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
01043   {
01044     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01045     {
01046       /* Enable the write protection for RTC registers */
01047       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01048
01049       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01050
01051       /* Process Unlocked */
01052       __HAL_UNLOCK(hrtc);
01053
01054       return HAL_TIMEOUT;
01055     }
01056   }
01057
01058   /* Clear the Wakeup Timer clock source bits in CR register */
01059   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
01060
01061   /* Configure the clock source */
01062   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
01063
01064   /* Configure the Wakeup Timer counter */
01065   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
01066
01067    /* Enable the Wakeup Timer */
01068   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
01069
01070   /* Enable the write protection for RTC registers */
01071   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01072
01073   hrtc->State = HAL_RTC_STATE_READY;
01074
01075   /* Process Unlocked */
01076   __HAL_UNLOCK(hrtc);
01077
01078   return HAL_OK;
01079 }
01080
01081 /**
01082   * @brief  Set wake up timer with interrupt.
01083   * @param  hrtc: RTC handle
01084   * @param  WakeUpCounter: Wake up counter
01085   * @param  WakeUpClock: Wake up clock
01086   * @retval HAL status
01087   */
01088 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
01089 {
01090   uint32_t tickstart = 0;
01091
01092   /* Check the parameters */
01093   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
01094   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
01095
01096   /* Process Locked */
01097   __HAL_LOCK(hrtc);
01098
01099   hrtc->State = HAL_RTC_STATE_BUSY;
01100
01101   /* Disable the write protection for RTC registers */
01102   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01103
01104   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
01105   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
01106   {
01107     tickstart = HAL_GetTick();
01108
01109     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
01110     while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
01111     {
01112       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01113       {
01114         /* Enable the write protection for RTC registers */
01115         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01116
01117         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01118
01119         /* Process Unlocked */
01120         __HAL_UNLOCK(hrtc);
01121
01122         return HAL_TIMEOUT;
01123       }
01124     }
01125   }
01126
01127   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
01128
01129   tickstart = HAL_GetTick();
01130
01131   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01132   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
01133   {
01134     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01135     {
01136       /* Enable the write protection for RTC registers */
01137       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01138
01139       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01140
01141       /* Process Unlocked */
01142       __HAL_UNLOCK(hrtc);
01143
01144       return HAL_TIMEOUT;
01145     }
01146   }
01147
01148   /* Configure the Wakeup Timer counter */
01149   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
01150
01151   /* Clear the Wakeup Timer clock source bits in CR register */
01152   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
01153
01154   /* Configure the clock source */
01155   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
01156
01157   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
01158   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
01159
01160   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
01161
01162   /* Configure the Interrupt in the RTC_CR register */
01163   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
01164
01165   /* Enable the Wakeup Timer */
01166   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
01167
01168   /* Enable the write protection for RTC registers */
01169   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01170
01171   hrtc->State = HAL_RTC_STATE_READY;
01172
01173   /* Process Unlocked */
01174   __HAL_UNLOCK(hrtc);
01175
01176   return HAL_OK;
01177 }
01178
01179 /**
01180   * @brief  Deactivate wake up timer counter.
01181   * @param  hrtc: RTC handle
01182   * @retval HAL status
01183   */
01184 uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
01185 {
01186   uint32_t tickstart = 0;
01187
01188   /* Process Locked */
01189   __HAL_LOCK(hrtc);
01190
01191   hrtc->State = HAL_RTC_STATE_BUSY;
01192
01193   /* Disable the write protection for RTC registers */
01194   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01195
01196   /* Disable the Wakeup Timer */
01197   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
01198
01199   /* In case of interrupt mode is used, the interrupt source must disabled */
01200   __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
01201
01202   tickstart = HAL_GetTick();
01203   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01204   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
01205   {
01206     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01207     {
01208       /* Enable the write protection for RTC registers */
01209       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01210
01211       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01212
01213       /* Process Unlocked */
01214       __HAL_UNLOCK(hrtc);
01215
01216       return HAL_TIMEOUT;
01217     }
01218   }
01219
01220   /* Enable the write protection for RTC registers */
01221   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01222
01223   hrtc->State = HAL_RTC_STATE_READY;
01224
01225   /* Process Unlocked */
01226   __HAL_UNLOCK(hrtc);
01227
01228   return HAL_OK;
01229 }
01230
01231 /**
01232   * @brief  Get wake up timer counter.
01233   * @param  hrtc: RTC handle
01234   * @retval Counter value
01235   */
01236 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
01237 {
01238   /* Get the counter value */
01239   return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
01240 }
01241
01242 /**
01243   * @brief  Handle Wake Up Timer interrupt request.
01244   * @param  hrtc: RTC handle
01245   * @retval None
01246   */
01247 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
01248 {
01249   /* Get the pending status of the WAKEUPTIMER Interrupt */
01250   if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
01251   {
01252     /* WAKEUPTIMER callback */
01253     HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
01254
01255     /* Clear the WAKEUPTIMER interrupt pending bit */
01256     __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01257   }
01258
01259
01260   /* Clear the EXTI's line Flag for RTC WakeUpTimer */
01261   __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
01262
01263   /* Change RTC state */
01264   hrtc->State = HAL_RTC_STATE_READY;
01265 }
01266
01267 /**
01268   * @brief  Wake Up Timer callback.
01269   * @param  hrtc: RTC handle
01270   * @retval None
01271   */
01272 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
01273 {
01274   /* Prevent unused argument(s) compilation warning */
01275   UNUSED(hrtc);
01276
01277   /* NOTE : This function should not be modified, when the callback is needed,
01278             the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
01279    */
01280 }
01281
01282 /**
01283   * @brief  Handle Wake Up Timer Polling.
01284   * @param  hrtc: RTC handle
01285   * @param  Timeout: Timeout duration
01286   * @retval HAL status
01287   */
01288 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01289 {
01290   uint32_t tickstart = HAL_GetTick();
01291
01292   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
01293   {
01294     if(Timeout != HAL_MAX_DELAY)
01295     {
01296       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01297       {
01298         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01299
01300         return HAL_TIMEOUT;
01301       }
01302     }
01303   }
01304
01305   /* Clear the WAKEUPTIMER Flag */
01306   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01307
01308   /* Change RTC state */
01309   hrtc->State = HAL_RTC_STATE_READY;
01310
01311   return HAL_OK;
01312 }
01313
01314 /**
01315   * @}
01316   */
01317
01318
01319 /** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
01320   * @brief    Extended Peripheral Control functions
01321   *
01322 @verbatim
01323  ===============================================================================
01324               ##### Extended Peripheral Control functions #####
01325  ===============================================================================
01326     [..]
01327     This subsection provides functions allowing to
01328       (+) Write a data in a specified RTC Backup data register
01329       (+) Read a data in a specified RTC Backup data register
01330       (+) Set the Coarse calibration parameters.
01331       (+) Deactivate the Coarse calibration parameters
01332       (+) Set the Smooth calibration parameters.
01333       (+) Configure the Synchronization Shift Control Settings.
01334       (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01335       (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01336       (+) Enable the RTC reference clock detection.
01337       (+) Disable the RTC reference clock detection.
01338       (+) Enable the Bypass Shadow feature.
01339       (+) Disable the Bypass Shadow feature.
01340
01341 @endverbatim
01342   * @{
01343   */
01344
01345 /**
01346   * @brief  Write a data in a specified RTC Backup data register.
01347   * @param  hrtc: RTC handle
01348   * @param  BackupRegister: RTC Backup data Register number.
01349   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01350   *                                 specify the register.
01351   * @param  Data: Data to be written in the specified RTC Backup data register.
01352   * @retval None
01353   */
01354 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
01355 {
01356   uint32_t tmp = 0;
01357
01358   /* Check the parameters */
01359   assert_param(IS_RTC_BKP(BackupRegister));
01360
01361   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01362   tmp += (BackupRegister * 4);
01363
01364   /* Write the specified register */
01365   *(__IO uint32_t *)tmp = (uint32_t)Data;
01366 }
01367
01368 /**
01369   * @brief  Read data from the specified RTC Backup data Register.
01370   * @param  hrtc: RTC handle
01371   * @param  BackupRegister: RTC Backup data Register number.
01372   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01373   *                                 specify the register.
01374   * @retval Read value
01375   */
01376 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
01377 {
01378   uint32_t tmp = 0;
01379
01380   /* Check the parameters */
01381   assert_param(IS_RTC_BKP(BackupRegister));
01382
01383   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01384   tmp += (BackupRegister * 4);
01385
01386   /* Read the specified register */
01387   return (*(__IO uint32_t *)tmp);
01388 }
01389
01390 /**
01391   * @brief  Set the Smooth calibration parameters.
01392   * @param  hrtc: RTC handle
01393   * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
01394   *          This parameter can be can be one of the following values :
01395   *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
01396   *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
01397   *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
01398   * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
01399   *          This parameter can be one of the following values:
01400   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
01401   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
01402   * @param  SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
01403   *          This parameter can be one any value from 0 to 0x000001FF.
01404   * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
01405   *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
01406   *         SmoothCalibMinusPulsesValue must be equal to 0.
01407   * @retval HAL status
01408   */
01409 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
01410 {
01411   uint32_t tickstart = 0;
01412
01413   /* Check the parameters */
01414   assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
01415   assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
01416   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
01417
01418   /* Process Locked */
01419   __HAL_LOCK(hrtc);
01420
01421   hrtc->State = HAL_RTC_STATE_BUSY;
01422
01423   /* Disable the write protection for RTC registers */
01424   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01425
01426   /* check if a calibration is pending*/
01427   if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
01428   {
01429     tickstart = HAL_GetTick();
01430
01431     /* check if a calibration is pending*/
01432     while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
01433     {
01434       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01435       {
01436         /* Enable the write protection for RTC registers */
01437         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01438
01439         /* Change RTC state */
01440         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01441
01442         /* Process Unlocked */
01443         __HAL_UNLOCK(hrtc);
01444
01445         return HAL_TIMEOUT;
01446       }
01447     }
01448   }
01449
01450   /* Configure the Smooth calibration settings */
01451   hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
01452
01453   /* Enable the write protection for RTC registers */
01454   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01455
01456   /* Change RTC state */
01457   hrtc->State = HAL_RTC_STATE_READY;
01458
01459   /* Process Unlocked */
01460   __HAL_UNLOCK(hrtc);
01461
01462   return HAL_OK;
01463 }
01464
01465 /**
01466   * @brief  Configure the Synchronization Shift Control Settings.
01467   * @note   When REFCKON is set, firmware must not write to Shift control register.
01468   * @param  hrtc: RTC handle
01469   * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
01470   *          This parameter can be one of the following values :
01471   *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
01472   *             @arg RTC_SHIFTADD1S_RESET: No effect.
01473   * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
01474   *          This parameter can be one any value from 0 to 0x7FFF.
01475   * @retval HAL status
01476   */
01477 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
01478 {
01479   uint32_t tickstart = 0;
01480
01481   /* Check the parameters */
01482   assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
01483   assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
01484
01485   /* Process Locked */
01486   __HAL_LOCK(hrtc);
01487
01488   hrtc->State = HAL_RTC_STATE_BUSY;
01489
01490   /* Disable the write protection for RTC registers */
01491   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01492
01493     tickstart = HAL_GetTick();
01494
01495     /* Wait until the shift is completed*/
01496     while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
01497     {
01498       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01499       {
01500         /* Enable the write protection for RTC registers */
01501         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01502
01503         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01504
01505         /* Process Unlocked */
01506         __HAL_UNLOCK(hrtc);
01507
01508         return HAL_TIMEOUT;
01509       }
01510     }
01511
01512     /* Check if the reference clock detection is disabled */
01513     if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
01514     {
01515       /* Configure the Shift settings */
01516       hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
01517
01518       /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
01519       if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
01520       {
01521         if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01522         {
01523           /* Enable the write protection for RTC registers */
01524           __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01525
01526           hrtc->State = HAL_RTC_STATE_ERROR;
01527
01528           /* Process Unlocked */
01529           __HAL_UNLOCK(hrtc);
01530
01531           return HAL_ERROR;
01532         }
01533       }
01534     }
01535     else
01536     {
01537       /* Enable the write protection for RTC registers */
01538       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01539
01540       /* Change RTC state */
01541       hrtc->State = HAL_RTC_STATE_ERROR;
01542
01543       /* Process Unlocked */
01544       __HAL_UNLOCK(hrtc);
01545
01546       return HAL_ERROR;
01547     }
01548
01549   /* Enable the write protection for RTC registers */
01550   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01551
01552   /* Change RTC state */
01553   hrtc->State = HAL_RTC_STATE_READY;
01554
01555   /* Process Unlocked */
01556   __HAL_UNLOCK(hrtc);
01557
01558   return HAL_OK;
01559 }
01560
01561 /**
01562   * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01563   * @param  hrtc: RTC handle
01564   * @param  CalibOutput : Select the Calibration output Selection .
01565   *          This parameter can be one of the following values:
01566   *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
01567   *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
01568   * @retval HAL status
01569   */
01570 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
01571 {
01572   /* Check the parameters */
01573   assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
01574
01575   /* Process Locked */
01576   __HAL_LOCK(hrtc);
01577
01578   hrtc->State = HAL_RTC_STATE_BUSY;
01579
01580   /* Disable the write protection for RTC registers */
01581   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01582
01583   /* Clear flags before config */
01584   hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
01585
01586   /* Configure the RTC_CR register */
01587   hrtc->Instance->CR |= (uint32_t)CalibOutput;
01588
01589   __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
01590
01591   /* Enable the write protection for RTC registers */
01592   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01593
01594   /* Change RTC state */
01595   hrtc->State = HAL_RTC_STATE_READY;
01596
01597   /* Process Unlocked */
01598   __HAL_UNLOCK(hrtc);
01599
01600   return HAL_OK;
01601 }
01602
01603 /**
01604   * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01605   * @param  hrtc: RTC handle
01606   * @retval HAL status
01607   */
01608 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
01609 {
01610   /* Process Locked */
01611   __HAL_LOCK(hrtc);
01612
01613   hrtc->State = HAL_RTC_STATE_BUSY;
01614
01615   /* Disable the write protection for RTC registers */
01616   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01617
01618   __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
01619
01620   /* Enable the write protection for RTC registers */
01621   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01622
01623   /* Change RTC state */
01624   hrtc->State = HAL_RTC_STATE_READY;
01625
01626   /* Process Unlocked */
01627   __HAL_UNLOCK(hrtc);
01628
01629   return HAL_OK;
01630 }
01631
01632 /**
01633   * @brief  Enable the RTC reference clock detection.
01634   * @param  hrtc: RTC handle
01635   * @retval HAL status
01636   */
01637 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
01638 {
01639   /* Process Locked */
01640   __HAL_LOCK(hrtc);
01641
01642   hrtc->State = HAL_RTC_STATE_BUSY;
01643
01644   /* Disable the write protection for RTC registers */
01645   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01646
01647   /* Set Initialization mode */
01648   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01649   {
01650     /* Enable the write protection for RTC registers */
01651     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01652
01653     /* Set RTC state*/
01654     hrtc->State = HAL_RTC_STATE_ERROR;
01655
01656     /* Process Unlocked */
01657     __HAL_UNLOCK(hrtc);
01658
01659     return HAL_ERROR;
01660   }
01661   else
01662   {
01663     __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
01664
01665     /* Exit Initialization mode */
01666     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01667   }
01668
01669   /* Enable the write protection for RTC registers */
01670   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01671
01672    /* Change RTC state */
01673   hrtc->State = HAL_RTC_STATE_READY;
01674
01675   /* Process Unlocked */
01676   __HAL_UNLOCK(hrtc);
01677
01678   return HAL_OK;
01679 }
01680
01681 /**
01682   * @brief  Disable the RTC reference clock detection.
01683   * @param  hrtc: RTC handle
01684   * @retval HAL status
01685   */
01686 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
01687 {
01688   /* Process Locked */
01689   __HAL_LOCK(hrtc);
01690
01691   hrtc->State = HAL_RTC_STATE_BUSY;
01692
01693   /* Disable the write protection for RTC registers */
01694   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01695
01696   /* Set Initialization mode */
01697   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01698   {
01699     /* Enable the write protection for RTC registers */
01700     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01701
01702     /* Set RTC state*/
01703     hrtc->State = HAL_RTC_STATE_ERROR;
01704
01705     /* Process Unlocked */
01706     __HAL_UNLOCK(hrtc);
01707
01708     return HAL_ERROR;
01709   }
01710   else
01711   {
01712     __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
01713
01714     /* Exit Initialization mode */
01715     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01716   }
01717
01718   /* Enable the write protection for RTC registers */
01719   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01720
01721   /* Change RTC state */
01722   hrtc->State = HAL_RTC_STATE_READY;
01723
01724   /* Process Unlocked */
01725   __HAL_UNLOCK(hrtc);
01726
01727   return HAL_OK;
01728 }
01729
01730 /**
01731   * @brief  Enable the Bypass Shadow feature.
01732   * @param  hrtc: RTC handle
01733   * @note   When the Bypass Shadow is enabled the calendar value are taken
01734   *         directly from the Calendar counter.
01735   * @retval HAL status
01736   */
01737 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
01738 {
01739   /* Process Locked */
01740   __HAL_LOCK(hrtc);
01741
01742   hrtc->State = HAL_RTC_STATE_BUSY;
01743
01744   /* Disable the write protection for RTC registers */
01745   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01746
01747   /* Set the BYPSHAD bit */
01748   hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
01749
01750   /* Enable the write protection for RTC registers */
01751   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01752
01753   /* Change RTC state */
01754   hrtc->State = HAL_RTC_STATE_READY;
01755
01756   /* Process Unlocked */
01757   __HAL_UNLOCK(hrtc);
01758
01759   return HAL_OK;
01760 }
01761
01762 /**
01763   * @brief  Disable the Bypass Shadow feature.
01764   * @param  hrtc: RTC handle
01765   * @note   When the Bypass Shadow is enabled the calendar value are taken
01766   *         directly from the Calendar counter.
01767   * @retval HAL status
01768   */
01769 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
01770 {
01771   /* Process Locked */
01772   __HAL_LOCK(hrtc);
01773
01774   hrtc->State = HAL_RTC_STATE_BUSY;
01775
01776   /* Disable the write protection for RTC registers */
01777   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01778
01779   /* Reset the BYPSHAD bit */
01780   hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
01781
01782   /* Enable the write protection for RTC registers */
01783   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01784
01785   /* Change RTC state */
01786   hrtc->State = HAL_RTC_STATE_READY;
01787
01788   /* Process Unlocked */
01789   __HAL_UNLOCK(hrtc);
01790
01791   return HAL_OK;
01792 }
01793
01794 /**
01795   * @}
01796   */
01797
01798 /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
01799   * @brief    Extended features functions
01800   *
01801 @verbatim
01802  ===============================================================================
01803                  ##### Extended features functions #####
01804  ===============================================================================
01805     [..]  This section provides functions allowing to:
01806       (+) RTC Alarm B callback
01807       (+) RTC Poll for Alarm B request
01808
01809 @endverbatim
01810   * @{
01811   */
01812
01813 /**
01814   * @brief  Alarm B callback.
01815   * @param  hrtc: RTC handle
01816   * @retval None
01817   */
01818 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
01819 {
01820   /* Prevent unused argument(s) compilation warning */
01821   UNUSED(hrtc);
01822
01823   /* NOTE : This function should not be modified, when the callback is needed,
01824             the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
01825    */
01826 }
01827
01828 /**
01829   * @brief  Handle Alarm B Polling request.
01830   * @param  hrtc: RTC handle
01831   * @param  Timeout: Timeout duration
01832   * @retval HAL status
01833   */
01834 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01835 {
01836   uint32_t tickstart = HAL_GetTick();
01837
01838   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
01839   {
01840     if(Timeout != HAL_MAX_DELAY)
01841     {
01842       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01843       {
01844         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01845         return HAL_TIMEOUT;
01846       }
01847     }
01848   }
01849
01850   /* Clear the Alarm Flag */
01851   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01852
01853   /* Change RTC state */
01854   hrtc->State = HAL_RTC_STATE_READY;
01855
01856   return HAL_OK;
01857 }
01858
01859 /**
01860   * @}
01861   */
01862
01863 /**
01864   * @}
01865   */
01866
01867 #endif /* HAL_RTC_MODULE_ENABLED */
01868 /**
01869   * @}
01870   */
01871
01872 /**
01873   * @}
01874   */
01875
01876 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_rtc_ex.h Source File

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stm32l4xx_hal_rtc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rtc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of RTC HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_RTC_EX_H
00040 #define __STM32L4xx_HAL_RTC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RTCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup RTCEx_Exported_Types RTCEx Exported Types
00059   * @{
00060   */
00061 /**
00062   * @brief  RTC Tamper structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
00067                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
00068
00069   uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.
00070                                              This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */
00071
00072   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
00073                                              This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
00074
00075   uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
00076                                              This parameter can be a value of @ref  RTCEx_Tamper_EraseBackUp_Definitions */
00077
00078   uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.
00079                                              This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */
00080
00081   uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
00082                                              This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
00083
00084   uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
00085                                              This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
00086
00087   uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
00088                                              This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
00089
00090   uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
00091                                              This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
00092
00093   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00094                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
00095 }RTC_TamperTypeDef;
00096
00097 /**
00098   * @}
00099   */
00100
00101 /* Exported constants --------------------------------------------------------*/
00102 /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
00103   * @{
00104   */
00105
00106 /** @defgroup RTCEx_Output_selection_Definitions RTC Output Selection Definitions
00107   * @{
00108   */
00109 #define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000)
00110 #define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000)
00111 #define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000)
00112 #define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000)
00113 /**
00114   * @}
00115   */
00116
00117 /** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
00118   * @{
00119   */
00120 #define RTC_BKP_DR0                       ((uint32_t)0x00000000)
00121 #define RTC_BKP_DR1                       ((uint32_t)0x00000001)
00122 #define RTC_BKP_DR2                       ((uint32_t)0x00000002)
00123 #define RTC_BKP_DR3                       ((uint32_t)0x00000003)
00124 #define RTC_BKP_DR4                       ((uint32_t)0x00000004)
00125 #define RTC_BKP_DR5                       ((uint32_t)0x00000005)
00126 #define RTC_BKP_DR6                       ((uint32_t)0x00000006)
00127 #define RTC_BKP_DR7                       ((uint32_t)0x00000007)
00128 #define RTC_BKP_DR8                       ((uint32_t)0x00000008)
00129 #define RTC_BKP_DR9                       ((uint32_t)0x00000009)
00130 #define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
00131 #define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
00132 #define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
00133 #define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
00134 #define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
00135 #define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
00136 #define RTC_BKP_DR16                      ((uint32_t)0x00000010)
00137 #define RTC_BKP_DR17                      ((uint32_t)0x00000011)
00138 #define RTC_BKP_DR18                      ((uint32_t)0x00000012)
00139 #define RTC_BKP_DR19                      ((uint32_t)0x00000013)
00140 #define RTC_BKP_DR20                      ((uint32_t)0x00000014)
00141 #define RTC_BKP_DR21                      ((uint32_t)0x00000015)
00142 #define RTC_BKP_DR22                      ((uint32_t)0x00000016)
00143 #define RTC_BKP_DR23                      ((uint32_t)0x00000017)
00144 #define RTC_BKP_DR24                      ((uint32_t)0x00000018)
00145 #define RTC_BKP_DR25                      ((uint32_t)0x00000019)
00146 #define RTC_BKP_DR26                      ((uint32_t)0x0000001A)
00147 #define RTC_BKP_DR27                      ((uint32_t)0x0000001B)
00148 #define RTC_BKP_DR28                      ((uint32_t)0x0000001C)
00149 #define RTC_BKP_DR29                      ((uint32_t)0x0000001D)
00150 #define RTC_BKP_DR30                      ((uint32_t)0x0000001E)
00151 #define RTC_BKP_DR31                      ((uint32_t)0x0000001F)
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions
00157   * @{
00158   */
00159 #define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000)
00160 #define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008)
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
00166   * @{
00167   */
00168 #define RTC_TIMESTAMPPIN_DEFAULT          ((uint32_t)0x00000000)
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
00174   * @{
00175   */
00176 #if defined(RTC_TAMPER1_SUPPORT)
00177 #define RTC_TAMPER_1                       RTC_TAMPCR_TAMP1E
00178 #endif /* RTC_TAMPER1_SUPPORT */
00179 #define RTC_TAMPER_2                       RTC_TAMPCR_TAMP2E
00180 #if defined(RTC_TAMPER3_SUPPORT)
00181 #define RTC_TAMPER_3                       RTC_TAMPCR_TAMP3E
00182 #endif /* RTC_TAMPER3_SUPPORT */
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions
00188   * @{
00189   */
00190 #if defined(RTC_TAMPER1_SUPPORT)
00191 #define RTC_TAMPER1_INTERRUPT              RTC_TAMPCR_TAMP1IE
00192 #endif /* RTC_TAMPER1_SUPPORT */
00193 #define RTC_TAMPER2_INTERRUPT              RTC_TAMPCR_TAMP2IE
00194 #if defined(RTC_TAMPER3_SUPPORT)
00195 #define RTC_TAMPER3_INTERRUPT              RTC_TAMPCR_TAMP3IE
00196 #endif /* RTC_TAMPER3_SUPPORT */
00197 #define RTC_ALL_TAMPER_INTERRUPT           RTC_TAMPCR_TAMPIE
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
00203   * @{
00204   */
00205 #define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000)
00206 #define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002)
00207 #define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
00208 #define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions
00214 * @{
00215 */
00216 #define RTC_TAMPER_ERASE_BACKUP_ENABLE     ((uint32_t)0x00000000)
00217 #define RTC_TAMPER_ERASE_BACKUP_DISABLE    ((uint32_t)0x00020000)
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions
00223 * @{
00224 */
00225 #define RTC_TAMPERMASK_FLAG_DISABLE        ((uint32_t)0x00000000)
00226 #define RTC_TAMPERMASK_FLAG_ENABLE         ((uint32_t)0x00040000)
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
00232   * @{
00233   */
00234 #define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000)  /*!< Tamper filter is disabled */
00235
00236 #define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800)  /*!< Tamper is activated after 2
00237                                                                 consecutive samples at the active level */
00238 #define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000)  /*!< Tamper is activated after 4
00239                                                                 consecutive samples at the active level */
00240 #define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800)  /*!< Tamper is activated after 8
00241                                                                 consecutive samples at the active level. */
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
00247   * @{
00248   */
00249 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000)  /*!< Each of the tamper inputs are sampled
00250                                                                              with a frequency =  RTCCLK / 32768 */
00251 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100)  /*!< Each of the tamper inputs are sampled
00252                                                                              with a frequency =  RTCCLK / 16384 */
00253 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200)  /*!< Each of the tamper inputs are sampled
00254                                                                              with a frequency =  RTCCLK / 8192  */
00255 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300)  /*!< Each of the tamper inputs are sampled
00256                                                                              with a frequency =  RTCCLK / 4096  */
00257 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400)  /*!< Each of the tamper inputs are sampled
00258                                                                              with a frequency =  RTCCLK / 2048  */
00259 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500)  /*!< Each of the tamper inputs are sampled
00260                                                                              with a frequency =  RTCCLK / 1024  */
00261 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600)  /*!< Each of the tamper inputs are sampled
00262                                                                              with a frequency =  RTCCLK / 512   */
00263 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700)  /*!< Each of the tamper inputs are sampled
00264                                                                              with a frequency =  RTCCLK / 256   */
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
00270   * @{
00271   */
00272 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before
00273                                                                          sampling during 1 RTCCLK cycle  */
00274 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before
00275                                                                          sampling during 2 RTCCLK cycles */
00276 #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before
00277                                                                          sampling during 4 RTCCLK cycles */
00278 #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before
00279                                                                          sampling during 8 RTCCLK cycles */
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
00285   * @{
00286   */
00287 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAMPCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */
00288 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)         /*!< TimeStamp on Tamper Detection event is not saved */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
00294   * @{
00295   */
00296 #define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000)              /*!< TimeStamp on Tamper Detection event saved        */
00297 #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)    /*!< TimeStamp on Tamper Detection event is not saved */
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions
00303   * @{
00304   */
00305 #define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000)
00306 #define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001)
00307 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002)
00308 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003)
00309 #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004)
00310 #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006)
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
00316   * @{
00317   */
00318 #define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00319                                                                     period is 32s,  else 2exp20 RTCCLK seconds */
00320 #define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00321                                                                     period is 16s, else 2exp19 RTCCLK seconds */
00322 #define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000)  /*!< If RTCCLK = 32768 Hz, Smooth calibration
00323                                                                     period is 8s, else 2exp18 RTCCLK seconds */
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions
00329   * @{
00330   */
00331 #define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000)  /*!< The number of RTCCLK pulses added
00332                                                                        during a X -second window = Y - CALM[8:0]
00333                                                                        with Y = 512, 256, 128 when X = 32, 16, 8 */
00334 #define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000)  /*!< The number of RTCCLK pulses subbstited
00335                                                                        during a 32-second window = CALM[8:0] */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
00341   * @{
00342   */
00343 #define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000)
00344 #define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000)
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
00350   * @{
00351   */
00352 #define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000)
00353 #define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000)
00354 /**
00355   * @}
00356   */
00357
00358 /**
00359   * @}
00360   */
00361
00362 /* Exported macros -----------------------------------------------------------*/
00363 /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
00364   * @{
00365   */
00366
00367 /**
00368   * @brief  Enable the RTC WakeUp Timer peripheral.
00369   * @param  __HANDLE__: specifies the RTC handle.
00370   * @retval None
00371   */
00372 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
00373
00374 /**
00375   * @brief  Disable the RTC WakeUp Timer peripheral.
00376   * @param  __HANDLE__: specifies the RTC handle.
00377   * @retval None
00378   */
00379 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
00380
00381 /**
00382   * @brief  Enable the RTC WakeUpTimer interrupt.
00383   * @param  __HANDLE__: specifies the RTC handle.
00384   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled.
00385   *         This parameter can be:
00386   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
00387   * @retval None
00388   */
00389 #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00390
00391 /**
00392   * @brief  Disable the RTC WakeUpTimer interrupt.
00393   * @param  __HANDLE__: specifies the RTC handle.
00394   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled.
00395   *         This parameter can be:
00396   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
00397   * @retval None
00398   */
00399 #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00400
00401 /**
00402   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
00403   * @param  __HANDLE__: specifies the RTC handle.
00404   * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check.
00405   *         This parameter can be:
00406   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00407   * @retval None
00408   */
00409 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
00410
00411 /**
00412   * @brief  Check whether the specified RTC Wake Up timer interrupt is enabled or not.
00413   * @param  __HANDLE__: specifies the RTC handle.
00414   * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
00415   *         This parameter can be:
00416   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00417   * @retval None
00418   */
00419 #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00420
00421 /**
00422   * @brief  Get the selected RTC WakeUpTimer's flag status.
00423   * @param  __HANDLE__: specifies the RTC handle.
00424   * @param  __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
00425   *          This parameter can be:
00426   *             @arg RTC_FLAG_WUTF
00427   *             @arg RTC_FLAG_WUTWF
00428   * @retval None
00429   */
00430 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00431
00432 /**
00433   * @brief  Clear the RTC Wake Up timer's pending flags.
00434   * @param  __HANDLE__: specifies the RTC handle.
00435   * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
00436   *         This parameter can be:
00437   *            @arg RTC_FLAG_WUTF
00438   * @retval None
00439   */
00440 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00441
00442 #if defined(RTC_TAMPER1_SUPPORT)
00443 /**
00444   * @brief  Enable the RTC Tamper1 input detection.
00445   * @param  __HANDLE__: specifies the RTC handle.
00446   * @retval None
00447   */
00448 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
00449
00450 /**
00451   * @brief  Disable the RTC Tamper1 input detection.
00452   * @param  __HANDLE__: specifies the RTC handle.
00453   * @retval None
00454   */
00455 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
00456 #endif /* RTC_TAMPER1_SUPPORT */
00457
00458 /**
00459   * @brief  Enable the RTC Tamper2 input detection.
00460   * @param  __HANDLE__: specifies the RTC handle.
00461   * @retval None
00462   */
00463 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
00464
00465 /**
00466   * @brief  Disable the RTC Tamper2 input detection.
00467   * @param  __HANDLE__: specifies the RTC handle.
00468   * @retval None
00469   */
00470 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
00471
00472 #if defined(RTC_TAMPER3_SUPPORT)
00473 /**
00474   * @brief  Enable the RTC Tamper3 input detection.
00475   * @param  __HANDLE__: specifies the RTC handle.
00476   * @retval None
00477   */
00478 #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
00479
00480 /**
00481   * @brief  Disable the RTC Tamper3 input detection.
00482   * @param  __HANDLE__: specifies the RTC handle.
00483   * @retval None
00484   */
00485 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
00486 #endif /* RTC_TAMPER3_SUPPORT */
00487
00488 /**
00489   * @brief  Enable the RTC Tamper interrupt.
00490   * @param  __HANDLE__: specifies the RTC handle.
00491   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
00492   *          This parameter can be any combination of the following values:
00493   *             @arg  RTC_IT_TAMP: All tampers interrupts
00494   *             @arg  RTC_IT_TAMP1: Tamper1 interrupt
00495   *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
00496   *             @arg  RTC_IT_TAMP3: Tamper3 interrupt
00497   * @retval None
00498   */
00499 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
00500
00501 /**
00502   * @brief  Disable the RTC Tamper interrupt.
00503   * @param  __HANDLE__: specifies the RTC handle.
00504   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
00505   *         This parameter can be any combination of the following values:
00506   *            @arg  RTC_IT_TAMP: All tampers interrupts
00507   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00508   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00509   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
00510   * @retval None
00511   */
00512 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
00513
00514 /**
00515   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
00516   * @param  __HANDLE__: specifies the RTC handle.
00517   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
00518   *         This parameter can be:
00519   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00520   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00521   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
00522   * @retval None
00523   */
00524 #if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
00525 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
00526                                                                       ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
00527                                                                       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
00528 #else
00529 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET)
00530 #endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */
00531
00532 /**
00533   * @brief  Check whether the specified RTC Tamper interrupt is enabled or not.
00534   * @param  __HANDLE__: specifies the RTC handle.
00535   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
00536   *         This parameter can be:
00537   *            @arg  RTC_IT_TAMP: All tampers interrupts
00538   *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
00539   *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
00540   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
00541   * @retval None
00542   */
00543 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00544
00545 /**
00546   * @brief  Get the selected RTC Tamper's flag status.
00547   * @param  __HANDLE__: specifies the RTC handle.
00548   * @param  __FLAG__: specifies the RTC Tamper Flag is pending or not.
00549   *          This parameter can be:
00550   *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
00551   *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
00552   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
00553   * @retval None
00554   */
00555 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00556
00557 /**
00558   * @brief  Clear the RTC Tamper's pending flags.
00559   * @param  __HANDLE__: specifies the RTC handle.
00560   * @param  __FLAG__: specifies the RTC Tamper Flag sources to clear.
00561   *          This parameter can be:
00562   *             @arg RTC_FLAG_TAMP1F: Tamper1 flag
00563   *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
00564   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
00565   * @retval None
00566   */
00567 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00568
00569 /**
00570   * @brief  Enable the RTC TimeStamp peripheral.
00571   * @param  __HANDLE__: specifies the RTC handle.
00572   * @retval None
00573   */
00574 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
00575
00576 /**
00577   * @brief  Disable the RTC TimeStamp peripheral.
00578   * @param  __HANDLE__: specifies the RTC handle.
00579   * @retval None
00580   */
00581 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
00582
00583 /**
00584   * @brief  Enable the RTC TimeStamp interrupt.
00585   * @param  __HANDLE__: specifies the RTC handle.
00586   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled.
00587   *         This parameter can be:
00588   *            @arg RTC_IT_TS: TimeStamp interrupt
00589   * @retval None
00590   */
00591 #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00592
00593 /**
00594   * @brief  Disable the RTC TimeStamp interrupt.
00595   * @param  __HANDLE__: specifies the RTC handle.
00596   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled.
00597   *         This parameter can be:
00598   *            @arg RTC_IT_TS: TimeStamp interrupt
00599   * @retval None
00600   */
00601 #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00602
00603 /**
00604   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
00605   * @param  __HANDLE__: specifies the RTC handle.
00606   * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt source to check.
00607   *         This parameter can be:
00608   *            @arg RTC_IT_TS: TimeStamp interrupt
00609   * @retval None
00610   */
00611 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
00612
00613 /**
00614   * @brief  Check whether the specified RTC Time Stamp interrupt is enabled or not.
00615   * @param  __HANDLE__: specifies the RTC handle.
00616   * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
00617   *         This parameter can be:
00618   *            @arg RTC_IT_TS: TimeStamp interrupt
00619   * @retval None
00620   */
00621 #define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
00622
00623 /**
00624   * @brief  Get the selected RTC TimeStamp's flag status.
00625   * @param  __HANDLE__: specifies the RTC handle.
00626   * @param  __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
00627   *         This parameter can be:
00628   *            @arg RTC_FLAG_TSF
00629   *            @arg RTC_FLAG_TSOVF
00630   * @retval None
00631   */
00632 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00633
00634 /**
00635   * @brief  Clear the RTC Time Stamp's pending flags.
00636   * @param  __HANDLE__: specifies the RTC handle.
00637   * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
00638   *          This parameter can be:
00639   *             @arg RTC_FLAG_TSF
00640   *             @arg RTC_FLAG_TSOVF
00641   * @retval None
00642   */
00643 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00644
00645 /**
00646   * @brief  Enable the RTC internal TimeStamp peripheral.
00647   * @param  __HANDLE__: specifies the RTC handle.
00648   * @retval None
00649   */
00650 #define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
00651
00652 /**
00653   * @brief  Disable the RTC internal TimeStamp peripheral.
00654   * @param  __HANDLE__: specifies the RTC handle.
00655   * @retval None
00656   */
00657 #define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
00658
00659 /**
00660   * @brief  Get the selected RTC Internal Time Stamp's flag status.
00661   * @param  __HANDLE__: specifies the RTC handle.
00662   * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not.
00663   *         This parameter can be:
00664   *            @arg RTC_FLAG_ITSF
00665   * @retval None
00666   */
00667 #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00668
00669 /**
00670   * @brief  Clear the RTC Internal Time Stamp's pending flags.
00671   * @param  __HANDLE__: specifies the RTC handle.
00672   * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear.
00673   *          This parameter can be:
00674   *             @arg RTC_FLAG_ITSF
00675   * @retval None
00676   */
00677 #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00678
00679 /**
00680   * @brief  Enable the RTC calibration output.
00681   * @param  __HANDLE__: specifies the RTC handle.
00682   * @retval None
00683   */
00684 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
00685
00686 /**
00687   * @brief  Disable the calibration output.
00688   * @param  __HANDLE__: specifies the RTC handle.
00689   * @retval None
00690   */
00691 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
00692
00693 /**
00694   * @brief  Enable the clock reference detection.
00695   * @param  __HANDLE__: specifies the RTC handle.
00696   * @retval None
00697   */
00698 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
00699
00700 /**
00701   * @brief  Disable the clock reference detection.
00702   * @param  __HANDLE__: specifies the RTC handle.
00703   * @retval None
00704   */
00705 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
00706
00707 /**
00708   * @brief  Get the selected RTC shift operation's flag status.
00709   * @param  __HANDLE__: specifies the RTC handle.
00710   * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
00711   *          This parameter can be:
00712   *             @arg RTC_FLAG_SHPF
00713   * @retval None
00714   */
00715 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
00716
00717 /**
00718   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
00719   * @retval None
00720   */
00721 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00722
00723 /**
00724   * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
00725   * @retval None
00726   */
00727 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00728
00729 /**
00730   * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
00731   * @retval None
00732   */
00733 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00734
00735 /**
00736   * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
00737   * @retval None
00738   */
00739 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00740
00741 /**
00742   * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
00743   * @retval None
00744   */
00745 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00746
00747 /**
00748   * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
00749   * @retval None
00750   */
00751 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00752
00753 /**
00754   * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
00755   * @retval None
00756   */
00757 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00758
00759 /**
00760   * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
00761   * @retval None
00762   */
00763 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00764
00765 /**
00766   * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
00767   * @retval None
00768   */
00769 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00770                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
00771                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
00772                                                                  } while(0)
00773
00774 /**
00775   * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
00776   * This parameter can be:
00777   * @retval None
00778   */
00779 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00780                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
00781                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
00782                                                                   } while(0)
00783
00784 /**
00785   * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
00786   * @retval Line Status.
00787   */
00788 #define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00789
00790 /**
00791   * @brief Clear the RTC WakeUp Timer associated Exti line flag.
00792   * @retval None
00793   */
00794 #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00795
00796 /**
00797   * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
00798   * @retval None
00799   */
00800 #define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00801
00802 /**
00803   * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
00804   * @retval None
00805   */
00806 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00807
00808 /**
00809   * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
00810   * @retval None
00811   */
00812 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00813
00814 /**
00815   * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
00816   * @retval None
00817   */
00818 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00819
00820 /**
00821   * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
00822   * @retval None
00823   */
00824 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00825
00826 /**
00827   * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00828   * @retval None
00829   */
00830 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00831
00832 /**
00833   * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00834   * @retval None
00835   */
00836 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00837
00838 /**
00839   * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00840   * @retval None
00841   */
00842 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00843
00844 /**
00845   * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00846   * @retval None
00847   */
00848 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00849
00850 /**
00851   * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00852   * @retval None
00853   */
00854 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00855                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
00856                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
00857                                                                       } while(0)
00858
00859 /**
00860   * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00861   * This parameter can be:
00862   * @retval None
00863   */
00864 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00865                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
00866                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
00867                                                                        } while(0)
00868
00869 /**
00870   * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
00871   * @retval Line Status.
00872   */
00873 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00874
00875 /**
00876   * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
00877   * @retval None
00878   */
00879 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00880
00881 /**
00882   * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
00883   * @retval None
00884   */
00885 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00886
00887 /**
00888   * @}
00889   */
00890
00891 /* Exported functions --------------------------------------------------------*/
00892 /** @addtogroup RTCEx_Exported_Functions
00893   * @{
00894   */
00895
00896 /* RTC TimeStamp and Tamper functions *****************************************/
00897 /** @addtogroup RTCEx_Exported_Functions_Group1
00898   * @{
00899   */
00900 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00901 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
00902 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
00903 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
00904 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
00905 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
00906
00907 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00908 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00909 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
00910 void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
00911
00912 #if defined(RTC_TAMPER1_SUPPORT)
00913 void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
00914 #endif /* RTC_TAMPER1_SUPPORT */
00915 void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
00916 #if defined(RTC_TAMPER3_SUPPORT)
00917 void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
00918 #endif /* RTC_TAMPER3_SUPPORT */
00919 void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
00920 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00921 #if defined(RTC_TAMPER1_SUPPORT)
00922 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00923 #endif /* RTC_TAMPER1_SUPPORT */
00924 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00925 #if defined(RTC_TAMPER3_SUPPORT)
00926 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00927 #endif /* RTC_TAMPER3_SUPPORT */
00928 /**
00929   * @}
00930   */
00931
00932 /* RTC Wake-up functions ******************************************************/
00933 /** @addtogroup RTCEx_Exported_Functions_Group2
00934   * @{
00935   */
00936 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00937 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
00938 uint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
00939 uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
00940 void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
00941 void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
00942 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00943 /**
00944   * @}
00945   */
00946
00947 /* Extended Control functions ************************************************/
00948 /** @addtogroup RTCEx_Exported_Functions_Group3
00949   * @{
00950   */
00951 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
00952 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
00953
00954 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
00955 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
00956 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
00957 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
00958 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
00959 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
00960 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
00961 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
00962 /**
00963   * @}
00964   */
00965
00966 /* Extended RTC features functions *******************************************/
00967 /** @addtogroup RTCEx_Exported_Functions_Group4
00968   * @{
00969   */
00970 void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
00971 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00972 /**
00973   * @}
00974   */
00975
00976 /**
00977   * @}
00978   */
00979
00980 /* Private types -------------------------------------------------------------*/
00981 /* Private variables ---------------------------------------------------------*/
00982 /* Private constants ---------------------------------------------------------*/
00983 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
00984   * @{
00985   */
00986 #define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)0x00080000)  /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
00987 #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the RTC Wakeup event */
00988
00989 /**
00990   * @}
00991   */
00992
00993 /* Private macros ------------------------------------------------------------*/
00994 /** @defgroup RTCEx_Private_Macros RTCEx Private Macros
00995   * @{
00996   */
00997
00998 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
00999   * @{
01000   */
01001
01002 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
01003                                ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
01004                                ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
01005                                ((OUTPUT) == RTC_OUTPUT_WAKEUP))
01006
01007 #define IS_RTC_BKP(BKP)                   ((BKP) < (uint32_t) RTC_BKP_NUMBER)
01008
01009 #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
01010                                  ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
01011
01012 #define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
01013
01014 #define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != (uint32_t)RESET))
01015
01016 #define IS_RTC_TIMESTAMP_PIN(PIN)  (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
01017
01018 #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
01019                                         ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
01020                                         ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
01021                                         ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
01022
01023 #define IS_RTC_TAMPER_ERASE_MODE(MODE)             (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
01024                                                     ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
01025
01026 #define IS_RTC_TAMPER_MASKFLAG_STATE(STATE)        (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
01027                                                     ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))
01028
01029 #define IS_RTC_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
01030                                        ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
01031                                        ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
01032                                        ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
01033
01034 #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
01035                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
01036                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
01037                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
01038                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
01039                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
01040                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
01041                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
01042
01043 #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
01044                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
01045                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
01046                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
01047
01048 #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
01049                                                               ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
01050
01051 #define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
01052                                            ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
01053
01054 #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
01055                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
01056                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
01057                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
01058                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
01059                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
01060
01061 #define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
01062
01063 #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
01064                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
01065                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
01066
01067 #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
01068                                         ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
01069
01070 #define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
01071
01072 #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
01073                                  ((SEL) == RTC_SHIFTADD1S_SET))
01074
01075 #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
01076
01077 #define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
01078                                       ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
01079
01080 /**
01081   * @}
01082   */
01083
01084 /**
01085   * @}
01086   */
01087
01088 /**
01089   * @}
01090   */
01091
01092 /**
01093   * @}
01094   */
01095
01096 #ifdef __cplusplus
01097 }
01098 #endif
01099
01100 #endif /* __STM32L4xx_HAL_RTC_EX_H */
01101
01102 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sai.c Source File

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stm32l4xx_hal_sai.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_sai.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SAI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Serial Audio Interface (SAI) peripheral:
00010   *           + Initialization/de-initialization functions
00011   *           + I/O operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                   ##### How to use this driver #####
00018   ==============================================================================
00019
00020   [..]
00021     The SAI HAL driver can be used as follows:
00022
00023     (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
00024     (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
00025         (##) Enable the SAI interface clock.
00026         (##) SAI pins configuration:
00027             (+++) Enable the clock for the SAI GPIOs.
00028             (+++) Configure these SAI pins as alternate function pull-up.
00029         (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
00030              and HAL_SAI_Receive_IT() APIs):
00031             (+++) Configure the SAI interrupt priority.
00032             (+++) Enable the NVIC SAI IRQ handle.
00033
00034         (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
00035              and HAL_SAI_Receive_DMA() APIs):
00036             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00037             (+++) Enable the DMAx interface clock.
00038             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00039             (+++) Configure the DMA Tx/Rx Stream.
00040             (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
00041             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00042                 DMA Tx/Rx Stream.
00043
00044     (#) The initialization can be done by two ways
00045         (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
00046         (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
00047
00048   [..]
00049     (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
00050         will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
00051         inside the transmit and receive process.
00052   [..]
00053     (@) Make sure that either:
00054         (+@) PLLSAI1CLK output is configured or
00055         (+@) PLLSAI2CLK output is configured or
00056         (+@) PLLSAI3CLK output is configured or
00057         (+@) External clock source is configured after setting correctly
00058              the define constant EXTERNAL_SAI1_CLOCK_VALUE or EXTERNAL_SAI2_CLOCK_VALUE in the stm32l4xx_hal_conf.h file.
00059
00060   [..]
00061     (@) In master Tx mode: enabling the audio block immediately generates the bit clock
00062         for the external slaves even if there is no data in the FIFO, However FS signal
00063         generation is conditioned by the presence of data in the FIFO.
00064
00065   [..]
00066     (@) In master Rx mode: enabling the audio block immediately generates the bit clock
00067         and FS signal for the external slaves.
00068
00069   [..]
00070     (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
00071         (+@) First bit Offset <= (SLOT size - Data size)
00072         (+@) Data size <= SLOT size
00073         (+@) Number of SLOT x SLOT size = Frame length
00074         (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
00075
00076   [..]
00077     Three operation modes are available within this driver :
00078
00079     *** Polling mode IO operation ***
00080     =================================
00081     [..]
00082       (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
00083       (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
00084
00085     *** Interrupt mode IO operation ***
00086     ===================================
00087     [..]
00088       (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
00089       (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
00090           add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
00091       (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
00092       (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
00093           add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
00094       (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
00095           add his own code by customization of function pointer HAL_SAI_ErrorCallback()
00096
00097     *** DMA mode IO operation ***
00098     =============================
00099     [..]
00100       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
00101       (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
00102           add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
00103       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
00104       (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
00105           add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
00106       (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
00107           add his own code by customization of function pointer HAL_SAI_ErrorCallback()
00108       (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
00109       (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
00110       (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
00111
00112     *** SAI HAL driver additional function list ***
00113     ===============================================
00114     [..]
00115       Below the list the others API available SAI HAL driver :
00116
00117       (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
00118       (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
00119       (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
00120       (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
00121       (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
00122       (+) HAL_SAI_Abort(): Abort the current transfer
00123
00124     *** SAI HAL driver macros list ***
00125     ==================================
00126     [..]
00127       Below the list of most used macros in SAI HAL driver :
00128
00129       (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
00130       (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
00131       (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
00132       (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
00133       (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
00134           enabled or disabled
00135       (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
00136
00137   @endverbatim
00138   ******************************************************************************
00139   * @attention
00140   *
00141   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00142   *
00143   * Redistribution and use in source and binary forms, with or without modification,
00144   * are permitted provided that the following conditions are met:
00145   *   1. Redistributions of source code must retain the above copyright notice,
00146   *      this list of conditions and the following disclaimer.
00147   *   2. Redistributions in binary form must reproduce the above copyright notice,
00148   *      this list of conditions and the following disclaimer in the documentation
00149   *      and/or other materials provided with the distribution.
00150   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00151   *      may be used to endorse or promote products derived from this software
00152   *      without specific prior written permission.
00153   *
00154   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00155   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00156   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00157   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00158   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00159   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00160   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00161   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00162   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00163   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00164   *
00165   ******************************************************************************
00166   */
00167
00168 /* Includes ------------------------------------------------------------------*/
00169 #include "stm32l4xx_hal.h"
00170
00171 /** @addtogroup STM32L4xx_HAL_Driver
00172   * @{
00173   */
00174
00175 /** @defgroup SAI SAI
00176   * @brief SAI HAL module driver
00177   * @{
00178   */
00179
00180 #ifdef HAL_SAI_MODULE_ENABLED
00181
00182 /* Private typedef -----------------------------------------------------------*/
00183
00184 /** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
00185   * @{
00186   */
00187 typedef enum {
00188   SAI_MODE_DMA,
00189   SAI_MODE_IT
00190 }SAI_ModeTypedef;
00191 /**
00192   * @}
00193   */
00194
00195 /* Private define ------------------------------------------------------------*/
00196
00197 /** @defgroup SAI_Private_Constants  SAI Private Constants
00198   * @{
00199   */
00200 #define SAI_FIFO_SIZE       8
00201 #define SAI_DEFAULT_TIMEOUT 4
00202 #define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
00203 /**
00204   * @}
00205   */
00206
00207 /* Private macro -------------------------------------------------------------*/
00208 /* Private variables ---------------------------------------------------------*/
00209 /* Private function prototypes -----------------------------------------------*/
00210
00211 /** @defgroup SAI_Private_Functions  SAI Private Functions
00212   * @{
00213   */
00214 static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
00215 static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
00216 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00217 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00218
00219 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
00220 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
00221 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
00222 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
00223 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
00224 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
00225 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
00226
00227 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
00228 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00229 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
00230 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00231 static void SAI_DMAError(DMA_HandleTypeDef *hdma);
00232 static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
00233 /**
00234   * @}
00235   */
00236
00237 /* Exported functions ---------------------------------------------------------*/
00238
00239 /** @defgroup SAI_Exported_Functions SAI Exported Functions
00240   * @{
00241   */
00242
00243 /** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
00244  *  @brief    Initialization and Configuration functions
00245  *
00246 @verbatim
00247  ===============================================================================
00248              ##### Initialization and de-initialization functions #####
00249  ===============================================================================
00250   [..]  This subsection provides a set of functions allowing to initialize and
00251         de-initialize the SAIx peripheral:
00252
00253       (+) User must implement HAL_SAI_MspInit() function in which he configures
00254           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00255
00256       (+) Call the function HAL_SAI_Init() to configure the selected device with
00257           the selected configuration:
00258         (++) Mode (Master/slave TX/RX)
00259         (++) Protocol
00260         (++) Data Size
00261         (++) MCLK Output
00262         (++) Audio frequency
00263         (++) FIFO Threshold
00264         (++) Frame Config
00265         (++) Slot Config
00266
00267       (+) Call the function HAL_SAI_DeInit() to restore the default configuration
00268           of the selected SAI peripheral.
00269
00270 @endverbatim
00271   * @{
00272   */
00273
00274 /**
00275   * @brief  Initialize the structure FrameInit, SlotInit and the low part of
00276   *         Init according to the specified parameters and call the function
00277   *         HAL_SAI_Init to initialize the SAI block.
00278   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00279   *               the configuration information for SAI module.
00280   * @param  protocol: one of the supported protocol @ref SAI_Protocol
00281   * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
00282   *                   the configuration information for SAI module.
00283   * @param  nbslot: Number of slot.
00284   * @retval HAL status
00285   */
00286 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
00287 {
00288   HAL_StatusTypeDef status = HAL_OK;
00289
00290   /* Check the parameters */
00291   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
00292   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
00293
00294   switch(protocol)
00295   {
00296   case SAI_I2S_STANDARD :
00297   case SAI_I2S_MSBJUSTIFIED :
00298   case SAI_I2S_LSBJUSTIFIED :
00299     status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
00300     break;
00301   case SAI_PCM_LONG :
00302   case SAI_PCM_SHORT :
00303     status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
00304     break;
00305   default :
00306     status = HAL_ERROR;
00307     break;
00308   }
00309
00310   if(status == HAL_OK)
00311   {
00312     status = HAL_SAI_Init(hsai);
00313   }
00314
00315   return status;
00316 }
00317
00318 /**
00319   * @brief  Initialize the SAI according to the specified parameters.
00320   *         in the SAI_InitTypeDef structure and initialize the associated handle.
00321   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00322   *                the configuration information for SAI module.
00323   * @retval HAL status
00324   */
00325 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
00326 {
00327   uint32_t tmpregisterGCR = 0;
00328   uint32_t ckstr_bits  = 0;
00329   uint32_t syncen_bits = 0;
00330
00331   /* Check the SAI handle allocation */
00332   if(hsai == NULL)
00333   {
00334     return HAL_ERROR;
00335   }
00336
00337   /* check the instance */
00338   assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
00339
00340   /* Check the SAI Block parameters */
00341   assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
00342   assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
00343   assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
00344   assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
00345   assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
00346   assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
00347   assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
00348   assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
00349   assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
00350   assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
00351   assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
00352   assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
00353   assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
00354   assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
00355
00356   /* Check the SAI Block Frame parameters */
00357   assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
00358   assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
00359   assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
00360   assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
00361   assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
00362
00363   /* Check the SAI Block Slot parameters */
00364   assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
00365   assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
00366   assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
00367   assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
00368
00369   if(hsai->State == HAL_SAI_STATE_RESET)
00370   {
00371     /* Allocate lock resource and initialize it */
00372     hsai->Lock = HAL_UNLOCKED;
00373
00374     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00375     HAL_SAI_MspInit(hsai);
00376   }
00377
00378   hsai->State = HAL_SAI_STATE_BUSY;
00379
00380   /* Disable the selected SAI peripheral */
00381   SAI_Disable(hsai);
00382
00383   /* SAI Block Synchro Configuration -----------------------------------------*/
00384   /* This setting must be done with both audio block (A & B) disabled         */
00385   switch(hsai->Init.SynchroExt)
00386   {
00387     case SAI_SYNCEXT_DISABLE :
00388       tmpregisterGCR = 0;
00389       break;
00390     case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
00391       tmpregisterGCR = SAI_GCR_SYNCOUT_0;
00392       break;
00393     case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
00394       tmpregisterGCR = SAI_GCR_SYNCOUT_1;
00395       break;
00396   }
00397
00398   switch(hsai->Init.Synchro)
00399   {
00400     case SAI_ASYNCHRONOUS :
00401       {
00402         syncen_bits = 0;
00403       }
00404       break;
00405     case SAI_SYNCHRONOUS :
00406       {
00407         syncen_bits = SAI_xCR1_SYNCEN_0;
00408       }
00409       break;
00410     case SAI_SYNCHRONOUS_EXT_SAI1 :
00411       {
00412         syncen_bits = SAI_xCR1_SYNCEN_1;
00413       }
00414       break;
00415     case SAI_SYNCHRONOUS_EXT_SAI2 :
00416       {
00417         syncen_bits = SAI_xCR1_SYNCEN_1;
00418         tmpregisterGCR |= SAI_GCR_SYNCIN_0;
00419       }
00420       break;
00421   }
00422
00423 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00424
00425   if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
00426   {
00427     SAI1->GCR = tmpregisterGCR;
00428   }
00429   else
00430   {
00431     SAI2->GCR = tmpregisterGCR;
00432   }
00433
00434 #else
00435
00436   SAI1->GCR = tmpregisterGCR;
00437
00438 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00439
00440   if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
00441   {
00442     uint32_t freq = 0;
00443     uint32_t tmpval;
00444
00445     /* In this case, the MCKDIV value is calculated to get AudioFrequency */
00446 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00447
00448     if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B ))
00449     {
00450       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
00451     }
00452     if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B ))
00453     {
00454       freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
00455     }
00456
00457 #else
00458
00459     freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
00460
00461 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00462
00463     /* Configure Master Clock using the following formula :
00464        MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS
00465        FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256
00466        MCKDIV[3:0] = SAI_CK_x / FS * 512 */
00467     /* (freq x 10) to keep Significant digits */
00468     tmpval = (freq * 10) / (hsai->Init.AudioFrequency * 2 * 256);
00469     hsai->Init.Mckdiv = tmpval / 10;
00470
00471     /* Round result to the nearest integer */
00472     if((tmpval % 10) > 8)
00473     {
00474       hsai->Init.Mckdiv+= 1;
00475     }
00476   }
00477
00478   /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
00479   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
00480   { /* Transmit */
00481     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR;
00482   }
00483   else
00484   { /* Receive */
00485     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0;
00486   }
00487
00488   /* SAI Block Configuration -------------------------------------------------*/
00489   /* SAI CR1 Configuration */
00490   hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
00491                          SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
00492                          SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
00493                          SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);
00494
00495   hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol |           \
00496                         hsai->Init.DataSize | hsai->Init.FirstBit  |           \
00497                         ckstr_bits | syncen_bits |                             \
00498                         hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
00499                         hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20));
00500
00501   /* SAI CR2 Configuration */
00502   hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
00503   hsai->Instance->CR2|=  (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
00504
00505   /* SAI Frame Configuration -----------------------------------------*/
00506   hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
00507                            SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
00508   hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) |
00509                           hsai->FrameInit.FSOffset |
00510                           hsai->FrameInit.FSDefinition |
00511                           hsai->FrameInit.FSPolarity   |
00512                           ((hsai->FrameInit.ActiveFrameLength - 1) << 8));
00513
00514   /* SAI Block_x SLOT Configuration ------------------------------------------*/
00515   /* This register has no meaning in AC 97 and SPDIF audio protocol */
00516   hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ |            \
00517                              SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));
00518
00519   hsai->Instance->SLOTR|=  hsai->SlotInit.FirstBitOffset |  hsai->SlotInit.SlotSize
00520                           | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) <<  8);
00521
00522   /* Initialize the error code */
00523   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00524
00525   /* Initialize the SAI state */
00526   hsai->State= HAL_SAI_STATE_READY;
00527
00528   /* Release Lock */
00529   __HAL_UNLOCK(hsai);
00530
00531   return HAL_OK;
00532 }
00533
00534 /**
00535   * @brief  DeInitialize the SAI peripheral.
00536   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00537   *                the configuration information for SAI module.
00538   * @retval HAL status
00539   */
00540 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
00541 {
00542   /* Check the SAI handle allocation */
00543   if(hsai == NULL)
00544   {
00545     return HAL_ERROR;
00546   }
00547
00548   hsai->State = HAL_SAI_STATE_BUSY;
00549
00550   /* Disabled All interrupt and clear all the flag */
00551   hsai->Instance->IMR = 0;
00552   hsai->Instance->CLRFR = 0xFFFFFFFFU;
00553
00554   /* Disable the SAI */
00555   SAI_Disable(hsai);
00556
00557   /* Flush the fifo */
00558   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00559
00560   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00561   HAL_SAI_MspDeInit(hsai);
00562
00563   /* Initialize the error code */
00564   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00565
00566   /* Initialize the SAI state */
00567   hsai->State = HAL_SAI_STATE_RESET;
00568
00569   /* Release Lock */
00570   __HAL_UNLOCK(hsai);
00571
00572   return HAL_OK;
00573 }
00574
00575 /**
00576   * @brief Initialize the SAI MSP.
00577   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00578   *                the configuration information for SAI module.
00579   * @retval None
00580   */
00581 __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
00582 {
00583   /* Prevent unused argument(s) compilation warning */
00584   UNUSED(hsai);
00585
00586   /* NOTE : This function should not be modified, when the callback is needed,
00587             the HAL_SAI_MspInit could be implemented in the user file
00588    */
00589 }
00590
00591 /**
00592   * @brief DeInitialize the SAI MSP.
00593   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00594   *                the configuration information for SAI module.
00595   * @retval None
00596   */
00597 __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
00598 {
00599   /* Prevent unused argument(s) compilation warning */
00600   UNUSED(hsai);
00601
00602   /* NOTE : This function should not be modified, when the callback is needed,
00603             the HAL_SAI_MspDeInit could be implemented in the user file
00604    */
00605 }
00606
00607 /**
00608   * @}
00609   */
00610
00611 /** @defgroup SAI_Exported_Functions_Group2 IO operation functions
00612  *  @brief    Data transfers functions
00613  *
00614 @verbatim
00615   ==============================================================================
00616                       ##### IO operation functions #####
00617   ==============================================================================
00618   [..]
00619     This subsection provides a set of functions allowing to manage the SAI data
00620     transfers.
00621
00622     (+) There are two modes of transfer:
00623       (++) Blocking mode : The communication is performed in the polling mode.
00624            The status of all data processing is returned by the same function
00625            after finishing transfer.
00626       (++) No-Blocking mode : The communication is performed using Interrupts
00627            or DMA. These functions return the status of the transfer startup.
00628            The end of the data processing will be indicated through the
00629            dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
00630            using DMA mode.
00631
00632     (+) Blocking mode functions are :
00633       (++) HAL_SAI_Transmit()
00634       (++) HAL_SAI_Receive()
00635       (++) HAL_SAI_TransmitReceive()
00636
00637     (+) Non Blocking mode functions with Interrupt are :
00638       (++) HAL_SAI_Transmit_IT()
00639       (++) HAL_SAI_Receive_IT()
00640       (++) HAL_SAI_TransmitReceive_IT()
00641
00642     (+) Non Blocking mode functions with DMA are :
00643       (++) HAL_SAI_Transmit_DMA()
00644       (++) HAL_SAI_Receive_DMA()
00645       (++) HAL_SAI_TransmitReceive_DMA()
00646
00647     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00648       (++) HAL_SAI_TxCpltCallback()
00649       (++) HAL_SAI_RxCpltCallback()
00650       (++) HAL_SAI_ErrorCallback()
00651
00652 @endverbatim
00653   * @{
00654   */
00655
00656 /**
00657   * @brief  Transmit an amount of data in blocking mode.
00658   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00659   *                the configuration information for SAI module.
00660   * @param  pData: Pointer to data buffer
00661   * @param  Size: Amount of data to be sent
00662   * @param  Timeout: Timeout duration
00663   * @retval HAL status
00664   */
00665 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
00666 {
00667   uint32_t tickstart = HAL_GetTick();
00668
00669   if((pData == NULL ) || (Size == 0))
00670   {
00671     return  HAL_ERROR;
00672   }
00673
00674   if(hsai->State == HAL_SAI_STATE_READY)
00675   {
00676     /* Process Locked */
00677     __HAL_LOCK(hsai);
00678
00679     hsai->XferSize = Size;
00680     hsai->XferCount = Size;
00681     hsai->pBuffPtr = pData;
00682     hsai->State = HAL_SAI_STATE_BUSY_TX;
00683     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00684
00685     /* Check if the SAI is already enabled */
00686     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00687     {
00688       /* fill the fifo with data before to enabled the SAI */
00689       SAI_FillFifo(hsai);
00690       /* Enable SAI peripheral */
00691       __HAL_SAI_ENABLE(hsai);
00692     }
00693
00694     while(hsai->XferCount > 0)
00695     {
00696       /* Write data if the FIFO is not full */
00697       if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
00698       {
00699         if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00700         {
00701           hsai->Instance->DR = (*hsai->pBuffPtr++);
00702         }
00703         else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00704         {
00705           hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
00706           hsai->pBuffPtr+= 2;
00707         }
00708         else
00709         {
00710           hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
00711           hsai->pBuffPtr+= 4;
00712         }
00713         hsai->XferCount--;
00714       }
00715       else
00716       {
00717         /* Check for the Timeout */
00718         if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
00719         {
00720           /* Update error code */
00721           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
00722
00723           /* Clear all the flags */
00724           hsai->Instance->CLRFR = 0xFFFFFFFFU;
00725
00726           /* Disable SAI peripheral */
00727           SAI_Disable(hsai);
00728
00729           /* Flush the fifo */
00730           SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00731
00732           /* Change the SAI state */
00733           hsai->State = HAL_SAI_STATE_READY;
00734
00735           /* Process Unlocked */
00736           __HAL_UNLOCK(hsai);
00737
00738           return HAL_ERROR;
00739         }
00740       }
00741     }
00742
00743     hsai->State = HAL_SAI_STATE_READY;
00744
00745     /* Process Unlocked */
00746     __HAL_UNLOCK(hsai);
00747
00748     return HAL_OK;
00749   }
00750   else
00751   {
00752     return HAL_BUSY;
00753   }
00754 }
00755
00756 /**
00757   * @brief  Receive an amount of data in blocking mode.
00758   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00759   *                the configuration information for SAI module.
00760   * @param  pData: Pointer to data buffer
00761   * @param  Size: Amount of data to be received
00762   * @param  Timeout: Timeout duration
00763   * @retval HAL status
00764   */
00765 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00766 {
00767   uint32_t tickstart = HAL_GetTick();
00768
00769   if((pData == NULL ) || (Size == 0))
00770   {
00771     return  HAL_ERROR;
00772   }
00773
00774   if(hsai->State == HAL_SAI_STATE_READY)
00775   {
00776     /* Process Locked */
00777     __HAL_LOCK(hsai);
00778
00779     hsai->pBuffPtr = pData;
00780     hsai->XferSize = Size;
00781     hsai->XferCount = Size;
00782     hsai->State = HAL_SAI_STATE_BUSY_RX;
00783     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00784
00785     /* Check if the SAI is already enabled */
00786     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00787     {
00788       /* Enable SAI peripheral */
00789       __HAL_SAI_ENABLE(hsai);
00790     }
00791
00792     /* Receive data */
00793     while(hsai->XferCount > 0)
00794     {
00795       if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
00796       {
00797         if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00798         {
00799           (*hsai->pBuffPtr++) = hsai->Instance->DR;
00800         }
00801         else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00802         {
00803           *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;
00804           hsai->pBuffPtr+= 2;
00805         }
00806         else
00807         {
00808           *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;
00809           hsai->pBuffPtr+= 4;
00810         }
00811         hsai->XferCount--;
00812       }
00813       else
00814       {
00815         /* Check for the Timeout */
00816         if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)))
00817         {
00818           /* Update error code */
00819           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
00820
00821           /* Clear all the flags */
00822           hsai->Instance->CLRFR = 0xFFFFFFFFU;
00823
00824           /* Disable SAI peripheral */
00825           SAI_Disable(hsai);
00826
00827           /* Flush the fifo */
00828           SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00829
00830           /* Change the SAI state */
00831           hsai->State = HAL_SAI_STATE_READY;
00832
00833           /* Process Unlocked */
00834           __HAL_UNLOCK(hsai);
00835
00836           return HAL_ERROR;
00837         }
00838       }
00839     }
00840
00841     hsai->State = HAL_SAI_STATE_READY;
00842
00843     /* Process Unlocked */
00844     __HAL_UNLOCK(hsai);
00845
00846     return HAL_OK;
00847   }
00848   else
00849   {
00850     return HAL_BUSY;
00851   }
00852 }
00853
00854 /**
00855   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
00856   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00857   *                the configuration information for SAI module.
00858   * @param  pData: Pointer to data buffer
00859   * @param  Size: Amount of data to be sent
00860   * @retval HAL status
00861   */
00862 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
00863 {
00864   if((pData == NULL) || (Size == 0))
00865   {
00866     return  HAL_ERROR;
00867   }
00868
00869   if(hsai->State == HAL_SAI_STATE_READY)
00870   {
00871     /* Process Locked */
00872     __HAL_LOCK(hsai);
00873
00874     hsai->pBuffPtr = pData;
00875     hsai->XferSize = Size;
00876     hsai->XferCount = Size;
00877     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00878     hsai->State = HAL_SAI_STATE_BUSY_TX;
00879
00880     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00881     {
00882       hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
00883     }
00884     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00885     {
00886       hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
00887     }
00888     else
00889     {
00890       hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
00891     }
00892
00893     /* Fill the fifo before starting the communication */
00894     SAI_FillFifo(hsai);
00895
00896     /* Enable FRQ and OVRUDR interrupts */
00897     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
00898
00899     /* Check if the SAI is already enabled */
00900     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00901     {
00902       /* Enable SAI peripheral */
00903       __HAL_SAI_ENABLE(hsai);
00904     }
00905     /* Process Unlocked */
00906     __HAL_UNLOCK(hsai);
00907
00908     return HAL_OK;
00909   }
00910   else
00911   {
00912     return HAL_BUSY;
00913   }
00914 }
00915
00916 /**
00917   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
00918   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00919   *                the configuration information for SAI module.
00920   * @param  pData: Pointer to data buffer
00921   * @param  Size: Amount of data to be received
00922   * @retval HAL status
00923   */
00924 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
00925 {
00926   if((pData == NULL) || (Size == 0))
00927   {
00928     return  HAL_ERROR;
00929   }
00930
00931   if(hsai->State == HAL_SAI_STATE_READY)
00932   {
00933     /* Process Locked */
00934     __HAL_LOCK(hsai);
00935
00936     hsai->pBuffPtr = pData;
00937     hsai->XferSize = Size;
00938     hsai->XferCount = Size;
00939     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00940     hsai->State = HAL_SAI_STATE_BUSY_RX;
00941
00942     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00943     {
00944       hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
00945     }
00946     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
00947     {
00948       hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
00949     }
00950     else
00951     {
00952       hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
00953     }
00954
00955     /* Enable TXE and OVRUDR interrupts */
00956     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
00957
00958     /* Check if the SAI is already enabled */
00959     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
00960     {
00961       /* Enable SAI peripheral */
00962       __HAL_SAI_ENABLE(hsai);
00963     }
00964
00965     /* Process Unlocked */
00966     __HAL_UNLOCK(hsai);
00967
00968     return HAL_OK;
00969   }
00970   else
00971   {
00972     return HAL_BUSY;
00973   }
00974 }
00975
00976 /**
00977   * @brief Pause the audio stream playing from the Media.
00978   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00979   *                the configuration information for SAI module.
00980   * @retval HAL status
00981   */
00982 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
00983 {
00984   /* Process Locked */
00985   __HAL_LOCK(hsai);
00986
00987   /* Pause the audio file playing by disabling the SAI DMA requests */
00988   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
00989
00990   /* Process Unlocked */
00991   __HAL_UNLOCK(hsai);
00992
00993   return HAL_OK;
00994 }
00995
00996 /**
00997   * @brief Resume the audio stream playing from the Media.
00998   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
00999   *                the configuration information for SAI module.
01000   * @retval HAL status
01001   */
01002 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
01003 {
01004   /* Process Locked */
01005   __HAL_LOCK(hsai);
01006
01007   /* Enable the SAI DMA requests */
01008   hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01009
01010   /* If the SAI peripheral is still not enabled, enable it */
01011   if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01012   {
01013     /* Enable SAI peripheral */
01014     __HAL_SAI_ENABLE(hsai);
01015   }
01016
01017   /* Process Unlocked */
01018   __HAL_UNLOCK(hsai);
01019
01020   return HAL_OK;
01021 }
01022
01023 /**
01024   * @brief Stop the audio stream playing from the Media.
01025   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01026   *                the configuration information for SAI module.
01027   * @retval HAL status
01028   */
01029 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
01030 {
01031   /* Process Locked */
01032   __HAL_LOCK(hsai);
01033
01034   /* Disable the SAI DMA request */
01035   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01036
01037   /* Abort the SAI DMA Streams */
01038   if(hsai->hdmatx != NULL)
01039   {
01040     if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
01041     {
01042       return HAL_ERROR;
01043     }
01044   }
01045
01046   if(hsai->hdmarx != NULL)
01047   {
01048     if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
01049     {
01050       return HAL_ERROR;
01051     }
01052   }
01053
01054   /* Disable SAI peripheral */
01055   SAI_Disable(hsai);
01056
01057   hsai->State = HAL_SAI_STATE_READY;
01058
01059   /* Process Unlocked */
01060   __HAL_UNLOCK(hsai);
01061
01062   return HAL_OK;
01063 }
01064
01065 /**
01066   * @brief Abort the current transfer and disable the SAI.
01067   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01068   *                the configuration information for SAI module.
01069   * @retval HAL status
01070   */
01071 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
01072 {
01073   /* Process Locked */
01074   __HAL_LOCK(hsai);
01075
01076   /* Check SAI DMA is enabled or not */
01077   if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01078   {
01079     /* Disable the SAI DMA request */
01080     hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01081
01082     /* Abort the SAI DMA Streams */
01083     if(hsai->hdmatx != NULL)
01084     {
01085       if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
01086       {
01087         return HAL_ERROR;
01088       }
01089     }
01090
01091     if(hsai->hdmarx != NULL)
01092     {
01093       if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
01094       {
01095         return HAL_ERROR;
01096       }
01097     }
01098   }
01099
01100   /* Disabled All interrupt and clear all the flag */
01101   hsai->Instance->IMR = 0;
01102   hsai->Instance->CLRFR = 0xFFFFFFFFU;
01103
01104   /* Disable SAI peripheral */
01105   SAI_Disable(hsai);
01106
01107   /* Flush the fifo */
01108   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01109
01110   hsai->State = HAL_SAI_STATE_READY;
01111
01112   /* Process Unlocked */
01113   __HAL_UNLOCK(hsai);
01114
01115   return HAL_OK;
01116 }
01117
01118 /**
01119   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01120   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01121   *                the configuration information for SAI module.
01122   * @param  pData: Pointer to data buffer
01123   * @param  Size: Amount of data to be sent
01124   * @retval HAL status
01125   */
01126 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01127 {
01128   if((pData == NULL) || (Size == 0))
01129   {
01130     return  HAL_ERROR;
01131   }
01132
01133   if(hsai->State == HAL_SAI_STATE_READY)
01134   {
01135     /* Process Locked */
01136     __HAL_LOCK(hsai);
01137
01138     hsai->pBuffPtr = pData;
01139     hsai->XferSize = Size;
01140     hsai->XferCount = Size;
01141     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01142     hsai->State = HAL_SAI_STATE_BUSY_TX;
01143
01144     /* Set the SAI Tx DMA Half transfer complete callback */
01145     hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
01146
01147     /* Set the SAI TxDMA transfer complete callback */
01148     hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
01149
01150     /* Set the DMA error callback */
01151     hsai->hdmatx->XferErrorCallback = SAI_DMAError;
01152
01153     /* Set the DMA Tx abort callback */
01154     hsai->hdmatx->XferAbortCallback = NULL;
01155
01156     /* Enable the Tx DMA Stream */
01157     if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)
01158     {
01159       __HAL_UNLOCK(hsai);
01160       return  HAL_ERROR;
01161     }
01162
01163     /* Check if the SAI is already enabled */
01164     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01165     {
01166       /* Enable SAI peripheral */
01167       __HAL_SAI_ENABLE(hsai);
01168     }
01169
01170     /* Enable the interrupts for error handling */
01171     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01172
01173     /* Enable SAI Tx DMA Request */
01174     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01175
01176     /* Process Unlocked */
01177     __HAL_UNLOCK(hsai);
01178
01179     return HAL_OK;
01180   }
01181   else
01182   {
01183     return HAL_BUSY;
01184   }
01185 }
01186
01187 /**
01188   * @brief  Receive an amount of data in non-blocking mode with DMA.
01189   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01190   *                the configuration information for SAI module.
01191   * @param  pData: Pointer to data buffer
01192   * @param  Size: Amount of data to be received
01193   * @retval HAL status
01194   */
01195 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01196 {
01197
01198   if((pData == NULL) || (Size == 0))
01199   {
01200     return  HAL_ERROR;
01201   }
01202
01203   if(hsai->State == HAL_SAI_STATE_READY)
01204   {
01205     /* Process Locked */
01206     __HAL_LOCK(hsai);
01207
01208     hsai->pBuffPtr = pData;
01209     hsai->XferSize = Size;
01210     hsai->XferCount = Size;
01211     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01212     hsai->State = HAL_SAI_STATE_BUSY_RX;
01213
01214     /* Set the SAI Rx DMA Half transfer complete callback */
01215     hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
01216
01217     /* Set the SAI Rx DMA transfer complete callback */
01218     hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
01219
01220     /* Set the DMA error callback */
01221     hsai->hdmarx->XferErrorCallback = SAI_DMAError;
01222
01223     /* Set the DMA Rx abort callback */
01224     hsai->hdmarx->XferAbortCallback = NULL;
01225
01226     /* Enable the Rx DMA Stream */
01227     if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)
01228     {
01229       __HAL_UNLOCK(hsai);
01230       return  HAL_ERROR;
01231     }
01232
01233     /* Check if the SAI is already enabled */
01234     if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
01235     {
01236       /* Enable SAI peripheral */
01237       __HAL_SAI_ENABLE(hsai);
01238     }
01239
01240     /* Enable the interrupts for error handling */
01241     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01242
01243     /* Enable SAI Rx DMA Request */
01244     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01245
01246     /* Process Unlocked */
01247     __HAL_UNLOCK(hsai);
01248
01249     return HAL_OK;
01250   }
01251   else
01252   {
01253     return HAL_BUSY;
01254   }
01255 }
01256
01257 /**
01258   * @brief  Enable the Tx mute mode.
01259   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01260   *                the configuration information for SAI module.
01261   * @param  val:  value sent during the mute @ref SAI_Block_Mute_Value
01262   * @retval HAL status
01263   */
01264 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
01265 {
01266   assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
01267
01268   if(hsai->State != HAL_SAI_STATE_RESET)
01269   {
01270     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01271     SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
01272     return HAL_OK;
01273   }
01274   return HAL_ERROR;
01275 }
01276
01277 /**
01278   * @brief  Disable the Tx mute mode.
01279   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01280   *                the configuration information for SAI module.
01281   * @retval HAL status
01282   */
01283 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
01284 {
01285   if(hsai->State != HAL_SAI_STATE_RESET)
01286   {
01287     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01288     return HAL_OK;
01289   }
01290   return HAL_ERROR;
01291 }
01292
01293 /**
01294   * @brief  Enable the Rx mute detection.
01295   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01296   *                the configuration information for SAI module.
01297   * @param  callback: function called when the mute is detected.
01298   * @param  counter: number a data before mute detection max 63.
01299   * @retval HAL status
01300   */
01301 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
01302 {
01303   assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
01304
01305   if(hsai->State != HAL_SAI_STATE_RESET)
01306   {
01307     /* set the mute counter */
01308     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
01309     SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));
01310     hsai->mutecallback = callback;
01311     /* enable the IT interrupt */
01312     __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
01313     return HAL_OK;
01314   }
01315   return HAL_ERROR;
01316 }
01317
01318 /**
01319   * @brief  Disable the Rx mute detection.
01320   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01321   *                the configuration information for SAI module.
01322   * @retval HAL status
01323   */
01324 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
01325 {
01326   if(hsai->State != HAL_SAI_STATE_RESET)
01327   {
01328     /* set the mutecallback to NULL */
01329     hsai->mutecallback = (SAIcallback)NULL;
01330     /* enable the IT interrupt */
01331     __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
01332     return HAL_OK;
01333   }
01334   return HAL_ERROR;
01335 }
01336
01337 /**
01338   * @brief  Handle SAI interrupt request.
01339   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01340   *                the configuration information for SAI module.
01341   * @retval None
01342   */
01343 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
01344 {
01345   if(hsai->State != HAL_SAI_STATE_RESET)
01346   {
01347     uint32_t itflags = hsai->Instance->SR;
01348     uint32_t itsources = hsai->Instance->IMR;
01349     uint32_t cr1config = hsai->Instance->CR1;
01350     uint32_t tmperror;
01351
01352     /* SAI Fifo request interrupt occured ------------------------------------*/
01353     if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
01354     {
01355       hsai->InterruptServiceRoutine(hsai);
01356     }
01357     /* SAI Overrun error interrupt occurred ----------------------------------*/
01358     else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
01359     {
01360       /* Clear the SAI Overrun flag */
01361       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01362       /* Get the SAI error code */
01363       tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
01364       /* Change the SAI error code */
01365       hsai->ErrorCode |= tmperror;
01366       /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01367       HAL_SAI_ErrorCallback(hsai);
01368     }
01369     /* SAI mutedet interrupt occurred ----------------------------------*/
01370     else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
01371     {
01372       /* Clear the SAI mutedet flag */
01373       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
01374       /* call the call back function */
01375       if(hsai->mutecallback != (SAIcallback)NULL)
01376       {
01377         /* inform the user that an RX mute event has been detected */
01378         hsai->mutecallback();
01379       }
01380     }
01381     /* SAI AFSDET interrupt occurred ----------------------------------*/
01382     else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
01383     {
01384       /* Change the SAI error code */
01385       hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
01386
01387       /* Check SAI DMA is enabled or not */
01388       if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01389       {
01390         /* Abort the SAI DMA Streams */
01391         if(hsai->hdmatx != NULL)
01392         {
01393           /* Set the DMA Tx abort callback */
01394           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01395
01396           /* Abort DMA in IT mode */
01397           HAL_DMA_Abort_IT(hsai->hdmatx);
01398         }
01399         else if(hsai->hdmarx != NULL)
01400         {
01401           /* Set the DMA Rx abort callback */
01402           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01403
01404           /* Abort DMA in IT mode */
01405           HAL_DMA_Abort_IT(hsai->hdmarx);
01406         }
01407       }
01408       else
01409       {
01410         /* Abort SAI */
01411         HAL_SAI_Abort(hsai);
01412
01413         /* Set error callback */
01414         HAL_SAI_ErrorCallback(hsai);
01415       }
01416     }
01417     /* SAI LFSDET interrupt occurred ----------------------------------*/
01418     else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
01419     {
01420       /* Change the SAI error code */
01421       hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
01422
01423       /* Check SAI DMA is enabled or not */
01424       if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01425       {
01426         /* Abort the SAI DMA Streams */
01427         if(hsai->hdmatx != NULL)
01428         {
01429           /* Set the DMA Tx abort callback */
01430           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01431
01432           /* Abort DMA in IT mode */
01433           HAL_DMA_Abort_IT(hsai->hdmatx);
01434         }
01435         else if(hsai->hdmarx != NULL)
01436         {
01437           /* Set the DMA Rx abort callback */
01438           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01439
01440           /* Abort DMA in IT mode */
01441           HAL_DMA_Abort_IT(hsai->hdmarx);
01442         }
01443       }
01444       else
01445       {
01446         /* Abort SAI */
01447         HAL_SAI_Abort(hsai);
01448
01449         /* Set error callback */
01450         HAL_SAI_ErrorCallback(hsai);
01451       }
01452     }
01453     /* SAI WCKCFG interrupt occurred ----------------------------------*/
01454     else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
01455     {
01456       /* Change the SAI error code */
01457       hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
01458
01459       /* Check SAI DMA is enabled or not */
01460       if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01461       {
01462         /* Abort the SAI DMA Streams */
01463         if(hsai->hdmatx != NULL)
01464         {
01465           /* Set the DMA Tx abort callback */
01466           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01467
01468           /* Abort DMA in IT mode */
01469           HAL_DMA_Abort_IT(hsai->hdmatx);
01470         }
01471         else if(hsai->hdmarx != NULL)
01472         {
01473           /* Set the DMA Rx abort callback */
01474           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01475
01476           /* Abort DMA in IT mode */
01477           HAL_DMA_Abort_IT(hsai->hdmarx);
01478         }
01479       }
01480       else
01481       {
01482         /* If WCKCFG occurs, SAI audio block is automatically disabled */
01483         /* Disable all interrupts and clear all flags */
01484         hsai->Instance->IMR = 0U;
01485         hsai->Instance->CLRFR = 0xFFFFFFFFU;
01486         /* Set the SAI state to ready to be able to start again the process */
01487         hsai->State = HAL_SAI_STATE_READY;
01488
01489         /* Initialize XferCount */
01490         hsai->XferCount = 0U;
01491
01492         /* SAI error Callback */
01493         HAL_SAI_ErrorCallback(hsai);
01494       }
01495     }
01496     /* SAI CNRDY interrupt occurred ----------------------------------*/
01497     else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
01498     {
01499       /* Clear the SAI CNRDY flag */
01500       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
01501       /* Change the SAI error code */
01502       hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
01503       /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01504       HAL_SAI_ErrorCallback(hsai);
01505     }
01506     else
01507     {
01508       /* Nothing to do */
01509     }
01510   }
01511 }
01512
01513 /**
01514   * @brief Tx Transfer completed callback.
01515   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01516   *                the configuration information for SAI module.
01517   * @retval None
01518   */
01519 __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
01520 {
01521   /* Prevent unused argument(s) compilation warning */
01522   UNUSED(hsai);
01523
01524   /* NOTE : This function should not be modified, when the callback is needed,
01525             the HAL_SAI_TxCpltCallback could be implemented in the user file
01526    */
01527 }
01528
01529 /**
01530   * @brief Tx Transfer Half completed callback.
01531   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01532   *                the configuration information for SAI module.
01533   * @retval None
01534   */
01535 __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
01536 {
01537   /* Prevent unused argument(s) compilation warning */
01538   UNUSED(hsai);
01539
01540   /* NOTE : This function should not be modified, when the callback is needed,
01541             the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
01542    */
01543 }
01544
01545 /**
01546   * @brief Rx Transfer completed callback.
01547   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01548   *                the configuration information for SAI module.
01549   * @retval None
01550   */
01551 __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
01552 {
01553   /* Prevent unused argument(s) compilation warning */
01554   UNUSED(hsai);
01555
01556   /* NOTE : This function should not be modified, when the callback is needed,
01557             the HAL_SAI_RxCpltCallback could be implemented in the user file
01558    */
01559 }
01560
01561 /**
01562   * @brief Rx Transfer half completed callback.
01563   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01564   *                the configuration information for SAI module.
01565   * @retval None
01566   */
01567 __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
01568 {
01569   /* Prevent unused argument(s) compilation warning */
01570   UNUSED(hsai);
01571
01572   /* NOTE : This function should not be modified, when the callback is needed,
01573             the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
01574    */
01575 }
01576
01577 /**
01578   * @brief SAI error callback.
01579   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01580   *                the configuration information for SAI module.
01581   * @retval None
01582   */
01583 __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
01584 {
01585   /* Prevent unused argument(s) compilation warning */
01586   UNUSED(hsai);
01587
01588   /* NOTE : This function should not be modified, when the callback is needed,
01589             the HAL_SAI_ErrorCallback could be implemented in the user file
01590    */
01591 }
01592
01593 /**
01594   * @}
01595   */
01596
01597
01598 /** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
01599  *  @brief    Peripheral State functions
01600  *
01601 @verbatim
01602   ===============================================================================
01603                 ##### Peripheral State and Errors functions #####
01604   ===============================================================================
01605   [..]
01606     This subsection permits to get in run-time the status of the peripheral
01607     and the data flow.
01608
01609 @endverbatim
01610   * @{
01611   */
01612
01613 /**
01614   * @brief  Return the SAI handle state.
01615   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01616   *                the configuration information for SAI module.
01617   * @retval HAL state
01618   */
01619 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
01620 {
01621   return hsai->State;
01622 }
01623
01624 /**
01625 * @brief  Return the SAI error code.
01626 * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01627   *              the configuration information for the specified SAI Block.
01628 * @retval SAI Error Code
01629 */
01630 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
01631 {
01632   return hsai->ErrorCode;
01633 }
01634 /**
01635   * @}
01636   */
01637
01638 /**
01639   * @}
01640   */
01641
01642 /** @addtogroup SAI_Private_Functions
01643  *  @brief      Private functions
01644   * @{
01645   */
01646
01647 /**
01648   * @brief  Initialize the SAI I2S protocol according to the specified parameters
01649   *         in the SAI_InitTypeDef and create the associated handle.
01650   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01651   *                the configuration information for SAI module.
01652   * @param  protocol: one of the supported protocol.
01653   * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
01654   *                the configuration information for SAI module.
01655   * @param  nbslot: number of slot minimum value is 2 and max is 16.
01656   *                    the value must be a multiple of 2.
01657   * @retval HAL status
01658   */
01659 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
01660 {
01661   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
01662   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
01663   /* Compute ClockStrobing according AudioMode */
01664   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01665   { /* Transmit */
01666     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
01667   }
01668   else
01669   { /* Receive */
01670     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
01671   }
01672   hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;
01673   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
01674   hsai->SlotInit.FirstBitOffset  = 0;
01675   hsai->SlotInit.SlotNumber      = nbslot;
01676
01677   /* in IS2 the number of slot must be even */
01678   if((nbslot & 0x1) != 0 )
01679   {
01680     return HAL_ERROR;
01681   }
01682
01683   switch(protocol)
01684   {
01685   case SAI_I2S_STANDARD :
01686     hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
01687     hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;
01688     break;
01689   case SAI_I2S_MSBJUSTIFIED :
01690   case SAI_I2S_LSBJUSTIFIED :
01691     hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
01692     hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;
01693     break;
01694   default :
01695     return HAL_ERROR;
01696   }
01697
01698   /* Frame definition */
01699   switch(datasize)
01700   {
01701   case SAI_PROTOCOL_DATASIZE_16BIT:
01702     hsai->Init.DataSize = SAI_DATASIZE_16;
01703     hsai->FrameInit.FrameLength = 32*(nbslot/2);
01704     hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2);
01705     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
01706     break;
01707   case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
01708     hsai->Init.DataSize = SAI_DATASIZE_16;
01709     hsai->FrameInit.FrameLength = 64*(nbslot/2);
01710     hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
01711     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01712     break;
01713   case SAI_PROTOCOL_DATASIZE_24BIT:
01714     hsai->Init.DataSize = SAI_DATASIZE_24;
01715     hsai->FrameInit.FrameLength = 64*(nbslot/2);
01716     hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
01717     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01718     break;
01719   case SAI_PROTOCOL_DATASIZE_32BIT:
01720     hsai->Init.DataSize = SAI_DATASIZE_32;
01721     hsai->FrameInit.FrameLength = 64*(nbslot/2);
01722     hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);
01723     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01724     break;
01725   default :
01726     return HAL_ERROR;
01727   }
01728   if(protocol == SAI_I2S_LSBJUSTIFIED)
01729   {
01730     if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
01731     {
01732       hsai->SlotInit.FirstBitOffset = 16;
01733     }
01734     if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
01735     {
01736       hsai->SlotInit.FirstBitOffset = 8;
01737     }
01738   }
01739   return HAL_OK;
01740 }
01741
01742 /**
01743   * @brief  Initialize the SAI PCM protocol according to the specified parameters
01744   *         in the SAI_InitTypeDef and create the associated handle.
01745   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01746   *                the configuration information for SAI module.
01747   * @param  protocol: one of the supported protocol
01748   * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize
01749   * @param  nbslot: number of slot minimum value is 1 and the max is 16.
01750   * @retval HAL status
01751   */
01752 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
01753 {
01754   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
01755   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
01756   /* Compute ClockStrobing according AudioMode */
01757   if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01758   { /* Transmit */
01759     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
01760   }
01761   else
01762   { /* Receive */
01763     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
01764   }
01765   hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;
01766   hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;
01767   hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;
01768   hsai->SlotInit.FirstBitOffset  = 0;
01769   hsai->SlotInit.SlotNumber      = nbslot;
01770   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
01771
01772   switch(protocol)
01773   {
01774   case SAI_PCM_SHORT :
01775     hsai->FrameInit.ActiveFrameLength = 1;
01776     break;
01777   case SAI_PCM_LONG :
01778     hsai->FrameInit.ActiveFrameLength = 13;
01779     break;
01780   default :
01781     return HAL_ERROR;
01782   }
01783
01784   switch(datasize)
01785   {
01786   case SAI_PROTOCOL_DATASIZE_16BIT:
01787     hsai->Init.DataSize = SAI_DATASIZE_16;
01788     hsai->FrameInit.FrameLength = 16 * nbslot;
01789     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
01790     break;
01791   case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
01792     hsai->Init.DataSize = SAI_DATASIZE_16;
01793     hsai->FrameInit.FrameLength = 32 * nbslot;
01794     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01795     break;
01796   case SAI_PROTOCOL_DATASIZE_24BIT :
01797     hsai->Init.DataSize = SAI_DATASIZE_24;
01798     hsai->FrameInit.FrameLength = 32 * nbslot;
01799     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01800     break;
01801   case SAI_PROTOCOL_DATASIZE_32BIT:
01802     hsai->Init.DataSize = SAI_DATASIZE_32;
01803     hsai->FrameInit.FrameLength = 32 * nbslot;
01804     hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
01805     break;
01806   default :
01807     return HAL_ERROR;
01808   }
01809
01810   return HAL_OK;
01811 }
01812
01813 /**
01814   * @brief  Fill the fifo.
01815   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01816   *                the configuration information for SAI module.
01817   * @retval None
01818   */
01819 static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
01820 {
01821   /* fill the fifo with data before to enabled the SAI */
01822   while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0))
01823   {
01824     if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01825     {
01826       hsai->Instance->DR = (*hsai->pBuffPtr++);
01827     }
01828     else if(hsai->Init.DataSize <= SAI_DATASIZE_16)
01829     {
01830       hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
01831       hsai->pBuffPtr+= 2;
01832     }
01833     else
01834     {
01835       hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
01836       hsai->pBuffPtr+= 4;
01837     }
01838     hsai->XferCount--;
01839   }
01840 }
01841
01842 /**
01843   * @brief  Return the interrupt flag to set according the SAI setup.
01844   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01845   *                the configuration information for SAI module.
01846   * @param  mode: SAI_MODE_DMA or SAI_MODE_IT
01847   * @retval the list of the IT flag to enable
01848  */
01849 static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
01850 {
01851   uint32_t tmpIT = SAI_IT_OVRUDR;
01852
01853   if(mode == SAI_MODE_IT)
01854   {
01855     tmpIT|= SAI_IT_FREQ;
01856   }
01857
01858   if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
01859     ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
01860   {
01861     tmpIT|= SAI_IT_CNRDY;
01862   }
01863
01864   if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
01865   {
01866     tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;
01867   }
01868   else
01869   {
01870     /* hsai has been configured in master mode */
01871     tmpIT|= SAI_IT_WCKCFG;
01872   }
01873   return tmpIT;
01874 }
01875
01876 /**
01877   * @brief  Disable the SAI and wait for the disabling.
01878   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01879   *                the configuration information for SAI module.
01880   * @retval None
01881   */
01882 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
01883 {
01884   uint32_t tickstart = HAL_GetTick();
01885   HAL_StatusTypeDef status = HAL_OK;
01886
01887   __HAL_SAI_DISABLE(hsai);
01888   while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET)
01889   {
01890     /* Check for the Timeout */
01891     if((HAL_GetTick() - tickstart) > SAI_DEFAULT_TIMEOUT)
01892     {
01893       /* Update error code */
01894       hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01895
01896       return HAL_TIMEOUT;
01897     }
01898   }
01899   return status;
01900 }
01901
01902 /**
01903   * @brief  Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
01904   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01905   *                the configuration information for SAI module.
01906   * @retval None
01907   */
01908 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
01909 {
01910   if(hsai->XferCount == 0)
01911   {
01912     /* Handle the end of the transmission */
01913     /* Disable FREQ and OVRUDR interrupts */
01914     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01915     hsai->State = HAL_SAI_STATE_READY;
01916     HAL_SAI_TxCpltCallback(hsai);
01917   }
01918   else
01919   {
01920     /* Write data on DR register */
01921     hsai->Instance->DR = (*hsai->pBuffPtr++);
01922     hsai->XferCount--;
01923   }
01924 }
01925
01926 /**
01927   * @brief  Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
01928   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01929   *                the configuration information for SAI module.
01930   * @retval None
01931   */
01932 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
01933 {
01934   if(hsai->XferCount == 0)
01935   {
01936     /* Handle the end of the transmission */
01937     /* Disable FREQ and OVRUDR interrupts */
01938     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01939     hsai->State = HAL_SAI_STATE_READY;
01940     HAL_SAI_TxCpltCallback(hsai);
01941   }
01942   else
01943   {
01944     /* Write data on DR register */
01945     hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
01946     hsai->pBuffPtr+=2;
01947     hsai->XferCount--;
01948   }
01949 }
01950
01951 /**
01952   * @brief  Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
01953   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01954   *                the configuration information for SAI module.
01955   * @retval None
01956   */
01957 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
01958 {
01959   if(hsai->XferCount == 0)
01960   {
01961     /* Handle the end of the transmission */
01962     /* Disable FREQ and OVRUDR interrupts */
01963     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01964     hsai->State = HAL_SAI_STATE_READY;
01965     HAL_SAI_TxCpltCallback(hsai);
01966   }
01967   else
01968   {
01969     /* Write data on DR register */
01970     hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
01971     hsai->pBuffPtr+=4;
01972     hsai->XferCount--;
01973   }
01974 }
01975
01976 /**
01977   * @brief  Rx Handler for Receive in Interrupt mode 8-Bit transfer.
01978   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
01979   *                the configuration information for SAI module.
01980   * @retval None
01981   */
01982 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
01983 {
01984   /* Receive data */
01985   (*hsai->pBuffPtr++) = hsai->Instance->DR;
01986   hsai->XferCount--;
01987
01988   /* Check end of the transfer */
01989   if(hsai->XferCount == 0)
01990   {
01991     /* Disable TXE and OVRUDR interrupts */
01992     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01993
01994     /* Clear the SAI Overrun flag */
01995     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01996
01997     hsai->State = HAL_SAI_STATE_READY;
01998     HAL_SAI_RxCpltCallback(hsai);
01999   }
02000 }
02001
02002 /**
02003   * @brief  Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
02004   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
02005   *                the configuration information for SAI module.
02006   * @retval None
02007   */
02008 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
02009 {
02010   /* Receive data */
02011   *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;
02012   hsai->pBuffPtr+=2;
02013   hsai->XferCount--;
02014
02015   /* Check end of the transfer */
02016   if(hsai->XferCount == 0)
02017   {
02018     /* Disable TXE and OVRUDR interrupts */
02019     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02020
02021     /* Clear the SAI Overrun flag */
02022     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02023
02024     hsai->State = HAL_SAI_STATE_READY;
02025     HAL_SAI_RxCpltCallback(hsai);
02026   }
02027 }
02028 /**
02029   * @brief  Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
02030   * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
02031   *                the configuration information for SAI module.
02032   * @retval None
02033   */
02034 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
02035 {
02036   /* Receive data */
02037   *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;
02038   hsai->pBuffPtr+=4;
02039   hsai->XferCount--;
02040
02041   /* Check end of the transfer */
02042   if(hsai->XferCount == 0)
02043   {
02044     /* Disable TXE and OVRUDR interrupts */
02045     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02046
02047     /* Clear the SAI Overrun flag */
02048     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02049
02050     hsai->State = HAL_SAI_STATE_READY;
02051     HAL_SAI_RxCpltCallback(hsai);
02052   }
02053 }
02054
02055 /**
02056   * @brief  DMA SAI transmit process complete callback.
02057   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02058   *                the configuration information for the specified DMA module.
02059   * @retval None
02060   */
02061 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
02062 {
02063   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
02064
02065   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
02066   {
02067     hsai->XferCount = 0;
02068
02069     /* Disable SAI Tx DMA Request */
02070     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
02071
02072     /* Stop the interrupts error handling */
02073     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
02074
02075     hsai->State= HAL_SAI_STATE_READY;
02076   }
02077   HAL_SAI_TxCpltCallback(hsai);
02078 }
02079
02080 /**
02081   * @brief  DMA SAI transmit process half complete callback.
02082   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02083   *                the configuration information for the specified DMA module.
02084   * @retval None
02085   */
02086 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02087 {
02088   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02089
02090   HAL_SAI_TxHalfCpltCallback(hsai);
02091 }
02092
02093 /**
02094   * @brief  DMA SAI receive process complete callback.
02095   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02096   *                the configuration information for the specified DMA module.
02097   * @retval None
02098   */
02099 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
02100 {
02101   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02102   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
02103   {
02104     /* Disable Rx DMA Request */
02105     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
02106     hsai->XferCount = 0;
02107
02108     /* Stop the interrupts error handling */
02109     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
02110
02111     hsai->State = HAL_SAI_STATE_READY;
02112   }
02113   HAL_SAI_RxCpltCallback(hsai);
02114 }
02115
02116 /**
02117   * @brief  DMA SAI receive process half complete callback
02118   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02119   *                the configuration information for the specified DMA module.
02120   * @retval None
02121   */
02122 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02123 {
02124   SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02125
02126   HAL_SAI_RxHalfCpltCallback(hsai);
02127 }
02128 /**
02129   * @brief  DMA SAI communication error callback.
02130   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02131   *                the configuration information for the specified DMA module.
02132   * @retval None
02133   */
02134 static void SAI_DMAError(DMA_HandleTypeDef *hdma)
02135 {
02136   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02137
02138   /* Set SAI error code */
02139   hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
02140
02141   /* Disable the SAI DMA request */
02142   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
02143
02144   /* Disable SAI peripheral */
02145   SAI_Disable(hsai);
02146
02147   /* Set the SAI state ready to be able to start again the process */
02148   hsai->State = HAL_SAI_STATE_READY;
02149
02150   /* Initialize XferCount */
02151   hsai->XferCount = 0U;
02152
02153   /* SAI error Callback */
02154   HAL_SAI_ErrorCallback(hsai);
02155 }
02156
02157 /**
02158   * @brief  DMA SAI Abort callback.
02159   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02160   *               the configuration information for the specified DMA module.
02161   * @retval None
02162   */
02163 static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
02164 {
02165   SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02166
02167   /* Disable DMA request */
02168   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
02169
02170   /* Disable all interrupts and clear all flags */
02171   hsai->Instance->IMR = 0U;
02172   hsai->Instance->CLRFR = 0xFFFFFFFFU;
02173
02174   if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
02175   {
02176     /* Disable SAI peripheral */
02177     SAI_Disable(hsai);
02178
02179     /* Flush the fifo */
02180     SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
02181   }
02182   /* Set the SAI state to ready to be able to start again the process */
02183   hsai->State = HAL_SAI_STATE_READY;
02184
02185   /* Initialize XferCount */
02186   hsai->XferCount = 0U;
02187
02188   /* SAI error Callback */
02189   HAL_SAI_ErrorCallback(hsai);
02190 }
02191
02192 /**
02193   * @}
02194   */
02195
02196 #endif /* HAL_SAI_MODULE_ENABLED */
02197 /**
02198   * @}
02199   */
02200
02201 /**
02202   * @}
02203   */
02204
02205 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sai.h Source File

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stm32l4xx_hal_sai.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_sai.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SAI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_SAI_H
00040 #define __STM32L4xx_HAL_SAI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SAI
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SAI_Exported_Types SAI Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  HAL State structures definition
00064   */
00065 typedef enum
00066 {
00067   HAL_SAI_STATE_RESET   = 0x00U, /*!< SAI not yet initialized or disabled  */
00068   HAL_SAI_STATE_READY   = 0x01U, /*!< SAI initialized and ready for use    */
00069   HAL_SAI_STATE_BUSY    = 0x02U, /*!< SAI internal process is ongoing      */
00070   HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
00071   HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing    */
00072 }HAL_SAI_StateTypeDef;
00073
00074 /**
00075   * @brief  SAI Callback prototype
00076   */
00077 typedef void (*SAIcallback)(void);
00078
00079 /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
00080   * @brief  SAI Init Structure definition
00081   * @{
00082   */
00083 typedef struct
00084 {
00085   uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
00086                                      This parameter can be a value of @ref SAI_Block_Mode */
00087
00088   uint32_t Synchro;             /*!< Specifies SAI Block synchronization
00089                                      This parameter can be a value of @ref SAI_Block_Synchronization */
00090
00091   uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common
00092                                      for BlockA and BlockB
00093                                      This parameter can be a value of @ref SAI_Block_SyncExt
00094                                      @note: If both audio blocks of same SAI are used, this parameter has
00095                                             to be set to the same value for each audio block */
00096
00097   uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
00098                                      This parameter can be a value of @ref SAI_Block_Output_Drive
00099                                      @note this value has to be set before enabling the audio block
00100                                      but after the audio block configuration. */
00101
00102   uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
00103                                      This parameter can be a value of @ref SAI_Block_NoDivider
00104                                      @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
00105                                             should be aligned to a number equal to a power of 2, from 8 to 256.
00106                                             If bit NODIV in the SAI_xCR1 register is set, the frame length can
00107                                             take any of the values without constraint since the input clock of
00108                                             the audio block should be equal to the bit clock.
00109                                             There is no MCLK_x clock which can be output. */
00110
00111   uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
00112                                      This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
00113
00114   uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
00115                                      This parameter can be a value of @ref SAI_Audio_Frequency */
00116
00117   uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for
00118                                      AudioFrequency the user choice
00119                                      This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
00120
00121   uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
00122                                      This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
00123
00124   uint32_t CompandingMode;      /*!< Specifies the companding mode type.
00125                                      This parameter can be a value of @ref SAI_Block_Companding_Mode */
00126
00127   uint32_t TriState;            /*!< Specifies the companding mode type.
00128                                      This parameter can be a value of @ref SAI_TRIState_Management */
00129
00130   /* This part of the structure is automatically filled if your are using the high level initialisation
00131      function HAL_SAI_InitProtocol */
00132
00133   uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
00134                                  This parameter can be a value of @ref SAI_Block_Protocol */
00135
00136   uint32_t DataSize;        /*!< Specifies the SAI Block data size.
00137                                  This parameter can be a value of @ref SAI_Block_Data_Size */
00138
00139   uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
00140                                  This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
00141
00142   uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
00143                                  This parameter can be a value of @ref SAI_Block_Clock_Strobing */
00144 }SAI_InitTypeDef;
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
00150   * @brief  SAI Frame Init structure definition
00151   * @{
00152   */
00153 typedef struct
00154 {
00155
00156   uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
00157                                     This parameter must be a number between Min_Data = 8 and Max_Data = 256.
00158                                     @note: If master clock MCLK_x pin is declared as an output, the frame length
00159                                            should be aligned to a number equal to power of 2 in order to keep
00160                                            in an audio frame, an integer number of MCLK pulses by bit Clock. */
00161
00162   uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
00163                                     This Parameter specifies the length in number of bit clock (SCK + 1)
00164                                     of the active level of FS signal in audio frame.
00165                                     This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
00166
00167   uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
00168                                     This parameter can be a value of @ref SAI_Block_FS_Definition */
00169
00170   uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
00171                                     This parameter can be a value of @ref SAI_Block_FS_Polarity */
00172
00173   uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
00174                                     This parameter can be a value of @ref SAI_Block_FS_Offset */
00175
00176 }SAI_FrameInitTypeDef;
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
00182   * @brief   SAI Block Slot Init Structure definition
00183   * @{
00184   */
00185 typedef struct
00186 {
00187   uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
00188                                  This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
00189
00190   uint32_t SlotSize;        /*!< Specifies the Slot Size.
00191                                  This parameter can be a value of @ref SAI_Block_Slot_Size */
00192
00193   uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
00194                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
00195
00196   uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
00197                                  This parameter can be a value of @ref SAI_Block_Slot_Active */
00198 }SAI_SlotInitTypeDef;
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
00204   * @brief  SAI handle Structure definition
00205   * @{
00206   */
00207 typedef struct __SAI_HandleTypeDef
00208 {
00209   SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */
00210
00211   SAI_InitTypeDef           Init;         /*!< SAI communication parameters */
00212
00213   SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */
00214
00215   SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */
00216
00217   uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */
00218
00219   uint16_t                  XferSize;     /*!< SAI transfer size */
00220
00221   uint16_t                  XferCount;    /*!< SAI transfer counter */
00222
00223   DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */
00224
00225   DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */
00226
00227   SAIcallback               mutecallback; /*!< SAI mute callback */
00228
00229   void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
00230
00231   HAL_LockTypeDef           Lock;         /*!< SAI locking object */
00232
00233   __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */
00234
00235   __IO uint32_t             ErrorCode;    /*!< SAI Error code */
00236 }SAI_HandleTypeDef;
00237 /**
00238   * @}
00239   */
00240
00241 /**
00242   * @}
00243   */
00244
00245 /* Exported constants --------------------------------------------------------*/
00246
00247 /** @defgroup SAI_Exported_Constants SAI Exported Constants
00248   * @{
00249   */
00250
00251 /** @defgroup SAI_Error_Code SAI Error Code
00252   * @{
00253   */
00254 #define HAL_SAI_ERROR_NONE    ((uint32_t)0x00000000U)  /*!< No error */
00255 #define HAL_SAI_ERROR_OVR     ((uint32_t)0x00000001U)  /*!< Overrun Error */
00256 #define HAL_SAI_ERROR_UDR     ((uint32_t)0x00000002U)  /*!< Underrun error */
00257 #define HAL_SAI_ERROR_AFSDET  ((uint32_t)0x00000004U)  /*!< Anticipated Frame synchronisation detection */
00258 #define HAL_SAI_ERROR_LFSDET  ((uint32_t)0x00000008U)  /*!< Late Frame synchronisation detection */
00259 #define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)  /*!< codec not ready */
00260 #define HAL_SAI_ERROR_WCKCFG  ((uint32_t)0x00000020U)  /*!< Wrong clock configuration */
00261 #define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)  /*!< Timeout error */
00262 #define HAL_SAI_ERROR_DMA     ((uint32_t)0x00000080U)  /*!< DMA error */
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup SAI_Block_SyncExt SAI External synchronisation
00268   * @{
00269   */
00270 #define SAI_SYNCEXT_DISABLE          0
00271 #define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
00272 #define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup SAI_Protocol SAI Supported protocol
00278   * @{
00279   */
00280 #define SAI_I2S_STANDARD      0
00281 #define SAI_I2S_MSBJUSTIFIED  1
00282 #define SAI_I2S_LSBJUSTIFIED  2
00283 #define SAI_PCM_LONG          3
00284 #define SAI_PCM_SHORT         4
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup SAI_Protocol_DataSize SAI protocol data size
00290   * @{
00291   */
00292 #define SAI_PROTOCOL_DATASIZE_16BIT         0
00293 #define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
00294 #define SAI_PROTOCOL_DATASIZE_24BIT         2
00295 #define SAI_PROTOCOL_DATASIZE_32BIT         3
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup SAI_Audio_Frequency SAI Audio Frequency
00301   * @{
00302   */
00303 #define SAI_AUDIO_FREQUENCY_192K          ((uint32_t)192000U)
00304 #define SAI_AUDIO_FREQUENCY_96K           ((uint32_t)96000U)
00305 #define SAI_AUDIO_FREQUENCY_48K           ((uint32_t)48000U)
00306 #define SAI_AUDIO_FREQUENCY_44K           ((uint32_t)44100U)
00307 #define SAI_AUDIO_FREQUENCY_32K           ((uint32_t)32000U)
00308 #define SAI_AUDIO_FREQUENCY_22K           ((uint32_t)22050U)
00309 #define SAI_AUDIO_FREQUENCY_16K           ((uint32_t)16000U)
00310 #define SAI_AUDIO_FREQUENCY_11K           ((uint32_t)11025U)
00311 #define SAI_AUDIO_FREQUENCY_8K            ((uint32_t)8000U)
00312 #define SAI_AUDIO_FREQUENCY_MCKDIV        ((uint32_t)0U)
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup SAI_Block_Mode SAI Block Mode
00318   * @{
00319   */
00320 #define SAI_MODEMASTER_TX         ((uint32_t)0x00000000U)
00321 #define SAI_MODEMASTER_RX         ((uint32_t)SAI_xCR1_MODE_0)
00322 #define SAI_MODESLAVE_TX          ((uint32_t)SAI_xCR1_MODE_1)
00323 #define SAI_MODESLAVE_RX          ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
00324
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup SAI_Block_Protocol SAI Block Protocol
00330   * @{
00331   */
00332 #define SAI_FREE_PROTOCOL                 ((uint32_t)0x00000000U)
00333 #define SAI_SPDIF_PROTOCOL                ((uint32_t)SAI_xCR1_PRTCFG_0)
00334 #define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)
00335 /**
00336   * @}
00337   */
00338
00339 /** @defgroup SAI_Block_Data_Size SAI Block Data Size
00340   * @{
00341   */
00342 #define SAI_DATASIZE_8     ((uint32_t)SAI_xCR1_DS_1)
00343 #define SAI_DATASIZE_10    ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
00344 #define SAI_DATASIZE_16    ((uint32_t)SAI_xCR1_DS_2)
00345 #define SAI_DATASIZE_20    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
00346 #define SAI_DATASIZE_24    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
00347 #define SAI_DATASIZE_32    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
00353   * @{
00354   */
00355 #define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000U)
00356 #define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
00362   * @{
00363   */
00364 #define SAI_CLOCKSTROBING_FALLINGEDGE     0
00365 #define SAI_CLOCKSTROBING_RISINGEDGE      1
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
00371   * @{
00372   */
00373 #define SAI_ASYNCHRONOUS                  0 /*!< Asynchronous */
00374 #define SAI_SYNCHRONOUS                   1 /*!< Synchronous with other block of same SAI */
00375 #define SAI_SYNCHRONOUS_EXT_SAI1          2 /*!< Synchronous with other SAI, SAI1 */
00376 #define SAI_SYNCHRONOUS_EXT_SAI2          3 /*!< Synchronous with other SAI, SAI2 */
00377 /**
00378   * @}
00379   */
00380
00381 /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
00382   * @{
00383   */
00384 #define SAI_OUTPUTDRIVE_DISABLE          ((uint32_t)0x00000000U)
00385 #define SAI_OUTPUTDRIVE_ENABLE           ((uint32_t)SAI_xCR1_OUTDRIV)
00386 /**
00387   * @}
00388   */
00389
00390 /** @defgroup SAI_Block_NoDivider SAI Block NoDivider
00391   * @{
00392   */
00393 #define SAI_MASTERDIVIDER_ENABLE         ((uint32_t)0x00000000U)
00394 #define SAI_MASTERDIVIDER_DISABLE        ((uint32_t)SAI_xCR1_NODIV)
00395 /**
00396   * @}
00397   */
00398
00399
00400 /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
00401   * @{
00402   */
00403 #define SAI_FS_STARTFRAME                 ((uint32_t)0x00000000U)
00404 #define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
00410   * @{
00411   */
00412 #define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000U)
00413 #define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPOL)
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
00419   * @{
00420   */
00421 #define SAI_FS_FIRSTBIT                   ((uint32_t)0x00000000U)
00422 #define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)
00423 /**
00424   * @}
00425   */
00426
00427
00428   /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
00429   * @{
00430   */
00431 #define SAI_SLOTSIZE_DATASIZE             ((uint32_t)0x00000000U)
00432 #define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
00433 #define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
00434 /**
00435   * @}
00436   */
00437
00438 /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
00439   * @{
00440   */
00441 #define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000U)
00442 #define SAI_SLOTACTIVE_0             ((uint32_t)0x00000001U)
00443 #define SAI_SLOTACTIVE_1             ((uint32_t)0x00000002U)
00444 #define SAI_SLOTACTIVE_2             ((uint32_t)0x00000004U)
00445 #define SAI_SLOTACTIVE_3             ((uint32_t)0x00000008U)
00446 #define SAI_SLOTACTIVE_4             ((uint32_t)0x00000010U)
00447 #define SAI_SLOTACTIVE_5             ((uint32_t)0x00000020U)
00448 #define SAI_SLOTACTIVE_6             ((uint32_t)0x00000040U)
00449 #define SAI_SLOTACTIVE_7             ((uint32_t)0x00000080U)
00450 #define SAI_SLOTACTIVE_8             ((uint32_t)0x00000100U)
00451 #define SAI_SLOTACTIVE_9             ((uint32_t)0x00000200U)
00452 #define SAI_SLOTACTIVE_10            ((uint32_t)0x00000400U)
00453 #define SAI_SLOTACTIVE_11            ((uint32_t)0x00000800U)
00454 #define SAI_SLOTACTIVE_12            ((uint32_t)0x00001000U)
00455 #define SAI_SLOTACTIVE_13            ((uint32_t)0x00002000U)
00456 #define SAI_SLOTACTIVE_14            ((uint32_t)0x00004000U)
00457 #define SAI_SLOTACTIVE_15            ((uint32_t)0x00008000U)
00458 #define SAI_SLOTACTIVE_ALL           ((uint32_t)0x0000FFFFU)
00459 /**
00460   * @}
00461   */
00462
00463 /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
00464   * @{
00465   */
00466 #define SAI_STEREOMODE               ((uint32_t)0x00000000U)
00467 #define SAI_MONOMODE                 ((uint32_t)SAI_xCR1_MONO)
00468 /**
00469   * @}
00470   */
00471
00472 /** @defgroup SAI_TRIState_Management SAI TRIState Management
00473   * @{
00474   */
00475 #define SAI_OUTPUT_NOTRELEASED    ((uint32_t)0x00000000U)
00476 #define SAI_OUTPUT_RELEASED       ((uint32_t)SAI_xCR2_TRIS)
00477 /**
00478   * @}
00479   */
00480
00481 /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
00482   * @{
00483   */
00484 #define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000U)
00485 #define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)(SAI_xCR2_FTH_0))
00486 #define SAI_FIFOTHRESHOLD_HF     ((uint32_t)(SAI_xCR2_FTH_1))
00487 #define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
00488 #define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)(SAI_xCR2_FTH_2))
00489 /**
00490   * @}
00491   */
00492
00493 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
00494   * @{
00495   */
00496 #define SAI_NOCOMPANDING                 ((uint32_t)0x00000000U)
00497 #define SAI_ULAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1))
00498 #define SAI_ALAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
00499 #define SAI_ULAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
00500 #define SAI_ALAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
00501 /**
00502   * @}
00503   */
00504
00505 /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
00506   * @{
00507   */
00508 #define SAI_ZERO_VALUE                     ((uint32_t)0x00000000U)
00509 #define SAI_LAST_SENT_VALUE                ((uint32_t)SAI_xCR2_MUTEVAL)
00510 /**
00511   * @}
00512   */
00513
00514 /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
00515   * @{
00516   */
00517 #define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)
00518 #define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)
00519 #define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)
00520 #define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)
00521 #define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)
00522 #define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)
00523 #define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)
00524 /**
00525   * @}
00526   */
00527
00528 /** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
00529   * @{
00530   */
00531 #define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)
00532 #define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)
00533 #define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)
00534 #define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)
00535 #define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)
00536 #define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)
00537 #define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
00543   * @{
00544   */
00545 #define SAI_FIFOSTATUS_EMPTY              ((uint32_t)0x00000000U)
00546 #define SAI_FIFOSTATUS_LESS1QUARTERFULL   ((uint32_t)0x00010000U)
00547 #define SAI_FIFOSTATUS_1QUARTERFULL       ((uint32_t)0x00020000U)
00548 #define SAI_FIFOSTATUS_HALFFULL           ((uint32_t)0x00030000U)
00549 #define SAI_FIFOSTATUS_3QUARTERFULL       ((uint32_t)0x00040000U)
00550 #define SAI_FIFOSTATUS_FULL               ((uint32_t)0x00050000U)
00551 /**
00552   * @}
00553   */
00554
00555 /**
00556   * @}
00557   */
00558
00559 /* Exported macro ------------------------------------------------------------*/
00560
00561 /** @defgroup SAI_Exported_Macros SAI Exported Macros
00562  *  @brief macros to handle interrupts and specific configurations
00563  * @{
00564  */
00565
00566 /** @brief Reset SAI handle state.
00567   * @param  __HANDLE__: specifies the SAI Handle.
00568   * @retval None
00569   */
00570 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
00571
00572 /** @brief  Enable or disable the specified SAI interrupts.
00573   * @param  __HANDLE__: specifies the SAI Handle.
00574   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00575   *         This parameter can be one of the following values:
00576   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00577   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00578   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00579   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00580   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00581   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00582   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00583   * @retval None
00584   */
00585 #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00586 #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
00587
00588 /** @brief  Check whether the specified SAI interrupt source is enabled or not.
00589   * @param  __HANDLE__: specifies the SAI Handle.
00590   * @param  __INTERRUPT__: specifies the SAI interrupt source to check.
00591   *         This parameter can be one of the following values:
00592   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00593   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00594   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00595   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00596   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00597   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00598   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00599   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00600   */
00601 #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00602
00603 /** @brief  Check whether the specified SAI flag is set or not.
00604   * @param  __HANDLE__: specifies the SAI Handle.
00605   * @param  __FLAG__: specifies the flag to check.
00606   *         This parameter can be one of the following values:
00607   *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
00608   *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
00609   *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
00610   *            @arg SAI_FLAG_FREQ: FIFO request flag.
00611   *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
00612   *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
00613   *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
00614   * @retval The new state of __FLAG__ (TRUE or FALSE).
00615   */
00616 #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00617
00618 /** @brief  Clear the specified SAI pending flag.
00619   * @param  __HANDLE__: specifies the SAI Handle.
00620   * @param  __FLAG__: specifies the flag to check.
00621   *          This parameter can be any combination of the following values:
00622   *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
00623   *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
00624   *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
00625   *            @arg SAI_FLAG_FREQ: Clear FIFO request
00626   *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
00627   *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
00628   *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
00629   *
00630   * @retval None
00631   */
00632 #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
00633
00634 #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
00635 #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
00636
00637  /**
00638   * @}
00639   */
00640
00641 /* Exported functions --------------------------------------------------------*/
00642
00643 /** @addtogroup SAI_Exported_Functions
00644   * @{
00645   */
00646
00647 /* Initialization/de-initialization functions  ********************************/
00648
00649 /** @addtogroup SAI_Exported_Functions_Group1
00650   * @{
00651   */
00652 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00653 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
00654 HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
00655 void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
00656 void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
00657
00658 /**
00659   * @}
00660   */
00661
00662 /* I/O operation functions  ***************************************************/
00663
00664 /** @addtogroup SAI_Exported_Functions_Group2
00665   * @{
00666   */
00667 /* Blocking mode: Polling */
00668 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00669 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00670
00671 /* Non-Blocking mode: Interrupt */
00672 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00673 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00674
00675 /* Non-Blocking mode: DMA */
00676 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00677 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00678 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
00679 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
00680 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
00681
00682 /* Abort function */
00683 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
00684
00685 /* Mute management */
00686 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
00687 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
00688 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
00689 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
00690
00691 /* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00692 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
00693 void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00694 void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
00695 void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00696 void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
00697 void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
00698 /**
00699   * @}
00700   */
00701
00702 /** @addtogroup SAI_Exported_Functions_Group3
00703   * @{
00704   */
00705 /* Peripheral State functions  ************************************************/
00706 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
00707 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
00708 /**
00709   * @}
00710   */
00711
00712 /**
00713   * @}
00714   */
00715
00716 /* Private macros ------------------------------------------------------------*/
00717 /** @addtogroup SAI_Private_Macros
00718   * @{
00719   */
00720 #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
00721                                      ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
00722                                      ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
00723
00724 #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
00725                                                ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
00726                                                ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
00727                                                ((PROTOCOL) == SAI_PCM_LONG)         ||\
00728                                                ((PROTOCOL) == SAI_PCM_SHORT))
00729
00730 #define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
00731                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
00732                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
00733                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
00734
00735 #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
00736                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
00737                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
00738                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
00739                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
00740
00741 #define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \
00742                                   ((MODE) == SAI_MODEMASTER_RX) || \
00743                                   ((MODE) == SAI_MODESLAVE_TX)  || \
00744                                   ((MODE) == SAI_MODESLAVE_RX))
00745
00746 #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
00747                                          ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
00748                                          ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
00749
00750 #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
00751                                          ((DATASIZE) == SAI_DATASIZE_10) || \
00752                                          ((DATASIZE) == SAI_DATASIZE_16) || \
00753                                          ((DATASIZE) == SAI_DATASIZE_20) || \
00754                                          ((DATASIZE) == SAI_DATASIZE_24) || \
00755                                          ((DATASIZE) == SAI_DATASIZE_32))
00756
00757 #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
00758                                      ((BIT) == SAI_FIRSTBIT_LSB))
00759
00760 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
00761                                             ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
00762
00763 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
00764                                        ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
00765                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
00766                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
00767
00768 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
00769                                           ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
00770
00771 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
00772                                            ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
00773
00774 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
00775
00776 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
00777                                            ((VALUE) == SAI_LAST_SENT_VALUE))
00778
00779 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
00780                                                ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
00781                                                ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
00782                                                ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
00783                                                ((MODE) == SAI_ALAW_2CPL_COMPANDING))
00784
00785 #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
00786                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
00787                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
00788                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
00789                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
00790
00791 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
00792                                                  ((STATE) == SAI_OUTPUT_RELEASED))
00793
00794 #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
00795                                        ((MODE) == SAI_STEREOMODE))
00796
00797 #define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
00798
00799 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
00800
00801 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
00802                                       ((SIZE) == SAI_SLOTSIZE_16B)      || \
00803                                       ((SIZE) == SAI_SLOTSIZE_32B))
00804
00805 #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
00806
00807 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
00808                                         ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
00809
00810 #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
00811                                             ((POLARITY) == SAI_FS_ACTIVE_HIGH))
00812
00813 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
00814                                                 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
00815
00816 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
00817
00818 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
00819
00820 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
00821
00822 /**
00823   * @}
00824   */
00825
00826 /* Private functions ---------------------------------------------------------*/
00827 /** @defgroup SAI_Private_Functions SAI Private Functions
00828   * @{
00829   */
00830
00831 /**
00832   * @}
00833   */
00834
00835 /**
00836   * @}
00837   */
00838
00839 /**
00840   * @}
00841   */
00842
00843 #ifdef __cplusplus
00844 }
00845 #endif
00846
00847 #endif /* __STM32L4xx_HAL_SAI_H */
00848
00849 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sd.c Source File

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stm32l4xx_hal_sd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_sd.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SD card HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Secure Digital (SD) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     This driver implements a high level communication layer for read and write from/to
00021     this memory. The needed STM32 hardware resources (SDMMC1 and GPIO) are performed by
00022     the user in HAL_SD_MspInit() function (MSP layer).
00023     Basically, the MSP layer configuration should be the same as we provide in the
00024     examples.
00025     You can easily tailor this configuration according to hardware resources.
00026
00027   [..]
00028     This driver is a generic layered driver for SDMMC memories which uses the HAL
00029     SDMMC driver functions to interface with SD and uSD cards devices.
00030     It is used as follows:
00031
00032     (#)Initialize the SDMMC1 low level resources by implementing the HAL_SD_MspInit() API:
00033         (##) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_SDMMC1 for
00034         PeriphClockSelection and select SDMMC1 clock source (MSI, main PLL or PLLSAI1)
00035         (##) Enable the SDMMC1 interface clock using __HAL_RCC_SDMMC1_CLK_ENABLE();
00036         (##) SDMMC pins configuration for SD card
00037             (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
00038             (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
00039                   and according to your pin assignment;
00040         (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
00041              and HAL_SD_WriteBlocks_DMA() APIs).
00042             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
00043             (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
00044         (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
00045             (+++) Configure the SDMMC and DMA interrupt priorities using functions
00046                   HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
00047             (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
00048             (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT()
00049                   and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process.
00050             (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT()
00051                   and __HAL_SD_SDMMC_CLEAR_IT()
00052     (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
00053
00054
00055   *** SD Card Initialization and configuration ***
00056   ================================================
00057   [..]
00058     To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes
00059     the SD Card and put it into StandBy State (Ready for data transfer).
00060     This function provide the following operations:
00061
00062     (#) Apply the SD Card initialization process at 400KHz and check the SD Card
00063         type (Standard Capacity or High Capacity). You can change or adapt this
00064         frequency by adjusting the "ClockDiv" field.
00065         The SD Card frequency (SDMMC_CK) is computed as follows:
00066      (++)
00067
00068            SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
00069
00070      -@@-  In initialization mode and according to the SD Card standard,
00071           make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
00072
00073     (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
00074         structure. This structure provide also ready computed SD Card capacity
00075         and Block size.
00076
00077         -@- These information are stored in SD handle structure in case of future use.
00078
00079     (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
00080         frequency is set to 24MHz. You can change or adapt this frequency by adjusting
00081         the "ClockDiv" field.
00082         In transfer mode and according to the SD Card standard, make sure that the
00083         SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
00084         To be able to use a frequency higher than 24MHz, you should use the SDMMC
00085         peripheral in bypass mode. Refer to the corresponding reference manual
00086         for more details.
00087
00088     (#) Select the corresponding SD Card according to the address read with the step 2.
00089
00090     (#) Configure the SD Card in wide bus mode: 4-bits data.
00091
00092   *** SD Card Read operation ***
00093   ==============================
00094   [..]
00095     (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
00096         This function support only 512-bytes block length (the block size should be
00097         chosen as 512 bytes).
00098         You can choose either one block read operation or multiple block read operation
00099         by adjusting the "NumberOfBlocks" parameter.
00100
00101     (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
00102         This function support only 512-bytes block length (the block size should be
00103         chosen as 512 bytes).
00104         You can choose either one block read operation or multiple block read operation
00105         by adjusting the "NumberOfBlocks" parameter.
00106         After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
00107         that the read transfer is done correctly in both DMA and SD sides.
00108
00109   *** SD Card Write operation ***
00110   ===============================
00111   [..]
00112     (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
00113         This function support only 512-bytes block length (the block size should be
00114         chosen as 512 bytes).
00115         You can choose either one block read operation or multiple block read operation
00116         by adjusting the "NumberOfBlocks" parameter.
00117
00118     (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
00119         This function support only 512-bytes block length (the block size should be
00120         chosen as 512 byte).
00121         You can choose either one block read operation or multiple block read operation
00122         by adjusting the "NumberOfBlocks" parameter.
00123         After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
00124         that the write transfer is done correctly in both DMA and SD sides.
00125
00126   *** SD card status ***
00127   ======================
00128   [..]
00129     (+) At any time, you can check the SD Card status and get the SD card state
00130         by using the HAL_SD_GetStatus() function. This function checks first if the
00131         SD card is still connected and then get the internal SD Card transfer state.
00132     (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus()
00133         function.
00134
00135   *** SD HAL driver macros list ***
00136   ==================================
00137   [..]
00138     Below the list of most used macros in SD HAL driver.
00139
00140     (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device
00141     (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device
00142     (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer
00143     (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer
00144     (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt
00145     (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt
00146     (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not
00147     (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags
00148     [..]
00149     (@) You can refer to the SD HAL driver header file for more useful macros
00150
00151   @endverbatim
00152   ******************************************************************************
00153   * @attention
00154   *
00155   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00156   *
00157   * Redistribution and use in source and binary forms, with or without modification,
00158   * are permitted provided that the following conditions are met:
00159   *   1. Redistributions of source code must retain the above copyright notice,
00160   *      this list of conditions and the following disclaimer.
00161   *   2. Redistributions in binary form must reproduce the above copyright notice,
00162   *      this list of conditions and the following disclaimer in the documentation
00163   *      and/or other materials provided with the distribution.
00164   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00165   *      may be used to endorse or promote products derived from this software
00166   *      without specific prior written permission.
00167   *
00168   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00169   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00170   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00171   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00172   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00173   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00174   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00175   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00176   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00177   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00178   *
00179   ******************************************************************************
00180   */
00181
00182 /* Includes ------------------------------------------------------------------*/
00183 #include "stm32l4xx_hal.h"
00184
00185 #if defined(SDMMC1)
00186
00187 /** @addtogroup STM32L4xx_HAL_Driver
00188   * @{
00189   */
00190
00191 /** @addtogroup SD
00192   * @{
00193   */
00194
00195 #ifdef HAL_SD_MODULE_ENABLED
00196
00197 /* Private typedef -----------------------------------------------------------*/
00198 /* Private define ------------------------------------------------------------*/
00199 /** @addtogroup SD_Private_Defines
00200   * @{
00201   */
00202 /**
00203   * @brief  SDMMC Data block size
00204   */
00205 #define DATA_BLOCK_SIZE                  ((uint32_t)(9 << 4))
00206 /**
00207   * @brief  SDMMC Static flags, Timeout, FIFO Address
00208   */
00209 #define SDMMC_STATIC_FLAGS               ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
00210                                                     SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\
00211                                                     SDMMC_FLAG_CMDREND  | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\
00212                                                     SDMMC_FLAG_DBCKEND))
00213
00214 #define SDMMC_CMD0TIMEOUT                ((uint32_t)0x00010000)
00215
00216 /**
00217   * @brief  Mask for errors Card Status R1 (OCR Register)
00218   */
00219 #define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000)
00220 #define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000)
00221 #define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000)
00222 #define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000)
00223 #define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000)
00224 #define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000)
00225 #define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000)
00226 #define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000)
00227 #define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000)
00228 #define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000)
00229 #define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000)
00230 #define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000)
00231 #define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000)
00232 #define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000)
00233 #define SD_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000)
00234 #define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000)
00235 #define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000)
00236 #define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000)
00237 #define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008)
00238 #define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008)
00239
00240 /**
00241   * @brief  Masks for R6 Response
00242   */
00243 #define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000)
00244 #define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000)
00245 #define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000)
00246
00247 #define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000)
00248 #define SD_HIGH_CAPACITY                ((uint32_t)0x40000000)
00249 #define SD_STD_CAPACITY                 ((uint32_t)0x00000000)
00250 #define SD_CHECK_PATTERN                ((uint32_t)0x000001AA)
00251
00252 #define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFF)
00253 #define SD_ALLZERO                      ((uint32_t)0x00000000)
00254
00255 #define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000)
00256 #define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000)
00257 #define SD_CARD_LOCKED                  ((uint32_t)0x02000000)
00258
00259 #define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFF)
00260 #define SD_0TO7BITS                     ((uint32_t)0x000000FF)
00261 #define SD_8TO15BITS                    ((uint32_t)0x0000FF00)
00262 #define SD_16TO23BITS                   ((uint32_t)0x00FF0000)
00263 #define SD_24TO31BITS                   ((uint32_t)0xFF000000)
00264 #define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFF)
00265
00266 #define SD_HALFFIFO                     ((uint32_t)0x00000008)
00267 #define SD_HALFFIFOBYTES                ((uint32_t)0x00000020)
00268
00269 /**
00270   * @brief  Command Class Supported
00271   */
00272 #define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080)
00273 #define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040)
00274 #define SD_CCCC_ERASE                   ((uint32_t)0x00000020)
00275
00276 /**
00277   * @brief  Following commands are SD Card Specific commands.
00278   *         SDMMC_APP_CMD should be sent before sending these commands.
00279   */
00280 #define SD_SDMMC_SEND_IF_COND            ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
00281 /**
00282   * @}
00283   */
00284
00285 /* Private macro -------------------------------------------------------------*/
00286 /* Private variables ---------------------------------------------------------*/
00287 /* Private function prototypes -----------------------------------------------*/
00288 /** @addtogroup SD_Private_Functions_Prototypes
00289   * @{
00290   */
00291 static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
00292 static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);
00293 static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd);
00294 static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
00295 static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
00296 static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
00297 static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
00298 static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
00299 static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
00300 static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
00301 static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
00302 static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
00303 static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
00304 static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
00305 static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
00306 static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
00307 static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
00308 static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
00309 static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
00310 static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
00311 /**
00312   * @}
00313   */
00314 /* Exported functions --------------------------------------------------------*/
00315 /** @addtogroup SD_Exported_Functions
00316   * @{
00317   */
00318
00319 /** @addtogroup SD_Exported_Functions_Group1
00320  *  @brief   Initialization and de-initialization functions
00321  *
00322 @verbatim
00323   ==============================================================================
00324           ##### Initialization and de-initialization functions #####
00325   ==============================================================================
00326   [..]
00327     This section provides functions allowing to initialize/de-initialize the SD
00328     card device to be ready for use.
00329
00330
00331 @endverbatim
00332   * @{
00333   */
00334
00335 /**
00336   * @brief  Initializes the SD card according to the specified parameters in the
00337             SD_HandleTypeDef and initialize the associated handle.
00338   * @param  hsd: SD handle
00339   * @param  SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information
00340   * @retval HAL SD error state
00341   */
00342 HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
00343 {
00344   __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
00345   SD_InitTypeDef tmpinit;
00346
00347   /* Initialize the low level hardware (MSP) */
00348   HAL_SD_MspInit(hsd);
00349
00350   /* Default SDMMC peripheral configuration for SD card initialization */
00351   tmpinit.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
00352   tmpinit.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;
00353   tmpinit.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
00354   tmpinit.BusWide             = SDMMC_BUS_WIDE_1B;
00355   tmpinit.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
00356   tmpinit.ClockDiv            = SDMMC_INIT_CLK_DIV;
00357
00358   /* Initialize SDMMC peripheral interface with default configuration */
00359   SDMMC_Init(hsd->Instance, tmpinit);
00360
00361   /* Identify card operating voltage */
00362   errorstate = SD_PowerON(hsd);
00363
00364   if(errorstate != SD_OK)
00365   {
00366     return errorstate;
00367   }
00368
00369   /* Initialize the present SDMMC card(s) and put them in idle state */
00370   errorstate = SD_Initialize_Cards(hsd);
00371
00372   if (errorstate != SD_OK)
00373   {
00374     return errorstate;
00375   }
00376
00377   /* Read CSD/CID MSD registers */
00378   errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
00379
00380   if (errorstate == SD_OK)
00381   {
00382     /* Select the Card */
00383     errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
00384   }
00385
00386   /* Configure SDMMC peripheral interface */
00387   SDMMC_Init(hsd->Instance, hsd->Init);
00388
00389   return errorstate;
00390 }
00391
00392 /**
00393   * @brief  De-Initializes the SD card.
00394   * @param  hsd: SD handle
00395   * @retval HAL status
00396   */
00397 HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
00398 {
00399
00400   /* Set SD power state to off */
00401   SD_PowerOFF(hsd);
00402
00403   /* De-Initialize the MSP layer */
00404   HAL_SD_MspDeInit(hsd);
00405
00406   return HAL_OK;
00407 }
00408
00409
00410 /**
00411   * @brief  Initializes the SD MSP.
00412   * @param  hsd: SD handle
00413   * @retval None
00414   */
00415 __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
00416 {
00417   /* Prevent unused argument(s) compilation warning */
00418   UNUSED(hsd);
00419
00420   /* NOTE : This function should not be modified, when the callback is needed,
00421             the HAL_SD_MspInit could be implemented in the user file
00422    */
00423 }
00424
00425 /**
00426   * @brief  De-Initialize SD MSP.
00427   * @param  hsd: SD handle
00428   * @retval None
00429   */
00430 __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
00431 {
00432   /* Prevent unused argument(s) compilation warning */
00433   UNUSED(hsd);
00434
00435   /* NOTE : This function should not be modified, when the callback is needed,
00436             the HAL_SD_MspDeInit could be implemented in the user file
00437    */
00438 }
00439
00440 /**
00441   * @}
00442   */
00443
00444 /** @addtogroup SD_Exported_Functions_Group2
00445  *  @brief   Data transfer functions
00446  *
00447 @verbatim
00448   ==============================================================================
00449                         ##### IO operation functions #####
00450   ==============================================================================
00451   [..]
00452     This subsection provides a set of functions allowing to manage the data
00453     transfer from/to SD card.
00454
00455 @endverbatim
00456   * @{
00457   */
00458
00459 /**
00460   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00461   *         is managed by polling mode.
00462   * @param  hsd: SD handle
00463   * @param  pReadBuffer: pointer to the buffer that will contain the received data
00464   * @param  ReadAddr: Address from where data is to be read
00465   * @param  BlockSize: SD card Data block size
00466   *   @note BlockSize must be 512 bytes.
00467   * @param  NumberOfBlocks: Number of SD blocks to read
00468   * @retval SD Card error state
00469   */
00470 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00471 {
00472   SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
00473   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
00474   HAL_SD_ErrorTypedef errorstate = SD_OK;
00475   uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;
00476
00477   /* Initialize data control register */
00478   hsd->Instance->DCTRL = 0;
00479
00480   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
00481   {
00482     BlockSize = 512;
00483     ReadAddr /= 512;
00484   }
00485
00486   /* Set Block Size for Card */
00487   sdmmc_cmdinitstructure.Argument         = (uint32_t) BlockSize;
00488   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
00489   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
00490   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
00491   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
00492   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00493
00494   /* Check for error conditions */
00495   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
00496
00497   if (errorstate != SD_OK)
00498   {
00499     return errorstate;
00500   }
00501
00502   /* Configure the SD DPSM (Data Path State Machine) */
00503   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
00504   sdmmc_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
00505   sdmmc_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
00506   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00507   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00508   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
00509   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
00510
00511   if(NumberOfBlocks > 1)
00512   {
00513     /* Send CMD18 READ_MULT_BLOCK with argument data address */
00514     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
00515   }
00516   else
00517   {
00518     /* Send CMD17 READ_SINGLE_BLOCK */
00519     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
00520   }
00521
00522   sdmmc_cmdinitstructure.Argument         = (uint32_t)ReadAddr;
00523   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00524
00525   /* Read block(s) in polling mode */
00526   if(NumberOfBlocks > 1)
00527   {
00528     /* Check for error conditions */
00529     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
00530
00531     if (errorstate != SD_OK)
00532     {
00533       return errorstate;
00534     }
00535
00536     /* Poll on SDMMC flags */
00537     while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00538     {
00539       if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
00540       {
00541         /* Read data from SDMMC Rx FIFO */
00542         for (count = 0; count < 8; count++)
00543         {
00544           *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
00545         }
00546
00547         tempbuff += 8;
00548       }
00549     }
00550   }
00551   else
00552   {
00553     /* Check for error conditions */
00554     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
00555
00556     if (errorstate != SD_OK)
00557     {
00558       return errorstate;
00559     }
00560
00561     /* In case of single block transfer, no need of stop transfer at all */
00562     while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
00563     {
00564       if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
00565       {
00566         /* Read data from SDMMC Rx FIFO */
00567         for (count = 0; count < 8; count++)
00568         {
00569           *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
00570         }
00571
00572         tempbuff += 8;
00573       }
00574     }
00575   }
00576
00577   /* Send stop transmission command in case of multiblock read */
00578   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))
00579   {
00580     if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
00581       (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
00582         (hsd->CardType == HIGH_CAPACITY_SD_CARD))
00583     {
00584       /* Send stop transmission command */
00585       errorstate = HAL_SD_StopTransfer(hsd);
00586     }
00587   }
00588
00589   /* Get error state */
00590   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
00591   {
00592     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
00593
00594     errorstate = SD_DATA_TIMEOUT;
00595
00596     return errorstate;
00597   }
00598   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
00599   {
00600     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
00601
00602     errorstate = SD_DATA_CRC_FAIL;
00603
00604     return errorstate;
00605   }
00606   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
00607   {
00608     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
00609
00610     errorstate = SD_RX_OVERRUN;
00611
00612     return errorstate;
00613   }
00614   else
00615   {
00616     /* No error flag set */
00617   }
00618
00619   count = SD_DATATIMEOUT;
00620
00621   /* Empty FIFO if there is still any data */
00622   while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
00623   {
00624     *tempbuff = SDMMC_ReadFIFO(hsd->Instance);
00625     tempbuff++;
00626     count--;
00627   }
00628
00629   /* Clear all the static flags */
00630   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00631
00632   return errorstate;
00633 }
00634
00635 /**
00636   * @brief  Allows to write block(s) to a specified address in a card. The Data
00637   *         transfer is managed by polling mode.
00638   * @param  hsd: SD handle
00639   * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
00640   * @param  WriteAddr: Address from where data is to be written
00641   * @param  BlockSize: SD card Data block size
00642   * @note   BlockSize must be 512 bytes.
00643   * @param  NumberOfBlocks: Number of SD blocks to write
00644   * @retval SD Card error state
00645   */
00646 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00647 {
00648   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
00649   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
00650   HAL_SD_ErrorTypedef errorstate = SD_OK;
00651   uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;
00652   uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
00653   uint8_t cardstate  = 0;
00654
00655   /* Initialize data control register */
00656   hsd->Instance->DCTRL = 0;
00657
00658   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
00659   {
00660     BlockSize = 512;
00661     WriteAddr /= 512;
00662   }
00663
00664   /* Set Block Size for Card */
00665   sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
00666   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
00667   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
00668   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
00669   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
00670   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00671
00672   /* Check for error conditions */
00673   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
00674
00675   if (errorstate != SD_OK)
00676   {
00677     return errorstate;
00678   }
00679
00680   if(NumberOfBlocks > 1)
00681   {
00682     /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
00683     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
00684   }
00685   else
00686   {
00687     /* Send CMD24 WRITE_SINGLE_BLOCK */
00688     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
00689   }
00690
00691   sdmmc_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
00692   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00693
00694   /* Check for error conditions */
00695   if(NumberOfBlocks > 1)
00696   {
00697     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
00698   }
00699   else
00700   {
00701     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
00702   }
00703
00704   if (errorstate != SD_OK)
00705   {
00706     return errorstate;
00707   }
00708
00709   /* Set total number of bytes to write */
00710   totalnumberofbytes = NumberOfBlocks * BlockSize;
00711
00712   /* Configure the SD DPSM (Data Path State Machine) */
00713   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
00714   sdmmc_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
00715   sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00716   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
00717   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00718   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
00719   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
00720
00721   /* Write block(s) in polling mode */
00722   if(NumberOfBlocks > 1)
00723   {
00724     while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
00725     {
00726       if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
00727       {
00728         if ((totalnumberofbytes - bytestransferred) < 32)
00729         {
00730           restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
00731
00732           /* Write data to SDMMC Tx FIFO */
00733           for (count = 0; count < restwords; count++)
00734           {
00735             SDMMC_WriteFIFO(hsd->Instance, tempbuff);
00736             tempbuff++;
00737             bytestransferred += 4;
00738           }
00739         }
00740         else
00741         {
00742           /* Write data to SDMMC Tx FIFO */
00743           for (count = 0; count < 8; count++)
00744           {
00745             SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
00746           }
00747
00748           tempbuff += 8;
00749           bytestransferred += 32;
00750         }
00751       }
00752     }
00753   }
00754   else
00755   {
00756     /* In case of single data block transfer no need of stop command at all */
00757     while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
00758     {
00759       if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))
00760       {
00761         if ((totalnumberofbytes - bytestransferred) < 32)
00762         {
00763           restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
00764
00765           /* Write data to SDMMC Tx FIFO */
00766           for (count = 0; count < restwords; count++)
00767           {
00768             SDMMC_WriteFIFO(hsd->Instance, tempbuff);
00769             tempbuff++;
00770             bytestransferred += 4;
00771           }
00772         }
00773         else
00774         {
00775           /* Write data to SDMMC Tx FIFO */
00776           for (count = 0; count < 8; count++)
00777           {
00778             SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));
00779           }
00780
00781           tempbuff += 8;
00782           bytestransferred += 32;
00783         }
00784       }
00785     }
00786   }
00787
00788   /* Send stop transmission command in case of multiblock write */
00789   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))
00790   {
00791     if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
00792       (hsd->CardType == HIGH_CAPACITY_SD_CARD))
00793     {
00794       /* Send stop transmission command */
00795       errorstate = HAL_SD_StopTransfer(hsd);
00796     }
00797   }
00798
00799   /* Get error state */
00800   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
00801   {
00802     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
00803
00804     errorstate = SD_DATA_TIMEOUT;
00805
00806     return errorstate;
00807   }
00808   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
00809   {
00810     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
00811
00812     errorstate = SD_DATA_CRC_FAIL;
00813
00814     return errorstate;
00815   }
00816   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
00817   {
00818     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);
00819
00820     errorstate = SD_TX_UNDERRUN;
00821
00822     return errorstate;
00823   }
00824   else
00825   {
00826     /* No error flag set */
00827   }
00828
00829   /* Clear all the static flags */
00830   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
00831
00832   /* Wait till the card is in programming state */
00833   errorstate = SD_IsCardProgramming(hsd, &cardstate);
00834
00835   while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
00836   {
00837     errorstate = SD_IsCardProgramming(hsd, &cardstate);
00838   }
00839
00840   return errorstate;
00841 }
00842
00843 /**
00844   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00845   *         is managed by DMA mode.
00846   * @note   This API should be followed by the function HAL_SD_CheckReadOperation()
00847   *         to check the completion of the read process
00848   * @param  hsd: SD handle
00849   * @param  pReadBuffer: Pointer to the buffer that will contain the received data
00850   * @param  ReadAddr: Address from where data is to be read
00851   * @param  BlockSize: SD card Data block size
00852   * @note   BlockSize must be 512 bytes.
00853   * @param  NumberOfBlocks: Number of blocks to read.
00854   * @retval SD Card error state
00855   */
00856 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00857 {
00858   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
00859   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
00860   HAL_SD_ErrorTypedef errorstate = SD_OK;
00861
00862   /* Initialize data control register */
00863   hsd->Instance->DCTRL = 0;
00864
00865   /* Initialize handle flags */
00866   hsd->SdTransferCplt  = 0;
00867   hsd->DmaTransferCplt = 0;
00868   hsd->SdTransferErr   = SD_OK;
00869
00870   /* Initialize SD Read operation */
00871   if(NumberOfBlocks > 1)
00872   {
00873     hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
00874   }
00875   else
00876   {
00877     hsd->SdOperation = SD_READ_SINGLE_BLOCK;
00878   }
00879
00880   /* Enable transfer interrupts */
00881   __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\
00882                                  SDMMC_IT_DTIMEOUT |\
00883                                  SDMMC_IT_DATAEND  |\
00884                                  SDMMC_IT_RXOVERR));
00885
00886   /* Enable SDMMC DMA transfer */
00887   __HAL_SD_SDMMC_DMA_ENABLE(hsd);
00888
00889   /* Configure DMA user callbacks */
00890   hsd->hdmarx->XferCpltCallback  = SD_DMA_RxCplt;
00891   hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
00892
00893   /* Change DMA direction Periph to Memory */
00894   hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
00895   hsd->hdmarx->Instance->CCR &= ~DMA_MEMORY_TO_PERIPH;
00896
00897   /* Enable the DMA Channel */
00898   HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
00899
00900   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
00901   {
00902     BlockSize = 512;
00903     ReadAddr /= 512;
00904   }
00905
00906   /* Set Block Size for Card */
00907   sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
00908   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
00909   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
00910   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
00911   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
00912   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00913
00914   /* Check for error conditions */
00915   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
00916
00917   if (errorstate != SD_OK)
00918   {
00919     return errorstate;
00920   }
00921
00922   /* Configure the SD DPSM (Data Path State Machine) */
00923   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
00924   sdmmc_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
00925   sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
00926   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
00927   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
00928   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
00929   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
00930
00931   /* Check number of blocks command */
00932   if(NumberOfBlocks > 1)
00933   {
00934     /* Send CMD18 READ_MULT_BLOCK with argument data address */
00935     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
00936   }
00937   else
00938   {
00939     /* Send CMD17 READ_SINGLE_BLOCK */
00940     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
00941   }
00942
00943   sdmmc_cmdinitstructure.Argument         = (uint32_t)ReadAddr;
00944   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
00945
00946   /* Check for error conditions */
00947   if(NumberOfBlocks > 1)
00948   {
00949     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
00950   }
00951   else
00952   {
00953     errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
00954   }
00955
00956   /* Update the SD transfer error in SD handle */
00957   hsd->SdTransferErr = errorstate;
00958
00959   return errorstate;
00960 }
00961
00962
00963 /**
00964   * @brief  Writes block(s) to a specified address in a card. The Data transfer
00965   *         is managed by DMA mode.
00966   * @note   This API should be followed by the function HAL_SD_CheckWriteOperation()
00967   *         to check the completion of the write process (by SD current status polling).
00968   * @param  hsd: SD handle
00969   * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
00970   * @param  WriteAddr: Address from where data is to be read
00971   * @param  BlockSize: the SD card Data block size
00972   * @note   BlockSize must be 512 bytes.
00973   * @param  NumberOfBlocks: Number of blocks to write
00974   * @retval SD Card error state
00975   */
00976 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
00977 {
00978   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
00979   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
00980   HAL_SD_ErrorTypedef errorstate = SD_OK;
00981
00982   /* Initialize data control register */
00983   hsd->Instance->DCTRL = 0;
00984
00985   /* Initialize handle flags */
00986   hsd->SdTransferCplt  = 0;
00987   hsd->DmaTransferCplt = 0;
00988   hsd->SdTransferErr   = SD_OK;
00989
00990   /* Initialize SD Write operation */
00991   if(NumberOfBlocks > 1)
00992   {
00993     hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
00994   }
00995   else
00996   {
00997     hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
00998   }
00999
01000   /* Enable transfer interrupts */
01001   __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\
01002                                  SDMMC_IT_DTIMEOUT |\
01003                                  SDMMC_IT_DATAEND  |\
01004                                  SDMMC_IT_TXUNDERR));
01005
01006   /* Configure DMA user callbacks */
01007   hsd->hdmatx->XferCpltCallback  = SD_DMA_TxCplt;
01008   hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
01009
01010   /* Change DMA direction Memory to Periph */
01011   hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
01012   hsd->hdmatx->Instance->CCR |= DMA_MEMORY_TO_PERIPH;
01013
01014   /* Enable the DMA Channel */
01015   HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
01016
01017   /* Enable SDMMC DMA transfer */
01018   __HAL_SD_SDMMC_DMA_ENABLE(hsd);
01019
01020   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
01021   {
01022     BlockSize = 512;
01023     WriteAddr /= 512;
01024   }
01025
01026   /* Set Block Size for Card */
01027   sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;
01028   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
01029   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
01030   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
01031   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
01032   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01033
01034   /* Check for error conditions */
01035   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
01036
01037   if (errorstate != SD_OK)
01038   {
01039     return errorstate;
01040   }
01041
01042   /* Check number of blocks command */
01043   if(NumberOfBlocks <= 1)
01044   {
01045     /* Send CMD24 WRITE_SINGLE_BLOCK */
01046     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
01047   }
01048   else
01049   {
01050     /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
01051     sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
01052   }
01053
01054   sdmmc_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
01055   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01056
01057   /* Check for error conditions */
01058   if(NumberOfBlocks > 1)
01059   {
01060     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
01061   }
01062   else
01063   {
01064     errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
01065   }
01066
01067   if (errorstate != SD_OK)
01068   {
01069     return errorstate;
01070   }
01071
01072   /* Configure the SD DPSM (Data Path State Machine) */
01073   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
01074   sdmmc_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
01075   sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
01076   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
01077   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01078   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
01079   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
01080
01081   hsd->SdTransferErr = errorstate;
01082
01083   return errorstate;
01084 }
01085
01086 /**
01087   * @brief  This function waits until the SD DMA data read transfer is finished.
01088   *         This API should be called after HAL_SD_ReadBlocks_DMA() function
01089   *         to insure that all data sent by the card is already transferred by the
01090   *         DMA controller.
01091   * @param  hsd: SD handle
01092   * @param  Timeout: Timeout duration
01093   * @retval SD Card error state
01094   */
01095 HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
01096 {
01097   HAL_SD_ErrorTypedef errorstate = SD_OK;
01098   uint32_t timeout = Timeout;
01099   uint32_t tmp1, tmp2;
01100   HAL_SD_ErrorTypedef tmp3;
01101
01102   /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
01103   tmp1 = hsd->DmaTransferCplt;
01104   tmp2 = hsd->SdTransferCplt;
01105   tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01106
01107   while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
01108   {
01109     tmp1 = hsd->DmaTransferCplt;
01110     tmp2 = hsd->SdTransferCplt;
01111     tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01112     timeout--;
01113   }
01114
01115   timeout = Timeout;
01116
01117   /* Wait until the Rx transfer is no longer active */
01118   while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) && (timeout > 0))
01119   {
01120     timeout--;
01121   }
01122
01123   /* Send stop command in multiblock read */
01124   if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
01125   {
01126     errorstate = HAL_SD_StopTransfer(hsd);
01127   }
01128
01129   if ((timeout == 0) && (errorstate == SD_OK))
01130   {
01131     errorstate = SD_DATA_TIMEOUT;
01132   }
01133
01134   /* Clear all the static flags */
01135   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01136
01137   /* Return error state */
01138   if (hsd->SdTransferErr != SD_OK)
01139   {
01140     return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
01141   }
01142
01143   return errorstate;
01144 }
01145
01146 /**
01147   * @brief  This function waits until the SD DMA data write transfer is finished.
01148   *         This API should be called after HAL_SD_WriteBlocks_DMA() function
01149   *         to insure that all data sent by the card is already transferred by the
01150   *         DMA controller.
01151   * @param  hsd: SD handle
01152   * @param  Timeout: Timeout duration
01153   * @retval SD Card error state
01154   */
01155 HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
01156 {
01157   HAL_SD_ErrorTypedef errorstate = SD_OK;
01158   uint32_t timeout = Timeout;
01159   uint32_t tmp1, tmp2;
01160   HAL_SD_ErrorTypedef tmp3;
01161
01162   /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
01163   tmp1 = hsd->DmaTransferCplt;
01164   tmp2 = hsd->SdTransferCplt;
01165   tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01166
01167   while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
01168   {
01169     tmp1 = hsd->DmaTransferCplt;
01170     tmp2 = hsd->SdTransferCplt;
01171     tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
01172     timeout--;
01173   }
01174
01175   timeout = Timeout;
01176
01177   /* Wait until the Tx transfer is no longer active */
01178   while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXACT))  && (timeout > 0))
01179   {
01180     timeout--;
01181   }
01182
01183   /* Send stop command in multiblock write */
01184   if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
01185   {
01186     errorstate = HAL_SD_StopTransfer(hsd);
01187   }
01188
01189   if ((timeout == 0) && (errorstate == SD_OK))
01190   {
01191     errorstate = SD_DATA_TIMEOUT;
01192   }
01193
01194   /* Clear all the static flags */
01195   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01196
01197   /* Return error state */
01198   if (hsd->SdTransferErr != SD_OK)
01199   {
01200     return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
01201   }
01202
01203   /* Wait until write is complete */
01204   while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
01205   {
01206   }
01207
01208   return errorstate;
01209 }
01210
01211 /**
01212   * @brief  Erases the specified memory area of the given SD card.
01213   * @param  hsd: SD handle
01214   * @param  startaddr: Start byte address
01215   * @param  endaddr: End byte address
01216   * @retval SD Card error state
01217   */
01218 HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
01219 {
01220   HAL_SD_ErrorTypedef errorstate = SD_OK;
01221   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
01222
01223   uint32_t delay         = 0;
01224   __IO uint32_t maxdelay = 0;
01225   uint8_t cardstate      = 0;
01226
01227   /* Check if the card command class supports erase command */
01228   if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)
01229   {
01230     errorstate = SD_REQUEST_NOT_APPLICABLE;
01231
01232     return errorstate;
01233   }
01234
01235   /* Get max delay value */
01236   maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);
01237
01238   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
01239   {
01240     errorstate = SD_LOCK_UNLOCK_FAILED;
01241
01242     return errorstate;
01243   }
01244
01245   /* Get start and end block for high capacity cards */
01246   if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
01247   {
01248     startaddr /= 512;
01249     endaddr   /= 512;
01250   }
01251
01252   /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
01253   if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
01254     (hsd->CardType == HIGH_CAPACITY_SD_CARD))
01255   {
01256     /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
01257     sdmmc_cmdinitstructure.Argument         =(uint32_t)startaddr;
01258     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_START;
01259     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
01260     sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
01261     sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
01262     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01263
01264     /* Check for error conditions */
01265     errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
01266
01267     if (errorstate != SD_OK)
01268     {
01269       return errorstate;
01270     }
01271
01272     /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
01273     sdmmc_cmdinitstructure.Argument         = (uint32_t)endaddr;
01274     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_END;
01275     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01276
01277     /* Check for error conditions */
01278     errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
01279
01280     if (errorstate != SD_OK)
01281     {
01282       return errorstate;
01283     }
01284   }
01285
01286   /* Send CMD38 ERASE */
01287   sdmmc_cmdinitstructure.Argument         = 0;
01288   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_ERASE;
01289   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01290
01291   /* Check for error conditions */
01292   errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
01293
01294   if (errorstate != SD_OK)
01295   {
01296     return errorstate;
01297   }
01298
01299   for (; delay < maxdelay; delay++)
01300   {
01301   }
01302
01303   /* Wait until the card is in programming state */
01304   errorstate = SD_IsCardProgramming(hsd, &cardstate);
01305
01306   delay = SD_DATATIMEOUT;
01307
01308   while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
01309   {
01310     errorstate = SD_IsCardProgramming(hsd, &cardstate);
01311     delay--;
01312   }
01313
01314   return errorstate;
01315 }
01316
01317 /**
01318   * @brief  This function handles SD card interrupt request.
01319   * @param  hsd: SD handle
01320   * @retval None
01321   */
01322 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
01323 {
01324   /* Check for SDMMC interrupt flags */
01325   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DATAEND))
01326   {
01327     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_IT_DATAEND);
01328
01329     /* SD transfer is complete */
01330     hsd->SdTransferCplt = 1;
01331
01332     /* No transfer error */
01333     hsd->SdTransferErr  = SD_OK;
01334
01335     HAL_SD_XferCpltCallback(hsd);
01336   }
01337   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL))
01338   {
01339     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
01340
01341     hsd->SdTransferErr = SD_DATA_CRC_FAIL;
01342
01343     HAL_SD_XferErrorCallback(hsd);
01344
01345   }
01346   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT))
01347   {
01348     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
01349
01350     hsd->SdTransferErr = SD_DATA_TIMEOUT;
01351
01352     HAL_SD_XferErrorCallback(hsd);
01353   }
01354   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_RXOVERR))
01355   {
01356     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
01357
01358     hsd->SdTransferErr = SD_RX_OVERRUN;
01359
01360     HAL_SD_XferErrorCallback(hsd);
01361   }
01362   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_TXUNDERR))
01363   {
01364     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);
01365
01366     hsd->SdTransferErr = SD_TX_UNDERRUN;
01367
01368     HAL_SD_XferErrorCallback(hsd);
01369   }
01370   else
01371   {
01372     /* No error flag set */
01373   }
01374
01375   /* Disable all SDMMC peripheral interrupt sources */
01376   __HAL_SD_SDMMC_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_DATAEND  |\
01377                                  SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF | SDMMC_IT_TXUNDERR |\
01378                                  SDMMC_IT_RXOVERR);
01379 }
01380
01381
01382 /**
01383   * @brief  SD end of transfer callback.
01384   * @param  hsd: SD handle
01385   * @retval None
01386   */
01387 __weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
01388 {
01389   /* Prevent unused argument(s) compilation warning */
01390   UNUSED(hsd);
01391
01392   /* NOTE : This function should not be modified, when the callback is needed,
01393             the HAL_SD_XferCpltCallback could be implemented in the user file
01394    */
01395 }
01396
01397 /**
01398   * @brief  SD Transfer Error callback.
01399   * @param  hsd: SD handle
01400   * @retval None
01401   */
01402 __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
01403 {
01404   /* Prevent unused argument(s) compilation warning */
01405   UNUSED(hsd);
01406
01407   /* NOTE : This function should not be modified, when the callback is needed,
01408             the HAL_SD_XferErrorCallback could be implemented in the user file
01409    */
01410 }
01411
01412 /**
01413   * @brief  SD Transfer complete Rx callback in non-blocking mode.
01414   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01415   *                the configuration information for the specified DMA module.
01416   * @retval None
01417   */
01418 __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
01419 {
01420   /* Prevent unused argument(s) compilation warning */
01421   UNUSED(hdma);
01422
01423   /* NOTE : This function should not be modified, when the callback is needed,
01424             the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
01425    */
01426 }
01427
01428 /**
01429   * @brief  SD DMA transfer complete Rx error callback.
01430   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01431   *                the configuration information for the specified DMA module.
01432   * @retval None
01433   */
01434 __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
01435 {
01436   /* Prevent unused argument(s) compilation warning */
01437   UNUSED(hdma);
01438
01439   /* NOTE : This function should not be modified, when the callback is needed,
01440             the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
01441    */
01442 }
01443
01444 /**
01445   * @brief  SD Transfer complete Tx callback in non-blocking mode.
01446   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01447   *                the configuration information for the specified DMA module.
01448   * @retval None
01449   */
01450 __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
01451 {
01452   /* Prevent unused argument(s) compilation warning */
01453   UNUSED(hdma);
01454
01455   /* NOTE : This function should not be modified, when the callback is needed,
01456             the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
01457    */
01458 }
01459
01460 /**
01461   * @brief  SD DMA transfer complete error Tx callback.
01462   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01463   *                the configuration information for the specified DMA module.
01464   * @retval None
01465   */
01466 __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
01467 {
01468   /* Prevent unused argument(s) compilation warning */
01469   UNUSED(hdma);
01470
01471   /* NOTE : This function should not be modified, when the callback is needed,
01472             the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
01473    */
01474 }
01475
01476 /**
01477   * @}
01478   */
01479
01480 /** @addtogroup SD_Exported_Functions_Group3
01481  *  @brief   management functions
01482  *
01483 @verbatim
01484   ==============================================================================
01485                       ##### Peripheral Control functions #####
01486   ==============================================================================
01487   [..]
01488     This subsection provides a set of functions allowing to control the SD card
01489     operations.
01490
01491 @endverbatim
01492   * @{
01493   */
01494
01495 /**
01496   * @brief  Returns information about specific card.
01497   * @param  hsd: SD handle
01498   * @param  pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that
01499   *         contains all SD cardinformation
01500   * @retval SD Card error state
01501   */
01502 HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
01503 {
01504   HAL_SD_ErrorTypedef errorstate = SD_OK;
01505   uint32_t tmp = 0;
01506
01507   pCardInfo->CardType = (uint8_t)(hsd->CardType);
01508   pCardInfo->RCA      = (uint16_t)(hsd->RCA);
01509
01510   /* Byte 0 */
01511   tmp = (hsd->CSD[0] & 0xFF000000) >> 24;
01512   pCardInfo->SD_csd.CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);
01513   pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
01514   pCardInfo->SD_csd.Reserved1      = tmp & 0x03;
01515
01516   /* Byte 1 */
01517   tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
01518   pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
01519
01520   /* Byte 2 */
01521   tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
01522   pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
01523
01524   /* Byte 3 */
01525   tmp = hsd->CSD[0] & 0x000000FF;
01526   pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
01527
01528   /* Byte 4 */
01529   tmp = (hsd->CSD[1] & 0xFF000000) >> 24;
01530   pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
01531
01532   /* Byte 5 */
01533   tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;
01534   pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
01535   pCardInfo->SD_csd.RdBlockLen       = (uint8_t)(tmp & 0x0F);
01536
01537   /* Byte 6 */
01538   tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;
01539   pCardInfo->SD_csd.PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);
01540   pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
01541   pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
01542   pCardInfo->SD_csd.DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);
01543   pCardInfo->SD_csd.Reserved2       = 0; /*!< Reserved */
01544
01545   if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
01546   {
01547     pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
01548
01549     /* Byte 7 */
01550     tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
01551     pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
01552
01553     /* Byte 8 */
01554     tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
01555     pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
01556
01557     pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
01558     pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
01559
01560     /* Byte 9 */
01561     tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
01562     pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
01563     pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
01564     pCardInfo->SD_csd.DeviceSizeMul      = (tmp & 0x03) << 1;
01565     /* Byte 10 */
01566     tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
01567     pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
01568
01569     pCardInfo->CardCapacity  = (pCardInfo->SD_csd.DeviceSize + 1) ;
01570     pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));
01571     pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);
01572     pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
01573   }
01574   else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
01575   {
01576     /* Byte 7 */
01577     tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
01578     pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
01579
01580     /* Byte 8 */
01581     tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
01582
01583     pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
01584
01585     /* Byte 9 */
01586     tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
01587
01588     pCardInfo->SD_csd.DeviceSize |= (tmp);
01589
01590     /* Byte 10 */
01591     tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
01592
01593     pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024);
01594     pCardInfo->CardBlockSize = 512;
01595   }
01596   else
01597   {
01598     /* Not supported card type */
01599     errorstate = SD_ERROR;
01600   }
01601
01602   pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
01603   pCardInfo->SD_csd.EraseGrMul  = (tmp & 0x3F) << 1;
01604
01605   /* Byte 11 */
01606   tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
01607   pCardInfo->SD_csd.EraseGrMul     |= (tmp & 0x80) >> 7;
01608   pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
01609
01610   /* Byte 12 */
01611   tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);
01612   pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
01613   pCardInfo->SD_csd.ManDeflECC        = (tmp & 0x60) >> 5;
01614   pCardInfo->SD_csd.WrSpeedFact       = (tmp & 0x1C) >> 2;
01615   pCardInfo->SD_csd.MaxWrBlockLen     = (tmp & 0x03) << 2;
01616
01617   /* Byte 13 */
01618   tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
01619   pCardInfo->SD_csd.MaxWrBlockLen      |= (tmp & 0xC0) >> 6;
01620   pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
01621   pCardInfo->SD_csd.Reserved3           = 0;
01622   pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
01623
01624   /* Byte 14 */
01625   tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
01626   pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
01627   pCardInfo->SD_csd.CopyFlag         = (tmp & 0x40) >> 6;
01628   pCardInfo->SD_csd.PermWrProtect    = (tmp & 0x20) >> 5;
01629   pCardInfo->SD_csd.TempWrProtect    = (tmp & 0x10) >> 4;
01630   pCardInfo->SD_csd.FileFormat       = (tmp & 0x0C) >> 2;
01631   pCardInfo->SD_csd.ECC              = (tmp & 0x03);
01632
01633   /* Byte 15 */
01634   tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
01635   pCardInfo->SD_csd.CSD_CRC   = (tmp & 0xFE) >> 1;
01636   pCardInfo->SD_csd.Reserved4 = 1;
01637
01638   /* Byte 0 */
01639   tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);
01640   pCardInfo->SD_cid.ManufacturerID = tmp;
01641
01642   /* Byte 1 */
01643   tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
01644   pCardInfo->SD_cid.OEM_AppliID = tmp << 8;
01645
01646   /* Byte 2 */
01647   tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
01648   pCardInfo->SD_cid.OEM_AppliID |= tmp;
01649
01650   /* Byte 3 */
01651   tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
01652   pCardInfo->SD_cid.ProdName1 = tmp << 24;
01653
01654   /* Byte 4 */
01655   tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);
01656   pCardInfo->SD_cid.ProdName1 |= tmp << 16;
01657
01658   /* Byte 5 */
01659   tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
01660   pCardInfo->SD_cid.ProdName1 |= tmp << 8;
01661
01662   /* Byte 6 */
01663   tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
01664   pCardInfo->SD_cid.ProdName1 |= tmp;
01665
01666   /* Byte 7 */
01667   tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
01668   pCardInfo->SD_cid.ProdName2 = tmp;
01669
01670   /* Byte 8 */
01671   tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);
01672   pCardInfo->SD_cid.ProdRev = tmp;
01673
01674   /* Byte 9 */
01675   tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
01676   pCardInfo->SD_cid.ProdSN = tmp << 24;
01677
01678   /* Byte 10 */
01679   tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
01680   pCardInfo->SD_cid.ProdSN |= tmp << 16;
01681
01682   /* Byte 11 */
01683   tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
01684   pCardInfo->SD_cid.ProdSN |= tmp << 8;
01685
01686   /* Byte 12 */
01687   tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);
01688   pCardInfo->SD_cid.ProdSN |= tmp;
01689
01690   /* Byte 13 */
01691   tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
01692   pCardInfo->SD_cid.Reserved1   |= (tmp & 0xF0) >> 4;
01693   pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
01694
01695   /* Byte 14 */
01696   tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
01697   pCardInfo->SD_cid.ManufactDate |= tmp;
01698
01699   /* Byte 15 */
01700   tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
01701   pCardInfo->SD_cid.CID_CRC   = (tmp & 0xFE) >> 1;
01702   pCardInfo->SD_cid.Reserved2 = 1;
01703
01704   return errorstate;
01705 }
01706
01707 /**
01708   * @brief  Enables wide bus operation for the requested card if supported by
01709   *         card.
01710   * @param  hsd: SD handle
01711   * @param  WideMode: Specifies the SD card wide bus mode
01712   *          This parameter can be one of the following values:
01713   *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
01714   *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
01715   *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
01716   * @retval SD Card error state
01717   */
01718 HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
01719 {
01720   HAL_SD_ErrorTypedef errorstate = SD_OK;
01721   SDMMC_InitTypeDef tmpinit;
01722
01723   /* MMC Card does not support this feature */
01724   if (hsd->CardType == MULTIMEDIA_CARD)
01725   {
01726     errorstate = SD_UNSUPPORTED_FEATURE;
01727
01728     return errorstate;
01729   }
01730   else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
01731     (hsd->CardType == HIGH_CAPACITY_SD_CARD))
01732   {
01733     if (WideMode == SDMMC_BUS_WIDE_8B)
01734     {
01735       errorstate = SD_UNSUPPORTED_FEATURE;
01736     }
01737     else if (WideMode == SDMMC_BUS_WIDE_4B)
01738     {
01739       errorstate = SD_WideBus_Enable(hsd);
01740     }
01741     else if (WideMode == SDMMC_BUS_WIDE_1B)
01742     {
01743       errorstate = SD_WideBus_Disable(hsd);
01744     }
01745     else
01746     {
01747       /* WideMode is not a valid argument*/
01748       errorstate = SD_INVALID_PARAMETER;
01749     }
01750
01751     if (errorstate == SD_OK)
01752     {
01753       /* Configure the SDMMC peripheral */
01754       tmpinit.ClockEdge           = hsd->Init.ClockEdge;
01755       tmpinit.ClockBypass         = hsd->Init.ClockBypass;
01756       tmpinit.ClockPowerSave      = hsd->Init.ClockPowerSave;
01757       tmpinit.BusWide             = WideMode;
01758       tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;
01759       tmpinit.ClockDiv            = hsd->Init.ClockDiv;
01760       SDMMC_Init(hsd->Instance, tmpinit);
01761     }
01762   }
01763
01764   return errorstate;
01765 }
01766
01767 /**
01768   * @brief  Aborts an ongoing data transfer.
01769   * @param  hsd: SD handle
01770   * @retval SD Card error state
01771   */
01772 HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
01773 {
01774   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
01775   HAL_SD_ErrorTypedef errorstate = SD_OK;
01776
01777   /* Send CMD12 STOP_TRANSMISSION  */
01778   sdmmc_cmdinitstructure.Argument         = 0;
01779   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_STOP_TRANSMISSION;
01780   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
01781   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
01782   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
01783   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01784
01785   /* Check for error conditions */
01786   errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
01787
01788   return errorstate;
01789 }
01790
01791 /**
01792   * @brief  Switches the SD card to High Speed mode.
01793   *         This API must be used after "Transfer State"
01794   * @note   This operation should be followed by the configuration
01795   *         of PLL to have SDMMCCK clock between 67 and 75 MHz
01796   * @param  hsd: SD handle
01797   * @retval SD Card error state
01798   */
01799 HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
01800 {
01801   HAL_SD_ErrorTypedef errorstate = SD_OK;
01802   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
01803   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
01804
01805   uint8_t SD_hs[64]  = {0};
01806   uint32_t SD_scr[2] = {0, 0};
01807   uint32_t SD_SPEC   = 0 ;
01808   uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;
01809
01810   /* Initialize the Data control register */
01811   hsd->Instance->DCTRL = 0;
01812
01813   /* Get SCR Register */
01814   errorstate = SD_FindSCR(hsd, SD_scr);
01815
01816   if (errorstate != SD_OK)
01817   {
01818     return errorstate;
01819   }
01820
01821   /* Test the Version supported by the card*/
01822   SD_SPEC = (SD_scr[1]  & 0x01000000) | (SD_scr[1]  & 0x02000000);
01823
01824   if (SD_SPEC != SD_ALLZERO)
01825   {
01826     /* Set Block Size for Card */
01827     sdmmc_cmdinitstructure.Argument         = (uint32_t)64;
01828     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
01829     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
01830     sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
01831     sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
01832     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01833
01834     /* Check for error conditions */
01835     errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
01836
01837     if (errorstate != SD_OK)
01838     {
01839       return errorstate;
01840     }
01841
01842     /* Configure the SD DPSM (Data Path State Machine) */
01843     sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
01844     sdmmc_datainitstructure.DataLength    = 64;
01845     sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
01846     sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
01847     sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
01848     sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
01849     SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
01850
01851     /* Send CMD6 switch mode */
01852     sdmmc_cmdinitstructure.Argument         = 0x80FFFF01;
01853     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_HS_SWITCH;
01854     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01855
01856     /* Check for error conditions */
01857     errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
01858
01859     if (errorstate != SD_OK)
01860     {
01861       return errorstate;
01862     }
01863
01864     while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
01865     {
01866       if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
01867       {
01868         for (count = 0; count < 8; count++)
01869         {
01870           *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);
01871         }
01872
01873         tempbuff += 8;
01874       }
01875     }
01876
01877     if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
01878     {
01879       __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
01880
01881       errorstate = SD_DATA_TIMEOUT;
01882
01883       return errorstate;
01884     }
01885     else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
01886     {
01887       __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
01888
01889       errorstate = SD_DATA_CRC_FAIL;
01890
01891       return errorstate;
01892     }
01893     else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
01894     {
01895       __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
01896
01897       errorstate = SD_RX_OVERRUN;
01898
01899       return errorstate;
01900     }
01901     else
01902     {
01903       /* No error flag set */
01904     }
01905
01906     count = SD_DATATIMEOUT;
01907
01908     while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
01909     {
01910       *tempbuff = SDMMC_ReadFIFO(hsd->Instance);
01911       tempbuff++;
01912       count--;
01913     }
01914
01915     /* Clear all the static flags */
01916     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
01917
01918     /* Test if the switch mode HS is ok */
01919     if ((SD_hs[13]& 2) != 2)
01920     {
01921       errorstate = SD_UNSUPPORTED_FEATURE;
01922     }
01923   }
01924
01925   return errorstate;
01926 }
01927
01928 /**
01929   * @}
01930   */
01931
01932 /** @addtogroup SD_Exported_Functions_Group4
01933  *  @brief   Peripheral State functions
01934  *
01935 @verbatim
01936   ==============================================================================
01937                       ##### Peripheral State functions #####
01938   ==============================================================================
01939   [..]
01940     This subsection permits to get in runtime the status of the peripheral
01941     and the data flow.
01942
01943 @endverbatim
01944   * @{
01945   */
01946
01947 /**
01948   * @brief  Returns the current SD card's status.
01949   * @param  hsd: SD handle
01950   * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
01951   *         SD Status register)
01952   * @retval SD Card error state
01953   */
01954 HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
01955 {
01956   SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
01957   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
01958   HAL_SD_ErrorTypedef errorstate = SD_OK;
01959   uint32_t count = 0;
01960
01961   /* Check SD response */
01962   if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
01963   {
01964     errorstate = SD_LOCK_UNLOCK_FAILED;
01965
01966     return errorstate;
01967   }
01968
01969   /* Set block size for card if it is not equal to current block size for card */
01970   sdmmc_cmdinitstructure.Argument         = 64;
01971   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
01972   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
01973   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
01974   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
01975   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01976
01977   /* Check for error conditions */
01978   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
01979
01980   if (errorstate != SD_OK)
01981   {
01982     return errorstate;
01983   }
01984
01985   /* Send CMD55 */
01986   sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
01987   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
01988   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
01989
01990   /* Check for error conditions */
01991   errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
01992
01993   if (errorstate != SD_OK)
01994   {
01995     return errorstate;
01996   }
01997
01998   /* Configure the SD DPSM (Data Path State Machine) */
01999   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
02000   sdmmc_datainitstructure.DataLength    = 64;
02001   sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
02002   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
02003   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
02004   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
02005   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
02006
02007   /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
02008   sdmmc_cmdinitstructure.Argument         = 0;
02009   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_STATUS;
02010   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02011
02012   /* Check for error conditions */
02013   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
02014
02015   if (errorstate != SD_OK)
02016   {
02017     return errorstate;
02018   }
02019
02020   /* Get status data */
02021   while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
02022   {
02023     if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
02024     {
02025       for (count = 0; count < 8; count++)
02026       {
02027         *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);
02028       }
02029
02030       pSDstatus += 8;
02031     }
02032   }
02033
02034   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
02035   {
02036     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
02037
02038     errorstate = SD_DATA_TIMEOUT;
02039
02040     return errorstate;
02041   }
02042   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
02043   {
02044     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
02045
02046     errorstate = SD_DATA_CRC_FAIL;
02047
02048     return errorstate;
02049   }
02050   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
02051   {
02052     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
02053
02054     errorstate = SD_RX_OVERRUN;
02055
02056     return errorstate;
02057   }
02058   else
02059   {
02060     /* No error flag set */
02061   }
02062
02063   count = SD_DATATIMEOUT;
02064   while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))
02065   {
02066     *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);
02067     pSDstatus++;
02068     count--;
02069   }
02070
02071   /* Clear all the static status flags*/
02072   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02073
02074   return errorstate;
02075 }
02076
02077 /**
02078   * @brief  Gets the current sd card data status.
02079   * @param  hsd: SD handle
02080   * @retval Data Transfer state
02081   */
02082 HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
02083 {
02084   HAL_SD_CardStateTypedef cardstate =  SD_CARD_TRANSFER;
02085
02086   /* Get SD card state */
02087   cardstate = SD_GetState(hsd);
02088
02089   /* Find SD status according to card state*/
02090   if (cardstate == SD_CARD_TRANSFER)
02091   {
02092     return SD_TRANSFER_OK;
02093   }
02094   else if(cardstate == SD_CARD_ERROR)
02095   {
02096     return SD_TRANSFER_ERROR;
02097   }
02098   else
02099   {
02100     return SD_TRANSFER_BUSY;
02101   }
02102 }
02103
02104 /**
02105   * @brief  Gets the SD card status.
02106   * @param  hsd: SD handle
02107   * @param  pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
02108   *         will contain the SD card status information
02109   * @retval SD Card error state
02110   */
02111 HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
02112 {
02113   HAL_SD_ErrorTypedef errorstate = SD_OK;
02114   uint32_t tmp = 0;
02115   uint32_t sd_status[16];
02116
02117   errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
02118
02119   if (errorstate  != SD_OK)
02120   {
02121     return errorstate;
02122   }
02123
02124   /* Byte 0 */
02125   tmp = (sd_status[0] & 0xC0) >> 6;
02126   pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
02127
02128   /* Byte 0 */
02129   tmp = (sd_status[0] & 0x20) >> 5;
02130   pCardStatus->SECURED_MODE = (uint8_t)tmp;
02131
02132   /* Byte 2 */
02133   tmp = (sd_status[2] & 0xFF);
02134   pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);
02135
02136   /* Byte 3 */
02137   tmp = (sd_status[3] & 0xFF);
02138   pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
02139
02140   /* Byte 4 */
02141   tmp = (sd_status[4] & 0xFF);
02142   pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);
02143
02144   /* Byte 5 */
02145   tmp = (sd_status[5] & 0xFF);
02146   pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);
02147
02148   /* Byte 6 */
02149   tmp = (sd_status[6] & 0xFF);
02150   pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);
02151
02152   /* Byte 7 */
02153   tmp = (sd_status[7] & 0xFF);
02154   pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
02155
02156   /* Byte 8 */
02157   tmp = (sd_status[8] & 0xFF);
02158   pCardStatus->SPEED_CLASS = (uint8_t)tmp;
02159
02160   /* Byte 9 */
02161   tmp = (sd_status[9] & 0xFF);
02162   pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
02163
02164   /* Byte 10 */
02165   tmp = (sd_status[10] & 0xF0) >> 4;
02166   pCardStatus->AU_SIZE = (uint8_t)tmp;
02167
02168   /* Byte 11 */
02169   tmp = (sd_status[11] & 0xFF);
02170   pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);
02171
02172   /* Byte 12 */
02173   tmp = (sd_status[12] & 0xFF);
02174   pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
02175
02176   /* Byte 13 */
02177   tmp = (sd_status[13] & 0xFC) >> 2;
02178   pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
02179
02180   /* Byte 13 */
02181   tmp = (sd_status[13] & 0x3);
02182   pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
02183
02184   return errorstate;
02185 }
02186
02187 /**
02188   * @}
02189   */
02190
02191 /**
02192   * @}
02193   */
02194
02195 /* Private function ----------------------------------------------------------*/
02196 /** @addtogroup SD_Private_Functions
02197   * @{
02198   */
02199
02200 /**
02201   * @brief  SD DMA transfer complete Rx callback.
02202   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02203   *                the configuration information for the specified DMA module.
02204   * @retval None
02205   */
02206 static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
02207 {
02208   SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02209
02210   /* DMA transfer is complete */
02211   hsd->DmaTransferCplt = 1;
02212
02213   /* Wait until SD transfer is complete */
02214   while(hsd->SdTransferCplt == 0)
02215   {
02216   }
02217
02218   /* Disable the DMA channel */
02219   HAL_DMA_Abort(hdma);
02220
02221   /* Transfer complete user callback */
02222   HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);
02223 }
02224
02225 /**
02226   * @brief  SD DMA transfer Error Rx callback.
02227   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02228   *                the configuration information for the specified DMA module.
02229   * @retval None
02230   */
02231 static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
02232 {
02233   SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02234
02235   /* Transfer complete user callback */
02236   HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
02237 }
02238
02239 /**
02240   * @brief  SD DMA transfer complete Tx callback.
02241   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02242   *                the configuration information for the specified DMA module.
02243   * @retval None
02244   */
02245 static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
02246 {
02247   SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02248
02249   /* DMA transfer is complete */
02250   hsd->DmaTransferCplt = 1;
02251
02252   /* Wait until SD transfer is complete */
02253   while(hsd->SdTransferCplt == 0)
02254   {
02255   }
02256
02257   /* Disable the DMA channel */
02258   HAL_DMA_Abort(hdma);
02259
02260   /* Transfer complete user callback */
02261   HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);
02262 }
02263
02264 /**
02265   * @brief  SD DMA transfer Error Tx callback.
02266   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02267   *                the configuration information for the specified DMA module.
02268   * @retval None
02269   */
02270 static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
02271 {
02272   SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02273
02274   /* Transfer complete user callback */
02275   HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
02276 }
02277
02278 /**
02279   * @brief  Returns the SD current state.
02280   * @param  hsd: SD handle
02281   * @retval SD card current state
02282   */
02283 static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
02284 {
02285   uint32_t resp1 = 0;
02286
02287   if (SD_SendStatus(hsd, &resp1) != SD_OK)
02288   {
02289     return SD_CARD_ERROR;
02290   }
02291   else
02292   {
02293     return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
02294   }
02295 }
02296
02297 /**
02298   * @brief  Initializes all cards or single card as the case may be Card(s) come
02299   *         into standby state.
02300   * @param  hsd: SD handle
02301   * @retval SD Card error state
02302   */
02303 static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
02304 {
02305   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
02306   HAL_SD_ErrorTypedef errorstate = SD_OK;
02307   uint16_t sd_rca = 1;
02308
02309   if(SDMMC_GetPowerState(hsd->Instance) == 0) /* Power off */
02310   {
02311     errorstate = SD_REQUEST_NOT_APPLICABLE;
02312
02313     return errorstate;
02314   }
02315
02316   if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
02317   {
02318     /* Send CMD2 ALL_SEND_CID */
02319     sdmmc_cmdinitstructure.Argument         = 0;
02320     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_ALL_SEND_CID;
02321     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_LONG;
02322     sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02323     sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02324     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02325
02326     /* Check for error conditions */
02327     errorstate = SD_CmdResp2Error(hsd);
02328
02329     if(errorstate != SD_OK)
02330     {
02331       return errorstate;
02332     }
02333
02334     /* Get Card identification number data */
02335     hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02336     hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
02337     hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
02338     hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
02339   }
02340
02341   if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1)    || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
02342      (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
02343   {
02344     /* Send CMD3 SET_REL_ADDR with argument 0 */
02345     /* SD Card publishes its RCA. */
02346     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_REL_ADDR;
02347     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02348     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02349
02350     /* Check for error conditions */
02351     errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
02352
02353     if(errorstate != SD_OK)
02354     {
02355       return errorstate;
02356     }
02357   }
02358
02359   if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
02360   {
02361     /* Get the SD card RCA */
02362     hsd->RCA = sd_rca;
02363
02364     /* Send CMD9 SEND_CSD with argument as card's RCA */
02365     sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
02366     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_CSD;
02367     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_LONG;
02368     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02369
02370     /* Check for error conditions */
02371     errorstate = SD_CmdResp2Error(hsd);
02372
02373     if(errorstate != SD_OK)
02374     {
02375       return errorstate;
02376     }
02377
02378     /* Get Card Specific Data */
02379     hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02380     hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
02381     hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
02382     hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
02383   }
02384
02385   /* All cards are initialized */
02386   return errorstate;
02387 }
02388
02389 /**
02390   * @brief  Selects or Deselects the corresponding card.
02391   * @param  hsd: SD handle
02392   * @param  addr: Address of the card to be selected
02393   * @retval SD Card error state
02394   */
02395 static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)
02396 {
02397   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
02398   HAL_SD_ErrorTypedef errorstate = SD_OK;
02399
02400   /* Send CMD7 SDMMC_SEL_DESEL_CARD */
02401   sdmmc_cmdinitstructure.Argument         = (uint32_t)addr;
02402   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEL_DESEL_CARD;
02403   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02404   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02405   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02406   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02407
02408   /* Check for error conditions */
02409   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
02410
02411   return errorstate;
02412 }
02413
02414 /**
02415   * @brief  Enquires cards about their operating voltage and configures clock
02416   *         controls and stores SD information that will be needed in future
02417   *         in the SD handle.
02418   * @param  hsd: SD handle
02419   * @retval SD Card error state
02420   */
02421 static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
02422 {
02423   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
02424   __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
02425   uint32_t response = 0, count = 0, validvoltage = 0;
02426   uint32_t sdtype = SD_STD_CAPACITY;
02427
02428   /* Power ON Sequence -------------------------------------------------------*/
02429   /* Disable SDMMC Clock */
02430   __HAL_SD_SDMMC_DISABLE(hsd);
02431
02432   /* Set Power State to ON */
02433   SDMMC_PowerState_ON(hsd->Instance);
02434
02435   /* 1ms: required power up waiting time before starting the SD initialization
02436      sequence */
02437   HAL_Delay(1);
02438
02439   /* Enable SDMMC Clock */
02440   __HAL_SD_SDMMC_ENABLE(hsd);
02441
02442   /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
02443   /* No CMD response required */
02444   sdmmc_cmdinitstructure.Argument         = 0;
02445   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_GO_IDLE_STATE;
02446   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_NO;
02447   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02448   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02449   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02450
02451   /* Check for error conditions */
02452   errorstate = SD_CmdError(hsd);
02453
02454   if(errorstate != SD_OK)
02455   {
02456     /* CMD Response Timeout (wait for CMDSENT flag) */
02457     return errorstate;
02458   }
02459
02460   /* CMD8: SEND_IF_COND ------------------------------------------------------*/
02461   /* Send CMD8 to verify SD card interface operating condition */
02462   /* Argument: - [31:12]: Reserved (shall be set to '0')
02463   - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
02464   - [7:0]: Check Pattern (recommended 0xAA) */
02465   /* CMD Response: R7 */
02466   sdmmc_cmdinitstructure.Argument         = SD_CHECK_PATTERN;
02467   sdmmc_cmdinitstructure.CmdIndex         = SD_SDMMC_SEND_IF_COND;
02468   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02469   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02470
02471   /* Check for error conditions */
02472   errorstate = SD_CmdResp7Error(hsd);
02473
02474   if (errorstate == SD_OK)
02475   {
02476     /* SD Card 2.0 */
02477     hsd->CardType = STD_CAPACITY_SD_CARD_V2_0;
02478     sdtype        = SD_HIGH_CAPACITY;
02479   }
02480
02481   /* Send CMD55 */
02482   sdmmc_cmdinitstructure.Argument         = 0;
02483   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
02484   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02485
02486   /* Check for error conditions */
02487   errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
02488
02489   /* If errorstate is Command Timeout, it is a MMC card */
02490   /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
02491      or SD card 1.x */
02492   if(errorstate == SD_OK)
02493   {
02494     /* SD CARD */
02495     /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
02496     while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
02497     {
02498
02499       /* SEND CMD55 APP_CMD with RCA as 0 */
02500       sdmmc_cmdinitstructure.Argument         = 0;
02501       sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
02502       sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02503       sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02504       sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02505       SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02506
02507       /* Check for error conditions */
02508       errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
02509
02510       if(errorstate != SD_OK)
02511       {
02512         return errorstate;
02513       }
02514
02515       /* Send CMD41 */
02516       sdmmc_cmdinitstructure.Argument         = SD_VOLTAGE_WINDOW_SD | sdtype;
02517       sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_OP_COND;
02518       sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02519       sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02520       sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02521       SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02522
02523       /* Check for error conditions */
02524       errorstate = SD_CmdResp3Error(hsd);
02525
02526       if(errorstate != SD_OK)
02527       {
02528         return errorstate;
02529       }
02530
02531       /* Get command response */
02532       response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02533
02534       /* Get operating voltage*/
02535       validvoltage = (((response >> 31) == 1) ? 1 : 0);
02536
02537       count++;
02538     }
02539
02540     if(count >= SD_MAX_VOLT_TRIAL)
02541     {
02542       errorstate = SD_INVALID_VOLTRANGE;
02543
02544       return errorstate;
02545     }
02546
02547     if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
02548     {
02549       hsd->CardType = HIGH_CAPACITY_SD_CARD;
02550     }
02551
02552   } /* else MMC Card */
02553
02554   return errorstate;
02555 }
02556
02557 /**
02558   * @brief  Turns the SDMMC output signals off.
02559   * @param  hsd: SD handle
02560   * @retval SD Card error state
02561   */
02562 static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
02563 {
02564   HAL_SD_ErrorTypedef errorstate = SD_OK;
02565
02566   /* Set Power State to OFF */
02567   SDMMC_PowerState_OFF(hsd->Instance);
02568
02569   return errorstate;
02570 }
02571
02572 /**
02573   * @brief  Returns the current card's status.
02574   * @param  hsd: SD handle
02575   * @param  pCardStatus: pointer to the buffer that will contain the SD card
02576   *         status (Card Status register)
02577   * @retval SD Card error state
02578   */
02579 static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
02580 {
02581   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
02582   HAL_SD_ErrorTypedef errorstate = SD_OK;
02583
02584   if(pCardStatus == NULL)
02585   {
02586     errorstate = SD_INVALID_PARAMETER;
02587
02588     return errorstate;
02589   }
02590
02591   /* Send Status command */
02592   sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
02593   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
02594   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
02595   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
02596   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
02597   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
02598
02599   /* Check for error conditions */
02600   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
02601
02602   if(errorstate != SD_OK)
02603   {
02604     return errorstate;
02605   }
02606
02607   /* Get SD card status */
02608   *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02609
02610   return errorstate;
02611 }
02612
02613 /**
02614   * @brief  Checks for error conditions for CMD0.
02615   * @param  hsd: SD handle
02616   * @retval SD Card error state
02617   */
02618 static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
02619 {
02620   HAL_SD_ErrorTypedef errorstate = SD_OK;
02621   uint32_t timeout, tmp;
02622
02623   timeout = SDMMC_CMD0TIMEOUT;
02624
02625   tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);
02626
02627   while((timeout > 0) && (!tmp))
02628   {
02629     tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);
02630     timeout--;
02631   }
02632
02633   if(timeout == 0)
02634   {
02635     errorstate = SD_CMD_RSP_TIMEOUT;
02636     return errorstate;
02637   }
02638
02639   /* Clear all the static flags */
02640   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02641
02642   return errorstate;
02643 }
02644
02645 /**
02646   * @brief  Checks for error conditions for R7 response.
02647   * @param  hsd: SD handle
02648   * @retval SD Card error state
02649   */
02650 static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
02651 {
02652   HAL_SD_ErrorTypedef errorstate = SD_ERROR;
02653   uint32_t timeout = SDMMC_CMD0TIMEOUT, tmp;
02654
02655   tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT);
02656
02657   while((!tmp) && (timeout > 0))
02658   {
02659     tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT);
02660     timeout--;
02661   }
02662
02663   tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02664
02665   if((timeout == 0) || tmp)
02666   {
02667     /* Card is not V2.0 compliant or card does not support the set voltage range */
02668     errorstate = SD_CMD_RSP_TIMEOUT;
02669
02670     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02671
02672     return errorstate;
02673   }
02674
02675   if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDREND))
02676   {
02677     /* Card is SD V2.0 compliant */
02678     errorstate = SD_OK;
02679
02680     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CMDREND);
02681
02682     return errorstate;
02683   }
02684
02685   return errorstate;
02686 }
02687
02688 /**
02689   * @brief  Checks for error conditions for R1 response.
02690   * @param  hsd: SD handle
02691   * @param  SD_CMD: The sent command index
02692   * @retval SD Card error state
02693   */
02694 static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
02695 {
02696   HAL_SD_ErrorTypedef errorstate = SD_OK;
02697   uint32_t response_r1;
02698
02699   while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
02700   {
02701   }
02702
02703   if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
02704   {
02705     errorstate = SD_CMD_RSP_TIMEOUT;
02706
02707     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02708
02709     return errorstate;
02710   }
02711   else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
02712   {
02713     errorstate = SD_CMD_CRC_FAIL;
02714
02715     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
02716
02717     return errorstate;
02718   }
02719
02720   /* Check response received is of desired command */
02721   if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)
02722   {
02723     errorstate = SD_ILLEGAL_CMD;
02724
02725     return errorstate;
02726   }
02727
02728   /* Clear all the static flags */
02729   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02730
02731   /* We have received response, retrieve it for analysis  */
02732   response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02733
02734   if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
02735   {
02736     return errorstate;
02737   }
02738
02739   if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
02740   {
02741     return(SD_ADDR_OUT_OF_RANGE);
02742   }
02743
02744   if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
02745   {
02746     return(SD_ADDR_MISALIGNED);
02747   }
02748
02749   if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
02750   {
02751     return(SD_BLOCK_LEN_ERR);
02752   }
02753
02754   if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
02755   {
02756     return(SD_ERASE_SEQ_ERR);
02757   }
02758
02759   if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
02760   {
02761     return(SD_BAD_ERASE_PARAM);
02762   }
02763
02764   if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
02765   {
02766     return(SD_WRITE_PROT_VIOLATION);
02767   }
02768
02769   if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
02770   {
02771     return(SD_LOCK_UNLOCK_FAILED);
02772   }
02773
02774   if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
02775   {
02776     return(SD_COM_CRC_FAILED);
02777   }
02778
02779   if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
02780   {
02781     return(SD_ILLEGAL_CMD);
02782   }
02783
02784   if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
02785   {
02786     return(SD_CARD_ECC_FAILED);
02787   }
02788
02789   if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
02790   {
02791     return(SD_CC_ERROR);
02792   }
02793
02794   if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
02795   {
02796     return(SD_GENERAL_UNKNOWN_ERROR);
02797   }
02798
02799   if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
02800   {
02801     return(SD_STREAM_READ_UNDERRUN);
02802   }
02803
02804   if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
02805   {
02806     return(SD_STREAM_WRITE_OVERRUN);
02807   }
02808
02809   if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
02810   {
02811     return(SD_CID_CSD_OVERWRITE);
02812   }
02813
02814   if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
02815   {
02816     return(SD_WP_ERASE_SKIP);
02817   }
02818
02819   if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
02820   {
02821     return(SD_CARD_ECC_DISABLED);
02822   }
02823
02824   if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
02825   {
02826     return(SD_ERASE_RESET);
02827   }
02828
02829   if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
02830   {
02831     return(SD_AKE_SEQ_ERROR);
02832   }
02833
02834   return errorstate;
02835 }
02836
02837 /**
02838   * @brief  Checks for error conditions for R3 (OCR) response.
02839   * @param  hsd: SD handle
02840   * @retval SD Card error state
02841   */
02842 static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
02843 {
02844   HAL_SD_ErrorTypedef errorstate = SD_OK;
02845
02846   while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
02847   {
02848   }
02849
02850   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
02851   {
02852     errorstate = SD_CMD_RSP_TIMEOUT;
02853
02854     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02855
02856     return errorstate;
02857   }
02858
02859   /* Clear all the static flags */
02860   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02861
02862   return errorstate;
02863 }
02864
02865 /**
02866   * @brief  Checks for error conditions for R2 (CID or CSD) response.
02867   * @param  hsd: SD handle
02868   * @retval SD Card error state
02869   */
02870 static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
02871 {
02872   HAL_SD_ErrorTypedef errorstate = SD_OK;
02873
02874   while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
02875   {
02876   }
02877
02878   if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
02879   {
02880     errorstate = SD_CMD_RSP_TIMEOUT;
02881
02882     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02883
02884     return errorstate;
02885   }
02886   else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
02887   {
02888     errorstate = SD_CMD_CRC_FAIL;
02889
02890     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
02891
02892     return errorstate;
02893   }
02894   else
02895   {
02896     /* No error flag set */
02897   }
02898
02899   /* Clear all the static flags */
02900   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02901
02902   return errorstate;
02903 }
02904
02905 /**
02906   * @brief  Checks for error conditions for R6 (RCA) response.
02907   * @param  hsd: SD handle
02908   * @param  SD_CMD: The sent command index
02909   * @param  pRCA: Pointer to the variable that will contain the SD card relative
02910   *         address RCA
02911   * @retval SD Card error state
02912   */
02913 static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
02914 {
02915   HAL_SD_ErrorTypedef errorstate = SD_OK;
02916   uint32_t response_r1;
02917
02918   while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
02919   {
02920   }
02921
02922   if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
02923   {
02924     errorstate = SD_CMD_RSP_TIMEOUT;
02925
02926     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
02927
02928     return errorstate;
02929   }
02930   else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
02931   {
02932     errorstate = SD_CMD_CRC_FAIL;
02933
02934     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
02935
02936     return errorstate;
02937   }
02938   else
02939   {
02940     /* No error flag set */
02941   }
02942
02943   /* Check response received is of desired command */
02944   if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)
02945   {
02946     errorstate = SD_ILLEGAL_CMD;
02947
02948     return errorstate;
02949   }
02950
02951   /* Clear all the static flags */
02952   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
02953
02954   /* We have received response, retrieve it.  */
02955   response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
02956
02957   if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
02958   {
02959     *pRCA = (uint16_t) (response_r1 >> 16);
02960
02961     return errorstate;
02962   }
02963
02964   if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
02965   {
02966     return(SD_GENERAL_UNKNOWN_ERROR);
02967   }
02968
02969   if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
02970   {
02971     return(SD_ILLEGAL_CMD);
02972   }
02973
02974   if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
02975   {
02976     return(SD_COM_CRC_FAILED);
02977   }
02978
02979   return errorstate;
02980 }
02981
02982 /**
02983   * @brief  Enables the SDMMC wide bus mode.
02984   * @param  hsd: SD handle
02985   * @retval SD Card error state
02986   */
02987 static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
02988 {
02989   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
02990   HAL_SD_ErrorTypedef errorstate = SD_OK;
02991
02992   uint32_t scr[2] = {0, 0};
02993
02994   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
02995   {
02996     errorstate = SD_LOCK_UNLOCK_FAILED;
02997
02998     return errorstate;
02999   }
03000
03001   /* Get SCR Register */
03002   errorstate = SD_FindSCR(hsd, scr);
03003
03004   if(errorstate != SD_OK)
03005   {
03006     return errorstate;
03007   }
03008
03009   /* If requested card supports wide bus operation */
03010   if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
03011   {
03012     /* Send CMD55 APP_CMD with argument as card's RCA.*/
03013     sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
03014     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
03015     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
03016     sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
03017     sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
03018     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03019
03020     /* Check for error conditions */
03021     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
03022
03023     if(errorstate != SD_OK)
03024     {
03025       return errorstate;
03026     }
03027
03028     /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
03029     sdmmc_cmdinitstructure.Argument         = 2;
03030     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
03031     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03032
03033     /* Check for error conditions */
03034     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
03035
03036     if(errorstate != SD_OK)
03037     {
03038       return errorstate;
03039     }
03040
03041     return errorstate;
03042   }
03043   else
03044   {
03045     errorstate = SD_REQUEST_NOT_APPLICABLE;
03046
03047     return errorstate;
03048   }
03049 }
03050
03051 /**
03052   * @brief  Disables the SDMMC wide bus mode.
03053   * @param  hsd: SD handle
03054   * @retval SD Card error state
03055   */
03056 static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
03057 {
03058   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
03059   HAL_SD_ErrorTypedef errorstate = SD_OK;
03060
03061   uint32_t scr[2] = {0, 0};
03062
03063   if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
03064   {
03065     errorstate = SD_LOCK_UNLOCK_FAILED;
03066
03067     return errorstate;
03068   }
03069
03070   /* Get SCR Register */
03071   errorstate = SD_FindSCR(hsd, scr);
03072
03073   if(errorstate != SD_OK)
03074   {
03075     return errorstate;
03076   }
03077
03078   /* If requested card supports 1 bit mode operation */
03079   if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
03080   {
03081     /* Send CMD55 APP_CMD with argument as card's RCA */
03082     sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
03083     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
03084     sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
03085     sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
03086     sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
03087     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03088
03089     /* Check for error conditions */
03090     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
03091
03092     if(errorstate != SD_OK)
03093     {
03094       return errorstate;
03095     }
03096
03097     /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
03098     sdmmc_cmdinitstructure.Argument         = 0;
03099     sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
03100     SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03101
03102     /* Check for error conditions */
03103     errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
03104
03105     if(errorstate != SD_OK)
03106     {
03107       return errorstate;
03108     }
03109
03110     return errorstate;
03111   }
03112   else
03113   {
03114     errorstate = SD_REQUEST_NOT_APPLICABLE;
03115
03116     return errorstate;
03117   }
03118 }
03119
03120
03121 /**
03122   * @brief  Finds the SD card SCR register value.
03123   * @param  hsd: SD handle
03124   * @param  pSCR: pointer to the buffer that will contain the SCR value
03125   * @retval SD Card error state
03126   */
03127 static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
03128 {
03129   SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;
03130   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
03131   HAL_SD_ErrorTypedef errorstate = SD_OK;
03132   uint32_t index = 0;
03133   uint32_t tempscr[2] = {0, 0};
03134
03135   /* Set Block Size To 8 Bytes */
03136   /* Send CMD55 APP_CMD with argument as card's RCA */
03137   sdmmc_cmdinitstructure.Argument         = (uint32_t)8;
03138   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
03139   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
03140   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
03141   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
03142   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03143
03144   /* Check for error conditions */
03145   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
03146
03147   if(errorstate != SD_OK)
03148   {
03149     return errorstate;
03150   }
03151
03152   /* Send CMD55 APP_CMD with argument as card's RCA */
03153   sdmmc_cmdinitstructure.Argument         = (uint32_t)((hsd->RCA) << 16);
03154   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
03155   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03156
03157   /* Check for error conditions */
03158   errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
03159
03160   if(errorstate != SD_OK)
03161   {
03162     return errorstate;
03163   }
03164   sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
03165   sdmmc_datainitstructure.DataLength    = 8;
03166   sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
03167   sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
03168   sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
03169   sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
03170   SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
03171
03172   /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
03173   sdmmc_cmdinitstructure.Argument         = 0;
03174   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_SEND_SCR;
03175   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03176
03177   /* Check for error conditions */
03178   errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
03179
03180   if(errorstate != SD_OK)
03181   {
03182     return errorstate;
03183   }
03184
03185   while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))
03186   {
03187     if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))
03188     {
03189       *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);
03190       index++;
03191     }
03192   }
03193
03194   if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
03195   {
03196     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
03197
03198     errorstate = SD_DATA_TIMEOUT;
03199
03200     return errorstate;
03201   }
03202   else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
03203   {
03204     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
03205
03206     errorstate = SD_DATA_CRC_FAIL;
03207
03208     return errorstate;
03209   }
03210   else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
03211   {
03212     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
03213
03214     errorstate = SD_RX_OVERRUN;
03215
03216     return errorstate;
03217   }
03218   else
03219   {
03220     /* No error flag set */
03221   }
03222
03223   /* Clear all the static flags */
03224   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
03225
03226   *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24)  | ((tempscr[0] & SD_8TO15BITS) << 8) |\
03227     ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
03228
03229   *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24)  | ((tempscr[1] & SD_8TO15BITS) << 8) |\
03230     ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
03231
03232   return errorstate;
03233 }
03234
03235 /**
03236   * @brief  Checks if the SD card is in programming state.
03237   * @param  hsd: SD handle
03238   * @param  pStatus: pointer to the variable that will contain the SD card state
03239   * @retval SD Card error state
03240   */
03241 static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
03242 {
03243   SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
03244   HAL_SD_ErrorTypedef errorstate = SD_OK;
03245   __IO uint32_t responseR1 = 0;
03246
03247   sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
03248   sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
03249   sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;
03250   sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;
03251   sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;
03252   SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
03253
03254   while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))
03255   {
03256   }
03257
03258   if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))
03259   {
03260     errorstate = SD_CMD_RSP_TIMEOUT;
03261
03262     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);
03263
03264     return errorstate;
03265   }
03266   else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))
03267   {
03268     errorstate = SD_CMD_CRC_FAIL;
03269
03270     __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);
03271
03272     return errorstate;
03273   }
03274   else
03275   {
03276     /* No error flag set */
03277   }
03278
03279   /* Check response received is of desired command */
03280   if((uint32_t)SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
03281   {
03282     errorstate = SD_ILLEGAL_CMD;
03283
03284     return errorstate;
03285   }
03286
03287   /* Clear all the static flags */
03288   __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
03289
03290
03291   /* We have received response, retrieve it for analysis */
03292   responseR1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
03293
03294   /* Find out card status */
03295   *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);
03296
03297   if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
03298   {
03299     return errorstate;
03300   }
03301
03302   if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
03303   {
03304     return(SD_ADDR_OUT_OF_RANGE);
03305   }
03306
03307   if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
03308   {
03309     return(SD_ADDR_MISALIGNED);
03310   }
03311
03312   if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
03313   {
03314     return(SD_BLOCK_LEN_ERR);
03315   }
03316
03317   if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
03318   {
03319     return(SD_ERASE_SEQ_ERR);
03320   }
03321
03322   if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
03323   {
03324     return(SD_BAD_ERASE_PARAM);
03325   }
03326
03327   if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
03328   {
03329     return(SD_WRITE_PROT_VIOLATION);
03330   }
03331
03332   if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
03333   {
03334     return(SD_LOCK_UNLOCK_FAILED);
03335   }
03336
03337   if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
03338   {
03339     return(SD_COM_CRC_FAILED);
03340   }
03341
03342   if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
03343   {
03344     return(SD_ILLEGAL_CMD);
03345   }
03346
03347   if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
03348   {
03349     return(SD_CARD_ECC_FAILED);
03350   }
03351
03352   if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
03353   {
03354     return(SD_CC_ERROR);
03355   }
03356
03357   if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
03358   {
03359     return(SD_GENERAL_UNKNOWN_ERROR);
03360   }
03361
03362   if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
03363   {
03364     return(SD_STREAM_READ_UNDERRUN);
03365   }
03366
03367   if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
03368   {
03369     return(SD_STREAM_WRITE_OVERRUN);
03370   }
03371
03372   if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
03373   {
03374     return(SD_CID_CSD_OVERWRITE);
03375   }
03376
03377   if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
03378   {
03379     return(SD_WP_ERASE_SKIP);
03380   }
03381
03382   if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
03383   {
03384     return(SD_CARD_ECC_DISABLED);
03385   }
03386
03387   if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
03388   {
03389     return(SD_ERASE_RESET);
03390   }
03391
03392   if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
03393   {
03394     return(SD_AKE_SEQ_ERROR);
03395   }
03396
03397   return errorstate;
03398 }
03399
03400 /**
03401   * @}
03402   */
03403
03404 #endif /* HAL_SD_MODULE_ENABLED */
03405
03406 /**
03407   * @}
03408   */
03409
03410 /**
03411   * @}
03412   */
03413
03414 #endif /* SDMMC1 */
03415
03416 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sd.h Source File

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stm32l4xx_hal_sd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_sd.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_SD_H
00040 #define __STM32L4xx_HAL_SD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(SDMMC1)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32l4xx_ll_sdmmc.h"
00050
00051 /** @addtogroup STM32L4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @defgroup SD SD
00056   * @brief SD HAL module driver
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup SD_Exported_Types SD Exported Types
00062   * @{
00063   */
00064
00065 /** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition
00066   * @{
00067   */
00068 #define SD_InitTypeDef      SDMMC_InitTypeDef
00069 #define SD_TypeDef          SDMMC_TypeDef
00070
00071 typedef struct
00072 {
00073   SD_TypeDef                   *Instance;        /*!< SDMMC register base address                     */
00074
00075   SD_InitTypeDef               Init;             /*!< SD required parameters                         */
00076
00077   HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
00078
00079   uint32_t                     CardType;         /*!< SD card type                                   */
00080
00081   uint32_t                     RCA;              /*!< SD relative card address                       */
00082
00083   uint32_t                     CSD[4];           /*!< SD card specific data table                    */
00084
00085   uint32_t                     CID[4];           /*!< SD card identification number table            */
00086
00087   __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
00088
00089   __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
00090
00091   __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
00092
00093   __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
00094
00095   DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
00096
00097   DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
00098
00099 }SD_HandleTypeDef;
00100 /**
00101   * @}
00102   */
00103
00104 /** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register
00105   * @{
00106   */
00107 typedef struct
00108 {
00109   __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
00110   __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
00111   __IO uint8_t  Reserved1;            /*!< Reserved                              */
00112   __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
00113   __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
00114   __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
00115   __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
00116   __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
00117   __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
00118   __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
00119   __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
00120   __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
00121   __IO uint8_t  Reserved2;            /*!< Reserved                              */
00122   __IO uint32_t DeviceSize;           /*!< Device Size                           */
00123   __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
00124   __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
00125   __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
00126   __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
00127   __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
00128   __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
00129   __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
00130   __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
00131   __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
00132   __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
00133   __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
00134   __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
00135   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
00136   __IO uint8_t  Reserved3;            /*!< Reserved                              */
00137   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
00138   __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
00139   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
00140   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
00141   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
00142   __IO uint8_t  FileFormat;           /*!< File format                           */
00143   __IO uint8_t  ECC;                  /*!< ECC code                              */
00144   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
00145   __IO uint8_t  Reserved4;            /*!< Always 1                              */
00146
00147 }HAL_SD_CSDTypedef;
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
00153   * @{
00154   */
00155 typedef struct
00156 {
00157   __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
00158   __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
00159   __IO uint32_t ProdName1;       /*!< Product Name part1    */
00160   __IO uint8_t  ProdName2;       /*!< Product Name part2    */
00161   __IO uint8_t  ProdRev;         /*!< Product Revision      */
00162   __IO uint32_t ProdSN;          /*!< Product Serial Number */
00163   __IO uint8_t  Reserved1;       /*!< Reserved1             */
00164   __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
00165   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
00166   __IO uint8_t  Reserved2;       /*!< Always 1              */
00167
00168 }HAL_SD_CIDTypedef;
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13
00174   * @{
00175   */
00176 typedef struct
00177 {
00178   __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
00179   __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
00180   __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
00181   __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
00182   __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
00183   __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
00184   __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
00185   __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
00186   __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
00187   __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
00188
00189 }HAL_SD_CardStatusTypedef;
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup SD_Exported_Types_Group5 SD Card information structure
00195   * @{
00196   */
00197 typedef struct
00198 {
00199   HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
00200   HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
00201   uint64_t            CardCapacity;   /*!< Card capacity                          */
00202   uint32_t            CardBlockSize;  /*!< Card block size                        */
00203   uint16_t            RCA;            /*!< SD relative card address               */
00204   uint8_t             CardType;       /*!< SD card type                           */
00205
00206 }HAL_SD_CardInfoTypedef;
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition
00212   * @{
00213   */
00214 typedef enum
00215 {
00216 /**
00217   * @brief  SD specific error defines
00218   */
00219   SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */
00220   SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */
00221   SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */
00222   SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */
00223   SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */
00224   SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */
00225   SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */
00226   SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */
00227   SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */
00228   SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
00229   SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */
00230   SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */
00231   SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */
00232   SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
00233   SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */
00234   SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */
00235   SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */
00236   SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */
00237   SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */
00238   SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */
00239   SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */
00240   SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */
00241   SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */
00242   SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */
00243   SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
00244   SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */
00245   SD_INVALID_VOLTRANGE               = (27),
00246   SD_ADDR_OUT_OF_RANGE               = (28),
00247   SD_SWITCH_ERROR                    = (29),
00248   SD_SDMMC_DISABLED                  = (30),
00249   SD_SDMMC_FUNCTION_BUSY             = (31),
00250   SD_SDMMC_FUNCTION_FAILED           = (32),
00251   SD_SDMMC_UNKNOWN_FUNCTION          = (33),
00252
00253 /**
00254   * @brief  Standard error defines
00255   */
00256   SD_INTERNAL_ERROR                  = (34),
00257   SD_NOT_CONFIGURED                  = (35),
00258   SD_REQUEST_PENDING                 = (36),
00259   SD_REQUEST_NOT_APPLICABLE          = (37),
00260   SD_INVALID_PARAMETER               = (38),
00261   SD_UNSUPPORTED_FEATURE             = (39),
00262   SD_UNSUPPORTED_HW                  = (40),
00263   SD_ERROR                           = (41),
00264   SD_OK                              = (0)
00265
00266 }HAL_SD_ErrorTypedef;
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
00272   * @{
00273   */
00274 typedef enum
00275 {
00276   SD_TRANSFER_OK    = 0,  /*!< Transfer success      */
00277   SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */
00278   SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */
00279
00280 }HAL_SD_TransferStateTypedef;
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
00286   * @{
00287   */
00288 typedef enum
00289 {
00290   SD_CARD_READY                  = ((uint32_t)0x00000001),  /*!< Card state is ready                     */
00291   SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),  /*!< Card is in identification state         */
00292   SD_CARD_STANDBY                = ((uint32_t)0x00000003),  /*!< Card is in standby state                */
00293   SD_CARD_TRANSFER               = ((uint32_t)0x00000004),  /*!< Card is in transfer state               */
00294   SD_CARD_SENDING                = ((uint32_t)0x00000005),  /*!< Card is sending an operation            */
00295   SD_CARD_RECEIVING              = ((uint32_t)0x00000006),  /*!< Card is receiving operation information */
00296   SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),  /*!< Card is in programming state            */
00297   SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),  /*!< Card is disconnected                    */
00298   SD_CARD_ERROR                  = ((uint32_t)0x000000FF)   /*!< Card is in error state                  */
00299
00300 }HAL_SD_CardStateTypedef;
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
00306   * @{
00307   */
00308 typedef enum
00309 {
00310   SD_READ_SINGLE_BLOCK    = 0,  /*!< Read single block operation      */
00311   SD_READ_MULTIPLE_BLOCK  = 1,  /*!< Read multiple blocks operation   */
00312   SD_WRITE_SINGLE_BLOCK   = 2,  /*!< Write single block operation     */
00313   SD_WRITE_MULTIPLE_BLOCK = 3   /*!< Write multiple blocks operation  */
00314
00315 }HAL_SD_OperationTypedef;
00316 /**
00317   * @}
00318   */
00319
00320 /**
00321   * @}
00322   */
00323
00324 /* Exported constants --------------------------------------------------------*/
00325 /** @defgroup SD_Exported_Constants SD Exported Constants
00326   * @{
00327   */
00328
00329 /**
00330   * @brief SD Commands Index
00331   */
00332 #define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)   /*!< Resets the SD memory card.                                                               */
00333 #define SD_CMD_SEND_OP_COND                        ((uint8_t)1)   /*!< Sends host capacity support information and activates the card's initialization process. */
00334 #define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
00335 #define SD_CMD_SET_REL_ADDR                        ((uint8_t)3)   /*!< Asks the card to publish a new relative address (RCA).                                   */
00336 #define SD_CMD_SET_DSR                             ((uint8_t)4)   /*!< Programs the DSR of all cards.                                                           */
00337 #define SD_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
00338                                                                        operating condition register (OCR) content in the response on the CMD line.              */
00339 #define SD_CMD_HS_SWITCH                           ((uint8_t)6)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
00340 #define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
00341 #define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
00342                                                                        and asks the card whether card supports voltage.                                         */
00343 #define SD_CMD_SEND_CSD                            ((uint8_t)9)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
00344 #define SD_CMD_SEND_CID                            ((uint8_t)10)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
00345 #define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11)  /*!< SD card doesn't support it.                                                              */
00346 #define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)  /*!< Forces the card to stop transmission.                                                    */
00347 #define SD_CMD_SEND_STATUS                         ((uint8_t)13)  /*!< Addressed card sends its status register.                                                */
00348 #define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14)
00349 #define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)  /*!< Sends an addressed card into the inactive state.                                         */
00350 #define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)  /*!< Sets the block length (in bytes for SDSC) for all following block commands
00351                                                                        (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
00352                                                                        for SDHS and SDXC.                                                                       */
00353 #define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
00354                                                                        fixed 512 bytes in case of SDHC and SDXC.                                                */
00355 #define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)  /*!< Continuously transfers data blocks from card to host until interrupted by
00356                                                                        STOP_TRANSMISSION command.                                                               */
00357 #define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
00358 #define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20)  /*!< Speed class control command.                                                             */
00359 #define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23)  /*!< Specify block count for CMD18 and CMD25.                                                 */
00360 #define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
00361                                                                        fixed 512 bytes in case of SDHC and SDXC.                                                */
00362 #define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
00363 #define SD_CMD_PROG_CID                            ((uint8_t)26)  /*!< Reserved for manufacturers.                                                              */
00364 #define SD_CMD_PROG_CSD                            ((uint8_t)27)  /*!< Programming of the programmable bits of the CSD.                                         */
00365 #define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)  /*!< Sets the write protection bit of the addressed group.                                    */
00366 #define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)  /*!< Clears the write protection bit of the addressed group.                                  */
00367 #define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)  /*!< Asks the card to send the status of the write protection bits.                           */
00368 #define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
00369 #define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
00370 #define SD_CMD_ERASE_GRP_START                     ((uint8_t)35)  /*!< Sets the address of the first write block to be erased. Reserved for each command
00371                                                                        system set by switch function command (CMD6).                                            */
00372 #define SD_CMD_ERASE_GRP_END                       ((uint8_t)36)  /*!< Sets the address of the last write block of the continuous range to be erased.
00373                                                                        Reserved for each command system set by switch function command (CMD6).                  */
00374 #define SD_CMD_ERASE                               ((uint8_t)38)  /*!< Reserved for SD security applications.                                                   */
00375 #define SD_CMD_FAST_IO                             ((uint8_t)39)  /*!< SD card doesn't support it (Reserved).                                                   */
00376 #define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40)  /*!< SD card doesn't support it (Reserved).                                                   */
00377 #define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
00378                                                                        the SET_BLOCK_LEN command.                                                               */
00379 #define SD_CMD_APP_CMD                             ((uint8_t)55)  /*!< Indicates to the card that the next command is an application specific command rather
00380                                                                        than a standard command.                                                                 */
00381 #define SD_CMD_GEN_CMD                             ((uint8_t)56)  /*!< Used either to transfer a data block to the card or to get a data block from the card
00382                                                                        for general purpose/application specific commands.                                       */
00383 #define SD_CMD_NO_CMD                              ((uint8_t)64)
00384
00385 /**
00386   * @brief Following commands are SD Card Specific commands.
00387   *        SDMMC_APP_CMD should be sent before sending these commands.
00388   */
00389 #define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
00390                                                                        widths are given in SCR register.                                                          */
00391 #define SD_CMD_SD_APP_STATUS                       ((uint8_t)13)  /*!< (ACMD13) Sends the SD status.                                                              */
00392 #define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
00393                                                                        32bit+CRC data block.                                                                      */
00394 #define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
00395                                                                        send its operating condition register (OCR) content in the response on the CMD line.       */
00396 #define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
00397 #define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51)  /*!< Reads the SD Configuration Register (SCR).                                                 */
00398 #define SD_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52)  /*!< For SD I/O card only, reserved for security specification.                                 */
00399 #define SD_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53)  /*!< For SD I/O card only, reserved for security specification.                                 */
00400
00401 /**
00402   * @brief Following commands are SD Card Specific security commands.
00403   *        SD_CMD_APP_CMD should be sent before sending these commands.
00404   */
00405 #define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43)  /*!< For SD card only */
00406 #define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44)  /*!< For SD card only */
00407 #define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45)  /*!< For SD card only */
00408 #define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46)  /*!< For SD card only */
00409 #define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47)  /*!< For SD card only */
00410 #define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48)  /*!< For SD card only */
00411 #define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18)  /*!< For SD card only */
00412 #define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25)  /*!< For SD card only */
00413 #define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38)  /*!< For SD card only */
00414 #define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49)  /*!< For SD card only */
00415 #define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48)  /*!< For SD card only */
00416
00417 /**
00418   * @brief Supported SD Memory Cards
00419   */
00420 #define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
00421 #define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
00422 #define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
00423 #define MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
00424 #define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
00425 #define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
00426 #define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
00427 #define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
00428 /**
00429   * @}
00430   */
00431
00432 /* Exported macro ------------------------------------------------------------*/
00433 /** @defgroup SD_Exported_macros SD Exported Macros
00434  *  @brief macros to handle interrupts and specific clock configurations
00435  * @{
00436  */
00437
00438 /**
00439   * @brief  Enable the SD device.
00440   * @retval None
00441   */
00442 #define __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
00443
00444 /**
00445   * @brief  Disable the SD device.
00446   * @retval None
00447   */
00448 #define __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
00449
00450 /**
00451   * @brief  Enable the SDMMC DMA transfer.
00452   * @retval None
00453   */
00454 #define __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
00455
00456 /**
00457   * @brief  Disable the SDMMC DMA transfer.
00458   * @retval None
00459   */
00460 #define __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__)  __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
00461
00462 /**
00463   * @brief  Enable the SD device interrupt.
00464   * @param  __HANDLE__: SD Handle
00465   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
00466   *         This parameter can be one or a combination of the following values:
00467   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00468   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00469   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00470   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00471   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00472   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00473   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00474   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00475   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00476   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00477   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
00478   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
00479   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
00480   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00481   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00482   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
00483   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
00484   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
00485   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
00486   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
00487   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
00488   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
00489   * @retval None
00490   */
00491 #define __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00492
00493 /**
00494   * @brief  Disable the SD device interrupt.
00495   * @param  __HANDLE__: SD Handle
00496   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
00497   *          This parameter can be one or a combination of the following values:
00498   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00499   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00500   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00501   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00502   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00503   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00504   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00505   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00506   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00507   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00508   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
00509   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
00510   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
00511   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00512   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00513   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
00514   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
00515   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
00516   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
00517   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
00518   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
00519   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
00520   * @retval None
00521   */
00522 #define __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00523
00524 /**
00525   * @brief  Check whether the specified SD flag is set or not.
00526   * @param  __HANDLE__: SD Handle
00527   * @param  __FLAG__: specifies the flag to check.
00528   *          This parameter can be one of the following values:
00529   *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
00530   *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00531   *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
00532   *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
00533   *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
00534   *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
00535   *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
00536   *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
00537   *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00538   *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00539   *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
00540   *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
00541   *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
00542   *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
00543   *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
00544   *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
00545   *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
00546   *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
00547   *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
00548   *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
00549   *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
00550   *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
00551   * @retval The new state of SD FLAG (SET or RESET).
00552   */
00553 #define __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
00554
00555 /**
00556   * @brief  Clear the SD's pending flags.
00557   * @param  __HANDLE__: SD Handle
00558   * @param  __FLAG__: specifies the flag to clear.
00559   *          This parameter can be one or a combination of the following values:
00560   *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
00561   *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00562   *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
00563   *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
00564   *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
00565   *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
00566   *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
00567   *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
00568   *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00569   *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00570   *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
00571   * @retval None
00572   */
00573 #define __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
00574
00575 /**
00576   * @brief  Check whether the specified SD interrupt has occurred or not.
00577   * @param  __HANDLE__: SD Handle
00578   * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
00579   *          This parameter can be one of the following values:
00580   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00581   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00582   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00583   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00584   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00585   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00586   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00587   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00588   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00589   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00590   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
00591   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
00592   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
00593   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00594   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00595   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
00596   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
00597   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
00598   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
00599   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
00600   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
00601   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
00602   * @retval The new state of SD IT (SET or RESET).
00603   */
00604 #define __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00605
00606 /**
00607   * @brief  Clear the SD's interrupt pending bits.
00608   * @param  __HANDLE__: SD Handle
00609   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00610   *          This parameter can be one or a combination of the following values:
00611   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00612   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00613   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00614   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00615   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00616   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00617   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00618   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00619   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
00620   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
00621   * @retval None
00622   */
00623 #define __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00624 /**
00625   * @}
00626   */
00627
00628 /* Exported functions --------------------------------------------------------*/
00629 /** @defgroup SD_Exported_Functions SD Exported Functions
00630   * @{
00631   */
00632
00633 /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
00634   * @{
00635   */
00636 HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
00637 HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
00638 void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
00639 void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
00640 /**
00641   * @}
00642   */
00643
00644 /** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
00645   * @{
00646   */
00647 /* Blocking mode: Polling */
00648 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00649 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00650 HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
00651
00652 /* Non-Blocking mode: Interrupt */
00653 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
00654
00655 /* Callback in non blocking modes (DMA) */
00656 void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
00657 void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
00658 void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
00659 void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
00660 void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
00661 void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
00662
00663 /* Non-Blocking mode: DMA */
00664 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00665 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
00666 HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
00667 HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
00668 /**
00669   * @}
00670   */
00671
00672 /** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
00673   * @{
00674   */
00675 HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
00676 HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
00677 HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
00678 HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
00679 /**
00680   * @}
00681   */
00682
00683 /* Peripheral State functions  ************************************************/
00684 /** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
00685   * @{
00686   */
00687 HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
00688 HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
00689 HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
00690 /**
00691   * @}
00692   */
00693
00694 /**
00695   * @}
00696   */
00697
00698 /* Private types -------------------------------------------------------------*/
00699 /** @defgroup SD_Private_Types SD Private Types
00700   * @{
00701   */
00702
00703 /**
00704   * @}
00705   */
00706
00707 /* Private defines -----------------------------------------------------------*/
00708 /** @defgroup SD_Private_Defines SD Private Defines
00709   * @{
00710   */
00711
00712 /**
00713   * @}
00714   */
00715
00716 /* Private variables ---------------------------------------------------------*/
00717 /** @defgroup SD_Private_Variables SD Private Variables
00718   * @{
00719   */
00720
00721 /**
00722   * @}
00723   */
00724
00725 /* Private constants ---------------------------------------------------------*/
00726 /** @defgroup SD_Private_Constants SD Private Constants
00727   * @{
00728   */
00729
00730 /**
00731   * @}
00732   */
00733
00734 /* Private macros ------------------------------------------------------------*/
00735 /** @defgroup SD_Private_Macros SD Private Macros
00736   * @{
00737   */
00738
00739 /**
00740   * @}
00741   */
00742
00743 /* Private functions prototypes ----------------------------------------------*/
00744 /** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
00745   * @{
00746   */
00747
00748 /**
00749   * @}
00750   */
00751
00752 /* Private functions ---------------------------------------------------------*/
00753 /** @defgroup SD_Private_Functions SD Private Functions
00754   * @{
00755   */
00756
00757 /**
00758   * @}
00759   */
00760
00761 /**
00762   * @}
00763   */
00764
00765 /**
00766   * @}
00767   */
00768
00769 #endif /* SDMMC1 */
00770
00771 #ifdef __cplusplus
00772 }
00773 #endif
00774
00775
00776 #endif /* __STM32L4xx_HAL_SD_H */
00777
00778 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smartcard.c Source File

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stm32l4xx_hal_smartcard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_smartcard.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SMARTCARD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the SMARTCARD peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Error functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     The SMARTCARD HAL driver can be used as follows:
00021
00022     (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
00023     (#) Associate a USART to the SMARTCARD handle hsmartcard.
00024     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
00025         (++) Enable the USARTx interface clock.
00026         (++) USART pins configuration:
00027              (+++) Enable the clock for the USART GPIOs.
00028              (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
00029         (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
00030              and HAL_SMARTCARD_Receive_IT() APIs):
00031              (++) Configure the USARTx interrupt priority.
00032              (++) Enable the NVIC USART IRQ handle.
00033         (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
00034              and HAL_SMARTCARD_Receive_DMA() APIs):
00035              (+++) Declare a DMA handle structure for the Tx/Rx channel.
00036              (+++) Enable the DMAx interface clock.
00037              (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00038              (+++) Configure the DMA Tx/Rx channel.
00039              (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
00040              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00041
00042     (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
00043         the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
00044         error enabling or disabling in the hsmartcard handle Init structure.
00045
00046     (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
00047         in the hsmartcard handle AdvancedInit structure.
00048
00049     (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
00050         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00051              by calling the customized HAL_SMARTCARD_MspInit() API.
00052         [..]
00053         (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
00054              RXNE interrupt and Error Interrupts) will be managed using the macros
00055              __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
00056
00057     [..]
00058     [..] Three operation modes are available within this driver :
00059
00060      *** Polling mode IO operation ***
00061      =================================
00062      [..]
00063        (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
00064        (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
00065
00066      *** Interrupt mode IO operation ***
00067      ===================================
00068      [..]
00069        (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
00070        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00071             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00072        (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
00073        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00074             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00075        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00076             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00077
00078      *** DMA mode IO operation ***
00079      ==============================
00080      [..]
00081        (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
00082        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00083             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00084        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
00085        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00086             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00087        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00088             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00089
00090      *** SMARTCARD HAL driver macros list ***
00091      ========================================
00092      [..]
00093        Below the list of most used macros in SMARTCARD HAL driver.
00094
00095        (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
00096        (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
00097        (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
00098        (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
00099        (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
00100
00101      [..]
00102        (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
00103
00104   @endverbatim
00105   ******************************************************************************
00106   * @attention
00107   *
00108   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00109   *
00110   * Redistribution and use in source and binary forms, with or without modification,
00111   * are permitted provided that the following conditions are met:
00112   *   1. Redistributions of source code must retain the above copyright notice,
00113   *      this list of conditions and the following disclaimer.
00114   *   2. Redistributions in binary form must reproduce the above copyright notice,
00115   *      this list of conditions and the following disclaimer in the documentation
00116   *      and/or other materials provided with the distribution.
00117   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00118   *      may be used to endorse or promote products derived from this software
00119   *      without specific prior written permission.
00120   *
00121   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00122   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00123   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00124   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00125   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00126   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00127   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00128   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00129   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00130   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00131   *
00132   ******************************************************************************
00133   */
00134
00135 /* Includes ------------------------------------------------------------------*/
00136 #include "stm32l4xx_hal.h"
00137
00138 /** @addtogroup STM32L4xx_HAL_Driver
00139   * @{
00140   */
00141
00142 /** @defgroup SMARTCARD SMARTCARD
00143   * @brief HAL SMARTCARD module driver
00144   * @{
00145   */
00146
00147 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00148
00149 /* Private typedef -----------------------------------------------------------*/
00150 /* Private define ------------------------------------------------------------*/
00151 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00152  * @{
00153  */
00154 #define SMARTCARD_TEACK_REACK_TIMEOUT               1000      /*!< SMARTCARD TX or RX enable acknowledge time-out value  */
00155
00156 #define USART_CR1_FIELDS      ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00157                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))       /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
00158 #define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
00159 #define USART_CR2_FIELDS      ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
00160 #define USART_CR3_FIELDS      ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))   /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
00161 /**
00162   * @}
00163   */
00164
00165 /* Private macros ------------------------------------------------------------*/
00166 /* Private variables ---------------------------------------------------------*/
00167 /* Private function prototypes -----------------------------------------------*/
00168 /** @addtogroup SMARTCARD_Private_Functions
00169   * @{
00170   */
00171 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00172 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00173 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
00174 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00175 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00176 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00177 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
00178 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00179 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00180 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00181 /**
00182   * @}
00183   */
00184
00185 /* Exported functions --------------------------------------------------------*/
00186
00187 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
00188   * @{
00189   */
00190
00191 /** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00192   *  @brief    Initialization and Configuration functions
00193   *
00194 @verbatim
00195   ===============================================================================
00196               ##### Initialization and Configuration functions #####
00197   ===============================================================================
00198   [..]
00199   This subsection provides a set of functions allowing to initialize the USARTx
00200   associated to the SmartCard.
00201   (+) These parameters can be configured:
00202       (++) Baud Rate
00203       (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
00204       (++) Receiver/transmitter modes
00205       (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
00206       (++) Prescaler value
00207       (++) Guard bit time
00208       (++) NACK enabling or disabling on transmission error
00209
00210   (+) The following advanced features can be configured as well:
00211       (++) TX and/or RX pin level inversion
00212       (++) data logical level inversion
00213       (++) RX and TX pins swap
00214       (++) RX overrun detection disabling
00215       (++) DMA disabling on RX error
00216       (++) MSB first on communication line
00217       (++) Time out enabling (and if activated, timeout value)
00218       (++) Block length
00219       (++) Auto-retry counter
00220   [..]
00221   The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
00222   (details for the procedures are available in reference manual).
00223
00224 @endverbatim
00225
00226   The USART frame format is given in the following table:
00227
00228     Table 1. USART frame format.
00229     +---------------------------------------------------------------+
00230     | M1M0 bits |  PCE bit  |            USART frame                |
00231     |-----------------------|---------------------------------------|
00232     |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
00233     +---------------------------------------------------------------+
00234
00235
00236   * @{
00237   */
00238
00239 /**
00240   * @brief Initialize the SMARTCARD mode according to the specified
00241   *        parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
00242   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00243   *                    the configuration information for the specified SMARTCARD module.
00244   * @retval HAL status
00245   */
00246 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
00247 {
00248   /* Check the SMARTCARD handle allocation */
00249   if(hsmartcard == NULL)
00250   {
00251     return HAL_ERROR;
00252   }
00253
00254   /* Check the USART associated to the SmartCard */
00255   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00256
00257   if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00258   {
00259     /* Allocate lock resource and initialize it */
00260     hsmartcard->Lock = HAL_UNLOCKED;
00261
00262     /* Init the low level hardware : GPIO, CLOCK */
00263     HAL_SMARTCARD_MspInit(hsmartcard);
00264   }
00265
00266   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00267
00268   /* Disable the Peripheral to set smartcard mode */
00269   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00270
00271   /* In SmartCard mode, the following bits must be kept cleared:
00272   - LINEN in the USART_CR2 register,
00273   - HDSEL and IREN  bits in the USART_CR3 register.*/
00274   CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
00275   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
00276
00277   /* set the USART in SMARTCARD mode */
00278   SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
00279
00280   /* Set the SMARTCARD Communication parameters */
00281   if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
00282   {
00283     return HAL_ERROR;
00284   }
00285
00286   /* Set the SMARTCARD transmission completion indication */
00287   SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
00288
00289   if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
00290   {
00291     SMARTCARD_AdvFeatureConfig(hsmartcard);
00292   }
00293
00294   /* Enable the Peripheral */
00295   SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00296
00297   /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
00298   return (SMARTCARD_CheckIdleState(hsmartcard));
00299 }
00300
00301
00302 /**
00303   * @brief DeInitialize the SMARTCARD peripheral.
00304   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00305   *                    the configuration information for the specified SMARTCARD module.
00306   * @retval HAL status
00307   */
00308 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00309 {
00310   /* Check the SMARTCARD handle allocation */
00311   if(hsmartcard == NULL)
00312   {
00313     return HAL_ERROR;
00314   }
00315
00316   /* Check the parameters */
00317   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00318
00319   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00320
00321   /* Disable the Peripheral */
00322   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00323
00324   WRITE_REG(hsmartcard->Instance->CR1, 0x0);
00325   WRITE_REG(hsmartcard->Instance->CR2, 0x0);
00326   WRITE_REG(hsmartcard->Instance->CR3, 0x0);
00327   WRITE_REG(hsmartcard->Instance->RTOR, 0x0);
00328   WRITE_REG(hsmartcard->Instance->GTPR, 0x0);
00329
00330   /* DeInit the low level hardware */
00331   HAL_SMARTCARD_MspDeInit(hsmartcard);
00332
00333   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00334   hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
00335   hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
00336
00337   /* Process Unlock */
00338   __HAL_UNLOCK(hsmartcard);
00339
00340   return HAL_OK;
00341 }
00342
00343 /**
00344   * @brief Initialize the SMARTCARD MSP.
00345   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00346   *                    the configuration information for the specified SMARTCARD module.
00347   * @retval None
00348   */
00349 __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
00350 {
00351   /* Prevent unused argument(s) compilation warning */
00352   UNUSED(hsmartcard);
00353
00354   /* NOTE : This function should not be modified, when the callback is needed,
00355             the HAL_SMARTCARD_MspInit can be implemented in the user file
00356    */
00357 }
00358
00359 /**
00360   * @brief DeInitialize the SMARTCARD MSP.
00361   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00362   *                    the configuration information for the specified SMARTCARD module.
00363   * @retval None
00364   */
00365 __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00366 {
00367   /* Prevent unused argument(s) compilation warning */
00368   UNUSED(hsmartcard);
00369
00370   /* NOTE : This function should not be modified, when the callback is needed,
00371             the HAL_SMARTCARD_MspDeInit can be implemented in the user file
00372    */
00373 }
00374
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
00380   *  @brief   SMARTCARD Transmit and Receive functions
00381   *
00382 @verbatim
00383   ==============================================================================
00384                          ##### IO operation functions #####
00385   ==============================================================================
00386   [..]
00387     This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
00388
00389   [..]
00390     Smartcard is a single wire half duplex communication protocol.
00391     The Smartcard interface is designed to support asynchronous protocol Smartcards as
00392     defined in the ISO 7816-3 standard. The USART should be configured as:
00393     (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
00394     (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
00395
00396   [..]
00397     (+) There are two modes of transfer:
00398         (++) Blocking mode: The communication is performed in polling mode.
00399              The HAL status of all data processing is returned by the same function
00400              after finishing transfer.
00401         (++) No-Blocking mode: The communication is performed using Interrupts
00402              or DMA, the relevant API's return the HAL status.
00403              The end of the data processing will be indicated through the
00404              dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
00405              using DMA mode.
00406         (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
00407              will be executed respectively at the end of the Transmit or Receive process
00408              The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
00409              error is detected.
00410
00411     (+) Blocking mode APIs are :
00412         (++) HAL_SMARTCARD_Transmit()
00413         (++) HAL_SMARTCARD_Receive()
00414
00415     (+) Non Blocking mode APIs with Interrupt are :
00416         (++) HAL_SMARTCARD_Transmit_IT()
00417         (++) HAL_SMARTCARD_Receive_IT()
00418         (++) HAL_SMARTCARD_IRQHandler()
00419
00420     (+) Non Blocking mode functions with DMA are :
00421         (++) HAL_SMARTCARD_Transmit_DMA()
00422         (++) HAL_SMARTCARD_Receive_DMA()
00423
00424     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00425         (++) HAL_SMARTCARD_TxCpltCallback()
00426         (++) HAL_SMARTCARD_RxCpltCallback()
00427         (++) HAL_SMARTCARD_ErrorCallback()
00428
00429 @endverbatim
00430   * @{
00431   */
00432
00433 /**
00434   * @brief Send an amount of data in blocking mode.
00435   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00436   *                    the configuration information for the specified SMARTCARD module.
00437   * @param pData: pointer to data buffer.
00438   * @param Size: amount of data to be sent.
00439   * @param Timeout : Timeout duration.
00440   * @retval HAL status
00441   */
00442 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00443 {
00444   uint32_t tickstart = 0;
00445
00446   /* Check that a Tx process is not already ongoing */
00447   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00448   {
00449     if((pData == NULL) || (Size == 0))
00450     {
00451       return  HAL_ERROR;
00452     }
00453
00454     /* Process Locked */
00455     __HAL_LOCK(hsmartcard);
00456
00457     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00458
00459     /* Init tickstart for timeout managment*/
00460     tickstart = HAL_GetTick();
00461
00462     /* Disable the Peripheral first to update mode for TX master */
00463     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00464
00465     /* Disable Rx, enable Tx */
00466     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00467     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00468     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00469
00470     /* Enable the Peripheral */
00471     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00472
00473     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00474     hsmartcard->TxXferSize = Size;
00475     hsmartcard->TxXferCount = Size;
00476
00477     while(hsmartcard->TxXferCount > 0)
00478     {
00479       hsmartcard->TxXferCount--;
00480       if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00481       {
00482         return HAL_TIMEOUT;
00483       }
00484       hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
00485     }
00486     if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
00487     {
00488       return HAL_TIMEOUT;
00489     }
00490     /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
00491     if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
00492     {
00493       /* Disable the Peripheral first to update modes */
00494       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00495       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00496       /* Enable the Peripheral */
00497       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00498     }
00499
00500     /* At end of Tx process, restore hsmartcard->gState to Ready */
00501     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00502
00503     /* Process Unlocked */
00504     __HAL_UNLOCK(hsmartcard);
00505
00506     return HAL_OK;
00507   }
00508   else
00509   {
00510     return HAL_BUSY;
00511   }
00512 }
00513
00514 /**
00515   * @brief Receive an amount of data in blocking mode.
00516   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00517   *                    the configuration information for the specified SMARTCARD module.
00518   * @param pData: pointer to data buffer.
00519   * @param Size: amount of data to be received.
00520   * @param Timeout : Timeout duration.
00521   * @retval HAL status
00522   */
00523 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00524 {
00525   uint32_t tickstart = 0;
00526
00527   /* Check that a Rx process is not already ongoing */
00528   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00529   {
00530     if((pData == NULL) || (Size == 0))
00531     {
00532       return  HAL_ERROR;
00533     }
00534
00535     /* Process Locked */
00536     __HAL_LOCK(hsmartcard);
00537
00538     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00539     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00540
00541     /* Init tickstart for timeout managment*/
00542     tickstart = HAL_GetTick();
00543
00544     hsmartcard->RxXferSize = Size;
00545     hsmartcard->RxXferCount = Size;
00546
00547     /* Check the remain data to be received */
00548     while(hsmartcard->RxXferCount > 0)
00549     {
00550       hsmartcard->RxXferCount--;
00551       if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00552       {
00553         return HAL_TIMEOUT;
00554       }
00555       *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
00556     }
00557
00558     /* At end of Rx process, restore hsmartcard->RxState to Ready */
00559     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00560
00561     /* Process Unlocked */
00562     __HAL_UNLOCK(hsmartcard);
00563
00564     return HAL_OK;
00565   }
00566   else
00567   {
00568     return HAL_BUSY;
00569   }
00570 }
00571
00572 /**
00573   * @brief Send an amount of data in interrupt mode.
00574   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00575   *                    the configuration information for the specified SMARTCARD module.
00576   * @param pData: pointer to data buffer.
00577   * @param Size: amount of data to be sent.
00578   * @retval HAL status
00579   */
00580 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00581 {
00582   /* Check that a Tx process is not already ongoing */
00583   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00584   {
00585     if((pData == NULL) || (Size == 0))
00586     {
00587       return HAL_ERROR;
00588     }
00589
00590     /* Process Locked */
00591     __HAL_LOCK(hsmartcard);
00592
00593     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00594     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00595
00596     hsmartcard->pTxBuffPtr = pData;
00597     hsmartcard->TxXferSize = Size;
00598     hsmartcard->TxXferCount = Size;
00599
00600     /* Disable the Peripheral first to update mode for TX master */
00601     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00602
00603     /* Disable Rx, enable Tx */
00604     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00605     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00606     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00607
00608     /* Enable the Peripheral */
00609     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00610
00611     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00612     __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
00613
00614     /* Process Unlocked */
00615     __HAL_UNLOCK(hsmartcard);
00616
00617     /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
00618     __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
00619
00620     return HAL_OK;
00621   }
00622   else
00623   {
00624     return HAL_BUSY;
00625   }
00626 }
00627
00628 /**
00629   * @brief Receive an amount of data in interrupt mode.
00630   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00631   *                    the configuration information for the specified SMARTCARD module.
00632   * @param pData: pointer to data buffer.
00633   * @param Size: amount of data to be received.
00634   * @retval HAL status
00635   */
00636 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00637 {
00638   /* Check that a Rx process is not already ongoing */
00639   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00640   {
00641     if((pData == NULL) || (Size == 0))
00642     {
00643       return HAL_ERROR;
00644     }
00645
00646     /* Process Locked */
00647     __HAL_LOCK(hsmartcard);
00648
00649     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00650     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00651
00652     hsmartcard->pRxBuffPtr = pData;
00653     hsmartcard->RxXferSize = Size;
00654     hsmartcard->RxXferCount = Size;
00655
00656     /* Process Unlocked */
00657     __HAL_UNLOCK(hsmartcard);
00658
00659     /* Enable the SMARTCARD Parity Error Interrupt */
00660     __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE);
00661
00662     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00663     __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
00664
00665     /* Enable the SMARTCARD Data Register not empty Interrupt */
00666     __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
00667
00668     return HAL_OK;
00669   }
00670   else
00671   {
00672     return HAL_BUSY;
00673   }
00674 }
00675
00676 /**
00677   * @brief Send an amount of data in DMA mode.
00678   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00679   *                    the configuration information for the specified SMARTCARD module.
00680   * @param pData: pointer to data buffer.
00681   * @param Size: amount of data to be sent.
00682   * @retval HAL status
00683   */
00684 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00685 {
00686   uint32_t *tmp;
00687
00688   /* Check that a Tx process is not already ongoing */
00689   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00690   {
00691     if((pData == NULL) || (Size == 0))
00692     {
00693       return HAL_ERROR;
00694     }
00695
00696     /* Process Locked */
00697     __HAL_LOCK(hsmartcard);
00698
00699     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00700
00701     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00702     hsmartcard->pTxBuffPtr = pData;
00703     hsmartcard->TxXferSize = Size;
00704     hsmartcard->TxXferCount = Size;
00705
00706     /* Disable the Peripheral first to update mode for TX master */
00707     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00708
00709     /* Disable Rx, enable Tx */
00710     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00711     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00712     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00713
00714     /* Enable the Peripheral */
00715     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00716
00717     /* Set the SMARTCARD DMA transfer complete callback */
00718     hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
00719
00720     /* Set the SMARTCARD error callback */
00721     hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
00722
00723     /* Enable the SMARTCARD transmit DMA channel */
00724     tmp = (uint32_t*)&pData;
00725     HAL_DMA_Start_IT(hsmartcard->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsmartcard->Instance->TDR, Size);
00726
00727     /* Clear the TC flag in the ICR register */
00728     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_TCF);
00729
00730     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00731        in the SMARTCARD associated USART CR3 register */
00732     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
00733
00734     /* Process Unlocked */
00735     __HAL_UNLOCK(hsmartcard);
00736
00737     return HAL_OK;
00738   }
00739   else
00740   {
00741     return HAL_BUSY;
00742   }
00743 }
00744
00745 /**
00746   * @brief Receive an amount of data in DMA mode.
00747   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00748   *                    the configuration information for the specified SMARTCARD module.
00749   * @param pData: pointer to data buffer.
00750   * @param Size: amount of data to be received.
00751   * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
00752   *         the received data contain the parity bit (MSB position).
00753   * @retval HAL status
00754   */
00755 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00756 {
00757   uint32_t *tmp;
00758
00759   /* Check that a Rx process is not already ongoing */
00760   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00761   {
00762     if((pData == NULL) || (Size == 0))
00763     {
00764       return HAL_ERROR;
00765     }
00766
00767     /* Process Locked */
00768     __HAL_LOCK(hsmartcard);
00769
00770     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00771     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00772
00773     hsmartcard->pRxBuffPtr = pData;
00774     hsmartcard->RxXferSize = Size;
00775
00776     /* Set the SMARTCARD DMA transfer complete callback */
00777     hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
00778
00779     /* Set the SMARTCARD DMA error callback */
00780     hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
00781
00782     /* Enable the DMA channel */
00783     tmp = (uint32_t*)&pData;
00784     HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, *(uint32_t*)tmp, Size);
00785
00786     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00787        in the SMARTCARD associated USART CR3 register */
00788     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
00789
00790     /* Process Unlocked */
00791     __HAL_UNLOCK(hsmartcard);
00792
00793     return HAL_OK;
00794   }
00795   else
00796   {
00797     return HAL_BUSY;
00798   }
00799 }
00800
00801 /**
00802   * @brief Handle SMARTCARD interrupt requests.
00803   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00804   *                    the configuration information for the specified SMARTCARD module.
00805   * @retval None
00806   */
00807 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
00808 {
00809   /* SMARTCARD parity error interrupt occurred -------------------------------------*/
00810   if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_PE) != RESET))
00811   {
00812     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
00813     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
00814     /* Set the SMARTCARD states ready to be able to start again the process */
00815     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00816     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00817   }
00818
00819   /* SMARTCARD frame error interrupt occurred --------------------------------------*/
00820   if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
00821   {
00822     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
00823     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
00824     /* Set the SMARTCARD states ready to be able to start again the process */
00825     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00826     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00827   }
00828
00829   /* SMARTCARD noise error interrupt occurred --------------------------------------*/
00830   if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
00831   {
00832     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
00833     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
00834     /* Set the SMARTCARD states ready to be able to start again the process */
00835     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00836     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00837   }
00838
00839   /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
00840   if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
00841   {
00842     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
00843     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
00844     /* Set the SMARTCARD states ready to be able to start again the process */
00845     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00846     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00847   }
00848
00849   /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
00850   if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RTO) != RESET))
00851   {
00852     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
00853     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
00854     /* Set the SMARTCARD states ready to be able to start again the process */
00855     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00856     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00857   }
00858
00859   /* Call SMARTCARD Error Call back function if need be --------------------------*/
00860   if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
00861   {
00862     HAL_SMARTCARD_ErrorCallback(hsmartcard);
00863   }
00864
00865   /* SMARTCARD in mode Receiver ---------------------------------------------------*/
00866   if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RXNE) != RESET))
00867   {
00868     SMARTCARD_Receive_IT(hsmartcard);
00869     /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
00870   }
00871
00872   /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
00873   if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_EOB) != RESET))
00874   {
00875     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00876     __HAL_UNLOCK(hsmartcard);
00877     HAL_SMARTCARD_RxCpltCallback(hsmartcard);
00878     /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
00879      * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
00880     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
00881   }
00882
00883   /* SMARTCARD in mode Transmitter ------------------------------------------------*/
00884  if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET))
00885   {
00886     SMARTCARD_Transmit_IT(hsmartcard);
00887   }
00888
00889   /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
00890  if((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET))
00891   {
00892     SMARTCARD_EndTransmit_IT(hsmartcard);
00893   }
00894 }
00895
00896 /**
00897   * @brief Tx Transfer completed callback.
00898   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00899   *                    the configuration information for the specified SMARTCARD module.
00900   * @retval None
00901   */
00902 __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00903 {
00904   /* Prevent unused argument(s) compilation warning */
00905   UNUSED(hsmartcard);
00906
00907   /* NOTE : This function should not be modified, when the callback is needed,
00908             the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
00909    */
00910 }
00911
00912 /**
00913   * @brief Rx Transfer completed callback.
00914   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00915   *                    the configuration information for the specified SMARTCARD module.
00916   * @retval None
00917   */
00918 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00919 {
00920   /* Prevent unused argument(s) compilation warning */
00921   UNUSED(hsmartcard);
00922
00923   /* NOTE : This function should not be modified, when the callback is needed,
00924             the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
00925    */
00926 }
00927
00928 /**
00929   * @brief SMARTCARD error callback.
00930   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00931   *                    the configuration information for the specified SMARTCARD module.
00932   * @retval None
00933   */
00934 __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00935 {
00936   /* Prevent unused argument(s) compilation warning */
00937   UNUSED(hsmartcard);
00938
00939   /* NOTE : This function should not be modified, when the callback is needed,
00940             the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
00941    */
00942 }
00943
00944 /**
00945   * @}
00946   */
00947
00948 /** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
00949   *  @brief   SMARTCARD State and Errors functions
00950   *
00951 @verbatim
00952   ==============================================================================
00953                   ##### Peripheral State and Errors functions #####
00954   ==============================================================================
00955   [..]
00956     This subsection provides a set of functions allowing to return the State of SmartCard
00957     handle and also return Peripheral Errors occurred during communication process
00958      (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
00959          of the SMARTCARD peripheral.
00960      (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
00961          communication.
00962
00963 @endverbatim
00964   * @{
00965   */
00966
00967
00968 /**
00969   * @brief  Return the SMARTCARD handle state.
00970   * @param  hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00971   *                     the configuration information for the specified SMARTCARD module.
00972   * @retval SMARTCARD handle state
00973   */
00974 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
00975 {
00976   uint32_t temp1= 0x00, temp2 = 0x00;
00977   temp1 = hsmartcard->gState;
00978   temp2 = hsmartcard->RxState;
00979
00980   return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
00981 }
00982
00983 /**
00984   * @brief  Return the SMARTCARD handle error code.
00985   * @param  hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00986   *                     the configuration information for the specified SMARTCARD module.
00987   * @retval SMARTCARD handle Error Code
00988 */
00989 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
00990 {
00991   return hsmartcard->ErrorCode;
00992 }
00993
00994 /**
00995   * @}
00996   */
00997
00998 /**
00999   * @}
01000   */
01001
01002 /** @defgroup SMARTCARD_Private_Functions   SMARTCARD Private Functions
01003   * @{
01004   */
01005
01006 /**
01007   * @brief Send an amount of data in non-blocking mode.
01008   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
01009   *                the configuration information for the specified SMARTCARD module.
01010   *         Function called under interruption only, once
01011   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
01012   * @retval HAL status
01013   */
01014 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01015 {
01016   /* Check that a Tx process is ongoing */
01017   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
01018   {
01019
01020     if(hsmartcard->TxXferCount == 0)
01021     {
01022       /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
01023       __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
01024
01025       /* Enable the SMARTCARD Transmit Complete Interrupt */
01026       __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
01027
01028       return HAL_OK;
01029     }
01030     else
01031     {
01032       hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
01033       hsmartcard->TxXferCount--;
01034
01035       return HAL_OK;
01036     }
01037   }
01038   else
01039   {
01040     return HAL_BUSY;
01041   }
01042 }
01043
01044 /**
01045   * @brief  Wrap up transmission in non-blocking mode.
01046   * @param  hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
01047   *                     the configuration information for the specified SMARTCARD module.
01048   * @retval HAL status
01049   */
01050 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01051 {
01052   /* Disable the SMARTCARD Transmit Complete Interrupt */
01053   __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
01054
01055   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01056   if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01057   {
01058     /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01059     __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
01060   }
01061   else
01062   {
01063     /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
01064     if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
01065     {
01066       /* Disable the Peripheral first to update modes */
01067       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01068       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
01069       /* Enable the Peripheral */
01070       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01071     }
01072   }
01073
01074   /* Tx process is ended, restore hsmartcard->gState to Ready */
01075   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01076
01077   HAL_SMARTCARD_TxCpltCallback(hsmartcard);
01078
01079   return HAL_OK;
01080 }
01081
01082
01083 /**
01084   * @brief Receive an amount of data in non-blocking mode.
01085   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
01086   *                the configuration information for the specified SMARTCARD module.
01087   *         Function called under interruption only, once
01088   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
01089   * @retval HAL status
01090   */
01091 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01092 {
01093   /* Check that a Rx process is ongoing */
01094   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
01095   {
01096     *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
01097
01098     if(--hsmartcard->RxXferCount == 0)
01099     {
01100       __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
01101
01102       /* Check if a transmit process is ongoing or not. If not disable ERR IT */
01103       if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01104       {
01105         /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01106         __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
01107       }
01108
01109       /* Disable the SMARTCARD Parity Error Interrupt */
01110       __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
01111
01112       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01113
01114       HAL_SMARTCARD_RxCpltCallback(hsmartcard);
01115
01116       return HAL_OK;
01117     }
01118
01119     return HAL_OK;
01120   }
01121   else
01122   {
01123     return HAL_BUSY;
01124   }
01125 }
01126
01127 /**
01128   * @brief  Handle SMARTCARD Communication Timeout.
01129   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01130   *                    the configuration information for the specified SMARTCARD module.
01131   * @param  Flag Specifies the SMARTCARD flag to check.
01132   * @param  Status The new Flag status (SET or RESET).
01133   * @param  Tickstart Tick start value
01134   * @param  Timeout Timeout duration.
01135   * @retval HAL status
01136   */
01137 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01138 {
01139   /* Wait until flag is set */
01140   while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
01141   {
01142     /* Check for the Timeout */
01143     if(Timeout != HAL_MAX_DELAY)
01144     {
01145       if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
01146       {
01147         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01148         CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
01149         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01150
01151         hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01152         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01153
01154         /* Process Unlocked */
01155         __HAL_UNLOCK(hsmartcard);
01156
01157         return HAL_TIMEOUT;
01158       }
01159     }
01160   }
01161   return HAL_OK;
01162 }
01163
01164 /**
01165   * @brief DMA SMARTCARD transmit process complete callback.
01166   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01167   *               the configuration information for the specified DMA module.
01168   * @retval None
01169   */
01170 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01171 {
01172   SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01173   hsmartcard->TxXferCount = 0;
01174
01175   /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01176   in the SMARTCARD associated USART CR3 register */
01177   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01178
01179   /* Enable the SMARTCARD Transmit Complete Interrupt */
01180   __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
01181 }
01182
01183 /**
01184   * @brief DMA SMARTCARD receive process complete callback.
01185   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01186   *               the configuration information for the specified DMA module.
01187   * @retval None
01188   */
01189 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01190 {
01191   SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01192   hsmartcard->RxXferCount = 0;
01193
01194   /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
01195      in the SMARTCARD associated USART CR3 register */
01196   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01197
01198   /* At end of Rx process, restore hsmartcard->RxState to Ready */
01199   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01200
01201   HAL_SMARTCARD_RxCpltCallback(hsmartcard);
01202 }
01203
01204 /**
01205   * @brief DMA SMARTCARD communication error callback.
01206   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01207   *               the configuration information for the specified DMA module.
01208   * @retval None
01209   */
01210 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
01211 {
01212   SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01213   hsmartcard->RxXferCount = 0;
01214   hsmartcard->TxXferCount = 0;
01215   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01216   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01217   hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
01218   HAL_SMARTCARD_ErrorCallback(hsmartcard);
01219 }
01220
01221 /**
01222   * @brief Configure the SMARTCARD associated USART peripheral.
01223   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
01224   *                    the configuration information for the specified SMARTCARD module.
01225   * @retval None
01226   */
01227 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
01228 {
01229   uint32_t tmpreg                          = 0x00000000;
01230   SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
01231   HAL_StatusTypeDef ret                    = HAL_OK;
01232
01233   /* Check the parameters */
01234   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
01235   assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
01236   assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
01237   assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
01238   assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
01239   assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
01240   assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
01241   assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
01242   assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
01243   assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
01244   assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
01245   assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
01246   assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
01247
01248   /*-------------------------- USART CR1 Configuration -----------------------*/
01249   /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
01250    * Oversampling is forced to 16 (OVER8 = 0).
01251    * Configure the Parity and Mode:
01252    *  set PS bit according to hsmartcard->Init.Parity value
01253    *  set TE and RE bits according to hsmartcard->Init.Mode value */
01254   tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
01255   tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
01256   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
01257
01258   /*-------------------------- USART CR2 Configuration -----------------------*/
01259   tmpreg = hsmartcard->Init.StopBits;
01260   /* Synchronous mode is activated by default */
01261   tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
01262   tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
01263   tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
01264   MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
01265
01266   /*-------------------------- USART CR3 Configuration -----------------------*/
01267   /* Configure
01268    * - one-bit sampling method versus three samples' majority rule
01269    *   according to hsmartcard->Init.OneBitSampling
01270    * - NACK transmission in case of parity error according
01271    *   to hsmartcard->Init.NACKEnable
01272    * - autoretry counter according to hsmartcard->Init.AutoRetryCount     */
01273   tmpreg =  (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
01274   tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
01275   MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
01276
01277   /*-------------------------- USART GTPR Configuration ----------------------*/
01278   tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
01279   MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
01280
01281   /*-------------------------- USART RTOR Configuration ----------------------*/
01282   tmpreg =   ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
01283   if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
01284   {
01285     assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
01286     tmpreg |=  (uint32_t) hsmartcard->Init.TimeOutValue;
01287   }
01288   MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
01289
01290   /*-------------------------- USART BRR Configuration -----------------------*/
01291   SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
01292   switch (clocksource)
01293   {
01294     case SMARTCARD_CLOCKSOURCE_PCLK1:
01295       hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01296       break;
01297     case SMARTCARD_CLOCKSOURCE_PCLK2:
01298       hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01299       break;
01300     case SMARTCARD_CLOCKSOURCE_HSI:
01301       hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01302       break;
01303     case SMARTCARD_CLOCKSOURCE_SYSCLK:
01304       hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01305       break;
01306     case SMARTCARD_CLOCKSOURCE_LSE:
01307       hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
01308       break;
01309     case SMARTCARD_CLOCKSOURCE_UNDEFINED:
01310     default:
01311       ret = HAL_ERROR;
01312       break;
01313   }
01314
01315   return ret;
01316 }
01317
01318
01319 /**
01320   * @brief Configure the SMARTCARD associated USART peripheral advanced features.
01321   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
01322   *                    the configuration information for the specified SMARTCARD module.
01323   * @retval None
01324   */
01325 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
01326 {
01327   /* Check whether the set of advanced features to configure is properly set */
01328   assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
01329
01330   /* if required, configure TX pin active level inversion */
01331   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
01332   {
01333     assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
01334     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
01335   }
01336
01337   /* if required, configure RX pin active level inversion */
01338   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
01339   {
01340     assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
01341     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
01342   }
01343
01344   /* if required, configure data inversion */
01345   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
01346   {
01347     assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
01348     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
01349   }
01350
01351   /* if required, configure RX/TX pins swap */
01352   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
01353   {
01354     assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
01355     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
01356   }
01357
01358   /* if required, configure RX overrun detection disabling */
01359   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
01360   {
01361     assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
01362     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
01363   }
01364
01365   /* if required, configure DMA disabling on reception error */
01366   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
01367   {
01368     assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
01369     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
01370   }
01371
01372   /* if required, configure MSB first on communication line */
01373   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
01374   {
01375     assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
01376     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
01377   }
01378
01379 }
01380
01381 /**
01382   * @brief Check the SMARTCARD Idle State.
01383   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
01384   *                    the configuration information for the specified SMARTCARD module.
01385   * @retval HAL status
01386   */
01387 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
01388 {
01389   uint32_t tickstart = 0;
01390
01391   /* Initialize the SMARTCARD ErrorCode */
01392   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01393
01394   /* Init tickstart for timeout managment*/
01395   tickstart = HAL_GetTick();
01396
01397   /* Check if the Transmitter is enabled */
01398   if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01399   {
01400     /* Wait until TEACK flag is set */
01401     if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
01402     {
01403       return HAL_TIMEOUT;
01404     }
01405   }
01406   /* Check if the Receiver is enabled */
01407   if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01408   {
01409     /* Wait until REACK flag is set */
01410     if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
01411     {
01412       return HAL_TIMEOUT;
01413     }
01414   }
01415
01416   /* Initialize the SMARTCARD states */
01417   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01418   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01419
01420   /* Process Unlocked */
01421   __HAL_UNLOCK(hsmartcard);
01422
01423   return HAL_OK;
01424 }
01425
01426 /**
01427   * @}
01428   */
01429
01430 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
01431 /**
01432   * @}
01433   */
01434
01435 /**
01436   * @}
01437   */
01438
01439 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smartcard.h Source File

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stm32l4xx_hal_smartcard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_smartcard.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SMARTCARD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_SMARTCARD_H
00040 #define __STM32L4xx_HAL_SMARTCARD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SMARTCARD
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief SMARTCARD Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
00068                                            The baud rate register is computed using the following formula:
00069                                               Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
00070
00071   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00072                                            This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
00073
00074   uint32_t StopBits;                  /*!< Specifies the number of stop bits.
00075                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
00076
00077   uint16_t Parity;                    /*!< Specifies the parity mode.
00078                                            This parameter can be a value of @ref SMARTCARD_Parity
00079                                            @note The parity is enabled by default (PCE is forced to 1).
00080                                                  Since the WordLength is forced to 8 bits + parity, M is
00081                                                  forced to 1 and the parity bit is the 9th bit. */
00082
00083   uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00084                                            This parameter can be a value of @ref SMARTCARD_Mode */
00085
00086   uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00087                                            This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
00088
00089   uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00090                                            This parameter can be a value of @ref SMARTCARD_Clock_Phase */
00091
00092   uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00093                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00094                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
00095
00096   uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00097                                            Selecting the single sample method increases the receiver tolerance to clock
00098                                            deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
00099
00100   uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler. */
00101
00102   uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
00103
00104   uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
00105                                            in case of parity error.
00106                                            This parameter can be a value of @ref SMARTCARD_NACK_Enable */
00107
00108   uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
00109                                             This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
00110
00111   uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
00112                                            it is used to implement the Character Wait Time (CWT) and
00113                                            Block Wait Time (BWT). It is coded over 24 bits. */
00114
00115   uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
00116                                            This parameter can be any value from 0x0 to 0xFF */
00117
00118   uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
00119                                             receive and transmit mode). When set to 0, retransmission is
00120                                             disabled. Otherwise, its maximum value is 7 (before signalling
00121                                             an error) */
00122
00123 }SMARTCARD_InitTypeDef;
00124
00125 /**
00126   * @brief  SMARTCARD advanced features initalization structure definition
00127   */
00128 typedef struct
00129 {
00130   uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
00131                                            advanced features may be initialized at the same time. This parameter
00132                                            can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
00133
00134   uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
00135                                            This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
00136
00137   uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
00138                                            This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
00139
00140   uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
00141                                            vs negative/inverted logic).
00142                                            This parameter can be a value of @ref SMARTCARD_Data_Inv */
00143
00144   uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
00145                                            This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
00146
00147   uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
00148                                            This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
00149
00150   uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
00151                                            This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
00152
00153   uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
00154                                            This parameter can be a value of @ref SMARTCARD_MSB_First */
00155
00156   uint16_t TxCompletionIndication;     /*!< Specifies which transmission completion indication is used: before (when
00157                                             relevant flag is available) or once guard time period has elapsed.
00158                                            This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
00159 }SMARTCARD_AdvFeatureInitTypeDef;
00160
00161 /**
00162   * @brief HAL SMARTCARD State structures definition
00163   * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
00164   *        - gState contains SMARTCARD state information related to global Handle management
00165   *          and also information related to Tx operations.
00166   *          gState value coding follow below described bitmap :
00167   *          b7-b6  Error information
00168   *             00 : No Error
00169   *             01 : (Not Used)
00170   *             10 : Timeout
00171   *             11 : Error
00172   *          b5     IP initilisation status
00173   *             0  : Reset (IP not initialized)
00174   *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
00175   *          b4-b3  (not used)
00176   *             xx : Should be set to 00
00177   *          b2     Intrinsic process state
00178   *             0  : Ready
00179   *             1  : Busy (IP busy with some configuration or internal operations)
00180   *          b1     (not used)
00181   *             x  : Should be set to 0
00182   *          b0     Tx state
00183   *             0  : Ready (no Tx operation ongoing)
00184   *             1  : Busy (Tx operation ongoing)
00185   *        - RxState contains information related to Rx operations.
00186   *          RxState value coding follow below described bitmap :
00187   *          b7-b6  (not used)
00188   *             xx : Should be set to 00
00189   *          b5     IP initilisation status
00190   *             0  : Reset (IP not initialized)
00191   *             1  : Init done (IP not initialized)
00192   *          b4-b2  (not used)
00193   *            xxx : Should be set to 000
00194   *          b1     Rx state
00195   *             0  : Ready (no Rx operation ongoing)
00196   *             1  : Busy (Rx operation ongoing)
00197   *          b0     (not used)
00198   *             x  : Should be set to 0.
00199   */
00200 typedef enum
00201 {
00202   HAL_SMARTCARD_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
00203                                                         Value is allowed for gState and RxState */
00204   HAL_SMARTCARD_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
00205                                                         Value is allowed for gState and RxState */
00206   HAL_SMARTCARD_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
00207                                                         Value is allowed for gState only */
00208   HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
00209                                                         Value is allowed for gState only */
00210   HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
00211                                                         Value is allowed for RxState only */
00212   HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
00213                                                         Not to be used for neither gState nor RxState.
00214                                                         Value is result of combination (Or) between gState and RxState values */
00215   HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
00216                                                         Value is allowed for gState only */
00217   HAL_SMARTCARD_STATE_ERROR             = 0xE0U    /*!< Error
00218                                                         Value is allowed for gState only */
00219 }HAL_SMARTCARD_StateTypeDef;
00220
00221 /**
00222   * @brief  HAL SMARTCARD Error Code structure definition
00223   */
00224 typedef enum
00225 {
00226   HAL_SMARTCARD_ERROR_NONE      = 0x00,    /*!< No error                */
00227   HAL_SMARTCARD_ERROR_PE        = 0x01,    /*!< Parity error            */
00228   HAL_SMARTCARD_ERROR_NE        = 0x02,    /*!< Noise error             */
00229   HAL_SMARTCARD_ERROR_FE        = 0x04,    /*!< frame error             */
00230   HAL_SMARTCARD_ERROR_ORE       = 0x08,    /*!< Overrun error           */
00231   HAL_SMARTCARD_ERROR_DMA       = 0x10,    /*!< DMA transfer error      */
00232   HAL_SMARTCARD_ERROR_RTO       = 0x20     /*!< Receiver TimeOut error  */
00233 }HAL_SMARTCARD_ErrorTypeDef;
00234
00235 /**
00236   * @brief  SMARTCARD handle Structure definition
00237   */
00238 typedef struct
00239 {
00240   USART_TypeDef                   *Instance;        /*!< USART registers base address                          */
00241
00242   SMARTCARD_InitTypeDef           Init;             /*!< SmartCard communication parameters                    */
00243
00244   SMARTCARD_AdvFeatureInitTypeDef AdvancedInit;     /*!< SmartCard advanced features initialization parameters */
00245
00246   uint8_t                         *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer               */
00247
00248   uint16_t                        TxXferSize;       /*!< SmartCard Tx Transfer size                            */
00249
00250   uint16_t                        TxXferCount;      /*!< SmartCard Tx Transfer Counter                         */
00251
00252   uint8_t                         *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer               */
00253
00254   uint16_t                        RxXferSize;       /*!< SmartCard Rx Transfer size                            */
00255
00256   uint16_t                        RxXferCount;      /*!< SmartCard Rx Transfer Counter                         */
00257
00258   DMA_HandleTypeDef               *hdmatx;          /*!< SmartCard Tx DMA Handle parameters                    */
00259
00260   DMA_HandleTypeDef               *hdmarx;          /*!< SmartCard Rx DMA Handle parameters                    */
00261
00262   HAL_LockTypeDef                 Lock;             /*!< Locking object                                        */
00263
00264   __IO HAL_SMARTCARD_StateTypeDef    gState;        /*!< SmartCard state information related to global Handle management
00265                                                          and also related to Tx operations.
00266                                                          This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00267
00268   __IO HAL_SMARTCARD_StateTypeDef    RxState;       /*!< SmartCard state information related to Rx operations.
00269                                                          This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00270
00271   uint32_t                        ErrorCode;        /*!< SmartCard Error code                                  */
00272
00273 }SMARTCARD_HandleTypeDef;
00274
00275 /**
00276   * @brief  SMARTCARD clock sources
00277   */
00278 typedef enum
00279 {
00280   SMARTCARD_CLOCKSOURCE_PCLK1     = 0x00, /*!< PCLK1 clock source     */
00281   SMARTCARD_CLOCKSOURCE_PCLK2     = 0x01, /*!< PCLK2 clock source     */
00282   SMARTCARD_CLOCKSOURCE_HSI       = 0x02, /*!< HSI clock source       */
00283   SMARTCARD_CLOCKSOURCE_SYSCLK    = 0x04, /*!< SYSCLK clock source    */
00284   SMARTCARD_CLOCKSOURCE_LSE       = 0x08, /*!< LSE clock source       */
00285   SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10  /*!< undefined clock source */
00286 }SMARTCARD_ClockSourceTypeDef;
00287
00288 /**
00289   * @}
00290   */
00291
00292 /* Exported constants --------------------------------------------------------*/
00293 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
00294   * @{
00295   */
00296
00297 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
00298   * @{
00299   */
00300 #define SMARTCARD_WORDLENGTH_9B             ((uint32_t)USART_CR1_M0)              /*!< SMARTCARD frame length */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
00306   * @{
00307   */
00308 #define SMARTCARD_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)                      /*!< SMARTCARD frame with 0.5 stop bit  */
00309 #define SMARTCARD_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
00315   * @{
00316   */
00317 #define SMARTCARD_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)                  /*!< SMARTCARD frame even parity */
00318 #define SMARTCARD_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity  */
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
00324   * @{
00325   */
00326 #define SMARTCARD_MODE_RX                   ((uint32_t)USART_CR1_RE)                  /*!< SMARTCARD RX mode        */
00327 #define SMARTCARD_MODE_TX                   ((uint32_t)USART_CR1_TE)                  /*!< SMARTCARD TX mode        */
00328 #define SMARTCARD_MODE_TX_RX                ((uint32_t)(USART_CR1_TE |USART_CR1_RE))  /*!< SMARTCARD RX and TX mode */
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
00334   * @{
00335   */
00336 #define SMARTCARD_POLARITY_LOW              ((uint32_t)0x00000000)                   /*!< SMARTCARD frame low polarity  */
00337 #define SMARTCARD_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)               /*!< SMARTCARD frame high polarity */
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
00343   * @{
00344   */
00345 #define SMARTCARD_PHASE_1EDGE               ((uint32_t)0x00000000)                  /*!< SMARTCARD frame phase on first clock transition  */
00346 #define SMARTCARD_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)              /*!< SMARTCARD frame phase on second clock transition */
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
00352   * @{
00353   */
00354 #define SMARTCARD_LASTBIT_DISABLE           ((uint32_t)0x00000000)                 /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
00355 #define SMARTCARD_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)             /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
00361   * @{
00362   */
00363 #define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    ((uint32_t)0x00000000)                 /*!< SMARTCARD frame one-bit sample disabled */
00364 #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     ((uint32_t)USART_CR3_ONEBIT)           /*!< SMARTCARD frame one-bit sample enabled  */
00365 /**
00366   * @}
00367   */
00368
00369
00370 /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
00371   * @{
00372   */
00373 #define SMARTCARD_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)            /*!< SMARTCARD NACK transmission disabled */
00374 #define SMARTCARD_NACK_DISABLE              ((uint32_t)0x00000000)                /*!< SMARTCARD NACK transmission enabled  */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
00380   * @{
00381   */
00382 #define SMARTCARD_TIMEOUT_DISABLE           ((uint32_t)0x00000000)                /*!< SMARTCARD receiver timeout disabled */
00383 #define SMARTCARD_TIMEOUT_ENABLE            ((uint32_t)USART_CR2_RTOEN)           /*!< SMARTCARD receiver timeout enabled  */
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
00389   * @{
00390   */
00391 #define SMARTCARD_ADVFEATURE_TXINV_DISABLE  ((uint32_t)0x00000000)                /*!< TX pin active level inversion disable */
00392 #define SMARTCARD_ADVFEATURE_TXINV_ENABLE   ((uint32_t)USART_CR2_TXINV)           /*!< TX pin active level inversion enable  */
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
00398   * @{
00399   */
00400 #define SMARTCARD_ADVFEATURE_RXINV_DISABLE  ((uint32_t)0x00000000)                /*!< RX pin active level inversion disable */
00401 #define SMARTCARD_ADVFEATURE_RXINV_ENABLE   ((uint32_t)USART_CR2_RXINV)           /*!< RX pin active level inversion enable  */
00402 /**
00403   * @}
00404   */
00405
00406 /** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
00407   * @{
00408   */
00409 #define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  ((uint32_t)0x00000000)              /*!< Binary data inversion disable */
00410 #define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
00416   * @{
00417   */
00418 #define SMARTCARD_ADVFEATURE_SWAP_DISABLE   ((uint32_t)0x00000000)                /*!< TX/RX pins swap disable */
00419 #define SMARTCARD_ADVFEATURE_SWAP_ENABLE    ((uint32_t)USART_CR2_SWAP)            /*!< TX/RX pins swap enable  */
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
00425   * @{
00426   */
00427 #define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   ((uint32_t)0x00000000)              /*!< RX overrun enable  */
00428 #define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
00434   * @{
00435   */
00436 #define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   ((uint32_t)0x00000000)         /*!< DMA enable on Reception Error  */
00437 #define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  ((uint32_t)USART_CR3_DDRE)     /*!< DMA disable on Reception Error */
00438 /**
00439   * @}
00440   */
00441
00442 /** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
00443   * @{
00444   */
00445 #define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      ((uint32_t)0x00000000)           /*!< Most significant bit sent/received first disable */
00446 #define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       ((uint32_t)USART_CR2_MSBFIRST)   /*!< Most significant bit sent/received first enable  */
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
00452   * @{
00453   */
00454 #define SMARTCARD_RXDATA_FLUSH_REQUEST      ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive data flush request */
00455 #define SMARTCARD_TXDATA_FLUSH_REQUEST      ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush request */
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
00461   * @{
00462   */
00463 #define SMARTCARD_CR3_SCARCNT_LSB_POS       ((uint32_t) 17)   /*!< SMARTCARD auto retry counter LSB position in CR3 register */
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
00469   * @{
00470   */
00471 #define SMARTCARD_GTPR_GT_LSB_POS           ((uint32_t) 8)   /*!<  SMARTCARD guard time value LSB position in GTPR register */
00472 /**
00473   * @}
00474   */
00475
00476 /** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
00477   * @{
00478   */
00479 #define SMARTCARD_RTOR_BLEN_LSB_POS         ((uint32_t) 24)  /*!< SMARTCARD block length LSB position in RTOR register */
00480 /**
00481   * @}
00482   */
00483
00484 /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
00485   * @{
00486   */
00487 #define SMARTCARD_IT_MASK                   ((uint16_t)0x001F)   /*!< SMARTCARD interruptions flags mask */
00488 /**
00489   * @}
00490   */
00491
00492 /**
00493   * @}
00494   */
00495
00496 /* Exported macros -----------------------------------------------------------*/
00497 /** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
00498   * @{
00499   */
00500
00501 /** @brief  Reset SMARTCARD handle states.
00502   * @param  __HANDLE__: SMARTCARD handle.
00503   * @retval None
00504   */
00505 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00506                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
00507                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
00508                                                           } while(0)
00509
00510 /** @brief  Flush the Smartcard Data registers.
00511   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00512   * @retval None
00513   */
00514 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                                 \
00515     do{                                                                              \
00516       SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
00517       SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
00518       } while(0)
00519
00520 /** @brief  Clear the specified SMARTCARD pending flag.
00521   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00522   * @param  __FLAG__: specifies the flag to check.
00523   *          This parameter can be any combination of the following values:
00524   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00525   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00526   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00527   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00528   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
00529   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00530   @if STM32L443xx
00531   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
00532   @endif
00533   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00534   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00535   * @retval None
00536   */
00537 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00538
00539 /** @brief  Clear the SMARTCARD PE pending flag.
00540   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00541   * @retval None
00542   */
00543 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
00544
00545
00546 /** @brief  Clear the SMARTCARD FE pending flag.
00547   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00548   * @retval None
00549   */
00550 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
00551
00552 /** @brief  Clear the SMARTCARD NE pending flag.
00553   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00554   * @retval None
00555   */
00556 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
00557
00558 /** @brief  Clear the SMARTCARD ORE pending flag.
00559   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00560   * @retval None
00561   */
00562 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
00563
00564 /** @brief  Clear the SMARTCARD IDLE pending flag.
00565   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00566   * @retval None
00567   */
00568 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
00569
00570 /** @brief  Check whether the specified Smartcard flag is set or not.
00571   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00572   * @param  __FLAG__: specifies the flag to check.
00573   *        This parameter can be one of the following values:
00574   @if STM32L443xx
00575   *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
00576   @endif
00577   *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
00578   *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
00579   *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
00580   *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
00581   *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
00582   *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
00583   *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
00584   *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
00585   *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag
00586   *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
00587   *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
00588   *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
00589   *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
00590   * @retval The new state of __FLAG__ (TRUE or FALSE).
00591   */
00592 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00593
00594
00595 /** @brief  Enable the specified SmartCard interrupt.
00596   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00597   * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
00598   *          This parameter can be one of the following values:
00599   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00600   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00601   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00602   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00603   @if STM32L443xx
00604   *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
00605   @endif
00606   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00607   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00608   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00609   *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
00610   * @retval None
00611   */
00612 #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00613                                                                 ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00614                                                                 ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00615
00616 /** @brief  Disable the specified SmartCard interrupt.
00617   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00618   * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
00619   *          This parameter can be one of the following values:
00620   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00621   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00622   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00623   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00624   @if STM32L443xx
00625   *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
00626   @endif
00627   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00628   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00629   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00630   *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
00631   * @retval None
00632   */
00633 #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00634                                                                 ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00635                                                                 ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00636
00637
00638 /** @brief  Check whether the specified SmartCard interrupt has occurred or not.
00639   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00640   * @param  __IT__: specifies the SMARTCARD interrupt to check.
00641   *          This parameter can be one of the following values:
00642   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00643   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00644   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00645   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00646   @if STM32L443xx
00647   *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
00648   @endif
00649   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00650   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00651   *            @arg @ref SMARTCARD_IT_ORE   Overrun error interrupt
00652   *            @arg @ref SMARTCARD_IT_NE    Noise error interrupt
00653   *            @arg @ref SMARTCARD_IT_FE    Framing error interrupt
00654   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00655   * @retval The new state of __IT__ (TRUE or FALSE).
00656   */
00657 #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
00658
00659 /** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
00660   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00661   * @param  __IT__: specifies the SMARTCARD interrupt source to check.
00662   *          This parameter can be one of the following values:
00663   *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
00664   *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
00665   *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
00666   *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
00667   @if STM32L443xx
00668   *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
00669   @endif
00670   *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
00671   *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt
00672   *            @arg @ref SMARTCARD_IT_ERR   Framing, overrun or noise error interrupt
00673   *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
00674   * @retval The new state of __IT__ (TRUE or FALSE).
00675   */
00676 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
00677                                                            (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
00678                                                            (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
00679
00680
00681 /** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
00682   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00683   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00684   *                       to clear the corresponding interrupt.
00685   *          This parameter can be one of the following values:
00686   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00687   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00688   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00689   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00690   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag
00691   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00692   @if STM32L443xx
00693   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
00694   @endif
00695   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00696   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00697   * @retval None
00698   */
00699 #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
00700
00701 /** @brief  Set a specific SMARTCARD request flag.
00702   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00703   * @param  __REQ__: specifies the request flag to set
00704   *          This parameter can be one of the following values:
00705   *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
00706   *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
00707   *
00708   * @retval None
00709   */
00710 #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00711
00712 /** @brief  Enable the SMARTCARD one bit sample method.
00713   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00714   * @retval None
00715   */
00716 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00717
00718 /** @brief  Disable the SMARTCARD one bit sample method.
00719   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00720   * @retval None
00721   */
00722 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00723
00724 /** @brief  Enable the USART associated to the SMARTCARD Handle.
00725   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00726   * @retval None
00727   */
00728 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00729
00730 /** @brief  Disable the USART associated to the SMARTCARD Handle
00731   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00732   * @retval None
00733   */
00734 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00735
00736 /**
00737   * @}
00738   */
00739
00740 /* Private macros -------------------------------------------------------------*/
00741 /** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
00742   * @{
00743   */
00744
00745 /** @brief  Check the Baud rate range.
00746   * @note   The maximum Baud Rate is derived from the maximum clock on L4 (80 MHz)
00747   *         divided by the oversampling used on the SMARTCARD (i.e. 16).
00748   * @param  __BAUDRATE__: Baud rate set by the configuration function.
00749   * @retval Test result (TRUE or FALSE)
00750   */
00751 #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 5000001)
00752
00753 /** @brief  Check the block length range.
00754   * @note   The maximum SMARTCARD block length is 0xFF.
00755   * @param  __LENGTH__: block length.
00756   * @retval Test result (TRUE or FALSE)
00757   */
00758 #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
00759
00760 /** @brief  Check the receiver timeout value.
00761   * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
00762   * @param  __TIMEOUTVALUE__: receiver timeout value.
00763   * @retval Test result (TRUE or FALSE)
00764   */
00765 #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFF)
00766
00767 /** @brief  Check the SMARTCARD autoretry counter value.
00768   * @note   The maximum number of retransmissions is 0x7.
00769   * @param  __COUNT__: number of retransmissions.
00770   * @retval Test result (TRUE or FALSE)
00771   */
00772 #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7)
00773
00774 /**
00775   * @brief Ensure that SMARTCARD frame length is valid.
00776   * @param __LENGTH__: SMARTCARD frame length.
00777   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00778   */
00779 #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
00780
00781 /**
00782   * @brief Ensure that SMARTCARD frame number of stop bits is valid.
00783   * @param __STOPBITS__: SMARTCARD frame number of stop bits.
00784   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00785   */
00786 #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
00787                                              ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
00788
00789 /**
00790   * @brief Ensure that SMARTCARD frame parity is valid.
00791   * @param __PARITY__: SMARTCARD frame parity.
00792   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00793   */
00794 #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
00795                                          ((__PARITY__) == SMARTCARD_PARITY_ODD))
00796
00797 /**
00798   * @brief Ensure that SMARTCARD communication mode is valid.
00799   * @param __MODE__: SMARTCARD communication mode.
00800   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00801   */
00802 #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
00803
00804 /**
00805   * @brief Ensure that SMARTCARD frame polarity is valid.
00806   * @param __CPOL__: SMARTCARD frame polarity.
00807   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00808   */
00809 #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
00810
00811 /**
00812   * @brief Ensure that SMARTCARD frame phase is valid.
00813   * @param __CPHA__: SMARTCARD frame phase.
00814   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00815   */
00816 #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
00817
00818 /**
00819   * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
00820   * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting.
00821   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00822   */
00823 #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
00824                                            ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
00825
00826 /**
00827   * @brief Ensure that SMARTCARD frame sampling is valid.
00828   * @param __ONEBIT__: SMARTCARD frame sampling.
00829   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00830   */
00831 #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
00832                                                  ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
00833
00834 /**
00835   * @brief Ensure that SMARTCARD NACK transmission setting is valid.
00836   * @param __NACK__: SMARTCARD NACK transmission setting.
00837   * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
00838   */
00839 #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
00840                                      ((__NACK__) == SMARTCARD_NACK_DISABLE))
00841
00842 /**
00843   * @brief Ensure that SMARTCARD receiver timeout setting is valid.
00844   * @param __TIMEOUT__: SMARTCARD receiver timeout setting.
00845   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
00846   */
00847 #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
00848                                            ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
00849
00850 /**
00851   * @brief Ensure that SMARTCARD advanced features initialization is valid.
00852   * @param __INIT__: SMARTCARD advanced features initialization.
00853   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
00854   */
00855 #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
00856                                                                SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
00857                                                                SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
00858                                                                SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
00859                                                                SMARTCARD_ADVFEATURE_SWAP_INIT              | \
00860                                                                SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
00861                                                                SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
00862                                                                SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
00863
00864 /**
00865   * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
00866   * @param __TXINV__: SMARTCARD frame TX inversion setting.
00867   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
00868   */
00869 #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
00870                                                   ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
00871
00872 /**
00873   * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
00874   * @param __RXINV__: SMARTCARD frame RX inversion setting.
00875   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
00876   */
00877 #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
00878                                                   ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
00879
00880 /**
00881   * @brief Ensure that SMARTCARD frame data inversion setting is valid.
00882   * @param __DATAINV__: SMARTCARD frame data inversion setting.
00883   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
00884   */
00885 #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
00886                                                       ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
00887
00888 /**
00889   * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
00890   * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting.
00891   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
00892   */
00893 #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
00894                                                 ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
00895
00896 /**
00897   * @brief Ensure that SMARTCARD frame overrun setting is valid.
00898   * @param __OVERRUN__: SMARTCARD frame overrun setting.
00899   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
00900   */
00901 #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
00902                                            ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
00903
00904 /**
00905   * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
00906   * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting.
00907   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
00908   */
00909 #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
00910                                                        ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
00911
00912 /**
00913   * @brief Ensure that SMARTCARD frame MSB first setting is valid.
00914   * @param __MSBFIRST__: SMARTCARD frame MSB first setting.
00915   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
00916   */
00917 #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
00918                                                         ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
00919
00920 /**
00921   * @brief Ensure that SMARTCARD request parameter is valid.
00922   * @param __PARAM__: SMARTCARD request parameter.
00923   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00924   */
00925 #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
00926                                                    ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
00927
00928 /**
00929   * @}
00930   */
00931
00932 /* Include SMARTCARD HAL Extended module */
00933 #include "stm32l4xx_hal_smartcard_ex.h"
00934
00935
00936 /* Exported functions --------------------------------------------------------*/
00937 /** @addtogroup SMARTCARD_Exported_Functions
00938   * @{
00939   */
00940
00941 /* Initialization and de-initialization functions  ****************************/
00942 /** @addtogroup SMARTCARD_Exported_Functions_Group1
00943   * @{
00944   */
00945
00946 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
00947 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
00948 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
00949 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
00950
00951 /**
00952   * @}
00953   */
00954
00955 /* IO operation functions *****************************************************/
00956 /** @addtogroup SMARTCARD_Exported_Functions_Group2
00957   * @{
00958   */
00959
00960 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00961 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00962 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
00963 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
00964 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
00965 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
00966 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
00967 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00968 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00969 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00970
00971 /**
00972   * @}
00973   */
00974
00975 /* Peripheral Control functions ***********************************************/
00976 /* Peripheral State and Error functions ***************************************/
00977 /** @addtogroup SMARTCARD_Exported_Functions_Group4
00978   * @{
00979   */
00980
00981 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
00982 uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
00983
00984 /**
00985   * @}
00986   */
00987
00988 /**
00989   * @}
00990   */
00991
00992 /**
00993   * @}
00994   */
00995
00996 /**
00997   * @}
00998   */
00999
01000 #ifdef __cplusplus
01001 }
01002 #endif
01003
01004 #endif /* __STM32L4xx_HAL_SMARTCARD_H */
01005
01006 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smartcard_ex.c Source File

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stm32l4xx_hal_smartcard_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_smartcard_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SMARTCARD HAL module driver.
00008   *          This file provides extended firmware functions to manage the following
00009   *          functionalities of the SmartCard.
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   *
00014   @verbatim
00015   =============================================================================
00016                ##### SMARTCARD peripheral extended features  #####
00017   =============================================================================
00018   [..]
00019   The Extended SMARTCARD HAL driver can be used as follows:
00020
00021     (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
00022         then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
00023         auto-retry counter,...) in the hsmartcard AdvancedInit structure.
00024
00025
00026
00027   @endverbatim
00028   ******************************************************************************
00029   * @attention
00030   *
00031   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00032   *
00033   * Redistribution and use in source and binary forms, with or without modification,
00034   * are permitted provided that the following conditions are met:
00035   *   1. Redistributions of source code must retain the above copyright notice,
00036   *      this list of conditions and the following disclaimer.
00037   *   2. Redistributions in binary form must reproduce the above copyright notice,
00038   *      this list of conditions and the following disclaimer in the documentation
00039   *      and/or other materials provided with the distribution.
00040   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00041   *      may be used to endorse or promote products derived from this software
00042   *      without specific prior written permission.
00043   *
00044   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00045   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00046   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00047   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00048   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00049   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00050   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00051   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00052   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00053   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00054   *
00055   ******************************************************************************
00056   */
00057
00058 /* Includes ------------------------------------------------------------------*/
00059 #include "stm32l4xx_hal.h"
00060
00061 /** @addtogroup STM32L4xx_HAL_Driver
00062   * @{
00063   */
00064
00065 /** @defgroup SMARTCARDEx SMARTCARDEx
00066   * @brief SMARTCARD Extended HAL module driver
00067   * @{
00068   */
00069 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00070
00071 /* Private typedef -----------------------------------------------------------*/
00072 /* Private define ------------------------------------------------------------*/
00073 /* Private macros ------------------------------------------------------------*/
00074 /* Private variables ---------------------------------------------------------*/
00075 /* Private function prototypes -----------------------------------------------*/
00076
00077 /* Exported functions --------------------------------------------------------*/
00078 /** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
00079   * @{
00080   */
00081
00082 /** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
00083   * @brief    Extended control functions
00084   *
00085 @verbatim
00086   ===============================================================================
00087                       ##### Peripheral Control functions #####
00088   ===============================================================================
00089   [..]
00090   This subsection provides a set of functions allowing to initialize the SMARTCARD.
00091      (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
00092      (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
00093      (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
00094      (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
00095
00096 @endverbatim
00097   * @{
00098   */
00099
00100 /**
00101   * @brief Update on the fly the SMARTCARD block length in RTOR register.
00102   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00103   *                    the configuration information for the specified SMARTCARD module.
00104   * @param BlockLength: SMARTCARD block length (8-bit long at most)
00105   * @retval None
00106   */
00107 void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
00108 {
00109   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
00110 }
00111
00112 /**
00113   * @brief Update on the fly the receiver timeout value in RTOR register.
00114   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00115   *                    the configuration information for the specified SMARTCARD module.
00116   * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
00117   *                     value must be less or equal to 0x0FFFFFFFF.
00118   * @retval None
00119   */
00120 void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
00121 {
00122   assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
00123   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
00124 }
00125
00126 /**
00127   * @brief Enable the SMARTCARD receiver timeout feature.
00128   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00129   *                    the configuration information for the specified SMARTCARD module.
00130   * @retval HAL status
00131   */
00132 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00133 {
00134
00135   if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00136   {
00137     /* Process Locked */
00138     __HAL_LOCK(hsmartcard);
00139
00140     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00141
00142     /* Set the USART RTOEN bit */
00143     SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00144
00145     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00146
00147     /* Process Unlocked */
00148     __HAL_UNLOCK(hsmartcard);
00149
00150     return HAL_OK;
00151   }
00152   else
00153   {
00154     return HAL_BUSY;
00155   }
00156 }
00157
00158 /**
00159   * @brief Disable the SMARTCARD receiver timeout feature.
00160   * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
00161   *                    the configuration information for the specified SMARTCARD module.
00162   * @retval HAL status
00163   */
00164 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00165 {
00166
00167   if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00168   {
00169     /* Process Locked */
00170     __HAL_LOCK(hsmartcard);
00171
00172     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00173
00174     /* Clear the USART RTOEN bit */
00175     CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00176
00177     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00178
00179     /* Process Unlocked */
00180     __HAL_UNLOCK(hsmartcard);
00181
00182     return HAL_OK;
00183   }
00184   else
00185   {
00186     return HAL_BUSY;
00187   }
00188 }
00189
00190 /**
00191   * @}
00192   */
00193
00194 /**
00195   * @}
00196   */
00197
00198 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00199
00200 /**
00201   * @}
00202   */
00203
00204 /**
00205   * @}
00206   */
00207
00208 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smartcard_ex.h Source File

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stm32l4xx_hal_smartcard_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_smartcard_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SMARTCARD HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_SMARTCARD_EX_H
00040 #define __STM32L4xx_HAL_SMARTCARD_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SMARTCARDEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059
00060 /** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
00065   * @{
00066   */
00067 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00068 #define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
00069 #endif /* defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) */
00070 #define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
00076   * @{
00077   */
00078 #define SMARTCARD_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000)    /*!< No advanced feature initialization                  */
00079 #define SMARTCARD_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001)    /*!< TX pin active level inversion                       */
00080 #define SMARTCARD_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002)    /*!< RX pin active level inversion                       */
00081 #define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004)    /*!< Binary data inversion                               */
00082 #define SMARTCARD_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008)    /*!< TX/RX pins swap                                     */
00083 #define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010)    /*!< RX overrun disable                                  */
00084 #define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020)    /*!< DMA disable on Reception Error                      */
00085 #define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080)    /*!< Most significant bit sent/received first            */
00086 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00087 #define SMARTCARD_ADVFEATURE_TXCOMPLETION            ((uint32_t)0x00000100)    /*!< TX completion indication before of after guard time */
00088 #endif /* defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) */
00089 /**
00090   * @}
00091   */
00092
00093
00094
00095
00096 /** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
00097   *        Elements values convention: 0xXXXX
00098   *           - 0xXXXX  : Flag mask in the ISR register
00099   * @{
00100   */
00101 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00102 #define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT      /*!< SMARTCARD transmission complete before guard time completion */
00103 #endif /* defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) */
00104 #define SMARTCARD_FLAG_REACK          USART_ISR_REACK      /*!< SMARTCARD receive enable acknowledge flag  */
00105 #define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK      /*!< SMARTCARD transmit enable acknowledge flag */
00106 #define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY       /*!< SMARTCARD busy flag                        */
00107 #define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF       /*!< SMARTCARD end of block flag                */
00108 #define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF       /*!< SMARTCARD receiver timeout flag            */
00109 #define SMARTCARD_FLAG_TXE            USART_ISR_TXE        /*!< SMARTCARD transmit data register empty     */
00110 #define SMARTCARD_FLAG_TC             USART_ISR_TC         /*!< SMARTCARD transmission complete            */
00111 #define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE       /*!< SMARTCARD read data register not empty     */
00112 #define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE       /*!< SMARTCARD idle line detection              */
00113 #define SMARTCARD_FLAG_ORE            USART_ISR_ORE        /*!< SMARTCARD overrun error                    */
00114 #define SMARTCARD_FLAG_NE             USART_ISR_NE         /*!< SMARTCARD noise error                      */
00115 #define SMARTCARD_FLAG_FE             USART_ISR_FE         /*!< SMARTCARD frame error                      */
00116 #define SMARTCARD_FLAG_PE             USART_ISR_PE         /*!< SMARTCARD parity error                     */
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
00122   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00123   *           - YYYYY  : Interrupt source position in the XX register (5 bits)
00124   *           - XX  : Interrupt source register (2 bits)
00125   *                 - 01: CR1 register
00126   *                 - 10: CR2 register
00127   *                 - 11: CR3 register
00128   *           - ZZZZZ  : Flag position in the ISR register(5 bits)
00129   * @{
00130   */
00131 #define SMARTCARD_IT_PE                     ((uint16_t)0x0028)        /*!< SMARTCARD parity error interruption                 */
00132 #define SMARTCARD_IT_TXE                    ((uint16_t)0x0727)        /*!< SMARTCARD transmit data register empty interruption */
00133 #define SMARTCARD_IT_TC                     ((uint16_t)0x0626)        /*!< SMARTCARD transmission complete interruption        */
00134 #define SMARTCARD_IT_RXNE                   ((uint16_t)0x0525)        /*!< SMARTCARD read data register not empty interruption */
00135 #define SMARTCARD_IT_IDLE                   ((uint16_t)0x0424)        /*!< SMARTCARD idle line detection interruption          */
00136
00137 #define SMARTCARD_IT_ERR                    ((uint16_t)0x0060)        /*!< SMARTCARD error interruption         */
00138 #define SMARTCARD_IT_ORE                    ((uint16_t)0x0300)        /*!< SMARTCARD overrun error interruption */
00139 #define SMARTCARD_IT_NE                     ((uint16_t)0x0200)        /*!< SMARTCARD noise error interruption   */
00140 #define SMARTCARD_IT_FE                     ((uint16_t)0x0100)        /*!< SMARTCARD frame error interruption   */
00141
00142 #define SMARTCARD_IT_EOB                    ((uint16_t)0x0C3B)        /*!< SMARTCARD end of block interruption     */
00143 #define SMARTCARD_IT_RTO                    ((uint16_t)0x0B3A)        /*!< SMARTCARD receiver timeout interruption */
00144
00145 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00146 #define SMARTCARD_IT_TCBGT                  ((uint16_t)0x1978)        /*!< SMARTCARD transmission complete before guard time completion interruption */
00147 #endif /* defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
00153   * @{
00154   */
00155 #define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
00156 #define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
00157 #define SMARTCARD_CLEAR_NEF                 USART_ICR_NCF     /*!< SMARTCARD noise detected clear flag        */
00158 #define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
00159 #define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
00160 #define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
00161 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00162 #define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
00163 #endif /* defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) */
00164 #define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
00165 #define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
00166 /**
00167   * @}
00168   */
00169
00170 /**
00171   * @}
00172   */
00173 /* Exported macros -----------------------------------------------------------*/
00174 /* Private macros ------------------------------------------------------------*/
00175 /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
00176   * @{
00177   */
00178
00179 /** @brief  Report the SMARTCARD clock source.
00180   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00181   * @param  __CLOCKSOURCE__: output variable.
00182   * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
00183   */
00184 #if defined (STM32L432xx) || defined (STM32L442xx)
00185 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00186   do {                                                         \
00187     if((__HANDLE__)->Instance == USART1)                       \
00188     {                                                          \
00189        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00190        {                                                       \
00191         case RCC_USART1CLKSOURCE_PCLK2:                        \
00192           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
00193           break;                                               \
00194         case RCC_USART1CLKSOURCE_HSI:                          \
00195           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00196           break;                                               \
00197         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00198           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00199           break;                                               \
00200         case RCC_USART1CLKSOURCE_LSE:                          \
00201           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00202           break;                                               \
00203         default:                                               \
00204           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00205           break;                                               \
00206        }                                                       \
00207     }                                                          \
00208     else if((__HANDLE__)->Instance == USART2)                  \
00209     {                                                          \
00210        switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00211        {                                                       \
00212         case RCC_USART2CLKSOURCE_PCLK1:                        \
00213           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00214           break;                                               \
00215         case RCC_USART2CLKSOURCE_HSI:                          \
00216           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00217           break;                                               \
00218         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00219           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00220           break;                                               \
00221         case RCC_USART2CLKSOURCE_LSE:                          \
00222           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00223           break;                                               \
00224         default:                                               \
00225           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00226           break;                                               \
00227        }                                                       \
00228     }                                                          \
00229   } while(0)
00230 #else
00231 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00232   do {                                                         \
00233     if((__HANDLE__)->Instance == USART1)                       \
00234     {                                                          \
00235        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00236        {                                                       \
00237         case RCC_USART1CLKSOURCE_PCLK2:                        \
00238           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
00239           break;                                               \
00240         case RCC_USART1CLKSOURCE_HSI:                          \
00241           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00242           break;                                               \
00243         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00244           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00245           break;                                               \
00246         case RCC_USART1CLKSOURCE_LSE:                          \
00247           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00248           break;                                               \
00249         default:                                               \
00250           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00251           break;                                               \
00252        }                                                       \
00253     }                                                          \
00254     else if((__HANDLE__)->Instance == USART2)                  \
00255     {                                                          \
00256        switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00257        {                                                       \
00258         case RCC_USART2CLKSOURCE_PCLK1:                        \
00259           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00260           break;                                               \
00261         case RCC_USART2CLKSOURCE_HSI:                          \
00262           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00263           break;                                               \
00264         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00265           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00266           break;                                               \
00267         case RCC_USART2CLKSOURCE_LSE:                          \
00268           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00269           break;                                               \
00270         default:                                               \
00271           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00272           break;                                               \
00273        }                                                       \
00274     }                                                          \
00275     else if((__HANDLE__)->Instance == USART3)                  \
00276     {                                                          \
00277        switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00278        {                                                       \
00279         case RCC_USART3CLKSOURCE_PCLK1:                        \
00280           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
00281           break;                                               \
00282         case RCC_USART3CLKSOURCE_HSI:                          \
00283           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00284           break;                                               \
00285         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00286           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00287           break;                                               \
00288         case RCC_USART3CLKSOURCE_LSE:                          \
00289           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00290           break;                                               \
00291         default:                                               \
00292           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00293           break;                                               \
00294        }                                                       \
00295     }                                                          \
00296   } while(0)
00297 #endif /* STM32L432xx || STM32L442xx */
00298
00299 /** @brief  Set the Transmission Completion flag
00300   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00301   * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
00302   *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
00303   *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
00304   * @retval None
00305   */
00306 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00307 #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)     \
00308   do {                                                            \
00309     (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
00310   } while(0)
00311 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00312 #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                          \
00313   do {                                                                                                 \
00314     if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))  \
00315     {                                                                                                  \
00316      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                       \
00317     }                                                                                                  \
00318     else                                                                                               \
00319     {                                                                                                  \
00320       assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
00321     }                                                                                                  \
00322   } while(0)
00323 #endif
00324
00325 /** @brief  Return the transmission completion flag.
00326   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00327   * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
00328   *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
00329   *        reported.
00330   * @retval Transmission completion flag
00331   */
00332 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00333 #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)    (SMARTCARD_FLAG_TC)
00334 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00335 #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)                                                         \
00336   (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
00337 #endif
00338
00339
00340 /**
00341   * @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
00342   * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag.
00343   * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
00344   */
00345 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00346 #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
00347 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00348 #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
00349                                                               ((__TXCOMPLETE__) == SMARTCARD_TC))
00350 #endif
00351
00352 /**
00353   * @}
00354   */
00355
00356 /* Exported functions --------------------------------------------------------*/
00357 /** @addtogroup SMARTCARDEx_Exported_Functions
00358   * @{
00359   */
00360
00361 /* Initialization and de-initialization functions  ****************************/
00362 /* IO operation methods *******************************************************/
00363
00364 /** @addtogroup SMARTCARDEx_Exported_Functions_Group1
00365   * @{
00366   */
00367
00368 /* Peripheral Control functions ***********************************************/
00369 void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
00370 void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
00371 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00372 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00373
00374 /**
00375   * @}
00376   */
00377
00378 /**
00379   * @}
00380   */
00381
00382
00383 /* Private functions ---------------------------------------------------------*/
00384
00385 /**
00386   * @}
00387   */
00388
00389 /**
00390   * @}
00391   */
00392
00393 #ifdef __cplusplus
00394 }
00395 #endif
00396
00397 #endif /* __STM32L4xx_HAL_SMARTCARD_EX_H */
00398
00399 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smbus.c Source File

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stm32l4xx_hal_smbus.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_smbus.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SMBUS HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the System Management Bus (SMBus) peripheral,
00010   *          based on I2C principles of operation :
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020     The SMBUS HAL driver can be used as follows:
00021
00022     (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
00023         SMBUS_HandleTypeDef  hsmbus;
00024
00025     (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
00026         (++) Enable the SMBUSx interface clock with __HAL_RCC_I2Cx_CLK_ENABLE()
00027         (++) SMBUS pins configuration
00028             (+++) Enable the clock for the SMBUS GPIOs
00029             (+++) Configure SMBUS pins as alternate function open-drain
00030         (++) NVIC configuration if you need to use interrupt process
00031             (+++) Configure the SMBUSx interrupt priority
00032             (+++) Enable the NVIC SMBUS IRQ Channel
00033
00034     (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing Mode,
00035         Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
00036         Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
00037
00038     (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
00039         (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00040              by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
00041
00042     (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
00043
00044     (#) For SMBUS IO operations, only one mode of operations is available within this driver :
00045
00046     *** Interrupt mode IO operation ***
00047     ===================================
00048     [..]
00049       (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
00050       (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
00051            add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
00052       (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
00053       (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
00054            add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
00055       (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
00056       (++) The associated previous transfer callback is called at the end of abort process
00057       (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
00058       (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
00059       (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
00060            using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
00061       (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
00062            add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
00063       (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
00064            add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
00065       (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
00066       (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
00067            add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
00068       (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
00069       (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
00070            add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
00071       (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
00072       (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
00073            add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
00074            to check the Alert Error Code using function HAL_SMBUS_GetError()
00075       (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
00076       (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
00077            add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
00078            to check the Error Code using function HAL_SMBUS_GetError()
00079
00080      *** SMBUS HAL driver macros list ***
00081      ==================================
00082      [..]
00083        Below the list of most used macros in SMBUS HAL driver.
00084
00085       (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
00086       (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
00087       (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
00088       (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag
00089       (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt
00090       (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt
00091
00092      [..]
00093        (@) You can refer to the SMBUS HAL driver header file for more useful macros
00094
00095
00096   @endverbatim
00097   ******************************************************************************
00098   * @attention
00099   *
00100   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00101   *
00102   * Redistribution and use in source and binary forms, with or without modification,
00103   * are permitted provided that the following conditions are met:
00104   *   1. Redistributions of source code must retain the above copyright notice,
00105   *      this list of conditions and the following disclaimer.
00106   *   2. Redistributions in binary form must reproduce the above copyright notice,
00107   *      this list of conditions and the following disclaimer in the documentation
00108   *      and/or other materials provided with the distribution.
00109   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00110   *      may be used to endorse or promote products derived from this software
00111   *      without specific prior written permission.
00112   *
00113   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00114   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00115   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00116   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00117   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00118   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00119   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00120   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00121   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00122   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00123   *
00124   ******************************************************************************
00125   */
00126
00127 /* Includes ------------------------------------------------------------------*/
00128 #include "stm32l4xx_hal.h"
00129
00130 /** @addtogroup STM32L4xx_HAL_Driver
00131   * @{
00132   */
00133
00134 /** @defgroup SMBUS SMBUS
00135   * @brief SMBUS HAL module driver
00136   * @{
00137   */
00138
00139 #ifdef HAL_SMBUS_MODULE_ENABLED
00140
00141 /* Private typedef -----------------------------------------------------------*/
00142 /* Private constants ---------------------------------------------------------*/
00143 /** @defgroup SMBUS_Private_Define SMBUS Private Constants
00144  * @{
00145  */
00146 #define TIMING_CLEAR_MASK   ((uint32_t)0xF0FFFFFF)      /*<! SMBUS TIMING clear register Mask */
00147 #define HAL_TIMEOUT_ADDR    ((uint32_t)10000)           /* 10 s  */
00148 #define HAL_TIMEOUT_BUSY    ((uint32_t)25)              /* 25 ms */
00149 #define HAL_TIMEOUT_DIR     ((uint32_t)25)              /* 25 ms */
00150 #define HAL_TIMEOUT_RXNE    ((uint32_t)25)              /* 25 ms */
00151 #define HAL_TIMEOUT_STOPF   ((uint32_t)25)              /* 25 ms */
00152 #define HAL_TIMEOUT_TC      ((uint32_t)25)              /* 25 ms */
00153 #define HAL_TIMEOUT_TCR     ((uint32_t)25)              /* 25 ms */
00154 #define HAL_TIMEOUT_TXIS    ((uint32_t)25)              /* 25 ms */
00155 #define MAX_NBYTE_SIZE      255
00156 /**
00157   * @}
00158   */
00159
00160 /* Private macro -------------------------------------------------------------*/
00161 /* Private variables ---------------------------------------------------------*/
00162 /* Private function prototypes -----------------------------------------------*/
00163 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
00164   * @{
00165   */
00166 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00167
00168 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
00169 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
00170 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
00171 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
00172
00173 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00174 /**
00175   * @}
00176   */
00177
00178 /* Exported functions --------------------------------------------------------*/
00179
00180 /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
00181   * @{
00182   */
00183
00184 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00185  *  @brief    Initialization and Configuration functions
00186  *
00187 @verbatim
00188  ===============================================================================
00189               ##### Initialization and de-initialization functions #####
00190  ===============================================================================
00191     [..]  This subsection provides a set of functions allowing to initialize and
00192           de-initialize the SMBUSx peripheral:
00193
00194       (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
00195           all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
00196
00197       (+) Call the function HAL_SMBUS_Init() to configure the selected device with
00198           the selected configuration:
00199         (++) Clock Timing
00200         (++) Bus Timeout
00201         (++) Analog Filer mode
00202         (++) Own Address 1
00203         (++) Addressing mode (Master, Slave)
00204         (++) Dual Addressing mode
00205         (++) Own Address 2
00206         (++) Own Address 2 Mask
00207         (++) General call mode
00208         (++) Nostretch mode
00209         (++) Packet Error Check mode
00210         (++) Peripheral mode
00211
00212
00213       (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
00214           of the selected SMBUSx peripheral.
00215
00216 @endverbatim
00217   * @{
00218   */
00219
00220 /**
00221   * @brief  Initialize the SMBUS according to the specified parameters
00222   *         in the SMBUS_InitTypeDef and initialize the associated handle.
00223   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00224   *                the configuration information for the specified SMBUS.
00225   * @retval HAL status
00226   */
00227 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
00228 {
00229   /* Check the SMBUS handle allocation */
00230   if(hsmbus == NULL)
00231   {
00232     return HAL_ERROR;
00233   }
00234
00235   /* Check the parameters */
00236   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00237   assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
00238   assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
00239   assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
00240   assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
00241   assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
00242   assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
00243   assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
00244   assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
00245   assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
00246   assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
00247
00248   if(hsmbus->State == HAL_SMBUS_STATE_RESET)
00249   {
00250     /* Allocate lock resource and initialize it */
00251     hsmbus->Lock = HAL_UNLOCKED;
00252
00253     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00254     HAL_SMBUS_MspInit(hsmbus);
00255   }
00256
00257   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00258
00259   /* Disable the selected SMBUS peripheral */
00260   __HAL_SMBUS_DISABLE(hsmbus);
00261
00262   /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
00263   /* Configure SMBUSx: Frequency range */
00264   hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
00265
00266   /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
00267   /* Configure SMBUSx: Bus Timeout  */
00268   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
00269   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
00270   hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
00271
00272   /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
00273   /* Configure SMBUSx: Own Address1 and ack own address1 mode */
00274   hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00275
00276   if(hsmbus->Init.OwnAddress1 != 0)
00277   {
00278     if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
00279   {
00280     hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
00281   }
00282     else /* SMBUS_ADDRESSINGMODE_10BIT */
00283   {
00284     hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
00285   }
00286   }
00287
00288   /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
00289   /* Configure SMBUSx: Addressing Master mode */
00290   if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
00291   {
00292     hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
00293   }
00294   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
00295   /* AUTOEND and NACK bit will be manage during Transfer process */
00296   hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00297
00298   /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
00299   /* Configure SMBUSx: Dual mode and Own Address2 */
00300   hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8));
00301
00302   /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
00303   /* Configure SMBUSx: Generalcall and NoStretch mode */
00304   hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
00305
00306   /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
00307   if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
00308      && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
00309   {
00310     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00311   }
00312
00313   /* Enable the selected SMBUS peripheral */
00314   __HAL_SMBUS_ENABLE(hsmbus);
00315
00316   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00317   hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
00318   hsmbus->State = HAL_SMBUS_STATE_READY;
00319
00320   return HAL_OK;
00321 }
00322
00323 /**
00324   * @brief  DeInitialize the SMBUS peripheral.
00325   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00326   *                the configuration information for the specified SMBUS.
00327   * @retval HAL status
00328   */
00329 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
00330 {
00331   /* Check the SMBUS handle allocation */
00332   if(hsmbus == NULL)
00333   {
00334     return HAL_ERROR;
00335   }
00336
00337   /* Check the parameters */
00338   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00339
00340   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00341
00342   /* Disable the SMBUS Peripheral Clock */
00343   __HAL_SMBUS_DISABLE(hsmbus);
00344
00345   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00346   HAL_SMBUS_MspDeInit(hsmbus);
00347
00348   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00349   hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
00350   hsmbus->State = HAL_SMBUS_STATE_RESET;
00351
00352    /* Release Lock */
00353   __HAL_UNLOCK(hsmbus);
00354
00355   return HAL_OK;
00356 }
00357
00358 /**
00359   * @brief Initialize the SMBUS MSP.
00360   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00361   *                the configuration information for the specified SMBUS.
00362   * @retval None
00363   */
00364 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
00365 {
00366   /* Prevent unused argument(s) compilation warning */
00367   UNUSED(hsmbus);
00368
00369   /* NOTE : This function should not be modified, when the callback is needed,
00370             the HAL_SMBUS_MspInit could be implemented in the user file
00371    */
00372 }
00373
00374 /**
00375   * @brief DeInitialize the SMBUS MSP.
00376   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00377   *                the configuration information for the specified SMBUS.
00378   * @retval None
00379   */
00380 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
00381 {
00382   /* Prevent unused argument(s) compilation warning */
00383   UNUSED(hsmbus);
00384
00385   /* NOTE : This function should not be modified, when the callback is needed,
00386             the HAL_SMBUS_MspDeInit could be implemented in the user file
00387    */
00388 }
00389
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00395  *  @brief   Data transfers functions
00396  *
00397 @verbatim
00398  ===============================================================================
00399                       ##### IO operation functions #####
00400  ===============================================================================
00401     [..]
00402     This subsection provides a set of functions allowing to manage the SMBUS data
00403     transfers.
00404
00405     (#) Blocking mode function to check if device is ready for usage is :
00406         (++) HAL_SMBUS_IsDeviceReady()
00407
00408     (#) There is only one mode of transfer:
00409        (++) No-Blocking mode : The communication is performed using Interrupts.
00410             These functions return the status of the transfer startup.
00411             The end of the data processing will be indicated through the
00412             dedicated SMBUS IRQ when using Interrupt mode.
00413
00414     (#) No-Blocking mode functions with Interrupt are :
00415         (++) HAL_SMBUS_Master_Transmit_IT()
00416         (++) HAL_SMBUS_Master_Receive_IT()
00417         (++) HAL_SMBUS_Slave_Transmit_IT()
00418         (++) HAL_SMBUS_Slave_Receive_IT()
00419         (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
00420         (++) HAL_SMBUS_DisableListen_IT()
00421         (++) HAL_SMBUS_EnableAlert_IT()
00422         (++) HAL_SMBUS_DisableAlert_IT()
00423
00424     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00425         (++) HAL_SMBUS_MasterTxCpltCallback()
00426         (++) HAL_SMBUS_MasterRxCpltCallback()
00427         (++) HAL_SMBUS_SlaveTxCpltCallback()
00428         (++) HAL_SMBUS_SlaveRxCpltCallback()
00429         (++) HAL_SMBUS_AddrCallback()
00430         (++) HAL_SMBUS_ListenCpltCallback()
00431         (++) HAL_SMBUS_ErrorCallback()
00432
00433 @endverbatim
00434   * @{
00435   */
00436
00437 /**
00438   * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
00439   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00440   *                the configuration information for the specified SMBUS.
00441   * @param  DevAddress: Target device address
00442   * @param  pData: Pointer to data buffer
00443   * @param  Size: Amount of data to be sent
00444   * @param  XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
00445   * @retval HAL status
00446   */
00447 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00448 {
00449   /* Check the parameters */
00450   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00451
00452   if(hsmbus->State == HAL_SMBUS_STATE_READY)
00453   {
00454     /* Process Locked */
00455     __HAL_LOCK(hsmbus);
00456
00457     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
00458     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00459     /* Prepare transfer parameters */
00460     hsmbus->pBuffPtr = pData;
00461     hsmbus->XferCount = Size;
00462     hsmbus->XferOptions = XferOptions;
00463
00464     /* In case of Quick command, remove autoend mode */
00465     /* Manage the stop generation by software */
00466     if(hsmbus->pBuffPtr == NULL)
00467     {
00468       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
00469     }
00470
00471     if(Size > MAX_NBYTE_SIZE)
00472     {
00473       hsmbus->XferSize = MAX_NBYTE_SIZE;
00474     }
00475     else
00476     {
00477       hsmbus->XferSize = Size;
00478     }
00479
00480     /* Send Slave Address */
00481     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00482     if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
00483     {
00484       SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
00485     }
00486     else
00487     {
00488       /* If transfer direction not change, do not generate Restart Condition */
00489       /* Mean Previous state is same as current state */
00490       if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
00491       {
00492         SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00493       }
00494       /* Else transfer direction change, so generate Restart with new transfer direction */
00495       else
00496       {
00497         SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
00498       }
00499
00500       /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
00501       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
00502       if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
00503       {
00504         hsmbus->XferSize--;
00505         hsmbus->XferCount--;
00506       }
00507     }
00508
00509     /* Process Unlocked */
00510     __HAL_UNLOCK(hsmbus);
00511
00512     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00513               to avoid the risk of SMBUS interrupt handle execution before current
00514               process unlock */
00515     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
00516
00517     return HAL_OK;
00518   }
00519   else
00520   {
00521     return HAL_BUSY;
00522   }
00523 }
00524
00525 /**
00526   * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
00527   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00528   *                the configuration information for the specified SMBUS.
00529   * @param  DevAddress: Target device address
00530   * @param  pData: Pointer to data buffer
00531   * @param  Size: Amount of data to be sent
00532   * @param  XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
00533   * @retval HAL status
00534   */
00535 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00536 {
00537   /* Check the parameters */
00538   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00539
00540   if(hsmbus->State == HAL_SMBUS_STATE_READY)
00541   {
00542     /* Process Locked */
00543     __HAL_LOCK(hsmbus);
00544
00545     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
00546     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00547
00548     /* Prepare transfer parameters */
00549     hsmbus->pBuffPtr = pData;
00550     hsmbus->XferCount = Size;
00551     hsmbus->XferOptions = XferOptions;
00552
00553     /* In case of Quick command, remove autoend mode */
00554     /* Manage the stop generation by software */
00555     if(hsmbus->pBuffPtr == NULL)
00556     {
00557       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
00558     }
00559
00560     if(Size > MAX_NBYTE_SIZE)
00561     {
00562       hsmbus->XferSize = MAX_NBYTE_SIZE;
00563     }
00564     else
00565     {
00566       hsmbus->XferSize = Size;
00567     }
00568
00569     /* Send Slave Address */
00570     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00571     if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
00572     {
00573       SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
00574     }
00575     else
00576     {
00577       /* If transfer direction not change, do not generate Restart Condition */
00578       /* Mean Previous state is same as current state */
00579       if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
00580       {
00581         SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00582       }
00583       /* Else transfer direction change, so generate Restart with new transfer direction */
00584       else
00585       {
00586         SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
00587       }
00588     }
00589
00590     /* Process Unlocked */
00591     __HAL_UNLOCK(hsmbus);
00592
00593     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00594               to avoid the risk of SMBUS interrupt handle execution before current
00595               process unlock */
00596     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
00597
00598     return HAL_OK;
00599   }
00600   else
00601   {
00602     return HAL_BUSY;
00603   }
00604 }
00605
00606 /**
00607   * @brief  Abort a master/host SMBUS process communication with Interrupt.
00608   * @note   This abort can be called only if state is ready
00609   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00610   *                the configuration information for the specified SMBUS.
00611   * @param  DevAddress: Target device address
00612   * @retval HAL status
00613   */
00614 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
00615 {
00616   if(hsmbus->State == HAL_SMBUS_STATE_READY)
00617   {
00618     /* Process Locked */
00619     __HAL_LOCK(hsmbus);
00620
00621     /* Keep the same state as previous */
00622     /* to perform as well the call of the corresponding end of transfer callback */
00623     if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
00624     {
00625       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
00626     }
00627     else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
00628     {
00629       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
00630     }
00631     else
00632     {
00633       /* Wrong usage of abort function */
00634       /* This function should be used only in case of abort monitored by master device */
00635       return HAL_ERROR;
00636     }
00637     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00638
00639     /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
00640     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
00641     SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
00642
00643     /* Process Unlocked */
00644     __HAL_UNLOCK(hsmbus);
00645
00646     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00647               to avoid the risk of SMBUS interrupt handle execution before current
00648               process unlock */
00649     if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
00650     {
00651       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
00652     }
00653     else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
00654     {
00655       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
00656     }
00657
00658     return HAL_OK;
00659   }
00660   else
00661   {
00662     return HAL_BUSY;
00663   }
00664 }
00665
00666 /**
00667   * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
00668   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00669   *                the configuration information for the specified SMBUS.
00670   * @param  pData: Pointer to data buffer
00671   * @param  Size: Amount of data to be sent
00672   * @param  XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
00673   * @retval HAL status
00674   */
00675 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00676 {
00677   /* Check the parameters */
00678   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00679
00680   if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
00681   {
00682     if((pData == NULL) || (Size == 0))
00683     {
00684       return  HAL_ERROR;
00685     }
00686
00687     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
00688     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
00689
00690     /* Process Locked */
00691     __HAL_LOCK(hsmbus);
00692
00693     hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
00694     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00695
00696     /* Set SBC bit to manage Acknowledge at each bit */
00697     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00698
00699     /* Enable Address Acknowledge */
00700     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
00701
00702     /* Prepare transfer parameters */
00703     hsmbus->pBuffPtr = pData;
00704     hsmbus->XferSize = Size;
00705     hsmbus->XferCount = Size;
00706     hsmbus->XferOptions = XferOptions;
00707
00708     if(Size > MAX_NBYTE_SIZE)
00709     {
00710       hsmbus->XferSize = MAX_NBYTE_SIZE;
00711     }
00712     else
00713     {
00714       hsmbus->XferSize = Size;
00715     }
00716
00717     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00718     if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
00719     {
00720       SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
00721     }
00722     else
00723     {
00724       /* Set NBYTE to transmit */
00725       SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00726
00727       /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
00728       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
00729       if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
00730       {
00731         hsmbus->XferSize--;
00732         hsmbus->XferCount--;
00733       }
00734     }
00735
00736     /* Clear ADDR flag after prepare the transfer parameters */
00737     /* This action will generate an acknowledge to the HOST */
00738     __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
00739
00740     /* Process Unlocked */
00741     __HAL_UNLOCK(hsmbus);
00742
00743     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00744               to avoid the risk of SMBUS interrupt handle execution before current
00745               process unlock */
00746     /* REnable ADDR interrupt */
00747     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
00748
00749     return HAL_OK;
00750   }
00751   else
00752   {
00753     return HAL_ERROR;
00754   }
00755 }
00756
00757 /**
00758   * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
00759   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00760   *                the configuration information for the specified SMBUS.
00761   * @param  pData: Pointer to data buffer
00762   * @param  Size: Amount of data to be sent
00763   * @param  XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
00764   * @retval HAL status
00765   */
00766 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00767 {
00768   /* Check the parameters */
00769   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00770
00771   if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
00772   {
00773     if((pData == NULL) || (Size == 0))
00774     {
00775       return  HAL_ERROR;
00776     }
00777
00778     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
00779     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
00780
00781     /* Process Locked */
00782     __HAL_LOCK(hsmbus);
00783
00784     hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
00785     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00786
00787     /* Set SBC bit to manage Acknowledge at each bit */
00788     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00789
00790     /* Enable Address Acknowledge */
00791     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
00792
00793     /* Prepare transfer parameters */
00794     hsmbus->pBuffPtr = pData;
00795     hsmbus->XferSize = Size;
00796     hsmbus->XferCount = Size;
00797     hsmbus->XferOptions = XferOptions;
00798
00799     /* Set NBYTE to receive */
00800     /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
00801     /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
00802     /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
00803     /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
00804     if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
00805     {
00806       SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00807     }
00808     else
00809     {
00810       SMBUS_TransferConfig(hsmbus,0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
00811     }
00812
00813     /* Clear ADDR flag after prepare the transfer parameters */
00814     /* This action will generate an acknowledge to the HOST */
00815     __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
00816
00817     /* Process Unlocked */
00818     __HAL_UNLOCK(hsmbus);
00819
00820     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00821               to avoid the risk of SMBUS interrupt handle execution before current
00822               process unlock */
00823     /* REnable ADDR interrupt */
00824     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
00825
00826     return HAL_OK;
00827   }
00828   else
00829   {
00830     return HAL_ERROR;
00831   }
00832 }
00833
00834 /**
00835   * @brief  Enable the Address listen mode with Interrupt.
00836   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00837   *                the configuration information for the specified SMBUS.
00838   * @retval HAL status
00839   */
00840 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
00841 {
00842   hsmbus->State = HAL_SMBUS_STATE_LISTEN;
00843
00844   /* Enable the Address Match interrupt */
00845   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
00846
00847   return HAL_OK;
00848 }
00849
00850 /**
00851   * @brief  Disable the Address listen mode with Interrupt.
00852   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00853   *                the configuration information for the specified SMBUS.
00854   * @retval HAL status
00855   */
00856 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
00857 {
00858   /* Disable Address listen mode only if a transfer is not ongoing */
00859   if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
00860   {
00861     hsmbus->State = HAL_SMBUS_STATE_READY;
00862
00863     /* Disable the Address Match interrupt */
00864     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
00865
00866     return HAL_OK;
00867   }
00868   else
00869   {
00870     return HAL_BUSY;
00871   }
00872 }
00873
00874 /**
00875   * @brief  Enable the SMBUS alert mode with Interrupt.
00876   * @param  hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
00877   *                the configuration information for the specified SMBUSx peripheral.
00878   * @retval HAL status
00879   */
00880 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
00881 {
00882   /* Enable SMBus alert */
00883   hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
00884
00885   /* Clear ALERT flag */
00886   __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
00887
00888   /* Enable Alert Interrupt */
00889   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
00890
00891   return HAL_OK;
00892 }
00893 /**
00894   * @brief  Disable the SMBUS alert mode with Interrupt.
00895   * @param  hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
00896   *                the configuration information for the specified SMBUSx peripheral.
00897   * @retval HAL status
00898   */
00899 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
00900 {
00901   /* Enable SMBus alert */
00902   hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
00903
00904   /* Disable Alert Interrupt */
00905   SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
00906
00907   return HAL_OK;
00908 }
00909
00910 /**
00911   * @brief  Check if target device is ready for communication.
00912   * @note   This function is used with Memory devices
00913   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
00914   *                the configuration information for the specified SMBUS.
00915   * @param  DevAddress: Target device address
00916   * @param  Trials: Number of trials
00917   * @param  Timeout: Timeout duration
00918   * @retval HAL status
00919   */
00920 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
00921 {
00922   uint32_t tickstart = 0;
00923
00924   __IO uint32_t SMBUS_Trials = 0;
00925
00926   if(hsmbus->State == HAL_SMBUS_STATE_READY)
00927   {
00928     if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
00929     {
00930       return HAL_BUSY;
00931     }
00932
00933     /* Process Locked */
00934     __HAL_LOCK(hsmbus);
00935
00936     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00937     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00938
00939     do
00940     {
00941       /* Generate Start */
00942       hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
00943
00944       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00945       /* Wait until STOPF flag is set or a NACK flag is set*/
00946       tickstart = HAL_GetTick();
00947       while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
00948       {
00949         if(Timeout != HAL_MAX_DELAY)
00950         {
00951           if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00952           {
00953             /* Device is ready */
00954             hsmbus->State = HAL_SMBUS_STATE_READY;
00955
00956             /* Process Unlocked */
00957             __HAL_UNLOCK(hsmbus);
00958             return HAL_TIMEOUT;
00959           }
00960         }
00961       }
00962
00963       /* Check if the NACKF flag has not been set */
00964       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
00965       {
00966         /* Wait until STOPF flag is reset */
00967         if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
00968         {
00969           return HAL_TIMEOUT;
00970         }
00971
00972         /* Clear STOP Flag */
00973         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
00974
00975         /* Device is ready */
00976         hsmbus->State = HAL_SMBUS_STATE_READY;
00977
00978         /* Process Unlocked */
00979         __HAL_UNLOCK(hsmbus);
00980
00981         return HAL_OK;
00982       }
00983       else
00984       {
00985         /* Wait until STOPF flag is reset */
00986         if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
00987         {
00988           return HAL_TIMEOUT;
00989         }
00990
00991         /* Clear NACK Flag */
00992         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
00993
00994         /* Clear STOP Flag, auto generated with autoend*/
00995         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
00996       }
00997
00998       /* Check if the maximum allowed number of trials has been reached */
00999       if (SMBUS_Trials++ == Trials)
01000       {
01001         /* Generate Stop */
01002         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
01003
01004         /* Wait until STOPF flag is reset */
01005         if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01006         {
01007           return HAL_TIMEOUT;
01008         }
01009
01010         /* Clear STOP Flag */
01011         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01012       }
01013     }while(SMBUS_Trials < Trials);
01014
01015     hsmbus->State = HAL_SMBUS_STATE_READY;
01016
01017     /* Process Unlocked */
01018     __HAL_UNLOCK(hsmbus);
01019
01020     return HAL_TIMEOUT;
01021   }
01022   else
01023   {
01024     return HAL_BUSY;
01025   }
01026 }
01027 /**
01028   * @}
01029   */
01030
01031 /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
01032  * @{
01033  */
01034
01035 /**
01036   * @brief  Handle SMBUS event interrupt request.
01037   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01038   *                the configuration information for the specified SMBUS.
01039   * @retval None
01040   */
01041 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01042 {
01043   uint32_t tmpisrvalue = 0;
01044
01045   /* Use a local variable to store the current ISR flags */
01046   /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
01047   tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
01048
01049   /* SMBUS in mode Transmitter ---------------------------------------------------*/
01050   if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
01051   {
01052     /* Slave mode selected */
01053     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01054     {
01055       SMBUS_Slave_ISR(hsmbus);
01056     }
01057     /* Master mode selected */
01058     else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01059     {
01060       SMBUS_Master_ISR(hsmbus);
01061     }
01062   }
01063
01064   /* SMBUS in mode Receiver ----------------------------------------------------*/
01065   if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
01066   {
01067     /* Slave mode selected */
01068     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
01069     {
01070       SMBUS_Slave_ISR(hsmbus);
01071     }
01072     /* Master mode selected */
01073     else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01074     {
01075       SMBUS_Master_ISR(hsmbus);
01076     }
01077   }
01078
01079    /* SMBUS in mode Listener Only --------------------------------------------------*/
01080   if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
01081      && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
01082   {
01083     if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
01084     {
01085       SMBUS_Slave_ISR(hsmbus);
01086     }
01087   }
01088 }
01089
01090 /**
01091   * @brief  Handle SMBUS error interrupt request.
01092   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01093   *                the configuration information for the specified SMBUS.
01094   * @retval None
01095   */
01096 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01097 {
01098   /* SMBUS Bus error interrupt occurred ------------------------------------*/
01099   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01100   {
01101     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
01102
01103     /* Clear BERR flag */
01104     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
01105   }
01106
01107   /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
01108   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01109   {
01110     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
01111
01112     /* Clear OVR flag */
01113     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
01114   }
01115
01116   /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
01117   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01118   {
01119     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
01120
01121     /* Clear ARLO flag */
01122     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
01123   }
01124
01125   /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
01126   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01127   {
01128     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
01129
01130     /* Clear TIMEOUT flag */
01131     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
01132   }
01133
01134   /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
01135   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01136   {
01137     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
01138
01139     /* Clear ALERT flag */
01140     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
01141   }
01142
01143   /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
01144   if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
01145   {
01146     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
01147
01148     /* Clear PEC error flag */
01149     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
01150   }
01151
01152   /* Call the Error Callback() in case of Error detected */
01153   if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
01154   {
01155     /* Do not Reset the HAL state in case of ALERT error */
01156     if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
01157     {
01158       if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01159          || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
01160       {
01161         /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
01162         /* keep HAL_SMBUS_STATE_LISTEN if set */
01163         hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01164         hsmbus->State = HAL_SMBUS_STATE_LISTEN;
01165       }
01166     }
01167
01168     /* Call the Error callback to prevent upper layer */
01169     HAL_SMBUS_ErrorCallback(hsmbus);
01170   }
01171 }
01172
01173 /**
01174   * @brief  Master Tx Transfer completed callback.
01175   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01176   *                the configuration information for the specified SMBUS.
01177   * @retval None
01178   */
01179 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01180 {
01181   /* Prevent unused argument(s) compilation warning */
01182   UNUSED(hsmbus);
01183
01184   /* NOTE : This function should not be modified, when the callback is needed,
01185             the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
01186    */
01187 }
01188
01189 /**
01190   * @brief  Master Rx Transfer completed callback.
01191   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01192   *                the configuration information for the specified SMBUS.
01193   * @retval None
01194   */
01195 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01196 {
01197   /* Prevent unused argument(s) compilation warning */
01198   UNUSED(hsmbus);
01199
01200   /* NOTE : This function should not be modified, when the callback is needed,
01201             the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
01202    */
01203 }
01204
01205 /** @brief  Slave Tx Transfer completed callback.
01206   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01207   *                the configuration information for the specified SMBUS.
01208   * @retval None
01209   */
01210 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01211 {
01212   /* Prevent unused argument(s) compilation warning */
01213   UNUSED(hsmbus);
01214
01215   /* NOTE : This function should not be modified, when the callback is needed,
01216             the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
01217    */
01218 }
01219
01220 /**
01221   * @brief  Slave Rx Transfer completed callback.
01222   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01223   *                the configuration information for the specified SMBUS.
01224   * @retval None
01225   */
01226 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01227 {
01228   /* Prevent unused argument(s) compilation warning */
01229   UNUSED(hsmbus);
01230
01231   /* NOTE : This function should not be modified, when the callback is needed,
01232             the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
01233    */
01234 }
01235
01236 /**
01237   * @brief  Slave Address Match callback.
01238   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01239   *                the configuration information for the specified SMBUS.
01240   * @param  TransferDirection: Master request Transfer Direction (Write/Read)
01241   * @param  AddrMatchCode: Address Match Code
01242   * @retval None
01243   */
01244 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
01245 {
01246   /* Prevent unused argument(s) compilation warning */
01247   UNUSED(hsmbus);
01248   UNUSED(TransferDirection);
01249   UNUSED(AddrMatchCode);
01250
01251   /* NOTE : This function should not be modified, when the callback is needed,
01252             the HAL_SMBUS_AddrCallback() could be implemented in the user file
01253    */
01254 }
01255
01256 /**
01257   * @brief  Listen Complete callback.
01258   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01259   *                the configuration information for the specified SMBUS.
01260   * @retval None
01261   */
01262 __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01263 {
01264   /* Prevent unused argument(s) compilation warning */
01265   UNUSED(hsmbus);
01266
01267   /* NOTE : This function should not be modified, when the callback is needed,
01268             the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
01269    */
01270 }
01271
01272 /**
01273   * @brief  SMBUS error callback.
01274   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01275   *                the configuration information for the specified SMBUS.
01276   * @retval None
01277   */
01278 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
01279 {
01280   /* Prevent unused argument(s) compilation warning */
01281   UNUSED(hsmbus);
01282
01283   /* NOTE : This function should not be modified, when the callback is needed,
01284             the HAL_SMBUS_ErrorCallback() could be implemented in the user file
01285    */
01286 }
01287
01288 /**
01289   * @}
01290   */
01291
01292 /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
01293  *  @brief   Peripheral State and Errors functions
01294  *
01295 @verbatim
01296  ===============================================================================
01297             ##### Peripheral State and Errors functions #####
01298  ===============================================================================
01299     [..]
01300     This subsection permits to get in run-time the status of the peripheral
01301     and the data flow.
01302
01303 @endverbatim
01304   * @{
01305   */
01306
01307 /**
01308   * @brief  Return the SMBUS handle state.
01309   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01310   *                the configuration information for the specified SMBUS.
01311   * @retval HAL state
01312   */
01313 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
01314 {
01315   /* Return SMBUS handle state */
01316   return hsmbus->State;
01317 }
01318
01319 /**
01320 * @brief  Return the SMBUS error code.
01321 * @param  hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
01322   *              the configuration information for the specified SMBUS.
01323 * @retval SMBUS Error Code
01324 */
01325 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
01326 {
01327   return hsmbus->ErrorCode;
01328 }
01329
01330 /**
01331   * @}
01332   */
01333
01334 /**
01335   * @}
01336   */
01337
01338 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
01339  *  @brief   Data transfers Private functions
01340   * @{
01341   */
01342
01343 /**
01344   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
01345   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01346   *                the configuration information for the specified SMBUS.
01347   * @retval HAL status
01348   */
01349 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
01350 {
01351   uint16_t DevAddress;
01352
01353   /* Process Locked */
01354   __HAL_LOCK(hsmbus);
01355
01356   if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
01357   {
01358     /* Clear NACK Flag */
01359     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01360
01361     /* Set corresponding Error Code */
01362     /* No need to generate STOP, it is automatically done */
01363     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
01364
01365     /* Process Unlocked */
01366     __HAL_UNLOCK(hsmbus);
01367
01368     /* Call the Error callback to prevent upper layer */
01369     HAL_SMBUS_ErrorCallback(hsmbus);
01370   }
01371   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
01372   {
01373
01374     /* Call the corresponding callback to inform upper layer of End of Transfer */
01375     if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01376     {
01377       /* Disable Interrupt */
01378       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01379
01380       /* Clear STOP Flag */
01381       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01382
01383       /* Clear Configuration Register 2 */
01384       SMBUS_RESET_CR2(hsmbus);
01385
01386       /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
01387       /* Disable the selected SMBUS peripheral */
01388       __HAL_SMBUS_DISABLE(hsmbus);
01389
01390       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01391       hsmbus->State = HAL_SMBUS_STATE_READY;
01392
01393       /* Process Unlocked */
01394       __HAL_UNLOCK(hsmbus);
01395
01396       /* REenable the selected SMBUS peripheral */
01397       __HAL_SMBUS_ENABLE(hsmbus);
01398
01399       HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01400     }
01401     else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01402     {
01403       /* Disable Interrupt */
01404       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01405
01406       /* Clear STOP Flag */
01407       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01408
01409       /* Clear Configuration Register 2 */
01410       SMBUS_RESET_CR2(hsmbus);
01411
01412       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01413       hsmbus->State = HAL_SMBUS_STATE_READY;
01414
01415       /* Process Unlocked */
01416       __HAL_UNLOCK(hsmbus);
01417
01418       HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01419     }
01420   }
01421   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
01422   {
01423     /* Read data from RXDR */
01424     (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
01425     hsmbus->XferSize--;
01426     hsmbus->XferCount--;
01427   }
01428   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
01429   {
01430     /* Write data to TXDR */
01431     hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
01432     hsmbus->XferSize--;
01433     hsmbus->XferCount--;
01434   }
01435   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
01436   {
01437     if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
01438     {
01439       DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
01440
01441       if(hsmbus->XferCount > MAX_NBYTE_SIZE)
01442       {
01443         SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
01444         hsmbus->XferSize = MAX_NBYTE_SIZE;
01445       }
01446       else
01447       {
01448         hsmbus->XferSize = hsmbus->XferCount;
01449         SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01450         /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01451         /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01452         if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
01453         {
01454           hsmbus->XferSize--;
01455           hsmbus->XferCount--;
01456         }
01457       }
01458     }
01459     else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0))
01460     {
01461       /* Call TxCpltCallback() if no stop mode is set */
01462       if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
01463       {
01464         /* Call the corresponding callback to inform upper layer of End of Transfer */
01465         if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01466         {
01467           /* Disable Interrupt */
01468           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01469           hsmbus->PreviousState = hsmbus->State;
01470           hsmbus->State = HAL_SMBUS_STATE_READY;
01471
01472           /* Process Unlocked */
01473           __HAL_UNLOCK(hsmbus);
01474
01475           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01476         }
01477         else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01478         {
01479           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01480           hsmbus->PreviousState = hsmbus->State;
01481           hsmbus->State = HAL_SMBUS_STATE_READY;
01482
01483           /* Process Unlocked */
01484           __HAL_UNLOCK(hsmbus);
01485
01486           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01487         }
01488       }
01489     }
01490   }
01491   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
01492   {
01493     if(hsmbus->XferCount == 0)
01494     {
01495       /* Specific use case for Quick command */
01496       if(hsmbus->pBuffPtr == NULL)
01497       {
01498         /* Generate a Stop command */
01499         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
01500       }
01501       /* Call TxCpltCallback() if no stop mode is set */
01502       else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
01503       {
01504         /* No Generate Stop, to permit restart mode */
01505         /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
01506
01507         /* Call the corresponding callback to inform upper layer of End of Transfer */
01508         if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01509         {
01510           /* Disable Interrupt */
01511           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01512           hsmbus->PreviousState = hsmbus->State;
01513           hsmbus->State = HAL_SMBUS_STATE_READY;
01514
01515           /* Process Unlocked */
01516           __HAL_UNLOCK(hsmbus);
01517
01518           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01519         }
01520         else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01521         {
01522           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01523           hsmbus->PreviousState = hsmbus->State;
01524           hsmbus->State = HAL_SMBUS_STATE_READY;
01525
01526           /* Process Unlocked */
01527           __HAL_UNLOCK(hsmbus);
01528
01529           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01530         }
01531       }
01532     }
01533   }
01534
01535   /* Process Unlocked */
01536   __HAL_UNLOCK(hsmbus);
01537
01538   return HAL_OK;
01539 }
01540 /**
01541   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
01542   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01543   *                the configuration information for the specified SMBUS.
01544   * @retval HAL status
01545   */
01546 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
01547 {
01548   uint8_t TransferDirection = 0;
01549   uint16_t SlaveAddrCode = 0;
01550
01551   /* Process Locked */
01552   __HAL_LOCK(hsmbus);
01553
01554   if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
01555   {
01556     /* Check that SMBUS transfer finished */
01557     /* if yes, normal use case, a NACK is sent by the HOST when Transfer is finished */
01558     /* Mean XferCount == 0*/
01559     /* So clear Flag NACKF only */
01560     if(hsmbus->XferCount == 0)
01561     {
01562       /* Clear NACK Flag */
01563       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01564
01565       /* Process Unlocked */
01566       __HAL_UNLOCK(hsmbus);
01567     }
01568     else
01569     {
01570       /* if no, error use case, a Non-Acknowledge of last Data is generated by the HOST*/
01571       /* Clear NACK Flag */
01572       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01573
01574       /* Set HAL State to "Idle" State, mean to LISTEN state */
01575       /* So reset Slave Busy state */
01576       hsmbus->PreviousState = hsmbus->State;
01577       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
01578       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
01579
01580       /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
01581       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
01582
01583       /* Set ErrorCode corresponding to a Non-Acknowledge */
01584       hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
01585
01586       /* Process Unlocked */
01587       __HAL_UNLOCK(hsmbus);
01588
01589       /* Call the Error callback to prevent upper layer */
01590       HAL_SMBUS_ErrorCallback(hsmbus);
01591     }
01592   }
01593   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
01594   {
01595     TransferDirection = SMBUS_GET_DIR(hsmbus);
01596     SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
01597
01598     /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
01599     /* Other ADDRInterrupt will be treat in next Listen use case */
01600     __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
01601
01602     /* Process Unlocked */
01603     __HAL_UNLOCK(hsmbus);
01604
01605     /* Call Slave Addr callback */
01606     HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
01607   }
01608   else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
01609   {
01610     if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
01611     {
01612       /* Read data from RXDR */
01613       (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
01614       hsmbus->XferSize--;
01615       hsmbus->XferCount--;
01616
01617       if(hsmbus->XferCount == 1)
01618       {
01619         /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
01620         /* or only the last Byte of Transfer */
01621         /* So reset the RELOAD bit mode */
01622         hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
01623         SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01624       }
01625       else if(hsmbus->XferCount == 0)
01626       {
01627         /* Last Byte is received, disable Interrupt */
01628         SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01629
01630         /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
01631         hsmbus->PreviousState = hsmbus->State;
01632         hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
01633
01634         /* Process Unlocked */
01635         __HAL_UNLOCK(hsmbus);
01636
01637         /* Call the Rx complete callback to inform upper layer of the end of receive process */
01638         HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
01639       }
01640       else
01641       {
01642         /* Set Reload for next Bytes */
01643         SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
01644
01645         /* Ack last Byte Read */
01646         hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01647       }
01648     }
01649     else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01650     {
01651       if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
01652       {
01653         if(hsmbus->XferCount > MAX_NBYTE_SIZE)
01654         {
01655           SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
01656           hsmbus->XferSize = MAX_NBYTE_SIZE;
01657         }
01658         else
01659         {
01660           hsmbus->XferSize = hsmbus->XferCount;
01661           SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01662           /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01663           /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01664           if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
01665           {
01666             hsmbus->XferSize--;
01667             hsmbus->XferCount--;
01668           }
01669         }
01670       }
01671     }
01672   }
01673   else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
01674   {
01675     /* Write data to TXDR only if XferCount not reach "0" */
01676     /* A TXIS flag can be set, during STOP treatment      */
01677     /* Check if all Data have already been sent */
01678     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
01679     if(hsmbus->XferCount > 0)
01680     {
01681       /* Write data to TXDR */
01682       hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
01683       hsmbus->XferCount--;
01684       hsmbus->XferSize--;
01685     }
01686
01687     if(hsmbus->XferCount == 0)
01688     {
01689       /* Last Byte is Transmitted */
01690       /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
01691       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01692       hsmbus->PreviousState = hsmbus->State;
01693       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
01694
01695       /* Process Unlocked */
01696       __HAL_UNLOCK(hsmbus);
01697
01698       /* Call the Tx complete callback to inform upper layer of the end of transmit process */
01699       HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
01700     }
01701   }
01702
01703   /* Check if STOPF is set */
01704   if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
01705   {
01706     if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01707     {
01708       /* Disable RX and TX Interrupts */
01709       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
01710
01711       /* Disable ADDR Interrupt */
01712       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
01713
01714       /* Disable Address Acknowledge */
01715       hsmbus->Instance->CR2 |= I2C_CR2_NACK;
01716
01717       /* Clear Configuration Register 2 */
01718       SMBUS_RESET_CR2(hsmbus);
01719
01720       /* Clear STOP Flag */
01721       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01722
01723      /* Clear ADDR flag */
01724      __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
01725
01726       hsmbus->XferOptions = 0;
01727       hsmbus->PreviousState = hsmbus->State;
01728       hsmbus->State = HAL_SMBUS_STATE_READY;
01729
01730       /* Process Unlocked */
01731       __HAL_UNLOCK(hsmbus);
01732
01733       /* Call the Listen Complete callback, to prevent upper layer of the end of Listen use case */
01734       HAL_SMBUS_ListenCpltCallback(hsmbus);
01735     }
01736   }
01737
01738   /* Process Unlocked */
01739   __HAL_UNLOCK(hsmbus);
01740
01741   return HAL_OK;
01742 }
01743 /**
01744   * @brief  Manage the enabling of Interrupts.
01745   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01746   *                the configuration information for the specified SMBUS.
01747   * @param  InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
01748   * @retval HAL status
01749   */
01750 static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
01751 {
01752   uint32_t tmpisr = 0;
01753
01754   if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
01755   {
01756     /* Enable ERR interrupt */
01757     tmpisr |= SMBUS_IT_ERRI;
01758   }
01759
01760   if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
01761   {
01762     /* Enable ADDR, STOP interrupt */
01763     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
01764   }
01765
01766   if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
01767   {
01768     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01769     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
01770   }
01771
01772   if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
01773   {
01774     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01775     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
01776   }
01777
01778   /* Enable interrupts only at the end */
01779   /* to avoid the risk of SMBUS interrupt handle execution before */
01780   /* all interrupts requested done */
01781   __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
01782
01783   return HAL_OK;
01784 }
01785 /**
01786   * @brief  Manage the disabling of Interrupts.
01787   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01788   *                the configuration information for the specified SMBUS.
01789   * @param  InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
01790   * @retval HAL status
01791   */
01792 static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
01793 {
01794   uint32_t tmpisr = 0;
01795
01796   if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
01797   {
01798     /* Disable ERR interrupt */
01799     tmpisr |= SMBUS_IT_ERRI;
01800   }
01801
01802   if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
01803   {
01804     /* Disable TC, STOP, NACK, TXI interrupt */
01805     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
01806
01807     if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
01808        && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
01809     {
01810       /* Disable ERR interrupt */
01811       tmpisr |= SMBUS_IT_ERRI;
01812     }
01813
01814     if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
01815     {
01816       /* Disable STOPI, NACKI */
01817       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
01818     }
01819   }
01820
01821   if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
01822   {
01823     /* Disable TC, STOP, NACK, RXI interrupt */
01824     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
01825
01826     if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
01827        && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
01828     {
01829       /* Disable ERR interrupt */
01830       tmpisr |= SMBUS_IT_ERRI;
01831     }
01832
01833     if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
01834     {
01835       /* Disable STOPI, NACKI */
01836       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
01837     }
01838   }
01839
01840   if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
01841   {
01842     /* Enable ADDR, STOP interrupt */
01843     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
01844
01845     if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
01846     {
01847       /* Disable ERR interrupt */
01848       tmpisr |= SMBUS_IT_ERRI;
01849     }
01850   }
01851
01852   /* Disable interrupts only at the end */
01853   /* to avoid a breaking situation like at "t" time */
01854   /* all disable interrupts request are not done */
01855   __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
01856
01857   return HAL_OK;
01858 }
01859 /**
01860   * @brief  Handle SMBUS Communication Timeout.
01861   * @param  hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
01862   *                the configuration information for the specified SMBUS.
01863   * @param  Flag: specifies the SMBUS flag to check.
01864   * @param  Status: The new Flag status (SET or RESET).
01865   * @param  Timeout: Timeout duration
01866   * @retval HAL status
01867   */
01868 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
01869 {
01870   uint32_t tickstart = HAL_GetTick();
01871
01872   /* Wait until flag is set */
01873   if(Status == RESET)
01874   {
01875     while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
01876     {
01877       /* Check for the Timeout */
01878       if(Timeout != HAL_MAX_DELAY)
01879       {
01880         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01881         {
01882           hsmbus->PreviousState = hsmbus->State;
01883           hsmbus->State= HAL_SMBUS_STATE_READY;
01884
01885           /* Process Unlocked */
01886           __HAL_UNLOCK(hsmbus);
01887
01888           return HAL_TIMEOUT;
01889         }
01890       }
01891     }
01892   }
01893   else
01894   {
01895     while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
01896     {
01897       /* Check for the Timeout */
01898       if(Timeout != HAL_MAX_DELAY)
01899       {
01900         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01901         {
01902           hsmbus->PreviousState = hsmbus->State;
01903           hsmbus->State= HAL_SMBUS_STATE_READY;
01904
01905           /* Process Unlocked */
01906           __HAL_UNLOCK(hsmbus);
01907
01908           return HAL_TIMEOUT;
01909         }
01910       }
01911     }
01912   }
01913   return HAL_OK;
01914 }
01915
01916 /**
01917   * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
01918   * @param  hsmbus: SMBUS handle.
01919   * @param  DevAddress: specifies the slave address to be programmed.
01920   * @param  Size: specifies the number of bytes to be programmed.
01921   *   This parameter must be a value between 0 and 255.
01922   * @param  Mode: new state of the SMBUS START condition generation.
01923   *   This parameter can be one or a combination  of the following values:
01924   *     @arg SMBUS_NO_MODE: No specific mode enabled.
01925   *     @arg SMBUS_RELOAD_MODE: Enable Reload mode.
01926   *     @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode.
01927   *     @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
01928   * @param  Request: new state of the SMBUS START condition generation.
01929   *   This parameter can be one of the following values:
01930   *     @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition.
01931   *     @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
01932   *     @arg SMBUS_GENERATE_START_READ: Generate Restart for read request.
01933   *     @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
01934   * @retval None
01935   */
01936 static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
01937 {
01938   uint32_t tmpreg = 0;
01939
01940   /* Check the parameters */
01941   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
01942   assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
01943   assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
01944
01945   /* Get the CR2 register value */
01946   tmpreg = hsmbus->Instance->CR2;
01947
01948   /* clear tmpreg specific bits */
01949   tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
01950
01951   /* update tmpreg */
01952   tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
01953               (uint32_t)Mode | (uint32_t)Request);
01954
01955   /* update CR2 register */
01956   hsmbus->Instance->CR2 = tmpreg;
01957 }
01958 /**
01959   * @}
01960   */
01961
01962 #endif /* HAL_SMBUS_MODULE_ENABLED */
01963 /**
01964   * @}
01965   */
01966
01967 /**
01968   * @}
01969   */
01970
01971 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_smbus.h Source File

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stm32l4xx_hal_smbus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_smbus.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SMBUS HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_SMBUS_H
00040 #define __STM32L4xx_HAL_SMBUS_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SMBUS
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
00059   * @{
00060   */
00061
00062 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
00063   * @brief  SMBUS Configuration Structure definition
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
00069                                      This parameter calculated by referring to SMBUS initialization
00070                                             section in Reference manual */
00071   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
00072                                      This parameter can be a value of @ref SMBUS_Analog_Filter */
00073
00074   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
00075                                      This parameter can be a 7-bit or 10-bit address. */
00076
00077   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
00078                                      This parameter can be a value of @ref SMBUS_addressing_mode */
00079
00080   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
00081                                      This parameter can be a value of @ref SMBUS_dual_addressing_mode */
00082
00083   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
00084                                      This parameter can be a 7-bit address. */
00085
00086   uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
00087                                      This parameter can be a value of @ref SMBUS_own_address2_masks. */
00088
00089   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
00090                                      This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
00091
00092   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
00093                                      This parameter can be a value of @ref SMBUS_nostretch_mode */
00094
00095   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
00096                                      This parameter can be a value of @ref SMBUS_packet_error_check_mode */
00097
00098   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
00099                                      This parameter can be a value of @ref SMBUS_peripheral_mode */
00100
00101   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
00102                                                                                                                                                 (Enable bits and different timeout values)
00103                                      This parameter calculated by referring to SMBUS initialization
00104                                          section in Reference manual */
00105 } SMBUS_InitTypeDef;
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup HAL_state_definition HAL state definition
00111   * @brief  HAL State definition
00112   * @{
00113   */
00114 #define HAL_SMBUS_STATE_RESET           ((uint32_t)0x00000000)  /*!< SMBUS not yet initialized or disabled         */
00115 #define HAL_SMBUS_STATE_READY           ((uint32_t)0x00000001)  /*!< SMBUS initialized and ready for use           */
00116 #define HAL_SMBUS_STATE_BUSY            ((uint32_t)0x00000002)  /*!< SMBUS internal process is ongoing             */
00117 #define HAL_SMBUS_STATE_MASTER_BUSY_TX  ((uint32_t)0x00000012)  /*!< Master Data Transmission process is ongoing   */
00118 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  ((uint32_t)0x00000022)  /*!< Master Data Reception process is ongoing      */
00119 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   ((uint32_t)0x00000032)  /*!< Slave Data Transmission process is ongoing    */
00120 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   ((uint32_t)0x00000042)  /*!< Slave Data Reception process is ongoing       */
00121 #define HAL_SMBUS_STATE_TIMEOUT         ((uint32_t)0x00000003)  /*!< Timeout state                                 */
00122 #define HAL_SMBUS_STATE_ERROR           ((uint32_t)0x00000004)  /*!< Reception process is ongoing                  */
00123 #define HAL_SMBUS_STATE_LISTEN          ((uint32_t)0x00000008)   /*!< Address Listen Mode is ongoing                */
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
00129   * @brief  SMBUS Error Code definition
00130   * @{
00131   */
00132 #define HAL_SMBUS_ERROR_NONE        ((uint32_t)0x00000000)    /*!< No error             */
00133 #define HAL_SMBUS_ERROR_BERR        ((uint32_t)0x00000001)    /*!< BERR error           */
00134 #define HAL_SMBUS_ERROR_ARLO        ((uint32_t)0x00000002)    /*!< ARLO error           */
00135 #define HAL_SMBUS_ERROR_ACKF        ((uint32_t)0x00000004)    /*!< ACKF error           */
00136 #define HAL_SMBUS_ERROR_OVR         ((uint32_t)0x00000008)    /*!< OVR error            */
00137 #define HAL_SMBUS_ERROR_HALTIMEOUT  ((uint32_t)0x00000010)    /*!< Timeout error        */
00138 #define HAL_SMBUS_ERROR_BUSTIMEOUT  ((uint32_t)0x00000020)    /*!< Bus Timeout error    */
00139 #define HAL_SMBUS_ERROR_ALERT       ((uint32_t)0x00000040)    /*!< Alert error          */
00140 #define HAL_SMBUS_ERROR_PECERR      ((uint32_t)0x00000080)    /*!< PEC error            */
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
00146   * @brief  SMBUS handle Structure definition
00147   * @{
00148   */
00149 typedef struct
00150 {
00151   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
00152
00153   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
00154
00155   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
00156
00157   uint16_t                     XferSize;        /*!< SMBUS transfer size                */
00158
00159   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
00160
00161   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
00162
00163   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
00164
00165   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
00166
00167   __IO uint32_t                State;           /*!< SMBUS communication state          */
00168
00169   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
00170
00171 }SMBUS_HandleTypeDef;
00172 /**
00173   * @}
00174   */
00175
00176 /**
00177   * @}
00178   */
00179 /* Exported constants --------------------------------------------------------*/
00180
00181 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
00182   * @{
00183   */
00184
00185 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
00186   * @{
00187   */
00188 #define SMBUS_ANALOGFILTER_ENABLE               ((uint32_t)0x00000000)
00189 #define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
00195   * @{
00196   */
00197 #define SMBUS_ADDRESSINGMODE_7BIT               ((uint32_t)0x00000001)
00198 #define SMBUS_ADDRESSINGMODE_10BIT              ((uint32_t)0x00000002)
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
00204   * @{
00205   */
00206
00207 #define SMBUS_DUALADDRESS_DISABLE               ((uint32_t)0x00000000)
00208 #define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup SMBUS_own_address2_masks SMBUS own address2 masks
00214   * @{
00215   */
00216
00217 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00)
00218 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01)
00219 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02)
00220 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03)
00221 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04)
00222 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05)
00223 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06)
00224 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07)
00225 /**
00226   * @}
00227   */
00228
00229
00230 /** @defgroup SMBUS_general_call_addressing_mode  SMBUS general call addressing mode
00231   * @{
00232   */
00233 #define SMBUS_GENERALCALL_DISABLE               ((uint32_t)0x00000000)
00234 #define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
00240   * @{
00241   */
00242 #define SMBUS_NOSTRETCH_DISABLE                 ((uint32_t)0x00000000)
00243 #define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
00249   * @{
00250   */
00251 #define SMBUS_PEC_DISABLE                       ((uint32_t)0x00000000)
00252 #define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
00258   * @{
00259   */
00260 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        (uint32_t)(I2C_CR1_SMBHEN)
00261 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (uint32_t)(0x00000000)
00262 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   (uint32_t)(I2C_CR1_SMBDEN)
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup SMBUS_ReloadEndMode_definition  SMBUS ReloadEndMode definition
00268   * @{
00269   */
00270
00271 #define  SMBUS_SOFTEND_MODE                     ((uint32_t)0x00000000)
00272 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
00273 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
00274 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
00280   * @{
00281   */
00282
00283 #define  SMBUS_NO_STARTSTOP                     ((uint32_t)0x00000000)
00284 #define  SMBUS_GENERATE_STOP                    I2C_CR2_STOP
00285 #define  SMBUS_GENERATE_START_READ              (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
00286 #define  SMBUS_GENERATE_START_WRITE             I2C_CR2_START
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup SMBUS_XferOptions_definition  SMBUS XferOptions definition
00292   * @{
00293   */
00294
00295 #define  SMBUS_FIRST_FRAME                      ((uint32_t)(SMBUS_SOFTEND_MODE))
00296 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
00297 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
00298 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
00299 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00300 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
00306   * @brief SMBUS Interrupt definition
00307   *        Elements values convention: 0xXXXXXXXX
00308   *           - XXXXXXXX  : Interrupt control mask
00309   * @{
00310   */
00311 #define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
00312 #define SMBUS_IT_TCI                            I2C_CR1_TCIE
00313 #define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
00314 #define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
00315 #define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
00316 #define SMBUS_IT_RXI                            I2C_CR1_RXIE
00317 #define SMBUS_IT_TXI                            I2C_CR1_TXIE
00318 #define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
00319 #define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
00320 #define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
00321 #define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
00327   * @brief Flag definition
00328   *        Elements values convention: 0xXXXXYYYY
00329   *           - XXXXXXXX  : Flag mask
00330   * @{
00331   */
00332
00333 #define  SMBUS_FLAG_TXE                   I2C_ISR_TXE
00334 #define  SMBUS_FLAG_TXIS                  I2C_ISR_TXIS
00335 #define  SMBUS_FLAG_RXNE                  I2C_ISR_RXNE
00336 #define  SMBUS_FLAG_ADDR                  I2C_ISR_ADDR
00337 #define  SMBUS_FLAG_AF                    I2C_ISR_NACKF
00338 #define  SMBUS_FLAG_STOPF                 I2C_ISR_STOPF
00339 #define  SMBUS_FLAG_TC                    I2C_ISR_TC
00340 #define  SMBUS_FLAG_TCR                   I2C_ISR_TCR
00341 #define  SMBUS_FLAG_BERR                  I2C_ISR_BERR
00342 #define  SMBUS_FLAG_ARLO                  I2C_ISR_ARLO
00343 #define  SMBUS_FLAG_OVR                   I2C_ISR_OVR
00344 #define  SMBUS_FLAG_PECERR                I2C_ISR_PECERR
00345 #define  SMBUS_FLAG_TIMEOUT               I2C_ISR_TIMEOUT
00346 #define  SMBUS_FLAG_ALERT                 I2C_ISR_ALERT
00347 #define  SMBUS_FLAG_BUSY                  I2C_ISR_BUSY
00348 #define  SMBUS_FLAG_DIR                   I2C_ISR_DIR
00349 /**
00350   * @}
00351   */
00352
00353 /**
00354   * @}
00355   */
00356
00357 /* Exported macros ------------------------------------------------------------*/
00358 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
00359   * @{
00360   */
00361
00362 /** @brief  Reset SMBUS handle state.
00363   * @param  __HANDLE__: specifies the SMBUS Handle.
00364   * @retval None
00365   */
00366 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)      ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
00367
00368 /** @brief  Enable the specified SMBUS interrupts.
00369   * @param  __HANDLE__: specifies the SMBUS Handle.
00370   * @param  __INTERRUPT__: specifies the interrupt source to enable.
00371   *        This parameter can be one of the following values:
00372   *            @arg SMBUS_IT_ERRI: Errors interrupt enable
00373   *            @arg SMBUS_IT_TCI: Transfer complete interrupt enable
00374   *            @arg SMBUS_IT_STOPI: STOP detection interrupt enable
00375   *            @arg SMBUS_IT_NACKI: NACK received interrupt enable
00376   *            @arg SMBUS_IT_ADDRI: Address match interrupt enable
00377   *            @arg SMBUS_IT_RXI: RX interrupt enable
00378   *            @arg SMBUS_IT_TXI: TX interrupt enable
00379   *
00380   * @retval None
00381   */
00382 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00383
00384 /** @brief  Disable the specified SMBUS interrupts.
00385   * @param  __HANDLE__: specifies the SMBUS Handle.
00386   * @param  __INTERRUPT__: specifies the interrupt source to disable.
00387   *        This parameter can be one of the following values:
00388   *            @arg SMBUS_IT_ERRI: Errors interrupt enable
00389   *            @arg SMBUS_IT_TCI: Transfer complete interrupt enable
00390   *            @arg SMBUS_IT_STOPI: STOP detection interrupt enable
00391   *            @arg SMBUS_IT_NACKI: NACK received interrupt enable
00392   *            @arg SMBUS_IT_ADDRI: Address match interrupt enable
00393   *            @arg SMBUS_IT_RXI: RX interrupt enable
00394   *            @arg SMBUS_IT_TXI: TX interrupt enable
00395   *
00396   * @retval None
00397   */
00398 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00399
00400 /** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
00401   * @param  __HANDLE__: specifies the SMBUS Handle.
00402   * @param  __INTERRUPT__: specifies the SMBUS interrupt source to check.
00403   *          This parameter can be one of the following values:
00404   *            @arg SMBUS_IT_ERRI: Errors interrupt enable
00405   *            @arg SMBUS_IT_TCI: Transfer complete interrupt enable
00406   *            @arg SMBUS_IT_STOPI: STOP detection interrupt enable
00407   *            @arg SMBUS_IT_NACKI: NACK received interrupt enable
00408   *            @arg SMBUS_IT_ADDRI: Address match interrupt enable
00409   *            @arg SMBUS_IT_RXI: RX interrupt enable
00410   *            @arg SMBUS_IT_TXI: TX interrupt enable
00411   *
00412   * @retval The new state of __IT__ (TRUE or FALSE).
00413   */
00414 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00415
00416 /** @brief  Check whether the specified SMBUS flag is set or not.
00417   * @param  __HANDLE__: specifies the SMBUS Handle.
00418   * @param  __FLAG__: specifies the flag to check.
00419   *        This parameter can be one of the following values:
00420   *            @arg SMBUS_FLAG_TXE:             Transmit data register empty
00421   *            @arg SMBUS_FLAG_TXIS:            Transmit interrupt status
00422   *            @arg SMBUS_FLAG_RXNE:            Receive data register not empty
00423   *            @arg SMBUS_FLAG_ADDR:            Address matched (slave mode)
00424   *            @arg SMBUS_FLAG_AF:              NACK received flag
00425   *            @arg SMBUS_FLAG_STOPF:           STOP detection flag
00426   *            @arg SMBUS_FLAG_TC:              Transfer complete (master mode)
00427   *            @arg SMBUS_FLAG_TCR:             Transfer complete reload
00428   *            @arg SMBUS_FLAG_BERR:            Bus error
00429   *            @arg SMBUS_FLAG_ARLO:            Arbitration lost
00430   *            @arg SMBUS_FLAG_OVR:             Overrun/Underrun
00431   *            @arg SMBUS_FLAG_PECERR:          PEC error in reception
00432   *            @arg SMBUS_FLAG_TIMEOUT:         Timeout or Tlow detection flag
00433   *            @arg SMBUS_FLAG_ALERT:           SMBus alert
00434   *            @arg SMBUS_FLAG_BUSY:            Bus busy
00435   *            @arg SMBUS_FLAG_DIR:             Transfer direction (slave mode)
00436   *
00437   * @retval The new state of __FLAG__ (TRUE or FALSE).
00438   */
00439 #define SMBUS_FLAG_MASK  ((uint32_t)0x0001FFFF)
00440 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__)      (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
00441
00442 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
00443   * @param  __HANDLE__: specifies the SMBUS Handle.
00444   * @param  __FLAG__: specifies the flag to clear.
00445   *          This parameter can be any combination of the following values:
00446   *            @arg SMBUS_FLAG_ADDR:            Address matched (slave mode)
00447   *            @arg SMBUS_FLAG_AF:              NACK received flag
00448   *            @arg SMBUS_FLAG_STOPF:           STOP detection flag
00449   *            @arg SMBUS_FLAG_BERR:            Bus error
00450   *            @arg SMBUS_FLAG_ARLO:            Arbitration lost
00451   *            @arg SMBUS_FLAG_OVR:             Overrun/Underrun
00452   *            @arg SMBUS_FLAG_PECERR:          PEC error in reception
00453   *            @arg SMBUS_FLAG_TIMEOUT:         Timeout or Tlow detection flag
00454   *            @arg SMBUS_FLAG_ALERT:           SMBus alert
00455   *
00456   * @retval None
00457   */
00458 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__)    ((__HANDLE__)->Instance->ICR = (__FLAG__))
00459
00460 /** @brief  Enable the specified SMBUS peripheral.
00461   * @param  __HANDLE__: specifies the SMBUS Handle.
00462   * @retval None
00463   */
00464 #define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00465
00466 /** @brief  Disable the specified SMBUS peripheral.
00467   * @param  __HANDLE__: specifies the SMBUS Handle.
00468   * @retval None
00469   */
00470 #define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00471
00472 /** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
00473   * @param  __HANDLE__: specifies the SMBUS Handle.
00474   * @retval None
00475   */
00476 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00477
00478 /**
00479   * @}
00480   */
00481
00482
00483 /* Private constants ---------------------------------------------------------*/
00484
00485 /* Private macros ------------------------------------------------------------*/
00486 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
00487   * @{
00488   */
00489
00490 #define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
00491                                                           ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
00492
00493 #define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
00494                                                           ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
00495
00496 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
00497                                                           ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
00498
00499 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
00500                                                          ((MASK) == SMBUS_OA2_MASK01)    || \
00501                                                          ((MASK) == SMBUS_OA2_MASK02)    || \
00502                                                          ((MASK) == SMBUS_OA2_MASK03)    || \
00503                                                          ((MASK) == SMBUS_OA2_MASK04)    || \
00504                                                          ((MASK) == SMBUS_OA2_MASK05)    || \
00505                                                          ((MASK) == SMBUS_OA2_MASK06)    || \
00506                                                          ((MASK) == SMBUS_OA2_MASK07))
00507
00508 #define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
00509                                                          ((CALL) == SMBUS_GENERALCALL_ENABLE))
00510
00511 #define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
00512                                                          ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
00513
00514 #define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
00515                                                           ((PEC) == SMBUS_PEC_ENABLE))
00516
00517 #define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
00518                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
00519                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
00520
00521 #define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \
00522                                                           ((MODE) == SMBUS_AUTOEND_MODE)                         || \
00523                                                           ((MODE) == SMBUS_SOFTEND_MODE)                         || \
00524                                                           ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
00525                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
00526                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
00527                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
00528
00529
00530 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
00531                                                           ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
00532                                                           ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
00533                                                           ((REQUEST) == SMBUS_NO_STARTSTOP))
00534
00535
00536 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == SMBUS_FIRST_FRAME)                        || \
00537                                                           ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
00538                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
00539                                                           ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
00540                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
00541                                                           ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
00542
00543 #define SMBUS_RESET_CR1(__HANDLE__)                     ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
00544 #define SMBUS_RESET_CR2(__HANDLE__)                     ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00545
00546 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)   (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00547                                                                   (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00548
00549 #define SMBUS_GET_ADDR_MATCH(__HANDLE__)                (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
00550 #define SMBUS_GET_DIR(__HANDLE__)                       (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
00551 #define SMBUS_GET_STOP_MODE(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00552 #define SMBUS_GET_PEC_MODE(__HANDLE__)                  ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
00553 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__)             ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
00554
00555 #define SMBUS_GET_ISR_REG(__HANDLE__)                   ((__HANDLE__)->Instance->ISR)
00556 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
00557
00558 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                 ((ADDRESS1) <= (uint32_t)0x000003FF)
00559 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                 ((ADDRESS2) <= (uint16_t)0x00FF)
00560
00561 /**
00562   * @}
00563   */
00564
00565 /* Private Functions ---------------------------------------------------------*/
00566 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
00567   * @{
00568   */
00569 /* Private functions are defined in stm32l4xx_hal_smbus.c file */
00570 /**
00571   * @}
00572   */
00573
00574 /* Exported functions --------------------------------------------------------*/
00575 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
00576   * @{
00577   */
00578
00579 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00580   * @{
00581   */
00582
00583 /* Initialization and de-initialization functions  **********************************/
00584 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
00585 HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
00586 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
00587 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
00588
00589 /**
00590   * @}
00591   */
00592
00593 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00594   * @{
00595   */
00596
00597 /* IO operation functions  *****************************************************/
00598 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
00599  * @{
00600  */
00601 /******* Blocking mode: Polling */
00602 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00603 /**
00604   * @}
00605   */
00606
00607 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
00608  * @{
00609  */
00610  /******* Non-Blocking mode: Interrupt */
00611 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00612 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00613 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
00614 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00615 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00616
00617 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00618 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00619 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00620 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00621 /**
00622   * @}
00623   */
00624
00625 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00626  * @{
00627  */
00628  /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
00629 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00630 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00631 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00632 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00633 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00634 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00635 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
00636 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00637 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
00638
00639 /**
00640   * @}
00641   */
00642
00643 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
00644   * @{
00645   */
00646
00647 /* Peripheral State and Errors functions  **************************************************/
00648 uint32_t               HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
00649 uint32_t               HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
00650
00651 /**
00652   * @}
00653   */
00654
00655 /**
00656   * @}
00657   */
00658
00659
00660
00661 /**
00662   * @}
00663   */
00664
00665 /**
00666   * @}
00667   */
00668
00669 /**
00670   * @}
00671   */
00672 #ifdef __cplusplus
00673 }
00674 #endif
00675
00676
00677 #endif /* __STM32L4xx_HAL_SMBUS_H */
00678
00679 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_spi.c Source File

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stm32l4xx_hal_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_spi.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       The SPI HAL driver can be used as follows:
00021
00022       (#) Declare a SPI_HandleTypeDef handle structure, for example:
00023           SPI_HandleTypeDef  hspi;
00024
00025       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
00026           (##) Enable the SPIx interface clock
00027           (##) SPI pins configuration
00028               (+++) Enable the clock for the SPI GPIOs
00029               (+++) Configure these SPI pins as alternate function push-pull
00030           (##) NVIC configuration if you need to use interrupt process
00031               (+++) Configure the SPIx interrupt priority
00032               (+++) Enable the NVIC SPI IRQ handle
00033           (##) DMA Configuration if you need to use DMA process
00034               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
00035               (+++) Enable the DMAx clock
00036               (+++) Configure the DMA handle parameters
00037               (+++) Configure the DMA Tx or Rx channel
00038               (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
00039               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
00040
00041       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
00042           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
00043
00044       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
00045           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00046               by calling the customized HAL_SPI_MspInit() API.
00047      [..]
00048        Circular mode restriction:
00049       (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
00050           (##) Master 2Lines RxOnly
00051           (##) Master 1Line Rx
00052       (#) The CRC feature is not managed when the DMA circular mode is enabled
00053       (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
00054           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
00055
00056   @endverbatim
00057   ******************************************************************************
00058   * @attention
00059   *
00060   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00061   *
00062   * Redistribution and use in source and binary forms, with or without modification,
00063   * are permitted provided that the following conditions are met:
00064   *   1. Redistributions of source code must retain the above copyright notice,
00065   *      this list of conditions and the following disclaimer.
00066   *   2. Redistributions in binary form must reproduce the above copyright notice,
00067   *      this list of conditions and the following disclaimer in the documentation
00068   *      and/or other materials provided with the distribution.
00069   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00070   *      may be used to endorse or promote products derived from this software
00071   *      without specific prior written permission.
00072   *
00073   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00074   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00075   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00076   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00077   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00078   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00079   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00080   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00081   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00082   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00083   *
00084   ******************************************************************************
00085   */
00086
00087 /* Includes ------------------------------------------------------------------*/
00088 #include "stm32l4xx_hal.h"
00089
00090 /** @addtogroup STM32L4xx_HAL_Driver
00091   * @{
00092   */
00093
00094 /** @defgroup SPI SPI
00095   * @brief SPI HAL module driver
00096   * @{
00097   */
00098 #ifdef HAL_SPI_MODULE_ENABLED
00099
00100 /* Private typedef -----------------------------------------------------------*/
00101 /* Private defines -----------------------------------------------------------*/
00102 /** @defgroup SPI_Private_Constants SPI Private Constants
00103   * @{
00104   */
00105 #define SPI_DEFAULT_TIMEOUT 50
00106 /**
00107   * @}
00108   */
00109
00110 /* Private macros ------------------------------------------------------------*/
00111 /* Private variables ---------------------------------------------------------*/
00112 /* Private function prototypes -----------------------------------------------*/
00113 /** @defgroup SPI_Private_Functions SPI Private Functions
00114   * @{
00115   */
00116 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00117 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00118 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00119 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
00120 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
00121 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00122 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
00123 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
00124 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
00125 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00126 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00127 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00128 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00129 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00130 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00131 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00132 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00133 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00134 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00135 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00136 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00137 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
00138 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
00139 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
00140 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
00141 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
00142 /**
00143   * @}
00144   */
00145
00146 /* Exported functions ---------------------------------------------------------*/
00147
00148 /** @defgroup SPI_Exported_Functions SPI Exported Functions
00149   * @{
00150   */
00151
00152 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00153  *  @brief    Initialization and Configuration functions
00154  *
00155 @verbatim
00156  ===============================================================================
00157               ##### Initialization and de-initialization functions #####
00158  ===============================================================================
00159     [..]  This subsection provides a set of functions allowing to initialize and
00160           de-initialize the SPIx peripheral:
00161
00162       (+) User must implement HAL_SPI_MspInit() function in which he configures
00163           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00164
00165       (+) Call the function HAL_SPI_Init() to configure the selected device with
00166           the selected configuration:
00167         (++) Mode
00168         (++) Direction
00169         (++) Data Size
00170         (++) Clock Polarity and Phase
00171         (++) NSS Management
00172         (++) BaudRate Prescaler
00173         (++) FirstBit
00174         (++) TIMode
00175         (++) CRC Calculation
00176         (++) CRC Polynomial if CRC enabled
00177         (++) CRC Length, used only with Data8 and Data16
00178         (++) FIFO reception threshold
00179
00180       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
00181           of the selected SPIx peripheral.
00182
00183 @endverbatim
00184   * @{
00185   */
00186
00187 /**
00188   * @brief  Initialize the SPI according to the specified parameters
00189   *         in the SPI_InitTypeDef and initialize the associated handle.
00190   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00191   *               the configuration information for SPI module.
00192   * @retval HAL status
00193   */
00194 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00195 {
00196   uint32_t frxth;
00197
00198   /* Check the SPI handle allocation */
00199   if(hspi == NULL)
00200   {
00201     return HAL_ERROR;
00202   }
00203
00204   /* Check the parameters */
00205   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00206   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00207   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00208   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00209   assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00210   assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00211   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00212   assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
00213   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00214   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00215   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
00216   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00217   assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00218   assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
00219
00220   if(hspi->State == HAL_SPI_STATE_RESET)
00221   {
00222     /* Allocate lock resource and initialize it */
00223     hspi->Lock = HAL_UNLOCKED;
00224
00225     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00226     HAL_SPI_MspInit(hspi);
00227   }
00228
00229   hspi->State = HAL_SPI_STATE_BUSY;
00230
00231   /* Disable the selected SPI peripheral */
00232   __HAL_SPI_DISABLE(hspi);
00233
00234   /* Align by default the rs fifo threshold on the data size */
00235   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00236   {
00237     frxth = SPI_RXFIFO_THRESHOLD_HF;
00238   }
00239   else
00240   {
00241     frxth = SPI_RXFIFO_THRESHOLD_QF;
00242   }
00243
00244   /* CRC calculation is valid only for 16Bit and 8 Bit */
00245   if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
00246   {
00247     /* CRC must be disabled */
00248     hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00249   }
00250
00251   /* Align the CRC Length on the data size */
00252   if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
00253   {
00254     /* CRC Length aligned on the data size : value set by default */
00255     if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00256     {
00257       hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
00258     }
00259     else
00260     {
00261       hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
00262     }
00263   }
00264
00265   /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
00266   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
00267   Communication speed, First bit, CRC calculation state, CRC Length */
00268   hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
00269                          hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
00270                          hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation);
00271
00272   if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
00273   {
00274     hspi->Instance->CR1|= SPI_CR1_CRCL;
00275   }
00276
00277   /* Configure : NSS management */
00278   /* Configure : Rx Fifo Threshold */
00279   hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
00280                          hspi->Init.DataSize ) | frxth;
00281
00282   /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
00283   /* Configure : CRC Polynomial */
00284   hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
00285
00286   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00287   hspi->State= HAL_SPI_STATE_READY;
00288
00289   return HAL_OK;
00290 }
00291
00292 /**
00293   * @brief  DeInitialize the SPI peripheral.
00294   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00295   *               the configuration information for SPI module.
00296   * @retval HAL status
00297   */
00298 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
00299 {
00300   /* Check the SPI handle allocation */
00301   if(hspi == NULL)
00302   {
00303     return HAL_ERROR;
00304   }
00305
00306   /* Check the parameters */
00307   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00308   hspi->State = HAL_SPI_STATE_BUSY;
00309
00310   /* Disable the SPI Peripheral Clock */
00311   __HAL_SPI_DISABLE(hspi);
00312
00313   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00314   HAL_SPI_MspDeInit(hspi);
00315
00316   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00317   hspi->State = HAL_SPI_STATE_RESET;
00318
00319   __HAL_UNLOCK(hspi);
00320
00321   return HAL_OK;
00322 }
00323
00324 /**
00325   * @brief Initialize the SPI MSP.
00326   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00327   *               the configuration information for SPI module.
00328   * @retval None
00329   */
00330 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
00331 {
00332   /* Prevent unused argument(s) compilation warning */
00333   UNUSED(hspi);
00334
00335   /* NOTE : This function should not be modified, when the callback is needed,
00336             the HAL_SPI_MspInit should be implemented in the user file
00337    */
00338 }
00339
00340 /**
00341   * @brief DeInitialize the SPI MSP.
00342   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00343   *               the configuration information for SPI module.
00344   * @retval None
00345   */
00346 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
00347 {
00348   /* Prevent unused argument(s) compilation warning */
00349   UNUSED(hspi);
00350
00351   /* NOTE : This function should not be modified, when the callback is needed,
00352             the HAL_SPI_MspDeInit should be implemented in the user file
00353    */
00354 }
00355
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
00361  *  @brief   Data transfers functions
00362  *
00363 @verbatim
00364   ==============================================================================
00365                       ##### IO operation functions #####
00366  ===============================================================================
00367  [..]
00368     This subsection provides a set of functions allowing to manage the SPI
00369     data transfers.
00370
00371     [..] The SPI supports master and slave mode :
00372
00373     (#) There are two modes of transfer:
00374        (++) Blocking mode: The communication is performed in polling mode.
00375             The HAL status of all data processing is returned by the same function
00376             after finishing transfer.
00377        (++) No-Blocking mode: The communication is performed using Interrupts
00378            or DMA, These APIs return the HAL status.
00379            The end of the data processing will be indicated through the
00380            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
00381            using DMA mode.
00382            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
00383            will be executed respectively at the end of the transmit or Receive process
00384            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
00385
00386     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
00387         exist for 1Line (simplex) and 2Lines (full duplex) modes.
00388
00389 @endverbatim
00390   * @{
00391   */
00392
00393 /**
00394   * @brief  Transmit an amount of data in blocking mode.
00395   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00396   *               the configuration information for SPI module.
00397   * @param  pData: pointer to data buffer
00398   * @param  Size: amount of data to be sent
00399   * @param  Timeout: Timeout duration
00400   * @retval HAL status
00401   */
00402 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00403 {
00404   uint32_t tickstart = HAL_GetTick();
00405   HAL_StatusTypeDef errorcode = HAL_OK;
00406
00407   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00408
00409   /* Process Locked */
00410   __HAL_LOCK(hspi);
00411
00412   if(hspi->State != HAL_SPI_STATE_READY)
00413   {
00414     errorcode = HAL_BUSY;
00415     goto error;
00416   }
00417
00418   if((pData == NULL ) || (Size == 0))
00419   {
00420     errorcode = HAL_ERROR;
00421     goto error;
00422   }
00423
00424   /* Set the transaction information */
00425   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00426   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00427   hspi->pTxBuffPtr  = pData;
00428   hspi->TxXferSize  = Size;
00429   hspi->TxXferCount = Size;
00430   hspi->pRxBuffPtr  = (uint8_t *)NULL;
00431   hspi->RxXferSize  = 0;
00432   hspi->RxXferCount = 0;
00433
00434   /* Configure communication direction : 1Line */
00435   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
00436   {
00437     SPI_1LINE_TX(hspi);
00438   }
00439
00440   /* Reset CRC Calculation */
00441   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00442   {
00443     SPI_RESET_CRC(hspi);
00444   }
00445
00446   /* Check if the SPI is already enabled */
00447   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00448   {
00449     /* Enable SPI peripheral */
00450     __HAL_SPI_ENABLE(hspi);
00451   }
00452
00453   /* Transmit data in 16 Bit mode */
00454   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00455   {
00456     /* Transmit data in 16 Bit mode */
00457     while (hspi->TxXferCount > 0)
00458     {
00459       /* Wait until TXE flag is set to send data */
00460       if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
00461       {
00462           hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00463           hspi->pTxBuffPtr += sizeof(uint16_t);
00464           hspi->TxXferCount--;
00465       }
00466       else
00467       {
00468         /* Timeout management */
00469         if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00470         {
00471           errorcode = HAL_TIMEOUT;
00472           goto error;
00473         }
00474       }
00475     }
00476   }
00477   /* Transmit data in 8 Bit mode */
00478   else
00479   {
00480     while (hspi->TxXferCount > 0)
00481     {
00482       /* Wait until TXE flag is set to send data */
00483       if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
00484       {
00485         if(hspi->TxXferCount > 1)
00486         {
00487           /* write on the data register in packing mode */
00488           hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
00489           hspi->pTxBuffPtr += sizeof(uint16_t);
00490           hspi->TxXferCount -= 2;
00491         }
00492         else
00493         {
00494           *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
00495           hspi->TxXferCount--;
00496         }
00497       }
00498       else
00499       {
00500         /* Timeout management */
00501         if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00502         {
00503           errorcode = HAL_TIMEOUT;
00504           goto error;
00505         }
00506       }
00507     }
00508   }
00509
00510   /* Enable CRC Transmission */
00511   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00512   {
00513      hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
00514   }
00515
00516   /* Check the end of the transaction */
00517   if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
00518   {
00519     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00520   }
00521
00522   /* Clear overrun flag in 2 Lines communication mode because received is not read */
00523   if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
00524   {
00525     __HAL_SPI_CLEAR_OVRFLAG(hspi);
00526   }
00527
00528   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00529   {
00530     errorcode = HAL_ERROR;
00531   }
00532
00533 error:
00534   hspi->State = HAL_SPI_STATE_READY;
00535   /* Process Unlocked */
00536   __HAL_UNLOCK(hspi);
00537   return errorcode;
00538 }
00539
00540 /**
00541   * @brief  Receive an amount of data in blocking mode.
00542   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00543   *               the configuration information for SPI module.
00544   * @param  pData: pointer to data buffer
00545   * @param  Size: amount of data to be received
00546   * @param  Timeout: Timeout duration
00547   * @retval HAL status
00548   */
00549 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00550 {
00551   __IO uint16_t tmpreg;
00552   uint32_t tickstart = HAL_GetTick();
00553   HAL_StatusTypeDef errorcode = HAL_OK;
00554
00555   if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
00556   {
00557     /* the receive process is not supported in 2Lines direction master mode */
00558     /* in this case we call the TransmitReceive process                     */
00559     /* Process Locked */
00560     return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
00561   }
00562
00563   /* Process Locked */
00564   __HAL_LOCK(hspi);
00565
00566   if(hspi->State != HAL_SPI_STATE_READY)
00567   {
00568     errorcode = HAL_BUSY;
00569     goto error;
00570   }
00571
00572   if((pData == NULL ) || (Size == 0))
00573   {
00574     errorcode = HAL_ERROR;
00575     goto error;
00576   }
00577
00578   hspi->State       = HAL_SPI_STATE_BUSY_RX;
00579   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00580   hspi->pRxBuffPtr  = pData;
00581   hspi->RxXferSize  = Size;
00582   hspi->RxXferCount = Size;
00583   hspi->pTxBuffPtr  = (uint8_t *)NULL;
00584   hspi->TxXferSize  = 0;
00585   hspi->TxXferCount = 0;
00586
00587   /* Reset CRC Calculation */
00588   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00589   {
00590     SPI_RESET_CRC(hspi);
00591     /* this is done to handle the CRCNEXT before the latest data */
00592     hspi->RxXferCount--;
00593   }
00594
00595   /* Set the Rx Fido threshold */
00596   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00597   {
00598     /* set fiforxthresold according the reception data length: 16bit */
00599     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00600   }
00601   else
00602   {
00603     /* set fiforxthresold according the reception data length: 8bit */
00604     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00605   }
00606
00607   /* Configure communication direction 1Line and enabled SPI if needed */
00608   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
00609   {
00610     SPI_1LINE_RX(hspi);
00611   }
00612
00613   /* Check if the SPI is already enabled */
00614   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00615   {
00616     /* Enable SPI peripheral */
00617     __HAL_SPI_ENABLE(hspi);
00618   }
00619
00620   if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
00621   {
00622     /* Transfer loop */
00623     while(hspi->RxXferCount > 0)
00624     {
00625       /* Check the RXNE flag */
00626       if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
00627       {
00628         /* read the received data */
00629         (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
00630         hspi->RxXferCount--;
00631       }
00632       else
00633       {
00634         /* Timeout management */
00635         if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00636         {
00637           errorcode = HAL_TIMEOUT;
00638           goto error;
00639         }
00640       }
00641     }
00642   }
00643   else
00644   {
00645     /* Transfer loop */
00646     while(hspi->RxXferCount > 0)
00647     {
00648       /* Check the RXNE flag */
00649       if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
00650       {
00651         *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
00652         hspi->pRxBuffPtr += sizeof(uint16_t);
00653         hspi->RxXferCount--;
00654       }
00655       else
00656       {
00657         /* Timeout management */
00658         if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00659         {
00660           errorcode = HAL_TIMEOUT;
00661           goto error;
00662         }
00663       }
00664     }
00665   }
00666
00667   /* Handle the CRC Transmission */
00668   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00669   {
00670     /* freeze the CRC before the latest data */
00671     hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
00672
00673     /* Read the latest data */
00674     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00675     {
00676       /* the latest data has not been received */
00677       errorcode = HAL_TIMEOUT;
00678       goto error;
00679     }
00680
00681     /* Receive last data in 16 Bit mode */
00682     if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00683     {
00684       *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
00685     }
00686     /* Receive last data in 8 Bit mode */
00687     else
00688     {
00689       *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
00690     }
00691
00692     /* Wait until TXE flag */
00693     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00694     {
00695       /* Flag Error*/
00696       hspi->ErrorCode = HAL_SPI_ERROR_CRC;
00697       errorcode = HAL_TIMEOUT;
00698       goto error;
00699     }
00700
00701     if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
00702     {
00703       tmpreg = hspi->Instance->DR;
00704       UNUSED(tmpreg); /* To avoid GCC warning */
00705     }
00706     else
00707     {
00708       tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
00709       UNUSED(tmpreg); /* To avoid GCC warning */
00710
00711       if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
00712       {
00713         if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00714         {
00715           /* Error on the CRC reception */
00716           hspi->ErrorCode = HAL_SPI_ERROR_CRC;
00717           errorcode = HAL_TIMEOUT;
00718           goto error;
00719         }
00720         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
00721         UNUSED(tmpreg); /* To avoid GCC warning */
00722       }
00723     }
00724   }
00725
00726   /* Check the end of the transaction */
00727   if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
00728   {
00729     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00730   }
00731
00732   /* Check if CRC error occurred */
00733   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
00734   {
00735     hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
00736     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
00737   }
00738
00739   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00740   {
00741     errorcode = HAL_ERROR;
00742   }
00743
00744 error :
00745   hspi->State = HAL_SPI_STATE_READY;
00746   __HAL_UNLOCK(hspi);
00747   return errorcode;
00748 }
00749
00750 /**
00751   * @brief  Transmit and Receive an amount of data in blocking mode.
00752   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00753   *               the configuration information for SPI module.
00754   * @param  pTxData: pointer to transmission data buffer
00755   * @param  pRxData: pointer to reception data buffer
00756   * @param  Size: amount of data to be sent and received
00757   * @param  Timeout: Timeout duration
00758   * @retval HAL status
00759   */
00760 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00761 {
00762 __IO uint16_t tmpreg;
00763   uint32_t tickstart = HAL_GetTick();
00764   HAL_StatusTypeDef errorcode = HAL_OK;
00765
00766   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
00767
00768   /* Process Locked */
00769   __HAL_LOCK(hspi);
00770
00771   if(hspi->State != HAL_SPI_STATE_READY)
00772   {
00773     errorcode = HAL_BUSY;
00774     goto error;
00775   }
00776
00777   if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
00778   {
00779     errorcode = HAL_ERROR;
00780     goto error;
00781   }
00782
00783   hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;
00784   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00785   hspi->pRxBuffPtr  = pRxData;
00786   hspi->RxXferCount = Size;
00787   hspi->RxXferSize  = Size;
00788   hspi->pTxBuffPtr  = pTxData;
00789   hspi->TxXferCount = Size;
00790   hspi->TxXferSize  = Size;
00791
00792   /* Reset CRC Calculation */
00793   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00794   {
00795     SPI_RESET_CRC(hspi);
00796   }
00797
00798   /* Set the Rx Fido threshold */
00799   if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
00800   {
00801     /* set fiforxthreshold according the reception data length: 16bit */
00802     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00803   }
00804   else
00805   {
00806     /* set fiforxthreshold according the reception data length: 8bit */
00807     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00808   }
00809
00810   /* Check if the SPI is already enabled */
00811   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
00812   {
00813     /* Enable SPI peripheral */
00814     __HAL_SPI_ENABLE(hspi);
00815   }
00816
00817   /* Transmit and Receive data in 16 Bit mode */
00818   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00819   {
00820     while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
00821     {
00822       /* Check TXE flag */
00823       if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
00824       {
00825         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00826         hspi->pTxBuffPtr += sizeof(uint16_t);
00827         hspi->TxXferCount--;
00828
00829         /* Enable CRC Transmission */
00830         if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
00831         {
00832           hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
00833         }
00834       }
00835
00836       /* Check RXNE flag */
00837       if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
00838       {
00839         *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
00840         hspi->pRxBuffPtr += sizeof(uint16_t);
00841         hspi->RxXferCount--;
00842       }
00843       if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
00844       {
00845         errorcode = HAL_TIMEOUT;
00846         goto error;
00847       }
00848     }
00849   }
00850   /* Transmit and Receive data in 8 Bit mode */
00851   else
00852   {
00853     while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
00854     {
00855       /* check TXE flag */
00856       if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
00857       {
00858         if(hspi->TxXferCount > 1)
00859         {
00860           hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
00861           hspi->pTxBuffPtr += sizeof(uint16_t);
00862           hspi->TxXferCount -= 2;
00863         }
00864         else
00865         {
00866           *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
00867           hspi->TxXferCount--;
00868         }
00869
00870         /* Enable CRC Transmission */
00871         if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
00872         {
00873           hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
00874         }
00875       }
00876
00877       /* Wait until RXNE flag is reset */
00878       if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
00879       {
00880         if(hspi->RxXferCount > 1)
00881         {
00882           *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
00883           hspi->pRxBuffPtr += sizeof(uint16_t);
00884           hspi->RxXferCount -= 2;
00885           if(hspi->RxXferCount <= 1)
00886           {
00887             /* set fiforxthresold before to switch on 8 bit data size */
00888             SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
00889           }
00890         }
00891         else
00892         {
00893           (*hspi->pRxBuffPtr++) =  *(__IO uint8_t *)&hspi->Instance->DR;
00894           hspi->RxXferCount--;
00895         }
00896       }
00897       if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
00898       {
00899         errorcode = HAL_TIMEOUT;
00900         goto error;
00901       }
00902     }
00903   }
00904
00905   /* Read CRC from DR to close CRC calculation process */
00906   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00907   {
00908     /* Wait until TXE flag */
00909     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00910     {
00911       /* Error on the CRC reception */
00912       hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
00913       errorcode = HAL_TIMEOUT;
00914       goto error;
00915     }
00916
00917     if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
00918     {
00919       tmpreg = hspi->Instance->DR;
00920       UNUSED(tmpreg); /* To avoid GCC warning */
00921     }
00922     else
00923     {
00924       tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
00925       UNUSED(tmpreg); /* To avoid GCC warning */
00926
00927       if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
00928       {
00929         if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
00930         {
00931           /* Error on the CRC reception */
00932           hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
00933           errorcode = HAL_TIMEOUT;
00934           goto error;
00935         }
00936         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
00937         UNUSED(tmpreg); /* To avoid GCC warning */
00938       }
00939     }
00940   }
00941
00942   /* Check if CRC error occurred */
00943   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
00944   {
00945     hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
00946     /* Clear CRC Flag */
00947     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
00948
00949     errorcode = HAL_ERROR;
00950   }
00951
00952   /* Check the end of the transaction */
00953   if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
00954   {
00955     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00956   }
00957
00958   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00959   {
00960     errorcode = HAL_ERROR;
00961   }
00962
00963 error :
00964   hspi->State = HAL_SPI_STATE_READY;
00965   __HAL_UNLOCK(hspi);
00966   return errorcode;
00967 }
00968
00969 /**
00970   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
00971   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00972   *               the configuration information for SPI module.
00973   * @param  pData: pointer to data buffer
00974   * @param  Size: amount of data to be sent
00975   * @retval HAL status
00976   */
00977 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
00978 {
00979   HAL_StatusTypeDef errorcode = HAL_OK;
00980   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00981
00982   /* Process Locked */
00983   __HAL_LOCK(hspi);
00984
00985   if((pData == NULL) || (Size == 0))
00986   {
00987     errorcode = HAL_ERROR;
00988     goto error;
00989   }
00990
00991   if(hspi->State != HAL_SPI_STATE_READY)
00992   {
00993     errorcode = HAL_BUSY;
00994     goto error;
00995   }
00996
00997   /* prepare the transfer */
00998   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00999   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01000   hspi->pTxBuffPtr  = pData;
01001   hspi->TxXferSize  = Size;
01002   hspi->TxXferCount = Size;
01003   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01004   hspi->RxXferSize  = 0;
01005   hspi->RxXferCount = 0;
01006   hspi->RxISR = NULL;
01007
01008   /* Set the function for IT treatment */
01009   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01010   {
01011     hspi->TxISR = SPI_TxISR_16BIT;
01012   }
01013   else
01014   {
01015     hspi->TxISR = SPI_TxISR_8BIT;
01016   }
01017
01018   /* Configure communication direction : 1Line */
01019   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01020   {
01021     SPI_1LINE_TX(hspi);
01022   }
01023
01024   /* Reset CRC Calculation */
01025   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01026   {
01027     SPI_RESET_CRC(hspi);
01028   }
01029
01030   /* Enable TXE and ERR interrupt */
01031   __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
01032
01033
01034   /* Check if the SPI is already enabled */
01035   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01036   {
01037     /* Enable SPI peripheral */
01038     __HAL_SPI_ENABLE(hspi);
01039   }
01040
01041 error :
01042   __HAL_UNLOCK(hspi);
01043   return errorcode;
01044 }
01045
01046 /**
01047   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01048   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01049   *               the configuration information for SPI module.
01050   * @param  pData: pointer to data buffer
01051   * @param  Size: amount of data to be sent
01052   * @retval HAL status
01053   */
01054 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01055 {
01056   HAL_StatusTypeDef errorcode = HAL_OK;
01057
01058   /* Process Locked */
01059   __HAL_LOCK(hspi);
01060
01061   if(hspi->State != HAL_SPI_STATE_READY)
01062   {
01063     errorcode = HAL_BUSY;
01064     goto error;
01065   }
01066   if((pData == NULL) || (Size == 0))
01067   {
01068     errorcode = HAL_ERROR;
01069     goto error;
01070   }
01071
01072   /* Configure communication */
01073   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01074   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01075   hspi->pRxBuffPtr  = pData;
01076   hspi->RxXferSize  = Size;
01077   hspi->RxXferCount = Size;
01078   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01079   hspi->TxXferSize  = 0;
01080   hspi->TxXferCount = 0;
01081
01082   if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
01083   {
01084     /* Process Unlocked */
01085     __HAL_UNLOCK(hspi);
01086     /* the receive process is not supported in 2Lines direction master mode */
01087     /* in this we call the TransmitReceive process          */
01088     return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
01089   }
01090
01091   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01092   {
01093     hspi->CRCSize = 1;
01094     if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01095     {
01096       hspi->CRCSize = 2;
01097     }
01098   }
01099   else
01100   {
01101     hspi->CRCSize = 0;
01102   }
01103
01104   hspi->TxISR = NULL;
01105   /* check the data size to adapt Rx threshold and the set the function for IT treatment */
01106   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01107   {
01108     /* set fiforxthresold according the reception data length: 16 bit */
01109     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01110     hspi->RxISR = SPI_RxISR_16BIT;
01111   }
01112   else
01113   {
01114     /* set fiforxthresold according the reception data length: 8 bit */
01115     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01116     hspi->RxISR = SPI_RxISR_8BIT;
01117   }
01118
01119   /* Configure communication direction : 1Line */
01120   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01121   {
01122     SPI_1LINE_RX(hspi);
01123   }
01124
01125   /* Reset CRC Calculation */
01126   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01127   {
01128     SPI_RESET_CRC(hspi);
01129   }
01130
01131   /* Enable TXE and ERR interrupt */
01132   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
01133
01134   /* Check if the SPI is already enabled */
01135   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01136   {
01137     /* Enable SPI peripheral */
01138     __HAL_SPI_ENABLE(hspi);
01139   }
01140
01141 error :
01142   /* Process Unlocked */
01143   __HAL_UNLOCK(hspi);
01144   return errorcode;
01145 }
01146
01147 /**
01148   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
01149   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01150   *               the configuration information for SPI module.
01151   * @param  pTxData: pointer to transmission data buffer
01152   * @param  pRxData: pointer to reception data buffer
01153   * @param  Size: amount of data to be sent and received
01154   * @retval HAL status
01155   */
01156 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01157 {
01158   HAL_StatusTypeDef errorcode = HAL_OK;
01159   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01160
01161   /* Process locked */
01162   __HAL_LOCK(hspi);
01163
01164   if(!((hspi->State == HAL_SPI_STATE_READY) || \
01165     ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
01166   {
01167     errorcode = HAL_BUSY;
01168     goto error;
01169   }
01170
01171   if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
01172   {
01173     errorcode = HAL_ERROR;
01174     goto error;
01175   }
01176
01177   hspi->CRCSize = 0;
01178   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01179   {
01180     hspi->CRCSize = 1;
01181     if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01182     {
01183       hspi->CRCSize = 2;
01184     }
01185   }
01186
01187   if(hspi->State != HAL_SPI_STATE_BUSY_RX)
01188   {
01189     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01190   }
01191
01192   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01193   hspi->pTxBuffPtr  = pTxData;
01194   hspi->TxXferSize  = Size;
01195   hspi->TxXferCount = Size;
01196   hspi->pRxBuffPtr  = pRxData;
01197   hspi->RxXferSize  = Size;
01198   hspi->RxXferCount = Size;
01199
01200   /* Set the function for IT treatment */
01201   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01202   {
01203     hspi->RxISR = SPI_2linesRxISR_16BIT;
01204     hspi->TxISR = SPI_2linesTxISR_16BIT;
01205   }
01206   else
01207   {
01208     hspi->RxISR = SPI_2linesRxISR_8BIT;
01209     hspi->TxISR = SPI_2linesTxISR_8BIT;
01210   }
01211
01212   /* Reset CRC Calculation */
01213   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01214   {
01215     SPI_RESET_CRC(hspi);
01216   }
01217
01218   /* check if packing mode is enabled and if there is more than 2 data to receive */
01219   if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
01220   {
01221     /* set fiforxthresold according the reception data length: 16 bit */
01222     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01223   }
01224   else
01225   {
01226     /* set fiforxthresold according the reception data length: 8 bit */
01227     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01228   }
01229
01230   /* Enable TXE, RXNE and ERR interrupt */
01231   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
01232
01233   /* Check if the SPI is already enabled */
01234   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01235   {
01236     /* Enable SPI peripheral */
01237     __HAL_SPI_ENABLE(hspi);
01238   }
01239
01240 error :
01241   /* Process Unlocked */
01242   __HAL_UNLOCK(hspi);
01243   return errorcode;
01244 }
01245
01246 /**
01247   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01248   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01249   *               the configuration information for SPI module.
01250   * @param  pData: pointer to data buffer
01251   * @param  Size: amount of data to be sent
01252   * @retval HAL status
01253   */
01254 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01255 {
01256   HAL_StatusTypeDef errorcode = HAL_OK;
01257   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01258
01259   /* Process Locked */
01260   __HAL_LOCK(hspi);
01261
01262   if(hspi->State != HAL_SPI_STATE_READY)
01263   {
01264     errorcode = HAL_BUSY;
01265     goto error;
01266   }
01267
01268   if((pData == NULL) || (Size == 0))
01269   {
01270     errorcode = HAL_ERROR;
01271     goto error;
01272   }
01273
01274   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01275   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01276   hspi->pTxBuffPtr  = pData;
01277   hspi->TxXferSize  = Size;
01278   hspi->TxXferCount = Size;
01279   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01280   hspi->RxXferSize  = 0;
01281   hspi->RxXferCount = 0;
01282
01283   /* Configure communication direction : 1Line */
01284   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01285   {
01286     SPI_1LINE_TX(hspi);
01287   }
01288
01289   /* Reset CRC Calculation */
01290   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01291   {
01292     SPI_RESET_CRC(hspi);
01293   }
01294
01295   /* Set the SPI TxDMA Half transfer complete callback */
01296   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
01297
01298   /* Set the SPI TxDMA transfer complete callback */
01299   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
01300
01301   /* Set the DMA error callback */
01302   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01303
01304   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01305   /* packing mode is enabled only if the DMA setting is HALWORD */
01306   if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
01307   {
01308     /* Check the even/odd of the data size + crc if enabled */
01309     if((hspi->TxXferCount & 0x1) == 0)
01310     {
01311       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01312       hspi->TxXferCount = (hspi->TxXferCount >> 1);
01313     }
01314     else
01315     {
01316       SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01317       hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
01318     }
01319   }
01320
01321   /* Enable the Tx DMA channel */
01322   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
01323
01324   /* Check if the SPI is already enabled */
01325   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01326   {
01327     /* Enable SPI peripheral */
01328     __HAL_SPI_ENABLE(hspi);
01329   }
01330
01331   /* Enable Tx DMA Request */
01332   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01333
01334 error :
01335   /* Process Unlocked */
01336   __HAL_UNLOCK(hspi);
01337   return errorcode;
01338 }
01339
01340 /**
01341   * @brief  Receive an amount of data in non-blocking mode with DMA.
01342   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01343   *               the configuration information for SPI module.
01344   * @param  pData: pointer to data buffer
01345   * @note  When the CRC feature is enabled the pData Length must be Size + 1.
01346   * @param  Size: amount of data to be sent
01347   * @retval HAL status
01348   */
01349 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01350 {
01351   HAL_StatusTypeDef errorcode = HAL_OK;
01352
01353   /* Process Locked */
01354   __HAL_LOCK(hspi);
01355
01356   if(hspi->State != HAL_SPI_STATE_READY)
01357   {
01358     errorcode = HAL_BUSY;
01359     goto error;
01360   }
01361
01362   if((pData == NULL) || (Size == 0))
01363   {
01364     errorcode = HAL_ERROR;
01365     goto error;
01366   }
01367
01368   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01369   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01370   hspi->pRxBuffPtr  = pData;
01371   hspi->RxXferSize  = Size;
01372   hspi->RxXferCount = Size;
01373   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01374   hspi->TxXferSize  = 0;
01375   hspi->TxXferCount = 0;
01376
01377   if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
01378   {
01379     /* Process Unlocked */
01380     __HAL_UNLOCK(hspi);
01381     /* the receive process is not supported in 2Lines direction master mode */
01382     /* in this case we call the TransmitReceive process                     */
01383     return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
01384   }
01385
01386   /* Configure communication direction : 1Line */
01387   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01388   {
01389     SPI_1LINE_RX(hspi);
01390   }
01391
01392   /* Reset CRC Calculation */
01393   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01394   {
01395     SPI_RESET_CRC(hspi);
01396   }
01397
01398   /* packing mode management is enabled by the DMA settings */
01399   if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
01400   {
01401     /* Restriction the DMA data received is not allowed in this mode */
01402     errorcode = HAL_ERROR;
01403     goto error;
01404   }
01405
01406   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01407   if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01408   {
01409     /* set fiforxthresold according the reception data length: 16bit */
01410     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01411   }
01412   else
01413   {
01414     /* set fiforxthresold according the reception data length: 8bit */
01415     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01416   }
01417
01418   /* Set the SPI RxDMA Half transfer complete callback */
01419   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01420
01421   /* Set the SPI Rx DMA transfer complete callback */
01422   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
01423
01424   /* Set the DMA error callback */
01425   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01426
01427   /* Enable Rx DMA Request */
01428   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
01429
01430   /* Enable the Rx DMA channel */
01431   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
01432
01433   /* Check if the SPI is already enabled */
01434   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01435   {
01436     /* Enable SPI peripheral */
01437     __HAL_SPI_ENABLE(hspi);
01438   }
01439
01440 error:
01441   /* Process Unlocked */
01442   __HAL_UNLOCK(hspi);
01443   return errorcode;
01444 }
01445
01446 /**
01447   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
01448   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01449   *               the configuration information for SPI module.
01450   * @param  pTxData: pointer to transmission data buffer
01451   * @param  pRxData: pointer to reception data buffer
01452   * @note  When the CRC feature is enabled the pRxData Length must be Size + 1
01453   * @param  Size: amount of data to be sent
01454   * @retval HAL status
01455   */
01456 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01457 {
01458   HAL_StatusTypeDef errorcode = HAL_OK;
01459   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01460
01461   /* Process locked */
01462   __HAL_LOCK(hspi);
01463
01464   if(!((hspi->State == HAL_SPI_STATE_READY) ||
01465       ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
01466   {
01467     errorcode = HAL_BUSY;
01468     goto error;
01469   }
01470
01471   if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
01472   {
01473     errorcode = HAL_ERROR;
01474     goto error;
01475   }
01476
01477   /* check if the transmit Receive function is not called by a receive master */
01478   if(hspi->State != HAL_SPI_STATE_BUSY_RX)
01479   {
01480     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01481   }
01482
01483   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01484   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01485   hspi->TxXferSize  = Size;
01486   hspi->TxXferCount = Size;
01487   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01488   hspi->RxXferSize  = Size;
01489   hspi->RxXferCount = Size;
01490
01491   /* Reset CRC Calculation + increase the rxsize */
01492   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01493   {
01494     SPI_RESET_CRC(hspi);
01495   }
01496
01497   /* Reset the threshold bit */
01498   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
01499
01500   /* the packing mode management is enabled by the DMA settings according the spi data size */
01501   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01502   {
01503     /* set fiforxthreshold according the reception data length: 16bit */
01504     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01505   }
01506   else
01507   {
01508     /* set fiforxthresold according the reception data length: 8bit */
01509     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01510
01511     if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
01512     {
01513       if((hspi->TxXferSize & 0x1) == 0x0)
01514       {
01515         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01516         hspi->TxXferCount = hspi->TxXferCount >> 1;
01517       }
01518       else
01519       {
01520         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01521         hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
01522       }
01523     }
01524
01525     if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
01526     {
01527       /* set fiforxthresold according the reception data length: 16bit */
01528       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01529
01530       if((hspi->RxXferCount & 0x1) == 0x0 )
01531       {
01532         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01533         hspi->RxXferCount = hspi->RxXferCount >> 1;
01534       }
01535       else
01536       {
01537         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01538         hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
01539       }
01540     }
01541   }
01542
01543   /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
01544      reception request (RXNE) */
01545   if(hspi->State == HAL_SPI_STATE_BUSY_RX)
01546   {
01547     /* Set the SPI Rx DMA Half transfer complete callback */
01548     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01549     hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
01550   }
01551   else
01552   {
01553     /* Set the SPI Rx DMA Half transfer complete callback */
01554     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
01555     hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
01556   }
01557
01558   /* Set the DMA error callback */
01559   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01560
01561   /* Enable Rx DMA Request */
01562   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
01563
01564   /* Enable the Rx DMA channel */
01565   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
01566
01567   /* Set the SPI DMA Tx Abort Complete callback to Null : Tx DMA will be aborted
01568      at end of Rx transfer (when Rx DMA Transfer Complete callback will be executed) */
01569   hspi->hdmatx->XferAbortCallback    = NULL;
01570   hspi->hdmatx->XferHalfCpltCallback = NULL;
01571   hspi->hdmatx->XferCpltCallback     = NULL;
01572   hspi->hdmatx->XferErrorCallback    = NULL;
01573
01574   /* Enable the Tx DMA channel */
01575   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
01576
01577   /* Check if the SPI is already enabled */
01578   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01579   {
01580     /* Enable SPI peripheral */
01581     __HAL_SPI_ENABLE(hspi);
01582   }
01583
01584   /* Enable Tx DMA Request */
01585   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01586
01587 error :
01588   /* Process Unlocked */
01589   __HAL_UNLOCK(hspi);
01590   return errorcode;
01591 }
01592
01593 /**
01594   * @brief Pause the DMA Transfer.
01595   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01596   *               the configuration information for the specified SPI module.
01597   * @retval HAL status
01598   */
01599 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
01600 {
01601   /* Process Locked */
01602   __HAL_LOCK(hspi);
01603
01604   /* Disable the SPI DMA Tx & Rx requests */
01605   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01606
01607   /* Process Unlocked */
01608   __HAL_UNLOCK(hspi);
01609
01610   return HAL_OK;
01611 }
01612
01613 /**
01614   * @brief Resume the DMA Transfer.
01615   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01616   *               the configuration information for the specified SPI module.
01617   * @retval HAL status
01618   */
01619 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
01620 {
01621   /* Process Locked */
01622   __HAL_LOCK(hspi);
01623
01624   /* Enable the SPI DMA Tx & Rx requests */
01625   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01626
01627   /* Process Unlocked */
01628   __HAL_UNLOCK(hspi);
01629
01630   return HAL_OK;
01631 }
01632
01633 /**
01634   * @brief Stop the DMA Transfer.
01635   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01636   *               the configuration information for the specified SPI module.
01637   * @retval HAL status
01638   */
01639 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
01640 {
01641   /* The Lock is not implemented on this API to allow the user application
01642      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
01643      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
01644      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
01645      */
01646
01647   /* Abort the SPI DMA tx channel */
01648   if(hspi->hdmatx != NULL)
01649   {
01650     HAL_DMA_Abort(hspi->hdmatx);
01651   }
01652   /* Abort the SPI DMA rx channel */
01653   if(hspi->hdmarx != NULL)
01654   {
01655     HAL_DMA_Abort(hspi->hdmarx);
01656   }
01657
01658   /* Disable the SPI DMA Tx & Rx requests */
01659   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01660   hspi->State = HAL_SPI_STATE_READY;
01661   return HAL_OK;
01662 }
01663
01664 /**
01665   * @brief  Handle SPI interrupt request.
01666   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01667   *               the configuration information for the specified SPI module.
01668   * @retval None
01669   */
01670 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
01671 {
01672   uint32_t itsource = hspi->Instance->CR2;
01673   uint32_t itflag   = hspi->Instance->SR;
01674
01675   /* SPI in mode Receiver ----------------------------------------------------*/
01676   if(((itflag & SPI_FLAG_OVR) == RESET) &&
01677      ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
01678   {
01679     hspi->RxISR(hspi);
01680     return;
01681   }
01682
01683   /* SPI in mode Transmitter ---------------------------------------------------*/
01684   if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
01685   {
01686     hspi->TxISR(hspi);
01687     return;
01688   }
01689
01690   /* SPI in Error Treatment ---------------------------------------------------*/
01691   if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
01692   {
01693     /* SPI Overrun error interrupt occurred -------------------------------------*/
01694     if((itflag & SPI_FLAG_OVR) != RESET)
01695     {
01696       if(hspi->State != HAL_SPI_STATE_BUSY_TX)
01697       {
01698         hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
01699         __HAL_SPI_CLEAR_OVRFLAG(hspi);
01700       }
01701       else
01702       {
01703         return;
01704       }
01705     }
01706
01707     /* SPI Mode Fault error interrupt occurred -------------------------------------*/
01708     if((itflag & SPI_FLAG_MODF) != RESET)
01709     {
01710       hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
01711       __HAL_SPI_CLEAR_MODFFLAG(hspi);
01712     }
01713
01714     /* SPI Frame error interrupt occurred ----------------------------------------*/
01715     if((itflag & SPI_FLAG_FRE) != RESET)
01716     {
01717       hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
01718       __HAL_SPI_CLEAR_FREFLAG(hspi);
01719     }
01720
01721     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
01722     hspi->State = HAL_SPI_STATE_READY;
01723     HAL_SPI_ErrorCallback(hspi);
01724     return;
01725   }
01726 }
01727
01728 /**
01729   * @brief Tx Transfer completed callback.
01730   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01731   *               the configuration information for SPI module.
01732   * @retval None
01733   */
01734 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
01735 {
01736   /* Prevent unused argument(s) compilation warning */
01737   UNUSED(hspi);
01738
01739   /* NOTE : This function should not be modified, when the callback is needed,
01740             the HAL_SPI_TxCpltCallback should be implemented in the user file
01741    */
01742 }
01743
01744 /**
01745   * @brief Rx Transfer completed callback.
01746   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01747   *               the configuration information for SPI module.
01748   * @retval None
01749   */
01750 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
01751 {
01752   /* Prevent unused argument(s) compilation warning */
01753   UNUSED(hspi);
01754
01755   /* NOTE : This function should not be modified, when the callback is needed,
01756             the HAL_SPI_RxCpltCallback should be implemented in the user file
01757    */
01758 }
01759
01760 /**
01761   * @brief Tx and Rx Transfer completed callback.
01762   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01763   *               the configuration information for SPI module.
01764   * @retval None
01765   */
01766 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
01767 {
01768   /* Prevent unused argument(s) compilation warning */
01769   UNUSED(hspi);
01770
01771   /* NOTE : This function should not be modified, when the callback is needed,
01772             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
01773    */
01774 }
01775
01776 /**
01777   * @brief Tx Half Transfer completed callback.
01778   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01779   *               the configuration information for SPI module.
01780   * @retval None
01781   */
01782 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
01783 {
01784   /* Prevent unused argument(s) compilation warning */
01785   UNUSED(hspi);
01786
01787   /* NOTE : This function should not be modified, when the callback is needed,
01788             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
01789    */
01790 }
01791
01792 /**
01793   * @brief Rx Half Transfer completed callback.
01794   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01795   *               the configuration information for SPI module.
01796   * @retval None
01797   */
01798 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
01799 {
01800   /* Prevent unused argument(s) compilation warning */
01801   UNUSED(hspi);
01802
01803   /* NOTE : This function should not be modified, when the callback is needed,
01804             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
01805    */
01806 }
01807
01808 /**
01809   * @brief Tx and Rx Half Transfer callback.
01810   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01811   *               the configuration information for SPI module.
01812   * @retval None
01813   */
01814 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
01815 {
01816   /* Prevent unused argument(s) compilation warning */
01817   UNUSED(hspi);
01818
01819   /* NOTE : This function should not be modified, when the callback is needed,
01820             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
01821    */
01822 }
01823
01824 /**
01825   * @brief SPI error callback.
01826   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01827   *               the configuration information for SPI module.
01828   * @retval None
01829   */
01830 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
01831 {
01832   /* Prevent unused argument(s) compilation warning */
01833   UNUSED(hspi);
01834
01835   /* NOTE : This function should not be modified, when the callback is needed,
01836             the HAL_SPI_ErrorCallback should be implemented in the user file
01837    */
01838   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
01839             and user can use HAL_SPI_GetError() API to check the latest error occurred
01840    */
01841 }
01842
01843 /**
01844   * @}
01845   */
01846
01847 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
01848   *  @brief   SPI control functions
01849   *
01850 @verbatim
01851  ===============================================================================
01852                       ##### Peripheral State and Errors functions #####
01853  ===============================================================================
01854     [..]
01855     This subsection provides a set of functions allowing to control the SPI.
01856      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
01857      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
01858 @endverbatim
01859   * @{
01860   */
01861
01862 /**
01863   * @brief  Return the SPI handle state.
01864   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01865   *               the configuration information for SPI module.
01866   * @retval SPI state
01867   */
01868 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
01869 {
01870   /* Return SPI handle state */
01871   return hspi->State;
01872 }
01873
01874 /**
01875   * @brief  Return the SPI error code.
01876   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01877   *               the configuration information for SPI module.
01878   * @retval SPI error code in bitmap format
01879   */
01880 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
01881 {
01882   return hspi->ErrorCode;
01883 }
01884
01885 /**
01886   * @}
01887   */
01888
01889
01890 /**
01891   * @}
01892   */
01893
01894 /** @addtogroup SPI_Private_Functions
01895  *  @brief   Private functions
01896   * @{
01897   */
01898
01899 /**
01900   * @brief DMA SPI transmit process complete callback.
01901   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01902   *               the configuration information for the specified DMA module.
01903   * @retval None
01904   */
01905 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01906 {
01907   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01908
01909   if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
01910   {
01911     /* Disable Tx DMA Request */
01912     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01913
01914     /* Check the end of the transaction */
01915     if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
01916     {
01917       hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
01918     }
01919
01920     /* Clear overrun flag in 2 Lines communication mode because received data is not read */
01921     if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
01922     {
01923       __HAL_SPI_CLEAR_OVRFLAG(hspi);
01924     }
01925
01926     hspi->TxXferCount = 0;
01927     hspi->State = HAL_SPI_STATE_READY;
01928
01929     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01930     {
01931       HAL_SPI_ErrorCallback(hspi);
01932       return;
01933     }
01934   }
01935   HAL_SPI_TxCpltCallback(hspi);
01936 }
01937
01938 /**
01939   * @brief DMA SPI receive process complete callback.
01940   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01941   *               the configuration information for the specified DMA module.
01942   * @retval None
01943   */
01944 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01945 {
01946   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01947
01948   if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
01949   {
01950     __IO uint16_t tmpreg;
01951
01952     /* CRC handling */
01953     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01954     {
01955       /* Wait until TXE flag */
01956       if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
01957       {
01958         /* Error on the CRC reception */
01959         hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
01960       }
01961       if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01962       {
01963         tmpreg = hspi->Instance->DR;
01964         UNUSED(tmpreg); /* To avoid GCC warning */
01965       }
01966       else
01967       {
01968         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
01969         UNUSED(tmpreg); /* To avoid GCC warning */
01970
01971         if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
01972         {
01973           if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
01974           {
01975             /* Error on the CRC reception */
01976             hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
01977           }
01978           tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
01979           UNUSED(tmpreg); /* To avoid GCC warning */
01980         }
01981       }
01982     }
01983
01984     /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
01985     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01986
01987     /* Check the end of the transaction */
01988     if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
01989     {
01990       hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
01991     }
01992
01993     hspi->RxXferCount = 0;
01994     hspi->State = HAL_SPI_STATE_READY;
01995
01996     /* Check if CRC error occurred */
01997     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
01998     {
01999       hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
02000       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02001     }
02002
02003     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02004     {
02005       HAL_SPI_ErrorCallback(hspi);
02006       return;
02007     }
02008   }
02009   HAL_SPI_RxCpltCallback(hspi);
02010 }
02011
02012 /**
02013   * @brief DMA SPI transmit receive process complete callback.
02014   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
02015   *               the configuration information for the specified DMA module.
02016   * @retval None
02017   */
02018 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02019 {
02020   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02021
02022   if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
02023   {
02024     __IO int16_t tmpreg;
02025     /* CRC handling */
02026     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02027     {
02028       if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
02029       {
02030         if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
02031         {
02032           /* Error on the CRC reception */
02033           hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
02034         }
02035         tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
02036         UNUSED(tmpreg); /* To avoid GCC warning */
02037       }
02038       else
02039       {
02040         if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
02041         {
02042           /* Error on the CRC reception */
02043           hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
02044         }
02045         tmpreg = hspi->Instance->DR;
02046         UNUSED(tmpreg); /* To avoid GCC warning */
02047       }
02048     }
02049
02050     /* Check the end of the transaction */
02051     if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
02052     {
02053       hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
02054     }
02055
02056     /* Disable Rx/Tx DMA Request */
02057     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02058
02059     hspi->TxXferCount = 0;
02060     hspi->RxXferCount = 0;
02061     hspi->State = HAL_SPI_STATE_READY;
02062
02063     /* Check if CRC error occurred */
02064     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
02065     {
02066       hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
02067       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02068     }
02069
02070     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02071     {
02072       HAL_SPI_ErrorCallback(hspi);
02073       return;
02074     }
02075   }
02076   HAL_SPI_TxRxCpltCallback(hspi);
02077 }
02078
02079 /**
02080   * @brief DMA SPI half transmit process complete callback.
02081   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
02082   *               the configuration information for the specified DMA module.
02083   * @retval None
02084   */
02085 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
02086 {
02087   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02088
02089   HAL_SPI_TxHalfCpltCallback(hspi);
02090 }
02091
02092 /**
02093   * @brief DMA SPI half receive process complete callback.
02094   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02095   *               the configuration information for the specified DMA module.
02096   * @retval None
02097   */
02098 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
02099 {
02100   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02101
02102   HAL_SPI_RxHalfCpltCallback(hspi);
02103 }
02104
02105 /**
02106   * @brief DMA SPI half transmit receive process complete callback.
02107   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
02108   *               the configuration information for the specified DMA module.
02109   * @retval None
02110   */
02111 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02112 {
02113   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02114
02115   HAL_SPI_TxRxHalfCpltCallback(hspi);
02116 }
02117
02118 /**
02119   * @brief DMA SPI communication error callback.
02120   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
02121   *               the configuration information for the specified DMA module.
02122   * @retval None
02123   */
02124 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
02125 {
02126   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02127
02128   /* Stop the disable DMA transfer on SPI side */
02129   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02130
02131   hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
02132   hspi->State = HAL_SPI_STATE_READY;
02133   HAL_SPI_ErrorCallback(hspi);
02134 }
02135
02136 /**
02137   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
02138   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02139   *               the configuration information for SPI module.
02140   * @retval None
02141   */
02142 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02143 {
02144   /* Receive data in packing mode */
02145   if(hspi->RxXferCount > 1)
02146   {
02147     *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
02148     hspi->pRxBuffPtr += sizeof(uint16_t);
02149     hspi->RxXferCount -= 2;
02150     if(hspi->RxXferCount == 1)
02151     {
02152       /* set fiforxthresold according the reception data length: 8bit */
02153       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02154     }
02155   }
02156   /* Receive data in 8 Bit mode */
02157   else
02158   {
02159     *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
02160     hspi->RxXferCount--;
02161   }
02162
02163   /* check end of the reception */
02164   if(hspi->RxXferCount == 0)
02165   {
02166     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02167     {
02168       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02169       hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
02170       return;
02171     }
02172
02173     /* Disable RXNE interrupt */
02174     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02175
02176     if(hspi->TxXferCount == 0)
02177     {
02178       SPI_CloseRxTx_ISR(hspi);
02179     }
02180   }
02181 }
02182
02183 /**
02184   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
02185   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02186   *               the configuration information for SPI module.
02187   * @retval None
02188   */
02189 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
02190 {
02191   __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
02192   UNUSED(tmpreg); /* To avoid GCC warning */
02193
02194   hspi->CRCSize--;
02195
02196   /* check end of the reception */
02197   if(hspi->CRCSize == 0)
02198   {
02199     /* Disable RXNE interrupt */
02200     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02201
02202     if(hspi->TxXferCount == 0)
02203     {
02204       SPI_CloseRxTx_ISR(hspi);
02205     }
02206   }
02207 }
02208
02209 /**
02210   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
02211   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02212   *               the configuration information for SPI module.
02213   * @retval None
02214   */
02215 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02216 {
02217   /* Transmit data in packing Bit mode */
02218   if(hspi->TxXferCount >= 2)
02219   {
02220     hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
02221     hspi->pTxBuffPtr += sizeof(uint16_t);
02222     hspi->TxXferCount -= 2;
02223   }
02224   /* Transmit data in 8 Bit mode */
02225   else
02226   {
02227     *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
02228     hspi->TxXferCount--;
02229   }
02230
02231   /* check the end of the transmission */
02232   if(hspi->TxXferCount == 0)
02233   {
02234     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02235     {
02236       hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02237     }
02238     /* Disable TXE interrupt */
02239     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
02240
02241     if(hspi->RxXferCount == 0)
02242     {
02243       SPI_CloseRxTx_ISR(hspi);
02244     }
02245   }
02246 }
02247
02248 /**
02249   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
02250   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02251   *               the configuration information for SPI module.
02252   * @retval None
02253   */
02254 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02255 {
02256   /* Receive data in 16 Bit mode */
02257   *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
02258   hspi->pRxBuffPtr += sizeof(uint16_t);
02259   hspi->RxXferCount--;
02260
02261   if(hspi->RxXferCount == 0)
02262   {
02263     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02264     {
02265       hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
02266       return;
02267     }
02268
02269     /* Disable RXNE interrupt */
02270     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02271
02272     if(hspi->TxXferCount == 0)
02273     {
02274       SPI_CloseRxTx_ISR(hspi);
02275     }
02276   }
02277 }
02278
02279 /**
02280   * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
02281   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02282   *               the configuration information for SPI module.
02283   * @retval None
02284   */
02285 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
02286 {
02287   /* Receive data in 16 Bit mode */
02288   __IO uint16_t tmpreg = hspi->Instance->DR;
02289   UNUSED(tmpreg); /* To avoid GCC warning */
02290
02291   /* Disable RXNE interrupt */
02292   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02293
02294   SPI_CloseRxTx_ISR(hspi);
02295 }
02296
02297 /**
02298   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
02299   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02300   *               the configuration information for SPI module.
02301   * @retval None
02302   */
02303 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02304 {
02305   /* Transmit data in 16 Bit mode */
02306   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
02307   hspi->pTxBuffPtr += sizeof(uint16_t);
02308   hspi->TxXferCount--;
02309
02310   /* Enable CRC Transmission */
02311   if(hspi->TxXferCount == 0)
02312   {
02313     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02314     {
02315       hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02316     }
02317     /* Disable TXE interrupt */
02318     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
02319
02320     if(hspi->RxXferCount == 0)
02321     {
02322       SPI_CloseRxTx_ISR(hspi);
02323     }
02324   }
02325 }
02326
02327 /**
02328   * @brief  Manage the CRC 8-bit receive in Interrupt context.
02329   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02330   *               the configuration information for SPI module.
02331   * @retval None
02332   */
02333 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
02334 {
02335   __IO uint8_t tmpreg = *((uint8_t*)&hspi->Instance->DR);
02336   UNUSED(tmpreg); /* To avoid GCC warning */
02337
02338   hspi->CRCSize--;
02339
02340   if(hspi->CRCSize == 0)
02341   {
02342     SPI_CloseRx_ISR(hspi);
02343   }
02344 }
02345
02346 /**
02347   * @brief  Manage the receive 8-bit in Interrupt context.
02348   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02349   *               the configuration information for SPI module.
02350   * @retval None
02351   */
02352 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02353 {
02354   *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
02355   hspi->RxXferCount--;
02356
02357   /* Enable CRC Transmission */
02358   if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
02359   {
02360     hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02361   }
02362
02363   if(hspi->RxXferCount == 0)
02364   {
02365     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02366     {
02367       hspi->RxISR =  SPI_RxISR_8BITCRC;
02368       return;
02369     }
02370     SPI_CloseRx_ISR(hspi);
02371   }
02372 }
02373
02374 /**
02375   * @brief  Manage the CRC 16-bit receive in Interrupt context.
02376   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02377   *               the configuration information for SPI module.
02378   * @retval None
02379   */
02380 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
02381 {
02382   __IO uint16_t tmpreg;
02383
02384   tmpreg = hspi->Instance->DR;
02385   UNUSED(tmpreg); /* To avoid GCC warning */
02386
02387   /* Disable RXNE and ERR interrupt */
02388   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02389
02390   SPI_CloseRx_ISR(hspi);
02391 }
02392
02393 /**
02394   * @brief  Manage the 16-bit receive in Interrupt context.
02395   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02396   *               the configuration information for SPI module.
02397   * @retval None
02398   */
02399 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02400 {
02401   *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
02402   hspi->pRxBuffPtr += sizeof(uint16_t);
02403   hspi->RxXferCount--;
02404
02405   /* Enable CRC Transmission */
02406   if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
02407   {
02408     hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02409   }
02410
02411   if(hspi->RxXferCount == 0)
02412   {
02413     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02414     {
02415       hspi->RxISR = SPI_RxISR_16BITCRC;
02416       return;
02417     }
02418     SPI_CloseRx_ISR(hspi);
02419   }
02420 }
02421
02422 /**
02423   * @brief  Handle the data 8-bit transmit in Interrupt mode.
02424   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02425   *               the configuration information for SPI module.
02426   * @retval None
02427   */
02428 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02429 {
02430   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
02431   hspi->TxXferCount--;
02432
02433   if(hspi->TxXferCount == 0)
02434   {
02435     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02436     {
02437       /* Enable CRC Transmission */
02438       hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02439     }
02440
02441     SPI_CloseTx_ISR(hspi);
02442   }
02443 }
02444
02445 /**
02446   * @brief  Handle the data 16-bit transmit in Interrupt mode.
02447   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02448   *               the configuration information for SPI module.
02449   * @retval None
02450   */
02451 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02452 {
02453   /* Transmit data in 16 Bit mode */
02454   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
02455   hspi->pTxBuffPtr += sizeof(uint16_t);
02456   hspi->TxXferCount--;
02457
02458   if(hspi->TxXferCount == 0)
02459   {
02460     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02461     {
02462       /* Enable CRC Transmission */
02463       hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
02464     }
02465     SPI_CloseTx_ISR(hspi);
02466   }
02467 }
02468
02469 /**
02470   * @brief Handle SPI Communication Timeout.
02471   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02472   *               the configuration information for SPI module.
02473   * @param Flag : SPI flag to check
02474   * @param State : flag state to check
02475   * @param Timeout : Timeout duration
02476   * @retval HAL status
02477   */
02478 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
02479 {
02480   uint32_t tickstart = HAL_GetTick();
02481
02482   while((hspi->Instance->SR & Flag) != State)
02483   {
02484     if(Timeout != HAL_MAX_DELAY)
02485     {
02486       if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
02487       {
02488         /* Disable the SPI and reset the CRC: the CRC value should be cleared
02489         on both master and slave sides in order to resynchronize the master
02490         and slave for their respective CRC calculation */
02491
02492         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
02493         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
02494
02495         if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02496         {
02497           /* Disable SPI peripheral */
02498           __HAL_SPI_DISABLE(hspi);
02499         }
02500
02501         /* Reset CRC Calculation */
02502         if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02503         {
02504           SPI_RESET_CRC(hspi);
02505         }
02506
02507         hspi->State= HAL_SPI_STATE_READY;
02508
02509         /* Process Unlocked */
02510         __HAL_UNLOCK(hspi);
02511
02512         return HAL_TIMEOUT;
02513       }
02514     }
02515   }
02516
02517   return HAL_OK;
02518 }
02519
02520 /**
02521   * @brief Handle SPI FIFO Communication Timeout.
02522   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02523   *               the configuration information for SPI module.
02524   * @param Fifo : Fifo to check
02525   * @param State : Fifo state to check
02526   * @param Timeout : Timeout duration
02527   * @retval HAL status
02528   */
02529 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
02530 {
02531   __IO uint8_t tmpreg;
02532   uint32_t tickstart = HAL_GetTick();
02533
02534   while((hspi->Instance->SR & Fifo) != State)
02535   {
02536     if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
02537     {
02538       tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
02539       UNUSED(tmpreg); /* To avoid GCC warning */
02540     }
02541
02542     if(Timeout != HAL_MAX_DELAY)
02543     {
02544       if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
02545       {
02546         /* Disable the SPI and reset the CRC: the CRC value should be cleared
02547                   on both master and slave sides in order to resynchronize the master
02548                  and slave for their respective CRC calculation */
02549
02550         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
02551         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
02552
02553         if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02554         {
02555           /* Disable SPI peripheral */
02556           __HAL_SPI_DISABLE(hspi);
02557         }
02558
02559         /* Reset CRC Calculation */
02560         if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02561         {
02562           SPI_RESET_CRC(hspi);
02563         }
02564
02565         hspi->State = HAL_SPI_STATE_READY;
02566
02567         /* Process Unlocked */
02568         __HAL_UNLOCK(hspi);
02569
02570         return HAL_TIMEOUT;
02571       }
02572     }
02573   }
02574
02575   return HAL_OK;
02576 }
02577
02578 /**
02579   * @brief Handle the check of the RX transaction complete.
02580   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02581   *               the configuration information for SPI module.
02582   * @param Timeout : Timeout duration
02583   * @retval None
02584   */
02585 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout)
02586 {
02587   if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02588   {
02589     /* Disable SPI peripheral */
02590     __HAL_SPI_DISABLE(hspi);
02591   }
02592
02593   /* Control the BSY flag */
02594   if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
02595   {
02596     hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
02597     return HAL_TIMEOUT;
02598   }
02599
02600   if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02601   {
02602     /* Empty the FRLVL fifo */
02603     if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
02604     {
02605       hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
02606       return HAL_TIMEOUT;
02607     }
02608   }
02609   return HAL_OK;
02610 }
02611
02612 /**
02613   * @brief Handle the check of the RXTX or TX transaction complete.
02614   * @param hspi: SPI handle
02615   * @param Timeout : Timeout duration
02616   */
02617 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
02618 {
02619   /* Control if the TX fifo is empty */
02620   if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
02621   {
02622     hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
02623     return HAL_TIMEOUT;
02624   }
02625   /* Control the BSY flag */
02626   if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
02627   {
02628     hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
02629     return HAL_TIMEOUT;
02630   }
02631   return HAL_OK;
02632 }
02633
02634 /**
02635   * @brief Handle the end of the RXTX transaction.
02636   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02637   *               the configuration information for SPI module.
02638   * @retval None
02639   */
02640 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
02641 {
02642   /* Disable ERR interrupt */
02643   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02644
02645   /* Check the end of the transaction */
02646   if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
02647   {
02648     hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
02649   }
02650
02651   /* Check if CRC error occurred */
02652   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
02653   {
02654     hspi->State = HAL_SPI_STATE_READY;
02655     hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
02656     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02657     HAL_SPI_ErrorCallback(hspi);
02658   }
02659   else
02660   {
02661     if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
02662     {
02663       if(hspi->State == HAL_SPI_STATE_BUSY_RX)
02664       {
02665         hspi->State = HAL_SPI_STATE_READY;
02666         HAL_SPI_RxCpltCallback(hspi);
02667       }
02668       else
02669       {
02670         hspi->State = HAL_SPI_STATE_READY;
02671         HAL_SPI_TxRxCpltCallback(hspi);
02672       }
02673     }
02674     else
02675     {
02676       hspi->State = HAL_SPI_STATE_READY;
02677       HAL_SPI_ErrorCallback(hspi);
02678     }
02679   }
02680 }
02681
02682 /**
02683   * @brief Handle the end of the RX transaction.
02684   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02685   *               the configuration information for SPI module.
02686   * @retval None
02687   */
02688 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
02689 {
02690     /* Disable RXNE and ERR interrupt */
02691     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02692
02693     /* Check the end of the transaction */
02694     if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
02695     {
02696       hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
02697     }
02698     hspi->State = HAL_SPI_STATE_READY;
02699
02700     /* Check if CRC error occurred */
02701     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
02702     {
02703       hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
02704       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02705       HAL_SPI_ErrorCallback(hspi);
02706     }
02707     else
02708     {
02709       if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
02710       {
02711         HAL_SPI_RxCpltCallback(hspi);
02712       }
02713       else
02714       {
02715         HAL_SPI_ErrorCallback(hspi);
02716       }
02717     }
02718 }
02719
02720 /**
02721   * @brief Handle the end of the TX transaction.
02722   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02723   *               the configuration information for SPI module.
02724   * @retval None
02725   */
02726 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
02727 {
02728   /* Disable TXE and ERR interrupt */
02729   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
02730
02731   /* Check the end of the transaction */
02732   if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
02733   {
02734     hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
02735   }
02736
02737   /* Clear overrun flag in 2 Lines communication mode because received is not read */
02738   if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
02739   {
02740     __HAL_SPI_CLEAR_OVRFLAG(hspi);
02741   }
02742
02743   hspi->State = HAL_SPI_STATE_READY;
02744   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02745   {
02746     HAL_SPI_ErrorCallback(hspi);
02747   }
02748   else
02749   {
02750     HAL_SPI_TxCpltCallback(hspi);
02751   }
02752 }
02753
02754 /**
02755   * @}
02756   */
02757
02758 #endif /* HAL_SPI_MODULE_ENABLED */
02759
02760 /**
02761   * @}
02762   */
02763
02764 /**
02765   * @}
02766   */
02767
02768 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_spi.h Source File

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stm32l4xx_hal_spi.h
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00001  /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_spi.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SPI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_SPI_H
00040 #define __STM32L4xx_HAL_SPI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SPI
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SPI_Exported_Types SPI Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  SPI Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Mode;                /*!< Specifies the SPI operating mode.
00068                                      This parameter can be a value of @ref SPI_Mode */
00069
00070   uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
00071                                      This parameter can be a value of @ref SPI_Direction */
00072
00073   uint32_t DataSize;            /*!< Specifies the SPI data size.
00074                                      This parameter can be a value of @ref SPI_Data_Size */
00075
00076   uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
00077                                      This parameter can be a value of @ref SPI_Clock_Polarity */
00078
00079   uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
00080                                      This parameter can be a value of @ref SPI_Clock_Phase */
00081
00082   uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
00083                                      hardware (NSS pin) or by software using the SSI bit.
00084                                      This parameter can be a value of @ref SPI_Slave_Select_management */
00085
00086   uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
00087                                      used to configure the transmit and receive SCK clock.
00088                                      This parameter can be a value of @ref SPI_BaudRate_Prescaler
00089                                      @note The communication clock is derived from the master
00090                                      clock. The slave clock does not need to be set. */
00091
00092   uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
00093                                      This parameter can be a value of @ref SPI_MSB_LSB_transmission */
00094
00095   uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not .
00096                                      This parameter can be a value of @ref SPI_TI_mode */
00097
00098   uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
00099                                      This parameter can be a value of @ref SPI_CRC_Calculation */
00100
00101   uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
00102                                      This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
00103
00104   uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
00105                                      CRC Length is only used with Data8 and Data16, not other data size
00106                                      This parameter can be a value of @ref SPI_CRC_length */
00107
00108   uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
00109                                      This parameter can be a value of @ref SPI_NSSP_Mode
00110                                      This mode is activated by the NSSP bit in the SPIx_CR2 register and
00111                                      it takes effect only if the SPI interface is configured as Motorola SPI
00112                                      master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
00113                                      CPOL setting is ignored).. */
00114 } SPI_InitTypeDef;
00115
00116 /**
00117   * @brief  HAL State structures definition
00118   */
00119 typedef enum
00120 {
00121   HAL_SPI_STATE_RESET      = 0x00,    /*!< Peripheral not Initialized                         */
00122   HAL_SPI_STATE_READY      = 0x01,    /*!< Peripheral Initialized and ready for use           */
00123   HAL_SPI_STATE_BUSY       = 0x02,    /*!< an internal process is ongoing                     */
00124   HAL_SPI_STATE_BUSY_TX    = 0x03,    /*!< Data Transmission process is ongoing               */
00125   HAL_SPI_STATE_BUSY_RX    = 0x04,    /*!< Data Reception process is ongoing                  */
00126   HAL_SPI_STATE_BUSY_TX_RX = 0x05,    /*!< Data Transmission and Reception process is ongoing*/
00127   HAL_SPI_STATE_ERROR      = 0x06     /*!< SPI error state                                   */
00128 }HAL_SPI_StateTypeDef;
00129
00130 /**
00131   * @brief  SPI handle Structure definition
00132   */
00133 typedef struct __SPI_HandleTypeDef
00134 {
00135   SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
00136
00137   SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
00138
00139   uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
00140
00141   uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
00142
00143   uint16_t                   TxXferCount;    /*!< SPI Tx Transfer Counter                  */
00144
00145   uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
00146
00147   uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
00148
00149   uint16_t                   RxXferCount;    /*!< SPI Rx Transfer Counter                  */
00150
00151   uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
00152
00153   void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */
00154
00155   void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */
00156
00157   DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
00158
00159   DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
00160
00161   HAL_LockTypeDef            Lock;           /*!< Locking object                           */
00162
00163   __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
00164
00165   __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
00166
00167 }SPI_HandleTypeDef;
00168
00169 /**
00170   * @}
00171   */
00172
00173 /* Exported constants --------------------------------------------------------*/
00174
00175 /** @defgroup SPI_Exported_Constants SPI Exported Constants
00176   * @{
00177   */
00178
00179 /** @defgroup SPI_Error_Code SPI Error Code
00180   * @{
00181   */
00182 #define HAL_SPI_ERROR_NONE   (uint32_t)0x00000000  /*!< No error                          */
00183 #define HAL_SPI_ERROR_MODF   (uint32_t)0x00000001  /*!< MODF error                        */
00184 #define HAL_SPI_ERROR_CRC    (uint32_t)0x00000002  /*!< CRC error                         */
00185 #define HAL_SPI_ERROR_OVR    (uint32_t)0x00000004  /*!< OVR error                         */
00186 #define HAL_SPI_ERROR_FRE    (uint32_t)0x00000008  /*!< FRE error                         */
00187 #define HAL_SPI_ERROR_DMA    (uint32_t)0x00000010  /*!< DMA transfer error                */
00188 #define HAL_SPI_ERROR_FLAG   (uint32_t)0x00000020  /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
00189 #define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040  /*!< Unknown error                     */
00190 /**
00191   * @}
00192   */
00193
00194
00195 /** @defgroup SPI_Mode SPI Mode
00196   * @{
00197   */
00198 #define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
00199 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup SPI_Direction SPI Direction Mode
00205   * @{
00206   */
00207 #define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000)
00208 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
00209 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup SPI_Data_Size SPI Data Size
00215   * @{
00216   */
00217 #define SPI_DATASIZE_4BIT               ((uint32_t)0x0300)
00218 #define SPI_DATASIZE_5BIT               ((uint32_t)0x0400)
00219 #define SPI_DATASIZE_6BIT               ((uint32_t)0x0500)
00220 #define SPI_DATASIZE_7BIT               ((uint32_t)0x0600)
00221 #define SPI_DATASIZE_8BIT               ((uint32_t)0x0700)
00222 #define SPI_DATASIZE_9BIT               ((uint32_t)0x0800)
00223 #define SPI_DATASIZE_10BIT              ((uint32_t)0x0900)
00224 #define SPI_DATASIZE_11BIT              ((uint32_t)0x0A00)
00225 #define SPI_DATASIZE_12BIT              ((uint32_t)0x0B00)
00226 #define SPI_DATASIZE_13BIT              ((uint32_t)0x0C00)
00227 #define SPI_DATASIZE_14BIT              ((uint32_t)0x0D00)
00228 #define SPI_DATASIZE_15BIT              ((uint32_t)0x0E00)
00229 #define SPI_DATASIZE_16BIT              ((uint32_t)0x0F00)
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
00235   * @{
00236   */
00237 #define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
00238 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup SPI_Clock_Phase SPI Clock Phase
00244   * @{
00245   */
00246 #define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
00247 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
00253   * @{
00254   */
00255 #define SPI_NSS_SOFT                    SPI_CR1_SSM
00256 #define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
00257 #define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000)
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
00263   * @{
00264   */
00265 #define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
00266 #define SPI_NSS_PULSE_DISABLE           ((uint32_t)0x00000000)
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
00272   * @{
00273   */
00274 #define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
00275 #define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008)
00276 #define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010)
00277 #define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018)
00278 #define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020)
00279 #define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028)
00280 #define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030)
00281 #define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038)
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
00287   * @{
00288   */
00289 #define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
00290 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup SPI_TI_mode SPI TI mode
00296   * @{
00297   */
00298 #define SPI_TIMODE_DISABLE              ((uint32_t)0x00000000)
00299 #define SPI_TIMODE_ENABLE               SPI_CR2_FRF
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
00305   * @{
00306   */
00307 #define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000)
00308 #define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup SPI_CRC_length SPI CRC Length
00314   * @{
00315   * This parameter can be one of the following values:
00316   *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
00317   *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
00318   *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
00319   */
00320 #define SPI_CRC_LENGTH_DATASIZE         ((uint32_t)0x00000000)
00321 #define SPI_CRC_LENGTH_8BIT             ((uint32_t)0x00000001)
00322 #define SPI_CRC_LENGTH_16BIT            ((uint32_t)0x00000002)
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
00328   * @{
00329   * This parameter can be one of the following values:
00330   *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
00331   *          RXNE event is generated if the FIFO
00332   *          level is greater or equal to 1/2(16-bits).
00333   *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
00334   *          level is greater or equal to 1/4(8 bits). */
00335 #define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
00336 #define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
00337 #define SPI_RXFIFO_THRESHOLD_HF         ((uint32_t)0x00000000)
00338
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
00344   * @brief SPI Interrupt definition
00345   *        Elements values convention: 0xXXXXXXXX
00346   *           - XXXXXXXX  : Interrupt control mask
00347   * @{
00348   */
00349 #define SPI_IT_TXE                      SPI_CR2_TXEIE
00350 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
00351 #define SPI_IT_ERR                      SPI_CR2_ERRIE
00352 /**
00353   * @}
00354   */
00355
00356
00357 /** @defgroup SPI_Flag_definition SPI Flag definition
00358   * @brief Flag definition
00359   *        Elements values convention: 0xXXXXYYYY
00360   *           - XXXX  : Flag register Index
00361   *           - YYYY  : Flag mask
00362   * @{
00363   */
00364 #define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */
00365 #define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */
00366 #define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */
00367 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
00368 #define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */
00369 #define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */
00370 #define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
00371 #define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level */
00372 #define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level */
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
00378   * @{
00379   */
00380 #define SPI_FTLVL_EMPTY           ((uint32_t)0x0000)
00381 #define SPI_FTLVL_QUARTER_FULL    ((uint32_t)0x0800)
00382 #define SPI_FTLVL_HALF_FULL       ((uint32_t)0x1000)
00383 #define SPI_FTLVL_FULL            ((uint32_t)0x1800)
00384
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
00390   * @{
00391   */
00392 #define SPI_FRLVL_EMPTY           ((uint32_t)0x0000)
00393 #define SPI_FRLVL_QUARTER_FULL    ((uint32_t)0x0200)
00394 #define SPI_FRLVL_HALF_FULL       ((uint32_t)0x0400)
00395 #define SPI_FRLVL_FULL            ((uint32_t)0x0600)
00396 /**
00397   * @}
00398   */
00399
00400 /**
00401   * @}
00402   */
00403
00404 /* Exported macros ------------------------------------------------------------*/
00405 /** @defgroup SPI_Exported_Macros SPI Exported Macros
00406   * @{
00407   */
00408
00409 /** @brief  Reset SPI handle state.
00410   * @param  __HANDLE__: SPI handle.
00411   * @retval None
00412   */
00413 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
00414
00415 /** @brief  Enable or disable the specified SPI interrupts.
00416   * @param  __HANDLE__: specifies the SPI Handle.
00417   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00418   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00419   *        This parameter can be one of the following values:
00420   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00421   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00422   *            @arg SPI_IT_ERR: Error interrupt enable
00423   * @retval None
00424   */
00425 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
00426 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
00427
00428 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
00429   * @param  __HANDLE__: specifies the SPI Handle.
00430   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00431   * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
00432   *          This parameter can be one of the following values:
00433   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00434   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00435   *            @arg SPI_IT_ERR: Error interrupt enable
00436   * @retval The new state of __IT__ (TRUE or FALSE).
00437   */
00438 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00439
00440 /** @brief  Check whether the specified SPI flag is set or not.
00441   * @param  __HANDLE__: specifies the SPI Handle.
00442   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00443   * @param  __FLAG__: specifies the flag to check.
00444   *        This parameter can be one of the following values:
00445   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00446   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00447   *            @arg SPI_FLAG_CRCERR: CRC error flag
00448   *            @arg SPI_FLAG_MODF: Mode fault flag
00449   *            @arg SPI_FLAG_OVR: Overrun flag
00450   *            @arg SPI_FLAG_BSY: Busy flag
00451   *            @arg SPI_FLAG_FRE: Frame format error flag
00452   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
00453   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
00454   * @retval The new state of __FLAG__ (TRUE or FALSE).
00455   */
00456 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00457
00458 /** @brief  Clear the SPI CRCERR pending flag.
00459   * @param  __HANDLE__: specifies the SPI Handle.
00460   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00461   * @retval None
00462   */
00463 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
00464
00465 /** @brief  Clear the SPI MODF pending flag.
00466   * @param  __HANDLE__: specifies the SPI Handle.
00467   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00468   *
00469   * @retval None
00470   */
00471 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)        \
00472    do{                                              \
00473      __IO uint32_t tmpreg;                          \
00474      tmpreg = (__HANDLE__)->Instance->SR;           \
00475      (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
00476      UNUSED(tmpreg);                                \
00477    } while(0)
00478
00479 /** @brief  Clear the SPI OVR pending flag.
00480   * @param  __HANDLE__: specifies the SPI Handle.
00481   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00482   *
00483   * @retval None
00484   */
00485 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)         \
00486    do{                                              \
00487      __IO uint32_t tmpreg;                          \
00488      tmpreg = (__HANDLE__)->Instance->DR;           \
00489      tmpreg = (__HANDLE__)->Instance->SR;           \
00490      UNUSED(tmpreg);                                \
00491    } while(0)
00492
00493 /** @brief  Clear the SPI FRE pending flag.
00494   * @param  __HANDLE__: specifies the SPI Handle.
00495   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00496   *
00497   * @retval None
00498   */
00499 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)         \
00500    do{                                              \
00501      __IO uint32_t tmpreg;                          \
00502      tmpreg = (__HANDLE__)->Instance->SR;           \
00503      UNUSED(tmpreg);                                \
00504    } while(0)
00505
00506 /** @brief  Enable the SPI peripheral.
00507   * @param  __HANDLE__: specifies the SPI Handle.
00508   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00509   * @retval None
00510   */
00511 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
00512
00513 /** @brief  Disable the SPI peripheral.
00514   * @param  __HANDLE__: specifies the SPI Handle.
00515   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00516   * @retval None
00517   */
00518 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
00519
00520 /**
00521   * @}
00522   */
00523
00524 /* Private macros --------------------------------------------------------*/
00525 /** @defgroup SPI_Private_Macros   SPI Private Macros
00526   * @{
00527   */
00528
00529 /** @brief  Set the SPI transmit-only mode.
00530   * @param  __HANDLE__: specifies the SPI Handle.
00531   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00532   * @retval None
00533   */
00534 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
00535
00536 /** @brief  Set the SPI receive-only mode.
00537   * @param  __HANDLE__: specifies the SPI Handle.
00538   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00539   * @retval None
00540   */
00541 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
00542
00543 /** @brief  Reset the CRC calculation of the SPI.
00544   * @param  __HANDLE__: specifies the SPI Handle.
00545   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00546   * @retval None
00547   */
00548 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
00549                                      (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
00550
00551 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
00552                            ((MODE) == SPI_MODE_MASTER))
00553
00554 #define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES) || \
00555                                   ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
00556                                   ((MODE) == SPI_DIRECTION_1LINE))
00557
00558 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
00559
00560 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
00561                                                  ((MODE) == SPI_DIRECTION_1LINE))
00562
00563 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
00564                                    ((DATASIZE) == SPI_DATASIZE_15BIT) || \
00565                                    ((DATASIZE) == SPI_DATASIZE_14BIT) || \
00566                                    ((DATASIZE) == SPI_DATASIZE_13BIT) || \
00567                                    ((DATASIZE) == SPI_DATASIZE_12BIT) || \
00568                                    ((DATASIZE) == SPI_DATASIZE_11BIT) || \
00569                                    ((DATASIZE) == SPI_DATASIZE_10BIT) || \
00570                                    ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
00571                                    ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
00572                                    ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
00573                                    ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
00574                                    ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
00575                                    ((DATASIZE) == SPI_DATASIZE_4BIT))
00576
00577 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
00578                            ((CPOL) == SPI_POLARITY_HIGH))
00579
00580 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
00581                            ((CPHA) == SPI_PHASE_2EDGE))
00582
00583 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
00584                          ((NSS) == SPI_NSS_HARD_INPUT) || \
00585                          ((NSS) == SPI_NSS_HARD_OUTPUT))
00586
00587 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
00588                            ((NSSP) == SPI_NSS_PULSE_DISABLE))
00589
00590 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
00591                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
00592                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
00593                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
00594                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
00595                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
00596                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
00597                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
00598
00599 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
00600                                ((BIT) == SPI_FIRSTBIT_LSB))
00601
00602 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
00603                              ((MODE) == SPI_TIMODE_ENABLE))
00604
00605 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
00606                                              ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
00607
00608 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
00609                                    ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
00610                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT))
00611
00612 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
00613
00614
00615 /**
00616   * @}
00617   */
00618
00619 /* Include SPI HAL Extended module */
00620 #include "stm32l4xx_hal_spi_ex.h"
00621
00622 /* Exported functions --------------------------------------------------------*/
00623 /** @addtogroup SPI_Exported_Functions
00624   * @{
00625   */
00626
00627 /* Initialization and de-initialization functions  ****************************/
00628 /** @addtogroup SPI_Exported_Functions_Group1
00629   * @{
00630   */
00631 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
00632 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
00633 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
00634 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
00635 /**
00636   * @}
00637   */
00638
00639 /* IO operation functions *****************************************************/
00640 /** @addtogroup SPI_Exported_Functions_Group2
00641   * @{
00642   */
00643 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00644 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00645 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00646 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00647 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00648 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00649 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00650 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00651 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00652 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
00653 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
00654 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
00655
00656 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
00657 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
00658 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
00659 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
00660 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00661 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00662 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00663 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
00664 /**
00665   * @}
00666   */
00667
00668 /* Peripheral State and Error functions ***************************************/
00669 /** @addtogroup SPI_Exported_Functions_Group3
00670   * @{
00671   */
00672 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
00673 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
00674 /**
00675   * @}
00676   */
00677
00678 /**
00679   * @}
00680   */
00681
00682 /**
00683   * @}
00684   */
00685
00686 /**
00687   * @}
00688   */
00689
00690 #ifdef __cplusplus
00691 }
00692 #endif
00693
00694 #endif /* __STM32L4xx_HAL_SPI_H */
00695
00696 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_spi_ex.c Source File

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stm32l4xx_hal_spi_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_spi_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Extended SPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          SPI peripheral extended functionalities :
00010   *           + IO operation functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32l4xx_hal.h"
00044
00045 /** @addtogroup STM32L4xx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup SPIEx SPIEx
00050   * @brief SPI Extended HAL module driver
00051   * @{
00052   */
00053 #ifdef HAL_SPI_MODULE_ENABLED
00054
00055 /* Private typedef -----------------------------------------------------------*/
00056 /* Private defines -----------------------------------------------------------*/
00057 /** @defgroup SPIEx_Private_Constants SPIEx Private Constants
00058   * @{
00059   */
00060 #define SPI_FIFO_SIZE       4
00061 /**
00062   * @}
00063   */
00064
00065 /* Private macros ------------------------------------------------------------*/
00066 /* Private variables ---------------------------------------------------------*/
00067 /* Private function prototypes -----------------------------------------------*/
00068 /* Exported functions ---------------------------------------------------------*/
00069
00070 /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
00071   * @{
00072   */
00073
00074 /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
00075  *  @brief   Data transfers functions
00076  *
00077 @verbatim
00078   ==============================================================================
00079                       ##### IO operation functions #####
00080  ===============================================================================
00081  [..]
00082     This subsection provides a set of extended functions to manage the SPI
00083     data transfers.
00084
00085     (#) Rx data flush function:
00086         (++) HAL_SPIEx_FlushRxFifo()
00087
00088 @endverbatim
00089   * @{
00090   */
00091
00092 /**
00093   * @brief Flush the RX fifo.
00094   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00095   *               the configuration information for the specified SPI module.
00096   * @retval HAL status
00097   */
00098 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
00099 {
00100   __IO uint32_t tmpreg;
00101   uint8_t  count = 0;
00102   while((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)
00103   {
00104     count++;
00105     tmpreg = hspi->Instance->DR;
00106     UNUSED(tmpreg); /* To avoid GCC warning */
00107     if(count == SPI_FIFO_SIZE)
00108     {
00109       return HAL_TIMEOUT;
00110     }
00111   }
00112   return HAL_OK;
00113 }
00114
00115 /**
00116   * @}
00117   */
00118
00119 /**
00120   * @}
00121   */
00122
00123 #endif /* HAL_SPI_MODULE_ENABLED */
00124
00125 /**
00126   * @}
00127   */
00128
00129 /**
00130   * @}
00131   */
00132
00133 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_spi_ex.h Source File

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stm32l4xx_hal_spi_ex.h
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00001  /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_spi_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SPI HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_SPI_EX_H
00040 #define __STM32L4xx_HAL_SPI_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SPIEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /* Exported macros ------------------------------------------------------------*/
00060 /* Exported functions --------------------------------------------------------*/
00061 /** @addtogroup SPIEx_Exported_Functions
00062   * @{
00063   */
00064
00065 /* Initialization and de-initialization functions  ****************************/
00066 /* IO operation functions *****************************************************/
00067 /** @addtogroup SPIEx_Exported_Functions_Group1
00068   * @{
00069   */
00070 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
00071 /**
00072   * @}
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /**
00080   * @}
00081   */
00082
00083 /**
00084   * @}
00085   */
00086
00087 #ifdef __cplusplus
00088 }
00089 #endif
00090
00091 #endif /* __STM32L4xx_HAL_SPI_EX_H */
00092
00093 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sram.c Source File

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stm32l4xx_hal_sram.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_sram.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SRAM HAL module driver.
00008   *          This file provides a generic firmware to drive SRAM memories
00009   *          mounted as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                           ##### How to use this driver #####
00014   ==============================================================================
00015   [..]
00016     This driver is a generic layered driver which contains a set of APIs used to
00017     control SRAM memories. It uses the FMC layer functions to interface
00018     with SRAM devices.
00019     The following sequence should be followed to configure the FMC to interface
00020     with SRAM/PSRAM memories:
00021
00022    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
00023           SRAM_HandleTypeDef  hsram; and:
00024
00025        (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
00026             values of the structure member.
00027
00028        (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
00029             base register instance for NOR or SRAM device
00030
00031        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
00032             base register instance for NOR or SRAM extended mode
00033
00034    (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
00035        mode timings; for example:
00036           FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
00037       and fill its fields with the allowed values of the structure member.
00038
00039    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
00040        performs the following sequence:
00041
00042        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
00043        (##) Control register configuration using the FMC NORSRAM interface function
00044             FMC_NORSRAM_Init()
00045        (##) Timing register configuration using the FMC NORSRAM interface function
00046             FMC_NORSRAM_Timing_Init()
00047        (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
00048             FMC_NORSRAM_Extended_Timing_Init()
00049        (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
00050
00051    (#) At this stage you can perform read/write accesses from/to the memory connected
00052        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
00053        following APIs:
00054        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
00055        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
00056
00057    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
00058        HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
00059
00060    (#) You can continuously monitor the SRAM device HAL state by calling the function
00061        HAL_SRAM_GetState()
00062
00063   @endverbatim
00064   ******************************************************************************
00065   * @attention
00066   *
00067   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00068   *
00069   * Redistribution and use in source and binary forms, with or without modification,
00070   * are permitted provided that the following conditions are met:
00071   *   1. Redistributions of source code must retain the above copyright notice,
00072   *      this list of conditions and the following disclaimer.
00073   *   2. Redistributions in binary form must reproduce the above copyright notice,
00074   *      this list of conditions and the following disclaimer in the documentation
00075   *      and/or other materials provided with the distribution.
00076   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00077   *      may be used to endorse or promote products derived from this software
00078   *      without specific prior written permission.
00079   *
00080   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00081   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00082   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00083   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00084   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00085   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00086   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00087   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00088   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00089   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00090   *
00091   ******************************************************************************
00092   */
00093
00094 /* Includes ------------------------------------------------------------------*/
00095 #include "stm32l4xx_hal.h"
00096
00097 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00098
00099 /** @addtogroup STM32L4xx_HAL_Driver
00100   * @{
00101   */
00102
00103 #ifdef HAL_SRAM_MODULE_ENABLED
00104
00105 /** @defgroup SRAM SRAM
00106   * @brief SRAM HAL module driver.
00107   * @{
00108   */
00109 /* Private typedef -----------------------------------------------------------*/
00110 /* Private define ------------------------------------------------------------*/
00111 /* Private macro -------------------------------------------------------------*/
00112 /* Private variables ---------------------------------------------------------*/
00113 /* Private function prototypes -----------------------------------------------*/
00114 /* Exported functions --------------------------------------------------------*/
00115
00116 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
00117   * @{
00118   */
00119
00120 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00121   * @brief    Initialization and Configuration functions.
00122   *
00123   @verbatim
00124   ==============================================================================
00125            ##### SRAM Initialization and de-initialization functions #####
00126   ==============================================================================
00127     [..]  This section provides functions allowing to initialize/de-initialize
00128           the SRAM memory.
00129
00130 @endverbatim
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  Perform the SRAM device initialization sequence.
00136   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00137   *                the configuration information for SRAM module.
00138   * @param  Timing: Pointer to SRAM control timing structure
00139   * @param  ExtTiming: Pointer to SRAM extended mode timing structure
00140   * @retval HAL status
00141   */
00142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00143 {
00144   /* Check the SRAM handle parameter */
00145   if(hsram == NULL)
00146   {
00147      return HAL_ERROR;
00148   }
00149
00150   if(hsram->State == HAL_SRAM_STATE_RESET)
00151   {
00152     /* Allocate lock resource and initialize it */
00153     hsram->Lock = HAL_UNLOCKED;
00154
00155     /* Initialize the low level hardware (MSP) */
00156     HAL_SRAM_MspInit(hsram);
00157   }
00158
00159   /* Initialize SRAM control Interface */
00160   FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
00161
00162   /* Initialize SRAM timing Interface */
00163   FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
00164
00165   /* Initialize SRAM extended mode timing Interface */
00166   FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);
00167
00168   /* Enable the NORSRAM device */
00169   __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
00170
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  Perform the SRAM device de-initialization sequence.
00176   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00177   *                the configuration information for SRAM module.
00178   * @retval HAL status
00179   */
00180 HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
00181 {
00182   /* De-Initialize the low level hardware (MSP) */
00183   HAL_SRAM_MspDeInit(hsram);
00184
00185   /* Configure the SRAM registers with their reset values */
00186   FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
00187
00188   hsram->State = HAL_SRAM_STATE_RESET;
00189
00190   /* Release Lock */
00191   __HAL_UNLOCK(hsram);
00192
00193   return HAL_OK;
00194 }
00195
00196 /**
00197   * @brief  Initialize the SRAM MSP.
00198   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00199   *                the configuration information for SRAM module.
00200   * @retval None
00201   */
00202 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
00203 {
00204   /* Prevent unused argument(s) compilation warning */
00205   UNUSED(hsram);
00206
00207   /* NOTE : This function should not be modified, when the callback is needed,
00208             the HAL_SRAM_MspInit could be implemented in the user file
00209    */
00210 }
00211
00212 /**
00213   * @brief  DeInitialize the SRAM MSP.
00214   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00215   *                the configuration information for SRAM module.
00216   * @retval None
00217   */
00218 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
00219 {
00220   /* Prevent unused argument(s) compilation warning */
00221   UNUSED(hsram);
00222
00223   /* NOTE : This function should not be modified, when the callback is needed,
00224             the HAL_SRAM_MspDeInit could be implemented in the user file
00225    */
00226 }
00227
00228 /**
00229   * @brief  DMA transfer complete callback.
00230   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
00231   *                the configuration information for SRAM module.
00232   * @retval None
00233   */
00234 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
00235 {
00236   /* Prevent unused argument(s) compilation warning */
00237   UNUSED(hdma);
00238
00239   /* NOTE : This function should not be modified, when the callback is needed,
00240             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
00241    */
00242 }
00243
00244 /**
00245   * @brief  DMA transfer complete error callback.
00246   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
00247   *                the configuration information for SRAM module.
00248   * @retval None
00249   */
00250 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
00251 {
00252   /* Prevent unused argument(s) compilation warning */
00253   UNUSED(hdma);
00254
00255   /* NOTE : This function should not be modified, when the callback is needed,
00256             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
00257    */
00258 }
00259
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00265   * @brief    Input Output and memory control functions
00266   *
00267   @verbatim
00268   ==============================================================================
00269                   ##### SRAM Input and Output functions #####
00270   ==============================================================================
00271   [..]
00272     This section provides functions allowing to use and control the SRAM memory
00273
00274 @endverbatim
00275   * @{
00276   */
00277
00278 /**
00279   * @brief  Read 8-bit buffer from SRAM memory.
00280   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00281   *                the configuration information for SRAM module.
00282   * @param  pAddress: Pointer to read start address
00283   * @param  pDstBuffer: Pointer to destination buffer
00284   * @param  BufferSize: Size of the buffer to read from memory
00285   * @retval HAL status
00286   */
00287 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00288 {
00289   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00290
00291   /* Process Locked */
00292   __HAL_LOCK(hsram);
00293
00294   /* Update the SRAM controller state */
00295   hsram->State = HAL_SRAM_STATE_BUSY;
00296
00297   /* Read data from memory */
00298   for(; BufferSize != 0; BufferSize--)
00299   {
00300     *pDstBuffer = *(__IO uint8_t *)psramaddress;
00301     pDstBuffer++;
00302     psramaddress++;
00303   }
00304
00305   /* Update the SRAM controller state */
00306   hsram->State = HAL_SRAM_STATE_READY;
00307
00308   /* Process unlocked */
00309   __HAL_UNLOCK(hsram);
00310
00311   return HAL_OK;
00312 }
00313
00314 /**
00315   * @brief  Write 8-bit buffer to SRAM memory.
00316   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00317   *                the configuration information for SRAM module.
00318   * @param  pAddress: Pointer to write start address
00319   * @param  pSrcBuffer: Pointer to source buffer to write
00320   * @param  BufferSize: Size of the buffer to write to memory
00321   * @retval HAL status
00322   */
00323 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00324 {
00325   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00326
00327   /* Check the SRAM controller state */
00328   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00329   {
00330     return  HAL_ERROR;
00331   }
00332
00333   /* Process Locked */
00334   __HAL_LOCK(hsram);
00335
00336   /* Update the SRAM controller state */
00337   hsram->State = HAL_SRAM_STATE_BUSY;
00338
00339   /* Write data to memory */
00340   for(; BufferSize != 0; BufferSize--)
00341   {
00342     *(__IO uint8_t *)psramaddress = *pSrcBuffer;
00343     pSrcBuffer++;
00344     psramaddress++;
00345   }
00346
00347   /* Update the SRAM controller state */
00348   hsram->State = HAL_SRAM_STATE_READY;
00349
00350   /* Process unlocked */
00351   __HAL_UNLOCK(hsram);
00352
00353   return HAL_OK;
00354 }
00355
00356 /**
00357   * @brief  Read 16-bit buffer from SRAM memory.
00358   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00359   *                the configuration information for SRAM module.
00360   * @param  pAddress: Pointer to read start address
00361   * @param  pDstBuffer: Pointer to destination buffer
00362   * @param  BufferSize: Size of the buffer to read from memory
00363   * @retval HAL status
00364   */
00365 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00366 {
00367   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00368
00369   /* Process Locked */
00370   __HAL_LOCK(hsram);
00371
00372   /* Update the SRAM controller state */
00373   hsram->State = HAL_SRAM_STATE_BUSY;
00374
00375   /* Read data from memory */
00376   for(; BufferSize != 0; BufferSize--)
00377   {
00378     *pDstBuffer = *(__IO uint16_t *)psramaddress;
00379     pDstBuffer++;
00380     psramaddress++;
00381   }
00382
00383   /* Update the SRAM controller state */
00384   hsram->State = HAL_SRAM_STATE_READY;
00385
00386   /* Process unlocked */
00387   __HAL_UNLOCK(hsram);
00388
00389   return HAL_OK;
00390 }
00391
00392 /**
00393   * @brief  Write 16-bit buffer to SRAM memory.
00394   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00395   *                the configuration information for SRAM module.
00396   * @param  pAddress: Pointer to write start address
00397   * @param  pSrcBuffer: Pointer to source buffer to write
00398   * @param  BufferSize: Size of the buffer to write to memory
00399   * @retval HAL status
00400   */
00401 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00402 {
00403   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00404
00405   /* Check the SRAM controller state */
00406   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00407   {
00408     return  HAL_ERROR;
00409   }
00410
00411   /* Process Locked */
00412   __HAL_LOCK(hsram);
00413
00414   /* Update the SRAM controller state */
00415   hsram->State = HAL_SRAM_STATE_BUSY;
00416
00417   /* Write data to memory */
00418   for(; BufferSize != 0; BufferSize--)
00419   {
00420     *(__IO uint16_t *)psramaddress = *pSrcBuffer;
00421     pSrcBuffer++;
00422     psramaddress++;
00423   }
00424
00425   /* Update the SRAM controller state */
00426   hsram->State = HAL_SRAM_STATE_READY;
00427
00428   /* Process unlocked */
00429   __HAL_UNLOCK(hsram);
00430
00431   return HAL_OK;
00432 }
00433
00434 /**
00435   * @brief  Read 32-bit buffer from SRAM memory.
00436   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00437   *                the configuration information for SRAM module.
00438   * @param  pAddress: Pointer to read start address
00439   * @param  pDstBuffer: Pointer to destination buffer
00440   * @param  BufferSize: Size of the buffer to read from memory
00441   * @retval HAL status
00442   */
00443 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00444 {
00445   /* Process Locked */
00446   __HAL_LOCK(hsram);
00447
00448   /* Update the SRAM controller state */
00449   hsram->State = HAL_SRAM_STATE_BUSY;
00450
00451   /* Read data from memory */
00452   for(; BufferSize != 0; BufferSize--)
00453   {
00454     *pDstBuffer = *(__IO uint32_t *)pAddress;
00455     pDstBuffer++;
00456     pAddress++;
00457   }
00458
00459   /* Update the SRAM controller state */
00460   hsram->State = HAL_SRAM_STATE_READY;
00461
00462   /* Process unlocked */
00463   __HAL_UNLOCK(hsram);
00464
00465   return HAL_OK;
00466 }
00467
00468 /**
00469   * @brief  Write 32-bit buffer to SRAM memory.
00470   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00471   *                the configuration information for SRAM module.
00472   * @param  pAddress: Pointer to write start address
00473   * @param  pSrcBuffer: Pointer to source buffer to write
00474   * @param  BufferSize: Size of the buffer to write to memory
00475   * @retval HAL status
00476   */
00477 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00478 {
00479   /* Check the SRAM controller state */
00480   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00481   {
00482     return  HAL_ERROR;
00483   }
00484
00485   /* Process Locked */
00486   __HAL_LOCK(hsram);
00487
00488   /* Update the SRAM controller state */
00489   hsram->State = HAL_SRAM_STATE_BUSY;
00490
00491   /* Write data to memory */
00492   for(; BufferSize != 0; BufferSize--)
00493   {
00494     *(__IO uint32_t *)pAddress = *pSrcBuffer;
00495     pSrcBuffer++;
00496     pAddress++;
00497   }
00498
00499   /* Update the SRAM controller state */
00500   hsram->State = HAL_SRAM_STATE_READY;
00501
00502   /* Process unlocked */
00503   __HAL_UNLOCK(hsram);
00504
00505   return HAL_OK;
00506 }
00507
00508 /**
00509   * @brief  Read a Word data buffer from the SRAM memory using DMA transfer.
00510   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00511   *                the configuration information for SRAM module.
00512   * @param  pAddress: Pointer to read start address
00513   * @param  pDstBuffer: Pointer to destination buffer
00514   * @param  BufferSize: Size of the buffer to read from memory
00515   * @retval HAL status
00516   */
00517 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00518 {
00519   /* Process Locked */
00520   __HAL_LOCK(hsram);
00521
00522   /* Update the SRAM controller state */
00523   hsram->State = HAL_SRAM_STATE_BUSY;
00524
00525   /* Configure DMA user callbacks */
00526   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00527   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00528
00529   /* Enable the DMA Channel */
00530   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
00531
00532   /* Update the SRAM controller state */
00533   hsram->State = HAL_SRAM_STATE_READY;
00534
00535   /* Process unlocked */
00536   __HAL_UNLOCK(hsram);
00537
00538   return HAL_OK;
00539 }
00540
00541 /**
00542   * @brief  Write a Word data buffer to SRAM memory using DMA transfer.
00543   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00544   *                the configuration information for SRAM module.
00545   * @param  pAddress: Pointer to write start address
00546   * @param  pSrcBuffer: Pointer to source buffer to write
00547   * @param  BufferSize: Size of the buffer to write to memory
00548   * @retval HAL status
00549   */
00550 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00551 {
00552   /* Check the SRAM controller state */
00553   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00554   {
00555     return  HAL_ERROR;
00556   }
00557
00558   /* Process Locked */
00559   __HAL_LOCK(hsram);
00560
00561   /* Update the SRAM controller state */
00562   hsram->State = HAL_SRAM_STATE_BUSY;
00563
00564   /* Configure DMA user callbacks */
00565   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00566   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00567
00568   /* Enable the DMA Channel */
00569   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
00570
00571   /* Update the SRAM controller state */
00572   hsram->State = HAL_SRAM_STATE_READY;
00573
00574   /* Process unlocked */
00575   __HAL_UNLOCK(hsram);
00576
00577   return HAL_OK;
00578 }
00579
00580 /**
00581   * @}
00582   */
00583
00584 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
00585  *  @brief   Control functions
00586  *
00587 @verbatim
00588   ==============================================================================
00589                         ##### SRAM Control functions #####
00590   ==============================================================================
00591   [..]
00592     This subsection provides a set of functions allowing to control dynamically
00593     the SRAM interface.
00594
00595 @endverbatim
00596   * @{
00597   */
00598
00599 /**
00600   * @brief  Enable dynamically SRAM write operation.
00601   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00602   *                the configuration information for SRAM module.
00603   * @retval HAL status
00604   */
00605 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
00606 {
00607   /* Process Locked */
00608   __HAL_LOCK(hsram);
00609
00610   /* Enable write operation */
00611   FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
00612
00613   /* Update the SRAM controller state */
00614   hsram->State = HAL_SRAM_STATE_READY;
00615
00616   /* Process unlocked */
00617   __HAL_UNLOCK(hsram);
00618
00619   return HAL_OK;
00620 }
00621
00622 /**
00623   * @brief  Disable dynamically SRAM write operation.
00624   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00625   *                the configuration information for SRAM module.
00626   * @retval HAL status
00627   */
00628 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
00629 {
00630   /* Process Locked */
00631   __HAL_LOCK(hsram);
00632
00633   /* Update the SRAM controller state */
00634   hsram->State = HAL_SRAM_STATE_BUSY;
00635
00636   /* Disable write operation */
00637   FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
00638
00639   /* Update the SRAM controller state */
00640   hsram->State = HAL_SRAM_STATE_PROTECTED;
00641
00642   /* Process unlocked */
00643   __HAL_UNLOCK(hsram);
00644
00645   return HAL_OK;
00646 }
00647
00648 /**
00649   * @}
00650   */
00651
00652 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
00653  *  @brief   Peripheral State functions
00654  *
00655 @verbatim
00656   ==============================================================================
00657                       ##### SRAM State functions #####
00658   ==============================================================================
00659   [..]
00660     This subsection permits to get in run-time the status of the SRAM controller
00661     and the data flow.
00662
00663 @endverbatim
00664   * @{
00665   */
00666
00667 /**
00668   * @brief  Return the SRAM controller handle state.
00669   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00670   *                the configuration information for SRAM module.
00671   * @retval HAL state
00672   */
00673 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
00674 {
00675   /* Return SRAM handle state */
00676   return hsram->State;
00677 }
00678
00679 /**
00680   * @}
00681   */
00682
00683 /**
00684   * @}
00685   */
00686 /**
00687   * @}
00688   */
00689 #endif /* HAL_SRAM_MODULE_ENABLED */
00690
00691 /**
00692   * @}
00693   */
00694
00695 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00696
00697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_sram.h Source File

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stm32l4xx_hal_sram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_sram.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SRAM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_SRAM_H
00040 #define __STM32L4xx_HAL_SRAM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32l4xx_ll_fmc.h"
00050
00051 /** @addtogroup STM32L4xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup SRAM
00056   * @{
00057   */
00058
00059 /* Exported typedef ----------------------------------------------------------*/
00060
00061 /** @defgroup SRAM_Exported_Types SRAM Exported Types
00062   * @{
00063   */
00064 /**
00065   * @brief  HAL SRAM State structures definition
00066   */
00067 typedef enum
00068 {
00069   HAL_SRAM_STATE_RESET     = 0x00,  /*!< SRAM not yet initialized or disabled           */
00070   HAL_SRAM_STATE_READY     = 0x01,  /*!< SRAM initialized and ready for use             */
00071   HAL_SRAM_STATE_BUSY      = 0x02,  /*!< SRAM internal process is ongoing               */
00072   HAL_SRAM_STATE_ERROR     = 0x03,  /*!< SRAM error state                               */
00073   HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
00074
00075 }HAL_SRAM_StateTypeDef;
00076
00077 /**
00078   * @brief  SRAM handle Structure definition
00079   */
00080 typedef struct
00081 {
00082   FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
00083
00084   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
00085
00086   FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
00087
00088   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
00089
00090   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
00091
00092   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
00093
00094 }SRAM_HandleTypeDef;
00095
00096 /**
00097   * @}
00098   */
00099
00100 /* Exported constants --------------------------------------------------------*/
00101 /* Exported macro ------------------------------------------------------------*/
00102
00103 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
00104  * @{
00105  */
00106
00107 /** @brief Reset SRAM handle state.
00108   * @param  __HANDLE__: SRAM handle
00109   * @retval None
00110   */
00111 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
00112
00113 /**
00114   * @}
00115   */
00116
00117 /* Exported functions --------------------------------------------------------*/
00118 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
00119   * @{
00120   */
00121
00122 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00123  * @{
00124  */
00125
00126 /* Initialization/de-initialization functions  ********************************/
00127 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00128 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
00129 void              HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
00130 void              HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
00131
00132 void              HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
00133 void              HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
00134
00135 /**
00136   * @}
00137   */
00138
00139 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00140  * @{
00141  */
00142
00143 /* I/O operation functions  ***************************************************/
00144 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00145 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00146 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00147 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00148 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00149 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00150 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00151 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00152
00153 /**
00154   * @}
00155   */
00156
00157 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
00158  * @{
00159  */
00160
00161 /* SRAM Control functions  ****************************************************/
00162 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
00163 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
00164
00165 /**
00166   * @}
00167   */
00168
00169 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
00170  * @{
00171  */
00172
00173 /* SRAM Peripheral State functions ********************************************/
00174 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
00175
00176 /**
00177   * @}
00178   */
00179
00180 /**
00181   * @}
00182   */
00183
00184 /**
00185   * @}
00186   */
00187
00188 /**
00189   * @}
00190   */
00191
00192 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00193
00194 #ifdef __cplusplus
00195 }
00196 #endif
00197
00198 #endif /* __STM32L4xx_HAL_SRAM_H */
00199
00200 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_swpmi.c Source File

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stm32l4xx_hal_swpmi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_swpmi.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SWPMI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Single Wire Protocol Master Interface (SWPMI).
00010   *           + Initialization and Configuration
00011   *           + Data transfers functions
00012   *           + DMA transfers management
00013   *           + Interrupts and flags management
00014   @verbatim
00015  ===============================================================================
00016                         ##### How to use this driver #####
00017  ===============================================================================
00018   [..]
00019      The SWPMI HAL driver can be used as follows:
00020
00021     (#) Declare a SWPMI_HandleTypeDef handle structure (eg. SWPMI_HandleTypeDef hswpmi).
00022
00023     (#) Initialize the SWPMI low level resources by implementing the HAL_SWPMI_MspInit() API:
00024         (##) Enable the SWPMIx interface clock with __HAL_RCC_SWPMIx_CLK_ENABLE().
00025         (##) SWPMI IO configuration:
00026             (+++) Enable the clock for the SWPMI GPIO.
00027             (+++) Configure these SWPMI pins as alternate function pull-up.
00028         (##) NVIC configuration if you need to use interrupt process (HAL_SWPMI_Transmit_IT()
00029              and HAL_SWPMI_Receive_IT() APIs):
00030             (+++) Configure the SWPMIx interrupt priority with HAL_NVIC_SetPriority().
00031             (+++) Enable the NVIC SWPMI IRQ handle with HAL_NVIC_EnableIRQ().
00032
00033         (##) DMA Configuration if you need to use DMA process (HAL_SWPMI_Transmit_DMA()
00034              and HAL_SWPMI_Receive_DMA() APIs):
00035             (+++) Declare a DMA handle structure for the Tx/Rx channels.
00036             (+++) Enable the DMAx interface clock.
00037             (+++) Configure the declared DMA handle structure with the required
00038                   Tx/Rx parameters.
00039             (+++) Configure the DMA Tx/Rx channels and requests.
00040             (+++) Associate the initialized DMA handle to the SWPMI DMA Tx/Rx handle.
00041             (+++) Configure the priority and enable the NVIC for the transfer complete
00042                   interrupt on the DMA Tx/Rx channels.
00043
00044     (#) Program the Bite Rate, Tx Buffering mode, Rx Buffering mode in the Init structure.
00045
00046     (#) Enable the SWPMI peripheral by calling the HAL_SWPMI_Init() function.
00047
00048   @endverbatim
00049   ******************************************************************************
00050   * @attention
00051   *
00052   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00053   *
00054   * Redistribution and use in source and binary forms, with or without modification,
00055   * are permitted provided that the following conditions are met:
00056   *   1. Redistributions of source code must retain the above copyright notice,
00057   *      this list of conditions and the following disclaimer.
00058   *   2. Redistributions in binary form must reproduce the above copyright notice,
00059   *      this list of conditions and the following disclaimer in the documentation
00060   *      and/or other materials provided with the distribution.
00061   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00062   *      may be used to endorse or promote products derived from this software
00063   *      without specific prior written permission.
00064   *
00065   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00066   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00067   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00068   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00069   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00070   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00071   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00072   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00073   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00074   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00075   *
00076   ******************************************************************************
00077   */
00078
00079 /* Includes ------------------------------------------------------------------*/
00080 #include "stm32l4xx_hal.h"
00081
00082 /** @addtogroup STM32L4xx_HAL_Driver
00083   * @{
00084   */
00085
00086 /** @defgroup SWPMI SWPMI
00087   * @brief HAL SWPMI module driver
00088   * @{
00089   */
00090 #ifdef HAL_SWPMI_MODULE_ENABLED
00091
00092 /* Private typedef -----------------------------------------------------------*/
00093 /* Private define ------------------------------------------------------------*/
00094 /* Private constants ---------------------------------------------------------*/
00095 /** @addtogroup SWPMI_Private_Constants SWPMI Private Constants
00096   * @{
00097   */
00098 #define SWPMI_TIMEOUT_VALUE       ((uint32_t) 22000)
00099
00100 /**
00101   * @}
00102   */
00103
00104 /* Private macros ------------------------------------------------------------*/
00105 /* Private variables ---------------------------------------------------------*/
00106 /* Private function prototypes -----------------------------------------------*/
00107 static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00108 static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00109 static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00110 static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00111 static void SWPMI_DMAError(DMA_HandleTypeDef *hdma);
00112 static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi);
00113 static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi);
00114 static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi);
00115 static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi);
00116 static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi);
00117 static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout);
00118
00119 /* Exported functions --------------------------------------------------------*/
00120
00121 /** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
00122   * @{
00123   */
00124
00125 /** @defgroup SWPMI_Exported_Group1 Initialization/de-initialization methods
00126   *  @brief    Initialization and Configuration functions
00127   *
00128 @verbatim
00129  ===============================================================================
00130             ##### Initialization and Configuration functions #####
00131  ===============================================================================
00132     [..]  This section provides functions allowing to:
00133       (+) Initialize and configure the SWPMI peripheral.
00134       (+) De-initialize the SWPMI peripheral.
00135
00136 @endverbatim
00137   * @{
00138   */
00139
00140 /**
00141   * @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef.
00142   * @param hswpmi: SWPMI handle
00143   * @retval HAL status
00144   */
00145 HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
00146 {
00147   HAL_StatusTypeDef status = HAL_OK;
00148   __IO uint32_t wait_loop_index = 0;
00149
00150   /* Check the SWPMI handle allocation */
00151   if(hswpmi == NULL)
00152   {
00153     status = HAL_ERROR;
00154   }
00155   else
00156   {
00157     /* Check the parameters */
00158     assert_param(IS_SWPMI_VOLTAGE_CLASS(hswpmi->Init.VoltageClass));
00159     assert_param(IS_SWPMI_BITRATE_VALUE(hswpmi->Init.BitRate));
00160     assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode));
00161     assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode));
00162
00163     if(hswpmi->State == HAL_SWPMI_STATE_RESET)
00164     {
00165       /* Allocate lock resource and initialize it */
00166       hswpmi->Lock = HAL_UNLOCKED;
00167     }
00168
00169     hswpmi->State = HAL_SWPMI_STATE_BUSY;
00170
00171     /* Disable SWPMI interface */
00172     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00173
00174     /* Clear all SWPMI interface flags */
00175     WRITE_REG(hswpmi->Instance->ICR, 0x019F);
00176
00177     /* Apply Voltage class selection */
00178     MODIFY_REG(hswpmi->Instance->OR, SWPMI_OR_CLASS, hswpmi->Init.VoltageClass);
00179
00180     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00181     HAL_SWPMI_MspInit(hswpmi);
00182
00183     /* If Voltage class B, apply 300 µs delay */
00184     if(hswpmi->Init.VoltageClass == SWPMI_VOLTAGE_CLASS_B)
00185     {
00186       /* Insure 300 µs wait to insure SWPMI_IO output not higher than 1.8V */
00187       /* Wait loop initialization and execution                            */
00188       /* Note: Variable divided by 4 to compensate partially CPU processing cycles. */
00189       wait_loop_index = (300 * (SystemCoreClock / (1000000 * 4))) + 150;
00190       while(wait_loop_index != 0)
00191       {
00192         wait_loop_index--;
00193       }
00194     }
00195
00196     /* Configure the BRR register (Bitrate) */
00197     WRITE_REG(hswpmi->Instance->BRR, hswpmi->Init.BitRate);
00198
00199     /* Apply SWPMI CR configuration */
00200     MODIFY_REG(hswpmi->Instance->CR, \
00201                SWPMI_CR_RXDMA | SWPMI_CR_TXDMA  | SWPMI_CR_RXMODE | SWPMI_CR_TXMODE, \
00202                hswpmi->Init.TxBufferingMode | hswpmi->Init.RxBufferingMode);
00203
00204     hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00205     hswpmi->State = HAL_SWPMI_STATE_READY;
00206
00207     /* Enable SWPMI peripheral if not */
00208     SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00209   }
00210
00211   return status;
00212 }
00213
00214 /**
00215   * @brief De-initialize the SWPMI peripheral.
00216   * @param hswpmi: SWPMI handle
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi)
00220 {
00221   HAL_StatusTypeDef status = HAL_OK;
00222
00223   /* Check the SWPMI handle allocation */
00224   if(hswpmi == NULL)
00225   {
00226     status = HAL_ERROR;
00227   }
00228   else
00229   {
00230     /* Check the parameters */
00231     assert_param(IS_SWPMI_INSTANCE(hswpmi->Instance));
00232
00233     hswpmi->State = HAL_SWPMI_STATE_BUSY;
00234
00235     /* Disable SWPMI interface */
00236     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00237
00238     /* DeInit the low level hardware */
00239     HAL_SWPMI_MspDeInit(hswpmi);
00240
00241     hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00242
00243     hswpmi->State = HAL_SWPMI_STATE_RESET;
00244
00245     /* Release Lock */
00246     __HAL_UNLOCK(hswpmi);
00247   }
00248
00249   return status;
00250 }
00251
00252 /**
00253   * @brief Initialize the SWPMI MSP.
00254   * @param hswpmi: SWPMI handle
00255   * @retval None
00256   */
00257 __weak void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi)
00258 {
00259   /* Prevent unused argument(s) compilation warning */
00260   UNUSED(hswpmi);
00261
00262   /* NOTE : This function should not be modified, when the callback is needed,
00263             the HAL_SWPMI_MspInit can be implemented in the user file
00264    */
00265 }
00266
00267 /**
00268   * @brief DeInitialize the SWPMI MSP.
00269   * @param hswpmi: SWPMI handle
00270   * @retval None
00271   */
00272 __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi)
00273 {
00274   /* Prevent unused argument(s) compilation warning */
00275   UNUSED(hswpmi);
00276
00277   /* NOTE : This function should not be modified, when the callback is needed,
00278             the HAL_SWPMI_MspDeInit can be implemented in the user file
00279    */
00280 }
00281
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SWPMI_Exported_Group2 IO operation methods
00287   *  @brief SWPMI Transmit/Receive functions
00288   *
00289 @verbatim
00290  ===============================================================================
00291                       ##### IO operation methods #####
00292  ===============================================================================
00293  [..]
00294     This subsection provides a set of functions allowing to manage the SWPMI
00295      data transfers.
00296
00297     (#) There are two modes of transfer:
00298        (++) Blocking mode: The communication is performed in polling mode.
00299             The HAL status of all data processing is returned by the same function
00300             after finishing transfer.
00301        (++) Non-Blocking mode: The communication is performed using Interrupts
00302            or DMA. The end of the data processing will be indicated through the
00303            dedicated SWPMI Interrupt handler (HAL_SWPMI_IRQHandler()) when using Interrupt mode or
00304            the selected DMA channel interrupt handler when using DMA mode.
00305            The HAL_SWPMI_TxCpltCallback(), HAL_SWPMI_RxCpltCallback() user callbacks
00306            will be executed respectively at the end of the transmit or receive process.
00307            The HAL_SWPMI_ErrorCallback() user callback will be executed when a communication error is detected.
00308
00309     (#) Blocking mode API's are:
00310         (++) HAL_SWPMI_Transmit()
00311         (++) HAL_SWPMI_Receive()
00312
00313     (#) Non-Blocking mode API's with Interrupt are:
00314         (++) HAL_SWPMI_Transmit_IT()
00315         (++) HAL_SWPMI_Receive_IT()
00316         (++) HAL_SWPMI_IRQHandler()
00317
00318     (#) Non-Blocking mode API's with DMA are:
00319         (++) HAL_SWPMI_Transmit_DMA()
00320         (++) HAL_SWPMI_Receive_DMA()
00321         (++) HAL_SWPMI_DMAPause()
00322         (++) HAL_SWPMI_DMAResume()
00323         (++) HAL_SWPMI_DMAStop()
00324
00325     (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
00326         (++) HAL_SWPMI_TxHalfCpltCallback()
00327         (++) HAL_SWPMI_TxCpltCallback()
00328         (++) HAL_SWPMI_RxHalfCpltCallback()
00329         (++) HAL_SWPMI_RxCpltCallback()
00330         (++) HAL_SWPMI_ErrorCallback()
00331
00332     (#) The capability to launch the above IO operations in loopback mode for
00333         user application verification:
00334         (++) HAL_SWPMI_EnableLoopback()
00335         (++) HAL_SWPMI_DisableLoopback()
00336
00337 @endverbatim
00338   * @{
00339   */
00340
00341 /**
00342   * @brief  Transmit an amount of data in blocking mode.
00343   * @param  hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
00344   *                the configuration information for SWPMI module.
00345   * @param  pData: Pointer to data buffer
00346   * @param  Size: Amount of data to be sent
00347   * @param  Timeout: Timeout duration
00348   * @retval HAL status
00349   */
00350 HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout)
00351 {
00352   uint32_t tickstart = HAL_GetTick();
00353   HAL_StatusTypeDef status = HAL_OK;
00354
00355   if((pData == NULL ) || (Size == 0))
00356   {
00357     status = HAL_ERROR;
00358   }
00359   else
00360   {
00361     /* Process Locked */
00362     __HAL_LOCK(hswpmi);
00363
00364     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
00365     {
00366       /* Check if a non-blocking receive process is ongoing or not */
00367       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00368       {
00369         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00370
00371         /* Disable any transmitter interrupts */
00372         __HAL_SWPMI_DISABLE_IT(hswpmi, SWPMI_IT_TCIE | SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
00373
00374         /* Disable any transmitter flags */
00375         __HAL_SWPMI_CLEAR_FLAG(hswpmi, SWPMI_FLAG_TXBEF | SWPMI_FLAG_TXUNRF | SWPMI_FLAG_TCF);
00376
00377         /* Enable SWPMI peripheral if not */
00378         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00379       }
00380       else
00381       {
00382         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00383       }
00384
00385       do
00386       {
00387         /* Wait the TXE to write data */
00388         if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
00389         {
00390           hswpmi->Instance->TDR = (*pData++);
00391           Size--;
00392         }
00393         else
00394         {
00395           /* Check for the Timeout */
00396           if(Timeout != HAL_MAX_DELAY)
00397           {
00398             if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
00399             {
00400               status = HAL_TIMEOUT;
00401               break;
00402             }
00403           }
00404         }
00405       } while(Size != 0);
00406
00407       /* Wait on TXBEF flag to be able to start a second transfer */
00408       if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
00409       {
00410         status = HAL_TIMEOUT;
00411       }
00412
00413       if(status == HAL_OK)
00414       {
00415         /* Check if a non-blocking receive Process is ongoing or not */
00416         if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
00417         {
00418           hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00419         }
00420         else
00421         {
00422           hswpmi->State = HAL_SWPMI_STATE_READY;
00423         }
00424       }
00425     }
00426     else
00427     {
00428       status = HAL_BUSY;
00429     }
00430   }
00431
00432   if((status != HAL_OK) && (status != HAL_BUSY))
00433   {
00434     hswpmi->State = HAL_SWPMI_STATE_READY;
00435   }
00436   /* Process Unlocked */
00437   __HAL_UNLOCK(hswpmi);
00438
00439   return status;
00440 }
00441
00442 /**
00443   * @brief  Receive an amount of data in blocking mode.
00444   * @param  hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
00445   *                the configuration information for SWPMI module.
00446   * @param  pData: Pointer to data buffer
00447   * @param  Size: Amount of data to be received
00448   * @param  Timeout: Timeout duration
00449   * @retval HAL status
00450   */
00451 HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
00452 {
00453   uint32_t tickstart = HAL_GetTick();
00454   HAL_StatusTypeDef status = HAL_OK;
00455
00456   if((pData == NULL ) || (Size == 0))
00457   {
00458     status = HAL_ERROR;
00459   }
00460   else
00461   {
00462     /* Process Locked */
00463     __HAL_LOCK(hswpmi);
00464
00465     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
00466     {
00467       /* Check if a non-blocking transmit process is ongoing or not */
00468       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00469       {
00470         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00471
00472         /* Disable any receiver interrupts */
00473         CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
00474
00475         /* Enable SWPMI peripheral if not */
00476         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00477       }
00478       else
00479       {
00480         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00481       }
00482
00483       do
00484       {
00485         /* Wait the RXNE to read data */
00486         if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
00487         {
00488           (*pData++) = hswpmi->Instance->RDR;
00489           Size--;
00490         }
00491         else
00492         {
00493           /* Check for the Timeout */
00494           if(Timeout != HAL_MAX_DELAY)
00495           {
00496             if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
00497             {
00498               status = HAL_TIMEOUT;
00499               break;
00500             }
00501           }
00502         }
00503       } while(Size != 0);
00504
00505       if(status == HAL_OK)
00506       {
00507         if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
00508         {
00509           /* Clear RXBFF at end of reception */
00510           WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
00511         }
00512
00513         /* Check if a non-blocking transmit Process is ongoing or not */
00514         if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
00515         {
00516           hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00517         }
00518         else
00519         {
00520           hswpmi->State = HAL_SWPMI_STATE_READY;
00521         }
00522       }
00523     }
00524     else
00525     {
00526       status = HAL_BUSY;
00527     }
00528   }
00529
00530   if((status != HAL_OK) && (status != HAL_BUSY))
00531   {
00532     hswpmi->State = HAL_SWPMI_STATE_READY;
00533   }
00534   /* Process Unlocked */
00535   __HAL_UNLOCK(hswpmi);
00536
00537   return status;
00538 }
00539
00540 /**
00541   * @brief  Transmit an amount of data in non-blocking mode with interrupt.
00542   * @param  hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains
00543   *                the configuration information for SWPMI module.
00544   * @param  pData: Pointer to data buffer
00545   * @param  Size: Amount of data to be sent
00546   * @retval HAL status
00547   */
00548 HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
00549 {
00550   HAL_StatusTypeDef status = HAL_OK;
00551
00552   if((pData == NULL ) || (Size == 0))
00553   {
00554     status =  HAL_ERROR;
00555   }
00556   else
00557   {
00558     /* Process Locked */
00559     __HAL_LOCK(hswpmi);
00560
00561     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
00562     {
00563       /* Update handle */
00564       hswpmi->pTxBuffPtr = pData;
00565       hswpmi->TxXferSize = Size;
00566       hswpmi->TxXferCount = Size;
00567       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00568
00569       /* Check if a receive process is ongoing or not */
00570       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00571       {
00572         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00573
00574         /* Enable SWPMI peripheral if not */
00575         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00576       }
00577       else
00578       {
00579         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00580       }
00581
00582       /* Enable the SWPMI transmit underrun error */
00583       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE);
00584
00585       /* Process Unlocked */
00586       __HAL_UNLOCK(hswpmi);
00587
00588       /* Enable the SWPMI interrupts:      */
00589       /* - Transmit data register empty    */
00590       /* - Transmit buffer empty           */
00591       /* - Transmit/Reception completion   */
00592       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TIE | SWPMI_IT_TXBEIE | SWPMI_IT_TCIE);
00593     }
00594     else
00595     {
00596       status =  HAL_BUSY;
00597
00598       /* Process Unlocked */
00599       __HAL_UNLOCK(hswpmi);
00600     }
00601   }
00602
00603   return status;
00604 }
00605
00606 /**
00607   * @brief Receive an amount of data in non-blocking mode with interrupt.
00608   * @param hswpmi: SWPMI handle
00609   * @param pData: pointer to data buffer
00610   * @param Size: amount of data to be received
00611   * @retval HAL status
00612   */
00613 HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
00614 {
00615   HAL_StatusTypeDef status = HAL_OK;
00616
00617   if((pData == NULL ) || (Size == 0))
00618   {
00619     status =  HAL_ERROR;
00620   }
00621   else
00622   {
00623     /* Process Locked */
00624     __HAL_LOCK(hswpmi);
00625
00626     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
00627     {
00628       /* Update handle */
00629       hswpmi->pRxBuffPtr = pData;
00630       hswpmi->RxXferSize = Size;
00631       hswpmi->RxXferCount = Size;
00632       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00633
00634       /* Check if a transmit process is ongoing or not */
00635       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00636       {
00637         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00638
00639         /* Enable SWPMI peripheral if not */
00640         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00641       }
00642       else
00643       {
00644         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00645       }
00646
00647       /* Process Unlocked */
00648       __HAL_UNLOCK(hswpmi);
00649
00650       /* Enable the SWPMI slave resume */
00651       /* Enable the SWPMI Data Register not empty Interrupt, receive CRC Error, receive overrun and RxBuf Interrupt */
00652       /*  Enable the SWPMI Transmit/Reception completion   */
00653       __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
00654     }
00655     else
00656     {
00657       status = HAL_BUSY;
00658
00659       /* Process Unlocked */
00660       __HAL_UNLOCK(hswpmi);
00661     }
00662   }
00663
00664   return status;
00665 }
00666
00667 /**
00668   * @brief Transmit an amount of data in non-blocking mode with DMA interrupt.
00669   * @param hswpmi: SWPMI handle
00670   * @param pData: pointer to data buffer
00671   * @param Size: amount of data to be sent
00672   * @retval HAL status
00673   */
00674 HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
00675 {
00676   HAL_StatusTypeDef status = HAL_OK;
00677
00678   if((pData == NULL ) || (Size == 0))
00679   {
00680     status =  HAL_ERROR;
00681   }
00682   else
00683   {
00684     /* Process Locked */
00685     __HAL_LOCK(hswpmi);
00686
00687     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX))
00688     {
00689       /* Update handle */
00690       hswpmi->pTxBuffPtr = pData;
00691       hswpmi->TxXferSize = Size;
00692       hswpmi->TxXferCount = Size;
00693       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00694
00695       /* Check if a receive process is ongoing or not */
00696       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00697       {
00698         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
00699
00700         /* Enable SWPMI peripheral if not */
00701         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00702       }
00703       else
00704       {
00705         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00706       }
00707
00708       /* Set the SWPMI DMA transfer complete callback */
00709       hswpmi->hdmatx->XferCpltCallback = SWPMI_DMATransmitCplt;
00710
00711       /* Set the SWPMI DMA Half transfer complete callback */
00712       hswpmi->hdmatx->XferHalfCpltCallback = SWPMI_DMATxHalfCplt;
00713
00714       /* Set the DMA error callback */
00715       hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError;
00716
00717       /* Enable the SWPMI transmit DMA Stream */
00718       HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size);
00719
00720       /* Process Unlocked */
00721       __HAL_UNLOCK(hswpmi);
00722
00723       /* Enable the DMA transfer for transmit request by setting the TXDMA bit
00724          in the SWPMI CR register */
00725       SET_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
00726     }
00727     else
00728     {
00729       status = HAL_BUSY;
00730
00731       /* Process Unlocked */
00732       __HAL_UNLOCK(hswpmi);
00733     }
00734   }
00735
00736   return status;
00737 }
00738
00739 /**
00740   * @brief Receive an amount of data in non-blocking mode with DMA interrupt.
00741   * @param hswpmi: SWPMI handle
00742   * @param pData: pointer to data buffer
00743   * @param Size: amount of data to be received
00744   * @retval HAL status
00745   */
00746 HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size)
00747 {
00748   HAL_StatusTypeDef status = HAL_OK;
00749
00750   if((pData == NULL ) || (Size == 0))
00751   {
00752     status =  HAL_ERROR;
00753   }
00754   else
00755   {
00756     /* Process Locked */
00757     __HAL_LOCK(hswpmi);
00758
00759     if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))
00760     {
00761       /* Update handle */
00762       hswpmi->pRxBuffPtr = pData;
00763       hswpmi->RxXferSize = Size;
00764       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
00765
00766       /* Check if a transmit process is ongoing or not */
00767       if(hswpmi->State == HAL_SWPMI_STATE_READY)
00768       {
00769         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
00770
00771         /* Enable SWPMI peripheral if not */
00772         SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00773       }
00774       else
00775       {
00776         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;
00777       }
00778
00779       /* Set the SWPMI DMA transfer complete callback */
00780       hswpmi->hdmarx->XferCpltCallback = SWPMI_DMAReceiveCplt;
00781
00782       /* Set the SWPMI DMA Half transfer complete callback */
00783       hswpmi->hdmarx->XferHalfCpltCallback = SWPMI_DMARxHalfCplt;
00784
00785       /* Set the DMA error callback */
00786       hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError;
00787
00788       /* Enable the DMA request */
00789       HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size);
00790
00791       /* Process Unlocked */
00792       __HAL_UNLOCK(hswpmi);
00793
00794       /* Enable the DMA transfer for the receiver request by setting the RXDMA bit
00795          in the SWPMI CR register */
00796       SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
00797     }
00798     else
00799     {
00800       status = HAL_BUSY;
00801
00802       /* Process Unlocked */
00803       __HAL_UNLOCK(hswpmi);
00804     }
00805   }
00806
00807   return status;
00808 }
00809
00810 /**
00811   * @brief Stop all DMA transfers.
00812   * @param hswpmi: SWPMI handle
00813   * @retval HAL_OK
00814   */
00815 HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi)
00816 {
00817   /* Process Locked */
00818   __HAL_LOCK(hswpmi);
00819
00820   /* Disable the SWPMI Tx/Rx DMA requests */
00821   CLEAR_BIT(hswpmi->Instance->CR, (SWPMI_CR_TXDMA | SWPMI_CR_RXDMA));
00822
00823   /* Abort the SWPMI DMA tx channel */
00824   if(hswpmi->hdmatx != NULL)
00825   {
00826     HAL_DMA_Abort(hswpmi->hdmatx);
00827   }
00828   /* Abort the SWPMI DMA rx channel */
00829   if(hswpmi->hdmarx != NULL)
00830   {
00831     HAL_DMA_Abort(hswpmi->hdmarx);
00832   }
00833
00834   /* Disable SWPMI interface */
00835   CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);
00836
00837   hswpmi->State = HAL_SWPMI_STATE_READY;
00838
00839   /* Process Unlocked */
00840   __HAL_UNLOCK(hswpmi);
00841
00842   return HAL_OK;
00843 }
00844
00845
00846 /**
00847   * @brief Enable the Loopback mode.
00848   * @param hswpmi: SWPMI handle
00849   * @note  Loopback mode is to be used only for test purposes
00850   * @retval HAL_OK / HAL_BUSY
00851   */
00852 HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi)
00853 {
00854   HAL_StatusTypeDef  status = HAL_OK;
00855
00856   /* Process Locked */
00857   __HAL_LOCK(hswpmi);
00858
00859   /* Check SWPMI not enabled */
00860   if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET)
00861   {
00862     status = HAL_BUSY;
00863   }
00864   else
00865   {
00866     /* Set Loopback */
00867     SET_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
00868   }
00869
00870   /* Process Unlocked */
00871   __HAL_UNLOCK(hswpmi);
00872
00873   return status;
00874 }
00875
00876 /**
00877   * @brief Disable the Loopback mode.
00878   * @param hswpmi: SWPMI handle
00879   * @note  Loopback mode is to be used only for test purposes
00880   * @retval HAL_OK / HAL_BUSY
00881   */
00882 HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi)
00883 {
00884   HAL_StatusTypeDef  status = HAL_OK;
00885
00886   /* Process Locked */
00887   __HAL_LOCK(hswpmi);
00888
00889   /* Check SWPMI not enabled */
00890   if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET)
00891   {
00892     status = HAL_BUSY;
00893   }
00894   else
00895   {
00896     /* Reset Loopback */
00897     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK);
00898   }
00899
00900   /* Process Unlocked */
00901   __HAL_UNLOCK(hswpmi);
00902
00903   return status;
00904 }
00905
00906 /**
00907   * @}
00908   */
00909
00910 /** @defgroup SWPMI_Exported_Group3 SWPMI IRQ handler and callbacks
00911  *  @brief  SWPMI  IRQ handler.
00912  *
00913 @verbatim
00914   ==============================================================================
00915                       ##### SWPMI IRQ handler and callbacks  #####
00916   ==============================================================================
00917 [..]  This section provides SWPMI IRQ handler and callback functions called within
00918       the IRQ handler.
00919
00920 @endverbatim
00921   * @{
00922   */
00923
00924 /**
00925   * @brief Handle SWPMI interrupt request.
00926   * @param hswpmi: SWPMI handle
00927   * @retval None
00928   */
00929 void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
00930 {
00931   uint32_t regisr = READ_REG(hswpmi->Instance->ISR);
00932   uint32_t regier = READ_REG(hswpmi->Instance->IER);
00933
00934   /* SWPMI CRC error interrupt occurred --------------------------------------*/
00935   if(((regisr & SWPMI_FLAG_RXBERF) != RESET) && ((regier & SWPMI_IT_RXBERIE) != RESET))
00936   {
00937     /* Disable Receive CRC interrupt */
00938     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE);
00939     /* Clear Receive CRC and Receive buffer full flag */
00940     WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBERF | SWPMI_FLAG_RXBFF);
00941
00942     hswpmi->ErrorCode |= HAL_SWPMI_ERROR_CRC;
00943   }
00944
00945   /* SWPMI Over-Run interrupt occurred -----------------------------------------*/
00946   if(((regisr & SWPMI_FLAG_RXOVRF) != RESET) && ((regier & SWPMI_IT_RXOVRIE) != RESET))
00947   {
00948     /* Disable Receive overrun interrupt */
00949     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE);
00950     /* Clear Receive overrun flag */
00951     WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXOVRF);
00952
00953     hswpmi->ErrorCode |= HAL_SWPMI_ERROR_OVR;
00954   }
00955
00956   /* SWPMI Under-Run interrupt occurred -----------------------------------------*/
00957   if(((regisr & SWPMI_FLAG_TXUNRF) != RESET) && ((regier & SWPMI_IT_TXUNRIE) != RESET))
00958   {
00959     /* Disable Transmit under run interrupt */
00960     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE);
00961     /* Clear Transmit under run flag */
00962     WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXUNRF);
00963
00964     hswpmi->ErrorCode |= HAL_SWPMI_ERROR_UDR;
00965   }
00966
00967    /* Call SWPMI Error Call back function if need be --------------------------*/
00968   if(hswpmi->ErrorCode != HAL_SWPMI_ERROR_NONE)
00969   {
00970     /* Set the SWPMI state ready to be able to start again the process */
00971     hswpmi->State = HAL_SWPMI_STATE_READY;
00972
00973     HAL_SWPMI_ErrorCallback(hswpmi);
00974   }
00975
00976   /* SWPMI in mode Receiver ---------------------------------------------------*/
00977   if(((regisr & SWPMI_FLAG_RXNE) != RESET) && ((regier & SWPMI_IT_RIE)  != RESET))
00978   {
00979     SWPMI_Receive_IT(hswpmi);
00980   }
00981
00982   /* SWPMI in mode Transmitter ------------------------------------------------*/
00983   if(((regisr & SWPMI_FLAG_TXE) != RESET) && ((regier & SWPMI_IT_TIE) != RESET))
00984   {
00985     SWPMI_Transmit_IT(hswpmi);
00986   }
00987
00988   /* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/
00989   if(((regisr & SWPMI_FLAG_TXBEF) != RESET) && ((regier & SWPMI_IT_TXBEIE) != RESET))
00990   {
00991     SWPMI_EndTransmit_IT(hswpmi);
00992   }
00993
00994   /* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/
00995   if(((regisr & SWPMI_FLAG_RXBFF) != RESET) && ((regier & SWPMI_IT_RXBFIE) != RESET))
00996   {
00997     SWPMI_EndReceive_IT(hswpmi);
00998   }
00999
01000   /* Both Transmission and reception complete ---------------------------------*/
01001   if(((regisr & SWPMI_FLAG_TCF) != RESET) && ((regier & SWPMI_IT_TCIE) != RESET))
01002   {
01003     SWPMI_EndTransmitReceive_IT(hswpmi);
01004   }
01005 }
01006
01007 /**
01008   * @brief Tx Transfer completed callback.
01009   * @param hswpmi: SWPMI handle
01010   * @retval None
01011   */
01012 __weak void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01013 {
01014   /* Prevent unused argument(s) compilation warning */
01015   UNUSED(hswpmi);
01016
01017   /* NOTE : This function should not be modified, when the callback is needed,
01018             the HAL_SWPMI_TxCpltCallback is to be implemented in the user file
01019    */
01020 }
01021
01022 /**
01023   * @brief  Tx Half Transfer completed callback.
01024   * @param  hswpmi: SWPMI handle
01025   * @retval None
01026   */
01027 __weak void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01028 {
01029   /* Prevent unused argument(s) compilation warning */
01030   UNUSED(hswpmi);
01031
01032   /* NOTE: This function should not be modified, when the callback is needed,
01033            the HAL_SWPMI_TxHalfCpltCallback is to be implemented in the user file
01034    */
01035 }
01036
01037 /**
01038   * @brief Rx Transfer completed callback.
01039   * @param hswpmi: SWPMI handle
01040   * @retval None
01041   */
01042 __weak void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01043 {
01044   /* Prevent unused argument(s) compilation warning */
01045   UNUSED(hswpmi);
01046
01047   /* NOTE : This function should not be modified, when the callback is needed,
01048             the HAL_SWPMI_RxCpltCallback is to be implemented in the user file
01049    */
01050 }
01051
01052 /**
01053   * @brief  Rx Half Transfer completed callback.
01054   * @param  hswpmi: SWPMI handle
01055   * @retval None
01056   */
01057 __weak void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi)
01058 {
01059   /* Prevent unused argument(s) compilation warning */
01060   UNUSED(hswpmi);
01061
01062   /* NOTE: This function should not be modified, when the callback is needed,
01063            the HAL_SWPMI_RxHalfCpltCallback is to be implemented in the user file
01064    */
01065 }
01066
01067 /**
01068   * @brief SWPMI error callback.
01069   * @param hswpmi: SWPMI handle
01070   * @retval None
01071   */
01072 __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi)
01073 {
01074   /* Prevent unused argument(s) compilation warning */
01075   UNUSED(hswpmi);
01076
01077   /* NOTE : This function should not be modified, when the callback is needed,
01078             the HAL_SWPMI_ErrorCallback is to be implemented in the user file
01079    */
01080 }
01081
01082 /**
01083   * @}
01084   */
01085
01086 /** @defgroup SWPMI_Exported_Group4 Peripheral Control methods
01087   *  @brief   SWPMI control functions
01088   *
01089 @verbatim
01090  ===============================================================================
01091                       ##### Peripheral Control methods #####
01092  ===============================================================================
01093     [..]
01094     This subsection provides a set of functions allowing to control the SWPMI.
01095      (+) HAL_SWPMI_GetState() API is helpful to check in run-time the state of the SWPMI peripheral
01096      (+) HAL_SWPMI_GetError() API is helpful to check in run-time the error state of the SWPMI peripheral
01097 @endverbatim
01098   * @{
01099   */
01100
01101 /**
01102   * @brief Return the SWPMI handle state.
01103   * @param hswpmi: SWPMI handle
01104   * @retval HAL state
01105   */
01106 HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi)
01107 {
01108   /* Return SWPMI handle state */
01109   return hswpmi->State;
01110 }
01111
01112 /**
01113 * @brief  Return the SWPMI error code.
01114 * @param  hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains
01115   *              the configuration information for the specified SWPMI.
01116 * @retval SWPMI Error Code
01117 */
01118 uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi)
01119 {
01120   return hswpmi->ErrorCode;
01121 }
01122
01123 /**
01124   * @}
01125   */
01126
01127 /**
01128   * @}
01129   */
01130
01131 /* Private functions ---------------------------------------------------------*/
01132
01133 /** @defgroup SWPMI_Private_Functions SWPMI Private Functions
01134   * @{
01135   */
01136
01137 /**
01138   * @brief Transmit an amount of data in interrupt mode.
01139   * @note  Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT()
01140   * @param  hswpmi: SWPMI handle
01141   * @retval HAL status
01142   */
01143 static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi)
01144 {
01145   HAL_StatusTypeDef status = HAL_OK;
01146
01147   if ((hswpmi->State == HAL_SWPMI_STATE_BUSY_TX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX))
01148   {
01149     if(hswpmi->TxXferCount == 0)
01150     {
01151       /* Disable the SWPMI TXE and Underrun Interrupts */
01152       CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE));
01153     }
01154     else
01155     {
01156       hswpmi->Instance->TDR = (uint32_t)(*hswpmi->pTxBuffPtr++);
01157       hswpmi->TxXferCount--;
01158     }
01159   }
01160   else
01161   {
01162     status = HAL_BUSY;
01163   }
01164
01165   return status;
01166 }
01167
01168 /**
01169   * @brief  Wraps up transmission in non-blocking mode.
01170   * @param  hswpmi: SWPMI handle
01171   * @retval HAL status
01172   * @retval HAL status
01173   */
01174 static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi)
01175 {
01176   /* Clear the SWPMI Transmit buffer empty Flag */
01177   WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXBEF);
01178   /* Disable the all SWPMI Transmit Interrupts  */
01179   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
01180
01181   /* Check if a receive Process is ongoing or not */
01182   if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01183   {
01184     hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
01185   }
01186   else
01187   {
01188     hswpmi->State = HAL_SWPMI_STATE_READY;
01189   }
01190
01191   HAL_SWPMI_TxCpltCallback(hswpmi);
01192
01193   return HAL_OK;
01194 }
01195
01196 /**
01197   * @brief Receive an amount of data in interrupt mode.
01198   * @note  Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT()
01199   * @param  hswpmi: SWPMI handle
01200   * @retval HAL status
01201   */
01202 static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi)
01203 {
01204   HAL_StatusTypeDef status = HAL_OK;
01205
01206   if((hswpmi->State == HAL_SWPMI_STATE_BUSY_RX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX))
01207   {
01208     *hswpmi->pRxBuffPtr++ = (uint32_t)(hswpmi->Instance->RDR);
01209
01210     if(--hswpmi->RxXferCount == 0)
01211     {
01212       /* Wait for RXBFF flag to update state */
01213       HAL_SWPMI_RxCpltCallback(hswpmi);
01214     }
01215   }
01216   else
01217   {
01218     status = HAL_BUSY;
01219   }
01220
01221   return status;
01222 }
01223
01224 /**
01225   * @brief  Wraps up reception in non-blocking mode.
01226   * @param  hswpmi: SWPMI handle
01227   * @retval HAL status
01228   * @retval HAL status
01229   */
01230 static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi)
01231 {
01232   /* Clear the SWPMI Receive buffer full Flag */
01233   WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
01234   /* Disable the all SWPMI Receive Interrupts  */
01235   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
01236
01237   /* Check if a transmit Process is ongoing or not */
01238   if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01239   {
01240     hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
01241   }
01242   else
01243   {
01244     hswpmi->State = HAL_SWPMI_STATE_READY;
01245   }
01246
01247   return HAL_OK;
01248 }
01249
01250 /**
01251   * @brief  Wraps up transmission and reception in non-blocking mode.
01252   * @param  hswpmi: SWPMI handle
01253   * @retval HAL status
01254   * @retval HAL status
01255   */
01256 static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi)
01257 {
01258   /* Clear the SWPMI Transmission Complete Flag */
01259   WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TCF);
01260   /* Disable the SWPMI Transmission  Complete Interrupt */
01261   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TCIE);
01262
01263   /* Check if a receive Process is ongoing or not */
01264   if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01265   {
01266     hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
01267   }
01268   else if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
01269   {
01270     hswpmi->State = HAL_SWPMI_STATE_READY;
01271   }
01272
01273   return HAL_OK;
01274 }
01275
01276 /**
01277   * @brief DMA SWPMI transmit process complete callback.
01278   * @param hdma: DMA handle
01279   * @retval None
01280   */
01281 static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01282 {
01283   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01284   uint32_t tickstart = 0;
01285
01286   /* DMA Normal mode*/
01287   if((hdma->Instance->CCR & DMA_CCR_CIRC) != SET)
01288   {
01289     hswpmi->TxXferCount = 0;
01290
01291     /* Disable the DMA transfer for transmit request by setting the TXDMA bit
01292     in the SWPMI CR register */
01293     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
01294
01295     /* Init tickstart for timeout managment*/
01296     tickstart = HAL_GetTick();
01297
01298     /* Wait the TXBEF */
01299     if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
01300     {
01301       /* Timeout occurred */
01302       HAL_SWPMI_ErrorCallback(hswpmi);
01303     }
01304     else
01305     {
01306       /* No Timeout */
01307       /* Check if a receive process is ongoing or not */
01308       if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01309       {
01310         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
01311       }
01312       else
01313       {
01314         hswpmi->State = HAL_SWPMI_STATE_READY;
01315       }
01316
01317       HAL_SWPMI_TxCpltCallback(hswpmi);
01318     }
01319   }
01320   /* DMA Circular mode */
01321   else
01322   {
01323     HAL_SWPMI_TxCpltCallback(hswpmi);
01324   }
01325 }
01326
01327 /**
01328   * @brief DMA SWPMI transmit process half complete callback.
01329   * @param hdma : DMA handle
01330   * @retval None
01331   */
01332 static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01333 {
01334   SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01335
01336   HAL_SWPMI_TxHalfCpltCallback(hswpmi);
01337 }
01338
01339
01340 /**
01341   * @brief DMA SWPMI receive process complete callback.
01342   * @param hdma: DMA handle
01343   * @retval None
01344   */
01345 static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01346 {
01347   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01348
01349   /* DMA Normal mode*/
01350   if((hdma->Instance->CCR & DMA_CCR_CIRC) == RESET)
01351   {
01352     hswpmi->RxXferCount = 0;
01353
01354     /* Disable the DMA transfer for the receiver request by setting the RXDMA bit
01355     in the SWPMI CR register */
01356     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
01357
01358     /* Check if a transmit Process is ongoing or not */
01359     if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
01360     {
01361       hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
01362     }
01363     else
01364     {
01365       hswpmi->State = HAL_SWPMI_STATE_READY;
01366     }
01367   }
01368   HAL_SWPMI_RxCpltCallback(hswpmi);
01369 }
01370
01371 /**
01372   * @brief DMA SWPMI receive process half complete callback.
01373   * @param hdma : DMA handle
01374   * @retval None
01375   */
01376 static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01377 {
01378   SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01379
01380   HAL_SWPMI_RxHalfCpltCallback(hswpmi);
01381 }
01382
01383 /**
01384   * @brief DMA SWPMI communication error callback.
01385   * @param hdma: DMA handle
01386   * @retval None
01387   */
01388 static void SWPMI_DMAError(DMA_HandleTypeDef *hdma)
01389 {
01390   SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01391
01392   /* Update handle */
01393   hswpmi->RxXferCount = 0;
01394   hswpmi->TxXferCount = 0;
01395   hswpmi->State= HAL_SWPMI_STATE_READY;
01396   hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
01397
01398   HAL_SWPMI_ErrorCallback(hswpmi);
01399 }
01400
01401 /**
01402   * @brief  Handle SWPMI Communication Timeout.
01403   * @param  hswpmi: SWPMI handle
01404   * @param  Flag: specifies the SWPMI flag to check.
01405   * @param  Tickstart Tick start value
01406   * @param  Timeout timeout duration.
01407   * @retval HAL status
01408   */
01409 static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout)
01410 {
01411   HAL_StatusTypeDef status = HAL_OK;
01412
01413   /* Wait until flag is set */
01414   while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
01415   {
01416     /* Check for the Timeout */
01417     if(Timeout != HAL_MAX_DELAY)
01418     {
01419       if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
01420       {
01421         hswpmi->State = HAL_SWPMI_STATE_READY;
01422
01423         status = HAL_TIMEOUT;
01424         break;
01425       }
01426     }
01427   }
01428
01429   return status;
01430 }
01431
01432 /**
01433   * @}
01434   */
01435
01436 #endif /* HAL_SWPMI_MODULE_ENABLED */
01437 /**
01438   * @}
01439   */
01440
01441 /**
01442   * @}
01443   */
01444
01445 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_swpmi.h Source File

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stm32l4xx_hal_swpmi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_swpmi.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SWPMI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_SWPMI_H
00040 #define __STM32L4xx_HAL_SWPMI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SWPMI
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SWPMI_Exported_Types SWPMI Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief SWPMI Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t VoltageClass;             /*!< Specifies the SWP Voltage Class.
00068                                           This parameter can be a value of @ref SWPMI_Voltage_Class */
00069
00070   uint32_t BitRate;                  /*!< Specifies the SWPMI Bitrate.
00071                                           This parameter must be a number between 0 and 63.
00072                                           The Bitrate is computed using the following formula:
00073                                           SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
00074                                           */
00075
00076   uint32_t TxBufferingMode;          /*!< Specifies the transmission buffering mode.
00077                                           This parameter can be a value of @ref SWPMI_Tx_Buffering_Mode */
00078
00079   uint32_t RxBufferingMode;          /*!< Specifies the reception buffering mode.
00080                                           This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */
00081
00082 }SWPMI_InitTypeDef;
00083
00084
00085 /**
00086   * @brief HAL SWPMI State structures definition
00087   */
00088 typedef enum
00089 {
00090   HAL_SWPMI_STATE_RESET             = 0x00,    /*!< Peripheral Reset state                             */
00091   HAL_SWPMI_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
00092   HAL_SWPMI_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
00093   HAL_SWPMI_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
00094   HAL_SWPMI_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
00095   HAL_SWPMI_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
00096   HAL_SWPMI_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
00097   HAL_SWPMI_STATE_ERROR             = 0x04     /*!< Error                                              */
00098 }HAL_SWPMI_StateTypeDef;
00099
00100 /**
00101   * @brief  SWPMI handle Structure definition
00102   */
00103 typedef struct
00104 {
00105   SWPMI_TypeDef                  *Instance;     /* SWPMI registers base address         */
00106
00107   SWPMI_InitTypeDef              Init;          /* SWMPI communication parameters       */
00108
00109   uint32_t                       *pTxBuffPtr;   /* Pointer to SWPMI Tx transfer Buffer  */
00110
00111   uint32_t                       TxXferSize;    /* SWPMI Tx Transfer size               */
00112
00113   uint32_t                       TxXferCount;   /* SWPMI Tx Transfer Counter            */
00114
00115   uint32_t                       *pRxBuffPtr;   /* Pointer to SWPMI Rx transfer Buffer  */
00116
00117   uint32_t                       RxXferSize;    /* SWPMI Rx Transfer size               */
00118
00119   uint32_t                       RxXferCount;   /* SWPMI Rx Transfer Counter            */
00120
00121   DMA_HandleTypeDef              *hdmatx;       /* SWPMI Tx DMA Handle parameters       */
00122
00123   DMA_HandleTypeDef              *hdmarx;       /* SWPMI Rx DMA Handle parameters       */
00124
00125   HAL_LockTypeDef                Lock;          /* SWPMI object                         */
00126
00127   __IO HAL_SWPMI_StateTypeDef    State;         /* SWPMI communication state            */
00128
00129   __IO uint32_t                  ErrorCode;     /* SWPMI Error code                     */
00130
00131 }SWPMI_HandleTypeDef;
00132
00133 /**
00134   * @}
00135   */
00136
00137 /* Exported constants --------------------------------------------------------*/
00138 /** @defgroup SWPMI_Exported_Constants SWPMI Exported Constants
00139   * @{
00140   */
00141
00142 /**
00143   * @defgroup SWPMI_Error_Code SWPMI Error Code Bitmap
00144   * @{
00145   */
00146 #define HAL_SWPMI_ERROR_NONE                 ((uint32_t)0x00000000) /*!< No error             */
00147 #define HAL_SWPMI_ERROR_CRC                  ((uint32_t)0x00000004) /*!< frame error          */
00148 #define HAL_SWPMI_ERROR_OVR                  ((uint32_t)0x00000008) /*!< Overrun error        */
00149 #define HAL_SWPMI_ERROR_UDR                  ((uint32_t)0x0000000C) /*!< Underrun error       */
00150 #define HAL_SWPMI_ERROR_DMA                  ((uint32_t)0x00000010) /*!< DMA transfer error   */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup SWPMI_Voltage_Class SWPMI Voltage Class
00156   * @{
00157   */
00158 #define SWPMI_VOLTAGE_CLASS_C                ((uint32_t)0x00000000)
00159 #define SWPMI_VOLTAGE_CLASS_B                SWPMI_OR_CLASS
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup SWPMI_Tx_Buffering_Mode SWPMI Tx Buffering Mode
00165   * @{
00166   */
00167 #define SWPMI_TX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)
00168 #define SWPMI_TX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)
00169 #define SWPMI_TX_MULTI_SOFTWAREBUFFER        SWPMI_CR_TXMODE
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup SWPMI_Rx_Buffering_Mode SWPMI Rx Buffering Mode
00175   * @{
00176   */
00177 #define SWPMI_RX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)
00178 #define SWPMI_RX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)
00179 #define SWPMI_RX_MULTI_SOFTWAREBUFFER        SWPMI_CR_RXMODE
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup SWPMI_Flags SWPMI Status Flags
00185   *        Elements values convention: 0xXXXXXXXX
00186   *           - 0xXXXXXXXX  : Flag mask in the ISR register
00187   * @{
00188   */
00189 #define SWPMI_FLAG_RXBFF                 SWPMI_ISR_RXBFF
00190 #define SWPMI_FLAG_TXBEF                 SWPMI_ISR_TXBEF
00191 #define SWPMI_FLAG_RXBERF                SWPMI_ISR_RXBERF
00192 #define SWPMI_FLAG_RXOVRF                SWPMI_ISR_RXOVRF
00193 #define SWPMI_FLAG_TXUNRF                SWPMI_ISR_TXUNRF
00194 #define SWPMI_FLAG_RXNE                  SWPMI_ISR_RXNE
00195 #define SWPMI_FLAG_TXE                   SWPMI_ISR_TXE
00196 #define SWPMI_FLAG_TCF                   SWPMI_ISR_TCF
00197 #define SWPMI_FLAG_SRF                   SWPMI_ISR_SRF
00198 #define SWPMI_FLAG_SUSP                  SWPMI_ISR_SUSP
00199 #define SWPMI_FLAG_DEACTF                SWPMI_ISR_DEACTF
00200 /**
00201   * @}
00202   */
00203
00204 /** @defgroup SWPMI_Interrupt_definition SWPMI Interrupts Definition
00205   *        Elements values convention: 0xXXXX
00206   *           - 0xXXXX  : Flag mask in the IER register
00207   * @{
00208   */
00209 #define SWPMI_IT_SRIE                    SWPMI_IER_SRIE
00210 #define SWPMI_IT_TCIE                    SWPMI_IER_TCIE
00211 #define SWPMI_IT_TIE                     SWPMI_IER_TIE
00212 #define SWPMI_IT_RIE                     SWPMI_IER_RIE
00213 #define SWPMI_IT_TXUNRIE                 SWPMI_IER_TXUNRIE
00214 #define SWPMI_IT_RXOVRIE                 SWPMI_IER_RXOVRIE
00215 #define SWPMI_IT_RXBERIE                 SWPMI_IER_RXBERIE
00216 #define SWPMI_IT_TXBEIE                  SWPMI_IER_TXBEIE
00217 #define SWPMI_IT_RXBFIE                  SWPMI_IER_RXBFIE
00218 /**
00219   * @}
00220   */
00221
00222 /**
00223   * @}
00224   */
00225
00226 /* Exported macros -----------------------------------------------------------*/
00227 /** @defgroup SWPMI_Exported_Macros SWPMI Exported Macros
00228   * @{
00229   */
00230
00231 /** @brief Reset SWPMI handle state.
00232   * @param  __HANDLE__: specifies the SWPMI Handle.
00233   * @retval None
00234   */
00235 #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
00236
00237 /**
00238   * @brief  Enable the SWPMI peripheral.
00239   * @param  __HANDLE__: SWPMI handle
00240   * @retval None
00241   */
00242 #define __HAL_SWPMI_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
00243
00244 /**
00245   * @brief  Disable the SWPMI peripheral.
00246   * @param  __HANDLE__: SWPMI handle
00247   * @retval None
00248   */
00249 #define __HAL_SWPMI_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
00250
00251 /** @brief  Check whether the specified SWPMI flag is set or not.
00252   * @param  __HANDLE__: specifies the SWPMI Handle.
00253   * @param  __FLAG__: specifies the flag to check.
00254   *        This parameter can be one of the following values:
00255   *            @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
00256   *            @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
00257   *            @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
00258   *            @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
00259   *            @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
00260   *            @arg SWPMI_FLAG_RXNE : Receive data register not empty.
00261   *            @arg SWPMI_FLAG_TXE : Transmit data register empty.
00262   *            @arg SWPMI_FLAG_TCF : Transfer complete flag.
00263   *            @arg SWPMI_FLAG_SRF : Slave resume flag.
00264   *            @arg SWPMI_FLAG_SUSP : SUSPEND flag.
00265   *            @arg SWPMI_FLAG_DEACTF : DEACTIVATED flag.
00266   * @retval The new state of __FLAG__ (TRUE or FALSE).
00267   */
00268 #define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
00269
00270 /** @brief  Clear the specified SWPMI ISR flag.
00271   * @param  __HANDLE__: specifies the SWPMI Handle.
00272   * @param  __FLAG__: specifies the flag to clear.
00273   *        This parameter can be one of the following values:
00274   *            @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
00275   *            @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
00276   *            @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
00277   *            @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
00278   *            @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
00279   *            @arg SWPMI_FLAG_TCF : Transfer complete flag.
00280   *            @arg SWPMI_FLAG_SRF : Slave resume flag.
00281   * @retval None
00282   */
00283 #define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
00284
00285 /** @brief  Enable the specified SWPMI interrupt.
00286   * @param  __HANDLE__: specifies the SWPMI Handle.
00287   * @param  __INTERRUPT__: specifies the SWPMI interrupt source to enable.
00288   *          This parameter can be one of the following values:
00289   *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
00290   *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
00291   *            @arg SWPMI_IT_TIE :  Transmit interrupt.
00292   *            @arg SWPMI_IT_RIE :  Receive interrupt.
00293   *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
00294   *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
00295   *            @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
00296   *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
00297   *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
00298   * @retval None
00299   */
00300 #define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
00301
00302 /** @brief  Disable the specified SWPMI interrupt.
00303   * @param  __HANDLE__: specifies the SWPMI Handle.
00304   * @param  __INTERRUPT__: specifies the SWPMI interrupt source to disable.
00305   *          This parameter can be one of the following values:
00306   *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
00307   *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
00308   *            @arg SWPMI_IT_TIE :  Transmit interrupt.
00309   *            @arg SWPMI_IT_RIE :  Receive interrupt.
00310   *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
00311   *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
00312   *            @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
00313   *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
00314   *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
00315   * @retval None
00316   */
00317 #define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
00318
00319 /** @brief  Check whether the specified SWPMI interrupt has occurred or not.
00320   * @param  __HANDLE__: specifies the SWPMI Handle.
00321   * @param  __IT__: specifies the SWPMI interrupt to check.
00322   *          This parameter can be one of the following values:
00323   *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
00324   *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
00325   *            @arg SWPMI_IT_TIE :  Transmit interrupt.
00326   *            @arg SWPMI_IT_RIE :  Receive interrupt.
00327   *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
00328   *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
00329   *            @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
00330   *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
00331   *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
00332   * @retval The new state of __IT__ (TRUE or FALSE).
00333   */
00334 #define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__)  (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
00335
00336 /** @brief  Check whether the specified SWPMI interrupt source is enabled or not.
00337   * @param  __HANDLE__: specifies the SWPMI Handle.
00338   * @param  __IT__: specifies the SWPMI interrupt source to check.
00339   *          This parameter can be one of the following values:
00340   *            @arg SWPMI_IT_SRIE : Slave resume interrupt.
00341   *            @arg SWPMI_IT_TCIE : Transmit complete interrupt.
00342   *            @arg SWPMI_IT_TIE :  Transmit interrupt.
00343   *            @arg SWPMI_IT_RIE :  Receive interrupt.
00344   *            @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
00345   *            @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
00346   *            @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
00347   *            @arg SWPMI_IT_TXBEIE :  Transmit buffer empty interrupt.
00348   *            @arg SWPMI_IT_RXBFIE :  Receive buffer full interrupt.
00349   * @retval The new state of __IT__ (TRUE or FALSE).
00350   */
00351 #define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
00352
00353 /**
00354   * @}
00355   */
00356
00357 /* Exported functions --------------------------------------------------------*/
00358 /** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
00359   * @{
00360   */
00361 /* Initialization/de-initialization functions  ********************************/
00362 HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi);
00363 HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi);
00364 void              HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi);
00365 void              HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi);
00366
00367 /* IO operation functions *****************************************************/
00368 HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00369 HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
00370 HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00371 HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00372 HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00373 HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
00374 HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi);
00375 HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi);
00376 HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi);
00377 void              HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi);
00378 void              HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00379 void              HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00380 void              HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00381 void              HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
00382 void              HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi);
00383
00384 /* Peripheral Control and State functions  ************************************/
00385 HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi);
00386 uint32_t               HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi);
00387
00388 /**
00389   * @}
00390   */
00391
00392 /* Private types -------------------------------------------------------------*/
00393 /** @defgroup SWPMI_Private_Types SWPMI Private Types
00394   * @{
00395   */
00396
00397 /**
00398   * @}
00399   */
00400
00401 /* Private variables ---------------------------------------------------------*/
00402 /** @defgroup SWPMI_Private_Variables SWPMI Private Variables
00403   * @{
00404   */
00405
00406 /**
00407   * @}
00408   */
00409
00410 /* Private constants ---------------------------------------------------------*/
00411 /** @defgroup SWPMI_Private_Constants SWPMI Private Constants
00412   * @{
00413   */
00414
00415 /**
00416   * @}
00417   */
00418
00419 /* Private macros ------------------------------------------------------------*/
00420 /** @defgroup SWPMI_Private_Macros SWPMI Private Macros
00421   * @{
00422   */
00423
00424
00425 #define IS_SWPMI_VOLTAGE_CLASS(__CLASS__)    (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
00426                                               ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))
00427
00428 #define IS_SWPMI_BITRATE_VALUE(__VALUE__)    (((__VALUE__) <= 63))
00429
00430
00431 #define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
00432                                               ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))
00433
00434
00435 #define IS_SWPMI_RX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
00436                                               ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))
00437
00438 /**
00439   * @}
00440   */
00441
00442 /**
00443   * @}
00444   */
00445
00446 /**
00447   * @}
00448   */
00449
00450 #ifdef __cplusplus
00451 }
00452 #endif
00453
00454 #endif /* __STM32L4xx_HAL_SWPMI_H */
00455
00456 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tim.c Source File

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stm32l4xx_hal_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   TIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer (TIM) peripheral:
00010   *           + Time Base Initialization
00011   *           + Time Base Start
00012   *           + Time Base Start Interruption
00013   *           + Time Base Start DMA
00014   *           + Time Output Compare/PWM Initialization
00015   *           + Time Output Compare/PWM Channel Configuration
00016   *           + Time Output Compare/PWM  Start
00017   *           + Time Output Compare/PWM  Start Interruption
00018   *           + Time Output Compare/PWM Start DMA
00019   *           + Time Input Capture Initialization
00020   *           + Time Input Capture Channel Configuration
00021   *           + Time Input Capture Start
00022   *           + Time Input Capture Start Interruption
00023   *           + Time Input Capture Start DMA
00024   *           + Time One Pulse Initialization
00025   *           + Time One Pulse Channel Configuration
00026   *           + Time One Pulse Start
00027   *           + Time Encoder Interface Initialization
00028   *           + Time Encoder Interface Start
00029   *           + Time Encoder Interface Start Interruption
00030   *           + Time Encoder Interface Start DMA
00031   *           + Commutation Event configuration with Interruption and DMA
00032   *           + Time OCRef clear configuration
00033   *           + Time External Clock configuration
00034   @verbatim
00035   ==============================================================================
00036                       ##### TIMER Generic features #####
00037   ==============================================================================
00038   [..] The Timer features include:
00039        (#) 16-bit up, down, up/down auto-reload counter.
00040        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
00041            counter clock frequency either by any factor between 1 and 65536.
00042        (#) Up to 4 independent channels for:
00043            (++) Input Capture
00044            (++) Output Compare
00045            (++) PWM generation (Edge and Center-aligned Mode)
00046            (++) One-pulse mode output
00047
00048             ##### How to use this driver #####
00049   ==============================================================================
00050     [..]
00051      (#) Initialize the TIM low level resources by implementing the following functions
00052          depending on the selected feature:
00053            (++) Time Base : HAL_TIM_Base_MspInit()
00054            (++) Input Capture : HAL_TIM_IC_MspInit()
00055            (++) Output Compare : HAL_TIM_OC_MspInit()
00056            (++) PWM generation : HAL_TIM_PWM_MspInit()
00057            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00058            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00059
00060      (#) Initialize the TIM low level resources :
00061         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00062         (##) TIM pins configuration
00063             (+++) Enable the clock for the TIM GPIOs using the following function:
00064              __HAL_RCC_GPIOx_CLK_ENABLE();
00065             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00066
00067      (#) The external Clock can be configured, if needed (the default clock is the
00068          internal clock from the APBx), using the following function:
00069          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00070          any start function.
00071
00072      (#) Configure the TIM in the desired functioning mode using one of the
00073        Initialization function of this driver:
00074        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
00075        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
00076             Output Compare signal.
00077        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
00078             PWM signal.
00079        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
00080             external signal.
00081          (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
00082               in One Pulse Mode.
00083        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00084
00085      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00086            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
00087            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
00088            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
00089            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
00090            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
00091            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00092
00093      (#) The DMA Burst is managed with the two following functions:
00094          HAL_TIM_DMABurst_WriteStart()
00095          HAL_TIM_DMABurst_ReadStart()
00096
00097   @endverbatim
00098   ******************************************************************************
00099   * @attention
00100   *
00101   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00102   *
00103   * Redistribution and use in source and binary forms, with or without modification,
00104   * are permitted provided that the following conditions are met:
00105   *   1. Redistributions of source code must retain the above copyright notice,
00106   *      this list of conditions and the following disclaimer.
00107   *   2. Redistributions in binary form must reproduce the above copyright notice,
00108   *      this list of conditions and the following disclaimer in the documentation
00109   *      and/or other materials provided with the distribution.
00110   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00111   *      may be used to endorse or promote products derived from this software
00112   *      without specific prior written permission.
00113   *
00114   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00115   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00116   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00117   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00118   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00119   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00120   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00121   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00122   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00123   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00124   *
00125   ******************************************************************************
00126   */
00127
00128 /* Includes ------------------------------------------------------------------*/
00129 #include "stm32l4xx_hal.h"
00130
00131 /** @addtogroup STM32L4xx_HAL_Driver
00132   * @{
00133   */
00134
00135 /** @defgroup TIM TIM
00136   * @brief TIM HAL module driver
00137   * @{
00138   */
00139
00140 #ifdef HAL_TIM_MODULE_ENABLED
00141
00142 /* Private typedef -----------------------------------------------------------*/
00143 /* Private define ------------------------------------------------------------*/
00144 /* Private macro -------------------------------------------------------------*/
00145 /* Private variables ---------------------------------------------------------*/
00146 /* Private function prototypes -----------------------------------------------*/
00147 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00148 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00149 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00150 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00151 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00152 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00153 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00154                        uint32_t TIM_ICFilter);
00155 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00156 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00157                        uint32_t TIM_ICFilter);
00158 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00159                        uint32_t TIM_ICFilter);
00160 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
00161 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00162 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00163 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00164                                      TIM_SlaveConfigTypeDef * sSlaveConfig);
00165 /* Exported functions --------------------------------------------------------*/
00166
00167 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00168   * @{
00169   */
00170
00171 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
00172  *  @brief    Time Base functions
00173  *
00174 @verbatim
00175   ==============================================================================
00176               ##### Time Base functions #####
00177   ==============================================================================
00178   [..]
00179     This section provides functions allowing to:
00180     (+) Initialize and configure the TIM base.
00181     (+) De-initialize the TIM base.
00182     (+) Start the Time Base.
00183     (+) Stop the Time Base.
00184     (+) Start the Time Base and enable interrupt.
00185     (+) Stop the Time Base and disable interrupt.
00186     (+) Start the Time Base and enable DMA transfer.
00187     (+) Stop the Time Base and disable DMA transfer.
00188
00189 @endverbatim
00190   * @{
00191   */
00192 /**
00193   * @brief  Initializes the TIM Time base Unit according to the specified
00194   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
00195   * @param  htim: TIM Base handle
00196   * @retval HAL status
00197   */
00198 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00199 {
00200   /* Check the TIM handle allocation */
00201   if(htim == NULL)
00202   {
00203     return HAL_ERROR;
00204   }
00205
00206   /* Check the parameters */
00207   assert_param(IS_TIM_INSTANCE(htim->Instance));
00208   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00209   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00210
00211   if(htim->State == HAL_TIM_STATE_RESET)
00212   {
00213     /* Allocate lock resource and initialize it */
00214     htim->Lock = HAL_UNLOCKED;
00215
00216     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00217     HAL_TIM_Base_MspInit(htim);
00218   }
00219
00220   /* Set the TIM state */
00221   htim->State= HAL_TIM_STATE_BUSY;
00222
00223   /* Set the Time Base configuration */
00224   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00225
00226   /* Initialize the TIM state*/
00227   htim->State= HAL_TIM_STATE_READY;
00228
00229   return HAL_OK;
00230 }
00231
00232 /**
00233   * @brief  DeInitialize the TIM Base peripheral
00234   * @param  htim: TIM Base handle
00235   * @retval HAL status
00236   */
00237 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00238 {
00239   /* Check the parameters */
00240   assert_param(IS_TIM_INSTANCE(htim->Instance));
00241
00242   htim->State = HAL_TIM_STATE_BUSY;
00243
00244   /* Disable the TIM Peripheral Clock */
00245   __HAL_TIM_DISABLE(htim);
00246
00247   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00248   HAL_TIM_Base_MspDeInit(htim);
00249
00250   /* Change TIM state */
00251   htim->State = HAL_TIM_STATE_RESET;
00252
00253   /* Release Lock */
00254   __HAL_UNLOCK(htim);
00255
00256   return HAL_OK;
00257 }
00258
00259 /**
00260   * @brief  Initializes the TIM Base MSP.
00261   * @param  htim: TIM handle
00262   * @retval None
00263   */
00264 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00265 {
00266   /* Prevent unused argument(s) compilation warning */
00267   UNUSED(htim);
00268
00269   /* NOTE : This function should not be modified, when the callback is needed,
00270             the HAL_TIM_Base_MspInit could be implemented in the user file
00271    */
00272 }
00273
00274 /**
00275   * @brief  DeInitialize TIM Base MSP.
00276   * @param  htim: TIM handle
00277   * @retval None
00278   */
00279 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00280 {
00281   /* Prevent unused argument(s) compilation warning */
00282   UNUSED(htim);
00283
00284   /* NOTE : This function should not be modified, when the callback is needed,
00285             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00286    */
00287 }
00288
00289
00290 /**
00291   * @brief  Starts the TIM Base generation.
00292   * @param  htim : TIM handle
00293   * @retval HAL status
00294 */
00295 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00296 {
00297   /* Check the parameters */
00298   assert_param(IS_TIM_INSTANCE(htim->Instance));
00299
00300   /* Set the TIM state */
00301   htim->State= HAL_TIM_STATE_BUSY;
00302
00303   /* Enable the Peripheral */
00304   __HAL_TIM_ENABLE(htim);
00305
00306   /* Change the TIM state*/
00307   htim->State= HAL_TIM_STATE_READY;
00308
00309   /* Return function status */
00310   return HAL_OK;
00311 }
00312
00313 /**
00314   * @brief  Stops the TIM Base generation.
00315   * @param  htim : TIM handle
00316   * @retval HAL status
00317 */
00318 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00319 {
00320   /* Check the parameters */
00321   assert_param(IS_TIM_INSTANCE(htim->Instance));
00322
00323   /* Set the TIM state */
00324   htim->State= HAL_TIM_STATE_BUSY;
00325
00326   /* Disable the Peripheral */
00327   __HAL_TIM_DISABLE(htim);
00328
00329   /* Change the TIM state*/
00330   htim->State= HAL_TIM_STATE_READY;
00331
00332   /* Return function status */
00333   return HAL_OK;
00334 }
00335
00336 /**
00337   * @brief  Starts the TIM Base generation in interrupt mode.
00338   * @param  htim : TIM handle
00339   * @retval HAL status
00340 */
00341 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00342 {
00343   /* Check the parameters */
00344   assert_param(IS_TIM_INSTANCE(htim->Instance));
00345
00346    /* Enable the TIM Update interrupt */
00347    __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00348
00349    /* Enable the Peripheral */
00350   __HAL_TIM_ENABLE(htim);
00351
00352   /* Return function status */
00353   return HAL_OK;
00354 }
00355
00356 /**
00357   * @brief  Stops the TIM Base generation in interrupt mode.
00358   * @param  htim : TIM handle
00359   * @retval HAL status
00360 */
00361 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00362 {
00363   /* Check the parameters */
00364   assert_param(IS_TIM_INSTANCE(htim->Instance));
00365   /* Disable the TIM Update interrupt */
00366   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00367
00368   /* Disable the Peripheral */
00369   __HAL_TIM_DISABLE(htim);
00370
00371   /* Return function status */
00372   return HAL_OK;
00373 }
00374
00375 /**
00376   * @brief  Starts the TIM Base generation in DMA mode.
00377   * @param  htim : TIM handle
00378   * @param  pData: The source Buffer address.
00379   * @param  Length: The length of data to be transferred from memory to peripheral.
00380   * @retval HAL status
00381 */
00382 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00383 {
00384   /* Check the parameters */
00385   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00386
00387   if((htim->State == HAL_TIM_STATE_BUSY))
00388   {
00389      return HAL_BUSY;
00390   }
00391   else if((htim->State == HAL_TIM_STATE_READY))
00392   {
00393     if((pData == 0 ) && (Length > 0))
00394     {
00395       return HAL_ERROR;
00396     }
00397     else
00398     {
00399       htim->State = HAL_TIM_STATE_BUSY;
00400     }
00401   }
00402   /* Set the DMA Period elapsed callback */
00403   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00404
00405   /* Set the DMA error callback */
00406   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
00407
00408   /* Enable the DMA channel */
00409   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
00410
00411   /* Enable the TIM Update DMA request */
00412   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00413
00414   /* Enable the Peripheral */
00415   __HAL_TIM_ENABLE(htim);
00416
00417   /* Return function status */
00418   return HAL_OK;
00419 }
00420
00421 /**
00422   * @brief  Stops the TIM Base generation in DMA mode.
00423   * @param  htim : TIM handle
00424   * @retval HAL status
00425 */
00426 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00427 {
00428   /* Check the parameters */
00429   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00430
00431   /* Disable the TIM Update DMA request */
00432   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00433
00434   /* Disable the Peripheral */
00435   __HAL_TIM_DISABLE(htim);
00436
00437   /* Change the htim state */
00438   htim->State = HAL_TIM_STATE_READY;
00439
00440   /* Return function status */
00441   return HAL_OK;
00442 }
00443
00444 /**
00445   * @}
00446   */
00447
00448 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
00449  *  @brief    Time Output Compare functions
00450  *
00451 @verbatim
00452   ==============================================================================
00453                   ##### Time Output Compare functions #####
00454   ==============================================================================
00455   [..]
00456     This section provides functions allowing to:
00457     (+) Initialize and configure the TIM Output Compare.
00458     (+) De-initialize the TIM Output Compare.
00459     (+) Start the Time Output Compare.
00460     (+) Stop the Time Output Compare.
00461     (+) Start the Time Output Compare and enable interrupt.
00462     (+) Stop the Time Output Compare and disable interrupt.
00463     (+) Start the Time Output Compare and enable DMA transfer.
00464     (+) Stop the Time Output Compare and disable DMA transfer.
00465
00466 @endverbatim
00467   * @{
00468   */
00469 /**
00470   * @brief  Initializes the TIM Output Compare according to the specified
00471   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
00472   * @param  htim: TIM Output Compare handle
00473   * @retval HAL status
00474   */
00475 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
00476 {
00477   /* Check the TIM handle allocation */
00478   if(htim == NULL)
00479   {
00480     return HAL_ERROR;
00481   }
00482
00483   /* Check the parameters */
00484   assert_param(IS_TIM_INSTANCE(htim->Instance));
00485   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00486   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00487
00488   if(htim->State == HAL_TIM_STATE_RESET)
00489   {
00490     /* Allocate lock resource and initialize it */
00491     htim->Lock = HAL_UNLOCKED;
00492
00493     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00494     HAL_TIM_OC_MspInit(htim);
00495   }
00496
00497   /* Set the TIM state */
00498   htim->State= HAL_TIM_STATE_BUSY;
00499
00500   /* Init the base time for the Output Compare */
00501   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00502
00503   /* Initialize the TIM state*/
00504   htim->State= HAL_TIM_STATE_READY;
00505
00506   return HAL_OK;
00507 }
00508
00509 /**
00510   * @brief  DeInitialize the TIM peripheral
00511   * @param  htim: TIM Output Compare handle
00512   * @retval HAL status
00513   */
00514 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00515 {
00516   /* Check the parameters */
00517   assert_param(IS_TIM_INSTANCE(htim->Instance));
00518
00519    htim->State = HAL_TIM_STATE_BUSY;
00520
00521   /* Disable the TIM Peripheral Clock */
00522   __HAL_TIM_DISABLE(htim);
00523
00524   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00525   HAL_TIM_OC_MspDeInit(htim);
00526
00527   /* Change TIM state */
00528   htim->State = HAL_TIM_STATE_RESET;
00529
00530   /* Release Lock */
00531   __HAL_UNLOCK(htim);
00532
00533   return HAL_OK;
00534 }
00535
00536 /**
00537   * @brief  Initializes the TIM Output Compare MSP.
00538   * @param  htim: TIM handle
00539   * @retval None
00540   */
00541 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00542 {
00543   /* Prevent unused argument(s) compilation warning */
00544   UNUSED(htim);
00545
00546   /* NOTE : This function should not be modified, when the callback is needed,
00547             the HAL_TIM_OC_MspInit could be implemented in the user file
00548    */
00549 }
00550
00551 /**
00552   * @brief  DeInitialize TIM Output Compare MSP.
00553   * @param  htim: TIM handle
00554   * @retval None
00555   */
00556 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00557 {
00558   /* Prevent unused argument(s) compilation warning */
00559   UNUSED(htim);
00560
00561   /* NOTE : This function should not be modified, when the callback is needed,
00562             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00563    */
00564 }
00565
00566 /**
00567   * @brief  Starts the TIM Output Compare signal generation.
00568   * @param  htim : TIM Output Compare handle
00569   * @param  Channel : TIM Channel to be enabled
00570   *          This parameter can be one of the following values:
00571   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00572   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00573   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00574   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00575   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00576   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00577   * @retval HAL status
00578 */
00579 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00580 {
00581   /* Check the parameters */
00582   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00583
00584   /* Enable the Output compare channel */
00585   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00586
00587   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00588   {
00589     /* Enable the main output */
00590     __HAL_TIM_MOE_ENABLE(htim);
00591   }
00592
00593   /* Enable the Peripheral */
00594   __HAL_TIM_ENABLE(htim);
00595
00596   /* Return function status */
00597   return HAL_OK;
00598 }
00599
00600 /**
00601   * @brief  Stops the TIM Output Compare signal generation.
00602   * @param  htim : TIM handle
00603   * @param  Channel : TIM Channel to be disabled
00604   *          This parameter can be one of the following values:
00605   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00606   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00607   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00608   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00609   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00610   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00611   * @retval HAL status
00612 */
00613 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00614 {
00615   /* Check the parameters */
00616   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00617
00618   /* Disable the Output compare channel */
00619   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00620
00621   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00622   {
00623     /* Disable the Main Ouput */
00624     __HAL_TIM_MOE_DISABLE(htim);
00625   }
00626
00627   /* Disable the Peripheral */
00628   __HAL_TIM_DISABLE(htim);
00629
00630   /* Return function status */
00631   return HAL_OK;
00632 }
00633
00634 /**
00635   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00636   * @param  htim : TIM OC handle
00637   * @param  Channel : TIM Channel to be enabled
00638   *          This parameter can be one of the following values:
00639   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00640   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00641   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00642   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00643   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00644   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00645   * @retval HAL status
00646 */
00647 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00648 {
00649   /* Check the parameters */
00650   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00651
00652   switch (Channel)
00653   {
00654     case TIM_CHANNEL_1:
00655     {
00656       /* Enable the TIM Capture/Compare 1 interrupt */
00657       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00658     }
00659     break;
00660
00661     case TIM_CHANNEL_2:
00662     {
00663       /* Enable the TIM Capture/Compare 2 interrupt */
00664       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00665     }
00666     break;
00667
00668     case TIM_CHANNEL_3:
00669     {
00670       /* Enable the TIM Capture/Compare 3 interrupt */
00671       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00672     }
00673     break;
00674
00675     case TIM_CHANNEL_4:
00676     {
00677       /* Enable the TIM Capture/Compare 4 interrupt */
00678       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00679     }
00680     break;
00681
00682     default:
00683     break;
00684   }
00685
00686   /* Enable the Output compare channel */
00687   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00688
00689   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00690   {
00691     /* Enable the main output */
00692     __HAL_TIM_MOE_ENABLE(htim);
00693   }
00694
00695   /* Enable the Peripheral */
00696   __HAL_TIM_ENABLE(htim);
00697
00698   /* Return function status */
00699   return HAL_OK;
00700 }
00701
00702 /**
00703   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00704   * @param  htim : TIM Output Compare handle
00705   * @param  Channel : TIM Channel to be disabled
00706   *          This parameter can be one of the following values:
00707   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00708   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00709   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00710   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00711   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00712   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00713   * @retval HAL status
00714 */
00715 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00716 {
00717   /* Check the parameters */
00718   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00719
00720   switch (Channel)
00721   {
00722     case TIM_CHANNEL_1:
00723     {
00724       /* Disable the TIM Capture/Compare 1 interrupt */
00725       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00726     }
00727     break;
00728
00729     case TIM_CHANNEL_2:
00730     {
00731       /* Disable the TIM Capture/Compare 2 interrupt */
00732       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00733     }
00734     break;
00735
00736     case TIM_CHANNEL_3:
00737     {
00738       /* Disable the TIM Capture/Compare 3 interrupt */
00739       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00740     }
00741     break;
00742
00743     case TIM_CHANNEL_4:
00744     {
00745       /* Disable the TIM Capture/Compare 4 interrupt */
00746       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00747     }
00748     break;
00749
00750     default:
00751     break;
00752   }
00753
00754   /* Disable the Output compare channel */
00755   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00756
00757   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00758   {
00759     /* Disable the Main Ouput */
00760     __HAL_TIM_MOE_DISABLE(htim);
00761   }
00762
00763   /* Disable the Peripheral */
00764   __HAL_TIM_DISABLE(htim);
00765
00766   /* Return function status */
00767   return HAL_OK;
00768 }
00769
00770 /**
00771   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
00772   * @param  htim : TIM Output Compare handle
00773   * @param  Channel : TIM Channel to be enabled
00774   *          This parameter can be one of the following values:
00775   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00776   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00777   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00778   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00779   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00780   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00781   * @param  pData: The source Buffer address.
00782   * @param  Length: The length of data to be transferred from memory to TIM peripheral
00783   * @retval HAL status
00784 */
00785 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00786 {
00787   /* Check the parameters */
00788   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00789
00790   if((htim->State == HAL_TIM_STATE_BUSY))
00791   {
00792      return HAL_BUSY;
00793   }
00794   else if((htim->State == HAL_TIM_STATE_READY))
00795   {
00796     if(((uint32_t)pData == 0 ) && (Length > 0))
00797     {
00798       return HAL_ERROR;
00799     }
00800     else
00801     {
00802       htim->State = HAL_TIM_STATE_BUSY;
00803     }
00804   }
00805   switch (Channel)
00806   {
00807     case TIM_CHANNEL_1:
00808     {
00809       /* Set the DMA Period elapsed callback */
00810       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00811
00812       /* Set the DMA error callback */
00813       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00814
00815       /* Enable the DMA channel */
00816       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00817
00818       /* Enable the TIM Capture/Compare 1 DMA request */
00819       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00820     }
00821     break;
00822
00823     case TIM_CHANNEL_2:
00824     {
00825       /* Set the DMA Period elapsed callback */
00826       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00827
00828       /* Set the DMA error callback */
00829       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00830
00831       /* Enable the DMA channel */
00832       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00833
00834       /* Enable the TIM Capture/Compare 2 DMA request */
00835       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00836     }
00837     break;
00838
00839     case TIM_CHANNEL_3:
00840     {
00841       /* Set the DMA Period elapsed callback */
00842       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00843
00844       /* Set the DMA error callback */
00845       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00846
00847       /* Enable the DMA channel */
00848       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00849
00850       /* Enable the TIM Capture/Compare 3 DMA request */
00851       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00852     }
00853     break;
00854
00855     case TIM_CHANNEL_4:
00856     {
00857      /* Set the DMA Period elapsed callback */
00858       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
00859
00860       /* Set the DMA error callback */
00861       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
00862
00863       /* Enable the DMA channel */
00864       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00865
00866       /* Enable the TIM Capture/Compare 4 DMA request */
00867       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00868     }
00869     break;
00870
00871   default:
00872     break;
00873   }
00874
00875   /* Enable the Output compare channel */
00876   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00877
00878   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00879   {
00880     /* Enable the main output */
00881     __HAL_TIM_MOE_ENABLE(htim);
00882   }
00883
00884   /* Enable the Peripheral */
00885   __HAL_TIM_ENABLE(htim);
00886
00887   /* Return function status */
00888   return HAL_OK;
00889 }
00890
00891 /**
00892   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
00893   * @param  htim : TIM Output Compare handle
00894   * @param  Channel : TIM Channel to be disabled
00895   *          This parameter can be one of the following values:
00896   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00897   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00898   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00899   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00900   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00901   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00902   * @retval HAL status
00903 */
00904 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00905 {
00906   /* Check the parameters */
00907   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00908
00909   switch (Channel)
00910   {
00911     case TIM_CHANNEL_1:
00912     {
00913       /* Disable the TIM Capture/Compare 1 DMA request */
00914       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00915     }
00916     break;
00917
00918     case TIM_CHANNEL_2:
00919     {
00920       /* Disable the TIM Capture/Compare 2 DMA request */
00921       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00922     }
00923     break;
00924
00925     case TIM_CHANNEL_3:
00926     {
00927       /* Disable the TIM Capture/Compare 3 DMA request */
00928       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00929     }
00930     break;
00931
00932     case TIM_CHANNEL_4:
00933     {
00934       /* Disable the TIM Capture/Compare 4 interrupt */
00935       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00936     }
00937     break;
00938
00939     default:
00940     break;
00941   }
00942
00943   /* Disable the Output compare channel */
00944   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00945
00946   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00947   {
00948     /* Disable the Main Ouput */
00949     __HAL_TIM_MOE_DISABLE(htim);
00950   }
00951
00952   /* Disable the Peripheral */
00953   __HAL_TIM_DISABLE(htim);
00954
00955   /* Change the htim state */
00956   htim->State = HAL_TIM_STATE_READY;
00957
00958   /* Return function status */
00959   return HAL_OK;
00960 }
00961
00962 /**
00963   * @}
00964   */
00965
00966 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
00967  *  @brief    Time PWM functions
00968  *
00969 @verbatim
00970   ==============================================================================
00971                           ##### Time PWM functions #####
00972   ==============================================================================
00973   [..]
00974     This section provides functions allowing to:
00975     (+) Initialize and configure the TIM OPWM.
00976     (+) De-initialize the TIM PWM.
00977     (+) Start the Time PWM.
00978     (+) Stop the Time PWM.
00979     (+) Start the Time PWM and enable interrupt.
00980     (+) Stop the Time PWM and disable interrupt.
00981     (+) Start the Time PWM and enable DMA transfer.
00982     (+) Stop the Time PWM and disable DMA transfer.
00983
00984 @endverbatim
00985   * @{
00986   */
00987 /**
00988   * @brief  Initializes the TIM PWM Time Base according to the specified
00989   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
00990   * @param  htim: TIM handle
00991   * @retval HAL status
00992   */
00993 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
00994 {
00995   /* Check the TIM handle allocation */
00996   if(htim == NULL)
00997   {
00998     return HAL_ERROR;
00999   }
01000
01001   /* Check the parameters */
01002   assert_param(IS_TIM_INSTANCE(htim->Instance));
01003   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01004   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01005
01006   if(htim->State == HAL_TIM_STATE_RESET)
01007   {
01008     /* Allocate lock resource and initialize it */
01009     htim->Lock = HAL_UNLOCKED;
01010
01011     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01012     HAL_TIM_PWM_MspInit(htim);
01013   }
01014
01015   /* Set the TIM state */
01016   htim->State= HAL_TIM_STATE_BUSY;
01017
01018   /* Init the base time for the PWM */
01019   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01020
01021   /* Initialize the TIM state*/
01022   htim->State= HAL_TIM_STATE_READY;
01023
01024   return HAL_OK;
01025 }
01026
01027 /**
01028   * @brief  DeInitialize the TIM peripheral
01029   * @param  htim: TIM handle
01030   * @retval HAL status
01031   */
01032 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01033 {
01034   /* Check the parameters */
01035   assert_param(IS_TIM_INSTANCE(htim->Instance));
01036
01037   htim->State = HAL_TIM_STATE_BUSY;
01038
01039   /* Disable the TIM Peripheral Clock */
01040   __HAL_TIM_DISABLE(htim);
01041
01042   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01043   HAL_TIM_PWM_MspDeInit(htim);
01044
01045   /* Change TIM state */
01046   htim->State = HAL_TIM_STATE_RESET;
01047
01048   /* Release Lock */
01049   __HAL_UNLOCK(htim);
01050
01051   return HAL_OK;
01052 }
01053
01054 /**
01055   * @brief  Initializes the TIM PWM MSP.
01056   * @param  htim: TIM handle
01057   * @retval None
01058   */
01059 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01060 {
01061   /* Prevent unused argument(s) compilation warning */
01062   UNUSED(htim);
01063
01064   /* NOTE : This function should not be modified, when the callback is needed,
01065             the HAL_TIM_PWM_MspInit could be implemented in the user file
01066    */
01067 }
01068
01069 /**
01070   * @brief  DeInitialize TIM PWM MSP.
01071   * @param  htim: TIM handle
01072   * @retval None
01073   */
01074 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01075 {
01076   /* Prevent unused argument(s) compilation warning */
01077   UNUSED(htim);
01078
01079   /* NOTE : This function should not be modified, when the callback is needed,
01080             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01081    */
01082 }
01083
01084 /**
01085   * @brief  Starts the PWM signal generation.
01086   * @param  htim : TIM handle
01087   * @param  Channel : TIM Channels to be enabled
01088   *          This parameter can be one of the following values:
01089   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01090   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01091   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01092   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01093   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01094   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01095   * @retval HAL status
01096 */
01097 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01098 {
01099   /* Check the parameters */
01100   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01101
01102   /* Enable the Capture compare channel */
01103   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01104
01105   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01106   {
01107     /* Enable the main output */
01108     __HAL_TIM_MOE_ENABLE(htim);
01109   }
01110
01111   /* Enable the Peripheral */
01112   __HAL_TIM_ENABLE(htim);
01113
01114   /* Return function status */
01115   return HAL_OK;
01116 }
01117
01118 /**
01119   * @brief  Stops the PWM signal generation.
01120   * @param  htim : TIM handle
01121   * @param  Channel : TIM Channels to be disabled
01122   *          This parameter can be one of the following values:
01123   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01124   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01125   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01126   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01127   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01128   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01129   * @retval HAL status
01130 */
01131 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01132 {
01133   /* Check the parameters */
01134   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01135
01136   /* Disable the Capture compare channel */
01137   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01138
01139   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01140   {
01141     /* Disable the Main Ouput */
01142     __HAL_TIM_MOE_DISABLE(htim);
01143   }
01144
01145   /* Disable the Peripheral */
01146   __HAL_TIM_DISABLE(htim);
01147
01148   /* Change the htim state */
01149   htim->State = HAL_TIM_STATE_READY;
01150
01151   /* Return function status */
01152   return HAL_OK;
01153 }
01154
01155 /**
01156   * @brief  Starts the PWM signal generation in interrupt mode.
01157   * @param  htim : TIM handle
01158   * @param  Channel : TIM Channel to be enabled
01159   *          This parameter can be one of the following values:
01160   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01161   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01162   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01163   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01164   * @retval HAL status
01165 */
01166 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01167 {
01168   /* Check the parameters */
01169   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01170
01171   switch (Channel)
01172   {
01173     case TIM_CHANNEL_1:
01174     {
01175       /* Enable the TIM Capture/Compare 1 interrupt */
01176       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01177     }
01178     break;
01179
01180     case TIM_CHANNEL_2:
01181     {
01182       /* Enable the TIM Capture/Compare 2 interrupt */
01183       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01184     }
01185     break;
01186
01187     case TIM_CHANNEL_3:
01188     {
01189       /* Enable the TIM Capture/Compare 3 interrupt */
01190       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01191     }
01192     break;
01193
01194     case TIM_CHANNEL_4:
01195     {
01196       /* Enable the TIM Capture/Compare 4 interrupt */
01197       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01198     }
01199     break;
01200
01201     default:
01202     break;
01203   }
01204
01205   /* Enable the Capture compare channel */
01206   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01207
01208   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01209   {
01210     /* Enable the main output */
01211     __HAL_TIM_MOE_ENABLE(htim);
01212   }
01213
01214   /* Enable the Peripheral */
01215   __HAL_TIM_ENABLE(htim);
01216
01217   /* Return function status */
01218   return HAL_OK;
01219 }
01220
01221 /**
01222   * @brief  Stops the PWM signal generation in interrupt mode.
01223   * @param  htim : TIM handle
01224   * @param  Channel : TIM Channels to be disabled
01225   *          This parameter can be one of the following values:
01226   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01227   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01228   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01229   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01230   * @retval HAL status
01231 */
01232 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01233 {
01234   /* Check the parameters */
01235   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01236
01237   switch (Channel)
01238   {
01239     case TIM_CHANNEL_1:
01240     {
01241       /* Disable the TIM Capture/Compare 1 interrupt */
01242       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01243     }
01244     break;
01245
01246     case TIM_CHANNEL_2:
01247     {
01248       /* Disable the TIM Capture/Compare 2 interrupt */
01249       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01250     }
01251     break;
01252
01253     case TIM_CHANNEL_3:
01254     {
01255       /* Disable the TIM Capture/Compare 3 interrupt */
01256       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01257     }
01258     break;
01259
01260     case TIM_CHANNEL_4:
01261     {
01262       /* Disable the TIM Capture/Compare 4 interrupt */
01263       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01264     }
01265     break;
01266
01267     default:
01268     break;
01269   }
01270
01271   /* Disable the Capture compare channel */
01272   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01273
01274   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01275   {
01276     /* Disable the Main Ouput */
01277     __HAL_TIM_MOE_DISABLE(htim);
01278   }
01279
01280   /* Disable the Peripheral */
01281   __HAL_TIM_DISABLE(htim);
01282
01283   /* Return function status */
01284   return HAL_OK;
01285 }
01286
01287 /**
01288   * @brief  Starts the TIM PWM signal generation in DMA mode.
01289   * @param  htim : TIM handle
01290   * @param  Channel : TIM Channels to be enabled
01291   *          This parameter can be one of the following values:
01292   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01293   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01294   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01295   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01296   * @param  pData: The source Buffer address.
01297   * @param  Length: The length of data to be transferred from memory to TIM peripheral
01298   * @retval HAL status
01299 */
01300 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01301 {
01302   /* Check the parameters */
01303   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01304
01305   if((htim->State == HAL_TIM_STATE_BUSY))
01306   {
01307      return HAL_BUSY;
01308   }
01309   else if((htim->State == HAL_TIM_STATE_READY))
01310   {
01311     if(((uint32_t)pData == 0 ) && (Length > 0))
01312     {
01313       return HAL_ERROR;
01314     }
01315     else
01316     {
01317       htim->State = HAL_TIM_STATE_BUSY;
01318     }
01319   }
01320   switch (Channel)
01321   {
01322     case TIM_CHANNEL_1:
01323     {
01324       /* Set the DMA Period elapsed callback */
01325       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01326
01327       /* Set the DMA error callback */
01328       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01329
01330       /* Enable the DMA channel */
01331       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01332
01333       /* Enable the TIM Capture/Compare 1 DMA request */
01334       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01335     }
01336     break;
01337
01338     case TIM_CHANNEL_2:
01339     {
01340       /* Set the DMA Period elapsed callback */
01341       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01342
01343       /* Set the DMA error callback */
01344       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01345
01346       /* Enable the DMA channel */
01347       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01348
01349       /* Enable the TIM Capture/Compare 2 DMA request */
01350       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01351     }
01352     break;
01353
01354     case TIM_CHANNEL_3:
01355     {
01356       /* Set the DMA Period elapsed callback */
01357       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01358
01359       /* Set the DMA error callback */
01360       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01361
01362       /* Enable the DMA channel */
01363       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01364
01365       /* Enable the TIM Output Capture/Compare 3 request */
01366       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01367     }
01368     break;
01369
01370     case TIM_CHANNEL_4:
01371     {
01372      /* Set the DMA Period elapsed callback */
01373       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01374
01375       /* Set the DMA error callback */
01376       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01377
01378       /* Enable the DMA channel */
01379       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01380
01381       /* Enable the TIM Capture/Compare 4 DMA request */
01382       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01383     }
01384     break;
01385
01386     default:
01387     break;
01388   }
01389
01390   /* Enable the Capture compare channel */
01391   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01392
01393   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01394   {
01395     /* Enable the main output */
01396     __HAL_TIM_MOE_ENABLE(htim);
01397   }
01398
01399   /* Enable the Peripheral */
01400   __HAL_TIM_ENABLE(htim);
01401
01402   /* Return function status */
01403   return HAL_OK;
01404 }
01405
01406 /**
01407   * @brief  Stops the TIM PWM signal generation in DMA mode.
01408   * @param  htim : TIM handle
01409   * @param  Channel : TIM Channels to be disabled
01410   *          This parameter can be one of the following values:
01411   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01412   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01413   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01414   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01415   * @retval HAL status
01416 */
01417 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01418 {
01419   /* Check the parameters */
01420   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01421
01422   switch (Channel)
01423   {
01424     case TIM_CHANNEL_1:
01425     {
01426       /* Disable the TIM Capture/Compare 1 DMA request */
01427       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01428     }
01429     break;
01430
01431     case TIM_CHANNEL_2:
01432     {
01433       /* Disable the TIM Capture/Compare 2 DMA request */
01434       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01435     }
01436     break;
01437
01438     case TIM_CHANNEL_3:
01439     {
01440       /* Disable the TIM Capture/Compare 3 DMA request */
01441       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01442     }
01443     break;
01444
01445     case TIM_CHANNEL_4:
01446     {
01447       /* Disable the TIM Capture/Compare 4 interrupt */
01448       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01449     }
01450     break;
01451
01452     default:
01453     break;
01454   }
01455
01456   /* Disable the Capture compare channel */
01457   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01458
01459   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01460   {
01461     /* Disable the Main Ouput */
01462     __HAL_TIM_MOE_DISABLE(htim);
01463   }
01464
01465   /* Disable the Peripheral */
01466   __HAL_TIM_DISABLE(htim);
01467
01468   /* Change the htim state */
01469   htim->State = HAL_TIM_STATE_READY;
01470
01471   /* Return function status */
01472   return HAL_OK;
01473 }
01474
01475 /**
01476   * @}
01477   */
01478
01479 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
01480  *  @brief    Time Input Capture functions
01481  *
01482 @verbatim
01483   ==============================================================================
01484               ##### Time Input Capture functions #####
01485   ==============================================================================
01486  [..]
01487    This section provides functions allowing to:
01488    (+) Initialize and configure the TIM Input Capture.
01489    (+) De-initialize the TIM Input Capture.
01490    (+) Start the Time Input Capture.
01491    (+) Stop the Time Input Capture.
01492    (+) Start the Time Input Capture and enable interrupt.
01493    (+) Stop the Time Input Capture and disable interrupt.
01494    (+) Start the Time Input Capture and enable DMA transfer.
01495    (+) Stop the Time Input Capture and disable DMA transfer.
01496
01497 @endverbatim
01498   * @{
01499   */
01500 /**
01501   * @brief  Initializes the TIM Input Capture Time base according to the specified
01502   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
01503   * @param  htim: TIM Input Capture handle
01504   * @retval HAL status
01505   */
01506 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
01507 {
01508   /* Check the TIM handle allocation */
01509   if(htim == NULL)
01510   {
01511     return HAL_ERROR;
01512   }
01513
01514   /* Check the parameters */
01515   assert_param(IS_TIM_INSTANCE(htim->Instance));
01516   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01517   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01518
01519   if(htim->State == HAL_TIM_STATE_RESET)
01520   {
01521     /* Allocate lock resource and initialize it */
01522     htim->Lock = HAL_UNLOCKED;
01523
01524     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01525     HAL_TIM_IC_MspInit(htim);
01526   }
01527
01528   /* Set the TIM state */
01529   htim->State= HAL_TIM_STATE_BUSY;
01530
01531   /* Init the base time for the input capture */
01532   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01533
01534   /* Initialize the TIM state*/
01535   htim->State= HAL_TIM_STATE_READY;
01536
01537   return HAL_OK;
01538 }
01539
01540 /**
01541   * @brief  DeInitialize the TIM peripheral
01542   * @param  htim: TIM Input Capture handle
01543   * @retval HAL status
01544   */
01545 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
01546 {
01547   /* Check the parameters */
01548   assert_param(IS_TIM_INSTANCE(htim->Instance));
01549
01550   htim->State = HAL_TIM_STATE_BUSY;
01551
01552   /* Disable the TIM Peripheral Clock */
01553   __HAL_TIM_DISABLE(htim);
01554
01555   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01556   HAL_TIM_IC_MspDeInit(htim);
01557
01558   /* Change TIM state */
01559   htim->State = HAL_TIM_STATE_RESET;
01560
01561   /* Release Lock */
01562   __HAL_UNLOCK(htim);
01563
01564   return HAL_OK;
01565 }
01566
01567 /**
01568   * @brief  Initializes the TIM INput Capture MSP.
01569   * @param  htim: TIM handle
01570   * @retval None
01571   */
01572 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
01573 {
01574   /* Prevent unused argument(s) compilation warning */
01575   UNUSED(htim);
01576
01577   /* NOTE : This function should not be modified, when the callback is needed,
01578             the HAL_TIM_IC_MspInit could be implemented in the user file
01579    */
01580 }
01581
01582 /**
01583   * @brief  DeInitialize TIM Input Capture MSP.
01584   * @param  htim: TIM handle
01585   * @retval None
01586   */
01587 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
01588 {
01589   /* Prevent unused argument(s) compilation warning */
01590   UNUSED(htim);
01591
01592   /* NOTE : This function should not be modified, when the callback is needed,
01593             the HAL_TIM_IC_MspDeInit could be implemented in the user file
01594    */
01595 }
01596
01597 /**
01598   * @brief  Starts the TIM Input Capture measurement.
01599   * @param  htim : TIM Input Capture handle
01600   * @param  Channel : TIM Channels to be enabled
01601   *          This parameter can be one of the following values:
01602   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01603   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01604   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01605   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01606   * @retval HAL status
01607 */
01608 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
01609 {
01610   /* Check the parameters */
01611   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01612
01613   /* Enable the Input Capture channel */
01614   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01615
01616   /* Enable the Peripheral */
01617   __HAL_TIM_ENABLE(htim);
01618
01619   /* Return function status */
01620   return HAL_OK;
01621 }
01622
01623 /**
01624   * @brief  Stops the TIM Input Capture measurement.
01625   * @param  htim : TIM handle
01626   * @param  Channel : TIM Channels to be disabled
01627   *          This parameter can be one of the following values:
01628   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01629   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01630   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01631   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01632   * @retval HAL status
01633 */
01634 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01635 {
01636   /* Check the parameters */
01637   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01638
01639   /* Disable the Input Capture channel */
01640   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01641
01642   /* Disable the Peripheral */
01643   __HAL_TIM_DISABLE(htim);
01644
01645   /* Return function status */
01646   return HAL_OK;
01647 }
01648
01649 /**
01650   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
01651   * @param  htim : TIM Input Capture handle
01652   * @param  Channel : TIM Channels to be enabled
01653   *          This parameter can be one of the following values:
01654   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01655   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01656   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01657   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01658   * @retval HAL status
01659 */
01660 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01661 {
01662   /* Check the parameters */
01663   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01664
01665   switch (Channel)
01666   {
01667     case TIM_CHANNEL_1:
01668     {
01669       /* Enable the TIM Capture/Compare 1 interrupt */
01670       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01671     }
01672     break;
01673
01674     case TIM_CHANNEL_2:
01675     {
01676       /* Enable the TIM Capture/Compare 2 interrupt */
01677       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01678     }
01679     break;
01680
01681     case TIM_CHANNEL_3:
01682     {
01683       /* Enable the TIM Capture/Compare 3 interrupt */
01684       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01685     }
01686     break;
01687
01688     case TIM_CHANNEL_4:
01689     {
01690       /* Enable the TIM Capture/Compare 4 interrupt */
01691       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01692     }
01693     break;
01694
01695     default:
01696     break;
01697   }
01698   /* Enable the Input Capture channel */
01699   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01700
01701   /* Enable the Peripheral */
01702   __HAL_TIM_ENABLE(htim);
01703
01704   /* Return function status */
01705   return HAL_OK;
01706 }
01707
01708 /**
01709   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
01710   * @param  htim : TIM handle
01711   * @param  Channel : TIM Channels to be disabled
01712   *          This parameter can be one of the following values:
01713   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01714   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01715   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01716   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01717   * @retval HAL status
01718 */
01719 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01720 {
01721   /* Check the parameters */
01722   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01723
01724   switch (Channel)
01725   {
01726     case TIM_CHANNEL_1:
01727     {
01728       /* Disable the TIM Capture/Compare 1 interrupt */
01729       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01730     }
01731     break;
01732
01733     case TIM_CHANNEL_2:
01734     {
01735       /* Disable the TIM Capture/Compare 2 interrupt */
01736       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01737     }
01738     break;
01739
01740     case TIM_CHANNEL_3:
01741     {
01742       /* Disable the TIM Capture/Compare 3 interrupt */
01743       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01744     }
01745     break;
01746
01747     case TIM_CHANNEL_4:
01748     {
01749       /* Disable the TIM Capture/Compare 4 interrupt */
01750       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01751     }
01752     break;
01753
01754     default:
01755     break;
01756   }
01757
01758   /* Disable the Input Capture channel */
01759   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01760
01761   /* Disable the Peripheral */
01762   __HAL_TIM_DISABLE(htim);
01763
01764   /* Return function status */
01765   return HAL_OK;
01766 }
01767
01768 /**
01769   * @brief  Starts the TIM Input Capture measurement on in DMA mode.
01770   * @param  htim : TIM Input Capture handle
01771   * @param  Channel : TIM Channels to be enabled
01772   *          This parameter can be one of the following values:
01773   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01774   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01775   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01776   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01777   * @param  pData: The destination Buffer address.
01778   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
01779   * @retval HAL status
01780 */
01781 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01782 {
01783   /* Check the parameters */
01784   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01785   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01786
01787   if((htim->State == HAL_TIM_STATE_BUSY))
01788   {
01789      return HAL_BUSY;
01790   }
01791   else if((htim->State == HAL_TIM_STATE_READY))
01792   {
01793     if((pData == 0 ) && (Length > 0))
01794     {
01795       return HAL_ERROR;
01796     }
01797     else
01798     {
01799       htim->State = HAL_TIM_STATE_BUSY;
01800     }
01801   }
01802
01803   switch (Channel)
01804   {
01805     case TIM_CHANNEL_1:
01806     {
01807       /* Set the DMA Period elapsed callback */
01808       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
01809
01810       /* Set the DMA error callback */
01811       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01812
01813       /* Enable the DMA channel */
01814       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
01815
01816       /* Enable the TIM Capture/Compare 1 DMA request */
01817       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01818     }
01819     break;
01820
01821     case TIM_CHANNEL_2:
01822     {
01823       /* Set the DMA Period elapsed callback */
01824       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
01825
01826       /* Set the DMA error callback */
01827       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01828
01829       /* Enable the DMA channel */
01830       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
01831
01832       /* Enable the TIM Capture/Compare 2  DMA request */
01833       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01834     }
01835     break;
01836
01837     case TIM_CHANNEL_3:
01838     {
01839       /* Set the DMA Period elapsed callback */
01840       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
01841
01842       /* Set the DMA error callback */
01843       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01844
01845       /* Enable the DMA channel */
01846       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
01847
01848       /* Enable the TIM Capture/Compare 3  DMA request */
01849       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01850     }
01851     break;
01852
01853     case TIM_CHANNEL_4:
01854     {
01855       /* Set the DMA Period elapsed callback */
01856       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
01857
01858       /* Set the DMA error callback */
01859       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01860
01861       /* Enable the DMA channel */
01862       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
01863
01864       /* Enable the TIM Capture/Compare 4  DMA request */
01865       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01866     }
01867     break;
01868
01869     default:
01870     break;
01871   }
01872
01873   /* Enable the Input Capture channel */
01874   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01875
01876   /* Enable the Peripheral */
01877   __HAL_TIM_ENABLE(htim);
01878
01879   /* Return function status */
01880   return HAL_OK;
01881 }
01882
01883 /**
01884   * @brief  Stops the TIM Input Capture measurement on in DMA mode.
01885   * @param  htim : TIM Input Capture handle
01886   * @param  Channel : TIM Channels to be disabled
01887   *          This parameter can be one of the following values:
01888   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01889   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01890   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01891   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01892   * @retval HAL status
01893 */
01894 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01895 {
01896   /* Check the parameters */
01897   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01898   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01899
01900   switch (Channel)
01901   {
01902     case TIM_CHANNEL_1:
01903     {
01904       /* Disable the TIM Capture/Compare 1 DMA request */
01905       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01906     }
01907     break;
01908
01909     case TIM_CHANNEL_2:
01910     {
01911       /* Disable the TIM Capture/Compare 2 DMA request */
01912       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01913     }
01914     break;
01915
01916     case TIM_CHANNEL_3:
01917     {
01918       /* Disable the TIM Capture/Compare 3  DMA request */
01919       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01920     }
01921     break;
01922
01923     case TIM_CHANNEL_4:
01924     {
01925       /* Disable the TIM Capture/Compare 4  DMA request */
01926       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01927     }
01928     break;
01929
01930     default:
01931     break;
01932   }
01933
01934   /* Disable the Input Capture channel */
01935   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01936
01937   /* Disable the Peripheral */
01938   __HAL_TIM_DISABLE(htim);
01939
01940   /* Change the htim state */
01941   htim->State = HAL_TIM_STATE_READY;
01942
01943   /* Return function status */
01944   return HAL_OK;
01945 }
01946 /**
01947   * @}
01948   */
01949
01950 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
01951  *  @brief    Time One Pulse functions
01952  *
01953 @verbatim
01954   ==============================================================================
01955                         ##### Time One Pulse functions #####
01956   ==============================================================================
01957   [..]
01958     This section provides functions allowing to:
01959     (+) Initialize and configure the TIM One Pulse.
01960     (+) De-initialize the TIM One Pulse.
01961     (+) Start the Time One Pulse.
01962     (+) Stop the Time One Pulse.
01963     (+) Start the Time One Pulse and enable interrupt.
01964     (+) Stop the Time One Pulse and disable interrupt.
01965     (+) Start the Time One Pulse and enable DMA transfer.
01966     (+) Stop the Time One Pulse and disable DMA transfer.
01967
01968 @endverbatim
01969   * @{
01970   */
01971 /**
01972   * @brief  Initializes the TIM One Pulse Time Base according to the specified
01973   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
01974   * @param  htim: TIM OnePulse handle
01975   * @param  OnePulseMode: Select the One pulse mode.
01976   *         This parameter can be one of the following values:
01977   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
01978   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
01979   * @retval HAL status
01980   */
01981 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
01982 {
01983   /* Check the TIM handle allocation */
01984   if(htim == NULL)
01985   {
01986     return HAL_ERROR;
01987   }
01988
01989   /* Check the parameters */
01990   assert_param(IS_TIM_INSTANCE(htim->Instance));
01991   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01992   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01993   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
01994
01995   if(htim->State == HAL_TIM_STATE_RESET)
01996   {
01997     /* Allocate lock resource and initialize it */
01998     htim->Lock = HAL_UNLOCKED;
01999
02000     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02001     HAL_TIM_OnePulse_MspInit(htim);
02002   }
02003
02004   /* Set the TIM state */
02005   htim->State= HAL_TIM_STATE_BUSY;
02006
02007   /* Configure the Time base in the One Pulse Mode */
02008   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02009
02010   /* Reset the OPM Bit */
02011   htim->Instance->CR1 &= ~TIM_CR1_OPM;
02012
02013   /* Configure the OPM Mode */
02014   htim->Instance->CR1 |= OnePulseMode;
02015
02016   /* Initialize the TIM state*/
02017   htim->State= HAL_TIM_STATE_READY;
02018
02019   return HAL_OK;
02020 }
02021
02022 /**
02023   * @brief  DeInitialize the TIM One Pulse
02024   * @param  htim: TIM One Pulse handle
02025   * @retval HAL status
02026   */
02027 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02028 {
02029   /* Check the parameters */
02030   assert_param(IS_TIM_INSTANCE(htim->Instance));
02031
02032   htim->State = HAL_TIM_STATE_BUSY;
02033
02034   /* Disable the TIM Peripheral Clock */
02035   __HAL_TIM_DISABLE(htim);
02036
02037   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02038   HAL_TIM_OnePulse_MspDeInit(htim);
02039
02040   /* Change TIM state */
02041   htim->State = HAL_TIM_STATE_RESET;
02042
02043   /* Release Lock */
02044   __HAL_UNLOCK(htim);
02045
02046   return HAL_OK;
02047 }
02048
02049 /**
02050   * @brief  Initializes the TIM One Pulse MSP.
02051   * @param  htim: TIM handle
02052   * @retval None
02053   */
02054 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02055 {
02056   /* Prevent unused argument(s) compilation warning */
02057   UNUSED(htim);
02058
02059   /* NOTE : This function should not be modified, when the callback is needed,
02060             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02061    */
02062 }
02063
02064 /**
02065   * @brief  DeInitialize TIM One Pulse MSP.
02066   * @param  htim: TIM handle
02067   * @retval None
02068   */
02069 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02070 {
02071   /* Prevent unused argument(s) compilation warning */
02072   UNUSED(htim);
02073
02074   /* NOTE : This function should not be modified, when the callback is needed,
02075             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02076    */
02077 }
02078
02079 /**
02080   * @brief  Starts the TIM One Pulse signal generation.
02081   * @param  htim : TIM One Pulse handle
02082   * @param  OutputChannel : TIM Channels to be enabled
02083   *          This parameter can be one of the following values:
02084   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02085   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02086   * @retval HAL status
02087 */
02088 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02089 {
02090   /* Prevent unused argument(s) compilation warning */
02091   UNUSED(OutputChannel);
02092
02093   /* Enable the Capture compare and the Input Capture channels
02094     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02095     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02096     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02097     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02098
02099     No need to enable the counter, it's enabled automatically by hardware
02100     (the counter starts in response to a stimulus and generate a pulse */
02101
02102   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02103   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02104
02105   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02106   {
02107     /* Enable the main output */
02108     __HAL_TIM_MOE_ENABLE(htim);
02109   }
02110
02111   /* Return function status */
02112   return HAL_OK;
02113 }
02114
02115 /**
02116   * @brief  Stops the TIM One Pulse signal generation.
02117   * @param  htim : TIM One Pulse handle
02118   * @param  OutputChannel : TIM Channels to be disable
02119   *          This parameter can be one of the following values:
02120   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02121   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02122   * @retval HAL status
02123 */
02124 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02125 {
02126   /* Prevent unused argument(s) compilation warning */
02127   UNUSED(OutputChannel);
02128
02129   /* Disable the Capture compare and the Input Capture channels
02130   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02131   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02132   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02133   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02134
02135   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02136   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02137
02138   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02139   {
02140     /* Disable the Main Ouput */
02141     __HAL_TIM_MOE_DISABLE(htim);
02142   }
02143
02144   /* Disable the Peripheral */
02145   __HAL_TIM_DISABLE(htim);
02146
02147   /* Return function status */
02148   return HAL_OK;
02149 }
02150
02151 /**
02152   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02153   * @param  htim : TIM One Pulse handle
02154   * @param  OutputChannel : TIM Channels to be enabled
02155   *          This parameter can be one of the following values:
02156   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02157   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02158   * @retval HAL status
02159 */
02160 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02161 {
02162   /* Prevent unused argument(s) compilation warning */
02163   UNUSED(OutputChannel);
02164
02165   /* Enable the Capture compare and the Input Capture channels
02166     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02167     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02168     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02169     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02170
02171     No need to enable the counter, it's enabled automatically by hardware
02172     (the counter starts in response to a stimulus and generate a pulse */
02173
02174   /* Enable the TIM Capture/Compare 1 interrupt */
02175   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02176
02177   /* Enable the TIM Capture/Compare 2 interrupt */
02178   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02179
02180   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02181   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02182
02183   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02184   {
02185     /* Enable the main output */
02186     __HAL_TIM_MOE_ENABLE(htim);
02187   }
02188
02189   /* Return function status */
02190   return HAL_OK;
02191 }
02192
02193 /**
02194   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02195   * @param  htim : TIM One Pulse handle
02196   * @param  OutputChannel : TIM Channels to be enabled
02197   *          This parameter can be one of the following values:
02198   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02199   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02200   * @retval HAL status
02201 */
02202 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02203 {
02204   /* Prevent unused argument(s) compilation warning */
02205   UNUSED(OutputChannel);
02206
02207   /* Disable the TIM Capture/Compare 1 interrupt */
02208   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02209
02210   /* Disable the TIM Capture/Compare 2 interrupt */
02211   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02212
02213   /* Disable the Capture compare and the Input Capture channels
02214   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02215   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02216   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02217   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02218   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02219   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02220
02221   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02222   {
02223     /* Disable the Main Ouput */
02224     __HAL_TIM_MOE_DISABLE(htim);
02225   }
02226
02227   /* Disable the Peripheral */
02228    __HAL_TIM_DISABLE(htim);
02229
02230   /* Return function status */
02231   return HAL_OK;
02232 }
02233
02234 /**
02235   * @}
02236   */
02237
02238 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
02239  *  @brief    Time Encoder functions
02240  *
02241 @verbatim
02242   ==============================================================================
02243                           ##### Time Encoder functions #####
02244   ==============================================================================
02245   [..]
02246     This section provides functions allowing to:
02247     (+) Initialize and configure the TIM Encoder.
02248     (+) De-initialize the TIM Encoder.
02249     (+) Start the Time Encoder.
02250     (+) Stop the Time Encoder.
02251     (+) Start the Time Encoder and enable interrupt.
02252     (+) Stop the Time Encoder and disable interrupt.
02253     (+) Start the Time Encoder and enable DMA transfer.
02254     (+) Stop the Time Encoder and disable DMA transfer.
02255
02256 @endverbatim
02257   * @{
02258   */
02259 /**
02260   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
02261   * @param  htim: TIM Encoder Interface handle
02262   * @param  sConfig: TIM Encoder Interface configuration structure
02263   * @retval HAL status
02264   */
02265 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
02266 {
02267   uint32_t tmpsmcr = 0;
02268   uint32_t tmpccmr1 = 0;
02269   uint32_t tmpccer = 0;
02270
02271   /* Check the TIM handle allocation */
02272   if(htim == NULL)
02273   {
02274     return HAL_ERROR;
02275   }
02276
02277   /* Check the parameters */
02278   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02279   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
02280   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
02281   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
02282   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
02283   assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
02284   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
02285   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
02286   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
02287   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
02288
02289   if(htim->State == HAL_TIM_STATE_RESET)
02290   {
02291     /* Allocate lock resource and initialize it */
02292     htim->Lock = HAL_UNLOCKED;
02293
02294     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02295     HAL_TIM_Encoder_MspInit(htim);
02296   }
02297
02298   /* Set the TIM state */
02299   htim->State= HAL_TIM_STATE_BUSY;
02300
02301   /* Reset the SMS bits */
02302   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
02303
02304   /* Configure the Time base in the Encoder Mode */
02305   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02306
02307   /* Get the TIMx SMCR register value */
02308   tmpsmcr = htim->Instance->SMCR;
02309
02310   /* Get the TIMx CCMR1 register value */
02311   tmpccmr1 = htim->Instance->CCMR1;
02312
02313   /* Get the TIMx CCER register value */
02314   tmpccer = htim->Instance->CCER;
02315
02316   /* Set the encoder Mode */
02317   tmpsmcr |= sConfig->EncoderMode;
02318
02319   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
02320   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
02321   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
02322
02323   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
02324   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
02325   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
02326   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
02327   tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
02328
02329   /* Set the TI1 and the TI2 Polarities */
02330   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
02331   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
02332   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
02333
02334   /* Write to TIMx SMCR */
02335   htim->Instance->SMCR = tmpsmcr;
02336
02337   /* Write to TIMx CCMR1 */
02338   htim->Instance->CCMR1 = tmpccmr1;
02339
02340   /* Write to TIMx CCER */
02341   htim->Instance->CCER = tmpccer;
02342
02343   /* Initialize the TIM state*/
02344   htim->State= HAL_TIM_STATE_READY;
02345
02346   return HAL_OK;
02347 }
02348
02349
02350 /**
02351   * @brief  DeInitialize the TIM Encoder interface
02352   * @param  htim: TIM Encoder handle
02353   * @retval HAL status
02354   */
02355 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
02356 {
02357   /* Check the parameters */
02358   assert_param(IS_TIM_INSTANCE(htim->Instance));
02359
02360   htim->State = HAL_TIM_STATE_BUSY;
02361
02362   /* Disable the TIM Peripheral Clock */
02363   __HAL_TIM_DISABLE(htim);
02364
02365   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02366   HAL_TIM_Encoder_MspDeInit(htim);
02367
02368   /* Change TIM state */
02369   htim->State = HAL_TIM_STATE_RESET;
02370
02371   /* Release Lock */
02372   __HAL_UNLOCK(htim);
02373
02374   return HAL_OK;
02375 }
02376
02377 /**
02378   * @brief  Initializes the TIM Encoder Interface MSP.
02379   * @param  htim: TIM handle
02380   * @retval None
02381   */
02382 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
02383 {
02384   /* Prevent unused argument(s) compilation warning */
02385   UNUSED(htim);
02386
02387   /* NOTE : This function should not be modified, when the callback is needed,
02388             the HAL_TIM_Encoder_MspInit could be implemented in the user file
02389    */
02390 }
02391
02392 /**
02393   * @brief  DeInitialize TIM Encoder Interface MSP.
02394   * @param  htim: TIM handle
02395   * @retval None
02396   */
02397 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
02398 {
02399   /* Prevent unused argument(s) compilation warning */
02400   UNUSED(htim);
02401
02402   /* NOTE : This function should not be modified, when the callback is needed,
02403             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
02404    */
02405 }
02406
02407 /**
02408   * @brief  Starts the TIM Encoder Interface.
02409   * @param  htim : TIM Encoder Interface handle
02410   * @param  Channel : TIM Channels to be enabled
02411   *          This parameter can be one of the following values:
02412   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02413   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02414   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02415   * @retval HAL status
02416 */
02417 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02418 {
02419   /* Check the parameters */
02420   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02421
02422   /* Enable the encoder interface channels */
02423   switch (Channel)
02424   {
02425     case TIM_CHANNEL_1:
02426     {
02427       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02428     }
02429     break;
02430
02431     case TIM_CHANNEL_2:
02432     {
02433       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02434     }
02435     break;
02436
02437     default :
02438     {
02439       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02440       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02441     }
02442     break;
02443   }
02444   /* Enable the Peripheral */
02445   __HAL_TIM_ENABLE(htim);
02446
02447   /* Return function status */
02448   return HAL_OK;
02449 }
02450
02451 /**
02452   * @brief  Stops the TIM Encoder Interface.
02453   * @param  htim : TIM Encoder Interface handle
02454   * @param  Channel : TIM Channels to be disabled
02455   *          This parameter can be one of the following values:
02456   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02457   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02458   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02459   * @retval HAL status
02460 */
02461 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02462 {
02463   /* Check the parameters */
02464     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02465
02466    /* Disable the Input Capture channels 1 and 2
02467     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02468   switch (Channel)
02469   {
02470     case TIM_CHANNEL_1:
02471     {
02472       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02473     }
02474     break;
02475
02476     case TIM_CHANNEL_2:
02477     {
02478       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02479     }
02480     break;
02481
02482     default :
02483     {
02484       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02485       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02486     }
02487     break;
02488   }
02489
02490   /* Disable the Peripheral */
02491   __HAL_TIM_DISABLE(htim);
02492
02493   /* Return function status */
02494   return HAL_OK;
02495 }
02496
02497 /**
02498   * @brief  Starts the TIM Encoder Interface in interrupt mode.
02499   * @param  htim : TIM Encoder Interface handle
02500   * @param  Channel : TIM Channels to be enabled
02501   *          This parameter can be one of the following values:
02502   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02503   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02504   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02505   * @retval HAL status
02506 */
02507 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02508 {
02509   /* Check the parameters */
02510   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02511
02512   /* Enable the encoder interface channels */
02513   /* Enable the capture compare Interrupts 1 and/or 2 */
02514   switch (Channel)
02515   {
02516     case TIM_CHANNEL_1:
02517     {
02518       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02519       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02520     }
02521     break;
02522
02523     case TIM_CHANNEL_2:
02524     {
02525       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02526       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02527     }
02528     break;
02529
02530     default :
02531     {
02532       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02533       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02534       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02535       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02536     }
02537     break;
02538   }
02539
02540   /* Enable the Peripheral */
02541   __HAL_TIM_ENABLE(htim);
02542
02543   /* Return function status */
02544   return HAL_OK;
02545 }
02546
02547 /**
02548   * @brief  Stops the TIM Encoder Interface in interrupt mode.
02549   * @param  htim : TIM Encoder Interface handle
02550   * @param  Channel : TIM Channels to be disabled
02551   *          This parameter can be one of the following values:
02552   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02553   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02554   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02555   * @retval HAL status
02556 */
02557 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02558 {
02559   /* Check the parameters */
02560   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02561
02562   /* Disable the Input Capture channels 1 and 2
02563     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02564   if(Channel == TIM_CHANNEL_1)
02565   {
02566     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02567
02568     /* Disable the capture compare Interrupts 1 */
02569   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02570   }
02571   else if(Channel == TIM_CHANNEL_2)
02572   {
02573     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02574
02575     /* Disable the capture compare Interrupts 2 */
02576   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02577   }
02578   else
02579   {
02580     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02581     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02582
02583     /* Disable the capture compare Interrupts 1 and 2 */
02584     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02585     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02586   }
02587
02588   /* Disable the Peripheral */
02589   __HAL_TIM_DISABLE(htim);
02590
02591   /* Change the htim state */
02592   htim->State = HAL_TIM_STATE_READY;
02593
02594   /* Return function status */
02595   return HAL_OK;
02596 }
02597
02598 /**
02599   * @brief  Starts the TIM Encoder Interface in DMA mode.
02600   * @param  htim : TIM Encoder Interface handle
02601   * @param  Channel : TIM Channels to be enabled
02602   *          This parameter can be one of the following values:
02603   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02604   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02605   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02606   * @param  pData1: The destination Buffer address for IC1.
02607   * @param  pData2: The destination Buffer address for IC2.
02608   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
02609   * @retval HAL status
02610 */
02611 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
02612 {
02613   /* Check the parameters */
02614   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02615
02616   if((htim->State == HAL_TIM_STATE_BUSY))
02617   {
02618      return HAL_BUSY;
02619   }
02620   else if((htim->State == HAL_TIM_STATE_READY))
02621   {
02622     if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
02623     {
02624       return HAL_ERROR;
02625     }
02626     else
02627     {
02628       htim->State = HAL_TIM_STATE_BUSY;
02629     }
02630   }
02631
02632   switch (Channel)
02633   {
02634     case TIM_CHANNEL_1:
02635     {
02636       /* Set the DMA Period elapsed callback */
02637       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02638
02639       /* Set the DMA error callback */
02640       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02641
02642       /* Enable the DMA channel */
02643       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
02644
02645       /* Enable the TIM Input Capture DMA request */
02646       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02647
02648       /* Enable the Peripheral */
02649       __HAL_TIM_ENABLE(htim);
02650
02651       /* Enable the Capture compare channel */
02652       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02653     }
02654     break;
02655
02656     case TIM_CHANNEL_2:
02657     {
02658       /* Set the DMA Period elapsed callback */
02659       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02660
02661       /* Set the DMA error callback */
02662       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
02663       /* Enable the DMA channel */
02664       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02665
02666       /* Enable the TIM Input Capture  DMA request */
02667       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02668
02669       /* Enable the Peripheral */
02670       __HAL_TIM_ENABLE(htim);
02671
02672       /* Enable the Capture compare channel */
02673       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02674     }
02675     break;
02676
02677     case TIM_CHANNEL_ALL:
02678     {
02679       /* Set the DMA Period elapsed callback */
02680       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02681
02682       /* Set the DMA error callback */
02683       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02684
02685       /* Enable the DMA channel */
02686       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
02687
02688       /* Set the DMA Period elapsed callback */
02689       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02690
02691       /* Set the DMA error callback */
02692       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
02693
02694       /* Enable the DMA channel */
02695       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02696
02697      /* Enable the Peripheral */
02698       __HAL_TIM_ENABLE(htim);
02699
02700       /* Enable the Capture compare channel */
02701       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02702       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02703
02704       /* Enable the TIM Input Capture  DMA request */
02705       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02706       /* Enable the TIM Input Capture  DMA request */
02707       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02708     }
02709     break;
02710
02711     default:
02712     break;
02713   }
02714   /* Return function status */
02715   return HAL_OK;
02716 }
02717
02718 /**
02719   * @brief  Stops the TIM Encoder Interface in DMA mode.
02720   * @param  htim : TIM Encoder Interface handle
02721   * @param  Channel : TIM Channels to be enabled
02722   *          This parameter can be one of the following values:
02723   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02724   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02725   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02726   * @retval HAL status
02727 */
02728 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02729 {
02730   /* Check the parameters */
02731   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02732
02733   /* Disable the Input Capture channels 1 and 2
02734     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02735   if(Channel == TIM_CHANNEL_1)
02736   {
02737     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02738
02739     /* Disable the capture compare DMA Request 1 */
02740     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02741   }
02742   else if(Channel == TIM_CHANNEL_2)
02743   {
02744     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02745
02746     /* Disable the capture compare DMA Request 2 */
02747     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02748   }
02749   else
02750   {
02751     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02752     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02753
02754     /* Disable the capture compare DMA Request 1 and 2 */
02755     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02756     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02757   }
02758
02759   /* Disable the Peripheral */
02760   __HAL_TIM_DISABLE(htim);
02761
02762   /* Change the htim state */
02763   htim->State = HAL_TIM_STATE_READY;
02764
02765   /* Return function status */
02766   return HAL_OK;
02767 }
02768
02769 /**
02770   * @}
02771   */
02772 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
02773  *  @brief    IRQ handler management
02774  *
02775 @verbatim
02776   ==============================================================================
02777                         ##### IRQ handler management #####
02778   ==============================================================================
02779   [..]
02780     This section provides Timer IRQ handler function.
02781
02782 @endverbatim
02783   * @{
02784   */
02785 /**
02786   * @brief  This function handles TIM interrupts requests.
02787   * @param  htim: TIM  handle
02788   * @retval None
02789   */
02790 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
02791 {
02792   /* Capture compare 1 event */
02793   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
02794   {
02795     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
02796     {
02797       {
02798         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
02799         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
02800
02801         /* Input capture event */
02802         if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
02803         {
02804           HAL_TIM_IC_CaptureCallback(htim);
02805         }
02806         /* Output compare event */
02807         else
02808         {
02809           HAL_TIM_OC_DelayElapsedCallback(htim);
02810           HAL_TIM_PWM_PulseFinishedCallback(htim);
02811         }
02812         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02813       }
02814     }
02815   }
02816   /* Capture compare 2 event */
02817   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
02818   {
02819     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
02820     {
02821       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
02822       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
02823       /* Input capture event */
02824       if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
02825       {
02826         HAL_TIM_IC_CaptureCallback(htim);
02827       }
02828       /* Output compare event */
02829       else
02830       {
02831         HAL_TIM_OC_DelayElapsedCallback(htim);
02832         HAL_TIM_PWM_PulseFinishedCallback(htim);
02833       }
02834       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02835     }
02836   }
02837   /* Capture compare 3 event */
02838   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
02839   {
02840     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
02841     {
02842       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
02843       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
02844       /* Input capture event */
02845       if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
02846       {
02847         HAL_TIM_IC_CaptureCallback(htim);
02848       }
02849       /* Output compare event */
02850       else
02851       {
02852         HAL_TIM_OC_DelayElapsedCallback(htim);
02853         HAL_TIM_PWM_PulseFinishedCallback(htim);
02854       }
02855       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02856     }
02857   }
02858   /* Capture compare 4 event */
02859   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
02860   {
02861     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
02862     {
02863       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
02864       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
02865       /* Input capture event */
02866       if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
02867       {
02868         HAL_TIM_IC_CaptureCallback(htim);
02869       }
02870       /* Output compare event */
02871       else
02872       {
02873         HAL_TIM_OC_DelayElapsedCallback(htim);
02874         HAL_TIM_PWM_PulseFinishedCallback(htim);
02875       }
02876       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02877     }
02878   }
02879   /* TIM Update event */
02880   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
02881   {
02882     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
02883     {
02884       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
02885       HAL_TIM_PeriodElapsedCallback(htim);
02886     }
02887   }
02888   /* TIM Break input event */
02889   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
02890   {
02891     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
02892     {
02893       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
02894       HAL_TIMEx_BreakCallback(htim);
02895     }
02896   }
02897   /* TIM Trigger detection event */
02898   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
02899   {
02900     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
02901     {
02902       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
02903       HAL_TIM_TriggerCallback(htim);
02904     }
02905   }
02906   /* TIM commutation event */
02907   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
02908   {
02909     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
02910     {
02911       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
02912       HAL_TIMEx_CommutationCallback(htim);
02913     }
02914   }
02915 }
02916
02917 /**
02918   * @}
02919   */
02920
02921 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
02922  *  @brief      Peripheral Control functions
02923  *
02924 @verbatim
02925   ==============================================================================
02926                    ##### Peripheral Control functions #####
02927   ==============================================================================
02928  [..]
02929    This section provides functions allowing to:
02930       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
02931       (+) Configure External Clock source.
02932       (+) Configure Complementary channels, break features and dead time.
02933       (+) Configure Master and the Slave synchronization.
02934       (+) Configure the DMA Burst Mode.
02935
02936 @endverbatim
02937   * @{
02938   */
02939
02940 /**
02941   * @brief  Initializes the TIM Output Compare Channels according to the specified
02942   *         parameters in the TIM_OC_InitTypeDef.
02943   * @param  htim: TIM Output Compare handle
02944   * @param  sConfig: TIM Output Compare configuration structure
02945   * @param  Channel : TIM Channels to configure
02946   *          This parameter can be one of the following values:
02947   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02948   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02949   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02950   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02951   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
02952   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
02953   * @retval HAL status
02954   */
02955 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
02956                                            TIM_OC_InitTypeDef* sConfig,
02957                                            uint32_t Channel)
02958 {
02959   /* Check the parameters */
02960   assert_param(IS_TIM_CHANNELS(Channel));
02961   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
02962   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
02963
02964   /* Process Locked */
02965   __HAL_LOCK(htim);
02966
02967   htim->State = HAL_TIM_STATE_BUSY;
02968
02969   switch (Channel)
02970   {
02971     case TIM_CHANNEL_1:
02972     {
02973       /* Check the parameters */
02974       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
02975
02976      /* Configure the TIM Channel 1 in Output Compare */
02977       TIM_OC1_SetConfig(htim->Instance, sConfig);
02978     }
02979     break;
02980
02981     case TIM_CHANNEL_2:
02982     {
02983       /* Check the parameters */
02984       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02985
02986       /* Configure the TIM Channel 2 in Output Compare */
02987       TIM_OC2_SetConfig(htim->Instance, sConfig);
02988     }
02989     break;
02990
02991     case TIM_CHANNEL_3:
02992     {
02993       /* Check the parameters */
02994       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
02995
02996       /* Configure the TIM Channel 3 in Output Compare */
02997       TIM_OC3_SetConfig(htim->Instance, sConfig);
02998     }
02999     break;
03000
03001     case TIM_CHANNEL_4:
03002     {
03003       /* Check the parameters */
03004       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03005
03006        /* Configure the TIM Channel 4 in Output Compare */
03007        TIM_OC4_SetConfig(htim->Instance, sConfig);
03008     }
03009     break;
03010
03011     case TIM_CHANNEL_5:
03012     {
03013       /* Check the parameters */
03014       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
03015
03016        /* Configure the TIM Channel 5 in Output Compare */
03017        TIM_OC5_SetConfig(htim->Instance, sConfig);
03018     }
03019     break;
03020
03021     case TIM_CHANNEL_6:
03022     {
03023       /* Check the parameters */
03024       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
03025
03026        /* Configure the TIM Channel 6 in Output Compare */
03027        TIM_OC6_SetConfig(htim->Instance, sConfig);
03028     }
03029     break;
03030
03031     default:
03032     break;
03033   }
03034
03035   htim->State = HAL_TIM_STATE_READY;
03036
03037   __HAL_UNLOCK(htim);
03038
03039   return HAL_OK;
03040 }
03041
03042 /**
03043   * @brief  Initializes the TIM Input Capture Channels according to the specified
03044   *         parameters in the TIM_IC_InitTypeDef.
03045   * @param  htim: TIM IC handle
03046   * @param  sConfig: TIM Input Capture configuration structure
03047   * @param  Channel : TIM Channels to be enabled
03048   *          This parameter can be one of the following values:
03049   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03050   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03051   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03052   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03053   * @retval HAL status
03054   */
03055 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
03056 {
03057   /* Check the parameters */
03058   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03059   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
03060   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
03061   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
03062   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
03063
03064   /* Process Locked */
03065   __HAL_LOCK(htim);
03066
03067   htim->State = HAL_TIM_STATE_BUSY;
03068
03069   if (Channel == TIM_CHANNEL_1)
03070   {
03071     /* TI1 Configuration */
03072     TIM_TI1_SetConfig(htim->Instance,
03073                sConfig->ICPolarity,
03074                sConfig->ICSelection,
03075                sConfig->ICFilter);
03076
03077     /* Reset the IC1PSC Bits */
03078     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03079
03080     /* Set the IC1PSC value */
03081     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
03082   }
03083   else if (Channel == TIM_CHANNEL_2)
03084   {
03085     /* TI2 Configuration */
03086     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03087
03088     TIM_TI2_SetConfig(htim->Instance,
03089                       sConfig->ICPolarity,
03090                       sConfig->ICSelection,
03091                       sConfig->ICFilter);
03092
03093     /* Reset the IC2PSC Bits */
03094     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03095
03096     /* Set the IC2PSC value */
03097     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
03098   }
03099   else if (Channel == TIM_CHANNEL_3)
03100   {
03101     /* TI3 Configuration */
03102     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03103
03104     TIM_TI3_SetConfig(htim->Instance,
03105                sConfig->ICPolarity,
03106                sConfig->ICSelection,
03107                sConfig->ICFilter);
03108
03109     /* Reset the IC3PSC Bits */
03110     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
03111
03112     /* Set the IC3PSC value */
03113     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
03114   }
03115   else
03116   {
03117     /* TI4 Configuration */
03118     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03119
03120     TIM_TI4_SetConfig(htim->Instance,
03121                sConfig->ICPolarity,
03122                sConfig->ICSelection,
03123                sConfig->ICFilter);
03124
03125     /* Reset the IC4PSC Bits */
03126     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
03127
03128     /* Set the IC4PSC value */
03129     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
03130   }
03131
03132   htim->State = HAL_TIM_STATE_READY;
03133
03134   __HAL_UNLOCK(htim);
03135
03136   return HAL_OK;
03137 }
03138
03139 /**
03140   * @brief  Initializes the TIM PWM  channels according to the specified
03141   *         parameters in the TIM_OC_InitTypeDef.
03142   * @param  htim: TIM PWM handle
03143   * @param  sConfig: TIM PWM configuration structure
03144   * @param  Channel : TIM Channels to be configured
03145   *          This parameter can be one of the following values:
03146   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03147   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03148   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03149   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03150   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
03151   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
03152   * @retval HAL status
03153   */
03154 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
03155                                             TIM_OC_InitTypeDef* sConfig,
03156                                             uint32_t Channel)
03157 {
03158   /* Check the parameters */
03159   assert_param(IS_TIM_CHANNELS(Channel));
03160   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
03161   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03162   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
03163
03164   /* Process Locked */
03165   __HAL_LOCK(htim);
03166
03167   htim->State = HAL_TIM_STATE_BUSY;
03168
03169   switch (Channel)
03170   {
03171     case TIM_CHANNEL_1:
03172     {
03173       /* Check the parameters */
03174       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03175
03176       /* Configure the Channel 1 in PWM mode */
03177       TIM_OC1_SetConfig(htim->Instance, sConfig);
03178
03179       /* Set the Preload enable bit for channel1 */
03180       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
03181
03182       /* Configure the Output Fast mode */
03183       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
03184       htim->Instance->CCMR1 |= sConfig->OCFastMode;
03185     }
03186     break;
03187
03188     case TIM_CHANNEL_2:
03189     {
03190       /* Check the parameters */
03191       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03192
03193       /* Configure the Channel 2 in PWM mode */
03194       TIM_OC2_SetConfig(htim->Instance, sConfig);
03195
03196       /* Set the Preload enable bit for channel2 */
03197       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
03198
03199       /* Configure the Output Fast mode */
03200       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
03201       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
03202     }
03203     break;
03204
03205     case TIM_CHANNEL_3:
03206     {
03207       /* Check the parameters */
03208       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03209
03210       /* Configure the Channel 3 in PWM mode */
03211       TIM_OC3_SetConfig(htim->Instance, sConfig);
03212
03213       /* Set the Preload enable bit for channel3 */
03214       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
03215
03216      /* Configure the Output Fast mode */
03217       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
03218       htim->Instance->CCMR2 |= sConfig->OCFastMode;
03219     }
03220     break;
03221
03222     case TIM_CHANNEL_4:
03223     {
03224       /* Check the parameters */
03225       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03226
03227       /* Configure the Channel 4 in PWM mode */
03228       TIM_OC4_SetConfig(htim->Instance, sConfig);
03229
03230       /* Set the Preload enable bit for channel4 */
03231       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
03232
03233      /* Configure the Output Fast mode */
03234       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
03235       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
03236     }
03237     break;
03238
03239     case TIM_CHANNEL_5:
03240     {
03241        /* Check the parameters */
03242       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
03243
03244      /* Configure the Channel 5 in PWM mode */
03245       TIM_OC5_SetConfig(htim->Instance, sConfig);
03246
03247       /* Set the Preload enable bit for channel5*/
03248       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
03249
03250      /* Configure the Output Fast mode */
03251       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
03252       htim->Instance->CCMR3 |= sConfig->OCFastMode;
03253     }
03254     break;
03255
03256     case TIM_CHANNEL_6:
03257     {
03258        /* Check the parameters */
03259       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
03260
03261      /* Configure the Channel 5 in PWM mode */
03262       TIM_OC6_SetConfig(htim->Instance, sConfig);
03263
03264       /* Set the Preload enable bit for channel6 */
03265       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
03266
03267      /* Configure the Output Fast mode */
03268       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
03269       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
03270     }
03271     break;
03272
03273     default:
03274     break;
03275   }
03276
03277   htim->State = HAL_TIM_STATE_READY;
03278
03279   __HAL_UNLOCK(htim);
03280
03281   return HAL_OK;
03282 }
03283
03284 /**
03285   * @brief  Initializes the TIM One Pulse Channels according to the specified
03286   *         parameters in the TIM_OnePulse_InitTypeDef.
03287   * @param  htim: TIM One Pulse handle
03288   * @param  sConfig: TIM One Pulse configuration structure
03289   * @param  OutputChannel : TIM Channels to be enabled
03290   *          This parameter can be one of the following values:
03291   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03292   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03293   * @param  InputChannel : TIM Channels to be enabled
03294   *          This parameter can be one of the following values:
03295   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03296   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03297   * @retval HAL status
03298   */
03299 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
03300 {
03301   TIM_OC_InitTypeDef temp1;
03302
03303   /* Check the parameters */
03304   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
03305   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
03306
03307   if(OutputChannel != InputChannel)
03308   {
03309   /* Process Locked */
03310   __HAL_LOCK(htim);
03311
03312   htim->State = HAL_TIM_STATE_BUSY;
03313
03314   /* Extract the Ouput compare configuration from sConfig structure */
03315   temp1.OCMode = sConfig->OCMode;
03316   temp1.Pulse = sConfig->Pulse;
03317   temp1.OCPolarity = sConfig->OCPolarity;
03318   temp1.OCNPolarity = sConfig->OCNPolarity;
03319   temp1.OCIdleState = sConfig->OCIdleState;
03320   temp1.OCNIdleState = sConfig->OCNIdleState;
03321
03322     switch (OutputChannel)
03323   {
03324     case TIM_CHANNEL_1:
03325     {
03326         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03327
03328       TIM_OC1_SetConfig(htim->Instance, &temp1);
03329     }
03330     break;
03331     case TIM_CHANNEL_2:
03332     {
03333         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03334
03335       TIM_OC2_SetConfig(htim->Instance, &temp1);
03336     }
03337     break;
03338     default:
03339     break;
03340   }
03341     switch (InputChannel)
03342   {
03343     case TIM_CHANNEL_1:
03344     {
03345         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03346
03347       TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
03348                         sConfig->ICSelection, sConfig->ICFilter);
03349
03350     /* Reset the IC1PSC Bits */
03351     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03352
03353     /* Select the Trigger source */
03354         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03355     htim->Instance->SMCR |= TIM_TS_TI1FP1;
03356
03357     /* Select the Slave Mode */
03358         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03359     htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03360     }
03361     break;
03362     case TIM_CHANNEL_2:
03363     {
03364         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03365
03366       TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
03367                  sConfig->ICSelection, sConfig->ICFilter);
03368
03369       /* Reset the IC2PSC Bits */
03370         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03371
03372       /* Select the Trigger source */
03373         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03374       htim->Instance->SMCR |= TIM_TS_TI2FP2;
03375
03376       /* Select the Slave Mode */
03377         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03378       htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03379     }
03380     break;
03381
03382     default:
03383     break;
03384   }
03385
03386   htim->State = HAL_TIM_STATE_READY;
03387
03388   __HAL_UNLOCK(htim);
03389
03390   return HAL_OK;
03391 }
03392   else
03393   {
03394     return HAL_ERROR;
03395   }
03396 }
03397
03398 /**
03399   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
03400   * @param  htim: TIM handle
03401   * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
03402   *         This parameters can be on of the following values:
03403   *            @arg TIM_DMABASE_CR1
03404   *            @arg TIM_DMABASE_CR2
03405   *            @arg TIM_DMABASE_SMCR
03406   *            @arg TIM_DMABASE_DIER
03407   *            @arg TIM_DMABASE_SR
03408   *            @arg TIM_DMABASE_EGR
03409   *            @arg TIM_DMABASE_CCMR1
03410   *            @arg TIM_DMABASE_CCMR2
03411   *            @arg TIM_DMABASE_CCER
03412   *            @arg TIM_DMABASE_CNT
03413   *            @arg TIM_DMABASE_PSC
03414   *            @arg TIM_DMABASE_ARR
03415   *            @arg TIM_DMABASE_RCR
03416   *            @arg TIM_DMABASE_CCR1
03417   *            @arg TIM_DMABASE_CCR2
03418   *            @arg TIM_DMABASE_CCR3
03419   *            @arg TIM_DMABASE_CCR4
03420   *            @arg TIM_DMABASE_BDTR
03421   *            @arg TIM_DMABASE_DCR
03422   * @param  BurstRequestSrc: TIM DMA Request sources
03423   *         This parameters can be on of the following values:
03424   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03425   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03426   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03427   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03428   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03429   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03430   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03431   * @param  BurstBuffer: The Buffer address.
03432   * @param  BurstLength: DMA Burst length. This parameter can be one value
03433   *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
03434   * @retval HAL status
03435   */
03436 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03437                                               uint32_t* BurstBuffer, uint32_t  BurstLength)
03438 {
03439   /* Check the parameters */
03440   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03441   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03442   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03443   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03444
03445   if((htim->State == HAL_TIM_STATE_BUSY))
03446   {
03447      return HAL_BUSY;
03448   }
03449   else if((htim->State == HAL_TIM_STATE_READY))
03450   {
03451     if((BurstBuffer == 0 ) && (BurstLength > 0))
03452     {
03453       return HAL_ERROR;
03454     }
03455     else
03456     {
03457       htim->State = HAL_TIM_STATE_BUSY;
03458     }
03459   }
03460   switch(BurstRequestSrc)
03461   {
03462     case TIM_DMA_UPDATE:
03463     {
03464       /* Set the DMA Period elapsed callback */
03465       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03466
03467       /* Set the DMA error callback */
03468       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03469
03470       /* Enable the DMA channel */
03471       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03472     }
03473     break;
03474     case TIM_DMA_CC1:
03475     {
03476       /* Set the DMA Period elapsed callback */
03477       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03478
03479       /* Set the DMA error callback */
03480       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03481
03482       /* Enable the DMA channel */
03483       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03484     }
03485     break;
03486     case TIM_DMA_CC2:
03487     {
03488       /* Set the DMA Period elapsed callback */
03489       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03490
03491       /* Set the DMA error callback */
03492       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03493
03494       /* Enable the DMA channel */
03495       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03496     }
03497     break;
03498     case TIM_DMA_CC3:
03499     {
03500       /* Set the DMA Period elapsed callback */
03501       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03502
03503       /* Set the DMA error callback */
03504       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03505
03506       /* Enable the DMA channel */
03507       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03508     }
03509     break;
03510     case TIM_DMA_CC4:
03511     {
03512       /* Set the DMA Period elapsed callback */
03513       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03514
03515       /* Set the DMA error callback */
03516       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
03517
03518       /* Enable the DMA channel */
03519       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03520     }
03521     break;
03522     case TIM_DMA_COM:
03523     {
03524       /* Set the DMA Period elapsed callback */
03525       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
03526
03527       /* Set the DMA error callback */
03528       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
03529
03530       /* Enable the DMA channel */
03531       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03532     }
03533     break;
03534     case TIM_DMA_TRIGGER:
03535     {
03536       /* Set the DMA Period elapsed callback */
03537       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03538
03539       /* Set the DMA error callback */
03540       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
03541
03542       /* Enable the DMA channel */
03543       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
03544     }
03545     break;
03546     default:
03547     break;
03548   }
03549    /* configure the DMA Burst Mode */
03550    htim->Instance->DCR = BurstBaseAddress | BurstLength;
03551
03552    /* Enable the TIM DMA Request */
03553    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03554
03555    htim->State = HAL_TIM_STATE_READY;
03556
03557   /* Return function status */
03558   return HAL_OK;
03559 }
03560
03561 /**
03562   * @brief  Stops the TIM DMA Burst mode
03563   * @param  htim: TIM handle
03564   * @param  BurstRequestSrc: TIM DMA Request sources to disable
03565   * @retval HAL status
03566   */
03567 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03568 {
03569   /* Check the parameters */
03570   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03571
03572   /* Abort the DMA transfer (at least disable the DMA channel) */
03573   switch(BurstRequestSrc)
03574   {
03575     case TIM_DMA_UPDATE:
03576     {
03577       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03578     }
03579     break;
03580     case TIM_DMA_CC1:
03581     {
03582       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03583     }
03584     break;
03585     case TIM_DMA_CC2:
03586     {
03587       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03588     }
03589     break;
03590     case TIM_DMA_CC3:
03591     {
03592       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03593     }
03594     break;
03595     case TIM_DMA_CC4:
03596     {
03597       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03598     }
03599     break;
03600     case TIM_DMA_COM:
03601     {
03602       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03603     }
03604     break;
03605     case TIM_DMA_TRIGGER:
03606     {
03607       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03608     }
03609     break;
03610     default:
03611     break;
03612   }
03613
03614   /* Disable the TIM Update DMA request */
03615   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03616
03617   /* Return function status */
03618   return HAL_OK;
03619 }
03620
03621 /**
03622   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
03623   * @param  htim: TIM handle
03624   * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
03625   *         This parameters can be on of the following values:
03626   *            @arg TIM_DMABASE_CR1
03627   *            @arg TIM_DMABASE_CR2
03628   *            @arg TIM_DMABASE_SMCR
03629   *            @arg TIM_DMABASE_DIER
03630   *            @arg TIM_DMABASE_SR
03631   *            @arg TIM_DMABASE_EGR
03632   *            @arg TIM_DMABASE_CCMR1
03633   *            @arg TIM_DMABASE_CCMR2
03634   *            @arg TIM_DMABASE_CCER
03635   *            @arg TIM_DMABASE_CNT
03636   *            @arg TIM_DMABASE_PSC
03637   *            @arg TIM_DMABASE_ARR
03638   *            @arg TIM_DMABASE_RCR
03639   *            @arg TIM_DMABASE_CCR1
03640   *            @arg TIM_DMABASE_CCR2
03641   *            @arg TIM_DMABASE_CCR3
03642   *            @arg TIM_DMABASE_CCR4
03643   *            @arg TIM_DMABASE_BDTR
03644   *            @arg TIM_DMABASE_DCR
03645   * @param  BurstRequestSrc: TIM DMA Request sources
03646   *         This parameters can be on of the following values:
03647   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03648   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03649   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03650   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03651   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03652   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03653   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03654   * @param  BurstBuffer: The Buffer address.
03655   * @param  BurstLength: DMA Burst length. This parameter can be one value
03656   *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
03657   * @retval HAL status
03658   */
03659 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03660                                              uint32_t  *BurstBuffer, uint32_t  BurstLength)
03661 {
03662   /* Check the parameters */
03663   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03664   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03665   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03666   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03667
03668   if((htim->State == HAL_TIM_STATE_BUSY))
03669   {
03670      return HAL_BUSY;
03671   }
03672   else if((htim->State == HAL_TIM_STATE_READY))
03673   {
03674     if((BurstBuffer == 0 ) && (BurstLength > 0))
03675     {
03676       return HAL_ERROR;
03677     }
03678     else
03679     {
03680       htim->State = HAL_TIM_STATE_BUSY;
03681     }
03682   }
03683   switch(BurstRequestSrc)
03684   {
03685     case TIM_DMA_UPDATE:
03686     {
03687       /* Set the DMA Period elapsed callback */
03688       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03689
03690       /* Set the DMA error callback */
03691       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03692
03693       /* Enable the DMA channel */
03694        HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03695     }
03696     break;
03697     case TIM_DMA_CC1:
03698     {
03699       /* Set the DMA Period elapsed callback */
03700       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMACaptureCplt;
03701
03702       /* Set the DMA error callback */
03703       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03704
03705       /* Enable the DMA channel */
03706       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03707     }
03708     break;
03709     case TIM_DMA_CC2:
03710     {
03711       /* Set the DMA Period elapsed callback */
03712       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMACaptureCplt;
03713
03714       /* Set the DMA error callback */
03715       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03716
03717       /* Enable the DMA channel */
03718       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03719     }
03720     break;
03721     case TIM_DMA_CC3:
03722     {
03723       /* Set the DMA Period elapsed callback */
03724       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMACaptureCplt;
03725
03726       /* Set the DMA error callback */
03727       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03728
03729       /* Enable the DMA channel */
03730       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03731     }
03732     break;
03733     case TIM_DMA_CC4:
03734     {
03735       /* Set the DMA Period elapsed callback */
03736       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMACaptureCplt;
03737
03738       /* Set the DMA error callback */
03739       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
03740
03741       /* Enable the DMA channel */
03742       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03743     }
03744     break;
03745     case TIM_DMA_COM:
03746     {
03747       /* Set the DMA Period elapsed callback */
03748       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
03749
03750       /* Set the DMA error callback */
03751       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
03752
03753       /* Enable the DMA channel */
03754       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03755     }
03756     break;
03757     case TIM_DMA_TRIGGER:
03758     {
03759       /* Set the DMA Period elapsed callback */
03760       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03761
03762       /* Set the DMA error callback */
03763       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
03764
03765       /* Enable the DMA channel */
03766       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
03767     }
03768     break;
03769     default:
03770     break;
03771   }
03772
03773   /* configure the DMA Burst Mode */
03774   htim->Instance->DCR = BurstBaseAddress | BurstLength;
03775
03776   /* Enable the TIM DMA Request */
03777   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03778
03779   htim->State = HAL_TIM_STATE_READY;
03780
03781   /* Return function status */
03782   return HAL_OK;
03783 }
03784
03785 /**
03786   * @brief  Stop the DMA burst reading
03787   * @param  htim: TIM handle
03788   * @param  BurstRequestSrc: TIM DMA Request sources to disable.
03789   * @retval HAL status
03790   */
03791 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03792 {
03793   /* Check the parameters */
03794   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03795
03796   /* Abort the DMA transfer (at least disable the DMA channel) */
03797   switch(BurstRequestSrc)
03798   {
03799     case TIM_DMA_UPDATE:
03800     {
03801       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03802     }
03803     break;
03804     case TIM_DMA_CC1:
03805     {
03806       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03807     }
03808     break;
03809     case TIM_DMA_CC2:
03810     {
03811       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03812     }
03813     break;
03814     case TIM_DMA_CC3:
03815     {
03816       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03817     }
03818     break;
03819     case TIM_DMA_CC4:
03820     {
03821       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03822     }
03823     break;
03824     case TIM_DMA_COM:
03825     {
03826       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03827     }
03828     break;
03829     case TIM_DMA_TRIGGER:
03830     {
03831       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03832     }
03833     break;
03834     default:
03835     break;
03836   }
03837
03838   /* Disable the TIM Update DMA request */
03839   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03840
03841   /* Return function status */
03842   return HAL_OK;
03843 }
03844
03845 /**
03846   * @brief  Generate a software event
03847   * @param  htim: TIM handle
03848   * @param  EventSource: specifies the event source.
03849   *          This parameter can be one of the following values:
03850   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
03851   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
03852   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
03853   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
03854   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
03855   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
03856   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
03857   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
03858   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
03859   * @retval None
03860   */
03861
03862 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
03863 {
03864   /* Check the parameters */
03865   assert_param(IS_TIM_INSTANCE(htim->Instance));
03866   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
03867
03868   /* Process Locked */
03869   __HAL_LOCK(htim);
03870
03871   /* Change the TIM state */
03872   htim->State = HAL_TIM_STATE_BUSY;
03873
03874   /* Set the event sources */
03875   htim->Instance->EGR = EventSource;
03876
03877   /* Change the TIM state */
03878   htim->State = HAL_TIM_STATE_READY;
03879
03880   __HAL_UNLOCK(htim);
03881
03882   /* Return function status */
03883   return HAL_OK;
03884 }
03885
03886 /**
03887   * @brief  Configures the OCRef clear feature
03888   * @param  htim: TIM handle
03889   * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
03890   *         contains the OCREF clear feature and parameters for the TIM peripheral.
03891   * @param  Channel: specifies the TIM Channel
03892   *          This parameter can be one of the following values:
03893   *            @arg TIM_Channel_1: TIM Channel 1
03894   *            @arg TIM_Channel_2: TIM Channel 2
03895   *            @arg TIM_Channel_3: TIM Channel 3
03896   *            @arg TIM_Channel_4: TIM Channel 4
03897   *            @arg TIM_Channel_5: TIM Channel 5
03898   *            @arg TIM_Channel_6: TIM Channel 6
03899   * @retval None
03900   */
03901 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
03902                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
03903                                            uint32_t Channel)
03904 {
03905   uint32_t tmpsmcr = 0;
03906
03907   /* Check the parameters */
03908   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
03909   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
03910
03911   /* Process Locked */
03912   __HAL_LOCK(htim);
03913
03914   switch (sClearInputConfig->ClearInputSource)
03915   {
03916     case TIM_CLEARINPUTSOURCE_NONE:
03917     {
03918       /* Get the TIMx SMCR register value */
03919       tmpsmcr = htim->Instance->SMCR;
03920
03921       /* Clear the OCREF clear selection bit */
03922       tmpsmcr &= ~TIM_SMCR_OCCS;
03923
03924       /* Clear the ETR Bits */
03925       tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
03926
03927       /* Set TIMx_SMCR */
03928       htim->Instance->SMCR = tmpsmcr;
03929    }
03930     break;
03931
03932     case TIM_CLEARINPUTSOURCE_OCREFCLR:
03933     {
03934       /* Clear the OCREF clear selection bit */
03935       htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
03936     }
03937     break;
03938
03939     case TIM_CLEARINPUTSOURCE_ETR:
03940     {
03941       /* Check the parameters */
03942       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
03943       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
03944       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
03945
03946       TIM_ETR_SetConfig(htim->Instance,
03947                         sClearInputConfig->ClearInputPrescaler,
03948                         sClearInputConfig->ClearInputPolarity,
03949                         sClearInputConfig->ClearInputFilter);
03950
03951       /* Set the OCREF clear selection bit */
03952       htim->Instance->SMCR |= TIM_SMCR_OCCS;
03953     }
03954     break;
03955
03956   default:
03957     break;
03958   }
03959
03960   switch (Channel)
03961   {
03962     case TIM_CHANNEL_1:
03963       {
03964         if(sClearInputConfig->ClearInputState != RESET)
03965         {
03966           /* Enable the OCREF clear feature for Channel 1 */
03967           htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
03968         }
03969         else
03970         {
03971           /* Disable the OCREF clear feature for Channel 1 */
03972           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
03973         }
03974       }
03975       break;
03976     case TIM_CHANNEL_2:
03977       {
03978         if(sClearInputConfig->ClearInputState != RESET)
03979         {
03980           /* Enable the OCREF clear feature for Channel 2 */
03981           htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
03982         }
03983         else
03984         {
03985           /* Disable the OCREF clear feature for Channel 2 */
03986           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
03987         }
03988       }
03989     break;
03990     case TIM_CHANNEL_3:
03991       {
03992         if(sClearInputConfig->ClearInputState != RESET)
03993         {
03994           /* Enable the OCREF clear feature for Channel 3 */
03995           htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
03996         }
03997         else
03998         {
03999           /* Disable the OCREF clear feature for Channel 3 */
04000           htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
04001         }
04002       }
04003     break;
04004     case TIM_CHANNEL_4:
04005       {
04006         if(sClearInputConfig->ClearInputState != RESET)
04007         {
04008           /* Enable the OCREF clear feature for Channel 4 */
04009           htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
04010         }
04011         else
04012         {
04013           /* Disable the OCREF clear feature for Channel 4 */
04014           htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
04015         }
04016       }
04017     break;
04018     case TIM_CHANNEL_5:
04019       {
04020         if(sClearInputConfig->ClearInputState != RESET)
04021         {
04022           /* Enable the OCREF clear feature for Channel 1 */
04023           htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
04024         }
04025         else
04026         {
04027           /* Disable the OCREF clear feature for Channel 1 */
04028           htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
04029         }
04030       }
04031     break;
04032     case TIM_CHANNEL_6:
04033       {
04034         if(sClearInputConfig->ClearInputState != RESET)
04035         {
04036           /* Enable the OCREF clear feature for Channel 1 */
04037           htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
04038         }
04039         else
04040         {
04041           /* Disable the OCREF clear feature for Channel 1 */
04042           htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
04043         }
04044       }
04045     break;
04046     default:
04047     break;
04048   }
04049
04050   __HAL_UNLOCK(htim);
04051
04052   return HAL_OK;
04053 }
04054
04055 /**
04056   * @brief   Configures the clock source to be used
04057   * @param  htim: TIM handle
04058   * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
04059   *         contains the clock source information for the TIM peripheral.
04060   * @retval HAL status
04061   */
04062 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
04063 {
04064   uint32_t tmpsmcr = 0;
04065
04066   /* Process Locked */
04067   __HAL_LOCK(htim);
04068
04069   htim->State = HAL_TIM_STATE_BUSY;
04070
04071   /* Check the parameters */
04072   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
04073
04074   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
04075   tmpsmcr = htim->Instance->SMCR;
04076   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
04077   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
04078   htim->Instance->SMCR = tmpsmcr;
04079
04080   switch (sClockSourceConfig->ClockSource)
04081   {
04082   case TIM_CLOCKSOURCE_INTERNAL:
04083     {
04084       assert_param(IS_TIM_INSTANCE(htim->Instance));
04085       /* Disable slave mode to clock the prescaler directly with the internal clock */
04086       htim->Instance->SMCR &= ~TIM_SMCR_SMS;
04087     }
04088     break;
04089
04090   case TIM_CLOCKSOURCE_ETRMODE1:
04091     {
04092       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
04093       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
04094
04095       /* Check ETR input conditioning related parameters */
04096       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04097       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04098       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04099
04100       /* Configure the ETR Clock source */
04101       TIM_ETR_SetConfig(htim->Instance,
04102                         sClockSourceConfig->ClockPrescaler,
04103                         sClockSourceConfig->ClockPolarity,
04104                         sClockSourceConfig->ClockFilter);
04105       /* Get the TIMx SMCR register value */
04106       tmpsmcr = htim->Instance->SMCR;
04107       /* Reset the SMS and TS Bits */
04108       tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
04109       /* Select the External clock mode1 and the ETRF trigger */
04110       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
04111       /* Write to TIMx SMCR */
04112       htim->Instance->SMCR = tmpsmcr;
04113     }
04114     break;
04115
04116   case TIM_CLOCKSOURCE_ETRMODE2:
04117     {
04118       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
04119       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
04120
04121       /* Check ETR input conditioning related parameters */
04122       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04123       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04124       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04125
04126       /* Configure the ETR Clock source */
04127       TIM_ETR_SetConfig(htim->Instance,
04128                         sClockSourceConfig->ClockPrescaler,
04129                         sClockSourceConfig->ClockPolarity,
04130                         sClockSourceConfig->ClockFilter);
04131       /* Enable the External clock mode2 */
04132       htim->Instance->SMCR |= TIM_SMCR_ECE;
04133     }
04134     break;
04135
04136   case TIM_CLOCKSOURCE_TI1:
04137     {
04138       /* Check whether or not the timer instance supports external clock mode 1 */
04139       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04140
04141       /* Check TI1 input conditioning related parameters */
04142       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04143       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04144
04145       TIM_TI1_ConfigInputStage(htim->Instance,
04146                                sClockSourceConfig->ClockPolarity,
04147                                sClockSourceConfig->ClockFilter);
04148       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
04149     }
04150     break;
04151
04152   case TIM_CLOCKSOURCE_TI2:
04153     {
04154       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
04155       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04156
04157        /* Check TI2 input conditioning related parameters */
04158       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04159       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04160
04161       TIM_TI2_ConfigInputStage(htim->Instance,
04162                                sClockSourceConfig->ClockPolarity,
04163                                sClockSourceConfig->ClockFilter);
04164       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
04165     }
04166     break;
04167
04168   case TIM_CLOCKSOURCE_TI1ED:
04169     {
04170       /* Check whether or not the timer instance supports external clock mode 1 */
04171       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04172
04173       /* Check TI1 input conditioning related parameters */
04174       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04175       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04176
04177       TIM_TI1_ConfigInputStage(htim->Instance,
04178                                sClockSourceConfig->ClockPolarity,
04179                                sClockSourceConfig->ClockFilter);
04180       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
04181     }
04182     break;
04183
04184   case TIM_CLOCKSOURCE_ITR0:
04185     {
04186       /* Check whether or not the timer instance supports internal trigger input */
04187       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04188
04189       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
04190     }
04191     break;
04192
04193   case TIM_CLOCKSOURCE_ITR1:
04194     {
04195       /* Check whether or not the timer instance supports internal trigger input */
04196       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04197
04198       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
04199     }
04200     break;
04201
04202   case TIM_CLOCKSOURCE_ITR2:
04203     {
04204       /* Check whether or not the timer instance supports internal trigger input */
04205       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04206
04207       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
04208     }
04209     break;
04210
04211   case TIM_CLOCKSOURCE_ITR3:
04212     {
04213       /* Check whether or not the timer instance supports internal trigger input */
04214       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04215
04216       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
04217     }
04218     break;
04219
04220   default:
04221     break;
04222   }
04223   htim->State = HAL_TIM_STATE_READY;
04224
04225   __HAL_UNLOCK(htim);
04226
04227   return HAL_OK;
04228 }
04229
04230 /**
04231   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
04232   *         or a XOR combination between CH1_input, CH2_input & CH3_input
04233   * @param  htim: TIM handle.
04234   * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
04235   *         output of a XOR gate.
04236   *          This parameter can be one of the following values:
04237   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
04238   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
04239   *            pins are connected to the TI1 input (XOR combination)
04240   * @retval HAL status
04241   */
04242 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
04243 {
04244   uint32_t tmpcr2 = 0;
04245
04246   /* Check the parameters */
04247   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
04248   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
04249
04250   /* Get the TIMx CR2 register value */
04251   tmpcr2 = htim->Instance->CR2;
04252
04253   /* Reset the TI1 selection */
04254   tmpcr2 &= ~TIM_CR2_TI1S;
04255
04256   /* Set the TI1 selection */
04257   tmpcr2 |= TI1_Selection;
04258
04259   /* Write to TIMxCR2 */
04260   htim->Instance->CR2 = tmpcr2;
04261
04262   return HAL_OK;
04263 }
04264
04265 /**
04266   * @brief  Configures the TIM in Slave mode
04267   * @param  htim: TIM handle.
04268   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
04269   *         contains the selected trigger (internal trigger input, filtered
04270   *         timer input or external trigger input) and the ) and the Slave
04271   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04272   * @retval HAL status
04273   */
04274 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
04275 {
04276   /* Check the parameters */
04277   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04278   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04279   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04280
04281   __HAL_LOCK(htim);
04282
04283   htim->State = HAL_TIM_STATE_BUSY;
04284
04285   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04286
04287   /* Disable Trigger Interrupt */
04288   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
04289
04290   /* Disable Trigger DMA request */
04291   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04292
04293   htim->State = HAL_TIM_STATE_READY;
04294
04295   __HAL_UNLOCK(htim);
04296
04297   return HAL_OK;
04298     }
04299
04300 /**
04301   * @brief  Configures the TIM in Slave mode in interrupt mode
04302   * @param  htim: TIM handle.
04303   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
04304   *         contains the selected trigger (internal trigger input, filtered
04305   *         timer input or external trigger input) and the ) and the Slave
04306   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04307   * @retval HAL status
04308   */
04309 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
04310                                                         TIM_SlaveConfigTypeDef * sSlaveConfig)
04311     {
04312       /* Check the parameters */
04313   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04314   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04315   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04316
04317   __HAL_LOCK(htim);
04318
04319   htim->State = HAL_TIM_STATE_BUSY;
04320
04321   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04322
04323   /* Enable Trigger Interrupt */
04324   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
04325
04326   /* Disable Trigger DMA request */
04327   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04328
04329   htim->State = HAL_TIM_STATE_READY;
04330
04331   __HAL_UNLOCK(htim);
04332
04333   return HAL_OK;
04334     }
04335
04336 /**
04337   * @brief  Read the captured value from Capture Compare unit
04338   * @param  htim: TIM handle.
04339   * @param  Channel : TIM Channels to be enabled
04340   *          This parameter can be one of the following values:
04341   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04342   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04343   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04344   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04345   * @retval Captured value
04346   */
04347 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
04348 {
04349   uint32_t tmpreg = 0;
04350
04351   __HAL_LOCK(htim);
04352
04353   switch (Channel)
04354   {
04355   case TIM_CHANNEL_1:
04356     {
04357       /* Check the parameters */
04358       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04359
04360       /* Return the capture 1 value */
04361       tmpreg =  htim->Instance->CCR1;
04362
04363       break;
04364     }
04365   case TIM_CHANNEL_2:
04366     {
04367       /* Check the parameters */
04368       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04369
04370       /* Return the capture 2 value */
04371       tmpreg =   htim->Instance->CCR2;
04372
04373       break;
04374     }
04375
04376   case TIM_CHANNEL_3:
04377     {
04378       /* Check the parameters */
04379       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04380
04381       /* Return the capture 3 value */
04382       tmpreg =   htim->Instance->CCR3;
04383
04384       break;
04385     }
04386
04387   case TIM_CHANNEL_4:
04388     {
04389       /* Check the parameters */
04390       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04391
04392       /* Return the capture 4 value */
04393       tmpreg =   htim->Instance->CCR4;
04394
04395       break;
04396     }
04397
04398   default:
04399     break;
04400   }
04401
04402   __HAL_UNLOCK(htim);
04403   return tmpreg;
04404 }
04405
04406 /**
04407   * @}
04408   */
04409
04410 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
04411  *  @brief    TIM Callbacks functions
04412  *
04413 @verbatim
04414   ==============================================================================
04415                         ##### TIM Callbacks functions #####
04416   ==============================================================================
04417  [..]
04418    This section provides TIM callback functions:
04419    (+) Timer Period elapsed callback
04420    (+) Timer Output Compare callback
04421    (+) Timer Input capture callback
04422    (+) Timer Trigger callback
04423    (+) Timer Error callback
04424
04425 @endverbatim
04426   * @{
04427   */
04428
04429 /**
04430   * @brief  Period elapsed callback in non-blocking mode
04431   * @param  htim : TIM handle
04432   * @retval None
04433   */
04434 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
04435 {
04436   /* Prevent unused argument(s) compilation warning */
04437   UNUSED(htim);
04438
04439   /* NOTE : This function should not be modified, when the callback is needed,
04440             the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
04441    */
04442
04443 }
04444 /**
04445   * @brief  Output Compare callback in non-blocking mode
04446   * @param  htim : TIM OC handle
04447   * @retval None
04448   */
04449 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
04450 {
04451   /* Prevent unused argument(s) compilation warning */
04452   UNUSED(htim);
04453
04454   /* NOTE : This function should not be modified, when the callback is needed,
04455             the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
04456    */
04457 }
04458 /**
04459   * @brief  Input Capture callback in non-blocking mode
04460   * @param  htim : TIM IC handle
04461   * @retval None
04462   */
04463 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
04464 {
04465   /* Prevent unused argument(s) compilation warning */
04466   UNUSED(htim);
04467
04468   /* NOTE : This function should not be modified, when the callback is needed,
04469             the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
04470    */
04471 }
04472
04473 /**
04474   * @brief  PWM Pulse finished callback in non-blocking mode
04475   * @param  htim : TIM handle
04476   * @retval None
04477   */
04478 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
04479 {
04480   /* Prevent unused argument(s) compilation warning */
04481   UNUSED(htim);
04482
04483   /* NOTE : This function should not be modified, when the callback is needed,
04484             the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
04485    */
04486 }
04487
04488 /**
04489   * @brief  Hall Trigger detection callback in non-blocking mode
04490   * @param  htim : TIM handle
04491   * @retval None
04492   */
04493 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
04494 {
04495   /* Prevent unused argument(s) compilation warning */
04496   UNUSED(htim);
04497
04498   /* NOTE : This function should not be modified, when the callback is needed,
04499             the HAL_TIM_TriggerCallback could be implemented in the user file
04500    */
04501 }
04502
04503 /**
04504   * @brief  Timer error callback in non-blocking mode
04505   * @param  htim : TIM handle
04506   * @retval None
04507   */
04508 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
04509 {
04510   /* Prevent unused argument(s) compilation warning */
04511   UNUSED(htim);
04512
04513   /* NOTE : This function should not be modified, when the callback is needed,
04514             the HAL_TIM_ErrorCallback could be implemented in the user file
04515    */
04516 }
04517
04518 /**
04519   * @}
04520   */
04521
04522 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
04523  *  @brief   Peripheral State functions
04524  *
04525 @verbatim
04526   ==============================================================================
04527                         ##### Peripheral State functions #####
04528   ==============================================================================
04529     [..]
04530     This subsection permits to get in run-time the status of the peripheral
04531     and the data flow.
04532
04533 @endverbatim
04534   * @{
04535   */
04536
04537 /**
04538   * @brief  Return the TIM Base handle state.
04539   * @param  htim: TIM Base handle
04540   * @retval HAL state
04541   */
04542 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
04543 {
04544   return htim->State;
04545 }
04546
04547 /**
04548   * @brief  Return the TIM OC handle state.
04549   * @param  htim: TIM Ouput Compare handle
04550   * @retval HAL state
04551   */
04552 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
04553 {
04554   return htim->State;
04555 }
04556
04557 /**
04558   * @brief  Return the TIM PWM handle state.
04559   * @param  htim: TIM handle
04560   * @retval HAL state
04561   */
04562 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
04563 {
04564   return htim->State;
04565 }
04566
04567 /**
04568   * @brief  Return the TIM Input Capture handle state.
04569   * @param  htim: TIM IC handle
04570   * @retval HAL state
04571   */
04572 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
04573 {
04574   return htim->State;
04575 }
04576
04577 /**
04578   * @brief  Return the TIM One Pulse Mode handle state.
04579   * @param  htim: TIM OPM handle
04580   * @retval HAL state
04581   */
04582 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
04583 {
04584   return htim->State;
04585 }
04586
04587 /**
04588   * @brief  Return the TIM Encoder Mode handle state.
04589   * @param  htim: TIM Encoder handle
04590   * @retval HAL state
04591   */
04592 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
04593 {
04594   return htim->State;
04595 }
04596
04597 /**
04598   * @}
04599   */
04600
04601 /**
04602   * @brief  TIM DMA error callback
04603   * @param  hdma : pointer to DMA handle.
04604   * @retval None
04605   */
04606 void TIM_DMAError(DMA_HandleTypeDef *hdma)
04607 {
04608   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04609
04610   htim->State= HAL_TIM_STATE_READY;
04611
04612   HAL_TIM_ErrorCallback(htim);
04613 }
04614
04615 /**
04616   * @brief  TIM DMA Delay Pulse complete callback.
04617   * @param  hdma : pointer to DMA handle.
04618   * @retval None
04619   */
04620 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
04621 {
04622   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04623
04624   htim->State= HAL_TIM_STATE_READY;
04625
04626   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04627   {
04628     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04629   }
04630   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04631   {
04632     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04633   }
04634   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04635   {
04636     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04637   }
04638   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04639   {
04640     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04641   }
04642
04643   HAL_TIM_PWM_PulseFinishedCallback(htim);
04644
04645   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04646 }
04647 /**
04648   * @brief  TIM DMA Capture complete callback.
04649   * @param  hdma : pointer to DMA handle.
04650   * @retval None
04651   */
04652 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
04653 {
04654   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04655
04656   htim->State= HAL_TIM_STATE_READY;
04657
04658   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04659   {
04660     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04661   }
04662   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04663   {
04664     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04665   }
04666   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04667   {
04668     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04669   }
04670   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04671   {
04672     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04673   }
04674
04675   HAL_TIM_IC_CaptureCallback(htim);
04676
04677   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04678 }
04679
04680 /**
04681   * @brief  TIM DMA Period Elapse complete callback.
04682   * @param  hdma : pointer to DMA handle.
04683   * @retval None
04684   */
04685 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
04686 {
04687   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04688
04689   htim->State= HAL_TIM_STATE_READY;
04690
04691   HAL_TIM_PeriodElapsedCallback(htim);
04692 }
04693
04694 /**
04695   * @brief  TIM DMA Trigger callback.
04696   * @param  hdma : pointer to DMA handle.
04697   * @retval None
04698   */
04699 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
04700 {
04701   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04702
04703   htim->State= HAL_TIM_STATE_READY;
04704
04705   HAL_TIM_TriggerCallback(htim);
04706 }
04707
04708 /**
04709   * @brief  Time Base configuration
04710   * @param  TIMx: TIM peripheral
04711   * @param  Structure: TIM Base configuration structure
04712   * @retval None
04713   */
04714 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
04715 {
04716   uint32_t tmpcr1 = 0;
04717   tmpcr1 = TIMx->CR1;
04718
04719   /* Set TIM Time Base Unit parameters ---------------------------------------*/
04720   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
04721   {
04722     /* Select the Counter Mode */
04723     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
04724     tmpcr1 |= Structure->CounterMode;
04725   }
04726
04727   if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
04728   {
04729     /* Set the clock division */
04730     tmpcr1 &= ~TIM_CR1_CKD;
04731     tmpcr1 |= (uint32_t)Structure->ClockDivision;
04732   }
04733
04734   TIMx->CR1 = tmpcr1;
04735
04736   /* Set the Autoreload value */
04737   TIMx->ARR = (uint32_t)Structure->Period ;
04738
04739   /* Set the Prescaler value */
04740   TIMx->PSC = (uint32_t)Structure->Prescaler;
04741
04742   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
04743   {
04744     /* Set the Repetition Counter value */
04745     TIMx->RCR = Structure->RepetitionCounter;
04746   }
04747
04748   /* Generate an update event to reload the Prescaler
04749      and the repetition counter(only for TIM1 and TIM8) value immediately */
04750   TIMx->EGR = TIM_EGR_UG;
04751 }
04752
04753 /**
04754   * @brief  Time Ouput Compare 1 configuration
04755   * @param  TIMx to select the TIM peripheral
04756   * @param  OC_Config: The ouput configuration structure
04757   * @retval None
04758   */
04759 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04760 {
04761   uint32_t tmpccmrx = 0;
04762   uint32_t tmpccer = 0;
04763   uint32_t tmpcr2 = 0;
04764
04765    /* Disable the Channel 1: Reset the CC1E Bit */
04766   TIMx->CCER &= ~TIM_CCER_CC1E;
04767
04768   /* Get the TIMx CCER register value */
04769   tmpccer = TIMx->CCER;
04770   /* Get the TIMx CR2 register value */
04771   tmpcr2 =  TIMx->CR2;
04772
04773   /* Get the TIMx CCMR1 register value */
04774   tmpccmrx = TIMx->CCMR1;
04775
04776   /* Reset the Output Compare Mode Bits */
04777   tmpccmrx &= ~TIM_CCMR1_OC1M;
04778   tmpccmrx &= ~TIM_CCMR1_CC1S;
04779   /* Select the Output Compare Mode */
04780   tmpccmrx |= OC_Config->OCMode;
04781
04782   /* Reset the Output Polarity level */
04783   tmpccer &= ~TIM_CCER_CC1P;
04784   /* Set the Output Compare Polarity */
04785   tmpccer |= OC_Config->OCPolarity;
04786
04787   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
04788   {
04789     /* Check parameters */
04790     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04791
04792     /* Reset the Output N Polarity level */
04793     tmpccer &= ~TIM_CCER_CC1NP;
04794     /* Set the Output N Polarity */
04795     tmpccer |= OC_Config->OCNPolarity;
04796     /* Reset the Output N State */
04797     tmpccer &= ~TIM_CCER_CC1NE;
04798   }
04799
04800   if(IS_TIM_BREAK_INSTANCE(TIMx))
04801   {
04802     /* Check parameters */
04803     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04804     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04805
04806     /* Reset the Output Compare and Output Compare N IDLE State */
04807     tmpcr2 &= ~TIM_CR2_OIS1;
04808     tmpcr2 &= ~TIM_CR2_OIS1N;
04809     /* Set the Output Idle state */
04810     tmpcr2 |= OC_Config->OCIdleState;
04811     /* Set the Output N Idle state */
04812     tmpcr2 |= OC_Config->OCNIdleState;
04813   }
04814   /* Write to TIMx CR2 */
04815   TIMx->CR2 = tmpcr2;
04816
04817   /* Write to TIMx CCMR1 */
04818   TIMx->CCMR1 = tmpccmrx;
04819
04820   /* Set the Capture Compare Register value */
04821   TIMx->CCR1 = OC_Config->Pulse;
04822
04823   /* Write to TIMx CCER */
04824   TIMx->CCER = tmpccer;
04825 }
04826
04827 /**
04828   * @brief  Time Ouput Compare 2 configuration
04829   * @param  TIMx to select the TIM peripheral
04830   * @param  OC_Config: The ouput configuration structure
04831   * @retval None
04832   */
04833 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04834 {
04835   uint32_t tmpccmrx = 0;
04836   uint32_t tmpccer = 0;
04837   uint32_t tmpcr2 = 0;
04838
04839   /* Disable the Channel 2: Reset the CC2E Bit */
04840   TIMx->CCER &= ~TIM_CCER_CC2E;
04841
04842   /* Get the TIMx CCER register value */
04843   tmpccer = TIMx->CCER;
04844   /* Get the TIMx CR2 register value */
04845   tmpcr2 =  TIMx->CR2;
04846
04847   /* Get the TIMx CCMR1 register value */
04848   tmpccmrx = TIMx->CCMR1;
04849
04850   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04851   tmpccmrx &= ~TIM_CCMR1_OC2M;
04852   tmpccmrx &= ~TIM_CCMR1_CC2S;
04853
04854   /* Select the Output Compare Mode */
04855   tmpccmrx |= (OC_Config->OCMode << 8);
04856
04857   /* Reset the Output Polarity level */
04858   tmpccer &= ~TIM_CCER_CC2P;
04859   /* Set the Output Compare Polarity */
04860   tmpccer |= (OC_Config->OCPolarity << 4);
04861
04862   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
04863   {
04864     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04865
04866     /* Reset the Output N Polarity level */
04867     tmpccer &= ~TIM_CCER_CC2NP;
04868     /* Set the Output N Polarity */
04869     tmpccer |= (OC_Config->OCNPolarity << 4);
04870     /* Reset the Output N State */
04871     tmpccer &= ~TIM_CCER_CC2NE;
04872
04873   }
04874
04875   if(IS_TIM_BREAK_INSTANCE(TIMx))
04876   {
04877     /* Check parameters */
04878     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04879     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04880
04881     /* Reset the Output Compare and Output Compare N IDLE State */
04882     tmpcr2 &= ~TIM_CR2_OIS2;
04883     tmpcr2 &= ~TIM_CR2_OIS2N;
04884     /* Set the Output Idle state */
04885     tmpcr2 |= (OC_Config->OCIdleState << 2);
04886     /* Set the Output N Idle state */
04887     tmpcr2 |= (OC_Config->OCNIdleState << 2);
04888   }
04889
04890   /* Write to TIMx CR2 */
04891   TIMx->CR2 = tmpcr2;
04892
04893   /* Write to TIMx CCMR1 */
04894   TIMx->CCMR1 = tmpccmrx;
04895
04896   /* Set the Capture Compare Register value */
04897   TIMx->CCR2 = OC_Config->Pulse;
04898
04899   /* Write to TIMx CCER */
04900   TIMx->CCER = tmpccer;
04901 }
04902
04903 /**
04904   * @brief  Time Ouput Compare 3 configuration
04905   * @param  TIMx to select the TIM peripheral
04906   * @param  OC_Config: The ouput configuration structure
04907   * @retval None
04908   */
04909 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04910 {
04911   uint32_t tmpccmrx = 0;
04912   uint32_t tmpccer = 0;
04913   uint32_t tmpcr2 = 0;
04914
04915   /* Disable the Channel 3: Reset the CC2E Bit */
04916   TIMx->CCER &= ~TIM_CCER_CC3E;
04917
04918   /* Get the TIMx CCER register value */
04919   tmpccer = TIMx->CCER;
04920   /* Get the TIMx CR2 register value */
04921   tmpcr2 =  TIMx->CR2;
04922
04923   /* Get the TIMx CCMR2 register value */
04924   tmpccmrx = TIMx->CCMR2;
04925
04926   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04927   tmpccmrx &= ~TIM_CCMR2_OC3M;
04928   tmpccmrx &= ~TIM_CCMR2_CC3S;
04929   /* Select the Output Compare Mode */
04930   tmpccmrx |= OC_Config->OCMode;
04931
04932   /* Reset the Output Polarity level */
04933   tmpccer &= ~TIM_CCER_CC3P;
04934   /* Set the Output Compare Polarity */
04935   tmpccer |= (OC_Config->OCPolarity << 8);
04936
04937   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
04938   {
04939     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04940
04941     /* Reset the Output N Polarity level */
04942     tmpccer &= ~TIM_CCER_CC3NP;
04943     /* Set the Output N Polarity */
04944     tmpccer |= (OC_Config->OCNPolarity << 8);
04945     /* Reset the Output N State */
04946     tmpccer &= ~TIM_CCER_CC3NE;
04947   }
04948
04949   if(IS_TIM_BREAK_INSTANCE(TIMx))
04950   {
04951     /* Check parameters */
04952     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04953     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04954
04955     /* Reset the Output Compare and Output Compare N IDLE State */
04956     tmpcr2 &= ~TIM_CR2_OIS3;
04957     tmpcr2 &= ~TIM_CR2_OIS3N;
04958     /* Set the Output Idle state */
04959     tmpcr2 |= (OC_Config->OCIdleState << 4);
04960     /* Set the Output N Idle state */
04961     tmpcr2 |= (OC_Config->OCNIdleState << 4);
04962   }
04963
04964   /* Write to TIMx CR2 */
04965   TIMx->CR2 = tmpcr2;
04966
04967   /* Write to TIMx CCMR2 */
04968   TIMx->CCMR2 = tmpccmrx;
04969
04970   /* Set the Capture Compare Register value */
04971   TIMx->CCR3 = OC_Config->Pulse;
04972
04973   /* Write to TIMx CCER */
04974   TIMx->CCER = tmpccer;
04975 }
04976
04977 /**
04978   * @brief  Time Ouput Compare 4 configuration
04979   * @param  TIMx to select the TIM peripheral
04980   * @param  OC_Config: The ouput configuration structure
04981   * @retval None
04982   */
04983 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04984 {
04985   uint32_t tmpccmrx = 0;
04986   uint32_t tmpccer = 0;
04987   uint32_t tmpcr2 = 0;
04988
04989   /* Disable the Channel 4: Reset the CC4E Bit */
04990   TIMx->CCER &= ~TIM_CCER_CC4E;
04991
04992   /* Get the TIMx CCER register value */
04993   tmpccer = TIMx->CCER;
04994   /* Get the TIMx CR2 register value */
04995   tmpcr2 =  TIMx->CR2;
04996
04997   /* Get the TIMx CCMR2 register value */
04998   tmpccmrx = TIMx->CCMR2;
04999
05000   /* Reset the Output Compare mode and Capture/Compare selection Bits */
05001   tmpccmrx &= ~TIM_CCMR2_OC4M;
05002   tmpccmrx &= ~TIM_CCMR2_CC4S;
05003
05004   /* Select the Output Compare Mode */
05005   tmpccmrx |= (OC_Config->OCMode << 8);
05006
05007   /* Reset the Output Polarity level */
05008   tmpccer &= ~TIM_CCER_CC4P;
05009   /* Set the Output Compare Polarity */
05010   tmpccer |= (OC_Config->OCPolarity << 12);
05011
05012   if(IS_TIM_BREAK_INSTANCE(TIMx))
05013   {
05014     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
05015
05016    /* Reset the Output Compare IDLE State */
05017     tmpcr2 &= ~TIM_CR2_OIS4;
05018     /* Set the Output Idle state */
05019     tmpcr2 |= (OC_Config->OCIdleState << 6);
05020   }
05021
05022   /* Write to TIMx CR2 */
05023   TIMx->CR2 = tmpcr2;
05024
05025   /* Write to TIMx CCMR2 */
05026   TIMx->CCMR2 = tmpccmrx;
05027
05028   /* Set the Capture Compare Register value */
05029   TIMx->CCR4 = OC_Config->Pulse;
05030
05031   /* Write to TIMx CCER */
05032   TIMx->CCER = tmpccer;
05033 }
05034
05035 /**
05036   * @brief  Timer Ouput Compare 5 configuration
05037   * @param  TIMx to select the TIM peripheral
05038   * @param  OC_Config: The ouput configuration structure
05039   * @retval None
05040   */
05041 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
05042                               TIM_OC_InitTypeDef *OC_Config)
05043 {
05044   uint32_t tmpccmrx = 0;
05045   uint32_t tmpccer = 0;
05046   uint32_t tmpcr2 = 0;
05047
05048   /* Disable the output: Reset the CCxE Bit */
05049   TIMx->CCER &= ~TIM_CCER_CC5E;
05050
05051   /* Get the TIMx CCER register value */
05052   tmpccer = TIMx->CCER;
05053   /* Get the TIMx CR2 register value */
05054   tmpcr2 =  TIMx->CR2;
05055   /* Get the TIMx CCMR1 register value */
05056   tmpccmrx = TIMx->CCMR3;
05057
05058   /* Reset the Output Compare Mode Bits */
05059   tmpccmrx &= ~(TIM_CCMR3_OC5M);
05060   /* Select the Output Compare Mode */
05061   tmpccmrx |= OC_Config->OCMode;
05062
05063   /* Reset the Output Polarity level */
05064   tmpccer &= ~TIM_CCER_CC5P;
05065   /* Set the Output Compare Polarity */
05066   tmpccer |= (OC_Config->OCPolarity << 16);
05067
05068   if(IS_TIM_BREAK_INSTANCE(TIMx))
05069   {
05070     /* Reset the Output Compare IDLE State */
05071     tmpcr2 &= ~TIM_CR2_OIS5;
05072     /* Set the Output Idle state */
05073     tmpcr2 |= (OC_Config->OCIdleState << 8);
05074   }
05075   /* Write to TIMx CR2 */
05076   TIMx->CR2 = tmpcr2;
05077
05078   /* Write to TIMx CCMR3 */
05079   TIMx->CCMR3 = tmpccmrx;
05080
05081   /* Set the Capture Compare Register value */
05082   TIMx->CCR5 = OC_Config->Pulse;
05083
05084   /* Write to TIMx CCER */
05085   TIMx->CCER = tmpccer;
05086 }
05087
05088 /**
05089   * @brief  Timer Ouput Compare 6 configuration
05090   * @param  TIMx to select the TIM peripheral
05091   * @param  OC_Config: The ouput configuration structure
05092   * @retval None
05093   */
05094 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
05095                               TIM_OC_InitTypeDef *OC_Config)
05096 {
05097   uint32_t tmpccmrx = 0;
05098   uint32_t tmpccer = 0;
05099   uint32_t tmpcr2 = 0;
05100
05101   /* Disable the output: Reset the CCxE Bit */
05102   TIMx->CCER &= ~TIM_CCER_CC6E;
05103
05104   /* Get the TIMx CCER register value */
05105   tmpccer = TIMx->CCER;
05106   /* Get the TIMx CR2 register value */
05107   tmpcr2 =  TIMx->CR2;
05108   /* Get the TIMx CCMR1 register value */
05109   tmpccmrx = TIMx->CCMR3;
05110
05111   /* Reset the Output Compare Mode Bits */
05112   tmpccmrx &= ~(TIM_CCMR3_OC6M);
05113   /* Select the Output Compare Mode */
05114   tmpccmrx |= (OC_Config->OCMode << 8);
05115
05116   /* Reset the Output Polarity level */
05117   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
05118   /* Set the Output Compare Polarity */
05119   tmpccer |= (OC_Config->OCPolarity << 20);
05120
05121   if(IS_TIM_BREAK_INSTANCE(TIMx))
05122   {
05123     /* Reset the Output Compare IDLE State */
05124     tmpcr2 &= ~TIM_CR2_OIS6;
05125     /* Set the Output Idle state */
05126     tmpcr2 |= (OC_Config->OCIdleState << 10);
05127   }
05128
05129   /* Write to TIMx CR2 */
05130   TIMx->CR2 = tmpcr2;
05131
05132   /* Write to TIMx CCMR3 */
05133   TIMx->CCMR3 = tmpccmrx;
05134
05135   /* Set the Capture Compare Register value */
05136   TIMx->CCR6 = OC_Config->Pulse;
05137
05138   /* Write to TIMx CCER */
05139   TIMx->CCER = tmpccer;
05140 }
05141
05142 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
05143                                      TIM_SlaveConfigTypeDef * sSlaveConfig)
05144 {
05145   uint32_t tmpsmcr = 0;
05146   uint32_t tmpccmr1 = 0;
05147   uint32_t tmpccer = 0;
05148
05149   /* Get the TIMx SMCR register value */
05150   tmpsmcr = htim->Instance->SMCR;
05151
05152   /* Reset the Trigger Selection Bits */
05153   tmpsmcr &= ~TIM_SMCR_TS;
05154   /* Set the Input Trigger source */
05155   tmpsmcr |= sSlaveConfig->InputTrigger;
05156
05157   /* Reset the slave mode Bits */
05158   tmpsmcr &= ~TIM_SMCR_SMS;
05159   /* Set the slave mode */
05160   tmpsmcr |= sSlaveConfig->SlaveMode;
05161
05162   /* Write to TIMx SMCR */
05163   htim->Instance->SMCR = tmpsmcr;
05164
05165   /* Configure the trigger prescaler, filter, and polarity */
05166   switch (sSlaveConfig->InputTrigger)
05167   {
05168   case TIM_TS_ETRF:
05169     {
05170       /* Check the parameters */
05171       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
05172       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
05173       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05174       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05175       /* Configure the ETR Trigger source */
05176       TIM_ETR_SetConfig(htim->Instance,
05177                         sSlaveConfig->TriggerPrescaler,
05178                         sSlaveConfig->TriggerPolarity,
05179                         sSlaveConfig->TriggerFilter);
05180     }
05181     break;
05182
05183   case TIM_TS_TI1F_ED:
05184     {
05185       /* Check the parameters */
05186       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05187       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05188
05189       /* Disable the Channel 1: Reset the CC1E Bit */
05190       tmpccer = htim->Instance->CCER;
05191       htim->Instance->CCER &= ~TIM_CCER_CC1E;
05192       tmpccmr1 = htim->Instance->CCMR1;
05193
05194       /* Set the filter */
05195       tmpccmr1 &= ~TIM_CCMR1_IC1F;
05196       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
05197
05198       /* Write to TIMx CCMR1 and CCER registers */
05199       htim->Instance->CCMR1 = tmpccmr1;
05200       htim->Instance->CCER = tmpccer;
05201
05202     }
05203     break;
05204
05205   case TIM_TS_TI1FP1:
05206     {
05207       /* Check the parameters */
05208       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
05209       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05210       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05211
05212       /* Configure TI1 Filter and Polarity */
05213       TIM_TI1_ConfigInputStage(htim->Instance,
05214                                sSlaveConfig->TriggerPolarity,
05215                                sSlaveConfig->TriggerFilter);
05216     }
05217     break;
05218
05219   case TIM_TS_TI2FP2:
05220     {
05221       /* Check the parameters */
05222       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05223       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
05224       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
05225
05226       /* Configure TI2 Filter and Polarity */
05227       TIM_TI2_ConfigInputStage(htim->Instance,
05228                                 sSlaveConfig->TriggerPolarity,
05229                                 sSlaveConfig->TriggerFilter);
05230     }
05231     break;
05232
05233   case TIM_TS_ITR0:
05234     {
05235       /* Check the parameter */
05236       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05237     }
05238     break;
05239
05240   case TIM_TS_ITR1:
05241     {
05242       /* Check the parameter */
05243       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05244     }
05245     break;
05246
05247   case TIM_TS_ITR2:
05248     {
05249       /* Check the parameter */
05250       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05251     }
05252     break;
05253
05254   case TIM_TS_ITR3:
05255     {
05256       /* Check the parameter */
05257       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05258     }
05259     break;
05260
05261   default:
05262     break;
05263   }
05264 }
05265
05266 /**
05267   * @brief  Configure the TI1 as Input.
05268   * @param  TIMx to select the TIM peripheral.
05269   * @param  TIM_ICPolarity : The Input Polarity.
05270   *          This parameter can be one of the following values:
05271   *            @arg TIM_ICPolarity_Rising
05272   *            @arg TIM_ICPolarity_Falling
05273   *            @arg TIM_ICPolarity_BothEdge
05274   * @param  TIM_ICSelection: specifies the input to be used.
05275   *          This parameter can be one of the following values:
05276   *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
05277   *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
05278   *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
05279   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05280   *          This parameter must be a value between 0x00 and 0x0F.
05281   * @retval None
05282   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
05283   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
05284   *        protected against un-initialized filter and polarity values.
05285   */
05286 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05287                        uint32_t TIM_ICFilter)
05288 {
05289   uint32_t tmpccmr1 = 0;
05290   uint32_t tmpccer = 0;
05291
05292   /* Disable the Channel 1: Reset the CC1E Bit */
05293   TIMx->CCER &= ~TIM_CCER_CC1E;
05294   tmpccmr1 = TIMx->CCMR1;
05295   tmpccer = TIMx->CCER;
05296
05297   /* Select the Input */
05298   if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
05299   {
05300     tmpccmr1 &= ~TIM_CCMR1_CC1S;
05301     tmpccmr1 |= TIM_ICSelection;
05302   }
05303   else
05304   {
05305     tmpccmr1 |= TIM_CCMR1_CC1S_0;
05306   }
05307
05308   /* Set the filter */
05309   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05310   tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
05311
05312   /* Select the Polarity and set the CC1E Bit */
05313   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05314   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
05315
05316   /* Write to TIMx CCMR1 and CCER registers */
05317   TIMx->CCMR1 = tmpccmr1;
05318   TIMx->CCER = tmpccer;
05319 }
05320
05321 /**
05322   * @brief  Configure the Polarity and Filter for TI1.
05323   * @param  TIMx to select the TIM peripheral.
05324   * @param  TIM_ICPolarity : The Input Polarity.
05325   *          This parameter can be one of the following values:
05326   *            @arg TIM_ICPolarity_Rising
05327   *            @arg TIM_ICPolarity_Falling
05328   *            @arg TIM_ICPolarity_BothEdge
05329   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05330   *          This parameter must be a value between 0x00 and 0x0F.
05331   * @retval None
05332   */
05333 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05334 {
05335   uint32_t tmpccmr1 = 0;
05336   uint32_t tmpccer = 0;
05337
05338   /* Disable the Channel 1: Reset the CC1E Bit */
05339   tmpccer = TIMx->CCER;
05340   TIMx->CCER &= ~TIM_CCER_CC1E;
05341   tmpccmr1 = TIMx->CCMR1;
05342
05343   /* Set the filter */
05344   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05345   tmpccmr1 |= (TIM_ICFilter << 4);
05346
05347   /* Select the Polarity and set the CC1E Bit */
05348   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05349   tmpccer |= TIM_ICPolarity;
05350
05351   /* Write to TIMx CCMR1 and CCER registers */
05352   TIMx->CCMR1 = tmpccmr1;
05353   TIMx->CCER = tmpccer;
05354 }
05355
05356 /**
05357   * @brief  Configure the TI2 as Input.
05358   * @param  TIMx to select the TIM peripheral
05359   * @param  TIM_ICPolarity : The Input Polarity.
05360   *          This parameter can be one of the following values:
05361   *            @arg TIM_ICPolarity_Rising
05362   *            @arg TIM_ICPolarity_Falling
05363   *            @arg TIM_ICPolarity_BothEdge
05364   * @param  TIM_ICSelection: specifies the input to be used.
05365   *          This parameter can be one of the following values:
05366   *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
05367   *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
05368   *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
05369   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05370   *          This parameter must be a value between 0x00 and 0x0F.
05371   * @retval None
05372   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
05373   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
05374   *        protected against un-initialized filter and polarity values.
05375   */
05376 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05377                        uint32_t TIM_ICFilter)
05378 {
05379   uint32_t tmpccmr1 = 0;
05380   uint32_t tmpccer = 0;
05381
05382   /* Disable the Channel 2: Reset the CC2E Bit */
05383   TIMx->CCER &= ~TIM_CCER_CC2E;
05384   tmpccmr1 = TIMx->CCMR1;
05385   tmpccer = TIMx->CCER;
05386
05387   /* Select the Input */
05388   tmpccmr1 &= ~TIM_CCMR1_CC2S;
05389   tmpccmr1 |= (TIM_ICSelection << 8);
05390
05391   /* Set the filter */
05392   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05393   tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
05394
05395   /* Select the Polarity and set the CC2E Bit */
05396   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05397   tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
05398
05399   /* Write to TIMx CCMR1 and CCER registers */
05400   TIMx->CCMR1 = tmpccmr1 ;
05401   TIMx->CCER = tmpccer;
05402 }
05403
05404 /**
05405   * @brief  Configure the Polarity and Filter for TI2.
05406   * @param  TIMx to select the TIM peripheral.
05407   * @param  TIM_ICPolarity : The Input Polarity.
05408   *          This parameter can be one of the following values:
05409   *            @arg TIM_ICPolarity_Rising
05410   *            @arg TIM_ICPolarity_Falling
05411   *            @arg TIM_ICPolarity_BothEdge
05412   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05413   *          This parameter must be a value between 0x00 and 0x0F.
05414   * @retval None
05415   */
05416 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05417 {
05418   uint32_t tmpccmr1 = 0;
05419   uint32_t tmpccer = 0;
05420
05421   /* Disable the Channel 2: Reset the CC2E Bit */
05422   TIMx->CCER &= ~TIM_CCER_CC2E;
05423   tmpccmr1 = TIMx->CCMR1;
05424   tmpccer = TIMx->CCER;
05425
05426   /* Set the filter */
05427   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05428   tmpccmr1 |= (TIM_ICFilter << 12);
05429
05430   /* Select the Polarity and set the CC2E Bit */
05431   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05432   tmpccer |= (TIM_ICPolarity << 4);
05433
05434   /* Write to TIMx CCMR1 and CCER registers */
05435   TIMx->CCMR1 = tmpccmr1 ;
05436   TIMx->CCER = tmpccer;
05437 }
05438
05439 /**
05440   * @brief  Configure the TI3 as Input.
05441   * @param  TIMx to select the TIM peripheral
05442   * @param  TIM_ICPolarity : The Input Polarity.
05443   *          This parameter can be one of the following values:
05444   *            @arg TIM_ICPolarity_Rising
05445   *            @arg TIM_ICPolarity_Falling
05446   *            @arg TIM_ICPolarity_BothEdge
05447   * @param  TIM_ICSelection: specifies the input to be used.
05448   *          This parameter can be one of the following values:
05449   *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
05450   *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
05451   *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
05452   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05453   *          This parameter must be a value between 0x00 and 0x0F.
05454   * @retval None
05455   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
05456   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
05457   *        protected against un-initialized filter and polarity values.
05458   */
05459 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05460                        uint32_t TIM_ICFilter)
05461 {
05462   uint32_t tmpccmr2 = 0;
05463   uint32_t tmpccer = 0;
05464
05465   /* Disable the Channel 3: Reset the CC3E Bit */
05466   TIMx->CCER &= ~TIM_CCER_CC3E;
05467   tmpccmr2 = TIMx->CCMR2;
05468   tmpccer = TIMx->CCER;
05469
05470   /* Select the Input */
05471   tmpccmr2 &= ~TIM_CCMR2_CC3S;
05472   tmpccmr2 |= TIM_ICSelection;
05473
05474   /* Set the filter */
05475   tmpccmr2 &= ~TIM_CCMR2_IC3F;
05476   tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
05477
05478   /* Select the Polarity and set the CC3E Bit */
05479   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
05480   tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
05481
05482   /* Write to TIMx CCMR2 and CCER registers */
05483   TIMx->CCMR2 = tmpccmr2;
05484   TIMx->CCER = tmpccer;
05485 }
05486
05487 /**
05488   * @brief  Configure the TI4 as Input.
05489   * @param  TIMx to select the TIM peripheral
05490   * @param  TIM_ICPolarity : The Input Polarity.
05491   *          This parameter can be one of the following values:
05492   *            @arg TIM_ICPolarity_Rising
05493   *            @arg TIM_ICPolarity_Falling
05494   *            @arg TIM_ICPolarity_BothEdge
05495   * @param  TIM_ICSelection: specifies the input to be used.
05496   *          This parameter can be one of the following values:
05497   *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
05498   *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
05499   *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
05500   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
05501   *          This parameter must be a value between 0x00 and 0x0F.
05502   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
05503   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
05504   *        protected against un-initialized filter and polarity values.
05505   * @retval None
05506   */
05507 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05508                        uint32_t TIM_ICFilter)
05509 {
05510   uint32_t tmpccmr2 = 0;
05511   uint32_t tmpccer = 0;
05512
05513   /* Disable the Channel 4: Reset the CC4E Bit */
05514   TIMx->CCER &= ~TIM_CCER_CC4E;
05515   tmpccmr2 = TIMx->CCMR2;
05516   tmpccer = TIMx->CCER;
05517
05518   /* Select the Input */
05519   tmpccmr2 &= ~TIM_CCMR2_CC4S;
05520   tmpccmr2 |= (TIM_ICSelection << 8);
05521
05522   /* Set the filter */
05523   tmpccmr2 &= ~TIM_CCMR2_IC4F;
05524   tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
05525
05526   /* Select the Polarity and set the CC4E Bit */
05527   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
05528   tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
05529
05530   /* Write to TIMx CCMR2 and CCER registers */
05531   TIMx->CCMR2 = tmpccmr2;
05532   TIMx->CCER = tmpccer ;
05533 }
05534
05535 /**
05536   * @brief  Selects the Input Trigger source
05537   * @param  TIMx to select the TIM peripheral
05538   * @param  InputTriggerSource: The Input Trigger source.
05539   *          This parameter can be one of the following values:
05540   *            @arg TIM_TS_ITR0: Internal Trigger 0
05541   *            @arg TIM_TS_ITR1: Internal Trigger 1
05542   *            @arg TIM_TS_ITR2: Internal Trigger 2
05543   *            @arg TIM_TS_ITR3: Internal Trigger 3
05544   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
05545   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
05546   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
05547   *            @arg TIM_TS_ETRF: External Trigger input
05548   * @retval None
05549   */
05550 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
05551 {
05552   uint32_t tmpsmcr = 0;
05553
05554    /* Get the TIMx SMCR register value */
05555    tmpsmcr = TIMx->SMCR;
05556    /* Reset the TS Bits */
05557    tmpsmcr &= ~TIM_SMCR_TS;
05558    /* Set the Input Trigger source and the slave mode*/
05559    tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
05560    /* Write to TIMx SMCR */
05561    TIMx->SMCR = tmpsmcr;
05562 }
05563 /**
05564   * @brief  Configures the TIMx External Trigger (ETR).
05565   * @param  TIMx to select the TIM peripheral
05566   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
05567   *          This parameter can be one of the following values:
05568   *            @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
05569   *            @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
05570   *            @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
05571   *            @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
05572   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
05573   *          This parameter can be one of the following values:
05574   *            @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
05575   *            @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
05576   * @param  ExtTRGFilter: External Trigger Filter.
05577   *          This parameter must be a value between 0x00 and 0x0F
05578   * @retval None
05579   */
05580 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
05581                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
05582 {
05583   uint32_t tmpsmcr = 0;
05584
05585   tmpsmcr = TIMx->SMCR;
05586
05587   /* Reset the ETR Bits */
05588   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
05589
05590   /* Set the Prescaler, the Filter value and the Polarity */
05591   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
05592
05593   /* Write to TIMx SMCR */
05594   TIMx->SMCR = tmpsmcr;
05595 }
05596
05597 /**
05598   * @brief  Enables or disables the TIM Capture Compare Channel x.
05599   * @param  TIMx to select the TIM peripheral
05600   * @param  Channel: specifies the TIM Channel
05601   *          This parameter can be one of the following values:
05602   *            @arg TIM_CHANNEL_1: TIM Channel 1
05603   *            @arg TIM_CHANNEL_2: TIM Channel 2
05604   *            @arg TIM_CHANNEL_3: TIM Channel 3
05605   *            @arg TIM_CHANNEL_4: TIM Channel 4
05606   * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
05607   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
05608   * @retval None
05609   */
05610 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
05611 {
05612   uint32_t tmp = 0;
05613
05614   /* Check the parameters */
05615   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
05616   assert_param(IS_TIM_CHANNELS(Channel));
05617
05618   tmp = TIM_CCER_CC1E << Channel;
05619
05620   /* Reset the CCxE Bit */
05621   TIMx->CCER &= ~tmp;
05622
05623   /* Set or reset the CCxE Bit */
05624   TIMx->CCER |=  (uint32_t)(ChannelState << Channel);
05625 }
05626
05627
05628 /**
05629   * @}
05630   */
05631
05632 #endif /* HAL_TIM_MODULE_ENABLED */
05633 /**
05634   * @}
05635   */
05636
05637 /**
05638   * @}
05639   */
05640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tim.h Source File

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stm32l4xx_hal_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of TIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_TIM_H
00040 #define __STM32L4xx_HAL_TIM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TIM
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIM_Exported_Types TIM Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  TIM Time base Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00068                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00069
00070   uint32_t CounterMode;       /*!< Specifies the counter mode.
00071                                    This parameter can be a value of @ref TIM_Counter_Mode */
00072
00073   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00074                                    Auto-Reload Register at the next update event.
00075                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
00076
00077   uint32_t ClockDivision;     /*!< Specifies the clock division.
00078                                    This parameter can be a value of @ref TIM_ClockDivision */
00079
00080   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00081                                     reaches zero, an update event is generated and counting restarts
00082                                     from the RCR value (N).
00083                                     This means in PWM mode that (N+1) corresponds to:
00084                                         - the number of PWM periods in edge-aligned mode
00085                                         - the number of half PWM period in center-aligned mode
00086                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00087                                      @note This parameter is valid only for TIM1 and TIM8. */
00088 } TIM_Base_InitTypeDef;
00089
00090 /**
00091   * @brief  TIM Output Compare Configuration Structure definition
00092   */
00093 typedef struct
00094 {
00095   uint32_t OCMode;        /*!< Specifies the TIM mode.
00096                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00097
00098   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00099                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00100
00101   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00102                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00103
00104   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00105                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00106                                @note This parameter is valid only for TIM1 and TIM8. */
00107
00108   uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
00109                                This parameter can be a value of @ref TIM_Output_Fast_State
00110                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00111
00112
00113   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00114                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00115                                @note This parameter is valid only for TIM1 and TIM8. */
00116
00117   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00118                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00119                                @note This parameter is valid only for TIM1 and TIM8. */
00120 } TIM_OC_InitTypeDef;
00121
00122 /**
00123   * @brief  TIM One Pulse Mode Configuration Structure definition
00124   */
00125 typedef struct
00126 {
00127   uint32_t OCMode;        /*!< Specifies the TIM mode.
00128                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00129
00130   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00131                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00132
00133   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00134                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00135
00136   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00137                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00138                                @note This parameter is valid only for TIM1 and TIM8. */
00139
00140   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00141                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00142                                @note This parameter is valid only for TIM1 and TIM8. */
00143
00144   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00145                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00146                                @note This parameter is valid only for TIM1 and TIM8. */
00147
00148   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00149                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00150
00151   uint32_t ICSelection;   /*!< Specifies the input.
00152                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00153
00154   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00155                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00156 } TIM_OnePulse_InitTypeDef;
00157
00158
00159 /**
00160   * @brief  TIM Input Capture Configuration Structure definition
00161   */
00162 typedef struct
00163 {
00164   uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
00165                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00166
00167   uint32_t ICSelection;  /*!< Specifies the input.
00168                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00169
00170   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00171                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00172
00173   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00174                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00175 } TIM_IC_InitTypeDef;
00176
00177 /**
00178   * @brief  TIM Encoder Configuration Structure definition
00179   */
00180 typedef struct
00181 {
00182   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00183                                This parameter can be a value of @ref TIM_Encoder_Mode */
00184
00185   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00186                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00187
00188   uint32_t IC1Selection;  /*!< Specifies the input.
00189                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00190
00191   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00192                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00193
00194   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00195                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00196
00197   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00198                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00199
00200   uint32_t IC2Selection;  /*!< Specifies the input.
00201                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00202
00203   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00204                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00205
00206   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00207                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00208 } TIM_Encoder_InitTypeDef;
00209
00210
00211 /**
00212   * @brief  Clock Configuration Handle Structure definition
00213   */
00214 typedef struct
00215 {
00216   uint32_t ClockSource;     /*!< TIM clock sources
00217                                  This parameter can be a value of @ref TIM_Clock_Source */
00218   uint32_t ClockPolarity;   /*!< TIM clock polarity
00219                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00220   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
00221                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00222   uint32_t ClockFilter;    /*!< TIM clock filter
00223                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00224 }TIM_ClockConfigTypeDef;
00225
00226 /**
00227   * @brief  Clear Input Configuration Handle Structure definition
00228   */
00229 typedef struct
00230 {
00231   uint32_t ClearInputState;      /*!< TIM clear Input state
00232                                       This parameter can be ENABLE or DISABLE */
00233   uint32_t ClearInputSource;     /*!< TIM clear Input sources
00234                                       This parameter can be a value of @ref TIM_ClearInput_Source */
00235   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
00236                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00237   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
00238                                       This parameter can be a value of @ref TIM_ClearInput_Prescaler */
00239   uint32_t ClearInputFilter;    /*!< TIM Clear Input filter
00240                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00241 }TIM_ClearInputConfigTypeDef;
00242
00243 /**
00244   * @brief  TIM Master configuration Structure definition
00245   * @note   Advanced timers provide TRGO2 internal line which is redirected
00246   *         to the ADC
00247   */
00248 typedef struct {
00249   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
00250                                       This parameter can be a value of @ref TIM_Master_Mode_Selection */
00251   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
00252                                       This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
00253   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
00254                                       This parameter can be a value of @ref TIM_Master_Slave_Mode */
00255 }TIM_MasterConfigTypeDef;
00256
00257 /**
00258   * @brief  TIM Slave configuration Structure definition
00259   */
00260 typedef struct {
00261   uint32_t  SlaveMode;      /*!< Slave mode selection
00262                                This parameter can be a value of @ref TIM_Slave_Mode */
00263   uint32_t  InputTrigger;      /*!< Input Trigger source
00264                                   This parameter can be a value of @ref TIM_Trigger_Selection */
00265   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00266                                   This parameter can be a value of @ref TIM_Trigger_Polarity */
00267   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00268                                   This parameter can be a value of @ref TIM_Trigger_Prescaler */
00269   uint32_t  TriggerFilter;     /*!< Input trigger filter
00270                                   This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
00271
00272 }TIM_SlaveConfigTypeDef;
00273
00274 /**
00275   * @brief  TIM Break input(s) and Dead time configuration Structure definition
00276   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
00277   *        filter and polarity.
00278   */
00279 typedef struct
00280 {
00281   uint32_t OffStateRunMode;           /*!< TIM off state in run mode
00282                                          This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00283   uint32_t OffStateIDLEMode;          /*!< TIM off state in IDLE mode
00284                                          This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00285   uint32_t LockLevel;                 /*!< TIM Lock level
00286                                          This parameter can be a value of @ref TIM_Lock_level */
00287   uint32_t DeadTime;                  /*!< TIM dead Time
00288                                          This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00289   uint32_t BreakState;                /*!< TIM Break State
00290                                          This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00291   uint32_t BreakPolarity;             /*!< TIM Break input polarity
00292                                          This parameter can be a value of @ref TIM_Break_Polarity */
00293   uint32_t BreakFilter;               /*!< Specifies the break input filter.
00294                                          This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00295   uint32_t Break2State;               /*!< TIM Break2 State
00296                                          This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
00297   uint32_t Break2Polarity;            /*!< TIM Break2 input polarity
00298                                          This parameter can be a value of @ref TIM_Break2_Polarity */
00299   uint32_t Break2Filter;              /*!< TIM break2 input filter.
00300                                          This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00301   uint32_t AutomaticOutput;           /*!< TIM Automatic Output Enable state
00302                                          This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00303 } TIM_BreakDeadTimeConfigTypeDef;
00304
00305 /**
00306   * @brief  HAL State structures definition
00307   */
00308 typedef enum
00309 {
00310   HAL_TIM_STATE_RESET             = 0x00,    /*!< Peripheral not yet initialized or disabled  */
00311   HAL_TIM_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
00312   HAL_TIM_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing              */
00313   HAL_TIM_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
00314   HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
00315 }HAL_TIM_StateTypeDef;
00316
00317 /**
00318   * @brief  HAL Active channel structures definition
00319   */
00320 typedef enum
00321 {
00322   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01,    /*!< The active channel is 1     */
00323   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02,    /*!< The active channel is 2     */
00324   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04,    /*!< The active channel is 3     */
00325   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08,    /*!< The active channel is 4     */
00326   HAL_TIM_ACTIVE_CHANNEL_5        = 0x10,    /*!< The active channel is 5     */
00327   HAL_TIM_ACTIVE_CHANNEL_6        = 0x20,    /*!< The active channel is 6     */
00328   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00    /*!< All active channels cleared */
00329 }HAL_TIM_ActiveChannel;
00330
00331 /**
00332   * @brief  TIM Time Base Handle Structure definition
00333   */
00334 typedef struct
00335 {
00336   TIM_TypeDef              *Instance;     /*!< Register base address             */
00337   TIM_Base_InitTypeDef     Init;          /*!< TIM Time Base required parameters */
00338   HAL_TIM_ActiveChannel    Channel;       /*!< Active channel                    */
00339   DMA_HandleTypeDef        *hdma[7];      /*!< DMA Handlers array
00340                                              This array is accessed by a @ref DMA_Handle_index */
00341   HAL_LockTypeDef          Lock;          /*!< Locking object                    */
00342   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
00343 }TIM_HandleTypeDef;
00344
00345 /**
00346   * @}
00347   */
00348 /* End of exported types -----------------------------------------------------*/
00349
00350 /* Exported constants --------------------------------------------------------*/
00351 /** @defgroup TIM_Exported_Constants TIM Exported Constants
00352   * @{
00353   */
00354
00355 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
00356   * @{
00357   */
00358 #define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001)
00359 #define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002)
00360 #define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000)
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
00366   * @{
00367   */
00368 #define TIM_DMABASE_CR1                    (0x00000000)
00369 #define TIM_DMABASE_CR2                    (0x00000001)
00370 #define TIM_DMABASE_SMCR                   (0x00000002)
00371 #define TIM_DMABASE_DIER                   (0x00000003)
00372 #define TIM_DMABASE_SR                     (0x00000004)
00373 #define TIM_DMABASE_EGR                    (0x00000005)
00374 #define TIM_DMABASE_CCMR1                  (0x00000006)
00375 #define TIM_DMABASE_CCMR2                  (0x00000007)
00376 #define TIM_DMABASE_CCER                   (0x00000008)
00377 #define TIM_DMABASE_CNT                    (0x00000009)
00378 #define TIM_DMABASE_PSC                    (0x0000000A)
00379 #define TIM_DMABASE_ARR                    (0x0000000B)
00380 #define TIM_DMABASE_RCR                    (0x0000000C)
00381 #define TIM_DMABASE_CCR1                   (0x0000000D)
00382 #define TIM_DMABASE_CCR2                   (0x0000000E)
00383 #define TIM_DMABASE_CCR3                   (0x0000000F)
00384 #define TIM_DMABASE_CCR4                   (0x00000010)
00385 #define TIM_DMABASE_BDTR                   (0x00000011)
00386 #define TIM_DMABASE_DCR                    (0x00000012)
00387 #define TIM_DMABASE_DMAR                   (0x00000013)
00388 #define TIM_DMABASE_OR1                    (0x00000014)
00389 #define TIM_DMABASE_CCMR3                  (0x00000015)
00390 #define TIM_DMABASE_CCR5                   (0x00000016)
00391 #define TIM_DMABASE_CCR6                   (0x00000017)
00392 #define TIM_DMABASE_OR2                    (0x00000018)
00393 #define TIM_DMABASE_OR3                    (0x00000019)
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup TIM_Event_Source TIM  Extended Event Source
00399   * @{
00400   */
00401 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
00402 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
00403 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
00404 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
00405 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
00406 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
00407 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
00408 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
00409 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
00410 /**
00411   * @}
00412   */
00413
00414 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
00415   * @{
00416   */
00417 #define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
00418 #define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
00419 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00420 /**
00421   * @}
00422   */
00423
00424 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
00425   * @{
00426   */
00427 #define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
00428 #define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
00434   * @{
00435   */
00436 #define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
00437 #define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
00438 #define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
00439 #define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
00440 /**
00441   * @}
00442   */
00443
00444 /** @defgroup TIM_Counter_Mode TIM Counter Mode
00445   * @{
00446   */
00447 #define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
00448 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
00449 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
00450 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
00451 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup TIM_ClockDivision TIM Clock Division
00457   * @{
00458   */
00459 #define TIM_CLOCKDIVISION_DIV1             ((uint32_t)0x0000)
00460 #define TIM_CLOCKDIVISION_DIV2             (TIM_CR1_CKD_0)
00461 #define TIM_CLOCKDIVISION_DIV4             (TIM_CR1_CKD_1)
00462 /**
00463   * @}
00464   */
00465
00466 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
00467   * @{
00468   */
00469 #define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
00470 #define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
00471 /**
00472   * @}
00473   */
00474
00475 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
00476   * @{
00477   */
00478 #define TIM_OCFAST_DISABLE                 ((uint32_t)0x0000)
00479 #define TIM_OCFAST_ENABLE                  (TIM_CCMR1_OC1FE)
00480 /**
00481   * @}
00482   */
00483
00484 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
00485   * @{
00486   */
00487 #define TIM_OUTPUTNSTATE_DISABLE           ((uint32_t)0x0000)
00488 #define TIM_OUTPUTNSTATE_ENABLE            (TIM_CCER_CC1NE)
00489 /**
00490   * @}
00491   */
00492
00493 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
00494   * @{
00495   */
00496 #define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
00497 #define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
00498 /**
00499   * @}
00500   */
00501
00502 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
00503   * @{
00504   */
00505 #define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000)
00506 #define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
00507 /**
00508   * @}
00509   */
00510
00511 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
00512   * @{
00513   */
00514 #define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
00515 #define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
00516 /**
00517   * @}
00518   */
00519
00520 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
00521   * @{
00522   */
00523 #define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
00524 #define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000)
00525 /**
00526   * @}
00527   */
00528
00529 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
00530   * @{
00531   */
00532 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
00533 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
00534 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
00535 /**
00536   * @}
00537   */
00538
00539 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
00540   * @{
00541   */
00542 #define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00543                                                                                connected to IC1, IC2, IC3 or IC4, respectively */
00544 #define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00545                                                                                connected to IC2, IC1, IC4 or IC3, respectively */
00546 #define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
00547 /**
00548   * @}
00549   */
00550
00551 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
00552   * @{
00553   */
00554 #define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)                 /*!< Capture performed each time an edge is detected on the capture input */
00555 #define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
00556 #define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
00557 #define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
00558 /**
00559   * @}
00560   */
00561
00562 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00563   * @{
00564   */
00565 #define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
00566 #define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
00567 /**
00568   * @}
00569   */
00570
00571 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00572   * @{
00573   */
00574 #define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
00575 #define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
00576 #define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
00577 /**
00578   * @}
00579   */
00580
00581 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
00582   * @{
00583   */
00584 #define TIM_IT_UPDATE                      (TIM_DIER_UIE)
00585 #define TIM_IT_CC1                         (TIM_DIER_CC1IE)
00586 #define TIM_IT_CC2                         (TIM_DIER_CC2IE)
00587 #define TIM_IT_CC3                         (TIM_DIER_CC3IE)
00588 #define TIM_IT_CC4                         (TIM_DIER_CC4IE)
00589 #define TIM_IT_COM                         (TIM_DIER_COMIE)
00590 #define TIM_IT_TRIGGER                     (TIM_DIER_TIE)
00591 #define TIM_IT_BREAK                       (TIM_DIER_BIE)
00592 /**
00593   * @}
00594   */
00595
00596 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
00597   * @{
00598   */
00599 #define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
00600 #define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000)
00601 /**
00602   * @}
00603   */
00604
00605 /** @defgroup TIM_DMA_sources TIM DMA Sources
00606   * @{
00607   */
00608 #define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
00609 #define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
00610 #define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
00611 #define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
00612 #define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
00613 #define TIM_DMA_COM                        (TIM_DIER_COMDE)
00614 #define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup TIM_Flag_definition TIM Flag Definition
00620   * @{
00621   */
00622 #define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
00623 #define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
00624 #define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
00625 #define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
00626 #define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
00627 #define TIM_FLAG_CC5                       (TIM_SR_CC5IF)
00628 #define TIM_FLAG_CC6                       (TIM_SR_CC6IF)
00629 #define TIM_FLAG_COM                       (TIM_SR_COMIF)
00630 #define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
00631 #define TIM_FLAG_BREAK                     (TIM_SR_BIF)
00632 #define TIM_FLAG_BREAK2                    (TIM_SR_B2IF)
00633 #define TIM_FLAG_SYSTEM_BREAK              (TIM_SR_SBIF)
00634 #define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
00635 #define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
00636 #define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
00637 #define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
00638 /**
00639   * @}
00640   */
00641
00642 /** @defgroup TIM_Channel TIM Channel
00643   * @{
00644   */
00645 #define TIM_CHANNEL_1                      ((uint32_t)0x0000)
00646 #define TIM_CHANNEL_2                      ((uint32_t)0x0004)
00647 #define TIM_CHANNEL_3                      ((uint32_t)0x0008)
00648 #define TIM_CHANNEL_4                      ((uint32_t)0x000C)
00649 #define TIM_CHANNEL_5                      ((uint32_t)0x0010)
00650 #define TIM_CHANNEL_6                      ((uint32_t)0x0014)
00651 #define TIM_CHANNEL_ALL                    ((uint32_t)0x003C)
00652 /**
00653   * @}
00654   */
00655
00656 /** @defgroup TIM_Clock_Source TIM Clock Source
00657   * @{
00658   */
00659 #define TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
00660 #define TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
00661 #define TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
00662 #define TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
00663 #define TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
00664 #define TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
00665 #define TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
00666 #define TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
00667 #define TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
00668 #define TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
00669 /**
00670   * @}
00671   */
00672
00673 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
00674   * @{
00675   */
00676 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
00677 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
00678 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
00679 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00680 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00681 /**
00682   * @}
00683   */
00684
00685 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
00686   * @{
00687   */
00688 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00689 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00690 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00691 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00692 /**
00693   * @}
00694   */
00695
00696 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
00697   * @{
00698   */
00699 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
00700 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                          /*!< Polarity for ETRx pin */
00701 /**
00702   * @}
00703   */
00704
00705 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00706   * @{
00707   */
00708 #define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
00709 #define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00710 #define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00711 #define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00712 /**
00713   * @}
00714   */
00715
00716 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
00717   * @{
00718   */
00719 #define TIM_OSSR_ENABLE                          (TIM_BDTR_OSSR)
00720 #define TIM_OSSR_DISABLE                   ((uint32_t)0x0000)
00721 /**
00722   * @}
00723   */
00724
00725 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
00726   * @{
00727   */
00728 #define TIM_OSSI_ENABLE                          (TIM_BDTR_OSSI)
00729 #define TIM_OSSI_DISABLE                   ((uint32_t)0x0000)
00730 /**
00731   * @}
00732   */
00733 /** @defgroup TIM_Lock_level  TIM Lock level
00734   * @{
00735   */
00736 #define TIM_LOCKLEVEL_OFF                        ((uint32_t)0x0000)
00737 #define TIM_LOCKLEVEL_1                    (TIM_BDTR_LOCK_0)
00738 #define TIM_LOCKLEVEL_2                    (TIM_BDTR_LOCK_1)
00739 #define TIM_LOCKLEVEL_3                    (TIM_BDTR_LOCK)
00740 /**
00741   * @}
00742   */
00743
00744 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
00745   * @{
00746   */
00747 #define TIM_BREAK_ENABLE                   (TIM_BDTR_BKE)
00748 #define TIM_BREAK_DISABLE                  ((uint32_t)0x0000)
00749 /**
00750   * @}
00751   */
00752
00753 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
00754   * @{
00755   */
00756 #define TIM_BREAKPOLARITY_LOW              ((uint32_t)0x0000)
00757 #define TIM_BREAKPOLARITY_HIGH             (TIM_BDTR_BKP)
00758 /**
00759   * @}
00760   */
00761
00762 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
00763   * @{
00764   */
00765 #define TIM_BREAK2_DISABLE                 ((uint32_t)0x00000000)
00766 #define TIM_BREAK2_ENABLE                  ((uint32_t)TIM_BDTR_BK2E)
00767 /**
00768   * @}
00769   */
00770
00771 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
00772   * @{
00773   */
00774 #define TIM_BREAK2POLARITY_LOW             ((uint32_t)0x00000000)
00775 #define TIM_BREAK2POLARITY_HIGH            ((uint32_t)TIM_BDTR_BK2P)
00776 /**
00777   * @}
00778   */
00779
00780 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
00781   * @{
00782   */
00783 #define TIM_AUTOMATICOUTPUT_ENABLE         (TIM_BDTR_AOE)
00784 #define TIM_AUTOMATICOUTPUT_DISABLE        ((uint32_t)0x0000)
00785 /**
00786   * @}
00787   */
00788
00789 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
00790   * @{
00791   */
00792 #define TIM_GROUPCH5_NONE       (uint32_t)0x00000000  /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00793 #define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
00794 #define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
00795 #define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)      /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
00796 /**
00797   * @}
00798   */
00799
00800 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
00801   * @{
00802   */
00803 #define TIM_TRGO_RESET            ((uint32_t)0x0000)
00804 #define TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
00805 #define TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
00806 #define TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00807 #define TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
00808 #define TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
00809 #define TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
00810 #define TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00811 /**
00812   * @}
00813   */
00814
00815 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
00816   * @{
00817   */
00818 #define TIM_TRGO2_RESET                          ((uint32_t)0x00000000)
00819 #define TIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))
00820 #define TIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))
00821 #define TIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00822 #define TIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))
00823 #define TIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
00824 #define TIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
00825 #define TIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00826 #define TIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))
00827 #define TIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
00828 #define TIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
00829 #define TIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00830 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
00831 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
00832 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
00833 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
00834 /**
00835   * @}
00836   */
00837
00838 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
00839   * @{
00840   */
00841 #define TIM_MASTERSLAVEMODE_ENABLE         ((uint32_t)0x0080)
00842 #define TIM_MASTERSLAVEMODE_DISABLE        ((uint32_t)0x0000)
00843 /**
00844   * @}
00845   */
00846
00847 /** @defgroup TIM_Slave_Mode TIM Slave mode
00848   * @{
00849   */
00850 #define TIM_SLAVEMODE_DISABLE                ((uint32_t)0x0000)
00851 #define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))
00852 #define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
00853 #define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
00854 #define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
00855 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))
00856 /**
00857   * @}
00858   */
00859
00860 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
00861   * @{
00862   */
00863 #define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
00864 #define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)
00865 #define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)
00866 #define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
00867 #define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
00868 #define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
00869 #define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
00870 #define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)
00871
00872 #define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)
00873 #define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
00874 #define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
00875 #define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
00876 #define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
00877 #define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
00878 /**
00879   * @}
00880   */
00881
00882 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
00883   * @{
00884   */
00885 #define TIM_TS_ITR0                        ((uint32_t)0x0000)
00886 #define TIM_TS_ITR1                        ((uint32_t)0x0010)
00887 #define TIM_TS_ITR2                        ((uint32_t)0x0020)
00888 #define TIM_TS_ITR3                        ((uint32_t)0x0030)
00889 #define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
00890 #define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
00891 #define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
00892 #define TIM_TS_ETRF                        ((uint32_t)0x0070)
00893 #define TIM_TS_NONE                        ((uint32_t)0xFFFF)
00894 /**
00895   * @}
00896   */
00897
00898 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
00899   * @{
00900   */
00901 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
00902 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
00903 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00904 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00905 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00906 /**
00907   * @}
00908   */
00909
00910 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
00911   * @{
00912   */
00913 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00914 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
00915 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
00916 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
00917 /**
00918   * @}
00919   */
00920
00921 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
00922   * @{
00923   */
00924 #define TIM_TI1SELECTION_CH1               ((uint32_t)0x0000)
00925 #define TIM_TI1SELECTION_XORCOMBINATION    (TIM_CR2_TI1S)
00926 /**
00927   * @}
00928   */
00929
00930 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
00931   * @{
00932   */
00933 #define TIM_DMABURSTLENGTH_1TRANSFER       (0x00000000)
00934 #define TIM_DMABURSTLENGTH_2TRANSFERS      (0x00000100)
00935 #define TIM_DMABURSTLENGTH_3TRANSFERS      (0x00000200)
00936 #define TIM_DMABURSTLENGTH_4TRANSFERS      (0x00000300)
00937 #define TIM_DMABURSTLENGTH_5TRANSFERS      (0x00000400)
00938 #define TIM_DMABURSTLENGTH_6TRANSFERS      (0x00000500)
00939 #define TIM_DMABURSTLENGTH_7TRANSFERS      (0x00000600)
00940 #define TIM_DMABURSTLENGTH_8TRANSFERS      (0x00000700)
00941 #define TIM_DMABURSTLENGTH_9TRANSFERS      (0x00000800)
00942 #define TIM_DMABURSTLENGTH_10TRANSFERS     (0x00000900)
00943 #define TIM_DMABURSTLENGTH_11TRANSFERS     (0x00000A00)
00944 #define TIM_DMABURSTLENGTH_12TRANSFERS     (0x00000B00)
00945 #define TIM_DMABURSTLENGTH_13TRANSFERS     (0x00000C00)
00946 #define TIM_DMABURSTLENGTH_14TRANSFERS     (0x00000D00)
00947 #define TIM_DMABURSTLENGTH_15TRANSFERS     (0x00000E00)
00948 #define TIM_DMABURSTLENGTH_16TRANSFERS     (0x00000F00)
00949 #define TIM_DMABURSTLENGTH_17TRANSFERS     (0x00001000)
00950 #define TIM_DMABURSTLENGTH_18TRANSFERS     (0x00001100)
00951 /**
00952   * @}
00953   */
00954
00955 /** @defgroup DMA_Handle_index TIM DMA Handle Index
00956   * @{
00957   */
00958 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0)       /*!< Index of the DMA handle used for Update DMA requests */
00959 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
00960 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
00961 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
00962 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
00963 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5)       /*!< Index of the DMA handle used for Commutation DMA requests */
00964 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
00965 /**
00966   * @}
00967   */
00968
00969 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
00970   * @{
00971   */
00972 #define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
00973 #define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
00974 #define TIM_CCxN_ENABLE                  ((uint32_t)0x0004)
00975 #define TIM_CCxN_DISABLE                 ((uint32_t)0x0000)
00976 /**
00977   * @}
00978   */
00979
00980 /** @defgroup TIM_Break_System TIM Break System
00981   * @{
00982   */
00983 #define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
00984 #define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
00985 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR  SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */
00986 #define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */
00987 /**
00988   * @}
00989   */
00990
00991 /**
00992   * @}
00993   */
00994 /* End of exported constants -------------------------------------------------*/
00995
00996 /* Exported macros -----------------------------------------------------------*/
00997 /** @defgroup TIM_Exported_Macros TIM Exported Macros
00998   * @{
00999   */
01000
01001 /** @brief  Reset TIM handle state.
01002   * @param  __HANDLE__: TIM handle.
01003   * @retval None
01004   */
01005 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
01006
01007 /**
01008   * @brief  Enable the TIM peripheral.
01009   * @param  __HANDLE__: TIM handle
01010   * @retval None
01011  */
01012 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
01013
01014 /**
01015   * @brief  Enable the TIM main Output.
01016   * @param  __HANDLE__: TIM handle
01017   * @retval None
01018   */
01019 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
01020
01021 /**
01022   * @brief  Disable the TIM peripheral.
01023   * @param  __HANDLE__: TIM handle
01024   * @retval None
01025   */
01026 #define __HAL_TIM_DISABLE(__HANDLE__) \
01027                         do { \
01028                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
01029                             { \
01030                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
01031                             { \
01032                               (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
01033                             } \
01034                           } \
01035                         } while(0)
01036
01037 /**
01038   * @brief  Disable the TIM main Output.
01039   * @param  __HANDLE__: TIM handle
01040   * @retval None
01041   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
01042   */
01043 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
01044                         do { \
01045                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
01046                           { \
01047                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
01048                             { \
01049                               (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
01050                             } \
01051                             } \
01052                         } while(0)
01053
01054 /** @brief  Enable the specified TIM interrupt.
01055   * @param  __HANDLE__: specifies the TIM Handle.
01056   * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.
01057   *          This parameter can be one of the following values:
01058   *            @arg TIM_IT_UPDATE: Update interrupt
01059   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01060   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01061   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01062   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01063   *            @arg TIM_IT_COM:   Commutation interrupt
01064   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01065   *            @arg TIM_IT_BREAK: Break interrupt
01066   * @retval None
01067   */
01068 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
01069
01070
01071 /** @brief  Disable the specified TIM interrupt.
01072   * @param  __HANDLE__: specifies the TIM Handle.
01073   * @param  __INTERRUPT__: specifies the TIM interrupt source to disable.
01074   *          This parameter can be one of the following values:
01075   *            @arg TIM_IT_UPDATE: Update interrupt
01076   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01077   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01078   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01079   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01080   *            @arg TIM_IT_COM:   Commutation interrupt
01081   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01082   *            @arg TIM_IT_BREAK: Break interrupt
01083   * @retval None
01084   */
01085 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
01086
01087 /** @brief  Enable the specified DMA request.
01088   * @param  __HANDLE__: specifies the TIM Handle.
01089   * @param  __DMA__: specifies the TIM DMA request to enable.
01090   *          This parameter can be one of the following values:
01091   *            @arg TIM_DMA_UPDATE: Update DMA request
01092   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01093   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01094   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01095   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01096   *            @arg TIM_DMA_COM:   Commutation DMA request
01097   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01098   *            @arg TIM_DMA_BREAK: Break DMA request
01099   * @retval None
01100   */
01101 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
01102
01103 /** @brief  Disable the specified DMA request.
01104   * @param  __HANDLE__: specifies the TIM Handle.
01105   * @param  __DMA__: specifies the TIM DMA request to disable.
01106   *          This parameter can be one of the following values:
01107   *            @arg TIM_DMA_UPDATE: Update DMA request
01108   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01109   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01110   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01111   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01112   *            @arg TIM_DMA_COM:   Commutation DMA request
01113   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01114   *            @arg TIM_DMA_BREAK: Break DMA request
01115   * @retval None
01116   */
01117 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
01118
01119 /** @brief  Check whether the specified TIM interrupt flag is set or not.
01120   * @param  __HANDLE__: specifies the TIM Handle.
01121   * @param  __FLAG__: specifies the TIM interrupt flag to check.
01122   *        This parameter can be one of the following values:
01123   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01124   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01125   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01126   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01127   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01128   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01129   *            @arg TIM_FLAG_CC6: Compare 5 interrupt flag
01130   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01131   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01132   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01133   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01134   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01135   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01136   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01137   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01138   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01139   * @retval The new state of __FLAG__ (TRUE or FALSE).
01140   */
01141 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
01142
01143 /** @brief  Clear the specified TIM interrupt flag.
01144   * @param  __HANDLE__: specifies the TIM Handle.
01145   * @param  __FLAG__: specifies the TIM interrupt flag to clear.
01146   *        This parameter can be one of the following values:
01147   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01148   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01149   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01150   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01151   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01152   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01153   *            @arg TIM_FLAG_CC6: Compare 5 interrupt flag
01154   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01155   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01156   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01157   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01158   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01159   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01160   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01161   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01162   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01163   * @retval The new state of __FLAG__ (TRUE or FALSE).
01164   */
01165 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
01166
01167 /**
01168   * @brief  Check whether the specified TIM interrupt source is enabled or not.
01169   * @param  __HANDLE__: TIM handle
01170   * @param  __INTERRUPT__: specifies the TIM interrupt source to check.
01171   *          This parameter can be one of the following values:
01172   *            @arg TIM_IT_UPDATE: Update interrupt
01173   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01174   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01175   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01176   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01177   *            @arg TIM_IT_COM:   Commutation interrupt
01178   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01179   *            @arg TIM_IT_BREAK: Break interrupt
01180   * @retval The state of TIM_IT (SET or RESET).
01181   */
01182 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
01183
01184 /** @brief Clear the TIM interrupt pending bits.
01185   * @param  __HANDLE__: TIM handle
01186   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
01187   *          This parameter can be one of the following values:
01188   *            @arg TIM_IT_UPDATE: Update interrupt
01189   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01190   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01191   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01192   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01193   *            @arg TIM_IT_COM:   Commutation interrupt
01194   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01195   *            @arg TIM_IT_BREAK: Break interrupt
01196   * @retval None
01197   */
01198 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
01199
01200 /**
01201   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
01202   * @param  __HANDLE__: TIM handle.
01203   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
01204   * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
01205 mode.
01206   */
01207 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
01208
01209
01210 /**
01211   * @brief  Set the TIM Prescaler on runtime.
01212   * @param  __HANDLE__: TIM handle.
01213   * @param  __PRESC__: specifies the Prescaler new value.
01214   * @retval None
01215   */
01216 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
01217
01218 /**
01219   * @brief  Set the TIM Counter Register value on runtime.
01220   * @param  __HANDLE__: TIM handle.
01221   * @param  __COUNTER__: specifies the Counter register new value.
01222   * @retval None
01223   */
01224 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
01225
01226 /**
01227   * @brief  Get the TIM Counter Register value on runtime.
01228   * @param  __HANDLE__: TIM handle.
01229   * @retval None
01230   */
01231 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
01232    ((__HANDLE__)->Instance->CNT)
01233
01234 /**
01235   * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
01236   * @param  __HANDLE__: TIM handle.
01237   * @param  __AUTORELOAD__: specifies the Counter register new value.
01238   * @retval None
01239   */
01240 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
01241                         do{                                                    \
01242                               (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
01243                               (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
01244                           } while(0)
01245
01246 /**
01247   * @brief  Get the TIM Autoreload Register value on runtime.
01248   * @param  __HANDLE__: TIM handle.
01249   * @retval None
01250   */
01251 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
01252    ((__HANDLE__)->Instance->ARR)
01253
01254 /**
01255   * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
01256   * @param  __HANDLE__: TIM handle.
01257   * @param  __CKD__: specifies the clock division value.
01258   *          This parameter can be one of the following value:
01259   *            @arg TIM_CLOCKDIVISION_DIV1
01260   *            @arg TIM_CLOCKDIVISION_DIV2
01261   *            @arg TIM_CLOCKDIVISION_DIV4
01262   * @retval None
01263   */
01264 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
01265                         do{                                                    \
01266                               (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
01267                               (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
01268                               (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
01269                           } while(0)
01270
01271 /**
01272   * @brief  Get the TIM Clock Division value on runtime.
01273   * @param  __HANDLE__: TIM handle.
01274   * @retval None
01275   */
01276 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
01277    ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
01278
01279 /**
01280   * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
01281   * @param  __HANDLE__: TIM handle.
01282   * @param  __CHANNEL__: TIM Channels to be configured.
01283   *          This parameter can be one of the following values:
01284   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01285   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01286   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01287   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01288   * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
01289   *          This parameter can be one of the following values:
01290   *            @arg TIM_ICPSC_DIV1: no prescaler
01291   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01292   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01293   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01294   * @retval None
01295   */
01296 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01297                         do{                                                    \
01298                               TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01299                               TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01300                           } while(0)
01301
01302 /**
01303   * @brief  Get the TIM Input Capture prescaler on runtime.
01304   * @param  __HANDLE__: TIM handle.
01305   * @param  __CHANNEL__: TIM Channels to be configured.
01306   *          This parameter can be one of the following values:
01307   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01308   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01309   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01310   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01311   * @retval None
01312   */
01313 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01314   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01315    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
01316    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01317    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
01318
01319 /**
01320   * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
01321   * @param  __HANDLE__: TIM handle.
01322   * @param  __CHANNEL__: TIM Channels to be configured.
01323   *          This parameter can be one of the following values:
01324   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01325   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01326   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01327   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01328   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01329   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01330   * @param  __COMPARE__: specifies the Capture Compare register new value.
01331   * @retval None
01332   */
01333 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
01334 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
01335  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
01336  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
01337  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
01338  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
01339  ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
01340
01341 /**
01342   * @brief  Get the TIM Capture Compare Register value on runtime.
01343   * @param  __HANDLE__: TIM handle.
01344   * @param  __CHANNEL__: TIM Channel associated with the capture compare register
01345   *          This parameter can be one of the following values:
01346   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
01347   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
01348   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
01349   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
01350   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
01351   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
01352   * @retval None
01353   */
01354 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
01355 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
01356  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
01357  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
01358  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
01359  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
01360  ((__HANDLE__)->Instance->CCR6))
01361
01362 /**
01363   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
01364   * @param  __HANDLE__: TIM handle.
01365   * @note  When the USR bit of the TIMx_CR1 register is set, only counter
01366   *        overflow/underflow generates an update interrupt or DMA request (if
01367   *        enabled)
01368   * @retval None
01369   */
01370 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
01371     ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
01372
01373 /**
01374   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
01375   * @param  __HANDLE__: TIM handle.
01376   * @note  When the USR bit of the TIMx_CR1 register is reset, any of the
01377   *        following events generate an update interrupt or DMA request (if
01378   *        enabled):
01379   *           _ Counter overflow underflow
01380   *           _ Setting the UG bit
01381   *           _ Update generation through the slave mode controller
01382   * @retval None
01383   */
01384 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
01385       ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
01386
01387 /**
01388   * @brief  Set the TIM Capture x input polarity on runtime.
01389   * @param  __HANDLE__: TIM handle.
01390   * @param  __CHANNEL__: TIM Channels to be configured.
01391   *          This parameter can be one of the following values:
01392   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01393   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01394   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01395   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01396   * @param  __POLARITY__: Polarity for TIx source
01397   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01398   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01399   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01400   * @retval None
01401   */
01402 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
01403         do{                                                                     \
01404           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01405           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01406         }while(0)
01407
01408 /**
01409   * @}
01410   */
01411 /* End of exported macros ----------------------------------------------------*/
01412
01413 /* Private constants ---------------------------------------------------------*/
01414 /** @defgroup TIM_Private_Constants TIM Private Constants
01415   * @{
01416   */
01417 /* The counter of a timer instance is disabled only if all the CCx and CCxN
01418    channels have been disabled */
01419 #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
01420 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
01421 /**
01422   * @}
01423   */
01424 /* End of private constants --------------------------------------------------*/
01425
01426 /* Private macros ------------------------------------------------------------*/
01427 /** @defgroup TIM_Private_Macros TIM Private Macros
01428   * @{
01429   */
01430
01431 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
01432                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
01433                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
01434
01435 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
01436                                    ((__BASE__) == TIM_DMABASE_CR2)   || \
01437                                    ((__BASE__) == TIM_DMABASE_SMCR)  || \
01438                                    ((__BASE__) == TIM_DMABASE_DIER)  || \
01439                                    ((__BASE__) == TIM_DMABASE_SR)    || \
01440                                    ((__BASE__) == TIM_DMABASE_EGR)   || \
01441                                    ((__BASE__) == TIM_DMABASE_CCMR1) || \
01442                                    ((__BASE__) == TIM_DMABASE_CCMR2) || \
01443                                    ((__BASE__) == TIM_DMABASE_CCER)  || \
01444                                    ((__BASE__) == TIM_DMABASE_CNT)   || \
01445                                    ((__BASE__) == TIM_DMABASE_PSC)   || \
01446                                    ((__BASE__) == TIM_DMABASE_ARR)   || \
01447                                    ((__BASE__) == TIM_DMABASE_RCR)   || \
01448                                    ((__BASE__) == TIM_DMABASE_CCR1)  || \
01449                                    ((__BASE__) == TIM_DMABASE_CCR2)  || \
01450                                    ((__BASE__) == TIM_DMABASE_CCR3)  || \
01451                                    ((__BASE__) == TIM_DMABASE_CCR4)  || \
01452                                    ((__BASE__) == TIM_DMABASE_BDTR)  || \
01453                                    ((__BASE__) == TIM_DMABASE_CCMR3) || \
01454                                    ((__BASE__) == TIM_DMABASE_CCR5)  || \
01455                                    ((__BASE__) == TIM_DMABASE_CCR6)  || \
01456                                    ((__BASE__) == TIM_DMABASE_OR1)   || \
01457                                    ((__BASE__) == TIM_DMABASE_OR2)   || \
01458                                    ((__BASE__) == TIM_DMABASE_OR3))
01459
01460
01461 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
01462
01463
01464 #define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
01465                                             ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
01466                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
01467                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
01468                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
01469
01470 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
01471                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
01472                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
01473
01474 #define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
01475                                             ((__STATE__) == TIM_OCFAST_ENABLE))
01476
01477 #define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
01478                                             ((__POLARITY__) == TIM_OCPOLARITY_LOW))
01479
01480 #define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
01481                                             ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
01482
01483 #define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
01484                                             ((__STATE__) == TIM_OCIDLESTATE_RESET))
01485
01486 #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
01487                                             ((__STATE__) == TIM_OCNIDLESTATE_RESET))
01488
01489 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
01490                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
01491                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
01492
01493 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
01494                                             ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
01495                                             ((__SELECTION__) == TIM_ICSELECTION_TRC))
01496
01497 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
01498                                             ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
01499                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
01500                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
01501
01502 #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
01503                                             ((__MODE__) == TIM_OPMODE_REPETITIVE))
01504
01505 #define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
01506                                             ((__MODE__) == TIM_ENCODERMODE_TI2) || \
01507                                             ((__MODE__) == TIM_ENCODERMODE_TI12))
01508
01509 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
01510
01511 #define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
01512                                             ((__CHANNEL__) == TIM_CHANNEL_2) || \
01513                                             ((__CHANNEL__) == TIM_CHANNEL_3) || \
01514                                             ((__CHANNEL__) == TIM_CHANNEL_4) || \
01515                                             ((__CHANNEL__) == TIM_CHANNEL_5) || \
01516                                             ((__CHANNEL__) == TIM_CHANNEL_6) || \
01517                                             ((__CHANNEL__) == TIM_CHANNEL_ALL))
01518
01519 #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
01520                                             ((__CHANNEL__) == TIM_CHANNEL_2))
01521
01522 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
01523                                                     ((__CHANNEL__) == TIM_CHANNEL_2) || \
01524                                                     ((__CHANNEL__) == TIM_CHANNEL_3))
01525
01526 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
01527                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
01528                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
01529                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
01530                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
01531                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
01532                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
01533                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
01534                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
01535                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
01536
01537 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
01538                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
01539                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
01540                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
01541                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
01542
01543 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
01544                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
01545                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
01546                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
01547
01548 #define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0xF)
01549
01550 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
01551                                                   ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
01552
01553 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
01554                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
01555                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
01556                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
01557
01558 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
01559
01560
01561 #define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
01562                                             ((__STATE__) == TIM_OSSR_DISABLE))
01563
01564 #define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
01565                                             ((__STATE__) == TIM_OSSI_DISABLE))
01566
01567 #define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
01568                                             ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
01569                                             ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
01570                                             ((__LEVEL__) == TIM_LOCKLEVEL_3))
01571
01572 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
01573
01574
01575 #define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
01576                                             ((__STATE__) == TIM_BREAK_DISABLE))
01577
01578 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
01579                                              ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
01580
01581 #define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
01582                                             ((__STATE__) == TIM_BREAK2_DISABLE))
01583
01584 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
01585                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
01586
01587 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
01588                                                   ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
01589
01590 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))
01591
01592 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
01593                                         ((__SOURCE__) == TIM_TRGO_ENABLE) || \
01594                                         ((__SOURCE__) == TIM_TRGO_UPDATE) || \
01595                                         ((__SOURCE__) == TIM_TRGO_OC1)    || \
01596                                         ((__SOURCE__) == TIM_TRGO_OC1REF) || \
01597                                         ((__SOURCE__) == TIM_TRGO_OC2REF) || \
01598                                         ((__SOURCE__) == TIM_TRGO_OC3REF) || \
01599                                         ((__SOURCE__) == TIM_TRGO_OC4REF))
01600
01601 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
01602                                          ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
01603                                          ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
01604                                          ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
01605                                          ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
01606                                          ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
01607                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01608                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01609                                          ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
01610                                          ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
01611                                          ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
01612                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
01613                                          ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
01614                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
01615                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
01616                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
01617                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
01618
01619 #define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
01620                                           ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
01621
01622 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
01623                                      ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
01624                                      ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
01625                                      ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
01626                                      ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
01627                                      ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
01628
01629 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
01630                                          ((__MODE__) == TIM_OCMODE_PWM2)               || \
01631                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
01632                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
01633                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
01634                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
01635
01636 #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
01637                                    ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
01638                                    ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
01639                                    ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
01640                                    ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
01641                                    ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
01642                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
01643                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
01644
01645 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01646                                                  ((__SELECTION__) == TIM_TS_ITR1) || \
01647                                                  ((__SELECTION__) == TIM_TS_ITR2) || \
01648                                                  ((__SELECTION__) == TIM_TS_ITR3) || \
01649                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
01650                                                  ((__SELECTION__) == TIM_TS_TI1FP1) || \
01651                                                  ((__SELECTION__) == TIM_TS_TI2FP2) || \
01652                                                  ((__SELECTION__) == TIM_TS_ETRF))
01653
01654 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01655                                                                ((__SELECTION__) == TIM_TS_ITR1) || \
01656                                                                ((__SELECTION__) == TIM_TS_ITR2) || \
01657                                                                ((__SELECTION__) == TIM_TS_ITR3) || \
01658                                                                ((__SELECTION__) == TIM_TS_NONE))
01659
01660
01661 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
01662                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
01663                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
01664                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
01665                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
01666
01667 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
01668                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
01669                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
01670                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
01671
01672 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
01673
01674 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
01675                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
01676
01677 #define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
01678                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
01679                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
01680                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
01681                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
01682                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
01683                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
01684                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
01685                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
01686                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
01687                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
01688                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
01689                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
01690                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
01691                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
01692                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
01693                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
01694                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
01695
01696 #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xF)
01697
01698 #define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFF)
01699
01700 #define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                 || \
01701                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                 || \
01702                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)  || \
01703                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
01704
01705 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
01706 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
01707  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
01708  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
01709  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
01710
01711 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
01712 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
01713  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
01714  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
01715  ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
01716
01717 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
01718 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
01719  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
01720  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
01721  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))
01722
01723 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
01724 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
01725  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
01726  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
01727  ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
01728
01729 /**
01730   * @}
01731   */
01732 /* End of private macros -----------------------------------------------------*/
01733
01734 /* Include TIM HAL Extended module */
01735 #include "stm32l4xx_hal_tim_ex.h"
01736
01737 /* Exported functions --------------------------------------------------------*/
01738 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
01739   * @{
01740   */
01741
01742 /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
01743  *  @brief    Time Base functions
01744  * @{
01745  */
01746 /* Time Base functions ********************************************************/
01747 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
01748 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
01749 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
01750 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
01751 /* Blocking mode: Polling */
01752 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
01753 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
01754 /* Non-Blocking mode: Interrupt */
01755 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
01756 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
01757 /* Non-Blocking mode: DMA */
01758 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
01759 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
01760 /**
01761   * @}
01762   */
01763
01764 /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
01765  *  @brief    Time Output Compare functions
01766  * @{
01767  */
01768 /* Timer Output Compare functions *********************************************/
01769 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
01770 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
01771 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
01772 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
01773 /* Blocking mode: Polling */
01774 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01775 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01776 /* Non-Blocking mode: Interrupt */
01777 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01778 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01779 /* Non-Blocking mode: DMA */
01780 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01781 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01782 /**
01783   * @}
01784   */
01785
01786 /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
01787  *  @brief    Time PWM functions
01788  * @{
01789  */
01790 /* Timer PWM functions ********************************************************/
01791 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
01792 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
01793 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
01794 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
01795 /* Blocking mode: Polling */
01796 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01797 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01798 /* Non-Blocking mode: Interrupt */
01799 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01800 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01801 /* Non-Blocking mode: DMA */
01802 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01803 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01804 /**
01805   * @}
01806   */
01807
01808 /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
01809  *  @brief    Time Input Capture functions
01810  * @{
01811  */
01812 /* Timer Input Capture functions **********************************************/
01813 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
01814 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
01815 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
01816 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
01817 /* Blocking mode: Polling */
01818 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01819 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01820 /* Non-Blocking mode: Interrupt */
01821 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01822 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01823 /* Non-Blocking mode: DMA */
01824 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01825 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01826 /**
01827   * @}
01828   */
01829
01830 /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
01831  *  @brief    Time One Pulse functions
01832  * @{
01833  */
01834 /* Timer One Pulse functions **************************************************/
01835 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
01836 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
01837 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
01838 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
01839 /* Blocking mode: Polling */
01840 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01841 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01842 /* Non-Blocking mode: Interrupt */
01843 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01844 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01845 /**
01846   * @}
01847   */
01848
01849 /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
01850  *  @brief    Time Encoder functions
01851  * @{
01852  */
01853 /* Timer Encoder functions ****************************************************/
01854 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
01855 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
01856 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
01857 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
01858  /* Blocking mode: Polling */
01859 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01860 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01861 /* Non-Blocking mode: Interrupt */
01862 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01863 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01864 /* Non-Blocking mode: DMA */
01865 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
01866 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01867 /**
01868   * @}
01869   */
01870
01871 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
01872  *  @brief    IRQ handler management
01873   * @{
01874   */
01875 /* Interrupt Handler functions  ***********************************************/
01876 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
01877 /**
01878   * @}
01879   */
01880
01881 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
01882  *  @brief      Peripheral Control functions
01883   * @{
01884   */
01885 /* Control functions  *********************************************************/
01886 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01887 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01888 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
01889 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
01890 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
01891 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
01892 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
01893 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01894 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01895 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01896                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01897 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01898 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01899                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01900 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01901 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
01902 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
01903 /**
01904   * @}
01905   */
01906
01907 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
01908  *  @brief    TIM Callbacks functions
01909   * @{
01910   */
01911 /* Callback in non blocking modes (Interrupt and DMA) *************************/
01912 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
01913 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
01914 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
01915 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
01916 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
01917 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
01918 /**
01919   * @}
01920   */
01921
01922 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
01923  *  @brief   Peripheral State functions
01924  * @{
01925  */
01926 /* Peripheral State functions  ************************************************/
01927 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
01928 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
01929 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
01930 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
01931 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
01932 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
01933 /**
01934   * @}
01935   */
01936
01937 /**
01938   * @}
01939   */
01940 /* End of exported functions -------------------------------------------------*/
01941
01942 /* Private functions----------------------------------------------------------*/
01943 /** @defgroup TIM_Private_Functions TIM Private Functions
01944 * @{
01945 */
01946 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
01947 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
01948 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01949 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
01950                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
01951
01952 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
01953 void TIM_DMAError(DMA_HandleTypeDef *hdma);
01954 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
01955 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
01956 /**
01957 * @}
01958 */
01959 /* End of private functions --------------------------------------------------*/
01960
01961 /**
01962   * @}
01963   */
01964
01965 /**
01966   * @}
01967   */
01968
01969 #ifdef __cplusplus
01970 }
01971 #endif
01972
01973 #endif /* __STM32L4xx_HAL_TIM_H */
01974
01975 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tim_ex.c Source File

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stm32l4xx_hal_tim_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   TIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer Extended peripheral:
00010   *           + Time Hall Sensor Interface Initialization
00011   *           + Time Hall Sensor Interface Start
00012   *           + Time Complementary signal break and dead time configuration
00013   *           + Time Master and Slave synchronization configuration
00014   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
00015   *           + Time OCRef clear configuration
00016   *           + Timer remapping capabilities configuration
00017   @verbatim
00018   ==============================================================================
00019                       ##### TIMER Extended features #####
00020   ==============================================================================
00021   [..]
00022     The Timer Extended features include:
00023     (#) Complementary outputs with programmable dead-time for :
00024         (++) Output Compare
00025         (++) PWM generation (Edge and Center-aligned Mode)
00026         (++) One-pulse mode output
00027     (#) Synchronization circuit to control the timer with external signals and to
00028         interconnect several timers together.
00029     (#) Break input to put the timer output signals in reset state or in a known state.
00030     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00031         positioning purposes
00032
00033             ##### How to use this driver #####
00034   ==============================================================================
00035     [..]
00036      (#) Initialize the TIM low level resources by implementing the following functions
00037          depending on the selected feature:
00038            (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
00039
00040      (#) Initialize the TIM low level resources :
00041         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00042         (##) TIM pins configuration
00043             (+++) Enable the clock for the TIM GPIOs using the following function:
00044               __HAL_RCC_GPIOx_CLK_ENABLE();
00045             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00046
00047      (#) The external Clock can be configured, if needed (the default clock is the
00048          internal clock from the APBx), using the following function:
00049          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00050          any start function.
00051
00052      (#) Configure the TIM in the desired functioning mode using one of the
00053          initialization function of this driver:
00054           (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the
00055               Timer Hall Sensor Interface and the commutation event with the corresponding
00056               Interrupt and DMA request if needed (Note that One Timer is used to interface
00057              with the Hall sensor Interface and another Timer should be used to use
00058              the commutation event).
00059
00060      (#) Activate the TIM peripheral using one of the start functions:
00061            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
00062            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
00063            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
00064            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
00065
00066
00067   @endverbatim
00068   ******************************************************************************
00069   * @attention
00070   *
00071   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00072   *
00073   * Redistribution and use in source and binary forms, with or without modification,
00074   * are permitted provided that the following conditions are met:
00075   *   1. Redistributions of source code must retain the above copyright notice,
00076   *      this list of conditions and the following disclaimer.
00077   *   2. Redistributions in binary form must reproduce the above copyright notice,
00078   *      this list of conditions and the following disclaimer in the documentation
00079   *      and/or other materials provided with the distribution.
00080   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00081   *      may be used to endorse or promote products derived from this software
00082   *      without specific prior written permission.
00083   *
00084   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00085   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00086   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00087   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00088   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00089   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00090   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00091   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00092   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00093   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00094   *
00095   ******************************************************************************
00096 */
00097
00098 /* Includes ------------------------------------------------------------------*/
00099 #include "stm32l4xx_hal.h"
00100
00101 /** @addtogroup STM32L4xx_HAL_Driver
00102   * @{
00103   */
00104
00105 /** @defgroup TIMEx TIMEx
00106   * @brief TIM Extended HAL module driver
00107   * @{
00108   */
00109
00110 #ifdef HAL_TIM_MODULE_ENABLED
00111
00112 /* Private typedef -----------------------------------------------------------*/
00113 /* Private define ------------------------------------------------------------*/
00114 #define BDTR_BKF_SHIFT (16)
00115 #define BDTR_BK2F_SHIFT (20)
00116 #define TIMx_ETRSEL_MASK ((uint32_t)0x0001C000)
00117
00118 /* Private macro -------------------------------------------------------------*/
00119 /* Private variables ---------------------------------------------------------*/
00120 /* Private function prototypes -----------------------------------------------*/
00121 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
00122
00123 /* Private functions ---------------------------------------------------------*/
00124
00125 /* Exported functions --------------------------------------------------------*/
00126 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
00127   * @{
00128   */
00129
00130 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00131   * @brief    Timer Hall Sensor functions
00132   *
00133 @verbatim
00134   ==============================================================================
00135                       ##### Timer Hall Sensor functions #####
00136   ==============================================================================
00137   [..]
00138     This section provides functions allowing to:
00139     (+) Initialize and configure TIM HAL Sensor.
00140     (+) De-initialize TIM HAL Sensor.
00141     (+) Start the Hall Sensor Interface.
00142     (+) Stop the Hall Sensor Interface.
00143     (+) Start the Hall Sensor Interface and enable interrupts.
00144     (+) Stop the Hall Sensor Interface and disable interrupts.
00145     (+) Start the Hall Sensor Interface and enable DMA transfers.
00146     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00147
00148 @endverbatim
00149   * @{
00150   */
00151 /**
00152   * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
00153   * @param  htim: TIM Encoder Interface handle
00154   * @param  sConfig: TIM Hall Sensor configuration structure
00155   * @retval HAL status
00156   */
00157 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
00158 {
00159   TIM_OC_InitTypeDef OC_Config;
00160
00161   /* Check the TIM handle allocation */
00162   if(htim == NULL)
00163   {
00164     return HAL_ERROR;
00165   }
00166
00167   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00168   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00169   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00170   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00171   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00172   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00173
00174   if(htim->State == HAL_TIM_STATE_RESET)
00175   {
00176     /* Allocate lock resource and initialize it */
00177     htim->Lock = HAL_UNLOCKED;
00178
00179     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00180     HAL_TIMEx_HallSensor_MspInit(htim);
00181   }
00182
00183   /* Set the TIM state */
00184   htim->State = HAL_TIM_STATE_BUSY;
00185
00186   /* Configure the Time base in the Encoder Mode */
00187   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00188
00189   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00190   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00191
00192   /* Reset the IC1PSC Bits */
00193   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00194   /* Set the IC1PSC value */
00195   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00196
00197   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00198   htim->Instance->CR2 |= TIM_CR2_TI1S;
00199
00200   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00201   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00202   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00203
00204   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00205   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00206   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00207
00208   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00209   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00210   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00211   OC_Config.OCMode = TIM_OCMODE_PWM2;
00212   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00213   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00214   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00215   OC_Config.Pulse = sConfig->Commutation_Delay;
00216
00217   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00218
00219   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00220     register to 101 */
00221   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00222   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00223
00224   /* Initialize the TIM state*/
00225   htim->State= HAL_TIM_STATE_READY;
00226
00227   return HAL_OK;
00228 }
00229
00230 /**
00231   * @brief  DeInitialize the TIM Hall Sensor interface
00232   * @param  htim: TIM Hall Sensor handle
00233   * @retval HAL status
00234   */
00235 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00236 {
00237   /* Check the parameters */
00238   assert_param(IS_TIM_INSTANCE(htim->Instance));
00239
00240   htim->State = HAL_TIM_STATE_BUSY;
00241
00242   /* Disable the TIM Peripheral Clock */
00243   __HAL_TIM_DISABLE(htim);
00244
00245   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00246   HAL_TIMEx_HallSensor_MspDeInit(htim);
00247
00248   /* Change TIM state */
00249   htim->State = HAL_TIM_STATE_RESET;
00250
00251   /* Release Lock */
00252   __HAL_UNLOCK(htim);
00253
00254   return HAL_OK;
00255 }
00256
00257 /**
00258   * @brief  Initializes the TIM Hall Sensor MSP.
00259   * @param  htim: TIM handle
00260   * @retval None
00261   */
00262 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00263 {
00264   /* Prevent unused argument(s) compilation warning */
00265   UNUSED(htim);
00266
00267   /* NOTE : This function should not be modified, when the callback is needed,
00268             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00269    */
00270 }
00271
00272 /**
00273   * @brief  DeInitialize TIM Hall Sensor MSP.
00274   * @param  htim: TIM handle
00275   * @retval None
00276   */
00277 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00278 {
00279   /* Prevent unused argument(s) compilation warning */
00280   UNUSED(htim);
00281
00282   /* NOTE : This function should not be modified, when the callback is needed,
00283             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00284    */
00285 }
00286
00287 /**
00288   * @brief  Starts the TIM Hall Sensor Interface.
00289   * @param  htim : TIM Hall Sensor handle
00290   * @retval HAL status
00291   */
00292 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00293 {
00294   /* Check the parameters */
00295   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00296
00297   /* Enable the Input Capture channels 1
00298     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00299   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00300
00301   /* Enable the Peripheral */
00302   __HAL_TIM_ENABLE(htim);
00303
00304   /* Return function status */
00305   return HAL_OK;
00306 }
00307
00308 /**
00309   * @brief  Stops the TIM Hall sensor Interface.
00310   * @param  htim : TIM Hall Sensor handle
00311   * @retval HAL status
00312   */
00313 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00314 {
00315   /* Check the parameters */
00316   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00317
00318   /* Disable the Input Capture channels 1, 2 and 3
00319     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00320   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00321
00322   /* Disable the Peripheral */
00323   __HAL_TIM_DISABLE(htim);
00324
00325   /* Return function status */
00326   return HAL_OK;
00327 }
00328
00329 /**
00330   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00331   * @param  htim : TIM Hall Sensor handle
00332   * @retval HAL status
00333   */
00334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00335 {
00336   /* Check the parameters */
00337   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00338
00339   /* Enable the capture compare Interrupts 1 event */
00340   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00341
00342   /* Enable the Input Capture channels 1
00343     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00344   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00345
00346   /* Enable the Peripheral */
00347   __HAL_TIM_ENABLE(htim);
00348
00349   /* Return function status */
00350   return HAL_OK;
00351 }
00352
00353 /**
00354   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00355   * @param  htim : TIM handle
00356   * @retval HAL status
00357   */
00358 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00359 {
00360   /* Check the parameters */
00361   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00362
00363   /* Disable the Input Capture channels 1
00364     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00365   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00366
00367   /* Disable the capture compare Interrupts event */
00368   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00369
00370   /* Disable the Peripheral */
00371   __HAL_TIM_DISABLE(htim);
00372
00373   /* Return function status */
00374   return HAL_OK;
00375 }
00376
00377 /**
00378   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00379   * @param  htim : TIM Hall Sensor handle
00380   * @param  pData: The destination Buffer address.
00381   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
00382   * @retval HAL status
00383   */
00384 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00385 {
00386   /* Check the parameters */
00387   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00388
00389    if((htim->State == HAL_TIM_STATE_BUSY))
00390   {
00391      return HAL_BUSY;
00392   }
00393   else if((htim->State == HAL_TIM_STATE_READY))
00394   {
00395     if(((uint32_t)pData == 0 ) && (Length > 0))
00396     {
00397       return HAL_ERROR;
00398     }
00399     else
00400     {
00401       htim->State = HAL_TIM_STATE_BUSY;
00402     }
00403   }
00404   /* Enable the Input Capture channels 1
00405     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00406   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00407
00408   /* Set the DMA Input Capture 1 Callback */
00409   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
00410   /* Set the DMA error callback */
00411   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00412
00413   /* Enable the DMA channel for Capture 1*/
00414   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
00415
00416   /* Enable the capture compare 1 Interrupt */
00417   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00418
00419   /* Enable the Peripheral */
00420   __HAL_TIM_ENABLE(htim);
00421
00422   /* Return function status */
00423   return HAL_OK;
00424 }
00425
00426 /**
00427   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00428   * @param  htim : TIM handle
00429   * @retval HAL status
00430   */
00431 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00432 {
00433   /* Check the parameters */
00434   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00435
00436   /* Disable the Input Capture channels 1
00437     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00438   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00439
00440
00441   /* Disable the capture compare Interrupts 1 event */
00442   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00443
00444   /* Disable the Peripheral */
00445   __HAL_TIM_DISABLE(htim);
00446
00447   /* Return function status */
00448   return HAL_OK;
00449 }
00450
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00456   *  @brief   Timer Complementary Output Compare functions
00457   *
00458 @verbatim
00459   ==============================================================================
00460               ##### Timer Complementary Output Compare functions #####
00461   ==============================================================================
00462   [..]
00463     This section provides functions allowing to:
00464     (+) Start the Complementary Output Compare/PWM.
00465     (+) Stop the Complementary Output Compare/PWM.
00466     (+) Start the Complementary Output Compare/PWM and enable interrupts.
00467     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
00468     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
00469     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
00470
00471 @endverbatim
00472   * @{
00473   */
00474
00475 /**
00476   * @brief  Starts the TIM Output Compare signal generation on the complementary
00477   *         output.
00478   * @param  htim : TIM Output Compare handle
00479   * @param  Channel : TIM Channel to be enabled
00480   *          This parameter can be one of the following values:
00481   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00482   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00483   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00484   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00485   * @retval HAL status
00486   */
00487 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00488 {
00489   /* Check the parameters */
00490   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00491
00492   /* Enable the Capture compare channel N */
00493   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00494
00495   /* Enable the Main Ouput */
00496   __HAL_TIM_MOE_ENABLE(htim);
00497
00498   /* Enable the Peripheral */
00499   __HAL_TIM_ENABLE(htim);
00500
00501   /* Return function status */
00502   return HAL_OK;
00503 }
00504
00505 /**
00506   * @brief  Stops the TIM Output Compare signal generation on the complementary
00507   *         output.
00508   * @param  htim : TIM handle
00509   * @param  Channel : TIM Channel to be disabled
00510   *          This parameter can be one of the following values:
00511   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00512   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00513   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00514   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00515   * @retval HAL status
00516   */
00517 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00518 {
00519   /* Check the parameters */
00520   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00521
00522   /* Disable the Capture compare channel N */
00523   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00524
00525   /* Disable the Main Ouput */
00526   __HAL_TIM_MOE_DISABLE(htim);
00527
00528   /* Disable the Peripheral */
00529   __HAL_TIM_DISABLE(htim);
00530
00531   /* Return function status */
00532   return HAL_OK;
00533 }
00534
00535 /**
00536   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00537   *         on the complementary output.
00538   * @param  htim : TIM OC handle
00539   * @param  Channel : TIM Channel to be enabled
00540   *          This parameter can be one of the following values:
00541   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00542   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00543   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00544   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00545   * @retval HAL status
00546   */
00547 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00548 {
00549   /* Check the parameters */
00550   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00551
00552   switch (Channel)
00553   {
00554     case TIM_CHANNEL_1:
00555     {
00556       /* Enable the TIM Output Compare interrupt */
00557       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00558     }
00559     break;
00560
00561     case TIM_CHANNEL_2:
00562     {
00563       /* Enable the TIM Output Compare interrupt */
00564       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00565     }
00566     break;
00567
00568     case TIM_CHANNEL_3:
00569     {
00570       /* Enable the TIM Output Compare interrupt */
00571       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00572     }
00573     break;
00574
00575     case TIM_CHANNEL_4:
00576     {
00577       /* Enable the TIM Output Compare interrupt */
00578       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00579     }
00580     break;
00581
00582     default:
00583     break;
00584   }
00585
00586   /* Enable the TIM Break interrupt */
00587   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00588
00589   /* Enable the Capture compare channel N */
00590   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00591
00592   /* Enable the Main Ouput */
00593   __HAL_TIM_MOE_ENABLE(htim);
00594
00595   /* Enable the Peripheral */
00596   __HAL_TIM_ENABLE(htim);
00597
00598   /* Return function status */
00599   return HAL_OK;
00600 }
00601
00602 /**
00603   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00604   *         on the complementary output.
00605   * @param  htim : TIM Output Compare handle
00606   * @param  Channel : TIM Channel to be disabled
00607   *          This parameter can be one of the following values:
00608   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00609   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00610   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00611   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00612   * @retval HAL status
00613   */
00614 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00615 {
00616   uint32_t tmpccer = 0;
00617
00618   /* Check the parameters */
00619   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00620
00621   switch (Channel)
00622   {
00623     case TIM_CHANNEL_1:
00624     {
00625       /* Disable the TIM Output Compare interrupt */
00626       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00627     }
00628     break;
00629
00630     case TIM_CHANNEL_2:
00631     {
00632       /* Disable the TIM Output Compare interrupt */
00633       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00634     }
00635     break;
00636
00637     case TIM_CHANNEL_3:
00638     {
00639       /* Disable the TIM Output Compare interrupt */
00640       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00641     }
00642     break;
00643
00644     case TIM_CHANNEL_4:
00645     {
00646       /* Disable the TIM Output Compare interrupt */
00647       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00648     }
00649     break;
00650
00651     default:
00652     break;
00653   }
00654
00655   /* Disable the Capture compare channel N */
00656   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00657
00658   /* Disable the TIM Break interrupt (only if no more channel is active) */
00659   tmpccer = htim->Instance->CCER;
00660   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
00661   {
00662     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00663   }
00664
00665   /* Disable the Main Ouput */
00666   __HAL_TIM_MOE_DISABLE(htim);
00667
00668   /* Disable the Peripheral */
00669   __HAL_TIM_DISABLE(htim);
00670
00671   /* Return function status */
00672   return HAL_OK;
00673 }
00674
00675 /**
00676   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00677   *         on the complementary output.
00678   * @param  htim : TIM Output Compare handle
00679   * @param  Channel : TIM Channel to be enabled
00680   *          This parameter can be one of the following values:
00681   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00682   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00683   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00684   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00685   * @param  pData: The source Buffer address.
00686   * @param  Length: The length of data to be transferred from memory to TIM peripheral
00687   * @retval HAL status
00688   */
00689 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00690 {
00691   /* Check the parameters */
00692   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00693
00694   if((htim->State == HAL_TIM_STATE_BUSY))
00695   {
00696      return HAL_BUSY;
00697   }
00698   else if((htim->State == HAL_TIM_STATE_READY))
00699   {
00700     if(((uint32_t)pData == 0 ) && (Length > 0))
00701     {
00702       return HAL_ERROR;
00703     }
00704     else
00705     {
00706       htim->State = HAL_TIM_STATE_BUSY;
00707     }
00708   }
00709   switch (Channel)
00710   {
00711     case TIM_CHANNEL_1:
00712     {
00713       /* Set the DMA Period elapsed callback */
00714       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00715
00716       /* Set the DMA error callback */
00717       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00718
00719       /* Enable the DMA channel */
00720       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00721
00722       /* Enable the TIM Output Compare DMA request */
00723       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00724     }
00725     break;
00726
00727     case TIM_CHANNEL_2:
00728     {
00729       /* Set the DMA Period elapsed callback */
00730       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00731
00732       /* Set the DMA error callback */
00733       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00734
00735       /* Enable the DMA channel */
00736       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00737
00738       /* Enable the TIM Output Compare DMA request */
00739       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00740     }
00741     break;
00742
00743     case TIM_CHANNEL_3:
00744 {
00745       /* Set the DMA Period elapsed callback */
00746       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00747
00748       /* Set the DMA error callback */
00749       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00750
00751       /* Enable the DMA channel */
00752       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00753
00754       /* Enable the TIM Output Compare DMA request */
00755       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00756     }
00757     break;
00758
00759     case TIM_CHANNEL_4:
00760     {
00761      /* Set the DMA Period elapsed callback */
00762       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
00763
00764       /* Set the DMA error callback */
00765       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
00766
00767       /* Enable the DMA channel */
00768       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00769
00770       /* Enable the TIM Output Compare DMA request */
00771       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00772     }
00773     break;
00774
00775     default:
00776     break;
00777   }
00778
00779   /* Enable the Capture compare channel N */
00780   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00781
00782   /* Enable the Main Ouput */
00783   __HAL_TIM_MOE_ENABLE(htim);
00784
00785   /* Enable the Peripheral */
00786   __HAL_TIM_ENABLE(htim);
00787
00788   /* Return function status */
00789   return HAL_OK;
00790 }
00791
00792 /**
00793   * @brief  Stops the TIM Output Compare signal generation in DMA mode
00794   *         on the complementary output.
00795   * @param  htim : TIM Output Compare handle
00796   * @param  Channel : TIM Channel to be disabled
00797   *          This parameter can be one of the following values:
00798   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00799   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00800   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00801   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00802   * @retval HAL status
00803   */
00804 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00805 {
00806   /* Check the parameters */
00807   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00808
00809   switch (Channel)
00810   {
00811     case TIM_CHANNEL_1:
00812     {
00813       /* Disable the TIM Output Compare DMA request */
00814       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00815     }
00816     break;
00817
00818     case TIM_CHANNEL_2:
00819     {
00820       /* Disable the TIM Output Compare DMA request */
00821       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00822     }
00823     break;
00824
00825     case TIM_CHANNEL_3:
00826     {
00827       /* Disable the TIM Output Compare DMA request */
00828       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00829     }
00830     break;
00831
00832     case TIM_CHANNEL_4:
00833     {
00834       /* Disable the TIM Output Compare interrupt */
00835       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00836     }
00837     break;
00838
00839     default:
00840     break;
00841   }
00842
00843   /* Disable the Capture compare channel N */
00844   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00845
00846   /* Disable the Main Ouput */
00847   __HAL_TIM_MOE_DISABLE(htim);
00848
00849   /* Disable the Peripheral */
00850   __HAL_TIM_DISABLE(htim);
00851
00852   /* Change the htim state */
00853   htim->State = HAL_TIM_STATE_READY;
00854
00855   /* Return function status */
00856   return HAL_OK;
00857 }
00858
00859 /**
00860   * @}
00861   */
00862
00863 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00864   * @brief    Timer Complementary PWM functions
00865   *
00866 @verbatim
00867   ==============================================================================
00868                  ##### Timer Complementary PWM functions #####
00869   ==============================================================================
00870   [..]
00871     This section provides functions allowing to:
00872     (+) Start the Complementary PWM.
00873     (+) Stop the Complementary PWM.
00874     (+) Start the Complementary PWM and enable interrupts.
00875     (+) Stop the Complementary PWM and disable interrupts.
00876     (+) Start the Complementary PWM and enable DMA transfers.
00877     (+) Stop the Complementary PWM and disable DMA transfers.
00878     (+) Start the Complementary Input Capture measurement.
00879     (+) Stop the Complementary Input Capture.
00880     (+) Start the Complementary Input Capture and enable interrupts.
00881     (+) Stop the Complementary Input Capture and disable interrupts.
00882     (+) Start the Complementary Input Capture and enable DMA transfers.
00883     (+) Stop the Complementary Input Capture and disable DMA transfers.
00884     (+) Start the Complementary One Pulse generation.
00885     (+) Stop the Complementary One Pulse.
00886     (+) Start the Complementary One Pulse and enable interrupts.
00887     (+) Stop the Complementary One Pulse and disable interrupts.
00888
00889 @endverbatim
00890   * @{
00891   */
00892
00893 /**
00894   * @brief  Starts the PWM signal generation on the complementary output.
00895   * @param  htim : TIM handle
00896   * @param  Channel : TIM Channel to be enabled
00897   *          This parameter can be one of the following values:
00898   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00899   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00900   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00901   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00902   * @retval HAL status
00903   */
00904 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00905 {
00906   /* Check the parameters */
00907   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00908
00909   /* Enable the complementary PWM output  */
00910   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00911
00912   /* Enable the Main Ouput */
00913   __HAL_TIM_MOE_ENABLE(htim);
00914
00915   /* Enable the Peripheral */
00916   __HAL_TIM_ENABLE(htim);
00917
00918   /* Return function status */
00919   return HAL_OK;
00920 }
00921
00922 /**
00923   * @brief  Stops the PWM signal generation on the complementary output.
00924   * @param  htim : TIM handle
00925   * @param  Channel : TIM Channel to be disabled
00926   *          This parameter can be one of the following values:
00927   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00928   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00929   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00930   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00931   * @retval HAL status
00932   */
00933 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00934 {
00935   /* Check the parameters */
00936   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00937
00938   /* Disable the complementary PWM output  */
00939   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00940
00941   /* Disable the Main Ouput */
00942   __HAL_TIM_MOE_DISABLE(htim);
00943
00944   /* Disable the Peripheral */
00945   __HAL_TIM_DISABLE(htim);
00946
00947   /* Return function status */
00948   return HAL_OK;
00949 }
00950
00951 /**
00952   * @brief  Starts the PWM signal generation in interrupt mode on the
00953   *         complementary output.
00954   * @param  htim : TIM handle
00955   * @param  Channel : TIM Channel to be disabled
00956   *          This parameter can be one of the following values:
00957   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00958   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00959   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00960   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00961   * @retval HAL status
00962   */
00963 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00964 {
00965   /* Check the parameters */
00966   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00967
00968   switch (Channel)
00969   {
00970     case TIM_CHANNEL_1:
00971     {
00972       /* Enable the TIM Capture/Compare 1 interrupt */
00973       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00974     }
00975     break;
00976
00977     case TIM_CHANNEL_2:
00978     {
00979       /* Enable the TIM Capture/Compare 2 interrupt */
00980       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00981     }
00982     break;
00983
00984     case TIM_CHANNEL_3:
00985     {
00986       /* Enable the TIM Capture/Compare 3 interrupt */
00987       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00988     }
00989     break;
00990
00991     case TIM_CHANNEL_4:
00992     {
00993       /* Enable the TIM Capture/Compare 4 interrupt */
00994       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00995     }
00996     break;
00997
00998     default:
00999     break;
01000   }
01001
01002   /* Enable the TIM Break interrupt */
01003   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
01004
01005   /* Enable the complementary PWM output  */
01006   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01007
01008   /* Enable the Main Ouput */
01009   __HAL_TIM_MOE_ENABLE(htim);
01010
01011   /* Enable the Peripheral */
01012   __HAL_TIM_ENABLE(htim);
01013
01014   /* Return function status */
01015   return HAL_OK;
01016 }
01017
01018 /**
01019   * @brief  Stops the PWM signal generation in interrupt mode on the
01020   *         complementary output.
01021   * @param  htim : TIM handle
01022   * @param  Channel : TIM Channel to be disabled
01023   *          This parameter can be one of the following values:
01024   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01025   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01026   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01027   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01028   * @retval HAL status
01029   */
01030 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01031 {
01032   uint32_t tmpccer = 0;
01033
01034   /* Check the parameters */
01035   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01036
01037   switch (Channel)
01038   {
01039     case TIM_CHANNEL_1:
01040     {
01041       /* Disable the TIM Capture/Compare 1 interrupt */
01042       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01043     }
01044     break;
01045
01046     case TIM_CHANNEL_2:
01047     {
01048       /* Disable the TIM Capture/Compare 2 interrupt */
01049       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01050     }
01051     break;
01052
01053     case TIM_CHANNEL_3:
01054     {
01055       /* Disable the TIM Capture/Compare 3 interrupt */
01056       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01057     }
01058     break;
01059
01060     case TIM_CHANNEL_4:
01061     {
01062       /* Disable the TIM Capture/Compare 3 interrupt */
01063       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01064     }
01065     break;
01066
01067     default:
01068     break;
01069   }
01070
01071   /* Disable the complementary PWM output  */
01072   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01073
01074
01075   /* Disable the TIM Break interrupt (only if no more channel is active) */
01076   tmpccer = htim->Instance->CCER;
01077   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
01078   {
01079     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01080   }
01081
01082   /* Disable the Main Ouput */
01083   __HAL_TIM_MOE_DISABLE(htim);
01084
01085   /* Disable the Peripheral */
01086   __HAL_TIM_DISABLE(htim);
01087
01088   /* Return function status */
01089   return HAL_OK;
01090 }
01091
01092 /**
01093   * @brief  Starts the TIM PWM signal generation in DMA mode on the
01094   *         complementary output
01095   * @param  htim : TIM handle
01096   * @param  Channel : TIM Channel to be enabled
01097   *          This parameter can be one of the following values:
01098   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01099   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01100   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01101   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01102   * @param  pData: The source Buffer address.
01103   * @param  Length: The length of data to be transferred from memory to TIM peripheral
01104   * @retval HAL status
01105   */
01106 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01107 {
01108   /* Check the parameters */
01109   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01110
01111   if((htim->State == HAL_TIM_STATE_BUSY))
01112   {
01113      return HAL_BUSY;
01114   }
01115   else if((htim->State == HAL_TIM_STATE_READY))
01116   {
01117     if(((uint32_t)pData == 0 ) && (Length > 0))
01118     {
01119       return HAL_ERROR;
01120     }
01121     else
01122     {
01123       htim->State = HAL_TIM_STATE_BUSY;
01124     }
01125   }
01126   switch (Channel)
01127   {
01128     case TIM_CHANNEL_1:
01129     {
01130       /* Set the DMA Period elapsed callback */
01131       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01132
01133       /* Set the DMA error callback */
01134       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01135
01136       /* Enable the DMA channel */
01137       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01138
01139       /* Enable the TIM Capture/Compare 1 DMA request */
01140       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01141     }
01142     break;
01143
01144     case TIM_CHANNEL_2:
01145     {
01146       /* Set the DMA Period elapsed callback */
01147       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01148
01149       /* Set the DMA error callback */
01150       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01151
01152       /* Enable the DMA channel */
01153       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01154
01155       /* Enable the TIM Capture/Compare 2 DMA request */
01156       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01157     }
01158     break;
01159
01160     case TIM_CHANNEL_3:
01161     {
01162       /* Set the DMA Period elapsed callback */
01163       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01164
01165       /* Set the DMA error callback */
01166       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01167
01168       /* Enable the DMA channel */
01169       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01170
01171       /* Enable the TIM Capture/Compare 3 DMA request */
01172       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01173     }
01174     break;
01175
01176     case TIM_CHANNEL_4:
01177     {
01178      /* Set the DMA Period elapsed callback */
01179       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01180
01181       /* Set the DMA error callback */
01182       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01183
01184       /* Enable the DMA channel */
01185       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01186
01187       /* Enable the TIM Capture/Compare 4 DMA request */
01188       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01189     }
01190     break;
01191
01192     default:
01193     break;
01194   }
01195
01196   /* Enable the complementary PWM output  */
01197   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01198
01199   /* Enable the Main Ouput */
01200   __HAL_TIM_MOE_ENABLE(htim);
01201
01202   /* Enable the Peripheral */
01203   __HAL_TIM_ENABLE(htim);
01204
01205   /* Return function status */
01206   return HAL_OK;
01207 }
01208
01209 /**
01210   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01211   *         output
01212   * @param  htim : TIM handle
01213   * @param  Channel : TIM Channel to be disabled
01214   *          This parameter can be one of the following values:
01215   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01216   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01217   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01218   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01219   * @retval HAL status
01220   */
01221 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01222 {
01223   /* Check the parameters */
01224   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01225
01226   switch (Channel)
01227   {
01228     case TIM_CHANNEL_1:
01229     {
01230       /* Disable the TIM Capture/Compare 1 DMA request */
01231       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01232     }
01233     break;
01234
01235     case TIM_CHANNEL_2:
01236     {
01237       /* Disable the TIM Capture/Compare 2 DMA request */
01238       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01239     }
01240     break;
01241
01242     case TIM_CHANNEL_3:
01243     {
01244       /* Disable the TIM Capture/Compare 3 DMA request */
01245       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01246     }
01247     break;
01248
01249     case TIM_CHANNEL_4:
01250     {
01251       /* Disable the TIM Capture/Compare 4 DMA request */
01252       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01253     }
01254     break;
01255
01256     default:
01257     break;
01258   }
01259
01260   /* Disable the complementary PWM output */
01261   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01262
01263   /* Disable the Main Ouput */
01264   __HAL_TIM_MOE_DISABLE(htim);
01265
01266   /* Disable the Peripheral */
01267   __HAL_TIM_DISABLE(htim);
01268
01269   /* Change the htim state */
01270   htim->State = HAL_TIM_STATE_READY;
01271
01272   /* Return function status */
01273   return HAL_OK;
01274 }
01275
01276 /**
01277   * @}
01278   */
01279
01280 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
01281   * @brief    Timer Complementary One Pulse functions
01282   *
01283 @verbatim
01284   ==============================================================================
01285                 ##### Timer Complementary One Pulse functions #####
01286   ==============================================================================
01287   [..]
01288     This section provides functions allowing to:
01289     (+) Start the Complementary One Pulse generation.
01290     (+) Stop the Complementary One Pulse.
01291     (+) Start the Complementary One Pulse and enable interrupts.
01292     (+) Stop the Complementary One Pulse and disable interrupts.
01293
01294 @endverbatim
01295   * @{
01296   */
01297
01298 /**
01299   * @brief  Starts the TIM One Pulse signal generation on the complementary
01300   *         output.
01301   * @param  htim : TIM One Pulse handle
01302   * @param  OutputChannel : TIM Channel to be enabled
01303   *          This parameter can be one of the following values:
01304   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01305   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01306   * @retval HAL status
01307   */
01308 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01309   {
01310   /* Check the parameters */
01311   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01312
01313   /* Enable the complementary One Pulse output */
01314   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01315
01316   /* Enable the Main Ouput */
01317   __HAL_TIM_MOE_ENABLE(htim);
01318
01319   /* Return function status */
01320   return HAL_OK;
01321 }
01322
01323 /**
01324   * @brief  Stops the TIM One Pulse signal generation on the complementary
01325   *         output.
01326   * @param  htim : TIM One Pulse handle
01327   * @param  OutputChannel : TIM Channel to be disabled
01328   *          This parameter can be one of the following values:
01329   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01330   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01331   * @retval HAL status
01332   */
01333 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01334 {
01335
01336   /* Check the parameters */
01337   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01338
01339   /* Disable the complementary One Pulse output */
01340   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01341
01342   /* Disable the Main Ouput */
01343   __HAL_TIM_MOE_DISABLE(htim);
01344
01345   /* Disable the Peripheral */
01346   __HAL_TIM_DISABLE(htim);
01347
01348   /* Return function status */
01349   return HAL_OK;
01350 }
01351
01352 /**
01353   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01354   *         complementary channel.
01355   * @param  htim : TIM One Pulse handle
01356   * @param  OutputChannel : TIM Channel to be enabled
01357   *          This parameter can be one of the following values:
01358   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01359   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01360   * @retval HAL status
01361   */
01362 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01363 {
01364   /* Check the parameters */
01365   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01366
01367   /* Enable the TIM Capture/Compare 1 interrupt */
01368   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01369
01370   /* Enable the TIM Capture/Compare 2 interrupt */
01371   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01372
01373   /* Enable the complementary One Pulse output */
01374   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01375
01376   /* Enable the Main Ouput */
01377   __HAL_TIM_MOE_ENABLE(htim);
01378
01379   /* Return function status */
01380   return HAL_OK;
01381 }
01382
01383 /**
01384   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01385   *         complementary channel.
01386   * @param  htim : TIM One Pulse handle
01387   * @param  OutputChannel : TIM Channel to be disabled
01388   *          This parameter can be one of the following values:
01389   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01390   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01391   * @retval HAL status
01392   */
01393 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01394 {
01395   /* Check the parameters */
01396   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01397
01398   /* Disable the TIM Capture/Compare 1 interrupt */
01399   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01400
01401   /* Disable the TIM Capture/Compare 2 interrupt */
01402   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01403
01404   /* Disable the complementary One Pulse output */
01405   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01406
01407   /* Disable the Main Ouput */
01408   __HAL_TIM_MOE_DISABLE(htim);
01409
01410   /* Disable the Peripheral */
01411   __HAL_TIM_DISABLE(htim);
01412
01413   /* Return function status */
01414   return HAL_OK;
01415 }
01416
01417 /**
01418   * @}
01419   */
01420
01421 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
01422   * @brief    Peripheral Control functions
01423   *
01424 @verbatim
01425   ==============================================================================
01426                     ##### Peripheral Control functions #####
01427   ==============================================================================
01428   [..]
01429     This section provides functions allowing to:
01430     (+) Configure the commutation event in case of use of the Hall sensor interface.
01431       (+) Configure Output channels for OC and PWM mode.
01432
01433       (+) Configure Complementary channels, break features and dead time.
01434       (+) Configure Master synchronization.
01435       (+) Configure timer remapping capabilities.
01436       (+) Enable or disable channel grouping
01437
01438 @endverbatim
01439   * @{
01440   */
01441
01442 /**
01443   * @brief  Configure the TIM commutation event sequence.
01444   * @note  This function is mandatory to use the commutation event in order to
01445   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01446   *        the typical use of this feature is with the use of another Timer(interface Timer)
01447   *        configured in Hall sensor interface, this interface Timer will generate the
01448   *        commutation at its TRGO output (connected to Timer used in this function) each time
01449   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01450   * @param  htim: TIM handle
01451   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01452   *          This parameter can be one of the following values:
01453   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01454   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01455   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01456   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01457   *            @arg TIM_TS_NONE: No trigger is needed
01458   * @param  CommutationSource : the Commutation Event source
01459   *          This parameter can be one of the following values:
01460   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01461   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01462   * @retval HAL status
01463   */
01464 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01465 {
01466   /* Check the parameters */
01467   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01468   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01469
01470   __HAL_LOCK(htim);
01471
01472   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01473       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01474   {
01475     /* Select the Input trigger */
01476     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01477     htim->Instance->SMCR |= InputTrigger;
01478   }
01479
01480   /* Select the Capture Compare preload feature */
01481   htim->Instance->CR2 |= TIM_CR2_CCPC;
01482   /* Select the Commutation event source */
01483   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01484   htim->Instance->CR2 |= CommutationSource;
01485
01486   __HAL_UNLOCK(htim);
01487
01488   return HAL_OK;
01489 }
01490
01491 /**
01492   * @brief  Configure the TIM commutation event sequence with interrupt.
01493   * @note  This function is mandatory to use the commutation event in order to
01494   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01495   *        the typical use of this feature is with the use of another Timer(interface Timer)
01496   *        configured in Hall sensor interface, this interface Timer will generate the
01497   *        commutation at its TRGO output (connected to Timer used in this function) each time
01498   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01499   * @param  htim: TIM handle
01500   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01501   *          This parameter can be one of the following values:
01502   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01503   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01504   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01505   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01506   *            @arg TIM_TS_NONE: No trigger is needed
01507   * @param  CommutationSource : the Commutation Event source
01508   *          This parameter can be one of the following values:
01509   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01510   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01511   * @retval HAL status
01512   */
01513 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01514 {
01515   /* Check the parameters */
01516   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01517   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01518
01519   __HAL_LOCK(htim);
01520
01521   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01522       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01523   {
01524     /* Select the Input trigger */
01525     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01526     htim->Instance->SMCR |= InputTrigger;
01527   }
01528
01529   /* Select the Capture Compare preload feature */
01530   htim->Instance->CR2 |= TIM_CR2_CCPC;
01531   /* Select the Commutation event source */
01532   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01533   htim->Instance->CR2 |= CommutationSource;
01534
01535   /* Enable the Commutation Interrupt Request */
01536   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
01537
01538   __HAL_UNLOCK(htim);
01539
01540   return HAL_OK;
01541 }
01542
01543 /**
01544   * @brief  Configure the TIM commutation event sequence with DMA.
01545   * @note  This function is mandatory to use the commutation event in order to
01546   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01547   *        the typical use of this feature is with the use of another Timer(interface Timer)
01548   *        configured in Hall sensor interface, this interface Timer will generate the
01549   *        commutation at its TRGO output (connected to Timer used in this function) each time
01550   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01551   * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
01552   * @param  htim: TIM handle
01553   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01554   *          This parameter can be one of the following values:
01555   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01556   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01557   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01558   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01559   *            @arg TIM_TS_NONE: No trigger is needed
01560   * @param  CommutationSource : the Commutation Event source
01561   *          This parameter can be one of the following values:
01562   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01563   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01564   * @retval HAL status
01565   */
01566 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01567 {
01568   /* Check the parameters */
01569   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01570   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01571
01572   __HAL_LOCK(htim);
01573
01574   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01575       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01576   {
01577     /* Select the Input trigger */
01578     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01579     htim->Instance->SMCR |= InputTrigger;
01580   }
01581
01582   /* Select the Capture Compare preload feature */
01583   htim->Instance->CR2 |= TIM_CR2_CCPC;
01584   /* Select the Commutation event source */
01585   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01586   htim->Instance->CR2 |= CommutationSource;
01587
01588   /* Enable the Commutation DMA Request */
01589   /* Set the DMA Commutation Callback */
01590   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
01591   /* Set the DMA error callback */
01592   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
01593
01594   /* Enable the Commutation DMA Request */
01595   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
01596
01597   __HAL_UNLOCK(htim);
01598
01599   return HAL_OK;
01600 }
01601
01602 /**
01603   * @brief  Configures the TIM in master mode.
01604   * @param  htim: TIM handle.
01605   * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
01606   *         contains the selected trigger output (TRGO) and the Master/Slave
01607   *         mode.
01608   * @retval HAL status
01609   */
01610 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
01611                                                       TIM_MasterConfigTypeDef * sMasterConfig)
01612 {
01613   uint32_t tmpcr2;
01614   uint32_t tmpsmcr;
01615
01616   /* Check the parameters */
01617   assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
01618   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
01619   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
01620
01621   /* Check input state */
01622   __HAL_LOCK(htim);
01623
01624  /* Get the TIMx CR2 register value */
01625   tmpcr2 = htim->Instance->CR2;
01626
01627   /* Get the TIMx SMCR register value */
01628   tmpsmcr = htim->Instance->SMCR;
01629
01630   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
01631   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
01632   {
01633     /* Check the parameters */
01634     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
01635
01636     /* Clear the MMS2 bits */
01637     tmpcr2 &= ~TIM_CR2_MMS2;
01638     /* Select the TRGO2 source*/
01639     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
01640   }
01641
01642   /* Reset the MMS Bits */
01643   tmpcr2 &= ~TIM_CR2_MMS;
01644   /* Select the TRGO source */
01645   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
01646
01647   /* Reset the MSM Bit */
01648   tmpsmcr &= ~TIM_SMCR_MSM;
01649   /* Set master mode */
01650   tmpsmcr |= sMasterConfig->MasterSlaveMode;
01651
01652   /* Update TIMx CR2 */
01653   htim->Instance->CR2 = tmpcr2;
01654
01655   /* Update TIMx SMCR */
01656   htim->Instance->SMCR = tmpsmcr;
01657
01658   __HAL_UNLOCK(htim);
01659
01660   return HAL_OK;
01661 }
01662
01663 /**
01664   * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
01665   *         and the AOE(automatic output enable).
01666   * @param  htim: TIM handle
01667   * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
01668   *         contains the BDTR Register configuration  information for the TIM peripheral.
01669   * @retval HAL status
01670   */
01671 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
01672                                                 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
01673 {
01674   uint32_t tmpbdtr = 0;
01675
01676   /* Check the parameters */
01677   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01678   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
01679   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
01680   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
01681   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
01682   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
01683   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
01684   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
01685   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
01686
01687   /* Check input state */
01688   __HAL_LOCK(htim);
01689
01690   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
01691      the OSSI State, the dead time value and the Automatic Output Enable Bit */
01692   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
01693   {
01694     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
01695     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
01696     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
01697
01698     /* Clear the BDTR bits */
01699     tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK |  TIM_BDTR_OSSI |
01700                  TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
01701                  TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
01702                  TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
01703
01704     /* Set the BDTR bits */
01705     tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
01706     tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
01707     tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
01708     tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
01709     tmpbdtr |= sBreakDeadTimeConfig->BreakState;
01710     tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
01711     tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
01712     tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
01713     tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
01714     tmpbdtr |= sBreakDeadTimeConfig->Break2State;
01715     tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
01716   }
01717   else
01718   {
01719     /* Clear the BDTR bits */
01720     tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK |  TIM_BDTR_OSSI |
01721                  TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
01722                  TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF);
01723
01724     /* Set the BDTR bits */
01725     tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
01726     tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
01727     tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
01728     tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
01729     tmpbdtr |= sBreakDeadTimeConfig->BreakState;
01730     tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
01731     tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
01732     tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
01733   }
01734
01735   /* Set TIMx_BDTR */
01736   htim->Instance->BDTR = tmpbdtr;
01737
01738   __HAL_UNLOCK(htim);
01739
01740   return HAL_OK;
01741 }
01742
01743 /**
01744   * @brief  Configures the break input source.
01745   * @param  htim: TIM handle.
01746   * @param  BreakInput: Break input to configure
01747   *          This parameter can be one of the following values:
01748   *            @arg TIM_BREAKINPUT_BRK: Timer break input
01749   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
01750   * @param  sBreakInputConfig: Break input source configuration
01751   * @retval HAL status
01752   */
01753 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
01754                                              uint32_t BreakInput,
01755                                              TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
01756
01757 {
01758   uint32_t tmporx = 0;
01759   uint32_t bkin_enable_mask = 0;
01760   uint32_t bkin_polarity_mask = 0;
01761   uint32_t bkin_enable_bitpos = 0;
01762   uint32_t bkin_polarity_bitpos = 0;
01763
01764   /* Check the parameters */
01765   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01766   assert_param(IS_TIM_BREAKINPUT(BreakInput));
01767   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
01768   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
01769
01770 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
01771   if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01772   {
01773     assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
01774   }
01775 #else
01776    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
01777 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01778
01779   /* Check input state */
01780   __HAL_LOCK(htim);
01781
01782   switch(sBreakInputConfig->Source)
01783   {
01784   case TIM_BREAKINPUTSOURCE_BKIN:
01785     {
01786       bkin_enable_mask = TIM1_OR2_BKINE;
01787       bkin_enable_bitpos = 0;
01788       bkin_polarity_mask = TIM1_OR2_BKINP;
01789       bkin_polarity_bitpos = 9;
01790     }
01791     break;
01792   case TIM_BREAKINPUTSOURCE_COMP1:
01793     {
01794       bkin_enable_mask = TIM1_OR2_BKCMP1E;
01795       bkin_enable_bitpos = 1;
01796       bkin_polarity_mask = TIM1_OR2_BKCMP1P;
01797       bkin_polarity_bitpos = 10;
01798     }
01799     break;
01800   case TIM_BREAKINPUTSOURCE_COMP2:
01801     {
01802       bkin_enable_mask = TIM1_OR2_BKCMP2E;
01803       bkin_enable_bitpos = 2;
01804       bkin_polarity_mask = TIM1_OR2_BKCMP2P;
01805       bkin_polarity_bitpos = 11;
01806     }
01807     break;
01808
01809 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
01810   case TIM_BREAKINPUTSOURCE_DFSDM1:
01811     {
01812       bkin_enable_mask = TIM1_OR2_BKDF1BK0E;
01813       bkin_enable_bitpos = 8;
01814     }
01815     break;
01816 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01817
01818   default:
01819     break;
01820   }
01821
01822   switch(BreakInput)
01823   {
01824     case TIM_BREAKINPUT_BRK:
01825       {
01826         /* Get the TIMx_OR2 register value */
01827         tmporx = htim->Instance->OR2;
01828
01829         /* Enable the break input */
01830         tmporx &= ~bkin_enable_mask;
01831         tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
01832
01833         /* Set the break input polarity */
01834 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
01835         if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01836 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01837         {
01838           tmporx &= ~bkin_polarity_mask;
01839           tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
01840         }
01841
01842         /* Set TIMx_OR2 */
01843         htim->Instance->OR2 = tmporx;
01844       }
01845         break;
01846     case TIM_BREAKINPUT_BRK2:
01847       {
01848         /* Get the TIMx_OR3 register value */
01849         tmporx = htim->Instance->OR3;
01850
01851         /* Enable the break input */
01852         tmporx &= ~bkin_enable_mask;
01853         tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
01854
01855         /* Set the break input polarity */
01856 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
01857         if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01858 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01859         {
01860           tmporx &= ~bkin_polarity_mask;
01861           tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
01862         }
01863
01864         /* Set TIMx_OR3 */
01865         htim->Instance->OR3 = tmporx;
01866       }
01867       break;
01868   default:
01869     break;
01870   }
01871
01872   __HAL_UNLOCK(htim);
01873
01874   return HAL_OK;
01875 }
01876
01877 /**
01878   * @brief  Configures the TIMx Remapping input capabilities.
01879   * @param  htim: TIM handle.
01880   * @param  Remap: specifies the TIM remapping source.
01881   *
01882   @if STM32L486xx
01883   *         For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
01884   *
01885   *                   field1 can have the following values:
01886   *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
01887   *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1
01888   *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2
01889   *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3
01890   *
01891   *                   field2 can have the following values:
01892   *            @arg TIM_TIM1_ETR_ADC3_NONE:           TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)
01893   *            @arg TIM_TIM1_ETR_ADC3_AWD1:           TIM1_ETR is connected to ADC3 AWD1
01894   *            @arg TIM_TIM1_ETR_ADC3_AWD2:           TIM1_ETR is connected to ADC3 AWD2
01895   *            @arg TIM_TIM1_ETR_ADC3_AWD3:           TIM1_ETR is connected to ADC3 AWD3
01896   *
01897   *                   field3 can have the following values:
01898   *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
01899   *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
01900   *
01901   *                   field4 can have the following values:
01902   *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output
01903   *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output
01904   *            @note  When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant
01905   @endif
01906   @if STM32L443xx
01907   *         For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3):
01908   *
01909   *                   field1 can have the following values:
01910   *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
01911   *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1
01912   *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2
01913   *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3
01914   *
01915   *                   field2 can have the following values:
01916   *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
01917   *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
01918   *
01919   *                   field3 can have the following values:
01920   *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output
01921   *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output
01922   *
01923   *            @note  When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant
01924   *
01925   @endif
01926   @if STM32L486xx
01927   *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
01928   *
01929   *                   field1 can have the following values:
01930   *            @arg TIM_TIM2_ITR1_TIM8_TRGO:          TIM2_ITR1 is connected to TIM8_TRGO
01931   *            @arg TIM_TIM2_ITR1_OTG_FS_SOF:         TIM2_ITR1 is connected to OTG_FS SOF
01932   *
01933   *                   field2 can have the following values:
01934   *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO
01935   *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE
01936   *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output
01937   *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output
01938   *
01939   *                   field3 can have the following values:
01940   *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
01941   *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
01942   *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
01943   *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
01944   @endif
01945   @if STM32L443xx
01946   *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
01947   *
01948   *                   field1 can have the following values:
01949   *            @arg TIM_TIM2_ITR1_NONE:               No internal trigger on TIM2_ITR1
01950   *            @arg TIM_TIM2_ITR1_USB_SOF:            TIM2_ITR1 is connected to USB SOF
01951   *
01952   *                   field2 can have the following values:
01953   *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO
01954   *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE
01955   *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output
01956   *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output
01957   *
01958   *                   field3 can have the following values:
01959   *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
01960   *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
01961   *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
01962   *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
01963   *
01964   @endif
01965   @if STM32L486xx
01966   *         For TIM3, the parameter is a combination 2 fields(field1 | field2):
01967   *
01968   *                   field1 can have the following values:
01969   *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
01970   *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
01971   *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
01972   *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
01973   *
01974   *                   field2 can have the following values:
01975   *            @arg TIM_TIM3_ETR_GPIO:                TIM3_ETR is connected to GPIO
01976   *            @arg TIM_TIM3_ETR_COMP1:               TIM3_ETR is connected to COMP1 output
01977   *
01978   @endif
01979   @if STM32L486xx
01980   *         For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):
01981   *
01982   *                   field1 can have the following values:
01983   *            @arg TIM_TIM8_ETR_ADC2_NONE:          TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)
01984   *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
01985   *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
01986   *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
01987   *
01988   *                   field2 can have the following values:
01989   *            @arg TIM_TIM8_ETR_ADC3_NONE:          TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)
01990   *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
01991   *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
01992   *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
01993   *
01994   *                   field3 can have the following values:
01995   *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
01996   *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
01997   *
01998   *                   field4 can have the following values:
01999   *            @arg TIM_TIM8_ETR_COMP1:               TIM8_ETR is connected to COMP1 output
02000   *            @arg TIM_TIM8_ETR_COMP2:               TIM8_ETR is connected to COMP2 output
02001   *            @note  When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant
02002   *
02003   @endif
02004   *         For TIM15, the parameter is a combination of 3 fields (field1 | field2):
02005   *
02006   *                   field1 can have the following values:
02007   *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
02008   *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
02009   *
02010   *                   field2 can have the following values:
02011   *            @arg TIM_TIM15_ENCODERMODE_NONE:      No redirection
02012   *            @arg TIM_TIM15_ENCODERMODE_TIM2:      TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
02013   *            @arg TIM_TIM15_ENCODERMODE_TIM3:      TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
02014   *            @arg TIM_TIM15_ENCODERMODE_TIM4:      TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
02015   *
02016   @if STM32L486xx
02017   *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
02018   *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
02019   *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
02020   *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
02021   *
02022   @endif
02023   @if STM32L443xx
02024   *         For TIM16, the parameter can have the following values:
02025   *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
02026   *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
02027   *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
02028   *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
02029   *            @arg TIM_TIM16_TI1_MSI:               TIM16 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)
02030   *            @arg TIM_TIM16_TI1_HSE_32:            TIM16 TI1 is connected to HSE div 32  (note that HSE div 32 must be selected as RTC clock source)
02031   *            @arg TIM_TIM16_TI1_MCO:               TIM16 TI1 is connected to MCO
02032   *
02033   @endif
02034   @if STM32L486xx
02035   *         For TIM17, the parameter can have the following values:
02036   *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
02037   *            @arg TIM_TIM17_TI1_MSI:               TIM17 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)
02038   *            @arg TIM_TIM17_TI1_HSE_32:            TIM17 TI1 is connected to HSE div 32
02039   *            @arg TIM_TIM17_TI1_MCO:               TIM17 TI1 is connected to MCO
02040   @endif
02041   *
02042   * @retval HAL status
02043   */
02044 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
02045 {
02046   uint32_t tmpor1 = 0;
02047   uint32_t tmpor2 = 0;
02048
02049   __HAL_LOCK(htim);
02050
02051   /* Check parameters */
02052   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
02053   assert_param(IS_TIM_REMAP(Remap));
02054
02055   /* Set ETR_SEL bit field (if required) */
02056   if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
02057   {
02058     tmpor2 = htim->Instance->OR2;
02059     tmpor2 &= ~TIMx_ETRSEL_MASK;
02060     tmpor2 |= (Remap & TIMx_ETRSEL_MASK);
02061
02062     /* Set TIMx_OR2 */
02063     htim->Instance->OR2 = tmpor2;
02064   }
02065
02066   /* Set other remapping capabilities */
02067   tmpor1 = Remap;
02068   tmpor1 &= ~TIMx_ETRSEL_MASK;
02069
02070   /* Set TIMx_OR1 */
02071   htim->Instance->OR1 = Remap;
02072
02073   /* Set TIMx_OR1 */
02074   htim->Instance->OR1 = tmpor1;
02075
02076   htim->State = HAL_TIM_STATE_READY;
02077
02078   __HAL_UNLOCK(htim);
02079
02080   return HAL_OK;
02081 }
02082
02083 /**
02084   * @brief  Group channel 5 and channel 1, 2 or 3
02085   * @param  htim: TIM handle.
02086   * @param  Channels: specifies the reference signal(s) the OC5REF is combined with.
02087   *         This parameter can be any combination of the following values:
02088   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
02089   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
02090   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
02091   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
02092   * @retval HAL status
02093   */
02094 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
02095 {
02096   /* Check parameters */
02097   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
02098   assert_param(IS_TIM_GROUPCH5(Channels));
02099
02100   /* Process Locked */
02101   __HAL_LOCK(htim);
02102
02103   htim->State = HAL_TIM_STATE_BUSY;
02104
02105   /* Clear GC5Cx bit fields */
02106   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
02107
02108   /* Set GC5Cx bit fields */
02109   htim->Instance->CCR5 |= Channels;
02110
02111   htim->State = HAL_TIM_STATE_READY;
02112
02113   __HAL_UNLOCK(htim);
02114
02115   return HAL_OK;
02116 }
02117
02118 /**
02119   * @}
02120   */
02121
02122 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
02123   * @brief    Extended Callbacks functions
02124   *
02125 @verbatim
02126   ==============================================================================
02127                     ##### Extended Callbacks functions #####
02128   ==============================================================================
02129   [..]
02130     This section provides Extended TIM callback functions:
02131     (+) Timer Commutation callback
02132     (+) Timer Break callback
02133
02134 @endverbatim
02135   * @{
02136   */
02137
02138 /**
02139   * @brief  Hall commutation changed callback in non-blocking mode
02140   * @param  htim : TIM handle
02141   * @retval None
02142   */
02143 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
02144 {
02145   /* Prevent unused argument(s) compilation warning */
02146   UNUSED(htim);
02147
02148   /* NOTE : This function should not be modified, when the callback is needed,
02149             the HAL_TIMEx_CommutationCallback could be implemented in the user file
02150    */
02151 }
02152
02153 /**
02154   * @brief  Hall Break detection callback in non-blocking mode
02155   * @param  htim : TIM handle
02156   * @retval None
02157   */
02158 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
02159 {
02160   /* Prevent unused argument(s) compilation warning */
02161   UNUSED(htim);
02162
02163   /* NOTE : This function should not be modified, when the callback is needed,
02164             the HAL_TIMEx_BreakCallback could be implemented in the user file
02165    */
02166 }
02167
02168 /**
02169   * @}
02170   */
02171
02172 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
02173   * @brief    Extended Peripheral State functions
02174   *
02175 @verbatim
02176   ==============================================================================
02177                 ##### Extended Peripheral State functions #####
02178   ==============================================================================
02179   [..]
02180     This subsection permits to get in run-time the status of the peripheral
02181     and the data flow.
02182
02183 @endverbatim
02184   * @{
02185   */
02186
02187 /**
02188   * @brief  Return the TIM Hall Sensor interface handle state.
02189   * @param  htim: TIM Hall Sensor handle
02190   * @retval HAL state
02191   */
02192 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
02193 {
02194   return htim->State;
02195 }
02196
02197 /**
02198   * @}
02199   */
02200
02201 /**
02202   * @brief  TIM DMA Commutation callback.
02203   * @param  hdma : pointer to DMA handle.
02204   * @retval None
02205   */
02206 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
02207 {
02208   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02209
02210   htim->State= HAL_TIM_STATE_READY;
02211
02212   HAL_TIMEx_CommutationCallback(htim);
02213 }
02214
02215 /**
02216   * @brief  Enables or disables the TIM Capture Compare Channel xN.
02217   * @param  TIMx to select the TIM peripheral
02218   * @param  Channel: specifies the TIM Channel
02219   *          This parameter can be one of the following values:
02220   *            @arg TIM_Channel_1: TIM Channel 1
02221   *            @arg TIM_Channel_2: TIM Channel 2
02222   *            @arg TIM_Channel_3: TIM Channel 3
02223   * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
02224   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
02225   * @retval None
02226   */
02227 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
02228 {
02229   uint32_t tmp = 0;
02230
02231   tmp = TIM_CCER_CC1NE << Channel;
02232
02233   /* Reset the CCxNE Bit */
02234   TIMx->CCER &=  ~tmp;
02235
02236   /* Set or reset the CCxNE Bit */
02237   TIMx->CCER |=  (uint32_t)(ChannelNState << Channel);
02238 }
02239
02240 /**
02241   * @}
02242   */
02243
02244 #endif /* HAL_TIM_MODULE_ENABLED */
02245 /**
02246   * @}
02247   */
02248
02249 /**
02250   * @}
02251   */
02252
02253 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tim_ex.h Source File

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stm32l4xx_hal_tim_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_tim_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of TIM HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_TIM_EX_H
00040 #define __STM32L4xx_HAL_TIM_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TIMEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  TIM Hall sensor Configuration Structure definition
00064   */
00065
00066 typedef struct
00067 {
00068
00069   uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
00070                                      This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00071
00072   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
00073                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00074
00075   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
00076                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00077
00078   uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00079                                      This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00080 } TIM_HallSensor_InitTypeDef;
00081
00082 /**
00083   * @brief  TIM Break/Break2 input configuration
00084   */
00085 typedef struct {
00086   uint32_t Source;         /*!< Specifies the source of the timer break input.
00087                                 This parameter can be a value of @ref TIMEx_Break_Input_Source */
00088   uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
00089                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
00090   uint32_t Polarity;       /*!< Specifies the break input source polarity.
00091                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
00092                                 Not relevant when analog watchdog output of the DFSDM1 used as break input source */
00093 } TIMEx_BreakInputConfigTypeDef;
00094
00095 /**
00096   * @}
00097   */
00098 /* End of exported types -----------------------------------------------------*/
00099
00100 /* Exported constants --------------------------------------------------------*/
00101 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
00102   * @{
00103   */
00104
00105 /** @defgroup TIMEx_Remap TIM  Extended Remapping
00106   * @{
00107   */
00108 #define TIM_TIM1_ETR_ADC1_NONE      ((uint32_t)(0x00000000))                              /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
00109 #define TIM_TIM1_ETR_ADC1_AWD1      (TIM1_OR1_ETR_ADC1_RMP_0)                             /* !< TIM1_ETR is connected to ADC1 AWD1 */
00110 #define TIM_TIM1_ETR_ADC1_AWD2      (TIM1_OR1_ETR_ADC1_RMP_1)                             /* !< TIM1_ETR is connected to ADC1 AWD2 */
00111 #define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0)   /* !< TIM1_ETR is connected to ADC1 AWD3 */
00112 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00113 #define TIM_TIM1_ETR_ADC3_NONE      ((uint32_t)(0x00000000))                              /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
00114 #define TIM_TIM1_ETR_ADC3_AWD1      (TIM1_OR1_ETR_ADC3_RMP_0)                             /* !< TIM1_ETR is connected to ADC3 AWD1 */
00115 #define TIM_TIM1_ETR_ADC3_AWD2      (TIM1_OR1_ETR_ADC3_RMP_1)                             /* !< TIM1_ETR is connected to ADC3 AWD2 */
00116 #define TIM_TIM1_ETR_ADC3_AWD3      (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0)   /* !< TIM1_ETR is connected to ADC3 AWD3 */
00117 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00118 #define TIM_TIM1_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM1 TI1 is connected to GPIO */
00119 #define TIM_TIM1_TI1_COMP1          (TIM1_OR1_TI1_RMP)                                    /* !< TIM1 TI1 is connected to COMP1 */
00120 #define TIM_TIM1_ETR_COMP1          (TIM1_OR2_ETRSEL_0)                                   /* !< TIM1_ETR is connected to COMP1 output */
00121 #define TIM_TIM1_ETR_COMP2          (TIM1_OR2_ETRSEL_1)                                   /* !< TIM1_ETR is connected to COMP2 output */
00122 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00123 #define TIM_TIM2_ITR1_TIM8_TRGO     ((uint32_t)(0x00000000))                              /* !< TIM2_ITR1 is connected to TIM8_TRGO */
00124 #define TIM_TIM2_ITR1_OTG_FS_SOF    (TIM2_OR1_ITR1_RMP)                                   /* !< TIM2_ITR1 is connected to OTG_FS SOF */
00125 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00126 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00127 #define TIM_TIM2_ITR1_NONE          ((uint32_t)(0x00000000))                              /* !< No internal trigger on TIM2_ITR1 */
00128 #define TIM_TIM2_ITR1_USB_SOF       (TIM2_OR1_ITR1_RMP)                                   /* !< TIM2_ITR1 is connected to USB SOF */
00129 #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx */
00130 #define TIM_TIM2_ETR_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM2_ETR is connected to GPIO */
00131 #define TIM_TIM2_ETR_LSE            (TIM2_OR1_ETR1_RMP)                                   /* !< TIM2_ETR is connected to LSE */
00132 #define TIM_TIM2_ETR_COMP1          (TIM2_OR2_ETRSEL_0)                                   /* !< TIM2_ETR is connected to COMP1 output */
00133 #define TIM_TIM2_ETR_COMP2          (TIM2_OR2_ETRSEL_1)                                   /* !< TIM2_ETR is connected to COMP2 output */
00134 #define TIM_TIM2_TI4_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM2 TI4 is connected to GPIO */
00135 #define TIM_TIM2_TI4_COMP1          (TIM2_OR1_TI4_RMP_0)                                  /* !< TIM2 TI4 is connected to COMP1 output */
00136 #define TIM_TIM2_TI4_COMP2          (TIM2_OR1_TI4_RMP_1)                                  /* !< TIM2 TI4 is connected to COMP2 output */
00137 #define TIM_TIM2_TI4_COMP1_COMP2    (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0)              /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
00138 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00139 #define TIM_TIM3_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM3 TI1 is connected to GPIO */
00140 #define TIM_TIM3_TI1_COMP1          (TIM3_OR1_TI1_RMP_0)                                  /* !< TIM3 TI1 is connected to COMP1 output */
00141 #define TIM_TIM3_TI1_COMP2          (TIM3_OR1_TI1_RMP_1)                                  /* !< TIM3 TI1 is connected to COMP2 output */
00142 #define TIM_TIM3_TI1_COMP1_COMP2    (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0)             /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
00143 #define TIM_TIM3_ETR_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM3_ETR is connected to GPIO */
00144 #define TIM_TIM3_ETR_COMP1          (TIM3_OR2_ETRSEL_0)                                   /* !< TIM3_ETR is connected to COMP1 output */
00145 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00146 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00147 #define TIM_TIM8_ETR_ADC2_NONE      ((uint32_t)(0x00000000))                              /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
00148 #define TIM_TIM8_ETR_ADC2_AWD1      (TIM8_OR1_ETR_ADC2_RMP_0)                             /* !< TIM8_ETR is connected to ADC2 AWD1 */
00149 #define TIM_TIM8_ETR_ADC2_AWD2      (TIM8_OR1_ETR_ADC2_RMP_1)                             /* !< TIM8_ETR is connected to ADC2 AWD2 */
00150 #define TIM_TIM8_ETR_ADC2_AWD3      (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0)   /* !< TIM8_ETR is connected to ADC2 AWD3 */
00151 #define TIM_TIM8_ETR_ADC3_NONE      ((uint32_t)(0x00000000))                              /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
00152 #define TIM_TIM8_ETR_ADC3_AWD1      (TIM8_OR1_ETR_ADC3_RMP_0)                             /* !< TIM8_ETR is connected to ADC3 AWD1 */
00153 #define TIM_TIM8_ETR_ADC3_AWD2      (TIM8_OR1_ETR_ADC3_RMP_1)                             /* !< TIM8_ETR is connected to ADC3 AWD2 */
00154 #define TIM_TIM8_ETR_ADC3_AWD3      (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0)   /* !< TIM8_ETR is connected to ADC3 AWD3 */
00155 #define TIM_TIM8_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM8 TI1 is connected to GPIO */
00156 #define TIM_TIM8_TI1_COMP2          (TIM8_OR1_TI1_RMP)                                    /* !< TIM8 TI1 is connected to COMP1 */
00157 #define TIM_TIM8_ETR_COMP1          (TIM8_OR2_ETRSEL_0)                                   /* !< TIM8_ETR is connected to COMP1 output */
00158 #define TIM_TIM8_ETR_COMP2          (TIM8_OR2_ETRSEL_1)                                   /* !< TIM8_ETR is connected to COMP2 output */
00159 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00160 #define TIM_TIM15_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM15 TI1 is connected to GPIO */
00161 #define TIM_TIM15_TI1_LSE           (TIM15_OR1_TI1_RMP)                                   /* !< TIM15 TI1 is connected to LSE */
00162 #define TIM_TIM15_ENCODERMODE_NONE  ((uint32_t)(0x00000000))                              /* !< No redirection */
00163 #define TIM_TIM15_ENCODERMODE_TIM2  (TIM15_OR1_ENCODER_MODE_0)                            /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
00164 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00165 #define TIM_TIM15_ENCODERMODE_TIM3  (TIM15_OR1_ENCODER_MODE_1)                            /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
00166 #define TIM_TIM15_ENCODERMODE_TIM4  (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
00167 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00168 #define TIM_TIM16_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM16 TI1 is connected to GPIO */
00169 #define TIM_TIM16_TI1_LSI           (TIM16_OR1_TI1_RMP_0)                                 /* !< TIM16 TI1 is connected to LSI */
00170 #define TIM_TIM16_TI1_LSE           (TIM16_OR1_TI1_RMP_1)                                 /* !< TIM16 TI1 is connected to LSE */
00171 #define TIM_TIM16_TI1_RTC           (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
00172 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00173 #define TIM_TIM16_TI1_MSI           (TIM16_OR1_TI1_RMP_2)                                 /* !< TIM16 TI1 is connected to MSI */
00174 #define TIM_TIM16_TI1_HSE_32        (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to HSE div 32 */
00175 #define TIM_TIM16_TI1_MCO           (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1)           /* !< TIM16 TI1 is connected to MCO */
00176 #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx */
00177 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00178 #define TIM_TIM17_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM17 TI1 is connected to GPIO */
00179 #define TIM_TIM17_TI1_MSI           (TIM17_OR1_TI1_RMP_0)                                 /* !< TIM17 TI1 is connected to MSI */
00180 #define TIM_TIM17_TI1_HSE_32        (TIM17_OR1_TI1_RMP_1)                                 /* !< TIM17 TI1 is connected to HSE div 32 */
00181 #define TIM_TIM17_TI1_MCO           (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0)           /* !< TIM17 TI1 is connected to MCO */
00182 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup TIMEx_Break_Input TIM  Extended Break input
00188   * @{
00189   */
00190 #define TIM_BREAKINPUT_BRK     ((uint32_t)(0x00000001)) /* !< Timer break input  */
00191 #define TIM_BREAKINPUT_BRK2    ((uint32_t)(0x00000002)) /* !< Timer break2 input */
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup TIMEx_Break_Input_Source TIM  Extended Break input source
00197   * @{
00198   */
00199 #define TIM_BREAKINPUTSOURCE_BKIN     ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin  */
00200 #define TIM_BREAKINPUTSOURCE_COMP1    ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
00201 #define TIM_BREAKINPUTSOURCE_COMP2    ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
00202 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00203 #define TIM_BREAKINPUTSOURCE_DFSDM1   ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
00204 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
00210   * @{
00211   */
00212 #define TIM_BREAKINPUTSOURCE_DISABLE     ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
00213 #define TIM_BREAKINPUTSOURCE_ENABLE      ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM  Extended Break input polarity
00219   * @{
00220   */
00221 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW     ((uint32_t)(0x00000001)) /* !< Break input source is active low */
00222 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
00223 /**
00224   * @}
00225   */
00226
00227 /**
00228   * @}
00229   */
00230 /* End of exported constants -------------------------------------------------*/
00231
00232 /* Exported macro ------------------------------------------------------------*/
00233 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
00234   * @{
00235   */
00236
00237 /**
00238   * @}
00239   */
00240 /* End of exported macro -----------------------------------------------------*/
00241
00242 /* Private macro -------------------------------------------------------------*/
00243 /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
00244   * @{
00245   */
00246 #define IS_TIM_REMAP(__REMAP__)    (((__REMAP__) <= (uint32_t)0x0001C01F))
00247
00248 #define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
00249                                             ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
00250
00251 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00252 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
00253                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
00254                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
00255                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
00256 #else
00257 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
00258                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
00259                                               ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
00260 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00261
00262 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
00263                                                    ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
00264
00265 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
00266                                                          ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
00267 /**
00268   * @}
00269   */
00270 /* End of private macro ------------------------------------------------------*/
00271
00272 /* Exported functions --------------------------------------------------------*/
00273 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
00274   * @{
00275   */
00276
00277 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00278  *  @brief    Timer Hall Sensor functions
00279  * @{
00280  */
00281 /*  Timer Hall Sensor functions  **********************************************/
00282 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
00283 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
00284
00285 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
00286 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
00287
00288  /* Blocking mode: Polling */
00289 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
00290 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
00291 /* Non-Blocking mode: Interrupt */
00292 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
00293 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
00294 /* Non-Blocking mode: DMA */
00295 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
00296 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
00297 /**
00298   * @}
00299   */
00300
00301 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00302  *  @brief   Timer Complementary Output Compare functions
00303  * @{
00304  */
00305 /*  Timer Complementary Output Compare functions  *****************************/
00306 /* Blocking mode: Polling */
00307 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00308 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00309
00310 /* Non-Blocking mode: Interrupt */
00311 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00312 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00313
00314 /* Non-Blocking mode: DMA */
00315 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00316 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00317 /**
00318   * @}
00319   */
00320
00321 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00322  *  @brief    Timer Complementary PWM functions
00323  * @{
00324  */
00325 /*  Timer Complementary PWM functions  ****************************************/
00326 /* Blocking mode: Polling */
00327 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00328 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00329
00330 /* Non-Blocking mode: Interrupt */
00331 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00332 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00333 /* Non-Blocking mode: DMA */
00334 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00335 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00336 /**
00337   * @}
00338   */
00339
00340 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
00341  *  @brief    Timer Complementary One Pulse functions
00342  * @{
00343  */
00344 /*  Timer Complementary One Pulse functions  **********************************/
00345 /* Blocking mode: Polling */
00346 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00347 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00348
00349 /* Non-Blocking mode: Interrupt */
00350 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00351 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00352 /**
00353   * @}
00354   */
00355
00356 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
00357  *  @brief    Peripheral Control functions
00358  * @{
00359  */
00360 /* Extended Control functions  ************************************************/
00361 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00362 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00363 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00364 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
00365 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
00366 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
00367 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
00368 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
00369
00370 /**
00371   * @}
00372   */
00373
00374 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
00375   * @brief    Extended Callbacks functions
00376   * @{
00377   */
00378 /* Extended Callback **********************************************************/
00379 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
00380 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
00381 /**
00382   * @}
00383   */
00384
00385 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
00386   * @brief    Extended Peripheral State functions
00387   * @{
00388   */
00389 /* Extended Peripheral State functions  ***************************************/
00390 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
00391 /**
00392   * @}
00393   */
00394
00395 /**
00396   * @}
00397   */
00398 /* End of exported functions -------------------------------------------------*/
00399
00400 /* Private functions----------------------------------------------------------*/
00401 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
00402 * @{
00403 */
00404 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
00405 /**
00406 * @}
00407 */
00408 /* End of private functions --------------------------------------------------*/
00409
00410 /**
00411   * @}
00412   */
00413
00414 /**
00415   * @}
00416   */
00417
00418 #ifdef __cplusplus
00419 }
00420 #endif
00421
00422
00423 #endif /* __STM32L4xx_HAL_TIM_EX_H */
00424
00425 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tsc.c Source File

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stm32l4xx_hal_tsc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_tsc.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Touch Sensing Controller (TSC) peripheral:
00009   *           + Initialization and De-initialization
00010   *           + Channel IOs, Shield IOs and Sampling IOs configuration
00011   *           + Start and Stop an acquisition
00012   *           + Read acquisition result
00013   *           + Interrupts and flags management
00014   *
00015   @verbatim
00016 ================================================================================
00017                        ##### TSC specific features #####
00018 ================================================================================
00019   [..]
00020   (#) Proven and robust surface charge transfer acquisition principle
00021
00022   (#) Supports up to 3 capacitive sensing channels per group
00023
00024   (#) Capacitive sensing channels can be acquired in parallel offering a very good
00025       response time
00026
00027   (#) Spread spectrum feature to improve system robustness in noisy environments
00028
00029   (#) Full hardware management of the charge transfer acquisition sequence
00030
00031   (#) Programmable charge transfer frequency
00032
00033   (#) Programmable sampling capacitor I/O pin
00034
00035   (#) Programmable channel I/O pin
00036
00037   (#) Programmable max count value to avoid long acquisition when a channel is faulty
00038
00039   (#) Dedicated end of acquisition and max count error flags with interrupt capability
00040
00041   (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
00042       components
00043
00044   (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
00045
00046
00047                           ##### How to use this driver #####
00048 ================================================================================
00049   [..]
00050     (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
00051
00052     (#) GPIO pins configuration
00053       (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
00054       (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
00055            and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
00056            using HAL_GPIO_Init() function.
00057
00058     (#) Interrupts configuration
00059       (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
00060            and HAL_NVIC_EnableIRQ() and function.
00061
00062     (#) TSC configuration
00063       (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
00064
00065  [..]   TSC peripheral alternate functions are mapped on AF9.
00066
00067   *** Acquisition sequence ***
00068   ===================================
00069   [..]
00070     (+) Discharge all IOs using HAL_TSC_IODischarge() function.
00071     (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
00072         of the sampling capacitor and electrodes design.
00073     (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
00074     (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
00075         If the synchronized mode is selected, the acquisition will start as soon as the signal
00076         is received on the synchro pin.
00077     (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
00078         HAL_TSC_GetState() function or using WFI instruction for example.
00079     (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
00080     (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
00081
00082   @endverbatim
00083   ******************************************************************************
00084
00085     Table 1. IOs for the STM32L4xx devices
00086     +--------------------------------+
00087     |       IOs    |   TSC functions |
00088     |--------------|-----------------|
00089     |   PB12 (AF)  |   TSC_G1_IO1    |
00090     |   PB13 (AF)  |   TSC_G1_IO2    |
00091     |   PB14 (AF)  |   TSC_G1_IO3    |
00092     |   PB15 (AF)  |   TSC_G1_IO4    |
00093     |--------------|-----------------|
00094     |   PB4 (AF)   |   TSC_G2_IO1    |
00095     |   PB5 (AF)   |   TSC_G2_IO2    |
00096     |   PB6 (AF)   |   TSC_G2_IO3    |
00097     |   PB7 (AF)   |   TSC_G2_IO4    |
00098     |--------------|-----------------|
00099     |   PA15 (AF)  |   TSC_G3_IO1    |
00100     |   PC10 (AF)  |   TSC_G3_IO2    |
00101     |   PC11 (AF)  |   TSC_G3_IO3    |
00102     |   PC12 (AF)  |   TSC_G3_IO4    |
00103     |--------------|-----------------|
00104     |   PC6 (AF)   |   TSC_G4_IO1    |
00105     |   PC7 (AF)   |   TSC_G4_IO2    |
00106     |   PC8 (AF)   |   TSC_G4_IO3    |
00107     |   PC9 (AF)   |   TSC_G4_IO4    |
00108     |--------------|-----------------|
00109     |   PE10 (AF)  |   TSC_G5_IO1    |
00110     |   PE11 (AF)  |   TSC_G5_IO2    |
00111     |   PE12 (AF)  |   TSC_G5_IO3    |
00112     |   PE13 (AF)  |   TSC_G5_IO4    |
00113     |--------------|-----------------|
00114     |   PD10 (AF)  |   TSC_G6_IO1    |
00115     |   PD11 (AF)  |   TSC_G6_IO2    |
00116     |   PD12 (AF)  |   TSC_G6_IO3    |
00117     |   PD13 (AF)  |   TSC_G6_IO4    |
00118     |--------------|-----------------|
00119     |   PE2 (AF)   |   TSC_G7_IO1    |
00120     |   PE3 (AF)   |   TSC_G7_IO2    |
00121     |   PE4 (AF)   |   TSC_G7_IO3    |
00122     |   PE5 (AF)   |   TSC_G7_IO4    |
00123     |--------------|-----------------|
00124     |   PF14 (AF)  |   TSC_G8_IO1    |
00125     |   PF15 (AF)  |   TSC_G8_IO2    |
00126     |   PG0 (AF)   |   TSC_G8_IO3    |
00127     |   PG1 (AF)   |   TSC_G8_IO4    |
00128     |--------------|-----------------|
00129     |   PB10 (AF)  |   TSC_SYNC      |
00130     |   PD2 (AF)   |                 |
00131     +--------------------------------+
00132
00133   ******************************************************************************
00134   * @attention
00135   *
00136   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00137   *
00138   * Redistribution and use in source and binary forms, with or without modification,
00139   * are permitted provided that the following conditions are met:
00140   *   1. Redistributions of source code must retain the above copyright notice,
00141   *      this list of conditions and the following disclaimer.
00142   *   2. Redistributions in binary form must reproduce the above copyright notice,
00143   *      this list of conditions and the following disclaimer in the documentation
00144   *      and/or other materials provided with the distribution.
00145   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00146   *      may be used to endorse or promote products derived from this software
00147   *      without specific prior written permission.
00148   *
00149   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00150   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00151   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00152   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00153   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00154   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00155   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00156   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00157   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00158   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00159   *
00160   ******************************************************************************
00161   */
00162
00163 /* Includes ------------------------------------------------------------------*/
00164 #include "stm32l4xx_hal.h"
00165
00166 /** @addtogroup STM32L4xx_HAL_Driver
00167   * @{
00168   */
00169
00170 /** @defgroup TSC TSC
00171   * @brief HAL TSC module driver
00172   * @{
00173   */
00174
00175 #ifdef HAL_TSC_MODULE_ENABLED
00176
00177 /* Private typedef -----------------------------------------------------------*/
00178 /* Private define ------------------------------------------------------------*/
00179 /* Private macro -------------------------------------------------------------*/
00180 /* Private variables ---------------------------------------------------------*/
00181 /* Private function prototypes -----------------------------------------------*/
00182 static uint32_t TSC_extract_groups(uint32_t iomask);
00183
00184 /* Exported functions --------------------------------------------------------*/
00185
00186 /** @defgroup TSC_Exported_Functions Exported Functions
00187   * @{
00188   */
00189
00190 /** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
00191  *  @brief    Initialization and Configuration functions
00192  *
00193 @verbatim
00194  ===============================================================================
00195               ##### Initialization and de-initialization functions #####
00196  ===============================================================================
00197     [..]  This section provides functions allowing to:
00198       (+) Initialize and configure the TSC.
00199       (+) De-initialize the TSC.
00200 @endverbatim
00201   * @{
00202   */
00203
00204 /**
00205   * @brief  Initialize the TSC peripheral according to the specified parameters
00206   *         in the TSC_InitTypeDef structure and initialize the associated handle.
00207   * @param  htsc: TSC handle
00208   * @retval HAL status
00209   */
00210 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
00211 {
00212   /* Check TSC handle allocation */
00213   if (htsc == NULL)
00214   {
00215     return HAL_ERROR;
00216   }
00217
00218   /* Check the parameters */
00219   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00220   assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
00221   assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
00222   assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
00223   assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
00224   assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
00225   assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
00226   assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
00227   assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
00228   assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
00229   assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
00230   assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
00231
00232   if(htsc->State == HAL_TSC_STATE_RESET)
00233   {
00234     /* Allocate lock resource and initialize it */
00235     htsc->Lock = HAL_UNLOCKED;
00236   }
00237
00238   /* Initialize the TSC state */
00239   htsc->State = HAL_TSC_STATE_BUSY;
00240
00241   /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00242   HAL_TSC_MspInit(htsc);
00243
00244   /*--------------------------------------------------------------------------*/
00245   /* Set TSC parameters */
00246
00247   /* Enable TSC */
00248   htsc->Instance->CR = TSC_CR_TSCE;
00249
00250   /* Set all functions */
00251   htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
00252                          htsc->Init.CTPulseLowLength |
00253                          (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) |
00254                          htsc->Init.SpreadSpectrumPrescaler |
00255                          htsc->Init.PulseGeneratorPrescaler |
00256                          htsc->Init.MaxCountValue |
00257                          htsc->Init.SynchroPinPolarity |
00258                          htsc->Init.AcquisitionMode);
00259
00260   /* Spread spectrum */
00261   if (htsc->Init.SpreadSpectrum == ENABLE)
00262   {
00263     htsc->Instance->CR |= TSC_CR_SSE;
00264   }
00265
00266   /* Disable Schmitt trigger hysteresis on all used TSC IOs */
00267   htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
00268
00269   /* Set channel and shield IOs */
00270   htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
00271
00272   /* Set sampling IOs */
00273   htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
00274
00275   /* Set the groups to be acquired */
00276   htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
00277
00278   /* Disable interrupts */
00279   htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
00280
00281   /* Clear flags */
00282   htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
00283
00284   /*--------------------------------------------------------------------------*/
00285
00286   /* Initialize the TSC state */
00287   htsc->State = HAL_TSC_STATE_READY;
00288
00289   /* Return function status */
00290   return HAL_OK;
00291 }
00292
00293 /**
00294   * @brief  Deinitialize the TSC peripheral registers to their default reset values.
00295   * @param  htsc: TSC handle
00296   * @retval HAL status
00297   */
00298 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
00299 {
00300   /* Check TSC handle allocation */
00301   if (htsc == NULL)
00302   {
00303     return HAL_ERROR;
00304   }
00305
00306   /* Check the parameters */
00307   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00308
00309   /* Change TSC state */
00310   htsc->State = HAL_TSC_STATE_BUSY;
00311
00312   /* DeInit the low level hardware */
00313   HAL_TSC_MspDeInit(htsc);
00314
00315   /* Change TSC state */
00316   htsc->State = HAL_TSC_STATE_RESET;
00317
00318   /* Process unlocked */
00319   __HAL_UNLOCK(htsc);
00320
00321   /* Return function status */
00322   return HAL_OK;
00323 }
00324
00325 /**
00326   * @brief  Initialize the TSC MSP.
00327   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00328   *         the configuration information for the specified TSC.
00329   * @retval None
00330   */
00331 __weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
00332 {
00333   /* Prevent unused argument(s) compilation warning */
00334   UNUSED(htsc);
00335
00336   /* NOTE : This function should not be modified, when the callback is needed,
00337             the HAL_TSC_MspInit could be implemented in the user file.
00338    */
00339 }
00340
00341 /**
00342   * @brief  DeInitialize the TSC MSP.
00343   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00344   *         the configuration information for the specified TSC.
00345   * @retval None
00346   */
00347 __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
00348 {
00349   /* Prevent unused argument(s) compilation warning */
00350   UNUSED(htsc);
00351
00352   /* NOTE : This function should not be modified, when the callback is needed,
00353             the HAL_TSC_MspDeInit could be implemented in the user file.
00354    */
00355 }
00356
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
00362  *  @brief    Input and Output operation functions
00363  *
00364 @verbatim
00365  ===============================================================================
00366              ##### IO Operation functions #####
00367  ===============================================================================
00368     [..]  This section provides functions allowing to:
00369       (+) Start acquisition in polling mode.
00370       (+) Start acquisition in interrupt mode.
00371       (+) Stop conversion in polling mode.
00372       (+) Stop conversion in interrupt mode.
00373       (+) Poll for acquisition completed.
00374       (+) Get group acquisition status.
00375       (+) Get group acquisition value.
00376 @endverbatim
00377   * @{
00378   */
00379
00380 /**
00381   * @brief  Start the acquisition.
00382   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00383   *         the configuration information for the specified TSC.
00384   * @retval HAL status
00385   */
00386 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
00387 {
00388   /* Check the parameters */
00389   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00390
00391   /* Process locked */
00392   __HAL_LOCK(htsc);
00393
00394   /* Change TSC state */
00395   htsc->State = HAL_TSC_STATE_BUSY;
00396
00397   /* Clear interrupts */
00398   __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
00399
00400   /* Clear flags */
00401   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00402
00403   /* Set touch sensing IOs not acquired to the specified IODefaultMode */
00404   if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
00405   {
00406     __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00407   }
00408   else
00409   {
00410     __HAL_TSC_SET_IODEF_INFLOAT(htsc);
00411   }
00412
00413   /* Launch the acquisition */
00414   __HAL_TSC_START_ACQ(htsc);
00415
00416   /* Process unlocked */
00417   __HAL_UNLOCK(htsc);
00418
00419   /* Return function status */
00420   return HAL_OK;
00421 }
00422
00423 /**
00424   * @brief  Start the acquisition in interrupt mode.
00425   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00426   *         the configuration information for the specified TSC.
00427   * @retval HAL status.
00428   */
00429 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
00430 {
00431   /* Check the parameters */
00432   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00433   assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
00434
00435   /* Process locked */
00436   __HAL_LOCK(htsc);
00437
00438   /* Change TSC state */
00439   htsc->State = HAL_TSC_STATE_BUSY;
00440
00441   /* Enable end of acquisition interrupt */
00442   __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
00443
00444   /* Enable max count error interrupt (optional) */
00445   if (htsc->Init.MaxCountInterrupt == ENABLE)
00446   {
00447     __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
00448   }
00449   else
00450   {
00451     __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
00452   }
00453
00454   /* Clear flags */
00455   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00456
00457   /* Set touch sensing IOs not acquired to the specified IODefaultMode */
00458   if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
00459   {
00460     __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00461   }
00462   else
00463   {
00464     __HAL_TSC_SET_IODEF_INFLOAT(htsc);
00465   }
00466
00467   /* Launch the acquisition */
00468   __HAL_TSC_START_ACQ(htsc);
00469
00470   /* Process unlocked */
00471   __HAL_UNLOCK(htsc);
00472
00473   /* Return function status */
00474   return HAL_OK;
00475 }
00476
00477 /**
00478   * @brief  Stop the acquisition previously launched in polling mode.
00479   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00480   *         the configuration information for the specified TSC.
00481   * @retval HAL status
00482   */
00483 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
00484 {
00485   /* Check the parameters */
00486   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00487
00488   /* Process locked */
00489   __HAL_LOCK(htsc);
00490
00491   /* Stop the acquisition */
00492   __HAL_TSC_STOP_ACQ(htsc);
00493
00494   /* Set touch sensing IOs in low power mode (output push-pull) */
00495   __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00496
00497   /* Clear flags */
00498   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00499
00500   /* Change TSC state */
00501   htsc->State = HAL_TSC_STATE_READY;
00502
00503   /* Process unlocked */
00504   __HAL_UNLOCK(htsc);
00505
00506   /* Return function status */
00507   return HAL_OK;
00508 }
00509
00510 /**
00511   * @brief  Stop the acquisition previously launched in interrupt mode.
00512   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00513   *         the configuration information for the specified TSC.
00514   * @retval HAL status
00515   */
00516 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
00517 {
00518   /* Check the parameters */
00519   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00520
00521   /* Process locked */
00522   __HAL_LOCK(htsc);
00523
00524   /* Stop the acquisition */
00525   __HAL_TSC_STOP_ACQ(htsc);
00526
00527   /* Set touch sensing IOs in low power mode (output push-pull) */
00528   __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00529
00530   /* Disable interrupts */
00531   __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
00532
00533   /* Clear flags */
00534   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00535
00536   /* Change TSC state */
00537   htsc->State = HAL_TSC_STATE_READY;
00538
00539   /* Process unlocked */
00540   __HAL_UNLOCK(htsc);
00541
00542   /* Return function status */
00543   return HAL_OK;
00544 }
00545
00546 /**
00547   * @brief  Start acquisition and wait until completion.
00548   * @note   There is no need of a timeout parameter as the max count error is already
00549   *         managed by the TSC peripheral.
00550   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00551   *         the configuration information for the specified TSC.
00552   * @retval HAL state
00553   */
00554 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
00555 {
00556   /* Check the parameters */
00557   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00558
00559   /* Process locked */
00560   __HAL_LOCK(htsc);
00561
00562   /* Check end of acquisition */
00563   while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
00564   {
00565     /* The timeout (max count error) is managed by the TSC peripheral itself. */
00566   }
00567
00568   /* Process unlocked */
00569   __HAL_UNLOCK(htsc);
00570
00571   return HAL_OK;
00572 }
00573
00574 /**
00575   * @brief  Get the acquisition status for a group.
00576   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00577   *         the configuration information for the specified TSC.
00578   * @param  gx_index: Index of the group
00579   * @retval Group status
00580   */
00581 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
00582 {
00583   /* Check the parameters */
00584   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00585   assert_param(IS_TSC_GROUP_INDEX(gx_index));
00586
00587   /* Return the group status */
00588   return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
00589 }
00590
00591 /**
00592   * @brief  Get the acquisition measure for a group.
00593   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00594   *         the configuration information for the specified TSC.
00595   * @param  gx_index: Index of the group
00596   * @retval Acquisition measure
00597   */
00598 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
00599 {
00600   /* Check the parameters */
00601   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00602   assert_param(IS_TSC_GROUP_INDEX(gx_index));
00603
00604   /* Return the group acquisition counter */
00605   return htsc->Instance->IOGXCR[gx_index];
00606 }
00607
00608 /**
00609   * @}
00610   */
00611
00612 /** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
00613  *  @brief    Peripheral Control functions
00614  *
00615 @verbatim
00616  ===============================================================================
00617              ##### Peripheral Control functions #####
00618  ===============================================================================
00619     [..]  This section provides functions allowing to:
00620       (+) Configure TSC IOs
00621       (+) Discharge TSC IOs
00622 @endverbatim
00623   * @{
00624   */
00625
00626 /**
00627   * @brief  Configure TSC IOs.
00628   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00629   *         the configuration information for the specified TSC.
00630   * @param  config: pointer to the configuration structure.
00631   * @retval HAL status
00632   */
00633 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
00634 {
00635   /* Check the parameters */
00636   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00637
00638   /* Process locked */
00639   __HAL_LOCK(htsc);
00640
00641   /* Stop acquisition */
00642   __HAL_TSC_STOP_ACQ(htsc);
00643
00644   /* Disable Schmitt trigger hysteresis on all used TSC IOs */
00645   htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
00646
00647   /* Set channel and shield IOs */
00648   htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
00649
00650   /* Set sampling IOs */
00651   htsc->Instance->IOSCR = config->SamplingIOs;
00652
00653   /* Set groups to be acquired */
00654   htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
00655
00656   /* Process unlocked */
00657   __HAL_UNLOCK(htsc);
00658
00659   /* Return function status */
00660   return HAL_OK;
00661 }
00662
00663 /**
00664   * @brief  Discharge TSC IOs.
00665   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00666   *         the configuration information for the specified TSC.
00667   * @param  choice: enable or disable
00668   * @retval HAL status
00669   */
00670 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
00671 {
00672   /* Check the parameters */
00673   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00674
00675   /* Process locked */
00676   __HAL_LOCK(htsc);
00677
00678   if (choice == ENABLE)
00679   {
00680     __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00681   }
00682   else
00683   {
00684     __HAL_TSC_SET_IODEF_INFLOAT(htsc);
00685   }
00686
00687   /* Process unlocked */
00688   __HAL_UNLOCK(htsc);
00689
00690   /* Return the group acquisition counter */
00691   return HAL_OK;
00692 }
00693
00694 /**
00695   * @}
00696   */
00697
00698 /** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
00699  *  @brief   Peripheral State and Errors functions
00700  *
00701 @verbatim
00702  ===============================================================================
00703             ##### State and Errors functions #####
00704  ===============================================================================
00705     [..]
00706     This subsection provides functions allowing to
00707       (+) Get TSC state.
00708
00709 @endverbatim
00710   * @{
00711   */
00712
00713 /**
00714   * @brief  Return the TSC handle state.
00715   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00716   *         the configuration information for the specified TSC.
00717   * @retval HAL state
00718   */
00719 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
00720 {
00721   /* Check the parameters */
00722   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00723
00724   if (htsc->State == HAL_TSC_STATE_BUSY)
00725   {
00726     /* Check end of acquisition flag */
00727     if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
00728     {
00729       /* Check max count error flag */
00730       if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
00731       {
00732         /* Change TSC state */
00733         htsc->State = HAL_TSC_STATE_ERROR;
00734       }
00735       else
00736       {
00737         /* Change TSC state */
00738         htsc->State = HAL_TSC_STATE_READY;
00739       }
00740     }
00741   }
00742
00743   /* Return TSC state */
00744   return htsc->State;
00745 }
00746
00747 /**
00748   * @}
00749   */
00750
00751 /** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00752  * @{
00753  */
00754
00755 /**
00756   * @brief  Handle TSC interrupt request.
00757   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00758   *         the configuration information for the specified TSC.
00759   * @retval None
00760   */
00761 void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
00762 {
00763   /* Check the parameters */
00764   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00765
00766   /* Check if the end of acquisition occurred */
00767   if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
00768   {
00769     /* Clear EOA flag */
00770     __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
00771   }
00772
00773   /* Check if max count error occurred */
00774   if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
00775   {
00776     /* Clear MCE flag */
00777     __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
00778     /* Change TSC state */
00779     htsc->State = HAL_TSC_STATE_ERROR;
00780     /* Conversion completed callback */
00781     HAL_TSC_ErrorCallback(htsc);
00782   }
00783   else
00784   {
00785     /* Change TSC state */
00786     htsc->State = HAL_TSC_STATE_READY;
00787     /* Conversion completed callback */
00788     HAL_TSC_ConvCpltCallback(htsc);
00789   }
00790 }
00791
00792 /**
00793   * @brief  Acquisition completed callback in non-blocking mode.
00794   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00795   *         the configuration information for the specified TSC.
00796   * @retval None
00797   */
00798 __weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
00799 {
00800   /* Prevent unused argument(s) compilation warning */
00801   UNUSED(htsc);
00802
00803   /* NOTE : This function should not be modified, when the callback is needed,
00804             the HAL_TSC_ConvCpltCallback could be implemented in the user file.
00805    */
00806 }
00807
00808 /**
00809   * @brief  Error callback in non-blocking mode.
00810   * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
00811   *         the configuration information for the specified TSC.
00812   * @retval None
00813   */
00814 __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
00815 {
00816   /* Prevent unused argument(s) compilation warning */
00817   UNUSED(htsc);
00818
00819   /* NOTE : This function should not be modified, when the callback is needed,
00820             the HAL_TSC_ErrorCallback could be implemented in the user file.
00821    */
00822 }
00823
00824 /**
00825   * @}
00826   */
00827
00828 /**
00829   * @}
00830   */
00831
00832 /* Private functions ---------------------------------------------------------*/
00833 /** @defgroup TSC_Private_Functions Private Functions
00834   * @{
00835   */
00836
00837 /**
00838   * @brief  Utility function used to set the acquired groups mask.
00839   * @param  iomask: Channels IOs mask
00840   * @retval Acquired groups mask
00841   */
00842 static uint32_t TSC_extract_groups(uint32_t iomask)
00843 {
00844   uint32_t groups = 0;
00845   uint32_t idx;
00846
00847   for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++)
00848   {
00849     if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET)
00850     {
00851       groups |= ((uint32_t)1 << idx);
00852     }
00853   }
00854
00855   return groups;
00856 }
00857
00858 /**
00859   * @}
00860   */
00861
00862 #endif /* HAL_TSC_MODULE_ENABLED */
00863
00864 /**
00865   * @}
00866   */
00867
00868 /**
00869   * @}
00870   */
00871
00872 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_tsc.h Source File

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stm32l4xx_hal_tsc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_tsc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of TSC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_TSC_H
00040 #define __STM32L4xx_HAL_TSC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TSC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TSC_Exported_Types TSC Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief TSC state structure definition
00064   */
00065 typedef enum
00066 {
00067   HAL_TSC_STATE_RESET  = 0x00, /*!< TSC registers have their reset value */
00068   HAL_TSC_STATE_READY  = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */
00069   HAL_TSC_STATE_BUSY   = 0x02, /*!< TSC initialization or acquisition is on-going */
00070   HAL_TSC_STATE_ERROR  = 0x03  /*!< Acquisition is completed with max count error */
00071 } HAL_TSC_StateTypeDef;
00072
00073 /**
00074   * @brief TSC group status structure definition
00075   */
00076 typedef enum
00077 {
00078   TSC_GROUP_ONGOING   = 0x00, /*!< Acquisition on group is on-going or not started */
00079   TSC_GROUP_COMPLETED = 0x01  /*!< Acquisition on group is completed with success (no max count error) */
00080 } TSC_GroupStatusTypeDef;
00081
00082 /**
00083   * @brief TSC init structure definition
00084   */
00085 typedef struct
00086 {
00087   uint32_t CTPulseHighLength;       /*!< Charge-transfer high pulse length
00088                                          This parameter can be a value of @ref TSC_CTPulseHL_Config  */
00089   uint32_t CTPulseLowLength;        /*!< Charge-transfer low pulse length
00090                                          This parameter can be a value of @ref TSC_CTPulseLL_Config  */
00091   uint32_t SpreadSpectrum;          /*!< Spread spectrum activation
00092                                          This parameter can be a value of @ref TSC_CTPulseLL_Config  */
00093   uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
00094                                          This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
00095   uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
00096                                          This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
00097   uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
00098                                          This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
00099   uint32_t MaxCountValue;           /*!< Max count value
00100                                          This parameter can be a value of @ref TSC_MaxCount_Value  */
00101   uint32_t IODefaultMode;           /*!< IO default mode
00102                                          This parameter can be a value of @ref TSC_IO_Default_Mode  */
00103   uint32_t SynchroPinPolarity;      /*!< Synchro pin polarity
00104                                          This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
00105   uint32_t AcquisitionMode;         /*!< Acquisition mode
00106                                          This parameter can be a value of @ref TSC_Acquisition_Mode  */
00107   uint32_t MaxCountInterrupt;       /*!< Max count interrupt activation
00108                                          This parameter can be set to ENABLE or DISABLE. */
00109   uint32_t ChannelIOs;              /*!< Channel IOs mask */
00110   uint32_t ShieldIOs;               /*!< Shield IOs mask */
00111   uint32_t SamplingIOs;             /*!< Sampling IOs mask */
00112 } TSC_InitTypeDef;
00113
00114 /**
00115   * @brief TSC IOs configuration structure definition
00116   */
00117 typedef struct
00118 {
00119   uint32_t ChannelIOs;  /*!< Channel IOs mask */
00120   uint32_t ShieldIOs;   /*!< Shield IOs mask */
00121   uint32_t SamplingIOs; /*!< Sampling IOs mask */
00122 } TSC_IOConfigTypeDef;
00123
00124 /**
00125   * @brief  TSC handle Structure definition
00126   */
00127 typedef struct
00128 {
00129   TSC_TypeDef               *Instance; /*!< Register base address */
00130   TSC_InitTypeDef           Init;      /*!< Initialization parameters */
00131   __IO HAL_TSC_StateTypeDef State;     /*!< Peripheral state */
00132   HAL_LockTypeDef           Lock;      /*!< Lock feature */
00133 } TSC_HandleTypeDef;
00134
00135 /**
00136   * @}
00137   */
00138
00139 /* Exported constants --------------------------------------------------------*/
00140 /** @defgroup TSC_Exported_Constants TSC Exported Constants
00141   * @{
00142   */
00143
00144 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length
00145   * @{
00146   */
00147 #define TSC_CTPH_1CYCLE   ((uint32_t)((uint32_t) 0 << 28))
00148 #define TSC_CTPH_2CYCLES  ((uint32_t)((uint32_t) 1 << 28))
00149 #define TSC_CTPH_3CYCLES  ((uint32_t)((uint32_t) 2 << 28))
00150 #define TSC_CTPH_4CYCLES  ((uint32_t)((uint32_t) 3 << 28))
00151 #define TSC_CTPH_5CYCLES  ((uint32_t)((uint32_t) 4 << 28))
00152 #define TSC_CTPH_6CYCLES  ((uint32_t)((uint32_t) 5 << 28))
00153 #define TSC_CTPH_7CYCLES  ((uint32_t)((uint32_t) 6 << 28))
00154 #define TSC_CTPH_8CYCLES  ((uint32_t)((uint32_t) 7 << 28))
00155 #define TSC_CTPH_9CYCLES  ((uint32_t)((uint32_t) 8 << 28))
00156 #define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
00157 #define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
00158 #define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
00159 #define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
00160 #define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
00161 #define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
00162 #define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
00168   * @{
00169   */
00170 #define TSC_CTPL_1CYCLE   ((uint32_t)((uint32_t) 0 << 24))
00171 #define TSC_CTPL_2CYCLES  ((uint32_t)((uint32_t) 1 << 24))
00172 #define TSC_CTPL_3CYCLES  ((uint32_t)((uint32_t) 2 << 24))
00173 #define TSC_CTPL_4CYCLES  ((uint32_t)((uint32_t) 3 << 24))
00174 #define TSC_CTPL_5CYCLES  ((uint32_t)((uint32_t) 4 << 24))
00175 #define TSC_CTPL_6CYCLES  ((uint32_t)((uint32_t) 5 << 24))
00176 #define TSC_CTPL_7CYCLES  ((uint32_t)((uint32_t) 6 << 24))
00177 #define TSC_CTPL_8CYCLES  ((uint32_t)((uint32_t) 7 << 24))
00178 #define TSC_CTPL_9CYCLES  ((uint32_t)((uint32_t) 8 << 24))
00179 #define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
00180 #define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
00181 #define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
00182 #define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
00183 #define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
00184 #define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
00185 #define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
00191   * @{
00192   */
00193 #define TSC_SS_PRESC_DIV1 ((uint32_t)0)
00194 #define TSC_SS_PRESC_DIV2  (TSC_CR_SSPSC)
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
00200   * @{
00201   */
00202 #define TSC_PG_PRESC_DIV1   ((uint32_t)(0 << 12))
00203 #define TSC_PG_PRESC_DIV2   ((uint32_t)(1 << 12))
00204 #define TSC_PG_PRESC_DIV4   ((uint32_t)(2 << 12))
00205 #define TSC_PG_PRESC_DIV8   ((uint32_t)(3 << 12))
00206 #define TSC_PG_PRESC_DIV16  ((uint32_t)(4 << 12))
00207 #define TSC_PG_PRESC_DIV32  ((uint32_t)(5 << 12))
00208 #define TSC_PG_PRESC_DIV64  ((uint32_t)(6 << 12))
00209 #define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup TSC_MaxCount_Value Max Count Value
00215   * @{
00216   */
00217 #define TSC_MCV_255   ((uint32_t)(0 << 5))
00218 #define TSC_MCV_511   ((uint32_t)(1 << 5))
00219 #define TSC_MCV_1023  ((uint32_t)(2 << 5))
00220 #define TSC_MCV_2047  ((uint32_t)(3 << 5))
00221 #define TSC_MCV_4095  ((uint32_t)(4 << 5))
00222 #define TSC_MCV_8191  ((uint32_t)(5 << 5))
00223 #define TSC_MCV_16383 ((uint32_t)(6 << 5))
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup TSC_IO_Default_Mode IO Default Mode
00229   * @{
00230   */
00231 #define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
00232 #define TSC_IODEF_IN_FLOAT   (TSC_CR_IODEF)
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
00238   * @{
00239   */
00240 #define TSC_SYNC_POLARITY_FALLING  ((uint32_t)0)
00241 #define TSC_SYNC_POLARITY_RISING   (TSC_CR_SYNCPOL)
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup TSC_Acquisition_Mode Acquisition Mode
00247   * @{
00248   */
00249 #define TSC_ACQ_MODE_NORMAL  ((uint32_t)0)
00250 #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup TSC_IO_Mode IO Mode
00256   * @{
00257   */
00258 #define TSC_IOMODE_UNUSED   ((uint32_t)0)
00259 #define TSC_IOMODE_CHANNEL  ((uint32_t)1)
00260 #define TSC_IOMODE_SHIELD   ((uint32_t)2)
00261 #define TSC_IOMODE_SAMPLING ((uint32_t)3)
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup TSC_interrupts_definition Interrupts definition
00267   * @{
00268   */
00269 #define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
00270 #define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup TSC_flags_definition Flags definition
00276   * @{
00277   */
00278 #define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
00279 #define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup TSC_Group_definition Group definition
00285   * @{
00286   */
00287 #define TSC_NB_OF_GROUPS (8)
00288
00289 #define TSC_GROUP1 ((uint32_t)0x00000001)
00290 #define TSC_GROUP2 ((uint32_t)0x00000002)
00291 #define TSC_GROUP3 ((uint32_t)0x00000004)
00292 #define TSC_GROUP4 ((uint32_t)0x00000008)
00293 #define TSC_GROUP5 ((uint32_t)0x00000010)
00294 #define TSC_GROUP6 ((uint32_t)0x00000020)
00295 #define TSC_GROUP7 ((uint32_t)0x00000040)
00296 #define TSC_GROUP8 ((uint32_t)0x00000080)
00297 #define TSC_ALL_GROUPS ((uint32_t)0x000000FF)
00298
00299 #define TSC_GROUP1_IDX ((uint32_t)0)
00300 #define TSC_GROUP2_IDX ((uint32_t)1)
00301 #define TSC_GROUP3_IDX ((uint32_t)2)
00302 #define TSC_GROUP4_IDX ((uint32_t)3)
00303 #define TSC_GROUP5_IDX ((uint32_t)4)
00304 #define TSC_GROUP6_IDX ((uint32_t)5)
00305 #define TSC_GROUP7_IDX ((uint32_t)6)
00306 #define TSC_GROUP8_IDX ((uint32_t)7)
00307
00308 #define TSC_GROUP1_IO1 ((uint32_t)0x00000001)
00309 #define TSC_GROUP1_IO2 ((uint32_t)0x00000002)
00310 #define TSC_GROUP1_IO3 ((uint32_t)0x00000004)
00311 #define TSC_GROUP1_IO4 ((uint32_t)0x00000008)
00312 #define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
00313
00314 #define TSC_GROUP2_IO1 ((uint32_t)0x00000010)
00315 #define TSC_GROUP2_IO2 ((uint32_t)0x00000020)
00316 #define TSC_GROUP2_IO3 ((uint32_t)0x00000040)
00317 #define TSC_GROUP2_IO4 ((uint32_t)0x00000080)
00318 #define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
00319
00320 #define TSC_GROUP3_IO1 ((uint32_t)0x00000100)
00321 #define TSC_GROUP3_IO2 ((uint32_t)0x00000200)
00322 #define TSC_GROUP3_IO3 ((uint32_t)0x00000400)
00323 #define TSC_GROUP3_IO4 ((uint32_t)0x00000800)
00324 #define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
00325
00326 #define TSC_GROUP4_IO1 ((uint32_t)0x00001000)
00327 #define TSC_GROUP4_IO2 ((uint32_t)0x00002000)
00328 #define TSC_GROUP4_IO3 ((uint32_t)0x00004000)
00329 #define TSC_GROUP4_IO4 ((uint32_t)0x00008000)
00330 #define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
00331
00332 #define TSC_GROUP5_IO1 ((uint32_t)0x00010000)
00333 #define TSC_GROUP5_IO2 ((uint32_t)0x00020000)
00334 #define TSC_GROUP5_IO3 ((uint32_t)0x00040000)
00335 #define TSC_GROUP5_IO4 ((uint32_t)0x00080000)
00336 #define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
00337
00338 #define TSC_GROUP6_IO1 ((uint32_t)0x00100000)
00339 #define TSC_GROUP6_IO2 ((uint32_t)0x00200000)
00340 #define TSC_GROUP6_IO3 ((uint32_t)0x00400000)
00341 #define TSC_GROUP6_IO4 ((uint32_t)0x00800000)
00342 #define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
00343
00344 #define TSC_GROUP7_IO1 ((uint32_t)0x01000000)
00345 #define TSC_GROUP7_IO2 ((uint32_t)0x02000000)
00346 #define TSC_GROUP7_IO3 ((uint32_t)0x04000000)
00347 #define TSC_GROUP7_IO4 ((uint32_t)0x08000000)
00348 #define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
00349
00350 #define TSC_GROUP8_IO1 ((uint32_t)0x10000000)
00351 #define TSC_GROUP8_IO2 ((uint32_t)0x20000000)
00352 #define TSC_GROUP8_IO3 ((uint32_t)0x40000000)
00353 #define TSC_GROUP8_IO4 ((uint32_t)0x80000000)
00354 #define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)
00355
00356 #define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 /* Exported macros -----------------------------------------------------------*/
00366
00367 /** @defgroup TSC_Exported_Macros TSC Exported Macros
00368   * @{
00369   */
00370
00371 /** @brief Reset TSC handle state.
00372   * @param  __HANDLE__: TSC handle
00373   * @retval None
00374   */
00375 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
00376
00377 /**
00378   * @brief Enable the TSC peripheral.
00379   * @param  __HANDLE__: TSC handle
00380   * @retval None
00381   */
00382 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
00383
00384 /**
00385   * @brief Disable the TSC peripheral.
00386   * @param  __HANDLE__: TSC handle
00387   * @retval None
00388   */
00389 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
00390
00391 /**
00392   * @brief Start acquisition.
00393   * @param  __HANDLE__: TSC handle
00394   * @retval None
00395   */
00396 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
00397
00398 /**
00399   * @brief Stop acquisition.
00400   * @param  __HANDLE__: TSC handle
00401   * @retval None
00402   */
00403 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
00404
00405 /**
00406   * @brief Set IO default mode to output push-pull low.
00407   * @param  __HANDLE__: TSC handle
00408   * @retval None
00409   */
00410 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
00411
00412 /**
00413   * @brief Set IO default mode to input floating.
00414   * @param  __HANDLE__: TSC handle
00415   * @retval None
00416   */
00417 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
00418
00419 /**
00420   * @brief Set synchronization polarity to falling edge.
00421   * @param  __HANDLE__: TSC handle
00422   * @retval None
00423   */
00424 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
00425
00426 /**
00427   * @brief Set synchronization polarity to rising edge and high level.
00428   * @param  __HANDLE__: TSC handle
00429   * @retval None
00430   */
00431 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
00432
00433 /**
00434   * @brief Enable TSC interrupt.
00435   * @param  __HANDLE__: TSC handle
00436   * @param  __INTERRUPT__: TSC interrupt
00437   * @retval None
00438   */
00439 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00440
00441 /**
00442   * @brief Disable TSC interrupt.
00443   * @param  __HANDLE__: TSC handle
00444   * @param  __INTERRUPT__: TSC interrupt
00445   * @retval None
00446   */
00447 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
00448
00449 /** @brief Check whether the specified TSC interrupt source is enabled or not.
00450   * @param  __HANDLE__: TSC Handle
00451   * @param  __INTERRUPT__: TSC interrupt
00452   * @retval SET or RESET
00453   */
00454 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00455
00456 /**
00457   * @brief Check whether the specified TSC flag is set or not.
00458   * @param  __HANDLE__: TSC handle
00459   * @param  __FLAG__: TSC flag
00460   * @retval SET or RESET
00461   */
00462 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00463
00464 /**
00465   * @brief Clear the TSC's pending flag.
00466   * @param  __HANDLE__: TSC handle
00467   * @param  __FLAG__: TSC flag
00468   * @retval None
00469   */
00470 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00471
00472 /**
00473   * @brief Enable schmitt trigger hysteresis on a group of IOs.
00474   * @param  __HANDLE__: TSC handle
00475   * @param  __GX_IOY_MASK__: IOs mask
00476   * @retval None
00477   */
00478 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
00479
00480 /**
00481   * @brief Disable schmitt trigger hysteresis on a group of IOs.
00482   * @param  __HANDLE__: TSC handle
00483   * @param  __GX_IOY_MASK__: IOs mask
00484   * @retval None
00485   */
00486 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
00487
00488 /**
00489   * @brief Open analog switch on a group of IOs.
00490   * @param  __HANDLE__: TSC handle
00491   * @param  __GX_IOY_MASK__: IOs mask
00492   * @retval None
00493   */
00494 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
00495
00496 /**
00497   * @brief Close analog switch on a group of IOs.
00498   * @param  __HANDLE__: TSC handle
00499   * @param  __GX_IOY_MASK__: IOs mask
00500   * @retval None
00501   */
00502 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
00503
00504 /**
00505   * @brief Enable a group of IOs in channel mode.
00506   * @param  __HANDLE__: TSC handle
00507   * @param  __GX_IOY_MASK__: IOs mask
00508   * @retval None
00509   */
00510 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
00511
00512 /**
00513   * @brief Disable a group of channel IOs.
00514   * @param  __HANDLE__: TSC handle
00515   * @param  __GX_IOY_MASK__: IOs mask
00516   * @retval None
00517   */
00518 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
00519
00520 /**
00521   * @brief Enable a group of IOs in sampling mode.
00522   * @param  __HANDLE__: TSC handle
00523   * @param  __GX_IOY_MASK__: IOs mask
00524   * @retval None
00525   */
00526 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
00527
00528 /**
00529   * @brief Disable a group of sampling IOs.
00530   * @param  __HANDLE__: TSC handle
00531   * @param  __GX_IOY_MASK__: IOs mask
00532   * @retval None
00533   */
00534 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
00535
00536 /**
00537   * @brief Enable acquisition groups.
00538   * @param  __HANDLE__: TSC handle
00539   * @param  __GX_MASK__: Groups mask
00540   * @retval None
00541   */
00542 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
00543
00544 /**
00545   * @brief Disable acquisition groups.
00546   * @param  __HANDLE__: TSC handle
00547   * @param  __GX_MASK__: Groups mask
00548   * @retval None
00549   */
00550 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
00551
00552 /** @brief Gets acquisition group status.
00553   * @param  __HANDLE__: TSC Handle
00554   * @param  __GX_INDEX__: Group index
00555   * @retval SET or RESET
00556   */
00557 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
00558 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
00559
00560 /**
00561   * @}
00562   */
00563
00564 /* Private macros ------------------------------------------------------------*/
00565
00566 /** @defgroup TSC_Private_Macros TSC Private Macros
00567   * @{
00568   */
00569
00570 #define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
00571                           ((VAL) == TSC_CTPH_2CYCLES) || \
00572                           ((VAL) == TSC_CTPH_3CYCLES) || \
00573                           ((VAL) == TSC_CTPH_4CYCLES) || \
00574                           ((VAL) == TSC_CTPH_5CYCLES) || \
00575                           ((VAL) == TSC_CTPH_6CYCLES) || \
00576                           ((VAL) == TSC_CTPH_7CYCLES) || \
00577                           ((VAL) == TSC_CTPH_8CYCLES) || \
00578                           ((VAL) == TSC_CTPH_9CYCLES) || \
00579                           ((VAL) == TSC_CTPH_10CYCLES) || \
00580                           ((VAL) == TSC_CTPH_11CYCLES) || \
00581                           ((VAL) == TSC_CTPH_12CYCLES) || \
00582                           ((VAL) == TSC_CTPH_13CYCLES) || \
00583                           ((VAL) == TSC_CTPH_14CYCLES) || \
00584                           ((VAL) == TSC_CTPH_15CYCLES) || \
00585                           ((VAL) == TSC_CTPH_16CYCLES))
00586
00587 #define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
00588                           ((VAL) == TSC_CTPL_2CYCLES) || \
00589                           ((VAL) == TSC_CTPL_3CYCLES) || \
00590                           ((VAL) == TSC_CTPL_4CYCLES) || \
00591                           ((VAL) == TSC_CTPL_5CYCLES) || \
00592                           ((VAL) == TSC_CTPL_6CYCLES) || \
00593                           ((VAL) == TSC_CTPL_7CYCLES) || \
00594                           ((VAL) == TSC_CTPL_8CYCLES) || \
00595                           ((VAL) == TSC_CTPL_9CYCLES) || \
00596                           ((VAL) == TSC_CTPL_10CYCLES) || \
00597                           ((VAL) == TSC_CTPL_11CYCLES) || \
00598                           ((VAL) == TSC_CTPL_12CYCLES) || \
00599                           ((VAL) == TSC_CTPL_13CYCLES) || \
00600                           ((VAL) == TSC_CTPL_14CYCLES) || \
00601                           ((VAL) == TSC_CTPL_15CYCLES) || \
00602                           ((VAL) == TSC_CTPL_16CYCLES))
00603
00604 #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
00605
00606 #define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
00607
00608 #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
00609
00610 #define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
00611                               ((VAL) == TSC_PG_PRESC_DIV2) || \
00612                               ((VAL) == TSC_PG_PRESC_DIV4) || \
00613                               ((VAL) == TSC_PG_PRESC_DIV8) || \
00614                               ((VAL) == TSC_PG_PRESC_DIV16) || \
00615                               ((VAL) == TSC_PG_PRESC_DIV32) || \
00616                               ((VAL) == TSC_PG_PRESC_DIV64) || \
00617                               ((VAL) == TSC_PG_PRESC_DIV128))
00618
00619 #define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
00620                          ((VAL) == TSC_MCV_511) || \
00621                          ((VAL) == TSC_MCV_1023) || \
00622                          ((VAL) == TSC_MCV_2047) || \
00623                          ((VAL) == TSC_MCV_4095) || \
00624                          ((VAL) == TSC_MCV_8191) || \
00625                          ((VAL) == TSC_MCV_16383))
00626
00627 #define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
00628
00629 #define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
00630
00631 #define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
00632
00633 #define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
00634                             ((VAL) == TSC_IOMODE_CHANNEL) || \
00635                             ((VAL) == TSC_IOMODE_SHIELD) || \
00636                             ((VAL) == TSC_IOMODE_SAMPLING))
00637
00638 #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
00639
00640 #define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
00641
00642 /**
00643   * @}
00644   */
00645
00646 /* Exported functions --------------------------------------------------------*/
00647 /** @addtogroup TSC_Exported_Functions
00648   * @{
00649   */
00650
00651 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
00652   * @{
00653   */
00654 /* Initialization and de-initialization functions *****************************/
00655 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
00656 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
00657 void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
00658 void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
00659 /**
00660   * @}
00661   */
00662
00663 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
00664   * @{
00665   */
00666 /* IO operation functions *****************************************************/
00667 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
00668 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
00669 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
00670 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
00671 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
00672 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
00673 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
00674 /**
00675   * @}
00676   */
00677
00678 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
00679   * @{
00680   */
00681 /* Peripheral Control functions ***********************************************/
00682 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
00683 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
00684 /**
00685   * @}
00686   */
00687
00688 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
00689   * @{
00690   */
00691 /* Peripheral State and Error functions ***************************************/
00692 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
00693 /**
00694   * @}
00695   */
00696
00697 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00698  * @{
00699  */
00700 /******* TSC IRQHandler and Callbacks used in Interrupt mode */
00701 void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
00702 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
00703 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
00704 /**
00705   * @}
00706   */
00707
00708 /**
00709   * @}
00710   */
00711
00712 /**
00713   * @}
00714   */
00715
00716 /**
00717   * @}
00718   */
00719
00720 #ifdef __cplusplus
00721 }
00722 #endif
00723
00724 #endif /* __STM32L4xx_HAL_TSC_H */
00725
00726 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_uart.c Source File

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stm32l4xx_hal_uart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_uart.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   UART HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *
00014   *
00015   @verbatim
00016  ===============================================================================
00017                         ##### How to use this driver #####
00018  ===============================================================================
00019   [..]
00020     The UART HAL driver can be used as follows:
00021
00022     (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
00023     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
00024         (++) Enable the USARTx interface clock.
00025         (++) UART pins configuration:
00026             (+++) Enable the clock for the UART GPIOs.
00027             (+++) Configure these UART pins as alternate function pull-up.
00028         (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
00029              and HAL_UART_Receive_IT() APIs):
00030             (+++) Configure the USARTx interrupt priority.
00031             (+++) Enable the NVIC USART IRQ handle.
00032         (++) UART interrupts handling:
00033               -@@-  The specific UART interrupts (Transmission complete interrupt,
00034                 RXNE interrupt and Error Interrupts) are managed using the macros
00035                 __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
00036         (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
00037              and HAL_UART_Receive_DMA() APIs):
00038             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00039             (+++) Enable the DMAx interface clock.
00040             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00041             (+++) Configure the DMA Tx/Rx channel.
00042             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
00043             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00044
00045     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00046         flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
00047
00048     (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
00049         in the huart handle AdvancedInit structure.
00050
00051     (#) For the UART asynchronous mode, initialize the UART registers by calling
00052         the HAL_UART_Init() API.
00053
00054     (#) For the UART Half duplex mode, initialize the UART registers by calling
00055         the HAL_HalfDuplex_Init() API.
00056
00057     (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
00058         by calling the HAL_LIN_Init() API.
00059
00060     (#) For the UART Multiprocessor mode, initialize the UART registers
00061         by calling the HAL_MultiProcessor_Init() API.
00062
00063     (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
00064         by calling the HAL_RS485Ex_Init() API.
00065
00066     [..]
00067     (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
00068         also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
00069         calling the customized HAL_UART_MspInit() API.
00070
00071   @endverbatim
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00076   *
00077   * Redistribution and use in source and binary forms, with or without modification,
00078   * are permitted provided that the following conditions are met:
00079   *   1. Redistributions of source code must retain the above copyright notice,
00080   *      this list of conditions and the following disclaimer.
00081   *   2. Redistributions in binary form must reproduce the above copyright notice,
00082   *      this list of conditions and the following disclaimer in the documentation
00083   *      and/or other materials provided with the distribution.
00084   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00085   *      may be used to endorse or promote products derived from this software
00086   *      without specific prior written permission.
00087   *
00088   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00089   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00090   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00091   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00092   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00093   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00094   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00095   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00096   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00097   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00098   *
00099   ******************************************************************************
00100   */
00101
00102 /* Includes ------------------------------------------------------------------*/
00103 #include "stm32l4xx_hal.h"
00104
00105 /** @addtogroup STM32L4xx_HAL_Driver
00106   * @{
00107   */
00108
00109 /** @defgroup UART UART
00110   * @brief HAL UART module driver
00111   * @{
00112   */
00113
00114 #ifdef HAL_UART_MODULE_ENABLED
00115
00116 /* Private typedef -----------------------------------------------------------*/
00117 /* Private define ------------------------------------------------------------*/
00118 /** @defgroup UART_Private_Constants UART Private Constants
00119   * @{
00120   */
00121 #define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00122                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
00123
00124 #define UART_LPUART_BRR_MIN           ((uint32_t)0x00000300)  /* LPUART BRR minimum authorized value */
00125 #define UART_LPUART_BRR_MAX           ((uint32_t)0x000FFFFF)  /* LPUART BRR maximum authorized value */
00126 /**
00127   * @}
00128   */
00129
00130 /* Private macros ------------------------------------------------------------*/
00131 /* Private variables ---------------------------------------------------------*/
00132 /* Private function prototypes -----------------------------------------------*/
00133 /** @addtogroup UART_Private_Functions
00134   * @{
00135   */
00136 static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
00137 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
00138 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00139 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00140 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00141 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00142 static void UART_DMAError(DMA_HandleTypeDef *hdma);
00143 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00144 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
00145 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
00146 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
00147 /**
00148   * @}
00149   */
00150
00151 /* Exported functions --------------------------------------------------------*/
00152
00153 /** @defgroup UART_Exported_Functions UART Exported Functions
00154   * @{
00155   */
00156
00157 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
00158   *  @brief    Initialization and Configuration functions
00159   *
00160 @verbatim
00161 ===============================================================================
00162             ##### Initialization and Configuration functions #####
00163  ===============================================================================
00164     [..]
00165     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00166     in asynchronous mode.
00167       (+) For the asynchronous mode the parameters below can be configured:
00168         (++) Baud Rate
00169         (++) Word Length
00170         (++) Stop Bit
00171         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00172              in the data register is transmitted but is changed by the parity bit.
00173         (++) Hardware flow control
00174         (++) Receiver/transmitter modes
00175         (++) Over Sampling Method
00176         (++) One-Bit Sampling Method
00177       (+) For the asynchronous mode, the following advanced features can be configured as well:
00178         (++) TX and/or RX pin level inversion
00179         (++) data logical level inversion
00180         (++) RX and TX pins swap
00181         (++) RX overrun detection disabling
00182         (++) DMA disabling on RX error
00183         (++) MSB first on communication line
00184         (++) auto Baud rate detection
00185     [..]
00186     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
00187     follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
00188     and UART multiprocessor mode configuration procedures (details for the procedures
00189     are available in reference manual).
00190
00191 @endverbatim
00192
00193   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00194   8-bit or 9-bit), the possible UART formats are listed in the
00195   following table.
00196
00197   Table 1. UART frame format.
00198     +-----------------------------------------------------------------------+
00199     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00200     |---------|---------|-----------|---------------------------------------|
00201     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00202     |---------|---------|-----------|---------------------------------------|
00203     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00204     |---------|---------|-----------|---------------------------------------|
00205     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00206     |---------|---------|-----------|---------------------------------------|
00207     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00208     |---------|---------|-----------|---------------------------------------|
00209     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00210     |---------|---------|-----------|---------------------------------------|
00211     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00212     +-----------------------------------------------------------------------+
00213
00214   * @{
00215   */
00216
00217 /**
00218   * @brief Initialize the UART mode according to the specified
00219   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00220   * @param huart: UART handle.
00221   * @retval HAL status
00222   */
00223 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
00224 {
00225   /* Check the UART handle allocation */
00226   if(huart == NULL)
00227   {
00228     return HAL_ERROR;
00229   }
00230
00231   if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
00232   {
00233     /* Check the parameters */
00234     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
00235   }
00236   else
00237   {
00238     /* Check the parameters */
00239     assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00240   }
00241
00242   if(huart->gState == HAL_UART_STATE_RESET)
00243   {
00244     /* Allocate lock resource and initialize it */
00245     huart->Lock = HAL_UNLOCKED;
00246
00247     /* Init the low level hardware : GPIO, CLOCK */
00248     HAL_UART_MspInit(huart);
00249   }
00250
00251   huart->gState = HAL_UART_STATE_BUSY;
00252
00253   /* Disable the Peripheral */
00254   __HAL_UART_DISABLE(huart);
00255
00256   /* Set the UART Communication parameters */
00257   if (UART_SetConfig(huart) == HAL_ERROR)
00258   {
00259     return HAL_ERROR;
00260   }
00261
00262   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00263   {
00264     UART_AdvFeatureConfig(huart);
00265   }
00266
00267   /* In asynchronous mode, the following bits must be kept cleared:
00268   - LINEN and CLKEN bits in the USART_CR2 register,
00269   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
00270   huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
00271   huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00272
00273   /* Enable the Peripheral */
00274   __HAL_UART_ENABLE(huart);
00275
00276   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00277   return (UART_CheckIdleState(huart));
00278 }
00279
00280 /**
00281   * @brief Initialize the half-duplex mode according to the specified
00282   *        parameters in the UART_InitTypeDef and creates the associated handle.
00283   * @param huart: UART handle.
00284   * @retval HAL status
00285   */
00286 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
00287 {
00288   /* Check the UART handle allocation */
00289   if(huart == NULL)
00290   {
00291     return HAL_ERROR;
00292   }
00293
00294   /* Check UART instance */
00295   assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
00296
00297   if(huart->gState == HAL_UART_STATE_RESET)
00298   {
00299     /* Allocate lock resource and initialize it */
00300     huart->Lock = HAL_UNLOCKED;
00301
00302     /* Init the low level hardware : GPIO, CLOCK */
00303     HAL_UART_MspInit(huart);
00304   }
00305
00306   huart->gState = HAL_UART_STATE_BUSY;
00307
00308   /* Disable the Peripheral */
00309   __HAL_UART_DISABLE(huart);
00310
00311   /* Set the UART Communication parameters */
00312   if (UART_SetConfig(huart) == HAL_ERROR)
00313   {
00314     return HAL_ERROR;
00315   }
00316
00317   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00318   {
00319     UART_AdvFeatureConfig(huart);
00320   }
00321
00322   /* In half-duplex mode, the following bits must be kept cleared:
00323   - LINEN and CLKEN bits in the USART_CR2 register,
00324   - SCEN and IREN bits in the USART_CR3 register.*/
00325   huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
00326   huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
00327
00328   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00329   huart->Instance->CR3 |= USART_CR3_HDSEL;
00330
00331   /* Enable the Peripheral */
00332   __HAL_UART_ENABLE(huart);
00333
00334   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00335   return (UART_CheckIdleState(huart));
00336 }
00337
00338
00339 /**
00340   * @brief Initialize the LIN mode according to the specified
00341   *        parameters in the UART_InitTypeDef and creates the associated handle .
00342   * @param huart: UART handle.
00343   * @param BreakDetectLength: specifies the LIN break detection length.
00344   *        This parameter can be one of the following values:
00345   *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
00346   *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
00347   * @retval HAL status
00348   */
00349 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
00350 {
00351   /* Check the UART handle allocation */
00352   if(huart == NULL)
00353   {
00354     return HAL_ERROR;
00355   }
00356
00357   /* Check the LIN UART instance */
00358   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
00359   /* Check the Break detection length parameter */
00360   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
00361
00362   /* LIN mode limited to 16-bit oversampling only */
00363   if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
00364   {
00365     return HAL_ERROR;
00366   }
00367   /* LIN mode limited to 8-bit data length */
00368   if(huart->Init.WordLength != UART_WORDLENGTH_8B)
00369   {
00370     return HAL_ERROR;
00371   }
00372
00373   if(huart->gState == HAL_UART_STATE_RESET)
00374   {
00375     /* Allocate lock resource and initialize it */
00376     huart->Lock = HAL_UNLOCKED;
00377
00378     /* Init the low level hardware : GPIO, CLOCK */
00379     HAL_UART_MspInit(huart);
00380   }
00381
00382   huart->gState = HAL_UART_STATE_BUSY;
00383
00384   /* Disable the Peripheral */
00385   __HAL_UART_DISABLE(huart);
00386
00387   /* Set the UART Communication parameters */
00388   if (UART_SetConfig(huart) == HAL_ERROR)
00389   {
00390     return HAL_ERROR;
00391   }
00392
00393   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00394   {
00395     UART_AdvFeatureConfig(huart);
00396   }
00397
00398   /* In LIN mode, the following bits must be kept cleared:
00399   - LINEN and CLKEN bits in the USART_CR2 register,
00400   - SCEN and IREN bits in the USART_CR3 register.*/
00401   huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
00402   huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
00403
00404   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00405   huart->Instance->CR2 |= USART_CR2_LINEN;
00406
00407   /* Set the USART LIN Break detection length. */
00408   MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
00409
00410   /* Enable the Peripheral */
00411   __HAL_UART_ENABLE(huart);
00412
00413   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00414   return (UART_CheckIdleState(huart));
00415 }
00416
00417
00418 /**
00419   * @brief Initialize the multiprocessor mode according to the specified
00420   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00421   * @param huart: UART handle.
00422   * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
00423   * @param WakeUpMethod: specifies the UART wakeup method.
00424   *        This parameter can be one of the following values:
00425   *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
00426   *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
00427   * @note  If the user resorts to idle line detection wake up, the Address parameter
00428   *        is useless and ignored by the initialization function.
00429   * @note  If the user resorts to address mark wake up, the address length detection
00430   *        is configured by default to 4 bits only. For the UART to be able to
00431   *        manage 6-, 7- or 8-bit long addresses detection, the API
00432   *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
00433   *        HAL_MultiProcessor_Init().
00434   * @retval HAL status
00435   */
00436 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
00437 {
00438   /* Check the UART handle allocation */
00439   if(huart == NULL)
00440   {
00441     return HAL_ERROR;
00442   }
00443
00444   /* Check the wake up method parameter */
00445   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
00446
00447   if(huart->gState == HAL_UART_STATE_RESET)
00448   {
00449     /* Allocate lock resource and initialize it */
00450     huart->Lock = HAL_UNLOCKED;
00451
00452     /* Init the low level hardware : GPIO, CLOCK */
00453     HAL_UART_MspInit(huart);
00454   }
00455
00456   huart->gState = HAL_UART_STATE_BUSY;
00457
00458   /* Disable the Peripheral */
00459   __HAL_UART_DISABLE(huart);
00460
00461   /* Set the UART Communication parameters */
00462   if (UART_SetConfig(huart) == HAL_ERROR)
00463   {
00464     return HAL_ERROR;
00465   }
00466
00467   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00468   {
00469     UART_AdvFeatureConfig(huart);
00470   }
00471
00472   /* In multiprocessor mode, the following bits must be kept cleared:
00473   - LINEN and CLKEN bits in the USART_CR2 register,
00474   - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
00475   huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
00476   huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00477
00478   if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
00479   {
00480     /* If address mark wake up method is chosen, set the USART address node */
00481     MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
00482   }
00483
00484   /* Set the wake up method by setting the WAKE bit in the CR1 register */
00485   MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
00486
00487   /* Enable the Peripheral */
00488   __HAL_UART_ENABLE(huart);
00489
00490   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00491   return (UART_CheckIdleState(huart));
00492 }
00493
00494
00495 /**
00496   * @brief DeInitialize the UART peripheral.
00497   * @param huart: UART handle.
00498   * @retval HAL status
00499   */
00500 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
00501 {
00502   /* Check the UART handle allocation */
00503   if(huart == NULL)
00504   {
00505     return HAL_ERROR;
00506   }
00507
00508   /* Check the parameters */
00509   assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00510
00511   huart->gState = HAL_UART_STATE_BUSY;
00512
00513   /* Disable the Peripheral */
00514   __HAL_UART_DISABLE(huart);
00515
00516   huart->Instance->CR1 = 0x0;
00517   huart->Instance->CR2 = 0x0;
00518   huart->Instance->CR3 = 0x0;
00519
00520   /* DeInit the low level hardware */
00521   HAL_UART_MspDeInit(huart);
00522
00523   huart->ErrorCode = HAL_UART_ERROR_NONE;
00524   huart->gState = HAL_UART_STATE_RESET;
00525   huart->RxState = HAL_UART_STATE_RESET;
00526
00527   /* Process Unlock */
00528   __HAL_UNLOCK(huart);
00529
00530   return HAL_OK;
00531 }
00532
00533 /**
00534   * @brief Initialize the UART MSP.
00535   * @param huart: UART handle.
00536   * @retval None
00537   */
00538 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
00539 {
00540   /* Prevent unused argument(s) compilation warning */
00541   UNUSED(huart);
00542
00543   /* NOTE : This function should not be modified, when the callback is needed,
00544             the HAL_UART_MspInit can be implemented in the user file
00545    */
00546 }
00547
00548 /**
00549   * @brief DeInitialize the UART MSP.
00550   * @param huart: UART handle.
00551   * @retval None
00552   */
00553 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
00554 {
00555   /* Prevent unused argument(s) compilation warning */
00556   UNUSED(huart);
00557
00558   /* NOTE : This function should not be modified, when the callback is needed,
00559             the HAL_UART_MspDeInit can be implemented in the user file
00560    */
00561 }
00562
00563 /**
00564   * @}
00565   */
00566
00567 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
00568   * @brief UART Transmit/Receive functions
00569   *
00570 @verbatim
00571  ===============================================================================
00572                       ##### IO operation functions #####
00573  ===============================================================================
00574     This subsection provides a set of functions allowing to manage the UART asynchronous
00575     and Half duplex data transfers.
00576
00577     (#) There are two mode of transfer:
00578        (+) Blocking mode: The communication is performed in polling mode.
00579             The HAL status of all data processing is returned by the same function
00580             after finishing transfer.
00581        (+) No-Blocking mode: The communication is performed using Interrupts
00582            or DMA, These API's return the HAL status.
00583            The end of the data processing will be indicated through the
00584            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
00585            using DMA mode.
00586            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
00587            will be executed respectively at the end of the transmit or Receive process
00588            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
00589
00590     (#) Blocking mode API's are :
00591         (+) HAL_UART_Transmit()
00592         (+) HAL_UART_Receive()
00593
00594     (#) Non-Blocking mode API's with Interrupt are :
00595         (+) HAL_UART_Transmit_IT()
00596         (+) HAL_UART_Receive_IT()
00597         (+) HAL_UART_IRQHandler()
00598
00599     (#) No-Blocking mode API's with DMA are :
00600         (+) HAL_UART_Transmit_DMA()
00601         (+) HAL_UART_Receive_DMA()
00602         (+) HAL_UART_DMAPause()
00603         (+) HAL_UART_DMAResume()
00604         (+) HAL_UART_DMAStop()
00605
00606     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
00607         (+) HAL_UART_TxHalfCpltCallback()
00608         (+) HAL_UART_TxCpltCallback()
00609         (+) HAL_UART_RxHalfCpltCallback()
00610         (+) HAL_UART_RxCpltCallback()
00611         (+) HAL_UART_ErrorCallback()
00612
00613     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00614         Errors are handled as follows :
00615        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00616            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00617            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00618            and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
00619        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00620            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00621            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
00622
00623     -@- In the Half duplex communication, it is forbidden to run the transmit
00624         and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
00625
00626 @endverbatim
00627   * @{
00628   */
00629
00630 /**
00631   * @brief Send an amount of data in blocking mode.
00632   * @param huart: UART handle.
00633   * @param pData: Pointer to data buffer.
00634   * @param Size: Amount of data to be sent.
00635   * @param Timeout: Timeout duration.
00636   * @retval HAL status
00637   */
00638 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00639 {
00640   uint16_t* tmp;
00641   uint32_t tickstart = 0;
00642
00643   /* Check that a Tx process is not already ongoing */
00644   if(huart->gState == HAL_UART_STATE_READY)
00645   {
00646     if((pData == NULL ) || (Size == 0))
00647     {
00648       return  HAL_ERROR;
00649     }
00650
00651     /* Process Locked */
00652     __HAL_LOCK(huart);
00653
00654     huart->ErrorCode = HAL_UART_ERROR_NONE;
00655     huart->gState = HAL_UART_STATE_BUSY_TX;
00656
00657     /* Init tickstart for timeout managment*/
00658     tickstart = HAL_GetTick();
00659
00660     huart->TxXferSize = Size;
00661     huart->TxXferCount = Size;
00662     while(huart->TxXferCount > 0)
00663     {
00664       huart->TxXferCount--;
00665       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00666       {
00667         return HAL_TIMEOUT;
00668       }
00669       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00670       {
00671         tmp = (uint16_t*) pData;
00672         huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
00673         pData += 2;
00674       }
00675       else
00676       {
00677         huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);
00678       }
00679     }
00680     if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00681     {
00682       return HAL_TIMEOUT;
00683     }
00684
00685     /* At end of Tx process, restore huart->gState to Ready */
00686     huart->gState = HAL_UART_STATE_READY;
00687
00688     /* Process Unlocked */
00689     __HAL_UNLOCK(huart);
00690
00691     return HAL_OK;
00692   }
00693   else
00694   {
00695     return HAL_BUSY;
00696   }
00697 }
00698
00699 /**
00700   * @brief Receive an amount of data in blocking mode.
00701   * @param huart: UART handle.
00702   * @param pData: pointer to data buffer.
00703   * @param Size: amount of data to be received.
00704   * @param Timeout: Timeout duration.
00705   * @retval HAL status
00706   */
00707 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00708 {
00709   uint16_t* tmp;
00710   uint16_t uhMask;
00711   uint32_t tickstart = 0;
00712
00713   /* Check that a Rx process is not already ongoing */
00714   if(huart->RxState == HAL_UART_STATE_READY)
00715   {
00716     if((pData == NULL ) || (Size == 0))
00717     {
00718       return  HAL_ERROR;
00719     }
00720
00721     /* Process Locked */
00722     __HAL_LOCK(huart);
00723
00724     huart->ErrorCode = HAL_UART_ERROR_NONE;
00725     huart->RxState = HAL_UART_STATE_BUSY_RX;
00726
00727     /* Init tickstart for timeout managment*/
00728     tickstart = HAL_GetTick();
00729
00730     huart->RxXferSize = Size;
00731     huart->RxXferCount = Size;
00732
00733     /* Computation of UART mask to apply to RDR register */
00734     UART_MASK_COMPUTATION(huart);
00735     uhMask = huart->Mask;
00736
00737     /* as long as data have to be received */
00738     while(huart->RxXferCount > 0)
00739     {
00740       huart->RxXferCount--;
00741       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00742       {
00743         return HAL_TIMEOUT;
00744       }
00745       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
00746       {
00747         tmp = (uint16_t*) pData ;
00748         *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
00749         pData +=2;
00750       }
00751       else
00752       {
00753         *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
00754       }
00755     }
00756
00757     /* At end of Rx process, restore huart->RxState to Ready */
00758     huart->RxState = HAL_UART_STATE_READY;
00759
00760     /* Process Unlocked */
00761     __HAL_UNLOCK(huart);
00762
00763     return HAL_OK;
00764   }
00765   else
00766   {
00767     return HAL_BUSY;
00768   }
00769 }
00770
00771 /**
00772   * @brief Send an amount of data in interrupt mode.
00773   * @param huart: UART handle.
00774   * @param pData: pointer to data buffer.
00775   * @param Size: amount of data to be sent.
00776   * @retval HAL status
00777   */
00778 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00779 {
00780   /* Check that a Tx process is not already ongoing */
00781   if(huart->gState == HAL_UART_STATE_READY)
00782   {
00783     if((pData == NULL ) || (Size == 0))
00784     {
00785       return HAL_ERROR;
00786     }
00787
00788     /* Process Locked */
00789     __HAL_LOCK(huart);
00790
00791     huart->pTxBuffPtr = pData;
00792     huart->TxXferSize = Size;
00793     huart->TxXferCount = Size;
00794
00795     huart->ErrorCode = HAL_UART_ERROR_NONE;
00796     huart->gState = HAL_UART_STATE_BUSY_TX;
00797
00798     /* Process Unlocked */
00799     __HAL_UNLOCK(huart);
00800
00801     /* Enable the UART Transmit Data Register Empty Interrupt */
00802     SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
00803
00804     return HAL_OK;
00805   }
00806   else
00807   {
00808     return HAL_BUSY;
00809   }
00810 }
00811
00812 /**
00813   * @brief Receive an amount of data in interrupt mode.
00814   * @param huart: UART handle.
00815   * @param pData: pointer to data buffer.
00816   * @param Size: amount of data to be received.
00817   * @retval HAL status
00818   */
00819 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00820 {
00821   /* Check that a Rx process is not already ongoing */
00822   if(huart->RxState == HAL_UART_STATE_READY)
00823   {
00824     if((pData == NULL ) || (Size == 0))
00825     {
00826       return HAL_ERROR;
00827     }
00828
00829     /* Process Locked */
00830     __HAL_LOCK(huart);
00831
00832     huart->pRxBuffPtr = pData;
00833     huart->RxXferSize = Size;
00834     huart->RxXferCount = Size;
00835
00836     /* Computation of UART mask to apply to RDR register */
00837     UART_MASK_COMPUTATION(huart);
00838
00839     huart->ErrorCode = HAL_UART_ERROR_NONE;
00840     huart->RxState = HAL_UART_STATE_BUSY_RX;
00841
00842     /* Process Unlocked */
00843     __HAL_UNLOCK(huart);
00844
00845     /* Enable the UART Parity Error Interrupt */
00846     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
00847
00848     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
00849     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
00850
00851     /* Enable the UART Data Register not empty Interrupt */
00852     SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);
00853
00854     return HAL_OK;
00855   }
00856   else
00857   {
00858     return HAL_BUSY;
00859   }
00860 }
00861
00862 /**
00863   * @brief Send an amount of data in DMA mode.
00864   * @param huart: UART handle.
00865   * @param pData: pointer to data buffer.
00866   * @param Size: amount of data to be sent.
00867   * @retval HAL status
00868   */
00869 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00870 {
00871   uint32_t *tmp;
00872
00873   /* Check that a Tx process is not already ongoing */
00874   if(huart->gState == HAL_UART_STATE_READY)
00875   {
00876     if((pData == NULL ) || (Size == 0))
00877     {
00878       return HAL_ERROR;
00879     }
00880
00881     /* Process Locked */
00882     __HAL_LOCK(huart);
00883
00884     huart->pTxBuffPtr = pData;
00885     huart->TxXferSize = Size;
00886     huart->TxXferCount = Size;
00887
00888     huart->ErrorCode = HAL_UART_ERROR_NONE;
00889     huart->gState = HAL_UART_STATE_BUSY_TX;
00890
00891     /* Set the UART DMA transfer complete callback */
00892     huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
00893
00894     /* Set the UART DMA Half transfer complete callback */
00895     huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
00896
00897     /* Set the DMA error callback */
00898     huart->hdmatx->XferErrorCallback = UART_DMAError;
00899
00900     /* Set the DMA abort callback */
00901     huart->hdmatx->XferAbortCallback = NULL;
00902
00903     /* Enable the UART transmit DMA channel */
00904     tmp = (uint32_t*)&pData;
00905     HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);
00906
00907     /* Clear the TC flag in the ICR register */
00908     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
00909
00910     /* Process Unlocked */
00911     __HAL_UNLOCK(huart);
00912
00913     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00914        in the UART CR3 register */
00915     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
00916
00917     return HAL_OK;
00918   }
00919   else
00920   {
00921     return HAL_BUSY;
00922   }
00923 }
00924
00925 /**
00926   * @brief Receive an amount of data in DMA mode.
00927   * @param huart: UART handle.
00928   * @param pData: pointer to data buffer.
00929   * @param Size: amount of data to be received.
00930   * @note   When the UART parity is enabled (PCE = 1), the received data contain
00931   *         the parity bit (MSB position).
00932   * @retval HAL status
00933   */
00934 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00935 {
00936   uint32_t *tmp;
00937
00938   /* Check that a Rx process is not already ongoing */
00939   if(huart->RxState == HAL_UART_STATE_READY)
00940   {
00941     if((pData == NULL ) || (Size == 0))
00942     {
00943       return HAL_ERROR;
00944     }
00945
00946     /* Process Locked */
00947     __HAL_LOCK(huart);
00948
00949     huart->pRxBuffPtr = pData;
00950     huart->RxXferSize = Size;
00951
00952     huart->ErrorCode = HAL_UART_ERROR_NONE;
00953     huart->RxState = HAL_UART_STATE_BUSY_RX;
00954
00955     /* Set the UART DMA transfer complete callback */
00956     huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
00957
00958     /* Set the UART DMA Half transfer complete callback */
00959     huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
00960
00961     /* Set the DMA error callback */
00962     huart->hdmarx->XferErrorCallback = UART_DMAError;
00963
00964     /* Set the DMA abort callback */
00965     huart->hdmarx->XferAbortCallback = NULL;
00966
00967     /* Enable the DMA channel */
00968     tmp = (uint32_t*)&pData;
00969     HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);
00970
00971     /* Process Unlocked */
00972     __HAL_UNLOCK(huart);
00973
00974     /* Enable the UART Parity Error Interrupt */
00975     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
00976
00977     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
00978     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
00979
00980     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00981        in the UART CR3 register */
00982     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
00983
00984     return HAL_OK;
00985   }
00986   else
00987   {
00988     return HAL_BUSY;
00989   }
00990 }
00991
00992 /**
00993   * @brief Pause the DMA Transfer.
00994   * @param huart: UART handle.
00995   * @retval HAL status
00996   */
00997 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
00998 {
00999   /* Process Locked */
01000   __HAL_LOCK(huart);
01001
01002   if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
01003       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
01004   {
01005     /* Disable the UART DMA Tx request */
01006     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01007   }
01008   if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
01009       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
01010   {
01011     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01012     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01013     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01014
01015     /* Disable the UART DMA Rx request */
01016     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01017   }
01018
01019   /* Process Unlocked */
01020   __HAL_UNLOCK(huart);
01021
01022   return HAL_OK;
01023 }
01024
01025 /**
01026   * @brief Resume the DMA Transfer.
01027   * @param huart: UART handle.
01028   * @retval HAL status
01029   */
01030 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
01031 {
01032   /* Process Locked */
01033   __HAL_LOCK(huart);
01034
01035   if(huart->gState == HAL_UART_STATE_BUSY_TX)
01036   {
01037     /* Enable the UART DMA Tx request */
01038     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01039   }
01040   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
01041   {
01042     /* Clear the Overrun flag before resuming the Rx transfer */
01043     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
01044
01045     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01046     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01047     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01048
01049     /* Enable the UART DMA Rx request */
01050     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01051   }
01052
01053   /* Process Unlocked */
01054   __HAL_UNLOCK(huart);
01055
01056   return HAL_OK;
01057 }
01058
01059 /**
01060   * @brief Stop the DMA Transfer.
01061   * @param huart: UART handle.
01062   * @retval HAL status
01063   */
01064 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
01065 {
01066   /* The Lock is not implemented on this API to allow the user application
01067      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
01068      HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
01069      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01070      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01071      the stream and the corresponding call back is executed. */
01072
01073   /* Stop UART DMA Tx request if ongoing */
01074   if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
01075       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
01076   {
01077     UART_EndTxTransfer(huart);
01078
01079     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01080
01081     /* Abort the UART DMA Tx channel */
01082     if(huart->hdmatx != NULL)
01083     {
01084       HAL_DMA_Abort(huart->hdmatx);
01085     }
01086   }
01087
01088   /* Stop UART DMA Rx request if ongoing */
01089   if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
01090       (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
01091   {
01092     UART_EndRxTransfer(huart);
01093
01094     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01095
01096     /* Abort the UART DMA Rx channel */
01097     if(huart->hdmarx != NULL)
01098     {
01099       HAL_DMA_Abort(huart->hdmarx);
01100     }
01101   }
01102
01103   return HAL_OK;
01104 }
01105
01106 /**
01107   * @brief Handle UART interrupt request.
01108   * @param huart: UART handle.
01109   * @retval None
01110   */
01111 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
01112 {
01113   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
01114   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
01115   uint32_t cr3its;
01116   uint32_t errorflags;
01117
01118   /* If no error occurs */
01119   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01120   if (errorflags == RESET)
01121   {
01122     /* UART in mode Receiver ---------------------------------------------------*/
01123     if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01124     {
01125       UART_Receive_IT(huart);
01126       return;
01127     }
01128   }
01129
01130   /* If some errors occur */
01131   cr3its = READ_REG(huart->Instance->CR3);
01132   if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
01133   {
01134     /* UART parity error interrupt occurred -------------------------------------*/
01135     if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01136     {
01137       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
01138
01139       huart->ErrorCode |= HAL_UART_ERROR_PE;
01140     }
01141
01142     /* UART frame error interrupt occurred --------------------------------------*/
01143     if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01144     {
01145       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
01146
01147       huart->ErrorCode |= HAL_UART_ERROR_FE;
01148     }
01149
01150     /* UART noise error interrupt occurred --------------------------------------*/
01151     if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01152     {
01153       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
01154
01155       huart->ErrorCode |= HAL_UART_ERROR_NE;
01156     }
01157
01158     /* UART Over-Run interrupt occurred -----------------------------------------*/
01159     if(((isrflags & USART_ISR_ORE) != RESET) &&
01160        (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
01161     {
01162       __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
01163
01164       huart->ErrorCode |= HAL_UART_ERROR_ORE;
01165     }
01166
01167     /* Call UART Error Call back function if need be --------------------------*/
01168     if(huart->ErrorCode != HAL_UART_ERROR_NONE)
01169     {
01170       /* UART in mode Receiver ---------------------------------------------------*/
01171       if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01172       {
01173         UART_Receive_IT(huart);
01174       }
01175
01176       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01177          consider error as blocking */
01178       if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
01179           (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
01180       {
01181         /* Blocking error : transfer is aborted
01182            Set the UART state ready to be able to start again the process,
01183            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01184         UART_EndRxTransfer(huart);
01185
01186         /* Disable the UART DMA Rx request if enabled */
01187         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01188         {
01189           CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01190
01191           /* Abort the UART DMA Rx channel */
01192           if(huart->hdmarx != NULL)
01193           {
01194             /* Set the UART DMA Abort callback :
01195             will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
01196             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
01197
01198             /* Abort DMA RX */
01199             if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01200             {
01201               /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
01202               huart->hdmarx->XferAbortCallback(huart->hdmarx);
01203             }
01204           }
01205           else
01206           {
01207             /* Call user error callback */
01208             HAL_UART_ErrorCallback(huart);
01209           }
01210         }
01211         else
01212         {
01213           /* Call user error callback */
01214           HAL_UART_ErrorCallback(huart);
01215         }
01216       }
01217       else
01218       {
01219         /* Non Blocking error : transfer could go on.
01220            Error is notified to user through user error callback */
01221         HAL_UART_ErrorCallback(huart);
01222         huart->ErrorCode = HAL_UART_ERROR_NONE;
01223       }
01224     }
01225     return;
01226
01227   } /* End if some error occurs */
01228
01229   /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
01230   cr3its = READ_REG(huart->Instance->CR3);
01231   if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
01232   {
01233     __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
01234     /* Set the UART state ready to be able to start again the process */
01235     huart->gState = HAL_UART_STATE_READY;
01236     huart->RxState = HAL_UART_STATE_READY;
01237     HAL_UARTEx_WakeupCallback(huart);
01238     return;
01239   }
01240
01241   /* UART in mode Transmitter ------------------------------------------------*/
01242   if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01243   {
01244     UART_Transmit_IT(huart);
01245     return;
01246   }
01247
01248   /* UART in mode Transmitter (transmission end) -----------------------------*/
01249   if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01250   {
01251     UART_EndTransmit_IT(huart);
01252     return;
01253   }
01254
01255 }
01256
01257 /**
01258   * @brief Tx Transfer completed callback.
01259   * @param huart: UART handle.
01260   * @retval None
01261   */
01262 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
01263 {
01264   /* Prevent unused argument(s) compilation warning */
01265   UNUSED(huart);
01266
01267   /* NOTE : This function should not be modified, when the callback is needed,
01268             the HAL_UART_TxCpltCallback can be implemented in the user file.
01269    */
01270 }
01271
01272 /**
01273   * @brief  Tx Half Transfer completed callback.
01274   * @param  huart: UART handle.
01275   * @retval None
01276   */
01277 __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
01278 {
01279   /* Prevent unused argument(s) compilation warning */
01280   UNUSED(huart);
01281
01282   /* NOTE: This function should not be modified, when the callback is needed,
01283            the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
01284    */
01285 }
01286
01287 /**
01288   * @brief Rx Transfer completed callback.
01289   * @param huart: UART handle.
01290   * @retval None
01291   */
01292 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
01293 {
01294   /* Prevent unused argument(s) compilation warning */
01295   UNUSED(huart);
01296
01297   /* NOTE : This function should not be modified, when the callback is needed,
01298             the HAL_UART_RxCpltCallback can be implemented in the user file.
01299    */
01300 }
01301
01302 /**
01303   * @brief  Rx Half Transfer completed callback.
01304   * @param  huart: UART handle.
01305   * @retval None
01306   */
01307 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
01308 {
01309   /* Prevent unused argument(s) compilation warning */
01310   UNUSED(huart);
01311
01312   /* NOTE: This function should not be modified, when the callback is needed,
01313            the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
01314    */
01315 }
01316
01317 /**
01318   * @brief UART error callback.
01319   * @param huart: UART handle.
01320   * @retval None
01321   */
01322 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
01323 {
01324   /* Prevent unused argument(s) compilation warning */
01325   UNUSED(huart);
01326
01327   /* NOTE : This function should not be modified, when the callback is needed,
01328             the HAL_UART_ErrorCallback can be implemented in the user file.
01329    */
01330 }
01331
01332 /**
01333   * @}
01334   */
01335
01336 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
01337   *  @brief   UART control functions
01338   *
01339 @verbatim
01340  ===============================================================================
01341                       ##### Peripheral Control functions #####
01342  ===============================================================================
01343     [..]
01344     This subsection provides a set of functions allowing to control the UART.
01345      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
01346      (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
01347      (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
01348      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
01349      (+) UART_SetConfig() API configures the UART peripheral
01350      (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
01351      (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
01352      (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters
01353      (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
01354      (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
01355      (+) HAL_LIN_SendBreak() API transmits the break characters
01356 @endverbatim
01357   * @{
01358   */
01359
01360 /**
01361   * @brief Enable UART in mute mode (does not mean UART enters mute mode;
01362   * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
01363   * @param huart: UART handle.
01364   * @retval HAL status
01365   */
01366 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
01367 {
01368   /* Process Locked */
01369   __HAL_LOCK(huart);
01370
01371   huart->gState = HAL_UART_STATE_BUSY;
01372
01373   /* Enable USART mute mode by setting the MME bit in the CR1 register */
01374   SET_BIT(huart->Instance->CR1, USART_CR1_MME);
01375
01376   huart->gState = HAL_UART_STATE_READY;
01377
01378   return (UART_CheckIdleState(huart));
01379 }
01380
01381 /**
01382   * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
01383   *         as it may not have been in mute mode at this very moment).
01384   * @param  huart: UART handle.
01385   * @retval HAL status
01386   */
01387 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
01388 {
01389   /* Process Locked */
01390   __HAL_LOCK(huart);
01391
01392   huart->gState = HAL_UART_STATE_BUSY;
01393
01394    /* Disable USART mute mode by clearing the MME bit in the CR1 register */
01395   CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
01396
01397   huart->gState = HAL_UART_STATE_READY;
01398
01399   return (UART_CheckIdleState(huart));
01400 }
01401
01402 /**
01403   * @brief Enter UART mute mode (means UART actually enters mute mode).
01404   * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
01405   * @param huart: UART handle.
01406   * @retval None
01407   */
01408 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
01409 {
01410   __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
01411 }
01412
01413 /**
01414   * @brief  Enable the UART transmitter and disable the UART receiver.
01415   * @param  huart: UART handle.
01416   * @retval HAL status
01417   */
01418 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
01419 {
01420   /* Process Locked */
01421   __HAL_LOCK(huart);
01422   huart->gState = HAL_UART_STATE_BUSY;
01423
01424   /* Clear TE and RE bits */
01425   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
01426   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
01427   SET_BIT(huart->Instance->CR1, USART_CR1_TE);
01428
01429   huart->gState = HAL_UART_STATE_READY;
01430
01431   /* Process Unlocked */
01432   __HAL_UNLOCK(huart);
01433
01434   return HAL_OK;
01435 }
01436
01437 /**
01438   * @brief  Enable the UART receiver and disable the UART transmitter.
01439   * @param  huart: UART handle.
01440   * @retval HAL status.
01441   */
01442 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
01443 {
01444   /* Process Locked */
01445   __HAL_LOCK(huart);
01446   huart->gState = HAL_UART_STATE_BUSY;
01447
01448   /* Clear TE and RE bits */
01449   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
01450   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
01451   SET_BIT(huart->Instance->CR1, USART_CR1_RE);
01452
01453   huart->gState = HAL_UART_STATE_READY;
01454   /* Process Unlocked */
01455   __HAL_UNLOCK(huart);
01456
01457   return HAL_OK;
01458 }
01459
01460
01461 /**
01462   * @brief  Transmit break characters.
01463   * @param  huart: UART handle.
01464   * @retval HAL status
01465   */
01466 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
01467 {
01468   /* Check the parameters */
01469   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
01470
01471   /* Process Locked */
01472   __HAL_LOCK(huart);
01473
01474   huart->gState = HAL_UART_STATE_BUSY;
01475
01476   /* Send break characters */
01477   huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
01478
01479   huart->gState = HAL_UART_STATE_READY;
01480
01481   /* Process Unlocked */
01482   __HAL_UNLOCK(huart);
01483
01484   return HAL_OK;
01485 }
01486
01487
01488 /**
01489   * @}
01490   */
01491
01492 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
01493  *  @brief   UART Peripheral State functions
01494  *
01495 @verbatim
01496   ==============================================================================
01497             ##### Peripheral State and Error functions #####
01498   ==============================================================================
01499     [..]
01500     This subsection provides functions allowing to :
01501       (+) Return the UART handle state.
01502       (+) Return the UART handle error code
01503
01504 @endverbatim
01505   * @{
01506   */
01507
01508 /**
01509   * @brief  Return the UART handle state.
01510   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
01511   *               the configuration information for the specified UART.
01512   * @retval HAL state
01513   */
01514 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
01515 {
01516   uint32_t temp1= 0x00, temp2 = 0x00;
01517   temp1 = huart->gState;
01518   temp2 = huart->RxState;
01519
01520   return (HAL_UART_StateTypeDef)(temp1 | temp2);
01521 }
01522
01523 /**
01524   * @brief  Return the UART handle error code.
01525   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
01526   *               the configuration information for the specified UART.
01527   * @retval UART Error Code
01528 */
01529 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
01530 {
01531   return huart->ErrorCode;
01532 }
01533 /**
01534   * @}
01535   */
01536
01537 /**
01538   * @}
01539   */
01540
01541 /** @defgroup UART_Private_Functions UART Private Functions
01542   * @{
01543   */
01544
01545 /**
01546   * @brief Configure the UART peripheral.
01547   * @param huart: UART handle.
01548   * @retval HAL status
01549   */
01550 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
01551 {
01552   uint32_t tmpreg                     = 0x00000000;
01553   UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
01554   uint16_t brrtemp                    = 0x0000;
01555   uint16_t usartdiv                   = 0x0000;
01556   HAL_StatusTypeDef ret               = HAL_OK;
01557
01558   /* Check the parameters */
01559   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
01560   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
01561   if(UART_INSTANCE_LOWPOWER(huart))
01562   {
01563     assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
01564   }
01565   else
01566   {
01567     assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
01568     assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
01569   }
01570
01571   assert_param(IS_UART_PARITY(huart->Init.Parity));
01572   assert_param(IS_UART_MODE(huart->Init.Mode));
01573   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
01574   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
01575
01576
01577   /*-------------------------- USART CR1 Configuration -----------------------*/
01578   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
01579    *  the UART Word Length, Parity, Mode and oversampling:
01580    *  set the M bits according to huart->Init.WordLength value
01581    *  set PCE and PS bits according to huart->Init.Parity value
01582    *  set TE and RE bits according to huart->Init.Mode value
01583    *  set OVER8 bit according to huart->Init.OverSampling value */
01584   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
01585   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
01586
01587   /*-------------------------- USART CR2 Configuration -----------------------*/
01588   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
01589    * to huart->Init.StopBits value */
01590   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
01591
01592   /*-------------------------- USART CR3 Configuration -----------------------*/
01593   /* Configure
01594    * - UART HardWare Flow Control: set CTSE and RTSE bits according
01595    *   to huart->Init.HwFlowCtl value
01596    * - one-bit sampling method versus three samples' majority rule according
01597    *   to huart->Init.OneBitSampling (not applicable to LPUART) */
01598   tmpreg = (uint32_t)huart->Init.HwFlowCtl;
01599   if (!(UART_INSTANCE_LOWPOWER(huart)))
01600   {
01601     tmpreg |= huart->Init.OneBitSampling;
01602   }
01603   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
01604
01605   /*-------------------------- USART BRR Configuration -----------------------*/
01606   UART_GETCLOCKSOURCE(huart, clocksource);
01607
01608   /* Check LPUART instance */
01609   if(UART_INSTANCE_LOWPOWER(huart))
01610   {
01611     /* Retrieve frequency clock */
01612     tmpreg = 0;
01613
01614     switch (clocksource)
01615     {
01616     case UART_CLOCKSOURCE_PCLK1:
01617       tmpreg = HAL_RCC_GetPCLK1Freq();
01618       break;
01619     case UART_CLOCKSOURCE_HSI:
01620       tmpreg = (uint32_t) HSI_VALUE;
01621       break;
01622     case UART_CLOCKSOURCE_SYSCLK:
01623       tmpreg = HAL_RCC_GetSysClockFreq();
01624       break;
01625     case UART_CLOCKSOURCE_LSE:
01626       tmpreg = (uint32_t) LSE_VALUE;
01627       break;
01628     case UART_CLOCKSOURCE_UNDEFINED:
01629     default:
01630         ret = HAL_ERROR;
01631       break;
01632     }
01633
01634     /* if proper clock source reported */
01635     if (tmpreg != 0)
01636     {
01637       /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
01638       if ( (tmpreg < (3 * huart->Init.BaudRate) ) ||
01639            (tmpreg > (4096 * huart->Init.BaudRate) ))
01640       {
01641         ret = HAL_ERROR;
01642       }
01643       else
01644       {
01645         switch (clocksource)
01646         {
01647         case UART_CLOCKSOURCE_PCLK1:
01648             tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
01649           break;
01650         case UART_CLOCKSOURCE_HSI:
01651             tmpreg = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate));
01652           break;
01653         case UART_CLOCKSOURCE_SYSCLK:
01654             tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
01655           break;
01656         case UART_CLOCKSOURCE_LSE:
01657             tmpreg = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate));
01658           break;
01659         case UART_CLOCKSOURCE_UNDEFINED:
01660         default:
01661             ret = HAL_ERROR;
01662           break;
01663         }
01664
01665         if ((tmpreg >= UART_LPUART_BRR_MIN) && (tmpreg <= UART_LPUART_BRR_MAX))
01666         {
01667            huart->Instance->BRR = tmpreg;
01668         }
01669         else
01670         {
01671           ret = HAL_ERROR;
01672         }
01673       }  /*   if ( (tmpreg < (3 * huart->Init.BaudRate) ) || (tmpreg > (4096 * huart->Init.BaudRate) )) */
01674     } /* if (tmpreg != 0) */
01675   }
01676   /* Check UART Over Sampling to set Baud Rate Register */
01677   else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
01678   {
01679     switch (clocksource)
01680     {
01681     case UART_CLOCKSOURCE_PCLK1:
01682         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
01683       break;
01684     case UART_CLOCKSOURCE_PCLK2:
01685         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
01686       break;
01687     case UART_CLOCKSOURCE_HSI:
01688         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
01689       break;
01690     case UART_CLOCKSOURCE_SYSCLK:
01691         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
01692       break;
01693     case UART_CLOCKSOURCE_LSE:
01694         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
01695       break;
01696     case UART_CLOCKSOURCE_UNDEFINED:
01697     default:
01698         ret = HAL_ERROR;
01699       break;
01700     }
01701
01702     brrtemp = usartdiv & 0xFFF0;
01703     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
01704     huart->Instance->BRR = brrtemp;
01705   }
01706   else
01707   {
01708     switch (clocksource)
01709     {
01710     case UART_CLOCKSOURCE_PCLK1:
01711         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
01712       break;
01713     case UART_CLOCKSOURCE_PCLK2:
01714         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
01715       break;
01716     case UART_CLOCKSOURCE_HSI:
01717         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
01718       break;
01719     case UART_CLOCKSOURCE_SYSCLK:
01720         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
01721       break;
01722     case UART_CLOCKSOURCE_LSE:
01723         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
01724       break;
01725     case UART_CLOCKSOURCE_UNDEFINED:
01726     default:
01727         ret = HAL_ERROR;
01728       break;
01729     }
01730   }
01731
01732   return ret;
01733
01734 }
01735
01736 /**
01737   * @brief Configure the UART peripheral advanced features.
01738   * @param huart: UART handle.
01739   * @retval None
01740   */
01741 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
01742 {
01743   /* Check whether the set of advanced features to configure is properly set */
01744   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
01745
01746   /* if required, configure TX pin active level inversion */
01747   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
01748   {
01749     assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
01750     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
01751   }
01752
01753   /* if required, configure RX pin active level inversion */
01754   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
01755   {
01756     assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
01757     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
01758   }
01759
01760   /* if required, configure data inversion */
01761   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
01762   {
01763     assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
01764     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
01765   }
01766
01767   /* if required, configure RX/TX pins swap */
01768   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
01769   {
01770     assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
01771     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
01772   }
01773
01774   /* if required, configure RX overrun detection disabling */
01775   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
01776   {
01777     assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
01778     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
01779   }
01780
01781   /* if required, configure DMA disabling on reception error */
01782   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
01783   {
01784     assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
01785     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
01786   }
01787
01788   /* if required, configure auto Baud rate detection scheme */
01789   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
01790   {
01791     assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
01792     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
01793     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
01794     /* set auto Baudrate detection parameters if detection is enabled */
01795     if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
01796     {
01797       assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
01798       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
01799     }
01800   }
01801
01802   /* if required, configure MSB first on communication line */
01803   if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
01804   {
01805     assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
01806     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
01807   }
01808 }
01809
01810 /**
01811   * @brief Check the UART Idle State.
01812   * @param huart: UART handle.
01813   * @retval HAL status
01814   */
01815 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
01816 {
01817   uint32_t tickstart = 0;
01818
01819   /* Initialize the UART ErrorCode */
01820   huart->ErrorCode = HAL_UART_ERROR_NONE;
01821
01822   /* Init tickstart for timeout managment*/
01823   tickstart = HAL_GetTick();
01824
01825   /* Check if the Transmitter is enabled */
01826   if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01827   {
01828     /* Wait until TEACK flag is set */
01829     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
01830     {
01831       /* Timeout occurred */
01832       return HAL_TIMEOUT;
01833     }
01834   }
01835   /* Check if the Receiver is enabled */
01836   if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01837   {
01838     /* Wait until REACK flag is set */
01839     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
01840     {
01841       /* Timeout occurred */
01842       return HAL_TIMEOUT;
01843     }
01844   }
01845
01846   /* Initialize the UART State */
01847   huart->gState= HAL_UART_STATE_READY;
01848   huart->RxState= HAL_UART_STATE_READY;
01849
01850   /* Process Unlocked */
01851   __HAL_UNLOCK(huart);
01852
01853   return HAL_OK;
01854 }
01855
01856 /**
01857   * @brief  Handle UART Communication Timeout.
01858   * @param  huart: UART handle.
01859   * @param  Flag Specifies the UART flag to check
01860   * @param  Status Flag status (SET or RESET)
01861   * @param  Tickstart Tick start value
01862   * @param  Timeout Timeout duration
01863   * @retval HAL status
01864   */
01865 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01866 {
01867   /* Wait until flag is set */
01868   while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
01869   {
01870     /* Check for the Timeout */
01871     if(Timeout != HAL_MAX_DELAY)
01872     {
01873       if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
01874       {
01875         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01876         CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
01877         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01878
01879         huart->gState = HAL_UART_STATE_READY;
01880         huart->RxState = HAL_UART_STATE_READY;
01881
01882         /* Process Unlocked */
01883         __HAL_UNLOCK(huart);
01884
01885         return HAL_TIMEOUT;
01886       }
01887     }
01888   }
01889   return HAL_OK;
01890 }
01891
01892
01893 /**
01894   * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
01895   * @param  huart: UART handle.
01896   * @retval None
01897   */
01898 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
01899 {
01900   /* At end of Tx process, restore huart->gState to Ready */
01901   huart->gState = HAL_UART_STATE_READY;
01902
01903   /* Disable TXEIE and TCIE interrupts */
01904   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01905 }
01906
01907
01908 /**
01909   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
01910   * @param  huart: UART handle.
01911   * @retval None
01912   */
01913 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
01914 {
01915   /* At end of Rx process, restore huart->RxState to Ready */
01916   huart->RxState = HAL_UART_STATE_READY;
01917
01918   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01919   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01920   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01921 }
01922
01923
01924 /**
01925   * @brief DMA UART transmit process complete callback.
01926   * @param hdma: DMA handle.
01927   * @retval None
01928   */
01929 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01930 {
01931   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01932
01933   /* DMA Normal mode */
01934   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
01935   {
01936     huart->TxXferCount = 0;
01937
01938     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01939        in the UART CR3 register */
01940     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01941
01942     /* Enable the UART Transmit Complete Interrupt */
01943     SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
01944   }
01945   /* DMA Circular mode */
01946   else
01947   {
01948     HAL_UART_TxCpltCallback(huart);
01949   }
01950
01951 }
01952
01953 /**
01954   * @brief DMA UART transmit process half complete callback.
01955   * @param hdma : DMA handle.
01956   * @retval None
01957   */
01958 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01959 {
01960   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01961
01962   HAL_UART_TxHalfCpltCallback(huart);
01963 }
01964
01965 /**
01966   * @brief DMA UART receive process complete callback.
01967   * @param hdma: DMA handle.
01968   * @retval None
01969   */
01970 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01971 {
01972   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01973
01974   /* DMA Normal mode */
01975   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
01976   {
01977     huart->RxXferCount = 0;
01978
01979     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01980     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01981     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01982
01983     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
01984        in the UART CR3 register */
01985     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01986
01987     /* At end of Rx process, restore huart->RxState to Ready */
01988     huart->RxState = HAL_UART_STATE_READY;
01989   }
01990
01991   HAL_UART_RxCpltCallback(huart);
01992 }
01993
01994 /**
01995   * @brief DMA UART receive process half complete callback.
01996   * @param hdma : DMA handle.
01997   * @retval None
01998   */
01999 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02000 {
02001   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02002
02003   HAL_UART_RxHalfCpltCallback(huart);
02004 }
02005
02006 /**
02007   * @brief DMA UART communication error callback.
02008   * @param hdma: DMA handle.
02009   * @retval None
02010   */
02011 static void UART_DMAError(DMA_HandleTypeDef *hdma)
02012 {
02013   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02014   huart->RxXferCount = 0;
02015   huart->TxXferCount = 0;
02016
02017   /* Stop UART DMA Tx request if ongoing */
02018   if (  (huart->gState == HAL_UART_STATE_BUSY_TX)
02019       &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
02020   {
02021     UART_EndTxTransfer(huart);
02022   }
02023
02024   /* Stop UART DMA Rx request if ongoing */
02025   if (  (huart->RxState == HAL_UART_STATE_BUSY_RX)
02026       &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
02027   {
02028     UART_EndRxTransfer(huart);
02029   }
02030
02031   huart->ErrorCode |= HAL_UART_ERROR_DMA;
02032   HAL_UART_ErrorCallback(huart);
02033 }
02034
02035 /**
02036   * @brief DMA UART communication abort callback, when call by HAL services on Error
02037   *        (To be called at end of DMA Abort procedure following error occurrence).
02038   * @param hdma: DMA handle.
02039   * @retval None
02040   */
02041 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02042 {
02043   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02044   huart->RxXferCount = 0;
02045   huart->TxXferCount = 0;
02046
02047   HAL_UART_ErrorCallback(huart);
02048 }
02049
02050 /**
02051   * @brief  Send an amount of data in interrupt mode.
02052   * @note   Function is called under interruption only, once
02053   *         interruptions have been enabled by HAL_UART_Transmit_IT().
02054   * @param  huart: UART handle.
02055   * @retval HAL status
02056   */
02057 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
02058 {
02059   uint16_t* tmp;
02060
02061   /* Check that a Tx process is ongoing */
02062   if (huart->gState == HAL_UART_STATE_BUSY_TX)
02063   {
02064
02065     if(huart->TxXferCount == 0)
02066     {
02067       /* Disable the UART Transmit Data Register Empty Interrupt */
02068       CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
02069
02070       /* Enable the UART Transmit Complete Interrupt */
02071       SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
02072
02073       return HAL_OK;
02074     }
02075     else
02076     {
02077       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
02078       {
02079         tmp = (uint16_t*) huart->pTxBuffPtr;
02080         huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
02081         huart->pTxBuffPtr += 2;
02082       }
02083       else
02084       {
02085         huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);
02086       }
02087
02088       huart->TxXferCount--;
02089
02090       return HAL_OK;
02091     }
02092   }
02093   else
02094   {
02095     return HAL_BUSY;
02096   }
02097 }
02098
02099
02100 /**
02101   * @brief  Wrap up transmission in non-blocking mode.
02102   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
02103   *                the configuration information for the specified UART module.
02104   * @retval HAL status
02105   */
02106 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
02107 {
02108   /* Disable the UART Transmit Complete Interrupt */
02109   CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
02110
02111   /* Tx process is ended, restore huart->gState to Ready */
02112   huart->gState = HAL_UART_STATE_READY;
02113
02114   HAL_UART_TxCpltCallback(huart);
02115
02116   return HAL_OK;
02117 }
02118
02119
02120 /**
02121   * @brief  Receive an amount of data in interrupt mode.
02122   * @note   Function is called under interruption only, once
02123   *         interruptions have been enabled by HAL_UART_Receive_IT()
02124   * @param  huart: UART handle.
02125   * @retval HAL status
02126   */
02127 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
02128 {
02129   uint16_t* tmp;
02130   uint16_t  uhMask = huart->Mask;
02131   uint16_t  uhdata;
02132
02133   /* Check that a Rx process is ongoing */
02134   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
02135   {
02136     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
02137     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
02138     {
02139       tmp = (uint16_t*) huart->pRxBuffPtr ;
02140       *tmp = (uint16_t)(uhdata & uhMask);
02141       huart->pRxBuffPtr +=2;
02142     }
02143     else
02144     {
02145       *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
02146     }
02147
02148     if(--huart->RxXferCount == 0)
02149     {
02150       /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
02151       CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02152
02153       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
02154       CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02155
02156       /* Rx process is completed, restore huart->RxState to Ready */
02157       huart->RxState = HAL_UART_STATE_READY;
02158
02159       HAL_UART_RxCpltCallback(huart);
02160
02161       return HAL_OK;
02162     }
02163
02164     return HAL_OK;
02165   }
02166   else
02167   {
02168     /* Clear RXNE interrupt flag */
02169     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
02170
02171     return HAL_BUSY;
02172   }
02173 }
02174
02175 /**
02176   * @}
02177   */
02178
02179 #endif /* HAL_UART_MODULE_ENABLED */
02180 /**
02181   * @}
02182   */
02183
02184 /**
02185   * @}
02186   */
02187
02188 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_uart.h Source File

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stm32l4xx_hal_uart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_uart.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of UART HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_UART_H
00040 #define __STM32L4xx_HAL_UART_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup UART
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup UART_Exported_Types UART Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief UART Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
00068                                            The baud rate register is computed using the following formula:
00069                                            - If oversampling is 16 or in LIN mode,
00070                                               Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
00071                                            - If oversampling is 8,
00072                                               Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
00073                                               Baud Rate Register[3] =  0
00074                                               Baud Rate Register[2:0] =  (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */
00075
00076   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00077                                            This parameter can be a value of @ref UARTEx_Word_Length. */
00078
00079   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00080                                            This parameter can be a value of @ref UART_Stop_Bits. */
00081
00082   uint32_t Parity;                    /*!< Specifies the parity mode.
00083                                            This parameter can be a value of @ref UART_Parity
00084                                            @note When parity is enabled, the computed parity is inserted
00085                                                  at the MSB position of the transmitted data (9th bit when
00086                                                  the word length is set to 9 data bits; 8th bit when the
00087                                                  word length is set to 8 data bits). */
00088
00089   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00090                                            This parameter can be a value of @ref UART_Mode. */
00091
00092   uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
00093                                            or disabled.
00094                                            This parameter can be a value of @ref UART_Hardware_Flow_Control. */
00095
00096   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
00097                                            This parameter can be a value of @ref UART_Over_Sampling. */
00098
00099   uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00100                                            Selecting the single sample method increases the receiver tolerance to clock
00101                                            deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
00102 }UART_InitTypeDef;
00103
00104 /**
00105   * @brief  UART Advanced Features initalization structure definition
00106   */
00107 typedef struct
00108 {
00109   uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
00110                                        Advanced Features may be initialized at the same time .
00111                                        This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
00112
00113   uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
00114                                        This parameter can be a value of @ref UART_Tx_Inv.  */
00115
00116   uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
00117                                        This parameter can be a value of @ref UART_Rx_Inv.  */
00118
00119   uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
00120                                        vs negative/inverted logic).
00121                                        This parameter can be a value of @ref UART_Data_Inv. */
00122
00123   uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
00124                                        This parameter can be a value of @ref UART_Rx_Tx_Swap. */
00125
00126   uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
00127                                        This parameter can be a value of @ref UART_Overrun_Disable. */
00128
00129   uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
00130                                        This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
00131
00132   uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
00133                                        This parameter can be a value of @ref UART_AutoBaudRate_Enable */
00134
00135   uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
00136                                        detection is carried out.
00137                                        This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
00138
00139   uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
00140                                        This parameter can be a value of @ref UART_MSB_First. */
00141 } UART_AdvFeatureInitTypeDef;
00142
00143
00144
00145 /**
00146   * @brief HAL UART State structures definition
00147   * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
00148   *        - gState contains UART state information related to global Handle management
00149   *          and also information related to Tx operations.
00150   *          gState value coding follow below described bitmap :
00151   *          b7-b6  Error information
00152   *             00 : No Error
00153   *             01 : (Not Used)
00154   *             10 : Timeout
00155   *             11 : Error
00156   *          b5     IP initilisation status
00157   *             0  : Reset (IP not initialized)
00158   *             1  : Init done (IP not initialized. HAL UART Init function already called)
00159   *          b4-b3  (not used)
00160   *             xx : Should be set to 00
00161   *          b2     Intrinsic process state
00162   *             0  : Ready
00163   *             1  : Busy (IP busy with some configuration or internal operations)
00164   *          b1     (not used)
00165   *             x  : Should be set to 0
00166   *          b0     Tx state
00167   *             0  : Ready (no Tx operation ongoing)
00168   *             1  : Busy (Tx operation ongoing)
00169   *        - RxState contains information related to Rx operations.
00170   *          RxState value coding follow below described bitmap :
00171   *          b7-b6  (not used)
00172   *             xx : Should be set to 00
00173   *          b5     IP initilisation status
00174   *             0  : Reset (IP not initialized)
00175   *             1  : Init done (IP not initialized)
00176   *          b4-b2  (not used)
00177   *            xxx : Should be set to 000
00178   *          b1     Rx state
00179   *             0  : Ready (no Rx operation ongoing)
00180   *             1  : Busy (Rx operation ongoing)
00181   *          b0     (not used)
00182   *             x  : Should be set to 0.
00183   */
00184 typedef enum
00185 {
00186   HAL_UART_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
00187                                                    Value is allowed for gState and RxState */
00188   HAL_UART_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
00189                                                    Value is allowed for gState and RxState */
00190   HAL_UART_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
00191                                                    Value is allowed for gState only */
00192   HAL_UART_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
00193                                                    Value is allowed for gState only */
00194   HAL_UART_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
00195                                                    Value is allowed for RxState only */
00196   HAL_UART_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
00197                                                    Not to be used for neither gState nor RxState.
00198                                                    Value is result of combination (Or) between gState and RxState values */
00199   HAL_UART_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
00200                                                    Value is allowed for gState only */
00201   HAL_UART_STATE_ERROR             = 0xE0U    /*!< Error
00202                                                    Value is allowed for gState only */
00203 }HAL_UART_StateTypeDef;
00204
00205 /**
00206   * @brief  HAL UART Error Code structure definition
00207   */
00208 typedef enum
00209 {
00210   HAL_UART_ERROR_NONE      = 0x00,    /*!< No error            */
00211   HAL_UART_ERROR_PE        = 0x01,    /*!< Parity error        */
00212   HAL_UART_ERROR_NE        = 0x02,    /*!< Noise error         */
00213   HAL_UART_ERROR_FE        = 0x04,    /*!< frame error         */
00214   HAL_UART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
00215   HAL_UART_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
00216 }HAL_UART_ErrorTypeDef;
00217
00218 /**
00219   * @brief UART clock sources definition
00220   */
00221 typedef enum
00222 {
00223   UART_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source     */
00224   UART_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source     */
00225   UART_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source       */
00226   UART_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source    */
00227   UART_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
00228   UART_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
00229 }UART_ClockSourceTypeDef;
00230
00231 /**
00232   * @brief  UART handle Structure definition
00233   */
00234 typedef struct
00235 {
00236   USART_TypeDef            *Instance;        /*!< UART registers base address        */
00237
00238   UART_InitTypeDef         Init;             /*!< UART communication parameters      */
00239
00240   UART_AdvFeatureInitTypeDef AdvancedInit;   /*!< UART Advanced Features initialization parameters */
00241
00242   uint8_t                  *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
00243
00244   uint16_t                 TxXferSize;       /*!< UART Tx Transfer size              */
00245
00246   uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
00247
00248   uint8_t                  *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
00249
00250   uint16_t                 RxXferSize;       /*!< UART Rx Transfer size              */
00251
00252   uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
00253
00254   uint16_t                 Mask;             /*!< UART Rx RDR register mask          */
00255
00256   DMA_HandleTypeDef        *hdmatx;          /*!< UART Tx DMA Handle parameters      */
00257
00258   DMA_HandleTypeDef        *hdmarx;          /*!< UART Rx DMA Handle parameters      */
00259
00260   HAL_LockTypeDef           Lock;            /*!< Locking object                     */
00261
00262   __IO HAL_UART_StateTypeDef    gState;      /*!< UART state information related to global Handle management
00263                                                   and also related to Tx operations.
00264                                                   This parameter can be a value of @ref HAL_UART_StateTypeDef */
00265
00266   __IO HAL_UART_StateTypeDef    RxState;     /*!< UART state information related to Rx operations.
00267                                                   This parameter can be a value of @ref HAL_UART_StateTypeDef */
00268
00269   __IO uint32_t             ErrorCode;       /*!< UART Error code                    */
00270
00271 }UART_HandleTypeDef;
00272
00273 /**
00274   * @}
00275   */
00276
00277 /* Exported constants --------------------------------------------------------*/
00278 /** @defgroup UART_Exported_Constants UART Exported Constants
00279   * @{
00280   */
00281
00282 /** @defgroup UART_Stop_Bits   UART Number of Stop Bits
00283   * @{
00284   */
00285 #define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
00286 #define UART_STOPBITS_1                     ((uint32_t)0x00000000)                /*!< UART frame with 1 stop bit    */
00287 #define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
00288 #define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup UART_Parity  UART Parity
00294   * @{
00295   */
00296 #define UART_PARITY_NONE                    ((uint32_t)0x00000000)                         /*!< No parity   */
00297 #define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                      /*!< Even parity */
00298 #define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))     /*!< Odd parity  */
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
00304   * @{
00305   */
00306 #define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000)                           /*!< No hardware control       */
00307 #define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)                       /*!< Request To Send           */
00308 #define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)                       /*!< Clear To Send             */
00309 #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))    /*!< Request and Clear To Send */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup UART_Mode UART Transfer Mode
00315   * @{
00316   */
00317 #define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)                    /*!< RX mode        */
00318 #define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)                    /*!< TX mode        */
00319 #define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))    /*!< RX and TX mode */
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup UART_State  UART State
00325   * @{
00326   */
00327 #define UART_STATE_DISABLE                  ((uint32_t)0x00000000)          /*!< UART disabled  */
00328 #define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)        /*!< UART enabled   */
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup UART_Over_Sampling UART Over Sampling
00334   * @{
00335   */
00336 #define UART_OVERSAMPLING_16                ((uint32_t)0x00000000)          /*!< Oversampling by 16 */
00337 #define UART_OVERSAMPLING_8                 ((uint32_t)USART_CR1_OVER8)     /*!< Oversampling by 8  */
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
00343   * @{
00344   */
00345 #define UART_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000)          /*!< One-bit sampling disable */
00346 #define UART_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT)    /*!< One-bit sampling enable  */
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
00352   * @{
00353   */
00354 #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    ((uint32_t)0x00000000)            /*!< Auto Baud rate detection on start bit            */
00355 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)   /*!< Auto Baud rate detection on falling edge         */
00356 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)   /*!< Auto Baud rate detection on 0x7F frame detection */
00357 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   ((uint32_t)USART_CR2_ABRMODE)     /*!< Auto Baud rate detection on 0x55 frame detection */
00358 /**
00359   * @}
00360   */
00361
00362 /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
00363   * @{
00364   */
00365 #define UART_RECEIVER_TIMEOUT_DISABLE       ((uint32_t)0x00000000)                  /*!< UART receiver timeout disable */
00366 #define UART_RECEIVER_TIMEOUT_ENABLE        ((uint32_t)USART_CR2_RTOEN)             /*!< UART receiver timeout enable  */
00367 /**
00368   * @}
00369   */
00370
00371 /** @defgroup UART_LIN    UART Local Interconnection Network mode
00372   * @{
00373   */
00374 #define UART_LIN_DISABLE                    ((uint32_t)0x00000000)                 /*!< Local Interconnect Network disable */
00375 #define UART_LIN_ENABLE                     ((uint32_t)USART_CR2_LINEN)            /*!< Local Interconnect Network enable  */
00376 /**
00377   * @}
00378   */
00379
00380 /** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
00381   * @{
00382   */
00383 #define UART_LINBREAKDETECTLENGTH_10B       ((uint32_t)0x00000000)                /*!< LIN 10-bit break detection length */
00384 #define UART_LINBREAKDETECTLENGTH_11B       ((uint32_t)USART_CR2_LBDL)            /*!< LIN 11-bit break detection length  */
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup UART_DMA_Tx    UART DMA Tx
00390   * @{
00391   */
00392 #define UART_DMA_TX_DISABLE                 ((uint32_t)0x00000000)                /*!< UART DMA TX disabled */
00393 #define UART_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)            /*!< UART DMA TX enabled  */
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup UART_DMA_Rx   UART DMA Rx
00399   * @{
00400   */
00401 #define UART_DMA_RX_DISABLE                 ((uint32_t)0x00000000)                  /*!< UART DMA RX disabled */
00402 #define UART_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)              /*!< UART DMA RX enabled  */
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
00408   * @{
00409   */
00410 #define UART_HALF_DUPLEX_DISABLE            ((uint32_t)0x00000000)                  /*!< UART half-duplex disabled */
00411 #define UART_HALF_DUPLEX_ENABLE             ((uint32_t)USART_CR3_HDSEL)             /*!< UART half-duplex enabled  */
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
00417   * @{
00418   */
00419 #define UART_WAKEUPMETHOD_IDLELINE          ((uint32_t)0x00000000)                  /*!< UART wake-up on idle line    */
00420 #define UART_WAKEUPMETHOD_ADDRESSMARK       ((uint32_t)USART_CR1_WAKE)              /*!< UART wake-up on address mark */
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup UART_Request_Parameters UART Request Parameters
00426   * @{
00427   */
00428 #define UART_AUTOBAUD_REQUEST               ((uint32_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
00429 #define UART_SENDBREAK_REQUEST              ((uint32_t)USART_RQR_SBKRQ)        /*!< Send Break Request          */
00430 #define UART_MUTE_MODE_REQUEST              ((uint32_t)USART_RQR_MMRQ)         /*!< Mute Mode Request           */
00431 #define UART_RXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
00432 #define UART_TXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
00438   * @{
00439   */
00440 #define UART_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000)          /*!< No advanced feature initialization       */
00441 #define UART_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001)          /*!< TX pin active level inversion            */
00442 #define UART_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002)          /*!< RX pin active level inversion            */
00443 #define UART_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004)          /*!< Binary data inversion                    */
00444 #define UART_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008)          /*!< TX/RX pins swap                          */
00445 #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010)          /*!< RX overrun disable                       */
00446 #define UART_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020)          /*!< DMA disable on Reception Error           */
00447 #define UART_ADVFEATURE_AUTOBAUDRATE_INIT       ((uint32_t)0x00000040)          /*!< Auto Baud rate detection initialization  */
00448 #define UART_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080)          /*!< Most significant bit sent/received first */
00449 /**
00450   * @}
00451   */
00452
00453 /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
00454   * @{
00455   */
00456 #define UART_ADVFEATURE_TXINV_DISABLE       ((uint32_t)0x00000000)              /*!< TX pin active level inversion disable */
00457 #define UART_ADVFEATURE_TXINV_ENABLE        ((uint32_t)USART_CR2_TXINV)         /*!< TX pin active level inversion enable  */
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
00463   * @{
00464   */
00465 #define UART_ADVFEATURE_RXINV_DISABLE       ((uint32_t)0x00000000)              /*!< RX pin active level inversion disable */
00466 #define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)         /*!< RX pin active level inversion enable  */
00467 /**
00468   * @}
00469   */
00470
00471 /** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
00472   * @{
00473   */
00474 #define UART_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000)              /*!< Binary data inversion disable */
00475 #define UART_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
00481   * @{
00482   */
00483 #define UART_ADVFEATURE_SWAP_DISABLE        ((uint32_t)0x00000000)              /*!< TX/RX pins swap disable */
00484 #define UART_ADVFEATURE_SWAP_ENABLE         ((uint32_t)USART_CR2_SWAP)          /*!< TX/RX pins swap enable  */
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
00490   * @{
00491   */
00492 #define UART_ADVFEATURE_OVERRUN_ENABLE      ((uint32_t)0x00000000)              /*!< RX overrun enable  */
00493 #define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
00499   * @{
00500   */
00501 #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   ((uint32_t)0x00000000)           /*!< RX Auto Baud rate detection enable  */
00502 #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)      /*!< RX Auto Baud rate detection disable */
00503 /**
00504   * @}
00505   */
00506
00507 /** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
00508   * @{
00509   */
00510 #define UART_ADVFEATURE_DMA_ENABLEONRXERROR    ((uint32_t)0x00000000)           /*!< DMA enable on Reception Error  */
00511 #define UART_ADVFEATURE_DMA_DISABLEONRXERROR   ((uint32_t)USART_CR3_DDRE)       /*!< DMA disable on Reception Error */
00512 /**
00513   * @}
00514   */
00515
00516 /** @defgroup UART_MSB_First   UART Advanced Feature MSB First
00517   * @{
00518   */
00519 #define UART_ADVFEATURE_MSBFIRST_DISABLE    ((uint32_t)0x00000000)              /*!< Most significant bit sent/received first disable */
00520 #define UART_ADVFEATURE_MSBFIRST_ENABLE     ((uint32_t)USART_CR2_MSBFIRST)      /*!< Most significant bit sent/received first enable  */
00521 /**
00522   * @}
00523   */
00524
00525 /** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
00526   * @{
00527   */
00528 #define UART_ADVFEATURE_STOPMODE_DISABLE    ((uint32_t)0x00000000)              /*!< UART stop mode disable */
00529 #define UART_ADVFEATURE_STOPMODE_ENABLE     ((uint32_t)USART_CR1_UESM)          /*!< UART stop mode enable  */
00530 /**
00531   * @}
00532   */
00533
00534 /** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
00535   * @{
00536   */
00537 #define UART_ADVFEATURE_MUTEMODE_DISABLE    ((uint32_t)0x00000000)              /*!< UART mute mode disable */
00538 #define UART_ADVFEATURE_MUTEMODE_ENABLE     ((uint32_t)USART_CR1_MME)           /*!< UART mute mode enable  */
00539 /**
00540   * @}
00541   */
00542
00543 /** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
00544   * @{
00545   */
00546 #define UART_CR2_ADDRESS_LSB_POS            ((uint32_t) 24)                     /*!< UART address-matching LSB position in CR2 register */
00547 /**
00548   * @}
00549   */
00550
00551 /** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
00552   * @{
00553   */
00554 #define UART_WAKEUP_ON_ADDRESS              ((uint32_t)0x00000000)              /*!< UART wake-up on address                         */
00555 #define UART_WAKEUP_ON_STARTBIT             ((uint32_t)USART_CR3_WUS_1)         /*!< UART wake-up on start bit                       */
00556 #define UART_WAKEUP_ON_READDATA_NONEMPTY    ((uint32_t)USART_CR3_WUS)           /*!< UART wake-up on receive data register not empty */
00557 /**
00558   * @}
00559   */
00560
00561 /** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
00562   * @{
00563   */
00564 #define UART_DE_POLARITY_HIGH               ((uint32_t)0x00000000)              /*!< Driver enable signal is active high */
00565 #define UART_DE_POLARITY_LOW                ((uint32_t)USART_CR3_DEP)           /*!< Driver enable signal is active low  */
00566 /**
00567   * @}
00568   */
00569
00570 /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
00571   * @{
00572   */
00573 #define UART_CR1_DEAT_ADDRESS_LSB_POS       ((uint32_t) 21)                     /*!< UART Driver Enable assertion time LSB position in CR1 register */
00574 /**
00575   * @}
00576   */
00577
00578 /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
00579   * @{
00580   */
00581 #define UART_CR1_DEDT_ADDRESS_LSB_POS       ((uint32_t) 16)                     /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
00582 /**
00583   * @}
00584   */
00585
00586 /** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
00587   * @{
00588   */
00589 #define UART_IT_MASK                        ((uint32_t)0x001F)                  /*!< UART interruptions flags mask */
00590 /**
00591   * @}
00592   */
00593
00594 /** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
00595   * @{
00596   */
00597 #define HAL_UART_TIMEOUT_VALUE              0x1FFFFFF                           /*!< UART polling-based communications time-out value */
00598 /**
00599   * @}
00600   */
00601
00602 /** @defgroup UART_Flags     UART Status Flags
00603   *        Elements values convention: 0xXXXX
00604   *           - 0xXXXX  : Flag mask in the ISR register
00605   * @{
00606   */
00607 #define UART_FLAG_REACK                     ((uint32_t)0x00400000)              /*!< UART receive enable acknowledge flag      */
00608 #define UART_FLAG_TEACK                     ((uint32_t)0x00200000)              /*!< UART transmit enable acknowledge flag     */
00609 #define UART_FLAG_WUF                       ((uint32_t)0x00100000)              /*!< UART wake-up from stop mode flag          */
00610 #define UART_FLAG_RWU                       ((uint32_t)0x00080000)              /*!< UART receiver wake-up from mute mode flag */
00611 #define UART_FLAG_SBKF                      ((uint32_t)0x00040000)              /*!< UART send break flag                      */
00612 #define UART_FLAG_CMF                       ((uint32_t)0x00020000)              /*!< UART character match flag                 */
00613 #define UART_FLAG_BUSY                      ((uint32_t)0x00010000)              /*!< UART busy flag                            */
00614 #define UART_FLAG_ABRF                      ((uint32_t)0x00008000)              /*!< UART auto Baud rate flag                  */
00615 #define UART_FLAG_ABRE                      ((uint32_t)0x00004000)              /*!< UART uto Baud rate error                  */
00616 #define UART_FLAG_EOBF                      ((uint32_t)0x00001000)              /*!< UART end of block flag                    */
00617 #define UART_FLAG_RTOF                      ((uint32_t)0x00000800)              /*!< UART receiver timeout flag                */
00618 #define UART_FLAG_CTS                       ((uint32_t)0x00000400)              /*!< UART clear to send flag                   */
00619 #define UART_FLAG_CTSIF                     ((uint32_t)0x00000200)              /*!< UART clear to send interrupt flag         */
00620 #define UART_FLAG_LBDF                      ((uint32_t)0x00000100)              /*!< UART LIN break detection flag             */
00621 #define UART_FLAG_TXE                       ((uint32_t)0x00000080)              /*!< UART transmit data register empty         */
00622 #define UART_FLAG_TC                        ((uint32_t)0x00000040)              /*!< UART transmission complete                */
00623 #define UART_FLAG_RXNE                      ((uint32_t)0x00000020)              /*!< UART read data register not empty         */
00624 #define UART_FLAG_IDLE                      ((uint32_t)0x00000010)              /*!< UART idle flag                            */
00625 #define UART_FLAG_ORE                       ((uint32_t)0x00000008)              /*!< UART overrun error                        */
00626 #define UART_FLAG_NE                        ((uint32_t)0x00000004)              /*!< UART noise error                          */
00627 #define UART_FLAG_FE                        ((uint32_t)0x00000002)              /*!< UART frame error                          */
00628 #define UART_FLAG_PE                        ((uint32_t)0x00000001)              /*!< UART parity error                         */
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup UART_Interrupt_definition   UART Interrupts Definition
00634   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00635   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00636   *           - XX  : Interrupt source register (2bits)
00637   *                 - 01: CR1 register
00638   *                 - 10: CR2 register
00639   *                 - 11: CR3 register
00640   *           - ZZZZZ  : Flag position in the ISR register(5bits)
00641   * @{
00642   */
00643 #define UART_IT_PE                          ((uint32_t)0x0028)                  /*!< UART parity error interruption                 */
00644 #define UART_IT_TXE                         ((uint32_t)0x0727)                  /*!< UART transmit data register empty interruption */
00645 #define UART_IT_TC                          ((uint32_t)0x0626)                  /*!< UART transmission complete interruption        */
00646 #define UART_IT_RXNE                        ((uint32_t)0x0525)                  /*!< UART read data register not empty interruption */
00647 #define UART_IT_IDLE                        ((uint32_t)0x0424)                  /*!< UART idle interruption                         */
00648 #define UART_IT_LBD                         ((uint32_t)0x0846)                  /*!< UART LIN break detection interruption          */
00649 #define UART_IT_CTS                         ((uint32_t)0x096A)                  /*!< UART CTS interruption                          */
00650 #define UART_IT_CM                          ((uint32_t)0x112E)                  /*!< UART character match interruption              */
00651 #define UART_IT_WUF                         ((uint32_t)0x1476)                  /*!< UART wake-up from stop mode interruption       */
00652
00653 /*        Elements values convention: 000000000XXYYYYYb
00654               - YYYYY  : Interrupt source position in the XX register (5bits)
00655               - XX  : Interrupt source register (2bits)
00656                     - 01: CR1 register
00657                     - 10: CR2 register
00658                     - 11: CR3 register */
00659 #define UART_IT_ERR                         ((uint32_t)0x0060)                  /*!< UART error interruption         */
00660
00661 /*       Elements values convention: 0000ZZZZ00000000b
00662              - ZZZZ  : Flag position in the ISR register(4bits) */
00663 #define UART_IT_ORE                         ((uint32_t)0x0300)                  /*!< UART overrun error interruption */
00664 #define UART_IT_NE                          ((uint32_t)0x0200)                  /*!< UART noise error interruption   */
00665 #define UART_IT_FE                          ((uint32_t)0x0100)                  /*!< UART frame error interruption   */
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
00671   * @{
00672   */
00673 #define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
00674 #define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
00675 #define UART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag         */
00676 #define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
00677 #define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
00678 #define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
00679 #define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
00680 #define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
00681 #define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag      */
00682 #define UART_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag           */
00683 #define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
00684 #define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
00685 /**
00686   * @}
00687   */
00688
00689
00690 /**
00691   * @}
00692   */
00693
00694 /* Exported macros -----------------------------------------------------------*/
00695 /** @defgroup UART_Exported_Macros UART Exported Macros
00696   * @{
00697   */
00698
00699 /** @brief  Reset UART handle states.
00700   * @param  __HANDLE__: UART handle.
00701   * @retval None
00702   */
00703 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00704                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00705                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00706                                                      } while(0)
00707 /** @brief  Flush the UART Data registers.
00708   * @param  __HANDLE__: specifies the UART Handle.
00709   * @retval None
00710   */
00711 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
00712   do{                \
00713       SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
00714       SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
00715     }  while(0)
00716
00717 /** @brief  Clear the specified UART pending flag.
00718   * @param  __HANDLE__: specifies the UART Handle.
00719   * @param  __FLAG__: specifies the flag to check.
00720   *          This parameter can be any combination of the following values:
00721   *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
00722   *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
00723   *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
00724   *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
00725   *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
00726   *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
00727   *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
00728   *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
00729   *            @arg @ref UART_CLEAR_RTOF     Receiver Time Out Clear Flag
00730   *            @arg @ref UART_CLEAR_EOBF     End Of Block Clear Flag
00731   *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
00732   *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
00733   * @retval None
00734   */
00735 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00736
00737 /** @brief  Clear the UART PE pending flag.
00738   * @param  __HANDLE__: specifies the UART Handle.
00739   * @retval None
00740   */
00741 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
00742
00743 /** @brief  Clear the UART FE pending flag.
00744   * @param  __HANDLE__: specifies the UART Handle.
00745   * @retval None
00746   */
00747 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
00748
00749 /** @brief  Clear the UART NE pending flag.
00750   * @param  __HANDLE__: specifies the UART Handle.
00751   * @retval None
00752   */
00753 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
00754
00755 /** @brief  Clear the UART ORE pending flag.
00756   * @param  __HANDLE__: specifies the UART Handle.
00757   * @retval None
00758   */
00759 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
00760
00761 /** @brief  Clear the UART IDLE pending flag.
00762   * @param  __HANDLE__: specifies the UART Handle.
00763   * @retval None
00764   */
00765 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
00766
00767 /** @brief  Check whether the specified UART flag is set or not.
00768   * @param  __HANDLE__: specifies the UART Handle.
00769   * @param  __FLAG__: specifies the flag to check.
00770   *        This parameter can be one of the following values:
00771   *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
00772   *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
00773   *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
00774   *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
00775   *            @arg @ref UART_FLAG_SBKF  Send Break flag
00776   *            @arg @ref UART_FLAG_CMF   Character match flag
00777   *            @arg @ref UART_FLAG_BUSY  Busy flag
00778   *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
00779   *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
00780   *            @arg @ref UART_FLAG_EOBF  End of block flag
00781   *            @arg @ref UART_FLAG_RTOF  Receiver timeout flag
00782   *            @arg @ref UART_FLAG_CTS   CTS Change flag
00783   *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
00784   *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
00785   *            @arg @ref UART_FLAG_TC    Transmission Complete flag
00786   *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
00787   *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
00788   *            @arg @ref UART_FLAG_ORE   Overrun Error flag
00789   *            @arg @ref UART_FLAG_NE    Noise Error flag
00790   *            @arg @ref UART_FLAG_FE    Framing Error flag
00791   *            @arg @ref UART_FLAG_PE    Parity Error flag
00792   * @retval The new state of __FLAG__ (TRUE or FALSE).
00793   */
00794 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00795
00796 /** @brief  Enable the specified UART interrupt.
00797   * @param  __HANDLE__: specifies the UART Handle.
00798   * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
00799   *          This parameter can be one of the following values:
00800   *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
00801   *            @arg @ref UART_IT_CM   Character match interrupt
00802   *            @arg @ref UART_IT_CTS  CTS change interrupt
00803   *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
00804   *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
00805   *            @arg @ref UART_IT_TC   Transmission complete interrupt
00806   *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
00807   *            @arg @ref UART_IT_IDLE Idle line detection interrupt
00808   *            @arg @ref UART_IT_PE   Parity Error interrupt
00809   *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
00810   * @retval None
00811   */
00812 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00813                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00814                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00815
00816
00817 /** @brief  Disable the specified UART interrupt.
00818   * @param  __HANDLE__: specifies the UART Handle.
00819   * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
00820   *          This parameter can be one of the following values:
00821   *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
00822   *            @arg @ref UART_IT_CM   Character match interrupt
00823   *            @arg @ref UART_IT_CTS  CTS change interrupt
00824   *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
00825   *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
00826   *            @arg @ref UART_IT_TC   Transmission complete interrupt
00827   *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
00828   *            @arg @ref UART_IT_IDLE Idle line detection interrupt
00829   *            @arg @ref UART_IT_PE   Parity Error interrupt
00830   *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
00831   * @retval None
00832   */
00833 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00834                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00835                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00836
00837 /** @brief  Check whether the specified UART interrupt has occurred or not.
00838   * @param  __HANDLE__: specifies the UART Handle.
00839   * @param  __IT__: specifies the UART interrupt to check.
00840   *          This parameter can be one of the following values:
00841   *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
00842   *            @arg @ref UART_IT_CM   Character match interrupt
00843   *            @arg @ref UART_IT_CTS  CTS change interrupt
00844   *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
00845   *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
00846   *            @arg @ref UART_IT_TC   Transmission complete interrupt
00847   *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
00848   *            @arg @ref UART_IT_IDLE Idle line detection interrupt
00849   *            @arg @ref UART_IT_ORE  Overrun Error interrupt
00850   *            @arg @ref UART_IT_NE   Noise Error interrupt
00851   *            @arg @ref UART_IT_FE   Framing Error interrupt
00852   *            @arg @ref UART_IT_PE   Parity Error interrupt
00853   * @retval The new state of __IT__ (TRUE or FALSE).
00854   */
00855 #define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
00856
00857 /** @brief  Check whether the specified UART interrupt source is enabled or not.
00858   * @param  __HANDLE__: specifies the UART Handle.
00859   * @param  __IT__: specifies the UART interrupt source to check.
00860   *          This parameter can be one of the following values:
00861   *            @arg @ref UART_IT_WUF  Wakeup from stop mode interrupt
00862   *            @arg @ref UART_IT_CM   Character match interrupt
00863   *            @arg @ref UART_IT_CTS  CTS change interrupt
00864   *            @arg @ref UART_IT_LBD  LIN Break detection interrupt
00865   *            @arg @ref UART_IT_TXE  Transmit Data Register empty interrupt
00866   *            @arg @ref UART_IT_TC   Transmission complete interrupt
00867   *            @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
00868   *            @arg @ref UART_IT_IDLE Idle line detection interrupt
00869   *            @arg @ref UART_IT_ERR  Error interrupt (Frame error, noise error, overrun error)
00870   *            @arg @ref UART_IT_PE   Parity Error interrupt
00871   * @retval The new state of __IT__ (TRUE or FALSE).
00872   */
00873 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
00874                                                        (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
00875
00876 /** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
00877   * @param  __HANDLE__: specifies the UART Handle.
00878   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00879   *                       to clear the corresponding interrupt
00880   *          This parameter can be one of the following values:
00881   *            @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
00882   *            @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
00883   *            @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
00884   *            @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
00885   *            @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
00886   *            @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
00887   *            @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
00888   *            @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
00889   *            @arg @ref UART_CLEAR_CMF Character Match Clear Flag
00890   *            @arg @ref UART_CLEAR_WUF  Wake Up from stop mode Clear Flag
00891   * @retval None
00892   */
00893 #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00894
00895 /** @brief  Set a specific UART request flag.
00896   * @param  __HANDLE__: specifies the UART Handle.
00897   * @param  __REQ__: specifies the request flag to set
00898   *          This parameter can be one of the following values:
00899   *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
00900   *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
00901   *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
00902   *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
00903   *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
00904   * @retval None
00905   */
00906 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
00907
00908 /** @brief  Enable the UART one bit sample method.
00909   * @param  __HANDLE__: specifies the UART Handle.
00910   * @retval None
00911   */
00912 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00913
00914 /** @brief  Disable the UART one bit sample method.
00915   * @param  __HANDLE__: specifies the UART Handle.
00916   * @retval None
00917   */
00918 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00919
00920 /** @brief  Enable UART.
00921   * @param  __HANDLE__: specifies the UART Handle.
00922   * @retval None
00923   */
00924 #define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00925
00926 /** @brief  Disable UART.
00927   * @param  __HANDLE__: specifies the UART Handle.
00928   * @retval None
00929   */
00930 #define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00931
00932 /** @brief  Enable CTS flow control.
00933   * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
00934   *         without need to call HAL_UART_Init() function.
00935   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00936   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
00937   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00938   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00939   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
00940   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
00941   * @param  __HANDLE__: specifies the UART Handle.
00942   * @retval None
00943   */
00944 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
00945   do{                                                      \
00946     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
00947     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
00948   } while(0)
00949
00950 /** @brief  Disable CTS flow control.
00951   * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
00952   *         without need to call HAL_UART_Init() function.
00953   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00954   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
00955   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00956   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00957   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
00958   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
00959   * @param  __HANDLE__: specifies the UART Handle.
00960   * @retval None
00961   */
00962 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
00963   do{                                                       \
00964     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
00965     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
00966   } while(0)
00967
00968 /** @brief  Enable RTS flow control.
00969   * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
00970   *         without need to call HAL_UART_Init() function.
00971   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00972   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
00973   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00974   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00975   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
00976   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
00977   * @param  __HANDLE__: specifies the UART Handle.
00978   * @retval None
00979   */
00980 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
00981   do{                                                     \
00982     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
00983     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
00984   } while(0)
00985
00986 /** @brief  Disable RTS flow control.
00987   * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
00988   *         without need to call HAL_UART_Init() function.
00989   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00990   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
00991   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00992   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00993   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
00994   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
00995   * @param  __HANDLE__: specifies the UART Handle.
00996   * @retval None
00997   */
00998 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
00999   do{                                                      \
01000     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
01001     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
01002   } while(0)
01003
01004 /**
01005   * @}
01006   */
01007
01008 /* Private macros --------------------------------------------------------*/
01009 /** @defgroup UART_Private_Macros   UART Private Macros
01010   * @{
01011   */
01012 /** @brief  BRR division operation to set BRR register with LPUART.
01013   * @param  __PCLK__: LPUART clock.
01014   * @param  __BAUD__: Baud rate set by the user.
01015   * @retval Division result
01016   */
01017 #define UART_DIV_LPUART(__PCLK__, __BAUD__)      ((((uint64_t)(__PCLK__)*256) + ((__BAUD__)/2)) / (__BAUD__))
01018
01019 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
01020   * @param  __PCLK__: UART clock.
01021   * @param  __BAUD__: Baud rate set by the user.
01022   * @retval Division result
01023   */
01024 #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__)   ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__))
01025
01026 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
01027   * @param  __PCLK__: UART clock.
01028   * @param  __BAUD__: Baud rate set by the user.
01029   * @retval Division result
01030   */
01031 #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__)  (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__))
01032
01033 /** @brief  Check whether or not UART instance is Low Power UART.
01034   * @param  __HANDLE__: specifies the UART Handle.
01035   * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
01036   */
01037 #define UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
01038
01039 /** @brief  Check UART Baud rate.
01040   * @param  __BAUDRATE__: Baudrate specified by the user.
01041   *         The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz)
01042   *         divided by the smallest oversampling used on the USART (i.e. 8)
01043   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
01044   */
01045 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
01046
01047 /** @brief  Check UART assertion time.
01048   * @param  __TIME__: 5-bit value assertion time.
01049   * @retval Test result (TRUE or FALSE).
01050   */
01051 #define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1F)
01052
01053 /** @brief  Check UART deassertion time.
01054   * @param  __TIME__: 5-bit value deassertion time.
01055   * @retval Test result (TRUE or FALSE).
01056   */
01057 #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
01058
01059 /**
01060   * @brief Ensure that UART frame number of stop bits is valid.
01061   * @param __STOPBITS__: UART frame number of stop bits.
01062   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)  UART_STOPBITS_1_5
01063   */
01064 #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
01065                                         ((__STOPBITS__) == UART_STOPBITS_1)   || \
01066                                         ((__STOPBITS__) == UART_STOPBITS_1_5) || \
01067                                         ((__STOPBITS__) == UART_STOPBITS_2))
01068
01069 /**
01070   * @brief Ensure that LPUART frame number of stop bits is valid.
01071   * @param __STOPBITS__: LPUART frame number of stop bits.
01072   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01073   */
01074 #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
01075                                           ((__STOPBITS__) == UART_STOPBITS_2))
01076
01077 /**
01078   * @brief Ensure that UART frame parity is valid.
01079   * @param __PARITY__: UART frame parity.
01080   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
01081   */
01082 #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
01083                                     ((__PARITY__) == UART_PARITY_EVEN) || \
01084                                     ((__PARITY__) == UART_PARITY_ODD))
01085
01086 /**
01087   * @brief Ensure that UART hardware flow control is valid.
01088   * @param __CONTROL__: UART hardware flow control.
01089   * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
01090   */
01091 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
01092                                    (((__CONTROL__) == UART_HWCONTROL_NONE) || \
01093                                     ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
01094                                     ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
01095                                     ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
01096
01097 /**
01098   * @brief Ensure that UART communication mode is valid.
01099   * @param __MODE__: UART communication mode.
01100   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01101   */
01102 #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
01103
01104 /**
01105   * @brief Ensure that UART state is valid.
01106   * @param __STATE__: UART state.
01107   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
01108   */
01109 #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
01110                                   ((__STATE__) == UART_STATE_ENABLE))
01111
01112 /**
01113   * @brief Ensure that UART oversampling is valid.
01114   * @param __SAMPLING__: UART oversampling.
01115   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
01116   */
01117 #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
01118                                             ((__SAMPLING__) == UART_OVERSAMPLING_8))
01119
01120 /**
01121   * @brief Ensure that UART frame sampling is valid.
01122   * @param __ONEBIT__: UART frame sampling.
01123   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
01124   */
01125 #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
01126                                             ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
01127
01128 /**
01129   * @brief Ensure that UART auto Baud rate detection mode is valid.
01130   * @param __MODE__: UART auto Baud rate detection mode.
01131   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01132   */
01133 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
01134                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
01135                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
01136                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
01137
01138 /**
01139   * @brief Ensure that UART receiver timeout setting is valid.
01140   * @param __TIMEOUT__: UART receiver timeout setting.
01141   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
01142   */
01143 #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
01144                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
01145
01146 /**
01147   * @brief Ensure that UART LIN state is valid.
01148   * @param __LIN__: UART LIN state.
01149   * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
01150   */
01151 #define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
01152                                      ((__LIN__) == UART_LIN_ENABLE))
01153
01154 /**
01155   * @brief Ensure that UART LIN break detection length is valid.
01156   * @param __LENGTH__: UART LIN break detection length.
01157   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
01158   */
01159 #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
01160                                                      ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
01161
01162 /**
01163   * @brief Ensure that UART DMA TX state is valid.
01164   * @param __DMATX__: UART DMA TX state.
01165   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
01166   */
01167 #define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
01168                                        ((__DMATX__) == UART_DMA_TX_ENABLE))
01169
01170 /**
01171   * @brief Ensure that UART DMA RX state is valid.
01172   * @param __DMARX__: UART DMA RX state.
01173   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
01174   */
01175 #define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
01176                                        ((__DMARX__) == UART_DMA_RX_ENABLE))
01177
01178 /**
01179   * @brief Ensure that UART half-duplex state is valid.
01180   * @param __HDSEL__: UART half-duplex state.
01181   * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
01182   */
01183 #define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
01184                                             ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
01185
01186 /**
01187   * @brief Ensure that UART wake-up method is valid.
01188   * @param __WAKEUP__: UART wake-up method .
01189   * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
01190   */
01191 #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
01192                                           ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
01193
01194 /**
01195   * @brief Ensure that UART request parameter is valid.
01196   * @param __PARAM__: UART request parameter.
01197   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01198   */
01199 #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
01200                                               ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
01201                                               ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
01202                                               ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
01203                                               ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
01204
01205 /**
01206   * @brief Ensure that UART advanced features initialization is valid.
01207   * @param __INIT__: UART advanced features initialization.
01208   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
01209   */
01210 #define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
01211                                                             UART_ADVFEATURE_TXINVERT_INIT          | \
01212                                                             UART_ADVFEATURE_RXINVERT_INIT          | \
01213                                                             UART_ADVFEATURE_DATAINVERT_INIT        | \
01214                                                             UART_ADVFEATURE_SWAP_INIT              | \
01215                                                             UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
01216                                                             UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
01217                                                             UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
01218                                                             UART_ADVFEATURE_MSBFIRST_INIT))
01219
01220 /**
01221   * @brief Ensure that UART frame TX inversion setting is valid.
01222   * @param __TXINV__: UART frame TX inversion setting.
01223   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
01224   */
01225 #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
01226                                              ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
01227
01228 /**
01229   * @brief Ensure that UART frame RX inversion setting is valid.
01230   * @param __RXINV__: UART frame RX inversion setting.
01231   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
01232   */
01233 #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
01234                                              ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
01235
01236 /**
01237   * @brief Ensure that UART frame data inversion setting is valid.
01238   * @param __DATAINV__: UART frame data inversion setting.
01239   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01240   */
01241 #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
01242                                                  ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
01243
01244 /**
01245   * @brief Ensure that UART frame RX/TX pins swap setting is valid.
01246   * @param __SWAP__: UART frame RX/TX pins swap setting.
01247   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01248   */
01249 #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
01250                                            ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
01251
01252 /**
01253   * @brief Ensure that UART frame overrun setting is valid.
01254   * @param __OVERRUN__: UART frame overrun setting.
01255   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01256   */
01257 #define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
01258                                           ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
01259
01260 /**
01261   * @brief Ensure that UART auto Baud rate state is valid.
01262   * @param __AUTOBAUDRATE__: UART auto Baud rate state.
01263   * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
01264   */
01265 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
01266                                                             ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
01267
01268 /**
01269   * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
01270   * @param __DMA__: UART DMA enabling or disabling on error setting.
01271   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01272   */
01273 #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01274                                                    ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
01275
01276 /**
01277   * @brief Ensure that UART frame MSB first setting is valid.
01278   * @param __MSBFIRST__: UART frame MSB first setting.
01279   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01280   */
01281 #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
01282                                                    ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
01283
01284 /**
01285   * @brief Ensure that UART stop mode state is valid.
01286   * @param __STOPMODE__: UART stop mode state.
01287   * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
01288   */
01289 #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
01290                                                    ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
01291
01292 /**
01293   * @brief Ensure that UART mute mode state is valid.
01294   * @param __MUTE__: UART mute mode state.
01295   * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
01296   */
01297 #define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
01298                                            ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
01299
01300 /**
01301   * @brief Ensure that UART wake-up selection is valid.
01302   * @param __WAKE__: UART wake-up selection.
01303   * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
01304   */
01305 #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
01306                                             ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
01307                                             ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
01308
01309 /**
01310   * @brief Ensure that UART driver enable polarity is valid.
01311   * @param __POLARITY__: UART driver enable polarity.
01312   * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
01313   */
01314 #define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
01315                                               ((__POLARITY__) == UART_DE_POLARITY_LOW))
01316
01317 /**
01318   * @}
01319   */
01320
01321 /* Include UART HAL Extended module */
01322 #include "stm32l4xx_hal_uart_ex.h"
01323
01324 /* Exported functions --------------------------------------------------------*/
01325 /** @addtogroup UART_Exported_Functions UART Exported Functions
01326   * @{
01327   */
01328
01329 /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
01330   * @{
01331   */
01332
01333 /* Initialization and de-initialization functions  ****************************/
01334 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
01335 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
01336 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
01337 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
01338 HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
01339 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
01340 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
01341
01342 /**
01343   * @}
01344   */
01345
01346 /** @addtogroup UART_Exported_Functions_Group2 IO operation functions
01347   * @{
01348   */
01349
01350 /* IO operation functions *****************************************************/
01351 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01352 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01353 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01354 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01355 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01356 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01357 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
01358 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
01359 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
01360 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
01361 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
01362 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
01363 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
01364 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
01365 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
01366
01367 /**
01368   * @}
01369   */
01370
01371 /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
01372   * @{
01373   */
01374
01375 /* Peripheral Control functions  ************************************************/
01376 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
01377 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
01378 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
01379 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
01380 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
01381 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
01382
01383 /**
01384   * @}
01385   */
01386
01387 /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
01388   * @{
01389   */
01390
01391 /* Peripheral State and Errors functions  **************************************************/
01392 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
01393 uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
01394
01395 /**
01396   * @}
01397   */
01398
01399 /**
01400   * @}
01401   */
01402
01403 /* Private functions -----------------------------------------------------------*/
01404 /** @addtogroup UART_Private_Functions UART Private Functions
01405   * @{
01406   */
01407
01408 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
01409 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
01410 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
01411 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
01412
01413 /**
01414   * @}
01415   */
01416
01417 /**
01418   * @}
01419   */
01420
01421 /**
01422   * @}
01423   */
01424
01425 #ifdef __cplusplus
01426 }
01427 #endif
01428
01429 #endif /* __STM32L4xx_HAL_UART_H */
01430
01431 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_uart_ex.c Source File

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stm32l4xx_hal_uart_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_uart_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Extended UART HAL module driver.
00008   *          This file provides firmware functions to manage the following extended
00009   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   *
00014   @verbatim
00015   ==============================================================================
00016                ##### UART peripheral extended features  #####
00017   ==============================================================================
00018
00019     (#) Declare a UART_HandleTypeDef handle structure.
00020
00021     (#) For the UART RS485 Driver Enable mode, initialize the UART registers
00022         by calling the HAL_RS485Ex_Init() API.
00023
00024
00025   @endverbatim
00026   ******************************************************************************
00027   * @attention
00028   *
00029   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00030   *
00031   * Redistribution and use in source and binary forms, with or without modification,
00032   * are permitted provided that the following conditions are met:
00033   *   1. Redistributions of source code must retain the above copyright notice,
00034   *      this list of conditions and the following disclaimer.
00035   *   2. Redistributions in binary form must reproduce the above copyright notice,
00036   *      this list of conditions and the following disclaimer in the documentation
00037   *      and/or other materials provided with the distribution.
00038   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00039   *      may be used to endorse or promote products derived from this software
00040   *      without specific prior written permission.
00041   *
00042   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00043   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00044   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00045   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00046   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00047   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00048   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00049   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00050   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00051   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00052   *
00053   ******************************************************************************
00054   */
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32l4xx_hal.h"
00058
00059 /** @addtogroup STM32L4xx_HAL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup UARTEx UARTEx
00064   * @brief UART Extended HAL module driver
00065   * @{
00066   */
00067
00068 #ifdef HAL_UART_MODULE_ENABLED
00069
00070 /* Private typedef -----------------------------------------------------------*/
00071 /* Private define ------------------------------------------------------------*/
00072 /* Private macros ------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074 /* Private function prototypes -----------------------------------------------*/
00075 /** @defgroup UARTEx_Private_Functions UARTEx Private Functions
00076   * @{
00077   */
00078 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00079 /**
00080   * @}
00081   */
00082
00083 /* Exported functions --------------------------------------------------------*/
00084
00085 /** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
00086   * @{
00087   */
00088
00089 /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
00090   * @brief    Extended Initialization and Configuration Functions
00091   *
00092 @verbatim
00093 ===============================================================================
00094             ##### Initialization and Configuration functions #####
00095  ===============================================================================
00096     [..]
00097     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00098     in asynchronous mode.
00099       (+) For the asynchronous mode the parameters below can be configured:
00100         (++) Baud Rate
00101         (++) Word Length
00102         (++) Stop Bit
00103         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00104              in the data register is transmitted but is changed by the parity bit.
00105         (++) Hardware flow control
00106         (++) Receiver/transmitter modes
00107         (++) Over Sampling Method
00108         (++) One-Bit Sampling Method
00109       (+) For the asynchronous mode, the following advanced features can be configured as well:
00110         (++) TX and/or RX pin level inversion
00111         (++) data logical level inversion
00112         (++) RX and TX pins swap
00113         (++) RX overrun detection disabling
00114         (++) DMA disabling on RX error
00115         (++) MSB first on communication line
00116         (++) auto Baud rate detection
00117     [..]
00118     The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
00119      procedures (details for the procedures are available in reference manual).
00120
00121 @endverbatim
00122
00123   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00124   8-bit or 9-bit), the possible UART formats are listed in the
00125   following table.
00126
00127     Table 1. UART frame format.
00128     +-----------------------------------------------------------------------+
00129     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00130     |---------|---------|-----------|---------------------------------------|
00131     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00132     |---------|---------|-----------|---------------------------------------|
00133     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00134     |---------|---------|-----------|---------------------------------------|
00135     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00136     |---------|---------|-----------|---------------------------------------|
00137     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00138     |---------|---------|-----------|---------------------------------------|
00139     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00140     |---------|---------|-----------|---------------------------------------|
00141     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00142     +-----------------------------------------------------------------------+
00143
00144   * @{
00145   */
00146
00147 /**
00148   * @brief Initialize the RS485 Driver enable feature according to the specified
00149   *         parameters in the UART_InitTypeDef and creates the associated handle.
00150   * @param huart: UART handle.
00151   * @param Polarity: select the driver enable polarity.
00152   *        This parameter can be one of the following values:
00153   *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
00154   *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
00155   * @param AssertionTime: Driver Enable assertion time:
00156   *                         5-bit value defining the time between the activation of the DE (Driver Enable)
00157   *                         signal and the beginning of the start bit. It is expressed in sample time
00158   *                         units (1/8 or 1/16 bit time, depending on the oversampling rate)
00159   * @param DeassertionTime: Driver Enable deassertion time:
00160   *                         5-bit value defining the time between the end of the last stop bit, in a
00161   *                         transmitted message, and the de-activation of the DE (Driver Enable) signal.
00162   *                         It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
00163   *                         oversampling rate).
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
00167 {
00168   uint32_t temp = 0x0;
00169
00170   /* Check the UART handle allocation */
00171   if(huart == NULL)
00172   {
00173     return HAL_ERROR;
00174   }
00175   /* Check the Driver Enable UART instance */
00176   assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
00177
00178   /* Check the Driver Enable polarity */
00179   assert_param(IS_UART_DE_POLARITY(Polarity));
00180
00181   /* Check the Driver Enable assertion time */
00182   assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
00183
00184   /* Check the Driver Enable deassertion time */
00185   assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
00186
00187   if(huart->gState == HAL_UART_STATE_RESET)
00188   {
00189     /* Allocate lock resource and initialize it */
00190     huart->Lock = HAL_UNLOCKED;
00191
00192     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00193     HAL_UART_MspInit(huart);
00194   }
00195
00196   huart->gState = HAL_UART_STATE_BUSY;
00197
00198   /* Disable the Peripheral */
00199   __HAL_UART_DISABLE(huart);
00200
00201   /* Set the UART Communication parameters */
00202   if (UART_SetConfig(huart) == HAL_ERROR)
00203   {
00204     return HAL_ERROR;
00205   }
00206
00207   if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00208   {
00209     UART_AdvFeatureConfig(huart);
00210   }
00211
00212   /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
00213   SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
00214
00215   /* Set the Driver Enable polarity */
00216   MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
00217
00218   /* Set the Driver Enable assertion and deassertion times */
00219   temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
00220   temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
00221   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
00222
00223   /* Enable the Peripheral */
00224   __HAL_UART_ENABLE(huart);
00225
00226   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00227   return (UART_CheckIdleState(huart));
00228 }
00229
00230
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
00236   * @brief    Extended Peripheral Control functions
00237  *
00238 @verbatim
00239  ===============================================================================
00240                       ##### Peripheral Control functions #####
00241  ===============================================================================
00242     [..] This section provides the following functions:
00243      (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
00244      (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
00245      (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
00246          detection length to more than 4 bits for multiprocessor address mark wake up.
00247      (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
00248          trigger: address match, Start Bit detection or RXNE bit status.
00249      (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
00250      (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
00251      (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt
00252
00253
00254 @endverbatim
00255   * @{
00256   */
00257
00258
00259
00260
00261 /**
00262   * @brief By default in multiprocessor mode, when the wake up method is set
00263   *        to address mark, the UART handles only 4-bit long addresses detection;
00264   *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
00265   *        long).
00266   * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
00267   *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
00268   * @param huart: UART handle.
00269   * @param AddressLength: this parameter can be one of the following values:
00270   *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
00271   *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
00272   * @retval HAL status
00273   */
00274 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
00275 {
00276   /* Check the UART handle allocation */
00277   if(huart == NULL)
00278   {
00279     return HAL_ERROR;
00280   }
00281
00282   /* Check the address length parameter */
00283   assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
00284
00285   huart->gState = HAL_UART_STATE_BUSY;
00286
00287   /* Disable the Peripheral */
00288   __HAL_UART_DISABLE(huart);
00289
00290   /* Set the address length */
00291   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
00292
00293   /* Enable the Peripheral */
00294   __HAL_UART_ENABLE(huart);
00295
00296   /* TEACK and/or REACK to check before moving huart->gState to Ready */
00297   return (UART_CheckIdleState(huart));
00298 }
00299
00300
00301 /**
00302   * @brief Set Wakeup from Stop mode interrupt flag selection.
00303   * @param huart: UART handle.
00304   * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
00305   * This parameter can be one of the following values:
00306   *      @arg @ref UART_WAKEUP_ON_ADDRESS
00307   *      @arg @ref UART_WAKEUP_ON_STARTBIT
00308   *      @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
00309   * @retval HAL status
00310   */
00311 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00312 {
00313   HAL_StatusTypeDef status = HAL_OK;
00314   uint32_t tickstart = 0;
00315
00316   /* check the wake-up from stop mode UART instance */
00317   assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
00318   /* check the wake-up selection parameter */
00319   assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
00320
00321   /* Process Locked */
00322   __HAL_LOCK(huart);
00323
00324   huart->gState = HAL_UART_STATE_BUSY;
00325
00326   /* Disable the Peripheral */
00327   __HAL_UART_DISABLE(huart);
00328
00329   /* Set the wake-up selection scheme */
00330   MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
00331
00332   if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
00333   {
00334     UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
00335   }
00336
00337   /* Enable the Peripheral */
00338   __HAL_UART_ENABLE(huart);
00339
00340   /* Init tickstart for timeout managment*/
00341   tickstart = HAL_GetTick();
00342
00343   /* Wait until REACK flag is set */
00344   if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
00345   {
00346     status = HAL_TIMEOUT;
00347   }
00348   else
00349   {
00350     /* Initialize the UART State */
00351     huart->gState = HAL_UART_STATE_READY;
00352   }
00353
00354   /* Process Unlocked */
00355   __HAL_UNLOCK(huart);
00356
00357   return status;
00358 }
00359
00360
00361 /**
00362   * @brief Enable UART Stop Mode.
00363   * @note  The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
00364   * @param huart: UART handle.
00365   * @retval HAL status
00366   */
00367 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
00368 {
00369   /* Process Locked */
00370   __HAL_LOCK(huart);
00371
00372   huart->gState = HAL_UART_STATE_BUSY;
00373
00374   /* Set UESM bit */
00375   SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
00376
00377   huart->gState = HAL_UART_STATE_READY;
00378
00379   /* Process Unlocked */
00380   __HAL_UNLOCK(huart);
00381
00382   return HAL_OK;
00383 }
00384
00385 /**
00386   * @brief Disable UART Stop Mode.
00387   * @param huart: UART handle.
00388   * @retval HAL status
00389   */
00390 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
00391 {
00392   /* Process Locked */
00393   __HAL_LOCK(huart);
00394
00395   huart->gState = HAL_UART_STATE_BUSY;
00396
00397   /* Clear UESM bit */
00398   CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
00399
00400   huart->gState = HAL_UART_STATE_READY;
00401
00402   /* Process Unlocked */
00403   __HAL_UNLOCK(huart);
00404
00405   return HAL_OK;
00406 }
00407
00408 /**
00409   * @brief UART wakeup from Stop mode callback.
00410   * @param huart: UART handle.
00411   * @retval None
00412   */
00413 __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
00414 {
00415   /* Prevent unused argument(s) compilation warning */
00416   UNUSED(huart);
00417
00418   /* NOTE : This function should not be modified, when the callback is needed,
00419             the HAL_UARTEx_WakeupCallback can be implemented in the user file.
00420    */
00421 }
00422
00423 /**
00424   * @}
00425   */
00426
00427 /**
00428   * @}
00429   */
00430
00431 /** @addtogroup UARTEx_Private_Functions
00432   * @{
00433   */
00434
00435 /**
00436   * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
00437   * @param huart: UART handle.
00438   * @param WakeUpSelection: UART wake up from stop mode parameters.
00439   * @retval None
00440   */
00441 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00442 {
00443   assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
00444
00445   /* Set the USART address length */
00446   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
00447
00448   /* Set the USART address node */
00449   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
00450 }
00451
00452 /**
00453   * @}
00454   */
00455
00456 #endif /* HAL_UART_MODULE_ENABLED */
00457
00458 /**
00459   * @}
00460   */
00461
00462 /**
00463   * @}
00464   */
00465
00466 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_uart_ex.h Source File

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stm32l4xx_hal_uart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_uart_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of UART HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_UART_EX_H
00040 #define __STM32L4xx_HAL_UART_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup UARTEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup UARTEx_Exported_Types UARTEx Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  UART wake up from stop mode parameters
00064   */
00065 typedef struct
00066 {
00067   uint32_t WakeUpEvent;        /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
00068                                     This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
00069                                     If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
00070                                     be filled up. */
00071
00072   uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
00073                                     This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
00074
00075   uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
00076 } UART_WakeUpTypeDef;
00077
00078 /**
00079   * @}
00080   */
00081
00082 /* Exported constants --------------------------------------------------------*/
00083 /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
00084   * @{
00085   */
00086
00087 /** @defgroup UARTEx_Word_Length UART Word Length
00088   * @{
00089   */
00090 #define UART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long UART frame */
00091 #define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long UART frame */
00092 #define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long UART frame */
00093 /**
00094   * @}
00095   */
00096
00097 /** @defgroup UARTEx_WakeUp_Address_Length UART Extended WakeUp Address Length
00098   * @{
00099   */
00100 #define UART_ADDRESS_DETECT_4B              ((uint32_t)0x00000000)       /*!< 4-bit long wake-up address */
00101 #define UART_ADDRESS_DETECT_7B              ((uint32_t)USART_CR2_ADDM7)  /*!< 7-bit long wake-up address */
00102 /**
00103   * @}
00104   */
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported macros -----------------------------------------------------------*/
00111 /* Exported functions --------------------------------------------------------*/
00112 /** @addtogroup UARTEx_Exported_Functions
00113   * @{
00114   */
00115
00116 /** @addtogroup UARTEx_Exported_Functions_Group1
00117   * @{
00118   */
00119
00120 /* Initialization and de-initialization functions  ****************************/
00121 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
00122
00123 /**
00124   * @}
00125   */
00126
00127 /* IO operation functions *****************************************************/
00128
00129 /** @addtogroup UARTEx_Exported_Functions_Group3
00130   * @{
00131   */
00132
00133 /* Peripheral Control functions  **********************************************/
00134 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00135 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
00136 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
00137 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
00138 void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
00139
00140 /**
00141   * @}
00142   */
00143
00144 /**
00145   * @}
00146   */
00147
00148 /* Private macros ------------------------------------------------------------*/
00149 /** @defgroup UARTEx_Private_Macros UARTEx Private Macros
00150   * @{
00151   */
00152
00153 /** @brief  Report the UART clock source.
00154   * @param  __HANDLE__: specifies the UART Handle.
00155   * @param  __CLOCKSOURCE__: output variable.
00156   * @retval UART clocking source, written in __CLOCKSOURCE__.
00157   */
00158 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00159 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00160   do {                                                        \
00161     if((__HANDLE__)->Instance == USART1)                      \
00162     {                                                         \
00163        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00164        {                                                      \
00165         case RCC_USART1CLKSOURCE_PCLK2:                       \
00166           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00167           break;                                              \
00168         case RCC_USART1CLKSOURCE_HSI:                         \
00169           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00170           break;                                              \
00171         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00172           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00173           break;                                              \
00174         case RCC_USART1CLKSOURCE_LSE:                         \
00175           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00176           break;                                              \
00177         default:                                              \
00178           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00179           break;                                              \
00180        }                                                      \
00181     }                                                         \
00182     else if((__HANDLE__)->Instance == USART2)                 \
00183     {                                                         \
00184        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00185        {                                                      \
00186         case RCC_USART2CLKSOURCE_PCLK1:                       \
00187           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00188           break;                                              \
00189         case RCC_USART2CLKSOURCE_HSI:                         \
00190           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00191           break;                                              \
00192         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00193           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00194           break;                                              \
00195         case RCC_USART2CLKSOURCE_LSE:                         \
00196           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00197           break;                                              \
00198         default:                                              \
00199           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00200           break;                                              \
00201        }                                                      \
00202     }                                                         \
00203     else if((__HANDLE__)->Instance == USART3)                 \
00204     {                                                         \
00205        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00206        {                                                      \
00207         case RCC_USART3CLKSOURCE_PCLK1:                       \
00208           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00209           break;                                              \
00210         case RCC_USART3CLKSOURCE_HSI:                         \
00211           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00212           break;                                              \
00213         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00214           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00215           break;                                              \
00216         case RCC_USART3CLKSOURCE_LSE:                         \
00217           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00218           break;                                              \
00219         default:                                              \
00220           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00221           break;                                              \
00222        }                                                      \
00223     }                                                         \
00224     else if((__HANDLE__)->Instance == UART4)                  \
00225     {                                                         \
00226        switch(__HAL_RCC_GET_UART4_SOURCE())                   \
00227        {                                                      \
00228         case RCC_UART4CLKSOURCE_PCLK1:                        \
00229           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00230           break;                                              \
00231         case RCC_UART4CLKSOURCE_HSI:                          \
00232           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00233           break;                                              \
00234         case RCC_UART4CLKSOURCE_SYSCLK:                       \
00235           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00236           break;                                              \
00237         case RCC_UART4CLKSOURCE_LSE:                          \
00238           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00239           break;                                              \
00240         default:                                              \
00241           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00242           break;                                              \
00243        }                                                      \
00244     }                                                         \
00245     else if ((__HANDLE__)->Instance == UART5)                 \
00246     {                                                         \
00247        switch(__HAL_RCC_GET_UART5_SOURCE())                   \
00248        {                                                      \
00249         case RCC_UART5CLKSOURCE_PCLK1:                        \
00250           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00251           break;                                              \
00252         case RCC_UART5CLKSOURCE_HSI:                          \
00253           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00254           break;                                              \
00255         case RCC_UART5CLKSOURCE_SYSCLK:                       \
00256           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00257           break;                                              \
00258         case RCC_UART5CLKSOURCE_LSE:                          \
00259           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00260           break;                                              \
00261         default:                                              \
00262           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00263           break;                                              \
00264        }                                                      \
00265     }                                                         \
00266     else if((__HANDLE__)->Instance == LPUART1)                \
00267     {                                                         \
00268        switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
00269        {                                                      \
00270         case RCC_LPUART1CLKSOURCE_PCLK1:                      \
00271           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00272           break;                                              \
00273         case RCC_LPUART1CLKSOURCE_HSI:                        \
00274           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00275           break;                                              \
00276         case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
00277           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00278           break;                                              \
00279         case RCC_LPUART1CLKSOURCE_LSE:                        \
00280           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00281           break;                                              \
00282         default:                                              \
00283           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00284           break;                                              \
00285        }                                                      \
00286     }                                                         \
00287   } while(0)
00288 #elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
00289 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00290   do {                                                        \
00291     if((__HANDLE__)->Instance == USART1)                      \
00292     {                                                         \
00293        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00294        {                                                      \
00295         case RCC_USART1CLKSOURCE_PCLK2:                       \
00296           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00297           break;                                              \
00298         case RCC_USART1CLKSOURCE_HSI:                         \
00299           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00300           break;                                              \
00301         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00302           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00303           break;                                              \
00304         case RCC_USART1CLKSOURCE_LSE:                         \
00305           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00306           break;                                              \
00307         default:                                              \
00308           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00309           break;                                              \
00310        }                                                      \
00311     }                                                         \
00312     else if((__HANDLE__)->Instance == USART2)                 \
00313     {                                                         \
00314        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00315        {                                                      \
00316         case RCC_USART2CLKSOURCE_PCLK1:                       \
00317           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00318           break;                                              \
00319         case RCC_USART2CLKSOURCE_HSI:                         \
00320           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00321           break;                                              \
00322         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00323           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00324           break;                                              \
00325         case RCC_USART2CLKSOURCE_LSE:                         \
00326           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00327           break;                                              \
00328         default:                                              \
00329           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00330           break;                                              \
00331        }                                                      \
00332     }                                                         \
00333     else if((__HANDLE__)->Instance == USART3)                 \
00334     {                                                         \
00335        switch(__HAL_RCC_GET_USART3_SOURCE())                  \
00336        {                                                      \
00337         case RCC_USART3CLKSOURCE_PCLK1:                       \
00338           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00339           break;                                              \
00340         case RCC_USART3CLKSOURCE_HSI:                         \
00341           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00342           break;                                              \
00343         case RCC_USART3CLKSOURCE_SYSCLK:                      \
00344           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00345           break;                                              \
00346         case RCC_USART3CLKSOURCE_LSE:                         \
00347           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00348           break;                                              \
00349         default:                                              \
00350           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00351           break;                                              \
00352        }                                                      \
00353     }                                                         \
00354     else if((__HANDLE__)->Instance == LPUART1)                \
00355     {                                                         \
00356        switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
00357        {                                                      \
00358         case RCC_LPUART1CLKSOURCE_PCLK1:                      \
00359           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00360           break;                                              \
00361         case RCC_LPUART1CLKSOURCE_HSI:                        \
00362           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00363           break;                                              \
00364         case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
00365           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00366           break;                                              \
00367         case RCC_LPUART1CLKSOURCE_LSE:                        \
00368           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00369           break;                                              \
00370         default:                                              \
00371           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00372           break;                                              \
00373        }                                                      \
00374     }                                                         \
00375   } while(0)
00376 #elif defined (STM32L432xx) || defined (STM32L442xx)
00377 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00378   do {                                                        \
00379     if((__HANDLE__)->Instance == USART1)                      \
00380     {                                                         \
00381        switch(__HAL_RCC_GET_USART1_SOURCE())                  \
00382        {                                                      \
00383         case RCC_USART1CLKSOURCE_PCLK2:                       \
00384           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00385           break;                                              \
00386         case RCC_USART1CLKSOURCE_HSI:                         \
00387           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00388           break;                                              \
00389         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00390           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00391           break;                                              \
00392         case RCC_USART1CLKSOURCE_LSE:                         \
00393           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00394           break;                                              \
00395         default:                                              \
00396           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00397           break;                                              \
00398        }                                                      \
00399     }                                                         \
00400     else if((__HANDLE__)->Instance == USART2)                 \
00401     {                                                         \
00402        switch(__HAL_RCC_GET_USART2_SOURCE())                  \
00403        {                                                      \
00404         case RCC_USART2CLKSOURCE_PCLK1:                       \
00405           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00406           break;                                              \
00407         case RCC_USART2CLKSOURCE_HSI:                         \
00408           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00409           break;                                              \
00410         case RCC_USART2CLKSOURCE_SYSCLK:                      \
00411           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00412           break;                                              \
00413         case RCC_USART2CLKSOURCE_LSE:                         \
00414           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00415           break;                                              \
00416         default:                                              \
00417           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00418           break;                                              \
00419        }                                                      \
00420     }                                                         \
00421     else if((__HANDLE__)->Instance == LPUART1)                \
00422     {                                                         \
00423        switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
00424        {                                                      \
00425         case RCC_LPUART1CLKSOURCE_PCLK1:                      \
00426           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00427           break;                                              \
00428         case RCC_LPUART1CLKSOURCE_HSI:                        \
00429           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00430           break;                                              \
00431         case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
00432           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00433           break;                                              \
00434         case RCC_LPUART1CLKSOURCE_LSE:                        \
00435           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00436           break;                                              \
00437         default:                                              \
00438           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00439           break;                                              \
00440        }                                                      \
00441     }                                                         \
00442   } while(0)
00443 #endif
00444
00445 /** @brief  Report the UART mask to apply to retrieve the received data
00446   *         according to the word length and to the parity bits activation.
00447   * @note   If PCE = 1, the parity bit is not included in the data extracted
00448   *         by the reception API().
00449   *         This masking operation is not carried out in the case of
00450   *         DMA transfers.
00451   * @param  __HANDLE__: specifies the UART Handle.
00452   * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
00453   */
00454 #define UART_MASK_COMPUTATION(__HANDLE__)                             \
00455   do {                                                                \
00456   if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
00457   {                                                                   \
00458      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00459      {                                                                \
00460         (__HANDLE__)->Mask = 0x01FF ;                                 \
00461      }                                                                \
00462      else                                                             \
00463      {                                                                \
00464         (__HANDLE__)->Mask = 0x00FF ;                                 \
00465      }                                                                \
00466   }                                                                   \
00467   else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
00468   {                                                                   \
00469      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00470      {                                                                \
00471         (__HANDLE__)->Mask = 0x00FF ;                                 \
00472      }                                                                \
00473      else                                                             \
00474      {                                                                \
00475         (__HANDLE__)->Mask = 0x007F ;                                 \
00476      }                                                                \
00477   }                                                                   \
00478   else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \
00479   {                                                                   \
00480      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
00481      {                                                                \
00482         (__HANDLE__)->Mask = 0x007F ;                                 \
00483      }                                                                \
00484      else                                                             \
00485      {                                                                \
00486         (__HANDLE__)->Mask = 0x003F ;                                 \
00487      }                                                                \
00488   }                                                                   \
00489 } while(0)
00490
00491
00492 /**
00493   * @brief Ensure that UART frame length is valid.
00494   * @param __LENGTH__: UART frame length.
00495   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00496   */
00497 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
00498                                          ((__LENGTH__) == UART_WORDLENGTH_8B) || \
00499                                          ((__LENGTH__) == UART_WORDLENGTH_9B))
00500
00501 /**
00502   * @brief Ensure that UART wake-up address length is valid.
00503   * @param __ADDRESS__: UART wake-up address length.
00504   * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
00505   */
00506 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
00507                                                    ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
00508
00509 /**
00510   * @}
00511   */
00512
00513 /* Private functions ---------------------------------------------------------*/
00514
00515 /**
00516   * @}
00517   */
00518
00519 /**
00520   * @}
00521   */
00522
00523 #ifdef __cplusplus
00524 }
00525 #endif
00526
00527 #endif /* __STM32L4xx_HAL_UART_EX_H */
00528
00529 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_usart.c Source File

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stm32l4xx_hal_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_usart.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   USART HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
00010   *          Peripheral (USART).
00011   *           + Initialization and de-initialization functions
00012   *           + IO operation functions
00013   *           + Peripheral Control functions
00014   *           + Peripheral State and Error functions
00015   *
00016   @verbatim
00017  ===============================================================================
00018                         ##### How to use this driver #####
00019  ===============================================================================
00020     [..]
00021       The USART HAL driver can be used as follows:
00022
00023       (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
00024       (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
00025           (++) Enable the USARTx interface clock.
00026           (++) USART pins configuration:
00027             (+++) Enable the clock for the USART GPIOs.
00028             (+++) Configure these USART pins as alternate function pull-up.
00029           (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
00030                 HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00031             (+++) Configure the USARTx interrupt priority.
00032             (+++) Enable the NVIC USART IRQ handle.
00033             (++) USART interrupts handling:
00034               -@@-   The specific USART interrupts (Transmission complete interrupt,
00035                   RXNE interrupt and Error Interrupts) will be managed using the macros
00036                   __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
00037           (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
00038                HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
00039             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00040             (+++) Enable the DMAx interface clock.
00041             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00042             (+++) Configure the DMA Tx/Rx channel.
00043             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
00044             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00045
00046       (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00047           flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
00048
00049       (#) Initialize the USART registers by calling the HAL_USART_Init() API:
00050           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00051                by calling the customized HAL_USART_MspInit(&husart) API.
00052
00053     [..]
00054      (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
00055         HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
00056         HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
00057
00058   @endverbatim
00059   ******************************************************************************
00060   * @attention
00061   *
00062   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00063   *
00064   * Redistribution and use in source and binary forms, with or without modification,
00065   * are permitted provided that the following conditions are met:
00066   *   1. Redistributions of source code must retain the above copyright notice,
00067   *      this list of conditions and the following disclaimer.
00068   *   2. Redistributions in binary form must reproduce the above copyright notice,
00069   *      this list of conditions and the following disclaimer in the documentation
00070   *      and/or other materials provided with the distribution.
00071   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00072   *      may be used to endorse or promote products derived from this software
00073   *      without specific prior written permission.
00074   *
00075   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00076   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00077   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00078   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00079   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00080   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00081   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00082   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00083   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00084   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00085   *
00086   ******************************************************************************
00087   */
00088
00089 /* Includes ------------------------------------------------------------------*/
00090 #include "stm32l4xx_hal.h"
00091
00092 /** @addtogroup STM32L4xx_HAL_Driver
00093   * @{
00094   */
00095
00096 /** @defgroup USART USART
00097   * @brief HAL USART Synchronous module driver
00098   * @{
00099   */
00100
00101 #ifdef HAL_USART_MODULE_ENABLED
00102
00103 /* Private typedef -----------------------------------------------------------*/
00104 /* Private define ------------------------------------------------------------*/
00105 /** @defgroup USART_Private_Constants USART Private Constants
00106   * @{
00107   */
00108 #define USART_DUMMY_DATA          ((uint16_t) 0xFFFF)           /*!< USART transmitted dummy data                     */
00109 #define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000)             /*!< USART TX or RX enable acknowledge time-out value */
00110 #define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00111                                               USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))    /*!< USART CR1 fields of parameters set by USART_SetConfig API */
00112 #define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
00113                                               USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
00114 /**
00115   * @}
00116   */
00117
00118 /* Private macros ------------------------------------------------------------*/
00119 /* Private variables ---------------------------------------------------------*/
00120 /* Private function prototypes -----------------------------------------------*/
00121 /** @addtogroup USART_Private_Functions
00122   * @{
00123   */
00124 static void USART_EndTransfer(USART_HandleTypeDef *husart);
00125 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00126 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00127 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00128 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00129 static void USART_DMAError(DMA_HandleTypeDef *hdma);
00130 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00131 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
00132 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
00133 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00134 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
00135 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
00136 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
00137 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
00138 /**
00139   * @}
00140   */
00141
00142 /* Exported functions --------------------------------------------------------*/
00143
00144 /** @defgroup USART_Exported_Functions USART Exported Functions
00145   * @{
00146   */
00147
00148 /** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00149   *  @brief    Initialization and Configuration functions
00150   *
00151 @verbatim
00152  ===============================================================================
00153             ##### Initialization and Configuration functions #####
00154  ===============================================================================
00155     [..]
00156     This subsection provides a set of functions allowing to initialize the USART
00157     in asynchronous and in synchronous modes.
00158       (+) For the asynchronous mode only these parameters can be configured:
00159         (++) Baud Rate
00160         (++) Word Length
00161         (++) Stop Bit
00162         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00163              in the data register is transmitted but is changed by the parity bit.
00164         (++) USART polarity
00165         (++) USART phase
00166         (++) USART LastBit
00167         (++) Receiver/transmitter modes
00168
00169     [..]
00170     The HAL_USART_Init() function follows the USART  synchronous configuration
00171     procedure (details for the procedure are available in reference manual).
00172
00173 @endverbatim
00174
00175   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00176   8-bit or 9-bit), the possible USART formats are listed in the
00177   following table.
00178
00179     Table 1. USART frame format.
00180     +-----------------------------------------------------------------------+
00181     |  M1 bit |  M0 bit |  PCE bit  |            USART frame                |
00182     |---------|---------|-----------|---------------------------------------|
00183     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00184     |---------|---------|-----------|---------------------------------------|
00185     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00186     |---------|---------|-----------|---------------------------------------|
00187     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00188     |---------|---------|-----------|---------------------------------------|
00189     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00190     |---------|---------|-----------|---------------------------------------|
00191     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00192     |---------|---------|-----------|---------------------------------------|
00193     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00194     +-----------------------------------------------------------------------+
00195
00196   * @{
00197   */
00198
00199 /**
00200   * @brief  Initializes the USART mode according to the specified
00201   *         parameters in the USART_InitTypeDef and initialize the associated handle.
00202   * @param husart: USART handle.
00203   * @retval HAL status
00204   */
00205 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
00206 {
00207   /* Check the USART handle allocation */
00208   if(husart == NULL)
00209   {
00210     return HAL_ERROR;
00211   }
00212
00213   /* Check the parameters */
00214   assert_param(IS_USART_INSTANCE(husart->Instance));
00215
00216   if(husart->State == HAL_USART_STATE_RESET)
00217   {
00218     /* Allocate lock resource and initialize it */
00219     husart->Lock = HAL_UNLOCKED;
00220
00221     /* Init the low level hardware : GPIO, CLOCK */
00222     HAL_USART_MspInit(husart);
00223   }
00224
00225   husart->State = HAL_USART_STATE_BUSY;
00226
00227   /* Disable the Peripheral */
00228   __HAL_USART_DISABLE(husart);
00229
00230   /* Set the Usart Communication parameters */
00231   if (USART_SetConfig(husart) == HAL_ERROR)
00232   {
00233     return HAL_ERROR;
00234   }
00235
00236   /* In Synchronous mode, the following bits must be kept cleared:
00237   - LINEN bit in the USART_CR2 register
00238   - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
00239   husart->Instance->CR2 &= ~USART_CR2_LINEN;
00240   husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00241
00242   /* Enable the Peripheral */
00243   __HAL_USART_ENABLE(husart);
00244
00245   /* TEACK and/or REACK to check before moving husart->State to Ready */
00246   return (USART_CheckIdleState(husart));
00247 }
00248
00249 /**
00250   * @brief DeInitialize the USART peripheral.
00251   * @param husart: USART handle.
00252   * @retval HAL status
00253   */
00254 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
00255 {
00256    /* Check the USART handle allocation */
00257   if(husart == NULL)
00258   {
00259     return HAL_ERROR;
00260   }
00261
00262   /* Check the parameters */
00263   assert_param(IS_USART_INSTANCE(husart->Instance));
00264
00265   husart->State = HAL_USART_STATE_BUSY;
00266
00267   husart->Instance->CR1 = 0x0;
00268   husart->Instance->CR2 = 0x0;
00269   husart->Instance->CR3 = 0x0;
00270
00271   /* DeInit the low level hardware */
00272   HAL_USART_MspDeInit(husart);
00273
00274   husart->ErrorCode = HAL_USART_ERROR_NONE;
00275   husart->State = HAL_USART_STATE_RESET;
00276
00277   /* Process Unlock */
00278   __HAL_UNLOCK(husart);
00279
00280   return HAL_OK;
00281 }
00282
00283 /**
00284   * @brief Initialize the USART MSP.
00285   * @param husart: USART handle.
00286   * @retval None
00287   */
00288 __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
00289 {
00290   /* Prevent unused argument(s) compilation warning */
00291   UNUSED(husart);
00292
00293   /* NOTE : This function should not be modified, when the callback is needed,
00294             the HAL_USART_MspInit can be implemented in the user file
00295    */
00296 }
00297
00298 /**
00299   * @brief DeInitialize the USART MSP.
00300   * @param husart: USART handle.
00301   * @retval None
00302   */
00303 __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
00304 {
00305   /* Prevent unused argument(s) compilation warning */
00306   UNUSED(husart);
00307
00308   /* NOTE : This function should not be modified, when the callback is needed,
00309             the HAL_USART_MspDeInit can be implemented in the user file
00310    */
00311 }
00312
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
00318   *  @brief   USART Transmit and Receive functions
00319   *
00320 @verbatim
00321  ===============================================================================
00322                       ##### IO operation functions #####
00323  ===============================================================================
00324     [..] This subsection provides a set of functions allowing to manage the USART synchronous
00325     data transfers.
00326
00327     [..] The USART supports master mode only: it cannot receive or send data related to an input
00328          clock (SCLK is always an output).
00329
00330     (#) There are two modes of transfer:
00331        (++) Blocking mode: The communication is performed in polling mode.
00332             The HAL status of all data processing is returned by the same function
00333             after finishing transfer.
00334        (++) No-Blocking mode: The communication is performed using Interrupts
00335            or DMA, These API's return the HAL status.
00336            The end of the data processing will be indicated through the
00337            dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
00338            using DMA mode.
00339            The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
00340            will be executed respectively at the end of the transmit or Receive process
00341            The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
00342
00343     (#) Blocking mode API's are :
00344         (++) HAL_USART_Transmit()in simplex mode
00345         (++) HAL_USART_Receive() in full duplex receive only
00346         (++) HAL_USART_TransmitReceive() in full duplex mode
00347
00348     (#) Non-Blocking mode API's with Interrupt are :
00349         (++) HAL_USART_Transmit_IT()in simplex mode
00350         (++) HAL_USART_Receive_IT() in full duplex receive only
00351         (++) HAL_USART_TransmitReceive_IT()in full duplex mode
00352         (++) HAL_USART_IRQHandler()
00353
00354     (#) No-Blocking mode API's  with DMA are :
00355         (++) HAL_USART_Transmit_DMA()in simplex mode
00356         (++) HAL_USART_Receive_DMA() in full duplex receive only
00357         (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
00358         (++) HAL_USART_DMAPause()
00359         (++) HAL_USART_DMAResume()
00360         (++) HAL_USART_DMAStop()
00361
00362     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00363         (++) HAL_USART_TxCpltCallback()
00364         (++) HAL_USART_RxCpltCallback()
00365         (++) HAL_USART_TxHalfCpltCallback()
00366         (++) HAL_USART_RxHalfCpltCallback()
00367         (++) HAL_USART_ErrorCallback()
00368         (++) HAL_USART_TxRxCpltCallback()
00369
00370     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00371         Errors are handled as follows :
00372        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00373            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00374            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00375            and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
00376        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00377            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00378            Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
00379
00380 @endverbatim
00381   * @{
00382   */
00383
00384 /**
00385   * @brief  Simplex send an amount of data in blocking mode.
00386   * @param  husart USART handle.
00387   * @param  pTxData Pointer to data buffer.
00388   * @param  Size Amount of data to be sent.
00389   * @param  Timeout Timeout duration.
00390   * @retval HAL status
00391   */
00392 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
00393 {
00394   uint16_t* tmp;
00395   uint32_t tickstart = 0;
00396
00397   if(husart->State == HAL_USART_STATE_READY)
00398   {
00399     if((pTxData == NULL) || (Size == 0))
00400     {
00401       return  HAL_ERROR;
00402     }
00403
00404     /* Process Locked */
00405     __HAL_LOCK(husart);
00406
00407     husart->ErrorCode = HAL_USART_ERROR_NONE;
00408     husart->State = HAL_USART_STATE_BUSY_TX;
00409
00410     /* Init tickstart for timeout managment*/
00411     tickstart = HAL_GetTick();
00412
00413     husart->TxXferSize = Size;
00414     husart->TxXferCount = Size;
00415
00416     /* Check the remaining data to be sent */
00417     while(husart->TxXferCount > 0)
00418     {
00419       husart->TxXferCount--;
00420       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00421       {
00422         return HAL_TIMEOUT;
00423       }
00424       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00425       {
00426         tmp = (uint16_t*) pTxData;
00427         husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
00428         pTxData += 2;
00429       }
00430       else
00431       {
00432         husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF);
00433       }
00434     }
00435
00436     if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00437     {
00438       return HAL_TIMEOUT;
00439     }
00440
00441     /* At end of Tx process, restore husart->State to Ready */
00442     husart->State = HAL_USART_STATE_READY;
00443
00444     /* Process Unlocked */
00445     __HAL_UNLOCK(husart);
00446
00447     return HAL_OK;
00448   }
00449   else
00450   {
00451     return HAL_BUSY;
00452   }
00453 }
00454
00455 /**
00456   * @brief Receive an amount of data in blocking mode.
00457   * @note  To receive synchronous data, dummy data are simultaneously transmitted.
00458   * @param husart USART handle.
00459   * @param pRxData Pointer to data buffer.
00460   * @param Size Amount of data to be received.
00461   * @param Timeout Timeout duration.
00462   * @retval HAL status
00463   */
00464 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00465 {
00466   uint16_t* tmp;
00467   uint16_t uhMask;
00468   uint32_t tickstart = 0;
00469
00470   if(husart->State == HAL_USART_STATE_READY)
00471   {
00472     if((pRxData == NULL) || (Size == 0))
00473     {
00474       return  HAL_ERROR;
00475     }
00476
00477     /* Process Locked */
00478     __HAL_LOCK(husart);
00479
00480     husart->ErrorCode = HAL_USART_ERROR_NONE;
00481     husart->State = HAL_USART_STATE_BUSY_RX;
00482
00483     /* Init tickstart for timeout managment*/
00484     tickstart = HAL_GetTick();
00485
00486     husart->RxXferSize = Size;
00487     husart->RxXferCount = Size;
00488
00489     /* Computation of USART mask to apply to RDR register */
00490     USART_MASK_COMPUTATION(husart);
00491     uhMask = husart->Mask;
00492
00493     /* as long as data have to be received */
00494     while(husart->RxXferCount > 0)
00495     {
00496       husart->RxXferCount--;
00497
00498       /* Wait until TC flag is set to send dummy byte in order to generate the
00499       * clock for the slave to send data.
00500        * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
00501        * can be written for all the cases. */
00502       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00503       {
00504         return HAL_TIMEOUT;
00505       }
00506       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
00507
00508       /* Wait for RXNE Flag */
00509       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00510       {
00511         return HAL_TIMEOUT;
00512       }
00513
00514       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00515       {
00516         tmp = (uint16_t*) pRxData ;
00517         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
00518         pRxData +=2;
00519       }
00520       else
00521       {
00522         *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
00523       }
00524     }
00525
00526     /* At end of Rx process, restore husart->State to Ready */
00527     husart->State = HAL_USART_STATE_READY;
00528
00529     /* Process Unlocked */
00530     __HAL_UNLOCK(husart);
00531
00532     return HAL_OK;
00533   }
00534   else
00535   {
00536     return HAL_BUSY;
00537   }
00538 }
00539
00540 /**
00541   * @brief  Full-Duplex Send and Receive an amount of data in blocking mode.
00542   * @param  husart USART handle.
00543   * @param  pTxData pointer to TX data buffer.
00544   * @param  pRxData pointer to RX data buffer.
00545   * @param  Size amount of data to be sent (same amount to be received).
00546   * @param  Timeout Timeout duration.
00547   * @retval HAL status
00548   */
00549 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00550 {
00551   uint16_t* tmp;
00552   uint16_t uhMask;
00553   uint32_t tickstart = 0;
00554
00555   if(husart->State == HAL_USART_STATE_READY)
00556   {
00557     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
00558     {
00559       return  HAL_ERROR;
00560     }
00561     /* Process Locked */
00562     __HAL_LOCK(husart);
00563
00564     husart->ErrorCode = HAL_USART_ERROR_NONE;
00565     husart->State = HAL_USART_STATE_BUSY_RX;
00566
00567     /* Init tickstart for timeout managment*/
00568     tickstart = HAL_GetTick();
00569
00570     husart->RxXferSize = Size;
00571     husart->TxXferSize = Size;
00572     husart->TxXferCount = Size;
00573     husart->RxXferCount = Size;
00574
00575     /* Computation of USART mask to apply to RDR register */
00576     USART_MASK_COMPUTATION(husart);
00577     uhMask = husart->Mask;
00578
00579     /* Check the remain data to be sent */
00580     while(husart->TxXferCount > 0)
00581     {
00582       husart->TxXferCount--;
00583       husart->RxXferCount--;
00584
00585       /* Wait until TC flag is set to send data */
00586       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00587       {
00588         return HAL_TIMEOUT;
00589       }
00590       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00591       {
00592         tmp = (uint16_t*) pTxData;
00593         husart->Instance->TDR = (*tmp & uhMask);
00594         pTxData += 2;
00595       }
00596       else
00597       {
00598         husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
00599       }
00600
00601       /* Wait for RXNE Flag */
00602       if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00603       {
00604         return HAL_TIMEOUT;
00605       }
00606
00607       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00608       {
00609         tmp = (uint16_t*) pRxData ;
00610         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
00611         pRxData +=2;
00612       }
00613       else
00614       {
00615         *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
00616       }
00617     }
00618
00619     /* At end of TxRx process, restore husart->State to Ready */
00620     husart->State = HAL_USART_STATE_READY;
00621
00622     /* Process Unlocked */
00623     __HAL_UNLOCK(husart);
00624
00625     return HAL_OK;
00626   }
00627   else
00628   {
00629     return HAL_BUSY;
00630   }
00631 }
00632
00633 /**
00634   * @brief  Send an amount of data in interrupt mode.
00635   * @param  husart USART handle.
00636   * @param  pTxData pointer to data buffer.
00637   * @param  Size amount of data to be sent.
00638   * @retval HAL status
00639   */
00640 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00641 {
00642   if(husart->State == HAL_USART_STATE_READY)
00643   {
00644     if((pTxData == NULL ) || (Size == 0))
00645     {
00646       return HAL_ERROR;
00647     }
00648
00649     /* Process Locked */
00650     __HAL_LOCK(husart);
00651
00652     husart->pTxBuffPtr = pTxData;
00653     husart->TxXferSize = Size;
00654     husart->TxXferCount = Size;
00655
00656     husart->ErrorCode = HAL_USART_ERROR_NONE;
00657     husart->State = HAL_USART_STATE_BUSY_TX;
00658
00659     /* The USART Error Interrupts: (Frame error, noise error, overrun error)
00660     are not managed by the USART Transmit Process to avoid the overrun interrupt
00661     when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
00662     to benefit for the frame error and noise interrupts the usart mode should be
00663     configured only for transmit "USART_MODE_TX" */
00664
00665     /* Process Unlocked */
00666     __HAL_UNLOCK(husart);
00667
00668     /* Enable the USART Transmit Data Register Empty Interrupt */
00669     __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
00670
00671     return HAL_OK;
00672   }
00673   else
00674   {
00675     return HAL_BUSY;
00676   }
00677 }
00678
00679 /**
00680   * @brief  Receive an amount of data in blocking mode.
00681   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
00682   * @param  husart USART handle.
00683   * @param  pRxData pointer to data buffer.
00684   * @param  Size amount of data to be received.
00685   * @retval HAL status
00686   */
00687 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00688 {
00689   if(husart->State == HAL_USART_STATE_READY)
00690   {
00691     if((pRxData == NULL ) || (Size == 0))
00692     {
00693       return HAL_ERROR;
00694     }
00695
00696     /* Process Locked */
00697     __HAL_LOCK(husart);
00698
00699     husart->pRxBuffPtr = pRxData;
00700     husart->RxXferSize = Size;
00701     husart->RxXferCount = Size;
00702
00703     USART_MASK_COMPUTATION(husart);
00704
00705     husart->ErrorCode = HAL_USART_ERROR_NONE;
00706     husart->State = HAL_USART_STATE_BUSY_RX;
00707
00708     /* Process Unlocked */
00709     __HAL_UNLOCK(husart);
00710
00711     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00712     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
00713
00714     /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
00715     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
00716
00717     /* Send dummy byte in order to generate the clock for the Slave to send the next data */
00718     if(husart->Init.WordLength == USART_WORDLENGTH_9B)
00719     {
00720       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FF);
00721     }
00722     else
00723     {
00724       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
00725     }
00726
00727     return HAL_OK;
00728   }
00729   else
00730   {
00731     return HAL_BUSY;
00732   }
00733 }
00734
00735 /**
00736   * @brief  Full-Duplex Send and Receive an amount of data in interrupt mode.
00737   * @param  husart USART handle.
00738   * @param  pTxData pointer to TX data buffer.
00739   * @param  pRxData pointer to RX data buffer.
00740   * @param  Size amount of data to be sent (same amount to be received).
00741   * @retval HAL status
00742   */
00743 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
00744 {
00745
00746   if(husart->State == HAL_USART_STATE_READY)
00747   {
00748     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
00749     {
00750       return HAL_ERROR;
00751     }
00752     /* Process Locked */
00753     __HAL_LOCK(husart);
00754
00755     husart->pRxBuffPtr = pRxData;
00756     husart->RxXferSize = Size;
00757     husart->RxXferCount = Size;
00758     husart->pTxBuffPtr = pTxData;
00759     husart->TxXferSize = Size;
00760     husart->TxXferCount = Size;
00761
00762     /* Computation of USART mask to apply to RDR register */
00763     USART_MASK_COMPUTATION(husart);
00764
00765     husart->ErrorCode = HAL_USART_ERROR_NONE;
00766     husart->State = HAL_USART_STATE_BUSY_TX_RX;
00767
00768     /* Process Unlocked */
00769     __HAL_UNLOCK(husart);
00770
00771     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00772     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
00773
00774     /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
00775     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
00776
00777     /* Enable the USART Transmit Data Register Empty Interrupt */
00778     SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
00779
00780     return HAL_OK;
00781   }
00782   else
00783   {
00784     return HAL_BUSY;
00785   }
00786 }
00787
00788 /**
00789   * @brief  Send an amount of data in DMA mode.
00790   * @param  husart USART handle.
00791   * @param  pTxData pointer to data buffer.
00792   * @param  Size amount of data to be sent.
00793   * @retval HAL status
00794   */
00795 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00796 {
00797   uint32_t *tmp;
00798
00799   if(husart->State == HAL_USART_STATE_READY)
00800   {
00801     if((pTxData == NULL ) || (Size == 0))
00802     {
00803       return HAL_ERROR;
00804     }
00805     /* Process Locked */
00806     __HAL_LOCK(husart);
00807
00808     husart->pTxBuffPtr = pTxData;
00809     husart->TxXferSize = Size;
00810     husart->TxXferCount = Size;
00811
00812     husart->ErrorCode = HAL_USART_ERROR_NONE;
00813     husart->State = HAL_USART_STATE_BUSY_TX;
00814
00815     /* Set the USART DMA transfer complete callback */
00816     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
00817
00818     /* Set the USART DMA Half transfer complete callback */
00819     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
00820
00821     /* Set the DMA error callback */
00822     husart->hdmatx->XferErrorCallback = USART_DMAError;
00823
00824     /* Enable the USART transmit DMA channel */
00825     tmp = (uint32_t*)&pTxData;
00826     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
00827
00828     /* Clear the TC flag in the ICR register */
00829     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
00830
00831     /* Process Unlocked */
00832     __HAL_UNLOCK(husart);
00833
00834     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00835        in the USART CR3 register */
00836     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
00837
00838     return HAL_OK;
00839   }
00840   else
00841   {
00842     return HAL_BUSY;
00843   }
00844 }
00845
00846 /**
00847   * @brief  Receive an amount of data in DMA mode.
00848   * @param  husart USART handle.
00849   * @param  pRxData pointer to data buffer.
00850   * @param  Size amount of data to be received.
00851   * @note   When the USART parity is enabled (PCE = 1), the received data contain
00852   *         the parity bit (MSB position).
00853   * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
00854   * @retval HAL status
00855   */
00856 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00857 {
00858   uint32_t *tmp;
00859
00860   /* Check that a Rx process is not already ongoing */
00861   if(husart->State == HAL_USART_STATE_READY)
00862   {
00863     if((pRxData == NULL ) || (Size == 0))
00864     {
00865       return HAL_ERROR;
00866     }
00867
00868     /* Process Locked */
00869     __HAL_LOCK(husart);
00870
00871     husart->pRxBuffPtr = pRxData;
00872     husart->RxXferSize = Size;
00873     husart->pTxBuffPtr = pRxData;
00874     husart->TxXferSize = Size;
00875
00876     husart->ErrorCode = HAL_USART_ERROR_NONE;
00877     husart->State = HAL_USART_STATE_BUSY_RX;
00878
00879     /* Set the USART DMA Rx transfer complete callback */
00880     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
00881
00882     /* Set the USART DMA Half transfer complete callback */
00883     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
00884
00885     /* Set the USART DMA Rx transfer error callback */
00886     husart->hdmarx->XferErrorCallback = USART_DMAError;
00887
00888     /* Enable the USART receive DMA channel */
00889     tmp = (uint32_t*)&pRxData;
00890     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
00891
00892     /* Enable the USART transmit DMA channel: the transmit channel is used in order
00893        to generate in the non-blocking mode the clock to the slave device,
00894        this mode isn't a simplex receive mode but a full-duplex receive mode */
00895     tmp = (uint32_t*)&pRxData;
00896     /* Set the USART DMA Tx Complete and Error callback to Null */
00897     husart->hdmatx->XferErrorCallback = NULL;
00898     husart->hdmatx->XferHalfCpltCallback = NULL;
00899     husart->hdmatx->XferCpltCallback = NULL;
00900     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
00901
00902     /* Process Unlocked */
00903     __HAL_UNLOCK(husart);
00904
00905     /* Enable the USART Parity Error Interrupt */
00906     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
00907
00908     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00909     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
00910
00911     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00912        in the USART CR3 register */
00913     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
00914
00915     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00916        in the USART CR3 register */
00917     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
00918
00919     return HAL_OK;
00920   }
00921   else
00922   {
00923     return HAL_BUSY;
00924   }
00925 }
00926
00927 /**
00928   * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode.
00929   * @param  husart USART handle.
00930   * @param  pTxData pointer to TX data buffer.
00931   * @param  pRxData pointer to RX data buffer.
00932   * @param  Size amount of data to be received/sent.
00933   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
00934   * @retval HAL status
00935   */
00936 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
00937 {
00938   uint32_t *tmp;
00939
00940   if(husart->State == HAL_USART_STATE_READY)
00941   {
00942     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
00943     {
00944       return HAL_ERROR;
00945     }
00946     /* Process Locked */
00947     __HAL_LOCK(husart);
00948
00949     husart->pRxBuffPtr = pRxData;
00950     husart->RxXferSize = Size;
00951     husart->pTxBuffPtr = pTxData;
00952     husart->TxXferSize = Size;
00953
00954     husart->ErrorCode = HAL_USART_ERROR_NONE;
00955     husart->State = HAL_USART_STATE_BUSY_TX_RX;
00956
00957     /* Set the USART DMA Rx transfer complete callback */
00958     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
00959
00960     /* Set the USART DMA Half transfer complete callback */
00961     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
00962
00963     /* Set the USART DMA Tx transfer complete callback */
00964     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
00965
00966     /* Set the USART DMA Half transfer complete callback */
00967     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
00968
00969     /* Set the USART DMA Tx transfer error callback */
00970     husart->hdmatx->XferErrorCallback = USART_DMAError;
00971
00972     /* Set the USART DMA Rx transfer error callback */
00973     husart->hdmarx->XferErrorCallback = USART_DMAError;
00974
00975     /* Enable the USART receive DMA channel */
00976     tmp = (uint32_t*)&pRxData;
00977     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
00978
00979     /* Enable the USART transmit DMA channel */
00980     tmp = (uint32_t*)&pTxData;
00981     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
00982
00983     /* Process Unlocked */
00984     __HAL_UNLOCK(husart);
00985
00986     /* Enable the USART Parity Error Interrupt */
00987     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
00988
00989     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00990     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
00991
00992     /* Clear the TC flag in the ICR register */
00993     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
00994
00995     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00996        in the USART CR3 register */
00997     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
00998
00999     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01000        in the USART CR3 register */
01001     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01002
01003     return HAL_OK;
01004   }
01005   else
01006   {
01007     return HAL_BUSY;
01008   }
01009 }
01010
01011 /**
01012   * @brief  Pause the DMA Transfer.
01013   * @param  husart USART handle.
01014   * @retval HAL status
01015   */
01016 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
01017 {
01018   /* Process Locked */
01019   __HAL_LOCK(husart);
01020
01021   if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
01022       (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
01023   {
01024     /* Disable the USART DMA Tx request */
01025     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01026   }
01027   else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
01028            (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
01029   {
01030     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01031     {
01032       /* Disable the USART DMA Tx request */
01033       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01034     }
01035     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01036     {
01037       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01038       CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01039       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01040
01041       /* Disable the USART DMA Rx request */
01042       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01043     }
01044   }
01045
01046   /* Process Unlocked */
01047   __HAL_UNLOCK(husart);
01048
01049   return HAL_OK;
01050 }
01051
01052 /**
01053   * @brief  Resume the DMA Transfer.
01054   * @param  husart USART handle.
01055   * @retval HAL status
01056   */
01057 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
01058 {
01059   /* Process Locked */
01060   __HAL_LOCK(husart);
01061
01062   if(husart->State == HAL_USART_STATE_BUSY_TX)
01063   {
01064     /* Enable the USART DMA Tx request */
01065     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01066   }
01067   else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
01068            (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
01069   {
01070     /* Clear the Overrun flag before resuming the Rx transfer*/
01071     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
01072
01073     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01074     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01075     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01076
01077     /* Enable the USART DMA Rx request  before the DMA Tx request */
01078     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01079
01080     /* Enable the USART DMA Tx request */
01081     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01082   }
01083
01084   /* Process Unlocked */
01085   __HAL_UNLOCK(husart);
01086
01087   return HAL_OK;
01088 }
01089
01090 /**
01091   * @brief  Stop the DMA Transfer.
01092   * @param  husart USART handle.
01093   * @retval HAL status
01094   */
01095 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
01096 {
01097   /* The Lock is not implemented on this API to allow the user application
01098      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
01099      HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
01100      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01101      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01102      the stream and the corresponding call back is executed. */
01103
01104   /* Disable the USART Tx/Rx DMA requests */
01105   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01106   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01107
01108   /* Abort the USART DMA tx channel */
01109   if(husart->hdmatx != NULL)
01110   {
01111     HAL_DMA_Abort(husart->hdmatx);
01112   }
01113   /* Abort the USART DMA rx channel */
01114   if(husart->hdmarx != NULL)
01115   {
01116     HAL_DMA_Abort(husart->hdmarx);
01117   }
01118
01119   USART_EndTransfer(husart);
01120   husart->State = HAL_USART_STATE_READY;
01121
01122   return HAL_OK;
01123 }
01124
01125 /**
01126   * @brief  Handle USART interrupt request.
01127   * @param  husart USART handle.
01128   * @retval None
01129   */
01130 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
01131 {
01132   uint32_t isrflags   = READ_REG(husart->Instance->ISR);
01133   uint32_t cr1its     = READ_REG(husart->Instance->CR1);
01134   uint32_t cr3its;
01135   uint32_t errorflags;
01136
01137   /* If no error occurs */
01138   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01139   if (errorflags == RESET)
01140   {
01141     /* USART in mode Receiver ---------------------------------------------------*/
01142     if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01143     {
01144       if(husart->State == HAL_USART_STATE_BUSY_RX)
01145       {
01146         USART_Receive_IT(husart);
01147       }
01148       else
01149       {
01150         USART_TransmitReceive_IT(husart);
01151       }
01152       return;
01153     }
01154   }
01155
01156   /* If some errors occur */
01157   cr3its = READ_REG(husart->Instance->CR3);
01158   if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
01159   {
01160     /* USART parity error interrupt occurred -------------------------------------*/
01161     if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01162     {
01163       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
01164
01165       husart->ErrorCode |= HAL_USART_ERROR_PE;
01166     }
01167
01168     /* USART frame error interrupt occurred --------------------------------------*/
01169     if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01170     {
01171       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
01172
01173       husart->ErrorCode |= HAL_USART_ERROR_FE;
01174     }
01175
01176     /* USART noise error interrupt occurred --------------------------------------*/
01177     if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01178     {
01179       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
01180
01181       husart->ErrorCode |= HAL_USART_ERROR_NE;
01182     }
01183
01184     /* USART Over-Run interrupt occurred -----------------------------------------*/
01185     if(((isrflags & USART_ISR_ORE) != RESET) &&
01186        (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
01187     {
01188       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
01189
01190       husart->ErrorCode |= HAL_USART_ERROR_ORE;
01191     }
01192
01193     /* Call USART Error Call back function if need be --------------------------*/
01194     if(husart->ErrorCode != HAL_USART_ERROR_NONE)
01195     {
01196       /* USART in mode Receiver ---------------------------------------------------*/
01197       if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01198       {
01199         if(husart->State == HAL_USART_STATE_BUSY_RX)
01200         {
01201           USART_Receive_IT(husart);
01202         }
01203         else
01204         {
01205           USART_TransmitReceive_IT(husart);
01206         }
01207       }
01208
01209       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01210          consider error as blocking */
01211       if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
01212           (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
01213       {
01214         /* Blocking error : transfer is aborted
01215            Set the USART state ready to be able to start again the process,
01216            Disable Interrupts, and disable DMA requests, if ongoing */
01217         USART_EndTransfer(husart);
01218
01219         /* Disable the USART DMA Rx request if enabled */
01220         if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01221         {
01222           CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
01223
01224           /* Abort the USART DMA Tx channel */
01225           if(husart->hdmatx != NULL)
01226           {
01227             /* Set the USART Tx DMA Abort callback to NULL : no callback
01228                executed at end of DMA abort procedure */
01229             husart->hdmatx->XferAbortCallback = NULL;
01230
01231             /* Abort DMA TX */
01232             HAL_DMA_Abort_IT(husart->hdmatx);
01233           }
01234
01235           /* Abort the USART DMA Rx channel */
01236           if(husart->hdmarx != NULL)
01237           {
01238             /* Set the USART Rx DMA Abort callback :
01239                will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
01240             husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
01241
01242             /* Abort DMA RX */
01243             if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
01244             {
01245               /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
01246               husart->hdmarx->XferAbortCallback(husart->hdmarx);
01247             }
01248           }
01249           else
01250           {
01251             /* Call user error callback */
01252             HAL_USART_ErrorCallback(husart);
01253           }
01254         }
01255         else
01256         {
01257           /* Call user error callback */
01258           HAL_USART_ErrorCallback(husart);
01259         }
01260       }
01261       else
01262       {
01263         /* Non Blocking error : transfer could go on.
01264            Error is notified to user through user error callback */
01265         HAL_USART_ErrorCallback(husart);
01266         husart->ErrorCode = HAL_USART_ERROR_NONE;
01267       }
01268     }
01269     return;
01270
01271   } /* End if some error occurs */
01272
01273
01274   /* USART in mode Transmitter ------------------------------------------------*/
01275   if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01276   {
01277     if(husart->State == HAL_USART_STATE_BUSY_TX)
01278     {
01279       USART_Transmit_IT(husart);
01280     }
01281     else
01282     {
01283       USART_TransmitReceive_IT(husart);
01284     }
01285     return;
01286   }
01287
01288   /* USART in mode Transmitter (transmission end) -----------------------------*/
01289   if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01290   {
01291     USART_EndTransmit_IT(husart);
01292     return;
01293   }
01294
01295 }
01296
01297 /**
01298   * @brief Tx Transfer completed callback.
01299   * @param husart: USART handle.
01300   * @retval None
01301   */
01302 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
01303 {
01304   /* Prevent unused argument(s) compilation warning */
01305   UNUSED(husart);
01306
01307   /* NOTE : This function should not be modified, when the callback is needed,
01308             the HAL_USART_TxCpltCallback can be implemented in the user file.
01309    */
01310 }
01311
01312 /**
01313   * @brief  Tx Half Transfer completed callback.
01314   * @param husart: USART handle.
01315   * @retval None
01316   */
01317 __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
01318 {
01319   /* Prevent unused argument(s) compilation warning */
01320   UNUSED(husart);
01321
01322   /* NOTE: This function should not be modified, when the callback is needed,
01323            the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
01324    */
01325 }
01326
01327 /**
01328   * @brief  Rx Transfer completed callback.
01329   * @param husart: USART handle.
01330   * @retval None
01331   */
01332 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
01333 {
01334   /* Prevent unused argument(s) compilation warning */
01335   UNUSED(husart);
01336
01337   /* NOTE: This function should not be modified, when the callback is needed,
01338            the HAL_USART_RxCpltCallback can be implemented in the user file.
01339    */
01340 }
01341
01342 /**
01343   * @brief Rx Half Transfer completed callback.
01344   * @param husart: USART handle.
01345   * @retval None
01346   */
01347 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
01348 {
01349   /* Prevent unused argument(s) compilation warning */
01350   UNUSED(husart);
01351
01352   /* NOTE : This function should not be modified, when the callback is needed,
01353             the HAL_USART_RxHalfCpltCallback can be implemented in the user file
01354    */
01355 }
01356
01357 /**
01358   * @brief Tx/Rx Transfers completed callback for the non-blocking process.
01359   * @param husart: USART handle.
01360   * @retval None
01361   */
01362 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
01363 {
01364   /* Prevent unused argument(s) compilation warning */
01365   UNUSED(husart);
01366
01367   /* NOTE : This function should not be modified, when the callback is needed,
01368             the HAL_USART_TxRxCpltCallback can be implemented in the user file
01369    */
01370 }
01371
01372 /**
01373   * @brief USART error callback.
01374   * @param husart: USART handle.
01375   * @retval None
01376   */
01377 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
01378 {
01379   /* Prevent unused argument(s) compilation warning */
01380   UNUSED(husart);
01381
01382   /* NOTE : This function should not be modified, when the callback is needed,
01383             the HAL_USART_ErrorCallback can be implemented in the user file.
01384    */
01385 }
01386
01387 /**
01388   * @}
01389   */
01390
01391 /** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
01392  *  @brief   USART Peripheral State and Error functions
01393  *
01394 @verbatim
01395   ==============================================================================
01396             ##### Peripheral State and Error functions #####
01397   ==============================================================================
01398     [..]
01399     This subsection provides functions allowing to :
01400       (+) Return the USART handle state
01401       (+) Return the USART handle error code
01402
01403 @endverbatim
01404   * @{
01405   */
01406
01407
01408 /**
01409   * @brief Return the USART handle state.
01410   * @param husart : pointer to a USART_HandleTypeDef structure that contains
01411   *              the configuration information for the specified USART.
01412   * @retval USART handle state
01413   */
01414 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
01415 {
01416   return husart->State;
01417 }
01418
01419 /**
01420   * @brief Return the USART error code.
01421   * @param husart : pointer to a USART_HandleTypeDef structure that contains
01422   *              the configuration information for the specified USART.
01423   * @retval USART handle Error Code
01424   */
01425 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
01426 {
01427   return husart->ErrorCode;
01428 }
01429
01430 /**
01431   * @}
01432   */
01433
01434 /**
01435   * @}
01436   */
01437
01438 /** @defgroup USART_Private_Functions USART Private Functions
01439  * @{
01440  */
01441
01442 /**
01443   * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
01444   * @param  husart USART handle.
01445   * @retval None
01446   */
01447 static void USART_EndTransfer(USART_HandleTypeDef *husart)
01448 {
01449   /* Disable TXEIE and TCIE interrupts */
01450   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01451   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE));
01452   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01453
01454   /* At end of process, restore husart->State to Ready */
01455   husart->State = HAL_USART_STATE_READY;
01456 }
01457
01458 /**
01459   * @brief  DMA USART transmit process complete callback.
01460   * @param  hdma DMA handle.
01461   * @retval None
01462   */
01463 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01464 {
01465   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01466
01467   /* DMA Normal mode */
01468   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
01469   {
01470     husart->TxXferCount = 0;
01471
01472     if(husart->State == HAL_USART_STATE_BUSY_TX)
01473     {
01474       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01475          in the USART CR3 register */
01476       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01477
01478       /* Enable the USART Transmit Complete Interrupt */
01479       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
01480     }
01481   }
01482   /* DMA Circular mode */
01483   else
01484   {
01485     if(husart->State == HAL_USART_STATE_BUSY_TX)
01486     {
01487     HAL_USART_TxCpltCallback(husart);
01488    }
01489  }
01490 }
01491
01492 /**
01493   * @brief  DMA USART transmit process half complete callback.
01494   * @param  hdma DMA handle.
01495   * @retval None
01496   */
01497 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01498 {
01499   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01500
01501   HAL_USART_TxHalfCpltCallback(husart);
01502 }
01503
01504 /**
01505   * @brief  DMA USART receive process complete callback.
01506   * @param  hdma DMA handle.
01507   * @retval None
01508   */
01509 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01510 {
01511   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01512
01513   /* DMA Normal mode */
01514   if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
01515   {
01516     husart->RxXferCount = 0;
01517
01518     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01519     CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01520     CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01521
01522     /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
01523        in USART CR3 register */
01524     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01525     /* similarly, disable the DMA TX transfer that was started to provide the
01526        clock to the slave device */
01527     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01528
01529     if(husart->State == HAL_USART_STATE_BUSY_RX)
01530     {
01531       HAL_USART_RxCpltCallback(husart);
01532     }
01533     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01534     else
01535     {
01536       HAL_USART_TxRxCpltCallback(husart);
01537     }
01538     husart->State= HAL_USART_STATE_READY;
01539   }
01540   /* DMA circular mode */
01541   else
01542   {
01543     if(husart->State == HAL_USART_STATE_BUSY_RX)
01544     {
01545       HAL_USART_RxCpltCallback(husart);
01546     }
01547     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01548     else
01549     {
01550       HAL_USART_TxRxCpltCallback(husart);
01551     }
01552   }
01553
01554 }
01555
01556 /**
01557   * @brief  DMA USART receive process half complete callback.
01558   * @param  hdma DMA handle.
01559   * @retval None
01560   */
01561 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01562 {
01563   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01564
01565   HAL_USART_RxHalfCpltCallback(husart);
01566 }
01567
01568 /**
01569   * @brief DMA USART communication error callback.
01570   * @param  hdma: DMA handle.
01571   * @retval None
01572   */
01573 static void USART_DMAError(DMA_HandleTypeDef *hdma)
01574 {
01575   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01576
01577   husart->RxXferCount = 0;
01578   husart->TxXferCount = 0;
01579   USART_EndTransfer(husart);
01580
01581   husart->ErrorCode |= HAL_USART_ERROR_DMA;
01582   husart->State= HAL_USART_STATE_READY;
01583
01584   HAL_USART_ErrorCallback(husart);
01585 }
01586
01587 /**
01588   * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
01589   *         (To be called at end of DMA Abort procedure following error occurrence).
01590   * @param  hdma DMA handle.
01591   * @retval None
01592   */
01593 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
01594 {
01595   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
01596   husart->RxXferCount = 0;
01597   husart->TxXferCount = 0;
01598
01599   HAL_USART_ErrorCallback(husart);
01600 }
01601
01602 /**
01603   * @brief  Handle USART Communication Timeout.
01604   * @param  husart USART handle.
01605   * @param  Flag Specifies the USART flag to check.
01606   * @param  Status the Flag status (SET or RESET).
01607   * @param  Tickstart Tick start value
01608   * @param  Timeout timeout duration.
01609   * @retval HAL status
01610   */
01611 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01612 {
01613   /* Wait until flag is set */
01614   while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
01615   {
01616     /* Check for the Timeout */
01617     if(Timeout != HAL_MAX_DELAY)
01618     {
01619       if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
01620       {
01621         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01622         CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
01623         CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01624
01625         husart->State= HAL_USART_STATE_READY;
01626
01627         /* Process Unlocked */
01628         __HAL_UNLOCK(husart);
01629
01630         return HAL_TIMEOUT;
01631       }
01632     }
01633   }
01634   return HAL_OK;
01635 }
01636
01637 /**
01638   * @brief Configure the USART peripheral.
01639   * @param husart: USART handle.
01640   * @retval HAL status
01641   */
01642 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
01643 {
01644   uint32_t tmpreg                      = 0x0;
01645   USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
01646   HAL_StatusTypeDef ret                = HAL_OK;
01647   uint16_t brrtemp                     = 0x0000;
01648   uint16_t usartdiv                    = 0x0000;
01649
01650   /* Check the parameters */
01651   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
01652   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
01653   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
01654   assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
01655   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
01656   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
01657   assert_param(IS_USART_PARITY(husart->Init.Parity));
01658   assert_param(IS_USART_MODE(husart->Init.Mode));
01659
01660
01661   /*-------------------------- USART CR1 Configuration -----------------------*/
01662    /* Clear M, PCE, PS, TE and RE bits and configure
01663    *  the USART Word Length, Parity and Mode:
01664    *  set the M bits according to husart->Init.WordLength value
01665    *  set PCE and PS bits according to husart->Init.Parity value
01666    *  set TE and RE bits according to husart->Init.Mode value
01667    *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8)  */
01668   tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
01669   MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
01670
01671   /*---------------------------- USART CR2 Configuration ---------------------*/
01672   /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
01673    * set CPOL bit according to husart->Init.CLKPolarity value
01674    * set CPHA bit according to husart->Init.CLKPhase value
01675    * set LBCL bit according to husart->Init.CLKLastBit value
01676    * set STOP[13:12] bits according to husart->Init.StopBits value */
01677   tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
01678   tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
01679   tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
01680   MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
01681
01682   /*-------------------------- USART CR3 Configuration -----------------------*/
01683   /* no CR3 register configuration                                            */
01684
01685   /*-------------------------- USART BRR Configuration -----------------------*/
01686   /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */
01687   USART_GETCLOCKSOURCE(husart, clocksource);
01688   switch (clocksource)
01689   {
01690     case USART_CLOCKSOURCE_PCLK1:
01691       usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
01692       break;
01693     case USART_CLOCKSOURCE_PCLK2:
01694       usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
01695       break;
01696     case USART_CLOCKSOURCE_HSI:
01697       usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
01698       break;
01699     case USART_CLOCKSOURCE_SYSCLK:
01700       usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
01701       break;
01702     case USART_CLOCKSOURCE_LSE:
01703       usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
01704       break;
01705     case USART_CLOCKSOURCE_UNDEFINED:
01706     default:
01707       ret = HAL_ERROR;
01708       break;
01709   }
01710
01711   brrtemp = usartdiv & 0xFFF0;
01712   brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
01713   husart->Instance->BRR = brrtemp;
01714
01715   return ret;
01716 }
01717
01718 /**
01719   * @brief Check the USART Idle State.
01720   * @param husart: USART handle.
01721   * @retval HAL status
01722   */
01723 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
01724 {
01725   uint32_t tickstart = 0;
01726
01727   /* Initialize the USART ErrorCode */
01728   husart->ErrorCode = HAL_USART_ERROR_NONE;
01729
01730   /* Init tickstart for timeout managment*/
01731   tickstart = HAL_GetTick();
01732
01733   /* Check if the Transmitter is enabled */
01734   if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
01735   {
01736     /* Wait until TEACK flag is set */
01737     if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
01738     {
01739       /* Timeout occurred */
01740       return HAL_TIMEOUT;
01741     }
01742   }
01743   /* Check if the Receiver is enabled */
01744   if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
01745   {
01746     /* Wait until REACK flag is set */
01747     if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
01748     {
01749       /* Timeout occurred */
01750       return HAL_TIMEOUT;
01751     }
01752   }
01753
01754   /* Initialize the USART state*/
01755   husart->State= HAL_USART_STATE_READY;
01756
01757   /* Process Unlocked */
01758   __HAL_UNLOCK(husart);
01759
01760   return HAL_OK;
01761 }
01762
01763 /**
01764   * @brief  Simplex send an amount of data in non-blocking mode.
01765   * @note   Function called under interruption only, once
01766   *         interruptions have been enabled by HAL_USART_Transmit_IT().
01767   * @note   The USART errors are not managed to avoid the overrun error.
01768   * @param  husart USART handle.
01769   * @retval HAL status
01770   */
01771 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
01772 {
01773   uint16_t* tmp;
01774
01775   /* Check that a Tx process is ongoing */
01776   if(husart->State == HAL_USART_STATE_BUSY_TX)
01777   {
01778
01779     if(husart->TxXferCount == 0)
01780     {
01781       /* Disable the USART Transmit data register empty interrupt */
01782       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01783
01784       /* Enable the USART Transmit Complete Interrupt */
01785       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
01786
01787       return HAL_OK;
01788     }
01789     else
01790     {
01791       if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01792       {
01793         tmp = (uint16_t*) husart->pTxBuffPtr;
01794         husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
01795         husart->pTxBuffPtr += 2;
01796       }
01797       else
01798       {
01799         husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
01800       }
01801
01802       husart->TxXferCount--;
01803
01804       return HAL_OK;
01805     }
01806   }
01807   else
01808   {
01809     return HAL_BUSY;
01810   }
01811 }
01812
01813
01814 /**
01815   * @brief  Wraps up transmission in non-blocking mode.
01816   * @param  husart Pointer to a USART_HandleTypeDef structure that contains
01817   *                the configuration information for the specified USART module.
01818   * @retval HAL status
01819   */
01820 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
01821 {
01822   /* Disable the USART Transmit Complete Interrupt */
01823   __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
01824
01825   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01826   __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01827
01828   /* Tx process is ended, restore husart->State to Ready */
01829   husart->State = HAL_USART_STATE_READY;
01830
01831   HAL_USART_TxCpltCallback(husart);
01832
01833   return HAL_OK;
01834 }
01835
01836
01837 /**
01838   * @brief  Simplex receive an amount of data in non-blocking mode.
01839   * @note   Function called under interruption only, once
01840   *         interruptions have been enabled by HAL_USART_Receive_IT().
01841   * @param  husart USART handle
01842   * @retval HAL status
01843   */
01844 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
01845 {
01846   uint16_t* tmp;
01847   uint16_t uhMask = husart->Mask;
01848
01849   if(husart->State == HAL_USART_STATE_BUSY_RX)
01850   {
01851
01852     if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01853     {
01854       tmp = (uint16_t*) husart->pRxBuffPtr;
01855       *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
01856       husart->pRxBuffPtr += 2;
01857     }
01858     else
01859     {
01860       *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
01861     }
01862     /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
01863     husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
01864
01865     if(--husart->RxXferCount == 0)
01866     {
01867       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
01868       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01869
01870       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01871       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01872
01873       /* Rx process is completed, restore husart->State to Ready */
01874       husart->State = HAL_USART_STATE_READY;
01875
01876       HAL_USART_RxCpltCallback(husart);
01877
01878       return HAL_OK;
01879     }
01880
01881     return HAL_OK;
01882   }
01883   else
01884   {
01885     return HAL_BUSY;
01886   }
01887 }
01888
01889 /**
01890   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
01891   * @note   Function called under interruption only, once
01892   *         interruptions have been enabled by HAL_USART_TransmitReceive_IT().
01893   * @param husart: USART handle.
01894   * @retval HAL status
01895   */
01896 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
01897 {
01898   uint16_t* tmp;
01899   uint16_t uhMask = husart->Mask;
01900
01901   if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
01902   {
01903
01904     if(husart->TxXferCount != 0x00)
01905     {
01906       if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
01907       {
01908         if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01909         {
01910           tmp = (uint16_t*) husart->pTxBuffPtr;
01911           husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
01912           husart->pTxBuffPtr += 2;
01913         }
01914         else
01915         {
01916           husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
01917         }
01918         husart->TxXferCount--;
01919
01920         /* Check the latest data transmitted */
01921         if(husart->TxXferCount == 0)
01922         {
01923            __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01924         }
01925       }
01926     }
01927
01928     if(husart->RxXferCount != 0x00)
01929     {
01930       if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
01931       {
01932         if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01933         {
01934           tmp = (uint16_t*) husart->pRxBuffPtr;
01935           *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
01936           husart->pRxBuffPtr += 2;
01937         }
01938         else
01939         {
01940           *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
01941         }
01942         husart->RxXferCount--;
01943       }
01944     }
01945
01946     /* Check the latest data received */
01947     if(husart->RxXferCount == 0)
01948     {
01949       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
01950       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01951
01952       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01953       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01954
01955       /* Rx process is completed, restore husart->State to Ready */
01956       husart->State = HAL_USART_STATE_READY;
01957
01958       HAL_USART_TxRxCpltCallback(husart);
01959
01960       return HAL_OK;
01961     }
01962
01963     return HAL_OK;
01964   }
01965   else
01966   {
01967     return HAL_BUSY;
01968   }
01969 }
01970
01971 /**
01972   * @}
01973   */
01974
01975 #endif /* HAL_USART_MODULE_ENABLED */
01976 /**
01977   * @}
01978   */
01979
01980 /**
01981   * @}
01982   */
01983
01984 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_usart.h Source File

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stm32l4xx_hal_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_usart.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of USART HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_USART_H
00040 #define __STM32L4xx_HAL_USART_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup USART
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup USART_Exported_Types USART Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief USART Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
00068                                            The baud rate is computed using the following formula:
00069                                               Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
00070
00071   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00072                                            This parameter can be a value of @ref USARTEx_Word_Length. */
00073
00074   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00075                                            This parameter can be a value of @ref USART_Stop_Bits. */
00076
00077   uint32_t Parity;                   /*!< Specifies the parity mode.
00078                                            This parameter can be a value of @ref USART_Parity
00079                                            @note When parity is enabled, the computed parity is inserted
00080                                                  at the MSB position of the transmitted data (9th bit when
00081                                                  the word length is set to 9 data bits; 8th bit when the
00082                                                  word length is set to 8 data bits). */
00083
00084   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00085                                            This parameter can be a value of @ref USART_Mode. */
00086
00087   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00088                                            This parameter can be a value of @ref USART_Clock_Polarity. */
00089
00090   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00091                                            This parameter can be a value of @ref USART_Clock_Phase. */
00092
00093   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00094                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00095                                            This parameter can be a value of @ref USART_Last_Bit. */
00096 }USART_InitTypeDef;
00097
00098 /**
00099   * @brief HAL USART State structures definition
00100   */
00101 typedef enum
00102 {
00103   HAL_USART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized                  */
00104   HAL_USART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use       */
00105   HAL_USART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                 */
00106   HAL_USART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing           */
00107   HAL_USART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing              */
00108   HAL_USART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission Reception process is ongoing */
00109   HAL_USART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                  */
00110   HAL_USART_STATE_ERROR             = 0x04     /*!< Error                                          */
00111 }HAL_USART_StateTypeDef;
00112
00113 /**
00114   * @brief  HAL USART Error Code structure definition
00115   */
00116 typedef enum
00117 {
00118   HAL_USART_ERROR_NONE      = 0x00,    /*!< No error            */
00119   HAL_USART_ERROR_PE        = 0x01,    /*!< Parity error        */
00120   HAL_USART_ERROR_NE        = 0x02,    /*!< Noise error         */
00121   HAL_USART_ERROR_FE        = 0x04,    /*!< frame error         */
00122   HAL_USART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
00123   HAL_USART_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
00124 }HAL_USART_ErrorTypeDef;
00125
00126 /**
00127   * @brief  USART clock sources definitions
00128   */
00129 typedef enum
00130 {
00131   USART_CLOCKSOURCE_PCLK1      = 0x00,    /*!< PCLK1 clock source     */
00132   USART_CLOCKSOURCE_PCLK2      = 0x01,    /*!< PCLK2 clock source     */
00133   USART_CLOCKSOURCE_HSI        = 0x02,    /*!< HSI clock source       */
00134   USART_CLOCKSOURCE_SYSCLK     = 0x04,    /*!< SYSCLK clock source    */
00135   USART_CLOCKSOURCE_LSE        = 0x08,    /*!< LSE clock source       */
00136   USART_CLOCKSOURCE_UNDEFINED  = 0x10     /*!< Undefined clock source */
00137 }USART_ClockSourceTypeDef;
00138
00139
00140 /**
00141   * @brief  USART handle Structure definition
00142   */
00143 typedef struct
00144 {
00145   USART_TypeDef                 *Instance;        /*!<  USART registers base address        */
00146
00147   USART_InitTypeDef             Init;             /*!< USART communication parameters      */
00148
00149   uint8_t                       *pTxBuffPtr;      /*!< Pointer to USART Tx transfer Buffer */
00150
00151   uint16_t                      TxXferSize;       /*!< USART Tx Transfer size              */
00152
00153   uint16_t                      TxXferCount;      /*!< USART Tx Transfer Counter           */
00154
00155   uint8_t                       *pRxBuffPtr;      /*!< Pointer to USART Rx transfer Buffer */
00156
00157   uint16_t                      RxXferSize;       /*!< USART Rx Transfer size              */
00158
00159   uint16_t                      RxXferCount;      /*!< USART Rx Transfer Counter           */
00160
00161   uint16_t                      Mask;             /*!< USART Rx RDR register mask          */
00162
00163   DMA_HandleTypeDef             *hdmatx;          /*!< USART Tx DMA Handle parameters      */
00164
00165   DMA_HandleTypeDef             *hdmarx;          /*!< USART Rx DMA Handle parameters      */
00166
00167   HAL_LockTypeDef               Lock;            /*!<  Locking object                      */
00168
00169   __IO HAL_USART_StateTypeDef   State;           /*!< USART communication state           */
00170
00171   __IO uint32_t                 ErrorCode;       /*!< USART Error code                    */
00172
00173 }USART_HandleTypeDef;
00174
00175 /**
00176   * @}
00177   */
00178
00179 /* Exported constants --------------------------------------------------------*/
00180 /** @defgroup USART_Exported_Constants USART Exported Constants
00181   * @{
00182   */
00183
00184 /** @defgroup USART_Stop_Bits  USART Number of Stop Bits
00185   * @{
00186   */
00187 #define USART_STOPBITS_0_5                   USART_CR2_STOP_0                     /*!< USART frame with 0.5 stop bit  */
00188 #define USART_STOPBITS_1                   ((uint32_t)0x00000000)                 /*!< USART frame with 1 stop bit    */
00189 #define USART_STOPBITS_1_5                  (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
00190 #define USART_STOPBITS_2                     USART_CR2_STOP_1                     /*!< USART frame with 2 stop bits   */
00191 /**
00192   * @}
00193   */
00194
00195 /** @defgroup USART_Parity    USART Parity
00196   * @{
00197   */
00198 #define USART_PARITY_NONE                   ((uint32_t)0x00000000)                      /*!< No parity   */
00199 #define USART_PARITY_EVEN                   ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
00200 #define USART_PARITY_ODD                    ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup USART_Mode   USART Mode
00206   * @{
00207   */
00208 #define USART_MODE_RX                       ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
00209 #define USART_MODE_TX                       ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
00210 #define USART_MODE_TX_RX                    ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup USART_Over_Sampling USART Over Sampling
00216   * @{
00217   */
00218 #define USART_OVERSAMPLING_16               ((uint32_t)0x00000000)          /*!< Oversampling by 16 */
00219 #define USART_OVERSAMPLING_8                ((uint32_t)USART_CR1_OVER8)     /*!< Oversampling by 8  */
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup USART_Clock  USART Clock
00225   * @{
00226   */
00227 #define USART_CLOCK_DISABLE                 ((uint32_t)0x00000000)        /*!< USART clock disable */
00228 #define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)   /*!< USART clock enable  */
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup USART_Clock_Polarity  USART Clock Polarity
00234   * @{
00235   */
00236 #define USART_POLARITY_LOW                  ((uint32_t)0x00000000)       /*!< Driver enable signal is active high */
00237 #define USART_POLARITY_HIGH                 ((uint32_t)USART_CR2_CPOL)   /*!< Driver enable signal is active low  */
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup USART_Clock_Phase   USART Clock Phase
00243   * @{
00244   */
00245 #define USART_PHASE_1EDGE                   ((uint32_t)0x00000000)       /*!< USART frame phase on first clock transition  */
00246 #define USART_PHASE_2EDGE                   ((uint32_t)USART_CR2_CPHA)   /*!< USART frame phase on second clock transition */
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup USART_Last_Bit  USART Last Bit
00252   * @{
00253   */
00254 #define USART_LASTBIT_DISABLE               ((uint32_t)0x00000000)       /*!< USART frame last data bit clock pulse not output to SCLK pin */
00255 #define USART_LASTBIT_ENABLE                ((uint32_t)USART_CR2_LBCL)   /*!< USART frame last data bit clock pulse output to SCLK pin     */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup USART_Request_Parameters  USART Request Parameters
00261   * @{
00262   */
00263 #define USART_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
00264 #define USART_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup USART_Flags      USART Flags
00270   *        Elements values convention: 0xXXXX
00271   *           - 0xXXXX  : Flag mask in the ISR register
00272   * @{
00273   */
00274 #define USART_FLAG_REACK                     ((uint32_t)0x00400000)    /*!< USART receive enable acknowledge flag  */
00275 #define USART_FLAG_TEACK                     ((uint32_t)0x00200000)    /*!< USART transmit enable acknowledge flag */
00276 #define USART_FLAG_BUSY                      ((uint32_t)0x00010000)    /*!< USART busy flag                        */
00277 #define USART_FLAG_CTS                       ((uint32_t)0x00000400)    /*!< USART clear to send flag               */
00278 #define USART_FLAG_CTSIF                     ((uint32_t)0x00000200)    /*!< USART clear to send interrupt flag     */
00279 #define USART_FLAG_LBDF                      ((uint32_t)0x00000100)    /*!< USART LIN break detection flag         */
00280 #define USART_FLAG_TXE                       ((uint32_t)0x00000080)    /*!< USART transmit data register empty     */
00281 #define USART_FLAG_TC                        ((uint32_t)0x00000040)    /*!< USART transmission complete            */
00282 #define USART_FLAG_RXNE                      ((uint32_t)0x00000020)    /*!< USART read data register not empty     */
00283 #define USART_FLAG_IDLE                      ((uint32_t)0x00000010)    /*!< USART idle flag                        */
00284 #define USART_FLAG_ORE                       ((uint32_t)0x00000008)    /*!< USART overrun error                    */
00285 #define USART_FLAG_NE                        ((uint32_t)0x00000004)    /*!< USART noise error                      */
00286 #define USART_FLAG_FE                        ((uint32_t)0x00000002)    /*!< USART frame error                      */
00287 #define USART_FLAG_PE                        ((uint32_t)0x00000001)    /*!< USART parity error                     */
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
00293   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00294   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00295   *           - XX  : Interrupt source register (2bits)
00296   *                 - 01: CR1 register
00297   *                 - 10: CR2 register
00298   *                 - 11: CR3 register
00299   *           - ZZZZ  : Flag position in the ISR register(4bits)
00300   * @{
00301   */
00302
00303 #define USART_IT_PE                          ((uint16_t)0x0028)     /*!< USART parity error interruption                 */
00304 #define USART_IT_TXE                         ((uint16_t)0x0727)     /*!< USART transmit data register empty interruption */
00305 #define USART_IT_TC                          ((uint16_t)0x0626)     /*!< USART transmission complete interruption        */
00306 #define USART_IT_RXNE                        ((uint16_t)0x0525)     /*!< USART read data register not empty interruption */
00307 #define USART_IT_IDLE                        ((uint16_t)0x0424)     /*!< USART idle interruption                         */
00308 #define USART_IT_ERR                         ((uint16_t)0x0060)     /*!< USART error interruption                        */
00309 #define USART_IT_ORE                         ((uint16_t)0x0300)     /*!< USART overrun error interruption                */
00310 #define USART_IT_NE                          ((uint16_t)0x0200)     /*!< USART noise error interruption                  */
00311 #define USART_IT_FE                          ((uint16_t)0x0100)     /*!< USART frame error interruption                  */
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
00317   * @{
00318   */
00319 #define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
00320 #define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
00321 #define USART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
00322 #define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
00323 #define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
00324 #define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
00330   * @{
00331   */
00332 #define USART_IT_MASK                             ((uint16_t)0x001F)     /*!< USART interruptions flags mask */
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /* Exported macros -----------------------------------------------------------*/
00342 /** @defgroup USART_Exported_Macros USART Exported Macros
00343   * @{
00344   */
00345
00346 /** @brief Reset USART handle state.
00347   * @param  __HANDLE__: USART handle.
00348   * @retval None
00349   */
00350 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
00351
00352 /** @brief  Check whether the specified USART flag is set or not.
00353   * @param  __HANDLE__: specifies the USART Handle
00354   * @param  __FLAG__: specifies the flag to check.
00355   *        This parameter can be one of the following values:
00356   *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
00357   *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
00358   *            @arg @ref USART_FLAG_BUSY  Busy flag
00359   *            @arg @ref USART_FLAG_CTS   CTS Change flag
00360   *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
00361   *            @arg @ref USART_FLAG_TC    Transmission Complete flag
00362   *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
00363   *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
00364   *            @arg @ref USART_FLAG_ORE   OverRun Error flag
00365   *            @arg @ref USART_FLAG_NE    Noise Error flag
00366   *            @arg @ref USART_FLAG_FE    Framing Error flag
00367   *            @arg @ref USART_FLAG_PE    Parity Error flag
00368   * @retval The new state of __FLAG__ (TRUE or FALSE).
00369   */
00370 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00371
00372 /** @brief  Clear the specified USART pending flag.
00373   * @param  __HANDLE__: specifies the USART Handle.
00374   * @param  __FLAG__: specifies the flag to check.
00375   *          This parameter can be any combination of the following values:
00376   *            @arg @ref USART_CLEAR_PEF
00377   *            @arg @ref USART_CLEAR_FEF
00378   *            @arg @ref USART_CLEAR_NEF
00379   *            @arg @ref USART_CLEAR_OREF
00380   *            @arg @ref USART_CLEAR_IDLEF
00381   *            @arg @ref USART_CLEAR_TCF
00382   * @retval None
00383   */
00384 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00385
00386 /** @brief  Clear the USART PE pending flag.
00387   * @param  __HANDLE__: specifies the USART Handle.
00388   * @retval None
00389   */
00390 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
00391
00392 /** @brief  Clear the USART FE pending flag.
00393   * @param  __HANDLE__: specifies the USART Handle.
00394   * @retval None
00395   */
00396 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
00397
00398 /** @brief  Clear the USART NE pending flag.
00399   * @param  __HANDLE__: specifies the USART Handle.
00400   * @retval None
00401   */
00402 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
00403
00404 /** @brief  Clear the USART ORE pending flag.
00405   * @param  __HANDLE__: specifies the USART Handle.
00406   * @retval None
00407   */
00408 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
00409
00410 /** @brief  Clear the USART IDLE pending flag.
00411   * @param  __HANDLE__: specifies the USART Handle.
00412   * @retval None
00413   */
00414 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
00415
00416 /** @brief  Enable the specified USART interrupt.
00417   * @param  __HANDLE__: specifies the USART Handle.
00418   * @param  __INTERRUPT__: specifies the USART interrupt source to enable.
00419   *          This parameter can be one of the following values:
00420   *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
00421   *            @arg @ref USART_IT_TC   Transmission complete interrupt
00422   *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
00423   *            @arg @ref USART_IT_IDLE Idle line detection interrupt
00424   *            @arg @ref USART_IT_PE   Parity Error interrupt
00425   *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00426   * @retval None
00427   */
00428 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00429                                                             ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00430                                                             ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00431
00432 /** @brief  Disable the specified USART interrupt.
00433   * @param  __HANDLE__: specifies the USART Handle.
00434   * @param  __INTERRUPT__: specifies the USART interrupt source to disable.
00435   *          This parameter can be one of the following values:
00436   *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
00437   *            @arg @ref USART_IT_TC   Transmission complete interrupt
00438   *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
00439   *            @arg @ref USART_IT_IDLE Idle line detection interrupt
00440   *            @arg @ref USART_IT_PE   Parity Error interrupt
00441   *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00442   * @retval None
00443   */
00444 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00445                                                             ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00446                                                             ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00447
00448
00449 /** @brief  Check whether the specified USART interrupt has occurred or not.
00450   * @param  __HANDLE__: specifies the USART Handle.
00451   * @param  __IT__: specifies the USART interrupt source to check.
00452   *          This parameter can be one of the following values:
00453   *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
00454   *            @arg @ref USART_IT_TC  Transmission complete interrupt
00455   *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
00456   *            @arg @ref USART_IT_IDLE Idle line detection interrupt
00457   *            @arg @ref USART_IT_ORE OverRun Error interrupt
00458   *            @arg @ref USART_IT_NE Noise Error interrupt
00459   *            @arg @ref USART_IT_FE Framing Error interrupt
00460   *            @arg @ref USART_IT_PE Parity Error interrupt
00461   * @retval The new state of __IT__ (TRUE or FALSE).
00462   */
00463 #define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
00464
00465 /** @brief  Check whether the specified USART interrupt source is enabled or not.
00466   * @param  __HANDLE__: specifies the USART Handle.
00467   * @param  __IT__: specifies the USART interrupt source to check.
00468   *          This parameter can be one of the following values:
00469   *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
00470   *            @arg @ref USART_IT_TC  Transmission complete interrupt
00471   *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
00472   *            @arg @ref USART_IT_IDLE Idle line detection interrupt
00473   *            @arg @ref USART_IT_ORE OverRun Error interrupt
00474   *            @arg @ref USART_IT_NE Noise Error interrupt
00475   *            @arg @ref USART_IT_FE Framing Error interrupt
00476   *            @arg @ref USART_IT_PE Parity Error interrupt
00477   * @retval The new state of __IT__ (TRUE or FALSE).
00478   */
00479 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
00480                                                    (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
00481                                                    (((uint16_t)(__IT__)) & USART_IT_MASK)))
00482
00483
00484 /** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
00485   * @param  __HANDLE__: specifies the USART Handle.
00486   * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
00487   *                       to clear the corresponding interrupt.
00488   *          This parameter can be one of the following values:
00489   *            @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
00490   *            @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
00491   *            @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
00492   *            @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
00493   *            @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
00494   *            @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
00495   * @retval None
00496   */
00497 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00498
00499 /** @brief  Set a specific USART request flag.
00500   * @param  __HANDLE__: specifies the USART Handle.
00501   * @param  __REQ__: specifies the request flag to set.
00502   *          This parameter can be one of the following values:
00503   *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
00504   *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
00505   *
00506   * @retval None
00507   */
00508 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (__REQ__))
00509
00510 /** @brief  Enable the USART one bit sample method.
00511   * @param  __HANDLE__: specifies the USART Handle.
00512   * @retval None
00513   */
00514 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00515
00516 /** @brief  Disable the USART one bit sample method.
00517   * @param  __HANDLE__: specifies the USART Handle.
00518   * @retval None
00519   */
00520 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00521
00522 /** @brief  Enable USART.
00523   * @param  __HANDLE__: specifies the USART Handle.
00524   * @retval None
00525   */
00526 #define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00527
00528 /** @brief  Disable USART.
00529   * @param  __HANDLE__: specifies the USART Handle.
00530   * @retval None
00531   */
00532 #define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00533
00534 /**
00535   * @}
00536   */
00537
00538 /* Private macros --------------------------------------------------------*/
00539 /** @defgroup USART_Private_Macros   USART Private Macros
00540   * @{
00541   */
00542
00543 /** @brief  Check USART Baud rate.
00544   * @param  __BAUDRATE__: Baudrate specified by the user.
00545   *         The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz)
00546   *         divided by the smallest oversampling used on the USART (i.e. 8).
00547   * @retval Test result (TRUE or FALSE).
00548   */
00549 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
00550
00551 /**
00552   * @brief Ensure that USART frame number of stop bits is valid.
00553   * @param __STOPBITS__: USART frame number of stop bits.
00554   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00555   */
00556 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
00557                                          ((__STOPBITS__) == USART_STOPBITS_1)   || \
00558                                          ((__STOPBITS__) == USART_STOPBITS_1_5) || \
00559                                          ((__STOPBITS__) == USART_STOPBITS_2))
00560
00561 /**
00562   * @brief Ensure that USART frame parity is valid.
00563   * @param __PARITY__: USART frame parity.
00564   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00565   */
00566 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
00567                                      ((__PARITY__) == USART_PARITY_EVEN) || \
00568                                      ((__PARITY__) == USART_PARITY_ODD))
00569
00570 /**
00571   * @brief Ensure that USART communication mode is valid.
00572   * @param __MODE__: USART communication mode.
00573   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00574   */
00575 #define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
00576
00577 /**
00578   * @brief Ensure that USART oversampling is valid.
00579   * @param __SAMPLING__: USART oversampling.
00580   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
00581   */
00582 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
00583                                              ((__SAMPLING__) == USART_OVERSAMPLING_8))
00584
00585 /**
00586   * @brief Ensure that USART clock state is valid.
00587   * @param __CLOCK__: USART clock state.
00588   * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
00589   */
00590 #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
00591                                    ((__CLOCK__) == USART_CLOCK_ENABLE))
00592
00593 /**
00594   * @brief Ensure that USART frame polarity is valid.
00595   * @param __CPOL__: USART frame polarity.
00596   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00597   */
00598 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
00599
00600 /**
00601   * @brief Ensure that USART frame phase is valid.
00602   * @param __CPHA__: USART frame phase.
00603   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00604   */
00605 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
00606
00607 /**
00608   * @brief Ensure that USART frame last bit clock pulse setting is valid.
00609   * @param __LASTBIT__: USART frame last bit clock pulse setting.
00610   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00611   */
00612 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
00613                                        ((__LASTBIT__) == USART_LASTBIT_ENABLE))
00614
00615 /**
00616   * @brief Ensure that USART request parameter is valid.
00617   * @param __PARAM__: USART request parameter.
00618   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00619   */
00620 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
00621                                                ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
00622
00623 /**
00624   * @}
00625   */
00626
00627 /* Include USART HAL Extended module */
00628 #include "stm32l4xx_hal_usart_ex.h"
00629
00630 /* Exported functions --------------------------------------------------------*/
00631 /** @addtogroup USART_Exported_Functions USART Exported Functions
00632   * @{
00633   */
00634
00635 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00636   * @{
00637   */
00638
00639 /* Initialization and de-initialization functions  ****************************/
00640 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
00641 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
00642 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
00643 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
00644
00645 /**
00646   * @}
00647   */
00648
00649 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
00650   * @{
00651   */
00652
00653 /* IO operation functions *****************************************************/
00654 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
00655 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00656 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00657 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00658 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00659 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
00660 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00661 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00662 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00663 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
00664 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
00665 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
00666 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
00667 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
00668 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
00669 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
00670 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
00671 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
00672 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
00673
00674 /**
00675   * @}
00676   */
00677
00678 /* Peripheral Control functions ***********************************************/
00679
00680 /** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
00681   * @{
00682   */
00683
00684 /* Peripheral State and Error functions ***************************************/
00685 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
00686 uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
00687
00688 /**
00689   * @}
00690   */
00691
00692 /**
00693   * @}
00694   */
00695
00696 /**
00697   * @}
00698   */
00699
00700 /**
00701   * @}
00702   */
00703
00704 #ifdef __cplusplus
00705 }
00706 #endif
00707
00708 #endif /* __STM32L4xx_HAL_USART_H */
00709
00710 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_usart_ex.h Source File

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stm32l4xx_hal_usart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_usart_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of USART HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_USART_EX_H
00040 #define __STM32L4xx_HAL_USART_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup USARTEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
00060   * @{
00061   */
00062
00063 /** @defgroup USARTEx_Word_Length USARTEx Word Length
00064   * @{
00065   */
00066 #define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long USART frame */
00067 #define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long USART frame */
00068 #define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long USART frame */
00069 /**
00070   * @}
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported functions --------------------------------------------------------*/
00078
00079 /* Private macros ------------------------------------------------------------*/
00080 /** @defgroup USARTEx_Private_Macros USARTEx Private Macros
00081   * @{
00082   */
00083
00084 /** @brief  Report the USART clock source.
00085   * @param  __HANDLE__: specifies the USART Handle.
00086   * @param  __CLOCKSOURCE__: output variable.
00087   * @retval the USART clocking source, written in __CLOCKSOURCE__.
00088   */
00089 #if defined (STM32L432xx) || defined (STM32L442xx)
00090 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00091   do {                                                         \
00092     if((__HANDLE__)->Instance == USART1)                       \
00093     {                                                          \
00094        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00095        {                                                       \
00096         case RCC_USART1CLKSOURCE_PCLK2:                        \
00097           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
00098           break;                                               \
00099         case RCC_USART1CLKSOURCE_HSI:                          \
00100           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00101           break;                                               \
00102         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00103           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00104           break;                                               \
00105         case RCC_USART1CLKSOURCE_LSE:                          \
00106           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00107           break;                                               \
00108         default:                                               \
00109           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00110           break;                                               \
00111        }                                                       \
00112     }                                                          \
00113     else if((__HANDLE__)->Instance == USART2)                  \
00114     {                                                          \
00115        switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00116        {                                                       \
00117         case RCC_USART2CLKSOURCE_PCLK1:                        \
00118           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00119           break;                                               \
00120         case RCC_USART2CLKSOURCE_HSI:                          \
00121           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00122           break;                                               \
00123         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00124           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00125           break;                                               \
00126         case RCC_USART2CLKSOURCE_LSE:                          \
00127           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00128           break;                                               \
00129         default:                                               \
00130           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00131           break;                                               \
00132        }                                                       \
00133     }                                                          \
00134   } while(0)
00135 #else
00136 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00137   do {                                                         \
00138     if((__HANDLE__)->Instance == USART1)                       \
00139     {                                                          \
00140        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00141        {                                                       \
00142         case RCC_USART1CLKSOURCE_PCLK2:                        \
00143           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
00144           break;                                               \
00145         case RCC_USART1CLKSOURCE_HSI:                          \
00146           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00147           break;                                               \
00148         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00149           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00150           break;                                               \
00151         case RCC_USART1CLKSOURCE_LSE:                          \
00152           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00153           break;                                               \
00154         default:                                               \
00155           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00156           break;                                               \
00157        }                                                       \
00158     }                                                          \
00159     else if((__HANDLE__)->Instance == USART2)                  \
00160     {                                                          \
00161        switch(__HAL_RCC_GET_USART2_SOURCE())                   \
00162        {                                                       \
00163         case RCC_USART2CLKSOURCE_PCLK1:                        \
00164           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00165           break;                                               \
00166         case RCC_USART2CLKSOURCE_HSI:                          \
00167           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00168           break;                                               \
00169         case RCC_USART2CLKSOURCE_SYSCLK:                       \
00170           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00171           break;                                               \
00172         case RCC_USART2CLKSOURCE_LSE:                          \
00173           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00174           break;                                               \
00175         default:                                               \
00176           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00177           break;                                               \
00178        }                                                       \
00179     }                                                          \
00180     else if((__HANDLE__)->Instance == USART3)                  \
00181     {                                                          \
00182        switch(__HAL_RCC_GET_USART3_SOURCE())                   \
00183        {                                                       \
00184         case RCC_USART3CLKSOURCE_PCLK1:                        \
00185           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
00186           break;                                               \
00187         case RCC_USART3CLKSOURCE_HSI:                          \
00188           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00189           break;                                               \
00190         case RCC_USART3CLKSOURCE_SYSCLK:                       \
00191           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00192           break;                                               \
00193         case RCC_USART3CLKSOURCE_LSE:                          \
00194           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00195           break;                                               \
00196         default:                                               \
00197           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00198           break;                                               \
00199        }                                                       \
00200     }                                                          \
00201   } while(0)
00202 #endif /* STM32L432xx || STM32L442xx */
00203
00204 /** @brief  Compute the USART mask to apply to retrieve the received data
00205   *         according to the word length and to the parity bits activation.
00206   * @note   If PCE = 1, the parity bit is not included in the data extracted
00207   *         by the reception API().
00208   *         This masking operation is not carried out in the case of
00209   *         DMA transfers.
00210   * @param  __HANDLE__: specifies the USART Handle.
00211   * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
00212   */
00213 #define USART_MASK_COMPUTATION(__HANDLE__)                            \
00214   do {                                                                \
00215   if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \
00216   {                                                                   \
00217      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00218      {                                                                \
00219         (__HANDLE__)->Mask = 0x01FF ;                                 \
00220      }                                                                \
00221      else                                                             \
00222      {                                                                \
00223         (__HANDLE__)->Mask = 0x00FF ;                                 \
00224      }                                                                \
00225   }                                                                   \
00226   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \
00227   {                                                                   \
00228      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00229      {                                                                \
00230         (__HANDLE__)->Mask = 0x00FF ;                                 \
00231      }                                                                \
00232      else                                                             \
00233      {                                                                \
00234         (__HANDLE__)->Mask = 0x007F ;                                 \
00235      }                                                                \
00236   }                                                                   \
00237   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)      \
00238   {                                                                   \
00239      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00240      {                                                                \
00241         (__HANDLE__)->Mask = 0x007F ;                                 \
00242      }                                                                \
00243      else                                                             \
00244      {                                                                \
00245         (__HANDLE__)->Mask = 0x003F ;                                 \
00246      }                                                                \
00247   }                                                                   \
00248 } while(0)
00249
00250
00251 /**
00252   * @brief Ensure that USART frame length is valid.
00253   * @param __LENGTH__: USART frame length.
00254   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00255   */
00256 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
00257                                           ((__LENGTH__) == USART_WORDLENGTH_8B) || \
00258                                           ((__LENGTH__) == USART_WORDLENGTH_9B))
00259
00260 /**
00261   * @}
00262   */
00263
00264 /* Exported functions --------------------------------------------------------*/
00265
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 #ifdef __cplusplus
00275 }
00276 #endif
00277
00278 #endif /* __STM32L4xx_HAL_USART_EX_H */
00279
00280 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_wwdg.c Source File

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stm32l4xx_hal_wwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_wwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   WWDG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Window Watchdog (WWDG) peripheral:
00010   *           + Initialization and Configuration function
00011   *           + IO operation functions
00012   @verbatim
00013   ==============================================================================
00014                       ##### WWDG specific features #####
00015   ==============================================================================
00016   [..]
00017     Once enabled the WWDG generates a system reset on expiry of a programmed
00018     time period, unless the program refreshes the counter (T[6;0] downcounter)
00019     before reaching 0x3F value (i.e. a reset is generated when the counter
00020     value rolls over from 0x40 to 0x3F).
00021
00022     (+) An MCU reset is also generated if the counter value is refreshed
00023         before the counter has reached the refresh window value. This
00024         implies that the counter must be refreshed in a limited window.
00025
00026     (+) Once enabled the WWDG cannot be disabled except by a system reset.
00027
00028     (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
00029         occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
00030
00031     (+) The WWDG downcounter input clock is derived from the APB clock divided
00032         by a programmable prescaler.
00033
00034     (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)
00035
00036     (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
00037         where T[5;0] are the lowest 6 bits of downcounter.
00038
00039     (+) WWDG Counter refresh is allowed between the following limits :
00040         (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
00041         (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)
00042
00043     (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms
00044
00045     (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
00046         operations or data logging must be performed before the actual reset is
00047         generated. When the downcounter reaches the value 0x40, an EWI interrupt
00048         is generated and the corresponding interrupt service routine (ISR) can
00049         be used to trigger specific actions (such as communications or data
00050         logging), before resetting the device.
00051         In some applications, the EWI interrupt can be used to manage a software
00052         system check and/or system recovery/graceful degradation, without
00053         generating a WWDG reset. In this case, the corresponding interrupt
00054         service routine (ISR) should reload the WWDG counter to avoid the WWDG
00055         reset, then trigger the required actions.
00056         Note:When the EWI interrupt cannot be served, e.g. due to a system lock
00057         in a higher priority task, the WWDG reset will eventually be generated.
00058
00059     (+) Debug mode : When the microcontroller enters debug mode (core halted),
00060         the WWDG counter either continues to work normally or stops, depending
00061         on DBG_WWDG_STOP configuration bit in DBG module, accessible through
00062         __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
00063
00064                      ##### How to use this driver #####
00065   ==============================================================================
00066   [..]
00067     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
00068
00069     (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
00070         Interrupt mode using using HAL_WWDG_Init() function.
00071         This enables WWDG peripheral and the downcounter starts downcounting
00072         from given counter value.
00073         Init function can be called again to modify all watchdog parameters,
00074         however if EWI mode has been set once, it can't be clear until next
00075         reset.
00076
00077     (+) The application program must refresh the WWDG counter at regular
00078         intervals during normal operation to prevent an MCU reset using
00079         HAL_WWDG_Refresh() function. This operation must occur only when
00080         the counter is lower than the window value already programmed.
00081
00082     (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
00083         the counter reaches 0x40. User can add his own code in weak function
00084         HAL_WWDG_EarlyWakeupCallback().
00085
00086      *** WWDG HAL driver macros list ***
00087      ==================================
00088      [..]
00089        Below the list of most used macros in WWDG HAL driver.
00090
00091       (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
00092       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
00093       (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
00094
00095   @endverbatim
00096   ******************************************************************************
00097   * @attention
00098   *
00099   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00100   *
00101   * Redistribution and use in source and binary forms, with or without modification,
00102   * are permitted provided that the following conditions are met:
00103   *   1. Redistributions of source code must retain the above copyright notice,
00104   *      this list of conditions and the following disclaimer.
00105   *   2. Redistributions in binary form must reproduce the above copyright notice,
00106   *      this list of conditions and the following disclaimer in the documentation
00107   *      and/or other materials provided with the distribution.
00108   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00109   *      may be used to endorse or promote products derived from this software
00110   *      without specific prior written permission.
00111   *
00112   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00113   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00114   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00115   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00116   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00117   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00118   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00119   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00120   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00121   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00122   *
00123   ******************************************************************************
00124   */
00125
00126 /* Includes ------------------------------------------------------------------*/
00127 #include "stm32l4xx_hal.h"
00128
00129 /** @addtogroup STM32L4xx_HAL_Driver
00130   * @{
00131   */
00132
00133 #ifdef HAL_WWDG_MODULE_ENABLED
00134 /** @defgroup WWDG WWDG
00135   * @brief WWDG HAL module driver.
00136   * @{
00137   */
00138
00139 /* Private typedef -----------------------------------------------------------*/
00140 /* Private define ------------------------------------------------------------*/
00141 /* Private macro -------------------------------------------------------------*/
00142 /* Private variables ---------------------------------------------------------*/
00143 /* Private function prototypes -----------------------------------------------*/
00144 /* Exported functions --------------------------------------------------------*/
00145
00146 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
00151  *  @brief    Initialization and Configuration functions.
00152  *
00153 @verbatim
00154   ==============================================================================
00155           ##### Initialization and Configuration functions #####
00156   ==============================================================================
00157   [..]
00158     This section provides functions allowing to:
00159       (+) Initialize and start the WWDG according to the specified parameters
00160           in the WWDG_InitTypeDef of associated handle.
00161       (+) Initialize the WWDG MSP.
00162
00163 @endverbatim
00164   * @{
00165   */
00166
00167 /**
00168   * @brief  Initialize the WWDG according to the specified.
00169   *         parameters in the WWDG_InitTypeDef of  associated handle.
00170   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00171   *                the configuration information for the specified WWDG module.
00172   * @retval HAL status
00173   */
00174 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
00175 {
00176   /* Check the WWDG handle allocation */
00177   if(hwwdg == NULL)
00178   {
00179     return HAL_ERROR;
00180   }
00181
00182   /* Check the parameters */
00183   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00184   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
00185   assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
00186   assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
00187   assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
00188
00189   /* Init the low level hardware */
00190   HAL_WWDG_MspInit(hwwdg);
00191
00192   /* Set WWDG Counter */
00193   WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
00194
00195   /* Set WWDG Prescaler and Window */
00196   WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
00197
00198   /* Return function status */
00199   return HAL_OK;
00200 }
00201
00202
00203 /**
00204   * @brief  Initialize the WWDG MSP.
00205   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00206   *                the configuration information for the specified WWDG module.
00207   * @note   When rewriting this function in user file, mechanism may be added
00208   *         to avoid multiple initialize when HAL_WWDG_Init function is called
00209   *         again to change parameters.
00210   * @retval None
00211   */
00212 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
00213 {
00214   /* Prevent unused argument(s) compilation warning */
00215   UNUSED(hwwdg);
00216
00217   /* NOTE: This function should not be modified, when the callback is needed,
00218            the HAL_WWDG_MspInit could be implemented in the user file
00219    */
00220 }
00221
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
00227  *  @brief    IO operation functions
00228  *
00229 @verbatim
00230   ==============================================================================
00231                       ##### IO operation functions #####
00232   ==============================================================================
00233   [..]
00234     This section provides functions allowing to:
00235     (+) Refresh the WWDG.
00236     (+) Handle WWDG interrupt request and associated function callback.
00237
00238 @endverbatim
00239   * @{
00240   */
00241
00242 /**
00243   * @brief  Refresh the WWDG.
00244   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00245   *                the configuration information for the specified WWDG module.
00246   * @retval HAL status
00247   */
00248 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
00249 {
00250   /* Write to WWDG CR the WWDG Counter value to refresh with */
00251   WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
00252
00253   /* Return function status */
00254   return HAL_OK;
00255 }
00256
00257 /**
00258   * @brief  Handle WWDG interrupt request.
00259   * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
00260   *         or data logging must be performed before the actual reset is generated.
00261   *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
00262   *         EWIMode set to WWDG_EWI_ENABLE.
00263   *         When the downcounter reaches the value 0x40, and EWI interrupt is
00264   *         generated and the corresponding Interrupt Service Routine (ISR) can
00265   *         be used to trigger specific actions (such as communications or data
00266   *         logging), before resetting the device.
00267   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00268   *                the configuration information for the specified WWDG module.
00269   * @retval None
00270   */
00271 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
00272 {
00273   /* Check if Early Wakeup Interrupt is enable */
00274   if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
00275   {
00276     /* Check if WWDG Early Wakeup Interrupt occurred */
00277     if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
00278     {
00279       /* Clear the WWDG Early Wakeup flag */
00280       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
00281
00282       /* Early Wakeup callback */
00283       HAL_WWDG_EarlyWakeupCallback(hwwdg);
00284     }
00285   }
00286 }
00287
00288
00289 /**
00290   * @brief  WWDG Early Wakeup callback.
00291   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00292   *                the configuration information for the specified WWDG module.
00293   * @retval None
00294   */
00295 __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
00296 {
00297   /* Prevent unused argument(s) compilation warning */
00298   UNUSED(hwwdg);
00299
00300   /* NOTE: This function should not be modified, when the callback is needed,
00301            the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
00302    */
00303 }
00304
00305 /**
00306   * @}
00307   */
00308
00309 /**
00310   * @}
00311   */
00312
00313 #endif /* HAL_WWDG_MODULE_ENABLED */
00314 /**
00315   * @}
00316   */
00317
00318 /**
00319   * @}
00320   */
00321
00322 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_hal_wwdg.h Source File

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stm32l4xx_hal_wwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_wwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of WWDG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_WWDG_H
00040 #define __STM32L4xx_HAL_WWDG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup WWDG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup WWDG_Exported_Types WWDG Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  WWDG Init structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
00069                                This parameter can be a value of @ref WWDG_Prescaler */
00070
00071   uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
00072                                This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
00073
00074   uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
00075                                This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
00076
00077   uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
00078                                This parameter can be a value of @ref WWDG_EWI_Mode */
00079
00080 }WWDG_InitTypeDef;
00081
00082 /**
00083   * @brief  WWDG handle Structure definition
00084   */
00085 typedef struct
00086 {
00087   WWDG_TypeDef                 *Instance;  /*!< Register base address    */
00088
00089   WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
00090
00091 }WWDG_HandleTypeDef;
00092 /**
00093   * @}
00094   */
00095
00096 /* Exported constants --------------------------------------------------------*/
00097
00098 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
00099   * @{
00100   */
00101
00102 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
00103   * @{
00104   */
00105 #define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup WWDG_Flag_definition WWDG Flag definition
00111   * @brief WWDG Flag definition
00112   * @{
00113   */
00114 #define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup WWDG_Prescaler WWDG Prescaler
00120   * @{
00121   */
00122 #define WWDG_PRESCALER_1                    0x00000000u       /*!< WWDG counter clock = (PCLK1/4096)/1 */
00123 #define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
00124 #define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
00125 #define WWDG_PRESCALER_8                    WWDG_CFR_WDGTB    /*!< WWDG counter clock = (PCLK1/4096)/8 */
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
00131   * @{
00132   */
00133 #define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
00134 #define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
00135 /**
00136   * @}
00137   */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /* Private macros ------------------------------------------------------------*/
00144
00145 /** @defgroup WWDG_Private_Macros WWDG Private Macros
00146   * @{
00147   */
00148 #define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1) || \
00149                                              ((__PRESCALER__) == WWDG_PRESCALER_2) || \
00150                                              ((__PRESCALER__) == WWDG_PRESCALER_4) || \
00151                                              ((__PRESCALER__) == WWDG_PRESCALER_8))
00152
00153 #define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
00154
00155 #define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
00156
00157 #define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
00158                                              ((__MODE__) == WWDG_EWI_DISABLE))
00159 /**
00160   * @}
00161   */
00162
00163
00164 /* Exported macros ------------------------------------------------------------*/
00165
00166 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
00167   * @{
00168   */
00169
00170 /**
00171   * @brief  Enable the WWDG peripheral.
00172   * @param  __HANDLE__  WWDG handle
00173   * @retval None
00174   */
00175 #define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
00176
00177 /**
00178   * @brief  Enable the WWDG early wakeup interrupt.
00179   * @param  __HANDLE__: WWDG handle
00180   * @param  __INTERRUPT__  specifies the interrupt to enable.
00181   *         This parameter can be one of the following values:
00182   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00183   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00184   * @retval None
00185   */
00186 #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
00187
00188 /**
00189   * @brief  Check whether the selected WWDG interrupt has occurred or not.
00190   * @param  __HANDLE__  WWDG handle
00191   * @param  __INTERRUPT__  specifies the it to check.
00192   *        This parameter can be one of the following values:
00193   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
00194   * @retval The new state of WWDG_FLAG (SET or RESET).
00195   */
00196 #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
00197
00198 /** @brief  Clear the WWDG interrupt pending bits.
00199   *         bits to clear the selected interrupt pending bits.
00200   * @param  __HANDLE__  WWDG handle
00201   * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
00202   *         This parameter can be one of the following values:
00203   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00204   */
00205 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
00206
00207 /**
00208   * @brief  Check whether the specified WWDG flag is set or not.
00209   * @param  __HANDLE__  WWDG handle
00210   * @param  __FLAG__  specifies the flag to check.
00211   *         This parameter can be one of the following values:
00212   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00213   * @retval The new state of WWDG_FLAG (SET or RESET).
00214   */
00215 #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00216
00217 /**
00218   * @brief  Clear the WWDG's pending flags.
00219   * @param  __HANDLE__  WWDG handle
00220   * @param  __FLAG__  specifies the flag to clear.
00221   *         This parameter can be one of the following values:
00222   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00223   * @retval None
00224   */
00225 #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00226
00227 /** @brief  Check whether the specified WWDG interrupt source is enabled or not.
00228   * @param  __HANDLE__  WWDG Handle.
00229   * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
00230   *         This parameter can be one of the following values:
00231   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
00232   * @retval state of __INTERRUPT__ (TRUE or FALSE).
00233   */
00234 #define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
00235
00236 /**
00237   * @}
00238   */
00239
00240 /* Exported functions --------------------------------------------------------*/
00241
00242 /** @addtogroup WWDG_Exported_Functions
00243   * @{
00244   */
00245
00246 /** @addtogroup WWDG_Exported_Functions_Group1
00247   * @{
00248   */
00249 /* Initialization/de-initialization functions  **********************************/
00250 HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
00251 void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
00252 /**
00253   * @}
00254   */
00255
00256 /** @addtogroup WWDG_Exported_Functions_Group2
00257   * @{
00258   */
00259 /* I/O operation functions ******************************************************/
00260 HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
00261 void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
00262 void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
00263 /**
00264   * @}
00265   */
00266
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /**
00276   * @}
00277   */
00278
00279 #ifdef __cplusplus
00280 }
00281 #endif
00282
00283 #endif /* __STM32L4xx_HAL_WWDG_H */
00284
00285 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_adc.c Source File

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stm32l4xx_ll_adc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_adc.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   ADC LL module driver
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_adc.h"
00041 #include "stm32l4xx_ll_bus.h"
00042
00043 #ifdef  USE_FULL_ASSERT
00044   #include "stm32_assert.h"
00045 #else
00046   #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
00054
00055 /** @addtogroup ADC_LL ADC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /** @addtogroup ADC_LL_Private_Constants
00063   * @{
00064   */
00065
00066 /* Definitions of ADC hardware constraints delays */
00067 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
00068 /*       not timeout values:                                                  */
00069 /*       Timeout values for ADC operations are dependent to device clock      */
00070 /*       configuration (system clock versus ADC clock),                       */
00071 /*       and therefore must be defined in user application.                   */
00072 /*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
00073 /*       values definition.                                                   */
00074 /* Note: ADC timeout values are defined here in CPU cycles to be independent  */
00075 /*       of device clock setting.                                             */
00076 /*       In user application, ADC timeout values should be defined with       */
00077 /*       temporal values, in function of device clock settings.               */
00078 /*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
00079 /*        - ADC clock from synchronous clock with AHB prescaler 512,          */
00080 /*          APB prescaler 16, ADC prescaler 4.                                */
00081 /*        - ADC clock from asynchronous clock (PLLSAI) with prescaler 1,      */
00082 /*          with highest ratio CPU clock frequency vs HSI clock frequency:    */
00083 /*          CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4.    */
00084 /* Unit: CPU cycles.                                                          */
00085 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          ((uint32_t) 512U * 16U * 4U)
00086 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
00087 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Private macros ------------------------------------------------------------*/
00094
00095 /** @addtogroup ADC_LL_Private_Macros
00096   * @{
00097   */
00098
00099 /* Check of parameters for configuration of ADC hierarchical scope:           */
00100 /* common to several ADC instances.                                           */
00101 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
00102   (   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
00103    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
00104    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
00105    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
00106    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
00107    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
00108    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
00109    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
00110    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
00111    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
00112    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
00113    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
00114    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
00115    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
00116    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
00117   )
00118
00119 /* Check of parameters for configuration of ADC hierarchical scope:           */
00120 /* ADC instance.                                                              */
00121 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
00122   (   ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
00123    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
00124    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
00125    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
00126   )
00127
00128 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
00129   (   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
00130    || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
00131   )
00132
00133 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
00134   (   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
00135    || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
00136   )
00137
00138 /* Check of parameters for configuration of ADC hierarchical scope:           */
00139 /* ADC group regular                                                          */
00140 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00141   (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
00142    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00143    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00144    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
00145    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
00146    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00147    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00148    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00149    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00150    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
00151    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
00152    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
00153    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
00154    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
00155    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
00156    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
00157    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00158   )
00159
00160 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
00161   (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
00162    || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
00163   )
00164
00165 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
00166   (   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
00167    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
00168    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
00169   )
00170
00171 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
00172   (   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
00173    || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
00174   )
00175
00176 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
00177   (   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
00178    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
00179    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
00180    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
00181    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
00182    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
00183    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
00184    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
00185    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
00186    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
00187    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
00188    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
00189    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
00190    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
00191    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
00192    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
00193   )
00194
00195 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
00196   (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
00197    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
00198    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
00199    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
00200    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
00201    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
00202    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
00203    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
00204    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
00205   )
00206
00207 /* Check of parameters for configuration of ADC hierarchical scope:           */
00208 /* ADC group injected                                                         */
00209 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
00210   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
00211    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00212    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00213    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00214    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00215    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
00216    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
00217    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
00218    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
00219    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
00220    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00221    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
00222    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
00223    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
00224    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
00225    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
00226    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
00227   )
00228
00229 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
00230   (   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
00231    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
00232    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
00233   )
00234
00235 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
00236   (   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
00237    || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
00238   )
00239
00240 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
00241   (   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
00242    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
00243    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
00244    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
00245   )
00246
00247 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
00248   (   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
00249    || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
00250   )
00251
00252 #if defined(ADC_MULTIMODE_SUPPORT)
00253 /* Check of parameters for configuration of ADC hierarchical scope:           */
00254 /* multimode.                                                                 */
00255 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \
00256   (   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \
00257    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
00258    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
00259    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
00260    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
00261    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
00262    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
00263    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
00264   )
00265
00266 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)                   \
00267   (   ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)              \
00268    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B)       \
00269    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B)         \
00270    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B)       \
00271    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B)         \
00272   )
00273
00274 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)                   \
00275   (   ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)           \
00276    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)          \
00277    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)          \
00278    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)          \
00279    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)          \
00280    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)          \
00281    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)          \
00282    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)          \
00283    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)          \
00284    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)         \
00285    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)         \
00286    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)         \
00287   )
00288
00289 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \
00290   (   ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                        \
00291    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
00292    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
00293   )
00294
00295 #endif /* ADC_MULTIMODE_SUPPORT */
00296 /**
00297   * @}
00298   */
00299
00300
00301 /* Private function prototypes -----------------------------------------------*/
00302
00303 /* Exported functions --------------------------------------------------------*/
00304 /** @addtogroup ADC_LL_Exported_Functions
00305   * @{
00306   */
00307
00308 /** @addtogroup ADC_LL_EF_Init
00309   * @{
00310   */
00311
00312 /**
00313   * @brief  De-initialize registers of all ADC instances belonging to
00314   *         the same ADC common instance to their default reset values.
00315   * @note   This function is performing a hard reset, using high level
00316   *         clock source RCC ADC reset.
00317   *         Caution: On this STM32 serie, if several ADC instances are available
00318   *         on the selected device, RCC ADC reset will reset
00319   *         all ADC instances belonging to the common ADC instance.
00320   *         To de-initialize only 1 ADC instance, use
00321   *         function @ref LL_ADC_DeInit().
00322   * @param  ADCxy_COMMON ADC common instance
00323   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00324   * @retval An ErrorStatus enumeration value:
00325   *          - SUCCESS: ADC common registers are de-initialized
00326   *          - ERROR: not applicable
00327   */
00328 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
00329 {
00330   /* Check the parameters */
00331   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00332
00333   /* Force reset of ADC clock (core clock) */
00334   LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
00335
00336   /* Release reset of ADC clock (core clock) */
00337   LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
00338
00339   return SUCCESS;
00340 }
00341
00342 /**
00343   * @brief  Initialize some features of ADC common parameters
00344   *         (all ADC instances belonging to the same ADC common instance)
00345   *         and multimode (for devices with several ADC instances available).
00346   * @note   The setting of ADC common parameters is conditioned to
00347   *         ADC instances state:
00348   *         All ADC instances belonging to the same ADC common instance
00349   *         must be disabled.
00350   * @param  ADCxy_COMMON ADC common instance
00351   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00352   * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00353   * @retval An ErrorStatus enumeration value:
00354   *          - SUCCESS: ADC common registers are initialized
00355   *          - ERROR: ADC common registers are not initialized
00356   */
00357 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
00358 {
00359   ErrorStatus status = SUCCESS;
00360
00361   /* Check the parameters */
00362   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00363   assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
00364
00365 #if defined(ADC_MULTIMODE_SUPPORT)
00366   assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
00367   if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
00368   {
00369     assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
00370     assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
00371   }
00372 #endif /* ADC_MULTIMODE_SUPPORT */
00373
00374   /* Note: Hardware constraint (refer to description of functions             */
00375   /*       "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"):               */
00376   /*       On this STM32 serie, setting of these features is conditioned to   */
00377   /*       ADC state:                                                         */
00378   /*       All ADC instances of the ADC common group must be disabled.        */
00379   if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
00380   {
00381     /* Configuration of ADC hierarchical scope:                               */
00382     /*  - common to several ADC                                               */
00383     /*    (all ADC instances belonging to the same ADC common instance)       */
00384     /*    - Set ADC clock (conversion clock)                                  */
00385     /*  - multimode (if several ADC instances available on the                */
00386     /*    selected device)                                                    */
00387     /*    - Set ADC multimode configuration                                   */
00388     /*    - Set ADC multimode DMA transfer                                    */
00389     /*    - Set ADC multimode: delay between 2 sampling phases                */
00390 #if defined(ADC_MULTIMODE_SUPPORT)
00391     if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
00392     {
00393       MODIFY_REG(ADCxy_COMMON->CCR,
00394                    ADC_CCR_CKMODE
00395                  | ADC_CCR_PRESC
00396                  | ADC_CCR_DUAL
00397                  | ADC_CCR_MDMA
00398                  | ADC_CCR_DELAY
00399                 ,
00400                    ADC_CommonInitStruct->CommonClock
00401                  | ADC_CommonInitStruct->Multimode
00402                  | ADC_CommonInitStruct->MultiDMATransfer
00403                  | ADC_CommonInitStruct->MultiTwoSamplingDelay
00404                 );
00405     }
00406     else
00407     {
00408       MODIFY_REG(ADCxy_COMMON->CCR,
00409                    ADC_CCR_CKMODE
00410                  | ADC_CCR_PRESC
00411                  | ADC_CCR_DUAL
00412                  | ADC_CCR_MDMA
00413                  | ADC_CCR_DELAY
00414                 ,
00415                    ADC_CommonInitStruct->CommonClock
00416                  | LL_ADC_MULTI_INDEPENDENT
00417                 );
00418     }
00419 #else
00420     LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
00421 #endif
00422   }
00423   else
00424   {
00425     /* Initialization error: One or several ADC instances belonging to        */
00426     /* the same ADC common instance are not disabled.                         */
00427     status = ERROR;
00428   }
00429
00430   return status;
00431 }
00432
00433 /**
00434   * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
00435   * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00436   *                              whose fields will be set to default values.
00437   * @retval None
00438   */
00439 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
00440 {
00441   /* Set ADC_CommonInitStruct fields to default values */
00442   /* Set fields of ADC common */
00443   /* (all ADC instances belonging to the same ADC common instance) */
00444   ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
00445
00446 #if defined(ADC_MULTIMODE_SUPPORT)
00447   /* Set fields of ADC multimode */
00448   ADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;
00449   ADC_CommonInitStruct->MultiDMATransfer      = LL_ADC_MULTI_REG_DMA_EACH_ADC;
00450   ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
00451 #endif /* ADC_MULTIMODE_SUPPORT */
00452 }
00453
00454 /**
00455   * @brief  De-initialize registers of the selected ADC instance
00456   *         to their default reset values.
00457   * @note   To reset all ADC instances quickly (perform a hard reset),
00458   *         use function @ref LL_ADC_CommonDeInit().
00459   * @note   If this functions returns error status, it means that ADC instance
00460   *         is in an unknown state.
00461   *         In this case, perform a hard reset using high level
00462   *         clock source RCC ADC reset.
00463   *         Caution: On this STM32 serie, if several ADC instances are available
00464   *         on the selected device, RCC ADC reset will reset
00465   *         all ADC instances belonging to the common ADC instance.
00466   *         Refer to function @ref LL_ADC_CommonDeInit().
00467   * @param  ADCx ADC instance
00468   * @retval An ErrorStatus enumeration value:
00469   *          - SUCCESS: ADC registers are de-initialized
00470   *          - ERROR: ADC registers are not de-initialized
00471   */
00472 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
00473 {
00474   ErrorStatus status = SUCCESS;
00475
00476   __IO uint32_t timeout_cpu_cycles = 0U;
00477
00478   /* Check the parameters */
00479   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00480
00481   /* Disable ADC instance if not already disabled.                            */
00482   if(LL_ADC_IsEnabled(ADCx) == 1U)
00483   {
00484     /* Set ADC group regular trigger source to SW start to ensure to not      */
00485     /* have an external trigger event occurring during the conversion stop    */
00486     /* ADC disable process.                                                   */
00487     LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
00488
00489     /* Stop potential ADC conversion on going on ADC group regular.           */
00490     if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
00491     {
00492       if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
00493       {
00494         LL_ADC_REG_StopConversion(ADCx);
00495       }
00496     }
00497
00498     /* Set ADC group injected trigger source to SW start to ensure to not     */
00499     /* have an external trigger event occurring during the conversion stop    */
00500     /* ADC disable process.                                                   */
00501     LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
00502
00503     /* Stop potential ADC conversion on going on ADC group injected.          */
00504     if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U)
00505     {
00506       if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U)
00507       {
00508         LL_ADC_INJ_StopConversion(ADCx);
00509       }
00510     }
00511
00512     /* Wait for ADC conversions are effectively stopped                       */
00513     timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
00514     while ((  LL_ADC_REG_IsStopConversionOngoing(ADCx)
00515             | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
00516     {
00517       if(timeout_cpu_cycles-- == 0U)
00518       {
00519         /* Time-out error */
00520         status = ERROR;
00521       }
00522     }
00523
00524     /* Flush group injected contexts queue (register JSQR):                   */
00525     /* Note: Bit JQM must be set to empty the contexts queue (otherwise       */
00526     /*       contexts queue is maintained with the last active context).      */
00527     LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
00528
00529     /* Disable the ADC instance */
00530     LL_ADC_Disable(ADCx);
00531
00532     /* Wait for ADC instance is effectively disabled */
00533     timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
00534     while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
00535     {
00536       if(timeout_cpu_cycles-- == 0U)
00537       {
00538         /* Time-out error */
00539         status = ERROR;
00540       }
00541     }
00542   }
00543
00544   /* Check whether ADC state is compliant with expected state */
00545   if(READ_BIT(ADCx->CR,
00546               (  ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
00547                | ADC_CR_ADDIS | ADC_CR_ADEN                                     )
00548              )
00549      == 0U)
00550   {
00551     /* ========== Reset ADC registers ========== */
00552     /* Reset register IER */
00553     CLEAR_BIT(ADCx->IER,
00554               (  LL_ADC_IT_ADRDY
00555                | LL_ADC_IT_EOC
00556                | LL_ADC_IT_EOS
00557                | LL_ADC_IT_OVR
00558                | LL_ADC_IT_EOSMP
00559                | LL_ADC_IT_JEOC
00560                | LL_ADC_IT_JEOS
00561                | LL_ADC_IT_JQOVF
00562                | LL_ADC_IT_AWD1
00563                | LL_ADC_IT_AWD2
00564                | LL_ADC_IT_AWD3 )
00565              );
00566
00567     /* Reset register ISR */
00568     SET_BIT(ADCx->ISR,
00569             (  LL_ADC_FLAG_ADRDY
00570              | LL_ADC_FLAG_EOC
00571              | LL_ADC_FLAG_EOS
00572              | LL_ADC_FLAG_OVR
00573              | LL_ADC_FLAG_EOSMP
00574              | LL_ADC_FLAG_JEOC
00575              | LL_ADC_FLAG_JEOS
00576              | LL_ADC_FLAG_JQOVF
00577              | LL_ADC_FLAG_AWD1
00578              | LL_ADC_FLAG_AWD2
00579              | LL_ADC_FLAG_AWD3 )
00580            );
00581
00582     /* Reset register CR */
00583     /*  - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,  */
00584     /*    ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in                      */
00585     /*    access mode "read-set": no direct reset applicable.                 */
00586     /*  - Reset Calibration mode to default setting (single ended).           */
00587     /*  - Disable ADC internal voltage regulator.                             */
00588     /*  - Enable ADC deep power down.                                         */
00589     /*    Note: ADC internal voltage regulator disable and ADC deep power     */
00590     /*          down enable are conditioned to ADC state disabled:            */
00591     /*          already done above.                                           */
00592     CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
00593     SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
00594
00595     /* Reset register CFGR */
00596     MODIFY_REG(ADCx->CFGR,
00597                (  ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN
00598                 | ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
00599                 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
00600                 | ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD
00601                 | ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN
00602                 | ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN  ),
00603                 ADC_CFGR_JQDIS
00604               );
00605
00606     /* Reset register CFGR2 */
00607     CLEAR_BIT(ADCx->CFGR2,
00608               (  ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
00609                | ADC_CFGR2_OVSR   | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
00610              );
00611
00612     /* Reset register SMPR1 */
00613     CLEAR_BIT(ADCx->SMPR1,
00614               (  ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
00615                | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
00616                | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
00617              );
00618
00619     /* Reset register SMPR2 */
00620     CLEAR_BIT(ADCx->SMPR2,
00621               (  ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
00622                | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
00623                | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
00624              );
00625
00626     /* Reset register TR1 */
00627     MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
00628
00629     /* Reset register TR2 */
00630     MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
00631
00632     /* Reset register TR3 */
00633     MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
00634
00635     /* Reset register SQR1 */
00636     CLEAR_BIT(ADCx->SQR1,
00637               (  ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
00638                | ADC_SQR1_SQ1 | ADC_SQR1_L)
00639              );
00640
00641     /* Reset register SQR2 */
00642     CLEAR_BIT(ADCx->SQR2,
00643               (  ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
00644                | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
00645              );
00646
00647     /* Reset register SQR3 */
00648     CLEAR_BIT(ADCx->SQR3,
00649               (  ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
00650                | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
00651              );
00652
00653     /* Reset register SQR4 */
00654     CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00655
00656     /* Reset register JSQR */
00657     CLEAR_BIT(ADCx->JSQR,
00658               (  ADC_JSQR_JL
00659                | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
00660                | ADC_JSQR_JSQ4    | ADC_JSQR_JSQ3
00661                | ADC_JSQR_JSQ2    | ADC_JSQR_JSQ1  )
00662              );
00663
00664     /* Reset register DR */
00665     /* Note: bits in access mode read only, no direct reset applicable */
00666
00667     /* Reset register OFR1 */
00668     CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
00669     /* Reset register OFR2 */
00670     CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
00671     /* Reset register OFR3 */
00672     CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
00673     /* Reset register OFR4 */
00674     CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
00675
00676     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00677     /* Note: bits in access mode read only, no direct reset applicable */
00678
00679     /* Reset register AWD2CR */
00680     CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
00681
00682     /* Reset register AWD3CR */
00683     CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
00684
00685     /* Reset register DIFSEL */
00686     CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
00687
00688     /* Reset register CALFACT */
00689     CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00690   }
00691   else
00692   {
00693     /* ADC instance is in an unknown state */
00694     /* Need to performing a hard reset of ADC instance, using high level      */
00695     /* clock source RCC ADC reset.                                            */
00696     /* Caution: On this STM32 serie, if several ADC instances are available   */
00697     /*          on the selected device, RCC ADC reset will reset              */
00698     /*          all ADC instances belonging to the common ADC instance.       */
00699     /* Caution: On this STM32 serie, if several ADC instances are available   */
00700     /*          on the selected device, RCC ADC reset will reset              */
00701     /*          all ADC instances belonging to the common ADC instance.       */
00702     status = ERROR;
00703   }
00704
00705   return status;
00706 }
00707
00708 /**
00709   * @brief  Initialize some features of ADC instance.
00710   * @note   These parameters have an impact on ADC scope: ADC instance.
00711   *         Affects both group regular and group injected (availability
00712   *         of ADC group injected depends on STM32 families).
00713   *         Refer to corresponding unitary functions into
00714   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00715   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00716   *         is conditioned to ADC state:
00717   *         ADC instance must be disabled.
00718   *         This condition is applied to all ADC features, for efficiency
00719   *         and compatibility over all STM32 families. However, the different
00720   *         features can be set under different ADC state conditions
00721   *         (setting possible with ADC enabled without conversion on going,
00722   *         ADC enabled with conversion on going, ...)
00723   *         Each feature can be updated afterwards with a unitary function
00724   *         and potentially with ADC in a different state than disabled,
00725   *         refer to description of each function for setting
00726   *         conditioned to ADC state.
00727   * @note   After using this function, some other features must be configured
00728   *         using LL unitary functions.
00729   *         The minimum configuration remaining to be done is:
00730   *          - Set ADC group regular or group injected sequencer:
00731   *            map channel on the selected sequencer rank.
00732   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
00733   *          - Set ADC channel sampling time
00734   *            Refer to function LL_ADC_SetChannelSamplingTime();
00735   * @param  ADCx ADC instance
00736   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00737   * @retval An ErrorStatus enumeration value:
00738   *          - SUCCESS: ADC registers are initialized
00739   *          - ERROR: ADC registers are not initialized
00740   */
00741 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
00742 {
00743   ErrorStatus status = SUCCESS;
00744
00745   /* Check the parameters */
00746   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00747
00748   assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
00749   assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
00750   assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
00751
00752   /* Note: Hardware constraint (refer to description of this function):       */
00753   /*       ADC instance must be disabled.                                     */
00754   if(LL_ADC_IsEnabled(ADCx) == 0U)
00755   {
00756     /* Configuration of ADC hierarchical scope:                               */
00757     /*  - ADC instance                                                        */
00758     /*    - Set ADC data resolution                                           */
00759     /*    - Set ADC conversion data alignment                                 */
00760     /*    - Set ADC low power mode                                            */
00761     MODIFY_REG(ADCx->CFGR,
00762                  ADC_CFGR_RES
00763                | ADC_CFGR_ALIGN
00764                | ADC_CFGR_AUTDLY
00765               ,
00766                  ADC_InitStruct->Resolution
00767                | ADC_InitStruct->DataAlignment
00768                | ADC_InitStruct->LowPowerMode
00769               );
00770
00771   }
00772   else
00773   {
00774     /* Initialization error: ADC instance is not disabled. */
00775     status = ERROR;
00776   }
00777   return status;
00778 }
00779
00780 /**
00781   * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
00782   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
00783   *                        whose fields will be set to default values.
00784   * @retval None
00785   */
00786 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
00787 {
00788   /* Set ADC_InitStruct fields to default values */
00789   /* Set fields of ADC instance */
00790   ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
00791   ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
00792   ADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
00793
00794 }
00795
00796 /**
00797   * @brief  Initialize some features of ADC group regular.
00798   * @note   These parameters have an impact on ADC scope: ADC group regular.
00799   *         Refer to corresponding unitary functions into
00800   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00801   *         (functions with prefix "REG").
00802   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00803   *         is conditioned to ADC state:
00804   *         ADC instance must be disabled.
00805   *         This condition is applied to all ADC features, for efficiency
00806   *         and compatibility over all STM32 families. However, the different
00807   *         features can be set under different ADC state conditions
00808   *         (setting possible with ADC enabled without conversion on going,
00809   *         ADC enabled with conversion on going, ...)
00810   *         Each feature can be updated afterwards with a unitary function
00811   *         and potentially with ADC in a different state than disabled,
00812   *         refer to description of each function for setting
00813   *         conditioned to ADC state.
00814   * @note   After using this function, other features must be configured
00815   *         using LL unitary functions.
00816   *         The minimum configuration remaining to be done is:
00817   *          - Set ADC group regular or group injected sequencer:
00818   *            map channel on the selected sequencer rank.
00819   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
00820   *          - Set ADC channel sampling time
00821   *            Refer to function LL_ADC_SetChannelSamplingTime();
00822   * @param  ADCx ADC instance
00823   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00824   * @retval An ErrorStatus enumeration value:
00825   *          - SUCCESS: ADC registers are initialized
00826   *          - ERROR: ADC registers are not initialized
00827   */
00828 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
00829 {
00830   ErrorStatus status = SUCCESS;
00831
00832   /* Check the parameters */
00833   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00834   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
00835   assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
00836   if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00837   {
00838     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
00839   }
00840   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
00841   assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
00842   assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
00843
00844   /* Note: Hardware constraint (refer to description of this function):       */
00845   /*       ADC instance must be disabled.                                     */
00846   if(LL_ADC_IsEnabled(ADCx) == 0U)
00847   {
00848     /* Configuration of ADC hierarchical scope:                               */
00849     /*  - ADC group regular                                                   */
00850     /*    - Set ADC group regular trigger source                              */
00851     /*    - Set ADC group regular sequencer length                            */
00852     /*    - Set ADC group regular sequencer discontinuous mode                */
00853     /*    - Set ADC group regular continuous mode                             */
00854     /*    - Set ADC group regular conversion data transfer: no transfer or    */
00855     /*      transfer by DMA, and DMA requests mode                            */
00856     /*    - Set ADC group regular overrun behavior                            */
00857     /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
00858     /*       setting of trigger source to SW start.                           */
00859     if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00860     {
00861       MODIFY_REG(ADCx->CFGR,
00862                    ADC_CFGR_EXTSEL
00863                  | ADC_CFGR_EXTEN
00864                  | ADC_CFGR_DISCEN
00865                  | ADC_CFGR_DISCNUM
00866                  | ADC_CFGR_CONT
00867                  | ADC_CFGR_DMAEN
00868                  | ADC_CFGR_DMACFG
00869                  | ADC_CFGR_OVRMOD
00870                 ,
00871                    ADC_REG_InitStruct->TriggerSource
00872                  | ADC_REG_InitStruct->SequencerDiscont
00873                  | ADC_REG_InitStruct->ContinuousMode
00874                  | ADC_REG_InitStruct->DMATransfer
00875                  | ADC_REG_InitStruct->Overrun
00876                 );
00877     }
00878     else
00879     {
00880       MODIFY_REG(ADCx->CFGR,
00881                    ADC_CFGR_EXTSEL
00882                  | ADC_CFGR_EXTEN
00883                  | ADC_CFGR_DISCEN
00884                  | ADC_CFGR_DISCNUM
00885                  | ADC_CFGR_CONT
00886                  | ADC_CFGR_DMAEN
00887                  | ADC_CFGR_DMACFG
00888                  | ADC_CFGR_OVRMOD
00889                 ,
00890                    ADC_REG_InitStruct->TriggerSource
00891                  | LL_ADC_REG_SEQ_DISCONT_DISABLE
00892                  | ADC_REG_InitStruct->ContinuousMode
00893                  | ADC_REG_InitStruct->DMATransfer
00894                  | ADC_REG_InitStruct->Overrun
00895                 );
00896     }
00897
00898     /* Set ADC group regular sequencer length and scan direction */
00899     LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
00900   }
00901   else
00902   {
00903     /* Initialization error: ADC instance is not disabled. */
00904     status = ERROR;
00905   }
00906   return status;
00907 }
00908
00909 /**
00910   * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
00911   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00912   *                            whose fields will be set to default values.
00913   * @retval None
00914   */
00915 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
00916 {
00917   /* Set ADC_REG_InitStruct fields to default values */
00918   /* Set fields of ADC group regular */
00919   /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by       */
00920   /*       setting of trigger source to SW start.                             */
00921   ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
00922   ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
00923   ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
00924   ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
00925   ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
00926   ADC_REG_InitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
00927 }
00928
00929 /**
00930   * @brief  Initialize some features of ADC group injected.
00931   * @note   These parameters have an impact on ADC scope: ADC group injected.
00932   *         Refer to corresponding unitary functions into
00933   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00934   *         (functions with prefix "INJ").
00935   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00936   *         is conditioned to ADC state:
00937   *         ADC instance must be disabled.
00938   *         This condition is applied to all ADC features, for efficiency
00939   *         and compatibility over all STM32 families. However, the different
00940   *         features can be set under different ADC state conditions
00941   *         (setting possible with ADC enabled without conversion on going,
00942   *         ADC enabled with conversion on going, ...)
00943   *         Each feature can be updated afterwards with a unitary function
00944   *         and potentially with ADC in a different state than disabled,
00945   *         refer to description of each function for setting
00946   *         conditioned to ADC state.
00947   * @note   After using this function, other features must be configured
00948   *         using LL unitary functions.
00949   *         The minimum configuration remaining to be done is:
00950   *          - Set ADC group injected sequencer:
00951   *            map channel on the selected sequencer rank.
00952   *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
00953   *          - Set ADC channel sampling time
00954   *            Refer to function LL_ADC_SetChannelSamplingTime();
00955   * @param  ADCx ADC instance
00956   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
00957   * @retval An ErrorStatus enumeration value:
00958   *          - SUCCESS: ADC registers are initialized
00959   *          - ERROR: ADC registers are not initialized
00960   */
00961 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
00962 {
00963   ErrorStatus status = SUCCESS;
00964
00965   /* Check the parameters */
00966   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00967   assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
00968   assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
00969   if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
00970   {
00971     assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
00972   }
00973   assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
00974
00975   /* Note: Hardware constraint (refer to description of this function):       */
00976   /*       ADC instance must be disabled.                                     */
00977   if(LL_ADC_IsEnabled(ADCx) == 0U)
00978   {
00979     /* Configuration of ADC hierarchical scope:                               */
00980     /*  - ADC group injected                                                  */
00981     /*    - Set ADC group injected trigger source                             */
00982     /*    - Set ADC group injected sequencer length                           */
00983     /*    - Set ADC group injected sequencer discontinuous mode               */
00984     /*    - Set ADC group injected conversion trigger: independent or         */
00985     /*      from ADC group regular                                            */
00986     /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
00987     /*       setting of trigger source to SW start.                           */
00988     if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00989     {
00990       MODIFY_REG(ADCx->CFGR,
00991                    ADC_CFGR_JDISCEN
00992                  | ADC_CFGR_JAUTO
00993                 ,
00994                    ADC_INJ_InitStruct->SequencerDiscont
00995                  | ADC_INJ_InitStruct->TrigAuto
00996                 );
00997     }
00998     else
00999     {
01000       MODIFY_REG(ADCx->CFGR,
01001                    ADC_CFGR_JDISCEN
01002                  | ADC_CFGR_JAUTO
01003                 ,
01004                    LL_ADC_REG_SEQ_DISCONT_DISABLE
01005                  | ADC_INJ_InitStruct->TrigAuto
01006                 );
01007     }
01008
01009     MODIFY_REG(ADCx->JSQR,
01010                  ADC_JSQR_JEXTSEL
01011                | ADC_JSQR_JEXTEN
01012                | ADC_JSQR_JL
01013               ,
01014                  ADC_INJ_InitStruct->TriggerSource
01015                | ADC_INJ_InitStruct->SequencerLength
01016               );
01017   }
01018   else
01019   {
01020     /* Initialization error: ADC instance is not disabled. */
01021     status = ERROR;
01022   }
01023   return status;
01024 }
01025
01026 /**
01027   * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
01028   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
01029   *                            whose fields will be set to default values.
01030   * @retval None
01031   */
01032 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
01033 {
01034   /* Set ADC_INJ_InitStruct fields to default values */
01035   /* Set fields of ADC group injected */
01036   ADC_INJ_InitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
01037   ADC_INJ_InitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
01038   ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
01039   ADC_INJ_InitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
01040 }
01041
01042 /**
01043   * @}
01044   */
01045
01046 /**
01047   * @}
01048   */
01049
01050 /**
01051   * @}
01052   */
01053
01054 #endif /* ADC1 || ADC2 || ADC3 */
01055
01056 /**
01057   * @}
01058   */
01059
01060 #endif /* USE_FULL_LL_DRIVER */
01061
01062 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_adc.h Source File

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stm32l4xx_ll_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_adc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of ADC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_ADC_H
00040 #define __STM32L4xx_LL_ADC_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
00054
00055 /** @defgroup ADC_LL ADC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
00064   * @{
00065   */
00066
00067 /* Internal mask for ADC group regular sequencer:                             */
00068 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
00069 /* - sequencer register offset                                                */
00070 /* - sequencer rank bits position into the selected register                  */
00071
00072 /* Internal register offset for ADC group regular sequencer configuration */
00073 /* (offset placed into a spare area of literal definition) */
00074 #define ADC_SQR1_REGOFFSET                 ((uint32_t)0x00000000U)
00075 #define ADC_SQR2_REGOFFSET                 ((uint32_t)0x00000100U)
00076 #define ADC_SQR3_REGOFFSET                 ((uint32_t)0x00000200U)
00077 #define ADC_SQR4_REGOFFSET                 ((uint32_t)0x00000300U)
00078
00079 #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
00080 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00081
00082 /* Definition of ADC group regular sequencer bits information to be inserted  */
00083 /* into ADC group regular sequencer ranks literals definition.                */
00084 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
00085 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
00086 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
00087 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
00088 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
00089 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
00090 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
00091 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
00092 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
00093 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
00094 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
00095 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
00096 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
00097 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
00098 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
00099 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
00100
00101
00102
00103 /* Internal mask for ADC group injected sequencer:                            */
00104 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
00105 /* - data register offset                                                     */
00106 /* - sequencer rank bits position into the selected register                  */
00107
00108 /* Internal register offset for ADC group injected data register */
00109 /* (offset placed into a spare area of literal definition) */
00110 #define ADC_JDR1_REGOFFSET                 ((uint32_t)0x00000000U)
00111 #define ADC_JDR2_REGOFFSET                 ((uint32_t)0x00000100U)
00112 #define ADC_JDR3_REGOFFSET                 ((uint32_t)0x00000200U)
00113 #define ADC_JDR4_REGOFFSET                 ((uint32_t)0x00000300U)
00114
00115 #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
00116 #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00117
00118 /* Definition of ADC group injected sequencer bits information to be inserted */
00119 /* into ADC group injected sequencer ranks literals definition.               */
00120 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
00121 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
00122 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
00123 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
00124
00125
00126
00127 /* Internal mask for ADC group regular trigger:                               */
00128 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
00129 /* - regular trigger source                                                   */
00130 /* - regular trigger edge                                                     */
00131 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00132
00133 /* Mask containing trigger source masks for each of possible                  */
00134 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00135 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00136 #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \
00137                                              ((ADC_CFGR_EXTSEL)                            << (4U * 1U)) | \
00138                                              ((ADC_CFGR_EXTSEL)                            << (4U * 2U)) | \
00139                                              ((ADC_CFGR_EXTSEL)                            << (4U * 3U))  )
00140
00141 /* Mask containing trigger edge masks for each of possible                    */
00142 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00143 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00144 #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \
00145                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1U)) | \
00146                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2U)) | \
00147                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3U))  )
00148
00149 /* Definition of ADC group regular trigger bits information.                  */
00150 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
00151 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
00152
00153
00154
00155 /* Internal mask for ADC group injected trigger:                              */
00156 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
00157 /* - injected trigger source                                                  */
00158 /* - injected trigger edge                                                    */
00159 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00160
00161 /* Mask containing trigger source masks for each of possible                  */
00162 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00163 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00164 #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \
00165                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1U)) | \
00166                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2U)) | \
00167                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3U))  )
00168
00169 /* Mask containing trigger edge masks for each of possible                    */
00170 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00171 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00172 #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \
00173                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1U)) | \
00174                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2U)) | \
00175                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3U))  )
00176
00177 /* Definition of ADC group injected trigger bits information.                 */
00178 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
00179 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
00180
00181
00182
00183
00184
00185
00186 /* Internal mask for ADC channel:                                             */
00187 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
00188 /* - channel identifier defined by number                                     */
00189 /* - channel identifier defined by bitfield                                   */
00190 /* - channel differentiation between external channels (connected to          */
00191 /*   GPIO pins) and internal channels (connected to internal paths)           */
00192 /* - channel sampling time defined by SMPRx register offset                   */
00193 /*   and SMPx bits positions into SMPRx register                              */
00194 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
00195 #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
00196 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
00197 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
00198 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
00199 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
00200
00201 /* Channel differentiation between external and internal channels */
00202 #define ADC_CHANNEL_ID_INTERNAL_CH         ((uint32_t)0x80000000U) /* Marker of internal channel */
00203 #define ADC_CHANNEL_ID_INTERNAL_CH_2       ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
00204 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
00205
00206 /* Internal register offset for ADC channel sampling time configuration */
00207 /* (offset placed into a spare area of literal definition) */
00208 #define ADC_SMPR1_REGOFFSET                ((uint32_t)0x00000000U)
00209 #define ADC_SMPR2_REGOFFSET                ((uint32_t)0x02000000U)
00210 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
00211
00212 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    ((uint32_t)0x01F00000U)
00213 #define ADC_CHANNEL_SMPx_BITOFFSET_POS     ((uint32_t)20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
00214
00215 /* Definition of channels ID number information to be inserted into           */
00216 /* channels literals definition.                                              */
00217 #define ADC_CHANNEL_0_NUMBER               ((uint32_t)0x00000000U)
00218 #define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)
00219 #define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )
00220 #define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00221 #define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )
00222 #define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
00223 #define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
00224 #define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00225 #define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )
00226 #define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)
00227 #define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )
00228 #define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00229 #define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )
00230 #define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
00231 #define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
00232 #define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00233 #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )
00234 #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)
00235 #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )
00236
00237 /* Definition of channels ID bitfield information to be inserted into         */
00238 /* channels literals definition.                                              */
00239 #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
00240 #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
00241 #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
00242 #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
00243 #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
00244 #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
00245 #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
00246 #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
00247 #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
00248 #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
00249 #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
00250 #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
00251 #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
00252 #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
00253 #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
00254 #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
00255 #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
00256 #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
00257 #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
00258
00259 /* Definition of channels sampling time information to be inserted into       */
00260 /* channels literals definition.                                              */
00261 #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
00262 #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
00263 #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
00264 #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
00265 #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
00266 #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
00267 #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
00268 #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
00269 #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
00270 #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
00271 #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
00272 #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
00273 #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
00274 #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
00275 #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
00276 #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
00277 #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
00278 #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
00279 #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
00280
00281
00282 /* Internal mask for ADC mode single or differential ended:                   */
00283 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
00284 /* the relevant bits for:                                                     */
00285 /* (concatenation of multiple bits used in different registers)               */
00286 /* - ADC calibration: calibration start, calibration factor get or set        */
00287 /* - ADC channels: set each ADC channel ending mode                           */
00288 #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
00289 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
00290 #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
00291 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
00292
00293
00294 /* Internal mask for ADC analog watchdog:                                     */
00295 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
00296 /* (concatenation of multiple bits used in different analog watchdogs,        */
00297 /* (feature of several watchdogs not available on all STM32 families)).       */
00298 /* - analog watchdog 1: monitored channel defined by number,                  */
00299 /*   selection of ADC group (ADC groups regular and-or injected).             */
00300 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
00301 /*   selection on groups.                                                     */
00302
00303 /* Internal register offset for ADC analog watchdog channel configuration */
00304 #define ADC_AWD_CR1_REGOFFSET              ((uint32_t)0x00000000U)
00305 #define ADC_AWD_CR2_REGOFFSET              ((uint32_t)0x00100000U)
00306 #define ADC_AWD_CR3_REGOFFSET              ((uint32_t)0x00200000U)
00307
00308 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
00309 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
00310 #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
00311 #define ADC_AWD_CR12_REGOFFSETGAP_VAL      ((uint32_t)0x00000024U)
00312
00313 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
00314
00315 #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
00316 #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
00317 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
00318
00319 /* Internal register offset for ADC analog watchdog threshold configuration */
00320 #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
00321 #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
00322 #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
00323 #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
00324
00325
00326 /* Internal mask for ADC offset:                                              */
00327 /* Internal register offset for ADC offset number configuration */
00328 #define ADC_OFR1_REGOFFSET                 ((uint32_t)0x00000000U)
00329 #define ADC_OFR2_REGOFFSET                 ((uint32_t)0x00000001U)
00330 #define ADC_OFR3_REGOFFSET                 ((uint32_t)0x00000002U)
00331 #define ADC_OFR4_REGOFFSET                 ((uint32_t)0x00000003U)
00332 #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
00333
00334
00335 /* ADC registers bits positions */
00336 #define ADC_CFGR_RES_BITOFFSET_POS         ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
00337 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS     ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
00338 #define ADC_CFGR_AWD1EN_BITOFFSET_POS      ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
00339 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
00340 #define ADC_TR1_HT1_BITOFFSET_POS          ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
00341
00342
00343 /* ADC registers bits groups */
00344 #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
00345
00346
00347 /* ADC internal channels related definitions */
00348 /* Internal voltage reference VrefInt */
00349 #define VREFINT_CAL_ADDR                   ((uint16_t*) ((uint32_t)0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00350 #define VREFINT_CAL_VREF                   ((uint32_t) 3000U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
00351 /* Temperature sensor */
00352 #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) ((uint32_t)0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00353 #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) ((uint32_t)0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00354 #define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00355 #define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00356 #define TEMPSENSOR_CAL_VREFANALOG          ((uint32_t) 3000U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
00357
00358
00359 /**
00360   * @}
00361   */
00362
00363
00364 /* Private macros ------------------------------------------------------------*/
00365 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
00366   * @{
00367   */
00368
00369 /**
00370   * @brief  Driver macro reserved for internal use: isolate bits with the
00371   *         selected mask and shift them to the register LSB
00372   *         (shift mask on register position bit 0).
00373   * @param  __BITS__ Bits in register 32 bits
00374   * @param  __MASK__ Mask in register 32 bits
00375   * @retval Bits in register 32 bits
00376   */
00377 #define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \
00378   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
00379
00380 /**
00381   * @brief  Driver macro reserved for internal use: set a pointer to
00382   *         a register from a register basis from which an offset
00383   *         is applied.
00384   * @param  __REG__ Register basis from which the offset is applied.
00385   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00386   * @retval Pointer to register address
00387   */
00388 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00389  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
00390
00391 /**
00392   * @}
00393   */
00394
00395
00396 /* Exported types ------------------------------------------------------------*/
00397 #if defined(USE_FULL_LL_DRIVER)
00398 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
00399   * @{
00400   */
00401
00402 /**
00403   * @brief  Structure definition of some features of ADC common parameters
00404   *         and multimode
00405   *         (all ADC instances belonging to the same ADC common instance).
00406   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
00407   *         is conditioned to ADC instances state (all ADC instances
00408   *         sharing the same ADC common instance):
00409   *         All ADC instances sharing the same ADC common instance must be
00410   *         disabled.
00411   */
00412 typedef struct
00413 {
00414   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
00415                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
00416                                              @note On this STM32 serie, if ADC group injected is used, some
00417                                                    clock ratio constraints between ADC clock and AHB clock
00418                                                    must be respected. Refer to reference manual.
00419
00420                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
00421
00422 #if defined(ADC_MULTIMODE_SUPPORT)
00423   uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
00424                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
00425
00426                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
00427
00428   uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
00429                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
00430
00431                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
00432
00433   uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
00434                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
00435
00436                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
00437 #endif /* ADC_MULTIMODE_SUPPORT */
00438
00439 } LL_ADC_CommonInitTypeDef;
00440
00441 /**
00442   * @brief  Structure definition of some features of ADC instance.
00443   * @note   These parameters have an impact on ADC scope: ADC instance.
00444   *         Affects both group regular and group injected (availability
00445   *         of ADC group injected depends on STM32 families).
00446   *         Refer to corresponding unitary functions into
00447   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00448   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00449   *         is conditioned to ADC state:
00450   *         ADC instance must be disabled.
00451   *         This condition is applied to all ADC features, for efficiency
00452   *         and compatibility over all STM32 families. However, the different
00453   *         features can be set under different ADC state conditions
00454   *         (setting possible with ADC enabled without conversion on going,
00455   *         ADC enabled with conversion on going, ...)
00456   *         Each feature can be updated afterwards with a unitary function
00457   *         and potentially with ADC in a different state than disabled,
00458   *         refer to description of each function for setting
00459   *         conditioned to ADC state.
00460   */
00461 typedef struct
00462 {
00463   uint32_t Resolution;                  /*!< Set ADC resolution.
00464                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
00465
00466                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
00467
00468   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
00469                                              This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
00470
00471                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
00472
00473   uint32_t LowPowerMode;                /*!< Set ADC low power mode.
00474                                              This parameter can be a value of @ref ADC_LL_EC_LP_MODE
00475
00476                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
00477
00478 } LL_ADC_InitTypeDef;
00479
00480 /**
00481   * @brief  Structure definition of some features of ADC group regular.
00482   * @note   These parameters have an impact on ADC scope: ADC group regular.
00483   *         Refer to corresponding unitary functions into
00484   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00485   *         (functions with prefix "REG").
00486   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
00487   *         is conditioned to ADC state:
00488   *         ADC instance must be disabled.
00489   *         This condition is applied to all ADC features, for efficiency
00490   *         and compatibility over all STM32 families. However, the different
00491   *         features can be set under different ADC state conditions
00492   *         (setting possible with ADC enabled without conversion on going,
00493   *         ADC enabled with conversion on going, ...)
00494   *         Each feature can be updated afterwards with a unitary function
00495   *         and potentially with ADC in a different state than disabled,
00496   *         refer to description of each function for setting
00497   *         conditioned to ADC state.
00498   */
00499 typedef struct
00500 {
00501   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
00502                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
00503                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
00504                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
00505                                                    In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
00506
00507                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
00508
00509   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
00510                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
00511
00512                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
00513
00514   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00515                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
00516                                              @note This parameter has an effect only if group regular sequencer is enabled
00517                                                    (scan length of 2 ranks or more).
00518
00519                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
00520
00521   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
00522                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
00523                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
00524
00525                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
00526
00527   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
00528                                              This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
00529
00530                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
00531
00532   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
00533                                              data preserved or overwritten.
00534                                              This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
00535
00536                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
00537
00538 } LL_ADC_REG_InitTypeDef;
00539
00540 /**
00541   * @brief  Structure definition of some features of ADC group injected.
00542   * @note   These parameters have an impact on ADC scope: ADC group injected.
00543   *         Refer to corresponding unitary functions into
00544   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00545   *         (functions with prefix "INJ").
00546   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
00547   *         is conditioned to ADC state:
00548   *         ADC instance must be disabled.
00549   *         This condition is applied to all ADC features, for efficiency
00550   *         and compatibility over all STM32 families. However, the different
00551   *         features can be set under different ADC state conditions
00552   *         (setting possible with ADC enabled without conversion on going,
00553   *         ADC enabled with conversion on going, ...)
00554   *         Each feature can be updated afterwards with a unitary function
00555   *         and potentially with ADC in a different state than disabled,
00556   *         refer to description of each function for setting
00557   *         conditioned to ADC state.
00558   */
00559 typedef struct
00560 {
00561   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
00562                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
00563                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
00564                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
00565                                                    In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
00566
00567                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
00568
00569   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
00570                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
00571
00572                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
00573
00574   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00575                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
00576                                              @note This parameter has an effect only if group injected sequencer is enabled
00577                                                    (scan length of 2 ranks or more).
00578
00579                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
00580
00581   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
00582                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
00583                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
00584
00585                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
00586
00587 } LL_ADC_INJ_InitTypeDef;
00588
00589 /**
00590   * @}
00591   */
00592 #endif /* USE_FULL_LL_DRIVER */
00593
00594 /* Exported constants --------------------------------------------------------*/
00595 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
00596   * @{
00597   */
00598
00599 /** @defgroup ADC_LL_EC_FLAG ADC flags
00600   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
00601   * @{
00602   */
00603 #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
00604 #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
00605 #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
00606 #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
00607 #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
00608 #define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */
00609 #define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */
00610 #define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */
00611 #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
00612 #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
00613 #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
00614 #if defined(ADC_MULTIMODE_SUPPORT)
00615 #define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */
00616 #define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */
00617 #define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of unitary conversion */
00618 #define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
00619 #define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of sequence conversions */
00620 #define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
00621 #define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular overrun */
00622 #define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular overrun */
00623 #define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of sampling phase */
00624 #define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of sampling phase */
00625 #define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of unitary conversion */
00626 #define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
00627 #define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of sequence conversions */
00628 #define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
00629 #define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected contexts queue overflow */
00630 #define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
00631 #define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
00632 #define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
00633 #define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
00634 #define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
00635 #define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
00636 #define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
00637 #endif
00638 /**
00639   * @}
00640   */
00641
00642 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
00643   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
00644   * @{
00645   */
00646 #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
00647 #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */
00648 #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */
00649 #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
00650 #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */
00651 #define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */
00652 #define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */
00653 #define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */
00654 #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
00655 #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
00656 #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
00657 /**
00658   * @}
00659   */
00660
00661 /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
00662   * @{
00663   */
00664 /* List of ADC registers intended to be used (most commonly) with             */
00665 /* DMA transfer.                                                              */
00666 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
00667 #define LL_ADC_DMA_REG_REGULAR_DATA          ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
00668 #if defined(ADC_MULTIMODE_SUPPORT)
00669 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
00670 #endif
00671 /**
00672   * @}
00673   */
00674
00675 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00676   * @{
00677   */
00678 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */
00679 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
00680 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
00681 #define LL_ADC_CLOCK_ASYNC_DIV1            ((uint32_t)0x00000000U)                               /*!< ADC asynchronous clock without prescaler */
00682 #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */
00683 #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */
00684 #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6   */
00685 #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8   */
00686 #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10  */
00687 #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12  */
00688 #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16  */
00689 #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32  */
00690 #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64  */
00691 #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128 */
00692 #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
00693 /**
00694   * @}
00695   */
00696
00697 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
00698   * @{
00699   */
00700 /* Note: Other measurement paths to internal channels may be available        */
00701 /*       (connections to other peripherals).                                  */
00702 /*       If they are not listed below, they do not require any specific       */
00703 /*       path enable. In this case, Access to measurement path is done        */
00704 /*       only by selecting the corresponding ADC internal channel.            */
00705 #define LL_ADC_PATH_INTERNAL_NONE          ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
00706 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
00707 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */
00708 #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */
00709 /**
00710   * @}
00711   */
00712
00713 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
00714   * @{
00715   */
00716 #define LL_ADC_RESOLUTION_12B              ((uint32_t)0x00000000U)             /*!< ADC resolution 12 bits */
00717 #define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */
00718 #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */
00719 #define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */
00720 /**
00721   * @}
00722   */
00723
00724 /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
00725   * @{
00726   */
00727 #define LL_ADC_DATA_ALIGN_RIGHT            ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
00728 #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)       /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
00729 /**
00730   * @}
00731   */
00732
00733 /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
00734   * @{
00735   */
00736 #define LL_ADC_LP_MODE_NONE                ((uint32_t)0x00000000U)              /*!< No ADC low power mode activated */
00737 #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
00738 /**
00739   * @}
00740   */
00741
00742 /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number
00743   * @{
00744   */
00745 #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00746 #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00747 #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00748 #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00749 /**
00750   * @}
00751   */
00752
00753 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
00754   * @{
00755   */
00756 #define LL_ADC_OFFSET_DISABLE              ((uint32_t)0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
00757 #define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
00758 /**
00759   * @}
00760   */
00761
00762 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
00763   * @{
00764   */
00765 #define LL_ADC_GROUP_REGULAR               ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
00766 #define LL_ADC_GROUP_INJECTED              ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
00767 #define LL_ADC_GROUP_REGULAR_INJECTED      ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
00768 /**
00769   * @}
00770   */
00771
00772 /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
00773   * @{
00774   */
00775 #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
00776 #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
00777 #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
00778 #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
00779 #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
00780 #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
00781 #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
00782 #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
00783 #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
00784 #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
00785 #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
00786 #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
00787 #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
00788 #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
00789 #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
00790 #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
00791 #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
00792 #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
00793 #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
00794 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_0  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. */
00795 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
00796 #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
00797 #if defined(ADC1) && !defined(ADC2)
00798 #define LL_ADC_CHANNEL_DAC1CH1             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
00799 #define LL_ADC_CHANNEL_DAC1CH2             (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
00800 #elif defined(ADC2)
00801 #define LL_ADC_CHANNEL_DAC1CH1_ADC2        (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
00802 #define LL_ADC_CHANNEL_DAC1CH2_ADC2        (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
00803 #if defined(ADC3)
00804 #define LL_ADC_CHANNEL_DAC1CH1_ADC3        (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
00805 #define LL_ADC_CHANNEL_DAC1CH2_ADC3        (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
00806 #endif
00807 #endif
00808 /**
00809   * @}
00810   */
00811
00812 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
00813   * @{
00814   */
00815 #define LL_ADC_REG_TRIG_SOFTWARE           ((uint32_t)0x00000000U)                                                                                         /*!< ADC group regular conversion trigger internal: SW start. */
00816 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00817 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00818 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00819 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00820 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00821 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00822 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00823 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00824 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00825 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00826 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00827 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00828 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
00829 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
00830 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00831 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00832 /**
00833   * @}
00834   */
00835
00836 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
00837   * @{
00838   */
00839 #define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */
00840 #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */
00841 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
00842 /**
00843   * @}
00844   */
00845
00846 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
00847 * @{
00848 */
00849 #define LL_ADC_REG_CONV_SINGLE             ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
00850 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
00851 /**
00852   * @}
00853   */
00854
00855 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
00856   * @{
00857   */
00858 #define LL_ADC_REG_DMA_TRANSFER_NONE       ((uint32_t)0x00000000U)              /*!< ADC conversions are not transferred by DMA */
00859 #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)   /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
00860 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)   /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
00861 /**
00862   * @}
00863   */
00864
00865 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
00866 * @{
00867 */
00868 #define LL_ADC_REG_OVR_DATA_PRESERVED      ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
00869 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */
00870 /**
00871   * @}
00872   */
00873
00874 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
00875   * @{
00876   */
00877 #define LL_ADC_REG_SEQ_SCAN_DISABLE        ((uint32_t)0x00000000U)                                     /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
00878 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
00879 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
00880 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
00881 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
00882 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
00883 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
00884 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
00885 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
00886 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
00887 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
00888 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
00889 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
00890 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
00891 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
00892 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
00893 /**
00894   * @}
00895   */
00896
00897 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
00898   * @{
00899   */
00900 #define LL_ADC_REG_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000U)                                                          /*!< ADC group regular sequencer discontinuous mode disable */
00901 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
00902 #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
00903 #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
00904 #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
00905 #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
00906 #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
00907 #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
00908 #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
00909 /**
00910   * @}
00911   */
00912
00913 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
00914   * @{
00915   */
00916 #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
00917 #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
00918 #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
00919 #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
00920 #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
00921 #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
00922 #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
00923 #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
00924 #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
00925 #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
00926 #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
00927 #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
00928 #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
00929 #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
00930 #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
00931 #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
00932 /**
00933   * @}
00934   */
00935
00936 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
00937   * @{
00938   */
00939 #define LL_ADC_INJ_TRIG_SOFTWARE           ((uint32_t)0x00000000U)                                                                                             /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
00940 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                     /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00941 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00942 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00943 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00944 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00945 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00946 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00947 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00948 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00949 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00950 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00951 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00952 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
00953 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
00954 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00955 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
00956 /**
00957   * @}
00958   */
00959
00960 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
00961   * @{
00962   */
00963 #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
00964 #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */
00965 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
00966 /**
00967   * @}
00968   */
00969
00970 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
00971 * @{
00972 */
00973 #define LL_ADC_INJ_TRIG_INDEPENDENT        ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
00974 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
00975 /**
00976   * @}
00977   */
00978
00979 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
00980   * @{
00981   */
00982 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
00983 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
00984 #define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
00985 /**
00986   * @}
00987   */
00988
00989 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
00990   * @{
00991   */
00992 #define LL_ADC_INJ_SEQ_SCAN_DISABLE        ((uint32_t)0x00000000U)         /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
00993 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
00994 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
00995 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
00996 /**
00997   * @}
00998   */
00999
01000 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
01001   * @{
01002   */
01003 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
01004 #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
01005 /**
01006   * @}
01007   */
01008
01009 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
01010   * @{
01011   */
01012 #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
01013 #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
01014 #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
01015 #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
01016 /**
01017   * @}
01018   */
01019
01020 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
01021   * @{
01022   */
01023 #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000U)                                               /*!< Sampling time 2.5 ADC clock cycles */
01024 #define LL_ADC_SAMPLINGTIME_6CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
01025 #define LL_ADC_SAMPLINGTIME_12CYCLES_5     (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 12.5 ADC clock cycles */
01026 #define LL_ADC_SAMPLINGTIME_24CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
01027 #define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 47.5 ADC clock cycles */
01028 #define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
01029 #define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 247.5 ADC clock cycles */
01030 #define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
01031 /**
01032   * @}
01033   */
01034
01035 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
01036   * @{
01037   */
01038 #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
01039 #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
01040 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
01041 /**
01042   * @}
01043   */
01044
01045 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
01046   * @{
01047   */
01048 #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
01049 #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
01050 #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
01051 /**
01052   * @}
01053   */
01054
01055 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
01056   * @{
01057   */
01058 #define LL_ADC_AWD_DISABLE                 ((uint32_t)0x00000000U)                                                                             /*!< ADC analog watchdog monitoring disabled */
01059 #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
01060 #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
01061 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
01062 #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
01063 #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
01064 #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
01065 #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
01066 #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
01067 #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
01068 #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
01069 #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
01070 #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
01071 #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
01072 #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
01073 #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
01074 #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
01075 #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
01076 #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
01077 #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
01078 #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
01079 #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
01080 #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
01081 #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
01082 #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
01083 #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
01084 #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
01085 #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
01086 #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
01087 #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
01088 #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
01089 #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
01090 #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
01091 #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
01092 #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
01093 #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
01094 #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
01095 #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
01096 #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
01097 #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
01098 #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
01099 #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
01100 #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
01101 #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
01102 #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
01103 #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
01104 #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
01105 #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
01106 #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
01107 #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
01108 #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
01109 #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
01110 #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
01111 #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
01112 #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
01113 #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
01114 #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
01115 #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
01116 #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
01117 #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
01118 #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
01119 #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
01120 #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
01121 #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
01122 #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
01123 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
01124 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
01125 #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
01126 #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
01127 #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
01128 #if defined(ADC1) && !defined(ADC2)
01129 #define LL_ADC_AWD_CH_DAC1CH1_REG          ((LL_ADC_CHANNEL_DAC1CH1       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */
01130 #define LL_ADC_AWD_CH_DAC1CH1_INJ          ((LL_ADC_CHANNEL_DAC1CH1       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */
01131 #define LL_ADC_AWD_CH_DAC1CH1_REG_INJ      ((LL_ADC_CHANNEL_DAC1CH1       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */
01132 #define LL_ADC_AWD_CH_DAC1CH2_REG          ((LL_ADC_CHANNEL_DAC1CH2       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */
01133 #define LL_ADC_AWD_CH_DAC1CH2_INJ          ((LL_ADC_CHANNEL_DAC1CH2       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */
01134 #define LL_ADC_AWD_CH_DAC1CH2_REG_INJ      ((LL_ADC_CHANNEL_DAC1CH2       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */
01135 #elif defined(ADC2)
01136 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
01137 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
01138 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
01139 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
01140 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
01141 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
01142 #if defined(ADC3)
01143 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
01144 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
01145 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
01146 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
01147 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
01148 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
01149 #endif
01150 #endif
01151 /**
01152   * @}
01153   */
01154
01155 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
01156   * @{
01157   */
01158 #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog threshold high */
01159 #define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
01160 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
01161 /**
01162   * @}
01163   */
01164
01165 /** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
01166   * @{
01167   */
01168 #define LL_ADC_OVS_DISABLE                 ((uint32_t)0x00000000U)                               /*!< ADC oversampling disabled. */
01169 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
01170 #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
01171 #define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */
01172 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
01173 /**
01174   * @}
01175   */
01176
01177 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
01178   * @{
01179   */
01180 #define LL_ADC_OVS_REG_CONT                ((uint32_t)0x00000000U)/*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
01181 #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
01182 /**
01183   * @}
01184   */
01185
01186 /** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
01187   * @{
01188   */
01189 #define LL_ADC_OVS_RATIO_2                 ((uint32_t)0x00000000U)                                  /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01190 #define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01191 #define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01192 #define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01193 #define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01194 #define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01195 #define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01196 #define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01197 /**
01198   * @}
01199   */
01200
01201 /** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift
01202   * @{
01203   */
01204 #define LL_ADC_OVS_SHIFT_NONE              ((uint32_t)0x00000000U)                                                     /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
01205 #define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
01206 #define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
01207 #define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
01208 #define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
01209 #define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
01210 #define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
01211 #define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
01212 #define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
01213 /**
01214   * @}
01215   */
01216
01217 #if defined(ADC_MULTIMODE_SUPPORT)
01218 /** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
01219   * @{
01220   */
01221 #define LL_ADC_MULTI_INDEPENDENT           ((uint32_t)0x00000000U)                                             /*!< ADC dual mode disabled (ADC independent mode) */
01222 #define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: group regular simultaneous */
01223 #define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
01224 #define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
01225 #define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
01226 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
01227 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
01228 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
01229 /**
01230   * @}
01231   */
01232
01233 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
01234   * @{
01235   */
01236 #define LL_ADC_MULTI_REG_DMA_EACH_ADC        ((uint32_t)0x00000000U)                            /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
01237 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (                 ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
01238 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B   (                 ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
01239 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
01240 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B   (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
01241 /**
01242   * @}
01243   */
01244
01245 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
01246   * @{
01247   */
01248 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   ((uint32_t)0x00000000U)                                                 /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
01249 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
01250 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
01251 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
01252 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
01253 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
01254 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
01255 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
01256 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
01257 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3                                     | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
01258 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
01259 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
01260 /**
01261   * @}
01262   */
01263
01264 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
01265   * @{
01266   */
01267 #define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
01268 #define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */
01269 #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
01270 /**
01271   * @}
01272   */
01273
01274 #endif /* ADC_MULTIMODE_SUPPORT */
01275
01276 /** @defgroup ADC_LL_EC_LEGACY ADC literals legacy naming
01277   * @{
01278   */
01279 #define LL_ADC_REG_TRIG_SW_START           (LL_ADC_REG_TRIG_SOFTWARE)
01280 #define LL_ADC_REG_TRIG_EXT_TIM1_CC1       (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
01281 #define LL_ADC_REG_TRIG_EXT_TIM1_CC2       (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
01282 #define LL_ADC_REG_TRIG_EXT_TIM1_CC3       (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
01283 #define LL_ADC_REG_TRIG_EXT_TIM2_CC2       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
01284 #define LL_ADC_REG_TRIG_EXT_TIM3_CC4       (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
01285 #define LL_ADC_REG_TRIG_EXT_TIM4_CC4       (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
01286
01287 #define LL_ADC_INJ_TRIG_SW_START           (LL_ADC_INJ_TRIG_SOFTWARE)
01288 #define LL_ADC_INJ_TRIG_EXT_TIM1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
01289 #define LL_ADC_INJ_TRIG_EXT_TIM2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
01290 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
01291 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC3       (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
01292 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC4       (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
01293 #define LL_ADC_INJ_TRIG_EXT_TIM8_CC4       (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
01294
01295 #define LL_ADC_OVS_DATA_SHIFT_NONE        (LL_ADC_OVS_SHIFT_NONE)
01296 #define LL_ADC_OVS_DATA_SHIFT_1           (LL_ADC_OVS_SHIFT_RIGHT_1)
01297 #define LL_ADC_OVS_DATA_SHIFT_2           (LL_ADC_OVS_SHIFT_RIGHT_2)
01298 #define LL_ADC_OVS_DATA_SHIFT_3           (LL_ADC_OVS_SHIFT_RIGHT_3)
01299 #define LL_ADC_OVS_DATA_SHIFT_4           (LL_ADC_OVS_SHIFT_RIGHT_4)
01300 #define LL_ADC_OVS_DATA_SHIFT_5           (LL_ADC_OVS_SHIFT_RIGHT_5)
01301 #define LL_ADC_OVS_DATA_SHIFT_6           (LL_ADC_OVS_SHIFT_RIGHT_6)
01302 #define LL_ADC_OVS_DATA_SHIFT_7           (LL_ADC_OVS_SHIFT_RIGHT_7)
01303 #define LL_ADC_OVS_DATA_SHIFT_8           (LL_ADC_OVS_SHIFT_RIGHT_8)
01304
01305 /**
01306   * @}
01307   */
01308
01309
01310 /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
01311   * @note   Only ADC IP HW delays are defined in ADC LL driver driver,
01312   *         not timeout values.
01313   *         For details on delays values, refer to descriptions in source code
01314   *         above each literal definition.
01315   * @{
01316   */
01317
01318 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
01319 /*       not timeout values.                                                  */
01320 /*       Timeout values for ADC operations are dependent to device clock      */
01321 /*       configuration (system clock versus ADC clock),                       */
01322 /*       and therefore must be defined in user application.                   */
01323 /*       Indications for estimation of ADC timeout delays, for this           */
01324 /*       STM32 serie:                                                         */
01325 /*       - ADC calibration time: maximum delay is 112/fADC.                   */
01326 /*         (refer to device datasheet, parameter "tCAL")                      */
01327 /*       - ADC enable time: maximum delay is 1 conversion cycle.              */
01328 /*         (refer to device datasheet, parameter "tSTAB")                     */
01329 /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
01330 /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
01331 /*         cycles                                                             */
01332 /*       - ADC conversion time: duration depending on ADC clock and ADC       */
01333 /*         configuration.                                                     */
01334 /*         (refer to device reference manual, section "Timing")               */
01335
01336 /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
01337 /* Delay set to maximum value (refer to device datasheet,                     */
01338 /* parameter "tADCVREG_STUP").                                                */
01339 /* Unit: us                                                                   */
01340 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t)  10U)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
01341
01342 /* Delay for internal voltage reference stabilization time.                   */
01343 /* Delay set to maximum value (refer to device datasheet,                     */
01344 /* parameter "tstart_vrefint").                                               */
01345 /* Unit: us                                                                   */
01346 #define LL_ADC_DELAY_VREFINT_STAB_US       ((uint32_t)  12U)  /*!< Delay for internal voltage reference stabilization time */
01347
01348 /* Delay for temperature sensor stabilization time.                           */
01349 /* Literal set to maximum value (refer to device datasheet,                   */
01350 /* parameter "tSTART").                                                       */
01351 /* Unit: us                                                                   */
01352 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ((uint32_t) 120U)  /*!< Delay for temperature sensor stabilization time */
01353
01354 /* Delay required between ADC end of calibration and ADC enable.              */
01355 /* Note: On this STM32 serie, a minimum number of ADC clock cycles            */
01356 /*       are required between ADC end of calibration and ADC enable.          */
01357 /*       Wait time can be computed in user application by waiting for the     */
01358 /*       equivalent number of CPU cycles, by taking into account              */
01359 /*       ratio of CPU clock versus ADC clock prescalers.                      */
01360 /* Unit: ADC clock cycles.                                                    */
01361 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U)  /*!< Delay required between ADC end of calibration and ADC enable */
01362
01363 /**
01364   * @}
01365   */
01366
01367 /**
01368   * @}
01369   */
01370
01371
01372 /* Exported macro ------------------------------------------------------------*/
01373 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
01374   * @{
01375   */
01376
01377 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
01378   * @{
01379   */
01380
01381 /**
01382   * @brief  Write a value in ADC register
01383   * @param  __INSTANCE__ ADC Instance
01384   * @param  __REG__ Register to be written
01385   * @param  __VALUE__ Value to be written in the register
01386   * @retval None
01387   */
01388 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01389
01390 /**
01391   * @brief  Read a value in ADC register
01392   * @param  __INSTANCE__ ADC Instance
01393   * @param  __REG__ Register to be read
01394   * @retval Register value
01395   */
01396 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01397 /**
01398   * @}
01399   */
01400
01401 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
01402   * @{
01403   */
01404
01405 /**
01406   * @brief  Helper macro to get ADC channel number in decimal format
01407   *         from literals LL_ADC_CHANNEL_x.
01408   * @note   Example:
01409   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
01410   *           will return decimal number "4".
01411   * @note   The input can be a value from functions where a channel
01412   *         number is returned, either defined with number
01413   *         or with bitfield (only one bit must be set).
01414   * @param  __CHANNEL__ This parameter can be one of the following values:
01415   *         @arg @ref LL_ADC_CHANNEL_0
01416   *         @arg @ref LL_ADC_CHANNEL_1            (7)
01417   *         @arg @ref LL_ADC_CHANNEL_2            (7)
01418   *         @arg @ref LL_ADC_CHANNEL_3            (7)
01419   *         @arg @ref LL_ADC_CHANNEL_4            (7)
01420   *         @arg @ref LL_ADC_CHANNEL_5            (7)
01421   *         @arg @ref LL_ADC_CHANNEL_6
01422   *         @arg @ref LL_ADC_CHANNEL_7
01423   *         @arg @ref LL_ADC_CHANNEL_8
01424   *         @arg @ref LL_ADC_CHANNEL_9
01425   *         @arg @ref LL_ADC_CHANNEL_10
01426   *         @arg @ref LL_ADC_CHANNEL_11
01427   *         @arg @ref LL_ADC_CHANNEL_12
01428   *         @arg @ref LL_ADC_CHANNEL_13
01429   *         @arg @ref LL_ADC_CHANNEL_14
01430   *         @arg @ref LL_ADC_CHANNEL_15
01431   *         @arg @ref LL_ADC_CHANNEL_16
01432   *         @arg @ref LL_ADC_CHANNEL_17
01433   *         @arg @ref LL_ADC_CHANNEL_18
01434   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01435   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01436   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01437   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
01438   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
01439   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
01440   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
01441   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
01442   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
01443   *
01444   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
01445   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
01446   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
01447   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
01448   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
01449   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
01450   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01451   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01452   * @retval Value between Min_Data=0 and Max_Data=18
01453   */
01454 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
01455   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U)                                  \
01456     ? (                                                                                    \
01457        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
01458       )                                                                                    \
01459       :                                                                                    \
01460       (                                                                                    \
01461        POSITION_VAL((__CHANNEL__))                                                         \
01462       )                                                                                    \
01463   )
01464
01465 /**
01466   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
01467   *         from number in decimal format.
01468   * @note   Example:
01469   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01470   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
01471   * @param  __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
01472   * @retval Returned value can be one of the following values:
01473   *         @arg @ref LL_ADC_CHANNEL_0
01474   *         @arg @ref LL_ADC_CHANNEL_1            (7)
01475   *         @arg @ref LL_ADC_CHANNEL_2            (7)
01476   *         @arg @ref LL_ADC_CHANNEL_3            (7)
01477   *         @arg @ref LL_ADC_CHANNEL_4            (7)
01478   *         @arg @ref LL_ADC_CHANNEL_5            (7)
01479   *         @arg @ref LL_ADC_CHANNEL_6
01480   *         @arg @ref LL_ADC_CHANNEL_7
01481   *         @arg @ref LL_ADC_CHANNEL_8
01482   *         @arg @ref LL_ADC_CHANNEL_9
01483   *         @arg @ref LL_ADC_CHANNEL_10
01484   *         @arg @ref LL_ADC_CHANNEL_11
01485   *         @arg @ref LL_ADC_CHANNEL_12
01486   *         @arg @ref LL_ADC_CHANNEL_13
01487   *         @arg @ref LL_ADC_CHANNEL_14
01488   *         @arg @ref LL_ADC_CHANNEL_15
01489   *         @arg @ref LL_ADC_CHANNEL_16
01490   *         @arg @ref LL_ADC_CHANNEL_17
01491   *         @arg @ref LL_ADC_CHANNEL_18
01492   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01493   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01494   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01495   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
01496   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
01497   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
01498   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
01499   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
01500   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
01501   *
01502   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
01503   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
01504   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
01505   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
01506   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
01507   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
01508   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01509   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
01510   *         (1, 2, 3, 4) For ADC channel read back from ADC register,
01511   *                      comparison with internal channel parameter to be done
01512   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01513   */
01514 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                          \
01515   (((__DECIMAL_NB__) <= 9U)                                                                                     \
01516     ? (                                                                                                         \
01517        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \
01518        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                       |        \
01519        (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \
01520       )                                                                                                         \
01521       :                                                                                                         \
01522       (                                                                                                         \
01523        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \
01524        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                              | \
01525        (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
01526       )                                                                                                         \
01527   )
01528
01529 /**
01530   * @brief  Helper macro to determine whether the selected channel
01531   *         corresponds to literal definitions of driver.
01532   * @note   The different literal definitions of ADC channels are:
01533   *         - ADC internal channel:
01534   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
01535   *         - ADC external channel (channel connected to a GPIO pin):
01536   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
01537   * @note   The channel parameter must be a value defined from literal
01538   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01539   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01540   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
01541   *         must not be a value from functions where a channel number is
01542   *         returned from ADC registers,
01543   *         because internal and external channels share the same channel
01544   *         number in ADC registers. The differentiation is made only with
01545   *         parameters definitions of driver.
01546   * @param  __CHANNEL__ This parameter can be one of the following values:
01547   *         @arg @ref LL_ADC_CHANNEL_0
01548   *         @arg @ref LL_ADC_CHANNEL_1            (7)
01549   *         @arg @ref LL_ADC_CHANNEL_2            (7)
01550   *         @arg @ref LL_ADC_CHANNEL_3            (7)
01551   *         @arg @ref LL_ADC_CHANNEL_4            (7)
01552   *         @arg @ref LL_ADC_CHANNEL_5            (7)
01553   *         @arg @ref LL_ADC_CHANNEL_6
01554   *         @arg @ref LL_ADC_CHANNEL_7
01555   *         @arg @ref LL_ADC_CHANNEL_8
01556   *         @arg @ref LL_ADC_CHANNEL_9
01557   *         @arg @ref LL_ADC_CHANNEL_10
01558   *         @arg @ref LL_ADC_CHANNEL_11
01559   *         @arg @ref LL_ADC_CHANNEL_12
01560   *         @arg @ref LL_ADC_CHANNEL_13
01561   *         @arg @ref LL_ADC_CHANNEL_14
01562   *         @arg @ref LL_ADC_CHANNEL_15
01563   *         @arg @ref LL_ADC_CHANNEL_16
01564   *         @arg @ref LL_ADC_CHANNEL_17
01565   *         @arg @ref LL_ADC_CHANNEL_18
01566   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01567   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01568   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01569   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
01570   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
01571   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
01572   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
01573   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
01574   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
01575   *
01576   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
01577   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
01578   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
01579   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
01580   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
01581   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
01582   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01583   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01584   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
01585   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
01586   */
01587 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
01588   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
01589
01590 /**
01591   * @brief  Helper macro to convert a channel defined from parameter
01592   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01593   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01594   *         to its equivalent parameter definition of a ADC external channel
01595   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
01596   * @note   The channel parameter can be, additionally to a value
01597   *         defined from parameter definition of a ADC internal channel
01598   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
01599   *         a value defined from parameter definition of
01600   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01601   *         or a value from functions where a channel number is returned
01602   *         from ADC registers.
01603   * @param  __CHANNEL__ This parameter can be one of the following values:
01604   *         @arg @ref LL_ADC_CHANNEL_0
01605   *         @arg @ref LL_ADC_CHANNEL_1            (7)
01606   *         @arg @ref LL_ADC_CHANNEL_2            (7)
01607   *         @arg @ref LL_ADC_CHANNEL_3            (7)
01608   *         @arg @ref LL_ADC_CHANNEL_4            (7)
01609   *         @arg @ref LL_ADC_CHANNEL_5            (7)
01610   *         @arg @ref LL_ADC_CHANNEL_6
01611   *         @arg @ref LL_ADC_CHANNEL_7
01612   *         @arg @ref LL_ADC_CHANNEL_8
01613   *         @arg @ref LL_ADC_CHANNEL_9
01614   *         @arg @ref LL_ADC_CHANNEL_10
01615   *         @arg @ref LL_ADC_CHANNEL_11
01616   *         @arg @ref LL_ADC_CHANNEL_12
01617   *         @arg @ref LL_ADC_CHANNEL_13
01618   *         @arg @ref LL_ADC_CHANNEL_14
01619   *         @arg @ref LL_ADC_CHANNEL_15
01620   *         @arg @ref LL_ADC_CHANNEL_16
01621   *         @arg @ref LL_ADC_CHANNEL_17
01622   *         @arg @ref LL_ADC_CHANNEL_18
01623   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01624   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01625   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01626   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
01627   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
01628   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
01629   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
01630   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
01631   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
01632   *
01633   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
01634   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
01635   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
01636   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
01637   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
01638   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
01639   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01640   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01641   * @retval Returned value can be one of the following values:
01642   *         @arg @ref LL_ADC_CHANNEL_0
01643   *         @arg @ref LL_ADC_CHANNEL_1
01644   *         @arg @ref LL_ADC_CHANNEL_2
01645   *         @arg @ref LL_ADC_CHANNEL_3
01646   *         @arg @ref LL_ADC_CHANNEL_4
01647   *         @arg @ref LL_ADC_CHANNEL_5
01648   *         @arg @ref LL_ADC_CHANNEL_6
01649   *         @arg @ref LL_ADC_CHANNEL_7
01650   *         @arg @ref LL_ADC_CHANNEL_8
01651   *         @arg @ref LL_ADC_CHANNEL_9
01652   *         @arg @ref LL_ADC_CHANNEL_10
01653   *         @arg @ref LL_ADC_CHANNEL_11
01654   *         @arg @ref LL_ADC_CHANNEL_12
01655   *         @arg @ref LL_ADC_CHANNEL_13
01656   *         @arg @ref LL_ADC_CHANNEL_14
01657   *         @arg @ref LL_ADC_CHANNEL_15
01658   *         @arg @ref LL_ADC_CHANNEL_16
01659   *         @arg @ref LL_ADC_CHANNEL_17
01660   *         @arg @ref LL_ADC_CHANNEL_18
01661   */
01662 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
01663   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
01664
01665 /**
01666   * @brief  Helper macro to determine whether the internal channel
01667   *         selected is available on the ADC instance selected.
01668   * @note   The channel parameter must be a value defined from parameter
01669   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01670   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01671   *         must not be a value defined from parameter definition of
01672   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01673   *         or a value from functions where a channel number is
01674   *         returned from ADC registers,
01675   *         because internal and external channels share the same channel
01676   *         number in ADC registers. The differentiation is made only with
01677   *         parameters definitions of driver.
01678   * @param  __ADC_INSTANCE__ ADC instance
01679   * @param  __CHANNEL__ This parameter can be one of the following values:
01680   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01681   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01682   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01683   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
01684   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
01685   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
01686   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
01687   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
01688   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
01689   *
01690   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
01691   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
01692   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
01693   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
01694   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
01695   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
01696   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
01697   *         Value "1" if the internal channel selected is available on the ADC instance selected.
01698   */
01699 #if defined (ADC1) && defined (ADC2) && defined (ADC3)
01700 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01701   (((__ADC_INSTANCE__) == ADC1)                                                \
01702     ? (                                                                        \
01703        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
01704        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
01705        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                  \
01706       )                                                                        \
01707       :                                                                        \
01708       ((__ADC_INSTANCE__) == ADC2)                                             \
01709       ? (                                                                      \
01710          ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                     \
01711          ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                     \
01712          ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                        \
01713         )                                                                      \
01714         :                                                                      \
01715         ((__ADC_INSTANCE__) == ADC3)                                           \
01716         ? (                                                                    \
01717            ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                   \
01718            ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                   \
01719            ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                   \
01720            ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) ||                   \
01721            ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3)                      \
01722           )                                                                    \
01723           :                                                                    \
01724           (0U)                                                                 \
01725   )
01726 #elif defined (ADC1) && defined (ADC2)
01727 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01728   (((__ADC_INSTANCE__) == ADC1)                                                \
01729     ? (                                                                        \
01730        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
01731        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
01732        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                  \
01733       )                                                                        \
01734       :                                                                        \
01735       ((__ADC_INSTANCE__) == ADC2)                                             \
01736       ? (                                                                      \
01737          ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                     \
01738          ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                     \
01739          ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                        \
01740         )                                                                      \
01741         :                                                                      \
01742         (0U)                                                                   \
01743   )
01744 #elif defined (ADC1)
01745 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01746   (                                                                            \
01747     ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
01748     ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
01749     ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)       ||                            \
01750     ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1)    ||                            \
01751     ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2)                                  \
01752   )
01753 #endif
01754
01755 /**
01756   * @brief  Helper macro to define ADC analog watchdog parameter:
01757   *         define a single channel to monitor with analog watchdog
01758   *         from sequencer channel and groups definition.
01759   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
01760   *         Example:
01761   *           LL_ADC_SetAnalogWDMonitChannels(
01762   *             ADC1, LL_ADC_AWD1,
01763   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
01764   * @param  __CHANNEL__ This parameter can be one of the following values:
01765   *         @arg @ref LL_ADC_CHANNEL_0
01766   *         @arg @ref LL_ADC_CHANNEL_1            (7)
01767   *         @arg @ref LL_ADC_CHANNEL_2            (7)
01768   *         @arg @ref LL_ADC_CHANNEL_3            (7)
01769   *         @arg @ref LL_ADC_CHANNEL_4            (7)
01770   *         @arg @ref LL_ADC_CHANNEL_5            (7)
01771   *         @arg @ref LL_ADC_CHANNEL_6
01772   *         @arg @ref LL_ADC_CHANNEL_7
01773   *         @arg @ref LL_ADC_CHANNEL_8
01774   *         @arg @ref LL_ADC_CHANNEL_9
01775   *         @arg @ref LL_ADC_CHANNEL_10
01776   *         @arg @ref LL_ADC_CHANNEL_11
01777   *         @arg @ref LL_ADC_CHANNEL_12
01778   *         @arg @ref LL_ADC_CHANNEL_13
01779   *         @arg @ref LL_ADC_CHANNEL_14
01780   *         @arg @ref LL_ADC_CHANNEL_15
01781   *         @arg @ref LL_ADC_CHANNEL_16
01782   *         @arg @ref LL_ADC_CHANNEL_17
01783   *         @arg @ref LL_ADC_CHANNEL_18
01784   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01785   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01786   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01787   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
01788   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
01789   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
01790   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
01791   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
01792   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
01793   *
01794   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
01795   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
01796   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
01797   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
01798   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
01799   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
01800   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01801   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
01802   *         (1, 2, 3, 4) For ADC channel read back from ADC register,
01803   *                      comparison with internal channel parameter to be done
01804   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01805   * @param  __GROUP__ This parameter can be one of the following values:
01806   *         @arg @ref LL_ADC_GROUP_REGULAR
01807   *         @arg @ref LL_ADC_GROUP_INJECTED
01808   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
01809   * @retval Returned value can be one of the following values:
01810   *         @arg @ref LL_ADC_AWD_DISABLE
01811   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
01812   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
01813   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
01814   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
01815   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
01816   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
01817   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
01818   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
01819   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
01820   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
01821   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
01822   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
01823   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
01824   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
01825   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
01826   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
01827   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
01828   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
01829   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
01830   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
01831   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
01832   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
01833   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
01834   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
01835   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
01836   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
01837   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
01838   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
01839   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
01840   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
01841   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
01842   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
01843   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
01844   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
01845   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
01846   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
01847   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
01848   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
01849   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
01850   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
01851   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
01852   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
01853   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
01854   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
01855   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
01856   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
01857   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
01858   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
01859   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
01860   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
01861   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
01862   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
01863   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
01864   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
01865   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
01866   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
01867   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
01868   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
01869   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
01870   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
01871   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)
01872   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)
01873   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)
01874   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(4)
01875   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(4)
01876   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (4)
01877   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(4)
01878   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(4)
01879   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (4)
01880   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG          (0)(2)(5)
01881   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ          (0)(2)(5)
01882   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ         (2)(5)
01883   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG          (0)(2)(5)
01884   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ          (0)(2)(5)
01885   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ         (2)(5)
01886   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)(6)
01887   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)(6)
01888   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)(6)
01889   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)(6)
01890   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)(6)
01891   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)(6)
01892   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     (0)(3)(6)
01893   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     (0)(3)(6)
01894   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ    (3)(6)
01895   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     (0)(3)(6)
01896   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     (0)(3)(6)
01897   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ    (3)(6)
01898   *
01899   *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
01900   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
01901   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
01902   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
01903   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
01904   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
01905   *         (6) On STM32L4, parameter available on devices with several ADC instances.
01906   */
01907 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
01908   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
01909     ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                        \
01910       :                                                                                                   \
01911       ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
01912        ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                    \
01913          :                                                                                                \
01914          (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  \
01915   )
01916
01917 /**
01918   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
01919   *         or low in function of ADC resolution, when ADC resolution is
01920   *         different of 12 bits.
01921   * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
01922   *         or @ref LL_ADC_SetAnalogWDThresholds().
01923   *         Example, with a ADC resolution of 8 bits, to set the value of
01924   *         analog watchdog threshold high (on 8 bits):
01925   *           LL_ADC_SetAnalogWDThresholds
01926   *            (< ADCx param >,
01927   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
01928   *            );
01929   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01930   *         @arg @ref LL_ADC_RESOLUTION_12B
01931   *         @arg @ref LL_ADC_RESOLUTION_10B
01932   *         @arg @ref LL_ADC_RESOLUTION_8B
01933   *         @arg @ref LL_ADC_RESOLUTION_6B
01934   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
01935   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01936   */
01937 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
01938   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
01939
01940 /**
01941   * @brief  Helper macro to get the value of ADC analog watchdog threshold high
01942   *         or low in function of ADC resolution, when ADC resolution is
01943   *         different of 12 bits.
01944   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
01945   *         Example, with a ADC resolution of 8 bits, to get the value of
01946   *         analog watchdog threshold high (on 8 bits):
01947   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
01948   *            (LL_ADC_RESOLUTION_8B,
01949   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
01950   *            );
01951   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01952   *         @arg @ref LL_ADC_RESOLUTION_12B
01953   *         @arg @ref LL_ADC_RESOLUTION_10B
01954   *         @arg @ref LL_ADC_RESOLUTION_8B
01955   *         @arg @ref LL_ADC_RESOLUTION_6B
01956   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
01957   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01958   */
01959 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
01960   ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
01961
01962 /**
01963   * @brief  Helper macro to get the ADC analog watchdog threshold high
01964   *         or low from raw value containing both thresholds concatenated.
01965   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
01966   *         Example, to get analog watchdog threshold high from the register raw value:
01967   *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
01968   * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
01969   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
01970   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
01971   * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01972   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01973   */
01974 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \
01975   (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
01976
01977 /**
01978   * @brief  Helper macro to set the ADC calibration value with both single ended
01979   *         and differential modes calibration factors concatenated.
01980   * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
01981   *         Example, to set calibration factors single ended to 0x55
01982   *         and differential ended to 0x2A:
01983   *           LL_ADC_SetCalibrationFactor(
01984   *             ADC1,
01985   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
01986   * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
01987   * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
01988   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01989   */
01990 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \
01991   (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))
01992
01993 #if defined(ADC_MULTIMODE_SUPPORT)
01994 /**
01995   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
01996   *         or ADC slave from raw value with both ADC conversion data concatenated.
01997   * @note   This macro is intended to be used when multimode transfer by DMA
01998   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
01999   *         In this case the transferred data need to processed with this macro
02000   *         to separate the conversion data of ADC master and ADC slave.
02001   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
02002   *         @arg @ref LL_ADC_MULTI_MASTER
02003   *         @arg @ref LL_ADC_MULTI_SLAVE
02004   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
02005   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
02006   */
02007 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
02008   (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
02009 #endif
02010
02011 /**
02012   * @brief  Helper macro to select the ADC common instance
02013   *         to which is belonging the selected ADC instance.
02014   * @note   ADC common register instance can be used for:
02015   *         - Set parameters common to several ADC instances
02016   *         - Multimode (for devices with several ADC instances)
02017   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
02018   * @param  __ADCx__ ADC instance
02019   * @retval ADC common register instance
02020   */
02021 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
02022 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
02023   (ADC123_COMMON)
02024 #elif defined(ADC1) && defined(ADC2)
02025 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
02026   (ADC12_COMMON)
02027 #else
02028 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
02029   (ADC1_COMMON)
02030 #endif
02031
02032 /**
02033   * @brief  Helper macro to check if all ADC instances sharing the same
02034   *         ADC common instance are disabled.
02035   * @note   This check is required by functions with setting conditioned to
02036   *         ADC state:
02037   *         All ADC instances of the ADC common group must be disabled.
02038   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
02039   * @note   On devices with only 1 ADC common instance, parameter of this macro
02040   *         is useless and can be ignored (parameter kept for compatibility
02041   *         with devices featuring several ADC common instances).
02042   * @param  __ADCXY_COMMON__ ADC common instance
02043   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02044   * @retval Value "0" if all ADC instances sharing the same ADC common instance
02045   *         are disabled.
02046   *         Value "1" if at least one ADC instance sharing the same ADC common instance
02047   *         is enabled.
02048   */
02049 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
02050 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
02051   (LL_ADC_IsEnabled(ADC1) |                                                    \
02052    LL_ADC_IsEnabled(ADC2) |                                                    \
02053    LL_ADC_IsEnabled(ADC3)  )
02054 #elif defined(ADC1) && defined(ADC2)
02055 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
02056   (LL_ADC_IsEnabled(ADC1) |                                                    \
02057    LL_ADC_IsEnabled(ADC2)  )
02058 #else
02059 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
02060   (LL_ADC_IsEnabled(ADC1))
02061 #endif
02062
02063 /**
02064   * @brief  Helper macro to define the ADC conversion data full-scale digital
02065   *         value corresponding to the selected ADC resolution.
02066   * @note   ADC conversion data full-scale corresponds to voltage range
02067   *         determined by analog voltage references Vref+ and Vref-
02068   *         (refer to reference manual).
02069   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02070   *         @arg @ref LL_ADC_RESOLUTION_12B
02071   *         @arg @ref LL_ADC_RESOLUTION_10B
02072   *         @arg @ref LL_ADC_RESOLUTION_8B
02073   *         @arg @ref LL_ADC_RESOLUTION_6B
02074   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
02075   */
02076 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
02077   (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
02078
02079 /**
02080   * @brief  Helper macro to convert the ADC conversion data from
02081   *         a resolution to another resolution.
02082   * @param  __DATA__ ADC conversion data to be converted
02083   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
02084   *         This parameter can be one of the following values:
02085   *         @arg @ref LL_ADC_RESOLUTION_12B
02086   *         @arg @ref LL_ADC_RESOLUTION_10B
02087   *         @arg @ref LL_ADC_RESOLUTION_8B
02088   *         @arg @ref LL_ADC_RESOLUTION_6B
02089   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
02090   *         This parameter can be one of the following values:
02091   *         @arg @ref LL_ADC_RESOLUTION_12B
02092   *         @arg @ref LL_ADC_RESOLUTION_10B
02093   *         @arg @ref LL_ADC_RESOLUTION_8B
02094   *         @arg @ref LL_ADC_RESOLUTION_6B
02095   * @retval ADC conversion data to the requested resolution
02096   */
02097 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
02098                                          __ADC_RESOLUTION_CURRENT__,\
02099                                          __ADC_RESOLUTION_TARGET__)            \
02100   (((__DATA__)                                                                 \
02101     << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))    \
02102    >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))       \
02103   )
02104
02105 /**
02106   * @brief  Helper macro to calculate the voltage (unit: mVolt)
02107   *         corresponding to a ADC conversion data (unit: digital value).
02108   * @note   Analog reference voltage (Vref+) must be either known from
02109   *         user board environment or can be calculated using ADC measurement
02110   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02111   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
02112   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
02113   *                       (unit: digital value).
02114   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02115   *         @arg @ref LL_ADC_RESOLUTION_12B
02116   *         @arg @ref LL_ADC_RESOLUTION_10B
02117   *         @arg @ref LL_ADC_RESOLUTION_8B
02118   *         @arg @ref LL_ADC_RESOLUTION_6B
02119   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
02120   */
02121 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
02122                                       __ADC_DATA__,\
02123                                       __ADC_RESOLUTION__)                      \
02124   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
02125    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
02126   )
02127
02128 /* Legacy define */
02129 #define __LL_ADC_CALC_DATA_VOLTAGE()  __LL_ADC_CALC_DATA_TO_VOLTAGE()
02130
02131 /**
02132   * @brief  Helper macro to calculate analog reference voltage (Vref+)
02133   *         (unit: mVolt) from ADC conversion data of internal voltage
02134   *         reference VrefInt.
02135   * @note   Computation is using VrefInt calibration value
02136   *         stored in system memory for each device during production.
02137   * @note   This voltage depends on user board environment: voltage level
02138   *         connected to pin Vref+.
02139   *         On devices with small package, the pin Vref+ is not present
02140   *         and internally bonded to pin Vdda.
02141   * @note   On this STM32 serie, calibration data of internal voltage reference
02142   *         VrefInt corresponds to a resolution of 12 bits,
02143   *         this is the recommended ADC resolution to convert voltage of
02144   *         internal voltage reference VrefInt.
02145   *         Otherwise, this macro performs the processing to scale
02146   *         ADC conversion data to 12 bits.
02147   * @param  __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
02148   *         of internal voltage reference VrefInt (unit: digital value).
02149   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
02150   *         @arg @ref LL_ADC_RESOLUTION_12B
02151   *         @arg @ref LL_ADC_RESOLUTION_10B
02152   *         @arg @ref LL_ADC_RESOLUTION_8B
02153   *         @arg @ref LL_ADC_RESOLUTION_6B
02154   * @retval Analog reference voltage (unit: mV)
02155   */
02156 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
02157                                          __ADC_RESOLUTION__)                   \
02158   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
02159     / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \
02160                                        (__ADC_RESOLUTION__),                   \
02161                                        LL_ADC_RESOLUTION_12B)                  \
02162   )
02163
02164 /**
02165   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
02166   *         from ADC conversion data of internal temperature sensor.
02167   * @note   Computation is using temperature sensor calibration values
02168   *         stored in system memory for each device during production.
02169   * @note   Calculation formula:
02170   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
02171   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
02172   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
02173   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
02174   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
02175   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
02176   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
02177   *                            TEMP_DEGC_CAL1 (calibrated in factory)
02178   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
02179   *                            TEMP_DEGC_CAL2 (calibrated in factory)
02180   *         Caution: Calculation relevancy under reserve that calibration
02181   *                  parameters are correct (address and data).
02182   *                  To calculate temperature using temperature sensor
02183   *                  datasheet typical values (generic values less, therefore
02184   *                  less accurate than calibrated values),
02185   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
02186   * @note   As calculation input, the analog reference voltage (Vref+) must be
02187   *         defined as it impacts the ADC LSB equivalent voltage.
02188   * @note   Analog reference voltage (Vref+) must be either known from
02189   *         user board environment or can be calculated using ADC measurement
02190   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02191   * @note   On this STM32 serie, calibration data of temperature sensor
02192   *         corresponds to a resolution of 12 bits,
02193   *         this is the recommended ADC resolution to convert voltage of
02194   *         temperature sensor.
02195   *         Otherwise, this macro performs the processing to scale
02196   *         ADC conversion data to 12 bits.
02197   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
02198   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
02199   *                                 temperature sensor (unit: digital value).
02200   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
02201   *                                 sensor voltage has been measured.
02202   *         This parameter can be one of the following values:
02203   *         @arg @ref LL_ADC_RESOLUTION_12B
02204   *         @arg @ref LL_ADC_RESOLUTION_10B
02205   *         @arg @ref LL_ADC_RESOLUTION_8B
02206   *         @arg @ref LL_ADC_RESOLUTION_6B
02207   * @retval Temperature (unit: degree Celsius)
02208   */
02209 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
02210                                   __TEMPSENSOR_ADC_DATA__,\
02211                                   __ADC_RESOLUTION__)                              \
02212   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
02213                                                     (__ADC_RESOLUTION__),          \
02214                                                     LL_ADC_RESOLUTION_12B)         \
02215                    * (__VREFANALOG_VOLTAGE__))                                     \
02216                   / TEMPSENSOR_CAL_VREFANALOG)                                     \
02217         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
02218      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
02219     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
02220    ) + TEMPSENSOR_CAL1_TEMP                                                        \
02221   )
02222
02223 /**
02224   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
02225   *         from ADC conversion data of internal temperature sensor.
02226   * @note   Computation is using temperature sensor typical values
02227   *         (refer to device datasheet).
02228   * @note   Calculation formula:
02229   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
02230   *                         / Avg_Slope + CALx_TEMP
02231   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
02232   *                                   (unit: digital value)
02233   *                Avg_Slope        = temperature sensor slope
02234   *                                   (unit: uV/Degree Celsius)
02235   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
02236   *                                   temperature CALx_TEMP (unit: mV)
02237   *         Caution: Calculation relevancy under reserve the temperature sensor
02238   *                  of the current device has characteristics in line with
02239   *                  datasheet typical values.
02240   *                  If temperature sensor calibration values are available on
02241   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
02242   *                  temperature calculation will be more accurate using
02243   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
02244   * @note   As calculation input, the analog reference voltage (Vref+) must be
02245   *         defined as it impacts the ADC LSB equivalent voltage.
02246   * @note   Analog reference voltage (Vref+) must be either known from
02247   *         user board environment or can be calculated using ADC measurement
02248   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
02249   * @note   ADC measurement data must correspond to a resolution of 12bits
02250   *         (full scale digital value 4095). If not the case, the data must be
02251   *         preliminarily rescaled to an equivalent resolution of 12 bits.
02252   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
02253   *                                       On STM32L4, refer to device datasheet parameter "Avg_Slope".
02254   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
02255   *                                       On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
02256   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
02257   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
02258   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
02259   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
02260   *         This parameter can be one of the following values:
02261   *         @arg @ref LL_ADC_RESOLUTION_12B
02262   *         @arg @ref LL_ADC_RESOLUTION_10B
02263   *         @arg @ref LL_ADC_RESOLUTION_8B
02264   *         @arg @ref LL_ADC_RESOLUTION_6B
02265   * @retval Temperature (unit: degree Celsius)
02266   */
02267 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
02268                                              __TEMPSENSOR_TYP_CALX_V__,\
02269                                              __TEMPSENSOR_CALX_TEMP__,\
02270                                              __VREFANALOG_VOLTAGE__,\
02271                                              __TEMPSENSOR_ADC_DATA__,\
02272                                              __ADC_RESOLUTION__)               \
02273   ((( (                                                                        \
02274        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
02275                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
02276                  * 1000)                                                       \
02277        -                                                                       \
02278        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
02279                  * 1000)                                                       \
02280       )                                                                        \
02281     ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
02282    ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
02283   )
02284
02285 /**
02286   * @}
02287   */
02288
02289 /**
02290   * @}
02291   */
02292
02293
02294 /* Exported functions --------------------------------------------------------*/
02295 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
02296   * @{
02297   */
02298
02299 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
02300   * @{
02301   */
02302 /* Note: LL ADC functions to set DMA transfer are located into sections of    */
02303 /*       configuration of ADC instance, groups and multimode (if available):  */
02304 /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
02305
02306 /**
02307   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
02308   *         ADC register address from ADC instance and a list of ADC registers
02309   *         intended to be used (most commonly) with DMA transfer.
02310   * @note   These ADC registers are data registers:
02311   *         when ADC conversion data is available in ADC data registers,
02312   *         ADC generates a DMA transfer request.
02313   * @note   This macro is intended to be used with LL DMA driver, refer to
02314   *         function "LL_DMA_ConfigAddresses()".
02315   *         Example:
02316   *           LL_DMA_ConfigAddresses(DMA1,
02317   *                                  LL_DMA_CHANNEL_1,
02318   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
02319   *                                  (uint32_t)&< array or variable >,
02320   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
02321   * @note   For devices with several ADC: in multimode, some devices
02322   *         use a different data register outside of ADC instance scope
02323   *         (common data register). This macro manages this register difference,
02324   *         only ADC instance has to be set as parameter.
02325   * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
02326   *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
02327   *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
02328   * @param  ADCx ADC instance
02329   * @param  Register This parameter can be one of the following values:
02330   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
02331   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
02332   *
02333   *         (1) Available on devices with several ADC instances.
02334   * @retval ADC register address
02335   */
02336 #if defined(ADC_MULTIMODE_SUPPORT)
02337 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
02338 {
02339   register uint32_t data_reg_addr = 0U;
02340
02341   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
02342   {
02343     /* Retrieve address of register DR */
02344     data_reg_addr = (uint32_t)&(ADCx->DR);
02345   }
02346   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
02347   {
02348     /* Retrieve address of register CDR */
02349     data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
02350   }
02351
02352   return data_reg_addr;
02353 }
02354 #else
02355 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
02356 {
02357   /* Retrieve address of register DR */
02358   return (uint32_t)&(ADCx->DR);
02359 }
02360 #endif
02361
02362 /**
02363   * @}
02364   */
02365
02366 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
02367   * @{
02368   */
02369
02370 /**
02371   * @brief  Set parameter common to several ADC: Clock source and prescaler.
02372   * @note   On this STM32 serie, if ADC group injected is used, some
02373   *         clock ratio constraints between ADC clock and AHB clock
02374   *         must be respected.
02375   *         Refer to reference manual.
02376   * @note   On this STM32 serie, setting of this feature is conditioned to
02377   *         ADC state:
02378   *         All ADC instances of the ADC common group must be disabled.
02379   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
02380   *         ADC instance or by using helper macro helper macro
02381   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
02382   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
02383   *         CCR      PRESC          LL_ADC_SetCommonClock
02384   * @param  ADCxy_COMMON ADC common instance
02385   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02386   * @param  CommonClock This parameter can be one of the following values:
02387   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
02388   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
02389   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
02390   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
02391   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
02392   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
02393   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
02394   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
02395   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
02396   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
02397   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
02398   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
02399   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
02400   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
02401   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
02402   * @retval None
02403   */
02404 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
02405 {
02406   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
02407 }
02408
02409 /**
02410   * @brief  Get parameter common to several ADC: Clock source and prescaler.
02411   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
02412   *         CCR      PRESC          LL_ADC_GetCommonClock
02413   * @param  ADCxy_COMMON ADC common instance
02414   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02415   * @retval Returned value can be one of the following values:
02416   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
02417   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
02418   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
02419   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
02420   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
02421   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
02422   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
02423   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
02424   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
02425   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
02426   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
02427   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
02428   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
02429   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
02430   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
02431   */
02432 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
02433 {
02434   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
02435 }
02436
02437 /**
02438   * @brief  Set parameter common to several ADC: measurement path to internal
02439   *         channels (VrefInt, temperature sensor, ...).
02440   * @note   One or several values can be selected.
02441   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
02442   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
02443   * @note   Stabilization time of measurement path to internal channel:
02444   *         After enabling internal paths, before starting ADC conversion,
02445   *         a delay is required for internal voltage reference and
02446   *         temperature sensor stabilization time.
02447   *         Refer to device datasheet.
02448   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
02449   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
02450   * @note   ADC internal channel sampling time constraint:
02451   *         For ADC conversion of internal channels,
02452   *         a sampling time minimum value is required.
02453   *         Refer to device datasheet.
02454   * @note   On this STM32 serie, setting of this feature is conditioned to
02455   *         ADC state:
02456   *         All ADC instances of the ADC common group must be disabled.
02457   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
02458   *         ADC instance or by using helper macro helper macro
02459   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
02460   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
02461   *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n
02462   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh
02463   * @param  ADCxy_COMMON ADC common instance
02464   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02465   * @param  PathInternal This parameter can be a combination of the following values:
02466   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
02467   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
02468   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
02469   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
02470   * @retval None
02471   */
02472 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
02473 {
02474   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
02475 }
02476
02477 /**
02478   * @brief  Get parameter common to several ADC: measurement path to internal
02479   *         channels (VrefInt, temperature sensor, ...).
02480   * @note   One or several values can be selected.
02481   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
02482   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
02483   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
02484   *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n
02485   *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh
02486   * @param  ADCxy_COMMON ADC common instance
02487   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02488   * @retval Returned value can be a combination of the following values:
02489   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
02490   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
02491   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
02492   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
02493   */
02494 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
02495 {
02496   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
02497 }
02498
02499 /**
02500   * @}
02501   */
02502
02503 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
02504   * @{
02505   */
02506
02507 /**
02508   * @brief  Set ADC calibration factor in the mode single-ended
02509   *         or differential (for devices with differential mode available).
02510   * @note   This function is intended to set calibration parameters
02511   *         without having to perform a new calibration using
02512   *         @ref LL_ADC_StartCalibration().
02513   * @note   For devices with differential mode available:
02514   *         Calibration of offset is specific to each of
02515   *         single-ended and differential modes
02516   *         (calibration factor must be specified for each of these
02517   *         differential modes, if used afterwards and if the application
02518   *         requires their calibration).
02519   * @note   In case of setting calibration factors of both modes single ended
02520   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
02521   *         both calibration factors must be concatenated.
02522   *         To perform this processing, use helper macro
02523   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
02524   * @note   On this STM32 serie, setting of this feature is conditioned to
02525   *         ADC state:
02526   *         ADC must be enabled, without calibration on going, without conversion
02527   *         on going on group regular.
02528   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
02529   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
02530   * @param  ADCx ADC instance
02531   * @param  SingleDiff This parameter can be one of the following values:
02532   *         @arg @ref LL_ADC_SINGLE_ENDED
02533   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
02534   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
02535   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
02536   * @retval None
02537   */
02538 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
02539 {
02540   MODIFY_REG(ADCx->CALFACT,
02541              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
02542              CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
02543 }
02544
02545 /**
02546   * @brief  Get ADC calibration factor in the mode single-ended
02547   *         or differential (for devices with differential mode available).
02548   * @note   Calibration factors are set by hardware after performing
02549   *         a calibration run using function @ref LL_ADC_StartCalibration().
02550   * @note   For devices with differential mode available:
02551   *         Calibration of offset is specific to each of
02552   *         single-ended and differential modes
02553   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
02554   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
02555   * @param  ADCx ADC instance
02556   * @param  SingleDiff This parameter can be one of the following values:
02557   *         @arg @ref LL_ADC_SINGLE_ENDED
02558   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
02559   * @retval Value between Min_Data=0x00 and Max_Data=0x7F
02560   */
02561 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
02562 {
02563   /* Retrieve bits with position in register depending on parameter           */
02564   /* "SingleDiff".                                                            */
02565   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
02566   /* containing other bits reserved for other purpose.                        */
02567   return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
02568 }
02569
02570 /**
02571   * @brief  Set ADC resolution.
02572   *         Refer to reference manual for alignments formats
02573   *         dependencies to ADC resolutions.
02574   * @note   On this STM32 serie, setting of this feature is conditioned to
02575   *         ADC state:
02576   *         ADC must be disabled or enabled without conversion on going
02577   *         on either groups regular or injected.
02578   * @rmtoll CFGR     RES            LL_ADC_SetResolution
02579   * @param  ADCx ADC instance
02580   * @param  Resolution This parameter can be one of the following values:
02581   *         @arg @ref LL_ADC_RESOLUTION_12B
02582   *         @arg @ref LL_ADC_RESOLUTION_10B
02583   *         @arg @ref LL_ADC_RESOLUTION_8B
02584   *         @arg @ref LL_ADC_RESOLUTION_6B
02585   * @retval None
02586   */
02587 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
02588 {
02589   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
02590 }
02591
02592 /**
02593   * @brief  Get ADC resolution.
02594   *         Refer to reference manual for alignments formats
02595   *         dependencies to ADC resolutions.
02596   * @rmtoll CFGR     RES            LL_ADC_GetResolution
02597   * @param  ADCx ADC instance
02598   * @retval Returned value can be one of the following values:
02599   *         @arg @ref LL_ADC_RESOLUTION_12B
02600   *         @arg @ref LL_ADC_RESOLUTION_10B
02601   *         @arg @ref LL_ADC_RESOLUTION_8B
02602   *         @arg @ref LL_ADC_RESOLUTION_6B
02603   */
02604 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
02605 {
02606   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
02607 }
02608
02609 /**
02610   * @brief  Set ADC conversion data alignment.
02611   * @note   Refer to reference manual for alignments formats
02612   *         dependencies to ADC resolutions.
02613   * @note   On this STM32 serie, setting of this feature is conditioned to
02614   *         ADC state:
02615   *         ADC must be disabled or enabled without conversion on going
02616   *         on either groups regular or injected.
02617   * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment
02618   * @param  ADCx ADC instance
02619   * @param  DataAlignment This parameter can be one of the following values:
02620   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
02621   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
02622   * @retval None
02623   */
02624 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
02625 {
02626   MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
02627 }
02628
02629 /**
02630   * @brief  Get ADC conversion data alignment.
02631   * @note   Refer to reference manual for alignments formats
02632   *         dependencies to ADC resolutions.
02633   * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment
02634   * @param  ADCx ADC instance
02635   * @retval Returned value can be one of the following values:
02636   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
02637   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
02638   */
02639 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
02640 {
02641   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
02642 }
02643
02644 /**
02645   * @brief  Set ADC low power mode.
02646   * @note   Description of ADC low power modes:
02647   *         - ADC low power mode "auto wait": Dynamic low power mode,
02648   *           ADC conversions occurrences are limited to the minimum necessary
02649   *           in order to reduce power consumption.
02650   *           New ADC conversion starts only when the previous
02651   *           unitary conversion data (for ADC group regular)
02652   *           or previous sequence conversions data (for ADC group injected)
02653   *           has been retrieved by user software.
02654   *           In the meantime, ADC remains idle: does not performs any
02655   *           other conversion.
02656   *           This mode allows to automatically adapt the ADC conversions
02657   *           triggers to the speed of the software that reads the data.
02658   *           Moreover, this avoids risk of overrun for low frequency
02659   *           applications.
02660   *           How to use this low power mode:
02661   *           - Do not use with interruption or DMA since these modes
02662   *             have to clear immediately the EOC flag to free the
02663   *             IRQ vector sequencer.
02664   *           - Do use with polling: 1. Start conversion,
02665   *             2. Later on, when conversion data is needed: poll for end of
02666   *             conversion  to ensure that conversion is completed and
02667   *             retrieve ADC conversion data. This will trig another
02668   *             ADC conversion start.
02669   *         - ADC low power mode "auto power-off" (feature available on
02670   *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
02671   *           the ADC automatically powers-off after a conversion and
02672   *           automatically wakes up when a new conversion is triggered
02673   *           (with startup time between trigger and start of sampling).
02674   *           This feature can be combined with low power mode "auto wait".
02675   * @note   With ADC low power mode "auto wait", the ADC conversion data read
02676   *         is corresponding to previous ADC conversion start, independently
02677   *         of delay during which ADC was idle.
02678   *         Therefore, the ADC conversion data may be outdated: does not
02679   *         correspond to the current voltage level on the selected
02680   *         ADC channel.
02681   * @note   On this STM32 serie, setting of this feature is conditioned to
02682   *         ADC state:
02683   *         ADC must be disabled or enabled without conversion on going
02684   *         on either groups regular or injected.
02685   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
02686   * @param  ADCx ADC instance
02687   * @param  LowPowerMode This parameter can be one of the following values:
02688   *         @arg @ref LL_ADC_LP_MODE_NONE
02689   *         @arg @ref LL_ADC_LP_AUTOWAIT
02690   * @retval None
02691   */
02692 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
02693 {
02694   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
02695 }
02696
02697 /**
02698   * @brief  Get ADC low power mode:
02699   * @note   Description of ADC low power modes:
02700   *         - ADC low power mode "auto wait": Dynamic low power mode,
02701   *           ADC conversions occurrences are limited to the minimum necessary
02702   *           in order to reduce power consumption.
02703   *           New ADC conversion starts only when the previous
02704   *           unitary conversion data (for ADC group regular)
02705   *           or previous sequence conversions data (for ADC group injected)
02706   *           has been retrieved by user software.
02707   *           In the meantime, ADC remains idle: does not performs any
02708   *           other conversion.
02709   *           This mode allows to automatically adapt the ADC conversions
02710   *           triggers to the speed of the software that reads the data.
02711   *           Moreover, this avoids risk of overrun for low frequency
02712   *           applications.
02713   *           How to use this low power mode:
02714   *           - Do not use with interruption or DMA since these modes
02715   *             have to clear immediately the EOC flag to free the
02716   *             IRQ vector sequencer.
02717   *           - Do use with polling: 1. Start conversion,
02718   *             2. Later on, when conversion data is needed: poll for end of
02719   *             conversion  to ensure that conversion is completed and
02720   *             retrieve ADC conversion data. This will trig another
02721   *             ADC conversion start.
02722   *         - ADC low power mode "auto power-off" (feature available on
02723   *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
02724   *           the ADC automatically powers-off after a conversion and
02725   *           automatically wakes up when a new conversion is triggered
02726   *           (with startup time between trigger and start of sampling).
02727   *           This feature can be combined with low power mode "auto wait".
02728   * @note   With ADC low power mode "auto wait", the ADC conversion data read
02729   *         is corresponding to previous ADC conversion start, independently
02730   *         of delay during which ADC was idle.
02731   *         Therefore, the ADC conversion data may be outdated: does not
02732   *         correspond to the current voltage level on the selected
02733   *         ADC channel.
02734   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
02735   * @param  ADCx ADC instance
02736   * @retval Returned value can be one of the following values:
02737   *         @arg @ref LL_ADC_LP_MODE_NONE
02738   *         @arg @ref LL_ADC_LP_AUTOWAIT
02739   */
02740 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
02741 {
02742   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
02743 }
02744
02745 /**
02746   * @brief  Set ADC selected offset number 1, 2, 3 or 4.
02747   * @note   This function set the 2 items of offset configuration:
02748   *         - ADC channel to which the offset programmed will be applied
02749   *           (independently of channel mapped on ADC group regular
02750   *           or group injected)
02751   *         - Offset level (offset to be subtracted from the raw
02752   *           converted data).
02753   * @note   Caution: Offset format is dependent to ADC resolution:
02754   *         offset has to be left-aligned on bit 11, the LSB (right bits)
02755   *         are set to 0.
02756   * @note   This function enables the offset, by default. It can be forced
02757   *         to disable state using function LL_ADC_SetOffsetState().
02758   * @note   If a channel is mapped on several offsets numbers, only the offset
02759   *         with the lowest value is considered for the subtraction.
02760   * @note   On this STM32 serie, setting of this feature is conditioned to
02761   *         ADC state:
02762   *         ADC must be disabled or enabled without conversion on going
02763   *         on either groups regular or injected.
02764   * @note   On STM32L4, some fast channels are available: fast analog inputs
02765   *         coming from GPIO pads (ADC_IN1..5).
02766   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
02767   *         OFR1     OFFSET1        LL_ADC_SetOffset\n
02768   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
02769   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
02770   *         OFR2     OFFSET2        LL_ADC_SetOffset\n
02771   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
02772   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
02773   *         OFR3     OFFSET3        LL_ADC_SetOffset\n
02774   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
02775   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
02776   *         OFR4     OFFSET4        LL_ADC_SetOffset\n
02777   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
02778   * @param  ADCx ADC instance
02779   * @param  Offsety This parameter can be one of the following values:
02780   *         @arg @ref LL_ADC_OFFSET_1
02781   *         @arg @ref LL_ADC_OFFSET_2
02782   *         @arg @ref LL_ADC_OFFSET_3
02783   *         @arg @ref LL_ADC_OFFSET_4
02784   * @param  Channel This parameter can be one of the following values:
02785   *         @arg @ref LL_ADC_CHANNEL_0
02786   *         @arg @ref LL_ADC_CHANNEL_1            (7)
02787   *         @arg @ref LL_ADC_CHANNEL_2            (7)
02788   *         @arg @ref LL_ADC_CHANNEL_3            (7)
02789   *         @arg @ref LL_ADC_CHANNEL_4            (7)
02790   *         @arg @ref LL_ADC_CHANNEL_5            (7)
02791   *         @arg @ref LL_ADC_CHANNEL_6
02792   *         @arg @ref LL_ADC_CHANNEL_7
02793   *         @arg @ref LL_ADC_CHANNEL_8
02794   *         @arg @ref LL_ADC_CHANNEL_9
02795   *         @arg @ref LL_ADC_CHANNEL_10
02796   *         @arg @ref LL_ADC_CHANNEL_11
02797   *         @arg @ref LL_ADC_CHANNEL_12
02798   *         @arg @ref LL_ADC_CHANNEL_13
02799   *         @arg @ref LL_ADC_CHANNEL_14
02800   *         @arg @ref LL_ADC_CHANNEL_15
02801   *         @arg @ref LL_ADC_CHANNEL_16
02802   *         @arg @ref LL_ADC_CHANNEL_17
02803   *         @arg @ref LL_ADC_CHANNEL_18
02804   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02805   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
02806   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
02807   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
02808   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
02809   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
02810   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
02811   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
02812   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
02813   *
02814   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
02815   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
02816   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
02817   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
02818   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
02819   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
02820   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
02821   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
02822   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
02823   * @retval None
02824   */
02825 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
02826 {
02827   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02828
02829   MODIFY_REG(*preg,
02830              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
02831              ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
02832 }
02833
02834 /**
02835   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
02836   *         Channel to which the offset programmed will be applied
02837   *         (independently of channel mapped on ADC group regular
02838   *         or group injected)
02839   * @note   Usage of the returned channel number:
02840   *         - To reinject this channel into another function LL_ADC_xxx:
02841   *           the returned channel number is only partly formatted on definition
02842   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
02843   *           with parts of literals LL_ADC_CHANNEL_x or using
02844   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02845   *           Then the selected literal LL_ADC_CHANNEL_x can be used
02846   *           as parameter for another function.
02847   *         - To get the channel number in decimal format:
02848   *           process the returned value with the helper macro
02849   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02850   * @note   On STM32L4, some fast channels are available: fast analog inputs
02851   *         coming from GPIO pads (ADC_IN1..5).
02852   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
02853   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
02854   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
02855   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
02856   * @param  ADCx ADC instance
02857   * @param  Offsety This parameter can be one of the following values:
02858   *         @arg @ref LL_ADC_OFFSET_1
02859   *         @arg @ref LL_ADC_OFFSET_2
02860   *         @arg @ref LL_ADC_OFFSET_3
02861   *         @arg @ref LL_ADC_OFFSET_4
02862   * @retval Returned value can be one of the following values:
02863   *         @arg @ref LL_ADC_CHANNEL_0
02864   *         @arg @ref LL_ADC_CHANNEL_1            (7)
02865   *         @arg @ref LL_ADC_CHANNEL_2            (7)
02866   *         @arg @ref LL_ADC_CHANNEL_3            (7)
02867   *         @arg @ref LL_ADC_CHANNEL_4            (7)
02868   *         @arg @ref LL_ADC_CHANNEL_5            (7)
02869   *         @arg @ref LL_ADC_CHANNEL_6
02870   *         @arg @ref LL_ADC_CHANNEL_7
02871   *         @arg @ref LL_ADC_CHANNEL_8
02872   *         @arg @ref LL_ADC_CHANNEL_9
02873   *         @arg @ref LL_ADC_CHANNEL_10
02874   *         @arg @ref LL_ADC_CHANNEL_11
02875   *         @arg @ref LL_ADC_CHANNEL_12
02876   *         @arg @ref LL_ADC_CHANNEL_13
02877   *         @arg @ref LL_ADC_CHANNEL_14
02878   *         @arg @ref LL_ADC_CHANNEL_15
02879   *         @arg @ref LL_ADC_CHANNEL_16
02880   *         @arg @ref LL_ADC_CHANNEL_17
02881   *         @arg @ref LL_ADC_CHANNEL_18
02882   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02883   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
02884   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
02885   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
02886   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
02887   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
02888   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
02889   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
02890   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
02891   *
02892   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
02893   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
02894   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
02895   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
02896   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
02897   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
02898   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
02899   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
02900   *         (1, 2, 3, 4) For ADC channel read back from ADC register,
02901   *                      comparison with internal channel parameter to be done
02902   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
02903   */
02904 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
02905 {
02906   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02907
02908   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
02909 }
02910
02911 /**
02912   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
02913   *         Offset level (offset to be subtracted from the raw
02914   *         converted data).
02915   * @note   Caution: Offset format is dependent to ADC resolution:
02916   *         offset has to be left-aligned on bit 11, the LSB (right bits)
02917   *         are set to 0.
02918   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
02919   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
02920   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
02921   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
02922   * @param  ADCx ADC instance
02923   * @param  Offsety This parameter can be one of the following values:
02924   *         @arg @ref LL_ADC_OFFSET_1
02925   *         @arg @ref LL_ADC_OFFSET_2
02926   *         @arg @ref LL_ADC_OFFSET_3
02927   *         @arg @ref LL_ADC_OFFSET_4
02928   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
02929   */
02930 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
02931 {
02932   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02933
02934   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
02935 }
02936
02937 /**
02938   * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
02939   *         force offset state disable or enable
02940   *         without modifying offset channel or offset value.
02941   * @note   This function should be needed only in case of offset to be
02942   *         enabled-disabled dynamically, and should not be needed in other cases:
02943   *         function LL_ADC_SetOffset() automatically enables the offset.
02944   * @note   On this STM32 serie, setting of this feature is conditioned to
02945   *         ADC state:
02946   *         ADC must be disabled or enabled without conversion on going
02947   *         on either groups regular or injected.
02948   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n
02949   *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n
02950   *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n
02951   *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState
02952   * @param  ADCx ADC instance
02953   * @param  Offsety This parameter can be one of the following values:
02954   *         @arg @ref LL_ADC_OFFSET_1
02955   *         @arg @ref LL_ADC_OFFSET_2
02956   *         @arg @ref LL_ADC_OFFSET_3
02957   *         @arg @ref LL_ADC_OFFSET_4
02958   * @param  OffsetState This parameter can be one of the following values:
02959   *         @arg @ref LL_ADC_OFFSET_DISABLE
02960   *         @arg @ref LL_ADC_OFFSET_ENABLE
02961   * @retval None
02962   */
02963 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
02964 {
02965   register uint32_t *preg = (uint32_t *)((uint32_t)
02966                             ((uint32_t)(&ADCx->OFR1) + (Offsety*4U)));
02967
02968   MODIFY_REG(*preg,
02969              ADC_OFR1_OFFSET1_EN,
02970              OffsetState);
02971 }
02972
02973 /**
02974   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
02975   *         offset state disabled or enabled.
02976   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n
02977   *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n
02978   *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n
02979   *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState
02980   * @param  ADCx ADC instance
02981   * @param  Offsety This parameter can be one of the following values:
02982   *         @arg @ref LL_ADC_OFFSET_1
02983   *         @arg @ref LL_ADC_OFFSET_2
02984   *         @arg @ref LL_ADC_OFFSET_3
02985   *         @arg @ref LL_ADC_OFFSET_4
02986   * @retval Returned value can be one of the following values:
02987   *         @arg @ref LL_ADC_OFFSET_DISABLE
02988   *         @arg @ref LL_ADC_OFFSET_ENABLE
02989   */
02990 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
02991 {
02992   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02993
02994   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
02995 }
02996
02997 /**
02998   * @}
02999   */
03000
03001 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
03002   * @{
03003   */
03004
03005 /**
03006   * @brief  Set ADC group regular conversion trigger source:
03007   *         internal (SW start) or from external IP (timer event,
03008   *         external interrupt line).
03009   * @note   On this STM32 serie, setting trigger source to external trigger
03010   *         also set trigger polarity to rising edge
03011   *         (default setting for compatibility with some ADC on other
03012   *         STM32 families having this setting set by HW default value).
03013   *         In case of need to modify trigger edge, use
03014   *         function @ref LL_ADC_REG_SetTriggerEdge().
03015   * @note   Availability of parameters of trigger sources from timer
03016   *         depends on timers availability on the selected device.
03017   * @note   On this STM32 serie, setting of this feature is conditioned to
03018   *         ADC state:
03019   *         ADC must be disabled or enabled without conversion on going
03020   *         on group regular.
03021   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n
03022   *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource
03023   * @param  ADCx ADC instance
03024   * @param  TriggerSource This parameter can be one of the following values:
03025   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
03026   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
03027   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
03028   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
03029   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
03030   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
03031   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
03032   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
03033   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
03034   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
03035   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
03036   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
03037   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
03038   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
03039   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
03040   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
03041   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
03042   * @retval None
03043   */
03044 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
03045 {
03046   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
03047 }
03048
03049 /**
03050   * @brief  Get ADC group regular conversion trigger source:
03051   *         internal (SW start) or from external IP (timer event,
03052   *         external interrupt line).
03053   * @note   To determine whether group regular trigger source is
03054   *         internal (SW start) or external, without detail
03055   *         of which peripheral is selected as external trigger,
03056   *         (equivalent to
03057   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
03058   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
03059   * @note   Availability of parameters of trigger sources from timer
03060   *         depends on timers availability on the selected device.
03061   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n
03062   *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource
03063   * @param  ADCx ADC instance
03064   * @retval Returned value can be one of the following values:
03065   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
03066   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
03067   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
03068   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
03069   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
03070   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
03071   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
03072   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
03073   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
03074   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
03075   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
03076   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
03077   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
03078   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
03079   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
03080   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
03081   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
03082   */
03083 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
03084 {
03085   register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
03086
03087   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
03088   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
03089   register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
03090
03091   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
03092   /* to match with triggers literals definition.                              */
03093   return ((TriggerSource
03094            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
03095           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
03096          );
03097 }
03098
03099 /**
03100   * @brief  Get ADC group regular conversion trigger source internal (SW start)
03101             or external.
03102   * @note   In case of group regular trigger source set to external trigger,
03103   *         to determine which peripheral is selected as external trigger,
03104   *         use function @ref LL_ADC_REG_GetTriggerSource().
03105   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
03106   * @param  ADCx ADC instance
03107   * @retval Value "0" if trigger source external trigger
03108   *         Value "1" if trigger source SW start.
03109   */
03110 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
03111 {
03112   return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN));
03113 }
03114
03115 /**
03116   * @brief  Set ADC group regular conversion trigger polarity.
03117   * @note   Applicable only for trigger source set to external trigger.
03118   * @note   On this STM32 serie, setting of this feature is conditioned to
03119   *         ADC state:
03120   *         ADC must be disabled or enabled without conversion on going
03121   *         on group regular.
03122   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge
03123   * @param  ADCx ADC instance
03124   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03125   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
03126   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
03127   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
03128   * @retval None
03129   */
03130 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
03131 {
03132   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
03133 }
03134
03135 /**
03136   * @brief  Get ADC group regular conversion trigger polarity.
03137   * @note   Applicable only for trigger source set to external trigger.
03138   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge
03139   * @param  ADCx ADC instance
03140   * @retval Returned value can be one of the following values:
03141   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
03142   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
03143   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
03144   */
03145 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
03146 {
03147   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
03148 }
03149
03150
03151 /**
03152   * @brief  Set ADC group regular sequencer length and scan direction.
03153   * @note   Description of ADC group regular sequencer features:
03154   *         - For devices with sequencer fully configurable
03155   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
03156   *           sequencer length and each rank affectation to a channel
03157   *           are configurable.
03158   *           This function performs configuration of:
03159   *           - Sequence length: Number of ranks in the scan sequence.
03160   *           - Sequence direction: Unless specified in parameters, sequencer
03161   *             scan direction is forward (from rank 1 to rank n).
03162   *           Sequencer ranks are selected using
03163   *           function "LL_ADC_REG_SetSequencerRanks()".
03164   *         - For devices with sequencer not fully configurable
03165   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
03166   *           sequencer length and each rank affectation to a channel
03167   *           are defined by channel number.
03168   *           This function performs configuration of:
03169   *           - Sequence length: Number of ranks in the scan sequence is
03170   *             defined by number of channels set in the sequence,
03171   *             rank of each channel is fixed by channel HW number.
03172   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
03173   *           - Sequence direction: Unless specified in parameters, sequencer
03174   *             scan direction is forward (from lowest channel number to
03175   *             highest channel number).
03176   *           Sequencer ranks are selected using
03177   *           function "LL_ADC_REG_SetSequencerChannels()".
03178   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03179   *         ADC conversion on only 1 channel.
03180   * @note   On this STM32 serie, setting of this feature is conditioned to
03181   *         ADC state:
03182   *         ADC must be disabled or enabled without conversion on going
03183   *         on group regular.
03184   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
03185   * @param  ADCx ADC instance
03186   * @param  SequencerNbRanks This parameter can be one of the following values:
03187   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
03188   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
03189   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
03190   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
03191   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
03192   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
03193   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
03194   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
03195   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
03196   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
03197   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
03198   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
03199   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
03200   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
03201   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
03202   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
03203   * @retval None
03204   */
03205 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
03206 {
03207   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
03208 }
03209
03210 /**
03211   * @brief  Get ADC group regular sequencer length and scan direction.
03212   * @note   Description of ADC group regular sequencer features:
03213   *         - For devices with sequencer fully configurable
03214   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
03215   *           sequencer length and each rank affectation to a channel
03216   *           are configurable.
03217   *           This function retrieves:
03218   *           - Sequence length: Number of ranks in the scan sequence.
03219   *           - Sequence direction: Unless specified in parameters, sequencer
03220   *             scan direction is forward (from rank 1 to rank n).
03221   *           Sequencer ranks are selected using
03222   *           function "LL_ADC_REG_SetSequencerRanks()".
03223   *         - For devices with sequencer not fully configurable
03224   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
03225   *           sequencer length and each rank affectation to a channel
03226   *           are defined by channel number.
03227   *           This function retrieves:
03228   *           - Sequence length: Number of ranks in the scan sequence is
03229   *             defined by number of channels set in the sequence,
03230   *             rank of each channel is fixed by channel HW number.
03231   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
03232   *           - Sequence direction: Unless specified in parameters, sequencer
03233   *             scan direction is forward (from lowest channel number to
03234   *             highest channel number).
03235   *           Sequencer ranks are selected using
03236   *           function "LL_ADC_REG_SetSequencerChannels()".
03237   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03238   *         ADC conversion on only 1 channel.
03239   * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
03240   * @param  ADCx ADC instance
03241   * @retval Returned value can be one of the following values:
03242   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
03243   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
03244   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
03245   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
03246   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
03247   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
03248   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
03249   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
03250   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
03251   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
03252   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
03253   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
03254   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
03255   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
03256   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
03257   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
03258   */
03259 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
03260 {
03261   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
03262 }
03263
03264 /**
03265   * @brief  Set ADC group regular sequencer discontinuous mode:
03266   *         sequence subdivided and scan conversions interrupted every selected
03267   *         number of ranks.
03268   * @note   It is not possible to enable both ADC group regular
03269   *         continuous mode and sequencer discontinuous mode.
03270   * @note   It is not possible to enable both ADC auto-injected mode
03271   *         and ADC group regular sequencer discontinuous mode.
03272   * @note   On this STM32 serie, setting of this feature is conditioned to
03273   *         ADC state:
03274   *         ADC must be disabled or enabled without conversion on going
03275   *         on group regular.
03276   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
03277   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
03278   * @param  ADCx ADC instance
03279   * @param  SeqDiscont This parameter can be one of the following values:
03280   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
03281   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
03282   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
03283   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
03284   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
03285   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
03286   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
03287   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
03288   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
03289   * @retval None
03290   */
03291 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
03292 {
03293   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
03294 }
03295
03296 /**
03297   * @brief  Get ADC group regular sequencer discontinuous mode:
03298   *         sequence subdivided and scan conversions interrupted every selected
03299   *         number of ranks.
03300   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
03301   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
03302   * @param  ADCx ADC instance
03303   * @retval Returned value can be one of the following values:
03304   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
03305   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
03306   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
03307   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
03308   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
03309   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
03310   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
03311   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
03312   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
03313   */
03314 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
03315 {
03316   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
03317 }
03318
03319 /**
03320   * @brief  Set ADC group regular sequence: channel on the selected
03321   *         scan sequence rank.
03322   * @note   This function performs configuration of:
03323   *         - Channels ordering into each rank of scan sequence:
03324   *           whatever channel can be placed into whatever rank.
03325   * @note   On this STM32 serie, ADC group regular sequencer is
03326   *         fully configurable: sequencer length and each rank
03327   *         affectation to a channel are configurable.
03328   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
03329   * @note   Depending on devices and packages, some channels may not be available.
03330   *         Refer to device datasheet for channels availability.
03331   * @note   On this STM32 serie, to measure internal channels (VrefInt,
03332   *         TempSensor, ...), measurement paths to internal channels must be
03333   *         enabled separately.
03334   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03335   * @note   On this STM32 serie, setting of this feature is conditioned to
03336   *         ADC state:
03337   *         ADC must be disabled or enabled without conversion on going
03338   *         on group regular.
03339   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
03340   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
03341   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
03342   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
03343   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
03344   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
03345   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
03346   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
03347   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
03348   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
03349   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
03350   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
03351   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
03352   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
03353   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
03354   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
03355   * @param  ADCx ADC instance
03356   * @param  Rank This parameter can be one of the following values:
03357   *         @arg @ref LL_ADC_REG_RANK_1
03358   *         @arg @ref LL_ADC_REG_RANK_2
03359   *         @arg @ref LL_ADC_REG_RANK_3
03360   *         @arg @ref LL_ADC_REG_RANK_4
03361   *         @arg @ref LL_ADC_REG_RANK_5
03362   *         @arg @ref LL_ADC_REG_RANK_6
03363   *         @arg @ref LL_ADC_REG_RANK_7
03364   *         @arg @ref LL_ADC_REG_RANK_8
03365   *         @arg @ref LL_ADC_REG_RANK_9
03366   *         @arg @ref LL_ADC_REG_RANK_10
03367   *         @arg @ref LL_ADC_REG_RANK_11
03368   *         @arg @ref LL_ADC_REG_RANK_12
03369   *         @arg @ref LL_ADC_REG_RANK_13
03370   *         @arg @ref LL_ADC_REG_RANK_14
03371   *         @arg @ref LL_ADC_REG_RANK_15
03372   *         @arg @ref LL_ADC_REG_RANK_16
03373   * @param  Channel This parameter can be one of the following values:
03374   *         @arg @ref LL_ADC_CHANNEL_0
03375   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03376   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03377   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03378   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03379   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03380   *         @arg @ref LL_ADC_CHANNEL_6
03381   *         @arg @ref LL_ADC_CHANNEL_7
03382   *         @arg @ref LL_ADC_CHANNEL_8
03383   *         @arg @ref LL_ADC_CHANNEL_9
03384   *         @arg @ref LL_ADC_CHANNEL_10
03385   *         @arg @ref LL_ADC_CHANNEL_11
03386   *         @arg @ref LL_ADC_CHANNEL_12
03387   *         @arg @ref LL_ADC_CHANNEL_13
03388   *         @arg @ref LL_ADC_CHANNEL_14
03389   *         @arg @ref LL_ADC_CHANNEL_15
03390   *         @arg @ref LL_ADC_CHANNEL_16
03391   *         @arg @ref LL_ADC_CHANNEL_17
03392   *         @arg @ref LL_ADC_CHANNEL_18
03393   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03394   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03395   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03396   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
03397   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
03398   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
03399   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
03400   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
03401   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
03402   *
03403   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
03404   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
03405   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
03406   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
03407   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
03408   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
03409   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03410   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03411   * @retval None
03412   */
03413 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
03414 {
03415   /* Set bits with content of parameter "Channel" with bits position          */
03416   /* in register and register position depending on parameter "Rank".         */
03417   /* Parameters "Rank" and "Channel" are used with masks because containing   */
03418   /* other bits reserved for other purpose.                                   */
03419   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
03420
03421   MODIFY_REG(*preg,
03422              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
03423              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
03424 }
03425
03426 /**
03427   * @brief  Get ADC group regular sequence: channel on the selected
03428   *         scan sequence rank.
03429   * @note   On this STM32 serie, ADC group regular sequencer is
03430   *         fully configurable: sequencer length and each rank
03431   *         affectation to a channel are configurable.
03432   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
03433   * @note   Depending on devices and packages, some channels may not be available.
03434   *         Refer to device datasheet for channels availability.
03435   * @note   Usage of the returned channel number:
03436   *         - To reinject this channel into another function LL_ADC_xxx:
03437   *           the returned channel number is only partly formatted on definition
03438   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
03439   *           with parts of literals LL_ADC_CHANNEL_x or using
03440   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03441   *           Then the selected literal LL_ADC_CHANNEL_x can be used
03442   *           as parameter for another function.
03443   *         - To get the channel number in decimal format:
03444   *           process the returned value with the helper macro
03445   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03446   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
03447   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
03448   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
03449   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
03450   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
03451   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
03452   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
03453   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
03454   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
03455   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
03456   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
03457   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
03458   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
03459   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
03460   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
03461   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
03462   * @param  ADCx ADC instance
03463   * @param  Rank This parameter can be one of the following values:
03464   *         @arg @ref LL_ADC_REG_RANK_1
03465   *         @arg @ref LL_ADC_REG_RANK_2
03466   *         @arg @ref LL_ADC_REG_RANK_3
03467   *         @arg @ref LL_ADC_REG_RANK_4
03468   *         @arg @ref LL_ADC_REG_RANK_5
03469   *         @arg @ref LL_ADC_REG_RANK_6
03470   *         @arg @ref LL_ADC_REG_RANK_7
03471   *         @arg @ref LL_ADC_REG_RANK_8
03472   *         @arg @ref LL_ADC_REG_RANK_9
03473   *         @arg @ref LL_ADC_REG_RANK_10
03474   *         @arg @ref LL_ADC_REG_RANK_11
03475   *         @arg @ref LL_ADC_REG_RANK_12
03476   *         @arg @ref LL_ADC_REG_RANK_13
03477   *         @arg @ref LL_ADC_REG_RANK_14
03478   *         @arg @ref LL_ADC_REG_RANK_15
03479   *         @arg @ref LL_ADC_REG_RANK_16
03480   * @retval Returned value can be one of the following values:
03481   *         @arg @ref LL_ADC_CHANNEL_0
03482   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03483   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03484   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03485   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03486   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03487   *         @arg @ref LL_ADC_CHANNEL_6
03488   *         @arg @ref LL_ADC_CHANNEL_7
03489   *         @arg @ref LL_ADC_CHANNEL_8
03490   *         @arg @ref LL_ADC_CHANNEL_9
03491   *         @arg @ref LL_ADC_CHANNEL_10
03492   *         @arg @ref LL_ADC_CHANNEL_11
03493   *         @arg @ref LL_ADC_CHANNEL_12
03494   *         @arg @ref LL_ADC_CHANNEL_13
03495   *         @arg @ref LL_ADC_CHANNEL_14
03496   *         @arg @ref LL_ADC_CHANNEL_15
03497   *         @arg @ref LL_ADC_CHANNEL_16
03498   *         @arg @ref LL_ADC_CHANNEL_17
03499   *         @arg @ref LL_ADC_CHANNEL_18
03500   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03501   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03502   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03503   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
03504   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
03505   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
03506   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
03507   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
03508   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
03509   *
03510   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
03511   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
03512   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
03513   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
03514   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
03515   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
03516   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03517   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
03518   *         (1, 2, 3, 4) For ADC channel read back from ADC register,
03519   *                      comparison with internal channel parameter to be done
03520   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
03521   */
03522 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
03523 {
03524   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
03525
03526   return (uint32_t) (READ_BIT(*preg,
03527                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
03528                      << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))
03529                     );
03530 }
03531
03532 /**
03533   * @brief  Set ADC continuous conversion mode on ADC group regular.
03534   * @note   Description of ADC continuous conversion mode:
03535   *         - single mode: one conversion per trigger
03536   *         - continuous mode: after the first trigger, following
03537   *           conversions launched successively automatically.
03538   * @note   It is not possible to enable both ADC group regular
03539   *         continuous mode and sequencer discontinuous mode.
03540   * @note   On this STM32 serie, setting of this feature is conditioned to
03541   *         ADC state:
03542   *         ADC must be disabled or enabled without conversion on going
03543   *         on group regular.
03544   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
03545   * @param  ADCx ADC instance
03546   * @param  Continuous This parameter can be one of the following values:
03547   *         @arg @ref LL_ADC_REG_CONV_SINGLE
03548   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
03549   * @retval None
03550   */
03551 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
03552 {
03553   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
03554 }
03555
03556 /**
03557   * @brief  Get ADC continuous conversion mode on ADC group regular.
03558   * @note   Description of ADC continuous conversion mode:
03559   *         - single mode: one conversion per trigger
03560   *         - continuous mode: after the first trigger, following
03561   *           conversions launched successively automatically.
03562   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
03563   * @param  ADCx ADC instance
03564   * @retval Returned value can be one of the following values:
03565   *         @arg @ref LL_ADC_REG_CONV_SINGLE
03566   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
03567   */
03568 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
03569 {
03570   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
03571 }
03572
03573 /**
03574   * @brief  Set ADC group regular conversion data transfer: no transfer or
03575   *         transfer by DMA, and DMA requests mode.
03576   * @note   If transfer by DMA selected, specifies the DMA requests
03577   *         mode:
03578   *         - Limited mode (One shot mode): DMA transfer requests are stopped
03579   *           when number of DMA data transfers (number of
03580   *           ADC conversions) is reached.
03581   *           This ADC mode is intended to be used with DMA mode non-circular.
03582   *         - Unlimited mode: DMA transfer requests are unlimited,
03583   *           whatever number of DMA data transfers (number of
03584   *           ADC conversions).
03585   *           This ADC mode is intended to be used with DMA mode circular.
03586   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
03587   *         mode non-circular:
03588   *         when DMA transfers size will be reached, DMA will stop transfers of
03589   *         ADC conversions data ADC will raise an overrun error
03590   *        (overrun flag and interruption if enabled).
03591   * @note   For devices with several ADC instances: ADC multimode DMA
03592   *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().
03593   * @note   To configure DMA source address (peripheral address),
03594   *         use function @ref LL_ADC_DMA_GetRegAddr().
03595   * @note   On this STM32 serie, setting of this feature is conditioned to
03596   *         ADC state:
03597   *         ADC must be disabled or enabled without conversion on going
03598   *         on either groups regular or injected.
03599   * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n
03600   *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer
03601   * @param  ADCx ADC instance
03602   * @param  DMATransfer This parameter can be one of the following values:
03603   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
03604   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
03605   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
03606   * @retval None
03607   */
03608 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
03609 {
03610   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
03611 }
03612
03613 /**
03614   * @brief  Get ADC group regular conversion data transfer: no transfer or
03615   *         transfer by DMA, and DMA requests mode.
03616   * @note   If transfer by DMA selected, specifies the DMA requests
03617   *         mode:
03618   *         - Limited mode (One shot mode): DMA transfer requests are stopped
03619   *           when number of DMA data transfers (number of
03620   *           ADC conversions) is reached.
03621   *           This ADC mode is intended to be used with DMA mode non-circular.
03622   *         - Unlimited mode: DMA transfer requests are unlimited,
03623   *           whatever number of DMA data transfers (number of
03624   *           ADC conversions).
03625   *           This ADC mode is intended to be used with DMA mode circular.
03626   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
03627   *         mode non-circular:
03628   *         when DMA transfers size will be reached, DMA will stop transfers of
03629   *         ADC conversions data ADC will raise an overrun error
03630   *         (overrun flag and interruption if enabled).
03631   * @note   For devices with several ADC instances: ADC multimode DMA
03632   *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().
03633   * @note   To configure DMA source address (peripheral address),
03634   *         use function @ref LL_ADC_DMA_GetRegAddr().
03635   * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n
03636   *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer
03637   * @param  ADCx ADC instance
03638   * @retval Returned value can be one of the following values:
03639   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
03640   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
03641   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
03642   */
03643 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
03644 {
03645   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
03646 }
03647
03648
03649 /**
03650   * @brief  Set ADC group regular behavior in case of overrun:
03651   *         data preserved or overwritten.
03652   * @note   Compatibility with devices without feature overrun:
03653   *         other devices without this feature have a behavior
03654   *         equivalent to data overwritten.
03655   *         The default setting of overrun is data preserved.
03656   *         Therefore, for compatibility with all devices, parameter
03657   *         overrun should be set to data overwritten.
03658   * @note   On this STM32 serie, setting of this feature is conditioned to
03659   *         ADC state:
03660   *         ADC must be disabled or enabled without conversion on going
03661   *         on group regular.
03662   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
03663   * @param  ADCx ADC instance
03664   * @param  Overrun This parameter can be one of the following values:
03665   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
03666   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
03667   * @retval None
03668   */
03669 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
03670 {
03671   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
03672 }
03673
03674 /**
03675   * @brief  Get ADC group regular behavior in case of overrun:
03676   *         data preserved or overwritten.
03677   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
03678   * @param  ADCx ADC instance
03679   * @retval Returned value can be one of the following values:
03680   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
03681   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
03682   */
03683 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
03684 {
03685   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
03686 }
03687
03688 /**
03689   * @}
03690   */
03691
03692 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
03693   * @{
03694   */
03695
03696 /**
03697   * @brief  Set ADC group injected conversion trigger source:
03698   *         internal (SW start) or from external IP (timer event,
03699   *         external interrupt line).
03700   * @note   On this STM32 serie, setting trigger source to external trigger
03701   *         also set trigger polarity to rising edge
03702   *         (default setting for compatibility with some ADC on other
03703   *         STM32 families having this setting set by HW default value).
03704   *         In case of need to modify trigger edge, use
03705   *         function @ref LL_ADC_INJ_SetTriggerEdge().
03706   * @note   Availability of parameters of trigger sources from timer
03707   *         depends on timers availability on the selected device.
03708   * @note   On this STM32 serie, setting of this feature is conditioned to
03709   *         ADC state:
03710   *         ADC must not be disabled. Can be enabled with or without conversion
03711   *         on going on either groups regular or injected.
03712   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
03713   *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
03714   * @param  ADCx ADC instance
03715   * @param  TriggerSource This parameter can be one of the following values:
03716   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
03717   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03718   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03719   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
03720   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
03721   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
03722   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
03723   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
03724   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
03725   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
03726   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
03727   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
03728   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
03729   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
03730   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
03731   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
03732   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
03733   * @retval None
03734   */
03735 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
03736 {
03737   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
03738 }
03739
03740 /**
03741   * @brief  Get ADC group injected conversion trigger source:
03742   *         internal (SW start) or from external IP (timer event,
03743   *         external interrupt line).
03744   * @note   To determine whether group injected trigger source is
03745   *         internal (SW start) or external, without detail
03746   *         of which peripheral is selected as external trigger,
03747   *         (equivalent to
03748   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
03749   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
03750   * @note   Availability of parameters of trigger sources from timer
03751   *         depends on timers availability on the selected device.
03752   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
03753   *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
03754   * @param  ADCx ADC instance
03755   * @retval Returned value can be one of the following values:
03756   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
03757   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03758   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03759   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
03760   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
03761   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
03762   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
03763   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
03764   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
03765   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
03766   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
03767   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
03768   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
03769   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
03770   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
03771   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
03772   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
03773   */
03774 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
03775 {
03776   register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
03777
03778   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
03779   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
03780   register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
03781
03782   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
03783   /* to match with triggers literals definition.                              */
03784   return ((TriggerSource
03785            & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
03786           | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
03787          );
03788 }
03789
03790 /**
03791   * @brief  Get ADC group injected conversion trigger source internal (SW start)
03792             or external
03793   * @note   In case of group injected trigger source set to external trigger,
03794   *         to determine which peripheral is selected as external trigger,
03795   *         use function @ref LL_ADC_INJ_GetTriggerSource.
03796   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
03797   * @param  ADCx ADC instance
03798   * @retval Value "0" if trigger source external trigger
03799   *         Value "1" if trigger source SW start.
03800   */
03801 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
03802 {
03803   return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN));
03804 }
03805
03806 /**
03807   * @brief  Set ADC group injected conversion trigger polarity.
03808   *         Applicable only for trigger source set to external trigger.
03809   * @note   On this STM32 serie, setting of this feature is conditioned to
03810   *         ADC state:
03811   *         ADC must not be disabled. Can be enabled with or without conversion
03812   *         on going on either groups regular or injected.
03813   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
03814   * @param  ADCx ADC instance
03815   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03816   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03817   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
03818   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
03819   * @retval None
03820   */
03821 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
03822 {
03823   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
03824 }
03825
03826 /**
03827   * @brief  Get ADC group injected conversion trigger polarity.
03828   *         Applicable only for trigger source set to external trigger.
03829   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
03830   * @param  ADCx ADC instance
03831   * @retval Returned value can be one of the following values:
03832   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03833   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
03834   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
03835   */
03836 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
03837 {
03838   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
03839 }
03840
03841 /**
03842   * @brief  Set ADC group injected sequencer length and scan direction.
03843   * @note   This function performs configuration of:
03844   *         - Sequence length: Number of ranks in the scan sequence.
03845   *         - Sequence direction: Unless specified in parameters, sequencer
03846   *           scan direction is forward (from rank 1 to rank n).
03847   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03848   *         ADC conversion on only 1 channel.
03849   * @note   On this STM32 serie, setting of this feature is conditioned to
03850   *         ADC state:
03851   *         ADC must not be disabled. Can be enabled with or without conversion
03852   *         on going on either groups regular or injected.
03853   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
03854   * @param  ADCx ADC instance
03855   * @param  SequencerNbRanks This parameter can be one of the following values:
03856   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
03857   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
03858   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
03859   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
03860   * @retval None
03861   */
03862 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
03863 {
03864   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
03865 }
03866
03867 /**
03868   * @brief  Get ADC group injected sequencer length and scan direction.
03869   * @note   This function retrieves:
03870   *         - Sequence length: Number of ranks in the scan sequence.
03871   *         - Sequence direction: Unless specified in parameters, sequencer
03872   *           scan direction is forward (from rank 1 to rank n).
03873   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03874   *         ADC conversion on only 1 channel.
03875   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
03876   * @param  ADCx ADC instance
03877   * @retval Returned value can be one of the following values:
03878   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
03879   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
03880   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
03881   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
03882   */
03883 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
03884 {
03885   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
03886 }
03887
03888 /**
03889   * @brief  Set ADC group injected sequencer discontinuous mode:
03890   *         sequence subdivided and scan conversions interrupted every selected
03891   *         number of ranks.
03892   * @note   It is not possible to enable both ADC group injected
03893   *         auto-injected mode and sequencer discontinuous mode.
03894   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
03895   * @param  ADCx ADC instance
03896   * @param  SeqDiscont This parameter can be one of the following values:
03897   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
03898   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
03899   * @retval None
03900   */
03901 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
03902 {
03903   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
03904 }
03905
03906 /**
03907   * @brief  Get ADC group injected sequencer discontinuous mode:
03908   *         sequence subdivided and scan conversions interrupted every selected
03909   *         number of ranks.
03910   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
03911   * @param  ADCx ADC instance
03912   * @retval Returned value can be one of the following values:
03913   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
03914   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
03915   */
03916 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
03917 {
03918   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
03919 }
03920
03921 /**
03922   * @brief  Set ADC group injected sequence: channel on the selected
03923   *         sequence rank.
03924   * @note   Depending on devices and packages, some channels may not be available.
03925   *         Refer to device datasheet for channels availability.
03926   * @note   On this STM32 serie, to measure internal channels (VrefInt,
03927   *         TempSensor, ...), measurement paths to internal channels must be
03928   *         enabled separately.
03929   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03930   * @note   On this STM32 serie, some fast channels are available: fast analog inputs
03931   *         coming from GPIO pads (ADC_IN1..5).
03932   * @note   On this STM32 serie, setting of this feature is conditioned to
03933   *         ADC state:
03934   *         ADC must not be disabled. Can be enabled with or without conversion
03935   *         on going on either groups regular or injected.
03936   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
03937   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
03938   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
03939   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
03940   * @param  ADCx ADC instance
03941   * @param  Rank This parameter can be one of the following values:
03942   *         @arg @ref LL_ADC_INJ_RANK_1
03943   *         @arg @ref LL_ADC_INJ_RANK_2
03944   *         @arg @ref LL_ADC_INJ_RANK_3
03945   *         @arg @ref LL_ADC_INJ_RANK_4
03946   * @param  Channel This parameter can be one of the following values:
03947   *         @arg @ref LL_ADC_CHANNEL_0
03948   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03949   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03950   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03951   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03952   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03953   *         @arg @ref LL_ADC_CHANNEL_6
03954   *         @arg @ref LL_ADC_CHANNEL_7
03955   *         @arg @ref LL_ADC_CHANNEL_8
03956   *         @arg @ref LL_ADC_CHANNEL_9
03957   *         @arg @ref LL_ADC_CHANNEL_10
03958   *         @arg @ref LL_ADC_CHANNEL_11
03959   *         @arg @ref LL_ADC_CHANNEL_12
03960   *         @arg @ref LL_ADC_CHANNEL_13
03961   *         @arg @ref LL_ADC_CHANNEL_14
03962   *         @arg @ref LL_ADC_CHANNEL_15
03963   *         @arg @ref LL_ADC_CHANNEL_16
03964   *         @arg @ref LL_ADC_CHANNEL_17
03965   *         @arg @ref LL_ADC_CHANNEL_18
03966   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03967   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03968   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03969   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
03970   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
03971   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
03972   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
03973   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
03974   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
03975   *
03976   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
03977   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
03978   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
03979   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
03980   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
03981   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
03982   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03983   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03984   * @retval None
03985   */
03986 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
03987 {
03988   /* Set bits with content of parameter "Channel" with bits position          */
03989   /* in register depending on parameter "Rank".                               */
03990   /* Parameters "Rank" and "Channel" are used with masks because containing   */
03991   /* other bits reserved for other purpose.                                   */
03992   MODIFY_REG(ADCx->JSQR,
03993              ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)),
03994              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)));
03995 }
03996
03997 /**
03998   * @brief  Get ADC group injected sequence: channel on the selected
03999   *         sequence rank.
04000   * @note   Depending on devices and packages, some channels may not be available.
04001   *         Refer to device datasheet for channels availability.
04002   * @note   Usage of the returned channel number:
04003   *         - To reinject this channel into another function LL_ADC_xxx:
04004   *           the returned channel number is only partly formatted on definition
04005   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
04006   *           with parts of literals LL_ADC_CHANNEL_x or using
04007   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04008   *           Then the selected literal LL_ADC_CHANNEL_x can be used
04009   *           as parameter for another function.
04010   *         - To get the channel number in decimal format:
04011   *           process the returned value with the helper macro
04012   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04013   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
04014   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
04015   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
04016   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
04017   * @param  ADCx ADC instance
04018   * @param  Rank This parameter can be one of the following values:
04019   *         @arg @ref LL_ADC_INJ_RANK_1
04020   *         @arg @ref LL_ADC_INJ_RANK_2
04021   *         @arg @ref LL_ADC_INJ_RANK_3
04022   *         @arg @ref LL_ADC_INJ_RANK_4
04023   * @retval Returned value can be one of the following values:
04024   *         @arg @ref LL_ADC_CHANNEL_0
04025   *         @arg @ref LL_ADC_CHANNEL_1            (7)
04026   *         @arg @ref LL_ADC_CHANNEL_2            (7)
04027   *         @arg @ref LL_ADC_CHANNEL_3            (7)
04028   *         @arg @ref LL_ADC_CHANNEL_4            (7)
04029   *         @arg @ref LL_ADC_CHANNEL_5            (7)
04030   *         @arg @ref LL_ADC_CHANNEL_6
04031   *         @arg @ref LL_ADC_CHANNEL_7
04032   *         @arg @ref LL_ADC_CHANNEL_8
04033   *         @arg @ref LL_ADC_CHANNEL_9
04034   *         @arg @ref LL_ADC_CHANNEL_10
04035   *         @arg @ref LL_ADC_CHANNEL_11
04036   *         @arg @ref LL_ADC_CHANNEL_12
04037   *         @arg @ref LL_ADC_CHANNEL_13
04038   *         @arg @ref LL_ADC_CHANNEL_14
04039   *         @arg @ref LL_ADC_CHANNEL_15
04040   *         @arg @ref LL_ADC_CHANNEL_16
04041   *         @arg @ref LL_ADC_CHANNEL_17
04042   *         @arg @ref LL_ADC_CHANNEL_18
04043   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04044   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
04045   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
04046   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
04047   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
04048   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
04049   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
04050   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
04051   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
04052   *
04053   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
04054   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
04055   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
04056   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
04057   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
04058   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
04059   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
04060   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
04061   *         (1, 2, 3, 4) For ADC channel read back from ADC register,
04062   *                      comparison with internal channel parameter to be done
04063   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
04064   */
04065 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
04066 {
04067   return (uint32_t)(READ_BIT(ADCx->JSQR,
04068                              ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)))
04069                     << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
04070                    );
04071 }
04072
04073 /**
04074   * @brief  Set ADC group injected conversion trigger:
04075   *         independent or from ADC group regular.
04076   * @note   This mode can be used to extend number of data registers
04077   *         updated after one ADC conversion trigger and with data
04078   *         permanently kept (not erased by successive conversions of scan of
04079   *         ADC sequencer ranks), up to 5 data registers:
04080   *         1 data register on ADC group regular, 4 data registers
04081   *         on ADC group injected.
04082   * @note   If ADC group injected injected trigger source is set to an
04083   *         external trigger, this feature must be must be set to
04084   *         independent trigger.
04085   *         ADC group injected automatic trigger is compliant only with
04086   *         group injected trigger source set to SW start, without any
04087   *         further action on  ADC group injected conversion start or stop:
04088   *         in this case, ADC group injected is controlled only
04089   *         from ADC group regular.
04090   * @note   It is not possible to enable both ADC group injected
04091   *         auto-injected mode and sequencer discontinuous mode.
04092   * @note   On this STM32 serie, setting of this feature is conditioned to
04093   *         ADC state:
04094   *         ADC must be disabled or enabled without conversion on going
04095   *         on either groups regular or injected.
04096   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
04097   * @param  ADCx ADC instance
04098   * @param  TrigAuto This parameter can be one of the following values:
04099   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
04100   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
04101   * @retval None
04102   */
04103 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
04104 {
04105   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
04106 }
04107
04108 /**
04109   * @brief  Get ADC group injected conversion trigger:
04110   *         independent or from ADC group regular.
04111   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
04112   * @param  ADCx ADC instance
04113   * @retval Returned value can be one of the following values:
04114   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
04115   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
04116   */
04117 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
04118 {
04119   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
04120 }
04121
04122 /**
04123   * @brief  Set ADC group injected contexts queue mode.
04124   * @note   A context is a setting of group injected sequencer:
04125   *         - group injected trigger
04126   *         - sequencer length
04127   *         - sequencer ranks
04128   *         If contexts queue is disabled:
04129   *         - only 1 sequence can be configured
04130   *           and is active perpetually.
04131   *         If contexts queue is enabled:
04132   *         - up to 2 contexts can be queued
04133   *           and are checked in and out as a FIFO stack (first-in, first-out).
04134   *         - If a new context is set when queues is full, error is triggered
04135   *           by interruption "Injected Queue Overflow".
04136   *         - Two behaviors are possible when all contexts have been processed:
04137   *           the contexts queue can maintain the last context active perpetually
04138   *           or can be empty and injected group triggers are disabled.
04139   *         - Triggers can be only external (not internal SW start)
04140   *         - Caution: The sequence must be fully configured in one time
04141   *           (one write of register JSQR makes a check-in of a new context
04142   *           into the queue).
04143   *           Therefore functions to set separately injected trigger and
04144   *           sequencer channels cannot be used, register JSQR must be set
04145   *           using function @ref LL_ADC_INJ_ConfigQueueContext().
04146   * @note   This parameter can be modified only when no conversion is on going
04147   *         on either groups regular or injected.
04148   * @note   A modification of the context mode (bit JQDIS) causes the contexts
04149   *         queue to be flushed and the register JSQR is cleared.
04150   * @note   On this STM32 serie, setting of this feature is conditioned to
04151   *         ADC state:
04152   *         ADC must be disabled or enabled without conversion on going
04153   *         on either groups regular or injected.
04154   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n
04155   *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode
04156   * @param  ADCx ADC instance
04157   * @param  QueueMode This parameter can be one of the following values:
04158   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
04159   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
04160   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
04161   * @retval None
04162   */
04163 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
04164 {
04165   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
04166 }
04167
04168 /**
04169   * @brief  Get ADC group injected context queue mode.
04170   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n
04171   *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode
04172   * @param  ADCx ADC instance
04173   * @retval Returned value can be one of the following values:
04174   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
04175   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
04176   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
04177   */
04178 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
04179 {
04180   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
04181 }
04182
04183 /**
04184   * @brief  Set one context on ADC group injected that will be checked in
04185   *         contexts queue.
04186   * @note   A context is a setting of group injected sequencer:
04187   *         - group injected trigger
04188   *         - sequencer length
04189   *         - sequencer ranks
04190   *         This function is intended to be used when contexts queue is enabled,
04191   *         because the sequence must be fully configured in one time
04192   *         (functions to set separately injected trigger and sequencer channels
04193   *         cannot be used):
04194   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
04195   * @note   In the contexts queue, only the active context can be read.
04196   *         The parameters of this function can be read using functions:
04197   *         @arg @ref LL_ADC_INJ_GetTriggerSource()
04198   *         @arg @ref LL_ADC_INJ_GetTriggerEdge()
04199   *         @arg @ref LL_ADC_INJ_GetSequencerRanks()
04200   * @note   On this STM32 serie, to measure internal channels (VrefInt,
04201   *         TempSensor, ...), measurement paths to internal channels must be
04202   *         enabled separately.
04203   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
04204   * @note   On this STM32 serie, some fast channels are available: fast analog inputs
04205   *         coming from GPIO pads (ADC_IN1..5).
04206   * @note   On this STM32 serie, setting of this feature is conditioned to
04207   *         ADC state:
04208   *         ADC must not be disabled. Can be enabled with or without conversion
04209   *         on going on either groups regular or injected.
04210   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
04211   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
04212   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
04213   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
04214   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
04215   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
04216   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
04217   * @param  ADCx ADC instance
04218   * @param  TriggerSource This parameter can be one of the following values:
04219   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
04220   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
04221   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
04222   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
04223   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
04224   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
04225   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
04226   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
04227   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
04228   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
04229   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
04230   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
04231   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
04232   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
04233   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
04234   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
04235   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
04236   * @param  ExternalTriggerEdge This parameter can be one of the following values:
04237   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
04238   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
04239   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
04240   *
04241   *         Note: This parameter is discarded in case of SW start:
04242   *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
04243   * @param  SequencerNbRanks This parameter can be one of the following values:
04244   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
04245   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
04246   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
04247   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
04248   * @param  Rank1_Channel This parameter can be one of the following values:
04249   *         @arg @ref LL_ADC_CHANNEL_0
04250   *         @arg @ref LL_ADC_CHANNEL_1            (7)
04251   *         @arg @ref LL_ADC_CHANNEL_2            (7)
04252   *         @arg @ref LL_ADC_CHANNEL_3            (7)
04253   *         @arg @ref LL_ADC_CHANNEL_4            (7)
04254   *         @arg @ref LL_ADC_CHANNEL_5            (7)
04255   *         @arg @ref LL_ADC_CHANNEL_6
04256   *         @arg @ref LL_ADC_CHANNEL_7
04257   *         @arg @ref LL_ADC_CHANNEL_8
04258   *         @arg @ref LL_ADC_CHANNEL_9
04259   *         @arg @ref LL_ADC_CHANNEL_10
04260   *         @arg @ref LL_ADC_CHANNEL_11
04261   *         @arg @ref LL_ADC_CHANNEL_12
04262   *         @arg @ref LL_ADC_CHANNEL_13
04263   *         @arg @ref LL_ADC_CHANNEL_14
04264   *         @arg @ref LL_ADC_CHANNEL_15
04265   *         @arg @ref LL_ADC_CHANNEL_16
04266   *         @arg @ref LL_ADC_CHANNEL_17
04267   *         @arg @ref LL_ADC_CHANNEL_18
04268   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04269   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
04270   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
04271   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
04272   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
04273   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
04274   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
04275   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
04276   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
04277   *
04278   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
04279   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
04280   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
04281   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
04282   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
04283   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
04284   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
04285   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
04286   * @param  Rank2_Channel This parameter can be one of the following values:
04287   *         @arg @ref LL_ADC_CHANNEL_0
04288   *         @arg @ref LL_ADC_CHANNEL_1            (7)
04289   *         @arg @ref LL_ADC_CHANNEL_2            (7)
04290   *         @arg @ref LL_ADC_CHANNEL_3            (7)
04291   *         @arg @ref LL_ADC_CHANNEL_4            (7)
04292   *         @arg @ref LL_ADC_CHANNEL_5            (7)
04293   *         @arg @ref LL_ADC_CHANNEL_6
04294   *         @arg @ref LL_ADC_CHANNEL_7
04295   *         @arg @ref LL_ADC_CHANNEL_8
04296   *         @arg @ref LL_ADC_CHANNEL_9
04297   *         @arg @ref LL_ADC_CHANNEL_10
04298   *         @arg @ref LL_ADC_CHANNEL_11
04299   *         @arg @ref LL_ADC_CHANNEL_12
04300   *         @arg @ref LL_ADC_CHANNEL_13
04301   *         @arg @ref LL_ADC_CHANNEL_14
04302   *         @arg @ref LL_ADC_CHANNEL_15
04303   *         @arg @ref LL_ADC_CHANNEL_16
04304   *         @arg @ref LL_ADC_CHANNEL_17
04305   *         @arg @ref LL_ADC_CHANNEL_18
04306   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04307   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
04308   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
04309   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
04310   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
04311   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
04312   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
04313   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
04314   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
04315   *
04316   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
04317   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
04318   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
04319   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
04320   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
04321   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
04322   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
04323   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
04324   * @param  Rank3_Channel This parameter can be one of the following values:
04325   *         @arg @ref LL_ADC_CHANNEL_0
04326   *         @arg @ref LL_ADC_CHANNEL_1            (7)
04327   *         @arg @ref LL_ADC_CHANNEL_2            (7)
04328   *         @arg @ref LL_ADC_CHANNEL_3            (7)
04329   *         @arg @ref LL_ADC_CHANNEL_4            (7)
04330   *         @arg @ref LL_ADC_CHANNEL_5            (7)
04331   *         @arg @ref LL_ADC_CHANNEL_6
04332   *         @arg @ref LL_ADC_CHANNEL_7
04333   *         @arg @ref LL_ADC_CHANNEL_8
04334   *         @arg @ref LL_ADC_CHANNEL_9
04335   *         @arg @ref LL_ADC_CHANNEL_10
04336   *         @arg @ref LL_ADC_CHANNEL_11
04337   *         @arg @ref LL_ADC_CHANNEL_12
04338   *         @arg @ref LL_ADC_CHANNEL_13
04339   *         @arg @ref LL_ADC_CHANNEL_14
04340   *         @arg @ref LL_ADC_CHANNEL_15
04341   *         @arg @ref LL_ADC_CHANNEL_16
04342   *         @arg @ref LL_ADC_CHANNEL_17
04343   *         @arg @ref LL_ADC_CHANNEL_18
04344   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04345   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
04346   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
04347   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
04348   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
04349   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
04350   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
04351   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
04352   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
04353   *
04354   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
04355   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
04356   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
04357   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
04358   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
04359   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
04360   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
04361   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
04362   * @param  Rank4_Channel This parameter can be one of the following values:
04363   *         @arg @ref LL_ADC_CHANNEL_0
04364   *         @arg @ref LL_ADC_CHANNEL_1            (7)
04365   *         @arg @ref LL_ADC_CHANNEL_2            (7)
04366   *         @arg @ref LL_ADC_CHANNEL_3            (7)
04367   *         @arg @ref LL_ADC_CHANNEL_4            (7)
04368   *         @arg @ref LL_ADC_CHANNEL_5            (7)
04369   *         @arg @ref LL_ADC_CHANNEL_6
04370   *         @arg @ref LL_ADC_CHANNEL_7
04371   *         @arg @ref LL_ADC_CHANNEL_8
04372   *         @arg @ref LL_ADC_CHANNEL_9
04373   *         @arg @ref LL_ADC_CHANNEL_10
04374   *         @arg @ref LL_ADC_CHANNEL_11
04375   *         @arg @ref LL_ADC_CHANNEL_12
04376   *         @arg @ref LL_ADC_CHANNEL_13
04377   *         @arg @ref LL_ADC_CHANNEL_14
04378   *         @arg @ref LL_ADC_CHANNEL_15
04379   *         @arg @ref LL_ADC_CHANNEL_16
04380   *         @arg @ref LL_ADC_CHANNEL_17
04381   *         @arg @ref LL_ADC_CHANNEL_18
04382   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04383   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
04384   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
04385   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
04386   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
04387   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
04388   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
04389   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
04390   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
04391   *
04392   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
04393   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
04394   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
04395   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
04396   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
04397   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
04398   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
04399   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
04400   * @retval None
04401   */
04402 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
04403                                                    uint32_t TriggerSource,
04404                                                    uint32_t ExternalTriggerEdge,
04405                                                    uint32_t SequencerNbRanks,
04406                                                    uint32_t Rank1_Channel,
04407                                                    uint32_t Rank2_Channel,
04408                                                    uint32_t Rank3_Channel,
04409                                                    uint32_t Rank4_Channel)
04410 {
04411   /* Set bits with content of parameter "Rankx_Channel" with bits position    */
04412   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
04413   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
04414   /* because containing other bits reserved for other purpose.                */
04415   /* If parameter "TriggerSource" is set to SW start, then parameter          */
04416   /* "ExternalTriggerEdge" is discarded.                                      */
04417   MODIFY_REG(ADCx->JSQR           ,
04418              ADC_JSQR_JEXTSEL |
04419              ADC_JSQR_JEXTEN  |
04420              ADC_JSQR_JSQ4    |
04421              ADC_JSQR_JSQ3    |
04422              ADC_JSQR_JSQ2    |
04423              ADC_JSQR_JSQ1    |
04424              ADC_JSQR_JL          ,
04425              TriggerSource       |
04426              (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) |
04427              ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) |
04428              ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) |
04429              ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) |
04430              ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) |
04431              SequencerNbRanks
04432             );
04433 }
04434
04435 /**
04436   * @}
04437   */
04438
04439 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
04440   * @{
04441   */
04442
04443 /**
04444   * @brief  Set sampling time of the selected ADC channel
04445   *         Unit: ADC clock cycles.
04446   * @note   On this device, sampling time is on channel scope: independently
04447   *         of channel mapped on ADC group regular or injected.
04448   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
04449   *         converted:
04450   *         sampling time constraints must be respected (sampling time can be
04451   *         adjusted in function of ADC clock frequency and sampling time
04452   *         setting).
04453   *         Refer to device datasheet for timings values (parameters TS_vrefint,
04454   *         TS_temp, ...).
04455   * @note   Conversion time is the addition of sampling time and processing time.
04456   *         On this STM32 serie, ADC processing time is:
04457   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
04458   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
04459   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
04460   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
04461   * @note   In case of ADC conversion of internal channel (VrefInt,
04462   *         temperature sensor, ...), a sampling time minimum value
04463   *         is required.
04464   *         Refer to device datasheet.
04465   * @note   On this STM32 serie, setting of this feature is conditioned to
04466   *         ADC state:
04467   *         ADC must be disabled or enabled without conversion on going
04468   *         on either groups regular or injected.
04469   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
04470   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
04471   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
04472   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
04473   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
04474   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
04475   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
04476   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
04477   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
04478   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
04479   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
04480   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
04481   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
04482   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
04483   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
04484   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
04485   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
04486   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
04487   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
04488   * @param  ADCx ADC instance
04489   * @param  Channel This parameter can be one of the following values:
04490   *         @arg @ref LL_ADC_CHANNEL_0
04491   *         @arg @ref LL_ADC_CHANNEL_1            (7)
04492   *         @arg @ref LL_ADC_CHANNEL_2            (7)
04493   *         @arg @ref LL_ADC_CHANNEL_3            (7)
04494   *         @arg @ref LL_ADC_CHANNEL_4            (7)
04495   *         @arg @ref LL_ADC_CHANNEL_5            (7)
04496   *         @arg @ref LL_ADC_CHANNEL_6
04497   *         @arg @ref LL_ADC_CHANNEL_7
04498   *         @arg @ref LL_ADC_CHANNEL_8
04499   *         @arg @ref LL_ADC_CHANNEL_9
04500   *         @arg @ref LL_ADC_CHANNEL_10
04501   *         @arg @ref LL_ADC_CHANNEL_11
04502   *         @arg @ref LL_ADC_CHANNEL_12
04503   *         @arg @ref LL_ADC_CHANNEL_13
04504   *         @arg @ref LL_ADC_CHANNEL_14
04505   *         @arg @ref LL_ADC_CHANNEL_15
04506   *         @arg @ref LL_ADC_CHANNEL_16
04507   *         @arg @ref LL_ADC_CHANNEL_17
04508   *         @arg @ref LL_ADC_CHANNEL_18
04509   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04510   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
04511   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
04512   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
04513   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
04514   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
04515   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
04516   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
04517   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
04518   *
04519   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
04520   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
04521   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
04522   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
04523   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
04524   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
04525   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
04526   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
04527   * @param  SamplingTime This parameter can be one of the following values:
04528   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
04529   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
04530   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
04531   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
04532   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
04533   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
04534   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
04535   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
04536   * @retval None
04537   */
04538 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
04539 {
04540   /* Set bits with content of parameter "SamplingTime" with bits position     */
04541   /* in register and register position depending on parameter "Channel".      */
04542   /* Parameter "Channel" is used with masks because containing                */
04543   /* other bits reserved for other purpose.                                   */
04544   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
04545
04546   MODIFY_REG(*preg,
04547              ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
04548              SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
04549 }
04550
04551 /**
04552   * @brief  Get sampling time of the selected ADC channel
04553   *         Unit: ADC clock cycles.
04554   * @note   On this device, sampling time is on channel scope: independently
04555   *         of channel mapped on ADC group regular or injected.
04556   * @note   Conversion time is the addition of sampling time and processing time.
04557   *         On this STM32 serie, ADC processing time is:
04558   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
04559   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
04560   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
04561   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
04562   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
04563   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
04564   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
04565   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
04566   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
04567   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
04568   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
04569   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
04570   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
04571   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
04572   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
04573   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
04574   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
04575   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
04576   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
04577   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
04578   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
04579   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
04580   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
04581   * @param  ADCx ADC instance
04582   * @param  Channel This parameter can be one of the following values:
04583   *         @arg @ref LL_ADC_CHANNEL_0
04584   *         @arg @ref LL_ADC_CHANNEL_1            (7)
04585   *         @arg @ref LL_ADC_CHANNEL_2            (7)
04586   *         @arg @ref LL_ADC_CHANNEL_3            (7)
04587   *         @arg @ref LL_ADC_CHANNEL_4            (7)
04588   *         @arg @ref LL_ADC_CHANNEL_5            (7)
04589   *         @arg @ref LL_ADC_CHANNEL_6
04590   *         @arg @ref LL_ADC_CHANNEL_7
04591   *         @arg @ref LL_ADC_CHANNEL_8
04592   *         @arg @ref LL_ADC_CHANNEL_9
04593   *         @arg @ref LL_ADC_CHANNEL_10
04594   *         @arg @ref LL_ADC_CHANNEL_11
04595   *         @arg @ref LL_ADC_CHANNEL_12
04596   *         @arg @ref LL_ADC_CHANNEL_13
04597   *         @arg @ref LL_ADC_CHANNEL_14
04598   *         @arg @ref LL_ADC_CHANNEL_15
04599   *         @arg @ref LL_ADC_CHANNEL_16
04600   *         @arg @ref LL_ADC_CHANNEL_17
04601   *         @arg @ref LL_ADC_CHANNEL_18
04602   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04603   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
04604   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
04605   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)
04606   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)
04607   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
04608   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
04609   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
04610   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
04611   *
04612   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
04613   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
04614   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
04615   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
04616   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
04617   *         (6) On STM32L4, parameter available on devices with several ADC instances.\n
04618   *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
04619   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
04620   * @retval Returned value can be one of the following values:
04621   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
04622   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
04623   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
04624   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
04625   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
04626   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
04627   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
04628   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
04629   */
04630 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
04631 {
04632   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
04633
04634   return (uint32_t)(READ_BIT(*preg,
04635                              ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
04636                     >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
04637                    );
04638 }
04639
04640 /**
04641   * @brief  Set mode single-ended or differential input of the selected
04642   *         ADC channel.
04643   * @note   Channel ending is on channel scope: independently of channel mapped
04644   *         on ADC group regular or injected.
04645   *         In differential mode: Differential measurement is carried out
04646   *         between the selected channel 'i' (positive input) and
04647   *         channel 'i+1' (negative input). Only channel 'i' has to be
04648   *         configured, channel 'i+1' is configured automatically.
04649   * @note   Refer to Reference Manual to ensure the selected channel is
04650   *         available in differential mode.
04651   *         For example, internal channels (VrefInt, TempSensor, ...) are
04652   *         not available in differential mode.
04653   * @note   When configuring a channel 'i' in differential mode,
04654   *         the channel 'i+1' is not usable separately.
04655   * @note   On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
04656   *         are internally fixed to single-ended inputs configuration.
04657   * @note   For ADC channels configured in differential mode, both inputs
04658   *         should be biased at (Vref+)/2 +/-200mV.
04659   *         (Vref+ is the analog voltage reference)
04660   * @note   On this STM32 serie, setting of this feature is conditioned to
04661   *         ADC state:
04662   *         ADC must be ADC disabled.
04663   * @note   One or several values can be selected.
04664   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
04665   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSamplingTime
04666   * @param  ADCx ADC instance
04667   * @param  Channel This parameter can be one of the following values:
04668   *         @arg @ref LL_ADC_CHANNEL_1
04669   *         @arg @ref LL_ADC_CHANNEL_2
04670   *         @arg @ref LL_ADC_CHANNEL_3
04671   *         @arg @ref LL_ADC_CHANNEL_4
04672   *         @arg @ref LL_ADC_CHANNEL_5
04673   *         @arg @ref LL_ADC_CHANNEL_6
04674   *         @arg @ref LL_ADC_CHANNEL_7
04675   *         @arg @ref LL_ADC_CHANNEL_8
04676   *         @arg @ref LL_ADC_CHANNEL_9
04677   *         @arg @ref LL_ADC_CHANNEL_10
04678   *         @arg @ref LL_ADC_CHANNEL_11
04679   *         @arg @ref LL_ADC_CHANNEL_12
04680   *         @arg @ref LL_ADC_CHANNEL_13
04681   *         @arg @ref LL_ADC_CHANNEL_14
04682   * @param  SingleDiff This parameter can be a combination of the following values:
04683   *         @arg @ref LL_ADC_SINGLE_ENDED
04684   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
04685   * @retval None
04686   */
04687 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
04688 {
04689   /* Bits of channels in single or differential mode are set only for         */
04690   /* differential mode (for single mode, mask of bits allowed to be set is    */
04691   /* shifted out of range of bits of channels in single or differential mode. */
04692   MODIFY_REG(ADCx->DIFSEL,
04693              Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
04694              (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
04695 }
04696
04697 /**
04698   * @brief  Get mode single-ended or differential input of the selected
04699   *         ADC channel.
04700   * @note   When configuring a channel 'i' in differential mode,
04701   *         the channel 'i+1' is not usable separately.
04702   *         Therefore, to ensure a channel is configured in single-ended mode,
04703   *         the configuration of channel itself and the channel 'i-1' must be
04704   *         read back (to ensure that the selected channel channel has not been
04705   *         configured in differential mode by the previous channel).
04706   * @note   Refer to Reference Manual to ensure the selected channel is
04707   *         available in differential mode.
04708   *         For example, internal channels (VrefInt, TempSensor, ...) are
04709   *         not available in differential mode.
04710   * @note   When configuring a channel 'i' in differential mode,
04711   *         the channel 'i+1' is not usable separately.
04712   * @note   On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
04713   *         are internally fixed to single-ended inputs configuration.
04714   * @note   One or several values can be selected. In this case, the value
04715   *         returned is null if all channels are in single ended-mode.
04716   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
04717   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSamplingTime
04718   * @param  ADCx ADC instance
04719   * @param  Channel This parameter can be a combination of the following values:
04720   *         @arg @ref LL_ADC_CHANNEL_0
04721   *         @arg @ref LL_ADC_CHANNEL_1
04722   *         @arg @ref LL_ADC_CHANNEL_2
04723   *         @arg @ref LL_ADC_CHANNEL_3
04724   *         @arg @ref LL_ADC_CHANNEL_4
04725   *         @arg @ref LL_ADC_CHANNEL_5
04726   *         @arg @ref LL_ADC_CHANNEL_6
04727   *         @arg @ref LL_ADC_CHANNEL_7
04728   *         @arg @ref LL_ADC_CHANNEL_8
04729   *         @arg @ref LL_ADC_CHANNEL_9
04730   *         @arg @ref LL_ADC_CHANNEL_10
04731   *         @arg @ref LL_ADC_CHANNEL_11
04732   *         @arg @ref LL_ADC_CHANNEL_12
04733   *         @arg @ref LL_ADC_CHANNEL_13
04734   *         @arg @ref LL_ADC_CHANNEL_14
04735   * @retval 0: channel in single-ended mode, else: channel in differential mode
04736   */
04737 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
04738 {
04739   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
04740 }
04741
04742 /**
04743   * @}
04744   */
04745
04746 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
04747   * @{
04748   */
04749
04750 /**
04751   * @brief  Set ADC analog watchdog monitored channels:
04752   *         a single channel, multiple channels or all channels,
04753   *         on ADC groups regular and-or injected.
04754   * @note   Once monitored channels are selected, analog watchdog
04755   *         is enabled.
04756   * @note   In case of need to define a single channel to monitor
04757   *         with analog watchdog from sequencer channel definition,
04758   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
04759   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
04760   *         instance:
04761   *         - AWD standard (instance AWD1):
04762   *           - channels monitored: can monitor 1 channel or all channels.
04763   *           - groups monitored: ADC groups regular and-or injected.
04764   *           - resolution: resolution is not limited (corresponds to
04765   *             ADC resolution configured).
04766   *         - AWD flexible (instances AWD2, AWD3):
04767   *           - channels monitored: flexible on channels monitored, selection is
04768   *             channel wise, from from 1 to all channels.
04769   *             Specificity of this analog watchdog: Multiple channels can
04770   *             be selected. For example:
04771   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04772   *           - groups monitored: not selection possible (monitoring on both
04773   *             groups regular and injected).
04774   *             Channels selected are monitored on groups regular and injected:
04775   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04776   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04777   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
04778   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04779   *             the 2 LSB are ignored.
04780   * @note   On this STM32 serie, setting of this feature is conditioned to
04781   *         ADC state:
04782   *         ADC must be disabled or enabled without conversion on going
04783   *         on either groups regular or injected.
04784   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
04785   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
04786   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
04787   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
04788   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
04789   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
04790   * @param  ADCx ADC instance
04791   * @param  AWDy This parameter can be one of the following values:
04792   *         @arg @ref LL_ADC_AWD1
04793   *         @arg @ref LL_ADC_AWD2
04794   *         @arg @ref LL_ADC_AWD3
04795   * @param  AWDChannelGroup This parameter can be one of the following values:
04796   *         @arg @ref LL_ADC_AWD_DISABLE
04797   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
04798   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
04799   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
04800   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
04801   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
04802   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
04803   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
04804   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
04805   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
04806   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
04807   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
04808   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
04809   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
04810   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
04811   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
04812   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
04813   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
04814   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
04815   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
04816   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
04817   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
04818   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
04819   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
04820   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
04821   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
04822   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
04823   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
04824   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
04825   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
04826   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
04827   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
04828   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
04829   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
04830   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
04831   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
04832   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
04833   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
04834   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
04835   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
04836   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
04837   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
04838   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
04839   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
04840   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
04841   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
04842   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
04843   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
04844   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
04845   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
04846   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
04847   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
04848   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
04849   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
04850   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
04851   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
04852   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
04853   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
04854   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
04855   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
04856   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
04857   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)
04858   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)
04859   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)
04860   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(4)
04861   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(4)
04862   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (4)
04863   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(4)
04864   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(4)
04865   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (4)
04866   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG          (0)(2)(5)
04867   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ          (0)(2)(5)
04868   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ         (2)(5)
04869   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG          (0)(2)(5)
04870   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ          (0)(2)(5)
04871   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ         (2)(5)
04872   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)(6)
04873   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)(6)
04874   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)(6)
04875   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)(6)
04876   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)(6)
04877   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)(6)
04878   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     (0)(3)(6)
04879   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     (0)(3)(6)
04880   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ    (3)(6)
04881   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     (0)(3)(6)
04882   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     (0)(3)(6)
04883   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ    (3)(6)
04884   *
04885   *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
04886   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
04887   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
04888   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
04889   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
04890   *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
04891   *         (6) On STM32L4, parameter available on devices with several ADC instances.
04892   * @retval None
04893   */
04894 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
04895 {
04896   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
04897   /* in register and register position depending on parameter "AWDy".         */
04898   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
04899   /* containing other bits reserved for other purpose.                        */
04900   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
04901                                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
04902
04903   MODIFY_REG(*preg,
04904              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
04905              AWDChannelGroup & AWDy);
04906 }
04907
04908 /**
04909   * @brief  Get ADC analog watchdog monitored channel.
04910   * @note   Usage of the returned channel number:
04911   *         - To reinject this channel into another function LL_ADC_xxx:
04912   *           the returned channel number is only partly formatted on definition
04913   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
04914   *           with parts of literals LL_ADC_CHANNEL_x or using
04915   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04916   *           Then the selected literal LL_ADC_CHANNEL_x can be used
04917   *           as parameter for another function.
04918   *         - To get the channel number in decimal format:
04919   *           process the returned value with the helper macro
04920   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04921   *           Applicable only when the analog watchdog is set to monitor
04922   *           one channel.
04923   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
04924   *         instance:
04925   *         - AWD standard (instance AWD1):
04926   *           - channels monitored: can monitor 1 channel or all channels.
04927   *           - groups monitored: ADC groups regular and-or injected.
04928   *           - resolution: resolution is not limited (corresponds to
04929   *             ADC resolution configured).
04930   *         - AWD flexible (instances AWD2, AWD3):
04931   *           - channels monitored: flexible on channels monitored, selection is
04932   *             channel wise, from from 1 to all channels.
04933   *             Specificity of this analog watchdog: Multiple channels can
04934   *             be selected. For example:
04935   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04936   *           - groups monitored: not selection possible (monitoring on both
04937   *             groups regular and injected).
04938   *             Channels selected are monitored on groups regular and injected:
04939   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04940   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04941   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
04942   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04943   *             the 2 LSB are ignored.
04944   * @note   On this STM32 serie, setting of this feature is conditioned to
04945   *         ADC state:
04946   *         ADC must be disabled or enabled without conversion on going
04947   *         on either groups regular or injected.
04948   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
04949   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
04950   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
04951   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
04952   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
04953   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
04954   * @param  ADCx ADC instance
04955   * @param  AWDy This parameter can be one of the following values:
04956   *         @arg @ref LL_ADC_AWD1
04957   *         @arg @ref LL_ADC_AWD2 (1)
04958   *         @arg @ref LL_ADC_AWD3 (1)
04959   *
04960   *         (1) On this AWD number, monitored channel can be retrieved
04961   *             if only 1 channel is programmed (or none or all channels).
04962   *             This function cannot retrieve monitored channel if
04963   *             multiple channels are programmed simultaneously
04964   *             by bitfield.
04965   * @retval Returned value can be one of the following values:
04966   *         @arg @ref LL_ADC_AWD_DISABLE
04967   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
04968   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
04969   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
04970   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
04971   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
04972   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
04973   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
04974   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
04975   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
04976   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
04977   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
04978   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
04979   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
04980   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
04981   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
04982   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
04983   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
04984   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
04985   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
04986   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
04987   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
04988   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
04989   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
04990   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
04991   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
04992   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
04993   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
04994   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
04995   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
04996   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
04997   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
04998   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
04999   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
05000   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
05001   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
05002   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
05003   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
05004   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
05005   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
05006   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
05007   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
05008   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
05009   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
05010   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
05011   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
05012   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
05013   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
05014   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
05015   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
05016   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
05017   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
05018   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
05019   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
05020   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
05021   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
05022   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
05023   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
05024   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
05025   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
05026   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
05027   *
05028   *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
05029   */
05030 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
05031 {
05032   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
05033                                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
05034
05035   /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to   */
05036   /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK.                   */
05037   register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK));
05038
05039   /* Set variable of AWD1 monitored channel according to AWD1 features        */
05040   /* and ADC channel definition:                                              */
05041   /* - channel ID with number                                                 */
05042   /* - channel ID with bitfield                                               */
05043   /* - AWD1 single or all channels                                            */
05044   /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of  */
05045   /*   AWD2 or AWD3 selected).                                                */
05046   register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS);
05047
05048   register uint32_t AWD1ChannelGroup = ( (  AWD123ChannelGroup
05049                                           | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle)
05050                                           | (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & ((uint32_t)0x00000001U)))
05051                                          )
05052                                         * (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) | ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS))
05053                                        );
05054
05055   /* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3      */
05056   /* features and ADC channel definition:                                     */
05057   /* - channel ID with number                                                 */
05058   /* - channel ID with bitfield                                               */
05059   /* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to    */
05060   /*   shift AWD1 equivalent single-all channels out of register)             */
05061   /* - AWD2-3 enable or disable                                               */
05062   /* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3,    */
05063   /*       channel can be read back if only 1 channel monitoring              */
05064   /*       is activated, therefore the channel monitoring value channel "3"   */
05065   /*       is not not supported by this function, there is no risk of         */
05066   /*       conflict.                                                          */
05067   register uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */
05068
05069   register uint32_t AWD23ChannelGroup = (((  AWD123ChannelGroup
05070                                            | ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
05071                                            | ((ADC_CFGR_AWD1SGL) >> ((((uint32_t)0x00000001U) >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U))
05072                                            | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)
05073                                           ) >> AWD23Enabled
05074                                          ) >> (((AWDy & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS) << 5U));
05075
05076   return (AWD1ChannelGroup | AWD23ChannelGroup);
05077 }
05078
05079 /**
05080   * @brief  Set ADC analog watchdog thresholds value of both thresholds
05081   *         high and low.
05082   * @note   If value of only one threshold high or low must be set,
05083   *         use function @ref LL_ADC_SetAnalogWDThresholds().
05084   * @note   In case of ADC resolution different of 12 bits,
05085   *         analog watchdog thresholds data require a specific shift.
05086   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
05087   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
05088   *         instance:
05089   *         - AWD standard (instance AWD1):
05090   *           - channels monitored: can monitor 1 channel or all channels.
05091   *           - groups monitored: ADC groups regular and-or injected.
05092   *           - resolution: resolution is not limited (corresponds to
05093   *             ADC resolution configured).
05094   *         - AWD flexible (instances AWD2, AWD3):
05095   *           - channels monitored: flexible on channels monitored, selection is
05096   *             channel wise, from from 1 to all channels.
05097   *             Specificity of this analog watchdog: Multiple channels can
05098   *             be selected. For example:
05099   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
05100   *           - groups monitored: not selection possible (monitoring on both
05101   *             groups regular and injected).
05102   *             Channels selected are monitored on groups regular and injected:
05103   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
05104   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
05105   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
05106   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
05107   *             the 2 LSB are ignored.
05108   * @note   On this STM32 serie, setting of this feature is conditioned to
05109   *         ADC state:
05110   *         ADC must be disabled or enabled without conversion on going
05111   *         on either groups regular or injected.
05112   * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n
05113   *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n
05114   *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n
05115   *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
05116   *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
05117   *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
05118   * @param  ADCx ADC instance
05119   * @param  AWDy This parameter can be one of the following values:
05120   *         @arg @ref LL_ADC_AWD1
05121   *         @arg @ref LL_ADC_AWD2
05122   *         @arg @ref LL_ADC_AWD3
05123   * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
05124   * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
05125   * @retval None
05126   */
05127 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
05128 {
05129   /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
05130   /* position in register and register position depending on parameter        */
05131   /* "AWDy".                                                                  */
05132   /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
05133   /* containing other bits reserved for other purpose.                        */
05134   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
05135
05136   MODIFY_REG(*preg,
05137              ADC_TR1_HT1 | ADC_TR1_LT1,
05138              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
05139 }
05140
05141 /**
05142   * @brief  Set ADC analog watchdog threshold value of threshold
05143   *         high or low.
05144   * @note   If values of both thresholds high or low must be set,
05145   *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
05146   * @note   In case of ADC resolution different of 12 bits,
05147   *         analog watchdog thresholds data require a specific shift.
05148   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
05149   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
05150   *         instance:
05151   *         - AWD standard (instance AWD1):
05152   *           - channels monitored: can monitor 1 channel or all channels.
05153   *           - groups monitored: ADC groups regular and-or injected.
05154   *           - resolution: resolution is not limited (corresponds to
05155   *             ADC resolution configured).
05156   *         - AWD flexible (instances AWD2, AWD3):
05157   *           - channels monitored: flexible on channels monitored, selection is
05158   *             channel wise, from from 1 to all channels.
05159   *             Specificity of this analog watchdog: Multiple channels can
05160   *             be selected. For example:
05161   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
05162   *           - groups monitored: not selection possible (monitoring on both
05163   *             groups regular and injected).
05164   *             Channels selected are monitored on groups regular and injected:
05165   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
05166   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
05167   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
05168   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
05169   *             the 2 LSB are ignored.
05170   * @note   On this STM32 serie, setting of this feature is conditioned to
05171   *         ADC state:
05172   *         ADC must be disabled or enabled without conversion on going
05173   *         on either groups regular or injected.
05174   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
05175   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
05176   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
05177   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
05178   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
05179   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
05180   * @param  ADCx ADC instance
05181   * @param  AWDy This parameter can be one of the following values:
05182   *         @arg @ref LL_ADC_AWD1
05183   *         @arg @ref LL_ADC_AWD2
05184   *         @arg @ref LL_ADC_AWD3
05185   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
05186   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
05187   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
05188   * @param  AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
05189   * @retval None
05190   */
05191 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
05192 {
05193   /* Set bits with content of parameter "AWDThresholdValue" with bits         */
05194   /* position in register and register position depending on parameters       */
05195   /* "AWDThresholdsHighLow" and "AWDy".                                       */
05196   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
05197   /* containing other bits reserved for other purpose.                        */
05198   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
05199
05200   MODIFY_REG(*preg,
05201              AWDThresholdsHighLow,
05202              AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow));
05203 }
05204
05205 /**
05206   * @brief  Get ADC analog watchdog threshold value of threshold high,
05207   *         threshold low or raw data with ADC thresholds high and low
05208   *         concatenated.
05209   * @note   If raw data with ADC thresholds high and low is retrieved,
05210   *         the data of each threshold high or low can be isolated
05211   *         using helper macro:
05212   *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
05213   * @note   In case of ADC resolution different of 12 bits,
05214   *         analog watchdog thresholds data require a specific shift.
05215   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
05216   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
05217   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
05218   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
05219   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
05220   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
05221   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
05222   * @param  ADCx ADC instance
05223   * @param  AWDy This parameter can be one of the following values:
05224   *         @arg @ref LL_ADC_AWD1
05225   *         @arg @ref LL_ADC_AWD2
05226   *         @arg @ref LL_ADC_AWD3
05227   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
05228   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
05229   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
05230   *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
05231   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
05232 */
05233 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
05234 {
05235   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
05236
05237   return (uint32_t)(READ_BIT(*preg,
05238                              (AWDThresholdsHighLow | ADC_TR1_LT1))
05239                     >> POSITION_VAL(AWDThresholdsHighLow)
05240                    );
05241 }
05242
05243 /**
05244   * @}
05245   */
05246
05247 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
05248   * @{
05249   */
05250
05251 /**
05252   * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
05253   *         (availability of ADC group injected depends on STM32 families).
05254   * @note   If both groups regular and injected are selected,
05255   *         specify behavior of ADC group injected interrupting
05256   *         group regular: when ADC group injected is triggered,
05257   *         the oversampling on ADC group regular is either
05258   *         temporary stopped and continued, or resumed from start
05259   *         (oversampler buffer reset).
05260   * @note   On this STM32 serie, setting of this feature is conditioned to
05261   *         ADC state:
05262   *         ADC must be disabled or enabled without conversion on going
05263   *         on either groups regular or injected.
05264   * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
05265   *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
05266   *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
05267   * @param  ADCx ADC instance
05268   * @param  OvsScope This parameter can be one of the following values:
05269   *         @arg @ref LL_ADC_OVS_DISABLE
05270   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
05271   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
05272   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
05273   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
05274   * @retval None
05275   */
05276 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
05277 {
05278   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
05279 }
05280
05281 /**
05282   * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
05283   *         (availability of ADC group injected depends on STM32 families).
05284   * @note   If both groups regular and injected are selected,
05285   *         specify behavior of ADC group injected interrupting
05286   *         group regular: when ADC group injected is triggered,
05287   *         the oversampling on ADC group regular is either
05288   *         temporary stopped and continued, or resumed from start
05289   *         (oversampler buffer reset).
05290   * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
05291   *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
05292   *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
05293   * @param  ADCx ADC instance
05294   * @retval Returned value can be one of the following values:
05295   *         @arg @ref LL_ADC_OVS_DISABLE
05296   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
05297   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
05298   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
05299   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
05300   */
05301 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
05302 {
05303   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
05304 }
05305
05306 /**
05307   * @brief  Set ADC oversampling discontinuous mode (triggered mode)
05308   *         on the selected ADC group.
05309   * @note   Number of oversampled conversions are done either in:
05310   *         - continuous mode (all conversions of oversampling ratio
05311   *           are done from 1 trigger)
05312   *         - discontinuous mode (each conversion of oversampling ratio
05313   *           needs a trigger)
05314   * @note   On this STM32 serie, setting of this feature is conditioned to
05315   *         ADC state:
05316   *         ADC must be disabled or enabled without conversion on going
05317   *         on group regular.
05318   * @note   On this STM32 serie, oversampling discontinuous mode
05319   *         (triggered mode) can be used only when oversampling is
05320   *         set on group regular only and in resumed mode.
05321   * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
05322   * @param  ADCx ADC instance
05323   * @param  OverSamplingDiscont This parameter can be one of the following values:
05324   *         @arg @ref LL_ADC_OVS_REG_CONT
05325   *         @arg @ref LL_ADC_OVS_REG_DISCONT
05326   * @retval None
05327   */
05328 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
05329 {
05330   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
05331 }
05332
05333 /**
05334   * @brief  Get ADC oversampling discontinuous mode (triggered mode)
05335   *         on the selected ADC group.
05336   * @note   Number of oversampled conversions are done either in:
05337   *         - continuous mode (all conversions of oversampling ratio
05338   *           are done from 1 trigger)
05339   *         - discontinuous mode (each conversion of oversampling ratio
05340   *           needs a trigger)
05341   * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
05342   * @param  ADCx ADC instance
05343   * @retval Returned value can be one of the following values:
05344   *         @arg @ref LL_ADC_OVS_REG_CONT
05345   *         @arg @ref LL_ADC_OVS_REG_DISCONT
05346   */
05347 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
05348 {
05349   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
05350 }
05351
05352 /**
05353   * @brief  Set ADC oversampling
05354   *         (impacting both ADC groups regular and injected)
05355   * @note   This function set the 2 items of oversampling configuration:
05356   *         - ratio
05357   *         - shift
05358   * @note   On this STM32 serie, setting of this feature is conditioned to
05359   *         ADC state:
05360   *         ADC must be disabled or enabled without conversion on going
05361   *         on either groups regular or injected.
05362   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
05363   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
05364   * @param  ADCx ADC instance
05365   * @param  Ratio This parameter can be one of the following values:
05366   *         @arg @ref LL_ADC_OVS_RATIO_2
05367   *         @arg @ref LL_ADC_OVS_RATIO_4
05368   *         @arg @ref LL_ADC_OVS_RATIO_8
05369   *         @arg @ref LL_ADC_OVS_RATIO_16
05370   *         @arg @ref LL_ADC_OVS_RATIO_32
05371   *         @arg @ref LL_ADC_OVS_RATIO_64
05372   *         @arg @ref LL_ADC_OVS_RATIO_128
05373   *         @arg @ref LL_ADC_OVS_RATIO_256
05374   * @param  Shift This parameter can be one of the following values:
05375   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
05376   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
05377   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
05378   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
05379   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
05380   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
05381   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
05382   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
05383   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
05384   * @retval None
05385   */
05386 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
05387 {
05388   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
05389 }
05390
05391 /**
05392   * @brief  Get ADC oversampling ratio
05393   *        (impacting both ADC groups regular and injected)
05394   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
05395   * @param  ADCx ADC instance
05396   * @retval Ratio This parameter can be one of the following values:
05397   *         @arg @ref LL_ADC_OVS_RATIO_2
05398   *         @arg @ref LL_ADC_OVS_RATIO_4
05399   *         @arg @ref LL_ADC_OVS_RATIO_8
05400   *         @arg @ref LL_ADC_OVS_RATIO_16
05401   *         @arg @ref LL_ADC_OVS_RATIO_32
05402   *         @arg @ref LL_ADC_OVS_RATIO_64
05403   *         @arg @ref LL_ADC_OVS_RATIO_128
05404   *         @arg @ref LL_ADC_OVS_RATIO_256
05405 */
05406 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
05407 {
05408   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
05409 }
05410
05411 /**
05412   * @brief  Get ADC oversampling shift
05413   *        (impacting both ADC groups regular and injected)
05414   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
05415   * @param  ADCx ADC instance
05416   * @retval Shift This parameter can be one of the following values:
05417   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
05418   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
05419   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
05420   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
05421   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
05422   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
05423   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
05424   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
05425   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
05426 */
05427 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
05428 {
05429   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
05430 }
05431
05432 /**
05433   * @}
05434   */
05435
05436 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
05437   * @{
05438   */
05439
05440 #if defined(ADC_MULTIMODE_SUPPORT)
05441 /**
05442   * @brief  Set ADC multimode configuration to operate in independent mode
05443   *         or multimode (for devices with several ADC instances).
05444   * @note   If multimode configuration: the selected ADC instance is
05445   *         either master or slave depending on hardware.
05446   *         Refer to reference manual.
05447   * @note   On this STM32 serie, setting of this feature is conditioned to
05448   *         ADC state:
05449   *         All ADC instances of the ADC common group must be disabled.
05450   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
05451   *         ADC instance or by using helper macro
05452   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
05453   * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
05454   * @param  ADCxy_COMMON ADC common instance
05455   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05456   * @param  Multimode This parameter can be one of the following values:
05457   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
05458   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
05459   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
05460   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
05461   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
05462   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
05463   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
05464   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
05465   * @retval None
05466   */
05467 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
05468 {
05469   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
05470 }
05471
05472 /**
05473   * @brief  Get ADC multimode configuration to operate in independent mode
05474   *         or multimode (for devices with several ADC instances).
05475   * @note   If multimode configuration: the selected ADC instance is
05476   *         either master or slave depending on hardware.
05477   *         Refer to reference manual.
05478   * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
05479   * @param  ADCxy_COMMON ADC common instance
05480   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05481   * @retval Returned value can be one of the following values:
05482   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
05483   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
05484   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
05485   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
05486   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
05487   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
05488   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
05489   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
05490   */
05491 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
05492 {
05493   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
05494 }
05495
05496 /**
05497   * @brief  Set ADC multimode conversion data transfer: no transfer
05498   *         or transfer by DMA.
05499   * @note   If ADC multimode transfer by DMA is not selected:
05500   *         each ADC uses its own DMA channel, with its individual
05501   *         DMA transfer settings.
05502   *         If ADC multimode transfer by DMA is selected:
05503   *         One DMA channel is used for both ADC (DMA of ADC master)
05504   *         Specifies the DMA requests mode:
05505   *         - Limited mode (One shot mode): DMA transfer requests are stopped
05506   *           when number of DMA data transfers (number of
05507   *           ADC conversions) is reached.
05508   *           This ADC mode is intended to be used with DMA mode non-circular.
05509   *         - Unlimited mode: DMA transfer requests are unlimited,
05510   *           whatever number of DMA data transfers (number of
05511   *           ADC conversions).
05512   *           This ADC mode is intended to be used with DMA mode circular.
05513   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
05514   *         mode non-circular:
05515   *         when DMA transfers size will be reached, DMA will stop transfers of
05516   *         ADC conversions data ADC will raise an overrun error
05517   *         (overrun flag and interruption if enabled).
05518   * @note   How to retrieve multimode conversion data:
05519   *         Whatever multimode transfer by DMA setting: using function
05520   *         @ref LL_ADC_REG_ReadMultiConversionData32().
05521   *         If ADC multimode transfer by DMA is selected: conversion data
05522   *         is a raw data with ADC master and slave concatenated.
05523   *         A macro is available to get the conversion data of
05524   *         ADC master or ADC slave: see helper macro
05525   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
05526   * @note   On this STM32 serie, setting of this feature is conditioned to
05527   *         ADC state:
05528   *         All ADC instances of the ADC common group must be disabled
05529   *         or enabled without conversion on going on group regular.
05530   * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n
05531   *         CCR      DMACFG         LL_ADC_SetMultiDMATransfer
05532   * @param  ADCxy_COMMON ADC common instance
05533   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05534   * @param  MultiDMATransfer This parameter can be one of the following values:
05535   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
05536   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
05537   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
05538   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
05539   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
05540   * @retval None
05541   */
05542 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
05543 {
05544   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
05545 }
05546
05547 /**
05548   * @brief  Get ADC multimode conversion data transfer: no transfer
05549   *         or transfer by DMA.
05550   * @note   If ADC multimode transfer by DMA is not selected:
05551   *         each ADC uses its own DMA channel, with its individual
05552   *         DMA transfer settings.
05553   *         If ADC multimode transfer by DMA is selected:
05554   *         One DMA channel is used for both ADC (DMA of ADC master)
05555   *         Specifies the DMA requests mode:
05556   *         - Limited mode (One shot mode): DMA transfer requests are stopped
05557   *           when number of DMA data transfers (number of
05558   *           ADC conversions) is reached.
05559   *           This ADC mode is intended to be used with DMA mode non-circular.
05560   *         - Unlimited mode: DMA transfer requests are unlimited,
05561   *           whatever number of DMA data transfers (number of
05562   *           ADC conversions).
05563   *           This ADC mode is intended to be used with DMA mode circular.
05564   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
05565   *         mode non-circular:
05566   *         when DMA transfers size will be reached, DMA will stop transfers of
05567   *         ADC conversions data ADC will raise an overrun error
05568   *         (overrun flag and interruption if enabled).
05569   * @note   How to retrieve multimode conversion data:
05570   *         Whatever multimode transfer by DMA setting: using function
05571   *         @ref LL_ADC_REG_ReadMultiConversionData32().
05572   *         If ADC multimode transfer by DMA is selected: conversion data
05573   *         is a raw data with ADC master and slave concatenated.
05574   *         A macro is available to get the conversion data of
05575   *         ADC master or ADC slave: see helper macro
05576   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
05577   * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n
05578   *         CCR      DMACFG         LL_ADC_GetMultiDMATransfer
05579   * @param  ADCxy_COMMON ADC common instance
05580   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05581   * @retval Returned value can be one of the following values:
05582   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
05583   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
05584   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
05585   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
05586   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
05587   */
05588 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
05589 {
05590   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
05591 }
05592
05593 /**
05594   * @brief  Set ADC multimode delay between 2 sampling phases.
05595   * @note   The sampling delay range depends on ADC resolution:
05596   *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
05597   *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
05598   *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
05599   *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
05600   * @note   On this STM32 serie, setting of this feature is conditioned to
05601   *         ADC state:
05602   *         All ADC instances of the ADC common group must be disabled.
05603   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
05604   *         ADC instance or by using helper macro helper macro
05605   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
05606   * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
05607   * @param  ADCxy_COMMON ADC common instance
05608   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05609   * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
05610   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
05611   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
05612   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
05613   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
05614   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
05615   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
05616   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
05617   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
05618   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
05619   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
05620   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
05621   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
05622   *
05623   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
05624   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
05625   *         (3) Parameter available only if ADC resolution is 12 bits.
05626   * @retval None
05627   */
05628 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
05629 {
05630   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
05631 }
05632
05633 /**
05634   * @brief  Get ADC multimode delay between 2 sampling phases.
05635   * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
05636   * @param  ADCxy_COMMON ADC common instance
05637   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05638   * @retval Returned value can be one of the following values:
05639   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
05640   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
05641   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
05642   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
05643   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
05644   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
05645   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
05646   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
05647   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
05648   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
05649   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
05650   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
05651   *
05652   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
05653   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
05654   *         (3) Parameter available only if ADC resolution is 12 bits.
05655   */
05656 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
05657 {
05658   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
05659 }
05660 #endif /* ADC_MULTIMODE_SUPPORT */
05661
05662 /**
05663   * @}
05664   */
05665 /** @defgroup ADC_LL_EF_Configuration_Leg_Functions Configuration of ADC alternate functions name
05666   * @{
05667   */
05668 /* Old functions name kept for legacy purpose, to be replaced by the          */
05669 /* current functions name.                                                    */
05670 __STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
05671 {
05672   LL_ADC_REG_SetTrigSource(ADCx, TriggerSource);
05673 }
05674 __STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
05675 {
05676   LL_ADC_INJ_SetTrigSource(ADCx, TriggerSource);
05677 }
05678
05679 /**
05680   * @}
05681   */
05682
05683 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
05684   * @{
05685   */
05686
05687 /**
05688   * @brief  Put ADC instance in deep power down state.
05689   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
05690   *         state, the internal analog calibration is lost. After exiting from
05691   *         deep power down, calibration must be relaunched or calibration factor
05692   *         (preliminarily saved) must be set back into calibration register.
05693   * @note   On this STM32 serie, setting of this feature is conditioned to
05694   *         ADC state:
05695   *         ADC must be ADC disabled.
05696   * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
05697   * @param  ADCx ADC instance
05698   * @retval None
05699   */
05700 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
05701 {
05702   /* Note: Write register with some additional bits forced to state reset     */
05703   /*       instead of modifying only the selected bit for this function,      */
05704   /*       to not interfere with bits with HW property "rs".                  */
05705   MODIFY_REG(ADCx->CR,
05706              ADC_CR_BITS_PROPERTY_RS,
05707              ADC_CR_DEEPPWD);
05708 }
05709
05710 /**
05711   * @brief  Disable ADC deep power down mode.
05712   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
05713   *         state, the internal analog calibration is lost. After exiting from
05714   *         deep power down, calibration must be relaunched or calibration factor
05715   *         (preliminarily saved) must be set back into calibration register.
05716   * @note   On this STM32 serie, setting of this feature is conditioned to
05717   *         ADC state:
05718   *         ADC must be ADC disabled.
05719   * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
05720   * @param  ADCx ADC instance
05721   * @retval None
05722   */
05723 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
05724 {
05725   /* Note: Write register with some additional bits forced to state reset     */
05726   /*       instead of modifying only the selected bit for this function,      */
05727   /*       to not interfere with bits with HW property "rs".                  */
05728   CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
05729 }
05730
05731 /**
05732   * @brief  Get the selected ADC instance deep power down state.
05733   * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
05734   * @param  ADCx ADC instance
05735   * @retval 0: deep power down is disabled, 1: deep power down is enabled.
05736   */
05737 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
05738 {
05739   return (READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD));
05740 }
05741
05742 /**
05743   * @brief  Enable ADC instance internal voltage regulator.
05744   * @note   On this STM32 serie, after ADC internal voltage regulator enable,
05745   *         a delay for ADC internal voltage regulator stabilization
05746   *         is required before performing a ADC calibration or ADC enable.
05747   *         Refer to device datasheet, parameter tADCVREG_STUP.
05748   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
05749   * @note   On this STM32 serie, setting of this feature is conditioned to
05750   *         ADC state:
05751   *         ADC must be ADC disabled.
05752   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
05753   * @param  ADCx ADC instance
05754   * @retval None
05755   */
05756 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
05757 {
05758   /* Note: Write register with some additional bits forced to state reset     */
05759   /*       instead of modifying only the selected bit for this function,      */
05760   /*       to not interfere with bits with HW property "rs".                  */
05761   MODIFY_REG(ADCx->CR,
05762              ADC_CR_BITS_PROPERTY_RS,
05763              ADC_CR_ADVREGEN);
05764 }
05765
05766 /**
05767   * @brief  Disable ADC internal voltage regulator.
05768   * @note   On this STM32 serie, setting of this feature is conditioned to
05769   *         ADC state:
05770   *         ADC must be ADC disabled.
05771   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
05772   * @param  ADCx ADC instance
05773   * @retval None
05774   */
05775 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
05776 {
05777   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
05778 }
05779
05780 /**
05781   * @brief  Get the selected ADC instance internal voltage regulator state.
05782   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
05783   * @param  ADCx ADC instance
05784   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
05785   */
05786 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
05787 {
05788   return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN));
05789 }
05790
05791 /**
05792   * @brief  Enable the selected ADC instance.
05793   * @note   On this STM32 serie, after ADC enable, a delay for
05794   *         ADC internal analog stabilization is required before performing a
05795   *         ADC conversion start.
05796   *         Refer to device datasheet, parameter tSTAB.
05797   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
05798   *         is enabled and when conversion clock is active.
05799   *         (not only core clock: this ADC has a dual clock domain)
05800   * @note   On this STM32 serie, setting of this feature is conditioned to
05801   *         ADC state:
05802   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
05803   * @rmtoll CR       ADEN           LL_ADC_Enable
05804   * @param  ADCx ADC instance
05805   * @retval None
05806   */
05807 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
05808 {
05809   /* Note: Write register with some additional bits forced to state reset     */
05810   /*       instead of modifying only the selected bit for this function,      */
05811   /*       to not interfere with bits with HW property "rs".                  */
05812   MODIFY_REG(ADCx->CR,
05813              ADC_CR_BITS_PROPERTY_RS,
05814              ADC_CR_ADEN);
05815 }
05816
05817 /**
05818   * @brief  Disable the selected ADC instance.
05819   * @note   On this STM32 serie, setting of this feature is conditioned to
05820   *         ADC state:
05821   *         ADC must be not disabled. Must be enabled without conversion on going
05822   *         on either groups regular or injected.
05823   * @rmtoll CR       ADDIS          LL_ADC_Disable
05824   * @param  ADCx ADC instance
05825   * @retval None
05826   */
05827 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
05828 {
05829   /* Note: Write register with some additional bits forced to state reset     */
05830   /*       instead of modifying only the selected bit for this function,      */
05831   /*       to not interfere with bits with HW property "rs".                  */
05832   MODIFY_REG(ADCx->CR,
05833              ADC_CR_BITS_PROPERTY_RS,
05834              ADC_CR_ADDIS);
05835 }
05836
05837 /**
05838   * @brief  Get the selected ADC instance enable state.
05839   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
05840   *         is enabled and when conversion clock is active.
05841   *         (not only core clock: this ADC has a dual clock domain)
05842   * @rmtoll CR       ADEN           LL_ADC_IsEnabled
05843   * @param  ADCx ADC instance
05844   * @retval 0: ADC is disabled, 1: ADC is enabled.
05845   */
05846 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
05847 {
05848   return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
05849 }
05850
05851 /**
05852   * @brief  Get the selected ADC instance disable state.
05853   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
05854   * @param  ADCx ADC instance
05855   * @retval 0: no ADC disable command on going.
05856   */
05857 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
05858 {
05859   return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
05860 }
05861
05862 /**
05863   * @brief  Start ADC calibration in the mode single-ended
05864   *         or differential (for devices with differential mode available).
05865   * @note   On this STM32 serie, a minimum number of ADC clock cycles
05866   *         are required between ADC end of calibration and ADC enable.
05867   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
05868   * @note   For devices with differential mode available:
05869   *         Calibration of offset is specific to each of
05870   *         single-ended and differential modes
05871   *         (calibration run must be performed for each of these
05872   *         differential modes, if used afterwards and if the application
05873   *         requires their calibration).
05874   * @note   On this STM32 serie, setting of this feature is conditioned to
05875   *         ADC state:
05876   *         ADC must be ADC disabled.
05877   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
05878   *         CR       ADCALDIF       LL_ADC_StartCalibration
05879   * @param  ADCx ADC instance
05880   * @param  SingleDiff This parameter can be one of the following values:
05881   *         @arg @ref LL_ADC_SINGLE_ENDED
05882   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
05883   * @retval None
05884   */
05885 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
05886 {
05887   /* Note: Write register with some additional bits forced to state reset     */
05888   /*       instead of modifying only the selected bit for this function,      */
05889   /*       to not interfere with bits with HW property "rs".                  */
05890   MODIFY_REG(ADCx->CR,
05891              ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
05892              ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
05893 }
05894
05895 /**
05896   * @brief  Get ADC calibration state.
05897   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
05898   * @param  ADCx ADC instance
05899   * @retval 0: calibration complete, 1: calibration in progress.
05900   */
05901 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
05902 {
05903   return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
05904 }
05905
05906 /**
05907   * @}
05908   */
05909
05910 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
05911   * @{
05912   */
05913
05914 /**
05915   * @brief  Start ADC group regular conversion.
05916   * @note   On this STM32 serie, this function is relevant for both
05917   *         internal trigger (SW start) and external trigger:
05918   *         - If ADC trigger has been set to software start, ADC conversion
05919   *           starts immediately.
05920   *         - If ADC trigger has been set to external trigger, ADC conversion
05921   *           will start at next trigger event (on the selected trigger edge)
05922   *           following the ADC start conversion command.
05923   * @note   On this STM32 serie, setting of this feature is conditioned to
05924   *         ADC state:
05925   *         ADC must be enabled without conversion on going on group regular,
05926   *         without conversion stop command on going on group regular.
05927   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
05928   * @param  ADCx ADC instance
05929   * @retval None
05930   */
05931 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
05932 {
05933   /* Note: Write register with some additional bits forced to state reset     */
05934   /*       instead of modifying only the selected bit for this function,      */
05935   /*       to not interfere with bits with HW property "rs".                  */
05936   MODIFY_REG(ADCx->CR,
05937              ADC_CR_BITS_PROPERTY_RS,
05938              ADC_CR_ADSTART);
05939 }
05940
05941 /**
05942   * @brief  Stop ADC group regular conversion.
05943   * @note   On this STM32 serie, setting of this feature is conditioned to
05944   *         ADC state:
05945   *         ADC must be enabled with conversion on going on group regular,
05946   *         without ADC disable command on going.
05947   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
05948   * @param  ADCx ADC instance
05949   * @retval None
05950   */
05951 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
05952 {
05953   /* Note: Write register with some additional bits forced to state reset     */
05954   /*       instead of modifying only the selected bit for this function,      */
05955   /*       to not interfere with bits with HW property "rs".                  */
05956   MODIFY_REG(ADCx->CR,
05957              ADC_CR_BITS_PROPERTY_RS,
05958              ADC_CR_ADSTP);
05959 }
05960
05961 /**
05962   * @brief  Get ADC group regular conversion state.
05963   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
05964   * @param  ADCx ADC instance
05965   * @retval 0: no conversion is on going on ADC group regular.
05966   */
05967 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
05968 {
05969   return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
05970 }
05971
05972 /**
05973   * @brief  Get ADC group regular command of conversion stop state
05974   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
05975   * @param  ADCx ADC instance
05976   * @retval 0: no command of conversion stop is on going on ADC group regular.
05977   */
05978 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
05979 {
05980   return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
05981 }
05982
05983 /**
05984   * @brief  Get ADC group regular conversion data, range fit for
05985   *         all ADC configurations: all ADC resolutions and
05986   *         all oversampling increased data width (for devices
05987   *         with feature oversampling).
05988   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
05989   * @param  ADCx ADC instance
05990   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
05991   */
05992 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
05993 {
05994   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05995 }
05996
05997 /**
05998   * @brief  Get ADC group regular conversion data, range fit for
05999   *         ADC resolution 12 bits.
06000   * @note   For devices with feature oversampling: Oversampling
06001   *         can increase data width, function for extended range
06002   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
06003   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
06004   * @param  ADCx ADC instance
06005   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
06006   */
06007 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
06008 {
06009   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
06010 }
06011
06012 /**
06013   * @brief  Get ADC group regular conversion data, range fit for
06014   *         ADC resolution 10 bits.
06015   * @note   For devices with feature oversampling: Oversampling
06016   *         can increase data width, function for extended range
06017   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
06018   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
06019   * @param  ADCx ADC instance
06020   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
06021   */
06022 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
06023 {
06024   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
06025 }
06026
06027 /**
06028   * @brief  Get ADC group regular conversion data, range fit for
06029   *         ADC resolution 8 bits.
06030   * @note   For devices with feature oversampling: Oversampling
06031   *         can increase data width, function for extended range
06032   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
06033   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
06034   * @param  ADCx ADC instance
06035   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
06036   */
06037 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
06038 {
06039   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
06040 }
06041
06042 /**
06043   * @brief  Get ADC group regular conversion data, range fit for
06044   *         ADC resolution 6 bits.
06045   * @note   For devices with feature oversampling: Oversampling
06046   *         can increase data width, function for extended range
06047   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
06048   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
06049   * @param  ADCx ADC instance
06050   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
06051   */
06052 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
06053 {
06054   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
06055 }
06056
06057 #if defined(ADC_MULTIMODE_SUPPORT)
06058 /**
06059   * @brief  Get ADC multimode conversion data of ADC master, ADC slave
06060   *         or raw data with ADC master and slave concatenated.
06061   * @note   If raw data with ADC master and slave concatenated is retrieved,
06062   *         a macro is available to get the conversion data of
06063   *         ADC master or ADC slave: see helper macro
06064   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
06065   *         (however this macro is mainly intended for multimode
06066   *         transfer by DMA, because this function can do the same
06067   *         by getting multimode conversion data of ADC master or ADC slave
06068   *         separately).
06069   * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n
06070   *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32
06071   * @param  ADCxy_COMMON ADC common instance
06072   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06073   * @param  ConversionData This parameter can be one of the following values:
06074   *         @arg @ref LL_ADC_MULTI_MASTER
06075   *         @arg @ref LL_ADC_MULTI_SLAVE
06076   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
06077   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
06078   */
06079 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
06080 {
06081   return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
06082                              ConversionData)
06083                     >> POSITION_VAL(ConversionData)
06084                    );
06085 }
06086 #endif /* ADC_MULTIMODE_SUPPORT */
06087
06088 /**
06089   * @}
06090   */
06091
06092 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
06093   * @{
06094   */
06095
06096 /**
06097   * @brief  Start ADC group injected conversion.
06098   * @note   On this STM32 serie, this function is relevant for both
06099   *         internal trigger (SW start) and external trigger:
06100   *         - If ADC trigger has been set to software start, ADC conversion
06101   *           starts immediately.
06102   *         - If ADC trigger has been set to external trigger, ADC conversion
06103   *           will start at next trigger event (on the selected trigger edge)
06104   *           following the ADC start conversion command.
06105   * @note   On this STM32 serie, setting of this feature is conditioned to
06106   *         ADC state:
06107   *         ADC must be enabled without conversion on going on group injected,
06108   *         without conversion stop command on going on group injected.
06109   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
06110   * @param  ADCx ADC instance
06111   * @retval None
06112   */
06113 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
06114 {
06115   /* Note: Write register with some additional bits forced to state reset     */
06116   /*       instead of modifying only the selected bit for this function,      */
06117   /*       to not interfere with bits with HW property "rs".                  */
06118   MODIFY_REG(ADCx->CR,
06119              ADC_CR_BITS_PROPERTY_RS,
06120              ADC_CR_JADSTART);
06121 }
06122
06123 /**
06124   * @brief  Stop ADC group injected conversion.
06125   * @note   On this STM32 serie, setting of this feature is conditioned to
06126   *         ADC state:
06127   *         ADC must be enabled with conversion on going on group injected,
06128   *         without ADC disable command on going.
06129   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
06130   * @param  ADCx ADC instance
06131   * @retval None
06132   */
06133 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
06134 {
06135   /* Note: Write register with some additional bits forced to state reset     */
06136   /*       instead of modifying only the selected bit for this function,      */
06137   /*       to not interfere with bits with HW property "rs".                  */
06138   MODIFY_REG(ADCx->CR,
06139              ADC_CR_BITS_PROPERTY_RS,
06140              ADC_CR_JADSTP);
06141 }
06142
06143 /**
06144   * @brief  Get ADC group injected conversion state.
06145   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
06146   * @param  ADCx ADC instance
06147   * @retval 0: no conversion is on going on ADC group injected.
06148   */
06149 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
06150 {
06151   return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));
06152 }
06153
06154 /**
06155   * @brief  Get ADC group injected command of conversion stop state
06156   * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
06157   * @param  ADCx ADC instance
06158   * @retval 0: no command of conversion stop is on going on ADC group injected.
06159   */
06160 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
06161 {
06162   return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));
06163 }
06164
06165 /**
06166   * @brief  Get ADC group regular conversion data, range fit for
06167   *         all ADC configurations: all ADC resolutions and
06168   *         all oversampling increased data width (for devices
06169   *         with feature oversampling).
06170   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
06171   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
06172   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
06173   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
06174   * @param  ADCx ADC instance
06175   * @param  Rank This parameter can be one of the following values:
06176   *         @arg @ref LL_ADC_INJ_RANK_1
06177   *         @arg @ref LL_ADC_INJ_RANK_2
06178   *         @arg @ref LL_ADC_INJ_RANK_3
06179   *         @arg @ref LL_ADC_INJ_RANK_4
06180   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
06181   */
06182 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
06183 {
06184   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
06185
06186   return (uint32_t)(READ_BIT(*preg,
06187                              ADC_JDR1_JDATA)
06188                    );
06189 }
06190
06191 /**
06192   * @brief  Get ADC group injected conversion data, range fit for
06193   *         ADC resolution 12 bits.
06194   * @note   For devices with feature oversampling: Oversampling
06195   *         can increase data width, function for extended range
06196   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06197   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
06198   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
06199   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
06200   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
06201   * @param  ADCx ADC instance
06202   * @param  Rank This parameter can be one of the following values:
06203   *         @arg @ref LL_ADC_INJ_RANK_1
06204   *         @arg @ref LL_ADC_INJ_RANK_2
06205   *         @arg @ref LL_ADC_INJ_RANK_3
06206   *         @arg @ref LL_ADC_INJ_RANK_4
06207   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
06208   */
06209 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
06210 {
06211   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
06212
06213   return (uint16_t)(READ_BIT(*preg,
06214                              ADC_JDR1_JDATA)
06215                    );
06216 }
06217
06218 /**
06219   * @brief  Get ADC group injected conversion data, range fit for
06220   *         ADC resolution 10 bits.
06221   * @note   For devices with feature oversampling: Oversampling
06222   *         can increase data width, function for extended range
06223   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06224   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
06225   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
06226   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
06227   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
06228   * @param  ADCx ADC instance
06229   * @param  Rank This parameter can be one of the following values:
06230   *         @arg @ref LL_ADC_INJ_RANK_1
06231   *         @arg @ref LL_ADC_INJ_RANK_2
06232   *         @arg @ref LL_ADC_INJ_RANK_3
06233   *         @arg @ref LL_ADC_INJ_RANK_4
06234   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
06235   */
06236 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
06237 {
06238   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
06239
06240   return (uint16_t)(READ_BIT(*preg,
06241                              ADC_JDR1_JDATA)
06242                    );
06243 }
06244
06245 /**
06246   * @brief  Get ADC group injected conversion data, range fit for
06247   *         ADC resolution 8 bits.
06248   * @note   For devices with feature oversampling: Oversampling
06249   *         can increase data width, function for extended range
06250   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06251   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
06252   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
06253   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
06254   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
06255   * @param  ADCx ADC instance
06256   * @param  Rank This parameter can be one of the following values:
06257   *         @arg @ref LL_ADC_INJ_RANK_1
06258   *         @arg @ref LL_ADC_INJ_RANK_2
06259   *         @arg @ref LL_ADC_INJ_RANK_3
06260   *         @arg @ref LL_ADC_INJ_RANK_4
06261   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
06262   */
06263 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
06264 {
06265   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
06266
06267   return (uint8_t)(READ_BIT(*preg,
06268                             ADC_JDR1_JDATA)
06269                   );
06270 }
06271
06272 /**
06273   * @brief  Get ADC group injected conversion data, range fit for
06274   *         ADC resolution 6 bits.
06275   * @note   For devices with feature oversampling: Oversampling
06276   *         can increase data width, function for extended range
06277   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
06278   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
06279   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
06280   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
06281   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
06282   * @param  ADCx ADC instance
06283   * @param  Rank This parameter can be one of the following values:
06284   *         @arg @ref LL_ADC_INJ_RANK_1
06285   *         @arg @ref LL_ADC_INJ_RANK_2
06286   *         @arg @ref LL_ADC_INJ_RANK_3
06287   *         @arg @ref LL_ADC_INJ_RANK_4
06288   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
06289   */
06290 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
06291 {
06292   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
06293
06294   return (uint8_t)(READ_BIT(*preg,
06295                             ADC_JDR1_JDATA)
06296                   );
06297 }
06298
06299 /**
06300   * @}
06301   */
06302
06303 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
06304   * @{
06305   */
06306
06307 /**
06308   * @brief  Get flag ADC ready.
06309   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
06310   *         is enabled and when conversion clock is active.
06311   *         (not only core clock: this ADC has a dual clock domain)
06312   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
06313   * @param  ADCx ADC instance
06314   * @retval State of bit (1 or 0).
06315   */
06316 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
06317 {
06318   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
06319 }
06320
06321 /**
06322   * @brief  Get flag ADC group regular end of unitary conversion.
06323   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
06324   * @param  ADCx ADC instance
06325   * @retval State of bit (1 or 0).
06326   */
06327 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
06328 {
06329   return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
06330 }
06331
06332 /**
06333   * @brief  Get flag ADC group regular end of sequence conversions.
06334   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
06335   * @param  ADCx ADC instance
06336   * @retval State of bit (1 or 0).
06337   */
06338 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
06339 {
06340   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
06341 }
06342
06343 /**
06344   * @brief  Get flag ADC group regular overrun.
06345   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
06346   * @param  ADCx ADC instance
06347   * @retval State of bit (1 or 0).
06348   */
06349 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
06350 {
06351   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
06352 }
06353
06354 /**
06355   * @brief  Get flag ADC group regular end of sampling phase.
06356   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
06357   * @param  ADCx ADC instance
06358   * @retval State of bit (1 or 0).
06359   */
06360 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
06361 {
06362   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
06363 }
06364
06365 /**
06366   * @brief  Get flag ADC group injected end of unitary conversion.
06367   * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
06368   * @param  ADCx ADC instance
06369   * @retval State of bit (1 or 0).
06370   */
06371 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
06372 {
06373   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC));
06374 }
06375
06376 /**
06377   * @brief  Get flag ADC group injected end of sequence conversions.
06378   * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
06379   * @param  ADCx ADC instance
06380   * @retval State of bit (1 or 0).
06381   */
06382 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
06383 {
06384   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
06385 }
06386
06387 /**
06388   * @brief  Get flag ADC group injected contexts queue overflow.
06389   * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF
06390   * @param  ADCx ADC instance
06391   * @retval State of bit (1 or 0).
06392   */
06393 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
06394 {
06395   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF));
06396 }
06397
06398 /**
06399   * @brief  Get flag ADC analog watchdog 1 flag
06400   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
06401   * @param  ADCx ADC instance
06402   * @retval State of bit (1 or 0).
06403   */
06404 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
06405 {
06406   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
06407 }
06408
06409 /**
06410   * @brief  Get flag ADC analog watchdog 2.
06411   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
06412   * @param  ADCx ADC instance
06413   * @retval State of bit (1 or 0).
06414   */
06415 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
06416 {
06417   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2));
06418 }
06419
06420 /**
06421   * @brief  Get flag ADC analog watchdog 3.
06422   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
06423   * @param  ADCx ADC instance
06424   * @retval State of bit (1 or 0).
06425   */
06426 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
06427 {
06428   return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3));
06429 }
06430
06431 /**
06432   * @brief  Clear flag ADC ready.
06433   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
06434   *         is enabled and when conversion clock is active.
06435   *         (not only core clock: this ADC has a dual clock domain)
06436   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
06437   * @param  ADCx ADC instance
06438   * @retval None
06439   */
06440 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
06441 {
06442   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
06443 }
06444
06445 /**
06446   * @brief  Clear flag ADC group regular end of unitary conversion.
06447   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
06448   * @param  ADCx ADC instance
06449   * @retval None
06450   */
06451 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
06452 {
06453   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
06454 }
06455
06456 /**
06457   * @brief  Clear flag ADC group regular end of sequence conversions.
06458   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
06459   * @param  ADCx ADC instance
06460   * @retval None
06461   */
06462 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
06463 {
06464   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
06465 }
06466
06467 /**
06468   * @brief  Clear flag ADC group regular overrun.
06469   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
06470   * @param  ADCx ADC instance
06471   * @retval None
06472   */
06473 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
06474 {
06475   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
06476 }
06477
06478 /**
06479   * @brief  Clear flag ADC group regular end of sampling phase.
06480   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
06481   * @param  ADCx ADC instance
06482   * @retval None
06483   */
06484 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
06485 {
06486   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
06487 }
06488
06489 /**
06490   * @brief  Clear flag ADC group injected end of unitary conversion.
06491   * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
06492   * @param  ADCx ADC instance
06493   * @retval None
06494   */
06495 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
06496 {
06497   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
06498 }
06499
06500 /**
06501   * @brief  Clear flag ADC group injected end of sequence conversions.
06502   * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
06503   * @param  ADCx ADC instance
06504   * @retval None
06505   */
06506 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
06507 {
06508   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
06509 }
06510
06511 /**
06512   * @brief  Clear flag ADC group injected contexts queue overflow.
06513   * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF
06514   * @param  ADCx ADC instance
06515   * @retval None
06516   */
06517 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
06518 {
06519   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
06520 }
06521
06522 /**
06523   * @brief  Clear flag ADC analog watchdog 1.
06524   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
06525   * @param  ADCx ADC instance
06526   * @retval None
06527   */
06528 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
06529 {
06530   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
06531 }
06532
06533 /**
06534   * @brief  Clear flag ADC analog watchdog 2.
06535   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
06536   * @param  ADCx ADC instance
06537   * @retval None
06538   */
06539 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
06540 {
06541   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
06542 }
06543
06544 /**
06545   * @brief  Clear flag ADC analog watchdog 3.
06546   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
06547   * @param  ADCx ADC instance
06548   * @retval None
06549   */
06550 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
06551 {
06552   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
06553 }
06554
06555 #if defined(ADC_MULTIMODE_SUPPORT)
06556 /**
06557   * @brief  Get flag multimode ADC ready of the ADC master.
06558   * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY
06559   * @param  ADCxy_COMMON ADC common instance
06560   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06561   * @retval State of bit (1 or 0).
06562   */
06563 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
06564 {
06565   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST));
06566 }
06567
06568 /**
06569   * @brief  Get flag multimode ADC ready of the ADC slave.
06570   * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY
06571   * @param  ADCxy_COMMON ADC common instance
06572   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06573   * @retval State of bit (1 or 0).
06574   */
06575 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
06576 {
06577   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV));
06578 }
06579
06580 /**
06581   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.
06582   * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC
06583   * @param  ADCxy_COMMON ADC common instance
06584   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06585   * @retval State of bit (1 or 0).
06586   */
06587 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
06588 {
06589   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
06590 }
06591
06592 /**
06593   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
06594   * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC
06595   * @param  ADCxy_COMMON ADC common instance
06596   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06597   * @retval State of bit (1 or 0).
06598   */
06599 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
06600 {
06601   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
06602 }
06603
06604 /**
06605   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
06606   * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS
06607   * @param  ADCxy_COMMON ADC common instance
06608   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06609   * @retval State of bit (1 or 0).
06610   */
06611 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
06612 {
06613   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST));
06614 }
06615
06616 /**
06617   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
06618   * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS
06619   * @param  ADCxy_COMMON ADC common instance
06620   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06621   * @retval State of bit (1 or 0).
06622   */
06623 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
06624 {
06625   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
06626 }
06627
06628 /**
06629   * @brief  Get flag multimode ADC group regular overrun of the ADC master.
06630   * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR
06631   * @param  ADCxy_COMMON ADC common instance
06632   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06633   * @retval State of bit (1 or 0).
06634   */
06635 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
06636 {
06637   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
06638 }
06639
06640 /**
06641   * @brief  Get flag multimode ADC group regular overrun of the ADC slave.
06642   * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR
06643   * @param  ADCxy_COMMON ADC common instance
06644   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06645   * @retval State of bit (1 or 0).
06646   */
06647 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
06648 {
06649   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV));
06650 }
06651
06652 /**
06653   * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.
06654   * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP
06655   * @param  ADCxy_COMMON ADC common instance
06656   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06657   * @retval State of bit (1 or 0).
06658   */
06659 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
06660 {
06661   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST));
06662 }
06663
06664 /**
06665   * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.
06666   * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP
06667   * @param  ADCxy_COMMON ADC common instance
06668   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06669   * @retval State of bit (1 or 0).
06670   */
06671 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
06672 {
06673   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV));
06674 }
06675
06676 /**
06677   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.
06678   * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC
06679   * @param  ADCxy_COMMON ADC common instance
06680   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06681   * @retval State of bit (1 or 0).
06682   */
06683 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
06684 {
06685   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST));
06686 }
06687
06688 /**
06689   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
06690   * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC
06691   * @param  ADCxy_COMMON ADC common instance
06692   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06693   * @retval State of bit (1 or 0).
06694   */
06695 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
06696 {
06697   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV));
06698 }
06699
06700 /**
06701   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
06702   * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS
06703   * @param  ADCxy_COMMON ADC common instance
06704   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06705   * @retval State of bit (1 or 0).
06706   */
06707 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
06708 {
06709   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST));
06710 }
06711
06712 /**
06713   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
06714   * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS
06715   * @param  ADCxy_COMMON ADC common instance
06716   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06717   * @retval State of bit (1 or 0).
06718   */
06719 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
06720 {
06721   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
06722 }
06723
06724 /**
06725   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.
06726   * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF
06727   * @param  ADCxy_COMMON ADC common instance
06728   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06729   * @retval State of bit (1 or 0).
06730   */
06731 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
06732 {
06733   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST));
06734 }
06735
06736 /**
06737   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.
06738   * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF
06739   * @param  ADCxy_COMMON ADC common instance
06740   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06741   * @retval State of bit (1 or 0).
06742   */
06743 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
06744 {
06745   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV));
06746 }
06747
06748 /**
06749   * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
06750   * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1
06751   * @param  ADCxy_COMMON ADC common instance
06752   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06753   * @retval State of bit (1 or 0).
06754   */
06755 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
06756 {
06757   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
06758 }
06759
06760 /**
06761   * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
06762   * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1
06763   * @param  ADCxy_COMMON ADC common instance
06764   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06765   * @retval State of bit (1 or 0).
06766   */
06767 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
06768 {
06769   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV));
06770 }
06771
06772 /**
06773   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.
06774   * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2
06775   * @param  ADCxy_COMMON ADC common instance
06776   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06777   * @retval State of bit (1 or 0).
06778   */
06779 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
06780 {
06781   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST));
06782 }
06783
06784 /**
06785   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.
06786   * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2
06787   * @param  ADCxy_COMMON ADC common instance
06788   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06789   * @retval State of bit (1 or 0).
06790   */
06791 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
06792 {
06793   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV));
06794 }
06795
06796 /**
06797   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.
06798   * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3
06799   * @param  ADCxy_COMMON ADC common instance
06800   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06801   * @retval State of bit (1 or 0).
06802   */
06803 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
06804 {
06805   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST));
06806 }
06807
06808 /**
06809   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.
06810   * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3
06811   * @param  ADCxy_COMMON ADC common instance
06812   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06813   * @retval State of bit (1 or 0).
06814   */
06815 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
06816 {
06817   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV));
06818 }
06819 #endif /* ADC_MULTIMODE_SUPPORT */
06820
06821 /**
06822   * @}
06823   */
06824
06825 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
06826   * @{
06827   */
06828
06829 /**
06830   * @brief  Enable ADC ready.
06831   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
06832   * @param  ADCx ADC instance
06833   * @retval None
06834   */
06835 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
06836 {
06837   SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
06838 }
06839
06840 /**
06841   * @brief  Enable interruption ADC group regular end of unitary conversion.
06842   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
06843   * @param  ADCx ADC instance
06844   * @retval None
06845   */
06846 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
06847 {
06848   SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
06849 }
06850
06851 /**
06852   * @brief  Enable interruption ADC group regular end of sequence conversions.
06853   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
06854   * @param  ADCx ADC instance
06855   * @retval None
06856   */
06857 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
06858 {
06859   SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
06860 }
06861
06862 /**
06863   * @brief  Enable ADC group regular interruption overrun.
06864   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
06865   * @param  ADCx ADC instance
06866   * @retval None
06867   */
06868 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
06869 {
06870   SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
06871 }
06872
06873 /**
06874   * @brief  Enable interruption ADC group regular end of sampling.
06875   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
06876   * @param  ADCx ADC instance
06877   * @retval None
06878   */
06879 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
06880 {
06881   SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
06882 }
06883
06884 /**
06885   * @brief  Enable interruption ADC group injected end of unitary conversion.
06886   * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
06887   * @param  ADCx ADC instance
06888   * @retval None
06889   */
06890 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
06891 {
06892   SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
06893 }
06894
06895 /**
06896   * @brief  Enable interruption ADC group injected end of sequence conversions.
06897   * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
06898   * @param  ADCx ADC instance
06899   * @retval None
06900   */
06901 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
06902 {
06903   SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
06904 }
06905
06906 /**
06907   * @brief  Enable interruption ADC group injected context queue overflow.
06908   * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF
06909   * @param  ADCx ADC instance
06910   * @retval None
06911   */
06912 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
06913 {
06914   SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
06915 }
06916
06917 /**
06918   * @brief  Enable interruption ADC analog watchdog 1.
06919   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
06920   * @param  ADCx ADC instance
06921   * @retval None
06922   */
06923 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
06924 {
06925   SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
06926 }
06927
06928 /**
06929   * @brief  Enable interruption ADC analog watchdog 2.
06930   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
06931   * @param  ADCx ADC instance
06932   * @retval None
06933   */
06934 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
06935 {
06936   SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
06937 }
06938
06939 /**
06940   * @brief  Enable interruption ADC analog watchdog 3.
06941   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
06942   * @param  ADCx ADC instance
06943   * @retval None
06944   */
06945 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
06946 {
06947   SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
06948 }
06949
06950 /**
06951   * @brief  Disable interruption ADC ready.
06952   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
06953   * @param  ADCx ADC instance
06954   * @retval None
06955   */
06956 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
06957 {
06958   CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
06959 }
06960
06961 /**
06962   * @brief  Disable interruption ADC group regular end of unitary conversion.
06963   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
06964   * @param  ADCx ADC instance
06965   * @retval None
06966   */
06967 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
06968 {
06969   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
06970 }
06971
06972 /**
06973   * @brief  Disable interruption ADC group regular end of sequence conversions.
06974   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
06975   * @param  ADCx ADC instance
06976   * @retval None
06977   */
06978 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
06979 {
06980   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
06981 }
06982
06983 /**
06984   * @brief  Disable interruption ADC group regular overrun.
06985   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
06986   * @param  ADCx ADC instance
06987   * @retval None
06988   */
06989 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
06990 {
06991   CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
06992 }
06993
06994 /**
06995   * @brief  Disable interruption ADC group regular end of sampling.
06996   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
06997   * @param  ADCx ADC instance
06998   * @retval None
06999   */
07000 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
07001 {
07002   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
07003 }
07004
07005 /**
07006   * @brief  Disable interruption ADC group regular end of unitary conversion.
07007   * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
07008   * @param  ADCx ADC instance
07009   * @retval None
07010   */
07011 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
07012 {
07013   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
07014 }
07015
07016 /**
07017   * @brief  Disable interruption ADC group injected end of sequence conversions.
07018   * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
07019   * @param  ADCx ADC instance
07020   * @retval None
07021   */
07022 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
07023 {
07024   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
07025 }
07026
07027 /**
07028   * @brief  Disable interruption ADC group injected context queue overflow.
07029   * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF
07030   * @param  ADCx ADC instance
07031   * @retval None
07032   */
07033 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
07034 {
07035   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
07036 }
07037
07038 /**
07039   * @brief  Disable interruption ADC analog watchdog 1.
07040   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
07041   * @param  ADCx ADC instance
07042   * @retval None
07043   */
07044 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
07045 {
07046   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
07047 }
07048
07049 /**
07050   * @brief  Disable interruption ADC analog watchdog 2.
07051   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
07052   * @param  ADCx ADC instance
07053   * @retval None
07054   */
07055 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
07056 {
07057   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
07058 }
07059
07060 /**
07061   * @brief  Disable interruption ADC analog watchdog 3.
07062   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
07063   * @param  ADCx ADC instance
07064   * @retval None
07065   */
07066 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
07067 {
07068   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
07069 }
07070
07071 /**
07072   * @brief  Get state of interruption ADC ready
07073   *         (0: interrupt disabled, 1: interrupt enabled).
07074   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
07075   * @param  ADCx ADC instance
07076   * @retval State of bit (1 or 0).
07077   */
07078 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
07079 {
07080   return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
07081 }
07082
07083 /**
07084   * @brief  Get state of interruption ADC group regular end of unitary conversion
07085   *         (0: interrupt disabled, 1: interrupt enabled).
07086   * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
07087   * @param  ADCx ADC instance
07088   * @retval State of bit (1 or 0).
07089   */
07090 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
07091 {
07092   return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
07093 }
07094
07095 /**
07096   * @brief  Get state of interruption ADC group regular end of sequence conversions
07097   *         (0: interrupt disabled, 1: interrupt enabled).
07098   * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
07099   * @param  ADCx ADC instance
07100   * @retval State of bit (1 or 0).
07101   */
07102 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
07103 {
07104   return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
07105 }
07106
07107 /**
07108   * @brief  Get state of interruption ADC group regular overrun
07109   *         (0: interrupt disabled, 1: interrupt enabled).
07110   * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
07111   * @param  ADCx ADC instance
07112   * @retval State of bit (1 or 0).
07113   */
07114 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
07115 {
07116   return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
07117 }
07118
07119 /**
07120   * @brief  Get state of interruption ADC group regular end of sampling
07121   *         (0: interrupt disabled, 1: interrupt enabled).
07122   * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
07123   * @param  ADCx ADC instance
07124   * @retval State of bit (1 or 0).
07125   */
07126 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
07127 {
07128   return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
07129 }
07130
07131 /**
07132   * @brief  Get state of interruption ADC group injected end of unitary conversion
07133   *         (0: interrupt disabled, 1: interrupt enabled).
07134   * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC
07135   * @param  ADCx ADC instance
07136   * @retval State of bit (1 or 0).
07137   */
07138 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
07139 {
07140   return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC));
07141 }
07142
07143 /**
07144   * @brief  Get state of interruption ADC group injected end of sequence conversions
07145   *         (0: interrupt disabled, 1: interrupt enabled).
07146   * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS
07147   * @param  ADCx ADC instance
07148   * @retval State of bit (1 or 0).
07149   */
07150 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
07151 {
07152   return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
07153 }
07154
07155 /**
07156   * @brief  Get state of interruption ADC group injected context queue overflow interrupt state
07157   *         (0: interrupt disabled, 1: interrupt enabled).
07158   * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF
07159   * @param  ADCx ADC instance
07160   * @retval State of bit (1 or 0).
07161   */
07162 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
07163 {
07164   return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF));
07165 }
07166
07167 /**
07168   * @brief  Get state of interruption ADC analog watchdog 1
07169   *         (0: interrupt disabled, 1: interrupt enabled).
07170   * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
07171   * @param  ADCx ADC instance
07172   * @retval State of bit (1 or 0).
07173   */
07174 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
07175 {
07176   return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
07177 }
07178
07179 /**
07180   * @brief  Get state of interruption Get ADC analog watchdog 2
07181   *         (0: interrupt disabled, 1: interrupt enabled).
07182   * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
07183   * @param  ADCx ADC instance
07184   * @retval State of bit (1 or 0).
07185   */
07186 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
07187 {
07188   return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2));
07189 }
07190
07191 /**
07192   * @brief  Get state of interruption Get ADC analog watchdog 3
07193   *         (0: interrupt disabled, 1: interrupt enabled).
07194   * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
07195   * @param  ADCx ADC instance
07196   * @retval State of bit (1 or 0).
07197   */
07198 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
07199 {
07200   return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3));
07201 }
07202
07203 /**
07204   * @}
07205   */
07206
07207 #if defined(USE_FULL_LL_DRIVER)
07208 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
07209   * @{
07210   */
07211
07212 /* Initialization of some features of ADC common parameters and multimode */
07213 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
07214 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
07215 void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
07216
07217 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
07218 /* (availability of ADC group injected depends on STM32 families) */
07219 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
07220
07221 /* Initialization of some features of ADC instance */
07222 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
07223 void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
07224
07225 /* Initialization of some features of ADC instance and ADC group regular */
07226 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
07227 void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
07228
07229 /* Initialization of some features of ADC instance and ADC group injected */
07230 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
07231 void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
07232
07233 /**
07234   * @}
07235   */
07236 #endif /* USE_FULL_LL_DRIVER */
07237
07238 /**
07239   * @}
07240   */
07241
07242 /**
07243   * @}
07244   */
07245
07246 #endif /* ADC1 || ADC2 || ADC3 */
07247
07248 /**
07249   * @}
07250   */
07251
07252 #ifdef __cplusplus
07253 }
07254 #endif
07255
07256 #endif /* __STM32L4xx_LL_ADC_H */
07257
07258 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_bus.h Source File

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stm32l4xx_ll_bus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_bus.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of BUS LL module.
00008
00009   @verbatim
00010                       ##### RCC Limitations #####
00011   ==============================================================================
00012     [..]
00013       A delay between an RCC peripheral clock enable and the effective peripheral
00014       enabling should be taken into account in order to manage the peripheral read/write
00015       from/to registers.
00016       (+) This delay depends on the peripheral mapping.
00017         (++) AHB & APB peripherals, 1 dummy read is necessary
00018
00019     [..]
00020       Workarounds:
00021       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
00022           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
00023
00024   @endverbatim
00025   ******************************************************************************
00026   * @attention
00027   *
00028   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00029   *
00030   * Redistribution and use in source and binary forms, with or without modification,
00031   * are permitted provided that the following conditions are met:
00032   *   1. Redistributions of source code must retain the above copyright notice,
00033   *      this list of conditions and the following disclaimer.
00034   *   2. Redistributions in binary form must reproduce the above copyright notice,
00035   *      this list of conditions and the following disclaimer in the documentation
00036   *      and/or other materials provided with the distribution.
00037   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00038   *      may be used to endorse or promote products derived from this software
00039   *      without specific prior written permission.
00040   *
00041   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00042   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00043   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00044   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00045   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00046   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00047   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00048   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00049   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00050   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00051   *
00052   ******************************************************************************
00053   */
00054
00055 /* Define to prevent recursive inclusion -------------------------------------*/
00056 #ifndef __STM32L4xx_LL_BUS_H
00057 #define __STM32L4xx_LL_BUS_H
00058
00059 #ifdef __cplusplus
00060 extern "C" {
00061 #endif
00062
00063 /* Includes ------------------------------------------------------------------*/
00064 #include "stm32l4xx.h"
00065
00066 /** @addtogroup STM32L4xx_LL_Driver
00067   * @{
00068   */
00069
00070 #if defined(RCC)
00071
00072 /** @defgroup BUS_LL BUS
00073   * @{
00074   */
00075
00076 /* Private types -------------------------------------------------------------*/
00077 /* Private variables ---------------------------------------------------------*/
00078
00079 /* Private constants ---------------------------------------------------------*/
00080
00081 /* Private macros ------------------------------------------------------------*/
00082
00083 /* Exported types ------------------------------------------------------------*/
00084 /* Exported constants --------------------------------------------------------*/
00085 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
00086   * @{
00087   */
00088
00089 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
00090   * @{
00091   */
00092 #define LL_AHB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00093 #define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN
00094 #define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN
00095 #define LL_AHB1_GRP1_PERIPH_FLASH          RCC_AHB1ENR_FLASHEN
00096 #define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN
00097 #define LL_AHB1_GRP1_PERIPH_TSC            RCC_AHB1ENR_TSCEN
00098 #define LL_AHB1_GRP1_PERIPH_SRAM1          RCC_AHB1SMENR_SRAM1SMEN
00099 /**
00100   * @}
00101   */
00102
00103 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
00104   * @{
00105   */
00106 #define LL_AHB2_GRP1_PERIPH_SRAM2          RCC_AHB2SMENR_SRAM2SMEN
00107 #define LL_AHB2_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00108 #define LL_AHB2_GRP1_PERIPH_GPIOA          RCC_AHB2ENR_GPIOAEN
00109 #define LL_AHB2_GRP1_PERIPH_GPIOB          RCC_AHB2ENR_GPIOBEN
00110 #define LL_AHB2_GRP1_PERIPH_GPIOC          RCC_AHB2ENR_GPIOCEN
00111 #if defined(GPIOD)
00112 #define LL_AHB2_GRP1_PERIPH_GPIOD          RCC_AHB2ENR_GPIODEN
00113 #endif /*GPIOD*/
00114 #if defined(GPIOE)
00115 #define LL_AHB2_GRP1_PERIPH_GPIOE          RCC_AHB2ENR_GPIOEEN
00116 #endif /*GPIOE*/
00117 #if defined(GPIOF)
00118 #define LL_AHB2_GRP1_PERIPH_GPIOF          RCC_AHB2ENR_GPIOFEN
00119 #endif /* GPIOF */
00120 #if defined(GPIOG)
00121 #define LL_AHB2_GRP1_PERIPH_GPIOG          RCC_AHB2ENR_GPIOGEN
00122 #endif /* GPIOG */
00123 #define LL_AHB2_GRP1_PERIPH_GPIOH          RCC_AHB2ENR_GPIOHEN
00124 #if defined(USB_OTG_FS)
00125 #define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
00126 #endif /* USB_OTG_FS */
00127 #define LL_AHB2_GRP1_PERIPH_ADC            RCC_AHB2ENR_ADCEN
00128 #if defined(AES)
00129 #define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
00130 #endif /* AES */
00131 #define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
00137   * @{
00138   */
00139 #define LL_AHB3_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00140 #if defined(FMC_Bank1_R)
00141 #define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
00142 #endif /* FMC_Bank1_R */
00143 #define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
00149   * @{
00150   */
00151 #define LL_APB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00152 #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR1_TIM2EN
00153 #if defined(TIM3)
00154 #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR1_TIM3EN
00155 #endif /* TIM3 */
00156 #if defined(TIM4)
00157 #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR1_TIM4EN
00158 #endif /* TIM4 */
00159 #if defined(TIM5)
00160 #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR1_TIM5EN
00161 #endif /* TIM5 */
00162 #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR1_TIM6EN
00163 #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR1_TIM7EN
00164 #if defined(LCD)
00165 #define LL_APB1_GRP1_PERIPH_LCD            RCC_APB1ENR1_LCDEN
00166 #endif /* LCD */
00167 #if defined(RCC_APB1ENR1_RTCAPBEN)
00168 #define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR1_RTCAPBEN
00169 #endif /* RCC_APB1ENR1_RTCAPBEN */
00170 #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR1_WWDGEN
00171 #if defined(SPI2)
00172 #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR1_SPI2EN
00173 #endif /* SPI2 */
00174 #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR1_SPI3EN
00175 #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR1_USART2EN
00176 #if defined(USART3)
00177 #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR1_USART3EN
00178 #endif /* USART3 */
00179 #if defined(UART4)
00180 #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR1_UART4EN
00181 #endif /* UART4 */
00182 #if defined(UART5)
00183 #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR1_UART5EN
00184 #endif /* UART5 */
00185 #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR1_I2C1EN
00186 #if defined(I2C2)
00187 #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR1_I2C2EN
00188 #endif /* I2C2 */
00189 #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR1_I2C3EN
00190 #if defined(CRS)
00191 #define LL_APB1_GRP1_PERIPH_CRS            RCC_APB1ENR1_CRSEN
00192 #endif /* CRS */
00193 #define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR1_CAN1EN
00194 #if defined(USB)
00195 #define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR1_USBFSEN
00196 #endif /* USB */
00197 #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR1_PWREN
00198 #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR1_DAC1EN
00199 #define LL_APB1_GRP1_PERIPH_OPAMP          RCC_APB1ENR1_OPAMPEN
00200 #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR1_LPTIM1EN
00201 /**
00202   * @}
00203   */
00204
00205
00206 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
00207   * @{
00208   */
00209 #define LL_APB1_GRP2_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00210 #define LL_APB1_GRP2_PERIPH_LPUART1        RCC_APB1ENR2_LPUART1EN
00211 #define LL_APB1_GRP2_PERIPH_SWPMI1         RCC_APB1ENR2_SWPMI1EN
00212 #define LL_APB1_GRP2_PERIPH_LPTIM2         RCC_APB1ENR2_LPTIM2EN
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
00218   * @{
00219   */
00220 #define LL_APB2_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00221 #define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN
00222 #define LL_APB2_GRP1_PERIPH_FW             RCC_APB2ENR_FWEN
00223 #if defined(SDMMC1)
00224 #define LL_APB2_GRP1_PERIPH_SDMMC1         RCC_APB2ENR_SDMMC1EN
00225 #endif /* SDMMC1 */
00226 #define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
00227 #define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
00228 #if defined(TIM8)
00229 #define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
00230 #endif /* TIM8 */
00231 #define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
00232 #define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
00233 #define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
00234 #if defined(TIM17)
00235 #define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
00236 #endif /* TIM17 */
00237 #define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
00238 #if defined(SAI2)
00239 #define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN
00240 #endif /* SAI2 */
00241 #if defined(DFSDM1_Channel0)
00242 #define LL_APB2_GRP1_PERIPH_DFSDM1         RCC_APB2ENR_DFSDM1EN
00243 #endif /* DFSDM1_Channel0 */
00244 /**
00245   * @}
00246   */
00247
00248 /** Legacy definitions for compatibility purpose
00249 @cond 0
00250 */
00251 #if defined(DFSDM1_Channel0)
00252 #define LL_APB2_GRP1_PERIPH_DFSDM          LL_APB2_GRP1_PERIPH_DFSDM1
00253 #endif /* DFSDM1_Channel0 */
00254 /**
00255 @endcond
00256   */
00257
00258 /**
00259   * @}
00260   */
00261
00262 /* Exported macro ------------------------------------------------------------*/
00263 /* Exported functions --------------------------------------------------------*/
00264 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
00265   * @{
00266   */
00267
00268 /** @defgroup BUS_LL_EF_AHB1 AHB1
00269   * @{
00270   */
00271
00272 /**
00273   * @brief  Enable AHB1 peripherals clock.
00274   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n
00275   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
00276   *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_EnableClock\n
00277   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_EnableClock\n
00278   *         AHB1ENR      TSCEN         LL_AHB1_GRP1_EnableClock
00279   * @param  Periphs This parameter can be a combination of the following values:
00280   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00281   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00282   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00283   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00284   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00285   *
00286   * @retval None
00287 */
00288 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
00289 {
00290   __IO uint32_t tmpreg;
00291   SET_BIT(RCC->AHB1ENR, Periphs);
00292   /* Delay after an RCC peripheral clock enabling */
00293   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
00294   (void)tmpreg;
00295 }
00296
00297 /**
00298   * @brief  Check if AHB1 peripheral clock is enabled or not
00299   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
00300   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
00301   *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_IsEnabledClock\n
00302   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\n
00303   *         AHB1ENR      TSCEN         LL_AHB1_GRP1_IsEnabledClock
00304   * @param  Periphs This parameter can be a combination of the following values:
00305   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00306   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00307   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00308   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00309   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00310   *
00311   * @retval State of Periphs (1 or 0).
00312 */
00313 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
00314 {
00315   return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
00316 }
00317
00318 /**
00319   * @brief  Disable AHB1 peripherals clock.
00320   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n
00321   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
00322   *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_DisableClock\n
00323   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_DisableClock\n
00324   *         AHB1ENR      TSCEN         LL_AHB1_GRP1_DisableClock
00325   * @param  Periphs This parameter can be a combination of the following values:
00326   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00327   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00328   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00329   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00330   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00331   *
00332   * @retval None
00333 */
00334 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
00335 {
00336   CLEAR_BIT(RCC->AHB1ENR, Periphs);
00337 }
00338
00339 /**
00340   * @brief  Force AHB1 peripherals reset.
00341   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
00342   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
00343   *         AHB1RSTR     FLASHRST      LL_AHB1_GRP1_ForceReset\n
00344   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
00345   *         AHB1RSTR     TSCRST        LL_AHB1_GRP1_ForceReset
00346   * @param  Periphs This parameter can be a combination of the following values:
00347   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00348   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00349   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00350   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00351   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00352   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00353   *
00354   * @retval None
00355 */
00356 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
00357 {
00358   SET_BIT(RCC->AHB1RSTR, Periphs);
00359 }
00360
00361 /**
00362   * @brief  Release AHB1 peripherals reset.
00363   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
00364   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
00365   *         AHB1RSTR     FLASHRST      LL_AHB1_GRP1_ReleaseReset\n
00366   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
00367   *         AHB1RSTR     TSCRST        LL_AHB1_GRP1_ReleaseReset
00368   * @param  Periphs This parameter can be a combination of the following values:
00369   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00370   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00371   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00372   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00373   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00374   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00375   *
00376   * @retval None
00377 */
00378 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
00379 {
00380   CLEAR_BIT(RCC->AHB1RSTR, Periphs);
00381 }
00382
00383 /**
00384   * @brief  Enable AHB1 peripheral clocks in Sleep and Stop modes
00385   * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
00386   *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
00387   *         AHB1SMENR    FLASHSMEN     LL_AHB1_GRP1_EnableClockStopSleep\n
00388   *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_EnableClockStopSleep\n
00389   *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_EnableClockStopSleep\n
00390   *         AHB1SMENR    TSCSMEN       LL_AHB1_GRP1_EnableClockStopSleep
00391   * @param  Periphs This parameter can be a combination of the following values:
00392   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00393   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00394   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00395   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
00396   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00397   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00398   *
00399   * @retval None
00400 */
00401 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
00402 {
00403   __IO uint32_t tmpreg;
00404   SET_BIT(RCC->AHB1SMENR, Periphs);
00405   /* Delay after an RCC peripheral clock enabling */
00406   tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
00407   (void)tmpreg;
00408 }
00409
00410 /**
00411   * @brief  Disable AHB1 peripheral clocks in Sleep and Stop modes
00412   * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
00413   *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
00414   *         AHB1SMENR    FLASHSMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
00415   *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
00416   *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_DisableClockStopSleep\n
00417   *         AHB1SMENR    TSCSMEN       LL_AHB1_GRP1_DisableClockStopSleep
00418   * @param  Periphs This parameter can be a combination of the following values:
00419   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00420   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00421   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00422   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
00423   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00424   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00425   *
00426   * @retval None
00427 */
00428 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
00429 {
00430   CLEAR_BIT(RCC->AHB1SMENR, Periphs);
00431 }
00432
00433 /**
00434   * @}
00435   */
00436
00437 /** @defgroup BUS_LL_EF_AHB2 AHB2
00438   * @{
00439   */
00440
00441 /**
00442   * @brief  Enable AHB2 peripherals clock.
00443   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_EnableClock\n
00444   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_EnableClock\n
00445   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_EnableClock\n
00446   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_EnableClock\n
00447   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_EnableClock\n
00448   *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_EnableClock\n
00449   *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_EnableClock\n
00450   *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_EnableClock\n
00451   *         AHB2ENR      OTGFSEN       LL_AHB2_GRP1_EnableClock\n
00452   *         AHB2ENR      ADCEN         LL_AHB2_GRP1_EnableClock\n
00453   *         AHB2ENR      AESEN         LL_AHB2_GRP1_EnableClock\n
00454   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock
00455   * @param  Periphs This parameter can be a combination of the following values:
00456   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00457   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00458   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00459   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
00460   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
00461   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
00462   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
00463   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00464   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
00465   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00466   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00467   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00468   *
00469   *         (*) value not defined in all devices.
00470   * @retval None
00471 */
00472 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
00473 {
00474   __IO uint32_t tmpreg;
00475   SET_BIT(RCC->AHB2ENR, Periphs);
00476   /* Delay after an RCC peripheral clock enabling */
00477   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
00478   (void)tmpreg;
00479 }
00480
00481 /**
00482   * @brief  Check if AHB2 peripheral clock is enabled or not
00483   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_IsEnabledClock\n
00484   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_IsEnabledClock\n
00485   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_IsEnabledClock\n
00486   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_IsEnabledClock\n
00487   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_IsEnabledClock\n
00488   *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_IsEnabledClock\n
00489   *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_IsEnabledClock\n
00490   *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_IsEnabledClock\n
00491   *         AHB2ENR      OTGFSEN       LL_AHB2_GRP1_IsEnabledClock\n
00492   *         AHB2ENR      ADCEN         LL_AHB2_GRP1_IsEnabledClock\n
00493   *         AHB2ENR      AESEN         LL_AHB2_GRP1_IsEnabledClock\n
00494   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock
00495   * @param  Periphs This parameter can be a combination of the following values:
00496   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00497   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00498   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00499   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
00500   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
00501   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
00502   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
00503   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00504   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
00505   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00506   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00507   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00508   *
00509   *         (*) value not defined in all devices.
00510   * @retval State of Periphs (1 or 0).
00511 */
00512 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
00513 {
00514   return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
00515 }
00516
00517 /**
00518   * @brief  Disable AHB2 peripherals clock.
00519   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_DisableClock\n
00520   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_DisableClock\n
00521   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_DisableClock\n
00522   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_DisableClock\n
00523   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_DisableClock\n
00524   *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_DisableClock\n
00525   *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_DisableClock\n
00526   *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_DisableClock\n
00527   *         AHB2ENR      OTGFSEN       LL_AHB2_GRP1_DisableClock\n
00528   *         AHB2ENR      ADCEN         LL_AHB2_GRP1_DisableClock\n
00529   *         AHB2ENR      AESEN         LL_AHB2_GRP1_DisableClock\n
00530   *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock
00531   * @param  Periphs This parameter can be a combination of the following values:
00532   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00533   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00534   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00535   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
00536   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
00537   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
00538   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
00539   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00540   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
00541   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00542   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00543   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00544   *
00545   *         (*) value not defined in all devices.
00546   * @retval None
00547 */
00548 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
00549 {
00550   CLEAR_BIT(RCC->AHB2ENR, Periphs);
00551 }
00552
00553 /**
00554   * @brief  Force AHB2 peripherals reset.
00555   * @rmtoll AHB2RSTR     GPIOARST      LL_AHB2_GRP1_ForceReset\n
00556   *         AHB2RSTR     GPIOBRST      LL_AHB2_GRP1_ForceReset\n
00557   *         AHB2RSTR     GPIOCRST      LL_AHB2_GRP1_ForceReset\n
00558   *         AHB2RSTR     GPIODRST      LL_AHB2_GRP1_ForceReset\n
00559   *         AHB2RSTR     GPIOERST      LL_AHB2_GRP1_ForceReset\n
00560   *         AHB2RSTR     GPIOFRST      LL_AHB2_GRP1_ForceReset\n
00561   *         AHB2RSTR     GPIOGRST      LL_AHB2_GRP1_ForceReset\n
00562   *         AHB2RSTR     GPIOHRST      LL_AHB2_GRP1_ForceReset\n
00563   *         AHB2RSTR     OTGFSRST      LL_AHB2_GRP1_ForceReset\n
00564   *         AHB2RSTR     ADCRST        LL_AHB2_GRP1_ForceReset\n
00565   *         AHB2RSTR     AESRST        LL_AHB2_GRP1_ForceReset\n
00566   *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset
00567   * @param  Periphs This parameter can be a combination of the following values:
00568   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
00569   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00570   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00571   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00572   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
00573   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
00574   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
00575   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
00576   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00577   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
00578   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00579   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00580   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00581   *
00582   *         (*) value not defined in all devices.
00583   * @retval None
00584 */
00585 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
00586 {
00587   SET_BIT(RCC->AHB2RSTR, Periphs);
00588 }
00589
00590 /**
00591   * @brief  Release AHB2 peripherals reset.
00592   * @rmtoll AHB2RSTR     GPIOARST      LL_AHB2_GRP1_ReleaseReset\n
00593   *         AHB2RSTR     GPIOBRST      LL_AHB2_GRP1_ReleaseReset\n
00594   *         AHB2RSTR     GPIOCRST      LL_AHB2_GRP1_ReleaseReset\n
00595   *         AHB2RSTR     GPIODRST      LL_AHB2_GRP1_ReleaseReset\n
00596   *         AHB2RSTR     GPIOERST      LL_AHB2_GRP1_ReleaseReset\n
00597   *         AHB2RSTR     GPIOFRST      LL_AHB2_GRP1_ReleaseReset\n
00598   *         AHB2RSTR     GPIOGRST      LL_AHB2_GRP1_ReleaseReset\n
00599   *         AHB2RSTR     GPIOHRST      LL_AHB2_GRP1_ReleaseReset\n
00600   *         AHB2RSTR     OTGFSRST      LL_AHB2_GRP1_ReleaseReset\n
00601   *         AHB2RSTR     ADCRST        LL_AHB2_GRP1_ReleaseReset\n
00602   *         AHB2RSTR     AESRST        LL_AHB2_GRP1_ReleaseReset\n
00603   *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset
00604   * @param  Periphs This parameter can be a combination of the following values:
00605   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
00606   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00607   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00608   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00609   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
00610   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
00611   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
00612   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
00613   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00614   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
00615   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00616   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00617   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00618   *
00619   *         (*) value not defined in all devices.
00620   * @retval None
00621 */
00622 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
00623 {
00624   CLEAR_BIT(RCC->AHB2RSTR, Periphs);
00625 }
00626
00627 /**
00628   * @brief  Enable AHB2 peripheral clocks in Sleep and Stop modes
00629   * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00630   *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00631   *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00632   *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00633   *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00634   *         AHB2SMENR    GPIOFSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00635   *         AHB2SMENR    GPIOGSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00636   *         AHB2SMENR    GPIOHSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00637   *         AHB2SMENR    SRAM2SMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00638   *         AHB2SMENR    OTGFSSMEN     LL_AHB2_GRP1_EnableClockStopSleep\n
00639   *         AHB2SMENR    ADCSMEN       LL_AHB2_GRP1_EnableClockStopSleep\n
00640   *         AHB2SMENR    AESSMEN       LL_AHB2_GRP1_EnableClockStopSleep\n
00641   *         AHB2SMENR    RNGSMEN       LL_AHB2_GRP1_EnableClockStopSleep
00642   * @param  Periphs This parameter can be a combination of the following values:
00643   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00644   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00645   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00646   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
00647   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
00648   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
00649   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
00650   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00651   *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
00652   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
00653   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00654   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00655   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00656   *
00657   *         (*) value not defined in all devices.
00658   * @retval None
00659 */
00660 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
00661 {
00662   __IO uint32_t tmpreg;
00663   SET_BIT(RCC->AHB2SMENR, Periphs);
00664   /* Delay after an RCC peripheral clock enabling */
00665   tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
00666   (void)tmpreg;
00667 }
00668
00669 /**
00670   * @brief  Disable AHB2 peripheral clocks in Sleep and Stop modes
00671   * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00672   *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00673   *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00674   *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00675   *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00676   *         AHB2SMENR    GPIOFSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00677   *         AHB2SMENR    GPIOGSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00678   *         AHB2SMENR    GPIOHSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00679   *         AHB2SMENR    SRAM2SMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00680   *         AHB2SMENR    OTGFSSMEN     LL_AHB2_GRP1_DisableClockStopSleep\n
00681   *         AHB2SMENR    ADCSMEN       LL_AHB2_GRP1_DisableClockStopSleep\n
00682   *         AHB2SMENR    AESSMEN       LL_AHB2_GRP1_DisableClockStopSleep\n
00683   *         AHB2SMENR    RNGSMEN       LL_AHB2_GRP1_DisableClockStopSleep
00684   * @param  Periphs This parameter can be a combination of the following values:
00685   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00686   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00687   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00688   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
00689   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
00690   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
00691   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
00692   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00693   *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
00694   *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
00695   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00696   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
00697   *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
00698   *
00699   *         (*) value not defined in all devices.
00700   * @retval None
00701 */
00702 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
00703 {
00704   CLEAR_BIT(RCC->AHB2SMENR, Periphs);
00705 }
00706
00707 /**
00708   * @}
00709   */
00710
00711 /** @defgroup BUS_LL_EF_AHB3 AHB3
00712   * @{
00713   */
00714
00715 /**
00716   * @brief  Enable AHB3 peripherals clock.
00717   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
00718   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
00719   * @param  Periphs This parameter can be a combination of the following values:
00720   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00721   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
00722   *
00723   *         (*) value not defined in all devices.
00724   * @retval None
00725 */
00726 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
00727 {
00728   __IO uint32_t tmpreg;
00729   SET_BIT(RCC->AHB3ENR, Periphs);
00730   /* Delay after an RCC peripheral clock enabling */
00731   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
00732   (void)tmpreg;
00733 }
00734
00735 /**
00736   * @brief  Check if AHB3 peripheral clock is enabled or not
00737   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
00738   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
00739   * @param  Periphs This parameter can be a combination of the following values:
00740   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00741   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
00742   *
00743   *         (*) value not defined in all devices.
00744   * @retval State of Periphs (1 or 0).
00745 */
00746 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
00747 {
00748   return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
00749 }
00750
00751 /**
00752   * @brief  Disable AHB3 peripherals clock.
00753   * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
00754   *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
00755   * @param  Periphs This parameter can be a combination of the following values:
00756   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00757   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
00758   *
00759   *         (*) value not defined in all devices.
00760   * @retval None
00761 */
00762 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
00763 {
00764   CLEAR_BIT(RCC->AHB3ENR, Periphs);
00765 }
00766
00767 /**
00768   * @brief  Force AHB3 peripherals reset.
00769   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
00770   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
00771   * @param  Periphs This parameter can be a combination of the following values:
00772   *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
00773   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00774   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
00775   *
00776   *         (*) value not defined in all devices.
00777   * @retval None
00778 */
00779 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
00780 {
00781   SET_BIT(RCC->AHB3RSTR, Periphs);
00782 }
00783
00784 /**
00785   * @brief  Release AHB3 peripherals reset.
00786   * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
00787   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
00788   * @param  Periphs This parameter can be a combination of the following values:
00789   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
00790   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00791   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
00792   *
00793   *         (*) value not defined in all devices.
00794   * @retval None
00795 */
00796 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
00797 {
00798   CLEAR_BIT(RCC->AHB3RSTR, Periphs);
00799 }
00800
00801 /**
00802   * @brief  Enable AHB3 peripheral clocks in Sleep and Stop modes
00803   * @rmtoll AHB3SMENR    FMCSMEN       LL_AHB3_GRP1_EnableClockStopSleep\n
00804   *         AHB3SMENR    QSPISMEN      LL_AHB3_GRP1_EnableClockStopSleep
00805   * @param  Periphs This parameter can be a combination of the following values:
00806   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00807   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
00808   *
00809   *         (*) value not defined in all devices.
00810   * @retval None
00811 */
00812 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
00813 {
00814   __IO uint32_t tmpreg;
00815   SET_BIT(RCC->AHB3SMENR, Periphs);
00816   /* Delay after an RCC peripheral clock enabling */
00817   tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
00818   (void)tmpreg;
00819 }
00820
00821 /**
00822   * @brief  Disable AHB3 peripheral clocks in Sleep and Stop modes
00823   * @rmtoll AHB3SMENR    FMCSMEN       LL_AHB3_GRP1_DisableClockStopSleep\n
00824   *         AHB3SMENR    QSPISMEN      LL_AHB3_GRP1_DisableClockStopSleep
00825   * @param  Periphs This parameter can be a combination of the following values:
00826   *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
00827   *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
00828   *
00829   *         (*) value not defined in all devices.
00830   * @retval None
00831 */
00832 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
00833 {
00834   CLEAR_BIT(RCC->AHB3SMENR, Periphs);
00835 }
00836
00837 /**
00838   * @}
00839   */
00840
00841 /** @defgroup BUS_LL_EF_APB1 APB1
00842   * @{
00843   */
00844
00845 /**
00846   * @brief  Enable APB1 peripherals clock.
00847   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_EnableClock\n
00848   *         APB1ENR1     TIM3EN        LL_APB1_GRP1_EnableClock\n
00849   *         APB1ENR1     TIM4EN        LL_APB1_GRP1_EnableClock\n
00850   *         APB1ENR1     TIM5EN        LL_APB1_GRP1_EnableClock\n
00851   *         APB1ENR1     TIM6EN        LL_APB1_GRP1_EnableClock\n
00852   *         APB1ENR1     TIM7EN        LL_APB1_GRP1_EnableClock\n
00853   *         APB1ENR1     LCDEN         LL_APB1_GRP1_EnableClock\n
00854   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_EnableClock\n
00855   *         APB1ENR1     WWDGEN        LL_APB1_GRP1_EnableClock\n
00856   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_EnableClock\n
00857   *         APB1ENR1     SPI3EN        LL_APB1_GRP1_EnableClock\n
00858   *         APB1ENR1     USART2EN      LL_APB1_GRP1_EnableClock\n
00859   *         APB1ENR1     USART3EN      LL_APB1_GRP1_EnableClock\n
00860   *         APB1ENR1     UART4EN       LL_APB1_GRP1_EnableClock\n
00861   *         APB1ENR1     UART5EN       LL_APB1_GRP1_EnableClock\n
00862   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_EnableClock\n
00863   *         APB1ENR1     I2C2EN        LL_APB1_GRP1_EnableClock\n
00864   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_EnableClock\n
00865   *         APB1ENR1     CRSEN         LL_APB1_GRP1_EnableClock\n
00866   *         APB1ENR1     CAN1EN        LL_APB1_GRP1_EnableClock\n
00867   *         APB1ENR1     PWREN         LL_APB1_GRP1_EnableClock\n
00868   *         APB1ENR1     DAC1EN        LL_APB1_GRP1_EnableClock\n
00869   *         APB1ENR1     OPAMPEN       LL_APB1_GRP1_EnableClock\n
00870   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_EnableClock
00871   * @param  Periphs This parameter can be a combination of the following values:
00872   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00873   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
00874   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00875   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00876   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
00877   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
00878   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
00879   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
00880   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00881   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00882   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
00883   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00884   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
00885   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00886   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00887   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00888   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00889   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
00890   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
00891   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
00892   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00893   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00894   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
00895   *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
00896   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
00897   *
00898   *         (*) value not defined in all devices.
00899   * @retval None
00900 */
00901 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
00902 {
00903   __IO uint32_t tmpreg;
00904   SET_BIT(RCC->APB1ENR1, Periphs);
00905   /* Delay after an RCC peripheral clock enabling */
00906   tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
00907   (void)tmpreg;
00908 }
00909
00910 /**
00911   * @brief  Enable APB1 peripherals clock.
00912   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_EnableClock\n
00913   *         APB1ENR2     SWPMI1EN      LL_APB1_GRP2_EnableClock\n
00914   *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_EnableClock
00915   * @param  Periphs This parameter can be a combination of the following values:
00916   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
00917   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
00918   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
00919   * @retval None
00920 */
00921 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
00922 {
00923   __IO uint32_t tmpreg;
00924   SET_BIT(RCC->APB1ENR2, Periphs);
00925   /* Delay after an RCC peripheral clock enabling */
00926   tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
00927   (void)tmpreg;
00928 }
00929
00930 /**
00931   * @brief  Check if APB1 peripheral clock is enabled or not
00932   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
00933   *         APB1ENR1     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
00934   *         APB1ENR1     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
00935   *         APB1ENR1     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
00936   *         APB1ENR1     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
00937   *         APB1ENR1     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
00938   *         APB1ENR1     LCDEN         LL_APB1_GRP1_IsEnabledClock\n
00939   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\n
00940   *         APB1ENR1     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
00941   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
00942   *         APB1ENR1     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
00943   *         APB1ENR1     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
00944   *         APB1ENR1     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
00945   *         APB1ENR1     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
00946   *         APB1ENR1     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
00947   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
00948   *         APB1ENR1     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
00949   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
00950   *         APB1ENR1     CRSEN         LL_APB1_GRP1_IsEnabledClock\n
00951   *         APB1ENR1     CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
00952   *         APB1ENR1     PWREN         LL_APB1_GRP1_IsEnabledClock\n
00953   *         APB1ENR1     DAC1EN        LL_APB1_GRP1_IsEnabledClock\n
00954   *         APB1ENR1     OPAMPEN       LL_APB1_GRP1_IsEnabledClock\n
00955   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock
00956   * @param  Periphs This parameter can be a combination of the following values:
00957   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00958   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
00959   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00960   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00961   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
00962   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
00963   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
00964   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
00965   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00966   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00967   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
00968   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00969   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
00970   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00971   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00972   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00973   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00974   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
00975   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
00976   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
00977   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00978   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00979   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
00980   *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
00981   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
00982   *
00983   *         (*) value not defined in all devices.
00984   * @retval State of Periphs (1 or 0).
00985 */
00986 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
00987 {
00988   return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs);
00989 }
00990
00991 /**
00992   * @brief  Check if APB1 peripheral clock is enabled or not
00993   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_IsEnabledClock\n
00994   *         APB1ENR2     SWPMI1EN      LL_APB1_GRP2_IsEnabledClock\n
00995   *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_IsEnabledClock
00996   * @param  Periphs This parameter can be a combination of the following values:
00997   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
00998   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
00999   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01000   * @retval State of Periphs (1 or 0).
01001 */
01002 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
01003 {
01004   return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs);
01005 }
01006
01007 /**
01008   * @brief  Disable APB1 peripherals clock.
01009   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_DisableClock\n
01010   *         APB1ENR1     TIM3EN        LL_APB1_GRP1_DisableClock\n
01011   *         APB1ENR1     TIM4EN        LL_APB1_GRP1_DisableClock\n
01012   *         APB1ENR1     TIM5EN        LL_APB1_GRP1_DisableClock\n
01013   *         APB1ENR1     TIM6EN        LL_APB1_GRP1_DisableClock\n
01014   *         APB1ENR1     TIM7EN        LL_APB1_GRP1_DisableClock\n
01015   *         APB1ENR1     LCDEN         LL_APB1_GRP1_DisableClock\n
01016   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_DisableClock\n
01017   *         APB1ENR1     WWDGEN        LL_APB1_GRP1_DisableClock\n
01018   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_DisableClock\n
01019   *         APB1ENR1     SPI3EN        LL_APB1_GRP1_DisableClock\n
01020   *         APB1ENR1     USART2EN      LL_APB1_GRP1_DisableClock\n
01021   *         APB1ENR1     USART3EN      LL_APB1_GRP1_DisableClock\n
01022   *         APB1ENR1     UART4EN       LL_APB1_GRP1_DisableClock\n
01023   *         APB1ENR1     UART5EN       LL_APB1_GRP1_DisableClock\n
01024   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_DisableClock\n
01025   *         APB1ENR1     I2C2EN        LL_APB1_GRP1_DisableClock\n
01026   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_DisableClock\n
01027   *         APB1ENR1     CRSEN         LL_APB1_GRP1_DisableClock\n
01028   *         APB1ENR1     CAN1EN        LL_APB1_GRP1_DisableClock\n
01029   *         APB1ENR1     PWREN         LL_APB1_GRP1_DisableClock\n
01030   *         APB1ENR1     DAC1EN        LL_APB1_GRP1_DisableClock\n
01031   *         APB1ENR1     OPAMPEN       LL_APB1_GRP1_DisableClock\n
01032   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_DisableClock
01033   * @param  Periphs This parameter can be a combination of the following values:
01034   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01035   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
01036   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
01037   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
01038   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01039   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01040   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
01041   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
01042   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
01043   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
01044   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01045   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01046   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
01047   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
01048   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
01049   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01050   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
01051   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01052   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
01053   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
01054   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
01055   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
01056   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
01057   *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
01058   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01059   *
01060   *         (*) value not defined in all devices.
01061   * @retval None
01062 */
01063 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
01064 {
01065   CLEAR_BIT(RCC->APB1ENR1, Periphs);
01066 }
01067
01068 /**
01069   * @brief  Disable APB1 peripherals clock.
01070   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_DisableClock\n
01071   *         APB1ENR2     SWPMI1EN      LL_APB1_GRP2_DisableClock\n
01072   *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_DisableClock
01073   * @param  Periphs This parameter can be a combination of the following values:
01074   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01075   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
01076   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01077   * @retval None
01078 */
01079 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
01080 {
01081   CLEAR_BIT(RCC->APB1ENR2, Periphs);
01082 }
01083
01084 /**
01085   * @brief  Force APB1 peripherals reset.
01086   * @rmtoll APB1RSTR1    TIM2RST       LL_APB1_GRP1_ForceReset\n
01087   *         APB1RSTR1    TIM3RST       LL_APB1_GRP1_ForceReset\n
01088   *         APB1RSTR1    TIM4RST       LL_APB1_GRP1_ForceReset\n
01089   *         APB1RSTR1    TIM5RST       LL_APB1_GRP1_ForceReset\n
01090   *         APB1RSTR1    TIM6RST       LL_APB1_GRP1_ForceReset\n
01091   *         APB1RSTR1    TIM7RST       LL_APB1_GRP1_ForceReset\n
01092   *         APB1RSTR1    LCDRST        LL_APB1_GRP1_ForceReset\n
01093   *         APB1RSTR1    SPI2RST       LL_APB1_GRP1_ForceReset\n
01094   *         APB1RSTR1    SPI3RST       LL_APB1_GRP1_ForceReset\n
01095   *         APB1RSTR1    USART2RST     LL_APB1_GRP1_ForceReset\n
01096   *         APB1RSTR1    USART3RST     LL_APB1_GRP1_ForceReset\n
01097   *         APB1RSTR1    UART4RST      LL_APB1_GRP1_ForceReset\n
01098   *         APB1RSTR1    UART5RST      LL_APB1_GRP1_ForceReset\n
01099   *         APB1RSTR1    I2C1RST       LL_APB1_GRP1_ForceReset\n
01100   *         APB1RSTR1    I2C2RST       LL_APB1_GRP1_ForceReset\n
01101   *         APB1RSTR1    I2C3RST       LL_APB1_GRP1_ForceReset\n
01102   *         APB1RSTR1    CRSRST        LL_APB1_GRP1_ForceReset\n
01103   *         APB1RSTR1    CAN1RST       LL_APB1_GRP1_ForceReset\n
01104   *         APB1RSTR1    PWRRST        LL_APB1_GRP1_ForceReset\n
01105   *         APB1RSTR1    DAC1RST       LL_APB1_GRP1_ForceReset\n
01106   *         APB1RSTR1    OPAMPRST      LL_APB1_GRP1_ForceReset\n
01107   *         APB1RSTR1    LPTIM1RST     LL_APB1_GRP1_ForceReset
01108   * @param  Periphs This parameter can be a combination of the following values:
01109   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
01110   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01111   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
01112   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
01113   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
01114   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01115   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01116   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
01117   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
01118   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01119   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01120   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
01121   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
01122   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
01123   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01124   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
01125   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01126   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
01127   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
01128   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
01129   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
01130   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
01131   *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
01132   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01133   *
01134   *         (*) value not defined in all devices.
01135   * @retval None
01136 */
01137 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
01138 {
01139   SET_BIT(RCC->APB1RSTR1, Periphs);
01140 }
01141
01142 /**
01143   * @brief  Force APB1 peripherals reset.
01144   * @rmtoll APB1RSTR2    LPUART1RST    LL_APB1_GRP2_ForceReset\n
01145   *         APB1RSTR2    SWPMI1RST     LL_APB1_GRP2_ForceReset\n
01146   *         APB1RSTR2    LPTIM2RST     LL_APB1_GRP2_ForceReset
01147   * @param  Periphs This parameter can be a combination of the following values:
01148   *         @arg @ref LL_APB1_GRP2_PERIPH_ALL
01149   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01150   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
01151   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01152   * @retval None
01153 */
01154 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
01155 {
01156   SET_BIT(RCC->APB1RSTR2, Periphs);
01157 }
01158
01159 /**
01160   * @brief  Release APB1 peripherals reset.
01161   * @rmtoll APB1RSTR1    TIM2RST       LL_APB1_GRP1_ReleaseReset\n
01162   *         APB1RSTR1    TIM3RST       LL_APB1_GRP1_ReleaseReset\n
01163   *         APB1RSTR1    TIM4RST       LL_APB1_GRP1_ReleaseReset\n
01164   *         APB1RSTR1    TIM5RST       LL_APB1_GRP1_ReleaseReset\n
01165   *         APB1RSTR1    TIM6RST       LL_APB1_GRP1_ReleaseReset\n
01166   *         APB1RSTR1    TIM7RST       LL_APB1_GRP1_ReleaseReset\n
01167   *         APB1RSTR1    LCDRST        LL_APB1_GRP1_ReleaseReset\n
01168   *         APB1RSTR1    SPI2RST       LL_APB1_GRP1_ReleaseReset\n
01169   *         APB1RSTR1    SPI3RST       LL_APB1_GRP1_ReleaseReset\n
01170   *         APB1RSTR1    USART2RST     LL_APB1_GRP1_ReleaseReset\n
01171   *         APB1RSTR1    USART3RST     LL_APB1_GRP1_ReleaseReset\n
01172   *         APB1RSTR1    UART4RST      LL_APB1_GRP1_ReleaseReset\n
01173   *         APB1RSTR1    UART5RST      LL_APB1_GRP1_ReleaseReset\n
01174   *         APB1RSTR1    I2C1RST       LL_APB1_GRP1_ReleaseReset\n
01175   *         APB1RSTR1    I2C2RST       LL_APB1_GRP1_ReleaseReset\n
01176   *         APB1RSTR1    I2C3RST       LL_APB1_GRP1_ReleaseReset\n
01177   *         APB1RSTR1    CRSRST        LL_APB1_GRP1_ReleaseReset\n
01178   *         APB1RSTR1    CAN1RST       LL_APB1_GRP1_ReleaseReset\n
01179   *         APB1RSTR1    PWRRST        LL_APB1_GRP1_ReleaseReset\n
01180   *         APB1RSTR1    DAC1RST       LL_APB1_GRP1_ReleaseReset\n
01181   *         APB1RSTR1    OPAMPRST      LL_APB1_GRP1_ReleaseReset\n
01182   *         APB1RSTR1    LPTIM1RST     LL_APB1_GRP1_ReleaseReset
01183   * @param  Periphs This parameter can be a combination of the following values:
01184   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
01185   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01186   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
01187   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
01188   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
01189   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01190   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01191   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
01192   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
01193   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01194   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01195   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
01196   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
01197   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
01198   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01199   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
01200   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01201   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
01202   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
01203   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
01204   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
01205   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
01206   *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
01207   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01208   *
01209   *         (*) value not defined in all devices.
01210   * @retval None
01211 */
01212 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
01213 {
01214   CLEAR_BIT(RCC->APB1RSTR1, Periphs);
01215 }
01216
01217 /**
01218   * @brief  Release APB1 peripherals reset.
01219   * @rmtoll APB1RSTR2    LPUART1RST    LL_APB1_GRP2_ReleaseReset\n
01220   *         APB1RSTR2    SWPMI1RST     LL_APB1_GRP2_ReleaseReset\n
01221   *         APB1RSTR2    LPTIM2RST     LL_APB1_GRP2_ReleaseReset
01222   * @param  Periphs This parameter can be a combination of the following values:
01223   *         @arg @ref LL_APB1_GRP2_PERIPH_ALL
01224   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01225   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
01226   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01227   * @retval None
01228 */
01229 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
01230 {
01231   CLEAR_BIT(RCC->APB1RSTR2, Periphs);
01232 }
01233
01234 /**
01235   * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes
01236   * @rmtoll APB1SMENR1   TIM2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01237   *         APB1SMENR1   TIM3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01238   *         APB1SMENR1   TIM4SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01239   *         APB1SMENR1   TIM5SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01240   *         APB1SMENR1   TIM6SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01241   *         APB1SMENR1   TIM7SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01242   *         APB1SMENR1   LCDSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
01243   *         APB1SMENR1   RTCAPBSMEN    LL_APB1_GRP1_EnableClockStopSleep\n
01244   *         APB1SMENR1   WWDGSMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01245   *         APB1SMENR1   SPI2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01246   *         APB1SMENR1   SPI3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01247   *         APB1SMENR1   USART2SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
01248   *         APB1SMENR1   USART3SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
01249   *         APB1SMENR1   UART4SMEN     LL_APB1_GRP1_EnableClockStopSleep\n
01250   *         APB1SMENR1   UART5SMEN     LL_APB1_GRP1_EnableClockStopSleep\n
01251   *         APB1SMENR1   I2C1SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01252   *         APB1SMENR1   I2C2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01253   *         APB1SMENR1   I2C3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01254   *         APB1SMENR1   CRSSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
01255   *         APB1SMENR1   CAN1SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01256   *         APB1SMENR1   PWRSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
01257   *         APB1SMENR1   DAC1SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
01258   *         APB1SMENR1   OPAMPSMEN     LL_APB1_GRP1_EnableClockStopSleep\n
01259   *         APB1SMENR1   LPTIM1SMEN    LL_APB1_GRP1_EnableClockStopSleep
01260   * @param  Periphs This parameter can be a combination of the following values:
01261   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01262   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
01263   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
01264   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
01265   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01266   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01267   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
01268   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
01269   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
01270   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
01271   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01272   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01273   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
01274   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
01275   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
01276   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01277   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
01278   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01279   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
01280   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
01281   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
01282   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
01283   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
01284   *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
01285   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01286   *
01287   *         (*) value not defined in all devices.
01288   * @retval None
01289 */
01290 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
01291 {
01292   __IO uint32_t tmpreg;
01293   SET_BIT(RCC->APB1SMENR1, Periphs);
01294   /* Delay after an RCC peripheral clock enabling */
01295   tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
01296   (void)tmpreg;
01297 }
01298
01299 /**
01300   * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes
01301   * @rmtoll APB1SMENR2   LPUART1SMEN   LL_APB1_GRP2_EnableClockStopSleep\n
01302   *         APB1SMENR2   SWPMI1SMEN    LL_APB1_GRP2_EnableClockStopSleep\n
01303   *         APB1SMENR2   LPTIM2SMEN    LL_APB1_GRP2_EnableClockStopSleep
01304   * @param  Periphs This parameter can be a combination of the following values:
01305   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01306   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
01307   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01308   * @retval None
01309 */
01310 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
01311 {
01312   __IO uint32_t tmpreg;
01313   SET_BIT(RCC->APB1SMENR2, Periphs);
01314   /* Delay after an RCC peripheral clock enabling */
01315   tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
01316   (void)tmpreg;
01317 }
01318
01319 /**
01320   * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes
01321   * @rmtoll APB1SMENR1   TIM2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01322   *         APB1SMENR1   TIM3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01323   *         APB1SMENR1   TIM4SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01324   *         APB1SMENR1   TIM5SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01325   *         APB1SMENR1   TIM6SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01326   *         APB1SMENR1   TIM7SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01327   *         APB1SMENR1   LCDSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
01328   *         APB1SMENR1   RTCAPBSMEN    LL_APB1_GRP1_DisableClockStopSleep\n
01329   *         APB1SMENR1   WWDGSMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01330   *         APB1SMENR1   SPI2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01331   *         APB1SMENR1   SPI3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01332   *         APB1SMENR1   USART2SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
01333   *         APB1SMENR1   USART3SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
01334   *         APB1SMENR1   UART4SMEN     LL_APB1_GRP1_DisableClockStopSleep\n
01335   *         APB1SMENR1   UART5SMEN     LL_APB1_GRP1_DisableClockStopSleep\n
01336   *         APB1SMENR1   I2C1SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01337   *         APB1SMENR1   I2C2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01338   *         APB1SMENR1   I2C3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01339   *         APB1SMENR1   CRSSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
01340   *         APB1SMENR1   CAN1SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01341   *         APB1SMENR1   PWRSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
01342   *         APB1SMENR1   DAC1SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
01343   *         APB1SMENR1   OPAMPSMEN     LL_APB1_GRP1_DisableClockStopSleep\n
01344   *         APB1SMENR1   LPTIM1SMEN    LL_APB1_GRP1_DisableClockStopSleep
01345   * @param  Periphs This parameter can be a combination of the following values:
01346   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01347   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
01348   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
01349   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
01350   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
01351   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
01352   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
01353   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
01354   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
01355   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
01356   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
01357   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
01358   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
01359   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
01360   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
01361   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01362   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
01363   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01364   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
01365   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1
01366   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
01367   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
01368   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
01369   *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
01370   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01371   *
01372   *         (*) value not defined in all devices.
01373   * @retval None
01374 */
01375 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
01376 {
01377   CLEAR_BIT(RCC->APB1SMENR1, Periphs);
01378 }
01379
01380 /**
01381   * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes
01382   * @rmtoll APB1SMENR2   LPUART1SMEN   LL_APB1_GRP2_DisableClockStopSleep\n
01383   *         APB1SMENR2   SWPMI1SMEN    LL_APB1_GRP2_DisableClockStopSleep\n
01384   *         APB1SMENR2   LPTIM2SMEN    LL_APB1_GRP2_DisableClockStopSleep
01385   * @param  Periphs This parameter can be a combination of the following values:
01386   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01387   *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
01388   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01389   * @retval None
01390 */
01391 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
01392 {
01393   CLEAR_BIT(RCC->APB1SMENR2, Periphs);
01394 }
01395
01396 /**
01397   * @}
01398   */
01399
01400 /** @defgroup BUS_LL_EF_APB2 APB2
01401   * @{
01402   */
01403
01404 /**
01405   * @brief  Enable APB2 peripherals clock.
01406   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_EnableClock\n
01407   *         APB2ENR      FWEN          LL_APB2_GRP1_EnableClock\n
01408   *         APB2ENR      SDMMC1EN      LL_APB2_GRP1_EnableClock\n
01409   *         APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
01410   *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
01411   *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
01412   *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
01413   *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
01414   *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
01415   *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
01416   *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n
01417   *         APB2ENR      SAI2EN        LL_APB2_GRP1_EnableClock\n
01418   *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_EnableClock
01419   * @param  Periphs This parameter can be a combination of the following values:
01420   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01421   *         @arg @ref LL_APB2_GRP1_PERIPH_FW
01422   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
01423   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01424   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01425   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
01426   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01427   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01428   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01429   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
01430   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01431   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
01432   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
01433   *
01434   *         (*) value not defined in all devices.
01435   * @retval None
01436 */
01437 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
01438 {
01439   __IO uint32_t tmpreg;
01440   SET_BIT(RCC->APB2ENR, Periphs);
01441   /* Delay after an RCC peripheral clock enabling */
01442   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
01443   (void)tmpreg;
01444 }
01445
01446 /**
01447   * @brief  Check if APB2 peripheral clock is enabled or not
01448   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
01449   *         APB2ENR      FWEN          LL_APB2_GRP1_IsEnabledClock\n
01450   *         APB2ENR      SDMMC1EN      LL_APB2_GRP1_IsEnabledClock\n
01451   *         APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
01452   *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
01453   *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
01454   *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
01455   *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
01456   *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
01457   *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
01458   *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
01459   *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
01460   *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_IsEnabledClock
01461   * @param  Periphs This parameter can be a combination of the following values:
01462   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01463   *         @arg @ref LL_APB2_GRP1_PERIPH_FW
01464   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
01465   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01466   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01467   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
01468   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01469   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01470   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01471   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
01472   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01473   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
01474   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
01475   *
01476   *         (*) value not defined in all devices.
01477   * @retval State of Periphs (1 or 0).
01478 */
01479 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
01480 {
01481   return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
01482 }
01483
01484 /**
01485   * @brief  Disable APB2 peripherals clock.
01486   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_DisableClock\n
01487   *         APB2ENR      SDMMC1EN      LL_APB2_GRP1_DisableClock\n
01488   *         APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
01489   *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
01490   *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
01491   *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
01492   *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
01493   *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
01494   *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
01495   *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n
01496   *         APB2ENR      SAI2EN        LL_APB2_GRP1_DisableClock\n
01497   *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_DisableClock
01498   * @param  Periphs This parameter can be a combination of the following values:
01499   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01500   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
01501   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01502   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01503   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
01504   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01505   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01506   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01507   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
01508   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01509   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
01510   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
01511   *
01512   *         (*) value not defined in all devices.
01513   * @retval None
01514 */
01515 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
01516 {
01517   CLEAR_BIT(RCC->APB2ENR, Periphs);
01518 }
01519
01520 /**
01521   * @brief  Force APB2 peripherals reset.
01522   * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ForceReset\n
01523   *         APB2RSTR     SDMMC1RST     LL_APB2_GRP1_ForceReset\n
01524   *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n
01525   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
01526   *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n
01527   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
01528   *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n
01529   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n
01530   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n
01531   *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset\n
01532   *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ForceReset\n
01533   *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ForceReset
01534   * @param  Periphs This parameter can be a combination of the following values:
01535   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
01536   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01537   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
01538   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01539   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01540   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
01541   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01542   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01543   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01544   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
01545   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01546   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
01547   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
01548   *
01549   *         (*) value not defined in all devices.
01550   * @retval None
01551 */
01552 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
01553 {
01554   SET_BIT(RCC->APB2RSTR, Periphs);
01555 }
01556
01557 /**
01558   * @brief  Release APB2 peripherals reset.
01559   * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ReleaseReset\n
01560   *         APB2RSTR     SDMMC1RST     LL_APB2_GRP1_ReleaseReset\n
01561   *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
01562   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
01563   *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n
01564   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
01565   *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
01566   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
01567   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
01568   *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset\n
01569   *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ReleaseReset\n
01570   *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ReleaseReset
01571   * @param  Periphs This parameter can be a combination of the following values:
01572   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
01573   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01574   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
01575   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01576   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01577   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
01578   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01579   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01580   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01581   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
01582   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01583   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
01584   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
01585   *
01586   *         (*) value not defined in all devices.
01587   * @retval None
01588 */
01589 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
01590 {
01591   CLEAR_BIT(RCC->APB2RSTR, Periphs);
01592 }
01593
01594 /**
01595   * @brief  Enable APB2 peripheral clocks in Sleep and Stop modes
01596   * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_EnableClockStopSleep\n
01597   *         APB2SMENR    SDMMC1SMEN    LL_APB2_GRP1_EnableClockStopSleep\n
01598   *         APB2SMENR    TIM1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
01599   *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
01600   *         APB2SMENR    TIM8SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
01601   *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_EnableClockStopSleep\n
01602   *         APB2SMENR    TIM15SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
01603   *         APB2SMENR    TIM16SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
01604   *         APB2SMENR    TIM17SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
01605   *         APB2SMENR    SAI1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
01606   *         APB2SMENR    SAI2SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
01607   *         APB2SMENR    DFSDM1SMEN    LL_APB2_GRP1_EnableClockStopSleep
01608   * @param  Periphs This parameter can be a combination of the following values:
01609   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01610   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
01611   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01612   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01613   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
01614   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01615   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01616   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01617   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
01618   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01619   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
01620   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
01621   *
01622   *         (*) value not defined in all devices.
01623   * @retval None
01624 */
01625 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
01626 {
01627   __IO uint32_t tmpreg;
01628   SET_BIT(RCC->APB2SMENR, Periphs);
01629   /* Delay after an RCC peripheral clock enabling */
01630   tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
01631   (void)tmpreg;
01632 }
01633
01634 /**
01635   * @brief  Disable APB2 peripheral clocks in Sleep and Stop modes
01636   * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_DisableClockStopSleep\n
01637   *         APB2SMENR    SDMMC1SMEN    LL_APB2_GRP1_DisableClockStopSleep\n
01638   *         APB2SMENR    TIM1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
01639   *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
01640   *         APB2SMENR    TIM8SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
01641   *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_DisableClockStopSleep\n
01642   *         APB2SMENR    TIM15SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
01643   *         APB2SMENR    TIM16SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
01644   *         APB2SMENR    TIM17SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
01645   *         APB2SMENR    SAI1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
01646   *         APB2SMENR    SAI2SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
01647   *         APB2SMENR    DFSDM1SMEN    LL_APB2_GRP1_DisableClockStopSleep
01648   * @param  Periphs This parameter can be a combination of the following values:
01649   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
01650   *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
01651   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01652   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01653   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
01654   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01655   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
01656   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01657   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
01658   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01659   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
01660   *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
01661   *
01662   *         (*) value not defined in all devices.
01663   * @retval None
01664 */
01665 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
01666 {
01667   CLEAR_BIT(RCC->APB2SMENR, Periphs);
01668 }
01669
01670 /**
01671   * @}
01672   */
01673
01674
01675 /**
01676   * @}
01677   */
01678
01679 /**
01680   * @}
01681   */
01682
01683 #endif /* defined(RCC) */
01684
01685 /**
01686   * @}
01687   */
01688
01689 #ifdef __cplusplus
01690 }
01691 #endif
01692
01693 #endif /* __STM32L4xx_LL_BUS_H */
01694
01695 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_comp.c Source File

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stm32l4xx_ll_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_comp.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   COMP LL module driver
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_comp.h"
00041
00042 #ifdef  USE_FULL_ASSERT
00043   #include "stm32_assert.h"
00044 #else
00045   #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32L4xx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined (COMP1) || defined (COMP2)
00053
00054 /** @addtogroup COMP_LL COMP
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062
00063 /** @addtogroup COMP_LL_Private_Macros
00064   * @{
00065   */
00066
00067 /* Check of parameters for configuration of COMP hierarchical scope:          */
00068 /* COMP instance.                                                             */
00069
00070 #define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
00071   (   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
00072    || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
00073    || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
00074   )
00075
00076 /* Note: On this STM32 serie, comparator input plus parameters are            */
00077 /*       the same on all COMP instances.                                      */
00078 /*       However, comparator instance kept as macro parameter for             */
00079 /*       compatibility with other STM32 families.                             */
00080 #if defined(COMP_CSR_INPSEL_1)
00081 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00082   (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
00083    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
00084    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                             \
00085   )
00086 #else
00087 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00088   (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
00089    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
00090   )
00091 #endif
00092
00093 /* Note: On this STM32 serie, comparator input minus parameters are           */
00094 /*       the same on all COMP instances.                                      */
00095 /*       However, comparator instance kept as macro parameter for             */
00096 /*       compatibility with other STM32 families.                             */
00097 #if defined(COMP_CSR_INMESEL_1)
00098 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00099   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00100    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00101    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00102    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00103    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
00104    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
00105    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00106    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
00107    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
00108    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
00109    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5)                           \
00110   )
00111 #else
00112 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00113   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00114    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00115    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00116    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00117    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
00118    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
00119    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00120    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
00121   )
00122 #endif
00123
00124 #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)                      \
00125   (   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
00126    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
00127    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
00128    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
00129   )
00130
00131 #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
00132   (   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
00133    || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
00134   )
00135
00136 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)          \
00137   (   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)               \
00138    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)     \
00139    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)     \
00140    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)     \
00141    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2)     \
00142    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)     \
00143    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2)    \
00144   )
00145
00146 /**
00147   * @}
00148   */
00149
00150
00151 /* Private function prototypes -----------------------------------------------*/
00152
00153 /* Exported functions --------------------------------------------------------*/
00154 /** @addtogroup COMP_LL_Exported_Functions
00155   * @{
00156   */
00157
00158 /** @addtogroup COMP_LL_EF_Init
00159   * @{
00160   */
00161
00162 /**
00163   * @brief  De-initialize registers of the selected COMP instance
00164   *         to their default reset values.
00165   * @note   If comparator is locked, de-initialization by software is
00166   *         not possible.
00167   *         The only way to unlock the comparator is a device hardware reset.
00168   * @param  COMPx COMP instance
00169   * @retval An ErrorStatus enumeration value:
00170   *          - SUCCESS: COMP registers are de-initialized
00171   *          - ERROR: COMP registers are not de-initialized
00172   */
00173 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
00174 {
00175   ErrorStatus status = SUCCESS;
00176
00177   /* Check the parameters */
00178   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00179
00180   /* Note: Hardware constraint (refer to description of this function):       */
00181   /*       COMP instance must not be locked.                                  */
00182   if(LL_COMP_IsLocked(COMPx) == 0U)
00183   {
00184     LL_COMP_WriteReg(COMPx, CSR, 0x00000000U);
00185
00186   }
00187   else
00188   {
00189     /* Comparator instance is locked: de-initialization by software is         */
00190     /* not possible.                                                           */
00191     /* The only way to unlock the comparator is a device hardware reset.       */
00192     status = ERROR;
00193   }
00194
00195   return status;
00196 }
00197
00198 /**
00199   * @brief  Initialize some features of COMP instance.
00200   * @note   This function configures features of the selected COMP instance.
00201   *         Some features are also available at scope COMP common instance
00202   *         (common to several COMP instances).
00203   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00204   * @param  COMPx COMP instance
00205   * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00206   * @retval An ErrorStatus enumeration value:
00207   *          - SUCCESS: COMP registers are initialized
00208   *          - ERROR: COMP registers are not initialized
00209   */
00210 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
00211 {
00212   ErrorStatus status = SUCCESS;
00213
00214   /* Check the parameters */
00215   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00216   assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
00217   assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
00218   assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
00219   assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
00220   assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
00221   assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource));
00222
00223   /* Note: Hardware constraint (refer to description of this function)        */
00224   /*       COMP instance must not be locked.                                  */
00225   if(LL_COMP_IsLocked(COMPx) == 0U)
00226   {
00227     /* Configuration of comparator instance :                                 */
00228     /*  - PowerMode                                                           */
00229     /*  - InputPlus                                                           */
00230     /*  - InputMinus                                                          */
00231     /*  - InputHysteresis                                                     */
00232     /*  - OutputPolarity                                                      */
00233     /*  - OutputBlankingSource                                                */
00234 #if defined(COMP_CSR_INMESEL_1)
00235     MODIFY_REG(COMPx->CSR,
00236                  COMP_CSR_PWRMODE
00237                | COMP_CSR_INPSEL
00238                | COMP_CSR_SCALEN
00239                | COMP_CSR_BRGEN
00240                | COMP_CSR_INMESEL
00241                | COMP_CSR_INMSEL
00242                | COMP_CSR_HYST
00243                | COMP_CSR_POLARITY
00244                | COMP_CSR_BLANKING
00245               ,
00246                  COMP_InitStruct->PowerMode
00247                | COMP_InitStruct->InputPlus
00248                | COMP_InitStruct->InputMinus
00249                | COMP_InitStruct->InputHysteresis
00250                | COMP_InitStruct->OutputPolarity
00251                | COMP_InitStruct->OutputBlankingSource
00252               );
00253 #else
00254     MODIFY_REG(COMPx->CSR,
00255                  COMP_CSR_PWRMODE
00256                | COMP_CSR_INPSEL
00257                | COMP_CSR_SCALEN
00258                | COMP_CSR_BRGEN
00259                | COMP_CSR_INMSEL
00260                | COMP_CSR_HYST
00261                | COMP_CSR_POLARITY
00262                | COMP_CSR_BLANKING
00263               ,
00264                  COMP_InitStruct->PowerMode
00265                | COMP_InitStruct->InputPlus
00266                | COMP_InitStruct->InputMinus
00267                | COMP_InitStruct->InputHysteresis
00268                | COMP_InitStruct->OutputPolarity
00269                | COMP_InitStruct->OutputBlankingSource
00270               );
00271 #endif
00272
00273   }
00274   else
00275   {
00276     /* Initialization error: COMP instance is locked.                         */
00277     status = ERROR;
00278   }
00279
00280   return status;
00281 }
00282
00283 /**
00284   * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
00285   * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure
00286   *                         whose fields will be set to default values.
00287   * @retval None
00288   */
00289 void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
00290 {
00291   /* Set COMP_InitStruct fields to default values */
00292   COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_ULTRALOWPOWER;
00293   COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
00294   COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
00295   COMP_InitStruct->InputHysteresis      = LL_COMP_HYSTERESIS_NONE;
00296   COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
00297   COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
00298 }
00299
00300 /**
00301   * @}
00302   */
00303
00304 /**
00305   * @}
00306   */
00307
00308 /**
00309   * @}
00310   */
00311
00312 #endif /* COMP1 || COMP2 */
00313
00314 /**
00315   * @}
00316   */
00317
00318 #endif /* USE_FULL_LL_DRIVER */
00319
00320 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_comp.h Source File

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stm32l4xx_ll_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_comp.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of COMP LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_COMP_H
00040 #define __STM32L4xx_LL_COMP_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (COMP1) || defined (COMP2)
00054
00055 /** @defgroup COMP_LL COMP
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /** @defgroup COMP_LL_Private_Constants COMP Private Constants
00063   * @{
00064   */
00065
00066 /* COMP registers bits positions */
00067 #define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
00068
00069 /**
00070   * @}
00071   */
00072
00073 /* Private macros ------------------------------------------------------------*/
00074 /* Exported types ------------------------------------------------------------*/
00075 #if defined(USE_FULL_LL_DRIVER)
00076 /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  Structure definition of some features of COMP instance.
00082   */
00083 typedef struct
00084 {
00085   uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
00086                                              This parameter can be a value of @ref COMP_LL_EC_POWERMODE
00087
00088                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
00089
00090   uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
00091                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
00092
00093                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
00094
00095   uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
00096                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
00097
00098                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
00099
00100   uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.
00101                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
00102
00103                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
00104
00105   uint32_t OutputPolarity;              /*!< Set comparator output polarity.
00106                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
00107
00108                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
00109
00110   uint32_t OutputBlankingSource;        /*!< Set comparator blanking source.
00111                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
00112
00113                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
00114
00115 } LL_COMP_InitTypeDef;
00116
00117 /**
00118   * @}
00119   */
00120 #endif /* USE_FULL_LL_DRIVER */
00121
00122 /* Exported constants --------------------------------------------------------*/
00123 /** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
00124   * @{
00125   */
00126
00127 /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
00128   * @{
00129   */
00130 #define LL_COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
00131 #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)      /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
00132 /**
00133   * @}
00134   */
00135
00136 /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
00137   * @{
00138   */
00139 #define LL_COMP_POWERMODE_HIGHSPEED     ((uint32_t)0x00000000U)                   /*!< COMP power mode to high speed */
00140 #define LL_COMP_POWERMODE_MEDIUMSPEED   (COMP_CSR_PWRMODE_0)                      /*!< COMP power mode to medium speed */
00141 #define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
00147   * @{
00148   */
00149 #define LL_COMP_INPUT_PLUS_IO1          ((uint32_t)0x00000000U)                 /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
00150 #define LL_COMP_INPUT_PLUS_IO2          (COMP_CSR_INPSEL_0)                     /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
00151 #if defined(COMP_CSR_INPSEL_1)
00152 #define LL_COMP_INPUT_PLUS_IO3          (COMP_CSR_INPSEL_1 | COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
00153 #endif
00154 /**
00155   * @}
00156   */
00157
00158 /** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
00159   * @{
00160   */
00161 #define LL_COMP_INPUT_MINUS_1_4VREFINT  (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt  */
00162 #define LL_COMP_INPUT_MINUS_1_2VREFINT  (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt  */
00163 #define LL_COMP_INPUT_MINUS_3_4VREFINT  (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt  */
00164 #define LL_COMP_INPUT_MINUS_VREFINT     (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
00165 #define LL_COMP_INPUT_MINUS_DAC1_CH1    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */
00166 #define LL_COMP_INPUT_MINUS_DAC1_CH2    (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */
00167 #define LL_COMP_INPUT_MINUS_IO1         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
00168 #define LL_COMP_INPUT_MINUS_IO2         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
00169 #if defined(COMP_CSR_INMESEL_1)
00170 #define LL_COMP_INPUT_MINUS_IO3         (                     COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
00171 #define LL_COMP_INPUT_MINUS_IO4         (COMP_CSR_INMESEL_1                      | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
00172 #define LL_COMP_INPUT_MINUS_IO5         (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
00173 #endif
00174 /**
00175   * @}
00176   */
00177
00178 /** @defgroup COMP_LL_EC_INPUT_LEGACY Comparator inputs legacy literals name
00179   * @{
00180   */
00181 #define LL_COMP_WINDOWMODE_ENABLE         LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
00182
00183 #define LL_COMP_INVERTINGINPUT_1_4VREFINT LL_COMP_INPUT_MINUS_1_4VREFINT
00184 #define LL_COMP_INVERTINGINPUT_1_2VREFINT LL_COMP_INPUT_MINUS_1_2VREFINT
00185 #define LL_COMP_INVERTINGINPUT_3_4VREFINT LL_COMP_INPUT_MINUS_3_4VREFINT
00186 #define LL_COMP_INVERTINGINPUT_VREFINT    LL_COMP_INPUT_MINUS_VREFINT
00187 #define LL_COMP_INVERTINGINPUT_DAC1       LL_COMP_INPUT_MINUS_DAC1_CH1
00188 #define LL_COMP_INVERTINGINPUT_DAC2       LL_COMP_INPUT_MINUS_DAC1_CH2
00189 #define LL_COMP_INVERTINGINPUT_IO1        LL_COMP_INPUT_MINUS_IO1
00190 #define LL_COMP_INVERTINGINPUT_IO2        LL_COMP_INPUT_MINUS_IO2
00191 #if defined(COMP_CSR_INMESEL_1)
00192 #define LL_COMP_INVERTINGINPUT_IO3        LL_COMP_INPUT_MINUS_IO3
00193 #define LL_COMP_INVERTINGINPUT_IO4        LL_COMP_INPUT_MINUS_IO4
00194 #define LL_COMP_INVERTINGINPUT_IO5        LL_COMP_INPUT_MINUS_IO5
00195 #endif
00196
00197 #define LL_COMP_NONINVERTINGINPUT_IO1     LL_COMP_INPUT_PLUS_IO1
00198 #define LL_COMP_NONINVERTINGINPUT_IO2     LL_COMP_INPUT_PLUS_IO2
00199 #if defined(COMP_CSR_INPSEL_1)
00200 #define LL_COMP_NONINVERTINGINPUT_IO3     LL_COMP_INPUT_PLUS_IO3
00201 #endif
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
00207   * @{
00208   */
00209 #define LL_COMP_HYSTERESIS_NONE         ((uint32_t)0x00000000U)             /*!< No hysteresis */
00210 #define LL_COMP_HYSTERESIS_LOW          (                  COMP_CSR_HYST_0) /*!< Hysteresis level low */
00211 #define LL_COMP_HYSTERESIS_MEDIUM       (COMP_CSR_HYST_1                  ) /*!< Hysteresis level medium */
00212 #define LL_COMP_HYSTERESIS_HIGH         (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
00218   * @{
00219   */
00220 #define LL_COMP_OUTPUTPOL_NONINVERTED   ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
00221 #define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_POLARITY)     /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
00227   * @{
00228   */
00229 #define LL_COMP_BLANKINGSRC_NONE        ((uint32_t)0x00000000U) /*!<Comparator output without blanking */
00230 #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1) */
00231 #define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1) */
00232 #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (COMP_CSR_BLANKING_2)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1) */
00233 #define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2  (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP2) */
00234 #define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2) */
00235 #define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2)   /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP2) */
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE_LEGACY Comparator output blanking source legacy literals name
00241   * @{
00242   */
00243 #define LL_COMP_BLANKINGSRC_TIM1_OC5    (LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1)
00244 #define LL_COMP_BLANKINGSRC_TIM2_OC3    (LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1)
00245 #define LL_COMP_BLANKINGSRC_TIM3_OC3    (LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1)
00246
00247 #define LL_COMP_BLANKINGSRC_TIM3_OC4    (LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2)
00248 #define LL_COMP_BLANKINGSRC_TIM8_OC5    (LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2)
00249 #define LL_COMP_BLANKINGSRC_TIM15_OC1   (LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2)
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
00255   * @{
00256   */
00257 #define LL_COMP_OUTPUT_LEVEL_LOW        ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
00258 #define LL_COMP_OUTPUT_LEVEL_HIGH       ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
00264   * @note   Only COMP IP HW delays are defined in COMP LL driver driver,
00265   *         not timeout values.
00266   *         For details on delays values, refer to descriptions in source code
00267   *         above each literal definition.
00268   * @{
00269   */
00270
00271 /* Delay for comparator startup time.                                         */
00272 /* Note: Delay required to reach propagation delay specification.             */
00273 /* Literal set to maximum value (refer to device datasheet,                   */
00274 /* parameter "tSTART").                                                       */
00275 /* Unit: us                                                                   */
00276 #define LL_COMP_DELAY_STARTUP_US          ((uint32_t) 80U)  /*!< Delay for COMP startup time */
00277
00278 /* Delay for comparator voltage scaler stabilization time.                    */
00279 /* Note: Voltage scaler is used when selecting comparator input               */
00280 /*       based on VrefInt: VrefInt or subdivision of VrefInt.                 */
00281 /* Literal set to maximum value (refer to device datasheet,                   */
00282 /* parameter "tSTART_SCALER").                                                */
00283 /* Unit: us                                                                   */
00284 #define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U)  /*!< Delay for COMP voltage scaler stabilization time */
00285
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294 /* Exported macro ------------------------------------------------------------*/
00295 /** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
00296   * @{
00297   */
00298 /** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
00299   * @{
00300   */
00301
00302 /**
00303   * @brief  Write a value in COMP register
00304   * @param  __INSTANCE__ comparator instance
00305   * @param  __REG__ Register to be written
00306   * @param  __VALUE__ Value to be written in the register
00307   * @retval None
00308   */
00309 #define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00310
00311 /**
00312   * @brief  Read a value in COMP register
00313   * @param  __INSTANCE__ comparator instance
00314   * @param  __REG__ Register to be read
00315   * @retval Register value
00316   */
00317 #define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
00323   * @{
00324   */
00325
00326 /**
00327   * @brief  Helper macro to select the COMP common instance
00328   *         to which is belonging the selected COMP instance.
00329   * @note   COMP common register instance can be used to
00330   *         set parameters common to several COMP instances.
00331   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00332   * @param  __COMPx__ COMP instance
00333   * @retval COMP common instance or value "0" if there is no COMP common instance.
00334   */
00335 #define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
00336   (COMP12_COMMON)
00337
00338 /**
00339   * @}
00340   */
00341
00342 /**
00343   * @}
00344   */
00345
00346 /* Exported functions --------------------------------------------------------*/
00347 /** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
00348   * @{
00349   */
00350
00351 /** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
00352   * @{
00353   */
00354
00355 /**
00356   * @brief  Set window mode of a pair of comparators instances
00357   *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
00358   * @rmtoll CSR      WINMODE        LL_COMP_SetCommonWindowMode
00359   * @param  COMPxy_COMMON Comparator common instance
00360   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00361   * @param  WindowMode This parameter can be one of the following values:
00362   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
00363   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
00364   * @retval None
00365   */
00366 __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
00367 {
00368   /* Note: On this STM32 serie, window mode can be set only                   */
00369   /*       from COMP instance: COMP2.                                         */
00370   MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WINMODE, WindowMode);
00371 }
00372
00373 /**
00374   * @brief  Get window mode of a pair of comparators instances
00375   *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
00376   * @rmtoll CSR      WINMODE        LL_COMP_GetCommonWindowMode
00377   * @param  COMPxy_COMMON Comparator common instance
00378   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00379   * @retval Returned value can be one of the following values:
00380   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
00381   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
00382   */
00383 __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
00384 {
00385   return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WINMODE));
00386 }
00387
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
00393   * @{
00394   */
00395
00396 /**
00397   * @brief  Set comparator instance operating mode to adjust power and speed.
00398   * @rmtoll CSR      PWRMODE        LL_COMP_SetPowerMode
00399   * @param  COMPx Comparator instance
00400   * @param  PowerMode This parameter can be one of the following values:
00401   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
00402   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
00403   *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
00404   * @retval None
00405   */
00406 __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
00407 {
00408   MODIFY_REG(COMPx->CSR, COMP_CSR_PWRMODE, PowerMode);
00409 }
00410
00411 /**
00412   * @brief  Get comparator instance operating mode to adjust power and speed.
00413   * @rmtoll CSR      PWRMODE        LL_COMP_GetPowerMode
00414   * @param  COMPx Comparator instance
00415   * @retval Returned value can be one of the following values:
00416   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
00417   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
00418   *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
00419   */
00420 __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
00421 {
00422   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE));
00423 }
00424
00425 /**
00426   * @}
00427   */
00428
00429 /** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
00430   * @{
00431   */
00432
00433 /**
00434   * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
00435   * @note   In case of comparator input selected to be connected to IO:
00436   *         GPIO pins are specific to each comparator instance.
00437   *         Refer to description of parameters or to reference manual.
00438   * @note   On this STM32 serie, scaler bridge is configurable:
00439   *         to optimize power consumption, this function enables the
00440   *         voltage scaler bridge only when required
00441   *         (when selecting comparator input based on VrefInt: VrefInt or
00442   *         subdivision of VrefInt).
00443   *         - For scaler bridge power consumption values,
00444   *           refer to device datasheet, parameter "IDDA(SCALER)".
00445   *         - Voltage scaler requires a delay for voltage stabilization.
00446   *           Refer to device datasheet, parameter "tSTART_SCALER".
00447   *         - Scaler bridge is common for all comparator instances,
00448   *           therefore if at least one of the comparator instance
00449   *           is requiring the scaler bridge, it remains enabled.
00450   * @rmtoll CSR      INMSEL         LL_COMP_ConfigInputs\n
00451   *         CSR      INPSEL         LL_COMP_ConfigInputs\n
00452   *         CSR      BRGEN          LL_COMP_ConfigInputs\n
00453   *         CSR      SCALEN         LL_COMP_ConfigInputs
00454   * @param  COMPx Comparator instance
00455   * @param  InputMinus This parameter can be one of the following values:
00456   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00457   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00458   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00459   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00460   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00461   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
00462   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00463   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00464   *         @arg @ref LL_COMP_INPUT_MINUS_IO3 (*)
00465   *         @arg @ref LL_COMP_INPUT_MINUS_IO4 (*)
00466   *         @arg @ref LL_COMP_INPUT_MINUS_IO5 (*)
00467   *
00468   *         (*) Parameter not available on all devices.
00469   * @param  InputPlus This parameter can be one of the following values:
00470   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00471   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00472   *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
00473   *
00474   *         (*) Parameter not available on all devices.
00475   * @retval None
00476   */
00477 __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
00478 {
00479 #if defined(COMP_CSR_INMESEL_1)
00480   MODIFY_REG(COMPx->CSR,
00481              COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
00482              InputMinus | InputPlus);
00483 #else
00484   MODIFY_REG(COMPx->CSR,
00485              COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
00486              InputMinus | InputPlus);
00487 #endif
00488 }
00489
00490 /**
00491   * @brief  Set comparator input plus (non-inverting).
00492   * @note   In case of comparator input selected to be connected to IO:
00493   *         GPIO pins are specific to each comparator instance.
00494   *         Refer to description of parameters or to reference manual.
00495   * @rmtoll CSR      INPSEL         LL_COMP_SetInputPlus
00496   * @param  COMPx Comparator instance
00497   * @param  InputPlus This parameter can be one of the following values:
00498   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00499   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00500   *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
00501   *
00502   *         (*) Parameter not available on all devices.
00503   * @retval None
00504   */
00505 __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
00506 {
00507   MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
00508 }
00509
00510 /**
00511   * @brief  Get comparator input plus (non-inverting).
00512   * @note   In case of comparator input selected to be connected to IO:
00513   *         GPIO pins are specific to each comparator instance.
00514   *         Refer to description of parameters or to reference manual.
00515   * @rmtoll CSR      INPSEL         LL_COMP_GetInputPlus
00516   * @param  COMPx Comparator instance
00517   * @retval Returned value can be one of the following values:
00518   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00519   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00520   *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
00521   *
00522   *         (*) Parameter not available on all devices.
00523   */
00524 __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
00525 {
00526   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
00527 }
00528
00529 /**
00530   * @brief  Set comparator input minus (inverting).
00531   * @note   In case of comparator input selected to be connected to IO:
00532   *         GPIO pins are specific to each comparator instance.
00533   *         Refer to description of parameters or to reference manual.
00534   * @note   On this STM32 serie, scaler bridge is configurable:
00535   *         to optimize power consumption, this function enables the
00536   *         voltage scaler bridge only when required
00537   *         (when selecting comparator input based on VrefInt: VrefInt or
00538   *         subdivision of VrefInt).
00539   *         - For scaler bridge power consumption values,
00540   *           refer to device datasheet, parameter "IDDA(SCALER)".
00541   *         - Voltage scaler requires a delay for voltage stabilization.
00542   *           Refer to device datasheet, parameter "tSTART_SCALER".
00543   *         - Scaler bridge is common for all comparator instances,
00544   *           therefore if at least one of the comparator instance
00545   *           is requiring the scaler bridge, it remains enabled.
00546   * @rmtoll CSR      INMSEL         LL_COMP_SetInputMinus\n
00547   *         CSR      BRGEN          LL_COMP_SetInputMinus\n
00548   *         CSR      SCALEN         LL_COMP_SetInputMinus
00549   * @param  COMPx Comparator instance
00550   * @param  InputMinus This parameter can be one of the following values:
00551   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00552   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00553   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00554   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00555   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00556   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
00557   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00558   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00559   *         @arg @ref LL_COMP_INPUT_MINUS_IO3 (*)
00560   *         @arg @ref LL_COMP_INPUT_MINUS_IO4 (*)
00561   *         @arg @ref LL_COMP_INPUT_MINUS_IO5 (*)
00562   *
00563   *         (*) Parameter not available on all devices.
00564   * @retval None
00565   */
00566 __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
00567 {
00568 #if defined(COMP_CSR_INMESEL_1)
00569   MODIFY_REG(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
00570 #else
00571   MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
00572 #endif
00573 }
00574
00575 /**
00576   * @brief  Get comparator input minus (inverting).
00577   * @note   In case of comparator input selected to be connected to IO:
00578   *         GPIO pins are specific to each comparator instance.
00579   *         Refer to description of parameters or to reference manual.
00580   * @rmtoll CSR      INMSEL         LL_COMP_GetInputMinus\n
00581   *         CSR      BRGEN          LL_COMP_GetInputMinus\n
00582   *         CSR      SCALEN         LL_COMP_GetInputMinus
00583   * @param  COMPx Comparator instance
00584   * @retval Returned value can be one of the following values:
00585   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00586   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00587   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00588   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00589   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
00590   *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
00591   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00592   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00593   *         @arg @ref LL_COMP_INPUT_MINUS_IO3 (*)
00594   *         @arg @ref LL_COMP_INPUT_MINUS_IO4 (*)
00595   *         @arg @ref LL_COMP_INPUT_MINUS_IO5 (*)
00596   *
00597   *         (*) Parameter not available on all devices.
00598   */
00599 __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
00600 {
00601 #if defined(COMP_CSR_INMESEL_1)
00602   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
00603 #else
00604   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
00605 #endif
00606 }
00607
00608 /**
00609   * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).
00610   * @rmtoll CSR      HYST           LL_COMP_SetInputHysteresis
00611   * @param  COMPx Comparator instance
00612   * @param  InputHysteresis This parameter can be one of the following values:
00613   *         @arg @ref LL_COMP_HYSTERESIS_NONE
00614   *         @arg @ref LL_COMP_HYSTERESIS_LOW
00615   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
00616   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
00617   * @retval None
00618   */
00619 __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
00620 {
00621   MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
00622 }
00623
00624 /**
00625   * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.
00626   * @rmtoll CSR      HYST           LL_COMP_GetInputHysteresis
00627   * @param  COMPx Comparator instance
00628   * @retval Returned value can be one of the following values:
00629   *         @arg @ref LL_COMP_HYSTERESIS_NONE
00630   *         @arg @ref LL_COMP_HYSTERESIS_LOW
00631   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
00632   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
00633   */
00634 __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
00635 {
00636   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
00637 }
00638
00639 /**
00640   * @}
00641   */
00642
00643 /** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
00644   * @{
00645   */
00646
00647 /**
00648   * @brief  Set comparator instance output polarity.
00649   * @rmtoll CSR      POLARITY       LL_COMP_SetOutputPolarity
00650   * @param  COMPx Comparator instance
00651   * @param  OutputPolarity This parameter can be one of the following values:
00652   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
00653   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
00654   * @retval None
00655   */
00656 __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
00657 {
00658   MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
00659 }
00660
00661 /**
00662   * @brief  Get comparator instance output polarity.
00663   * @rmtoll CSR      POLARITY       LL_COMP_GetOutputPolarity
00664   * @param  COMPx Comparator instance
00665   * @retval Returned value can be one of the following values:
00666   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
00667   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
00668   */
00669 __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
00670 {
00671   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
00672 }
00673
00674 /**
00675   * @brief  Set comparator instance blanking source.
00676   * @note   Blanking source may be specific to each comparator instance.
00677   *         Refer to description of parameters or to reference manual.
00678   * @note   Availability of parameters of blanking source from timer
00679   *         depends on timers availability on the selected device.
00680   * @rmtoll CSR      BLANKING       LL_COMP_SetOutputBlankingSource
00681   * @param  COMPx Comparator instance
00682   * @param  BlankingSource This parameter can be one of the following values:
00683   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
00684   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (1)(2)
00685   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (1)(2)
00686   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (1)(2)
00687   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2  (1)(3)
00688   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (1)(3)
00689   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (1)(3)
00690   *
00691   *         (1) Parameter availability depending on timer availability
00692   *             on the selected device.
00693   *         (2) On STM32L4, parameter available only on comparator instance: COMP1.
00694   *         (3) On STM32L4, parameter available only on comparator instance: COMP2.
00695   * @retval None
00696   */
00697 __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
00698 {
00699   MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKING, BlankingSource);
00700 }
00701
00702 /**
00703   * @brief  Get comparator instance blanking source.
00704   * @note   Availability of parameters of blanking source from timer
00705   *         depends on timers availability on the selected device.
00706   * @note   Blanking source may be specific to each comparator instance.
00707   *         Refer to description of parameters or to reference manual.
00708   * @rmtoll CSR      BLANKING       LL_COMP_GetOutputBlankingSource
00709   * @param  COMPx Comparator instance
00710   * @retval Returned value can be one of the following values:
00711   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
00712   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (1)(2)
00713   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (1)(2)
00714   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (1)(2)
00715   *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2  (1)(3)
00716   *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (1)(3)
00717   *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (1)(3)
00718   *
00719   *         (1) Parameter availability depending on timer availability
00720   *             on the selected device.
00721   *         (2) On STM32L4, parameter available only on comparator instance: COMP1.
00722   *         (3) On STM32L4, parameter available only on comparator instance: COMP2.
00723   */
00724 __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
00725 {
00726   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
00727 }
00728
00729 /**
00730   * @}
00731   */
00732
00733 /** @defgroup COMP_LL_EF_Configuration_Legacy_Functions Configuration of COMP, legacy functions name
00734   * @{
00735   */
00736 /* Old functions name kept for legacy purpose, to be replaced by the          */
00737 /* current functions name.                                                    */
00738 __STATIC_INLINE void LL_COMP_SetInputNonInverting(COMP_TypeDef *COMPx, uint32_t InputNonInverting)
00739 {
00740   LL_COMP_SetInputPlus(COMPx, InputNonInverting);
00741 }
00742 __STATIC_INLINE uint32_t LL_COMP_GetInputNonInverting(COMP_TypeDef *COMPx)
00743 {
00744   return LL_COMP_GetInputPlus(COMPx);
00745 }
00746
00747 __STATIC_INLINE void LL_COMP_SetInputInverting(COMP_TypeDef *COMPx, uint32_t InputInverting)
00748 {
00749   LL_COMP_SetInputMinus(COMPx, InputInverting);
00750 }
00751 __STATIC_INLINE uint32_t LL_COMP_GetInputInverting(COMP_TypeDef *COMPx)
00752 {
00753   return LL_COMP_GetInputMinus(COMPx);
00754 }
00755
00756 /**
00757   * @}
00758   */
00759
00760 /** @defgroup COMP_LL_EF_Operation Operation on comparator instance
00761   * @{
00762   */
00763
00764 /**
00765   * @brief  Enable comparator instance.
00766   * @note   After enable from off state, comparator requires a delay
00767   *         to reach reach propagation delay specification.
00768   *         Refer to device datasheet, parameter "tSTART".
00769   * @rmtoll CSR      EN             LL_COMP_Enable
00770   * @param  COMPx Comparator instance
00771   * @retval None
00772   */
00773 __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
00774 {
00775   SET_BIT(COMPx->CSR, COMP_CSR_EN);
00776 }
00777
00778 /**
00779   * @brief  Disable comparator instance.
00780   * @rmtoll CSR      EN             LL_COMP_Disable
00781   * @param  COMPx Comparator instance
00782   * @retval None
00783   */
00784 __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
00785 {
00786   CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
00787 }
00788
00789 /**
00790   * @brief  Get comparator enable state
00791   *         (0: COMP is disabled, 1: COMP is enabled)
00792   * @rmtoll CSR      EN             LL_COMP_IsEnabled
00793   * @param  COMPx Comparator instance
00794   * @retval State of bit (1 or 0).
00795   */
00796 __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
00797 {
00798   return (READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN));
00799 }
00800
00801 /**
00802   * @brief  Lock comparator instance.
00803   * @note   Once locked, comparator configuration can be accessed in read-only.
00804   * @note   The only way to unlock the comparator is a device hardware reset.
00805   * @rmtoll CSR      LOCK           LL_COMP_Lock
00806   * @param  COMPx Comparator instance
00807   * @retval None
00808   */
00809 __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
00810 {
00811   SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
00812 }
00813
00814 /**
00815   * @brief  Get comparator lock state
00816   *         (0: COMP is unlocked, 1: COMP is locked).
00817   * @note   Once locked, comparator configuration can be accessed in read-only.
00818   * @note   The only way to unlock the comparator is a device hardware reset.
00819   * @rmtoll CSR      LOCK           LL_COMP_IsLocked
00820   * @param  COMPx Comparator instance
00821   * @retval State of bit (1 or 0).
00822   */
00823 __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
00824 {
00825   return (READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK));
00826 }
00827
00828 /**
00829   * @brief  Read comparator instance output level.
00830   * @note   The comparator output level depends on the selected polarity
00831   *         (Refer to function @ref LL_COMP_SetOutputPolarity()).
00832   *         If the comparator polarity is not inverted:
00833   *          - Comparator output is low when the input plus
00834   *            is at a lower voltage than the input minus
00835   *          - Comparator output is high when the input plus
00836   *            is at a higher voltage than the input minus
00837   *         If the comparator polarity is inverted:
00838   *          - Comparator output is high when the input plus
00839   *            is at a lower voltage than the input minus
00840   *          - Comparator output is low when the input plus
00841   *            is at a higher voltage than the input minus
00842   * @rmtoll CSR      VALUE          LL_COMP_ReadOutputLevel
00843   * @param  COMPx Comparator instance
00844   * @retval Returned value can be one of the following values:
00845   *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
00846   *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
00847   */
00848 __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
00849 {
00850   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
00851                     >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
00852 }
00853
00854 /**
00855   * @}
00856   */
00857
00858 #if defined(USE_FULL_LL_DRIVER)
00859 /** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
00860   * @{
00861   */
00862
00863 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
00864 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
00865 void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
00866
00867 /**
00868   * @}
00869   */
00870 #endif /* USE_FULL_LL_DRIVER */
00871
00872 /**
00873   * @}
00874   */
00875
00876 /**
00877   * @}
00878   */
00879
00880 #endif /* COMP1 || COMP2 */
00881
00882 /**
00883   * @}
00884   */
00885
00886 #ifdef __cplusplus
00887 }
00888 #endif
00889
00890 #endif /* __STM32L4xx_LL_COMP_H */
00891
00892 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_cortex.h Source File

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stm32l4xx_ll_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_cortex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of CORTEX LL module.
00008   @verbatim
00009   ==============================================================================
00010                      ##### How to use this driver #####
00011   ==============================================================================
00012     [..]
00013     The LL CORTEX driver contains a set of generic APIs that can be
00014     used by user:
00015       (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
00016           functions
00017       (+) Low power mode configuration (SCB register of Cortex-MCU)
00018       (+) MPU API to configure and enable regions
00019       (+) API to access to MCU info (CPUID register)
00020       (+) API to enable fault handler (SHCSR accesses)
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00027   *
00028   * Redistribution and use in source and binary forms, with or without modification,
00029   * are permitted provided that the following conditions are met:
00030   *   1. Redistributions of source code must retain the above copyright notice,
00031   *      this list of conditions and the following disclaimer.
00032   *   2. Redistributions in binary form must reproduce the above copyright notice,
00033   *      this list of conditions and the following disclaimer in the documentation
00034   *      and/or other materials provided with the distribution.
00035   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00036   *      may be used to endorse or promote products derived from this software
00037   *      without specific prior written permission.
00038   *
00039   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00040   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00041   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00042   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00043   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00044   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00045   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00046   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00047   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00048   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Define to prevent recursive inclusion -------------------------------------*/
00054 #ifndef __STM32L4xx_LL_CORTEX_H
00055 #define __STM32L4xx_LL_CORTEX_H
00056
00057 #ifdef __cplusplus
00058 extern "C" {
00059 #endif
00060
00061 /* Includes ------------------------------------------------------------------*/
00062 #include "stm32l4xx.h"
00063
00064 /** @addtogroup STM32L4xx_LL_Driver
00065   * @{
00066   */
00067
00068 /** @defgroup CORTEX_LL CORTEX
00069   * @{
00070   */
00071
00072 /* Private types -------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074
00075 /* Private constants ---------------------------------------------------------*/
00076
00077 /* Private macros ------------------------------------------------------------*/
00078
00079 /* Exported types ------------------------------------------------------------*/
00080 /* Exported constants --------------------------------------------------------*/
00081 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
00082   * @{
00083   */
00084
00085 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
00086   * @{
00087   */
00088 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     ((uint32_t)0x00000000U)                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
00089 #define LL_SYSTICK_CLKSOURCE_HCLK          ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
00090 /**
00091   * @}
00092   */
00093
00094 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
00095   * @{
00096   */
00097 #define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
00098 #define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
00099 #define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
00100 /**
00101   * @}
00102   */
00103
00104 #if __MPU_PRESENT
00105
00106 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
00107   * @{
00108   */
00109 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     ((uint32_t)0x00000000U)                            /*!< Disable NMI and privileged SW access */
00110 #define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
00111 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
00112 #define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
00113 /**
00114   * @}
00115   */
00116
00117 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
00118   * @{
00119   */
00120 #define LL_MPU_REGION_NUMBER0              ((uint32_t)0x00U) /*!< REGION Number 0 */
00121 #define LL_MPU_REGION_NUMBER1              ((uint32_t)0x01U) /*!< REGION Number 1 */
00122 #define LL_MPU_REGION_NUMBER2              ((uint32_t)0x02U) /*!< REGION Number 2 */
00123 #define LL_MPU_REGION_NUMBER3              ((uint32_t)0x03U) /*!< REGION Number 3 */
00124 #define LL_MPU_REGION_NUMBER4              ((uint32_t)0x04U) /*!< REGION Number 4 */
00125 #define LL_MPU_REGION_NUMBER5              ((uint32_t)0x05U) /*!< REGION Number 5 */
00126 #define LL_MPU_REGION_NUMBER6              ((uint32_t)0x06U) /*!< REGION Number 6 */
00127 #define LL_MPU_REGION_NUMBER7              ((uint32_t)0x07U) /*!< REGION Number 7 */
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
00133   * @{
00134   */
00135 #define LL_MPU_REGION_SIZE_32B             ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
00136 #define LL_MPU_REGION_SIZE_64B             ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
00137 #define LL_MPU_REGION_SIZE_128B            ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
00138 #define LL_MPU_REGION_SIZE_256B            ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
00139 #define LL_MPU_REGION_SIZE_512B            ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
00140 #define LL_MPU_REGION_SIZE_1KB             ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
00141 #define LL_MPU_REGION_SIZE_2KB             ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
00142 #define LL_MPU_REGION_SIZE_4KB             ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
00143 #define LL_MPU_REGION_SIZE_8KB             ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
00144 #define LL_MPU_REGION_SIZE_16KB            ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
00145 #define LL_MPU_REGION_SIZE_32KB            ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
00146 #define LL_MPU_REGION_SIZE_64KB            ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
00147 #define LL_MPU_REGION_SIZE_128KB           ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
00148 #define LL_MPU_REGION_SIZE_256KB           ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
00149 #define LL_MPU_REGION_SIZE_512KB           ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
00150 #define LL_MPU_REGION_SIZE_1MB             ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
00151 #define LL_MPU_REGION_SIZE_2MB             ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
00152 #define LL_MPU_REGION_SIZE_4MB             ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
00153 #define LL_MPU_REGION_SIZE_8MB             ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
00154 #define LL_MPU_REGION_SIZE_16MB            ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
00155 #define LL_MPU_REGION_SIZE_32MB            ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
00156 #define LL_MPU_REGION_SIZE_64MB            ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
00157 #define LL_MPU_REGION_SIZE_128MB           ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
00158 #define LL_MPU_REGION_SIZE_256MB           ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
00159 #define LL_MPU_REGION_SIZE_512MB           ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
00160 #define LL_MPU_REGION_SIZE_1GB             ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
00161 #define LL_MPU_REGION_SIZE_2GB             ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
00162 #define LL_MPU_REGION_SIZE_4GB             ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
00168   * @{
00169   */
00170 #define LL_MPU_REGION_NO_ACCESS            ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
00171 #define LL_MPU_REGION_PRIV_RW              ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
00172 #define LL_MPU_REGION_PRIV_RW_URO          ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
00173 #define LL_MPU_REGION_FULL_ACCESS          ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
00174 #define LL_MPU_REGION_PRIV_RO              ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
00175 #define LL_MPU_REGION_PRIV_RO_URO          ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
00181   * @{
00182   */
00183 #define LL_MPU_TEX_LEVEL0                  ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
00184 #define LL_MPU_TEX_LEVEL1                  ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
00185 #define LL_MPU_TEX_LEVEL2                  ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
00186 #define LL_MPU_TEX_LEVEL4                  ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
00192   * @{
00193   */
00194 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE   ((uint32_t)0x00U) /*!< Instruction fetches enabled */
00195 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
00201   * @{
00202   */
00203 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
00204 #define LL_MPU_ACCESS_NOT_SHAREABLE        ((uint32_t)0x00U) /*!< Not Shareable memory attribute */
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
00210   * @{
00211   */
00212 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
00213 #define LL_MPU_ACCESS_NOT_CACHEABLE        ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
00219   * @{
00220   */
00221 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
00222 #define LL_MPU_ACCESS_NOT_BUFFERABLE       ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */
00223 /**
00224   * @}
00225   */
00226 #endif /* __MPU_PRESENT */
00227 /**
00228   * @}
00229   */
00230
00231 /* Exported macro ------------------------------------------------------------*/
00232
00233 /* Exported functions --------------------------------------------------------*/
00234 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
00235   * @{
00236   */
00237
00238 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
00239   * @{
00240   */
00241
00242 /**
00243   * @brief  This function checks if the Systick counter flag is active or not.
00244   * @note   It can be used in timeout function on application side.
00245   * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
00246   * @retval State of bit (1 or 0).
00247   */
00248 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
00249 {
00250   return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
00251 }
00252
00253 /**
00254   * @brief  Configures the SysTick clock source
00255   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
00256   * @param  Source This parameter can be one of the following values:
00257   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00258   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00259   * @retval None
00260   */
00261 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
00262 {
00263   if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
00264   {
00265     SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00266   }
00267   else
00268   {
00269     CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00270   }
00271 }
00272
00273 /**
00274   * @brief  Get the SysTick clock source
00275   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
00276   * @retval Returned value can be one of the following values:
00277   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00278   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00279   */
00280 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
00281 {
00282   return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00283 }
00284
00285 /**
00286   * @brief  Enable SysTick exception request
00287   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
00288   * @retval None
00289   */
00290 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
00291 {
00292   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00293 }
00294
00295 /**
00296   * @brief  Disable SysTick exception request
00297   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
00298   * @retval None
00299   */
00300 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
00301 {
00302   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00303 }
00304
00305 /**
00306   * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
00307   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
00308   * @retval State of bit (1 or 0).
00309   */
00310 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
00311 {
00312   return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
00313 }
00314
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
00320   * @{
00321   */
00322
00323 /**
00324   * @brief  Processor uses sleep as its low power mode
00325   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
00326   * @retval None
00327   */
00328 __STATIC_INLINE void LL_LPM_EnableSleep(void)
00329 {
00330   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00331   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00332 }
00333
00334 /**
00335   * @brief  Processor uses deep sleep as its low power mode
00336   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
00337   * @retval None
00338   */
00339 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
00340 {
00341   /* Set SLEEPDEEP bit of Cortex System Control Register */
00342   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00343 }
00344
00345 /**
00346   * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
00347   * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
00348   *         empty main application.
00349   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
00350   * @retval None
00351   */
00352 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
00353 {
00354   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00355   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00356 }
00357
00358 /**
00359   * @brief  Do not sleep when returning to Thread mode.
00360   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
00361   * @retval None
00362   */
00363 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
00364 {
00365   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00366   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00367 }
00368
00369 /**
00370   * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
00371   *         processor.
00372   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
00373   * @retval None
00374   */
00375 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
00376 {
00377   /* Set SEVEONPEND bit of Cortex System Control Register */
00378   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00379 }
00380
00381 /**
00382   * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
00383   *         excluded
00384   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
00385   * @retval None
00386   */
00387 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
00388 {
00389   /* Clear SEVEONPEND bit of Cortex System Control Register */
00390   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00391 }
00392
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
00398   * @{
00399   */
00400
00401 /**
00402   * @brief  Enable a fault in System handler control register (SHCSR)
00403   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
00404   * @param  Fault This parameter can be a combination of the following values:
00405   *         @arg @ref LL_HANDLER_FAULT_USG
00406   *         @arg @ref LL_HANDLER_FAULT_BUS
00407   *         @arg @ref LL_HANDLER_FAULT_MEM
00408   * @retval None
00409   */
00410 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
00411 {
00412   /* Enable the system handler fault */
00413   SET_BIT(SCB->SHCSR, Fault);
00414 }
00415
00416 /**
00417   * @brief  Disable a fault in System handler control register (SHCSR)
00418   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
00419   * @param  Fault This parameter can be a combination of the following values:
00420   *         @arg @ref LL_HANDLER_FAULT_USG
00421   *         @arg @ref LL_HANDLER_FAULT_BUS
00422   *         @arg @ref LL_HANDLER_FAULT_MEM
00423   * @retval None
00424   */
00425 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
00426 {
00427   /* Disable the system handler fault */
00428   CLEAR_BIT(SCB->SHCSR, Fault);
00429 }
00430
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
00436   * @{
00437   */
00438
00439 /**
00440   * @brief  Get Implementer code
00441   * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
00442   * @retval Value should be equal to 0x41 for ARM
00443   */
00444 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
00445 {
00446   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
00447 }
00448
00449 /**
00450   * @brief  Get Variant number (The r value in the rnpn product revision identifier)
00451   * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
00452   * @retval Value between 0 and 255 (0x0: revision 0)
00453   */
00454 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
00455 {
00456   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
00457 }
00458
00459 /**
00460   * @brief  Get Constant number
00461   * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
00462   * @retval Value should be equal to 0xF for Cortex-M4 devices
00463   */
00464 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
00465 {
00466   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
00467 }
00468
00469 /**
00470   * @brief  Get Part number
00471   * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
00472   * @retval Value should be equal to 0xC24 for Cortex-M4
00473   */
00474 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
00475 {
00476   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
00477 }
00478
00479 /**
00480   * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
00481   * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
00482   * @retval Value between 0 and 255 (0x1: patch 1)
00483   */
00484 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
00485 {
00486   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
00487 }
00488
00489 /**
00490   * @}
00491   */
00492
00493 #if __MPU_PRESENT
00494 /** @defgroup CORTEX_LL_EF_MPU MPU
00495   * @{
00496   */
00497
00498 /**
00499   * @brief  Enable MPU with input options
00500   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
00501   * @param  Options This parameter can be one of the following values:
00502   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
00503   *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
00504   *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
00505   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
00506   * @retval None
00507   */
00508 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
00509 {
00510   /* Enable the MPU*/
00511   WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
00512   /* Ensure MPU settings take effects */
00513   __DSB();
00514   /* Sequence instruction fetches using update settings */
00515   __ISB();
00516 }
00517
00518 /**
00519   * @brief  Disable MPU
00520   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
00521   * @retval None
00522   */
00523 __STATIC_INLINE void LL_MPU_Disable(void)
00524 {
00525   /* Make sure outstanding transfers are done */
00526   __DMB();
00527   /* Disable MPU*/
00528   WRITE_REG(MPU->CTRL, 0U);
00529 }
00530
00531 /**
00532   * @brief  Check if MPU is enabled or not
00533   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
00534   * @retval State of bit (1 or 0).
00535   */
00536 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
00537 {
00538   return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
00539 }
00540
00541 /**
00542   * @brief  Enable a MPU region
00543   * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
00544   * @param  Region This parameter can be one of the following values:
00545   *         @arg @ref LL_MPU_REGION_NUMBER0
00546   *         @arg @ref LL_MPU_REGION_NUMBER1
00547   *         @arg @ref LL_MPU_REGION_NUMBER2
00548   *         @arg @ref LL_MPU_REGION_NUMBER3
00549   *         @arg @ref LL_MPU_REGION_NUMBER4
00550   *         @arg @ref LL_MPU_REGION_NUMBER5
00551   *         @arg @ref LL_MPU_REGION_NUMBER6
00552   *         @arg @ref LL_MPU_REGION_NUMBER7
00553   * @retval None
00554   */
00555 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
00556 {
00557   /* Set Region number */
00558   WRITE_REG(MPU->RNR, Region);
00559   /* Enable the MPU region */
00560   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00561 }
00562
00563 /**
00564   * @brief  Configure and enable a region
00565   * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
00566   *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
00567   *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
00568   *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
00569   *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
00570   *         MPU_RASR     S             LL_MPU_ConfigRegion\n
00571   *         MPU_RASR     C             LL_MPU_ConfigRegion\n
00572   *         MPU_RASR     B             LL_MPU_ConfigRegion\n
00573   *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
00574   * @param  Region This parameter can be one of the following values:
00575   *         @arg @ref LL_MPU_REGION_NUMBER0
00576   *         @arg @ref LL_MPU_REGION_NUMBER1
00577   *         @arg @ref LL_MPU_REGION_NUMBER2
00578   *         @arg @ref LL_MPU_REGION_NUMBER3
00579   *         @arg @ref LL_MPU_REGION_NUMBER4
00580   *         @arg @ref LL_MPU_REGION_NUMBER5
00581   *         @arg @ref LL_MPU_REGION_NUMBER6
00582   *         @arg @ref LL_MPU_REGION_NUMBER7
00583   * @param  Address Value of region base address
00584   * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
00585   * @param  Attributes This parameter can be a combination of the following values:
00586   *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
00587   *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
00588   *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
00589   *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
00590   *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
00591   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
00592   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
00593   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
00594   *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
00595   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
00596   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
00597   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
00598   *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
00599   * @retval None
00600   */
00601 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
00602 {
00603   /* Set Region number */
00604   WRITE_REG(MPU->RNR, Region);
00605   /* Set base address */
00606   WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
00607   /* Configure MPU */
00608   WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
00609 }
00610
00611 /**
00612   * @brief  Disable a region
00613   * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
00614   *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
00615   * @param  Region This parameter can be one of the following values:
00616   *         @arg @ref LL_MPU_REGION_NUMBER0
00617   *         @arg @ref LL_MPU_REGION_NUMBER1
00618   *         @arg @ref LL_MPU_REGION_NUMBER2
00619   *         @arg @ref LL_MPU_REGION_NUMBER3
00620   *         @arg @ref LL_MPU_REGION_NUMBER4
00621   *         @arg @ref LL_MPU_REGION_NUMBER5
00622   *         @arg @ref LL_MPU_REGION_NUMBER6
00623   *         @arg @ref LL_MPU_REGION_NUMBER7
00624   * @retval None
00625   */
00626 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
00627 {
00628   /* Set Region number */
00629   WRITE_REG(MPU->RNR, Region);
00630   /* Disable the MPU region */
00631   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00632 }
00633
00634 /**
00635   * @}
00636   */
00637
00638 #endif /* __MPU_PRESENT */
00639 /**
00640   * @}
00641   */
00642
00643 /**
00644   * @}
00645   */
00646
00647 /**
00648   * @}
00649   */
00650
00651 #ifdef __cplusplus
00652 }
00653 #endif
00654
00655 #endif /* __STM32L4xx_LL_CORTEX_H */
00656
00657 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_crc.c Source File

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stm32l4xx_ll_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_crc.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   CRC LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_crc.h"
00041 #include "stm32l4xx_ll_bus.h"
00042
00043 #ifdef  USE_FULL_ASSERT
00044 #include "stm32_assert.h"
00045 #else
00046 #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (CRC)
00054
00055 /** @addtogroup CRC_LL
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064
00065 /* Exported functions --------------------------------------------------------*/
00066 /** @addtogroup CRC_LL_Exported_Functions
00067   * @{
00068   */
00069
00070 /** @addtogroup CRC_LL_EF_Init
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  De-initialize CRC registers (Registers restored to their default values).
00076   * @param  CRCx CRC Instance
00077   * @retval An ErrorStatus enumeration value:
00078   *          - SUCCESS: CRC registers are de-initialized
00079   *          - ERROR: CRC registers are not de-initialized
00080   */
00081 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
00082 {
00083   ErrorStatus status = SUCCESS;
00084
00085   /* Check the parameters */
00086   assert_param(IS_CRC_ALL_INSTANCE(CRCx));
00087
00088   if (CRCx == CRC)
00089   {
00090     /* Force CRC reset */
00091     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
00092
00093     /* Release CRC reset */
00094     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
00095   }
00096   else
00097   {
00098     status = ERROR;
00099   }
00100
00101   return (status);
00102 }
00103
00104 /**
00105   * @}
00106   */
00107
00108 /**
00109   * @}
00110   */
00111
00112 /**
00113   * @}
00114   */
00115
00116 #endif /* defined (CRC) */
00117
00118 /**
00119   * @}
00120   */
00121
00122 #endif /* USE_FULL_LL_DRIVER */
00123
00124 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00125
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_crc.h Source File

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stm32l4xx_ll_crc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_crc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of CRC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_CRC_H
00040 #define __STM32L4xx_LL_CRC_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(CRC)
00054
00055 /** @defgroup CRC_LL CRC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063
00064 /* Exported types ------------------------------------------------------------*/
00065 /* Exported constants --------------------------------------------------------*/
00066 /** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
00067   * @{
00068   */
00069
00070 /** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
00071   * @{
00072   */
00073 #define LL_CRC_POLYLENGTH_32B              (uint32_t)0x00000000U                    /*!< 32 bits Polynomial size */
00074 #define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
00075 #define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
00076 #define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
00082   * @{
00083   */
00084 #define LL_CRC_INDATA_REVERSE_NONE         (uint32_t)0x00000000U                    /*!< Input Data bit order not affected */
00085 #define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
00086 #define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
00087 #define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
00088 /**
00089   * @}
00090   */
00091
00092 /** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
00093   * @{
00094   */
00095 #define LL_CRC_OUTDATA_REVERSE_NONE        (uint32_t)0x00000000U                     /*!< Output Data bit order not affected */
00096 #define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
00097 /**
00098   * @}
00099   */
00100
00101 /** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
00102   * @brief    Normal representation of this polynomial value is
00103   *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
00104   * @{
00105   */
00106 #define LL_CRC_DEFAULT_CRC32_POLY          (uint32_t)0x04C11DB7U                     /*!< Default CRC generating polynomial value */
00107 /**
00108   * @}
00109   */
00110
00111 /** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
00112   * @{
00113   */
00114 #define LL_CRC_DEFAULT_CRC_INITVALUE       (uint32_t)0xFFFFFFFFU                     /*!< Default CRC computation initialization value */
00115 /**
00116   * @}
00117   */
00118
00119 /**
00120   * @}
00121   */
00122
00123 /* Exported macro ------------------------------------------------------------*/
00124 /** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
00125   * @{
00126   */
00127
00128 /** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  Write a value in CRC register
00134   * @param  __INSTANCE__ CRC Instance
00135   * @param  __REG__ Register to be written
00136   * @param  __VALUE__ Value to be written in the register
00137   * @retval None
00138   */
00139 #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00140
00141 /**
00142   * @brief  Read a value in CRC register
00143   * @param  __INSTANCE__ CRC Instance
00144   * @param  __REG__ Register to be read
00145   * @retval Register value
00146   */
00147 #define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00148 /**
00149   * @}
00150   */
00151
00152 /**
00153   * @}
00154   */
00155
00156
00157 /* Exported functions --------------------------------------------------------*/
00158 /** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
00159   * @{
00160   */
00161
00162 /** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
00163   * @{
00164   */
00165
00166 /**
00167   * @brief  Reset the CRC calculation unit.
00168   * @note   If Programmable Initial CRC value feature
00169   *         is available, also set the Data Register to the value stored in the
00170   *         CRC_INIT register, otherwise, reset Data Register to its default value.
00171   * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
00172   * @param  CRCx CRC Instance
00173   * @retval None
00174   */
00175 __STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
00176 {
00177   SET_BIT(CRCx->CR, CRC_CR_RESET);
00178 }
00179
00180 /**
00181   * @brief  Configure size of the polynomial.
00182   * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
00183   * @param  CRCx CRC Instance
00184   * @param  PolySize This parameter can be one of the following values:
00185   *         @arg @ref LL_CRC_POLYLENGTH_32B
00186   *         @arg @ref LL_CRC_POLYLENGTH_16B
00187   *         @arg @ref LL_CRC_POLYLENGTH_8B
00188   *         @arg @ref LL_CRC_POLYLENGTH_7B
00189   * @retval None
00190   */
00191 __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
00192 {
00193   MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
00194 }
00195
00196 /**
00197   * @brief  Return size of the polynomial.
00198   * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
00199   * @param  CRCx CRC Instance
00200   * @retval Returned value can be one of the following values:
00201   *         @arg @ref LL_CRC_POLYLENGTH_32B
00202   *         @arg @ref LL_CRC_POLYLENGTH_16B
00203   *         @arg @ref LL_CRC_POLYLENGTH_8B
00204   *         @arg @ref LL_CRC_POLYLENGTH_7B
00205   */
00206 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
00207 {
00208   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
00209 }
00210
00211 /**
00212   * @brief  Configure the reversal of the bit order of the input data
00213   * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
00214   * @param  CRCx CRC Instance
00215   * @param  ReverseMode This parameter can be one of the following values:
00216   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00217   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00218   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00219   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00220   * @retval None
00221   */
00222 __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00223 {
00224   MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
00225 }
00226
00227 /**
00228   * @brief  Return type of reversal for input data bit order
00229   * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
00230   * @param  CRCx CRC Instance
00231   * @retval Returned value can be one of the following values:
00232   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00233   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00234   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00235   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00236   */
00237 __STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
00238 {
00239   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
00240 }
00241
00242 /**
00243   * @brief  Configure the reversal of the bit order of the Output data
00244   * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
00245   * @param  CRCx CRC Instance
00246   * @param  ReverseMode This parameter can be one of the following values:
00247   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00248   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00249   * @retval None
00250   */
00251 __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00252 {
00253   MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
00254 }
00255
00256 /**
00257   * @brief  Configure the reversal of the bit order of the Output data
00258   * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
00259   * @param  CRCx CRC Instance
00260   * @retval Returned value can be one of the following values:
00261   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00262   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00263   */
00264 __STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
00265 {
00266   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
00267 }
00268
00269 /**
00270   * @brief  Initialize the Programmable initial CRC value.
00271   * @note   If the CRC size is less than 32 bits, the least significant bits
00272   *         are used to write the correct value
00273   * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
00274   * @rmtoll INIT         INIT          LL_CRC_SetInitialData
00275   * @param  CRCx CRC Instance
00276   * @param  InitCrc Value to be programmed in Programmable initial CRC value register
00277   * @retval None
00278   */
00279 __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
00280 {
00281   WRITE_REG(CRCx->INIT, InitCrc);
00282 }
00283
00284 /**
00285   * @brief  Return current Initial CRC value.
00286   * @note   If the CRC size is less than 32 bits, the least significant bits
00287   *         are used to read the correct value
00288   * @rmtoll INIT         INIT          LL_CRC_GetInitialData
00289   * @param  CRCx CRC Instance
00290   * @retval Value programmed in Programmable initial CRC value register
00291   */
00292 __STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
00293 {
00294   return (uint32_t)(READ_REG(CRCx->INIT));
00295 }
00296
00297 /**
00298   * @brief  Initialize the Programmable polynomial value
00299   *         (coefficients of the polynomial to be used for CRC calculation).
00300   * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
00301   * @note   Please check Reference Manual and existing Errata Sheets,
00302   *         regarding possible limitations for Polynomial values usage.
00303   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00304   * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
00305   * @param  CRCx CRC Instance
00306   * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
00307   * @retval None
00308   */
00309 __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
00310 {
00311   WRITE_REG(CRCx->POL, PolynomCoef);
00312 }
00313
00314 /**
00315   * @brief  Return current Programmable polynomial value
00316   * @note   Please check Reference Manual and existing Errata Sheets,
00317   *         regarding possible limitations for Polynomial values usage.
00318   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00319   * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
00320   * @param  CRCx CRC Instance
00321   * @retval Value programmed in Programmable Polynomial value register
00322   */
00323 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
00324 {
00325   return (uint32_t)(READ_REG(CRCx->POL));
00326 }
00327
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup CRC_LL_EF_Data_Management Data_Management
00333   * @{
00334   */
00335
00336 /**
00337   * @brief  Write given 32-bit data to the CRC calculator
00338   * @rmtoll DR           DR            LL_CRC_FeedData32
00339   * @param  CRCx CRC Instance
00340   * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
00341   * @retval None
00342   */
00343 __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
00344 {
00345   WRITE_REG(CRCx->DR, InData);
00346 }
00347
00348 /**
00349   * @brief  Write given 16-bit data to the CRC calculator
00350   * @rmtoll DR           DR            LL_CRC_FeedData16
00351   * @param  CRCx CRC Instance
00352   * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
00353   * @retval None
00354   */
00355 __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
00356 {
00357   *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
00358 }
00359
00360 /**
00361   * @brief  Write given 8-bit data to the CRC calculator
00362   * @rmtoll DR           DR            LL_CRC_FeedData8
00363   * @param  CRCx CRC Instance
00364   * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
00365   * @retval None
00366   */
00367 __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
00368 {
00369   *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
00370 }
00371
00372 /**
00373   * @brief  Return current CRC calculation result. 32 bits value is returned.
00374   * @rmtoll DR           DR            LL_CRC_ReadData32
00375   * @param  CRCx CRC Instance
00376   * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
00377   */
00378 __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
00379 {
00380   return (uint32_t)(READ_REG(CRCx->DR));
00381 }
00382
00383 /**
00384   * @brief  Return current CRC calculation result. 16 bits value is returned.
00385   * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
00386   * @rmtoll DR           DR            LL_CRC_ReadData16
00387   * @param  CRCx CRC Instance
00388   * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
00389   */
00390 __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
00391 {
00392   return (uint16_t)READ_REG(CRCx->DR);
00393 }
00394
00395 /**
00396   * @brief  Return current CRC calculation result. 8 bits value is returned.
00397   * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
00398   * @rmtoll DR           DR            LL_CRC_ReadData8
00399   * @param  CRCx CRC Instance
00400   * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
00401   */
00402 __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
00403 {
00404   return (uint8_t)READ_REG(CRCx->DR);
00405 }
00406
00407 /**
00408   * @brief  Return current CRC calculation result. 7 bits value is returned.
00409   * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
00410   * @rmtoll DR           DR            LL_CRC_ReadData7
00411   * @param  CRCx CRC Instance
00412   * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
00413   */
00414 __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
00415 {
00416   return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
00417 }
00418
00419 /**
00420   * @brief  Return data stored in the Independent Data(IDR) register.
00421   * @note   This register can be used as a temporary storage location for one byte.
00422   * @rmtoll IDR          IDR           LL_CRC_Read_IDR
00423   * @param  CRCx CRC Instance
00424   * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
00425   */
00426 __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
00427 {
00428   return (uint32_t)(READ_REG(CRCx->IDR));
00429 }
00430
00431 /**
00432   * @brief  Store data in the Independent Data(IDR) register.
00433   * @note   This register can be used as a temporary storage location for one byte.
00434   * @rmtoll IDR          IDR           LL_CRC_Write_IDR
00435   * @param  CRCx CRC Instance
00436   * @param  InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
00437   * @retval None
00438   */
00439 __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
00440 {
00441   *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
00442 }
00443 /**
00444   * @}
00445   */
00446
00447 #if defined(USE_FULL_LL_DRIVER)
00448 /** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
00449   * @{
00450   */
00451
00452 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
00453
00454 /**
00455   * @}
00456   */
00457 #endif /* USE_FULL_LL_DRIVER */
00458
00459 /**
00460   * @}
00461   */
00462
00463 /**
00464   * @}
00465   */
00466
00467 #endif /* defined(CRC) */
00468
00469 /**
00470   * @}
00471   */
00472
00473 #ifdef __cplusplus
00474 }
00475 #endif
00476
00477 #endif /* __STM32L4xx_LL_CRC_H */
00478
00479 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_crs.c Source File

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stm32l4xx_ll_crs.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   CRS LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_crs.h"
00041 #include "stm32l4xx_ll_bus.h"
00042
00043 /** @addtogroup STM32L4xx_LL_Driver
00044   * @{
00045   */
00046
00047 #if defined(CRS)
00048
00049 /** @defgroup CRS_LL CRS
00050   * @{
00051   */
00052
00053 /* Private types -------------------------------------------------------------*/
00054 /* Private variables ---------------------------------------------------------*/
00055 /* Private constants ---------------------------------------------------------*/
00056 /* Private macros ------------------------------------------------------------*/
00057 /* Private function prototypes -----------------------------------------------*/
00058
00059 /* Exported functions --------------------------------------------------------*/
00060 /** @addtogroup CRS_LL_Exported_Functions
00061   * @{
00062   */
00063
00064 /** @addtogroup CRS_LL_EF_Init
00065   * @{
00066   */
00067
00068 /**
00069   * @brief  De-Initializes CRS peripheral registers to their default reset values.
00070   * @retval An ErrorStatus enumeration value:
00071   *          - SUCCESS: CRS registers are de-initialized
00072   *          - ERROR: not applicable
00073   */
00074 ErrorStatus LL_CRS_DeInit(void)
00075 {
00076   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
00077   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
00078
00079   return  SUCCESS;
00080 }
00081
00082
00083
00084 /**
00085   * @}
00086   */
00087
00088 /**
00089   * @}
00090   */
00091
00092 /**
00093   * @}
00094   */
00095
00096 #endif /* defined(CRS) */
00097
00098 /**
00099   * @}
00100   */
00101
00102 #endif /* USE_FULL_LL_DRIVER */
00103
00104 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_crs.h Source File

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stm32l4xx_ll_crs.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of CRS LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_CRS_H
00040 #define __STM32L4xx_LL_CRS_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(CRS)
00054
00055 /** @defgroup CRS_LL CRS
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
00064   * @{
00065   */
00066
00067 /* Defines used for the bit position in the register and perform offsets*/
00068 #define CRS_POSITION_TRIM        (uint32_t)POSITION_VAL(CRS_CR_TRIM)    /* bit position in CR reg */
00069 #define CRS_POSITION_FECAP       (uint32_t)POSITION_VAL(CRS_ISR_FECAP)  /* bit position in ISR reg */
00070 #define CRS_POSITION_FELIM       (uint32_t)POSITION_VAL(CRS_CFGR_FELIM) /* bit position in CFGR reg */
00071
00072
00073 /**
00074   * @}
00075   */
00076
00077 /* Private macros ------------------------------------------------------------*/
00078
00079 /* Exported types ------------------------------------------------------------*/
00080 /* Exported constants --------------------------------------------------------*/
00081 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
00082   * @{
00083   */
00084
00085 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
00086   * @brief    Flags defines which can be used with LL_CRS_ReadReg function
00087   * @{
00088   */
00089 #define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
00090 #define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
00091 #define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
00092 #define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
00093 #define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
00094 #define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
00095 #define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
00096 /**
00097   * @}
00098   */
00099
00100 /** @defgroup CRS_LL_EC_IT IT Defines
00101   * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
00102   * @{
00103   */
00104 #define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
00105 #define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
00106 #define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
00107 #define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
00113   * @{
00114   */
00115 #define LL_CRS_SYNC_DIV_1                  ((uint32_t)0x00U)                         /*!< Synchro Signal not divided (default) */
00116 #define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
00117 #define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
00118 #define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
00119 #define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
00120 #define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
00121 #define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
00122 #define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
00123 /**
00124   * @}
00125   */
00126
00127 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
00128   * @{
00129   */
00130 #define LL_CRS_SYNC_SOURCE_GPIO            ((uint32_t)0x00U)       /*!< Synchro Signal soucre GPIO */
00131 #define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
00132 #define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
00138   * @{
00139   */
00140 #define LL_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00U)     /*!< Synchro Active on rising edge (default) */
00141 #define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
00147   * @{
00148   */
00149 #define LL_CRS_FREQ_ERROR_DIR_UP             ((uint32_t)0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
00150 #define LL_CRS_FREQ_ERROR_DIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
00156   * @{
00157   */
00158 /**
00159   * @brief Reset value of the RELOAD field
00160   * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
00161   *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
00162   */
00163 #define LL_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7FU)
00164
00165 /**
00166   * @brief Reset value of Frequency error limit.
00167   */
00168 #define LL_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22U)
00169
00170 /**
00171   * @brief Reset value of the HSI48 Calibration field
00172   * @note The default value is 32, which corresponds to the middle of the trimming interval.
00173   *       The trimming step is around 67 kHz between two consecutive TRIM steps.
00174   *       A higher TRIM value corresponds to a higher output frequency
00175   */
00176 #define LL_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x20U)
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /* Exported macro ------------------------------------------------------------*/
00186 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
00187   * @{
00188   */
00189
00190 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
00191   * @{
00192   */
00193
00194 /**
00195   * @brief  Write a value in CRS register
00196   * @param  __INSTANCE__ CRS Instance
00197   * @param  __REG__ Register to be written
00198   * @param  __VALUE__ Value to be written in the register
00199   * @retval None
00200   */
00201 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00202
00203 /**
00204   * @brief  Read a value in CRS register
00205   * @param  __INSTANCE__ CRS Instance
00206   * @param  __REG__ Register to be read
00207   * @retval Register value
00208   */
00209 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
00215   * @{
00216   */
00217
00218 /**
00219   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
00220   * @note   The RELOAD value should be selected according to the ratio between
00221   *         the target frequency and the frequency of the synchronization source after
00222   *         prescaling. It is then decreased by one in order to reach the expected
00223   *         synchronization on the zero value. The formula is the following:
00224   *              RELOAD = (fTARGET / fSYNC) -1
00225   * @param  __FTARGET__ Target frequency (value in Hz)
00226   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
00227   * @retval Reload value (in Hz)
00228   */
00229 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
00230
00231 /**
00232   * @}
00233   */
00234
00235 /**
00236   * @}
00237   */
00238
00239 /* Exported functions --------------------------------------------------------*/
00240 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
00241   * @{
00242   */
00243
00244 /** @defgroup CRS_LL_EF_Configuration Configuration
00245   * @{
00246   */
00247
00248 /**
00249   * @brief  Enable Frequency error counter
00250   * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
00251   * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
00252   * @retval None
00253   */
00254 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
00255 {
00256   SET_BIT(CRS->CR, CRS_CR_CEN);
00257 }
00258
00259 /**
00260   * @brief  Disable Frequency error counter
00261   * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
00262   * @retval None
00263   */
00264 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
00265 {
00266   CLEAR_BIT(CRS->CR, CRS_CR_CEN);
00267 }
00268
00269 /**
00270   * @brief  Check if Frequency error counter is enabled or not
00271   * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
00272   * @retval State of bit (1 or 0).
00273   */
00274 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
00275 {
00276   return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
00277 }
00278
00279 /**
00280   * @brief  Enable Automatic trimming counter
00281   * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
00282   * @retval None
00283   */
00284 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
00285 {
00286   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00287 }
00288
00289 /**
00290   * @brief  Disable Automatic trimming counter
00291   * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
00292   * @retval None
00293   */
00294 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
00295 {
00296   CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00297 }
00298
00299 /**
00300   * @brief  Check if Automatic trimming is enabled or not
00301   * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
00302   * @retval State of bit (1 or 0).
00303   */
00304 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
00305 {
00306   return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
00307 }
00308
00309 /**
00310   * @brief  Set HSI48 oscillator smooth trimming
00311   * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
00312   * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
00313   * @param  Value a number between Min_Data = 0 and Max_Data = 63
00314   * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
00315   * @retval None
00316   */
00317 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
00318 {
00319   MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
00320 }
00321
00322 /**
00323   * @brief  Get HSI48 oscillator smooth trimming
00324   * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
00325   * @retval a number between Min_Data = 0 and Max_Data = 63
00326   */
00327 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
00328 {
00329   return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
00330 }
00331
00332 /**
00333   * @brief  Set counter reload value
00334   * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
00335   * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
00336   * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
00337   *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
00338   * @retval None
00339   */
00340 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
00341 {
00342   MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
00343 }
00344
00345 /**
00346   * @brief  Get counter reload value
00347   * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
00348   * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
00349   */
00350 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
00351 {
00352   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
00353 }
00354
00355 /**
00356   * @brief  Set frequency error limit
00357   * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
00358   * @param  Value a number between Min_Data = 0 and Max_Data = 255
00359   * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
00360   * @retval None
00361   */
00362 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
00363 {
00364   MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
00365 }
00366
00367 /**
00368   * @brief  Get frequency error limit
00369   * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
00370   * @retval A number between Min_Data = 0 and Max_Data = 255
00371   */
00372 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
00373 {
00374   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
00375 }
00376
00377 /**
00378   * @brief  Set division factor for SYNC signal
00379   * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
00380   * @param  Divider This parameter can be one of the following values:
00381   *         @arg @ref LL_CRS_SYNC_DIV_1
00382   *         @arg @ref LL_CRS_SYNC_DIV_2
00383   *         @arg @ref LL_CRS_SYNC_DIV_4
00384   *         @arg @ref LL_CRS_SYNC_DIV_8
00385   *         @arg @ref LL_CRS_SYNC_DIV_16
00386   *         @arg @ref LL_CRS_SYNC_DIV_32
00387   *         @arg @ref LL_CRS_SYNC_DIV_64
00388   *         @arg @ref LL_CRS_SYNC_DIV_128
00389   * @retval None
00390   */
00391 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
00392 {
00393   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
00394 }
00395
00396 /**
00397   * @brief  Get division factor for SYNC signal
00398   * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
00399   * @retval Returned value can be one of the following values:
00400   *         @arg @ref LL_CRS_SYNC_DIV_1
00401   *         @arg @ref LL_CRS_SYNC_DIV_2
00402   *         @arg @ref LL_CRS_SYNC_DIV_4
00403   *         @arg @ref LL_CRS_SYNC_DIV_8
00404   *         @arg @ref LL_CRS_SYNC_DIV_16
00405   *         @arg @ref LL_CRS_SYNC_DIV_32
00406   *         @arg @ref LL_CRS_SYNC_DIV_64
00407   *         @arg @ref LL_CRS_SYNC_DIV_128
00408   */
00409 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
00410 {
00411   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
00412 }
00413
00414 /**
00415   * @brief  Set SYNC signal source
00416   * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
00417   * @param  Source This parameter can be one of the following values:
00418   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00419   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00420   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00421   * @retval None
00422   */
00423 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
00424 {
00425   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
00426 }
00427
00428 /**
00429   * @brief  Get SYNC signal source
00430   * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
00431   * @retval Returned value can be one of the following values:
00432   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00433   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00434   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00435   */
00436 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
00437 {
00438   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
00439 }
00440
00441 /**
00442   * @brief  Set input polarity for the SYNC signal source
00443   * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
00444   * @param  Polarity This parameter can be one of the following values:
00445   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00446   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00447   * @retval None
00448   */
00449 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
00450 {
00451   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
00452 }
00453
00454 /**
00455   * @brief  Get input polarity for the SYNC signal source
00456   * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
00457   * @retval Returned value can be one of the following values:
00458   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00459   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00460   */
00461 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
00462 {
00463   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
00464 }
00465
00466 /**
00467   * @brief  Configure CRS for the synchronization
00468   * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
00469   *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
00470   *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
00471   *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
00472   *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
00473   *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
00474   * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
00475   * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
00476   * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
00477   * @param  Settings This parameter can be a combination of the following values:
00478   *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
00479   *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
00480   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
00481   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
00482   * @retval None
00483   */
00484 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
00485 {
00486   MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
00487   MODIFY_REG(CRS->CFGR,
00488              CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
00489              ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
00490 }
00491
00492 /**
00493   * @}
00494   */
00495
00496 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
00497   * @{
00498   */
00499
00500 /**
00501   * @brief  Generate software SYNC event
00502   * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
00503   * @retval None
00504   */
00505 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
00506 {
00507   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
00508 }
00509
00510 /**
00511   * @brief  Get the frequency error direction latched in the time of the last
00512   * SYNC event
00513   * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
00514   * @retval Returned value can be one of the following values:
00515   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
00516   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
00517   */
00518 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
00519 {
00520   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
00521 }
00522
00523 /**
00524   * @brief  Get the frequency error counter value latched in the time of the last SYNC event
00525   * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
00526   * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
00527   */
00528 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
00529 {
00530   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
00531 }
00532
00533 /**
00534   * @}
00535   */
00536
00537 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
00538   * @{
00539   */
00540
00541 /**
00542   * @brief  Check if SYNC event OK signal occurred or not
00543   * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
00544   * @retval State of bit (1 or 0).
00545   */
00546 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
00547 {
00548   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
00549 }
00550
00551 /**
00552   * @brief  Check if SYNC warning signal occurred or not
00553   * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
00554   * @retval State of bit (1 or 0).
00555   */
00556 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
00557 {
00558   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
00559 }
00560
00561 /**
00562   * @brief  Check if Synchronization or trimming error signal occurred or not
00563   * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
00564   * @retval State of bit (1 or 0).
00565   */
00566 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
00567 {
00568   return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
00569 }
00570
00571 /**
00572   * @brief  Check if Expected SYNC signal occurred or not
00573   * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
00574   * @retval State of bit (1 or 0).
00575   */
00576 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
00577 {
00578   return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
00579 }
00580
00581 /**
00582   * @brief  Check if SYNC error signal occurred or not
00583   * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
00584   * @retval State of bit (1 or 0).
00585   */
00586 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
00587 {
00588   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
00589 }
00590
00591 /**
00592   * @brief  Check if SYNC missed error signal occurred or not
00593   * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
00594   * @retval State of bit (1 or 0).
00595   */
00596 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
00597 {
00598   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
00599 }
00600
00601 /**
00602   * @brief  Check if Trimming overflow or underflow occurred or not
00603   * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
00604   * @retval State of bit (1 or 0).
00605   */
00606 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
00607 {
00608   return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
00609 }
00610
00611 /**
00612   * @brief  Clear the SYNC event OK flag
00613   * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
00617 {
00618   WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
00619 }
00620
00621 /**
00622   * @brief  Clear the  SYNC warning flag
00623   * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
00624   * @retval None
00625   */
00626 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
00627 {
00628   WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
00629 }
00630
00631 /**
00632   * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
00633   * the ERR flag
00634   * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
00635   * @retval None
00636   */
00637 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
00638 {
00639   WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
00640 }
00641
00642 /**
00643   * @brief  Clear Expected SYNC flag
00644   * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
00645   * @retval None
00646   */
00647 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
00648 {
00649   WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
00650 }
00651
00652 /**
00653   * @}
00654   */
00655
00656 /** @defgroup CRS_LL_EF_IT_Management IT_Management
00657   * @{
00658   */
00659
00660 /**
00661   * @brief  Enable SYNC event OK interrupt
00662   * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
00663   * @retval None
00664   */
00665 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
00666 {
00667   SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00668 }
00669
00670 /**
00671   * @brief  Disable SYNC event OK interrupt
00672   * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
00673   * @retval None
00674   */
00675 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
00676 {
00677   CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00678 }
00679
00680 /**
00681   * @brief  Check if SYNC event OK interrupt is enabled or not
00682   * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
00683   * @retval State of bit (1 or 0).
00684   */
00685 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
00686 {
00687   return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
00688 }
00689
00690 /**
00691   * @brief  Enable SYNC warning interrupt
00692   * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
00693   * @retval None
00694   */
00695 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
00696 {
00697   SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00698 }
00699
00700 /**
00701   * @brief  Disable SYNC warning interrupt
00702   * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
00703   * @retval None
00704   */
00705 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
00706 {
00707   CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00708 }
00709
00710 /**
00711   * @brief  Check if SYNC warning interrupt is enabled or not
00712   * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
00713   * @retval State of bit (1 or 0).
00714   */
00715 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
00716 {
00717   return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
00718 }
00719
00720 /**
00721   * @brief  Enable Synchronization or trimming error interrupt
00722   * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
00723   * @retval None
00724   */
00725 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
00726 {
00727   SET_BIT(CRS->CR, CRS_CR_ERRIE);
00728 }
00729
00730 /**
00731   * @brief  Disable Synchronization or trimming error interrupt
00732   * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
00733   * @retval None
00734   */
00735 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
00736 {
00737   CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
00738 }
00739
00740 /**
00741   * @brief  Check if Synchronization or trimming error interrupt is enabled or not
00742   * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
00743   * @retval State of bit (1 or 0).
00744   */
00745 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
00746 {
00747   return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
00748 }
00749
00750 /**
00751   * @brief  Enable Expected SYNC interrupt
00752   * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
00753   * @retval None
00754   */
00755 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
00756 {
00757   SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
00758 }
00759
00760 /**
00761   * @brief  Disable Expected SYNC interrupt
00762   * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
00763   * @retval None
00764   */
00765 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
00766 {
00767   CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
00768 }
00769
00770 /**
00771   * @brief  Check if Expected SYNC interrupt is enabled or not
00772   * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
00773   * @retval State of bit (1 or 0).
00774   */
00775 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
00776 {
00777   return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
00778 }
00779
00780 /**
00781   * @}
00782   */
00783
00784 #if defined(USE_FULL_LL_DRIVER)
00785 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
00786   * @{
00787   */
00788
00789 ErrorStatus LL_CRS_DeInit(void);
00790
00791 /**
00792   * @}
00793   */
00794 #endif /* USE_FULL_LL_DRIVER */
00795
00796 /**
00797   * @}
00798   */
00799
00800 /**
00801   * @}
00802   */
00803
00804 #endif /* defined(CRS) */
00805
00806 /**
00807   * @}
00808   */
00809
00810 #ifdef __cplusplus
00811 }
00812 #endif
00813
00814 #endif /* __STM32L4xx_LL_CRS_H */
00815
00816 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_dac.c Source File

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stm32l4xx_ll_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_dac.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   DAC LL module driver
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_dac.h"
00041 #include "stm32l4xx_ll_bus.h"
00042
00043 #ifdef  USE_FULL_ASSERT
00044   #include "stm32_assert.h"
00045 #else
00046   #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (DAC1)
00054
00055 /** @addtogroup DAC_LL DAC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063
00064 /** @addtogroup DAC_LL_Private_Macros
00065   * @{
00066   */
00067
00068 #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                           \
00069   (                                                                            \
00070       ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                  \
00071    || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                                  \
00072   )
00073
00074 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00075   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00076    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00077    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
00078    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO)                      \
00079    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00080    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
00081    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)                      \
00082    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00083   )
00084
00085 #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)           \
00086   (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)     \
00087    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
00088    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
00089   )
00090
00091 #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__)      \
00092   (   ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)     \
00093    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)  \
00094    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)  \
00095    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)  \
00096    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)  \
00097    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)  \
00098    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)  \
00099    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)  \
00100    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)  \
00101    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)  \
00102    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
00103    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
00104    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)       \
00105    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)       \
00106    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)       \
00107    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)      \
00108    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)      \
00109    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)      \
00110    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)     \
00111    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)     \
00112    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)     \
00113    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)    \
00114    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)    \
00115    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)    \
00116   )
00117
00118 #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
00119   (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
00120    || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
00121   )
00122
00123 #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)                     \
00124   (   ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                  \
00125    || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)              \
00126   )
00127
00128 #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)                                 \
00129   (   ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                         \
00130    || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)                \
00131   )
00132
00133 /**
00134   * @}
00135   */
00136
00137
00138 /* Private function prototypes -----------------------------------------------*/
00139
00140 /* Exported functions --------------------------------------------------------*/
00141 /** @addtogroup DAC_LL_Exported_Functions
00142   * @{
00143   */
00144
00145 /** @addtogroup DAC_LL_EF_Init
00146   * @{
00147   */
00148
00149 /**
00150   * @brief  De-initialize registers of the selected DAC instance
00151   *         to their default reset values.
00152   * @param  DACx DAC instance
00153   * @retval An ErrorStatus enumeration value:
00154   *          - SUCCESS: DAC registers are de-initialized
00155   *          - ERROR: not applicable
00156   */
00157 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
00158 {
00159   /* Check the parameters */
00160   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00161
00162   /* Force reset of DAC clock */
00163   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
00164
00165   /* Release reset of DAC clock */
00166   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
00167
00168   return SUCCESS;
00169 }
00170
00171 /**
00172   * @brief  Initialize some features of DAC instance.
00173   * @note   The setting of these parameters by function @ref LL_DAC_Init()
00174   *         is conditioned to DAC state:
00175   *         DAC instance must be disabled.
00176   * @param  DACx DAC instance
00177   * @param  DAC_Channel This parameter can be one of the following values:
00178   *         @arg @ref LL_DAC_CHANNEL_1
00179   *         @arg @ref LL_DAC_CHANNEL_2
00180   * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
00181   * @retval An ErrorStatus enumeration value:
00182   *          - SUCCESS: DAC registers are initialized
00183   *          - ERROR: DAC registers are not initialized
00184   */
00185 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
00186 {
00187   ErrorStatus status = SUCCESS;
00188
00189   /* Check the parameters */
00190   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00191   assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
00192   assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
00193   assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
00194   assert_param(IS_LL_DAC_OUTPUT_CONNECTION(DAC_InitStruct->OutputConnection));
00195   assert_param(IS_LL_DAC_OUTPUT_MODE(DAC_InitStruct->OutputMode));
00196   assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
00197   if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00198   {
00199     assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
00200   }
00201
00202   /* Note: Hardware constraint (refer to description of this function)        */
00203   /*       DAC instance must be disabled.                                     */
00204   if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
00205   {
00206     /* Configuration of DAC channel:                                          */
00207     /*  - TriggerSource                                                       */
00208     /*  - WaveAutoGeneration                                                  */
00209     /*  - OutputBuffer                                                        */
00210     /*  - OutputConnection                                                    */
00211     /*  - OutputMode                                                          */
00212     if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00213     {
00214       MODIFY_REG(DACx->CR,
00215                  (  DAC_CR_TSEL1
00216                   | DAC_CR_WAVE1
00217                   | DAC_CR_MAMP1
00218                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00219                 ,
00220                  (  DAC_InitStruct->TriggerSource
00221                   | DAC_InitStruct->WaveAutoGeneration
00222                   | DAC_InitStruct->WaveAutoGenerationConfig
00223                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00224                 );
00225     }
00226     else
00227     {
00228       MODIFY_REG(DACx->CR,
00229                  (  DAC_CR_TSEL1
00230                   | DAC_CR_WAVE1
00231                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00232                 ,
00233                  (  DAC_InitStruct->TriggerSource
00234                   | LL_DAC_WAVE_AUTO_GENERATION_NONE
00235                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00236                 );
00237     }
00238
00239     MODIFY_REG(DACx->MCR,
00240                (  DAC_MCR_MODE1_1
00241                 | DAC_MCR_MODE1_0
00242                 | DAC_MCR_MODE1_2
00243                ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00244               ,
00245                (  DAC_InitStruct->OutputBuffer
00246                 | DAC_InitStruct->OutputConnection
00247                 | DAC_InitStruct->OutputMode
00248                ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00249               );
00250   }
00251   else
00252   {
00253     /* Initialization error: DAC instance is not disabled.                    */
00254     status = ERROR;
00255   }
00256   return status;
00257 }
00258
00259 /**
00260   * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
00261   * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
00262   *                       whose fields will be set to default values.
00263   * @retval None
00264   */
00265 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
00266 {
00267   /* Set DAC_InitStruct fields to default values */
00268   DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
00269   DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
00270   /* Note: Parameter discarded if wave auto generation is disabled,           */
00271   /*       set anyway to its default value.                                   */
00272   DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
00273   DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
00274   DAC_InitStruct->OutputConnection         = LL_DAC_OUTPUT_CONNECT_GPIO;
00275   DAC_InitStruct->OutputMode               = LL_DAC_OUTPUT_MODE_NORMAL;
00276 }
00277
00278 /**
00279   * @}
00280   */
00281
00282 /**
00283   * @}
00284   */
00285
00286 /**
00287   * @}
00288   */
00289
00290 #endif /* DAC1 */
00291
00292 /**
00293   * @}
00294   */
00295
00296 #endif /* USE_FULL_LL_DRIVER */
00297
00298 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_dac.h Source File

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stm32l4xx_ll_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_dac.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of DAC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_DAC_H
00040 #define __STM32L4xx_LL_DAC_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (DAC1)
00054
00055 /** @defgroup DAC_LL DAC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
00064   * @{
00065   */
00066
00067 /* Internal masks for DAC channels definition */
00068 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
00069 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR            */
00070 /* - channel bits position into register SWTRIG                               */
00071 /* - channel register offset of data holding register DHRx                    */
00072 /* - channel register offset of data output register DORx                     */
00073 /* - channel register offset of sample-and-hold sample time register SHSRx    */
00074
00075 #define DAC_CR_CH1_BITOFFSET           ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
00076 #define DAC_CR_CH2_BITOFFSET           ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
00077 #define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
00078
00079 #define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
00080 #define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
00081 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
00082
00083 #define DAC_REG_DHR12R1_REGOFFSET      ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
00084 #define DAC_REG_DHR12L1_REGOFFSET      ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00085 #define DAC_REG_DHR8R1_REGOFFSET       ((uint32_t)0x02000000U) /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00086 #define DAC_REG_DHR12R2_REGOFFSET      ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
00087 #define DAC_REG_DHR12L2_REGOFFSET      ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00088 #define DAC_REG_DHR8R2_REGOFFSET       ((uint32_t)0x05000000U) /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00089 #define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
00090 #define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
00091 #define DAC_REG_DHR8RX_REGOFFSET_MASK  ((uint32_t)0x0F000000U)
00092 #define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
00093
00094 #define DAC_REG_DOR1_REGOFFSET         ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
00095 #define DAC_REG_DOR2_REGOFFSET         ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
00096 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
00097
00098 #define DAC_REG_SHSR1_REGOFFSET        ((uint32_t)0x00000000U) /* Register SHSRx channel 1 taken as reference */
00099 #define DAC_REG_SHSR2_REGOFFSET        ((uint32_t)0x00001000U) /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */
00100 #define DAC_REG_SHSRX_REGOFFSET_MASK   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
00101
00102 /* DAC registers bits positions */
00103 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
00104 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
00105 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS  ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
00106
00107 /* Miscellaneous data */
00108 #define DAC_DIGITAL_SCALE_12BITS           ((uint32_t)4095U)                     /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
00109
00110 /**
00111   * @}
00112   */
00113
00114
00115 /* Private macros ------------------------------------------------------------*/
00116 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
00117   * @{
00118   */
00119
00120 /**
00121   * @brief  Driver macro reserved for internal use: isolate bits with the
00122   *         selected mask and shift them to the register LSB
00123   *         (shift mask on register position bit 0).
00124   * @param  __BITS__ Bits in register 32 bits
00125   * @param  __MASK__ Mask in register 32 bits
00126   * @retval Bits in register 32 bits
00127 */
00128 #define __DAC_MASK_SHIFT(__BITS__, __MASK__)                                   \
00129   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
00130
00131 /**
00132   * @brief  Driver macro reserved for internal use: set a pointer to
00133   *         a register from a register basis from which an offset
00134   *         is applied.
00135   * @param  __REG__ Register basis from which the offset is applied.
00136   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00137   * @retval Pointer to register address
00138 */
00139 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00140  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
00141
00142 /**
00143   * @}
00144   */
00145
00146
00147 /* Exported types ------------------------------------------------------------*/
00148 #if defined(USE_FULL_LL_DRIVER)
00149 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
00150   * @{
00151   */
00152
00153 /**
00154   * @brief  Structure definition of some features of DAC instance.
00155   */
00156 typedef struct
00157 {
00158   uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
00159                                              This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
00160
00161                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
00162
00163   uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
00164                                              This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
00165
00166                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
00167
00168   uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
00169                                              If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
00170                                              If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
00171                                              @note If waveform automatic generation mode is disabled, this parameter is discarded.
00172
00173                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
00174
00175   uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
00176                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
00177
00178                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
00179
00180   uint32_t OutputConnection;            /*!< Set the output connection for the selected DAC channel.
00181                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
00182
00183                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
00184
00185   uint32_t OutputMode;                  /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
00186                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
00187
00188                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
00189
00190 } LL_DAC_InitTypeDef;
00191
00192 /**
00193   * @}
00194   */
00195 #endif /* USE_FULL_LL_DRIVER */
00196
00197 /* Exported constants --------------------------------------------------------*/
00198 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
00199   * @{
00200   */
00201
00202 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
00203   * @brief    Flags defines which can be used with LL_DAC_ReadReg function
00204   * @{
00205   */
00206 /* DAC channel 1 flags */
00207 #define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
00208 #define LL_DAC_FLAG_CAL1                   (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
00209 #define LL_DAC_FLAG_BWST1                  (DAC_SR_BWST1)     /*!< DAC channel 1 flag busy writing sample time */
00210
00211 /* DAC channel 2 flags */
00212 #define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
00213 #define LL_DAC_FLAG_CAL2                   (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
00214 #define LL_DAC_FLAG_BWST2                  (DAC_SR_BWST2)     /*!< DAC channel 2 flag busy writing sample time */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup DAC_LL_EC_IT DAC interruptions
00220   * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
00221   * @{
00222   */
00223 #define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
00224 #define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
00230   * @{
00231   */
00232 #define LL_DAC_CHANNEL_1                   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
00233 #define LL_DAC_CHANNEL_2                   (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
00239   * @{
00240   */
00241 #define LL_DAC_MODE_NORMAL_OPERATION       ((uint32_t)0x00000000U) /*!< DAC channel in mode normal operation */
00242 #define LL_DAC_MODE_CALIBRATION            (DAC_CR_CEN1)           /*!< DAC channel in mode calibration */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
00248   * @{
00249   */
00250 #define LL_DAC_TRIG_SOFTWARE               (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
00251 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
00252 #define LL_DAC_TRIG_EXT_TIM4_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
00253 #define LL_DAC_TRIG_EXT_TIM5_TRGO          (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
00254 #define LL_DAC_TRIG_EXT_TIM6_TRGO          ((uint32_t)0x00000000U)                            /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
00255 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
00256 #define LL_DAC_TRIG_EXT_TIM8_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
00257 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
00263   * @{
00264   */
00265 #define LL_DAC_WAVE_AUTO_GENERATION_NONE     ((uint32_t)0x00000000U) /*!< DAC channel wave auto generation mode disabled. */
00266 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (DAC_CR_WAVE1_0)        /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
00267 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)        /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
00273   * @{
00274   */
00275 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0      ((uint32_t)0x00000000U)                                             /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
00276 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
00277 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
00278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
00279 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
00280 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
00281 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
00282 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
00283 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
00284 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
00285 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
00286 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
00292   * @{
00293   */
00294 #define LL_DAC_TRIANGLE_AMPLITUDE_1        ((uint32_t)0x00000000U)                                             /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
00295 #define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
00296 #define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
00297 #define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
00298 #define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
00299 #define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
00300 #define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
00301 #define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
00302 #define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
00303 #define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
00304 #define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
00305 #define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
00311   * @{
00312   */
00313 #define LL_DAC_OUTPUT_MODE_NORMAL          ((uint32_t)0x00000000U) /*!< The selected DAC channel output is on mode normal. */
00314 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)       /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
00320   * @{
00321   */
00322 #define LL_DAC_OUTPUT_BUFFER_ENABLE        ((uint32_t)0x00000000U) /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
00323 #define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_MCR_MODE1_1)       /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
00329   * @{
00330   */
00331 #define LL_DAC_OUTPUT_CONNECT_GPIO         ((uint32_t)0x00000000U) /*!< The selected DAC channel output is connected to external pin */
00332 #define LL_DAC_OUTPUT_CONNECT_INTERNAL     (DAC_MCR_MODE1_0)       /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming
00338   * @{
00339   */
00340 #define LL_DAC_TRIGGER_SOFTWARE            (LL_DAC_TRIG_SOFTWARE)
00341 #define LL_DAC_TRIGGER_TIM2_TRGO           (LL_DAC_TRIG_EXT_TIM2_TRGO)
00342 #define LL_DAC_TRIGGER_TIM4_TRGO           (LL_DAC_TRIG_EXT_TIM4_TRGO)
00343 #define LL_DAC_TRIGGER_TIM5_TRGO           (LL_DAC_TRIG_EXT_TIM5_TRGO)
00344 #define LL_DAC_TRIGGER_TIM6_TRGO           (LL_DAC_TRIG_EXT_TIM6_TRGO)
00345 #define LL_DAC_TRIGGER_TIM7_TRGO           (LL_DAC_TRIG_EXT_TIM7_TRGO)
00346 #define LL_DAC_TRIGGER_TIM8_TRGO           (LL_DAC_TRIG_EXT_TIM8_TRGO)
00347 #define LL_DAC_TRIGGER_EXT_IT9             (LL_DAC_TRIG_EXT_EXTI_LINE9)
00348
00349 #define LL_DAC_WAVEGENERATION_NONE         (LL_DAC_WAVE_AUTO_GENERATION_NONE)
00350 #define LL_DAC_WAVEGENERATION_NOISE        (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
00351 #define LL_DAC_WAVEGENERATION_TRIANGLE     (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
00352
00353 #define LL_DAC_CONNECT_GPIO                (LL_DAC_OUTPUT_CONNECT_GPIO)
00354 #define LL_DAC_CONNECT_INTERNAL            (LL_DAC_OUTPUT_CONNECT_INTERNAL)
00355 /**
00356   * @}
00357   */
00358
00359
00360 /** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
00361   * @{
00362   */
00363 #define LL_DAC_RESOLUTION_12B              ((uint32_t)0x00000000U) /*!< DAC channel resolution 12 bits */
00364 #define LL_DAC_RESOLUTION_8B               ((uint32_t)0x00000002U) /*!< DAC channel resolution 8 bits */
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
00370   * @{
00371   */
00372 /* List of DAC registers intended to be used (most commonly) with             */
00373 /* DMA transfer.                                                              */
00374 /* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
00375 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
00376 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
00377 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_MASK  /*!< DAC channel data holding register 8 bits right aligned */
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
00383   * @note   Only DAC IP HW delays are defined in DAC LL driver driver,
00384   *         not timeout values.
00385   *         For details on delays values, refer to descriptions in source code
00386   *         above each literal definition.
00387   * @{
00388   */
00389
00390 /* Delay for DAC channel voltage settling time from DAC channel startup       */
00391 /* (transition from disable to enable).                                       */
00392 /* Note: DAC channel startup time depends on board application environment:   */
00393 /*       impedance connected to DAC channel output.                           */
00394 /*       The delay below is specified under conditions:                       */
00395 /*        - voltage maximum transition (lowest to highest value)              */
00396 /*        - until voltage reaches final value +-1LSB                          */
00397 /*        - DAC channel output buffer enabled                                 */
00398 /*        - load impedance of 5kOhm (min), 50pF (max)                         */
00399 /* Literal set to maximum value (refer to device datasheet,                   */
00400 /* parameter "tWAKEUP").                                                      */
00401 /* Unit: us                                                                   */
00402 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t)  8U)  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
00403
00404
00405 /* Delay for DAC channel voltage settling time.                               */
00406 /* Note: DAC channel startup time depends on board application environment:   */
00407 /*       impedance connected to DAC channel output.                           */
00408 /*       The delay below is specified under conditions:                       */
00409 /*        - voltage maximum transition (lowest to highest value)              */
00410 /*        - until voltage reaches final value +-1LSB                          */
00411 /*        - DAC channel output buffer enabled                                 */
00412 /*        - load impedance of 5kOhm min, 50pF max                             */
00413 /* Literal set to maximum value (refer to device datasheet,                   */
00414 /* parameter "tSETTLING").                                                    */
00415 /* Unit: us                                                                   */
00416 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US  ((uint32_t)  2U)  /*!< Delay for DAC channel voltage settling time */
00417
00418 /**
00419   * @}
00420   */
00421
00422 /**
00423   * @}
00424   */
00425
00426 /* Exported macro ------------------------------------------------------------*/
00427 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
00428   * @{
00429   */
00430
00431 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
00432   * @{
00433   */
00434
00435 /**
00436   * @brief  Write a value in DAC register
00437   * @param  __INSTANCE__ DAC Instance
00438   * @param  __REG__ Register to be written
00439   * @param  __VALUE__ Value to be written in the register
00440   * @retval None
00441   */
00442 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00443
00444 /**
00445   * @brief  Read a value in DAC register
00446   * @param  __INSTANCE__ DAC Instance
00447   * @param  __REG__ Register to be read
00448   * @retval Register value
00449   */
00450 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00451
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
00457   * @{
00458   */
00459
00460 /**
00461   * @brief  Helper macro to get DAC channel number in decimal format
00462   *         from literals LL_DAC_CHANNEL_x.
00463   *         Example:
00464   *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
00465   *            will return decimal number "1".
00466   * @note   The input can be a value from functions where a channel
00467   *         number is returned.
00468   * @param  __CHANNEL__ This parameter can be one of the following values:
00469   *         @arg @ref LL_DAC_CHANNEL_1
00470   *         @arg @ref LL_DAC_CHANNEL_2
00471   * @retval 1...2
00472   */
00473 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
00474   ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
00475
00476 /**
00477   * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
00478   *         from number in decimal format.
00479   *         Example:
00480   *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
00481   *           will return a data equivalent to "LL_DAC_CHANNEL_1".
00482   * @note  If the input parameter does not correspond to a DAC channel,
00483   *        this macro returns value '0'.
00484   * @param  __DECIMAL_NB__ 1...2
00485   * @retval Returned value can be one of the following values:
00486   *         @arg @ref LL_DAC_CHANNEL_1
00487   *         @arg @ref LL_DAC_CHANNEL_2
00488   */
00489 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
00490   (((__DECIMAL_NB__) == 1U)                                                     \
00491     ? (                                                                        \
00492        LL_DAC_CHANNEL_1                                                        \
00493       )                                                                        \
00494       :                                                                        \
00495       (((__DECIMAL_NB__) == 2U)                                                 \
00496         ? (                                                                    \
00497            LL_DAC_CHANNEL_2                                                    \
00498           )                                                                    \
00499           :                                                                    \
00500           (                                                                    \
00501            0                                                                   \
00502           )                                                                    \
00503       )                                                                        \
00504   )
00505
00506 /**
00507   * @brief  Helper macro to define the DAC conversion data full-scale digital
00508   *         value corresponding to the selected DAC resolution.
00509   * @note   DAC conversion data full-scale corresponds to voltage range
00510   *         determined by analog voltage references Vref+ and Vref-
00511   *         (refer to reference manual).
00512   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00513   *         @arg @ref LL_DAC_RESOLUTION_12B
00514   *         @arg @ref LL_DAC_RESOLUTION_8B
00515   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
00516   */
00517 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
00518   (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
00519
00520 /**
00521   * @brief  Helper macro to calculate the DAC conversion data (unit: digital
00522   *         value) corresponding to a voltage (unit: mVolt).
00523   * @note   This helper macro is intended to provide input data in voltage
00524   *         rather than digital value,
00525   *         to be used with LL DAC functions such as
00526   *         @ref LL_DAC_ConvertData12RightAligned().
00527   * @note   Analog reference voltage (Vref+) must be either known from
00528   *         user board environment or can be calculated using ADC measurement
00529   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
00530   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
00531   * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
00532   *                         (unit: mVolt).
00533   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00534   *         @arg @ref LL_DAC_RESOLUTION_12B
00535   *         @arg @ref LL_DAC_RESOLUTION_8B
00536   * @retval DAC conversion data (unit: digital value)
00537   */
00538 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
00539                                       __DAC_VOLTAGE__,\
00540                                       __DAC_RESOLUTION__)                      \
00541   ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
00542    / (__VREFANALOG_VOLTAGE__)                                                  \
00543   )
00544
00545 /**
00546   * @}
00547   */
00548
00549 /**
00550   * @}
00551   */
00552
00553
00554 /* Exported functions --------------------------------------------------------*/
00555 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
00556   * @{
00557   */
00558 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
00559   * @{
00560   */
00561
00562 /**
00563   * @brief  Set the operating mode for the selected DAC channel:
00564   *         calibration or normal operating mode.
00565   * @rmtoll CR       CEN1           LL_DAC_SetMode\n
00566   *         CR       CEN2           LL_DAC_SetMode
00567   * @param  DACx DAC instance
00568   * @param  DAC_Channel This parameter can be one of the following values:
00569   *         @arg @ref LL_DAC_CHANNEL_1
00570   *         @arg @ref LL_DAC_CHANNEL_2
00571   * @param  ChannelMode This parameter can be one of the following values:
00572   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
00573   *         @arg @ref LL_DAC_MODE_CALIBRATION
00574   * @retval None
00575   */
00576 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
00577 {
00578   MODIFY_REG(DACx->CR,
00579              DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00580              ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00581 }
00582
00583 /**
00584   * @brief  Get the operating mode for the selected DAC channel:
00585   *         calibration or normal operating mode.
00586   * @rmtoll CR       CEN1           LL_DAC_GetMode\n
00587   *         CR       CEN2           LL_DAC_GetMode
00588   * @param  DACx DAC instance
00589   * @param  DAC_Channel This parameter can be one of the following values:
00590   *         @arg @ref LL_DAC_CHANNEL_1
00591   *         @arg @ref LL_DAC_CHANNEL_2
00592   * @retval Returned value can be one of the following values:
00593   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
00594   *         @arg @ref LL_DAC_MODE_CALIBRATION
00595   */
00596 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00597 {
00598   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00599                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00600                    );
00601 }
00602
00603 /**
00604   * @brief  Set the offset trimming value for the selected DAC channel.
00605   *         Trimming has an impact when output buffer is enabled
00606   *         and is intended to replace factory calibration default values.
00607   * @rmtoll CCR      OTRIM1         LL_DAC_SetTrimmingValue\n
00608   *         CCR      OTRIM2         LL_DAC_SetTrimmingValue
00609   * @param  DACx DAC instance
00610   * @param  DAC_Channel This parameter can be one of the following values:
00611   *         @arg @ref LL_DAC_CHANNEL_1
00612   *         @arg @ref LL_DAC_CHANNEL_2
00613   * @param  TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
00617 {
00618   MODIFY_REG(DACx->CCR,
00619              DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00620              TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00621 }
00622
00623 /**
00624   * @brief  Get the offset trimming value for the selected DAC channel.
00625   *         Trimming has an impact when output buffer is enabled
00626   *         and is intended to replace factory calibration default values.
00627   * @rmtoll CCR      OTRIM1         LL_DAC_GetTrimmingValue\n
00628   *         CCR      OTRIM2         LL_DAC_GetTrimmingValue
00629   * @param  DACx DAC instance
00630   * @param  DAC_Channel This parameter can be one of the following values:
00631   *         @arg @ref LL_DAC_CHANNEL_1
00632   *         @arg @ref LL_DAC_CHANNEL_2
00633   * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
00634   */
00635 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00636 {
00637   return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00638                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00639                    );
00640 }
00641
00642 /**
00643   * @brief  Set the conversion trigger source for the selected DAC channel.
00644   * @note   For conversion trigger source to be effective, DAC trigger
00645   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00646   * @note   To set conversion trigger source, DAC channel must be disabled.
00647   *         Otherwise, the setting is discarded.
00648   * @note   Availability of parameters of trigger sources from timer
00649   *         depends on timers availability on the selected device.
00650   * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
00651   *         CR       TSEL2          LL_DAC_SetTriggerSource
00652   * @param  DACx DAC instance
00653   * @param  DAC_Channel This parameter can be one of the following values:
00654   *         @arg @ref LL_DAC_CHANNEL_1
00655   *         @arg @ref LL_DAC_CHANNEL_2
00656   * @param  TriggerSource This parameter can be one of the following values:
00657   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00658   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00659   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
00660   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
00661   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00662   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00663   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
00664   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
00668 {
00669   MODIFY_REG(DACx->CR,
00670              DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00671              TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00672 }
00673
00674 /**
00675   * @brief  Get the conversion trigger source for the selected DAC channel.
00676   * @note   For conversion trigger source to be effective, DAC trigger
00677   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00678   * @note   Availability of parameters of trigger sources from timer
00679   *         depends on timers availability on the selected device.
00680   * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
00681   *         CR       TSEL2          LL_DAC_GetTriggerSource
00682   * @param  DACx DAC instance
00683   * @param  DAC_Channel This parameter can be one of the following values:
00684   *         @arg @ref LL_DAC_CHANNEL_1
00685   *         @arg @ref LL_DAC_CHANNEL_2
00686   * @retval Returned value can be one of the following values:
00687   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00688   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00689   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
00690   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
00691   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00692   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00693   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
00694   *         @arg @ref LL_DAC_TRIGGER_EXT_IT9
00695   */
00696 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00697 {
00698   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00699                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00700                    );
00701 }
00702
00703 /**
00704   * @brief  Set the waveform automatic generation mode
00705   *         for the selected DAC channel.
00706   * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
00707   *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
00708   * @param  DACx DAC instance
00709   * @param  DAC_Channel This parameter can be one of the following values:
00710   *         @arg @ref LL_DAC_CHANNEL_1
00711   *         @arg @ref LL_DAC_CHANNEL_2
00712   * @param  WaveAutoGeneration This parameter can be one of the following values:
00713   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00714   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00715   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00716   * @retval None
00717   */
00718 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
00719 {
00720   MODIFY_REG(DACx->CR,
00721              DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00722              WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00723 }
00724
00725 /**
00726   * @brief  Get the waveform automatic generation mode
00727   *         for the selected DAC channel.
00728   * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
00729   *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
00730   * @param  DACx DAC instance
00731   * @param  DAC_Channel This parameter can be one of the following values:
00732   *         @arg @ref LL_DAC_CHANNEL_1
00733   *         @arg @ref LL_DAC_CHANNEL_2
00734   * @retval Returned value can be one of the following values:
00735   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00736   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00737   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00738   */
00739 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00740 {
00741   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00742                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00743                    );
00744 }
00745
00746 /**
00747   * @brief  Set the noise waveform generation for the selected DAC channel:
00748   *         Noise mode and parameters LFSR (linear feedback shift register).
00749   * @note   For wave generation to be effective, DAC channel
00750   *         wave generation mode must be enabled using
00751   *         function @ref LL_DAC_SetWaveAutoGeneration().
00752   * @note   This setting can be set when the selected DAC channel is disabled
00753   *         (otherwise, the setting operation is ignored).
00754   * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
00755   *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
00756   * @param  DACx DAC instance
00757   * @param  DAC_Channel This parameter can be one of the following values:
00758   *         @arg @ref LL_DAC_CHANNEL_1
00759   *         @arg @ref LL_DAC_CHANNEL_2
00760   * @param  NoiseLFSRMask This parameter can be one of the following values:
00761   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00762   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00763   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00764   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00765   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00766   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00767   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00768   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00769   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00770   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00771   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00772   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00773   * @retval None
00774   */
00775 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
00776 {
00777   MODIFY_REG(DACx->CR,
00778              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00779              NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00780 }
00781
00782 /**
00783   * @brief  Set the noise waveform generation for the selected DAC channel:
00784   *         Noise mode and parameters LFSR (linear feedback shift register).
00785   * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
00786   *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
00787   * @param  DACx DAC instance
00788   * @param  DAC_Channel This parameter can be one of the following values:
00789   *         @arg @ref LL_DAC_CHANNEL_1
00790   *         @arg @ref LL_DAC_CHANNEL_2
00791   * @retval Returned value can be one of the following values:
00792   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00793   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00794   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00795   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00796   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00797   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00798   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00799   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00800   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00801   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00802   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00803   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00804   */
00805 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00806 {
00807   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00808                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00809                    );
00810 }
00811
00812 /**
00813   * @brief  Set the triangle waveform generation for the selected DAC channel:
00814   *         triangle mode and amplitude.
00815   * @note   For wave generation to be effective, DAC channel
00816   *         wave generation mode must be enabled using
00817   *         function @ref LL_DAC_SetWaveAutoGeneration().
00818   * @note   This setting can be set when the selected DAC channel is disabled
00819   *         (otherwise, the setting operation is ignored).
00820   * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
00821   *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
00822   * @param  DACx DAC instance
00823   * @param  DAC_Channel This parameter can be one of the following values:
00824   *         @arg @ref LL_DAC_CHANNEL_1
00825   *         @arg @ref LL_DAC_CHANNEL_2
00826   * @param  TriangleAmplitude This parameter can be one of the following values:
00827   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00828   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00829   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00830   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00831   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00832   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00833   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00834   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00835   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00836   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00837   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00838   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00839   * @retval None
00840   */
00841 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
00842 {
00843   MODIFY_REG(DACx->CR,
00844              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00845              TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00846 }
00847
00848 /**
00849   * @brief  Set the triangle waveform generation for the selected DAC channel:
00850   *         triangle mode and amplitude.
00851   * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
00852   *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
00853   * @param  DACx DAC instance
00854   * @param  DAC_Channel This parameter can be one of the following values:
00855   *         @arg @ref LL_DAC_CHANNEL_1
00856   *         @arg @ref LL_DAC_CHANNEL_2
00857   * @retval Returned value can be one of the following values:
00858   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00859   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00860   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00861   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00862   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00863   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00864   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00865   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00866   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00867   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00868   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00869   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00870   */
00871 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00872 {
00873   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00874                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00875                    );
00876 }
00877
00878 /**
00879   * @brief  Set the output for the selected DAC channel.
00880   * @note   This function set several features:
00881   *         - mode normal or sample-and-hold
00882   *         - buffer
00883   *         - connection to GPIO or internal path.
00884   *         These features can also be set individually using
00885   *         dedicated functions:
00886   *         - @ref LL_DAC_SetOutputBuffer()
00887   *         - @ref LL_DAC_SetOutputMode()
00888   *         - @ref LL_DAC_SetOutputConnection()
00889   * @note   On this STM32 serie, output connection depends on output mode
00890   *         (normal or sample and hold) and output buffer state.
00891   *         - if output connection is set to internal path and output buffer
00892   *           is enabled (whatever output mode):
00893   *           output connection is also connected to GPIO pin
00894   *           (both connections to GPIO pin and internal path).
00895   *         - if output connection is set to GPIO pin, output buffer
00896   *           is disabled, output mode set to sample and hold:
00897   *           output connection is also connected to internal path
00898   *           (both connections to GPIO pin and internal path).
00899   * @note   Mode sample-and-hold requires an external capacitor
00900   *         to be connected between DAC channel output and ground.
00901   *         Capacitor value depends on load on DAC channel output and
00902   *         sample-and-hold timings configured.
00903   *         As indication, capacitor typical value is 100nF
00904   *         (refer to device datasheet, parameter "CSH").
00905   * @rmtoll CR       MODE1          LL_DAC_ConfigOutput\n
00906   *         CR       MODE2          LL_DAC_ConfigOutput
00907   * @param  DACx DAC instance
00908   * @param  DAC_Channel This parameter can be one of the following values:
00909   *         @arg @ref LL_DAC_CHANNEL_1
00910   *         @arg @ref LL_DAC_CHANNEL_2
00911   * @param  OutputMode This parameter can be one of the following values:
00912   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00913   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00914   * @param  OutputBuffer This parameter can be one of the following values:
00915   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00916   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00917   * @param  OutputConnection This parameter can be one of the following values:
00918   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
00919   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
00920   * @retval None
00921   */
00922 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
00923 {
00924   MODIFY_REG(DACx->MCR,
00925              (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00926              (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00927 }
00928
00929 /**
00930   * @brief  Set the output mode normal or sample-and-hold
00931   *         for the selected DAC channel.
00932   * @note   Mode sample-and-hold requires an external capacitor
00933   *         to be connected between DAC channel output and ground.
00934   *         Capacitor value depends on load on DAC channel output and
00935   *         sample-and-hold timings configured.
00936   *         As indication, capacitor typical value is 100nF
00937   *         (refer to device datasheet, parameter "CSH").
00938   * @rmtoll CR       MODE1          LL_DAC_SetOutputMode\n
00939   *         CR       MODE2          LL_DAC_SetOutputMode
00940   * @param  DACx DAC instance
00941   * @param  DAC_Channel This parameter can be one of the following values:
00942   *         @arg @ref LL_DAC_CHANNEL_1
00943   *         @arg @ref LL_DAC_CHANNEL_2
00944   * @param  OutputMode This parameter can be one of the following values:
00945   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00946   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00947   * @retval None
00948   */
00949 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
00950 {
00951   MODIFY_REG(DACx->MCR,
00952              DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00953              OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00954 }
00955
00956 /**
00957   * @brief  Get the output mode normal or sample-and-hold for the selected DAC channel.
00958   * @rmtoll CR       MODE1          LL_DAC_GetOutputMode\n
00959   *         CR       MODE2          LL_DAC_GetOutputMode
00960   * @param  DACx DAC instance
00961   * @param  DAC_Channel This parameter can be one of the following values:
00962   *         @arg @ref LL_DAC_CHANNEL_1
00963   *         @arg @ref LL_DAC_CHANNEL_2
00964   * @retval Returned value can be one of the following values:
00965   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00966   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00967   */
00968 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00969 {
00970   return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00971                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00972                    );
00973 }
00974
00975 /**
00976   * @brief  Set the output buffer for the selected DAC channel.
00977   * @note   On this STM32 serie, when buffer is enabled, its offset can be
00978   *         trimmed: factory calibration default values can be
00979   *         replaced by user trimming values, using function
00980   *         @ref LL_DAC_SetTrimmingValue().
00981   * @rmtoll CR       MODE1          LL_DAC_SetOutputBuffer\n
00982   *         CR       MODE2          LL_DAC_SetOutputBuffer
00983   * @param  DACx DAC instance
00984   * @param  DAC_Channel This parameter can be one of the following values:
00985   *         @arg @ref LL_DAC_CHANNEL_1
00986   *         @arg @ref LL_DAC_CHANNEL_2
00987   * @param  OutputBuffer This parameter can be one of the following values:
00988   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00989   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00990   * @retval None
00991   */
00992 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
00993 {
00994   MODIFY_REG(DACx->MCR,
00995              DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00996              OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00997 }
00998
00999 /**
01000   * @brief  Get the output buffer state for the selected DAC channel.
01001   * @rmtoll CR       MODE1          LL_DAC_GetOutputBuffer\n
01002   *         CR       MODE2          LL_DAC_GetOutputBuffer
01003   * @param  DACx DAC instance
01004   * @param  DAC_Channel This parameter can be one of the following values:
01005   *         @arg @ref LL_DAC_CHANNEL_1
01006   *         @arg @ref LL_DAC_CHANNEL_2
01007   * @retval Returned value can be one of the following values:
01008   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
01009   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
01010   */
01011 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01012 {
01013   return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01014                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01015                    );
01016 }
01017
01018 /**
01019   * @brief  Set the output connection for the selected DAC channel.
01020   * @note   On this STM32 serie, output connection depends on output mode (normal or
01021   *         sample and hold) and output buffer state.
01022   *         - if output connection is set to internal path and output buffer
01023   *           is enabled (whatever output mode):
01024   *           output connection is also connected to GPIO pin
01025   *           (both connections to GPIO pin and internal path).
01026   *         - if output connection is set to GPIO pin, output buffer
01027   *           is disabled, output mode set to sample and hold:
01028   *           output connection is also connected to internal path
01029   *           (both connections to GPIO pin and internal path).
01030   * @rmtoll CR       MODE1          LL_DAC_SetOutputConnection\n
01031   *         CR       MODE2          LL_DAC_SetOutputConnection
01032   * @param  DACx DAC instance
01033   * @param  DAC_Channel This parameter can be one of the following values:
01034   *         @arg @ref LL_DAC_CHANNEL_1
01035   *         @arg @ref LL_DAC_CHANNEL_2
01036   * @param  OutputConnection This parameter can be one of the following values:
01037   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01038   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01039   * @retval None
01040   */
01041 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
01042 {
01043   MODIFY_REG(DACx->MCR,
01044              DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01045              OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01046 }
01047
01048 /**
01049   * @brief  Get the output connection for the selected DAC channel.
01050   * @note   On this STM32 serie, output connection depends on output mode (normal or
01051   *         sample and hold) and output buffer state.
01052   *         - if output connection is set to internal path and output buffer
01053   *           is enabled (whatever output mode):
01054   *           output connection is also connected to GPIO pin
01055   *           (both connections to GPIO pin and internal path).
01056   *         - if output connection is set to GPIO pin, output buffer
01057   *           is disabled, output mode set to sample and hold:
01058   *           output connection is also connected to internal path
01059   *           (both connections to GPIO pin and internal path).
01060   * @rmtoll CR       MODE1          LL_DAC_GetOutputConnection\n
01061   *         CR       MODE2          LL_DAC_GetOutputConnection
01062   * @param  DACx DAC instance
01063   * @param  DAC_Channel This parameter can be one of the following values:
01064   *         @arg @ref LL_DAC_CHANNEL_1
01065   *         @arg @ref LL_DAC_CHANNEL_2
01066   * @retval Returned value can be one of the following values:
01067   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01068   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01069   */
01070 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01071 {
01072   return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01073                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01074                    );
01075 }
01076
01077 /**
01078   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01079   *         sample time
01080   * @note   Sample time must be set when DAC channel is disabled
01081   *         or during DAC operation when DAC channel flag BWSTx is reset,
01082   *         otherwise the setting is ignored.
01083   *         Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
01084   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_SetSampleAndHoldSampleTime\n
01085   *         SHSR2    TSAMPLE2       LL_DAC_SetSampleAndHoldSampleTime
01086   * @param  DACx DAC instance
01087   * @param  DAC_Channel This parameter can be one of the following values:
01088   *         @arg @ref LL_DAC_CHANNEL_1
01089   *         @arg @ref LL_DAC_CHANNEL_2
01090   * @param  SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
01091   * @retval None
01092   */
01093 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
01094 {
01095   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK));
01096
01097   MODIFY_REG(*preg,
01098              DAC_SHSR1_TSAMPLE1,
01099              SampleTime);
01100 }
01101
01102 /**
01103   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01104   *         sample time
01105   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_GetSampleAndHoldSampleTime\n
01106   *         SHSR2    TSAMPLE2       LL_DAC_GetSampleAndHoldSampleTime
01107   * @param  DACx DAC instance
01108   * @param  DAC_Channel This parameter can be one of the following values:
01109   *         @arg @ref LL_DAC_CHANNEL_1
01110   *         @arg @ref LL_DAC_CHANNEL_2
01111   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
01112   */
01113 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01114 {
01115   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK));
01116
01117   return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
01118 }
01119
01120 /**
01121   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01122   *         hold time
01123   * @rmtoll SHHR     THOLD1         LL_DAC_SetSampleAndHoldHoldTime\n
01124   *         SHHR     THOLD2         LL_DAC_SetSampleAndHoldHoldTime
01125   * @param  DACx DAC instance
01126   * @param  DAC_Channel This parameter can be one of the following values:
01127   *         @arg @ref LL_DAC_CHANNEL_1
01128   *         @arg @ref LL_DAC_CHANNEL_2
01129   * @param  HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
01130   * @retval None
01131   */
01132 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
01133 {
01134   MODIFY_REG(DACx->SHHR,
01135              DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01136              HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01137 }
01138
01139 /**
01140   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01141   *         hold time
01142   * @rmtoll SHHR     THOLD1         LL_DAC_GetSampleAndHoldHoldTime\n
01143   *         SHHR     THOLD2         LL_DAC_GetSampleAndHoldHoldTime
01144   * @param  DACx DAC instance
01145   * @param  DAC_Channel This parameter can be one of the following values:
01146   *         @arg @ref LL_DAC_CHANNEL_1
01147   *         @arg @ref LL_DAC_CHANNEL_2
01148   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
01149   */
01150 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01151 {
01152   return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01153                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01154                    );
01155 }
01156
01157 /**
01158   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01159   *         refresh time
01160   * @rmtoll SHRR     TREFRESH1      LL_DAC_SetSampleAndHoldRefreshTime\n
01161   *         SHRR     TREFRESH2      LL_DAC_SetSampleAndHoldRefreshTime
01162   * @param  DACx DAC instance
01163   * @param  DAC_Channel This parameter can be one of the following values:
01164   *         @arg @ref LL_DAC_CHANNEL_1
01165   *         @arg @ref LL_DAC_CHANNEL_2
01166   * @param  RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
01167   * @retval None
01168   */
01169 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
01170 {
01171   MODIFY_REG(DACx->SHRR,
01172              DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01173              RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01174 }
01175
01176 /**
01177   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01178   *         refresh time
01179   * @rmtoll SHRR     TREFRESH1      LL_DAC_GetSampleAndHoldRefreshTime\n
01180   *         SHRR     TREFRESH2      LL_DAC_GetSampleAndHoldRefreshTime
01181   * @param  DACx DAC instance
01182   * @param  DAC_Channel This parameter can be one of the following values:
01183   *         @arg @ref LL_DAC_CHANNEL_1
01184   *         @arg @ref LL_DAC_CHANNEL_2
01185   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01186   */
01187 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01188 {
01189   return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01190                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01191                    );
01192 }
01193
01194 /**
01195   * @}
01196   */
01197
01198 /** @defgroup DAC_LL_EF_Configuration_Legacy_Functions DAC configuration, legacy functions name
01199   * @{
01200   */
01201 /* Old functions name kept for legacy purpose, to be replaced by the          */
01202 /* current functions name.                                                    */
01203 __STATIC_INLINE void LL_DAC_SetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveMode)
01204 {
01205   LL_DAC_SetWaveAutoGeneration(DACx, DAC_Channel, WaveMode);
01206 }
01207 __STATIC_INLINE uint32_t LL_DAC_GetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01208 {
01209   return LL_DAC_GetWaveAutoGeneration(DACx, DAC_Channel);
01210 }
01211
01212 /**
01213   * @}
01214   */
01215
01216 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
01217   * @{
01218   */
01219
01220 /**
01221   * @brief  Enable DAC DMA transfer request of the selected channel.
01222   * @note   To configure DMA source address (peripheral address),
01223   *         use function @ref LL_DAC_DMA_GetRegAddr().
01224   * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
01225   *         CR       DMAEN2         LL_DAC_EnableDMAReq
01226   * @param  DACx DAC instance
01227   * @param  DAC_Channel This parameter can be one of the following values:
01228   *         @arg @ref LL_DAC_CHANNEL_1
01229   *         @arg @ref LL_DAC_CHANNEL_2
01230   * @retval None
01231   */
01232 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01233 {
01234   SET_BIT(DACx->CR,
01235           DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01236 }
01237
01238 /**
01239   * @brief  Disable DAC DMA transfer request of the selected channel.
01240   * @note   To configure DMA source address (peripheral address),
01241   *         use function @ref LL_DAC_DMA_GetRegAddr().
01242   * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
01243   *         CR       DMAEN2         LL_DAC_DisableDMAReq
01244   * @param  DACx DAC instance
01245   * @param  DAC_Channel This parameter can be one of the following values:
01246   *         @arg @ref LL_DAC_CHANNEL_1
01247   *         @arg @ref LL_DAC_CHANNEL_2
01248   * @retval None
01249   */
01250 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01251 {
01252   CLEAR_BIT(DACx->CR,
01253             DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01254 }
01255
01256 /**
01257   * @brief  Get DAC DMA transfer request state of the selected channel.
01258   *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
01259   * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
01260   *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
01261   * @param  DACx DAC instance
01262   * @param  DAC_Channel This parameter can be one of the following values:
01263   *         @arg @ref LL_DAC_CHANNEL_1
01264   *         @arg @ref LL_DAC_CHANNEL_2
01265   * @retval State of bit (1 or 0).
01266   */
01267 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01268 {
01269   return (READ_BIT(DACx->CR,
01270                    DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01271           == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
01272 }
01273
01274 /**
01275   * @brief  Function to help to configure DMA transfer to DAC: retrieve the
01276   *         DAC register address from DAC instance and a list of DAC registers
01277   *         intended to be used (most commonly) with DMA transfer.
01278   * @note   These DAC registers are data holding registers:
01279   *         when DAC conversion is requested, DAC generates a DMA transfer
01280   *         request to have data available in DAC data holding registers.
01281   * @note   This macro is intended to be used with LL DMA driver, refer to
01282   *         function "LL_DMA_ConfigAddresses()".
01283   *         Example:
01284   *           LL_DMA_ConfigAddresses(DMA1,
01285   *                                  LL_DMA_CHANNEL_1,
01286   *                                  (uint32_t)&< array or variable >,
01287   *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
01288   *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
01289   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01290   *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01291   *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01292   *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
01293   *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
01294   *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
01295   * @param  DACx DAC instance
01296   * @param  DAC_Channel This parameter can be one of the following values:
01297   *         @arg @ref LL_DAC_CHANNEL_1
01298   *         @arg @ref LL_DAC_CHANNEL_2
01299   * @param  Register This parameter can be one of the following values:
01300   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
01301   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
01302   *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
01303   * @retval DAC register address
01304   */
01305 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
01306 {
01307   /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
01308   /* DAC channel selected.                                                    */
01309   return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
01310 }
01311 /**
01312   * @}
01313   */
01314
01315 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
01316   * @{
01317   */
01318
01319 /**
01320   * @brief  Enable DAC selected channel.
01321   * @rmtoll CR       EN1            LL_DAC_Enable\n
01322   *         CR       EN2            LL_DAC_Enable
01323   * @note   After enable from off state, DAC channel requires a delay
01324   *         for output voltage to reach accuracy +/- 1 LSB.
01325   *         Refer to device datasheet, parameter "tWAKEUP".
01326   * @param  DACx DAC instance
01327   * @param  DAC_Channel This parameter can be one of the following values:
01328   *         @arg @ref LL_DAC_CHANNEL_1
01329   *         @arg @ref LL_DAC_CHANNEL_2
01330   * @retval None
01331   */
01332 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01333 {
01334   SET_BIT(DACx->CR,
01335           DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01336 }
01337
01338 /**
01339   * @brief  Disable DAC selected channel.
01340   * @rmtoll CR       EN1            LL_DAC_Disable\n
01341   *         CR       EN2            LL_DAC_Disable
01342   * @param  DACx DAC instance
01343   * @param  DAC_Channel This parameter can be one of the following values:
01344   *         @arg @ref LL_DAC_CHANNEL_1
01345   *         @arg @ref LL_DAC_CHANNEL_2
01346   * @retval None
01347   */
01348 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01349 {
01350   CLEAR_BIT(DACx->CR,
01351             DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01352 }
01353
01354 /**
01355   * @brief  Get DAC enable state of the selected channel.
01356   *         (0: DAC channel is disabled, 1: DAC channel is enabled)
01357   * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
01358   *         CR       EN2            LL_DAC_IsEnabled
01359   * @param  DACx DAC instance
01360   * @param  DAC_Channel This parameter can be one of the following values:
01361   *         @arg @ref LL_DAC_CHANNEL_1
01362   *         @arg @ref LL_DAC_CHANNEL_2
01363   * @retval State of bit (1 or 0).
01364   */
01365 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01366 {
01367   return (READ_BIT(DACx->CR,
01368                    DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01369           == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
01370 }
01371
01372 /**
01373   * @brief  Enable DAC trigger of the selected channel.
01374   * @note   - If DAC trigger is disabled, DAC conversion is performed
01375   *           automatically once the data holding register is updated,
01376   *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01377   *           @ref LL_DAC_ConvertData12RightAligned(), ...
01378   *         - If DAC trigger is enabled, DAC conversion is performed
01379   *           only when a hardware of software trigger event is occurring.
01380   *           Select trigger source using
01381   *           function @ref LL_DAC_SetTriggerSource().
01382   * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
01383   *         CR       TEN2           LL_DAC_EnableTrigger
01384   * @param  DACx DAC instance
01385   * @param  DAC_Channel This parameter can be one of the following values:
01386   *         @arg @ref LL_DAC_CHANNEL_1
01387   *         @arg @ref LL_DAC_CHANNEL_2
01388   * @retval None
01389   */
01390 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01391 {
01392   SET_BIT(DACx->CR,
01393           DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01394 }
01395
01396 /**
01397   * @brief  Disable DAC trigger of the selected channel.
01398   * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
01399   *         CR       TEN2           LL_DAC_DisableTrigger
01400   * @param  DACx DAC instance
01401   * @param  DAC_Channel This parameter can be one of the following values:
01402   *         @arg @ref LL_DAC_CHANNEL_1
01403   *         @arg @ref LL_DAC_CHANNEL_2
01404   * @retval None
01405   */
01406 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01407 {
01408   CLEAR_BIT(DACx->CR,
01409             DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01410 }
01411
01412 /**
01413   * @brief  Get DAC trigger state of the selected channel.
01414   *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
01415   * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
01416   *         CR       TEN2           LL_DAC_IsTriggerEnabled
01417   * @param  DACx DAC instance
01418   * @param  DAC_Channel This parameter can be one of the following values:
01419   *         @arg @ref LL_DAC_CHANNEL_1
01420   *         @arg @ref LL_DAC_CHANNEL_2
01421   * @retval State of bit (1 or 0).
01422   */
01423 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01424 {
01425   return (READ_BIT(DACx->CR,
01426                    DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01427           == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
01428 }
01429
01430 /**
01431   * @brief  Trig DAC conversion by software for the selected DAC channel.
01432   * @note   Preliminarily, DAC trigger must be set to software trigger
01433   *         using function @ref LL_DAC_SetTriggerSource()
01434   *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
01435   *         and DAC trigger must be enabled using
01436   *         function @ref LL_DAC_EnableTrigger().
01437   * @note   For devices featuring DAC with 2 channels: this function
01438   *         can perform a SW start of both DAC channels simultaneously.
01439   *         Two channels can be selected as parameter.
01440   *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
01441   * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
01442   *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
01443   * @param  DACx DAC instance
01444   * @param  DAC_Channel  This parameter can a combination of the following values:
01445   *         @arg @ref LL_DAC_CHANNEL_1
01446   *         @arg @ref LL_DAC_CHANNEL_2
01447   * @retval None
01448   */
01449 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01450 {
01451   SET_BIT(DACx->SWTRIGR,
01452           (DAC_Channel & DAC_SWTR_CHX_MASK));
01453 }
01454
01455 /**
01456   * @brief  Set the data to be loaded in the data holding register
01457   *         in format 12 bits left alignment (LSB aligned on bit 0),
01458   *         for the selected DAC channel.
01459   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
01460   *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
01461   * @param  DACx DAC instance
01462   * @param  DAC_Channel This parameter can be one of the following values:
01463   *         @arg @ref LL_DAC_CHANNEL_1
01464   *         @arg @ref LL_DAC_CHANNEL_2
01465   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01466   * @retval None
01467   */
01468 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01469 {
01470   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
01471
01472   MODIFY_REG(*preg,
01473              DAC_DHR12R1_DACC1DHR,
01474              Data);
01475 }
01476
01477 /**
01478   * @brief  Set the data to be loaded in the data holding register
01479   *         in format 12 bits left alignment (MSB aligned on bit 15),
01480   *         for the selected DAC channel.
01481   * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
01482   *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
01483   * @param  DACx DAC instance
01484   * @param  DAC_Channel This parameter can be one of the following values:
01485   *         @arg @ref LL_DAC_CHANNEL_1
01486   *         @arg @ref LL_DAC_CHANNEL_2
01487   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01488   * @retval None
01489   */
01490 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01491 {
01492   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
01493
01494   MODIFY_REG(*preg,
01495              DAC_DHR12L1_DACC1DHR,
01496              Data);
01497 }
01498
01499 /**
01500   * @brief  Set the data to be loaded in the data holding register
01501   *         in format 8 bits left alignment (LSB aligned on bit 0),
01502   *         for the selected DAC channel.
01503   * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
01504   *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
01505   * @param  DACx DAC instance
01506   * @param  DAC_Channel This parameter can be one of the following values:
01507   *         @arg @ref LL_DAC_CHANNEL_1
01508   *         @arg @ref LL_DAC_CHANNEL_2
01509   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
01510   * @retval None
01511   */
01512 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01513 {
01514   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
01515
01516   MODIFY_REG(*preg,
01517              DAC_DHR8R1_DACC1DHR,
01518              Data);
01519 }
01520
01521 /**
01522   * @brief  Set the data to be loaded in the data holding register
01523   *         in format 12 bits left alignment (LSB aligned on bit 0),
01524   *         for both DAC channels.
01525   * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
01526   *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
01527   * @param  DACx DAC instance
01528   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01529   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01530   * @retval None
01531   */
01532 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01533 {
01534   MODIFY_REG(DACx->DHR12RD,
01535              (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
01536              ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01537 }
01538
01539 /**
01540   * @brief  Set the data to be loaded in the data holding register
01541   *         in format 12 bits left alignment (MSB aligned on bit 15),
01542   *         for both DAC channels.
01543   * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
01544   *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
01545   * @param  DACx DAC instance
01546   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01547   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01548   * @retval None
01549   */
01550 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01551 {
01552   /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
01553   /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
01554   /*       the 4 LSB must be taken into account for the shift value.          */
01555   MODIFY_REG(DACx->DHR12LD,
01556              (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
01557              ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
01558 }
01559
01560 /**
01561   * @brief  Set the data to be loaded in the data holding register
01562   *         in format 8 bits left alignment (LSB aligned on bit 0),
01563   *         for both DAC channels.
01564   * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
01565   *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
01566   * @param  DACx DAC instance
01567   * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
01568   * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
01569   * @retval None
01570   */
01571 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01572 {
01573   MODIFY_REG(DACx->DHR8RD,
01574              (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
01575              ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01576 }
01577
01578 /**
01579   * @brief  Retrieve output data currently generated for the selected DAC channel.
01580   * @note   Whatever alignment and resolution settings
01581   *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01582   *         @ref LL_DAC_ConvertData12RightAligned(), ...),
01583   *         output data format is 12 bits right aligned (LSB aligned on bit 0).
01584   * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
01585   *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
01586   * @param  DACx DAC instance
01587   * @param  DAC_Channel This parameter can be one of the following values:
01588   *         @arg @ref LL_DAC_CHANNEL_1
01589   *         @arg @ref LL_DAC_CHANNEL_2
01590   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01591   */
01592 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01593 {
01594   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
01595
01596   return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
01597 }
01598
01599 /**
01600   * @}
01601   */
01602
01603 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
01604   * @{
01605   */
01606 /**
01607   * @brief  Get DAC calibration offset flag for DAC channel 1
01608   * @rmtoll SR       CAL_FLAG1      LL_DAC_IsActiveFlag_CAL1
01609   * @param  DACx DAC instance
01610   * @retval State of bit (1 or 0).
01611   */
01612 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
01613 {
01614   return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1));
01615 }
01616
01617 /**
01618   * @brief  Get DAC calibration offset flag for DAC channel 2
01619   * @rmtoll SR       CAL_FLAG2      LL_DAC_IsActiveFlag_CAL2
01620   * @param  DACx DAC instance
01621   * @retval State of bit (1 or 0).
01622   */
01623 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
01624 {
01625   return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2));
01626 }
01627
01628 /**
01629   * @brief  Get DAC busy writing sample time flag for DAC channel 1
01630   * @rmtoll SR       BWST1          LL_DAC_IsActiveFlag_BWST1
01631   * @param  DACx DAC instance
01632   * @retval State of bit (1 or 0).
01633   */
01634 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
01635 {
01636   return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1));
01637 }
01638
01639 /**
01640   * @brief  Get DAC busy writing sample time flag for DAC channel 2
01641   * @rmtoll SR       BWST2          LL_DAC_IsActiveFlag_BWST2
01642   * @param  DACx DAC instance
01643   * @retval State of bit (1 or 0).
01644   */
01645 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
01646 {
01647   return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2));
01648 }
01649
01650 /**
01651   * @brief  Get DAC underrun flag for DAC channel 1
01652   * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
01653   * @param  DACx DAC instance
01654   * @retval State of bit (1 or 0).
01655   */
01656 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
01657 {
01658   return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
01659 }
01660
01661 /**
01662   * @brief  Get DAC underrun flag for DAC channel 2
01663   * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
01664   * @param  DACx DAC instance
01665   * @retval State of bit (1 or 0).
01666   */
01667 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
01668 {
01669   return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
01670 }
01671
01672 /**
01673   * @brief  Clear DAC underrun flag for DAC channel 1
01674   * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
01675   * @param  DACx DAC instance
01676   * @retval None
01677   */
01678 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
01679 {
01680   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
01681 }
01682
01683 /**
01684   * @brief  Clear DAC underrun flag for DAC channel 2
01685   * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
01686   * @param  DACx DAC instance
01687   * @retval None
01688   */
01689 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
01690 {
01691   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
01692 }
01693
01694 /**
01695   * @}
01696   */
01697
01698 /** @defgroup DAC_LL_EF_IT_Management IT management
01699   * @{
01700   */
01701
01702 /**
01703   * @brief  Enable DMA underrun interrupt for DAC channel 1
01704   * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
01705   * @param  DACx DAC instance
01706   * @retval None
01707   */
01708 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
01709 {
01710   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01711 }
01712
01713 /**
01714   * @brief  Enable DMA underrun interrupt for DAC channel 2
01715   * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
01716   * @param  DACx DAC instance
01717   * @retval None
01718   */
01719 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
01720 {
01721   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01722 }
01723
01724 /**
01725   * @brief  Disable DMA underrun interrupt for DAC channel 1
01726   * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
01727   * @param  DACx DAC instance
01728   * @retval None
01729   */
01730 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
01731 {
01732   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01733 }
01734
01735 /**
01736   * @brief  Disable DMA underrun interrupt for DAC channel 2
01737   * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
01738   * @param  DACx DAC instance
01739   * @retval None
01740   */
01741 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
01742 {
01743   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01744 }
01745
01746 /**
01747   * @brief  Get DMA underrun interrupt for DAC channel 1
01748   * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
01749   * @param  DACx DAC instance
01750   * @retval State of bit (1 or 0).
01751   */
01752 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
01753 {
01754   return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
01755 }
01756
01757 /**
01758   * @brief  Get DMA underrun interrupt for DAC channel 2
01759   * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
01760   * @param  DACx DAC instance
01761   * @retval State of bit (1 or 0).
01762   */
01763 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
01764 {
01765   return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
01766 }
01767
01768 /**
01769   * @}
01770   */
01771
01772 #if defined(USE_FULL_LL_DRIVER)
01773 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
01774   * @{
01775   */
01776
01777 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
01778 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
01779 void        LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
01780
01781 /**
01782   * @}
01783   */
01784 #endif /* USE_FULL_LL_DRIVER */
01785
01786 /**
01787   * @}
01788   */
01789
01790 /**
01791   * @}
01792   */
01793
01794 #endif /* DAC1 */
01795
01796 /**
01797   * @}
01798   */
01799
01800 #ifdef __cplusplus
01801 }
01802 #endif
01803
01804 #endif /* __STM32L4xx_LL_DAC_H */
01805
01806 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_dma.c Source File

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stm32l4xx_ll_dma.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_dma.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   DMA LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_dma.h"
00041 #include "stm32l4xx_ll_bus.h"
00042 #ifdef  USE_FULL_ASSERT
00043 #include "stm32_assert.h"
00044 #else
00045 #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32L4xx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined (DMA1) || defined (DMA2)
00053
00054 /** @defgroup DMA_LL DMA
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062 /** @addtogroup DMA_LL_Private_Macros
00063   * @{
00064   */
00065 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
00066                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
00067                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
00068
00069 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
00070                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
00071
00072 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
00073                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
00074
00075 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
00076                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
00077
00078 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
00079                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
00080                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
00081
00082 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
00083                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
00084                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
00085
00086 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= (uint32_t)0x0000FFFFU)
00087
00088 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      (((__VALUE__) == LL_DMA_REQUEST_0)  || \
00089                                                  ((__VALUE__) == LL_DMA_REQUEST_1)  || \
00090                                                  ((__VALUE__) == LL_DMA_REQUEST_2)  || \
00091                                                  ((__VALUE__) == LL_DMA_REQUEST_3)  || \
00092                                                  ((__VALUE__) == LL_DMA_REQUEST_4)  || \
00093                                                  ((__VALUE__) == LL_DMA_REQUEST_5)  || \
00094                                                  ((__VALUE__) == LL_DMA_REQUEST_6)  || \
00095                                                  ((__VALUE__) == LL_DMA_REQUEST_7))
00096
00097 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
00098                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
00099                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
00100                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
00101
00102 #if defined (DMA2)
00103 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
00104 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00105                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00106                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00107                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00108                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00109                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00110                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00111                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
00112                                                          (((INSTANCE) == DMA2) && \
00113                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00114                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00115                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00116                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00117                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00118                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00119                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))))
00120 #else
00121 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00122                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00123                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00124                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00125                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00126                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00127                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00128                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
00129                                                          (((INSTANCE) == DMA2) && \
00130                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00131                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00132                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00133                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00134                                                           ((CHANNEL) == LL_DMA_CHANNEL_5))))
00135 #endif
00136 #else
00137 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00138                                                             (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
00139                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00140                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00141                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00142                                                             ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00143                                                             ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00144                                                             ((CHANNEL) == LL_DMA_CHANNEL_7))))
00145 #endif
00146 /**
00147   * @}
00148   */
00149
00150 /* Private function prototypes -----------------------------------------------*/
00151
00152 /* Exported functions --------------------------------------------------------*/
00153 /** @addtogroup DMA_LL_Exported_Functions
00154   * @{
00155   */
00156
00157 /** @addtogroup DMA_LL_EF_Init
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  De-initialize the DMA registers to their default reset values.
00163   * @param  DMAx DMAx Instance
00164   * @param  Channel This parameter can be one of the following values:
00165   *         @arg @ref LL_DMA_CHANNEL_1
00166   *         @arg @ref LL_DMA_CHANNEL_2
00167   *         @arg @ref LL_DMA_CHANNEL_3
00168   *         @arg @ref LL_DMA_CHANNEL_4
00169   *         @arg @ref LL_DMA_CHANNEL_5
00170   *         @arg @ref LL_DMA_CHANNEL_6
00171   *         @arg @ref LL_DMA_CHANNEL_7
00172   *         @arg @ref LL_DMA_CHANNEL_ALL
00173   * @retval An ErrorStatus enumeration value:
00174   *          - SUCCESS: DMA registers are de-initialized
00175   *          - ERROR: DMA registers are not de-initialized
00176   */
00177 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
00178 {
00179   DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
00180   ErrorStatus status = SUCCESS;
00181
00182   /* Check the DMA Instance DMAx and Channel parameters*/
00183   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
00184
00185   if (Channel == LL_DMA_CHANNEL_ALL)
00186   {
00187     if (DMAx == DMA1)
00188     {
00189       /* Force reset of DMA clock */
00190       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
00191
00192       /* Release reset of DMA clock */
00193       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
00194     }
00195 #if defined(DMA2)
00196     else if (DMAx == DMA2)
00197     {
00198       /* Force reset of DMA clock */
00199       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
00200
00201       /* Release reset of DMA clock */
00202       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
00203     }
00204 #endif
00205     else
00206     {
00207       status = ERROR;
00208     }
00209   }
00210   else
00211   {
00212     tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
00213
00214     /* Disable the selected DMAx_Channely */
00215     CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
00216
00217     /* Reset DMAx_Channely control register */
00218     LL_DMA_WriteReg(tmp, CCR, 0U);
00219
00220     /* Reset DMAx_Channely remaining bytes register */
00221     LL_DMA_WriteReg(tmp, CNDTR, 0U);
00222
00223     /* Reset DMAx_Channely peripheral address register */
00224     LL_DMA_WriteReg(tmp, CPAR, 0U);
00225
00226     /* Reset DMAx_Channely memory address register */
00227     LL_DMA_WriteReg(tmp, CMAR, 0U);
00228
00229     /* Reset Request register field for DMAx Channel */
00230     LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
00231
00232     if (Channel == LL_DMA_CHANNEL_1)
00233     {
00234       /* Reset interrupt pending bits for DMAx Channel1 */
00235       LL_DMA_ClearFlag_GI1(DMAx);
00236     }
00237     else if (Channel == LL_DMA_CHANNEL_2)
00238     {
00239       /* Reset interrupt pending bits for DMAx Channel2 */
00240       LL_DMA_ClearFlag_GI2(DMAx);
00241     }
00242     else if (Channel == LL_DMA_CHANNEL_3)
00243     {
00244       /* Reset interrupt pending bits for DMAx Channel3 */
00245       LL_DMA_ClearFlag_GI3(DMAx);
00246     }
00247     else if (Channel == LL_DMA_CHANNEL_4)
00248     {
00249       /* Reset interrupt pending bits for DMAx Channel4 */
00250       LL_DMA_ClearFlag_GI4(DMAx);
00251     }
00252     else if (Channel == LL_DMA_CHANNEL_5)
00253     {
00254       /* Reset interrupt pending bits for DMAx Channel5 */
00255       LL_DMA_ClearFlag_GI5(DMAx);
00256     }
00257
00258     else if (Channel == LL_DMA_CHANNEL_6)
00259     {
00260       /* Reset interrupt pending bits for DMAx Channel6 */
00261       LL_DMA_ClearFlag_GI6(DMAx);
00262     }
00263     else if (Channel == LL_DMA_CHANNEL_7)
00264     {
00265       /* Reset interrupt pending bits for DMAx Channel7 */
00266       LL_DMA_ClearFlag_GI7(DMAx);
00267     }
00268     else
00269     {
00270       status = ERROR;
00271     }
00272   }
00273
00274   return status;
00275 }
00276
00277 /**
00278   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
00279   * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
00280   *         @arg @ref __LL_DMA_GET_INSTANCE
00281   *         @arg @ref __LL_DMA_GET_CHANNEL
00282   * @param  DMAx DMAx Instance
00283   * @param  Channel This parameter can be one of the following values:
00284   *         @arg @ref LL_DMA_CHANNEL_1
00285   *         @arg @ref LL_DMA_CHANNEL_2
00286   *         @arg @ref LL_DMA_CHANNEL_3
00287   *         @arg @ref LL_DMA_CHANNEL_4
00288   *         @arg @ref LL_DMA_CHANNEL_5
00289   *         @arg @ref LL_DMA_CHANNEL_6
00290   *         @arg @ref LL_DMA_CHANNEL_7
00291   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
00292   * @retval An ErrorStatus enumeration value:
00293   *          - SUCCESS: DMA registers are initialized
00294   *          - ERROR: Not applicable
00295   */
00296 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
00297 {
00298   /* Check the DMA Instance DMAx and Channel parameters*/
00299   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
00300
00301   /* Check the DMA parameters from DMA_InitStruct */
00302   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
00303   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
00304   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
00305   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
00306   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
00307   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
00308   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
00309   assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
00310   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
00311
00312   /*---------------------------- DMAx CCR Configuration ------------------------
00313    * Configure DMAx_Channely: data transfer direction, data transfer mode,
00314    *                          peripheral and memory increment mode,
00315    *                          data size alignment and  priority level with parameters :
00316    * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
00317    * - Mode:           DMA_CCR_CIRC bit
00318    * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
00319    * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
00320    * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
00321    * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
00322    * - Priority:               DMA_CCR_PL[1:0] bits
00323    */
00324   LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
00325                         DMA_InitStruct->Mode                   | \
00326                         DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
00327                         DMA_InitStruct->MemoryOrM2MDstIncMode  | \
00328                         DMA_InitStruct->PeriphOrM2MSrcDataSize | \
00329                         DMA_InitStruct->MemoryOrM2MDstDataSize | \
00330                         DMA_InitStruct->Priority);
00331
00332   /*-------------------------- DMAx CMAR Configuration -------------------------
00333    * Configure the memory or destination base address with parameter :
00334    * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
00335    */
00336   LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
00337
00338   /*-------------------------- DMAx CPAR Configuration -------------------------
00339    * Configure the peripheral or source base address with parameter :
00340    * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
00341    */
00342   LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
00343
00344   /*--------------------------- DMAx CNDTR Configuration -----------------------
00345    * Configure the peripheral base address with parameter :
00346    * - NbData: DMA_CNDTR_NDT[15:0] bits
00347    */
00348   LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
00349
00350   /*--------------------------- DMAx CSELR Configuration -----------------------
00351    * Configure the peripheral base address with parameter :
00352    * - PeriphRequest: DMA_CSELR[31:0] bits
00353    */
00354   LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
00355
00356   return SUCCESS;
00357 }
00358
00359 /**
00360   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
00361   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
00362   * @retval None
00363   */
00364 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
00365 {
00366   /* Set DMA_InitStruct fields to default values */
00367   DMA_InitStruct->PeriphOrM2MSrcAddress  = (uint32_t)0x00000000U;
00368   DMA_InitStruct->MemoryOrM2MDstAddress  = (uint32_t)0x00000000U;
00369   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
00370   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
00371   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
00372   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
00373   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
00374   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
00375   DMA_InitStruct->NbData                 = (uint32_t)0x00000000U;
00376   DMA_InitStruct->PeriphRequest          = LL_DMA_REQUEST_0;
00377   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
00378 }
00379
00380 /**
00381   * @}
00382   */
00383
00384 /**
00385   * @}
00386   */
00387
00388 /**
00389   * @}
00390   */
00391
00392 #endif /* DMA1 || DMA2 */
00393
00394 /**
00395   * @}
00396   */
00397
00398 #endif /* USE_FULL_LL_DRIVER */
00399
00400 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_dma.h Source File

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stm32l4xx_ll_dma.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_dma.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of DMA LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_DMA_H
00040 #define __STM32L4xx_LL_DMA_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (DMA1) || defined (DMA2)
00054
00055 /** @defgroup DMA_LL DMA
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
00062   * @{
00063   */
00064 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
00065 static const uint8_t CHANNEL_OFFSET_TAB[] =
00066 {
00067   (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
00068   (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
00069   (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
00070   (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
00071   (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
00072   (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
00073   (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
00074 };
00075 /**
00076   * @}
00077   */
00078
00079 /* Private constants ---------------------------------------------------------*/
00080 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
00081   * @{
00082   */
00083 /* Define used to get CSELR register offset */
00084 #define DMA_CSELR_OFFSET                  (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
00085
00086 /* Defines used for the bit position in the register and perform offsets */
00087 #define DMA_POSITION_CSELR_CXS            POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
00088 /**
00089   * @}
00090   */
00091
00092 /* Private macros ------------------------------------------------------------*/
00093 #if defined(USE_FULL_LL_DRIVER)
00094 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
00095   * @{
00096   */
00097 /**
00098   * @}
00099   */
00100 #endif /*USE_FULL_LL_DRIVER*/
00101
00102 /* Exported types ------------------------------------------------------------*/
00103 #if defined(USE_FULL_LL_DRIVER)
00104 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
00105   * @{
00106   */
00107 typedef struct
00108 {
00109   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
00110                                         or as Source base address in case of memory to memory transfer direction.
00111
00112                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00113
00114   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
00115                                         or as Destination base address in case of memory to memory transfer direction.
00116
00117                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00118
00119   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
00120                                         from memory to memory or from peripheral to memory.
00121                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
00122
00123                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
00124
00125   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
00126                                         This parameter can be a value of @ref DMA_LL_EC_MODE
00127                                         @note: The circular buffer mode cannot be used if the memory to memory
00128                                                data transfer direction is configured on the selected Channel
00129
00130                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
00131
00132   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
00133                                         is incremented or not.
00134                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
00135
00136                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
00137
00138   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
00139                                         is incremented or not.
00140                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
00141
00142                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
00143
00144   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
00145                                         in case of memory to memory transfer direction.
00146                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
00147
00148                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
00149
00150   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
00151                                         in case of memory to memory transfer direction.
00152                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
00153
00154                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
00155
00156   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
00157                                         The data unit is equal to the source buffer configuration set in PeripheralSize
00158                                         or MemorySize parameters depending in the transfer direction.
00159                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
00160
00161                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
00162
00163   uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
00164                                         This parameter can be a value of @ref DMA_LL_EC_REQUEST
00165
00166                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
00167
00168   uint32_t Priority;               /*!< Specifies the channel priority level.
00169                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
00170
00171                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
00172
00173 } LL_DMA_InitTypeDef;
00174 /**
00175   * @}
00176   */
00177 #endif /*USE_FULL_LL_DRIVER*/
00178
00179 /* Exported constants --------------------------------------------------------*/
00180 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
00181   * @{
00182   */
00183 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
00184   * @brief    Flags defines which can be used with LL_DMA_WriteReg function
00185   * @{
00186   */
00187 #define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
00188 #define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
00189 #define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
00190 #define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
00191 #define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
00192 #define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
00193 #define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
00194 #define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
00195 #define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
00196 #define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
00197 #define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
00198 #define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
00199 #define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
00200 #define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
00201 #define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
00202 #define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
00203 #define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
00204 #define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
00205 #define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
00206 #define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
00207 #define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
00208 #define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
00209 #define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
00210 #define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
00211 #define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
00212 #define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
00213 #define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
00214 #define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
00220   * @brief    Flags defines which can be used with LL_DMA_ReadReg function
00221   * @{
00222   */
00223 #define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
00224 #define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
00225 #define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
00226 #define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
00227 #define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
00228 #define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
00229 #define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
00230 #define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
00231 #define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
00232 #define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
00233 #define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
00234 #define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
00235 #define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
00236 #define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
00237 #define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
00238 #define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
00239 #define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
00240 #define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
00241 #define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
00242 #define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
00243 #define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
00244 #define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
00245 #define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
00246 #define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
00247 #define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
00248 #define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
00249 #define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
00250 #define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup DMA_LL_EC_IT IT Defines
00256   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
00257   * @{
00258   */
00259 #define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
00260 #define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
00261 #define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
00267   * @{
00268   */
00269 #define LL_DMA_CHANNEL_1                  ((uint32_t)0x00000001U) /*!< DMA Channel 1 */
00270 #define LL_DMA_CHANNEL_2                  ((uint32_t)0x00000002U) /*!< DMA Channel 2 */
00271 #define LL_DMA_CHANNEL_3                  ((uint32_t)0x00000003U) /*!< DMA Channel 3 */
00272 #define LL_DMA_CHANNEL_4                  ((uint32_t)0x00000004U) /*!< DMA Channel 4 */
00273 #define LL_DMA_CHANNEL_5                  ((uint32_t)0x00000005U) /*!< DMA Channel 5 */
00274 #define LL_DMA_CHANNEL_6                  ((uint32_t)0x00000006U) /*!< DMA Channel 6 */
00275 #define LL_DMA_CHANNEL_7                  ((uint32_t)0x00000007U) /*!< DMA Channel 7 */
00276 #if defined(USE_FULL_LL_DRIVER)
00277 #define LL_DMA_CHANNEL_ALL                ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
00278 #endif /*USE_FULL_LL_DRIVER*/
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
00284   * @{
00285   */
00286 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
00287 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
00288 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup DMA_LL_EC_MODE Transfer mode
00294   * @{
00295   */
00296 #define LL_DMA_MODE_NORMAL                ((uint32_t)0x00000000U) /*!< Normal Mode                  */
00297 #define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
00303   * @{
00304   */
00305 #define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
00306 #define LL_DMA_PERIPH_NOINCREMENT         ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
00312   * @{
00313   */
00314 #define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
00315 #define LL_DMA_MEMORY_NOINCREMENT         ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
00321   * @{
00322   */
00323 #define LL_DMA_PDATAALIGN_BYTE            ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte     */
00324 #define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
00325 #define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
00331   * @{
00332   */
00333 #define LL_DMA_MDATAALIGN_BYTE            ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte     */
00334 #define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
00335 #define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
00341   * @{
00342   */
00343 #define LL_DMA_PRIORITY_LOW               ((uint32_t)0x00000000U) /*!< Priority level : Low       */
00344 #define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
00345 #define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
00346 #define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
00352   * @{
00353   */
00354 #define LL_DMA_REQUEST_0                  ((uint32_t)0x00000000U) /*!< DMA peripheral request 0  */
00355 #define LL_DMA_REQUEST_1                  ((uint32_t)0x00000001U) /*!< DMA peripheral request 1  */
00356 #define LL_DMA_REQUEST_2                  ((uint32_t)0x00000002U) /*!< DMA peripheral request 2  */
00357 #define LL_DMA_REQUEST_3                  ((uint32_t)0x00000003U) /*!< DMA peripheral request 3  */
00358 #define LL_DMA_REQUEST_4                  ((uint32_t)0x00000004U) /*!< DMA peripheral request 4  */
00359 #define LL_DMA_REQUEST_5                  ((uint32_t)0x00000005U) /*!< DMA peripheral request 5  */
00360 #define LL_DMA_REQUEST_6                  ((uint32_t)0x00000006U) /*!< DMA peripheral request 6  */
00361 #define LL_DMA_REQUEST_7                  ((uint32_t)0x00000007U) /*!< DMA peripheral request 7  */
00362 /**
00363   * @}
00364   */
00365
00366 /**
00367   * @}
00368   */
00369
00370 /* Exported macro ------------------------------------------------------------*/
00371 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
00372   * @{
00373   */
00374
00375 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
00376   * @{
00377   */
00378 /**
00379   * @brief  Write a value in DMA register
00380   * @param  __INSTANCE__ DMA Instance
00381   * @param  __REG__ Register to be written
00382   * @param  __VALUE__ Value to be written in the register
00383   * @retval None
00384   */
00385 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00386
00387 /**
00388   * @brief  Read a value in DMA register
00389   * @param  __INSTANCE__ DMA Instance
00390   * @param  __REG__ Register to be read
00391   * @retval Register value
00392   */
00393 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
00399   * @{
00400   */
00401 /**
00402   * @brief  Convert DMAx_Channely into DMAx
00403   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00404   * @retval DMAx
00405   */
00406 #if defined(DMA2)
00407 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
00408 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ?  DMA2 : DMA1)
00409 #else
00410 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
00411 #endif
00412
00413 /**
00414   * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
00415   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00416   * @retval LL_DMA_CHANNEL_y
00417   */
00418 #if defined (DMA2)
00419 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
00420 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00421 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00422  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
00423  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00424  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
00425  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00426  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
00427  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00428  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
00429  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00430  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
00431  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00432  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
00433  LL_DMA_CHANNEL_7)
00434 #else
00435 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00436 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00437  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
00438  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00439  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
00440  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00441  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
00442  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00443  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
00444  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00445  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
00446  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00447  LL_DMA_CHANNEL_7)
00448 #endif
00449 #else
00450 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00451 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00452  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00453  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00454  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00455  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00456  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00457  LL_DMA_CHANNEL_7)
00458 #endif
00459
00460 /**
00461   * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
00462   * @param  __DMA_INSTANCE__ DMAx
00463   * @param  __CHANNEL__ LL_DMA_CHANNEL_y
00464   * @retval DMAx_Channely
00465   */
00466 #if defined (DMA2)
00467 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
00468 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00469 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00470  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
00471  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00472  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
00473  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00474  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
00475  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00476  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
00477  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00478  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
00479  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00480  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
00481  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
00482  DMA2_Channel7)
00483 #else
00484 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00485 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00486  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
00487  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00488  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
00489  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00490  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
00491  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00492  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
00493  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00494  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
00495  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00496  DMA1_Channel7)
00497 #endif
00498 #else
00499 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00500 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00501  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00502  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00503  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00504  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00505  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00506  DMA1_Channel7)
00507 #endif
00508
00509 /**
00510   * @}
00511   */
00512
00513 /**
00514   * @}
00515   */
00516
00517 /* Exported functions --------------------------------------------------------*/
00518 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
00519  * @{
00520  */
00521
00522 /** @defgroup DMA_LL_EF_Configuration Configuration
00523   * @{
00524   */
00525 /**
00526   * @brief  Enable DMA channel.
00527   * @rmtoll CCR          EN            LL_DMA_EnableChannel
00528   * @param  DMAx DMAx Instance
00529   * @param  Channel This parameter can be one of the following values:
00530   *         @arg @ref LL_DMA_CHANNEL_1
00531   *         @arg @ref LL_DMA_CHANNEL_2
00532   *         @arg @ref LL_DMA_CHANNEL_3
00533   *         @arg @ref LL_DMA_CHANNEL_4
00534   *         @arg @ref LL_DMA_CHANNEL_5
00535   *         @arg @ref LL_DMA_CHANNEL_6
00536   *         @arg @ref LL_DMA_CHANNEL_7
00537   * @retval None
00538   */
00539 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00540 {
00541   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
00542 }
00543
00544 /**
00545   * @brief  Disable DMA channel.
00546   * @rmtoll CCR          EN            LL_DMA_DisableChannel
00547   * @param  DMAx DMAx Instance
00548   * @param  Channel This parameter can be one of the following values:
00549   *         @arg @ref LL_DMA_CHANNEL_1
00550   *         @arg @ref LL_DMA_CHANNEL_2
00551   *         @arg @ref LL_DMA_CHANNEL_3
00552   *         @arg @ref LL_DMA_CHANNEL_4
00553   *         @arg @ref LL_DMA_CHANNEL_5
00554   *         @arg @ref LL_DMA_CHANNEL_6
00555   *         @arg @ref LL_DMA_CHANNEL_7
00556   * @retval None
00557   */
00558 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00559 {
00560   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
00561 }
00562
00563 /**
00564   * @brief  Check if DMA channel is enabled or disabled.
00565   * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
00566   * @param  DMAx DMAx Instance
00567   * @param  Channel This parameter can be one of the following values:
00568   *         @arg @ref LL_DMA_CHANNEL_1
00569   *         @arg @ref LL_DMA_CHANNEL_2
00570   *         @arg @ref LL_DMA_CHANNEL_3
00571   *         @arg @ref LL_DMA_CHANNEL_4
00572   *         @arg @ref LL_DMA_CHANNEL_5
00573   *         @arg @ref LL_DMA_CHANNEL_6
00574   *         @arg @ref LL_DMA_CHANNEL_7
00575   * @retval State of bit (1 or 0).
00576   */
00577 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00578 {
00579   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00580                    DMA_CCR_EN) == (DMA_CCR_EN));
00581 }
00582
00583 /**
00584   * @brief  Configure all parameters link to DMA transfer.
00585   * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
00586   *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
00587   *         CCR          CIRC          LL_DMA_ConfigTransfer\n
00588   *         CCR          PINC          LL_DMA_ConfigTransfer\n
00589   *         CCR          MINC          LL_DMA_ConfigTransfer\n
00590   *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
00591   *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
00592   *         CCR          PL            LL_DMA_ConfigTransfer
00593   * @param  DMAx DMAx Instance
00594   * @param  Channel This parameter can be one of the following values:
00595   *         @arg @ref LL_DMA_CHANNEL_1
00596   *         @arg @ref LL_DMA_CHANNEL_2
00597   *         @arg @ref LL_DMA_CHANNEL_3
00598   *         @arg @ref LL_DMA_CHANNEL_4
00599   *         @arg @ref LL_DMA_CHANNEL_5
00600   *         @arg @ref LL_DMA_CHANNEL_6
00601   *         @arg @ref LL_DMA_CHANNEL_7
00602   * @param  Configuration This parameter must be a combination of all the following values:
00603   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00604   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
00605   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
00606   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
00607   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
00608   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
00609   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
00610   * @retval None
00611   */
00612 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
00613 {
00614   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00615              DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
00616              Configuration);
00617 }
00618
00619 /**
00620   * @brief  Set Data transfer direction (read from peripheral or from memory).
00621   * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
00622   *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
00623   * @param  DMAx DMAx Instance
00624   * @param  Channel This parameter can be one of the following values:
00625   *         @arg @ref LL_DMA_CHANNEL_1
00626   *         @arg @ref LL_DMA_CHANNEL_2
00627   *         @arg @ref LL_DMA_CHANNEL_3
00628   *         @arg @ref LL_DMA_CHANNEL_4
00629   *         @arg @ref LL_DMA_CHANNEL_5
00630   *         @arg @ref LL_DMA_CHANNEL_6
00631   *         @arg @ref LL_DMA_CHANNEL_7
00632   * @param  Direction This parameter can be one of the following values:
00633   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00634   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00635   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00636   * @retval None
00637   */
00638 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
00639 {
00640   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00641              DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
00642 }
00643
00644 /**
00645   * @brief  Get Data transfer direction (read from peripheral or from memory).
00646   * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
00647   *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
00648   * @param  DMAx DMAx Instance
00649   * @param  Channel This parameter can be one of the following values:
00650   *         @arg @ref LL_DMA_CHANNEL_1
00651   *         @arg @ref LL_DMA_CHANNEL_2
00652   *         @arg @ref LL_DMA_CHANNEL_3
00653   *         @arg @ref LL_DMA_CHANNEL_4
00654   *         @arg @ref LL_DMA_CHANNEL_5
00655   *         @arg @ref LL_DMA_CHANNEL_6
00656   *         @arg @ref LL_DMA_CHANNEL_7
00657   * @retval Returned value can be one of the following values:
00658   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00659   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00660   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00661   */
00662 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
00663 {
00664   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00665                    DMA_CCR_DIR | DMA_CCR_MEM2MEM));
00666 }
00667
00668 /**
00669   * @brief  Set DMA mode circular or normal.
00670   * @note The circular buffer mode cannot be used if the memory-to-memory
00671   * data transfer is configured on the selected Channel.
00672   * @rmtoll CCR          CIRC          LL_DMA_SetMode
00673   * @param  DMAx DMAx Instance
00674   * @param  Channel This parameter can be one of the following values:
00675   *         @arg @ref LL_DMA_CHANNEL_1
00676   *         @arg @ref LL_DMA_CHANNEL_2
00677   *         @arg @ref LL_DMA_CHANNEL_3
00678   *         @arg @ref LL_DMA_CHANNEL_4
00679   *         @arg @ref LL_DMA_CHANNEL_5
00680   *         @arg @ref LL_DMA_CHANNEL_6
00681   *         @arg @ref LL_DMA_CHANNEL_7
00682   * @param  Mode This parameter can be one of the following values:
00683   *         @arg @ref LL_DMA_MODE_NORMAL
00684   *         @arg @ref LL_DMA_MODE_CIRCULAR
00685   * @retval None
00686   */
00687 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
00688 {
00689   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
00690              Mode);
00691 }
00692
00693 /**
00694   * @brief  Get DMA mode circular or normal.
00695   * @rmtoll CCR          CIRC          LL_DMA_GetMode
00696   * @param  DMAx DMAx Instance
00697   * @param  Channel This parameter can be one of the following values:
00698   *         @arg @ref LL_DMA_CHANNEL_1
00699   *         @arg @ref LL_DMA_CHANNEL_2
00700   *         @arg @ref LL_DMA_CHANNEL_3
00701   *         @arg @ref LL_DMA_CHANNEL_4
00702   *         @arg @ref LL_DMA_CHANNEL_5
00703   *         @arg @ref LL_DMA_CHANNEL_6
00704   *         @arg @ref LL_DMA_CHANNEL_7
00705   * @retval Returned value can be one of the following values:
00706   *         @arg @ref LL_DMA_MODE_NORMAL
00707   *         @arg @ref LL_DMA_MODE_CIRCULAR
00708   */
00709 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
00710 {
00711   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00712                    DMA_CCR_CIRC));
00713 }
00714
00715 /**
00716   * @brief  Set Peripheral increment mode.
00717   * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
00718   * @param  DMAx DMAx Instance
00719   * @param  Channel This parameter can be one of the following values:
00720   *         @arg @ref LL_DMA_CHANNEL_1
00721   *         @arg @ref LL_DMA_CHANNEL_2
00722   *         @arg @ref LL_DMA_CHANNEL_3
00723   *         @arg @ref LL_DMA_CHANNEL_4
00724   *         @arg @ref LL_DMA_CHANNEL_5
00725   *         @arg @ref LL_DMA_CHANNEL_6
00726   *         @arg @ref LL_DMA_CHANNEL_7
00727   * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
00728   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00729   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00730   * @retval None
00731   */
00732 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
00733 {
00734   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
00735              PeriphOrM2MSrcIncMode);
00736 }
00737
00738 /**
00739   * @brief  Get Peripheral increment mode.
00740   * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
00741   * @param  DMAx DMAx Instance
00742   * @param  Channel This parameter can be one of the following values:
00743   *         @arg @ref LL_DMA_CHANNEL_1
00744   *         @arg @ref LL_DMA_CHANNEL_2
00745   *         @arg @ref LL_DMA_CHANNEL_3
00746   *         @arg @ref LL_DMA_CHANNEL_4
00747   *         @arg @ref LL_DMA_CHANNEL_5
00748   *         @arg @ref LL_DMA_CHANNEL_6
00749   *         @arg @ref LL_DMA_CHANNEL_7
00750   * @retval Returned value can be one of the following values:
00751   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00752   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00753   */
00754 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00755 {
00756   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00757                    DMA_CCR_PINC));
00758 }
00759
00760 /**
00761   * @brief  Set Memory increment mode.
00762   * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
00763   * @param  DMAx DMAx Instance
00764   * @param  Channel This parameter can be one of the following values:
00765   *         @arg @ref LL_DMA_CHANNEL_1
00766   *         @arg @ref LL_DMA_CHANNEL_2
00767   *         @arg @ref LL_DMA_CHANNEL_3
00768   *         @arg @ref LL_DMA_CHANNEL_4
00769   *         @arg @ref LL_DMA_CHANNEL_5
00770   *         @arg @ref LL_DMA_CHANNEL_6
00771   *         @arg @ref LL_DMA_CHANNEL_7
00772   * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
00773   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00774   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00775   * @retval None
00776   */
00777 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
00778 {
00779   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
00780              MemoryOrM2MDstIncMode);
00781 }
00782
00783 /**
00784   * @brief  Get Memory increment mode.
00785   * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
00786   * @param  DMAx DMAx Instance
00787   * @param  Channel This parameter can be one of the following values:
00788   *         @arg @ref LL_DMA_CHANNEL_1
00789   *         @arg @ref LL_DMA_CHANNEL_2
00790   *         @arg @ref LL_DMA_CHANNEL_3
00791   *         @arg @ref LL_DMA_CHANNEL_4
00792   *         @arg @ref LL_DMA_CHANNEL_5
00793   *         @arg @ref LL_DMA_CHANNEL_6
00794   *         @arg @ref LL_DMA_CHANNEL_7
00795   * @retval Returned value can be one of the following values:
00796   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00797   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00798   */
00799 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00800 {
00801   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00802                    DMA_CCR_MINC));
00803 }
00804
00805 /**
00806   * @brief  Set Peripheral size.
00807   * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
00808   * @param  DMAx DMAx Instance
00809   * @param  Channel This parameter can be one of the following values:
00810   *         @arg @ref LL_DMA_CHANNEL_1
00811   *         @arg @ref LL_DMA_CHANNEL_2
00812   *         @arg @ref LL_DMA_CHANNEL_3
00813   *         @arg @ref LL_DMA_CHANNEL_4
00814   *         @arg @ref LL_DMA_CHANNEL_5
00815   *         @arg @ref LL_DMA_CHANNEL_6
00816   *         @arg @ref LL_DMA_CHANNEL_7
00817   * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
00818   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00819   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00820   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00821   * @retval None
00822   */
00823 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
00824 {
00825   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
00826              PeriphOrM2MSrcDataSize);
00827 }
00828
00829 /**
00830   * @brief  Get Peripheral size.
00831   * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
00832   * @param  DMAx DMAx Instance
00833   * @param  Channel This parameter can be one of the following values:
00834   *         @arg @ref LL_DMA_CHANNEL_1
00835   *         @arg @ref LL_DMA_CHANNEL_2
00836   *         @arg @ref LL_DMA_CHANNEL_3
00837   *         @arg @ref LL_DMA_CHANNEL_4
00838   *         @arg @ref LL_DMA_CHANNEL_5
00839   *         @arg @ref LL_DMA_CHANNEL_6
00840   *         @arg @ref LL_DMA_CHANNEL_7
00841   * @retval Returned value can be one of the following values:
00842   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00843   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00844   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00845   */
00846 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
00847 {
00848   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00849                    DMA_CCR_PSIZE));
00850 }
00851
00852 /**
00853   * @brief  Set Memory size.
00854   * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
00855   * @param  DMAx DMAx Instance
00856   * @param  Channel This parameter can be one of the following values:
00857   *         @arg @ref LL_DMA_CHANNEL_1
00858   *         @arg @ref LL_DMA_CHANNEL_2
00859   *         @arg @ref LL_DMA_CHANNEL_3
00860   *         @arg @ref LL_DMA_CHANNEL_4
00861   *         @arg @ref LL_DMA_CHANNEL_5
00862   *         @arg @ref LL_DMA_CHANNEL_6
00863   *         @arg @ref LL_DMA_CHANNEL_7
00864   * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
00865   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00866   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00867   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00868   * @retval None
00869   */
00870 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
00871 {
00872   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
00873              MemoryOrM2MDstDataSize);
00874 }
00875
00876 /**
00877   * @brief  Get Memory size.
00878   * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
00879   * @param  DMAx DMAx Instance
00880   * @param  Channel This parameter can be one of the following values:
00881   *         @arg @ref LL_DMA_CHANNEL_1
00882   *         @arg @ref LL_DMA_CHANNEL_2
00883   *         @arg @ref LL_DMA_CHANNEL_3
00884   *         @arg @ref LL_DMA_CHANNEL_4
00885   *         @arg @ref LL_DMA_CHANNEL_5
00886   *         @arg @ref LL_DMA_CHANNEL_6
00887   *         @arg @ref LL_DMA_CHANNEL_7
00888   * @retval Returned value can be one of the following values:
00889   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00890   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00891   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00892   */
00893 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
00894 {
00895   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00896                    DMA_CCR_MSIZE));
00897 }
00898
00899 /**
00900   * @brief  Set Channel priority level.
00901   * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
00902   * @param  DMAx DMAx Instance
00903   * @param  Channel This parameter can be one of the following values:
00904   *         @arg @ref LL_DMA_CHANNEL_1
00905   *         @arg @ref LL_DMA_CHANNEL_2
00906   *         @arg @ref LL_DMA_CHANNEL_3
00907   *         @arg @ref LL_DMA_CHANNEL_4
00908   *         @arg @ref LL_DMA_CHANNEL_5
00909   *         @arg @ref LL_DMA_CHANNEL_6
00910   *         @arg @ref LL_DMA_CHANNEL_7
00911   * @param  Priority This parameter can be one of the following values:
00912   *         @arg @ref LL_DMA_PRIORITY_LOW
00913   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00914   *         @arg @ref LL_DMA_PRIORITY_HIGH
00915   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00916   * @retval None
00917   */
00918 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
00919 {
00920   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
00921              Priority);
00922 }
00923
00924 /**
00925   * @brief  Get Channel priority level.
00926   * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
00927   * @param  DMAx DMAx Instance
00928   * @param  Channel This parameter can be one of the following values:
00929   *         @arg @ref LL_DMA_CHANNEL_1
00930   *         @arg @ref LL_DMA_CHANNEL_2
00931   *         @arg @ref LL_DMA_CHANNEL_3
00932   *         @arg @ref LL_DMA_CHANNEL_4
00933   *         @arg @ref LL_DMA_CHANNEL_5
00934   *         @arg @ref LL_DMA_CHANNEL_6
00935   *         @arg @ref LL_DMA_CHANNEL_7
00936   * @retval Returned value can be one of the following values:
00937   *         @arg @ref LL_DMA_PRIORITY_LOW
00938   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00939   *         @arg @ref LL_DMA_PRIORITY_HIGH
00940   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00941   */
00942 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
00943 {
00944   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00945                    DMA_CCR_PL));
00946 }
00947
00948 /**
00949   * @brief  Set Number of data to transfer.
00950   * @note   This action has no effect if
00951   *         channel is enabled.
00952   * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
00953   * @param  DMAx DMAx Instance
00954   * @param  Channel This parameter can be one of the following values:
00955   *         @arg @ref LL_DMA_CHANNEL_1
00956   *         @arg @ref LL_DMA_CHANNEL_2
00957   *         @arg @ref LL_DMA_CHANNEL_3
00958   *         @arg @ref LL_DMA_CHANNEL_4
00959   *         @arg @ref LL_DMA_CHANNEL_5
00960   *         @arg @ref LL_DMA_CHANNEL_6
00961   *         @arg @ref LL_DMA_CHANNEL_7
00962   * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
00963   * @retval None
00964   */
00965 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
00966 {
00967   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
00968              DMA_CNDTR_NDT, NbData);
00969 }
00970
00971 /**
00972   * @brief  Get Number of data to transfer.
00973   * @note   Once the channel is enabled, the return value indicate the
00974   *         remaining bytes to be transmitted.
00975   * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
00976   * @param  DMAx DMAx Instance
00977   * @param  Channel This parameter can be one of the following values:
00978   *         @arg @ref LL_DMA_CHANNEL_1
00979   *         @arg @ref LL_DMA_CHANNEL_2
00980   *         @arg @ref LL_DMA_CHANNEL_3
00981   *         @arg @ref LL_DMA_CHANNEL_4
00982   *         @arg @ref LL_DMA_CHANNEL_5
00983   *         @arg @ref LL_DMA_CHANNEL_6
00984   *         @arg @ref LL_DMA_CHANNEL_7
00985   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00986   */
00987 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
00988 {
00989   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
00990                    DMA_CNDTR_NDT));
00991 }
00992
00993 /**
00994   * @brief  Configure the Source and Destination addresses.
00995   * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
00996   * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
00997   *         CMAR         MA            LL_DMA_ConfigAddresses
00998   * @param  DMAx DMAx Instance
00999   * @param  Channel This parameter can be one of the following values:
01000   *         @arg @ref LL_DMA_CHANNEL_1
01001   *         @arg @ref LL_DMA_CHANNEL_2
01002   *         @arg @ref LL_DMA_CHANNEL_3
01003   *         @arg @ref LL_DMA_CHANNEL_4
01004   *         @arg @ref LL_DMA_CHANNEL_5
01005   *         @arg @ref LL_DMA_CHANNEL_6
01006   *         @arg @ref LL_DMA_CHANNEL_7
01007   * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01008   * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01009   * @param  Direction This parameter can be one of the following values:
01010   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
01011   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
01012   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
01013   * @retval None
01014   */
01015 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
01016                                             uint32_t DstAddress, uint32_t Direction)
01017 {
01018   /* Direction Memory to Periph */
01019   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
01020   {
01021     MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
01022                SrcAddress);
01023     MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
01024                DstAddress);
01025   }
01026   /* Direction Periph to Memory and Memory to Memory */
01027   else
01028   {
01029     MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
01030                SrcAddress);
01031     MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
01032                DstAddress);
01033   }
01034 }
01035
01036 /**
01037   * @brief  Set the Memory address.
01038   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01039   * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
01040   * @param  DMAx DMAx Instance
01041   * @param  Channel This parameter can be one of the following values:
01042   *         @arg @ref LL_DMA_CHANNEL_1
01043   *         @arg @ref LL_DMA_CHANNEL_2
01044   *         @arg @ref LL_DMA_CHANNEL_3
01045   *         @arg @ref LL_DMA_CHANNEL_4
01046   *         @arg @ref LL_DMA_CHANNEL_5
01047   *         @arg @ref LL_DMA_CHANNEL_6
01048   *         @arg @ref LL_DMA_CHANNEL_7
01049   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01050   * @retval None
01051   */
01052 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01053 {
01054   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
01055              MemoryAddress);
01056 }
01057
01058 /**
01059   * @brief  Set the Peripheral address.
01060   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01061   * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
01062   * @param  DMAx DMAx Instance
01063   * @param  Channel This parameter can be one of the following values:
01064   *         @arg @ref LL_DMA_CHANNEL_1
01065   *         @arg @ref LL_DMA_CHANNEL_2
01066   *         @arg @ref LL_DMA_CHANNEL_3
01067   *         @arg @ref LL_DMA_CHANNEL_4
01068   *         @arg @ref LL_DMA_CHANNEL_5
01069   *         @arg @ref LL_DMA_CHANNEL_6
01070   *         @arg @ref LL_DMA_CHANNEL_7
01071   * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01072   * @retval None
01073   */
01074 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
01075 {
01076   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
01077              PeriphAddress);
01078 }
01079
01080 /**
01081   * @brief  Get Memory address.
01082   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01083   * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
01084   * @param  DMAx DMAx Instance
01085   * @param  Channel This parameter can be one of the following values:
01086   *         @arg @ref LL_DMA_CHANNEL_1
01087   *         @arg @ref LL_DMA_CHANNEL_2
01088   *         @arg @ref LL_DMA_CHANNEL_3
01089   *         @arg @ref LL_DMA_CHANNEL_4
01090   *         @arg @ref LL_DMA_CHANNEL_5
01091   *         @arg @ref LL_DMA_CHANNEL_6
01092   *         @arg @ref LL_DMA_CHANNEL_7
01093   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01094   */
01095 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01096 {
01097   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
01098                    DMA_CMAR_MA));
01099 }
01100
01101 /**
01102   * @brief  Get Peripheral address.
01103   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01104   * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
01105   * @param  DMAx DMAx Instance
01106   * @param  Channel This parameter can be one of the following values:
01107   *         @arg @ref LL_DMA_CHANNEL_1
01108   *         @arg @ref LL_DMA_CHANNEL_2
01109   *         @arg @ref LL_DMA_CHANNEL_3
01110   *         @arg @ref LL_DMA_CHANNEL_4
01111   *         @arg @ref LL_DMA_CHANNEL_5
01112   *         @arg @ref LL_DMA_CHANNEL_6
01113   *         @arg @ref LL_DMA_CHANNEL_7
01114   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01115   */
01116 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01117 {
01118   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
01119                    DMA_CPAR_PA));
01120 }
01121
01122 /**
01123   * @brief  Set the Memory to Memory Source address.
01124   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01125   * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
01126   * @param  DMAx DMAx Instance
01127   * @param  Channel This parameter can be one of the following values:
01128   *         @arg @ref LL_DMA_CHANNEL_1
01129   *         @arg @ref LL_DMA_CHANNEL_2
01130   *         @arg @ref LL_DMA_CHANNEL_3
01131   *         @arg @ref LL_DMA_CHANNEL_4
01132   *         @arg @ref LL_DMA_CHANNEL_5
01133   *         @arg @ref LL_DMA_CHANNEL_6
01134   *         @arg @ref LL_DMA_CHANNEL_7
01135   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01136   * @retval None
01137   */
01138 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01139 {
01140   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
01141              MemoryAddress);
01142 }
01143
01144 /**
01145   * @brief  Set the Memory to Memory Destination address.
01146   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01147   * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
01148   * @param  DMAx DMAx Instance
01149   * @param  Channel This parameter can be one of the following values:
01150   *         @arg @ref LL_DMA_CHANNEL_1
01151   *         @arg @ref LL_DMA_CHANNEL_2
01152   *         @arg @ref LL_DMA_CHANNEL_3
01153   *         @arg @ref LL_DMA_CHANNEL_4
01154   *         @arg @ref LL_DMA_CHANNEL_5
01155   *         @arg @ref LL_DMA_CHANNEL_6
01156   *         @arg @ref LL_DMA_CHANNEL_7
01157   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01158   * @retval None
01159   */
01160 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01161 {
01162   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
01163              MemoryAddress);
01164 }
01165
01166 /**
01167   * @brief  Get the Memory to Memory Source address.
01168   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01169   * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
01170   * @param  DMAx DMAx Instance
01171   * @param  Channel This parameter can be one of the following values:
01172   *         @arg @ref LL_DMA_CHANNEL_1
01173   *         @arg @ref LL_DMA_CHANNEL_2
01174   *         @arg @ref LL_DMA_CHANNEL_3
01175   *         @arg @ref LL_DMA_CHANNEL_4
01176   *         @arg @ref LL_DMA_CHANNEL_5
01177   *         @arg @ref LL_DMA_CHANNEL_6
01178   *         @arg @ref LL_DMA_CHANNEL_7
01179   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01180   */
01181 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01182 {
01183   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
01184                    DMA_CPAR_PA));
01185 }
01186
01187 /**
01188   * @brief  Get the Memory to Memory Destination address.
01189   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01190   * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
01191   * @param  DMAx DMAx Instance
01192   * @param  Channel This parameter can be one of the following values:
01193   *         @arg @ref LL_DMA_CHANNEL_1
01194   *         @arg @ref LL_DMA_CHANNEL_2
01195   *         @arg @ref LL_DMA_CHANNEL_3
01196   *         @arg @ref LL_DMA_CHANNEL_4
01197   *         @arg @ref LL_DMA_CHANNEL_5
01198   *         @arg @ref LL_DMA_CHANNEL_6
01199   *         @arg @ref LL_DMA_CHANNEL_7
01200   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01201   */
01202 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01203 {
01204   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
01205                    DMA_CMAR_MA));
01206 }
01207
01208 /**
01209   * @brief  Set DMA request for DMA instance on Channel x.
01210   * @note   Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
01211   * @rmtoll CSELR        C1S           LL_DMA_SetPeriphRequest\n
01212   *         CSELR        C2S           LL_DMA_SetPeriphRequest\n
01213   *         CSELR        C3S           LL_DMA_SetPeriphRequest\n
01214   *         CSELR        C4S           LL_DMA_SetPeriphRequest\n
01215   *         CSELR        C5S           LL_DMA_SetPeriphRequest\n
01216   *         CSELR        C6S           LL_DMA_SetPeriphRequest\n
01217   *         CSELR        C7S           LL_DMA_SetPeriphRequest
01218   * @param  DMAx DMAx Instance
01219   * @param  Channel This parameter can be one of the following values:
01220   *         @arg @ref LL_DMA_CHANNEL_1
01221   *         @arg @ref LL_DMA_CHANNEL_2
01222   *         @arg @ref LL_DMA_CHANNEL_3
01223   *         @arg @ref LL_DMA_CHANNEL_4
01224   *         @arg @ref LL_DMA_CHANNEL_5
01225   *         @arg @ref LL_DMA_CHANNEL_6
01226   *         @arg @ref LL_DMA_CHANNEL_7
01227   * @param  PeriphRequest This parameter can be one of the following values:
01228   *         @arg @ref LL_DMA_REQUEST_0
01229   *         @arg @ref LL_DMA_REQUEST_1
01230   *         @arg @ref LL_DMA_REQUEST_2
01231   *         @arg @ref LL_DMA_REQUEST_3
01232   *         @arg @ref LL_DMA_REQUEST_4
01233   *         @arg @ref LL_DMA_REQUEST_5
01234   *         @arg @ref LL_DMA_REQUEST_6
01235   *         @arg @ref LL_DMA_REQUEST_7
01236   * @retval None
01237   */
01238 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
01239 {
01240   MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
01241              DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
01242 }
01243
01244 /**
01245   * @brief  Get DMA request for DMA instance on Channel x.
01246   * @rmtoll CSELR        C1S           LL_DMA_GetPeriphRequest\n
01247   *         CSELR        C2S           LL_DMA_GetPeriphRequest\n
01248   *         CSELR        C3S           LL_DMA_GetPeriphRequest\n
01249   *         CSELR        C4S           LL_DMA_GetPeriphRequest\n
01250   *         CSELR        C5S           LL_DMA_GetPeriphRequest\n
01251   *         CSELR        C6S           LL_DMA_GetPeriphRequest\n
01252   *         CSELR        C7S           LL_DMA_GetPeriphRequest
01253   * @param  DMAx DMAx Instance
01254   * @param  Channel This parameter can be one of the following values:
01255   *         @arg @ref LL_DMA_CHANNEL_1
01256   *         @arg @ref LL_DMA_CHANNEL_2
01257   *         @arg @ref LL_DMA_CHANNEL_3
01258   *         @arg @ref LL_DMA_CHANNEL_4
01259   *         @arg @ref LL_DMA_CHANNEL_5
01260   *         @arg @ref LL_DMA_CHANNEL_6
01261   *         @arg @ref LL_DMA_CHANNEL_7
01262   * @retval Returned value can be one of the following values:
01263   *         @arg @ref LL_DMA_REQUEST_0
01264   *         @arg @ref LL_DMA_REQUEST_1
01265   *         @arg @ref LL_DMA_REQUEST_2
01266   *         @arg @ref LL_DMA_REQUEST_3
01267   *         @arg @ref LL_DMA_REQUEST_4
01268   *         @arg @ref LL_DMA_REQUEST_5
01269   *         @arg @ref LL_DMA_REQUEST_6
01270   *         @arg @ref LL_DMA_REQUEST_7
01271   */
01272 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
01273 {
01274   return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
01275                    DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
01276 }
01277
01278 /**
01279   * @}
01280   */
01281
01282 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
01283   * @{
01284   */
01285
01286 /**
01287   * @brief  Get Channel 1 global interrupt flag.
01288   * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
01289   * @param  DMAx DMAx Instance
01290   * @retval State of bit (1 or 0).
01291   */
01292 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
01293 {
01294   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
01295 }
01296
01297 /**
01298   * @brief  Get Channel 2 global interrupt flag.
01299   * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
01300   * @param  DMAx DMAx Instance
01301   * @retval State of bit (1 or 0).
01302   */
01303 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
01304 {
01305   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
01306 }
01307
01308 /**
01309   * @brief  Get Channel 3 global interrupt flag.
01310   * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
01311   * @param  DMAx DMAx Instance
01312   * @retval State of bit (1 or 0).
01313   */
01314 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
01315 {
01316   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
01317 }
01318
01319 /**
01320   * @brief  Get Channel 4 global interrupt flag.
01321   * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
01322   * @param  DMAx DMAx Instance
01323   * @retval State of bit (1 or 0).
01324   */
01325 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
01326 {
01327   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
01328 }
01329
01330 /**
01331   * @brief  Get Channel 5 global interrupt flag.
01332   * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
01333   * @param  DMAx DMAx Instance
01334   * @retval State of bit (1 or 0).
01335   */
01336 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
01337 {
01338   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
01339 }
01340
01341 /**
01342   * @brief  Get Channel 6 global interrupt flag.
01343   * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
01344   * @param  DMAx DMAx Instance
01345   * @retval State of bit (1 or 0).
01346   */
01347 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
01348 {
01349   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
01350 }
01351
01352 /**
01353   * @brief  Get Channel 7 global interrupt flag.
01354   * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
01355   * @param  DMAx DMAx Instance
01356   * @retval State of bit (1 or 0).
01357   */
01358 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
01359 {
01360   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
01361 }
01362
01363 /**
01364   * @brief  Get Channel 1 transfer complete flag.
01365   * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
01366   * @param  DMAx DMAx Instance
01367   * @retval State of bit (1 or 0).
01368   */
01369 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
01370 {
01371   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
01372 }
01373
01374 /**
01375   * @brief  Get Channel 2 transfer complete flag.
01376   * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
01377   * @param  DMAx DMAx Instance
01378   * @retval State of bit (1 or 0).
01379   */
01380 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
01381 {
01382   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
01383 }
01384
01385 /**
01386   * @brief  Get Channel 3 transfer complete flag.
01387   * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
01388   * @param  DMAx DMAx Instance
01389   * @retval State of bit (1 or 0).
01390   */
01391 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
01392 {
01393   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
01394 }
01395
01396 /**
01397   * @brief  Get Channel 4 transfer complete flag.
01398   * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
01399   * @param  DMAx DMAx Instance
01400   * @retval State of bit (1 or 0).
01401   */
01402 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
01403 {
01404   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
01405 }
01406
01407 /**
01408   * @brief  Get Channel 5 transfer complete flag.
01409   * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
01410   * @param  DMAx DMAx Instance
01411   * @retval State of bit (1 or 0).
01412   */
01413 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
01414 {
01415   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
01416 }
01417
01418 /**
01419   * @brief  Get Channel 6 transfer complete flag.
01420   * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
01421   * @param  DMAx DMAx Instance
01422   * @retval State of bit (1 or 0).
01423   */
01424 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
01425 {
01426   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
01427 }
01428
01429 /**
01430   * @brief  Get Channel 7 transfer complete flag.
01431   * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
01432   * @param  DMAx DMAx Instance
01433   * @retval State of bit (1 or 0).
01434   */
01435 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
01436 {
01437   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
01438 }
01439
01440 /**
01441   * @brief  Get Channel 1 half transfer flag.
01442   * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
01443   * @param  DMAx DMAx Instance
01444   * @retval State of bit (1 or 0).
01445   */
01446 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
01447 {
01448   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
01449 }
01450
01451 /**
01452   * @brief  Get Channel 2 half transfer flag.
01453   * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
01454   * @param  DMAx DMAx Instance
01455   * @retval State of bit (1 or 0).
01456   */
01457 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
01458 {
01459   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
01460 }
01461
01462 /**
01463   * @brief  Get Channel 3 half transfer flag.
01464   * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
01465   * @param  DMAx DMAx Instance
01466   * @retval State of bit (1 or 0).
01467   */
01468 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
01469 {
01470   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
01471 }
01472
01473 /**
01474   * @brief  Get Channel 4 half transfer flag.
01475   * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
01476   * @param  DMAx DMAx Instance
01477   * @retval State of bit (1 or 0).
01478   */
01479 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
01480 {
01481   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
01482 }
01483
01484 /**
01485   * @brief  Get Channel 5 half transfer flag.
01486   * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
01487   * @param  DMAx DMAx Instance
01488   * @retval State of bit (1 or 0).
01489   */
01490 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
01491 {
01492   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
01493 }
01494
01495 /**
01496   * @brief  Get Channel 6 half transfer flag.
01497   * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
01498   * @param  DMAx DMAx Instance
01499   * @retval State of bit (1 or 0).
01500   */
01501 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
01502 {
01503   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
01504 }
01505
01506 /**
01507   * @brief  Get Channel 7 half transfer flag.
01508   * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
01509   * @param  DMAx DMAx Instance
01510   * @retval State of bit (1 or 0).
01511   */
01512 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
01513 {
01514   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
01515 }
01516
01517 /**
01518   * @brief  Get Channel 1 transfer error flag.
01519   * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
01520   * @param  DMAx DMAx Instance
01521   * @retval State of bit (1 or 0).
01522   */
01523 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
01524 {
01525   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
01526 }
01527
01528 /**
01529   * @brief  Get Channel 2 transfer error flag.
01530   * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
01531   * @param  DMAx DMAx Instance
01532   * @retval State of bit (1 or 0).
01533   */
01534 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
01535 {
01536   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
01537 }
01538
01539 /**
01540   * @brief  Get Channel 3 transfer error flag.
01541   * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
01542   * @param  DMAx DMAx Instance
01543   * @retval State of bit (1 or 0).
01544   */
01545 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
01546 {
01547   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
01548 }
01549
01550 /**
01551   * @brief  Get Channel 4 transfer error flag.
01552   * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
01553   * @param  DMAx DMAx Instance
01554   * @retval State of bit (1 or 0).
01555   */
01556 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
01557 {
01558   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
01559 }
01560
01561 /**
01562   * @brief  Get Channel 5 transfer error flag.
01563   * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
01564   * @param  DMAx DMAx Instance
01565   * @retval State of bit (1 or 0).
01566   */
01567 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
01568 {
01569   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
01570 }
01571
01572 /**
01573   * @brief  Get Channel 6 transfer error flag.
01574   * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
01575   * @param  DMAx DMAx Instance
01576   * @retval State of bit (1 or 0).
01577   */
01578 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
01579 {
01580   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
01581 }
01582
01583 /**
01584   * @brief  Get Channel 7 transfer error flag.
01585   * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
01586   * @param  DMAx DMAx Instance
01587   * @retval State of bit (1 or 0).
01588   */
01589 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
01590 {
01591   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
01592 }
01593
01594 /**
01595   * @brief  Clear Channel 1 global interrupt flag.
01596   * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
01597   * @param  DMAx DMAx Instance
01598   * @retval None
01599   */
01600 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
01601 {
01602   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
01603 }
01604
01605 /**
01606   * @brief  Clear Channel 2 global interrupt flag.
01607   * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
01608   * @param  DMAx DMAx Instance
01609   * @retval None
01610   */
01611 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
01612 {
01613   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
01614 }
01615
01616 /**
01617   * @brief  Clear Channel 3 global interrupt flag.
01618   * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
01619   * @param  DMAx DMAx Instance
01620   * @retval None
01621   */
01622 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
01623 {
01624   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
01625 }
01626
01627 /**
01628   * @brief  Clear Channel 4 global interrupt flag.
01629   * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
01630   * @param  DMAx DMAx Instance
01631   * @retval None
01632   */
01633 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
01634 {
01635   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
01636 }
01637
01638 /**
01639   * @brief  Clear Channel 5 global interrupt flag.
01640   * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
01641   * @param  DMAx DMAx Instance
01642   * @retval None
01643   */
01644 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
01645 {
01646   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
01647 }
01648
01649 /**
01650   * @brief  Clear Channel 6 global interrupt flag.
01651   * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
01652   * @param  DMAx DMAx Instance
01653   * @retval None
01654   */
01655 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
01656 {
01657   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
01658 }
01659
01660 /**
01661   * @brief  Clear Channel 7 global interrupt flag.
01662   * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
01663   * @param  DMAx DMAx Instance
01664   * @retval None
01665   */
01666 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
01667 {
01668   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
01669 }
01670
01671 /**
01672   * @brief  Clear Channel 1  transfer complete flag.
01673   * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
01674   * @param  DMAx DMAx Instance
01675   * @retval None
01676   */
01677 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
01678 {
01679   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
01680 }
01681
01682 /**
01683   * @brief  Clear Channel 2  transfer complete flag.
01684   * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
01685   * @param  DMAx DMAx Instance
01686   * @retval None
01687   */
01688 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
01689 {
01690   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
01691 }
01692
01693 /**
01694   * @brief  Clear Channel 3  transfer complete flag.
01695   * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
01696   * @param  DMAx DMAx Instance
01697   * @retval None
01698   */
01699 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
01700 {
01701   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
01702 }
01703
01704 /**
01705   * @brief  Clear Channel 4  transfer complete flag.
01706   * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
01707   * @param  DMAx DMAx Instance
01708   * @retval None
01709   */
01710 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
01711 {
01712   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
01713 }
01714
01715 /**
01716   * @brief  Clear Channel 5  transfer complete flag.
01717   * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
01718   * @param  DMAx DMAx Instance
01719   * @retval None
01720   */
01721 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
01722 {
01723   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
01724 }
01725
01726 /**
01727   * @brief  Clear Channel 6  transfer complete flag.
01728   * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
01729   * @param  DMAx DMAx Instance
01730   * @retval None
01731   */
01732 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
01733 {
01734   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
01735 }
01736
01737 /**
01738   * @brief  Clear Channel 7  transfer complete flag.
01739   * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
01740   * @param  DMAx DMAx Instance
01741   * @retval None
01742   */
01743 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
01744 {
01745   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
01746 }
01747
01748 /**
01749   * @brief  Clear Channel 1  half transfer flag.
01750   * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
01751   * @param  DMAx DMAx Instance
01752   * @retval None
01753   */
01754 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
01755 {
01756   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
01757 }
01758
01759 /**
01760   * @brief  Clear Channel 2  half transfer flag.
01761   * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
01762   * @param  DMAx DMAx Instance
01763   * @retval None
01764   */
01765 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
01766 {
01767   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
01768 }
01769
01770 /**
01771   * @brief  Clear Channel 3  half transfer flag.
01772   * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
01773   * @param  DMAx DMAx Instance
01774   * @retval None
01775   */
01776 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
01777 {
01778   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
01779 }
01780
01781 /**
01782   * @brief  Clear Channel 4  half transfer flag.
01783   * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
01784   * @param  DMAx DMAx Instance
01785   * @retval None
01786   */
01787 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
01788 {
01789   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
01790 }
01791
01792 /**
01793   * @brief  Clear Channel 5  half transfer flag.
01794   * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
01795   * @param  DMAx DMAx Instance
01796   * @retval None
01797   */
01798 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
01799 {
01800   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
01801 }
01802
01803 /**
01804   * @brief  Clear Channel 6  half transfer flag.
01805   * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
01806   * @param  DMAx DMAx Instance
01807   * @retval None
01808   */
01809 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
01810 {
01811   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
01812 }
01813
01814 /**
01815   * @brief  Clear Channel 7  half transfer flag.
01816   * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
01817   * @param  DMAx DMAx Instance
01818   * @retval None
01819   */
01820 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
01821 {
01822   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
01823 }
01824
01825 /**
01826   * @brief  Clear Channel 1 transfer error flag.
01827   * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
01828   * @param  DMAx DMAx Instance
01829   * @retval None
01830   */
01831 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
01832 {
01833   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
01834 }
01835
01836 /**
01837   * @brief  Clear Channel 2 transfer error flag.
01838   * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
01839   * @param  DMAx DMAx Instance
01840   * @retval None
01841   */
01842 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
01843 {
01844   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
01845 }
01846
01847 /**
01848   * @brief  Clear Channel 3 transfer error flag.
01849   * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
01850   * @param  DMAx DMAx Instance
01851   * @retval None
01852   */
01853 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
01854 {
01855   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
01856 }
01857
01858 /**
01859   * @brief  Clear Channel 4 transfer error flag.
01860   * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
01861   * @param  DMAx DMAx Instance
01862   * @retval None
01863   */
01864 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
01865 {
01866   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
01867 }
01868
01869 /**
01870   * @brief  Clear Channel 5 transfer error flag.
01871   * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
01872   * @param  DMAx DMAx Instance
01873   * @retval None
01874   */
01875 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
01876 {
01877   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
01878 }
01879
01880 /**
01881   * @brief  Clear Channel 6 transfer error flag.
01882   * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
01883   * @param  DMAx DMAx Instance
01884   * @retval None
01885   */
01886 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
01887 {
01888   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
01889 }
01890
01891 /**
01892   * @brief  Clear Channel 7 transfer error flag.
01893   * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
01894   * @param  DMAx DMAx Instance
01895   * @retval None
01896   */
01897 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
01898 {
01899   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
01900 }
01901
01902 /**
01903   * @}
01904   */
01905
01906 /** @defgroup DMA_LL_EF_IT_Management IT_Management
01907   * @{
01908   */
01909 /**
01910   * @brief  Enable Transfer complete interrupt.
01911   * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
01912   * @param  DMAx DMAx Instance
01913   * @param  Channel This parameter can be one of the following values:
01914   *         @arg @ref LL_DMA_CHANNEL_1
01915   *         @arg @ref LL_DMA_CHANNEL_2
01916   *         @arg @ref LL_DMA_CHANNEL_3
01917   *         @arg @ref LL_DMA_CHANNEL_4
01918   *         @arg @ref LL_DMA_CHANNEL_5
01919   *         @arg @ref LL_DMA_CHANNEL_6
01920   *         @arg @ref LL_DMA_CHANNEL_7
01921   * @retval None
01922   */
01923 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
01924 {
01925   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
01926 }
01927
01928 /**
01929   * @brief  Enable Half transfer interrupt.
01930   * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
01931   * @param  DMAx DMAx Instance
01932   * @param  Channel This parameter can be one of the following values:
01933   *         @arg @ref LL_DMA_CHANNEL_1
01934   *         @arg @ref LL_DMA_CHANNEL_2
01935   *         @arg @ref LL_DMA_CHANNEL_3
01936   *         @arg @ref LL_DMA_CHANNEL_4
01937   *         @arg @ref LL_DMA_CHANNEL_5
01938   *         @arg @ref LL_DMA_CHANNEL_6
01939   *         @arg @ref LL_DMA_CHANNEL_7
01940   * @retval None
01941   */
01942 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
01943 {
01944   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
01945 }
01946
01947 /**
01948   * @brief  Enable Transfer error interrupt.
01949   * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
01950   * @param  DMAx DMAx Instance
01951   * @param  Channel This parameter can be one of the following values:
01952   *         @arg @ref LL_DMA_CHANNEL_1
01953   *         @arg @ref LL_DMA_CHANNEL_2
01954   *         @arg @ref LL_DMA_CHANNEL_3
01955   *         @arg @ref LL_DMA_CHANNEL_4
01956   *         @arg @ref LL_DMA_CHANNEL_5
01957   *         @arg @ref LL_DMA_CHANNEL_6
01958   *         @arg @ref LL_DMA_CHANNEL_7
01959   * @retval None
01960   */
01961 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
01962 {
01963   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
01964 }
01965
01966 /**
01967   * @brief  Disable Transfer complete interrupt.
01968   * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
01969   * @param  DMAx DMAx Instance
01970   * @param  Channel This parameter can be one of the following values:
01971   *         @arg @ref LL_DMA_CHANNEL_1
01972   *         @arg @ref LL_DMA_CHANNEL_2
01973   *         @arg @ref LL_DMA_CHANNEL_3
01974   *         @arg @ref LL_DMA_CHANNEL_4
01975   *         @arg @ref LL_DMA_CHANNEL_5
01976   *         @arg @ref LL_DMA_CHANNEL_6
01977   *         @arg @ref LL_DMA_CHANNEL_7
01978   * @retval None
01979   */
01980 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
01981 {
01982   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
01983 }
01984
01985 /**
01986   * @brief  Disable Half transfer interrupt.
01987   * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
01988   * @param  DMAx DMAx Instance
01989   * @param  Channel This parameter can be one of the following values:
01990   *         @arg @ref LL_DMA_CHANNEL_1
01991   *         @arg @ref LL_DMA_CHANNEL_2
01992   *         @arg @ref LL_DMA_CHANNEL_3
01993   *         @arg @ref LL_DMA_CHANNEL_4
01994   *         @arg @ref LL_DMA_CHANNEL_5
01995   *         @arg @ref LL_DMA_CHANNEL_6
01996   *         @arg @ref LL_DMA_CHANNEL_7
01997   * @retval None
01998   */
01999 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
02000 {
02001   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
02002 }
02003
02004 /**
02005   * @brief  Disable Transfer error interrupt.
02006   * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
02007   * @param  DMAx DMAx Instance
02008   * @param  Channel This parameter can be one of the following values:
02009   *         @arg @ref LL_DMA_CHANNEL_1
02010   *         @arg @ref LL_DMA_CHANNEL_2
02011   *         @arg @ref LL_DMA_CHANNEL_3
02012   *         @arg @ref LL_DMA_CHANNEL_4
02013   *         @arg @ref LL_DMA_CHANNEL_5
02014   *         @arg @ref LL_DMA_CHANNEL_6
02015   *         @arg @ref LL_DMA_CHANNEL_7
02016   * @retval None
02017   */
02018 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
02019 {
02020   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
02021 }
02022
02023 /**
02024   * @brief  Check if Transfer complete Interrupt is enabled.
02025   * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
02026   * @param  DMAx DMAx Instance
02027   * @param  Channel This parameter can be one of the following values:
02028   *         @arg @ref LL_DMA_CHANNEL_1
02029   *         @arg @ref LL_DMA_CHANNEL_2
02030   *         @arg @ref LL_DMA_CHANNEL_3
02031   *         @arg @ref LL_DMA_CHANNEL_4
02032   *         @arg @ref LL_DMA_CHANNEL_5
02033   *         @arg @ref LL_DMA_CHANNEL_6
02034   *         @arg @ref LL_DMA_CHANNEL_7
02035   * @retval State of bit (1 or 0).
02036   */
02037 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
02038 {
02039   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
02040                    DMA_CCR_TCIE) == (DMA_CCR_TCIE));
02041 }
02042
02043 /**
02044   * @brief  Check if Half transfer Interrupt is enabled.
02045   * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
02046   * @param  DMAx DMAx Instance
02047   * @param  Channel This parameter can be one of the following values:
02048   *         @arg @ref LL_DMA_CHANNEL_1
02049   *         @arg @ref LL_DMA_CHANNEL_2
02050   *         @arg @ref LL_DMA_CHANNEL_3
02051   *         @arg @ref LL_DMA_CHANNEL_4
02052   *         @arg @ref LL_DMA_CHANNEL_5
02053   *         @arg @ref LL_DMA_CHANNEL_6
02054   *         @arg @ref LL_DMA_CHANNEL_7
02055   * @retval State of bit (1 or 0).
02056   */
02057 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
02058 {
02059   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
02060                    DMA_CCR_HTIE) == (DMA_CCR_HTIE));
02061 }
02062
02063 /**
02064   * @brief  Check if Transfer error Interrupt is enabled.
02065   * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
02066   * @param  DMAx DMAx Instance
02067   * @param  Channel This parameter can be one of the following values:
02068   *         @arg @ref LL_DMA_CHANNEL_1
02069   *         @arg @ref LL_DMA_CHANNEL_2
02070   *         @arg @ref LL_DMA_CHANNEL_3
02071   *         @arg @ref LL_DMA_CHANNEL_4
02072   *         @arg @ref LL_DMA_CHANNEL_5
02073   *         @arg @ref LL_DMA_CHANNEL_6
02074   *         @arg @ref LL_DMA_CHANNEL_7
02075   * @retval State of bit (1 or 0).
02076   */
02077 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
02078 {
02079   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
02080                    DMA_CCR_TEIE) == (DMA_CCR_TEIE));
02081 }
02082
02083 /**
02084   * @}
02085   */
02086
02087 #if defined(USE_FULL_LL_DRIVER)
02088 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
02089   * @{
02090   */
02091
02092 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
02093 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
02094 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
02095
02096 /**
02097   * @}
02098   */
02099 #endif /* USE_FULL_LL_DRIVER */
02100
02101 /**
02102   * @}
02103   */
02104
02105 /**
02106   * @}
02107   */
02108
02109 #endif /* DMA1 || DMA2 */
02110
02111 /**
02112   * @}
02113   */
02114
02115 #ifdef __cplusplus
02116 }
02117 #endif
02118
02119 #endif /* __STM32L4xx_LL_DMA_H */
02120
02121 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_exti.c Source File

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stm32l4xx_ll_exti.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_exti.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   EXTI LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_exti.h"
00041 #ifdef  USE_FULL_ASSERT
00042 #include "stm32_assert.h"
00043 #else
00044 #define assert_param(expr) ((void)0U)
00045 #endif
00046
00047 /** @addtogroup STM32L4xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (EXTI)
00052
00053 /** @defgroup EXTI_LL EXTI
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /* Private macros ------------------------------------------------------------*/
00061 /** @addtogroup EXTI_LL_Private_Macros
00062   * @{
00063   */
00064
00065 #define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
00066 #define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
00067
00068 #define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
00069                                                    || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
00070                                                    || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
00071
00072
00073 #define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
00074                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
00075                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
00076                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
00077
00078 /**
00079   * @}
00080   */
00081
00082 /* Private function prototypes -----------------------------------------------*/
00083
00084 /* Exported functions --------------------------------------------------------*/
00085 /** @addtogroup EXTI_LL_Exported_Functions
00086   * @{
00087   */
00088
00089 /** @addtogroup EXTI_LL_EF_Init
00090   * @{
00091   */
00092
00093 /**
00094   * @brief  De-initialize the EXTI registers to their default reset values.
00095   * @retval An ErrorStatus enumeration value:
00096   *          - SUCCESS: EXTI registers are de-initialized
00097   *          - ERROR: not applicable
00098   */
00099 uint32_t LL_EXTI_DeInit(void)
00100 {
00101   /* Interrupt mask register set to default reset values */
00102   LL_EXTI_WriteReg(IMR1,   0xFF820000U);
00103   /* Event mask register set to default reset values */
00104   LL_EXTI_WriteReg(EMR1,   0x00000000U);
00105   /* Rising Trigger selection register set to default reset values */
00106   LL_EXTI_WriteReg(RTSR1,  0x00000000U);
00107   /* Falling Trigger selection register set to default reset values */
00108   LL_EXTI_WriteReg(FTSR1,  0x00000000U);
00109   /* Software interrupt event register set to default reset values */
00110   LL_EXTI_WriteReg(SWIER1, 0x00000000U);
00111   /* Pending register set to default reset values */
00112   LL_EXTI_WriteReg(PR1,    0x007DFFFFU);
00113
00114   /* Interrupt mask register 2 set to default reset values */
00115   LL_EXTI_WriteReg(IMR2,        0x00000087U);
00116   /* Event mask register 2 set to default reset values */
00117   LL_EXTI_WriteReg(EMR2,        0x00000000U);
00118   /* Rising Trigger selection register 2 set to default reset values */
00119   LL_EXTI_WriteReg(RTSR2,       0x00000000U);
00120   /* Falling Trigger selection register 2 set to default reset values */
00121   LL_EXTI_WriteReg(FTSR2,       0x00000000U);
00122   /* Software interrupt event register 2 set to default reset values */
00123   LL_EXTI_WriteReg(SWIER2,      0x00000000U);
00124   /* Pending register 2 set to default reset values */
00125   LL_EXTI_WriteReg(PR2,         0x00000078U);
00126
00127   return SUCCESS;
00128 }
00129
00130 /**
00131   * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
00132   * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
00133   * @retval An ErrorStatus enumeration value:
00134   *          - SUCCESS: EXTI registers are initialized
00135   *          - ERROR: not applicable
00136   */
00137 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00138 {
00139   ErrorStatus status = SUCCESS;
00140   /* Check the parameters */
00141   assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
00142   assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
00143   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
00144   assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
00145
00146   /* ENABLE LineCommand */
00147   if (EXTI_InitStruct->LineCommand != DISABLE)
00148   {
00149     assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
00150
00151     /* Configure EXTI Lines in range from 0 to 31 */
00152     if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
00153     {
00154       switch (EXTI_InitStruct->Mode)
00155       {
00156         case LL_EXTI_MODE_IT:
00157           /* First Disable Event on provided Lines */
00158           LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00159           /* Then Enable IT on provided Lines */
00160           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00161           break;
00162         case LL_EXTI_MODE_EVENT:
00163           /* First Disable IT on provided Lines */
00164           LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00165           /* Then Enable Event on provided Lines */
00166           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00167           break;
00168         case LL_EXTI_MODE_IT_EVENT:
00169           /* Directly Enable IT & Event on provided Lines */
00170           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00171           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00172           break;
00173         default:
00174           status = ERROR;
00175           break;
00176       }
00177       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00178       {
00179         switch (EXTI_InitStruct->Trigger)
00180         {
00181           case LL_EXTI_TRIGGER_RISING:
00182             /* First Disable Falling Trigger on provided Lines */
00183             LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00184             /* Then Enable Rising Trigger on provided Lines */
00185             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00186             break;
00187           case LL_EXTI_TRIGGER_FALLING:
00188             /* First Disable Rising Trigger on provided Lines */
00189             LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00190             /* Then Enable Falling Trigger on provided Lines */
00191             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00192             break;
00193           case LL_EXTI_TRIGGER_RISING_FALLING:
00194             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00195             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00196             break;
00197           default:
00198             status = ERROR;
00199             break;
00200         }
00201       }
00202     }
00203     /* Configure EXTI Lines in range from 32 to 63 */
00204     if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
00205     {
00206       switch (EXTI_InitStruct->Mode)
00207       {
00208         case LL_EXTI_MODE_IT:
00209           /* First Disable Event on provided Lines */
00210           LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00211           /* Then Enable IT on provided Lines */
00212           LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00213           break;
00214         case LL_EXTI_MODE_EVENT:
00215           /* First Disable IT on provided Lines */
00216           LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00217           /* Then Enable Event on provided Lines */
00218           LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00219           break;
00220         case LL_EXTI_MODE_IT_EVENT:
00221           /* Directly Enable IT & Event on provided Lines */
00222           LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00223           LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00224           break;
00225         default:
00226           status = ERROR;
00227           break;
00228       }
00229       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00230       {
00231         switch (EXTI_InitStruct->Trigger)
00232         {
00233           case LL_EXTI_TRIGGER_RISING:
00234             /* First Disable Falling Trigger on provided Lines */
00235             LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00236             /* Then Enable IT on provided Lines */
00237             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00238             break;
00239           case LL_EXTI_TRIGGER_FALLING:
00240             /* First Disable Rising Trigger on provided Lines */
00241             LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00242             /* Then Enable Falling Trigger on provided Lines */
00243             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00244             break;
00245           case LL_EXTI_TRIGGER_RISING_FALLING:
00246             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00247             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00248             break;
00249           default:
00250             status = ERROR;
00251             break;
00252         }
00253       }
00254     }
00255   }
00256   /* DISABLE LineCommand */
00257   else
00258   {
00259     /* De-configure EXTI Lines in range from 0 to 31 */
00260     LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00261     LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00262     /* De-configure EXTI Lines in range from 32 to 63 */
00263     LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00264     LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00265   }
00266   return status;
00267 }
00268
00269 /**
00270   * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
00271   * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
00272   * @retval None
00273   */
00274 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00275 {
00276   EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
00277   EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
00278   EXTI_InitStruct->LineCommand    = DISABLE;
00279   EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
00280   EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
00281 }
00282
00283 /**
00284   * @}
00285   */
00286
00287 /**
00288   * @}
00289   */
00290
00291 /**
00292   * @}
00293   */
00294
00295 #endif /* defined (EXTI) */
00296
00297 /**
00298   * @}
00299   */
00300
00301 #endif /* USE_FULL_LL_DRIVER */
00302
00303 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_exti.h Source File

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stm32l4xx_ll_exti.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_exti.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of EXTI LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_EXTI_H
00040 #define __STM32L4xx_LL_EXTI_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (EXTI)
00054
00055 /** @defgroup EXTI_LL EXTI
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private Macros ------------------------------------------------------------*/
00063 #if defined(USE_FULL_LL_DRIVER)
00064 /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
00065   * @{
00066   */
00067 /**
00068   * @}
00069   */
00070 #endif /*USE_FULL_LL_DRIVER*/
00071 /* Exported types ------------------------------------------------------------*/
00072 #if defined(USE_FULL_LL_DRIVER)
00073 /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
00074   * @{
00075   */
00076 typedef struct
00077 {
00078
00079   uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
00080                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00081
00082   uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
00083                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00084
00085   FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
00086                                      This parameter can be set either to ENABLE or DISABLE */
00087
00088   uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
00089                                      This parameter can be a value of @ref EXTI_LL_EC_MODE. */
00090
00091   uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
00092                                      This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
00093 } LL_EXTI_InitTypeDef;
00094
00095 /**
00096   * @}
00097   */
00098 #endif /*USE_FULL_LL_DRIVER*/
00099
00100 /* Exported constants --------------------------------------------------------*/
00101 /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
00102   * @{
00103   */
00104
00105 /** @defgroup EXTI_LL_EC_LINE LINE
00106   * @{
00107   */
00108 #define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
00109 #define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
00110 #define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
00111 #define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
00112 #define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
00113 #define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
00114 #define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
00115 #define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
00116 #define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
00117 #define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
00118 #define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
00119 #define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
00120 #define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
00121 #define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
00122 #define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
00123 #define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
00124 #if defined(EXTI_IMR1_IM16)
00125 #define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
00126 #endif
00127 #define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
00128 #define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
00129 #define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
00130 #if defined(EXTI_IMR1_IM20)
00131 #define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
00132 #endif
00133 #if defined(EXTI_IMR1_IM21)
00134 #define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
00135 #endif
00136 #if defined(EXTI_IMR1_IM22)
00137 #define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
00138 #endif
00139 #define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
00140 #if defined(EXTI_IMR1_IM24)
00141 #define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
00142 #endif
00143 #if defined(EXTI_IMR1_IM25)
00144 #define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
00145 #endif
00146 #if defined(EXTI_IMR1_IM26)
00147 #define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
00148 #endif
00149 #if defined(EXTI_IMR1_IM27)
00150 #define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
00151 #endif
00152 #if defined(EXTI_IMR1_IM28)
00153 #define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
00154 #endif
00155 #if defined(EXTI_IMR1_IM29)
00156 #define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
00157 #endif
00158 #if defined(EXTI_IMR1_IM30)
00159 #define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
00160 #endif
00161 #if defined(EXTI_IMR1_IM31)
00162 #define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
00163 #endif
00164 #define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
00165
00166 #define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
00167 #define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
00168 #define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
00169 #define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
00170 #define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
00171 #define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
00172 #define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
00173 #define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
00174 #define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
00175
00176 #define LL_EXTI_LINE_ALL               ((uint32_t)0xFFFFFFFFU)  /*!< All Extended line */
00177
00178 #if defined(USE_FULL_LL_DRIVER)
00179 #define LL_EXTI_LINE_NONE              ((uint32_t)0x00000000U)  /*!< None Extended line */
00180 #endif /*USE_FULL_LL_DRIVER*/
00181
00182 /**
00183   * @}
00184   */
00185 #if defined(USE_FULL_LL_DRIVER)
00186
00187 /** @defgroup EXTI_LL_EC_MODE Mode
00188   * @{
00189   */
00190 #define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
00191 #define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
00192 #define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
00198   * @{
00199   */
00200 #define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
00201 #define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
00202 #define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
00203 #define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
00204
00205 /**
00206   * @}
00207   */
00208
00209
00210 #endif /*USE_FULL_LL_DRIVER*/
00211
00212
00213 /**
00214   * @}
00215   */
00216
00217 /* Exported macro ------------------------------------------------------------*/
00218 /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
00219   * @{
00220   */
00221
00222 /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
00223   * @{
00224   */
00225
00226 /**
00227   * @brief  Write a value in EXTI register
00228   * @param  __REG__ Register to be written
00229   * @param  __VALUE__ Value to be written in the register
00230   * @retval None
00231   */
00232 #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
00233
00234 /**
00235   * @brief  Read a value in EXTI register
00236   * @param  __REG__ Register to be read
00237   * @retval Register value
00238   */
00239 #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
00240 /**
00241   * @}
00242   */
00243
00244
00245 /**
00246   * @}
00247   */
00248
00249
00250
00251 /* Exported functions --------------------------------------------------------*/
00252 /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
00253  * @{
00254  */
00255 /** @defgroup EXTI_LL_EF_IT_Management IT_Management
00256   * @{
00257   */
00258
00259 /**
00260   * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
00261   * @note The reset value for the direct or internal lines (see RM)
00262   *       is set to 1 in order to enable the interrupt by default.
00263   *       Bits are set automatically at Power on.
00264   * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
00265   * @param  ExtiLine This parameter can be one of the following values:
00266   *         @arg @ref LL_EXTI_LINE_0
00267   *         @arg @ref LL_EXTI_LINE_1
00268   *         @arg @ref LL_EXTI_LINE_2
00269   *         @arg @ref LL_EXTI_LINE_3
00270   *         @arg @ref LL_EXTI_LINE_4
00271   *         @arg @ref LL_EXTI_LINE_5
00272   *         @arg @ref LL_EXTI_LINE_6
00273   *         @arg @ref LL_EXTI_LINE_7
00274   *         @arg @ref LL_EXTI_LINE_8
00275   *         @arg @ref LL_EXTI_LINE_9
00276   *         @arg @ref LL_EXTI_LINE_10
00277   *         @arg @ref LL_EXTI_LINE_11
00278   *         @arg @ref LL_EXTI_LINE_12
00279   *         @arg @ref LL_EXTI_LINE_13
00280   *         @arg @ref LL_EXTI_LINE_14
00281   *         @arg @ref LL_EXTI_LINE_15
00282   *         @arg @ref LL_EXTI_LINE_16
00283   *         @arg @ref LL_EXTI_LINE_17
00284   *         @arg @ref LL_EXTI_LINE_18
00285   *         @arg @ref LL_EXTI_LINE_19
00286   *         @arg @ref LL_EXTI_LINE_20
00287   *         @arg @ref LL_EXTI_LINE_21
00288   *         @arg @ref LL_EXTI_LINE_22
00289   *         @arg @ref LL_EXTI_LINE_23
00290   *         @arg @ref LL_EXTI_LINE_24
00291   *         @arg @ref LL_EXTI_LINE_25
00292   *         @arg @ref LL_EXTI_LINE_26
00293   *         @arg @ref LL_EXTI_LINE_27
00294   *         @arg @ref LL_EXTI_LINE_28
00295   *         @arg @ref LL_EXTI_LINE_29
00296   *         @arg @ref LL_EXTI_LINE_30
00297   *         @arg @ref LL_EXTI_LINE_31
00298   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00299   * @note   Please check each device line mapping for EXTI Line availability
00300   * @retval None
00301   */
00302 __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
00303 {
00304   SET_BIT(EXTI->IMR1, ExtiLine);
00305 }
00306 /**
00307   * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
00308   * @note The reset value for the direct lines (lines from 32 to 34, line
00309   *       39) is set to 1 in order to enable the interrupt by default.
00310   *       Bits are set automatically at Power on.
00311   * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
00312   * @param  ExtiLine This parameter can be one of the following values:
00313   *         @arg @ref LL_EXTI_LINE_32
00314   *         @arg @ref LL_EXTI_LINE_33
00315   *         @arg @ref LL_EXTI_LINE_34
00316   *         @arg @ref LL_EXTI_LINE_35
00317   *         @arg @ref LL_EXTI_LINE_36
00318   *         @arg @ref LL_EXTI_LINE_37
00319   *         @arg @ref LL_EXTI_LINE_38
00320   *         @arg @ref LL_EXTI_LINE_39
00321   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00322   * @retval None
00323   */
00324 __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
00325 {
00326   SET_BIT(EXTI->IMR2, ExtiLine);
00327 }
00328
00329 /**
00330   * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
00331   * @note The reset value for the direct or internal lines (see RM)
00332   *       is set to 1 in order to enable the interrupt by default.
00333   *       Bits are set automatically at Power on.
00334   * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
00335   * @param  ExtiLine This parameter can be one of the following values:
00336   *         @arg @ref LL_EXTI_LINE_0
00337   *         @arg @ref LL_EXTI_LINE_1
00338   *         @arg @ref LL_EXTI_LINE_2
00339   *         @arg @ref LL_EXTI_LINE_3
00340   *         @arg @ref LL_EXTI_LINE_4
00341   *         @arg @ref LL_EXTI_LINE_5
00342   *         @arg @ref LL_EXTI_LINE_6
00343   *         @arg @ref LL_EXTI_LINE_7
00344   *         @arg @ref LL_EXTI_LINE_8
00345   *         @arg @ref LL_EXTI_LINE_9
00346   *         @arg @ref LL_EXTI_LINE_10
00347   *         @arg @ref LL_EXTI_LINE_11
00348   *         @arg @ref LL_EXTI_LINE_12
00349   *         @arg @ref LL_EXTI_LINE_13
00350   *         @arg @ref LL_EXTI_LINE_14
00351   *         @arg @ref LL_EXTI_LINE_15
00352   *         @arg @ref LL_EXTI_LINE_16
00353   *         @arg @ref LL_EXTI_LINE_17
00354   *         @arg @ref LL_EXTI_LINE_18
00355   *         @arg @ref LL_EXTI_LINE_19
00356   *         @arg @ref LL_EXTI_LINE_20
00357   *         @arg @ref LL_EXTI_LINE_21
00358   *         @arg @ref LL_EXTI_LINE_22
00359   *         @arg @ref LL_EXTI_LINE_23
00360   *         @arg @ref LL_EXTI_LINE_24
00361   *         @arg @ref LL_EXTI_LINE_25
00362   *         @arg @ref LL_EXTI_LINE_26
00363   *         @arg @ref LL_EXTI_LINE_27
00364   *         @arg @ref LL_EXTI_LINE_28
00365   *         @arg @ref LL_EXTI_LINE_29
00366   *         @arg @ref LL_EXTI_LINE_30
00367   *         @arg @ref LL_EXTI_LINE_31
00368   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00369   * @note   Please check each device line mapping for EXTI Line availability
00370   * @retval None
00371   */
00372 __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
00373 {
00374   CLEAR_BIT(EXTI->IMR1, ExtiLine);
00375 }
00376
00377 /**
00378   * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
00379   * @note The reset value for the direct lines (lines from 32 to 34, line
00380   *       39) is set to 1 in order to enable the interrupt by default.
00381   *       Bits are set automatically at Power on.
00382   * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
00383   * @param  ExtiLine This parameter can be one of the following values:
00384   *         @arg @ref LL_EXTI_LINE_32
00385   *         @arg @ref LL_EXTI_LINE_33
00386   *         @arg @ref LL_EXTI_LINE_34
00387   *         @arg @ref LL_EXTI_LINE_35
00388   *         @arg @ref LL_EXTI_LINE_36
00389   *         @arg @ref LL_EXTI_LINE_37
00390   *         @arg @ref LL_EXTI_LINE_38
00391   *         @arg @ref LL_EXTI_LINE_39
00392   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00393   * @retval None
00394   */
00395 __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
00396 {
00397   CLEAR_BIT(EXTI->IMR2, ExtiLine);
00398 }
00399
00400 /**
00401   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
00402   * @note The reset value for the direct or internal lines (see RM)
00403   *       is set to 1 in order to enable the interrupt by default.
00404   *       Bits are set automatically at Power on.
00405   * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
00406   * @param  ExtiLine This parameter can be one of the following values:
00407   *         @arg @ref LL_EXTI_LINE_0
00408   *         @arg @ref LL_EXTI_LINE_1
00409   *         @arg @ref LL_EXTI_LINE_2
00410   *         @arg @ref LL_EXTI_LINE_3
00411   *         @arg @ref LL_EXTI_LINE_4
00412   *         @arg @ref LL_EXTI_LINE_5
00413   *         @arg @ref LL_EXTI_LINE_6
00414   *         @arg @ref LL_EXTI_LINE_7
00415   *         @arg @ref LL_EXTI_LINE_8
00416   *         @arg @ref LL_EXTI_LINE_9
00417   *         @arg @ref LL_EXTI_LINE_10
00418   *         @arg @ref LL_EXTI_LINE_11
00419   *         @arg @ref LL_EXTI_LINE_12
00420   *         @arg @ref LL_EXTI_LINE_13
00421   *         @arg @ref LL_EXTI_LINE_14
00422   *         @arg @ref LL_EXTI_LINE_15
00423   *         @arg @ref LL_EXTI_LINE_16
00424   *         @arg @ref LL_EXTI_LINE_17
00425   *         @arg @ref LL_EXTI_LINE_18
00426   *         @arg @ref LL_EXTI_LINE_19
00427   *         @arg @ref LL_EXTI_LINE_20
00428   *         @arg @ref LL_EXTI_LINE_21
00429   *         @arg @ref LL_EXTI_LINE_22
00430   *         @arg @ref LL_EXTI_LINE_23
00431   *         @arg @ref LL_EXTI_LINE_24
00432   *         @arg @ref LL_EXTI_LINE_25
00433   *         @arg @ref LL_EXTI_LINE_26
00434   *         @arg @ref LL_EXTI_LINE_27
00435   *         @arg @ref LL_EXTI_LINE_28
00436   *         @arg @ref LL_EXTI_LINE_29
00437   *         @arg @ref LL_EXTI_LINE_30
00438   *         @arg @ref LL_EXTI_LINE_31
00439   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00440   * @note   Please check each device line mapping for EXTI Line availability
00441   * @retval State of bit (1 or 0).
00442   */
00443 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
00444 {
00445   return (READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine));
00446 }
00447
00448 /**
00449   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
00450   * @note The reset value for the direct lines (lines from 32 to 34, line
00451   *       39) is set to 1 in order to enable the interrupt by default.
00452   *       Bits are set automatically at Power on.
00453   * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
00454   * @param  ExtiLine This parameter can be one of the following values:
00455   *         @arg @ref LL_EXTI_LINE_32
00456   *         @arg @ref LL_EXTI_LINE_33
00457   *         @arg @ref LL_EXTI_LINE_34
00458   *         @arg @ref LL_EXTI_LINE_35
00459   *         @arg @ref LL_EXTI_LINE_36
00460   *         @arg @ref LL_EXTI_LINE_37
00461   *         @arg @ref LL_EXTI_LINE_38
00462   *         @arg @ref LL_EXTI_LINE_39
00463   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00464   * @retval State of bit (1 or 0).
00465   */
00466 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
00467 {
00468   return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine));
00469 }
00470
00471 /**
00472   * @}
00473   */
00474
00475 /** @defgroup EXTI_LL_EF_Event_Management Event_Management
00476   * @{
00477   */
00478
00479 /**
00480   * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
00481   * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
00482   * @param  ExtiLine This parameter can be one of the following values:
00483   *         @arg @ref LL_EXTI_LINE_0
00484   *         @arg @ref LL_EXTI_LINE_1
00485   *         @arg @ref LL_EXTI_LINE_2
00486   *         @arg @ref LL_EXTI_LINE_3
00487   *         @arg @ref LL_EXTI_LINE_4
00488   *         @arg @ref LL_EXTI_LINE_5
00489   *         @arg @ref LL_EXTI_LINE_6
00490   *         @arg @ref LL_EXTI_LINE_7
00491   *         @arg @ref LL_EXTI_LINE_8
00492   *         @arg @ref LL_EXTI_LINE_9
00493   *         @arg @ref LL_EXTI_LINE_10
00494   *         @arg @ref LL_EXTI_LINE_11
00495   *         @arg @ref LL_EXTI_LINE_12
00496   *         @arg @ref LL_EXTI_LINE_13
00497   *         @arg @ref LL_EXTI_LINE_14
00498   *         @arg @ref LL_EXTI_LINE_15
00499   *         @arg @ref LL_EXTI_LINE_16
00500   *         @arg @ref LL_EXTI_LINE_17
00501   *         @arg @ref LL_EXTI_LINE_18
00502   *         @arg @ref LL_EXTI_LINE_19
00503   *         @arg @ref LL_EXTI_LINE_20
00504   *         @arg @ref LL_EXTI_LINE_21
00505   *         @arg @ref LL_EXTI_LINE_22
00506   *         @arg @ref LL_EXTI_LINE_23
00507   *         @arg @ref LL_EXTI_LINE_24
00508   *         @arg @ref LL_EXTI_LINE_25
00509   *         @arg @ref LL_EXTI_LINE_26
00510   *         @arg @ref LL_EXTI_LINE_27
00511   *         @arg @ref LL_EXTI_LINE_28
00512   *         @arg @ref LL_EXTI_LINE_29
00513   *         @arg @ref LL_EXTI_LINE_30
00514   *         @arg @ref LL_EXTI_LINE_31
00515   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00516   * @note   Please check each device line mapping for EXTI Line availability
00517   * @retval None
00518   */
00519 __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
00520 {
00521   SET_BIT(EXTI->EMR1, ExtiLine);
00522
00523 }
00524
00525 /**
00526   * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
00527   * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
00528   * @param  ExtiLine This parameter can be a combination of the following values:
00529   *         @arg @ref LL_EXTI_LINE_32
00530   *         @arg @ref LL_EXTI_LINE_33
00531   *         @arg @ref LL_EXTI_LINE_34
00532   *         @arg @ref LL_EXTI_LINE_35
00533   *         @arg @ref LL_EXTI_LINE_36
00534   *         @arg @ref LL_EXTI_LINE_37
00535   *         @arg @ref LL_EXTI_LINE_38
00536   *         @arg @ref LL_EXTI_LINE_39
00537   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00538   * @retval None
00539   */
00540 __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
00541 {
00542   SET_BIT(EXTI->EMR2, ExtiLine);
00543 }
00544
00545 /**
00546   * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
00547   * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
00548   * @param  ExtiLine This parameter can be one of the following values:
00549   *         @arg @ref LL_EXTI_LINE_0
00550   *         @arg @ref LL_EXTI_LINE_1
00551   *         @arg @ref LL_EXTI_LINE_2
00552   *         @arg @ref LL_EXTI_LINE_3
00553   *         @arg @ref LL_EXTI_LINE_4
00554   *         @arg @ref LL_EXTI_LINE_5
00555   *         @arg @ref LL_EXTI_LINE_6
00556   *         @arg @ref LL_EXTI_LINE_7
00557   *         @arg @ref LL_EXTI_LINE_8
00558   *         @arg @ref LL_EXTI_LINE_9
00559   *         @arg @ref LL_EXTI_LINE_10
00560   *         @arg @ref LL_EXTI_LINE_11
00561   *         @arg @ref LL_EXTI_LINE_12
00562   *         @arg @ref LL_EXTI_LINE_13
00563   *         @arg @ref LL_EXTI_LINE_14
00564   *         @arg @ref LL_EXTI_LINE_15
00565   *         @arg @ref LL_EXTI_LINE_16
00566   *         @arg @ref LL_EXTI_LINE_17
00567   *         @arg @ref LL_EXTI_LINE_18
00568   *         @arg @ref LL_EXTI_LINE_19
00569   *         @arg @ref LL_EXTI_LINE_20
00570   *         @arg @ref LL_EXTI_LINE_21
00571   *         @arg @ref LL_EXTI_LINE_22
00572   *         @arg @ref LL_EXTI_LINE_23
00573   *         @arg @ref LL_EXTI_LINE_24
00574   *         @arg @ref LL_EXTI_LINE_25
00575   *         @arg @ref LL_EXTI_LINE_26
00576   *         @arg @ref LL_EXTI_LINE_27
00577   *         @arg @ref LL_EXTI_LINE_28
00578   *         @arg @ref LL_EXTI_LINE_29
00579   *         @arg @ref LL_EXTI_LINE_30
00580   *         @arg @ref LL_EXTI_LINE_31
00581   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00582   * @note   Please check each device line mapping for EXTI Line availability
00583   * @retval None
00584   */
00585 __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
00586 {
00587   CLEAR_BIT(EXTI->EMR1, ExtiLine);
00588 }
00589
00590 /**
00591   * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
00592   * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
00593   * @param  ExtiLine This parameter can be a combination of the following values:
00594   *         @arg @ref LL_EXTI_LINE_32
00595   *         @arg @ref LL_EXTI_LINE_33
00596   *         @arg @ref LL_EXTI_LINE_34
00597   *         @arg @ref LL_EXTI_LINE_35
00598   *         @arg @ref LL_EXTI_LINE_36
00599   *         @arg @ref LL_EXTI_LINE_37
00600   *         @arg @ref LL_EXTI_LINE_38
00601   *         @arg @ref LL_EXTI_LINE_39
00602   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00603   * @retval None
00604   */
00605 __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
00606 {
00607   CLEAR_BIT(EXTI->EMR2, ExtiLine);
00608 }
00609
00610 /**
00611   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
00612   * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
00613   * @param  ExtiLine This parameter can be one of the following values:
00614   *         @arg @ref LL_EXTI_LINE_0
00615   *         @arg @ref LL_EXTI_LINE_1
00616   *         @arg @ref LL_EXTI_LINE_2
00617   *         @arg @ref LL_EXTI_LINE_3
00618   *         @arg @ref LL_EXTI_LINE_4
00619   *         @arg @ref LL_EXTI_LINE_5
00620   *         @arg @ref LL_EXTI_LINE_6
00621   *         @arg @ref LL_EXTI_LINE_7
00622   *         @arg @ref LL_EXTI_LINE_8
00623   *         @arg @ref LL_EXTI_LINE_9
00624   *         @arg @ref LL_EXTI_LINE_10
00625   *         @arg @ref LL_EXTI_LINE_11
00626   *         @arg @ref LL_EXTI_LINE_12
00627   *         @arg @ref LL_EXTI_LINE_13
00628   *         @arg @ref LL_EXTI_LINE_14
00629   *         @arg @ref LL_EXTI_LINE_15
00630   *         @arg @ref LL_EXTI_LINE_16
00631   *         @arg @ref LL_EXTI_LINE_17
00632   *         @arg @ref LL_EXTI_LINE_18
00633   *         @arg @ref LL_EXTI_LINE_19
00634   *         @arg @ref LL_EXTI_LINE_20
00635   *         @arg @ref LL_EXTI_LINE_21
00636   *         @arg @ref LL_EXTI_LINE_22
00637   *         @arg @ref LL_EXTI_LINE_23
00638   *         @arg @ref LL_EXTI_LINE_24
00639   *         @arg @ref LL_EXTI_LINE_25
00640   *         @arg @ref LL_EXTI_LINE_26
00641   *         @arg @ref LL_EXTI_LINE_27
00642   *         @arg @ref LL_EXTI_LINE_28
00643   *         @arg @ref LL_EXTI_LINE_29
00644   *         @arg @ref LL_EXTI_LINE_30
00645   *         @arg @ref LL_EXTI_LINE_31
00646   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00647   * @note   Please check each device line mapping for EXTI Line availability
00648   * @retval State of bit (1 or 0).
00649   */
00650 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
00651 {
00652   return (READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine));
00653
00654 }
00655
00656 /**
00657   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
00658   * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
00659   * @param  ExtiLine This parameter can be a combination of the following values:
00660   *         @arg @ref LL_EXTI_LINE_32
00661   *         @arg @ref LL_EXTI_LINE_33
00662   *         @arg @ref LL_EXTI_LINE_34
00663   *         @arg @ref LL_EXTI_LINE_35
00664   *         @arg @ref LL_EXTI_LINE_36
00665   *         @arg @ref LL_EXTI_LINE_37
00666   *         @arg @ref LL_EXTI_LINE_38
00667   *         @arg @ref LL_EXTI_LINE_39
00668   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00669   * @retval State of bit (1 or 0).
00670   */
00671 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
00672 {
00673   return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine));
00674 }
00675
00676 /**
00677   * @}
00678   */
00679
00680 /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
00681   * @{
00682   */
00683
00684 /**
00685   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00686   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00687   *       generated on these lines. If a rising edge on a configurable interrupt
00688   *       line occurs during a write operation in the EXTI_RTSR register, the
00689   *       pending bit is not set.
00690   *       Rising and falling edge triggers can be set for
00691   *       the same interrupt line. In this case, both generate a trigger
00692   *       condition.
00693   * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
00694   * @param  ExtiLine This parameter can be a combination of the following values:
00695   *         @arg @ref LL_EXTI_LINE_0
00696   *         @arg @ref LL_EXTI_LINE_1
00697   *         @arg @ref LL_EXTI_LINE_2
00698   *         @arg @ref LL_EXTI_LINE_3
00699   *         @arg @ref LL_EXTI_LINE_4
00700   *         @arg @ref LL_EXTI_LINE_5
00701   *         @arg @ref LL_EXTI_LINE_6
00702   *         @arg @ref LL_EXTI_LINE_7
00703   *         @arg @ref LL_EXTI_LINE_8
00704   *         @arg @ref LL_EXTI_LINE_9
00705   *         @arg @ref LL_EXTI_LINE_10
00706   *         @arg @ref LL_EXTI_LINE_11
00707   *         @arg @ref LL_EXTI_LINE_12
00708   *         @arg @ref LL_EXTI_LINE_13
00709   *         @arg @ref LL_EXTI_LINE_14
00710   *         @arg @ref LL_EXTI_LINE_15
00711   *         @arg @ref LL_EXTI_LINE_16
00712   *         @arg @ref LL_EXTI_LINE_18
00713   *         @arg @ref LL_EXTI_LINE_19
00714   *         @arg @ref LL_EXTI_LINE_20
00715   *         @arg @ref LL_EXTI_LINE_21
00716   *         @arg @ref LL_EXTI_LINE_22
00717   *         @arg @ref LL_EXTI_LINE_29
00718   *         @arg @ref LL_EXTI_LINE_30
00719   *         @arg @ref LL_EXTI_LINE_31
00720   * @note   Please check each device line mapping for EXTI Line availability
00721   * @retval None
00722   */
00723 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
00724 {
00725   SET_BIT(EXTI->RTSR1, ExtiLine);
00726
00727 }
00728
00729 /**
00730   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
00731   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00732   *       generated on these lines. If a rising edge on a configurable interrupt
00733   *       line occurs during a write operation in the EXTI_RTSR register, the
00734   *       pending bit is not set.Rising and falling edge triggers can be set for
00735   *       the same interrupt line. In this case, both generate a trigger
00736   *       condition.
00737   * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
00738   * @param  ExtiLine This parameter can be a combination of the following values:
00739   *         @arg @ref LL_EXTI_LINE_35
00740   *         @arg @ref LL_EXTI_LINE_36
00741   *         @arg @ref LL_EXTI_LINE_37
00742   *         @arg @ref LL_EXTI_LINE_38
00743   * @retval None
00744   */
00745 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
00746 {
00747   SET_BIT(EXTI->RTSR2, ExtiLine);
00748 }
00749
00750 /**
00751   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00752   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00753   *       generated on these lines. If a rising edge on a configurable interrupt
00754   *       line occurs during a write operation in the EXTI_RTSR register, the
00755   *       pending bit is not set.
00756   *       Rising and falling edge triggers can be set for
00757   *       the same interrupt line. In this case, both generate a trigger
00758   *       condition.
00759   * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
00760   * @param  ExtiLine This parameter can be a combination of the following values:
00761   *         @arg @ref LL_EXTI_LINE_0
00762   *         @arg @ref LL_EXTI_LINE_1
00763   *         @arg @ref LL_EXTI_LINE_2
00764   *         @arg @ref LL_EXTI_LINE_3
00765   *         @arg @ref LL_EXTI_LINE_4
00766   *         @arg @ref LL_EXTI_LINE_5
00767   *         @arg @ref LL_EXTI_LINE_6
00768   *         @arg @ref LL_EXTI_LINE_7
00769   *         @arg @ref LL_EXTI_LINE_8
00770   *         @arg @ref LL_EXTI_LINE_9
00771   *         @arg @ref LL_EXTI_LINE_10
00772   *         @arg @ref LL_EXTI_LINE_11
00773   *         @arg @ref LL_EXTI_LINE_12
00774   *         @arg @ref LL_EXTI_LINE_13
00775   *         @arg @ref LL_EXTI_LINE_14
00776   *         @arg @ref LL_EXTI_LINE_15
00777   *         @arg @ref LL_EXTI_LINE_16
00778   *         @arg @ref LL_EXTI_LINE_18
00779   *         @arg @ref LL_EXTI_LINE_19
00780   *         @arg @ref LL_EXTI_LINE_20
00781   *         @arg @ref LL_EXTI_LINE_21
00782   *         @arg @ref LL_EXTI_LINE_22
00783   *         @arg @ref LL_EXTI_LINE_29
00784   *         @arg @ref LL_EXTI_LINE_30
00785   *         @arg @ref LL_EXTI_LINE_31
00786   * @note   Please check each device line mapping for EXTI Line availability
00787   * @retval None
00788   */
00789 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
00790 {
00791   CLEAR_BIT(EXTI->RTSR1, ExtiLine);
00792
00793 }
00794
00795 /**
00796   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
00797   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00798   *       generated on these lines. If a rising edge on a configurable interrupt
00799   *       line occurs during a write operation in the EXTI_RTSR register, the
00800   *       pending bit is not set.
00801   *       Rising and falling edge triggers can be set for
00802   *       the same interrupt line. In this case, both generate a trigger
00803   *       condition.
00804   * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
00805   * @param  ExtiLine This parameter can be a combination of the following values:
00806   *         @arg @ref LL_EXTI_LINE_35
00807   *         @arg @ref LL_EXTI_LINE_36
00808   *         @arg @ref LL_EXTI_LINE_37
00809   *         @arg @ref LL_EXTI_LINE_38
00810   * @retval None
00811   */
00812 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
00813 {
00814   CLEAR_BIT(EXTI->RTSR2, ExtiLine);
00815 }
00816
00817 /**
00818   * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
00819   * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
00820   * @param  ExtiLine This parameter can be a combination of the following values:
00821   *         @arg @ref LL_EXTI_LINE_0
00822   *         @arg @ref LL_EXTI_LINE_1
00823   *         @arg @ref LL_EXTI_LINE_2
00824   *         @arg @ref LL_EXTI_LINE_3
00825   *         @arg @ref LL_EXTI_LINE_4
00826   *         @arg @ref LL_EXTI_LINE_5
00827   *         @arg @ref LL_EXTI_LINE_6
00828   *         @arg @ref LL_EXTI_LINE_7
00829   *         @arg @ref LL_EXTI_LINE_8
00830   *         @arg @ref LL_EXTI_LINE_9
00831   *         @arg @ref LL_EXTI_LINE_10
00832   *         @arg @ref LL_EXTI_LINE_11
00833   *         @arg @ref LL_EXTI_LINE_12
00834   *         @arg @ref LL_EXTI_LINE_13
00835   *         @arg @ref LL_EXTI_LINE_14
00836   *         @arg @ref LL_EXTI_LINE_15
00837   *         @arg @ref LL_EXTI_LINE_16
00838   *         @arg @ref LL_EXTI_LINE_18
00839   *         @arg @ref LL_EXTI_LINE_19
00840   *         @arg @ref LL_EXTI_LINE_20
00841   *         @arg @ref LL_EXTI_LINE_21
00842   *         @arg @ref LL_EXTI_LINE_22
00843   *         @arg @ref LL_EXTI_LINE_29
00844   *         @arg @ref LL_EXTI_LINE_30
00845   *         @arg @ref LL_EXTI_LINE_31
00846   * @note   Please check each device line mapping for EXTI Line availability
00847   * @retval State of bit (1 or 0).
00848   */
00849 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
00850 {
00851   return (READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine));
00852 }
00853
00854 /**
00855   * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
00856   * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
00857   * @param  ExtiLine This parameter can be a combination of the following values:
00858   *         @arg @ref LL_EXTI_LINE_35
00859   *         @arg @ref LL_EXTI_LINE_36
00860   *         @arg @ref LL_EXTI_LINE_37
00861   *         @arg @ref LL_EXTI_LINE_38
00862   * @retval State of bit (1 or 0).
00863   */
00864 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
00865 {
00866   return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine));
00867 }
00868
00869 /**
00870   * @}
00871   */
00872
00873 /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
00874   * @{
00875   */
00876
00877 /**
00878   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
00879   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00880   *       generated on these lines. If a falling edge on a configurable interrupt
00881   *       line occurs during a write operation in the EXTI_FTSR register, the
00882   *       pending bit is not set.
00883   *       Rising and falling edge triggers can be set for
00884   *       the same interrupt line. In this case, both generate a trigger
00885   *       condition.
00886   * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
00887   * @param  ExtiLine This parameter can be a combination of the following values:
00888   *         @arg @ref LL_EXTI_LINE_0
00889   *         @arg @ref LL_EXTI_LINE_1
00890   *         @arg @ref LL_EXTI_LINE_2
00891   *         @arg @ref LL_EXTI_LINE_3
00892   *         @arg @ref LL_EXTI_LINE_4
00893   *         @arg @ref LL_EXTI_LINE_5
00894   *         @arg @ref LL_EXTI_LINE_6
00895   *         @arg @ref LL_EXTI_LINE_7
00896   *         @arg @ref LL_EXTI_LINE_8
00897   *         @arg @ref LL_EXTI_LINE_9
00898   *         @arg @ref LL_EXTI_LINE_10
00899   *         @arg @ref LL_EXTI_LINE_11
00900   *         @arg @ref LL_EXTI_LINE_12
00901   *         @arg @ref LL_EXTI_LINE_13
00902   *         @arg @ref LL_EXTI_LINE_14
00903   *         @arg @ref LL_EXTI_LINE_15
00904   *         @arg @ref LL_EXTI_LINE_16
00905   *         @arg @ref LL_EXTI_LINE_18
00906   *         @arg @ref LL_EXTI_LINE_19
00907   *         @arg @ref LL_EXTI_LINE_20
00908   *         @arg @ref LL_EXTI_LINE_21
00909   *         @arg @ref LL_EXTI_LINE_22
00910   *         @arg @ref LL_EXTI_LINE_29
00911   *         @arg @ref LL_EXTI_LINE_30
00912   *         @arg @ref LL_EXTI_LINE_31
00913   * @note   Please check each device line mapping for EXTI Line availability
00914   * @retval None
00915   */
00916 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
00917 {
00918   SET_BIT(EXTI->FTSR1, ExtiLine);
00919 }
00920
00921 /**
00922   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
00923   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00924   *       generated on these lines. If a Falling edge on a configurable interrupt
00925   *       line occurs during a write operation in the EXTI_FTSR register, the
00926   *       pending bit is not set.
00927   *       Rising and falling edge triggers can be set for
00928   *       the same interrupt line. In this case, both generate a trigger
00929   *       condition.
00930   * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
00931   * @param  ExtiLine This parameter can be a combination of the following values:
00932   *         @arg @ref LL_EXTI_LINE_35
00933   *         @arg @ref LL_EXTI_LINE_36
00934   *         @arg @ref LL_EXTI_LINE_37
00935   *         @arg @ref LL_EXTI_LINE_38
00936   * @retval None
00937   */
00938 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
00939 {
00940   SET_BIT(EXTI->FTSR2, ExtiLine);
00941 }
00942
00943 /**
00944   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
00945   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00946   *       generated on these lines. If a Falling edge on a configurable interrupt
00947   *       line occurs during a write operation in the EXTI_FTSR register, the
00948   *       pending bit is not set.
00949   *       Rising and falling edge triggers can be set for the same interrupt line.
00950   *       In this case, both generate a trigger condition.
00951   * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
00952   * @param  ExtiLine This parameter can be a combination of the following values:
00953   *         @arg @ref LL_EXTI_LINE_0
00954   *         @arg @ref LL_EXTI_LINE_1
00955   *         @arg @ref LL_EXTI_LINE_2
00956   *         @arg @ref LL_EXTI_LINE_3
00957   *         @arg @ref LL_EXTI_LINE_4
00958   *         @arg @ref LL_EXTI_LINE_5
00959   *         @arg @ref LL_EXTI_LINE_6
00960   *         @arg @ref LL_EXTI_LINE_7
00961   *         @arg @ref LL_EXTI_LINE_8
00962   *         @arg @ref LL_EXTI_LINE_9
00963   *         @arg @ref LL_EXTI_LINE_10
00964   *         @arg @ref LL_EXTI_LINE_11
00965   *         @arg @ref LL_EXTI_LINE_12
00966   *         @arg @ref LL_EXTI_LINE_13
00967   *         @arg @ref LL_EXTI_LINE_14
00968   *         @arg @ref LL_EXTI_LINE_15
00969   *         @arg @ref LL_EXTI_LINE_16
00970   *         @arg @ref LL_EXTI_LINE_18
00971   *         @arg @ref LL_EXTI_LINE_19
00972   *         @arg @ref LL_EXTI_LINE_20
00973   *         @arg @ref LL_EXTI_LINE_21
00974   *         @arg @ref LL_EXTI_LINE_22
00975   *         @arg @ref LL_EXTI_LINE_29
00976   *         @arg @ref LL_EXTI_LINE_30
00977   *         @arg @ref LL_EXTI_LINE_31
00978   * @note   Please check each device line mapping for EXTI Line availability
00979   * @retval None
00980   */
00981 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
00982 {
00983   CLEAR_BIT(EXTI->FTSR1, ExtiLine);
00984 }
00985
00986 /**
00987   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
00988   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00989   *       generated on these lines. If a Falling edge on a configurable interrupt
00990   *       line occurs during a write operation in the EXTI_FTSR register, the
00991   *       pending bit is not set.
00992   *       Rising and falling edge triggers can be set for the same interrupt line.
00993   *       In this case, both generate a trigger condition.
00994   * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
00995   * @param  ExtiLine This parameter can be a combination of the following values:
00996   *         @arg @ref LL_EXTI_LINE_35
00997   *         @arg @ref LL_EXTI_LINE_36
00998   *         @arg @ref LL_EXTI_LINE_37
00999   *         @arg @ref LL_EXTI_LINE_38
01000   * @retval None
01001   */
01002 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
01003 {
01004   CLEAR_BIT(EXTI->FTSR2, ExtiLine);
01005 }
01006
01007 /**
01008   * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
01009   * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
01010   * @param  ExtiLine This parameter can be a combination of the following values:
01011   *         @arg @ref LL_EXTI_LINE_0
01012   *         @arg @ref LL_EXTI_LINE_1
01013   *         @arg @ref LL_EXTI_LINE_2
01014   *         @arg @ref LL_EXTI_LINE_3
01015   *         @arg @ref LL_EXTI_LINE_4
01016   *         @arg @ref LL_EXTI_LINE_5
01017   *         @arg @ref LL_EXTI_LINE_6
01018   *         @arg @ref LL_EXTI_LINE_7
01019   *         @arg @ref LL_EXTI_LINE_8
01020   *         @arg @ref LL_EXTI_LINE_9
01021   *         @arg @ref LL_EXTI_LINE_10
01022   *         @arg @ref LL_EXTI_LINE_11
01023   *         @arg @ref LL_EXTI_LINE_12
01024   *         @arg @ref LL_EXTI_LINE_13
01025   *         @arg @ref LL_EXTI_LINE_14
01026   *         @arg @ref LL_EXTI_LINE_15
01027   *         @arg @ref LL_EXTI_LINE_16
01028   *         @arg @ref LL_EXTI_LINE_18
01029   *         @arg @ref LL_EXTI_LINE_19
01030   *         @arg @ref LL_EXTI_LINE_20
01031   *         @arg @ref LL_EXTI_LINE_21
01032   *         @arg @ref LL_EXTI_LINE_22
01033   *         @arg @ref LL_EXTI_LINE_29
01034   *         @arg @ref LL_EXTI_LINE_30
01035   *         @arg @ref LL_EXTI_LINE_31
01036   * @note   Please check each device line mapping for EXTI Line availability
01037   * @retval State of bit (1 or 0).
01038   */
01039 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
01040 {
01041   return (READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine));
01042 }
01043
01044 /**
01045   * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
01046   * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
01047   * @param  ExtiLine This parameter can be a combination of the following values:
01048   *         @arg @ref LL_EXTI_LINE_35
01049   *         @arg @ref LL_EXTI_LINE_36
01050   *         @arg @ref LL_EXTI_LINE_37
01051   *         @arg @ref LL_EXTI_LINE_38
01052   * @retval State of bit (1 or 0).
01053   */
01054 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
01055 {
01056   return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine));
01057 }
01058
01059 /**
01060   * @}
01061   */
01062
01063 /** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
01064   * @{
01065   */
01066
01067 /**
01068   * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
01069   * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
01070   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
01071   *       resulting in an interrupt request generation.
01072   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
01073   *       register (by writing a 1 into the bit)
01074   * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
01075   * @param  ExtiLine This parameter can be a combination of the following values:
01076   *         @arg @ref LL_EXTI_LINE_0
01077   *         @arg @ref LL_EXTI_LINE_1
01078   *         @arg @ref LL_EXTI_LINE_2
01079   *         @arg @ref LL_EXTI_LINE_3
01080   *         @arg @ref LL_EXTI_LINE_4
01081   *         @arg @ref LL_EXTI_LINE_5
01082   *         @arg @ref LL_EXTI_LINE_6
01083   *         @arg @ref LL_EXTI_LINE_7
01084   *         @arg @ref LL_EXTI_LINE_8
01085   *         @arg @ref LL_EXTI_LINE_9
01086   *         @arg @ref LL_EXTI_LINE_10
01087   *         @arg @ref LL_EXTI_LINE_11
01088   *         @arg @ref LL_EXTI_LINE_12
01089   *         @arg @ref LL_EXTI_LINE_13
01090   *         @arg @ref LL_EXTI_LINE_14
01091   *         @arg @ref LL_EXTI_LINE_15
01092   *         @arg @ref LL_EXTI_LINE_16
01093   *         @arg @ref LL_EXTI_LINE_18
01094   *         @arg @ref LL_EXTI_LINE_19
01095   *         @arg @ref LL_EXTI_LINE_20
01096   *         @arg @ref LL_EXTI_LINE_21
01097   *         @arg @ref LL_EXTI_LINE_22
01098   *         @arg @ref LL_EXTI_LINE_29
01099   *         @arg @ref LL_EXTI_LINE_30
01100   *         @arg @ref LL_EXTI_LINE_31
01101   * @note   Please check each device line mapping for EXTI Line availability
01102   * @retval None
01103   */
01104 __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
01105 {
01106   SET_BIT(EXTI->SWIER1, ExtiLine);
01107 }
01108
01109 /**
01110   * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
01111   * @note If the interrupt is enabled on this line inthe EXTI_IMR, writing a 1 to
01112   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
01113   *       resulting in an interrupt request generation.
01114   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
01115   *       register (by writing a 1 into the bit)
01116   * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
01117   * @param  ExtiLine This parameter can be a combination of the following values:
01118   *         @arg @ref LL_EXTI_LINE_35
01119   *         @arg @ref LL_EXTI_LINE_36
01120   *         @arg @ref LL_EXTI_LINE_37
01121   *         @arg @ref LL_EXTI_LINE_38
01122   * @retval None
01123   */
01124 __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
01125 {
01126   SET_BIT(EXTI->SWIER2, ExtiLine);
01127 }
01128
01129 /**
01130   * @}
01131   */
01132
01133 /** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
01134   * @{
01135   */
01136
01137 /**
01138   * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
01139   * @note This bit is set when the selected edge event arrives on the interrupt
01140   *       line. This bit is cleared by writing a 1 to the bit.
01141   * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31
01142   * @param  ExtiLine This parameter can be a combination of the following values:
01143   *         @arg @ref LL_EXTI_LINE_0
01144   *         @arg @ref LL_EXTI_LINE_1
01145   *         @arg @ref LL_EXTI_LINE_2
01146   *         @arg @ref LL_EXTI_LINE_3
01147   *         @arg @ref LL_EXTI_LINE_4
01148   *         @arg @ref LL_EXTI_LINE_5
01149   *         @arg @ref LL_EXTI_LINE_6
01150   *         @arg @ref LL_EXTI_LINE_7
01151   *         @arg @ref LL_EXTI_LINE_8
01152   *         @arg @ref LL_EXTI_LINE_9
01153   *         @arg @ref LL_EXTI_LINE_10
01154   *         @arg @ref LL_EXTI_LINE_11
01155   *         @arg @ref LL_EXTI_LINE_12
01156   *         @arg @ref LL_EXTI_LINE_13
01157   *         @arg @ref LL_EXTI_LINE_14
01158   *         @arg @ref LL_EXTI_LINE_15
01159   *         @arg @ref LL_EXTI_LINE_16
01160   *         @arg @ref LL_EXTI_LINE_18
01161   *         @arg @ref LL_EXTI_LINE_19
01162   *         @arg @ref LL_EXTI_LINE_20
01163   *         @arg @ref LL_EXTI_LINE_21
01164   *         @arg @ref LL_EXTI_LINE_22
01165   *         @arg @ref LL_EXTI_LINE_29
01166   *         @arg @ref LL_EXTI_LINE_30
01167   *         @arg @ref LL_EXTI_LINE_31
01168   * @note   Please check each device line mapping for EXTI Line availability
01169   * @retval State of bit (1 or 0).
01170   */
01171 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
01172 {
01173   return (READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine));
01174 }
01175
01176 /**
01177   * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
01178   * @note This bit is set when the selected edge event arrives on the interrupt
01179   *       line. This bit is cleared by writing a 1 to the bit.
01180   * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
01181   * @param  ExtiLine This parameter can be a combination of the following values:
01182   *         @arg @ref LL_EXTI_LINE_35
01183   *         @arg @ref LL_EXTI_LINE_36
01184   *         @arg @ref LL_EXTI_LINE_37
01185   *         @arg @ref LL_EXTI_LINE_38
01186   * @retval State of bit (1 or 0).
01187   */
01188 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
01189 {
01190   return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine));
01191 }
01192
01193 /**
01194   * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
01195   * @note This bit is set when the selected edge event arrives on the interrupt
01196   *       line. This bit is cleared by writing a 1 to the bit.
01197   * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31
01198   * @param  ExtiLine This parameter can be a combination of the following values:
01199   *         @arg @ref LL_EXTI_LINE_0
01200   *         @arg @ref LL_EXTI_LINE_1
01201   *         @arg @ref LL_EXTI_LINE_2
01202   *         @arg @ref LL_EXTI_LINE_3
01203   *         @arg @ref LL_EXTI_LINE_4
01204   *         @arg @ref LL_EXTI_LINE_5
01205   *         @arg @ref LL_EXTI_LINE_6
01206   *         @arg @ref LL_EXTI_LINE_7
01207   *         @arg @ref LL_EXTI_LINE_8
01208   *         @arg @ref LL_EXTI_LINE_9
01209   *         @arg @ref LL_EXTI_LINE_10
01210   *         @arg @ref LL_EXTI_LINE_11
01211   *         @arg @ref LL_EXTI_LINE_12
01212   *         @arg @ref LL_EXTI_LINE_13
01213   *         @arg @ref LL_EXTI_LINE_14
01214   *         @arg @ref LL_EXTI_LINE_15
01215   *         @arg @ref LL_EXTI_LINE_16
01216   *         @arg @ref LL_EXTI_LINE_18
01217   *         @arg @ref LL_EXTI_LINE_19
01218   *         @arg @ref LL_EXTI_LINE_20
01219   *         @arg @ref LL_EXTI_LINE_21
01220   *         @arg @ref LL_EXTI_LINE_22
01221   *         @arg @ref LL_EXTI_LINE_29
01222   *         @arg @ref LL_EXTI_LINE_30
01223   *         @arg @ref LL_EXTI_LINE_31
01224   * @note   Please check each device line mapping for EXTI Line availability
01225   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01226   */
01227 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
01228 {
01229   return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
01230 }
01231
01232
01233 /**
01234   * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
01235   * @note This bit is set when the selected edge event arrives on the interrupt
01236   *       line. This bit is cleared by writing a 1 to the bit.
01237   * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
01238   * @param  ExtiLine This parameter can be a combination of the following values:
01239   *         @arg @ref LL_EXTI_LINE_35
01240   *         @arg @ref LL_EXTI_LINE_36
01241   *         @arg @ref LL_EXTI_LINE_37
01242   *         @arg @ref LL_EXTI_LINE_38
01243   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01244   */
01245 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
01246 {
01247   return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
01248 }
01249
01250 /**
01251   * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
01252   * @note This bit is set when the selected edge event arrives on the interrupt
01253   *       line. This bit is cleared by writing a 1 to the bit.
01254   * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31
01255   * @param  ExtiLine This parameter can be a combination of the following values:
01256   *         @arg @ref LL_EXTI_LINE_0
01257   *         @arg @ref LL_EXTI_LINE_1
01258   *         @arg @ref LL_EXTI_LINE_2
01259   *         @arg @ref LL_EXTI_LINE_3
01260   *         @arg @ref LL_EXTI_LINE_4
01261   *         @arg @ref LL_EXTI_LINE_5
01262   *         @arg @ref LL_EXTI_LINE_6
01263   *         @arg @ref LL_EXTI_LINE_7
01264   *         @arg @ref LL_EXTI_LINE_8
01265   *         @arg @ref LL_EXTI_LINE_9
01266   *         @arg @ref LL_EXTI_LINE_10
01267   *         @arg @ref LL_EXTI_LINE_11
01268   *         @arg @ref LL_EXTI_LINE_12
01269   *         @arg @ref LL_EXTI_LINE_13
01270   *         @arg @ref LL_EXTI_LINE_14
01271   *         @arg @ref LL_EXTI_LINE_15
01272   *         @arg @ref LL_EXTI_LINE_16
01273   *         @arg @ref LL_EXTI_LINE_18
01274   *         @arg @ref LL_EXTI_LINE_19
01275   *         @arg @ref LL_EXTI_LINE_20
01276   *         @arg @ref LL_EXTI_LINE_21
01277   *         @arg @ref LL_EXTI_LINE_22
01278   *         @arg @ref LL_EXTI_LINE_29
01279   *         @arg @ref LL_EXTI_LINE_30
01280   *         @arg @ref LL_EXTI_LINE_31
01281   * @note   Please check each device line mapping for EXTI Line availability
01282   * @retval None
01283   */
01284 __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
01285 {
01286   WRITE_REG(EXTI->PR1, ExtiLine);
01287 }
01288
01289 /**
01290   * @brief  Clear ExtLine Flags for  Lines in range 32 to 63
01291   * @note This bit is set when the selected edge event arrives on the interrupt
01292   *       line. This bit is cleared by writing a 1 to the bit.
01293   * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
01294   * @param  ExtiLine This parameter can be a combination of the following values:
01295   *         @arg @ref LL_EXTI_LINE_35
01296   *         @arg @ref LL_EXTI_LINE_36
01297   *         @arg @ref LL_EXTI_LINE_37
01298   *         @arg @ref LL_EXTI_LINE_38
01299   * @retval None
01300   */
01301 __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
01302 {
01303   WRITE_REG(EXTI->PR2, ExtiLine);
01304 }
01305
01306 /**
01307   * @}
01308   */
01309
01310 #if defined(USE_FULL_LL_DRIVER)
01311 /** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
01312   * @{
01313   */
01314
01315 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
01316 uint32_t LL_EXTI_DeInit(void);
01317 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
01318
01319
01320 /**
01321   * @}
01322   */
01323 #endif /* USE_FULL_LL_DRIVER */
01324
01325 /**
01326   * @}
01327   */
01328
01329 /**
01330   * @}
01331   */
01332
01333 #endif /* EXTI */
01334
01335 /**
01336   * @}
01337   */
01338
01339 #ifdef __cplusplus
01340 }
01341 #endif
01342
01343 #endif /* __STM32L4xx_LL_EXTI_H */
01344
01345 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_gpio.c Source File

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stm32l4xx_ll_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_gpio.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   GPIO LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_gpio.h"
00041 #include "stm32l4xx_ll_bus.h"
00042 #ifdef  USE_FULL_ASSERT
00043 #include "stm32_assert.h"
00044 #else
00045 #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32L4xx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI)
00053
00054 /** @addtogroup GPIO_LL
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062 /** @addtogroup GPIO_LL_Private_Macros
00063   * @{
00064   */
00065 #define IS_LL_GPIO_PIN(__VALUE__)          ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
00066
00067 #define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
00068                                             ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
00069                                             ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
00070                                             ((__VALUE__) == LL_GPIO_MODE_ANALOG))
00071
00072 #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
00073                                             ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
00074
00075 #define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
00076                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
00077                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
00078                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
00079
00080 #define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
00081                                             ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
00082                                             ((__VALUE__) == LL_GPIO_PULL_DOWN))
00083
00084 #define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
00085                                             ((__VALUE__) == LL_GPIO_AF_1  )   ||\
00086                                             ((__VALUE__) == LL_GPIO_AF_2  )   ||\
00087                                             ((__VALUE__) == LL_GPIO_AF_3  )   ||\
00088                                             ((__VALUE__) == LL_GPIO_AF_4  )   ||\
00089                                             ((__VALUE__) == LL_GPIO_AF_5  )   ||\
00090                                             ((__VALUE__) == LL_GPIO_AF_6  )   ||\
00091                                             ((__VALUE__) == LL_GPIO_AF_7  )   ||\
00092                                             ((__VALUE__) == LL_GPIO_AF_8  )   ||\
00093                                             ((__VALUE__) == LL_GPIO_AF_9  )   ||\
00094                                             ((__VALUE__) == LL_GPIO_AF_10 )   ||\
00095                                             ((__VALUE__) == LL_GPIO_AF_11 )   ||\
00096                                             ((__VALUE__) == LL_GPIO_AF_12 )   ||\
00097                                             ((__VALUE__) == LL_GPIO_AF_13 )   ||\
00098                                             ((__VALUE__) == LL_GPIO_AF_14 )   ||\
00099                                             ((__VALUE__) == LL_GPIO_AF_15 ))
00100 /**
00101   * @}
00102   */
00103
00104 /* Private function prototypes -----------------------------------------------*/
00105
00106 /* Exported functions --------------------------------------------------------*/
00107 /** @addtogroup GPIO_LL_Exported_Functions
00108   * @{
00109   */
00110
00111 /** @addtogroup GPIO_LL_EF_Init
00112   * @{
00113   */
00114
00115 /**
00116   * @brief  De-initialize GPIO registers (Registers restored to their default values).
00117   * @param  GPIOx GPIO Port
00118   * @retval An ErrorStatus enumeration value:
00119   *          - SUCCESS: GPIO registers are de-initialized
00120   *          - ERROR:   Wrong GPIO Port
00121   */
00122 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
00123 {
00124   ErrorStatus status = SUCCESS;
00125
00126   /* Check the parameters */
00127   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00128
00129   /* Force and Release reset on clock of GPIOx Port */
00130   if (GPIOx == GPIOA)
00131   {
00132     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA);
00133     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA);
00134   }
00135   else if (GPIOx == GPIOB)
00136   {
00137     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB);
00138     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB);
00139   }
00140   else if (GPIOx == GPIOC)
00141   {
00142     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC);
00143     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC);
00144   }
00145 #if defined(GPIOD)
00146   else if (GPIOx == GPIOD)
00147   {
00148     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD);
00149     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD);
00150   }
00151 #endif /* GPIOD */
00152 #if defined(GPIOE)
00153   else if (GPIOx == GPIOE)
00154   {
00155     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE);
00156     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE);
00157   }
00158 #endif /* GPIOE */
00159 #if defined(GPIOF)
00160   else if (GPIOx == GPIOF)
00161   {
00162     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOF);
00163     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOF);
00164   }
00165 #endif /* GPIOF */
00166 #if defined(GPIOG)
00167   else if (GPIOx == GPIOG)
00168   {
00169     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOG);
00170     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOG);
00171   }
00172 #endif /* GPIOG */
00173 #if defined(GPIOH)
00174   else if (GPIOx == GPIOH)
00175   {
00176     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH);
00177     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH);
00178   }
00179 #endif /* GPIOH */
00180 #if defined(GPIOI)
00181   else if (GPIOx == GPIOI)
00182   {
00183     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOI);
00184     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI);
00185   }
00186 #endif /* GPIOI */
00187   else
00188   {
00189     status = ERROR;
00190   }
00191
00192   return (status);
00193 }
00194
00195 /**
00196   * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
00197   * @param  GPIOx GPIO Port
00198   * @param  GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
00199   *         that contains the configuration information for the specified GPIO peripheral.
00200   * @retval An ErrorStatus enumeration value:
00201   *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
00202   *          - ERROR:   Not applicable
00203   */
00204 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
00205 {
00206   uint32_t pinpos     = 0x00000000U;
00207   uint32_t currentpin = 0x00000000U;
00208
00209   /* Check the parameters */
00210   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00211   assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
00212   assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
00213   assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
00214
00215   /* ------------------------- Configure the port pins ---------------- */
00216   /* Initialize  pinpos on first pin set */
00217   pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
00218
00219   /* Configure the port pins */
00220   while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
00221   {
00222     /* Get current io position */
00223     currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
00224
00225     if (currentpin)
00226     {
00227       /* Pin Mode configuration */
00228       LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
00229
00230       if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
00231       {
00232         /* Check Speed mode parameters */
00233         assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
00234
00235         /* Speed mode configuration */
00236         LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
00237       }
00238
00239       /* Pull-up Pull down resistor configuration*/
00240       LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
00241
00242       if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
00243       {
00244         /* Check Alternate parameter */
00245         assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
00246
00247         /* Speed mode configuration */
00248         if (POSITION_VAL(currentpin) < 0x00000008U)
00249         {
00250           LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00251         }
00252         else
00253         {
00254           LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00255         }
00256       }
00257     }
00258     pinpos++;
00259   }
00260
00261   if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
00262   {
00263     /* Check Output mode parameters */
00264     assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
00265
00266     /* Output mode configuration*/
00267     LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
00268
00269   }
00270   return (SUCCESS);
00271 }
00272
00273 /**
00274   * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
00275   * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
00276   *                          whose fields will be set to default values.
00277   * @retval None
00278   */
00279
00280 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
00281 {
00282   /* Reset GPIO init structure parameters values */
00283   GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
00284   GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
00285   GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
00286   GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
00287   GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
00288   GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
00289 }
00290
00291 /**
00292   * @}
00293   */
00294
00295 /**
00296   * @}
00297   */
00298
00299 /**
00300   * @}
00301   */
00302
00303 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */
00304
00305 /**
00306   * @}
00307   */
00308
00309 #endif /* USE_FULL_LL_DRIVER */
00310
00311 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00312
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_gpio.h Source File

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stm32l4xx_ll_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_gpio.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of GPIO LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_GPIO_H
00040 #define __STM32L4xx_LL_GPIO_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI)
00054
00055 /** @defgroup GPIO_LL GPIO
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 #if defined(USE_FULL_LL_DRIVER)
00064 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
00065   * @{
00066   */
00067
00068 /**
00069   * @}
00070   */
00071 #endif /*USE_FULL_LL_DRIVER*/
00072
00073 /* Exported types ------------------------------------------------------------*/
00074 #if defined(USE_FULL_LL_DRIVER)
00075 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
00076   * @{
00077   */
00078
00079 /**
00080   * @brief LL GPIO Init Structure definition
00081   */
00082 typedef struct
00083 {
00084   uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
00085                               This parameter can be any value of @ref GPIO_LL_EC_PIN */
00086
00087   uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
00088                               This parameter can be a value of @ref GPIO_LL_EC_MODE.
00089
00090                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
00091
00092   uint32_t Speed;        /*!< Specifies the speed for the selected pins.
00093                               This parameter can be a value of @ref GPIO_LL_EC_SPEED.
00094
00095                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
00096
00097   uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
00098                               This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
00099
00100                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
00101
00102   uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
00103                               This parameter can be a value of @ref GPIO_LL_EC_PULL.
00104
00105                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
00106
00107   uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
00108                               This parameter can be a value of @ref GPIO_LL_EC_AF.
00109
00110                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
00111 } LL_GPIO_InitTypeDef;
00112
00113 /**
00114   * @}
00115   */
00116 #endif /* USE_FULL_LL_DRIVER */
00117
00118 /* Exported constants --------------------------------------------------------*/
00119 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
00120   * @{
00121   */
00122
00123 /** @defgroup GPIO_LL_EC_PIN PIN
00124   * @{
00125   */
00126 #define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
00127 #define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
00128 #define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
00129 #define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
00130 #define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
00131 #define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
00132 #define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
00133 #define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
00134 #define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
00135 #define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
00136 #define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
00137 #define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
00138 #define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
00139 #define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
00140 #define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
00141 #define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
00142 #define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
00143                                            GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
00144                                            GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
00145                                            GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
00146                                            GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
00147                                            GPIO_BSRR_BS15) /*!< Select all pins */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup GPIO_LL_EC_MODE Mode
00153   * @{
00154   */
00155 #define LL_GPIO_MODE_INPUT                 ((uint32_t)0x00000000U) /*!< Select input mode */
00156 #define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
00157 #define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
00158 #define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
00164   * @{
00165   */
00166 #define LL_GPIO_OUTPUT_PUSHPULL            ((uint32_t)0x00000000U) /*!< Select push-pull as output type */
00167 #define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup GPIO_LL_EC_SPEED Output Speed
00173   * @{
00174   */
00175 #define LL_GPIO_SPEED_FREQ_LOW             ((uint32_t)0x00000000U) /*!< Select I/O low output speed    */
00176 #define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
00177 #define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
00178 #define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
00179 /**
00180   * @}
00181   */
00182 #define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
00183 #define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
00184 #define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
00185 #define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
00186
00187
00188 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
00189   * @{
00190   */
00191 #define LL_GPIO_PULL_NO                    ((uint32_t)0x00000000U) /*!< Select I/O no pull */
00192 #define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
00193 #define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup GPIO_LL_EC_AF Alternate Function
00199   * @{
00200   */
00201 #define LL_GPIO_AF_0                       ((uint32_t)0x0000000U) /*!< Select alternate function 0 */
00202 #define LL_GPIO_AF_1                       ((uint32_t)0x0000001U) /*!< Select alternate function 1 */
00203 #define LL_GPIO_AF_2                       ((uint32_t)0x0000002U) /*!< Select alternate function 2 */
00204 #define LL_GPIO_AF_3                       ((uint32_t)0x0000003U) /*!< Select alternate function 3 */
00205 #define LL_GPIO_AF_4                       ((uint32_t)0x0000004U) /*!< Select alternate function 4 */
00206 #define LL_GPIO_AF_5                       ((uint32_t)0x0000005U) /*!< Select alternate function 5 */
00207 #define LL_GPIO_AF_6                       ((uint32_t)0x0000006U) /*!< Select alternate function 6 */
00208 #define LL_GPIO_AF_7                       ((uint32_t)0x0000007U) /*!< Select alternate function 7 */
00209 #define LL_GPIO_AF_8                       ((uint32_t)0x0000008U) /*!< Select alternate function 8 */
00210 #define LL_GPIO_AF_9                       ((uint32_t)0x0000009U) /*!< Select alternate function 9 */
00211 #define LL_GPIO_AF_10                      ((uint32_t)0x000000AU) /*!< Select alternate function 10 */
00212 #define LL_GPIO_AF_11                      ((uint32_t)0x000000BU) /*!< Select alternate function 11 */
00213 #define LL_GPIO_AF_12                      ((uint32_t)0x000000CU) /*!< Select alternate function 12 */
00214 #define LL_GPIO_AF_13                      ((uint32_t)0x000000DU) /*!< Select alternate function 13 */
00215 #define LL_GPIO_AF_14                      ((uint32_t)0x000000EU) /*!< Select alternate function 14 */
00216 #define LL_GPIO_AF_15                      ((uint32_t)0x000000FU) /*!< Select alternate function 15 */
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /* Exported macro ------------------------------------------------------------*/
00226 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
00227   * @{
00228   */
00229
00230 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
00231   * @{
00232   */
00233
00234 /**
00235   * @brief  Write a value in GPIO register
00236   * @param  __INSTANCE__ GPIO Instance
00237   * @param  __REG__ Register to be written
00238   * @param  __VALUE__ Value to be written in the register
00239   * @retval None
00240   */
00241 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00242
00243 /**
00244   * @brief  Read a value in GPIO register
00245   * @param  __INSTANCE__ GPIO Instance
00246   * @param  __REG__ Register to be read
00247   * @retval Register value
00248   */
00249 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00250 /**
00251   * @}
00252   */
00253
00254 /**
00255   * @}
00256   */
00257
00258 /* Exported functions --------------------------------------------------------*/
00259 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
00260   * @{
00261   */
00262
00263 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
00264   * @{
00265   */
00266
00267 /**
00268   * @brief  Configure gpio mode for a dedicated pin on dedicated port.
00269   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00270   * @note   Warning: only one pin can be passed as parameter.
00271   * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
00272   * @param  GPIOx GPIO Port
00273   * @param  Pin This parameter can be one of the following values:
00274   *         @arg @ref LL_GPIO_PIN_0
00275   *         @arg @ref LL_GPIO_PIN_1
00276   *         @arg @ref LL_GPIO_PIN_2
00277   *         @arg @ref LL_GPIO_PIN_3
00278   *         @arg @ref LL_GPIO_PIN_4
00279   *         @arg @ref LL_GPIO_PIN_5
00280   *         @arg @ref LL_GPIO_PIN_6
00281   *         @arg @ref LL_GPIO_PIN_7
00282   *         @arg @ref LL_GPIO_PIN_8
00283   *         @arg @ref LL_GPIO_PIN_9
00284   *         @arg @ref LL_GPIO_PIN_10
00285   *         @arg @ref LL_GPIO_PIN_11
00286   *         @arg @ref LL_GPIO_PIN_12
00287   *         @arg @ref LL_GPIO_PIN_13
00288   *         @arg @ref LL_GPIO_PIN_14
00289   *         @arg @ref LL_GPIO_PIN_15
00290   * @param  Mode This parameter can be one of the following values:
00291   *         @arg @ref LL_GPIO_MODE_INPUT
00292   *         @arg @ref LL_GPIO_MODE_OUTPUT
00293   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00294   *         @arg @ref LL_GPIO_MODE_ANALOG
00295   * @retval None
00296   */
00297 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
00298 {
00299   MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
00300 }
00301
00302 /**
00303   * @brief  Return gpio mode for a dedicated pin on dedicated port.
00304   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00305   * @note   Warning: only one pin can be passed as parameter.
00306   * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
00307   * @param  GPIOx GPIO Port
00308   * @param  Pin This parameter can be one of the following values:
00309   *         @arg @ref LL_GPIO_PIN_0
00310   *         @arg @ref LL_GPIO_PIN_1
00311   *         @arg @ref LL_GPIO_PIN_2
00312   *         @arg @ref LL_GPIO_PIN_3
00313   *         @arg @ref LL_GPIO_PIN_4
00314   *         @arg @ref LL_GPIO_PIN_5
00315   *         @arg @ref LL_GPIO_PIN_6
00316   *         @arg @ref LL_GPIO_PIN_7
00317   *         @arg @ref LL_GPIO_PIN_8
00318   *         @arg @ref LL_GPIO_PIN_9
00319   *         @arg @ref LL_GPIO_PIN_10
00320   *         @arg @ref LL_GPIO_PIN_11
00321   *         @arg @ref LL_GPIO_PIN_12
00322   *         @arg @ref LL_GPIO_PIN_13
00323   *         @arg @ref LL_GPIO_PIN_14
00324   *         @arg @ref LL_GPIO_PIN_15
00325   * @retval Returned value can be one of the following values:
00326   *         @arg @ref LL_GPIO_MODE_INPUT
00327   *         @arg @ref LL_GPIO_MODE_OUTPUT
00328   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00329   *         @arg @ref LL_GPIO_MODE_ANALOG
00330   */
00331 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
00332 {
00333   return (uint32_t)(READ_BIT(GPIOx->MODER,
00334                              (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00335 }
00336
00337 /**
00338   * @brief  Configure gpio output type for several pins on dedicated port.
00339   * @note   Output type as to be set when gpio pin is in output or
00340   *         alternate modes. Possible type are Push-pull or Open-drain.
00341   * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
00342   * @param  GPIOx GPIO Port
00343   * @param  PinMask This parameter can be a combination of the following values:
00344   *         @arg @ref LL_GPIO_PIN_0
00345   *         @arg @ref LL_GPIO_PIN_1
00346   *         @arg @ref LL_GPIO_PIN_2
00347   *         @arg @ref LL_GPIO_PIN_3
00348   *         @arg @ref LL_GPIO_PIN_4
00349   *         @arg @ref LL_GPIO_PIN_5
00350   *         @arg @ref LL_GPIO_PIN_6
00351   *         @arg @ref LL_GPIO_PIN_7
00352   *         @arg @ref LL_GPIO_PIN_8
00353   *         @arg @ref LL_GPIO_PIN_9
00354   *         @arg @ref LL_GPIO_PIN_10
00355   *         @arg @ref LL_GPIO_PIN_11
00356   *         @arg @ref LL_GPIO_PIN_12
00357   *         @arg @ref LL_GPIO_PIN_13
00358   *         @arg @ref LL_GPIO_PIN_14
00359   *         @arg @ref LL_GPIO_PIN_15
00360   *         @arg @ref LL_GPIO_PIN_ALL
00361   * @param  OutputType This parameter can be one of the following values:
00362   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00363   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00364   * @retval None
00365   */
00366 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
00367 {
00368   MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
00369 }
00370
00371 /**
00372   * @brief  Return gpio output type for several pins on dedicated port.
00373   * @note   Output type as to be set when gpio pin is in output or
00374   *         alternate modes. Possible type are Push-pull or Open-drain.
00375   * @note   Warning: only one pin can be passed as parameter.
00376   * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
00377   * @param  GPIOx GPIO Port
00378   * @param  Pin This parameter can be one of the following values:
00379   *         @arg @ref LL_GPIO_PIN_0
00380   *         @arg @ref LL_GPIO_PIN_1
00381   *         @arg @ref LL_GPIO_PIN_2
00382   *         @arg @ref LL_GPIO_PIN_3
00383   *         @arg @ref LL_GPIO_PIN_4
00384   *         @arg @ref LL_GPIO_PIN_5
00385   *         @arg @ref LL_GPIO_PIN_6
00386   *         @arg @ref LL_GPIO_PIN_7
00387   *         @arg @ref LL_GPIO_PIN_8
00388   *         @arg @ref LL_GPIO_PIN_9
00389   *         @arg @ref LL_GPIO_PIN_10
00390   *         @arg @ref LL_GPIO_PIN_11
00391   *         @arg @ref LL_GPIO_PIN_12
00392   *         @arg @ref LL_GPIO_PIN_13
00393   *         @arg @ref LL_GPIO_PIN_14
00394   *         @arg @ref LL_GPIO_PIN_15
00395   *         @arg @ref LL_GPIO_PIN_ALL
00396   * @retval Returned value can be one of the following values:
00397   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00398   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00399   */
00400 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
00401 {
00402   return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
00403 }
00404
00405 /**
00406   * @brief  Configure gpio speed for a dedicated pin on dedicated port.
00407   * @note   I/O speed can be Low, Medium, Fast or High speed.
00408   * @note   Warning: only one pin can be passed as parameter.
00409   * @note   Refer to datasheet for frequency specifications and the power
00410   *         supply and load conditions for each speed.
00411   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
00412   * @param  GPIOx GPIO Port
00413   * @param  Pin This parameter can be one of the following values:
00414   *         @arg @ref LL_GPIO_PIN_0
00415   *         @arg @ref LL_GPIO_PIN_1
00416   *         @arg @ref LL_GPIO_PIN_2
00417   *         @arg @ref LL_GPIO_PIN_3
00418   *         @arg @ref LL_GPIO_PIN_4
00419   *         @arg @ref LL_GPIO_PIN_5
00420   *         @arg @ref LL_GPIO_PIN_6
00421   *         @arg @ref LL_GPIO_PIN_7
00422   *         @arg @ref LL_GPIO_PIN_8
00423   *         @arg @ref LL_GPIO_PIN_9
00424   *         @arg @ref LL_GPIO_PIN_10
00425   *         @arg @ref LL_GPIO_PIN_11
00426   *         @arg @ref LL_GPIO_PIN_12
00427   *         @arg @ref LL_GPIO_PIN_13
00428   *         @arg @ref LL_GPIO_PIN_14
00429   *         @arg @ref LL_GPIO_PIN_15
00430   * @param  Speed This parameter can be one of the following values:
00431   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00432   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00433   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00434   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
00435   * @retval None
00436   */
00437 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
00438 {
00439   MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
00440              (Speed << (POSITION_VAL(Pin) * 2U)));
00441 }
00442
00443 /**
00444   * @brief  Return gpio speed for a dedicated pin on dedicated port.
00445   * @note   I/O speed can be Low, Medium, Fast or High speed.
00446   * @note   Warning: only one pin can be passed as parameter.
00447   * @note   Refer to datasheet for frequency specifications and the power
00448   *         supply and load conditions for each speed.
00449   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
00450   * @param  GPIOx GPIO Port
00451   * @param  Pin This parameter can be one of the following values:
00452   *         @arg @ref LL_GPIO_PIN_0
00453   *         @arg @ref LL_GPIO_PIN_1
00454   *         @arg @ref LL_GPIO_PIN_2
00455   *         @arg @ref LL_GPIO_PIN_3
00456   *         @arg @ref LL_GPIO_PIN_4
00457   *         @arg @ref LL_GPIO_PIN_5
00458   *         @arg @ref LL_GPIO_PIN_6
00459   *         @arg @ref LL_GPIO_PIN_7
00460   *         @arg @ref LL_GPIO_PIN_8
00461   *         @arg @ref LL_GPIO_PIN_9
00462   *         @arg @ref LL_GPIO_PIN_10
00463   *         @arg @ref LL_GPIO_PIN_11
00464   *         @arg @ref LL_GPIO_PIN_12
00465   *         @arg @ref LL_GPIO_PIN_13
00466   *         @arg @ref LL_GPIO_PIN_14
00467   *         @arg @ref LL_GPIO_PIN_15
00468   * @retval Returned value can be one of the following values:
00469   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00470   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00471   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00472   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
00473   */
00474 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
00475 {
00476   return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
00477                              (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00478 }
00479
00480 /**
00481   * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
00482   * @note   Warning: only one pin can be passed as parameter.
00483   * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
00484   * @param  GPIOx GPIO Port
00485   * @param  Pin This parameter can be one of the following values:
00486   *         @arg @ref LL_GPIO_PIN_0
00487   *         @arg @ref LL_GPIO_PIN_1
00488   *         @arg @ref LL_GPIO_PIN_2
00489   *         @arg @ref LL_GPIO_PIN_3
00490   *         @arg @ref LL_GPIO_PIN_4
00491   *         @arg @ref LL_GPIO_PIN_5
00492   *         @arg @ref LL_GPIO_PIN_6
00493   *         @arg @ref LL_GPIO_PIN_7
00494   *         @arg @ref LL_GPIO_PIN_8
00495   *         @arg @ref LL_GPIO_PIN_9
00496   *         @arg @ref LL_GPIO_PIN_10
00497   *         @arg @ref LL_GPIO_PIN_11
00498   *         @arg @ref LL_GPIO_PIN_12
00499   *         @arg @ref LL_GPIO_PIN_13
00500   *         @arg @ref LL_GPIO_PIN_14
00501   *         @arg @ref LL_GPIO_PIN_15
00502   * @param  Pull This parameter can be one of the following values:
00503   *         @arg @ref LL_GPIO_PULL_NO
00504   *         @arg @ref LL_GPIO_PULL_UP
00505   *         @arg @ref LL_GPIO_PULL_DOWN
00506   * @retval None
00507   */
00508 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
00509 {
00510   MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
00511 }
00512
00513 /**
00514   * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
00515   * @note   Warning: only one pin can be passed as parameter.
00516   * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
00517   * @param  GPIOx GPIO Port
00518   * @param  Pin This parameter can be one of the following values:
00519   *         @arg @ref LL_GPIO_PIN_0
00520   *         @arg @ref LL_GPIO_PIN_1
00521   *         @arg @ref LL_GPIO_PIN_2
00522   *         @arg @ref LL_GPIO_PIN_3
00523   *         @arg @ref LL_GPIO_PIN_4
00524   *         @arg @ref LL_GPIO_PIN_5
00525   *         @arg @ref LL_GPIO_PIN_6
00526   *         @arg @ref LL_GPIO_PIN_7
00527   *         @arg @ref LL_GPIO_PIN_8
00528   *         @arg @ref LL_GPIO_PIN_9
00529   *         @arg @ref LL_GPIO_PIN_10
00530   *         @arg @ref LL_GPIO_PIN_11
00531   *         @arg @ref LL_GPIO_PIN_12
00532   *         @arg @ref LL_GPIO_PIN_13
00533   *         @arg @ref LL_GPIO_PIN_14
00534   *         @arg @ref LL_GPIO_PIN_15
00535   * @retval Returned value can be one of the following values:
00536   *         @arg @ref LL_GPIO_PULL_NO
00537   *         @arg @ref LL_GPIO_PULL_UP
00538   *         @arg @ref LL_GPIO_PULL_DOWN
00539   */
00540 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
00541 {
00542   return (uint32_t)(READ_BIT(GPIOx->PUPDR,
00543                              (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00544 }
00545
00546 /**
00547   * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00548   * @note   Possible values are from AF0 to AF15 depending on target.
00549   * @note   Warning: only one pin can be passed as parameter.
00550   * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
00551   * @param  GPIOx GPIO Port
00552   * @param  Pin This parameter can be one of the following values:
00553   *         @arg @ref LL_GPIO_PIN_0
00554   *         @arg @ref LL_GPIO_PIN_1
00555   *         @arg @ref LL_GPIO_PIN_2
00556   *         @arg @ref LL_GPIO_PIN_3
00557   *         @arg @ref LL_GPIO_PIN_4
00558   *         @arg @ref LL_GPIO_PIN_5
00559   *         @arg @ref LL_GPIO_PIN_6
00560   *         @arg @ref LL_GPIO_PIN_7
00561   * @param  Alternate This parameter can be one of the following values:
00562   *         @arg @ref LL_GPIO_AF_0
00563   *         @arg @ref LL_GPIO_AF_1
00564   *         @arg @ref LL_GPIO_AF_2
00565   *         @arg @ref LL_GPIO_AF_3
00566   *         @arg @ref LL_GPIO_AF_4
00567   *         @arg @ref LL_GPIO_AF_5
00568   *         @arg @ref LL_GPIO_AF_6
00569   *         @arg @ref LL_GPIO_AF_7
00570   *         @arg @ref LL_GPIO_AF_8
00571   *         @arg @ref LL_GPIO_AF_9
00572   *         @arg @ref LL_GPIO_AF_10
00573   *         @arg @ref LL_GPIO_AF_11
00574   *         @arg @ref LL_GPIO_AF_12
00575   *         @arg @ref LL_GPIO_AF_13
00576   *         @arg @ref LL_GPIO_AF_14
00577   *         @arg @ref LL_GPIO_AF_15
00578   * @retval None
00579   */
00580 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00581 {
00582   MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
00583              (Alternate << (POSITION_VAL(Pin) * 4U)));
00584 }
00585
00586 /**
00587   * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00588   * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
00589   * @param  GPIOx GPIO Port
00590   * @param  Pin This parameter can be one of the following values:
00591   *         @arg @ref LL_GPIO_PIN_0
00592   *         @arg @ref LL_GPIO_PIN_1
00593   *         @arg @ref LL_GPIO_PIN_2
00594   *         @arg @ref LL_GPIO_PIN_3
00595   *         @arg @ref LL_GPIO_PIN_4
00596   *         @arg @ref LL_GPIO_PIN_5
00597   *         @arg @ref LL_GPIO_PIN_6
00598   *         @arg @ref LL_GPIO_PIN_7
00599   * @retval Returned value can be one of the following values:
00600   *         @arg @ref LL_GPIO_AF_0
00601   *         @arg @ref LL_GPIO_AF_1
00602   *         @arg @ref LL_GPIO_AF_2
00603   *         @arg @ref LL_GPIO_AF_3
00604   *         @arg @ref LL_GPIO_AF_4
00605   *         @arg @ref LL_GPIO_AF_5
00606   *         @arg @ref LL_GPIO_AF_6
00607   *         @arg @ref LL_GPIO_AF_7
00608   *         @arg @ref LL_GPIO_AF_8
00609   *         @arg @ref LL_GPIO_AF_9
00610   *         @arg @ref LL_GPIO_AF_10
00611   *         @arg @ref LL_GPIO_AF_11
00612   *         @arg @ref LL_GPIO_AF_12
00613   *         @arg @ref LL_GPIO_AF_13
00614   *         @arg @ref LL_GPIO_AF_14
00615   *         @arg @ref LL_GPIO_AF_15
00616   */
00617 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
00618 {
00619   return (uint32_t)(READ_BIT(GPIOx->AFR[0],
00620                              (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
00621 }
00622
00623 /**
00624   * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00625   * @note   Possible values are from AF0 to AF15 depending on target.
00626   * @note   Warning: only one pin can be passed as parameter.
00627   * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
00628   * @param  GPIOx GPIO Port
00629   * @param  Pin This parameter can be one of the following values:
00630   *         @arg @ref LL_GPIO_PIN_8
00631   *         @arg @ref LL_GPIO_PIN_9
00632   *         @arg @ref LL_GPIO_PIN_10
00633   *         @arg @ref LL_GPIO_PIN_11
00634   *         @arg @ref LL_GPIO_PIN_12
00635   *         @arg @ref LL_GPIO_PIN_13
00636   *         @arg @ref LL_GPIO_PIN_14
00637   *         @arg @ref LL_GPIO_PIN_15
00638   * @param  Alternate This parameter can be one of the following values:
00639   *         @arg @ref LL_GPIO_AF_0
00640   *         @arg @ref LL_GPIO_AF_1
00641   *         @arg @ref LL_GPIO_AF_2
00642   *         @arg @ref LL_GPIO_AF_3
00643   *         @arg @ref LL_GPIO_AF_4
00644   *         @arg @ref LL_GPIO_AF_5
00645   *         @arg @ref LL_GPIO_AF_6
00646   *         @arg @ref LL_GPIO_AF_7
00647   *         @arg @ref LL_GPIO_AF_8
00648   *         @arg @ref LL_GPIO_AF_9
00649   *         @arg @ref LL_GPIO_AF_10
00650   *         @arg @ref LL_GPIO_AF_11
00651   *         @arg @ref LL_GPIO_AF_12
00652   *         @arg @ref LL_GPIO_AF_13
00653   *         @arg @ref LL_GPIO_AF_14
00654   *         @arg @ref LL_GPIO_AF_15
00655   * @retval None
00656   */
00657 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00658 {
00659   MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
00660              (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
00661 }
00662
00663 /**
00664   * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00665   * @note   Possible values are from AF0 to AF15 depending on target.
00666   * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
00667   * @param  GPIOx GPIO Port
00668   * @param  Pin This parameter can be one of the following values:
00669   *         @arg @ref LL_GPIO_PIN_8
00670   *         @arg @ref LL_GPIO_PIN_9
00671   *         @arg @ref LL_GPIO_PIN_10
00672   *         @arg @ref LL_GPIO_PIN_11
00673   *         @arg @ref LL_GPIO_PIN_12
00674   *         @arg @ref LL_GPIO_PIN_13
00675   *         @arg @ref LL_GPIO_PIN_14
00676   *         @arg @ref LL_GPIO_PIN_15
00677   * @retval Returned value can be one of the following values:
00678   *         @arg @ref LL_GPIO_AF_0
00679   *         @arg @ref LL_GPIO_AF_1
00680   *         @arg @ref LL_GPIO_AF_2
00681   *         @arg @ref LL_GPIO_AF_3
00682   *         @arg @ref LL_GPIO_AF_4
00683   *         @arg @ref LL_GPIO_AF_5
00684   *         @arg @ref LL_GPIO_AF_6
00685   *         @arg @ref LL_GPIO_AF_7
00686   *         @arg @ref LL_GPIO_AF_8
00687   *         @arg @ref LL_GPIO_AF_9
00688   *         @arg @ref LL_GPIO_AF_10
00689   *         @arg @ref LL_GPIO_AF_11
00690   *         @arg @ref LL_GPIO_AF_12
00691   *         @arg @ref LL_GPIO_AF_13
00692   *         @arg @ref LL_GPIO_AF_14
00693   *         @arg @ref LL_GPIO_AF_15
00694   */
00695 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
00696 {
00697   return (uint32_t)(READ_BIT(GPIOx->AFR[1],
00698                              (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
00699 }
00700
00701 #if defined(GPIO_ASCR_ASC0)
00702 /**
00703   * @brief  Connect analog switch to ADC input of several pins for a dedicated port.
00704   * @note   This bit must be set prior to the ADC conversion.
00705   *         Only the IO which connected to the ADC input are effective.
00706   *         Other IO must be kept reset value
00707   * @rmtoll ASCR         ASCy          LL_GPIO_EnablePinAnalogControl
00708   * @param  GPIOx GPIO Port
00709   * @param  PinMask This parameter can be a combination of the following values:
00710   *         @arg @ref LL_GPIO_PIN_0
00711   *         @arg @ref LL_GPIO_PIN_1
00712   *         @arg @ref LL_GPIO_PIN_2
00713   *         @arg @ref LL_GPIO_PIN_3
00714   *         @arg @ref LL_GPIO_PIN_4
00715   *         @arg @ref LL_GPIO_PIN_5
00716   *         @arg @ref LL_GPIO_PIN_6
00717   *         @arg @ref LL_GPIO_PIN_7
00718   *         @arg @ref LL_GPIO_PIN_8
00719   *         @arg @ref LL_GPIO_PIN_9
00720   *         @arg @ref LL_GPIO_PIN_10
00721   *         @arg @ref LL_GPIO_PIN_11
00722   *         @arg @ref LL_GPIO_PIN_12
00723   *         @arg @ref LL_GPIO_PIN_13
00724   *         @arg @ref LL_GPIO_PIN_14
00725   *         @arg @ref LL_GPIO_PIN_15
00726   *         @arg @ref LL_GPIO_PIN_ALL
00727   * @retval None
00728   */
00729 __STATIC_INLINE void LL_GPIO_EnablePinAnalogControl(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00730 {
00731   SET_BIT(GPIOx->ASCR, PinMask);
00732 }
00733
00734 /**
00735   * @brief  Disconnect analog switch to ADC input of several pins for a dedicated port.
00736   * @rmtoll ASCR         ASCy          LL_GPIO_DisablePinAnalogControl
00737   * @param  GPIOx GPIO Port
00738   * @param  PinMask This parameter can be a combination of the following values:
00739   *         @arg @ref LL_GPIO_PIN_0
00740   *         @arg @ref LL_GPIO_PIN_1
00741   *         @arg @ref LL_GPIO_PIN_2
00742   *         @arg @ref LL_GPIO_PIN_3
00743   *         @arg @ref LL_GPIO_PIN_4
00744   *         @arg @ref LL_GPIO_PIN_5
00745   *         @arg @ref LL_GPIO_PIN_6
00746   *         @arg @ref LL_GPIO_PIN_7
00747   *         @arg @ref LL_GPIO_PIN_8
00748   *         @arg @ref LL_GPIO_PIN_9
00749   *         @arg @ref LL_GPIO_PIN_10
00750   *         @arg @ref LL_GPIO_PIN_11
00751   *         @arg @ref LL_GPIO_PIN_12
00752   *         @arg @ref LL_GPIO_PIN_13
00753   *         @arg @ref LL_GPIO_PIN_14
00754   *         @arg @ref LL_GPIO_PIN_15
00755   *         @arg @ref LL_GPIO_PIN_ALL
00756   * @retval None
00757   */
00758 __STATIC_INLINE void LL_GPIO_DisablePinAnalogControl(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00759 {
00760   CLEAR_BIT(GPIOx->ASCR, PinMask);
00761 }
00762 #endif /* GPIO_ASCR_ASC0 */
00763
00764 /**
00765   * @brief  Lock configuration of several pins for a dedicated port.
00766   * @note   When the lock sequence has been applied on a port bit, the
00767   *         value of this port bit can no longer be modified until the
00768   *         next reset.
00769   * @note   Each lock bit freezes a specific configuration register
00770   *         (control and alternate function registers).
00771   * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
00772   * @param  GPIOx GPIO Port
00773   * @param  PinMask This parameter can be a combination of the following values:
00774   *         @arg @ref LL_GPIO_PIN_0
00775   *         @arg @ref LL_GPIO_PIN_1
00776   *         @arg @ref LL_GPIO_PIN_2
00777   *         @arg @ref LL_GPIO_PIN_3
00778   *         @arg @ref LL_GPIO_PIN_4
00779   *         @arg @ref LL_GPIO_PIN_5
00780   *         @arg @ref LL_GPIO_PIN_6
00781   *         @arg @ref LL_GPIO_PIN_7
00782   *         @arg @ref LL_GPIO_PIN_8
00783   *         @arg @ref LL_GPIO_PIN_9
00784   *         @arg @ref LL_GPIO_PIN_10
00785   *         @arg @ref LL_GPIO_PIN_11
00786   *         @arg @ref LL_GPIO_PIN_12
00787   *         @arg @ref LL_GPIO_PIN_13
00788   *         @arg @ref LL_GPIO_PIN_14
00789   *         @arg @ref LL_GPIO_PIN_15
00790   *         @arg @ref LL_GPIO_PIN_ALL
00791   * @retval None
00792   */
00793 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00794 {
00795   __IO uint32_t temp;
00796   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00797   WRITE_REG(GPIOx->LCKR, PinMask);
00798   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00799   temp = READ_REG(GPIOx->LCKR);
00800   (void) temp;
00801 }
00802
00803 /**
00804   * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
00805   * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
00806   * @param  GPIOx GPIO Port
00807   * @param  PinMask This parameter can be a combination of the following values:
00808   *         @arg @ref LL_GPIO_PIN_0
00809   *         @arg @ref LL_GPIO_PIN_1
00810   *         @arg @ref LL_GPIO_PIN_2
00811   *         @arg @ref LL_GPIO_PIN_3
00812   *         @arg @ref LL_GPIO_PIN_4
00813   *         @arg @ref LL_GPIO_PIN_5
00814   *         @arg @ref LL_GPIO_PIN_6
00815   *         @arg @ref LL_GPIO_PIN_7
00816   *         @arg @ref LL_GPIO_PIN_8
00817   *         @arg @ref LL_GPIO_PIN_9
00818   *         @arg @ref LL_GPIO_PIN_10
00819   *         @arg @ref LL_GPIO_PIN_11
00820   *         @arg @ref LL_GPIO_PIN_12
00821   *         @arg @ref LL_GPIO_PIN_13
00822   *         @arg @ref LL_GPIO_PIN_14
00823   *         @arg @ref LL_GPIO_PIN_15
00824   *         @arg @ref LL_GPIO_PIN_ALL
00825   * @retval State of bit (1 or 0).
00826   */
00827 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00828 {
00829   return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
00830 }
00831
00832 /**
00833   * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
00834   * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
00835   * @param  GPIOx GPIO Port
00836   * @retval State of bit (1 or 0).
00837   */
00838 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
00839 {
00840   return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
00841 }
00842
00843 /**
00844   * @}
00845   */
00846
00847 /** @defgroup GPIO_LL_EF_Data_Access Data Access
00848   * @{
00849   */
00850
00851 /**
00852   * @brief  Return full input data register value for a dedicated port.
00853   * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
00854   * @param  GPIOx GPIO Port
00855   * @retval Input data register value of port
00856   */
00857 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
00858 {
00859   return (uint32_t)(READ_REG(GPIOx->IDR));
00860 }
00861
00862 /**
00863   * @brief  Return if input data level for several pins of dedicated port is high or low.
00864   * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
00865   * @param  GPIOx GPIO Port
00866   * @param  PinMask This parameter can be a combination of the following values:
00867   *         @arg @ref LL_GPIO_PIN_0
00868   *         @arg @ref LL_GPIO_PIN_1
00869   *         @arg @ref LL_GPIO_PIN_2
00870   *         @arg @ref LL_GPIO_PIN_3
00871   *         @arg @ref LL_GPIO_PIN_4
00872   *         @arg @ref LL_GPIO_PIN_5
00873   *         @arg @ref LL_GPIO_PIN_6
00874   *         @arg @ref LL_GPIO_PIN_7
00875   *         @arg @ref LL_GPIO_PIN_8
00876   *         @arg @ref LL_GPIO_PIN_9
00877   *         @arg @ref LL_GPIO_PIN_10
00878   *         @arg @ref LL_GPIO_PIN_11
00879   *         @arg @ref LL_GPIO_PIN_12
00880   *         @arg @ref LL_GPIO_PIN_13
00881   *         @arg @ref LL_GPIO_PIN_14
00882   *         @arg @ref LL_GPIO_PIN_15
00883   *         @arg @ref LL_GPIO_PIN_ALL
00884   * @retval State of bit (1 or 0).
00885   */
00886 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00887 {
00888   return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
00889 }
00890
00891 /**
00892   * @brief  Write output data register for the port.
00893   * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
00894   * @param  GPIOx GPIO Port
00895   * @param  PortValue Level value for each pin of the port
00896   * @retval None
00897   */
00898 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
00899 {
00900   WRITE_REG(GPIOx->ODR, PortValue);
00901 }
00902
00903 /**
00904   * @brief  Return full output data register value for a dedicated port.
00905   * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
00906   * @param  GPIOx GPIO Port
00907   * @retval Output data register value of port
00908   */
00909 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
00910 {
00911   return (uint32_t)(READ_REG(GPIOx->ODR));
00912 }
00913
00914 /**
00915   * @brief  Return if input data level for several pins of dedicated port is high or low.
00916   * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
00917   * @param  GPIOx GPIO Port
00918   * @param  PinMask This parameter can be a combination of the following values:
00919   *         @arg @ref LL_GPIO_PIN_0
00920   *         @arg @ref LL_GPIO_PIN_1
00921   *         @arg @ref LL_GPIO_PIN_2
00922   *         @arg @ref LL_GPIO_PIN_3
00923   *         @arg @ref LL_GPIO_PIN_4
00924   *         @arg @ref LL_GPIO_PIN_5
00925   *         @arg @ref LL_GPIO_PIN_6
00926   *         @arg @ref LL_GPIO_PIN_7
00927   *         @arg @ref LL_GPIO_PIN_8
00928   *         @arg @ref LL_GPIO_PIN_9
00929   *         @arg @ref LL_GPIO_PIN_10
00930   *         @arg @ref LL_GPIO_PIN_11
00931   *         @arg @ref LL_GPIO_PIN_12
00932   *         @arg @ref LL_GPIO_PIN_13
00933   *         @arg @ref LL_GPIO_PIN_14
00934   *         @arg @ref LL_GPIO_PIN_15
00935   *         @arg @ref LL_GPIO_PIN_ALL
00936   * @retval State of bit (1 or 0).
00937   */
00938 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00939 {
00940   return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
00941 }
00942
00943 /**
00944   * @brief  Set several pins to high level on dedicated gpio port.
00945   * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
00946   * @param  GPIOx GPIO Port
00947   * @param  PinMask This parameter can be a combination of the following values:
00948   *         @arg @ref LL_GPIO_PIN_0
00949   *         @arg @ref LL_GPIO_PIN_1
00950   *         @arg @ref LL_GPIO_PIN_2
00951   *         @arg @ref LL_GPIO_PIN_3
00952   *         @arg @ref LL_GPIO_PIN_4
00953   *         @arg @ref LL_GPIO_PIN_5
00954   *         @arg @ref LL_GPIO_PIN_6
00955   *         @arg @ref LL_GPIO_PIN_7
00956   *         @arg @ref LL_GPIO_PIN_8
00957   *         @arg @ref LL_GPIO_PIN_9
00958   *         @arg @ref LL_GPIO_PIN_10
00959   *         @arg @ref LL_GPIO_PIN_11
00960   *         @arg @ref LL_GPIO_PIN_12
00961   *         @arg @ref LL_GPIO_PIN_13
00962   *         @arg @ref LL_GPIO_PIN_14
00963   *         @arg @ref LL_GPIO_PIN_15
00964   *         @arg @ref LL_GPIO_PIN_ALL
00965   * @retval None
00966   */
00967 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00968 {
00969   WRITE_REG(GPIOx->BSRR, PinMask);
00970 }
00971
00972 /**
00973   * @brief  Set several pins to low level on dedicated gpio port.
00974   * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
00975   * @param  GPIOx GPIO Port
00976   * @param  PinMask This parameter can be a combination of the following values:
00977   *         @arg @ref LL_GPIO_PIN_0
00978   *         @arg @ref LL_GPIO_PIN_1
00979   *         @arg @ref LL_GPIO_PIN_2
00980   *         @arg @ref LL_GPIO_PIN_3
00981   *         @arg @ref LL_GPIO_PIN_4
00982   *         @arg @ref LL_GPIO_PIN_5
00983   *         @arg @ref LL_GPIO_PIN_6
00984   *         @arg @ref LL_GPIO_PIN_7
00985   *         @arg @ref LL_GPIO_PIN_8
00986   *         @arg @ref LL_GPIO_PIN_9
00987   *         @arg @ref LL_GPIO_PIN_10
00988   *         @arg @ref LL_GPIO_PIN_11
00989   *         @arg @ref LL_GPIO_PIN_12
00990   *         @arg @ref LL_GPIO_PIN_13
00991   *         @arg @ref LL_GPIO_PIN_14
00992   *         @arg @ref LL_GPIO_PIN_15
00993   *         @arg @ref LL_GPIO_PIN_ALL
00994   * @retval None
00995   */
00996 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00997 {
00998   WRITE_REG(GPIOx->BRR, PinMask);
00999 }
01000
01001 /**
01002   * @brief  Toggle data value for several pin of dedicated port.
01003   * @rmtoll ODR          ODy           LL_GPIO_TogglePin
01004   * @param  GPIOx GPIO Port
01005   * @param  PinMask This parameter can be a combination of the following values:
01006   *         @arg @ref LL_GPIO_PIN_0
01007   *         @arg @ref LL_GPIO_PIN_1
01008   *         @arg @ref LL_GPIO_PIN_2
01009   *         @arg @ref LL_GPIO_PIN_3
01010   *         @arg @ref LL_GPIO_PIN_4
01011   *         @arg @ref LL_GPIO_PIN_5
01012   *         @arg @ref LL_GPIO_PIN_6
01013   *         @arg @ref LL_GPIO_PIN_7
01014   *         @arg @ref LL_GPIO_PIN_8
01015   *         @arg @ref LL_GPIO_PIN_9
01016   *         @arg @ref LL_GPIO_PIN_10
01017   *         @arg @ref LL_GPIO_PIN_11
01018   *         @arg @ref LL_GPIO_PIN_12
01019   *         @arg @ref LL_GPIO_PIN_13
01020   *         @arg @ref LL_GPIO_PIN_14
01021   *         @arg @ref LL_GPIO_PIN_15
01022   *         @arg @ref LL_GPIO_PIN_ALL
01023   * @retval None
01024   */
01025 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
01026 {
01027   WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
01028 }
01029
01030 /**
01031   * @}
01032   */
01033
01034 #if defined(USE_FULL_LL_DRIVER)
01035 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
01036   * @{
01037   */
01038
01039 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
01040 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
01041 void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
01042
01043 /**
01044   * @}
01045   */
01046 #endif /* USE_FULL_LL_DRIVER */
01047
01048 /**
01049   * @}
01050   */
01051
01052 /**
01053   * @}
01054   */
01055
01056 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */
01057 /**
01058   * @}
01059   */
01060
01061 #ifdef __cplusplus
01062 }
01063 #endif
01064
01065 #endif /* __STM32L4xx_LL_GPIO_H */
01066
01067 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_i2c.c Source File

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stm32l4xx_ll_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_i2c.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   I2C LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_i2c.h"
00041 #include "stm32l4xx_ll_bus.h"
00042 #ifdef  USE_FULL_ASSERT
00043 #include "stm32_assert.h"
00044 #else
00045 #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32L4xx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
00053
00054 /** @defgroup I2C_LL I2C
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062 /** @addtogroup I2C_LL_Private_Macros
00063   * @{
00064   */
00065
00066 #define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
00067                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
00068                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
00069                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
00070
00071 #define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
00072                                                  ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
00073
00074 #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
00075
00076 #define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= (uint32_t)0x000003FFU)
00077
00078 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
00079                                                  ((__VALUE__) == LL_I2C_NACK))
00080
00081 #define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
00082                                                  ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
00083 /**
00084   * @}
00085   */
00086
00087 /* Private function prototypes -----------------------------------------------*/
00088
00089 /* Exported functions --------------------------------------------------------*/
00090 /** @addtogroup I2C_LL_Exported_Functions
00091   * @{
00092   */
00093
00094 /** @addtogroup I2C_LL_EF_Init
00095   * @{
00096   */
00097
00098 /**
00099   * @brief  De-initialize the I2C registers to their default reset values.
00100   * @param  I2Cx I2C Instance.
00101   * @retval An ErrorStatus enumeration value:
00102   *          - SUCCESS: I2C registers are de-initialized
00103   *          - ERROR: I2C registers are not de-initialized
00104   */
00105 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
00106 {
00107   ErrorStatus status = SUCCESS;
00108
00109   /* Check the I2C Instance I2Cx */
00110   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00111
00112   if (I2Cx == I2C1)
00113   {
00114     /* Force reset of I2C clock */
00115     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
00116
00117     /* Release reset of I2C clock */
00118     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
00119   }
00120 #if defined(I2C2)
00121   else if (I2Cx == I2C2)
00122   {
00123     /* Force reset of I2C clock */
00124     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
00125
00126     /* Release reset of I2C clock */
00127     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
00128
00129   }
00130 #endif
00131   else if (I2Cx == I2C3)
00132   {
00133     /* Force reset of I2C clock */
00134     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
00135
00136     /* Release reset of I2C clock */
00137     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
00138   }
00139   else
00140   {
00141     status = ERROR;
00142   }
00143
00144   return status;
00145 }
00146
00147 /**
00148   * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
00149   * @param  I2Cx I2C Instance.
00150   * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
00151   * @retval An ErrorStatus enumeration value:
00152   *          - SUCCESS: I2C registers are initialized
00153   *          - ERROR: Not applicable
00154   */
00155 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
00156 {
00157   /* Check the I2C Instance I2Cx */
00158   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00159
00160   /* Check the I2C parameters from I2C_InitStruct */
00161   assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
00162   assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
00163   assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
00164   assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
00165   assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
00166   assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
00167
00168   /* Disable the selected I2Cx Peripheral */
00169   LL_I2C_Disable(I2Cx);
00170
00171   /*---------------------------- I2Cx CR1 Configuration ------------------------
00172    * Configure the analog and digital noise filters with parameters :
00173    * - AnalogFilter: I2C_CR1_ANFOFF bit
00174    * - DigitalFilter: I2C_CR1_DNF[3:0] bits
00175    */
00176   LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
00177
00178   /*---------------------------- I2Cx TIMINGR Configuration --------------------
00179    * Configure the SDA setup, hold time and the SCL high, low period with parameter :
00180    * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
00181    *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
00182    */
00183   LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
00184
00185   /* Enable the selected I2Cx Peripheral */
00186   LL_I2C_Enable(I2Cx);
00187
00188   /*---------------------------- I2Cx OAR1 Configuration -----------------------
00189    * Disable, Configure and Enable I2Cx device own address 1 with parameters :
00190    * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
00191    * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
00192    */
00193   LL_I2C_DisableOwnAddress1(I2Cx);
00194   LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
00195   LL_I2C_EnableOwnAddress1(I2Cx);
00196
00197   /*---------------------------- I2Cx MODE Configuration -----------------------
00198   * Configure I2Cx peripheral mode with parameter :
00199    * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
00200    */
00201   LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
00202
00203   /*---------------------------- I2Cx CR2 Configuration ------------------------
00204    * Configure the ACKnowledge or Non ACKnowledge condition
00205    * after the address receive match code or next received byte with parameter :
00206    * - TypeAcknowledge: I2C_CR2_NACK bit
00207    */
00208   LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
00209
00210   return SUCCESS;
00211 }
00212
00213 /**
00214   * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
00215   * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
00216   * @retval None
00217   */
00218 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
00219 {
00220   /* Set I2C_InitStruct fields to default values */
00221   I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
00222   I2C_InitStruct->Timing          = 0U;
00223   I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
00224   I2C_InitStruct->DigitalFilter   = 0U;
00225   I2C_InitStruct->OwnAddress1     = 0U;
00226   I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
00227   I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
00228 }
00229
00230 /**
00231   * @}
00232   */
00233
00234 /**
00235   * @}
00236   */
00237
00238 /**
00239   * @}
00240   */
00241
00242 #endif /* I2C1 || I2C2 || I2C3 */
00243
00244 /**
00245   * @}
00246   */
00247
00248 #endif /* USE_FULL_LL_DRIVER */
00249
00250 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:14 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_i2c.h Source File

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stm32l4xx_ll_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_i2c.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of I2C LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_I2C_H
00040 #define __STM32L4xx_LL_I2C_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
00054
00055 /** @defgroup I2C_LL I2C
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
00064   * @{
00065   */
00066 /* Defines used for the bit position in the register and perform offsets */
00067 #define I2C_POSITION_CR1_DNF            (uint32_t)POSITION_VAL(I2C_CR1_DNF)
00068 #define I2C_POSITION_CR2_NBYTES         (uint32_t)POSITION_VAL(I2C_CR2_NBYTES)
00069 #define I2C_POSITION_TIMINGR_PRESC      (uint32_t)POSITION_VAL(I2C_TIMINGR_PRESC)
00070 #define I2C_POSITION_TIMINGR_SCLDEL     (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLDEL)
00071 #define I2C_POSITION_TIMINGR_SDADEL     (uint32_t)POSITION_VAL(I2C_TIMINGR_SDADEL)
00072 #define I2C_POSITION_TIMINGR_SCLH       (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLH)
00073 #define I2C_POSITION_TIMINGR_SCLL       (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLL)
00074 #define I2C_POSITION_ISR_ADDCODE        (uint32_t)POSITION_VAL(I2C_ISR_ADDCODE)
00075 #define I2C_POSITION_TIMEOUTR_TIMEOUTB  (uint32_t)POSITION_VAL(I2C_TIMEOUTR_TIMEOUTB)
00076 /**
00077   * @}
00078   */
00079
00080 /* Private macros ------------------------------------------------------------*/
00081 #if defined(USE_FULL_LL_DRIVER)
00082 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
00083   * @{
00084   */
00085 /**
00086   * @}
00087   */
00088 #endif /*USE_FULL_LL_DRIVER*/
00089
00090 /* Exported types ------------------------------------------------------------*/
00091 #if defined(USE_FULL_LL_DRIVER)
00092 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
00093   * @{
00094   */
00095 typedef struct
00096 {
00097   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
00098                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
00099
00100                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
00101
00102   uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
00103                                      This parameter must be set by referring to the STM32CubeMX Tool and
00104                                      the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
00105
00106                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
00107
00108   uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
00109                                      This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
00110
00111                                      This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
00112
00113   uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
00114                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
00115
00116                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
00117
00118   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
00119                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
00120
00121                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00122
00123   uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
00124                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
00125
00126                                      This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
00127
00128   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
00129                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
00130
00131                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00132 } LL_I2C_InitTypeDef;
00133 /**
00134   * @}
00135   */
00136 #endif /*USE_FULL_LL_DRIVER*/
00137
00138 /* Exported constants --------------------------------------------------------*/
00139 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
00140   * @{
00141   */
00142
00143 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
00144   * @brief    Flags defines which can be used with LL_I2C_WriteReg function
00145   * @{
00146   */
00147 #define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
00148 #define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
00149 #define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
00150 #define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
00151 #define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
00152 #define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
00153 #define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
00154 #define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
00155 #define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
00161   * @brief    Flags defines which can be used with LL_I2C_ReadReg function
00162   * @{
00163   */
00164 #define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
00165 #define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
00166 #define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
00167 #define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
00168 #define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
00169 #define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
00170 #define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
00171 #define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
00172 #define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
00173 #define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
00174 #define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
00175 #define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
00176 #define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
00177 #define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
00178 #define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup I2C_LL_EC_IT IT Defines
00184   * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
00185   * @{
00186   */
00187 #define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
00188 #define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
00189 #define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
00190 #define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
00191 #define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
00192 #define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
00193 #define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
00199   * @{
00200   */
00201 #define LL_I2C_MODE_I2C                    ((uint32_t)0x00000000U)  /*!< I2C Master or Slave mode                                    */
00202 #define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge                              */
00203 #define LL_I2C_MODE_SMBUS_DEVICE           ((uint32_t)0x00000000U)  /*!< SMBus Device default mode (Default address not acknowledge) */
00204 #define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge                    */
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
00210   * @{
00211   */
00212 #define LL_I2C_ANALOGFILTER_ENABLE          ((uint32_t)0x00000000U) /*!< Analog filter is enabled.  */
00213 #define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
00219   * @{
00220   */
00221 #define LL_I2C_ADDRESSING_MODE_7BIT         ((uint32_t) 0x00000000U) /*!< Master operates in 7-bit addressing mode. */
00222 #define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
00228   * @{
00229   */
00230 #define LL_I2C_OWNADDRESS1_7BIT             ((uint32_t)0x00000000U) /*!< Own address 1 is a 7-bit address. */
00231 #define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
00237   * @{
00238   */
00239 #define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                                */
00240 #define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared.                */
00241 #define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared.                */
00242 #define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared.                */
00243 #define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared.                */
00244 #define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared.                */
00245 #define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.                  */
00246 #define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done. All Address2 are acknowledged.*/
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
00252   * @{
00253   */
00254 #define LL_I2C_ACK                          ((uint32_t) 0x00000000U) /*!< ACK is sent after current received byte. */
00255 #define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
00261   * @{
00262   */
00263 #define LL_I2C_ADDRSLAVE_7BIT               ((uint32_t)0x00000000U)  /*!< Slave Address in 7-bit. */
00264 #define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
00270   * @{
00271   */
00272 #define LL_I2C_REQUEST_WRITE                ((uint32_t)0x00000000U)  /*!< Master request a write transfer. */
00273 #define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
00279   * @{
00280   */
00281 #define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD                                      /*!< Enable I2C Reload mode.                                   */
00282 #define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND                                     /*!< Enable I2C Automatic end mode with no HW PEC comparison.  */
00283 #define LL_I2C_MODE_SOFTEND                 ((uint32_t)0x00000000U)                             /*!< Enable I2C Software end mode with no HW PEC comparison.   */
00284 #define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD                                  /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00285 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND                                 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00286 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND                                 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00287 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00288 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
00294   * @{
00295   */
00296 #define LL_I2C_GENERATE_NOSTARTSTOP         ((uint32_t)0x00000000U)                                      /*!< Don't Generate Stop and Start condition.                */
00297 #define LL_I2C_GENERATE_STOP                I2C_CR2_STOP                                                 /*!< Generate Stop condition (Size should be set to 0).      */
00298 #define LL_I2C_GENERATE_START_READ          (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Start for read request.                        */
00299 #define LL_I2C_GENERATE_START_WRITE         I2C_CR2_START                                                /*!< Generate Start for write request.                       */
00300 #define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Restart for read request, slave 7Bit address.  */
00301 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE  I2C_CR2_START                                                /*!< Generate Restart for write request, slave 7Bit address. */
00302 #define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
00303 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START                                                /*!< Generate Restart for write request, slave 10Bit address.*/
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
00309   * @{
00310   */
00311 #define LL_I2C_DIRECTION_WRITE              ((uint32_t)0x00000000U)  /*!< Write transfer request by master, slave enters receiver mode.  */
00312 #define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master, slave enters transmitter mode.*/
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
00318   * @{
00319   */
00320 #define LL_I2C_DMA_REG_DATA_TRANSMIT        ((uint32_t)0x00000000U)  /*!< Get address of data register used for transmission */
00321 #define LL_I2C_DMA_REG_DATA_RECEIVE         ((uint32_t)0x00000001U)  /*!< Get address of data register used for reception */
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
00327   * @{
00328   */
00329 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW  ((uint32_t) 0x00000000U) /*!< TimeoutA is used to detect SCL low level timeout.              */
00330 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
00336   * @{
00337   */
00338 #define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                                   /*!< TimeoutA enable bit                                */
00339 #define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                                     /*!< TimeoutB (extended clock) enable bit               */
00340 #define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
00341 /**
00342   * @}
00343   */
00344
00345 /**
00346   * @}
00347   */
00348
00349 /* Exported macro ------------------------------------------------------------*/
00350 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
00351   * @{
00352   */
00353
00354 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
00355   * @{
00356   */
00357
00358 /**
00359   * @brief  Write a value in I2C register
00360   * @param  __INSTANCE__ I2C Instance
00361   * @param  __REG__ Register to be written
00362   * @param  __VALUE__ Value to be written in the register
00363   * @retval None
00364   */
00365 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00366
00367 /**
00368   * @brief  Read a value in I2C register
00369   * @param  __INSTANCE__ I2C Instance
00370   * @param  __REG__ Register to be read
00371   * @retval Register value
00372   */
00373 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00374 /**
00375   * @}
00376   */
00377
00378 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
00379   * @{
00380   */
00381 /**
00382   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00383   * @param  __PRESCALER__ This parameter must be a value between  0 and 0xF.
00384   * @param  __DATA_SETUP_TIME__ This parameter must be a value between 0 and 0xF. (tscldel = (SCLDEL+1)xtpresc)
00385   * @param  __DATA_HOLD_TIME__ This parameter must be a value between 0 and 0xF. (tsdadel = SDADELxtpresc)
00386   * @param  __CLOCK_HIGH_PERIOD__ This parameter must be a value between 0 and 0xFF. (tsclh = (SCLH+1)xtpresc)
00387   * @param  __CLOCK_LOW_PERIOD__ This parameter must be a value between  0 and 0xFF. (tscll = (SCLL+1)xtpresc)
00388   * @retval Value between 0 and 0xFFFFFFFF
00389   */
00390 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)   \
00391         ((((uint32_t)(__PRESCALER__)         << I2C_POSITION_TIMINGR_PRESC)  & I2C_TIMINGR_PRESC)   | \
00392          (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL)  | \
00393          (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL)  | \
00394          (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH)   & I2C_TIMINGR_SCLH)    | \
00395          (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_POSITION_TIMINGR_SCLL)   & I2C_TIMINGR_SCLL))
00396 /**
00397   * @}
00398   */
00399
00400 /**
00401   * @}
00402   */
00403
00404 /* Exported functions --------------------------------------------------------*/
00405 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
00406   * @{
00407   */
00408
00409 /** @defgroup I2C_LL_EF_Configuration Configuration
00410   * @{
00411   */
00412
00413 /**
00414   * @brief  Enable I2C peripheral (PE = 1).
00415   * @rmtoll CR1          PE            LL_I2C_Enable
00416   * @param  I2Cx I2C Instance.
00417   * @retval None
00418   */
00419 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
00420 {
00421   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
00422 }
00423
00424 /**
00425   * @brief  Disable I2C peripheral (PE = 0).
00426   * @note   When PE = 0, the I2C SCL and SDA lines are released.
00427   *         Internal state machines and status bits are put back to their reset value.
00428   *         When cleared, PE must be kept low for at least 3 APB clock cycles.
00429   * @rmtoll CR1          PE            LL_I2C_Disable
00430   * @param  I2Cx I2C Instance.
00431   * @retval None
00432   */
00433 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
00434 {
00435   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
00436 }
00437
00438 /**
00439   * @brief  Check if the I2C peripheral is enabled or disabled.
00440   * @rmtoll CR1          PE            LL_I2C_IsEnabled
00441   * @param  I2Cx I2C Instance.
00442   * @retval State of bit (1 or 0).
00443   */
00444 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
00445 {
00446   return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
00447 }
00448
00449 /**
00450   * @brief  Configure Noise Filters (Analog and Digital).
00451   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00452   *         The filters can only be programmed when the I2C is disabled (PE = 0).
00453   * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
00454   *         CR1          DNF           LL_I2C_ConfigFilters
00455   * @param  I2Cx I2C Instance.
00456   * @param  AnalogFilter This parameter can be one of the following values:
00457   *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
00458   *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
00459   * @param  DigitalFilter This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00460   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00461   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00462   * @retval None
00463   */
00464 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
00465 {
00466   MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_POSITION_CR1_DNF));
00467 }
00468
00469 /**
00470   * @brief  Configure Digital Noise Filter.
00471   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00472   *         This filter can only be programmed when the I2C is disabled (PE = 0).
00473   * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
00474   * @param  I2Cx I2C Instance.
00475   * @param  DigitalFilter This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00476   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00477   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00478   * @retval None
00479   */
00480 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
00481 {
00482   MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_POSITION_CR1_DNF);
00483 }
00484
00485 /**
00486   * @brief  Get the current Digital Noise Filter configuration.
00487   * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
00488   * @param  I2Cx I2C Instance.
00489   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00490   */
00491 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
00492 {
00493   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_POSITION_CR1_DNF);
00494 }
00495
00496 /**
00497   * @brief  Enable Analog Noise Filter.
00498   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00499   * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
00500   * @param  I2Cx I2C Instance.
00501   * @retval None
00502   */
00503 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
00504 {
00505   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00506 }
00507
00508 /**
00509   * @brief  Disable Analog Noise Filter.
00510   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00511   * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
00512   * @param  I2Cx I2C Instance.
00513   * @retval None
00514   */
00515 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
00516 {
00517   SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00518 }
00519
00520 /**
00521   * @brief  Check if Analog Noise Filter is enabled or disabled.
00522   * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
00523   * @param  I2Cx I2C Instance.
00524   * @retval State of bit (1 or 0).
00525   */
00526 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
00527 {
00528   return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
00529 }
00530
00531 /**
00532   * @brief  Enable DMA transmission requests.
00533   * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
00534   * @param  I2Cx I2C Instance.
00535   * @retval None
00536   */
00537 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
00538 {
00539   SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00540 }
00541
00542 /**
00543   * @brief  Disable DMA transmission requests.
00544   * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
00545   * @param  I2Cx I2C Instance.
00546   * @retval None
00547   */
00548 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
00549 {
00550   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00551 }
00552
00553 /**
00554   * @brief  Check if DMA transmission requests are enabled or disabled.
00555   * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
00556   * @param  I2Cx I2C Instance.
00557   * @retval State of bit (1 or 0).
00558   */
00559 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
00560 {
00561   return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
00562 }
00563
00564 /**
00565   * @brief  Enable DMA reception requests.
00566   * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
00567   * @param  I2Cx I2C Instance.
00568   * @retval None
00569   */
00570 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
00571 {
00572   SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00573 }
00574
00575 /**
00576   * @brief  Disable DMA reception requests.
00577   * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
00578   * @param  I2Cx I2C Instance.
00579   * @retval None
00580   */
00581 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
00582 {
00583   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00584 }
00585
00586 /**
00587   * @brief  Check if DMA reception requests are enabled or disabled.
00588   * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
00589   * @param  I2Cx I2C Instance.
00590   * @retval State of bit (1 or 0).
00591   */
00592 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
00593 {
00594   return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
00595 }
00596
00597 /**
00598   * @brief  Get the data register address used for DMA transfer
00599   * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
00600   *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
00601   * @param  I2Cx I2C Instance
00602   * @param  Direction This parameter can be one of the following values:
00603   *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
00604   *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
00605   * @retval Address of data register
00606   */
00607 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
00608 {
00609   register uint32_t data_reg_addr = 0U;
00610
00611   if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
00612   {
00613     /* return address of TXDR register */
00614     data_reg_addr = (uint32_t) & (I2Cx->TXDR);
00615   }
00616   else
00617   {
00618     /* return address of RXDR register */
00619     data_reg_addr = (uint32_t) & (I2Cx->RXDR);
00620   }
00621
00622   return data_reg_addr;
00623 }
00624
00625 /**
00626   * @brief  Enable Clock stretching.
00627   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00628   * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
00629   * @param  I2Cx I2C Instance.
00630   * @retval None
00631   */
00632 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
00633 {
00634   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00635 }
00636
00637 /**
00638   * @brief  Disable Clock stretching.
00639   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00640   * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
00641   * @param  I2Cx I2C Instance.
00642   * @retval None
00643   */
00644 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
00645 {
00646   SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00647 }
00648
00649 /**
00650   * @brief  Check if Clock stretching is enabled or disabled.
00651   * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
00652   * @param  I2Cx I2C Instance.
00653   * @retval State of bit (1 or 0).
00654   */
00655 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
00656 {
00657   return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
00658 }
00659
00660 /**
00661   * @brief  Enable hardware byte control in slave mode.
00662   * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
00663   * @param  I2Cx I2C Instance.
00664   * @retval None
00665   */
00666 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
00667 {
00668   SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
00669 }
00670
00671 /**
00672   * @brief  Disable hardware byte control in slave mode.
00673   * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
00674   * @param  I2Cx I2C Instance.
00675   * @retval None
00676   */
00677 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
00678 {
00679   CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
00680 }
00681
00682 /**
00683   * @brief  Check if hardware byte control in slave mode is enabled or disabled.
00684   * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
00685   * @param  I2Cx I2C Instance.
00686   * @retval State of bit (1 or 0).
00687   */
00688 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
00689 {
00690   return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
00691 }
00692
00693 /**
00694   * @brief  Enable Wakeup from STOP.
00695   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00696   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00697   * @note   This bit can only be programmed when Digital Filter is disabled.
00698   * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
00699   * @param  I2Cx I2C Instance.
00700   * @retval None
00701   */
00702 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
00703 {
00704   SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00705 }
00706
00707 /**
00708   * @brief  Disable Wakeup from STOP.
00709   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00710   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00711   * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
00712   * @param  I2Cx I2C Instance.
00713   * @retval None
00714   */
00715 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
00716 {
00717   CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00718 }
00719
00720 /**
00721   * @brief  Check if Wakeup from STOP is enabled or disabled.
00722   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00723   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00724   * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
00725   * @param  I2Cx I2C Instance.
00726   * @retval State of bit (1 or 0).
00727   */
00728 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
00729 {
00730   return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
00731 }
00732
00733 /**
00734   * @brief  Enable General Call.
00735   * @note   When enabled the Address 0x00 is ACKed.
00736   * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
00737   * @param  I2Cx I2C Instance.
00738   * @retval None
00739   */
00740 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
00741 {
00742   SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00743 }
00744
00745 /**
00746   * @brief  Disable General Call.
00747   * @note   When disabled the Address 0x00 is NACKed.
00748   * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
00749   * @param  I2Cx I2C Instance.
00750   * @retval None
00751   */
00752 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
00753 {
00754   CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00755 }
00756
00757 /**
00758   * @brief  Check if General Call is enabled or disabled.
00759   * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
00760   * @param  I2Cx I2C Instance.
00761   * @retval State of bit (1 or 0).
00762   */
00763 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
00764 {
00765   return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
00766 }
00767
00768 /**
00769   * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
00770   * @note   Changing this bit is not allowed, when the START bit is set.
00771   * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
00772   * @param  I2Cx I2C Instance.
00773   * @param  AddressingMode This parameter can be one of the following values:
00774   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00775   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00776   * @retval None
00777   */
00778 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
00779 {
00780   MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
00781 }
00782
00783 /**
00784   * @brief  Get the Master addressing mode.
00785   * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
00786   * @param  I2Cx I2C Instance.
00787   * @retval Returned value can be one of the following values:
00788   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00789   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00790   */
00791 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
00792 {
00793   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
00794 }
00795
00796 /**
00797   * @brief  Set the Own Address1.
00798   * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
00799   *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
00800   * @param  I2Cx I2C Instance.
00801   * @param  OwnAddress1 This parameter must be a value between 0 and 0x3FF.
00802   * @param  OwnAddrSize This parameter can be one of the following values:
00803   *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
00804   *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
00805   * @retval None
00806   */
00807 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
00808 {
00809   MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
00810 }
00811
00812 /**
00813   * @brief  Enable acknowledge on Own Address1 match address.
00814   * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
00815   * @param  I2Cx I2C Instance.
00816   * @retval None
00817   */
00818 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
00819 {
00820   SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00821 }
00822
00823 /**
00824   * @brief  Disable acknowledge on Own Address1 match address.
00825   * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
00826   * @param  I2Cx I2C Instance.
00827   * @retval None
00828   */
00829 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
00830 {
00831   CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00832 }
00833
00834 /**
00835   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00836   * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
00837   * @param  I2Cx I2C Instance.
00838   * @retval State of bit (1 or 0).
00839   */
00840 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
00841 {
00842   return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
00843 }
00844
00845 /**
00846   * @brief  Set the 7bits Own Address2.
00847   * @note   This action has no effect if own address2 is enabled.
00848   * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
00849   *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
00850   * @param  I2Cx I2C Instance.
00851   * @param  OwnAddress2 Value between 0 and 0x7F.
00852   * @param  OwnAddrMask This parameter can be one of the following values:
00853   *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
00854   *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
00855   *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
00856   *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
00857   *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
00858   *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
00859   *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
00860   *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
00861   * @retval None
00862   */
00863 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
00864 {
00865   MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
00866 }
00867
00868 /**
00869   * @brief  Enable acknowledge on Own Address2 match address.
00870   * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
00871   * @param  I2Cx I2C Instance.
00872   * @retval None
00873   */
00874 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
00875 {
00876   SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00877 }
00878
00879 /**
00880   * @brief  Disable  acknowledge on Own Address2 match address.
00881   * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
00882   * @param  I2Cx I2C Instance.
00883   * @retval None
00884   */
00885 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
00886 {
00887   CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00888 }
00889
00890 /**
00891   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00892   * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
00893   * @param  I2Cx I2C Instance.
00894   * @retval State of bit (1 or 0).
00895   */
00896 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
00897 {
00898   return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
00899 }
00900
00901 /**
00902   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00903   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00904   * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
00905   * @param  I2Cx I2C Instance.
00906   * @param  Timing This parameter must be a value between  0 and 0xFFFFFFFF.
00907   * @note   This parameter is computed with the STM32CubeMX Tool.
00908   * @retval None
00909   */
00910 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
00911 {
00912   WRITE_REG(I2Cx->TIMINGR, Timing);
00913 }
00914
00915 /**
00916   * @brief  Get the Timing Prescaler setting.
00917   * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
00918   * @param  I2Cx I2C Instance.
00919   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00920   */
00921 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
00922 {
00923   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_POSITION_TIMINGR_PRESC);
00924 }
00925
00926 /**
00927   * @brief  Get the SCL low period setting.
00928   * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
00929   * @param  I2Cx I2C Instance.
00930   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00931   */
00932 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
00933 {
00934   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_POSITION_TIMINGR_SCLL);
00935 }
00936
00937 /**
00938   * @brief  Get the SCL high period setting.
00939   * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
00940   * @param  I2Cx I2C Instance.
00941   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00942   */
00943 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
00944 {
00945   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_POSITION_TIMINGR_SCLH);
00946 }
00947
00948 /**
00949   * @brief  Get the SDA hold time.
00950   * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
00951   * @param  I2Cx I2C Instance.
00952   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00953   */
00954 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
00955 {
00956   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_POSITION_TIMINGR_SDADEL);
00957 }
00958
00959 /**
00960   * @brief  Get the SDA setup time.
00961   * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
00962   * @param  I2Cx I2C Instance.
00963   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00964   */
00965 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
00966 {
00967   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_POSITION_TIMINGR_SCLDEL);
00968 }
00969
00970 /**
00971   * @brief  Configure peripheral mode.
00972   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00973   *         SMBus feature is supported by the I2Cx Instance.
00974   * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
00975   *         CR1          SMBDEN        LL_I2C_SetMode
00976   * @param  I2Cx I2C Instance.
00977   * @param  PeripheralMode This parameter can be one of the following values:
00978   *         @arg @ref LL_I2C_MODE_I2C
00979   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00980   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00981   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00982   * @retval None
00983   */
00984 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
00985 {
00986   MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
00987 }
00988
00989 /**
00990   * @brief  Get peripheral mode.
00991   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00992   *         SMBus feature is supported by the I2Cx Instance.
00993   * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
00994   *         CR1          SMBDEN        LL_I2C_GetMode
00995   * @param  I2Cx I2C Instance.
00996   * @retval Returned value can be one of the following values:
00997   *         @arg @ref LL_I2C_MODE_I2C
00998   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00999   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
01000   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
01001   */
01002 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
01003 {
01004   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
01005 }
01006
01007 /**
01008   * @brief  Enable SMBus alert (Host or Device mode)
01009   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01010   *         SMBus feature is supported by the I2Cx Instance.
01011   * @note   SMBus Device mode:
01012   *         - SMBus Alert pin is drived low and
01013   *           Alert Response Address Header acknowledge is enabled.
01014   *         SMBus Host mode:
01015   *         - SMBus Alert pin management is supported.
01016   * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
01017   * @param  I2Cx I2C Instance.
01018   * @retval None
01019   */
01020 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
01021 {
01022   SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01023 }
01024
01025 /**
01026   * @brief  Disable SMBus alert (Host or Device mode)
01027   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01028   *         SMBus feature is supported by the I2Cx Instance.
01029   * @note   SMBus Device mode:
01030   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
01031   *           Alert Response Address Header acknowledge is disabled.
01032   *         SMBus Host mode:
01033   *         - SMBus Alert pin management is not supported.
01034   * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
01035   * @param  I2Cx I2C Instance.
01036   * @retval None
01037   */
01038 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
01039 {
01040   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01041 }
01042
01043 /**
01044   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
01045   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01046   *         SMBus feature is supported by the I2Cx Instance.
01047   * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
01048   * @param  I2Cx I2C Instance.
01049   * @retval State of bit (1 or 0).
01050   */
01051 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
01052 {
01053   return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
01054 }
01055
01056 /**
01057   * @brief  Enable SMBus Packet Error Calculation (PEC).
01058   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01059   *         SMBus feature is supported by the I2Cx Instance.
01060   * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
01061   * @param  I2Cx I2C Instance.
01062   * @retval None
01063   */
01064 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
01065 {
01066   SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01067 }
01068
01069 /**
01070   * @brief  Disable SMBus Packet Error Calculation (PEC).
01071   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01072   *         SMBus feature is supported by the I2Cx Instance.
01073   * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
01074   * @param  I2Cx I2C Instance.
01075   * @retval None
01076   */
01077 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
01078 {
01079   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01080 }
01081
01082 /**
01083   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
01084   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01085   *         SMBus feature is supported by the I2Cx Instance.
01086   * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
01087   * @param  I2Cx I2C Instance.
01088   * @retval State of bit (1 or 0).
01089   */
01090 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
01091 {
01092   return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
01093 }
01094
01095 /**
01096   * @brief  Configure the SMBus Clock Timeout.
01097   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01098   *         SMBus feature is supported by the I2Cx Instance.
01099   * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
01100   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
01101   *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
01102   *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
01103   * @param  I2Cx I2C Instance.
01104   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01105   * @param  TimeoutAMode This parameter can be one of the following values:
01106   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01107   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01108   * @param  TimeoutB
01109   *               @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
01110   * @retval None
01111   */
01112 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
01113                                                uint32_t TimeoutB)
01114 {
01115   MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
01116              TimeoutA | TimeoutAMode | (TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB));
01117 }
01118
01119 /**
01120   * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
01121   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01122   *         SMBus feature is supported by the I2Cx Instance.
01123   * @note   These bits can only be programmed when TimeoutA is disabled.
01124   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
01125   * @param  I2Cx I2C Instance.
01126   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01127   * @retval None
01128   */
01129 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
01130 {
01131   WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
01132 }
01133
01134 /**
01135   * @brief  Get the SMBus Clock TimeoutA setting.
01136   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01137   *         SMBus feature is supported by the I2Cx Instance.
01138   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
01139   * @param  I2Cx I2C Instance.
01140   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01141   */
01142 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
01143 {
01144   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
01145 }
01146
01147 /**
01148   * @brief  Set the SMBus Clock TimeoutA mode.
01149   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01150   *         SMBus feature is supported by the I2Cx Instance.
01151   * @note   This bit can only be programmed when TimeoutA is disabled.
01152   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
01153   * @param  I2Cx I2C Instance.
01154   * @param  TimeoutAMode This parameter can be one of the following values:
01155   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01156   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01157   * @retval None
01158   */
01159 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
01160 {
01161   WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
01162 }
01163
01164 /**
01165   * @brief  Get the SMBus Clock TimeoutA mode.
01166   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01167   *         SMBus feature is supported by the I2Cx Instance.
01168   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
01169   * @param  I2Cx I2C Instance.
01170   * @retval Returned value can be one of the following values:
01171   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01172   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01173   */
01174 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
01175 {
01176   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
01177 }
01178
01179 /**
01180   * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
01181   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01182   *         SMBus feature is supported by the I2Cx Instance.
01183   * @note   These bits can only be programmed when TimeoutB is disabled.
01184   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
01185   * @param  I2Cx I2C Instance.
01186   * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01187   * @retval None
01188   */
01189 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
01190 {
01191   WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB);
01192 }
01193
01194 /**
01195   * @brief  Get the SMBus Extented Cumulative Clock TimeoutB setting.
01196   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01197   *         SMBus feature is supported by the I2Cx Instance.
01198   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
01199   * @param  I2Cx I2C Instance.
01200   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01201   */
01202 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
01203 {
01204   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_POSITION_TIMEOUTR_TIMEOUTB);
01205 }
01206
01207 /**
01208   * @brief  Enable the SMBus Clock Timeout.
01209   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01210   *         SMBus feature is supported by the I2Cx Instance.
01211   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
01212   *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
01213   * @param  I2Cx I2C Instance.
01214   * @param  ClockTimeout This parameter can be one of the following values:
01215   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01216   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01217   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01218   * @retval None
01219   */
01220 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01221 {
01222   SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01223 }
01224
01225 /**
01226   * @brief  Disable the SMBus Clock Timeout.
01227   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01228   *         SMBus feature is supported by the I2Cx Instance.
01229   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
01230   *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
01231   * @param  I2Cx I2C Instance.
01232   * @param  ClockTimeout This parameter can be one of the following values:
01233   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01234   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01235   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01236   * @retval None
01237   */
01238 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01239 {
01240   CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01241 }
01242
01243 /**
01244   * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
01245   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01246   *         SMBus feature is supported by the I2Cx Instance.
01247   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
01248   *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
01249   * @param  I2Cx I2C Instance.
01250   * @param  ClockTimeout This parameter can be one of the following values:
01251   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01252   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01253   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01254   * @retval State of bit (1 or 0).
01255   */
01256 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01257 {
01258   return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
01259 }
01260
01261 /**
01262   * @}
01263   */
01264
01265 /** @defgroup I2C_LL_EF_IT_Management IT_Management
01266   * @{
01267   */
01268
01269 /**
01270   * @brief  Enable TXIS interrupt.
01271   * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
01272   * @param  I2Cx I2C Instance.
01273   * @retval None
01274   */
01275 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
01276 {
01277   SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01278 }
01279
01280 /**
01281   * @brief  Disable TXIS interrupt.
01282   * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
01283   * @param  I2Cx I2C Instance.
01284   * @retval None
01285   */
01286 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
01287 {
01288   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01289 }
01290
01291 /**
01292   * @brief  Check if the TXIS Interrupt is enabled or disabled.
01293   * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
01294   * @param  I2Cx I2C Instance.
01295   * @retval State of bit (1 or 0).
01296   */
01297 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
01298 {
01299   return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
01300 }
01301
01302 /**
01303   * @brief  Enable RXNE interrupt.
01304   * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
01305   * @param  I2Cx I2C Instance.
01306   * @retval None
01307   */
01308 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
01309 {
01310   SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01311 }
01312
01313 /**
01314   * @brief  Disable RXNE interrupt.
01315   * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
01316   * @param  I2Cx I2C Instance.
01317   * @retval None
01318   */
01319 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
01320 {
01321   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01322 }
01323
01324 /**
01325   * @brief  Check if the RXNE Interrupt is enabled or disabled.
01326   * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
01327   * @param  I2Cx I2C Instance.
01328   * @retval State of bit (1 or 0).
01329   */
01330 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
01331 {
01332   return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
01333 }
01334
01335 /**
01336   * @brief  Enable Address match interrupt (slave mode only).
01337   * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
01338   * @param  I2Cx I2C Instance.
01339   * @retval None
01340   */
01341 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
01342 {
01343   SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01344 }
01345
01346 /**
01347   * @brief  Disable Address match interrupt (slave mode only).
01348   * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
01349   * @param  I2Cx I2C Instance.
01350   * @retval None
01351   */
01352 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
01353 {
01354   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01355 }
01356
01357 /**
01358   * @brief  Check if Address match interrupt is enabled or disabled.
01359   * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
01360   * @param  I2Cx I2C Instance.
01361   * @retval State of bit (1 or 0).
01362   */
01363 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
01364 {
01365   return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
01366 }
01367
01368 /**
01369   * @brief  Enable Not acknowledge received interrupt.
01370   * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
01371   * @param  I2Cx I2C Instance.
01372   * @retval None
01373   */
01374 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
01375 {
01376   SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01377 }
01378
01379 /**
01380   * @brief  Disable Not acknowledge received interrupt.
01381   * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
01382   * @param  I2Cx I2C Instance.
01383   * @retval None
01384   */
01385 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
01386 {
01387   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01388 }
01389
01390 /**
01391   * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
01392   * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
01393   * @param  I2Cx I2C Instance.
01394   * @retval State of bit (1 or 0).
01395   */
01396 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
01397 {
01398   return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
01399 }
01400
01401 /**
01402   * @brief  Enable STOP detection interrupt.
01403   * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
01404   * @param  I2Cx I2C Instance.
01405   * @retval None
01406   */
01407 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
01408 {
01409   SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01410 }
01411
01412 /**
01413   * @brief  Disable STOP detection interrupt.
01414   * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
01415   * @param  I2Cx I2C Instance.
01416   * @retval None
01417   */
01418 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
01419 {
01420   CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01421 }
01422
01423 /**
01424   * @brief  Check if STOP detection interrupt is enabled or disabled.
01425   * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
01426   * @param  I2Cx I2C Instance.
01427   * @retval State of bit (1 or 0).
01428   */
01429 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
01430 {
01431   return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
01432 }
01433
01434 /**
01435   * @brief  Enable Transfer Complete interrupt.
01436   * @note   Any of these events will generate interrupt :
01437   *         Transfer Complete (TC)
01438   *         Transfer Complete Reload (TCR)
01439   * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
01440   * @param  I2Cx I2C Instance.
01441   * @retval None
01442   */
01443 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
01444 {
01445   SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01446 }
01447
01448 /**
01449   * @brief  Disable Transfer Complete interrupt.
01450   * @note   Any of these events will generate interrupt :
01451   *         Transfer Complete (TC)
01452   *         Transfer Complete Reload (TCR)
01453   * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
01454   * @param  I2Cx I2C Instance.
01455   * @retval None
01456   */
01457 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
01458 {
01459   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01460 }
01461
01462 /**
01463   * @brief  Check if Transfer Complete interrupt is enabled or disabled.
01464   * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
01465   * @param  I2Cx I2C Instance.
01466   * @retval State of bit (1 or 0).
01467   */
01468 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
01469 {
01470   return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
01471 }
01472
01473 /**
01474   * @brief  Enable Error interrupts.
01475   * @note   Any of these errors will generate interrupt :
01476   *         Arbitration Loss (ARLO)
01477   *         Bus Error detection (BERR)
01478   *         Overrun/Underrun (OVR)
01479   *         SMBus Timeout detection (TIMEOUT)
01480   *         SMBus PEC error detection (PECERR)
01481   *         SMBus Alert pin event detection (ALERT)
01482   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01483   *         SMBus feature is supported by the I2Cx Instance.
01484   * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
01485   * @param  I2Cx I2C Instance.
01486   * @retval None
01487   */
01488 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
01489 {
01490   SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01491 }
01492
01493 /**
01494   * @brief  Disable Error interrupts.
01495   * @note   Any of these errors will generate interrupt :
01496   *         Arbitration Loss (ARLO)
01497   *         Bus Error detection (BERR)
01498   *         Overrun/Underrun (OVR)
01499   *         SMBus Timeout detection (TIMEOUT)
01500   *         SMBus PEC error detection (PECERR)
01501   *         SMBus Alert pin event detection (ALERT)
01502   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01503   *         SMBus feature is supported by the I2Cx Instance.
01504   * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
01505   * @param  I2Cx I2C Instance.
01506   * @retval None
01507   */
01508 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
01509 {
01510   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01511 }
01512
01513 /**
01514   * @brief  Check if Error interrupts is enabled of disabled.
01515   * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
01516   * @param  I2Cx I2C Instance.
01517   * @retval State of bit (1 or 0).
01518   */
01519 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
01520 {
01521   return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
01522 }
01523
01524 /**
01525   * @}
01526   */
01527
01528 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
01529   * @{
01530   */
01531
01532 /**
01533   * @brief  Indicate the status of Transmit data register empty flag.
01534   * @note   RESET: When next data is written in Transmit data register.
01535   *         SET: When Transmit data register is empty.
01536   * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
01537   * @param  I2Cx I2C Instance.
01538   * @retval State of bit (1 or 0).
01539   */
01540 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
01541 {
01542   return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
01543 }
01544
01545 /**
01546   * @brief  Indicate the status of Transmit interrupt flag.
01547   * @note   RESET: When next data is written in Transmit data register.
01548   *         SET: When Transmit data register is empty.
01549   * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
01550   * @param  I2Cx I2C Instance.
01551   * @retval State of bit (1 or 0).
01552   */
01553 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
01554 {
01555   return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
01556 }
01557
01558 /**
01559   * @brief  Indicate the status of Receive data register not empty flag.
01560   * @note   RESET: When Receive data register is read.
01561   *         SET: When the received data is copied in Receive data register.
01562   * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
01563   * @param  I2Cx I2C Instance.
01564   * @retval State of bit (1 or 0).
01565   */
01566 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
01567 {
01568   return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
01569 }
01570
01571 /**
01572   * @brief  Indicate the status of Address matched flag (slave mode).
01573   * @note   RESET: Clear default value.
01574   *         SET: When the received slave address matched with one of the enabled slave address.
01575   * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
01576   * @param  I2Cx I2C Instance.
01577   * @retval State of bit (1 or 0).
01578   */
01579 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
01580 {
01581   return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
01582 }
01583
01584 /**
01585   * @brief  Indicate the status of Not Acknowledge received flag.
01586   * @note   RESET: Clear default value.
01587   *         SET: When a NACK is received after a byte transmission.
01588   * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
01589   * @param  I2Cx I2C Instance.
01590   * @retval State of bit (1 or 0).
01591   */
01592 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
01593 {
01594   return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
01595 }
01596
01597 /**
01598   * @brief  Indicate the status of Stop detection flag.
01599   * @note   RESET: Clear default value.
01600   *         SET: When a Stop condition is detected.
01601   * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
01602   * @param  I2Cx I2C Instance.
01603   * @retval State of bit (1 or 0).
01604   */
01605 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
01606 {
01607   return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
01608 }
01609
01610 /**
01611   * @brief  Indicate the status of Transfer complete flag (master mode).
01612   * @note   RESET: Clear default value.
01613   *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
01614   * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
01615   * @param  I2Cx I2C Instance.
01616   * @retval State of bit (1 or 0).
01617   */
01618 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
01619 {
01620   return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
01621 }
01622
01623 /**
01624   * @brief  Indicate the status of Transfer complete flag (master mode).
01625   * @note   RESET: Clear default value.
01626   *         SET: When RELOAD=1 and NBYTES date have been transferred.
01627   * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
01628   * @param  I2Cx I2C Instance.
01629   * @retval State of bit (1 or 0).
01630   */
01631 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
01632 {
01633   return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
01634 }
01635
01636 /**
01637   * @brief  Indicate the status of Bus error flag.
01638   * @note   RESET: Clear default value.
01639   *         SET: When a misplaced Start or Stop condition is detected.
01640   * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
01641   * @param  I2Cx I2C Instance.
01642   * @retval State of bit (1 or 0).
01643   */
01644 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
01645 {
01646   return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
01647 }
01648
01649 /**
01650   * @brief  Indicate the status of Arbitration lost flag.
01651   * @note   RESET: Clear default value.
01652   *         SET: When arbitration lost.
01653   * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
01654   * @param  I2Cx I2C Instance.
01655   * @retval State of bit (1 or 0).
01656   */
01657 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
01658 {
01659   return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
01660 }
01661
01662 /**
01663   * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
01664   * @note   RESET: Clear default value.
01665   *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
01666   * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
01667   * @param  I2Cx I2C Instance.
01668   * @retval State of bit (1 or 0).
01669   */
01670 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
01671 {
01672   return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
01673 }
01674
01675 /**
01676   * @brief  Indicate the status of Bus Busy flag.
01677   * @note   RESET: Clear default value.
01678   *         SET: When a Start condition is detected.
01679   * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
01680   * @param  I2Cx I2C Instance.
01681   * @retval State of bit (1 or 0).
01682   */
01683 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
01684 {
01685   return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
01686 }
01687
01688 /**
01689   * @brief  Clear Address Matched flag.
01690   * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
01691   * @param  I2Cx I2C Instance.
01692   * @retval None
01693   */
01694 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
01695 {
01696   SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
01697 }
01698
01699 /**
01700   * @brief  Clear Not Acknowledge flag.
01701   * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
01702   * @param  I2Cx I2C Instance.
01703   * @retval None
01704   */
01705 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
01706 {
01707   SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
01708 }
01709
01710 /**
01711   * @brief  Clear Stop detection flag.
01712   * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
01713   * @param  I2Cx I2C Instance.
01714   * @retval None
01715   */
01716 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
01717 {
01718   SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
01719 }
01720
01721 /**
01722   * @brief  Clear Transmit data register empty flag (TXE).
01723   * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
01724   * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
01725   * @param  I2Cx I2C Instance.
01726   * @retval None
01727   */
01728 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
01729 {
01730   WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
01731 }
01732
01733 /**
01734   * @brief  Clear Bus error flag.
01735   * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
01736   * @param  I2Cx I2C Instance.
01737   * @retval None
01738   */
01739 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
01740 {
01741   SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
01742 }
01743
01744 /**
01745   * @brief  Clear Arbitration lost flag.
01746   * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
01747   * @param  I2Cx I2C Instance.
01748   * @retval None
01749   */
01750 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
01751 {
01752   SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
01753 }
01754
01755 /**
01756   * @brief  Clear Overrun/Underrun flag.
01757   * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
01758   * @param  I2Cx I2C Instance.
01759   * @retval None
01760   */
01761 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
01762 {
01763   SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
01764 }
01765
01766 /**
01767   * @brief  Indicate the status of SMBus PEC error flag in reception.
01768   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01769   *         SMBus feature is supported by the I2Cx Instance.
01770   * @note   RESET: Clear default value.
01771   *         SET: When the received PEC does not match with the PEC register content.
01772   * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
01773   * @param  I2Cx I2C Instance.
01774   * @retval State of bit (1 or 0).
01775   */
01776 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01777 {
01778   return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
01779 }
01780
01781 /**
01782   * @brief  Indicate the status of SMBus Timeout detection flag.
01783   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01784   *         SMBus feature is supported by the I2Cx Instance.
01785   * @note   RESET: Clear default value.
01786   *         SET: When a timeout or extended clock timeout occurs.
01787   * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
01788   * @param  I2Cx I2C Instance.
01789   * @retval State of bit (1 or 0).
01790   */
01791 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01792 {
01793   return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
01794 }
01795
01796 /**
01797   * @brief  Indicate the status of SMBus alert flag.
01798   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01799   *         SMBus feature is supported by the I2Cx Instance.
01800   * @note   RESET: Clear default value.
01801   *         SET: When SMBus host configuration, SMBus alert enabled and
01802   *              a falling edge event occurs on SMBA pin.
01803   * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
01804   * @param  I2Cx I2C Instance.
01805   * @retval State of bit (1 or 0).
01806   */
01807 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01808 {
01809   return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
01810 }
01811
01812 /**
01813   * @brief  Clear SMBus PEC error flag.
01814   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01815   *         SMBus feature is supported by the I2Cx Instance.
01816   * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
01817   * @param  I2Cx I2C Instance.
01818   * @retval None
01819   */
01820 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01821 {
01822   SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
01823 }
01824
01825 /**
01826   * @brief  Clear SMBus Timeout detection flag.
01827   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01828   *         SMBus feature is supported by the I2Cx Instance.
01829   * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
01830   * @param  I2Cx I2C Instance.
01831   * @retval None
01832   */
01833 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01834 {
01835   SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
01836 }
01837
01838 /**
01839   * @brief  Clear SMBus Alert flag.
01840   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01841   *         SMBus feature is supported by the I2Cx Instance.
01842   * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
01843   * @param  I2Cx I2C Instance.
01844   * @retval None
01845   */
01846 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01847 {
01848   SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
01849 }
01850
01851 /**
01852   * @}
01853   */
01854
01855 /** @defgroup I2C_LL_EF_Data_Management Data_Management
01856   * @{
01857   */
01858
01859 /**
01860   * @brief  Enable automatic STOP condition generation (master mode).
01861   * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
01862   *         This bit has no effect in slave mode or when RELOAD bit is set.
01863   * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
01864   * @param  I2Cx I2C Instance.
01865   * @retval None
01866   */
01867 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
01868 {
01869   SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01870 }
01871
01872 /**
01873   * @brief  Disable automatic STOP condition generation (master mode).
01874   * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
01875   * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
01876   * @param  I2Cx I2C Instance.
01877   * @retval None
01878   */
01879 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
01880 {
01881   CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01882 }
01883
01884 /**
01885   * @brief  Check if automatic STOP condition is enabled or disabled.
01886   * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
01887   * @param  I2Cx I2C Instance.
01888   * @retval State of bit (1 or 0).
01889   */
01890 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
01891 {
01892   return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
01893 }
01894
01895 /**
01896   * @brief  Enable reload mode (master mode).
01897   * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
01898   * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
01899   * @param  I2Cx I2C Instance.
01900   * @retval None
01901   */
01902 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
01903 {
01904   SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01905 }
01906
01907 /**
01908   * @brief  Disable reload mode (master mode).
01909   * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
01910   * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
01911   * @param  I2Cx I2C Instance.
01912   * @retval None
01913   */
01914 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
01915 {
01916   CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01917 }
01918
01919 /**
01920   * @brief  Check if reload mode is enabled or disabled.
01921   * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
01922   * @param  I2Cx I2C Instance.
01923   * @retval State of bit (1 or 0).
01924   */
01925 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
01926 {
01927   return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
01928 }
01929
01930 /**
01931   * @brief  Configure the number of bytes for transfer.
01932   * @note   Changing these bits when START bit is set is not allowed.
01933   * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
01934   * @param  I2Cx I2C Instance.
01935   * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
01936   * @retval None
01937   */
01938 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
01939 {
01940   MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_POSITION_CR2_NBYTES);
01941 }
01942
01943 /**
01944   * @brief  Get the number of bytes configured for transfer.
01945   * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
01946   * @param  I2Cx I2C Instance.
01947   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
01948   */
01949 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
01950 {
01951   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_POSITION_CR2_NBYTES);
01952 }
01953
01954 /**
01955   * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
01956   * @note   Usage in Slave mode only.
01957   * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
01958   * @param  I2Cx I2C Instance.
01959   * @param  TypeAcknowledge This parameter can be one of the following values:
01960   *         @arg @ref LL_I2C_ACK
01961   *         @arg @ref LL_I2C_NACK
01962   * @retval None
01963   */
01964 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
01965 {
01966   MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
01967 }
01968
01969 /**
01970   * @brief  Generate a STOP condition after the current byte transfer (master mode).
01971   * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
01972   * @param  I2Cx I2C Instance.
01973   * @retval None
01974   */
01975 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
01976 {
01977   SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
01978 }
01979
01980 /**
01981   * @brief  Generate a START or RESTART condition
01982   * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
01983   *         This action has no effect when RELOAD is set.
01984   * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
01985   * @param  I2Cx I2C Instance.
01986   * @retval None
01987   */
01988 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
01989 {
01990   SET_BIT(I2Cx->CR2, I2C_CR2_START);
01991 }
01992
01993 /**
01994   * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
01995   * @note   The master sends the complete 10bit slave address read sequence :
01996   *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
01997   * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
01998   * @param  I2Cx I2C Instance.
01999   * @retval None
02000   */
02001 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
02002 {
02003   CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
02004 }
02005
02006 /**
02007   * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
02008   * @note   The master only sends the first 7 bits of 10bit address in Read direction.
02009   * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
02010   * @param  I2Cx I2C Instance.
02011   * @retval None
02012   */
02013 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
02014 {
02015   SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
02016 }
02017
02018 /**
02019   * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
02020   * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
02021   * @param  I2Cx I2C Instance.
02022   * @retval State of bit (1 or 0).
02023   */
02024 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
02025 {
02026   return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
02027 }
02028
02029 /**
02030   * @brief  Configure the transfer direction (master mode).
02031   * @note   Changing these bits when START bit is set is not allowed.
02032   * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
02033   * @param  I2Cx I2C Instance.
02034   * @param  TransferRequest This parameter can be one of the following values:
02035   *         @arg @ref LL_I2C_REQUEST_WRITE
02036   *         @arg @ref LL_I2C_REQUEST_READ
02037   * @retval None
02038   */
02039 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
02040 {
02041   MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
02042 }
02043
02044 /**
02045   * @brief  Get the transfer direction requested (master mode).
02046   * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
02047   * @param  I2Cx I2C Instance.
02048   * @retval Returned value can be one of the following values:
02049   *         @arg @ref LL_I2C_REQUEST_WRITE
02050   *         @arg @ref LL_I2C_REQUEST_READ
02051   */
02052 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
02053 {
02054   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
02055 }
02056
02057 /**
02058   * @brief  Configure the slave address for transfer (master mode).
02059   * @note   Changing these bits when START bit is set is not allowed.
02060   * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
02061   * @param  I2Cx I2C Instance.
02062   * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
02063   * @retval None
02064   */
02065 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
02066 {
02067   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
02068 }
02069
02070 /**
02071   * @brief  Get the slave address programmed for transfer.
02072   * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
02073   * @param  I2Cx I2C Instance.
02074   * @retval Value between Min_Data=0x0 and Max_Data=0x3F
02075   */
02076 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
02077 {
02078   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
02079 }
02080
02081 /**
02082   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
02083   * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
02084   *         CR2          ADD10         LL_I2C_HandleTransfer\n
02085   *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
02086   *         CR2          START         LL_I2C_HandleTransfer\n
02087   *         CR2          STOP          LL_I2C_HandleTransfer\n
02088   *         CR2          RELOAD        LL_I2C_HandleTransfer\n
02089   *         CR2          NBYTES        LL_I2C_HandleTransfer\n
02090   *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
02091   *         CR2          HEAD10R       LL_I2C_HandleTransfer
02092   * @param  I2Cx I2C Instance.
02093   * @param  SlaveAddr Specifies the slave address to be programmed.
02094   * @param  SlaveAddrSize This parameter can be one of the following values:
02095   *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
02096   *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
02097   * @param  TransferSize Specifies the number of bytes to be programmed.
02098   *         This parameter must be a value between 0 and 255.
02099   * @param  EndMode This parameter can be one of the following values:
02100   *         @arg @ref LL_I2C_MODE_RELOAD
02101   *         @arg @ref LL_I2C_MODE_AUTOEND
02102   *         @arg @ref LL_I2C_MODE_SOFTEND
02103   *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
02104   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
02105   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
02106   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
02107   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
02108   * @param  Request This parameter can be one of the following values:
02109   *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
02110   *         @arg @ref LL_I2C_GENERATE_STOP
02111   *         @arg @ref LL_I2C_GENERATE_START_READ
02112   *         @arg @ref LL_I2C_GENERATE_START_WRITE
02113   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
02114   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
02115   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
02116   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
02117   * @retval None
02118   */
02119 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
02120                                            uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
02121 {
02122   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
02123              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
02124              SlaveAddr | SlaveAddrSize | TransferSize << I2C_POSITION_CR2_NBYTES | EndMode | Request);
02125 }
02126
02127 /**
02128   * @brief  Indicate the value of transfer direction (slave mode).
02129   * @note   RESET: Write transfer, Slave enters in receiver mode.
02130   *         SET: Read transfer, Slave enters in transmitter mode.
02131   * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
02132   * @param  I2Cx I2C Instance.
02133   * @retval Returned value can be one of the following values:
02134   *         @arg @ref LL_I2C_DIRECTION_WRITE
02135   *         @arg @ref LL_I2C_DIRECTION_READ
02136   */
02137 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
02138 {
02139   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
02140 }
02141
02142 /**
02143   * @brief  Return the slave matched address.
02144   * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
02145   * @param  I2Cx I2C Instance.
02146   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
02147   */
02148 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
02149 {
02150   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_POSITION_ISR_ADDCODE << 1);
02151 }
02152
02153 /**
02154   * @brief  Enable internal comparison of Packet Error byte (transmission or reception mode).
02155   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02156   *         SMBus feature is supported by the I2Cx Instance.
02157   * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
02158   *         This bit has no effect when RELOAD bit is set.
02159   *         This bit has no effect in device mode when SBC bit is not set.
02160   * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
02161   * @param  I2Cx I2C Instance.
02162   * @retval None
02163   */
02164 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
02165 {
02166   SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
02167 }
02168
02169 /**
02170   * @brief  Check if Packet Error byte internal comparison is requested or not.
02171   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02172   *         SMBus feature is supported by the I2Cx Instance.
02173   * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
02174   * @param  I2Cx I2C Instance.
02175   * @retval State of bit (1 or 0).
02176   */
02177 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
02178 {
02179   return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
02180 }
02181
02182 /**
02183   * @brief  Get the Packet Error byte calculated.
02184   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02185   *         SMBus feature is supported by the I2Cx Instance.
02186   * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
02187   * @param  I2Cx I2C Instance.
02188   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02189 */
02190 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
02191 {
02192   return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
02193 }
02194
02195 /**
02196   * @brief  Read Receive Data register.
02197   * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
02198   * @param  I2Cx I2C Instance.
02199   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02200   */
02201 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
02202 {
02203   return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
02204 }
02205
02206 /**
02207   * @brief  Write in Transmit Data Register .
02208   * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
02209   * @param  I2Cx I2C Instance.
02210   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
02211   * @retval None
02212   */
02213 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
02214 {
02215   WRITE_REG(I2Cx->TXDR, Data);
02216 }
02217
02218 /**
02219   * @}
02220   */
02221
02222 #if defined(USE_FULL_LL_DRIVER)
02223 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
02224   * @{
02225   */
02226
02227 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
02228 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
02229 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
02230
02231
02232 /**
02233   * @}
02234   */
02235 #endif /* USE_FULL_LL_DRIVER */
02236
02237 /**
02238   * @}
02239   */
02240
02241 /**
02242   * @}
02243   */
02244
02245 #endif /* I2C1 || I2C2 || I2C3 */
02246
02247 /**
02248   * @}
02249   */
02250
02251 #ifdef __cplusplus
02252 }
02253 #endif
02254
02255 #endif /* __STM32L4xx_LL_I2C_H */
02256
02257 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_iwdg.h Source File

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stm32l4xx_ll_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_iwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of IWDG LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_IWDG_H
00040 #define __STM32L4xx_LL_IWDG_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(IWDG)
00054
00055 /** @defgroup IWDG_LL IWDG
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
00064   * @{
00065   */
00066
00067 #define LL_IWDG_KEY_RELOAD                 ((uint32_t)0x0000AAAAU)               /*!< IWDG Reload Counter Enable   */
00068 #define LL_IWDG_KEY_ENABLE                 ((uint32_t)0x0000CCCCU)               /*!< IWDG Peripheral Enable       */
00069 #define LL_IWDG_KEY_WR_ACCESS_ENABLE       ((uint32_t)0x00005555U)               /*!< IWDG KR Write Access Enable  */
00070 #define LL_IWDG_KEY_WR_ACCESS_DISABLE      ((uint32_t)0x00000000U)               /*!< IWDG KR Write Access Disable */
00071
00072 /**
00073   * @}
00074   */
00075
00076 /* Private macros ------------------------------------------------------------*/
00077
00078 /* Exported types ------------------------------------------------------------*/
00079 /* Exported constants --------------------------------------------------------*/
00080 /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
00081   * @{
00082   */
00083
00084 /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
00085   * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
00086   * @{
00087   */
00088 #define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
00089 #define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
00090 #define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
00091
00092 /**
00093   * @}
00094   */
00095
00096 /** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
00097   * @{
00098   */
00099 #define LL_IWDG_PRESCALER_4                ((uint32_t)0x00000000U)               /*!< Divider by 4   */
00100 #define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
00101 #define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
00102 #define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
00103 #define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
00104 #define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
00105 #define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
00106 /**
00107   * @}
00108   */
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Exported macro ------------------------------------------------------------*/
00115 /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
00116   * @{
00117   */
00118
00119 /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
00120   * @{
00121   */
00122
00123 /**
00124   * @brief  Write a value in IWDG register
00125   * @param  __INSTANCE__ IWDG Instance
00126   * @param  __REG__ Register to be written
00127   * @param  __VALUE__ Value to be written in the register
00128   * @retval None
00129   */
00130 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00131
00132 /**
00133   * @brief  Read a value in IWDG register
00134   * @param  __INSTANCE__ IWDG Instance
00135   * @param  __REG__ Register to be read
00136   * @retval Register value
00137   */
00138 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00139 /**
00140   * @}
00141   */
00142
00143 /**
00144   * @}
00145   */
00146
00147
00148 /* Exported functions --------------------------------------------------------*/
00149 /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
00150   * @{
00151   */
00152 /** @defgroup IWDG_LL_EF_Configuration Configuration
00153   * @{
00154   */
00155
00156 /**
00157   * @brief  Start the Independent Watchdog
00158   * @note   Except if the hardware watchdog option is selected
00159   * @rmtoll KR           KEY           LL_IWDG_Enable
00160   * @param  IWDGx IWDG Instance
00161   * @retval None
00162   */
00163 __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
00164 {
00165   WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
00166 }
00167
00168 /**
00169   * @brief  Reloads IWDG counter with value defined in the reload register
00170   * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
00171   * @param  IWDGx IWDG Instance
00172   * @retval None
00173   */
00174 __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
00175 {
00176   WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
00177 }
00178
00179 /**
00180   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00181   * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
00182   * @param  IWDGx IWDG Instance
00183   * @retval None
00184   */
00185 __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
00186 {
00187   WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
00188 }
00189
00190 /**
00191   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00192   * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
00193   * @param  IWDGx IWDG Instance
00194   * @retval None
00195   */
00196 __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
00197 {
00198   WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
00199 }
00200
00201 /**
00202   * @brief  Select the prescaler of the IWDG
00203   * @rmtoll PR           PR            LL_IWDG_SetPrescaler
00204   * @param  IWDGx IWDG Instance
00205   * @param  Prescaler This parameter can be one of the following values:
00206   *         @arg @ref LL_IWDG_PRESCALER_4
00207   *         @arg @ref LL_IWDG_PRESCALER_8
00208   *         @arg @ref LL_IWDG_PRESCALER_16
00209   *         @arg @ref LL_IWDG_PRESCALER_32
00210   *         @arg @ref LL_IWDG_PRESCALER_64
00211   *         @arg @ref LL_IWDG_PRESCALER_128
00212   *         @arg @ref LL_IWDG_PRESCALER_256
00213   * @retval None
00214   */
00215 __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
00216 {
00217   WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
00218 }
00219
00220 /**
00221   * @brief  Get the selected prescaler of the IWDG
00222   * @rmtoll PR           PR            LL_IWDG_GetPrescaler
00223   * @param  IWDGx IWDG Instance
00224   * @retval Returned value can be one of the following values:
00225   *         @arg @ref LL_IWDG_PRESCALER_4
00226   *         @arg @ref LL_IWDG_PRESCALER_8
00227   *         @arg @ref LL_IWDG_PRESCALER_16
00228   *         @arg @ref LL_IWDG_PRESCALER_32
00229   *         @arg @ref LL_IWDG_PRESCALER_64
00230   *         @arg @ref LL_IWDG_PRESCALER_128
00231   *         @arg @ref LL_IWDG_PRESCALER_256
00232   */
00233 __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
00234 {
00235   return (uint32_t)(READ_REG(IWDGx->PR));
00236 }
00237
00238 /**
00239   * @brief  Specify the IWDG down-counter reload value
00240   * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
00241   * @param  IWDGx IWDG Instance
00242   * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
00243   * @retval None
00244   */
00245 __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
00246 {
00247   WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
00248 }
00249
00250 /**
00251   * @brief  Get the specified IWDG down-counter reload value
00252   * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
00253   * @param  IWDGx IWDG Instance
00254   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00255   */
00256 __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
00257 {
00258   return (uint32_t)(READ_REG(IWDGx->RLR));
00259 }
00260
00261 /**
00262   * @brief  Specify high limit of the window value to be compared to the down-counter.
00263   * @rmtoll WINR         WIN           LL_IWDG_SetWindow
00264   * @param  IWDGx IWDG Instance
00265   * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
00266   * @retval None
00267   */
00268 __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
00269 {
00270   WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
00271 }
00272
00273 /**
00274   * @brief  Get the high limit of the window value specified.
00275   * @rmtoll WINR         WIN           LL_IWDG_GetWindow
00276   * @param  IWDGx IWDG Instance
00277   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00278   */
00279 __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
00280 {
00281   return (uint32_t)(READ_REG(IWDGx->WINR));
00282 }
00283
00284 /**
00285   * @}
00286   */
00287
00288 /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
00289   * @{
00290   */
00291
00292 /**
00293   * @brief  Check if flag Prescaler Value Update is set or not
00294   * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
00295   * @param  IWDGx IWDG Instance
00296   * @retval State of bit (1 or 0).
00297   */
00298 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
00299 {
00300   return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
00301 }
00302
00303 /**
00304   * @brief  Check if flag Reload Value Update is set or not
00305   * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
00306   * @param  IWDGx IWDG Instance
00307   * @retval State of bit (1 or 0).
00308   */
00309 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
00310 {
00311   return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
00312 }
00313
00314 /**
00315   * @brief  Check if flag Window Value Update is set or not
00316   * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
00317   * @param  IWDGx IWDG Instance
00318   * @retval State of bit (1 or 0).
00319   */
00320 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
00321 {
00322   return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
00323 }
00324
00325 /**
00326   * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
00327   * @rmtoll SR           PVU           LL_IWDG_IsReady\n
00328   *         SR           WVU           LL_IWDG_IsReady\n
00329   *         SR           RVU           LL_IWDG_IsReady
00330   * @param  IWDGx IWDG Instance
00331   * @retval State of bits (1 or 0).
00332   */
00333 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
00334 {
00335   return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
00336 }
00337
00338 /**
00339   * @}
00340   */
00341
00342
00343 /**
00344   * @}
00345   */
00346
00347 /**
00348   * @}
00349   */
00350
00351 #endif /* IWDG) */
00352
00353 /**
00354   * @}
00355   */
00356
00357 #ifdef __cplusplus
00358 }
00359 #endif
00360
00361 #endif /* __STM32L4xx_LL_IWDG_H */
00362
00363 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_lptim.c Source File

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stm32l4xx_ll_lptim.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_lptim.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   LPTIM LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_lptim.h"
00041 #include "stm32l4xx_ll_bus.h"
00042
00043 #ifdef  USE_FULL_ASSERT
00044   #include "stm32_assert.h"
00045 #else
00046   #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (LPTIM1) || defined (LPTIM2)
00054
00055 /** @addtogroup LPTIM_LL
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 /** @addtogroup LPTIM_LL_Private_Macros
00064   * @{
00065   */
00066 #define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
00067                                        || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
00068
00069 #define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
00070                                           || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
00071                                           || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
00072                                           || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
00073                                           || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
00074                                           || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
00075                                           || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
00076                                           || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
00077
00078 #define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
00079                                    || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
00080
00081 #define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
00082                                           || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
00083 /**
00084   * @}
00085   */
00086
00087
00088 /* Private function prototypes -----------------------------------------------*/
00089 /* Exported functions --------------------------------------------------------*/
00090 /** @addtogroup LPTIM_LL_Exported_Functions
00091   * @{
00092   */
00093
00094 /** @addtogroup LPTIM_LL_EF_Init
00095   * @{
00096   */
00097
00098 /**
00099   * @brief  Set LPTIMx registers to their reset values.
00100   * @param  LPTIMx LP Timer instance
00101   * @retval An ErrorStatus enumeration value:
00102   *          - SUCCESS: LPTIMx registers are de-initialized
00103   *          - ERROR: invalid LPTIMx instance
00104   */
00105 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
00106 {
00107   ErrorStatus result = SUCCESS;
00108
00109   /* Check the parameters */
00110   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00111
00112   if (LPTIMx == LPTIM1)
00113   {
00114     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
00115     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
00116   }
00117 #if defined(LPTIM2)
00118   else if (LPTIMx == LPTIM2)
00119   {
00120     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
00121     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
00122   }
00123 #endif
00124   else
00125   {
00126     result = ERROR;
00127   }
00128
00129   return result;
00130 }
00131
00132 /**
00133   * @brief  Set each fields of the LPTIM_InitStruct structure to its default
00134   *         value.
00135   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
00136   * @retval None
00137   */
00138 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
00139 {
00140   /* Set the default configuration */
00141   LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
00142   LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
00143   LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
00144   LPTIM_InitStruct->Polarity    = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
00145 }
00146
00147 /**
00148   * @brief  Configure the LPTIMx peripheral according to the specified parameters.
00149   * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
00150   * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
00151   * @param  LPTIMx LP Timer Instance
00152   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
00153   * @retval An ErrorStatus enumeration value:
00154   *          - SUCCESS: LPTIMx instance has been initialized
00155   *          - ERROR: LPTIMx instance hasn't been initialized
00156   */
00157 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
00158 {
00159   ErrorStatus result = SUCCESS;
00160
00161   /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
00162      (ENABLE bit is reset to 0).
00163   */
00164   if (LL_LPTIM_IsEnabled(LPTIMx))
00165   {
00166     result = ERROR;
00167   }
00168   else
00169   {
00170   /* Check the parameters */
00171   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00172   assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
00173   assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
00174   assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
00175   assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
00176
00177   /* Set CKSEL bitfield according to ClockSource value */
00178   /* Set PRESC bitfield according to Prescaler value */
00179   /* Set WAVE bitfield according to Waveform value */
00180   /* Set WAVEPOL bitfield according to Polarity value */
00181   MODIFY_REG(LPTIMx->CFGR,
00182              (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL),
00183              LPTIM_InitStruct->ClockSource | \
00184              LPTIM_InitStruct->Prescaler | \
00185              LPTIM_InitStruct->Waveform | \
00186              LPTIM_InitStruct->Polarity);
00187   }
00188
00189   return result;
00190 }
00191
00192 /**
00193   * @}
00194   */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /**
00201   * @}
00202   */
00203
00204 #endif /* defined (LPTIM1) || defined (LPTIM2) */
00205
00206 /**
00207   * @}
00208   */
00209
00210 #endif /* USE_FULL_LL_DRIVER */
00211
00212 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_lptim.h Source File

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stm32l4xx_ll_lptim.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_lptim.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of LPTIM LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_LPTIM_H
00040 #define __STM32L4xx_LL_LPTIM_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052 #if defined (LPTIM1) || defined (LPTIM2)
00053
00054 /** @defgroup LPTIM_LL LPTIM
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060
00061 /* Private constants ---------------------------------------------------------*/
00062
00063 /* Private macros ------------------------------------------------------------*/
00064 /* Private macros ------------------------------------------------------------*/
00065 #if defined(USE_FULL_LL_DRIVER)
00066 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
00067   * @{
00068   */
00069 /**
00070   * @}
00071   */
00072 #endif /*USE_FULL_LL_DRIVER*/
00073
00074 /* Exported types ------------------------------------------------------------*/
00075 #if defined(USE_FULL_LL_DRIVER)
00076 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  LPTIM Init structure definition
00082   */
00083 typedef struct
00084 {
00085   uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
00086                                 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
00087
00088                                 This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
00089
00090   uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
00091                                 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
00092
00093                                 This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
00094
00095   uint32_t Waveform;       /*!< Specifies the waveform shape.
00096                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
00097
00098                                 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
00099
00100   uint32_t Polarity;       /*!< Specifies waveform polarity.
00101                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
00102
00103                                 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
00104 } LL_LPTIM_InitTypeDef;
00105
00106 /**
00107   * @}
00108   */
00109 #endif /* USE_FULL_LL_DRIVER */
00110
00111 /* Exported constants --------------------------------------------------------*/
00112 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
00113   * @{
00114   */
00115
00116 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
00117   * @brief    Flags defines which can be used with LL_LPTIM_ReadReg function
00118   * @{
00119   */
00120 #define LL_LPTIM_ISR_CMPM                     LPTIM_ISR_CMPM     /*!< Compare match */
00121 #define LL_LPTIM_ISR_ARRM                     LPTIM_ISR_ARRM     /*!< Autoreload match */
00122 #define LL_LPTIM_ISR_EXTTRIG                  LPTIM_ISR_EXTTRIG  /*!< External trigger edge event */
00123 #define LL_LPTIM_ISR_CMPOK                    LPTIM_ISR_CMPOK    /*!< Compare register update OK */
00124 #define LL_LPTIM_ISR_ARROK                    LPTIM_ISR_ARROK    /*!< Autoreload register update OK */
00125 #define LL_LPTIM_ISR_UP                       LPTIM_ISR_UP       /*!< Counter direction change down to up */
00126 #define LL_LPTIM_ISR_DOWN                     LPTIM_ISR_DOWN     /*!< Counter direction change up to down */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup LPTIM_LL_EC_IT IT Defines
00132   * @brief    IT defines which can be used with LL_LPTIM_ReadReg and  LL_LPTIM_WriteReg functions
00133   * @{
00134   */
00135 #define LL_LPTIM_IER_CMPMIE                   LPTIM_IER_CMPMIE       /*!< Compare match Interrupt Enable */
00136 #define LL_LPTIM_IER_ARRMIE                   LPTIM_IER_ARRMIE       /*!< Autoreload match Interrupt Enable */
00137 #define LL_LPTIM_IER_EXTTRIGIE                LPTIM_IER_EXTTRIGIE    /*!< External trigger valid edge Interrupt Enable */
00138 #define LL_LPTIM_IER_CMPOKIE                  LPTIM_IER_CMPOKIE      /*!< Compare register update OK Interrupt Enable */
00139 #define LL_LPTIM_IER_ARROKIE                  LPTIM_IER_ARROKIE      /*!< Autoreload register update OK Interrupt Enable */
00140 #define LL_LPTIM_IER_UPIE                     LPTIM_IER_UPIE         /*!< Direction change to UP Interrupt Enable */
00141 #define LL_LPTIM_IER_DOWNIE                   LPTIM_IER_DOWNIE       /*!< Direction change to down Interrupt Enable */
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
00147   * @{
00148   */
00149 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CR_CNTSTRT       /*!<LP Timer starts in continuous mode*/
00150 #define LL_LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CR_SNGSTRT       /*!<LP Tilmer starts in single mode*/
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
00156   * @{
00157   */
00158 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE        ((uint32_t)0x00000000U) /*!<Preload is disabled: registers are updated after each APB bus write access*/
00159 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFGR_PRELOAD      /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
00165   * @{
00166   */
00167 #define LL_LPTIM_COUNTER_MODE_INTERNAL        ((uint32_t)0x00000000U) /*!<The counter is incremented following each internal clock pulse*/
00168 #define LL_LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFGR_COUNTMODE    /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
00174   * @{
00175   */
00176 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM          ((uint32_t)0x00000000U) /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
00177 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFGR_WAVE         /*!<LPTIM  generates a Set Once waveform*/
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
00183   * @{
00184   */
00185 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR      ((uint32_t) 0x00000000U) /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
00186 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CFGR_WAVPOL        /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
00192   * @{
00193   */
00194 #define LL_LPTIM_PRESCALER_DIV1               ((uint32_t)0x000000U)                     /*!<Prescaler division factor is set to 1*/
00195 #define LL_LPTIM_PRESCALER_DIV2               LPTIM_CFGR_PRESC_0                        /*!<Prescaler division factor is set to 2*/
00196 #define LL_LPTIM_PRESCALER_DIV4               LPTIM_CFGR_PRESC_1                        /*!<Prescaler division factor is set to 4*/
00197 #define LL_LPTIM_PRESCALER_DIV8               (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
00198 #define LL_LPTIM_PRESCALER_DIV16              LPTIM_CFGR_PRESC_2                        /*!<Prescaler division factor is set to 16*/
00199 #define LL_LPTIM_PRESCALER_DIV32              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
00200 #define LL_LPTIM_PRESCALER_DIV64              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
00201 #define LL_LPTIM_PRESCALER_DIV128             LPTIM_CFGR_PRESC                          /*!<Prescaler division factor is set to 128*/
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
00207   * @{
00208   */
00209 #define LL_LPTIM_TRIG_SOURCE_GPIO             ((uint32_t)0x00000000U)                       /*!<External input trigger is connected to TIMx_ETR input*/
00210 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFGR_TRIGSEL_0                          /*!<External input trigger is connected to RTC Alarm A*/
00211 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFGR_TRIGSEL_1                          /*!<External input trigger is connected to RTC Alarm B*/
00212 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
00213 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFGR_TRIGSEL_2                          /*!<External input trigger is connected to RTC Tamper 2*/
00214 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
00215 #define LL_LPTIM_TRIG_SOURCE_COMP1            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
00216 #define LL_LPTIM_TRIG_SOURCE_COMP2            LPTIM_CFGR_TRIGSEL                            /*!<External input trigger is connected to COMP2 output*/
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
00222   * @{
00223   */
00224 #define LL_LPTIM_TRIG_FILTER_NONE             ((uint32_t)0x00000000U) /*!<Any trigger active level change is considered as a valid trigger*/
00225 #define LL_LPTIM_TRIG_FILTER_2                LPTIM_CFGR_TRGFLT_0     /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
00226 #define LL_LPTIM_TRIG_FILTER_4                LPTIM_CFGR_TRGFLT_1     /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
00227 #define LL_LPTIM_TRIG_FILTER_8                LPTIM_CFGR_TRGFLT       /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
00233   * @{
00234   */
00235 #define LL_LPTIM_TRIG_POLARITY_RISING         LPTIM_CFGR_TRIGEN_0    /*!<LPTIM counter starts when a rising edge is detected*/
00236 #define LL_LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFGR_TRIGEN_1    /*!<LPTIM counter starts when a falling edge is detected*/
00237 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN      /*!<LPTIM counter starts when a rising or a falling edge is detected*/
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
00243   * @{
00244   */
00245 #define LL_LPTIM_CLK_SOURCE_INTERNAL          ((uint32_t)0x00000000U) /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
00246 #define LL_LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFGR_CKSEL        /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
00252   * @{
00253   */
00254 #define LL_LPTIM_CLK_FILTER_NONE              ((uint32_t)0x00000000U) /*!<Any external clock signal level change is considered as a valid transition*/
00255 #define LL_LPTIM_CLK_FILTER_2                 LPTIM_CFGR_CKFLT_0      /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
00256 #define LL_LPTIM_CLK_FILTER_4                 LPTIM_CFGR_CKFLT_1      /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
00257 #define LL_LPTIM_CLK_FILTER_8                 LPTIM_CFGR_CKFLT        /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
00263   * @{
00264   */
00265 #define LL_LPTIM_CLK_POLARITY_RISING          ((uint32_t)0x00000000U) /*!< The rising edge is the active edge used for counting*/
00266 #define LL_LPTIM_CLK_POLARITY_FALLING         LPTIM_CFGR_CKPOL_0      /*!< The falling edge is the active edge used for counting*/
00267 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFGR_CKPOL_1      /*!< Both edges are active edges*/
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
00273   * @{
00274   */
00275 #define LL_LPTIM_ENCODER_MODE_RISING          ((uint32_t)0x00000000U) /*!< The rising edge is the active edge used for counting*/
00276 #define LL_LPTIM_ENCODER_MODE_FALLING         LPTIM_CFGR_CKPOL_0      /*!< The falling edge is the active edge used for counting*/
00277 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFGR_CKPOL_1      /*!< Both edges are active edges*/
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
00283   * @{
00284   */
00285
00286 #define LL_LPTIM_INPUT1_SRC_GPIO         ((uint32_t)0x00000000U) /*!< For LPTIM1 and LPTIM2 */
00287 #define LL_LPTIM_INPUT1_SRC_COMP1        LPTIM_OR_OR_0           /*!< For LPTIM1 and LPTIM2 */
00288 #define LL_LPTIM_INPUT1_SRC_COMP2        LPTIM_OR_OR_1           /*!< For LPTIM2 */
00289 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2  LPTIM_OR_OR             /*!< For LPTIM2 */
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
00295   * @{
00296   */
00297
00298 #define LL_LPTIM_INPUT2_SRC_GPIO         ((uint32_t)0x00000000U) /*!< For LPTIM1 */
00299 #define LL_LPTIM_INPUT2_SRC_COMP2        LPTIM_OR_OR_1           /*!< For LPTIM1 */
00300 /**
00301   * @}
00302   */
00303
00304 /**
00305   * @}
00306   */
00307
00308 /* Exported macro ------------------------------------------------------------*/
00309 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
00310   * @{
00311   */
00312
00313 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
00314   * @{
00315   */
00316
00317 /**
00318   * @brief  Write a value in LPTIM register
00319   * @param  __INSTANCE__ LPTIM Instance
00320   * @param  __REG__ Register to be written
00321   * @param  __VALUE__ Value to be written in the register
00322   * @retval None
00323   */
00324 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00325
00326 /**
00327   * @brief  Read a value in LPTIM register
00328   * @param  __INSTANCE__ LPTIM Instance
00329   * @param  __REG__ Register to be read
00330   * @retval Register value
00331   */
00332 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341
00342 /* Exported functions --------------------------------------------------------*/
00343 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
00344   * @{
00345   */
00346
00347 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
00348   * @{
00349   */
00350
00351 /**
00352   * @brief  Enable the LPTIM instance
00353   * @note After setting the ENABLE bit, a delay of two counter clock is needed
00354   *       before the LPTIM instance is actually enabled.
00355   * @rmtoll CR           ENABLE        LL_LPTIM_Enable
00356   * @param  LPTIMx Low-Power Timer instance
00357   * @retval None
00358   */
00359 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
00360 {
00361   SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
00362 }
00363
00364 /**
00365   * @brief  Disable the LPTIM instance
00366   * @rmtoll CR           ENABLE        LL_LPTIM_Disable
00367   * @param  LPTIMx Low-Power Timer instance
00368   * @retval None
00369   */
00370 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
00371 {
00372   CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
00373 }
00374
00375 /**
00376   * @brief  Indicates whether the LPTIM instance is enabled.
00377   * @rmtoll CR           ENABLE        LL_LPTIM_IsEnabled
00378   * @param  LPTIMx Low-Power Timer instance
00379   * @retval State of bit (1 or 0).
00380   */
00381 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
00382 {
00383   return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE));
00384 }
00385
00386 /**
00387   * @brief  Starts the LPTIM counter in the desired mode.
00388   * @note LPTIM instance must be enabled before starting the counter.
00389   * @note It is possible to change on the fly from One Shot mode to
00390   *       Continuous mode.
00391   * @rmtoll CR           CNTSTRT       LL_LPTIM_StartCounter\n
00392   *         CR           SNGSTRT       LL_LPTIM_StartCounter
00393   * @param  LPTIMx Low-Power Timer instance
00394   * @param  OperatingMode This parameter can be one of the following values:
00395   *         @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
00396   *         @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
00397   * @retval None
00398   */
00399 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
00400 {
00401   MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
00402 }
00403
00404 /**
00405   * @brief  Set the LPTIM registers update mode (enable/disable register preload)
00406   * @note This function must be called when the LPTIM instance is disabled.
00407   * @rmtoll CFGR         PRELOAD       LL_LPTIM_SetUpdateMode
00408   * @param  LPTIMx Low-Power Timer instance
00409   * @param  UpdateMode This parameter can be one of the following values:
00410   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
00411   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
00412   * @retval None
00413   */
00414 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
00415 {
00416   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
00417 }
00418
00419 /**
00420   * @brief  Get the LPTIM registers update mode
00421   * @rmtoll CFGR         PRELOAD       LL_LPTIM_GetUpdateMode
00422   * @param  LPTIMx Low-Power Timer instance
00423   * @retval Returned value can be one of the following values:
00424   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
00425   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
00426   */
00427 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
00428 {
00429   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
00430 }
00431
00432 /**
00433   * @brief  Set the auto reload value
00434   * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
00435   * @note After a write to the LPTIMx_ARR register a new write operation to the
00436   *       same register can only be performed when the previous write operation
00437   *       is completed. Any successive write before  the ARROK flag be set, will
00438   *       lead to unpredictable results.
00439   * @note autoreload value be strictly greater than the compare value.
00440   * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload
00441   * @param  LPTIMx Low-Power Timer instance
00442   * @param  AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
00443   * @retval None
00444   */
00445 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
00446 {
00447   MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
00448 }
00449
00450 /**
00451   * @brief  Get actual auto reload value
00452   * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload
00453   * @param  LPTIMx Low-Power Timer instance
00454   * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
00455   */
00456 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
00457 {
00458   return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
00459 }
00460
00461 /**
00462   * @brief  Set the compare value
00463   * @note After a write to the LPTIMx_CMP register a new write operation to the
00464   *       same register can only be performed when the previous write operation
00465   *       is completed. Any successive write before the CMPOK flag be set, will
00466   *       lead to unpredictable results.
00467   * @rmtoll CMP          CMP           LL_LPTIM_SetCompare
00468   * @param  LPTIMx Low-Power Timer instance
00469   * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
00470   * @retval None
00471   */
00472 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
00473 {
00474   MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
00475 }
00476
00477 /**
00478   * @brief  Get actual compare value
00479   * @rmtoll CMP          CMP           LL_LPTIM_GetCompare
00480   * @param  LPTIMx Low-Power Timer instance
00481   * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
00482   */
00483 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
00484 {
00485   return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
00486 }
00487
00488 /**
00489   * @brief  Get actual counter value
00490   * @note When the LPTIM instance is running with an asynchronous clock, reading
00491   *       the LPTIMx_CNT register may return unreliable values. So in this case
00492   *       it is necessary to perform two consecutive read accesses and verify
00493   *       that the two returned values are identical.
00494   * @rmtoll CNT          CNT           LL_LPTIM_GetCounter
00495   * @param  LPTIMx Low-Power Timer instance
00496   * @retval Counter value
00497   */
00498 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
00499 {
00500   return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
00501 }
00502
00503 /**
00504   * @brief  Set the counter mode (selection of the LPTIM counter clock source).
00505   * @note The counter mode can be set only when the LPTIM instance is disabled.
00506   * @rmtoll CFGR         COUNTMODE     LL_LPTIM_SetCounterMode
00507   * @param  LPTIMx Low-Power Timer instance
00508   * @param  CounterMode This parameter can be one of the following values:
00509   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
00510   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
00511   * @retval None
00512   */
00513 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
00514 {
00515   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
00516 }
00517
00518 /**
00519   * @brief  Get the counter mode
00520   * @rmtoll CFGR         COUNTMODE     LL_LPTIM_GetCounterMode
00521   * @param  LPTIMx Low-Power Timer instance
00522   * @retval Returned value can be one of the following values:
00523   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
00524   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
00525   */
00526 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
00527 {
00528   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
00529 }
00530
00531 /**
00532   * @brief  Configure the LPTIM instance output (LPTIMx_OUT)
00533   * @note This function must be called when the LPTIM instance is disabled.
00534   * @note Regarding the LPTIM output polarity the change takes effect
00535   *       immediately, so the output default value will change immediately after
00536   *       the polarity is re-configured, even before the timer is enabled.
00537   * @rmtoll CFGR         WAVE          LL_LPTIM_ConfigOutput\n
00538   *         CFGR         WAVPOL        LL_LPTIM_ConfigOutput
00539   * @param  LPTIMx Low-Power Timer instance
00540   * @param  Waveform This parameter can be one of the following values:
00541   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00542   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00543   * @param  Polarity This parameter can be one of the following values:
00544   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00545   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00546   * @retval None
00547   */
00548 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
00549 {
00550   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
00551 }
00552
00553 /**
00554   * @brief  Set  waveform shape
00555   * @rmtoll CFGR         WAVE          LL_LPTIM_SetWaveform
00556   * @param  LPTIMx Low-Power Timer instance
00557   * @param  Waveform This parameter can be one of the following values:
00558   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00559   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00560   * @retval None
00561   */
00562 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
00563 {
00564   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
00565 }
00566
00567 /**
00568   * @brief  Get actual waveform shape
00569   * @rmtoll CFGR         WAVE          LL_LPTIM_GetWaveform
00570   * @param  LPTIMx Low-Power Timer instance
00571   * @retval Returned value can be one of the following values:
00572   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00573   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00574   */
00575 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
00576 {
00577   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
00578 }
00579
00580 /**
00581   * @brief  Set  output polarity
00582   * @rmtoll CFGR         WAVPOL        LL_LPTIM_SetPolarity
00583   * @param  LPTIMx Low-Power Timer instance
00584   * @param  Polarity This parameter can be one of the following values:
00585   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00586   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00587   * @retval None
00588   */
00589 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
00590 {
00591   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
00592 }
00593
00594 /**
00595   * @brief  Get actual output polarity
00596   * @rmtoll CFGR         WAVPOL        LL_LPTIM_GetPolarity
00597   * @param  LPTIMx Low-Power Timer instance
00598   * @retval Returned value can be one of the following values:
00599   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00600   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00601   */
00602 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
00603 {
00604   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
00605 }
00606
00607 /**
00608   * @brief  Set actual prescaler division ratio.
00609   * @note This function must be called when the LPTIM instance is disabled.
00610   * @note When the LPTIM is configured to be clocked by an internal clock source
00611   *       and the LPTIM counter is configured to be updated by active edges
00612   *       detected on the LPTIM external Input1, the internal clock provided to
00613   *       the LPTIM must be not be prescaled.
00614   * @rmtoll CFGR         PRESC         LL_LPTIM_SetPrescaler
00615   * @param  LPTIMx Low-Power Timer instance
00616   * @param  Prescaler This parameter can be one of the following values:
00617   *         @arg @ref LL_LPTIM_PRESCALER_DIV1
00618   *         @arg @ref LL_LPTIM_PRESCALER_DIV2
00619   *         @arg @ref LL_LPTIM_PRESCALER_DIV4
00620   *         @arg @ref LL_LPTIM_PRESCALER_DIV8
00621   *         @arg @ref LL_LPTIM_PRESCALER_DIV16
00622   *         @arg @ref LL_LPTIM_PRESCALER_DIV32
00623   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
00624   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
00625   * @retval None
00626   */
00627 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
00628 {
00629   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
00630 }
00631
00632 /**
00633   * @brief  Get actual prescaler division ratio.
00634   * @rmtoll CFGR         PRESC         LL_LPTIM_GetPrescaler
00635   * @param  LPTIMx Low-Power Timer instance
00636   * @retval Returned value can be one of the following values:
00637   *         @arg @ref LL_LPTIM_PRESCALER_DIV1
00638   *         @arg @ref LL_LPTIM_PRESCALER_DIV2
00639   *         @arg @ref LL_LPTIM_PRESCALER_DIV4
00640   *         @arg @ref LL_LPTIM_PRESCALER_DIV8
00641   *         @arg @ref LL_LPTIM_PRESCALER_DIV16
00642   *         @arg @ref LL_LPTIM_PRESCALER_DIV32
00643   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
00644   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
00645   */
00646 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
00647 {
00648   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
00649 }
00650
00651 /**
00652   * @brief  Set LPTIM input 1 source (default GPIO).
00653   * @rmtoll OR         OR_0         LL_LPTIM_SetInput1Src
00654   * @rmtoll OR         OR_1         LL_LPTIM_SetInput1Src
00655   * @param  LPTIMx Low-Power Timer instance
00656   * @param  Src This parameter can be one of the following values:
00657   *         @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
00658   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
00659   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
00660   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
00661   * @retval None
00662   */
00663 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
00664 {
00665   WRITE_REG(LPTIMx->OR, Src);
00666 }
00667
00668 /**
00669   * @brief  Set LPTIM input 2 source (default GPIO).
00670   * @rmtoll OR         OR_0         LL_LPTIM_SetInput2Src
00671   * @param  LPTIMx Low-Power Timer instance
00672   * @param  Src This parameter can be one of the following values:
00673   *         @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
00674   *         @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
00675   * @retval None
00676   */
00677 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
00678 {
00679   WRITE_REG(LPTIMx->OR, Src);
00680 }
00681
00682 /**
00683   * @}
00684   */
00685
00686 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
00687   * @{
00688   */
00689
00690 /**
00691   * @brief  Enable the timeout function
00692   * @note This function must be called when the LPTIM instance is disabled.
00693   * @note The first trigger event will start the timer, any successive trigger
00694   *       event will reset the counter and the timer will restart.
00695   * @note The timeout value corresponds to the compare value; if no trigger
00696   *       occurs within the expected time frame, the MCU is waked-up by the
00697   *       compare match event.
00698   * @rmtoll CFGR         TIMOUT        LL_LPTIM_EnableTimeout
00699   * @param  LPTIMx Low-Power Timer instance
00700   * @retval None
00701   */
00702 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
00703 {
00704   SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
00705 }
00706
00707 /**
00708   * @brief  Disable the timeout function
00709   * @note This function must be called when the LPTIM instance is disabled.
00710   * @note A trigger event arriving when the timer is already started will be
00711   *       ignored.
00712   * @rmtoll CFGR         TIMOUT        LL_LPTIM_DisableTimeout
00713   * @param  LPTIMx Low-Power Timer instance
00714   * @retval None
00715   */
00716 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
00717 {
00718   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
00719 }
00720
00721 /**
00722   * @brief  Indicate whether the timeout function is enabled.
00723   * @rmtoll CFGR         TIMOUT        LL_LPTIM_IsEnabledTimeout
00724   * @param  LPTIMx Low-Power Timer instance
00725   * @retval State of bit (1 or 0).
00726   */
00727 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
00728 {
00729   return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT));
00730 }
00731
00732 /**
00733   * @brief  Start the LPTIM counter
00734   * @note This function must be called when the LPTIM instance is disabled.
00735   * @rmtoll CFGR         TRIGEN        LL_LPTIM_TrigSw
00736   * @param  LPTIMx Low-Power Timer instance
00737   * @retval None
00738   */
00739 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
00740 {
00741   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
00742 }
00743
00744 /**
00745   * @brief  Configure the external trigger used as a trigger event for the LPTIM.
00746   * @note This function must be called when the LPTIM instance is disabled.
00747   * @note An internal clock source must be present when a digital filter is
00748   *       required for the trigger.
00749   * @rmtoll CFGR         TRIGSEL       LL_LPTIM_ConfigTrigger\n
00750   *         CFGR         TRGFLT        LL_LPTIM_ConfigTrigger\n
00751   *         CFGR         TRIGEN        LL_LPTIM_ConfigTrigger
00752   * @param  LPTIMx Low-Power Timer instance
00753   * @param  Source This parameter can be one of the following values:
00754   *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
00755   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
00756   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
00757   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
00758   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
00759   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
00760   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
00761   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
00762   * @param  Filter This parameter can be one of the following values:
00763   *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
00764   *         @arg @ref LL_LPTIM_TRIG_FILTER_2
00765   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
00766   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
00767   * @param  Polarity This parameter can be one of the following values:
00768   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
00769   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
00770   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
00771   * @retval None
00772   */
00773 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
00774 {
00775   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
00776 }
00777
00778 /**
00779   * @brief  Get actual external trigger source.
00780   * @rmtoll CFGR         TRIGSEL       LL_LPTIM_GetTriggerSource
00781   * @param  LPTIMx Low-Power Timer instance
00782   * @retval Returned value can be one of the following values:
00783   *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
00784   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
00785   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
00786   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
00787   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
00788   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
00789   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
00790   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
00791   */
00792 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
00793 {
00794   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
00795 }
00796
00797 /**
00798   * @brief  Get actual external trigger filter.
00799   * @rmtoll CFGR         TRGFLT        LL_LPTIM_GetTriggerFilter
00800   * @param  LPTIMx Low-Power Timer instance
00801   * @retval Returned value can be one of the following values:
00802   *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
00803   *         @arg @ref LL_LPTIM_TRIG_FILTER_2
00804   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
00805   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
00806   */
00807 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
00808 {
00809   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
00810 }
00811
00812 /**
00813   * @brief  Get actual external trigger polarity.
00814   * @rmtoll CFGR         TRIGEN        LL_LPTIM_GetTriggerPolarity
00815   * @param  LPTIMx Low-Power Timer instance
00816   * @retval Returned value can be one of the following values:
00817   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
00818   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
00819   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
00820   */
00821 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
00822 {
00823   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
00824 }
00825
00826 /**
00827   * @}
00828   */
00829
00830 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
00831   * @{
00832   */
00833
00834 /**
00835   * @brief  Set the source of the clock used by the LPTIM instance.
00836   * @note This function must be called when the LPTIM instance is disabled.
00837   * @rmtoll CFGR         CKSEL         LL_LPTIM_SetClockSource
00838   * @param  LPTIMx Low-Power Timer instance
00839   * @param  ClockSource This parameter can be one of the following values:
00840   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
00841   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
00842   * @retval None
00843   */
00844 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
00845 {
00846   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
00847 }
00848
00849 /**
00850   * @brief  Get actual LPTIM instance clock source.
00851   * @rmtoll CFGR         CKSEL         LL_LPTIM_GetClockSource
00852   * @param  LPTIMx Low-Power Timer instance
00853   * @retval Returned value can be one of the following values:
00854   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
00855   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
00856   */
00857 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
00858 {
00859   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
00860 }
00861
00862 /**
00863   * @brief  Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
00864   * @note This function must be called when the LPTIM instance is disabled.
00865   * @note When both external clock signal edges are considered active ones,
00866   *       the LPTIM must also be clocked by an internal clock source with a
00867   *       frequency equal to at least four times the external clock frequency.
00868   * @note An internal clock source must be present when a digital filter is
00869   *       required for external clock.
00870   * @rmtoll CFGR         CKFLT         LL_LPTIM_ConfigClock\n
00871   *         CFGR         CKPOL         LL_LPTIM_ConfigClock
00872   * @param  LPTIMx Low-Power Timer instance
00873   * @param  ClockFilter This parameter can be one of the following values:
00874   *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
00875   *         @arg @ref LL_LPTIM_CLK_FILTER_2
00876   *         @arg @ref LL_LPTIM_CLK_FILTER_4
00877   *         @arg @ref LL_LPTIM_CLK_FILTER_8
00878   * @param  ClockPolarity This parameter can be one of the following values:
00879   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
00880   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
00881   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
00882   * @retval None
00883   */
00884 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
00885 {
00886   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
00887 }
00888
00889 /**
00890   * @brief  Get actual clock polarity
00891   * @rmtoll CFGR         CKPOL         LL_LPTIM_GetClockPolarity
00892   * @param  LPTIMx Low-Power Timer instance
00893   * @retval Returned value can be one of the following values:
00894   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
00895   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
00896   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
00897   */
00898 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
00899 {
00900   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
00901 }
00902
00903 /**
00904   * @brief  Get actual clock digital filter
00905   * @rmtoll CFGR         CKFLT         LL_LPTIM_GetClockFilter
00906   * @param  LPTIMx Low-Power Timer instance
00907   * @retval Returned value can be one of the following values:
00908   *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
00909   *         @arg @ref LL_LPTIM_CLK_FILTER_2
00910   *         @arg @ref LL_LPTIM_CLK_FILTER_4
00911   *         @arg @ref LL_LPTIM_CLK_FILTER_8
00912   */
00913 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
00914 {
00915   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
00916 }
00917
00918 /**
00919   * @}
00920   */
00921
00922 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
00923   * @{
00924   */
00925
00926 /**
00927   * @brief  Configure the encoder mode.
00928   * @note This function must be called when the LPTIM instance is disabled.
00929   * @rmtoll CFGR         CKPOL         LL_LPTIM_SetEncoderMode
00930   * @param  LPTIMx Low-Power Timer instance
00931   * @param  EncoderMode This parameter can be one of the following values:
00932   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
00933   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
00934   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
00935   * @retval None
00936   */
00937 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
00938 {
00939   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
00940 }
00941
00942 /**
00943   * @brief  Get actual encoder mode.
00944   * @rmtoll CFGR         CKPOL         LL_LPTIM_GetEncoderMode
00945   * @param  LPTIMx Low-Power Timer instance
00946   * @retval Returned value can be one of the following values:
00947   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
00948   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
00949   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
00950   */
00951 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
00952 {
00953   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
00954 }
00955
00956 /**
00957   * @brief  Enable the encoder mode
00958   * @note This function must be called when the LPTIM instance is disabled.
00959   * @note In this mode the LPTIM instance must be clocked by an internal clock
00960   *       source. Also, the prescaler division ratio must be equal to 1.
00961   * @note LPTIM instance must be configured in continuous mode prior enabling
00962   *       the encoder mode.
00963   * @rmtoll CFGR         ENC           LL_LPTIM_EnableEncoderMode
00964   * @param  LPTIMx Low-Power Timer instance
00965   * @retval None
00966   */
00967 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
00968 {
00969   SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
00970 }
00971
00972 /**
00973   * @brief  Disable the encoder mode
00974   * @note This function must be called when the LPTIM instance is disabled.
00975   * @rmtoll CFGR         ENC           LL_LPTIM_DisableEncoderMode
00976   * @param  LPTIMx Low-Power Timer instance
00977   * @retval None
00978   */
00979 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
00980 {
00981   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
00982 }
00983
00984 /**
00985   * @brief  Indicates whether the LPTIM operates in encoder mode.
00986   * @rmtoll CFGR         ENC           LL_LPTIM_IsEnabledEncoderMode
00987   * @param  LPTIMx Low-Power Timer instance
00988   * @retval State of bit (1 or 0).
00989   */
00990 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
00991 {
00992   return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC));
00993 }
00994
00995 /**
00996   * @}
00997   */
00998
00999 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
01000   * @{
01001   */
01002
01003 /**
01004   * @brief  Clear the compare match flag (CMPMCF)
01005   * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFLAG_CMPM
01006   * @param  LPTIMx Low-Power Timer instance
01007   * @retval None
01008   */
01009 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
01010 {
01011   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
01012 }
01013
01014 /**
01015   * @brief  Inform application whether a compare match interrupt has occurred.
01016   * @rmtoll ISR          CMPM          LL_LPTIM_IsActiveFlag_CMPM
01017   * @param  LPTIMx Low-Power Timer instance
01018   * @retval State of bit (1 or 0).
01019   */
01020 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
01021 {
01022   return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM));
01023 }
01024
01025 /**
01026   * @brief  Clear the autoreload match flag (ARRMCF)
01027   * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFLAG_ARRM
01028   * @param  LPTIMx Low-Power Timer instance
01029   * @retval None
01030   */
01031 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
01032 {
01033   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
01034 }
01035
01036 /**
01037   * @brief  Inform application whether a autoreload match interrupt has occured.
01038   * @rmtoll ISR          ARRM          LL_LPTIM_IsActiveFlag_ARRM
01039   * @param  LPTIMx Low-Power Timer instance
01040   * @retval State of bit (1 or 0).
01041   */
01042 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
01043 {
01044   return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM));
01045 }
01046
01047 /**
01048   * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).
01049   * @rmtoll ICR          EXTTRIGCF     LL_LPTIM_ClearFlag_EXTTRIG
01050   * @param  LPTIMx Low-Power Timer instance
01051   * @retval None
01052   */
01053 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01054 {
01055   SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
01056 }
01057
01058 /**
01059   * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.
01060   * @rmtoll ISR          EXTTRIG       LL_LPTIM_IsActiveFlag_EXTTRIG
01061   * @param  LPTIMx Low-Power Timer instance
01062   * @retval State of bit (1 or 0).
01063   */
01064 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01065 {
01066   return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG));
01067 }
01068
01069 /**
01070   * @brief  Clear the compare register update interrupt flag (CMPOKCF).
01071   * @rmtoll ICR          CMPOKCF       LL_LPTIM_ClearFlag_CMPOK
01072   * @param  LPTIMx Low-Power Timer instance
01073   * @retval None
01074   */
01075 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
01076 {
01077   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
01078 }
01079
01080 /**
01081   * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
01082   * @rmtoll ISR          CMPOK         LL_LPTIM_IsActiveFlag_CMPOK
01083   * @param  LPTIMx Low-Power Timer instance
01084   * @retval State of bit (1 or 0).
01085   */
01086 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
01087 {
01088   return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK));
01089 }
01090
01091 /**
01092   * @brief  Clear the autoreload register update interrupt flag (ARROKCF).
01093   * @rmtoll ICR          ARROKCF       LL_LPTIM_ClearFlag_ARROK
01094   * @param  LPTIMx Low-Power Timer instance
01095   * @retval None
01096   */
01097 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
01098 {
01099   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
01100 }
01101
01102 /**
01103   * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
01104   * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK
01105   * @param  LPTIMx Low-Power Timer instance
01106   * @retval State of bit (1 or 0).
01107   */
01108 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
01109 {
01110   return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK));
01111 }
01112
01113 /**
01114   * @brief  Clear the counter direction change to up interrupt flag (UPCF).
01115   * @rmtoll ICR          UPCF          LL_LPTIM_ClearFlag_UP
01116   * @param  LPTIMx Low-Power Timer instance
01117   * @retval None
01118   */
01119 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
01120 {
01121   SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
01122 }
01123
01124 /**
01125   * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
01126   * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP
01127   * @param  LPTIMx Low-Power Timer instance
01128   * @retval State of bit (1 or 0).
01129   */
01130 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
01131 {
01132   return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP));
01133 }
01134
01135 /**
01136   * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).
01137   * @rmtoll ICR          DOWNCF        LL_LPTIM_ClearFlag_DOWN
01138   * @param  LPTIMx Low-Power Timer instance
01139   * @retval None
01140   */
01141 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
01142 {
01143   SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
01144 }
01145
01146 /**
01147   * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
01148   * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN
01149   * @param  LPTIMx Low-Power Timer instance
01150   * @retval State of bit (1 or 0).
01151   */
01152 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
01153 {
01154   return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN));
01155 }
01156
01157 /**
01158   * @}
01159   */
01160
01161 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
01162   * @{
01163   */
01164
01165 /**
01166   * @brief  Enable compare match interrupt (CMPMIE).
01167   * @rmtoll IER          CMPMIE        LL_LPTIM_EnableIT_CMPM
01168   * @param  LPTIMx Low-Power Timer instance
01169   * @retval None
01170   */
01171 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
01172 {
01173   SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
01174 }
01175
01176 /**
01177   * @brief  Disable compare match interrupt (CMPMIE).
01178   * @rmtoll IER          CMPMIE        LL_LPTIM_DisableIT_CMPM
01179   * @param  LPTIMx Low-Power Timer instance
01180   * @retval None
01181   */
01182 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
01183 {
01184   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
01185 }
01186
01187 /**
01188   * @brief  Indicates whether the compare match interrupt (CMPMIE) is enabled.
01189   * @rmtoll IER          CMPMIE        LL_LPTIM_IsEnabledIT_CMPM
01190   * @param  LPTIMx Low-Power Timer instance
01191   * @retval State of bit (1 or 0).
01192   */
01193 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
01194 {
01195   return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE));
01196 }
01197
01198 /**
01199   * @brief  Enable autoreload match interrupt (ARRMIE).
01200   * @rmtoll IER          ARRMIE        LL_LPTIM_EnableIT_ARRM
01201   * @param  LPTIMx Low-Power Timer instance
01202   * @retval None
01203   */
01204 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
01205 {
01206   SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
01207 }
01208
01209 /**
01210   * @brief  Disable autoreload match interrupt (ARRMIE).
01211   * @rmtoll IER          ARRMIE        LL_LPTIM_DisableIT_ARRM
01212   * @param  LPTIMx Low-Power Timer instance
01213   * @retval None
01214   */
01215 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
01216 {
01217   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
01218 }
01219
01220 /**
01221   * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
01222   * @rmtoll IER          ARRMIE        LL_LPTIM_IsEnabledIT_ARRM
01223   * @param  LPTIMx Low-Power Timer instance
01224   * @retval State of bit (1 or 0).
01225   */
01226 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
01227 {
01228   return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE));
01229 }
01230
01231 /**
01232   * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).
01233   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_EnableIT_EXTTRIG
01234   * @param  LPTIMx Low-Power Timer instance
01235   * @retval None
01236   */
01237 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01238 {
01239   SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
01240 }
01241
01242 /**
01243   * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).
01244   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_DisableIT_EXTTRIG
01245   * @param  LPTIMx Low-Power Timer instance
01246   * @retval None
01247   */
01248 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01249 {
01250   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
01251 }
01252
01253 /**
01254   * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
01255   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_IsEnabledIT_EXTTRIG
01256   * @param  LPTIMx Low-Power Timer instance
01257   * @retval State of bit (1 or 0).
01258   */
01259 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01260 {
01261   return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE));
01262 }
01263
01264 /**
01265   * @brief  Enable compare register write completed interrupt (CMPOKIE).
01266   * @rmtoll IER          CMPOKIE       LL_LPTIM_EnableIT_CMPOK
01267   * @param  LPTIMx Low-Power Timer instance
01268   * @retval None
01269   */
01270 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01271 {
01272   SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
01273 }
01274
01275 /**
01276   * @brief  Disable compare register write completed interrupt (CMPOKIE).
01277   * @rmtoll IER          CMPOKIE       LL_LPTIM_DisableIT_CMPOK
01278   * @param  LPTIMx Low-Power Timer instance
01279   * @retval None
01280   */
01281 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01282 {
01283   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
01284 }
01285
01286 /**
01287   * @brief  Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
01288   * @rmtoll IER          CMPOKIE       LL_LPTIM_IsEnabledIT_CMPOK
01289   * @param  LPTIMx Low-Power Timer instance
01290   * @retval State of bit (1 or 0).
01291   */
01292 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01293 {
01294   return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE));
01295 }
01296
01297 /**
01298   * @brief  Enable autoreload register write completed interrupt (ARROKIE).
01299   * @rmtoll IER          ARROKIE       LL_LPTIM_EnableIT_ARROK
01300   * @param  LPTIMx Low-Power Timer instance
01301   * @retval None
01302   */
01303 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
01304 {
01305   SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
01306 }
01307
01308 /**
01309   * @brief  Disable autoreload register write completed interrupt (ARROKIE).
01310   * @rmtoll IER          ARROKIE       LL_LPTIM_DisableIT_ARROK
01311   * @param  LPTIMx Low-Power Timer instance
01312   * @retval None
01313   */
01314 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
01315 {
01316   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
01317 }
01318
01319 /**
01320   * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
01321   * @rmtoll IER          ARROKIE       LL_LPTIM_IsEnabledIT_ARROK
01322   * @param  LPTIMx Low-Power Timer instance
01323   * @retval State of bit (1 or 0).
01324   */
01325 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
01326 {
01327   return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE));
01328 }
01329
01330 /**
01331   * @brief  Enable direction change to up interrupt (UPIE).
01332   * @rmtoll IER          UPIE          LL_LPTIM_EnableIT_UP
01333   * @param  LPTIMx Low-Power Timer instance
01334   * @retval None
01335   */
01336 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
01337 {
01338   SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
01339 }
01340
01341 /**
01342   * @brief  Disable direction change to up interrupt (UPIE).
01343   * @rmtoll IER          UPIE          LL_LPTIM_DisableIT_UP
01344   * @param  LPTIMx Low-Power Timer instance
01345   * @retval None
01346   */
01347 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
01348 {
01349   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
01350 }
01351
01352 /**
01353   * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.
01354   * @rmtoll IER          UPIE          LL_LPTIM_IsEnabledIT_UP
01355   * @param  LPTIMx Low-Power Timer instance
01356   * @retval State of bit (1 or 0).
01357   */
01358 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
01359 {
01360   return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE));
01361 }
01362
01363 /**
01364   * @brief  Enable direction change to down interrupt (DOWNIE).
01365   * @rmtoll IER          DOWNIE        LL_LPTIM_EnableIT_DOWN
01366   * @param  LPTIMx Low-Power Timer instance
01367   * @retval None
01368   */
01369 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
01370 {
01371   SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
01372 }
01373
01374 /**
01375   * @brief  Disable direction change to down interrupt (DOWNIE).
01376   * @rmtoll IER          DOWNIE        LL_LPTIM_DisableIT_DOWN
01377   * @param  LPTIMx Low-Power Timer instance
01378   * @retval None
01379   */
01380 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
01381 {
01382   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
01383 }
01384
01385 /**
01386   * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
01387   * @rmtoll IER          DOWNIE        LL_LPTIM_IsEnabledIT_DOWN
01388   * @param  LPTIMx Low-Power Timer instance
01389   * @retval State of bit (1 or 0).
01390   */
01391 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
01392 {
01393   return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE));
01394 }
01395
01396 /**
01397   * @}
01398   */
01399
01400 #if defined(USE_FULL_LL_DRIVER)
01401 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
01402   * @{
01403   */
01404
01405 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
01406 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
01407 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
01408 /**
01409   * @}
01410   */
01411 #endif /* USE_FULL_LL_DRIVER */
01412
01413 /**
01414   * @}
01415   */
01416
01417 /**
01418   * @}
01419   */
01420
01421 #endif /* LPTIM1 || LPTIM2 */
01422
01423 /**
01424   * @}
01425   */
01426
01427 #ifdef __cplusplus
01428 }
01429 #endif
01430
01431 #endif /* __STM32L4xx_LL_LPTIM_H */
01432
01433 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_lpuart.c Source File

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stm32l4xx_ll_lpuart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_lpuart.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   LPUART LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_lpuart.h"
00041 #include "stm32l4xx_ll_rcc.h"
00042 #include "stm32l4xx_ll_bus.h"
00043 #ifdef  USE_FULL_ASSERT
00044 #include "stm32_assert.h"
00045 #else
00046 #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (LPUART1)
00054
00055 /** @addtogroup LPUART_LL
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /** @addtogroup LPUART_LL_Private_Constants
00063   * @{
00064   */
00065
00066 /**
00067   * @}
00068   */
00069
00070
00071 /* Private macros ------------------------------------------------------------*/
00072 /** @addtogroup LPUART_LL_Private_Macros
00073   * @{
00074   */
00075
00076 /* Check of parameters for configuration of LPUART registers                  */
00077
00078 /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */
00079 /*              value :                                                       */
00080 /*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */
00081 /*                - LPUART_BRR register value should be >= 0x300              */
00082 /*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */
00083 /*              Baudrate specified by the user should belong to [8, 26000000].*/
00084 #define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 26000000U) && ((__BAUDRATE__) >= 8U))
00085
00086 #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
00087                                         || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
00088                                         || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
00089                                         || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
00090
00091 #define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
00092                                      || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
00093                                      || ((__VALUE__) == LL_LPUART_PARITY_ODD))
00094
00095 #define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
00096                                         || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
00097                                         || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
00098
00099 #define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
00100                                        || ((__VALUE__) == LL_LPUART_STOPBITS_2))
00101
00102 #define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
00103                                        || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
00104                                        || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
00105                                        || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
00106
00107 /**
00108   * @}
00109   */
00110
00111 /* Private function prototypes -----------------------------------------------*/
00112
00113 /* Exported functions --------------------------------------------------------*/
00114 /** @addtogroup LPUART_LL_Exported_Functions
00115   * @{
00116   */
00117
00118 /** @addtogroup LPUART_LL_EF_Init
00119   * @{
00120   */
00121
00122 /**
00123   * @brief  De-initialize LPUART registers (Registers restored to their default values).
00124   * @param  LPUARTx LPUART Instance
00125   * @retval An ErrorStatus enumeration value:
00126   *          - SUCCESS: LPUART registers are de-initialized
00127   *          - ERROR: not applicable
00128   */
00129 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
00130 {
00131   ErrorStatus status = SUCCESS;
00132
00133   /* Check the parameters */
00134   assert_param(IS_LPUART_INSTANCE(LPUARTx));
00135
00136   /* Force reset of LPUART peripheral */
00137   LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1);
00138
00139   /* Release reset of LPUART peripheral */
00140   LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1);
00141
00142   return (status);
00143 }
00144
00145 /**
00146   * @brief  Initialize LPUART registers according to the specified
00147   *         parameters in LPUART_InitStruct.
00148   * @note   As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0),
00149   *         LPUART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00150   * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
00151   * @param  LPUARTx LPUART Instance
00152   * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
00153   *         that contains the configuration information for the specified LPUART peripheral.
00154   * @retval An ErrorStatus enumeration value:
00155   *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
00156   *          - ERROR: Problem occurred during LPUART Registers initialization
00157   */
00158 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
00159 {
00160   ErrorStatus status = ERROR;
00161   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
00162
00163   /* Check the parameters */
00164   assert_param(IS_LPUART_INSTANCE(LPUARTx));
00165   assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
00166   assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
00167   assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
00168   assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
00169   assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
00170   assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
00171
00172   /* LPUART needs to be in disabled state, in order to be able to configure some bits in
00173      CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
00174   if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
00175   {
00176     /*---------------------------- LPUART CR1 Configuration -----------------------
00177      * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
00178      * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
00179      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
00180      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
00181      */
00182     MODIFY_REG(LPUARTx->CR1,
00183                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
00184                (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
00185
00186     /*---------------------------- LPUART CR2 Configuration -----------------------
00187      * Configure LPUARTx CR2 (Stop bits) with parameters:
00188      * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
00189      */
00190     LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
00191
00192     /*---------------------------- LPUART CR3 Configuration -----------------------
00193      * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
00194      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->HardwareFlowControl value.
00195      */
00196     LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
00197
00198     /*---------------------------- LPUART BRR Configuration -----------------------
00199      * Retrieve Clock frequency used for LPUART Peripheral
00200      */
00201     periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
00202
00203     /* Configure the LPUART Baud Rate :
00204        - valid baud rate value (different from 0) is required
00205        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00206     */
00207     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00208         && (LPUART_InitStruct->BaudRate != 0U))
00209     {
00210       status = SUCCESS;
00211       LL_LPUART_SetBaudRate(LPUARTx,
00212                             periphclk,
00213                             LPUART_InitStruct->BaudRate);
00214     }
00215   }
00216
00217   return (status);
00218 }
00219
00220 /**
00221   * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
00222   * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
00223   *                          whose fields will be set to default values.
00224   * @retval None
00225   */
00226
00227 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
00228 {
00229   /* Set LPUART_InitStruct fields to default values */
00230   LPUART_InitStruct->BaudRate            = 9600U;
00231   LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
00232   LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
00233   LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
00234   LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;
00235   LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
00236 }
00237
00238 /**
00239   * @}
00240   */
00241
00242 /**
00243   * @}
00244   */
00245
00246 /**
00247   * @}
00248   */
00249
00250 #endif /* defined (LPUART1) */
00251
00252 /**
00253   * @}
00254   */
00255
00256 #endif /* USE_FULL_LL_DRIVER */
00257
00258 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00259
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_lpuart.h Source File

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stm32l4xx_ll_lpuart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_lpuart.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of LPUART LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_LPUART_H
00040 #define __STM32L4xx_LL_LPUART_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (LPUART1)
00054
00055 /** @defgroup LPUART_LL LPUART
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
00064   * @{
00065   */
00066
00067 /* Defines used for the bit position in the register and perform offsets*/
00068 #define LPUART_POSITION_CR1_DEDT      (uint32_t)POSITION_VAL(USART_CR1_DEDT)
00069 #define LPUART_POSITION_CR1_DEAT      (uint32_t)POSITION_VAL(USART_CR1_DEAT)
00070 #define LPUART_POSITION_CR2_ADD       (uint32_t)POSITION_VAL(USART_CR2_ADD)
00071
00072 /* Defines used in Baud Rate related macros and corresponding register setting computation */
00073 #define LPUART_LPUARTDIV_FREQ_MUL     (uint32_t)(256U)
00074 #define LPUART_BRR_MASK               (uint32_t)(0x000FFFFFU)
00075 #define LPUART_BRR_MIN_VALUE          (uint32_t)(0x00000300U)
00076 /**
00077   * @}
00078   */
00079
00080
00081 /* Private macros ------------------------------------------------------------*/
00082 #if defined(USE_FULL_LL_DRIVER)
00083 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
00084   * @{
00085   */
00086 /**
00087   * @}
00088   */
00089 #endif /*USE_FULL_LL_DRIVER*/
00090
00091 /* Exported types ------------------------------------------------------------*/
00092 #if defined(USE_FULL_LL_DRIVER)
00093 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
00094   * @{
00095   */
00096
00097 /**
00098   * @brief LL LPUART Init Structure definition
00099   */
00100 typedef struct
00101 {
00102   uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
00103
00104                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
00105
00106   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00107                                            This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
00108
00109                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
00110
00111   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00112                                            This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
00113
00114                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
00115
00116   uint32_t Parity;                    /*!< Specifies the parity mode.
00117                                            This parameter can be a value of @ref LPUART_LL_EC_PARITY.
00118
00119                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
00120
00121   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00122                                            This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
00123
00124                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
00125
00126   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00127                                            This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
00128
00129                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
00130
00131 } LL_LPUART_InitTypeDef;
00132
00133 /**
00134   * @}
00135   */
00136 #endif /* USE_FULL_LL_DRIVER */
00137
00138 /* Exported constants --------------------------------------------------------*/
00139 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
00140   * @{
00141   */
00142
00143 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
00144   * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
00145   * @{
00146   */
00147 #define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error flag */
00148 #define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error flag */
00149 #define LL_LPUART_ICR_NCF                  USART_ICR_NCF                 /*!< Noise detected flag */
00150 #define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error flag */
00151 #define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected flag */
00152 #define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete flag */
00153 #define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS flag */
00154 #define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match flag */
00155 #define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
00161   * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
00162   * @{
00163   */
00164 #define LL_LPUART_ISR_PE                   USART_ISR_PE                  /*!< Parity error flag */
00165 #define LL_LPUART_ISR_FE                   USART_ISR_FE                  /*!< Framing error flag */
00166 #define LL_LPUART_ISR_NE                   USART_ISR_NE                  /*!< Noise detected flag */
00167 #define LL_LPUART_ISR_ORE                  USART_ISR_ORE                 /*!< Overrun error flag */
00168 #define LL_LPUART_ISR_IDLE                 USART_ISR_IDLE                /*!< Idle line detected flag */
00169 #define LL_LPUART_ISR_RXNE                 USART_ISR_RXNE                /*!< Read data register not empty flag */
00170 #define LL_LPUART_ISR_TC                   USART_ISR_TC                  /*!< Transmission complete flag */
00171 #define LL_LPUART_ISR_TXE                  USART_ISR_TXE                 /*!< Transmit data register empty flag */
00172 #define LL_LPUART_ISR_CTSIF                USART_ISR_CTSIF               /*!< CTS interrupt flag */
00173 #define LL_LPUART_ISR_CTS                  USART_ISR_CTS                 /*!< CTS flag */
00174 #define LL_LPUART_ISR_BUSY                 USART_ISR_BUSY                /*!< Busy flag */
00175 #define LL_LPUART_ISR_CMF                  USART_ISR_CMF                 /*!< Character match flag */
00176 #define LL_LPUART_ISR_SBKF                 USART_ISR_SBKF                /*!< Send break flag */
00177 #define LL_LPUART_ISR_RWU                  USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00178 #define LL_LPUART_ISR_WUF                  USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00179 #define LL_LPUART_ISR_TEACK                USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00180 #define LL_LPUART_ISR_REACK                USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup LPUART_LL_EC_IT IT Defines
00186   * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
00187   * @{
00188   */
00189 #define LL_LPUART_CR1_IDLEIE               USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00190 #define LL_LPUART_CR1_RXNEIE               USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
00191 #define LL_LPUART_CR1_TCIE                 USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00192 #define LL_LPUART_CR1_TXEIE                USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
00193 #define LL_LPUART_CR1_PEIE                 USART_CR1_PEIE                /*!< Parity error */
00194 #define LL_LPUART_CR1_CMIE                 USART_CR1_CMIE                /*!< Character match interrupt enable */
00195 #define LL_LPUART_CR3_EIE                  USART_CR3_EIE                 /*!< Error interrupt enable */
00196 #define LL_LPUART_CR3_CTSIE                USART_CR3_CTSIE               /*!< CTS interrupt enable */
00197 #define LL_LPUART_CR3_WUFIE                USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup LPUART_LL_EC_DIRECTION Direction
00203   * @{
00204   */
00205 #define LL_LPUART_DIRECTION_NONE           (uint32_t)0x00000000U              /*!< Transmitter and Receiver are disabled */
00206 #define LL_LPUART_DIRECTION_RX             USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00207 #define LL_LPUART_DIRECTION_TX             USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00208 #define LL_LPUART_DIRECTION_TX_RX          (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup LPUART_LL_EC_PARITY Parity Control
00214   * @{
00215   */
00216 #define LL_LPUART_PARITY_NONE              (uint32_t)0x00000000U              /*!< Parity control disabled */
00217 #define LL_LPUART_PARITY_EVEN              USART_CR1_PCE                      /*!< Parity control enabled and Even Parity is selected */
00218 #define LL_LPUART_PARITY_ODD               (USART_CR1_PCE | USART_CR1_PS)     /*!< Parity control enabled and Odd Parity is selected */
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
00224   * @{
00225   */
00226 #define LL_LPUART_WAKEUP_IDLELINE          (uint32_t)0x00000000U              /*!<  LPUART wake up from Mute mode on Idle Line */
00227 #define LL_LPUART_WAKEUP_ADDRESSMARK       USART_CR1_WAKE                     /*!<  LPUART wake up from Mute mode on Address Mark */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
00233   * @{
00234   */
00235 #define LL_LPUART_DATAWIDTH_7B             USART_CR1_M1                       /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00236 #define LL_LPUART_DATAWIDTH_8B             (uint32_t)0x00000000U              /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00237 #define LL_LPUART_DATAWIDTH_9B             USART_CR1_M0                       /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
00243   * @{
00244   */
00245 #define LL_LPUART_STOPBITS_1               (uint32_t)0x00000000U              /*!< 1 stop bit */
00246 #define LL_LPUART_STOPBITS_2               USART_CR2_STOP_1                   /*!< 2 stop bits */
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
00252   * @{
00253   */
00254 #define LL_LPUART_TXRX_STANDARD            (uint32_t)0x00000000U              /*!< TX/RX pins are used as defined in standard pinout */
00255 #define LL_LPUART_TXRX_SWAPPED             (USART_CR2_SWAP)                   /*!< TX and RX pins functions are swapped.             */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00261   * @{
00262   */
00263 #define LL_LPUART_RXPIN_LEVEL_STANDARD     (uint32_t)0x00000000U              /*!< RX pin signal works using the standard logic levels */
00264 #define LL_LPUART_RXPIN_LEVEL_INVERTED     (USART_CR2_RXINV)                  /*!< RX pin signal values are inverted.                  */
00265 /**
00266   * @}
00267   */
00268
00269 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00270   * @{
00271   */
00272 #define LL_LPUART_TXPIN_LEVEL_STANDARD     (uint32_t)0x00000000U              /*!< TX pin signal works using the standard logic levels */
00273 #define LL_LPUART_TXPIN_LEVEL_INVERTED     (USART_CR2_TXINV)                  /*!< TX pin signal values are inverted.                  */
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
00279   * @{
00280   */
00281 #define LL_LPUART_BINARY_LOGIC_POSITIVE    (uint32_t)0x00000000U              /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00282 #define LL_LPUART_BINARY_LOGIC_NEGATIVE    USART_CR2_DATAINV                  /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
00288   * @{
00289   */
00290 #define LL_LPUART_BITORDER_LSBFIRST        (uint32_t)0x00000000U              /*!< data is transmitted/received with data bit 0 first, following the start bit */
00291 #define LL_LPUART_BITORDER_MSBFIRST        USART_CR2_MSBFIRST                 /*!< data is transmitted/received with the MSB first, following the start bit */
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
00297   * @{
00298   */
00299 #define LL_LPUART_ADDRESS_DETECT_4B        (uint32_t)0x00000000U              /*!< 4-bit address detection method selected */
00300 #define LL_LPUART_ADDRESS_DETECT_7B        USART_CR2_ADDM7                    /*!< 7-bit address detection (in 8-bit data mode) method selected */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
00306   * @{
00307   */
00308 #define LL_LPUART_HWCONTROL_NONE           (uint32_t)0x00000000U              /*!< CTS and RTS hardware flow control disabled */
00309 #define LL_LPUART_HWCONTROL_RTS            USART_CR3_RTSE                     /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00310 #define LL_LPUART_HWCONTROL_CTS            USART_CR3_CTSE                     /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00311 #define LL_LPUART_HWCONTROL_RTS_CTS        (USART_CR3_RTSE | USART_CR3_CTSE)  /*!< CTS and RTS hardware flow control enabled */
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
00317   * @{
00318   */
00319 #define LL_LPUART_WAKEUP_ON_ADDRESS        (uint32_t)0x00000000U                   /*!< Wake up active on address match */
00320 #define LL_LPUART_WAKEUP_ON_STARTBIT       USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00321 #define LL_LPUART_WAKEUP_ON_RXNE           (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
00327   * @{
00328   */
00329 #define LL_LPUART_DE_POLARITY_HIGH         (uint32_t)0x00000000U              /*!< DE signal is active high */
00330 #define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP                      /*!< DE signal is active low */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
00336   * @{
00337   */
00338 #define LL_LPUART_DMA_REG_DATA_TRANSMIT    (uint32_t)0U                       /*!< Get address of data register used for transmission */
00339 #define LL_LPUART_DMA_REG_DATA_RECEIVE     (uint32_t)1U                       /*!< Get address of data register used for reception */
00340 /**
00341   * @}
00342   */
00343
00344 /**
00345   * @}
00346   */
00347
00348 /* Exported macro ------------------------------------------------------------*/
00349 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
00350   * @{
00351   */
00352
00353 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
00354   * @{
00355   */
00356
00357 /**
00358   * @brief  Write a value in LPUART register
00359   * @param  __INSTANCE__ LPUART Instance
00360   * @param  __REG__ Register to be written
00361   * @param  __VALUE__ Value to be written in the register
00362   * @retval None
00363   */
00364 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00365
00366 /**
00367   * @brief  Read a value in LPUART register
00368   * @param  __INSTANCE__ LPUART Instance
00369   * @param  __REG__ Register to be read
00370   * @retval Register value
00371   */
00372 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
00378   * @{
00379   */
00380
00381 /**
00382   * @brief  Compute LPUARTDIV value according to Peripheral Clock and
00383   *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
00384   * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
00385   * @param  __BAUDRATE__ Baud Rate value to achieve
00386   * @retval LPUARTDIV value to be used for BRR register filling
00387   */
00388 #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
00389
00390 /**
00391   * @}
00392   */
00393
00394 /**
00395   * @}
00396   */
00397
00398 /* Exported functions --------------------------------------------------------*/
00399 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
00400   * @{
00401   */
00402
00403 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
00404   * @{
00405   */
00406
00407 /**
00408   * @brief  LPUART Enable
00409   * @rmtoll CR1          UE            LL_LPUART_Enable
00410   * @param  LPUARTx LPUART Instance
00411   * @retval None
00412   */
00413 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
00414 {
00415   SET_BIT(LPUARTx->CR1, USART_CR1_UE);
00416 }
00417
00418 /**
00419   * @brief  LPUART Disable
00420   * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
00421   *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
00422   *         flags, in the LPUARTx_ISR are set to their default values.
00423   * @note   In order to go into low-power mode without generating errors on the line,
00424   *         the TE bit must be reset before and the software must wait
00425   *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
00426   *         The DMA requests are also reset when UE = 0 so the DMA channel must
00427   *         be disabled before resetting the UE bit.
00428   * @rmtoll CR1          UE            LL_LPUART_Disable
00429   * @param  LPUARTx LPUART Instance
00430   * @retval None
00431   */
00432 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
00433 {
00434   CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
00435 }
00436
00437 /**
00438   * @brief  Indicate if LPUART is enabled
00439   * @rmtoll CR1          UE            LL_LPUART_IsEnabled
00440   * @param  LPUARTx LPUART Instance
00441   * @retval State of bit (1 or 0).
00442   */
00443 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
00444 {
00445   return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
00446 }
00447
00448 /**
00449   * @brief  LPUART enabled in STOP Mode
00450   * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
00451   *         LPUART clock selection is HSI or LSE in RCC.
00452   * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
00453   * @param  LPUARTx LPUART Instance
00454   * @retval None
00455   */
00456 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
00457 {
00458   SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
00459 }
00460
00461 /**
00462   * @brief  LPUART disabled in STOP Mode
00463   * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
00464   * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
00465   * @param  LPUARTx LPUART Instance
00466   * @retval None
00467   */
00468 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
00469 {
00470   CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
00471 }
00472
00473 /**
00474   * @brief  Indicate if LPUART is enabled in STOP Mode
00475   *         (able to wake up MCU from Stop mode or not)
00476   * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
00477   * @param  LPUARTx LPUART Instance
00478   * @retval State of bit (1 or 0).
00479   */
00480 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
00481 {
00482   return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
00483 }
00484
00485 /**
00486   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00487   * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
00488   * @param  LPUARTx LPUART Instance
00489   * @retval None
00490   */
00491 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
00492 {
00493   SET_BIT(LPUARTx->CR1, USART_CR1_RE);
00494 }
00495
00496 /**
00497   * @brief  Receiver Disable
00498   * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
00499   * @param  LPUARTx LPUART Instance
00500   * @retval None
00501   */
00502 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
00503 {
00504   CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
00505 }
00506
00507 /**
00508   * @brief  Transmitter Enable
00509   * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
00510   * @param  LPUARTx LPUART Instance
00511   * @retval None
00512   */
00513 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
00514 {
00515   SET_BIT(LPUARTx->CR1, USART_CR1_TE);
00516 }
00517
00518 /**
00519   * @brief  Transmitter Disable
00520   * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
00521   * @param  LPUARTx LPUART Instance
00522   * @retval None
00523   */
00524 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
00525 {
00526   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
00527 }
00528
00529 /**
00530   * @brief  Configure simultaneously enabled/disabled states
00531   *         of Transmitter and Receiver
00532   * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
00533   *         CR1          TE            LL_LPUART_SetTransferDirection
00534   * @param  LPUARTx LPUART Instance
00535   * @param  TransferDirection This parameter can be one of the following values:
00536   *         @arg @ref LL_LPUART_DIRECTION_NONE
00537   *         @arg @ref LL_LPUART_DIRECTION_RX
00538   *         @arg @ref LL_LPUART_DIRECTION_TX
00539   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00540   * @retval None
00541   */
00542 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
00543 {
00544   MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00545 }
00546
00547 /**
00548   * @brief  Return enabled/disabled states of Transmitter and Receiver
00549   * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
00550   *         CR1          TE            LL_LPUART_GetTransferDirection
00551   * @param  LPUARTx LPUART Instance
00552   * @retval Returned value can be one of the following values:
00553   *         @arg @ref LL_LPUART_DIRECTION_NONE
00554   *         @arg @ref LL_LPUART_DIRECTION_RX
00555   *         @arg @ref LL_LPUART_DIRECTION_TX
00556   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00557   */
00558 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
00559 {
00560   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00561 }
00562
00563 /**
00564   * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
00565   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00566   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00567   *         (depending on data width) and parity is checked on the received data.
00568   * @rmtoll CR1          PS            LL_LPUART_SetParity\n
00569   *         CR1          PCE           LL_LPUART_SetParity
00570   * @param  LPUARTx LPUART Instance
00571   * @param  Parity This parameter can be one of the following values:
00572   *         @arg @ref LL_LPUART_PARITY_NONE
00573   *         @arg @ref LL_LPUART_PARITY_EVEN
00574   *         @arg @ref LL_LPUART_PARITY_ODD
00575   * @retval None
00576   */
00577 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
00578 {
00579   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00580 }
00581
00582 /**
00583   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00584   * @rmtoll CR1          PS            LL_LPUART_GetParity\n
00585   *         CR1          PCE           LL_LPUART_GetParity
00586   * @param  LPUARTx LPUART Instance
00587   * @retval Returned value can be one of the following values:
00588   *         @arg @ref LL_LPUART_PARITY_NONE
00589   *         @arg @ref LL_LPUART_PARITY_EVEN
00590   *         @arg @ref LL_LPUART_PARITY_ODD
00591   */
00592 __STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
00593 {
00594   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00595 }
00596
00597 /**
00598   * @brief  Set Receiver Wake Up method from Mute mode.
00599   * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
00600   * @param  LPUARTx LPUART Instance
00601   * @param  Method This parameter can be one of the following values:
00602   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00603   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00604   * @retval None
00605   */
00606 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
00607 {
00608   MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
00609 }
00610
00611 /**
00612   * @brief  Return Receiver Wake Up method from Mute mode
00613   * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
00614   * @param  LPUARTx LPUART Instance
00615   * @retval Returned value can be one of the following values:
00616   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00617   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00618   */
00619 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
00620 {
00621   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
00622 }
00623
00624 /**
00625   * @brief  Set Word length (nb of data bits, excluding start and stop bits)
00626   * @rmtoll CR1          M             LL_LPUART_SetDataWidth
00627   * @param  LPUARTx LPUART Instance
00628   * @param  DataWidth This parameter can be one of the following values:
00629   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00630   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00631   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00632   * @retval None
00633   */
00634 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
00635 {
00636   MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
00637 }
00638
00639 /**
00640   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00641   * @rmtoll CR1          M             LL_LPUART_GetDataWidth
00642   * @param  LPUARTx LPUART Instance
00643   * @retval Returned value can be one of the following values:
00644   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00645   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00646   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00647   */
00648 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
00649 {
00650   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
00651 }
00652
00653 /**
00654   * @brief  Allow switch between Mute Mode and Active mode
00655   * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
00656   * @param  LPUARTx LPUART Instance
00657   * @retval None
00658   */
00659 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
00660 {
00661   SET_BIT(LPUARTx->CR1, USART_CR1_MME);
00662 }
00663
00664 /**
00665   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
00666   * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
00667   * @param  LPUARTx LPUART Instance
00668   * @retval None
00669   */
00670 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
00671 {
00672   CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
00673 }
00674
00675 /**
00676   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
00677   * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
00678   * @param  LPUARTx LPUART Instance
00679   * @retval State of bit (1 or 0).
00680   */
00681 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
00682 {
00683   return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
00684 }
00685
00686 /**
00687   * @brief  Set the length of the stop bits
00688   * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
00689   * @param  LPUARTx LPUART Instance
00690   * @param  StopBits This parameter can be one of the following values:
00691   *         @arg @ref LL_LPUART_STOPBITS_1
00692   *         @arg @ref LL_LPUART_STOPBITS_2
00693   * @retval None
00694   */
00695 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
00696 {
00697   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
00698 }
00699
00700 /**
00701   * @brief  Retrieve the length of the stop bits
00702   * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
00703   * @param  LPUARTx LPUART Instance
00704   * @retval Returned value can be one of the following values:
00705   *         @arg @ref LL_LPUART_STOPBITS_1
00706   *         @arg @ref LL_LPUART_STOPBITS_2
00707   */
00708 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
00709 {
00710   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
00711 }
00712
00713 /**
00714   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
00715   * @note   Call of this function is equivalent to following function call sequence :
00716   *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
00717   *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
00718   *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
00719   * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
00720   *         CR1          PCE           LL_LPUART_ConfigCharacter\n
00721   *         CR1          M             LL_LPUART_ConfigCharacter\n
00722   *         CR2          STOP          LL_LPUART_ConfigCharacter
00723   * @param  LPUARTx LPUART Instance
00724   * @param  DataWidth This parameter can be one of the following values:
00725   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00726   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00727   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00728   * @param  Parity This parameter can be one of the following values:
00729   *         @arg @ref LL_LPUART_PARITY_NONE
00730   *         @arg @ref LL_LPUART_PARITY_EVEN
00731   *         @arg @ref LL_LPUART_PARITY_ODD
00732   * @param  StopBits This parameter can be one of the following values:
00733   *         @arg @ref LL_LPUART_STOPBITS_1
00734   *         @arg @ref LL_LPUART_STOPBITS_2
00735   * @retval None
00736   */
00737 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
00738                                                uint32_t StopBits)
00739 {
00740   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
00741   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
00742 }
00743
00744 /**
00745   * @brief  Configure TX/RX pins swapping setting.
00746   * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
00747   * @param  LPUARTx LPUART Instance
00748   * @param  SwapConfig This parameter can be one of the following values:
00749   *         @arg @ref LL_LPUART_TXRX_STANDARD
00750   *         @arg @ref LL_LPUART_TXRX_SWAPPED
00751   * @retval None
00752   */
00753 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
00754 {
00755   MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
00756 }
00757
00758 /**
00759   * @brief  Retrieve TX/RX pins swapping configuration.
00760   * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
00761   * @param  LPUARTx LPUART Instance
00762   * @retval Returned value can be one of the following values:
00763   *         @arg @ref LL_LPUART_TXRX_STANDARD
00764   *         @arg @ref LL_LPUART_TXRX_SWAPPED
00765   */
00766 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
00767 {
00768   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
00769 }
00770
00771 /**
00772   * @brief  Configure RX pin active level logic
00773   * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
00774   * @param  LPUARTx LPUART Instance
00775   * @param  PinInvMethod This parameter can be one of the following values:
00776   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
00777   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
00778   * @retval None
00779   */
00780 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
00781 {
00782   MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
00783 }
00784
00785 /**
00786   * @brief  Retrieve RX pin active level logic configuration
00787   * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
00788   * @param  LPUARTx LPUART Instance
00789   * @retval Returned value can be one of the following values:
00790   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
00791   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
00792   */
00793 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
00794 {
00795   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
00796 }
00797
00798 /**
00799   * @brief  Configure TX pin active level logic
00800   * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
00801   * @param  LPUARTx LPUART Instance
00802   * @param  PinInvMethod This parameter can be one of the following values:
00803   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
00804   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
00805   * @retval None
00806   */
00807 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
00808 {
00809   MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
00810 }
00811
00812 /**
00813   * @brief  Retrieve TX pin active level logic configuration
00814   * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
00815   * @param  LPUARTx LPUART Instance
00816   * @retval Returned value can be one of the following values:
00817   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
00818   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
00819   */
00820 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
00821 {
00822   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
00823 }
00824
00825 /**
00826   * @brief  Configure Binary data logic.
00827   *
00828   * @note   Allow to define how Logical data from the data register are send/received :
00829   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
00830   * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
00831   * @param  LPUARTx LPUART Instance
00832   * @param  DataLogic This parameter can be one of the following values:
00833   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
00834   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
00835   * @retval None
00836   */
00837 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
00838 {
00839   MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
00840 }
00841
00842 /**
00843   * @brief  Retrieve Binary data configuration
00844   * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
00845   * @param  LPUARTx LPUART Instance
00846   * @retval Returned value can be one of the following values:
00847   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
00848   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
00849   */
00850 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
00851 {
00852   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
00853 }
00854
00855 /**
00856   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
00857   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
00858   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
00859   * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
00860   * @param  LPUARTx LPUART Instance
00861   * @param  BitOrder This parameter can be one of the following values:
00862   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
00863   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
00864   * @retval None
00865   */
00866 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
00867 {
00868   MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
00869 }
00870
00871 /**
00872   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
00873   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
00874   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
00875   * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
00876   * @param  LPUARTx LPUART Instance
00877   * @retval Returned value can be one of the following values:
00878   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
00879   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
00880   */
00881 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
00882 {
00883   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
00884 }
00885
00886 /**
00887   * @brief  Set Address of the LPUART node.
00888   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
00889   *         for wake up with address mark detection.
00890   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
00891   *         (b7-b4 should be set to 0)
00892   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
00893   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
00894   *         for wake up with 7-bit address mark detection.
00895   *         The MSB of the character sent by the transmitter should be equal to 1.
00896   *         It may also be used for character detection during normal reception,
00897   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
00898   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
00899   *         value and CMF flag is set on match)
00900   * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
00901   *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
00902   * @param  LPUARTx LPUART Instance
00903   * @param  AddressLen This parameter can be one of the following values:
00904   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
00905   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
00906   * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
00907   * @retval None
00908   */
00909 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
00910 {
00911   MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
00912              (uint32_t)(AddressLen | (NodeAddress << LPUART_POSITION_CR2_ADD)));
00913 }
00914
00915 /**
00916   * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
00917   * @note   If 4-bit Address Detection is selected in ADDM7,
00918   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
00919   *         If 7-bit Address Detection is selected in ADDM7,
00920   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
00921   * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
00922   * @param  LPUARTx LPUART Instance
00923   * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
00924   */
00925 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
00926 {
00927   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> LPUART_POSITION_CR2_ADD);
00928 }
00929
00930 /**
00931   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
00932   * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
00933   * @param  LPUARTx LPUART Instance
00934   * @retval Returned value can be one of the following values:
00935   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
00936   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
00937   */
00938 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
00939 {
00940   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
00941 }
00942
00943 /**
00944   * @brief  Enable RTS HW Flow Control
00945   * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
00946   * @param  LPUARTx LPUART Instance
00947   * @retval None
00948   */
00949 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
00950 {
00951   SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
00952 }
00953
00954 /**
00955   * @brief  Disable RTS HW Flow Control
00956   * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
00957   * @param  LPUARTx LPUART Instance
00958   * @retval None
00959   */
00960 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
00961 {
00962   CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
00963 }
00964
00965 /**
00966   * @brief  Enable CTS HW Flow Control
00967   * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
00968   * @param  LPUARTx LPUART Instance
00969   * @retval None
00970   */
00971 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
00972 {
00973   SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
00974 }
00975
00976 /**
00977   * @brief  Disable CTS HW Flow Control
00978   * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
00979   * @param  LPUARTx LPUART Instance
00980   * @retval None
00981   */
00982 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
00983 {
00984   CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
00985 }
00986
00987 /**
00988   * @brief  Configure HW Flow Control mode (both CTS and RTS)
00989   * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
00990   *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
00991   * @param  LPUARTx LPUART Instance
00992   * @param  HardwareFlowControl This parameter can be one of the following values:
00993   *         @arg @ref LL_LPUART_HWCONTROL_NONE
00994   *         @arg @ref LL_LPUART_HWCONTROL_RTS
00995   *         @arg @ref LL_LPUART_HWCONTROL_CTS
00996   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
00997   * @retval None
00998   */
00999 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
01000 {
01001   MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01002 }
01003
01004 /**
01005   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01006   * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
01007   *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
01008   * @param  LPUARTx LPUART Instance
01009   * @retval Returned value can be one of the following values:
01010   *         @arg @ref LL_LPUART_HWCONTROL_NONE
01011   *         @arg @ref LL_LPUART_HWCONTROL_RTS
01012   *         @arg @ref LL_LPUART_HWCONTROL_CTS
01013   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
01014   */
01015 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
01016 {
01017   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01018 }
01019
01020 /**
01021   * @brief  Enable Overrun detection
01022   * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
01023   * @param  LPUARTx LPUART Instance
01024   * @retval None
01025   */
01026 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
01027 {
01028   CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01029 }
01030
01031 /**
01032   * @brief  Disable Overrun detection
01033   * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
01034   * @param  LPUARTx LPUART Instance
01035   * @retval None
01036   */
01037 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
01038 {
01039   SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01040 }
01041
01042 /**
01043   * @brief  Indicate if Overrun detection is enabled
01044   * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
01045   * @param  LPUARTx LPUART Instance
01046   * @retval State of bit (1 or 0).
01047   */
01048 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
01049 {
01050   return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
01051 }
01052
01053 /**
01054   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01055   * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
01056   * @param  LPUARTx LPUART Instance
01057   * @param  Type This parameter can be one of the following values:
01058   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01059   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01060   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01061   * @retval None
01062   */
01063 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
01064 {
01065   MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
01066 }
01067
01068 /**
01069   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01070   * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
01071   * @param  LPUARTx LPUART Instance
01072   * @retval Returned value can be one of the following values:
01073   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01074   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01075   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01076   */
01077 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
01078 {
01079   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
01080 }
01081
01082 /**
01083   * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
01084   *
01085   * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
01086   *         according to used Peripheral Clock and expected Baud Rate values
01087   * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
01088   *         (Baud rate value != 0).
01089   * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
01090   *         a care should be taken when generating high baud rates using high PeriphClk
01091   *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
01092   * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
01093   * @param  LPUARTx LPUART Instance
01094   * @param  PeriphClk Peripheral Clock
01095   * @param  BaudRate Baud Rate
01096   * @retval None
01097   */
01098 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
01099 {
01100   LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
01101 }
01102
01103 /**
01104   * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
01105   *         (full BRR content), and to used Peripheral Clock values
01106   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01107   * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
01108   * @param  LPUARTx LPUART Instance
01109   * @param  PeriphClk Peripheral Clock
01110   * @retval Baud Rate
01111   */
01112 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
01113 {
01114   register uint32_t lpuartdiv = 0x0U;
01115   register uint32_t brrresult = 0x0U;
01116
01117   lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
01118
01119   if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
01120   {
01121     brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
01122   }
01123
01124   return (brrresult);
01125 }
01126
01127 /**
01128   * @}
01129   */
01130
01131 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
01132   * @{
01133   */
01134
01135 /**
01136   * @brief  Enable Single Wire Half-Duplex mode
01137   * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
01138   * @param  LPUARTx LPUART Instance
01139   * @retval None
01140   */
01141 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
01142 {
01143   SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01144 }
01145
01146 /**
01147   * @brief  Disable Single Wire Half-Duplex mode
01148   * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
01149   * @param  LPUARTx LPUART Instance
01150   * @retval None
01151   */
01152 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
01153 {
01154   CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01155 }
01156
01157 /**
01158   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
01159   * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
01160   * @param  LPUARTx LPUART Instance
01161   * @retval State of bit (1 or 0).
01162   */
01163 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
01164 {
01165   return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
01166 }
01167
01168 /**
01169   * @}
01170   */
01171
01172 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
01173   * @{
01174   */
01175
01176 /**
01177   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01178   * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
01179   * @param  LPUARTx LPUART Instance
01180   * @param  Time Value between Min_Data=0 and Max_Data=31
01181   * @retval None
01182   */
01183 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01184 {
01185   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << LPUART_POSITION_CR1_DEDT);
01186 }
01187
01188 /**
01189   * @brief  Return DEDT (Driver Enable De-Assertion Time)
01190   * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
01191   * @param  LPUARTx LPUART Instance
01192   * @retval Time value expressed on 5 bits ([4:0] bits) : c
01193   */
01194 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
01195 {
01196   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> LPUART_POSITION_CR1_DEDT);
01197 }
01198
01199 /**
01200   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01201   * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
01202   * @param  LPUARTx LPUART Instance
01203   * @param  Time Value between Min_Data=0 and Max_Data=31
01204   * @retval None
01205   */
01206 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01207 {
01208   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << LPUART_POSITION_CR1_DEAT);
01209 }
01210
01211 /**
01212   * @brief  Return DEAT (Driver Enable Assertion Time)
01213   * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
01214   * @param  LPUARTx LPUART Instance
01215   * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
01216   */
01217 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
01218 {
01219   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> LPUART_POSITION_CR1_DEAT);
01220 }
01221
01222 /**
01223   * @brief  Enable Driver Enable (DE) Mode
01224   * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
01225   * @param  LPUARTx LPUART Instance
01226   * @retval None
01227   */
01228 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
01229 {
01230   SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
01231 }
01232
01233 /**
01234   * @brief  Disable Driver Enable (DE) Mode
01235   * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
01236   * @param  LPUARTx LPUART Instance
01237   * @retval None
01238   */
01239 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
01240 {
01241   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
01242 }
01243
01244 /**
01245   * @brief  Indicate if Driver Enable (DE) Mode is enabled
01246   * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
01247   * @param  LPUARTx LPUART Instance
01248   * @retval State of bit (1 or 0).
01249   */
01250 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
01251 {
01252   return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
01253 }
01254
01255 /**
01256   * @brief  Select Driver Enable Polarity
01257   * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
01258   * @param  LPUARTx LPUART Instance
01259   * @param  Polarity This parameter can be one of the following values:
01260   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01261   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01262   * @retval None
01263   */
01264 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
01265 {
01266   MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
01267 }
01268
01269 /**
01270   * @brief  Return Driver Enable Polarity
01271   * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
01272   * @param  LPUARTx LPUART Instance
01273   * @retval Returned value can be one of the following values:
01274   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01275   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01276   */
01277 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
01278 {
01279   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
01280 }
01281
01282 /**
01283   * @}
01284   */
01285
01286 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
01287   * @{
01288   */
01289
01290 /**
01291   * @brief  Check if the LPUART Parity Error Flag is set or not
01292   * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
01293   * @param  LPUARTx LPUART Instance
01294   * @retval State of bit (1 or 0).
01295   */
01296 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
01297 {
01298   return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
01299 }
01300
01301 /**
01302   * @brief  Check if the LPUART Framing Error Flag is set or not
01303   * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
01304   * @param  LPUARTx LPUART Instance
01305   * @retval State of bit (1 or 0).
01306   */
01307 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
01308 {
01309   return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
01310 }
01311
01312 /**
01313   * @brief  Check if the LPUART Noise detected Flag is set or not
01314   * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
01315   * @param  LPUARTx LPUART Instance
01316   * @retval State of bit (1 or 0).
01317   */
01318 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
01319 {
01320   return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
01321 }
01322
01323 /**
01324   * @brief  Check if the LPUART OverRun Error Flag is set or not
01325   * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
01326   * @param  LPUARTx LPUART Instance
01327   * @retval State of bit (1 or 0).
01328   */
01329 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
01330 {
01331   return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
01332 }
01333
01334 /**
01335   * @brief  Check if the LPUART IDLE line detected Flag is set or not
01336   * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
01337   * @param  LPUARTx LPUART Instance
01338   * @retval State of bit (1 or 0).
01339   */
01340 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
01341 {
01342   return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
01343 }
01344
01345 /**
01346   * @brief  Check if the LPUART Read Data Register Not Empty Flag is set or not
01347   * @rmtoll ISR          RXNE          LL_LPUART_IsActiveFlag_RXNE
01348   * @param  LPUARTx LPUART Instance
01349   * @retval State of bit (1 or 0).
01350   */
01351 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
01352 {
01353   return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
01354 }
01355
01356 /**
01357   * @brief  Check if the LPUART Transmission Complete Flag is set or not
01358   * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
01359   * @param  LPUARTx LPUART Instance
01360   * @retval State of bit (1 or 0).
01361   */
01362 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
01363 {
01364   return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
01365 }
01366
01367 /**
01368   * @brief  Check if the LPUART Transmit Data Register Empty Flag is set or not
01369   * @rmtoll ISR          TXE           LL_LPUART_IsActiveFlag_TXE
01370   * @param  LPUARTx LPUART Instance
01371   * @retval State of bit (1 or 0).
01372   */
01373 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
01374 {
01375   return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
01376 }
01377
01378 /**
01379   * @brief  Check if the LPUART CTS interrupt Flag is set or not
01380   * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
01381   * @param  LPUARTx LPUART Instance
01382   * @retval State of bit (1 or 0).
01383   */
01384 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
01385 {
01386   return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
01387 }
01388
01389 /**
01390   * @brief  Check if the LPUART CTS Flag is set or not
01391   * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
01392   * @param  LPUARTx LPUART Instance
01393   * @retval State of bit (1 or 0).
01394   */
01395 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
01396 {
01397   return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
01398 }
01399
01400 /**
01401   * @brief  Check if the LPUART Busy Flag is set or not
01402   * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
01403   * @param  LPUARTx LPUART Instance
01404   * @retval State of bit (1 or 0).
01405   */
01406 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
01407 {
01408   return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
01409 }
01410
01411 /**
01412   * @brief  Check if the LPUART Character Match Flag is set or not
01413   * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
01414   * @param  LPUARTx LPUART Instance
01415   * @retval State of bit (1 or 0).
01416   */
01417 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
01418 {
01419   return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
01420 }
01421
01422 /**
01423   * @brief  Check if the LPUART Send Break Flag is set or not
01424   * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
01425   * @param  LPUARTx LPUART Instance
01426   * @retval State of bit (1 or 0).
01427   */
01428 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
01429 {
01430   return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
01431 }
01432
01433 /**
01434   * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
01435   * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
01436   * @param  LPUARTx LPUART Instance
01437   * @retval State of bit (1 or 0).
01438   */
01439 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
01440 {
01441   return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
01442 }
01443
01444 /**
01445   * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
01446   * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
01447   * @param  LPUARTx LPUART Instance
01448   * @retval State of bit (1 or 0).
01449   */
01450 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
01451 {
01452   return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
01453 }
01454
01455 /**
01456   * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
01457   * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
01458   * @param  LPUARTx LPUART Instance
01459   * @retval State of bit (1 or 0).
01460   */
01461 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
01462 {
01463   return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
01464 }
01465
01466 /**
01467   * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
01468   * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
01469   * @param  LPUARTx LPUART Instance
01470   * @retval State of bit (1 or 0).
01471   */
01472 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
01473 {
01474   return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
01475 }
01476
01477 /**
01478   * @brief  Clear Parity Error Flag
01479   * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
01480   * @param  LPUARTx LPUART Instance
01481   * @retval None
01482   */
01483 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
01484 {
01485   WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
01486 }
01487
01488 /**
01489   * @brief  Clear Framing Error Flag
01490   * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
01491   * @param  LPUARTx LPUART Instance
01492   * @retval None
01493   */
01494 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
01495 {
01496   WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
01497 }
01498
01499 /**
01500   * @brief  Clear Noise detected Flag
01501   * @rmtoll ICR          NCF           LL_LPUART_ClearFlag_NE
01502   * @param  LPUARTx LPUART Instance
01503   * @retval None
01504   */
01505 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
01506 {
01507   WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);
01508 }
01509
01510 /**
01511   * @brief  Clear OverRun Error Flag
01512   * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
01513   * @param  LPUARTx LPUART Instance
01514   * @retval None
01515   */
01516 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
01517 {
01518   WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
01519 }
01520
01521 /**
01522   * @brief  Clear IDLE line detected Flag
01523   * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
01524   * @param  LPUARTx LPUART Instance
01525   * @retval None
01526   */
01527 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
01528 {
01529   WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
01530 }
01531
01532 /**
01533   * @brief  Clear Transmission Complete Flag
01534   * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
01535   * @param  LPUARTx LPUART Instance
01536   * @retval None
01537   */
01538 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
01539 {
01540   WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
01541 }
01542
01543 /**
01544   * @brief  Clear CTS Interrupt Flag
01545   * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
01546   * @param  LPUARTx LPUART Instance
01547   * @retval None
01548   */
01549 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
01550 {
01551   WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
01552 }
01553
01554 /**
01555   * @brief  Clear Character Match Flag
01556   * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
01557   * @param  LPUARTx LPUART Instance
01558   * @retval None
01559   */
01560 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
01561 {
01562   WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
01563 }
01564
01565 /**
01566   * @brief  Clear Wake Up from stop mode Flag
01567   * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
01568   * @param  LPUARTx LPUART Instance
01569   * @retval None
01570   */
01571 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
01572 {
01573   WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
01574 }
01575
01576 /**
01577   * @}
01578   */
01579
01580 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
01581   * @{
01582   */
01583
01584 /**
01585   * @brief  Enable IDLE Interrupt
01586   * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
01587   * @param  LPUARTx LPUART Instance
01588   * @retval None
01589   */
01590 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
01591 {
01592   SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
01593 }
01594
01595 /**
01596   * @brief  Enable RX Not Empty Interrupt
01597   * @rmtoll CR1          RXNEIE        LL_LPUART_EnableIT_RXNE
01598   * @param  LPUARTx LPUART Instance
01599   * @retval None
01600   */
01601 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
01602 {
01603   SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
01604 }
01605
01606 /**
01607   * @brief  Enable Transmission Complete Interrupt
01608   * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
01609   * @param  LPUARTx LPUART Instance
01610   * @retval None
01611   */
01612 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
01613 {
01614   SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
01615 }
01616
01617 /**
01618   * @brief  Enable TX Empty Interrupt
01619   * @rmtoll CR1          TXEIE         LL_LPUART_EnableIT_TXE
01620   * @param  LPUARTx LPUART Instance
01621   * @retval None
01622   */
01623 __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
01624 {
01625   SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
01626 }
01627
01628 /**
01629   * @brief  Enable Parity Error Interrupt
01630   * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
01631   * @param  LPUARTx LPUART Instance
01632   * @retval None
01633   */
01634 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
01635 {
01636   SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
01637 }
01638
01639 /**
01640   * @brief  Enable Character Match Interrupt
01641   * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
01642   * @param  LPUARTx LPUART Instance
01643   * @retval None
01644   */
01645 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
01646 {
01647   SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
01648 }
01649
01650 /**
01651   * @brief  Enable Error Interrupt
01652   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
01653   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
01654   *         - 0: Interrupt is inhibited
01655   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
01656   * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
01657   * @param  LPUARTx LPUART Instance
01658   * @retval None
01659   */
01660 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
01661 {
01662   SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
01663 }
01664
01665 /**
01666   * @brief  Enable CTS Interrupt
01667   * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
01668   * @param  LPUARTx LPUART Instance
01669   * @retval None
01670   */
01671 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
01672 {
01673   SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
01674 }
01675
01676 /**
01677   * @brief  Enable Wake Up from Stop Mode Interrupt
01678   * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
01679   * @param  LPUARTx LPUART Instance
01680   * @retval None
01681   */
01682 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
01683 {
01684   SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
01685 }
01686
01687 /**
01688   * @brief  Disable IDLE Interrupt
01689   * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
01690   * @param  LPUARTx LPUART Instance
01691   * @retval None
01692   */
01693 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
01694 {
01695   CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
01696 }
01697
01698 /**
01699   * @brief  Disable RX Not Empty Interrupt
01700   * @rmtoll CR1          RXNEIE        LL_LPUART_DisableIT_RXNE
01701   * @param  LPUARTx LPUART Instance
01702   * @retval None
01703   */
01704 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
01705 {
01706   CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
01707 }
01708
01709 /**
01710   * @brief  Disable Transmission Complete Interrupt
01711   * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
01712   * @param  LPUARTx LPUART Instance
01713   * @retval None
01714   */
01715 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
01716 {
01717   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
01718 }
01719
01720 /**
01721   * @brief  Disable TX Empty Interrupt
01722   * @rmtoll CR1          TXEIE         LL_LPUART_DisableIT_TXE
01723   * @param  LPUARTx LPUART Instance
01724   * @retval None
01725   */
01726 __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
01727 {
01728   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
01729 }
01730
01731 /**
01732   * @brief  Disable Parity Error Interrupt
01733   * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
01734   * @param  LPUARTx LPUART Instance
01735   * @retval None
01736   */
01737 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
01738 {
01739   CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
01740 }
01741
01742 /**
01743   * @brief  Disable Character Match Interrupt
01744   * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
01745   * @param  LPUARTx LPUART Instance
01746   * @retval None
01747   */
01748 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
01749 {
01750   CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
01751 }
01752
01753 /**
01754   * @brief  Disable Error Interrupt
01755   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
01756   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
01757   *         - 0: Interrupt is inhibited
01758   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
01759   * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
01760   * @param  LPUARTx LPUART Instance
01761   * @retval None
01762   */
01763 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
01764 {
01765   CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
01766 }
01767
01768 /**
01769   * @brief  Disable CTS Interrupt
01770   * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
01771   * @param  LPUARTx LPUART Instance
01772   * @retval None
01773   */
01774 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
01775 {
01776   CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
01777 }
01778
01779 /**
01780   * @brief  Disable Wake Up from Stop Mode Interrupt
01781   * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
01782   * @param  LPUARTx LPUART Instance
01783   * @retval None
01784   */
01785 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
01786 {
01787   CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
01788 }
01789
01790 /**
01791   * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
01792   * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
01793   * @param  LPUARTx LPUART Instance
01794   * @retval State of bit (1 or 0).
01795   */
01796 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
01797 {
01798   return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
01799 }
01800
01801 /**
01802   * @brief  Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
01803   * @rmtoll CR1          RXNEIE        LL_LPUART_IsEnabledIT_RXNE
01804   * @param  LPUARTx LPUART Instance
01805   * @retval State of bit (1 or 0).
01806   */
01807 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
01808 {
01809   return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
01810 }
01811
01812 /**
01813   * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
01814   * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
01815   * @param  LPUARTx LPUART Instance
01816   * @retval State of bit (1 or 0).
01817   */
01818 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
01819 {
01820   return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
01821 }
01822
01823 /**
01824   * @brief  Check if the LPUART TX Empty Interrupt is enabled or disabled.
01825   * @rmtoll CR1          TXEIE         LL_LPUART_IsEnabledIT_TXE
01826   * @param  LPUARTx LPUART Instance
01827   * @retval State of bit (1 or 0).
01828   */
01829 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
01830 {
01831   return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
01832 }
01833
01834 /**
01835   * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
01836   * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
01837   * @param  LPUARTx LPUART Instance
01838   * @retval State of bit (1 or 0).
01839   */
01840 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
01841 {
01842   return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
01843 }
01844
01845 /**
01846   * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
01847   * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
01848   * @param  LPUARTx LPUART Instance
01849   * @retval State of bit (1 or 0).
01850   */
01851 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
01852 {
01853   return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
01854 }
01855
01856 /**
01857   * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
01858   * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
01859   * @param  LPUARTx LPUART Instance
01860   * @retval State of bit (1 or 0).
01861   */
01862 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
01863 {
01864   return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
01865 }
01866
01867 /**
01868   * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
01869   * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
01870   * @param  LPUARTx LPUART Instance
01871   * @retval State of bit (1 or 0).
01872   */
01873 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
01874 {
01875   return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
01876 }
01877
01878 /**
01879   * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
01880   * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
01881   * @param  LPUARTx LPUART Instance
01882   * @retval State of bit (1 or 0).
01883   */
01884 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
01885 {
01886   return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
01887 }
01888
01889 /**
01890   * @}
01891   */
01892
01893 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
01894   * @{
01895   */
01896
01897 /**
01898   * @brief  Enable DMA Mode for reception
01899   * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
01900   * @param  LPUARTx LPUART Instance
01901   * @retval None
01902   */
01903 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
01904 {
01905   SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
01906 }
01907
01908 /**
01909   * @brief  Disable DMA Mode for reception
01910   * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
01911   * @param  LPUARTx LPUART Instance
01912   * @retval None
01913   */
01914 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
01915 {
01916   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
01917 }
01918
01919 /**
01920   * @brief  Check if DMA Mode is enabled for reception
01921   * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
01922   * @param  LPUARTx LPUART Instance
01923   * @retval State of bit (1 or 0).
01924   */
01925 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
01926 {
01927   return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
01928 }
01929
01930 /**
01931   * @brief  Enable DMA Mode for transmission
01932   * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
01933   * @param  LPUARTx LPUART Instance
01934   * @retval None
01935   */
01936 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
01937 {
01938   SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
01939 }
01940
01941 /**
01942   * @brief  Disable DMA Mode for transmission
01943   * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
01944   * @param  LPUARTx LPUART Instance
01945   * @retval None
01946   */
01947 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
01948 {
01949   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
01950 }
01951
01952 /**
01953   * @brief  Check if DMA Mode is enabled for transmission
01954   * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
01955   * @param  LPUARTx LPUART Instance
01956   * @retval State of bit (1 or 0).
01957   */
01958 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
01959 {
01960   return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
01961 }
01962
01963 /**
01964   * @brief  Enable DMA Disabling on Reception Error
01965   * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
01966   * @param  LPUARTx LPUART Instance
01967   * @retval None
01968   */
01969 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
01970 {
01971   SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
01972 }
01973
01974 /**
01975   * @brief  Disable DMA Disabling on Reception Error
01976   * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
01977   * @param  LPUARTx LPUART Instance
01978   * @retval None
01979   */
01980 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
01981 {
01982   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
01983 }
01984
01985 /**
01986   * @brief  Indicate if DMA Disabling on Reception Error is disabled
01987   * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
01988   * @param  LPUARTx LPUART Instance
01989   * @retval State of bit (1 or 0).
01990   */
01991 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
01992 {
01993   return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
01994 }
01995
01996 /**
01997   * @brief  Get the LPUART data register address used for DMA transfer
01998   * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
01999   * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
02000   * @param  LPUARTx LPUART Instance
02001   * @param  Direction This parameter can be one of the following values:
02002   *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
02003   *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
02004   * @retval Address of data register
02005   */
02006 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
02007 {
02008   register uint32_t data_reg_addr = 0U;
02009
02010   if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
02011   {
02012     /* return address of TDR register */
02013     data_reg_addr = (uint32_t) &(LPUARTx->TDR);
02014   }
02015   else
02016   {
02017     /* return address of RDR register */
02018     data_reg_addr = (uint32_t) &(LPUARTx->RDR);
02019   }
02020
02021   return data_reg_addr;
02022 }
02023
02024 /**
02025   * @}
02026   */
02027
02028 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
02029   * @{
02030   */
02031
02032 /**
02033   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
02034   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
02035   * @param  LPUARTx LPUART Instance
02036   * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
02037   */
02038 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
02039 {
02040   return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
02041 }
02042
02043 /**
02044   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
02045   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
02046   * @param  LPUARTx LPUART Instance
02047   * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
02048   */
02049 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
02050 {
02051   return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
02052 }
02053
02054 /**
02055   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
02056   * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
02057   * @param  LPUARTx LPUART Instance
02058   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
02059   * @retval None
02060   */
02061 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
02062 {
02063   LPUARTx->TDR = Value;
02064 }
02065
02066 /**
02067   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
02068   * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
02069   * @param  LPUARTx LPUART Instance
02070   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
02071   * @retval None
02072   */
02073 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
02074 {
02075   LPUARTx->TDR = Value & 0x1FFU;
02076 }
02077
02078 /**
02079   * @}
02080   */
02081
02082 /** @defgroup LPUART_LL_EF_Execution Execution
02083   * @{
02084   */
02085
02086 /**
02087   * @brief  Request Break sending
02088   * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
02089   * @param  LPUARTx LPUART Instance
02090   * @retval None
02091   */
02092 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
02093 {
02094   SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ);
02095 }
02096
02097 /**
02098   * @brief  Put LPUART in mute mode and set the RWU flag
02099   * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
02100   * @param  LPUARTx LPUART Instance
02101   * @retval None
02102   */
02103 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
02104 {
02105   SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ);
02106 }
02107
02108 /**
02109   * @brief  Request a Receive Data flush
02110   * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
02111   * @param  LPUARTx LPUART Instance
02112   * @retval None
02113   */
02114 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
02115 {
02116   SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ);
02117 }
02118
02119 /**
02120   * @}
02121   */
02122
02123 #if defined(USE_FULL_LL_DRIVER)
02124 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
02125   * @{
02126   */
02127 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
02128 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
02129 void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
02130 /**
02131   * @}
02132   */
02133 #endif /* USE_FULL_LL_DRIVER */
02134
02135 /**
02136   * @}
02137   */
02138
02139 /**
02140   * @}
02141   */
02142
02143 #endif /* LPUART1 */
02144
02145 /**
02146   * @}
02147   */
02148
02149 #ifdef __cplusplus
02150 }
02151 #endif
02152
02153 #endif /* __STM32L4xx_LL_LPUART_H */
02154
02155 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_opamp.c Source File

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stm32l4xx_ll_opamp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_opamp.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   OPAMP LL module driver
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_opamp.h"
00041
00042 #ifdef  USE_FULL_ASSERT
00043   #include "stm32_assert.h"
00044 #else
00045   #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32L4xx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined (OPAMP1) || defined (OPAMP2)
00053
00054 /** @addtogroup OPAMP_LL OPAMP
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062
00063 /** @addtogroup OPAMP_LL_Private_Macros
00064   * @{
00065   */
00066
00067 /* Check of parameters for configuration of OPAMP hierarchical scope:         */
00068 /* OPAMP instance.                                                            */
00069
00070 #define IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)                                 \
00071   (   ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMAL)                          \
00072    || ((__POWER_MODE__) == LL_OPAMP_POWERMODE_LOWPOWER))
00073
00074 #define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)                       \
00075   (   ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE)                      \
00076    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER)                        \
00077    || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA)                             \
00078   )
00079
00080 /* Note: Comparator non-inverting inputs parameters are the same on all       */
00081 /*       OPAMP instances.                                                     */
00082 /*       However, comparator instance kept as macro parameter for             */
00083 /*       compatibility with other STM32 families.                             */
00084 #define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__)     \
00085   (   ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)               \
00086    || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC1_CH1)          \
00087   )
00088
00089 /* Note: Comparator non-inverting inputs parameters are the same on all       */
00090 /*       OPAMP instances.                                                     */
00091 /*       However, comparator instance kept as macro parameter for             */
00092 /*       compatibility with other STM32 families.                             */
00093 #define IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__)           \
00094   (   ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0)                     \
00095    || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1)                     \
00096    || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO)              \
00097   )
00098
00099 /**
00100   * @}
00101   */
00102
00103
00104 /* Private function prototypes -----------------------------------------------*/
00105
00106 /* Exported functions --------------------------------------------------------*/
00107 /** @addtogroup OPAMP_LL_Exported_Functions
00108   * @{
00109   */
00110
00111 /** @addtogroup OPAMP_LL_EF_Init
00112   * @{
00113   */
00114
00115 /**
00116   * @brief  De-initialize registers of the selected OPAMP instance
00117   *         to their default reset values.
00118   * @param  OPAMPx OPAMP instance
00119   * @retval An ErrorStatus enumeration value:
00120   *          - SUCCESS: OPAMP registers are de-initialized
00121   *          - ERROR: OPAMP registers are not de-initialized
00122   */
00123 ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx)
00124 {
00125   ErrorStatus status = SUCCESS;
00126
00127   /* Check the parameters */
00128   assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
00129
00130   LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000U);
00131
00132   return status;
00133 }
00134
00135 /**
00136   * @brief  Initialize some features of OPAMP instance.
00137   * @note   This function reset bit of calibration mode to ensure
00138   *         to be in functional mode, in order to have OPAMP parameters
00139   *         (inputs selection, ...) set with the corresponding OPAMP mode
00140   *         to be effective.
00141   * @note   This function configures features of the selected OPAMP instance.
00142   *         Some features are also available at scope OPAMP common instance
00143   *         (common to several OPAMP instances).
00144   *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
00145   * @param  OPAMPx OPAMP instance
00146   * @param  OPAMP_InitStruct Pointer to a @ref LL_OPAMP_InitTypeDef structure
00147   * @retval An ErrorStatus enumeration value:
00148   *          - SUCCESS: OPAMP registers are initialized
00149   *          - ERROR: OPAMP registers are not initialized
00150   */
00151 ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
00152 {
00153   /* Check the parameters */
00154   assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
00155   assert_param(IS_LL_OPAMP_POWER_MODE(OPAMP_InitStruct->PowerMode));
00156   assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode));
00157   assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMPx, OPAMP_InitStruct->InputNonInverting));
00158
00159   /* Note: OPAMP inverting input can be used with OPAMP in mode standalone    */
00160   /*       or PGA with external capacitors for filtering circuit.             */
00161   /*       Otherwise (OPAMP in mode follower), OPAMP inverting input is       */
00162   /*       not used (not connected to GPIO pin).                              */
00163   if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
00164   {
00165     assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMPx, OPAMP_InitStruct->InputInverting));
00166   }
00167
00168   /* Configuration of OPAMP instance :                                        */
00169   /*  - PowerMode                                                             */
00170   /*  - Functional mode                                                       */
00171   /*  - Input non-inverting                                                   */
00172   /*  - Input inverting                                                       */
00173   /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode.      */
00174   if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
00175   {
00176     MODIFY_REG(OPAMPx->CSR,
00177                  OPAMP_CSR_OPALPM
00178                | OPAMP_CSR_OPAMODE
00179                | OPAMP_CSR_CALON
00180                | OPAMP_CSR_VMSEL
00181                | OPAMP_CSR_VPSEL
00182               ,
00183                  (OPAMP_InitStruct->PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK)
00184                | OPAMP_InitStruct->FunctionalMode
00185                | OPAMP_InitStruct->InputNonInverting
00186                | OPAMP_InitStruct->InputInverting
00187               );
00188   }
00189   else
00190   {
00191     MODIFY_REG(OPAMPx->CSR,
00192                  OPAMP_CSR_OPALPM
00193                | OPAMP_CSR_OPAMODE
00194                | OPAMP_CSR_CALON
00195                | OPAMP_CSR_VMSEL
00196                | OPAMP_CSR_VPSEL
00197               ,
00198                  (OPAMP_InitStruct->PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK)
00199                | LL_OPAMP_MODE_FOLLOWER
00200                | OPAMP_InitStruct->InputNonInverting
00201                | LL_OPAMP_INPUT_INVERT_CONNECT_NO
00202               );
00203   }
00204
00205   return SUCCESS;
00206 }
00207
00208 /**
00209   * @brief Set each @ref LL_OPAMP_InitTypeDef field to default value.
00210   * @param OPAMP_InitStruct pointer to a @ref LL_OPAMP_InitTypeDef structure
00211   *                         whose fields will be set to default values.
00212   * @retval None
00213   */
00214 void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
00215 {
00216   /* Set OPAMP_InitStruct fields to default values */
00217   OPAMP_InitStruct->PowerMode         = LL_OPAMP_POWERMODE_NORMAL;
00218   OPAMP_InitStruct->FunctionalMode    = LL_OPAMP_MODE_FOLLOWER;
00219   OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
00220   /* Note: Parameter discarded if OPAMP in functional mode follower,          */
00221   /*       set anyway to its default value.                                   */
00222   OPAMP_InitStruct->InputInverting    = LL_OPAMP_INPUT_INVERT_CONNECT_NO;
00223 }
00224
00225 /**
00226   * @}
00227   */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /**
00234   * @}
00235   */
00236
00237 #endif /* OPAMP1 || OPAMP2 */
00238
00239 /**
00240   * @}
00241   */
00242
00243 #endif /* USE_FULL_LL_DRIVER */
00244
00245 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_opamp.h Source File

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stm32l4xx_ll_opamp.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_opamp.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of OPAMP LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_OPAMP_H
00040 #define __STM32L4xx_LL_OPAMP_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (OPAMP1) || defined (OPAMP2)
00054
00055 /** @defgroup OPAMP_LL OPAMP
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
00064   * @{
00065   */
00066
00067 /* Internal mask for OPAMP power mode:                                        */
00068 /* To select into literal LL_OPAMP_POWERMODE_x the relevant bits for:         */
00069 /* - OPAMP power mode into control register                                   */
00070 /* - OPAMP trimming register offset                                           */
00071
00072 /* Internal register offset for OPAMP trimming configuration */
00073 #define OPAMP_POWERMODE_OTR_REGOFFSET       ((uint32_t)0x00000000U)
00074 #define OPAMP_POWERMODE_LPOTR_REGOFFSET     ((uint32_t)0x00000001U)
00075 #define OPAMP_POWERMODE_OTR_REGOFFSET_MASK  (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET)
00076
00077 /* Mask for OPAMP power mode into control register */
00078 #define OPAMP_POWERMODE_CSR_BIT_MASK        (OPAMP_CSR_OPALPM)
00079
00080 /* Internal mask for OPAMP trimming of transistors differential pair NMOS     */
00081 /* or PMOS.                                                                   */
00082 /* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for:          */
00083 /* - OPAMP trimming selection of transistors differential pair                */
00084 /* - OPAMP trimming values of transistors differential pair                   */
00085 #define OPAMP_TRIMMING_SELECT_MASK          (OPAMP1_CSR_CALSEL)
00086 #define OPAMP_TRIMMING_VALUE_MASK           (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)
00087
00088 /**
00089   * @}
00090   */
00091
00092
00093 /* Private macros ------------------------------------------------------------*/
00094 /** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
00095   * @{
00096   */
00097
00098 /**
00099   * @brief  Driver macro reserved for internal use: set a pointer to
00100   *         a register from a register basis from which an offset
00101   *         is applied.
00102   * @param  __REG__ Register basis from which the offset is applied.
00103   * @param  __REG_OFFSET__ Offset to be applied (unit: number of registers).
00104   * @retval Register address
00105 */
00106 #define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__)                        \
00107  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
00108
00109
00110
00111
00112 /**
00113   * @}
00114   */
00115
00116
00117 /* Exported types ------------------------------------------------------------*/
00118 #if defined(USE_FULL_LL_DRIVER)
00119 /** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
00120   * @{
00121   */
00122
00123 /**
00124   * @brief  Structure definition of some features of OPAMP instance.
00125   */
00126 typedef struct
00127 {
00128   uint32_t PowerMode;                   /*!< Set OPAMP power mode.
00129                                              This parameter can be a value of @ref OPAMP_LL_EC_POWERMODE
00130
00131                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetPowerMode(). */
00132
00133   uint32_t FunctionalMode;              /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
00134                                              This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
00135                                              @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().
00136
00137                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
00138
00139   uint32_t InputNonInverting;           /*!< Set OPAMP input non-inverting connection.
00140                                              This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
00141
00142                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
00143
00144   uint32_t InputInverting;              /*!< Set OPAMP inverting input connection.
00145                                              This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
00146                                              @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
00147
00148                                              This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
00149
00150 } LL_OPAMP_InitTypeDef;
00151
00152 /**
00153   * @}
00154   */
00155 #endif /* USE_FULL_LL_DRIVER */
00156
00157 /* Exported constants --------------------------------------------------------*/
00158 /** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
00159   * @{
00160   */
00161
00162 /** @defgroup OPAMP_LL_EC_POWERSUPPLY_RANGE OPAMP power supply range
00163   * @{
00164   */
00165 #define LL_OPAMP_POWERSUPPLY_RANGE_LOW  ((uint32_t)0x00000000U) /*!< Power supply range low. On STM32L4 serie: Vdda lower than 2.4V. */
00166 #define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP1_CSR_OPARANGE)   /*!< Power supply range high. On STM32L4 serie: Vdda higher than 2.4V. */
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup OPAMP_LL_EC_POWERMODE OPAMP power mode
00172   * @{
00173   */
00174 #define LL_OPAMP_POWERMODE_NORMAL       (OPAMP_POWERMODE_OTR_REGOFFSET)                      /*!< OPAMP power mode normal */
00175 #define LL_OPAMP_POWERMODE_LOWPOWER     (OPAMP_POWERMODE_LPOTR_REGOFFSET | OPAMP_CSR_OPALPM) /*!< OPAMP power mode low-power */
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
00181   * @{
00182   */
00183 #define LL_OPAMP_MODE_FUNCTIONAL        ((uint32_t)0x00000000U)                     /*!< OPAMP functional mode */
00184 #define LL_OPAMP_MODE_CALIBRATION       (OPAMP1_CSR_CALON)                          /*!< OPAMP calibration mode */
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
00190   * @{
00191   */
00192 #define LL_OPAMP_MODE_STANDALONE        ((uint32_t)0x00000000U)                     /*!< OPAMP functional mode, OPAMP operation in standalone */
00193 #define LL_OPAMP_MODE_FOLLOWER          (OPAMP_CSR_OPAMODE_1 | OPAMP_CSR_OPAMODE_0) /*!< OPAMP functional mode, OPAMP operation in follower */
00194 #define LL_OPAMP_MODE_PGA               (OPAMP_CSR_OPAMODE_1)                       /*!< OPAMP functional mode, OPAMP operation in PGA */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
00200   * @{
00201   */
00202 #define LL_OPAMP_PGA_GAIN_2             ((uint32_t)0x00000000U)                    /*!< OPAMP PGA gain 2 */
00203 #define LL_OPAMP_PGA_GAIN_4             (OPAMP_CSR_PGGAIN_0)                       /*!< OPAMP PGA gain 4 */
00204 #define LL_OPAMP_PGA_GAIN_8             (OPAMP_CSR_PGGAIN_1)                       /*!< OPAMP PGA gain 8 */
00205 #define LL_OPAMP_PGA_GAIN_16            (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 ) /*!< OPAMP PGA gain 16 */
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
00211   * @{
00212   */
00213 #define LL_OPAMP_INPUT_NONINVERT_IO0      ((uint32_t)0x00000000U) /*!< OPAMP non inverting input connected to GPIO pin */
00214 #define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 (OPAMP1_CSR_VPSEL)      /*!< OPAMP non inverting input connected to DAC1 channel1 output */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
00220   * @{
00221   */
00222 #define LL_OPAMP_INPUT_INVERT_IO0        ((uint32_t)0x00000000U) /*!< OPAMP inverting input connected to GPIO pin (valid also in PGA mode for filtering). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
00223 #define LL_OPAMP_INPUT_INVERT_IO1        (OPAMP1_CSR_VMSEL_0)    /*!< OPAMP inverting input (low leakage input) connected to GPIO pin (available only on package BGA132). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
00224 #define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP1_CSR_VMSEL_1)    /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering) */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup OPAMP_LL_EC_INPUT_LEGACY OPAMP inputs legacy literals name
00230   * @{
00231   */
00232 #define LL_OPAMP_NONINVERTINGINPUT_IO0      LL_OPAMP_INPUT_NONINVERT_IO0
00233 #define LL_OPAMP_NONINVERTINGINPUT_DAC_CH   LL_OPAMP_INPUT_NONINVERT_DAC1_CH1
00234
00235 #define LL_OPAMP_INVERTINGINPUT_IO0         LL_OPAMP_INPUT_INVERT_IO0
00236 #define LL_OPAMP_INVERTINGINPUT_IO1         LL_OPAMP_INPUT_INVERT_IO1
00237 #define LL_OPAMP_INVERTINGINPUT_CONNECT_NO  LL_OPAMP_INPUT_INVERT_CONNECT_NO
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
00243   * @{
00244   */
00245 #define LL_OPAMP_TRIMMING_FACTORY       ((uint32_t)0x00000000U) /*!< OPAMP trimming factors set to factory values */
00246 #define LL_OPAMP_TRIMMING_USER          (OPAMP_CSR_USERTRIM)    /*!< OPAMP trimming factors set to user values */
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
00252   * @{
00253   */
00254 #define LL_OPAMP_TRIMMING_NMOS          (OPAMP_OTR_TRIMOFFSETN)                     /*!< OPAMP trimming of transistors differential pair NMOS */
00255 #define LL_OPAMP_TRIMMING_PMOS          (OPAMP_OTR_TRIMOFFSETP | OPAMP1_CSR_CALSEL) /*!< OPAMP trimming of transistors differential pair PMOS */
00256 /**
00257   * @}
00258   */
00259
00260 /**
00261   * @}
00262   */
00263
00264 /* Exported macro ------------------------------------------------------------*/
00265 /** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
00266   * @{
00267   */
00268 /** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
00269   * @{
00270   */
00271 /**
00272   * @brief  Write a value in OPAMP register
00273   * @param  __INSTANCE__ OPAMP Instance
00274   * @param  __REG__ Register to be written
00275   * @param  __VALUE__ Value to be written in the register
00276   * @retval None
00277   */
00278 #define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00279
00280 /**
00281   * @brief  Read a value in OPAMP register
00282   * @param  __INSTANCE__ OPAMP Instance
00283   * @param  __REG__ Register to be read
00284   * @retval Register value
00285   */
00286 #define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup OPAMP_LL_EM_HELPER_MACRO OPAMP helper macro
00292   * @{
00293   */
00294
00295 /**
00296   * @brief  Helper macro to select the OPAMP common instance
00297   *         to which is belonging the selected OPAMP instance.
00298   * @note   OPAMP common register instance can be used to
00299   *         set parameters common to several OPAMP instances.
00300   *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
00301   * @param  __OPAMPx__ OPAMP instance
00302   * @retval OPAMP common instance
00303   */
00304 #if defined(OPAMP1) && defined(OPAMP2)
00305 #define __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__)                                 \
00306   (OPAMP12_COMMON)
00307 #else
00308 #define __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__)                                 \
00309   (OPAMP1_COMMON)
00310 #endif
00311
00312 /**
00313   * @brief  Helper macro to check if all OPAMP instances sharing the same
00314   *         OPAMP common instance are disabled.
00315   * @note   This check is required by functions with setting conditioned to
00316   *         OPAMP state:
00317   *         All OPAMP instances of the OPAMP common group must be disabled.
00318   *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
00319   * @retval 0: All OPAMP instances sharing the same OPAMP common instance
00320   *            are disabled.
00321   *         1: At least one OPAMP instance sharing the same OPAMP common instance
00322   *            is enabled
00323   */
00324 #if defined(OPAMP1) && defined(OPAMP2)
00325 #define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()                            \
00326   (LL_OPAMP_IsEnabled(OPAMP1) |                                                \
00327    LL_OPAMP_IsEnabled(OPAMP2)  )
00328 #else
00329 #define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()                            \
00330   (LL_OPAMP_IsEnabled(OPAMP1))
00331 #endif
00332
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /* Exported functions --------------------------------------------------------*/
00342 /** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
00343   * @{
00344   */
00345
00346 /** @defgroup OPAMP_LL_EF_Configuration_opamp_common Configuration of OPAMP hierarchical scope: common to several OPAMP instances
00347   * @{
00348   */
00349
00350 /**
00351   * @brief  Set OPAMP power range.
00352   * @note   The OPAMP power range applies to several OPAMP instances
00353   *         (if several OPAMP instances available on the selected device).
00354   * @note   On this STM32 serie, setting of this feature is conditioned to
00355   *         OPAMP state:
00356   *         All OPAMP instances of the OPAMP common group must be disabled.
00357   *         This check can be done with function @ref LL_OPAMP_IsEnabled() for each
00358   *         OPAMP instance or by using helper macro
00359   *         @ref __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE().
00360   * @rmtoll CSR      OPARANGE       LL_OPAMP_SetCommonPowerRange
00361   * @param  OPAMPxy_COMMON OPAMP common instance
00362   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_OPAMP_COMMON_INSTANCE() )
00363   * @param  PowerRange This parameter can be one of the following values:
00364   *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW
00365   *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH
00366   * @retval None
00367   */
00368 __STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange)
00369 {
00370   MODIFY_REG(OPAMP1->CSR, OPAMP1_CSR_OPARANGE, PowerRange);
00371 }
00372
00373 /**
00374   * @brief  Get OPAMP power range.
00375   * @note   The OPAMP power range applies to several OPAMP instances
00376   *         (if several OPAMP instances available on the selected device).
00377   * @rmtoll CSR      OPARANGE       LL_OPAMP_GetCommonPowerRange
00378   * @param  OPAMPxy_COMMON OPAMP common instance
00379   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_OPAMP_COMMON_INSTANCE() )
00380   * @retval Returned value can be one of the following values:
00381   *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW
00382   *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH
00383   */
00384 __STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON)
00385 {
00386   return (uint32_t)(READ_BIT(OPAMP1->CSR, OPAMP1_CSR_OPARANGE));
00387 }
00388
00389 /**
00390   * @}
00391   */
00392
00393 /** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
00394   * @{
00395   */
00396
00397 /**
00398   * @brief  Set OPAMP power mode.
00399   * @note   The OPAMP must be disabled to change this configuration.
00400   * @rmtoll CSR      OPALPM         LL_OPAMP_SetPowerMode
00401   * @param  OPAMPx OPAMP instance
00402   * @param  PowerMode This parameter can be one of the following values:
00403   *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
00404   *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
00405   * @retval None
00406   */
00407 __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
00408 {
00409   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPALPM, (PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK));
00410 }
00411
00412 /**
00413   * @brief  Get OPAMP power mode.
00414   * @rmtoll CSR      OPALPM         LL_OPAMP_GetPowerMode
00415   * @param  OPAMPx OPAMP instance
00416   * @retval Returned value can be one of the following values:
00417   *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
00418   *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
00419   */
00420 __STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
00421 {
00422   register uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPALPM));
00423
00424   return (uint32_t)(power_mode | (power_mode >> (POSITION_VAL(OPAMP_CSR_OPALPM))));
00425 }
00426
00427 /**
00428   * @brief  Set OPAMP mode calibration or functional.
00429   * @note   OPAMP mode corresponds to functional or calibration mode:
00430   *          - functional mode: OPAMP operation in standalone, follower, ...
00431   *            Set functional mode using function
00432   *            @ref LL_OPAMP_SetFunctionalMode().
00433   *          - calibration mode: offset calibration of the selected
00434   *            transistors differential pair NMOS or PMOS.
00435   * @note   On this STM32 serie, during calibration, OPAMP functional
00436   *         mode must be set to standalone or follower mode
00437   *         (in order to open internal connections to resistors
00438   *         of PGA mode).
00439   *         Refer to function @ref LL_OPAMP_SetFunctionalMode().
00440   * @rmtoll CSR      CALON          LL_OPAMP_SetMode
00441   * @param  OPAMPx OPAMP instance
00442   * @param  Mode This parameter can be one of the following values:
00443   *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
00444   *         @arg @ref LL_OPAMP_MODE_CALIBRATION
00445   * @retval None
00446   */
00447 __STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
00448 {
00449   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
00450 }
00451
00452 /**
00453   * @brief  Get OPAMP mode calibration or functional.
00454   * @note   OPAMP mode corresponds to functional or calibration mode:
00455   *          - functional mode: OPAMP operation in standalone, follower, ...
00456   *            Set functional mode using function
00457   *            @ref LL_OPAMP_SetFunctionalMode().
00458   *          - calibration mode: offset calibration of the selected
00459   *            transistors differential pair NMOS or PMOS.
00460   * @rmtoll CSR      CALON          LL_OPAMP_GetMode
00461   * @param  OPAMPx OPAMP instance
00462   * @retval Returned value can be one of the following values:
00463   *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
00464   *         @arg @ref LL_OPAMP_MODE_CALIBRATION
00465   */
00466 __STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
00467 {
00468   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
00469 }
00470
00471 /**
00472   * @brief  Set OPAMP functional mode by setting internal connections.
00473   *         OPAMP operation in standalone, follower, ...
00474   * @note   This function reset bit of calibration mode to ensure
00475   *         to be in functional mode, in order to have OPAMP parameters
00476   *         (inputs selection, ...) set with the corresponding OPAMP mode
00477   *         to be effective.
00478   * @rmtoll CSR      OPAMODE        LL_OPAMP_SetFunctionalMode
00479   * @param  OPAMPx OPAMP instance
00480   * @param  FunctionalMode This parameter can be one of the following values:
00481   *         @arg @ref LL_OPAMP_MODE_STANDALONE
00482   *         @arg @ref LL_OPAMP_MODE_FOLLOWER
00483   *         @arg @ref LL_OPAMP_MODE_PGA
00484   * @retval None
00485   */
00486 __STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
00487 {
00488   /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
00489   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPAMODE | OPAMP_CSR_CALON, FunctionalMode);
00490 }
00491
00492 /**
00493   * @brief  Get OPAMP functional mode from setting of internal connections.
00494   *         OPAMP operation in standalone, follower, ...
00495   * @rmtoll CSR      OPAMODE        LL_OPAMP_GetFunctionalMode
00496   * @param  OPAMPx OPAMP instance
00497   * @retval Returned value can be one of the following values:
00498   *         @arg @ref LL_OPAMP_MODE_STANDALONE
00499   *         @arg @ref LL_OPAMP_MODE_FOLLOWER
00500   *         @arg @ref LL_OPAMP_MODE_PGA
00501   */
00502 __STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
00503 {
00504   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMODE));
00505 }
00506
00507 /**
00508   * @brief  Set OPAMP PGA gain.
00509   * @note   Preliminarily, OPAMP must be set in mode PGA
00510   *         using function @ref LL_OPAMP_SetFunctionalMode().
00511   * @rmtoll CSR      PGGAIN         LL_OPAMP_SetPGAGain
00512   * @param  OPAMPx OPAMP instance
00513   * @param  PGAGain This parameter can be one of the following values:
00514   *         @arg @ref LL_OPAMP_PGA_GAIN_2
00515   *         @arg @ref LL_OPAMP_PGA_GAIN_4
00516   *         @arg @ref LL_OPAMP_PGA_GAIN_8
00517   *         @arg @ref LL_OPAMP_PGA_GAIN_16
00518   * @retval None
00519   */
00520 __STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
00521 {
00522   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN, PGAGain);
00523 }
00524
00525 /**
00526   * @brief  Get OPAMP PGA gain.
00527   * @note   Preliminarily, OPAMP must be set in mode PGA
00528   *         using function @ref LL_OPAMP_SetFunctionalMode().
00529   * @rmtoll CSR      PGGAIN         LL_OPAMP_GetPGAGain
00530   * @param  OPAMPx OPAMP instance
00531   * @retval Returned value can be one of the following values:
00532   *         @arg @ref LL_OPAMP_PGA_GAIN_2
00533   *         @arg @ref LL_OPAMP_PGA_GAIN_4
00534   *         @arg @ref LL_OPAMP_PGA_GAIN_8
00535   *         @arg @ref LL_OPAMP_PGA_GAIN_16
00536   */
00537 __STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
00538 {
00539   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN));
00540 }
00541
00542 /**
00543   * @}
00544   */
00545
00546 /** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
00547   * @{
00548   */
00549
00550 /**
00551   * @brief  Set OPAMP non-inverting input connection.
00552   * @rmtoll CSR      VPSEL          LL_OPAMP_SetInputNonInverting
00553   * @param  OPAMPx OPAMP instance
00554   * @param  InputNonInverting This parameter can be one of the following values:
00555   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
00556   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC1_CH1
00557   * @retval None
00558   */
00559 __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
00560 {
00561   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);
00562 }
00563
00564 /**
00565   * @brief  Get OPAMP non-inverting input connection.
00566   * @rmtoll CSR      VPSEL          LL_OPAMP_GetInputNonInverting
00567   * @param  OPAMPx OPAMP instance
00568   * @retval Returned value can be one of the following values:
00569   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
00570   *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC1_CH1
00571   */
00572 __STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
00573 {
00574   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));
00575 }
00576
00577 /**
00578   * @brief  Set OPAMP inverting input connection.
00579   * @note   OPAMP inverting input is used with OPAMP in mode standalone
00580   *         or PGA with external capacitors for filtering circuit.
00581   *         Otherwise (OPAMP in mode follower), OPAMP inverting input
00582   *         is not used (not connected to GPIO pin).
00583   * @rmtoll CSR      VMSEL          LL_OPAMP_SetInputInverting
00584   * @param  OPAMPx OPAMP instance
00585   * @param  InputInverting This parameter can be one of the following values:
00586   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
00587   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1
00588   *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
00589   * @retval None
00590   */
00591 __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
00592 {
00593   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VMSEL, InputInverting);
00594 }
00595
00596 /**
00597   * @brief  Get OPAMP inverting input connection.
00598   * @rmtoll CSR      VMSEL          LL_OPAMP_GetInputInverting
00599   * @param  OPAMPx OPAMP instance
00600   * @retval Returned value can be one of the following values:
00601   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
00602   *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1
00603   *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
00604   */
00605 __STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
00606 {
00607   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL));
00608 }
00609
00610 /**
00611   * @}
00612   */
00613
00614 /** @defgroup OPAMP_LL_EF_Configuration_Legacy_Functions Configuration of OPAMP, legacy functions name
00615   * @{
00616   */
00617 /* Old functions name kept for legacy purpose, to be replaced by the          */
00618 /* current functions name.                                                    */
00619 __STATIC_INLINE void LL_OPAMP_SetNonInvertingInput(OPAMP_TypeDef *OPAMPx, uint32_t NonInvertingInput)
00620 {
00621   LL_OPAMP_SetInputNonInverting(OPAMPx, NonInvertingInput);
00622 }
00623
00624 __STATIC_INLINE void LL_OPAMP_SetInvertingInput(OPAMP_TypeDef *OPAMPx, uint32_t InvertingInput)
00625 {
00626   LL_OPAMP_SetInputInverting(OPAMPx, InvertingInput);
00627 }
00628
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
00634   * @{
00635   */
00636
00637 /**
00638   * @brief  Set OPAMP trimming mode.
00639   * @rmtoll CSR      USERTRIM       LL_OPAMP_SetTrimmingMode
00640   * @param  OPAMPx OPAMP instance
00641   * @param  TrimmingMode This parameter can be one of the following values:
00642   *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
00643   *         @arg @ref LL_OPAMP_TRIMMING_USER
00644   * @retval None
00645   */
00646 __STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
00647 {
00648   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
00649 }
00650
00651 /**
00652   * @brief  Get OPAMP trimming mode.
00653   * @rmtoll CSR      USERTRIM       LL_OPAMP_GetTrimmingMode
00654   * @param  OPAMPx OPAMP instance
00655   * @retval Returned value can be one of the following values:
00656   *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
00657   *         @arg @ref LL_OPAMP_TRIMMING_USER
00658   */
00659 __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
00660 {
00661   return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
00662 }
00663
00664 /**
00665   * @brief  Set OPAMP offset to calibrate the selected transistors
00666   *         differential pair NMOS or PMOS.
00667   * @note   Preliminarily, OPAMP must be set in mode calibration
00668   *         using function @ref LL_OPAMP_SetMode().
00669   * @rmtoll CSR      CALSEL         LL_OPAMP_SetCalibrationSelection
00670   * @param  OPAMPx OPAMP instance
00671   * @param  TransistorsDiffPair This parameter can be one of the following values:
00672   *         @arg @ref LL_OPAMP_TRIMMING_NMOS
00673   *         @arg @ref LL_OPAMP_TRIMMING_PMOS
00674   * @retval None
00675   */
00676 __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
00677 {
00678   /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because            */
00679   /* containing other bits reserved for other purpose.                        */
00680   MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
00681 }
00682
00683 /**
00684   * @brief  Get OPAMP offset to calibrate the selected transistors
00685   *         differential pair NMOS or PMOS.
00686   * @note   Preliminarily, OPAMP must be set in mode calibration
00687   *         using function @ref LL_OPAMP_SetMode().
00688   * @rmtoll CSR      CALSEL         LL_OPAMP_GetCalibrationSelection
00689   * @param  OPAMPx OPAMP instance
00690   * @retval Returned value can be one of the following values:
00691   *         @arg @ref LL_OPAMP_TRIMMING_NMOS
00692   *         @arg @ref LL_OPAMP_TRIMMING_PMOS
00693   */
00694 __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
00695 {
00696   register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
00697
00698   return (CalibrationSelection |
00699           ((OPAMP_OTR_TRIMOFFSETN) << (POSITION_VAL(OPAMP_OTR_TRIMOFFSETP) * (CalibrationSelection && OPAMP1_CSR_CALSEL))));
00700 }
00701
00702 /**
00703   * @brief  Get OPAMP calibration result of toggling output.
00704   * @note   This functions returns:
00705   *         0 if OPAMP calibration output is reset
00706   *         1 if OPAMP calibration output is set
00707   * @rmtoll CSR      CALOUT         LL_OPAMP_IsCalibrationOutputSet
00708   * @param  OPAMPx OPAMP instance
00709   * @retval State of bit (1 or 0).
00710   */
00711 __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
00712 {
00713   return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT);
00714 }
00715
00716 /**
00717   * @brief  Set OPAMP trimming factor for the selected transistors
00718   *         differential pair NMOS or PMOS, corresponding to the selected
00719   *         power mode.
00720   * @rmtoll OTR      TRIMOFFSETN    LL_OPAMP_SetTrimmingValue\n
00721   *         OTR      TRIMOFFSETP    LL_OPAMP_SetTrimmingValue\n
00722   *         LPOTR    TRIMLPOFFSETN  LL_OPAMP_SetTrimmingValue\n
00723   *         LPOTR    TRIMLPOFFSETP  LL_OPAMP_SetTrimmingValue
00724   * @param  OPAMPx OPAMP instance
00725   * @param  PowerMode This parameter can be one of the following values:
00726   *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
00727   *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
00728   * @param  TransistorsDiffPair This parameter can be one of the following values:
00729   *         @arg @ref LL_OPAMP_TRIMMING_NMOS
00730   *         @arg @ref LL_OPAMP_TRIMMING_PMOS
00731   * @param  TrimmingValue 0x00...0x1F
00732   * @retval None
00733   */
00734 __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
00735 {
00736   register uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
00737
00738   /* Set bits with position in register depending on parameter                */
00739   /* "TransistorsDiffPair".                                                   */
00740   /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because             */
00741   /* containing other bits reserved for other purpose.                        */
00742   MODIFY_REG(*preg,
00743              (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
00744              TrimmingValue << (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)));
00745 }
00746
00747 /**
00748   * @brief  Get OPAMP trimming factor for the selected transistors
00749   *         differential pair NMOS or PMOS, corresponding to the selected
00750   *         power mode.
00751   * @rmtoll OTR      TRIMOFFSETN    LL_OPAMP_SetTrimmingValue\n
00752   *         OTR      TRIMOFFSETP    LL_OPAMP_SetTrimmingValue\n
00753   *         LPOTR    TRIMLPOFFSETN  LL_OPAMP_SetTrimmingValue\n
00754   *         LPOTR    TRIMLPOFFSETP  LL_OPAMP_SetTrimmingValue
00755   * @param  OPAMPx OPAMP instance
00756   * @param  PowerMode This parameter can be one of the following values:
00757   *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
00758   *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
00759   * @param  TransistorsDiffPair This parameter can be one of the following values:
00760   *         @arg @ref LL_OPAMP_TRIMMING_NMOS
00761   *         @arg @ref LL_OPAMP_TRIMMING_PMOS
00762   * @retval 0x0...0x1F
00763   */
00764 __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
00765 {
00766   register uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
00767
00768   /* Retrieve bits with position in register depending on parameter           */
00769   /* "TransistorsDiffPair".                                                   */
00770   /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because             */
00771   /* containing other bits reserved for other purpose.                        */
00772   return (uint32_t)(READ_BIT(*preg, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
00773                     >> (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
00774                    );
00775 }
00776
00777 /**
00778   * @}
00779   */
00780
00781 /** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
00782   * @{
00783   */
00784 /**
00785   * @brief  Enable OPAMP instance.
00786   * @note   After enable from off state, OPAMP requires a delay
00787   *         to fullfill wake up time specification.
00788   *         Refer to device datasheet, parameter "tWAKEUP".
00789   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Enable
00790   * @param  OPAMPx OPAMP instance
00791   * @retval None
00792   */
00793 __STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
00794 {
00795   SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
00796 }
00797
00798 /**
00799   * @brief  Disable OPAMP instance.
00800   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Disable
00801   * @param  OPAMPx OPAMP instance
00802   * @retval None
00803   */
00804 __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
00805 {
00806   CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
00807 }
00808
00809 /**
00810   * @brief  Get OPAMP instance enable state
00811   *         (0: OPAMP is disabled, 1: OPAMP is enabled)
00812   * @rmtoll CSR      OPAMPXEN       LL_OPAMP_IsEnabled
00813   * @param  OPAMPx OPAMP instance
00814   * @retval State of bit (1 or 0).
00815   */
00816 __STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
00817 {
00818   return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN));
00819 }
00820
00821 /**
00822   * @}
00823   */
00824
00825 #if defined(USE_FULL_LL_DRIVER)
00826 /** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
00827   * @{
00828   */
00829
00830 ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
00831 ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
00832 void        LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
00833
00834 /**
00835   * @}
00836   */
00837 #endif /* USE_FULL_LL_DRIVER */
00838
00839 /**
00840   * @}
00841   */
00842
00843 /**
00844   * @}
00845   */
00846
00847 #endif /* OPAMP1 || OPAMP2 */
00848
00849 /**
00850   * @}
00851   */
00852
00853 #ifdef __cplusplus
00854 }
00855 #endif
00856
00857 #endif /* __STM32L4xx_LL_OPAMP_H */
00858
00859 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_pwr.c Source File

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stm32l4xx_ll_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_pwr.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   PWR LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_pwr.h"
00041 #include "stm32l4xx_ll_bus.h"
00042
00043 /** @addtogroup STM32L4xx_LL_Driver
00044   * @{
00045   */
00046
00047 #if defined(PWR)
00048
00049 /** @defgroup PWR_LL PWR
00050   * @{
00051   */
00052
00053 /* Private types -------------------------------------------------------------*/
00054 /* Private variables ---------------------------------------------------------*/
00055 /* Private constants ---------------------------------------------------------*/
00056 /* Private macros ------------------------------------------------------------*/
00057 /* Private function prototypes -----------------------------------------------*/
00058
00059 /* Exported functions --------------------------------------------------------*/
00060 /** @addtogroup PWR_LL_Exported_Functions
00061   * @{
00062   */
00063
00064 /** @addtogroup PWR_LL_EF_Init
00065   * @{
00066   */
00067
00068 /**
00069   * @brief  De-initialize the PWR registers to their default reset values.
00070   * @retval An ErrorStatus enumeration value:
00071   *          - SUCCESS: PWR registers are de-initialized
00072   *          - ERROR: not applicable
00073   */
00074 ErrorStatus LL_PWR_DeInit(void)
00075 {
00076   /* Force reset of PWR clock */
00077   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
00078
00079   /* Release reset of PWR clock */
00080   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
00081
00082   return SUCCESS;
00083 }
00084
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /**
00094   * @}
00095   */
00096 #endif /* defined(PWR) */
00097 /**
00098   * @}
00099   */
00100
00101 #endif /* USE_FULL_LL_DRIVER */
00102
00103 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_pwr.h Source File

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stm32l4xx_ll_pwr.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_pwr.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of PWR LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_PWR_H
00040 #define __STM32L4xx_LL_PWR_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(PWR)
00054
00055 /** @defgroup PWR_LL PWR
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063
00064 /* Private macros ------------------------------------------------------------*/
00065
00066 /* Exported types ------------------------------------------------------------*/
00067 /* Exported constants --------------------------------------------------------*/
00068 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
00069   * @{
00070   */
00071
00072 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
00073   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
00074   * @{
00075   */
00076 #define LL_PWR_SCR_CSBF                    PWR_SCR_CSBF
00077 #define LL_PWR_SCR_CWUF                    PWR_SCR_CWUF
00078 #define LL_PWR_SCR_CWUF5                   PWR_SCR_CWUF5
00079 #define LL_PWR_SCR_CWUF4                   PWR_SCR_CWUF4
00080 #define LL_PWR_SCR_CWUF3                   PWR_SCR_CWUF3
00081 #define LL_PWR_SCR_CWUF2                   PWR_SCR_CWUF2
00082 #define LL_PWR_SCR_CWUF1                   PWR_SCR_CWUF1
00083 /**
00084   * @}
00085   */
00086
00087 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
00088   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
00089   * @{
00090   */
00091 #define LL_PWR_SR1_WUFI                    PWR_SR1_WUFI
00092 #define LL_PWR_SR1_SBF                     PWR_SR1_SBF
00093 #define LL_PWR_SR1_WUF5                    PWR_SR1_WUF5
00094 #define LL_PWR_SR1_WUF4                    PWR_SR1_WUF4
00095 #define LL_PWR_SR1_WUF3                    PWR_SR1_WUF3
00096 #define LL_PWR_SR1_WUF2                    PWR_SR1_WUF2
00097 #define LL_PWR_SR1_WUF1                    PWR_SR1_WUF1
00098 #define LL_PWR_SR2_PVMO4                   PWR_SR2_PVMO4
00099 #define LL_PWR_SR2_PVMO3                   PWR_SR2_PVMO3
00100 #if defined(PWR_SR2_PVMO2)
00101 #define LL_PWR_SR2_PVMO2                   PWR_SR2_PVMO2
00102 #endif /* PWR_SR2_PVMO2 */
00103 #define LL_PWR_SR2_PVMO1                   PWR_SR2_PVMO1
00104 #define LL_PWR_SR2_PVDO                    PWR_SR2_PVDO
00105 #define LL_PWR_SR2_VOSF                    PWR_SR2_VOSF
00106 #define LL_PWR_SR2_REGLPF                  PWR_SR2_REGLPF
00107 #define LL_PWR_SR2_REGLPS                  PWR_SR2_REGLPS
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
00113   * @{
00114   */
00115 #define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR1_VOS_0)
00116 #define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR1_VOS_1)
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
00122   * @{
00123   */
00124 #define LL_PWR_MODE_STOP0                  (PWR_CR1_LPMS_STOP0)
00125 #define LL_PWR_MODE_STOP1                  (PWR_CR1_LPMS_STOP1)
00126 #define LL_PWR_MODE_STOP2                  (PWR_CR1_LPMS_STOP2)
00127 #define LL_PWR_MODE_STANDBY                (PWR_CR1_LPMS_STANDBY)
00128 #define LL_PWR_MODE_SHUTDOWN               (PWR_CR1_LPMS_SHUTDOWN)
00129 /**
00130   * @}
00131   */
00132
00133 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 PVM VDDUSB 1
00134   * @{
00135   */
00136 #if defined(USB_OTG_FS)
00137 #define LL_PWR_PVM_VDDUSB_1_2V             (PWR_CR2_PVME1)     /* Monitoring VDDUSB vs. 1.2V */
00138 #endif /* USB_OTG_FS */
00139 #if defined(PWR_CR2_PVME2)
00140 #define LL_PWR_PVM_VDDIO2_0_9V             (PWR_CR2_PVME2)     /* Monitoring VDDIO2 vs. 0.9V */
00141 #endif /* PWR_CR2_PVME2 */
00142 #define LL_PWR_PVM_VDDA_1_62V              (PWR_CR2_PVME3)     /* Monitoring VDDA vs. 1.62V  */
00143 #define LL_PWR_PVM_VDDA_2_2V               (PWR_CR2_PVME4)     /* Monitoring VDDA vs. 2.2V   */
00144 /**
00145   * @}
00146   */
00147
00148 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
00149   * @{
00150   */
00151 #define LL_PWR_PVDLEVEL_0                  (PWR_CR2_PLS_LEV0)  /* VPVD0 around 2.0 V */
00152 #define LL_PWR_PVDLEVEL_1                  (PWR_CR2_PLS_LEV1)  /* VPVD1 around 2.2 V */
00153 #define LL_PWR_PVDLEVEL_2                  (PWR_CR2_PLS_LEV2)  /* VPVD2 around 2.4 V */
00154 #define LL_PWR_PVDLEVEL_3                  (PWR_CR2_PLS_LEV3)  /* VPVD3 around 2.5 V */
00155 #define LL_PWR_PVDLEVEL_4                  (PWR_CR2_PLS_LEV4)  /* VPVD4 around 2.6 V */
00156 #define LL_PWR_PVDLEVEL_5                  (PWR_CR2_PLS_LEV5)  /* VPVD5 around 2.8 V */
00157 #define LL_PWR_PVDLEVEL_6                  (PWR_CR2_PLS_LEV6)  /* VPVD6 around 2.9 V */
00158 #define LL_PWR_PVDLEVEL_7                  (PWR_CR2_PLS_LEV7)  /* External input analog voltage   (Compare internally to VREFINT) */
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
00164   * @{
00165   */
00166 #define LL_PWR_WAKEUP_PIN1                 (PWR_CR3_EWUP1)
00167 #define LL_PWR_WAKEUP_PIN2                 (PWR_CR3_EWUP2)
00168 #define LL_PWR_WAKEUP_PIN3                 (PWR_CR3_EWUP3)
00169 #define LL_PWR_WAKEUP_PIN4                 (PWR_CR3_EWUP4)
00170 #define LL_PWR_WAKEUP_PIN5                 (PWR_CR3_EWUP5)
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
00176   * @{
00177   */
00178 #define LL_PWR_BATT_CHARG_RESISTOR_5K      ((uint32_t)0x00000000)
00179 #define LL_PWR_BATT_CHARGRESISTOR_1_5K     (PWR_CR4_VBRS)
00180 /**
00181   * @}
00182   */
00183
00184 /** @defgroup PWR_LL_EC_GPIO GPIO
00185   * @{
00186   */
00187 #define LL_PWR_GPIO_A                      ((uint32_t)(&(PWR->PUCRA)))
00188 #define LL_PWR_GPIO_B                      ((uint32_t)(&(PWR->PUCRB)))
00189 #define LL_PWR_GPIO_C                      ((uint32_t)(&(PWR->PUCRC)))
00190 #define LL_PWR_GPIO_D                      ((uint32_t)(&(PWR->PUCRD)))
00191 #define LL_PWR_GPIO_E                      ((uint32_t)(&(PWR->PUCRE)))
00192 #if defined(GPIOF)
00193 #define LL_PWR_GPIO_F                      ((uint32_t)(&(PWR->PUCRF)))
00194 #endif /* GPIOF */
00195 #if defined(GPIOG)
00196 #define LL_PWR_GPIO_G                      ((uint32_t)(&(PWR->PUCRG)))
00197 #endif /* GPIOG */
00198 #define LL_PWR_GPIO_H                      ((uint32_t)(&(PWR->PUCRH)))
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
00204   * @{
00205   */
00206 #define LL_PWR_GPIO_BIT_0                  ((uint32_t)0x00000001)
00207 #define LL_PWR_GPIO_BIT_1                  ((uint32_t)0x00000002)
00208 #define LL_PWR_GPIO_BIT_2                  ((uint32_t)0x00000004)
00209 #define LL_PWR_GPIO_BIT_3                  ((uint32_t)0x00000008)
00210 #define LL_PWR_GPIO_BIT_4                  ((uint32_t)0x00000010)
00211 #define LL_PWR_GPIO_BIT_5                  ((uint32_t)0x00000020)
00212 #define LL_PWR_GPIO_BIT_6                  ((uint32_t)0x00000040)
00213 #define LL_PWR_GPIO_BIT_7                  ((uint32_t)0x00000080)
00214 #define LL_PWR_GPIO_BIT_8                  ((uint32_t)0x00000100)
00215 #define LL_PWR_GPIO_BIT_9                  ((uint32_t)0x00000200)
00216 #define LL_PWR_GPIO_BIT_10                 ((uint32_t)0x00000400)
00217 #define LL_PWR_GPIO_BIT_11                 ((uint32_t)0x00000800)
00218 #define LL_PWR_GPIO_BIT_12                 ((uint32_t)0x00001000)
00219 #define LL_PWR_GPIO_BIT_13                 ((uint32_t)0x00002000)
00220 #define LL_PWR_GPIO_BIT_14                 ((uint32_t)0x00004000)
00221 #define LL_PWR_GPIO_BIT_15                 ((uint32_t)0x00008000)
00222 /**
00223   * @}
00224   */
00225
00226 /**
00227   * @}
00228   */
00229
00230 /* Exported macro ------------------------------------------------------------*/
00231 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
00232   * @{
00233   */
00234
00235 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
00236   * @{
00237   */
00238
00239 /**
00240   * @brief  Write a value in PWR register
00241   * @param  __REG__ Register to be written
00242   * @param  __VALUE__ Value to be written in the register
00243   * @retval None
00244   */
00245 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
00246
00247 /**
00248   * @brief  Read a value in PWR register
00249   * @param  __REG__ Register to be read
00250   * @retval Register value
00251   */
00252 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
00253 /**
00254   * @}
00255   */
00256
00257 /**
00258   * @}
00259   */
00260
00261
00262 /* Exported functions --------------------------------------------------------*/
00263 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
00264   * @{
00265   */
00266
00267 /** @defgroup PWR_LL_EF_Configuration Configuration
00268   * @{
00269   */
00270
00271 /**
00272   * @brief  Switch the regulator from main mode to low-power mode
00273   * @rmtoll CR1          LPR           LL_PWR_EnableLowPowerRunMode
00274   * @retval None
00275   */
00276 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
00277 {
00278   SET_BIT(PWR->CR1, PWR_CR1_LPR);
00279 }
00280
00281 /**
00282   * @brief  Switch the regulator from low-power mode to main mode
00283   * @rmtoll CR1          LPR           LL_PWR_DisableLowPowerRunMode
00284   * @retval None
00285   */
00286 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
00287 {
00288   CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
00289 }
00290
00291 /**
00292   * @brief  Check if the regulator is in low-power mode
00293   * @rmtoll CR1          LPR           LL_PWR_IsEnabledLowPowerRunMode
00294   * @retval State of bit (1 or 0).
00295   */
00296 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
00297 {
00298   return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR));
00299 }
00300
00301 /**
00302   * @brief  Switch from run main mode to run low-power mode.
00303   * @rmtoll CR1          LPR           LL_PWR_EnterLowPowerRunMode
00304   * @retval None
00305   */
00306 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
00307 {
00308   LL_PWR_EnableLowPowerRunMode();
00309 }
00310
00311 /**
00312   * @brief  Switch from run main mode to low-power mode.
00313   * @rmtoll CR1          LPR           LL_PWR_ExitLowPowerRunMode
00314   * @retval None
00315   */
00316 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
00317 {
00318   LL_PWR_DisableLowPowerRunMode();
00319 }
00320
00321 /**
00322   * @brief  Set the main internal regulator output voltage
00323   * @rmtoll CR1          VOS           LL_PWR_SetRegulVoltageScaling
00324   * @param  VoltageScaling This parameter can be one of the following values:
00325   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
00326   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
00327   * @retval None
00328   */
00329 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
00330 {
00331   MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
00332 }
00333
00334 /**
00335   * @brief  Get the main internal regulator output voltage
00336   * @rmtoll CR1          VOS           LL_PWR_GetRegulVoltageScaling
00337   * @retval Returned value can be one of the following values:
00338   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
00339   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
00340   */
00341 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
00342 {
00343   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
00344 }
00345
00346 /**
00347   * @brief  Enable access to the backup domain
00348   * @rmtoll CR1          DBP           LL_PWR_EnableBkUpAccess
00349   * @retval None
00350   */
00351 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
00352 {
00353   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00354 }
00355
00356 /**
00357   * @brief  Disable access to the backup domain
00358   * @rmtoll CR1          DBP           LL_PWR_DisableBkUpAccess
00359   * @retval None
00360   */
00361 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
00362 {
00363   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00364 }
00365
00366 /**
00367   * @brief  Check if the backup domain is enabled
00368   * @rmtoll CR1          DBP           LL_PWR_IsEnabledBkUpAccess
00369   * @retval State of bit (1 or 0).
00370   */
00371 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
00372 {
00373   return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP));
00374 }
00375
00376 /**
00377   * @brief  Set Low-Power mode
00378   * @rmtoll CR1          LPMS          LL_PWR_SetPowerMode
00379   * @param  LowPowerMode This parameter can be one of the following values:
00380   *         @arg @ref LL_PWR_MODE_STOP0
00381   *         @arg @ref LL_PWR_MODE_STOP1
00382   *         @arg @ref LL_PWR_MODE_STOP2
00383   *         @arg @ref LL_PWR_MODE_STANDBY
00384   *         @arg @ref LL_PWR_MODE_SHUTDOWN
00385   * @retval None
00386   */
00387 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
00388 {
00389   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
00390 }
00391
00392 /**
00393   * @brief  Get Low-Power mode
00394   * @rmtoll CR1          LPMS          LL_PWR_GetPowerMode
00395   * @retval Returned value can be one of the following values:
00396   *         @arg @ref LL_PWR_MODE_STOP0
00397   *         @arg @ref LL_PWR_MODE_STOP1
00398   *         @arg @ref LL_PWR_MODE_STOP2
00399   *         @arg @ref LL_PWR_MODE_STANDBY
00400   *         @arg @ref LL_PWR_MODE_SHUTDOWN
00401   */
00402 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
00403 {
00404   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
00405 }
00406
00407 #if defined(USB_OTG_FS)
00408 /**
00409   * @brief  Enable VDDUSB supply
00410   * @rmtoll CR2          USV           LL_PWR_EnableVddUSB
00411   * @retval None
00412   */
00413 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
00414 {
00415   SET_BIT(PWR->CR2, PWR_CR2_USV);
00416 }
00417 #endif /* USB_OTG_FS */
00418
00419 #if defined(USB_OTG_FS)
00420 /**
00421   * @brief  Disable VDDUSB supply
00422   * @rmtoll CR2          USV           LL_PWR_DisableVddUSB
00423   * @retval None
00424   */
00425 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
00426 {
00427   CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
00428 }
00429 #endif /* USB_OTG_FS */
00430
00431 #if defined(USB_OTG_FS)
00432 /**
00433   * @brief  Check if VDDUSB supply is enabled
00434   * @rmtoll CR2          USV           LL_PWR_IsEnabledVddUSB
00435   * @retval State of bit (1 or 0).
00436   */
00437 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
00438 {
00439   return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV));
00440 }
00441 #endif /* USB_OTG_FS */
00442
00443 #if defined(PWR_CR2_IOSV)
00444 /**
00445   * @brief  Enable VDDIO2 supply
00446   * @rmtoll CR2          IOSV          LL_PWR_EnableVddIO2
00447   * @retval None
00448   */
00449 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
00450 {
00451   SET_BIT(PWR->CR2, PWR_CR2_IOSV);
00452 }
00453
00454 /**
00455   * @brief  Disable VDDIO2 supply
00456   * @rmtoll CR2          IOSV          LL_PWR_DisableVddIO2
00457   * @retval None
00458   */
00459 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
00460 {
00461   CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
00462 }
00463
00464 /**
00465   * @brief  Check if VDDIO2 supply is enabled
00466   * @rmtoll CR2          IOSV          LL_PWR_IsEnabledVddIO2
00467   * @retval State of bit (1 or 0).
00468   */
00469 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
00470 {
00471   return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV));
00472 }
00473 #endif /* PWR_CR2_IOSV */
00474
00475 /**
00476   * @brief  Enable the Power Voltage Monitoring on a peripheral
00477   * @rmtoll CR2          PVME1         LL_PWR_EnablePVM\n
00478   *         CR2          PVME2         LL_PWR_EnablePVM\n
00479   *         CR2          PVME3         LL_PWR_EnablePVM\n
00480   *         CR2          PVME4         LL_PWR_EnablePVM
00481   * @param  PeriphVoltage This parameter can be one of the following values:
00482   *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
00483   *         @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
00484   *         @arg @ref LL_PWR_PVM_VDDA_1_62V
00485   *         @arg @ref LL_PWR_PVM_VDDA_2_2V
00486   *
00487   *         (*) value not defined in all devices
00488   * @retval None
00489   */
00490 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
00491 {
00492   SET_BIT(PWR->CR2, PeriphVoltage);
00493 }
00494
00495 /**
00496   * @brief  Disable the Power Voltage Monitoring on a peripheral
00497   * @rmtoll CR2          PVME1         LL_PWR_DisablePVM\n
00498   *         CR2          PVME2         LL_PWR_DisablePVM\n
00499   *         CR2          PVME3         LL_PWR_DisablePVM\n
00500   *         CR2          PVME4         LL_PWR_DisablePVM
00501   * @param  PeriphVoltage This parameter can be one of the following values:
00502   *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
00503   *         @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
00504   *         @arg @ref LL_PWR_PVM_VDDA_1_62V
00505   *         @arg @ref LL_PWR_PVM_VDDA_2_2V
00506   *
00507   *         (*) value not defined in all devices
00508   * @retval None
00509   */
00510 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
00511 {
00512   CLEAR_BIT(PWR->CR2, PeriphVoltage);
00513 }
00514
00515 /**
00516   * @brief  Check if Power Voltage Monitoring  is enabled on a peripheral
00517   * @rmtoll CR2          PVME1         LL_PWR_IsEnabledPVM\n
00518   *         CR2          PVME2         LL_PWR_IsEnabledPVM\n
00519   *         CR2          PVME3         LL_PWR_IsEnabledPVM\n
00520   *         CR2          PVME4         LL_PWR_IsEnabledPVM
00521   * @param  PeriphVoltage This parameter can be one of the following values:
00522   *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
00523   *         @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
00524   *         @arg @ref LL_PWR_PVM_VDDA_1_62V
00525   *         @arg @ref LL_PWR_PVM_VDDA_2_2V
00526   *
00527   *         (*) value not defined in all devices
00528   * @retval State of bit (1 or 0).
00529   */
00530 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
00531 {
00532   return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage));
00533 }
00534
00535 /**
00536   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
00537   * @rmtoll CR2          PLS           LL_PWR_SetPVDLevel
00538   * @param  PVDLevel This parameter can be one of the following values:
00539   *         @arg @ref LL_PWR_PVDLEVEL_0
00540   *         @arg @ref LL_PWR_PVDLEVEL_1
00541   *         @arg @ref LL_PWR_PVDLEVEL_2
00542   *         @arg @ref LL_PWR_PVDLEVEL_3
00543   *         @arg @ref LL_PWR_PVDLEVEL_4
00544   *         @arg @ref LL_PWR_PVDLEVEL_5
00545   *         @arg @ref LL_PWR_PVDLEVEL_6
00546   *         @arg @ref LL_PWR_PVDLEVEL_7
00547   * @retval None
00548   */
00549 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
00550 {
00551   MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
00552 }
00553
00554 /**
00555   * @brief  Get the voltage threshold detection
00556   * @rmtoll CR2          PLS           LL_PWR_GetPVDLevel
00557   * @retval Returned value can be one of the following values:
00558   *         @arg @ref LL_PWR_PVDLEVEL_0
00559   *         @arg @ref LL_PWR_PVDLEVEL_1
00560   *         @arg @ref LL_PWR_PVDLEVEL_2
00561   *         @arg @ref LL_PWR_PVDLEVEL_3
00562   *         @arg @ref LL_PWR_PVDLEVEL_4
00563   *         @arg @ref LL_PWR_PVDLEVEL_5
00564   *         @arg @ref LL_PWR_PVDLEVEL_6
00565   *         @arg @ref LL_PWR_PVDLEVEL_7
00566   */
00567 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
00568 {
00569   return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
00570 }
00571
00572 /**
00573   * @brief  Enable Power Voltage Detector
00574   * @rmtoll CR2          PVDE          LL_PWR_EnablePVD
00575   * @retval None
00576   */
00577 __STATIC_INLINE void LL_PWR_EnablePVD(void)
00578 {
00579   SET_BIT(PWR->CR2, PWR_CR2_PVDE);
00580 }
00581
00582 /**
00583   * @brief  Disable Power Voltage Detector
00584   * @rmtoll CR2          PVDE          LL_PWR_DisablePVD
00585   * @retval None
00586   */
00587 __STATIC_INLINE void LL_PWR_DisablePVD(void)
00588 {
00589   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
00590 }
00591
00592 /**
00593   * @brief  Check if Power Voltage Detector is enabled
00594   * @rmtoll CR2          PVDE          LL_PWR_IsEnabledPVD
00595   * @retval State of bit (1 or 0).
00596   */
00597 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
00598 {
00599   return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE));
00600 }
00601
00602 /**
00603   * @brief  Enable Internal Wake-up line
00604   * @rmtoll CR3          EIWF          LL_PWR_EnableInternWU
00605   * @retval None
00606   */
00607 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
00608 {
00609   SET_BIT(PWR->CR3, PWR_CR3_EIWF);
00610 }
00611
00612 /**
00613   * @brief  Disable Internal Wake-up line
00614   * @rmtoll CR3          EIWF          LL_PWR_DisableInternWU
00615   * @retval None
00616   */
00617 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
00618 {
00619   CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
00620 }
00621
00622 /**
00623   * @brief  Check if Internal Wake-up line is enabled
00624   * @rmtoll CR3          EIWF          LL_PWR_IsEnabledInternWU
00625   * @retval State of bit (1 or 0).
00626   */
00627 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
00628 {
00629   return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF));
00630 }
00631
00632 /**
00633   * @brief  Enable pull-up and pull-down configuration
00634   * @rmtoll CR3          APC           LL_PWR_EnablePUPDCfg
00635   * @retval None
00636   */
00637 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
00638 {
00639   SET_BIT(PWR->CR3, PWR_CR3_APC);
00640 }
00641
00642 /**
00643   * @brief  Disable pull-up and pull-down configuration
00644   * @rmtoll CR3          APC           LL_PWR_DisablePUPDCfg
00645   * @retval None
00646   */
00647 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
00648 {
00649   CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
00650 }
00651
00652 /**
00653   * @brief  Check if pull-up and pull-down configuration  is enabled
00654   * @rmtoll CR3          APC           LL_PWR_IsEnabledPUPDCfg
00655   * @retval State of bit (1 or 0).
00656   */
00657 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
00658 {
00659   return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC));
00660 }
00661
00662 /**
00663   * @brief  Enable SRAM2 content retention in Standby mode
00664   * @rmtoll CR3          RRS           LL_PWR_EnableSRAM2Retention
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
00668 {
00669   SET_BIT(PWR->CR3, PWR_CR3_RRS);
00670 }
00671
00672 /**
00673   * @brief  Disable SRAM2 content retention in Standby mode
00674   * @rmtoll CR3          RRS           LL_PWR_DisableSRAM2Retention
00675   * @retval None
00676   */
00677 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
00678 {
00679   CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
00680 }
00681
00682 /**
00683   * @brief  Check if SRAM2 content retention in Standby mode  is enabled
00684   * @rmtoll CR3          RRS           LL_PWR_IsEnabledSRAM2Retention
00685   * @retval State of bit (1 or 0).
00686   */
00687 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
00688 {
00689   return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS));
00690 }
00691
00692 /**
00693   * @brief  Enable the WakeUp PINx functionality
00694   * @rmtoll CR3          EWUP1         LL_PWR_EnableWakeUpPin\n
00695   *         CR3          EWUP2         LL_PWR_EnableWakeUpPin\n
00696   *         CR3          EWUP3         LL_PWR_EnableWakeUpPin\n
00697   *         CR3          EWUP4         LL_PWR_EnableWakeUpPin\n
00698   *         CR3          EWUP5         LL_PWR_EnableWakeUpPin
00699   * @param  WakeUpPin This parameter can be one of the following values:
00700   *         @arg @ref LL_PWR_WAKEUP_PIN1
00701   *         @arg @ref LL_PWR_WAKEUP_PIN2
00702   *         @arg @ref LL_PWR_WAKEUP_PIN3
00703   *         @arg @ref LL_PWR_WAKEUP_PIN4
00704   *         @arg @ref LL_PWR_WAKEUP_PIN5
00705   * @retval None
00706   */
00707 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
00708 {
00709   SET_BIT(PWR->CR3, WakeUpPin);
00710 }
00711
00712 /**
00713   * @brief  Disable the WakeUp PINx functionality
00714   * @rmtoll CR3          EWUP1         LL_PWR_DisableWakeUpPin\n
00715   *         CR3          EWUP2         LL_PWR_DisableWakeUpPin\n
00716   *         CR3          EWUP3         LL_PWR_DisableWakeUpPin\n
00717   *         CR3          EWUP4         LL_PWR_DisableWakeUpPin\n
00718   *         CR3          EWUP5         LL_PWR_DisableWakeUpPin
00719   * @param  WakeUpPin This parameter can be one of the following values:
00720   *         @arg @ref LL_PWR_WAKEUP_PIN1
00721   *         @arg @ref LL_PWR_WAKEUP_PIN2
00722   *         @arg @ref LL_PWR_WAKEUP_PIN3
00723   *         @arg @ref LL_PWR_WAKEUP_PIN4
00724   *         @arg @ref LL_PWR_WAKEUP_PIN5
00725   * @retval None
00726   */
00727 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
00728 {
00729   CLEAR_BIT(PWR->CR3, WakeUpPin);
00730 }
00731
00732 /**
00733   * @brief  Check if the WakeUp PINx functionality is enabled
00734   * @rmtoll CR3          EWUP1         LL_PWR_IsEnabledWakeUpPin\n
00735   *         CR3          EWUP2         LL_PWR_IsEnabledWakeUpPin\n
00736   *         CR3          EWUP3         LL_PWR_IsEnabledWakeUpPin\n
00737   *         CR3          EWUP4         LL_PWR_IsEnabledWakeUpPin\n
00738   *         CR3          EWUP5         LL_PWR_IsEnabledWakeUpPin
00739   * @param  WakeUpPin This parameter can be one of the following values:
00740   *         @arg @ref LL_PWR_WAKEUP_PIN1
00741   *         @arg @ref LL_PWR_WAKEUP_PIN2
00742   *         @arg @ref LL_PWR_WAKEUP_PIN3
00743   *         @arg @ref LL_PWR_WAKEUP_PIN4
00744   *         @arg @ref LL_PWR_WAKEUP_PIN5
00745   * @retval State of bit (1 or 0).
00746   */
00747 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
00748 {
00749   return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin));
00750 }
00751
00752 /**
00753   * @brief  Set the resistor impedance
00754   * @rmtoll CR4          VBRS          LL_PWR_SetBattChargResistor
00755   * @param  Resistor This parameter can be one of the following values:
00756   *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
00757   *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
00758   * @retval None
00759   */
00760 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
00761 {
00762   MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
00763 }
00764
00765 /**
00766   * @brief  Get the resistor impedance
00767   * @rmtoll CR4          VBRS          LL_PWR_GetBattChargResistor
00768   * @retval Returned value can be one of the following values:
00769   *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
00770   *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
00771   */
00772 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
00773 {
00774   return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
00775 }
00776
00777 /**
00778   * @brief  Enable battery charging
00779   * @rmtoll CR4          VBE           LL_PWR_EnableBatteryCharging
00780   * @retval None
00781   */
00782 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
00783 {
00784   SET_BIT(PWR->CR4, PWR_CR4_VBE);
00785 }
00786
00787 /**
00788   * @brief  Disable battery charging
00789   * @rmtoll CR4          VBE           LL_PWR_DisableBatteryCharging
00790   * @retval None
00791   */
00792 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
00793 {
00794   CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
00795 }
00796
00797 /**
00798   * @brief  Check if battery charging is enabled
00799   * @rmtoll CR4          VBE           LL_PWR_IsEnabledBatteryCharging
00800   * @retval State of bit (1 or 0).
00801   */
00802 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
00803 {
00804   return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE));
00805 }
00806
00807 /**
00808   * @brief  Set the Wake-Up pin polarity low for the event detection
00809   * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityLow\n
00810   *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityLow\n
00811   *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityLow\n
00812   *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityLow\n
00813   *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityLow
00814   * @param  WakeUpPin This parameter can be one of the following values:
00815   *         @arg @ref LL_PWR_WAKEUP_PIN1
00816   *         @arg @ref LL_PWR_WAKEUP_PIN2
00817   *         @arg @ref LL_PWR_WAKEUP_PIN3
00818   *         @arg @ref LL_PWR_WAKEUP_PIN4
00819   *         @arg @ref LL_PWR_WAKEUP_PIN5
00820   * @retval None
00821   */
00822 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
00823 {
00824   SET_BIT(PWR->CR4, WakeUpPin);
00825 }
00826
00827 /**
00828   * @brief  Set the Wake-Up pin polarity high for the event detection
00829   * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityHigh\n
00830   *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityHigh\n
00831   *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityHigh\n
00832   *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityHigh\n
00833   *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityHigh
00834   * @param  WakeUpPin This parameter can be one of the following values:
00835   *         @arg @ref LL_PWR_WAKEUP_PIN1
00836   *         @arg @ref LL_PWR_WAKEUP_PIN2
00837   *         @arg @ref LL_PWR_WAKEUP_PIN3
00838   *         @arg @ref LL_PWR_WAKEUP_PIN4
00839   *         @arg @ref LL_PWR_WAKEUP_PIN5
00840   * @retval None
00841   */
00842 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
00843 {
00844   CLEAR_BIT(PWR->CR4, WakeUpPin);
00845 }
00846
00847 /**
00848   * @brief  Get the Wake-Up pin polarity for the event detection
00849   * @rmtoll CR4          WP1           LL_PWR_IsWakeUpPinPolarityLow\n
00850   *         CR4          WP2           LL_PWR_IsWakeUpPinPolarityLow\n
00851   *         CR4          WP3           LL_PWR_IsWakeUpPinPolarityLow\n
00852   *         CR4          WP4           LL_PWR_IsWakeUpPinPolarityLow\n
00853   *         CR4          WP5           LL_PWR_IsWakeUpPinPolarityLow
00854   * @param  WakeUpPin This parameter can be one of the following values:
00855   *         @arg @ref LL_PWR_WAKEUP_PIN1
00856   *         @arg @ref LL_PWR_WAKEUP_PIN2
00857   *         @arg @ref LL_PWR_WAKEUP_PIN3
00858   *         @arg @ref LL_PWR_WAKEUP_PIN4
00859   *         @arg @ref LL_PWR_WAKEUP_PIN5
00860   * @retval State of bit (1 or 0).
00861   */
00862 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
00863 {
00864   return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin));
00865 }
00866
00867 /**
00868   * @brief  Enable GPIO pull-up state in Standby and Shutdown modes
00869   * @rmtoll PUCRA        PU0-15        LL_PWR_EnableGPIOPullUp\n
00870   *         PUCRB        PU0-15        LL_PWR_EnableGPIOPullUp\n
00871   *         PUCRC        PU0-15        LL_PWR_EnableGPIOPullUp\n
00872   *         PUCRD        PU0-15        LL_PWR_EnableGPIOPullUp\n
00873   *         PUCRE        PU0-15        LL_PWR_EnableGPIOPullUp\n
00874   *         PUCRF        PU0-15        LL_PWR_EnableGPIOPullUp\n
00875   *         PUCRG        PU0-15        LL_PWR_EnableGPIOPullUp\n
00876   *         PUCRH        PU0-1         LL_PWR_EnableGPIOPullUp
00877   * @param  GPIO This parameter can be one of the following values:
00878   *         @arg @ref LL_PWR_GPIO_A
00879   *         @arg @ref LL_PWR_GPIO_B
00880   *         @arg @ref LL_PWR_GPIO_C
00881   *         @arg @ref LL_PWR_GPIO_D
00882   *         @arg @ref LL_PWR_GPIO_E
00883   *         @arg @ref LL_PWR_GPIO_F (*)
00884   *         @arg @ref LL_PWR_GPIO_G (*)
00885   *         @arg @ref LL_PWR_GPIO_H
00886   *
00887   *         (*) value not defined in all devices
00888   * @param  GPIONumber This parameter can be one of the following values:
00889   *         @arg @ref LL_PWR_GPIO_BIT_0
00890   *         @arg @ref LL_PWR_GPIO_BIT_1
00891   *         @arg @ref LL_PWR_GPIO_BIT_2
00892   *         @arg @ref LL_PWR_GPIO_BIT_3
00893   *         @arg @ref LL_PWR_GPIO_BIT_4
00894   *         @arg @ref LL_PWR_GPIO_BIT_5
00895   *         @arg @ref LL_PWR_GPIO_BIT_6
00896   *         @arg @ref LL_PWR_GPIO_BIT_7
00897   *         @arg @ref LL_PWR_GPIO_BIT_8
00898   *         @arg @ref LL_PWR_GPIO_BIT_9
00899   *         @arg @ref LL_PWR_GPIO_BIT_10
00900   *         @arg @ref LL_PWR_GPIO_BIT_11
00901   *         @arg @ref LL_PWR_GPIO_BIT_12
00902   *         @arg @ref LL_PWR_GPIO_BIT_13
00903   *         @arg @ref LL_PWR_GPIO_BIT_14
00904   *         @arg @ref LL_PWR_GPIO_BIT_15
00905   * @retval None
00906   */
00907 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00908 {
00909   SET_BIT(*((uint32_t *)GPIO), GPIONumber);
00910 }
00911
00912 /**
00913   * @brief  Disable GPIO pull-up state in Standby and Shutdown modes
00914   * @rmtoll PUCRA        PU0-15        LL_PWR_DisableGPIOPullUp\n
00915   *         PUCRB        PU0-15        LL_PWR_DisableGPIOPullUp\n
00916   *         PUCRC        PU0-15        LL_PWR_DisableGPIOPullUp\n
00917   *         PUCRD        PU0-15        LL_PWR_DisableGPIOPullUp\n
00918   *         PUCRE        PU0-15        LL_PWR_DisableGPIOPullUp\n
00919   *         PUCRF        PU0-15        LL_PWR_DisableGPIOPullUp\n
00920   *         PUCRG        PU0-15        LL_PWR_DisableGPIOPullUp\n
00921   *         PUCRH        PU0-1         LL_PWR_DisableGPIOPullUp
00922   * @param  GPIO This parameter can be one of the following values:
00923   *         @arg @ref LL_PWR_GPIO_A
00924   *         @arg @ref LL_PWR_GPIO_B
00925   *         @arg @ref LL_PWR_GPIO_C
00926   *         @arg @ref LL_PWR_GPIO_D
00927   *         @arg @ref LL_PWR_GPIO_E
00928   *         @arg @ref LL_PWR_GPIO_F (*)
00929   *         @arg @ref LL_PWR_GPIO_G (*)
00930   *         @arg @ref LL_PWR_GPIO_H
00931   *
00932   *         (*) value not defined in all devices
00933   * @param  GPIONumber This parameter can be one of the following values:
00934   *         @arg @ref LL_PWR_GPIO_BIT_0
00935   *         @arg @ref LL_PWR_GPIO_BIT_1
00936   *         @arg @ref LL_PWR_GPIO_BIT_2
00937   *         @arg @ref LL_PWR_GPIO_BIT_3
00938   *         @arg @ref LL_PWR_GPIO_BIT_4
00939   *         @arg @ref LL_PWR_GPIO_BIT_5
00940   *         @arg @ref LL_PWR_GPIO_BIT_6
00941   *         @arg @ref LL_PWR_GPIO_BIT_7
00942   *         @arg @ref LL_PWR_GPIO_BIT_8
00943   *         @arg @ref LL_PWR_GPIO_BIT_9
00944   *         @arg @ref LL_PWR_GPIO_BIT_10
00945   *         @arg @ref LL_PWR_GPIO_BIT_11
00946   *         @arg @ref LL_PWR_GPIO_BIT_12
00947   *         @arg @ref LL_PWR_GPIO_BIT_13
00948   *         @arg @ref LL_PWR_GPIO_BIT_14
00949   *         @arg @ref LL_PWR_GPIO_BIT_15
00950   * @retval None
00951   */
00952 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00953 {
00954   CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber);
00955 }
00956
00957 /**
00958   * @brief  Check if GPIO pull-up state is enabled
00959   * @rmtoll PUCRA        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
00960   *         PUCRB        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
00961   *         PUCRC        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
00962   *         PUCRD        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
00963   *         PUCRE        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
00964   *         PUCRF        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
00965   *         PUCRG        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
00966   *         PUCRH        PU0-1         LL_PWR_IsEnabledGPIOPullUp
00967   * @param  GPIO This parameter can be one of the following values:
00968   *         @arg @ref LL_PWR_GPIO_A
00969   *         @arg @ref LL_PWR_GPIO_B
00970   *         @arg @ref LL_PWR_GPIO_C
00971   *         @arg @ref LL_PWR_GPIO_D
00972   *         @arg @ref LL_PWR_GPIO_E
00973   *         @arg @ref LL_PWR_GPIO_F (*)
00974   *         @arg @ref LL_PWR_GPIO_G (*)
00975   *         @arg @ref LL_PWR_GPIO_H
00976   *
00977   *         (*) value not defined in all devices
00978   * @param  GPIONumber This parameter can be one of the following values:
00979   *         @arg @ref LL_PWR_GPIO_BIT_0
00980   *         @arg @ref LL_PWR_GPIO_BIT_1
00981   *         @arg @ref LL_PWR_GPIO_BIT_2
00982   *         @arg @ref LL_PWR_GPIO_BIT_3
00983   *         @arg @ref LL_PWR_GPIO_BIT_4
00984   *         @arg @ref LL_PWR_GPIO_BIT_5
00985   *         @arg @ref LL_PWR_GPIO_BIT_6
00986   *         @arg @ref LL_PWR_GPIO_BIT_7
00987   *         @arg @ref LL_PWR_GPIO_BIT_8
00988   *         @arg @ref LL_PWR_GPIO_BIT_9
00989   *         @arg @ref LL_PWR_GPIO_BIT_10
00990   *         @arg @ref LL_PWR_GPIO_BIT_11
00991   *         @arg @ref LL_PWR_GPIO_BIT_12
00992   *         @arg @ref LL_PWR_GPIO_BIT_13
00993   *         @arg @ref LL_PWR_GPIO_BIT_14
00994   *         @arg @ref LL_PWR_GPIO_BIT_15
00995   * @retval State of bit (1 or 0).
00996   */
00997 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00998 {
00999   return (READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber));
01000 }
01001
01002 /**
01003   * @brief  Enable GPIO pull-down state in Standby and Shutdown modes
01004   * @rmtoll PDCRA        PD0-15        LL_PWR_EnableGPIOPullDown\n
01005   *         PDCRB        PD0-15        LL_PWR_EnableGPIOPullDown\n
01006   *         PDCRC        PD0-15        LL_PWR_EnableGPIOPullDown\n
01007   *         PDCRD        PD0-15        LL_PWR_EnableGPIOPullDown\n
01008   *         PDCRE        PD0-15        LL_PWR_EnableGPIOPullDown\n
01009   *         PDCRF        PD0-15        LL_PWR_EnableGPIOPullDown\n
01010   *         PDCRG        PD0-15        LL_PWR_EnableGPIOPullDown\n
01011   *         PDCRH        PD0-1         LL_PWR_EnableGPIOPullDown
01012   * @param  GPIO This parameter can be one of the following values:
01013   *         @arg @ref LL_PWR_GPIO_A
01014   *         @arg @ref LL_PWR_GPIO_B
01015   *         @arg @ref LL_PWR_GPIO_C
01016   *         @arg @ref LL_PWR_GPIO_D
01017   *         @arg @ref LL_PWR_GPIO_E
01018   *         @arg @ref LL_PWR_GPIO_F (*)
01019   *         @arg @ref LL_PWR_GPIO_G (*)
01020   *         @arg @ref LL_PWR_GPIO_H
01021   *
01022   *         (*) value not defined in all devices
01023   * @param  GPIONumber This parameter can be one of the following values:
01024   *         @arg @ref LL_PWR_GPIO_BIT_0
01025   *         @arg @ref LL_PWR_GPIO_BIT_1
01026   *         @arg @ref LL_PWR_GPIO_BIT_2
01027   *         @arg @ref LL_PWR_GPIO_BIT_3
01028   *         @arg @ref LL_PWR_GPIO_BIT_4
01029   *         @arg @ref LL_PWR_GPIO_BIT_5
01030   *         @arg @ref LL_PWR_GPIO_BIT_6
01031   *         @arg @ref LL_PWR_GPIO_BIT_7
01032   *         @arg @ref LL_PWR_GPIO_BIT_8
01033   *         @arg @ref LL_PWR_GPIO_BIT_9
01034   *         @arg @ref LL_PWR_GPIO_BIT_10
01035   *         @arg @ref LL_PWR_GPIO_BIT_11
01036   *         @arg @ref LL_PWR_GPIO_BIT_12
01037   *         @arg @ref LL_PWR_GPIO_BIT_13
01038   *         @arg @ref LL_PWR_GPIO_BIT_14
01039   *         @arg @ref LL_PWR_GPIO_BIT_15
01040   * @retval None
01041   */
01042 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01043 {
01044   register uint32_t temp = (uint32_t)(GPIO) + 4;
01045   SET_BIT(*((uint32_t *)(temp)), GPIONumber);
01046 }
01047
01048 /**
01049   * @brief  Disable GPIO pull-down state in Standby and Shutdown modes
01050   * @rmtoll PDCRA        PD0-15        LL_PWR_DisableGPIOPullDown\n
01051   *         PDCRB        PD0-15        LL_PWR_DisableGPIOPullDown\n
01052   *         PDCRC        PD0-15        LL_PWR_DisableGPIOPullDown\n
01053   *         PDCRD        PD0-15        LL_PWR_DisableGPIOPullDown\n
01054   *         PDCRE        PD0-15        LL_PWR_DisableGPIOPullDown\n
01055   *         PDCRF        PD0-15        LL_PWR_DisableGPIOPullDown\n
01056   *         PDCRG        PD0-15        LL_PWR_DisableGPIOPullDown\n
01057   *         PDCRH        PD0-1         LL_PWR_DisableGPIOPullDown
01058   * @param  GPIO This parameter can be one of the following values:
01059   *         @arg @ref LL_PWR_GPIO_A
01060   *         @arg @ref LL_PWR_GPIO_B
01061   *         @arg @ref LL_PWR_GPIO_C
01062   *         @arg @ref LL_PWR_GPIO_D
01063   *         @arg @ref LL_PWR_GPIO_E
01064   *         @arg @ref LL_PWR_GPIO_F (*)
01065   *         @arg @ref LL_PWR_GPIO_G (*)
01066   *         @arg @ref LL_PWR_GPIO_H
01067   *
01068   *         (*) value not defined in all devices
01069   * @param  GPIONumber This parameter can be one of the following values:
01070   *         @arg @ref LL_PWR_GPIO_BIT_0
01071   *         @arg @ref LL_PWR_GPIO_BIT_1
01072   *         @arg @ref LL_PWR_GPIO_BIT_2
01073   *         @arg @ref LL_PWR_GPIO_BIT_3
01074   *         @arg @ref LL_PWR_GPIO_BIT_4
01075   *         @arg @ref LL_PWR_GPIO_BIT_5
01076   *         @arg @ref LL_PWR_GPIO_BIT_6
01077   *         @arg @ref LL_PWR_GPIO_BIT_7
01078   *         @arg @ref LL_PWR_GPIO_BIT_8
01079   *         @arg @ref LL_PWR_GPIO_BIT_9
01080   *         @arg @ref LL_PWR_GPIO_BIT_10
01081   *         @arg @ref LL_PWR_GPIO_BIT_11
01082   *         @arg @ref LL_PWR_GPIO_BIT_12
01083   *         @arg @ref LL_PWR_GPIO_BIT_13
01084   *         @arg @ref LL_PWR_GPIO_BIT_14
01085   *         @arg @ref LL_PWR_GPIO_BIT_15
01086   * @retval None
01087   */
01088 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01089 {
01090   register uint32_t temp = (uint32_t)(GPIO) + 4;
01091   CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber);
01092 }
01093
01094 /**
01095   * @brief  Check if GPIO pull-down state is enabled
01096   * @rmtoll PDCRA        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01097   *         PDCRB        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01098   *         PDCRC        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01099   *         PDCRD        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01100   *         PDCRE        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01101   *         PDCRF        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01102   *         PDCRG        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01103   *         PDCRH        PD0-1         LL_PWR_IsEnabledGPIOPullDown
01104   * @param  GPIO This parameter can be one of the following values:
01105   *         @arg @ref LL_PWR_GPIO_A
01106   *         @arg @ref LL_PWR_GPIO_B
01107   *         @arg @ref LL_PWR_GPIO_C
01108   *         @arg @ref LL_PWR_GPIO_D
01109   *         @arg @ref LL_PWR_GPIO_E
01110   *         @arg @ref LL_PWR_GPIO_F (*)
01111   *         @arg @ref LL_PWR_GPIO_G (*)
01112   *         @arg @ref LL_PWR_GPIO_H
01113   *
01114   *         (*) value not defined in all devices
01115   * @param  GPIONumber This parameter can be one of the following values:
01116   *         @arg @ref LL_PWR_GPIO_BIT_0
01117   *         @arg @ref LL_PWR_GPIO_BIT_1
01118   *         @arg @ref LL_PWR_GPIO_BIT_2
01119   *         @arg @ref LL_PWR_GPIO_BIT_3
01120   *         @arg @ref LL_PWR_GPIO_BIT_4
01121   *         @arg @ref LL_PWR_GPIO_BIT_5
01122   *         @arg @ref LL_PWR_GPIO_BIT_6
01123   *         @arg @ref LL_PWR_GPIO_BIT_7
01124   *         @arg @ref LL_PWR_GPIO_BIT_8
01125   *         @arg @ref LL_PWR_GPIO_BIT_9
01126   *         @arg @ref LL_PWR_GPIO_BIT_10
01127   *         @arg @ref LL_PWR_GPIO_BIT_11
01128   *         @arg @ref LL_PWR_GPIO_BIT_12
01129   *         @arg @ref LL_PWR_GPIO_BIT_13
01130   *         @arg @ref LL_PWR_GPIO_BIT_14
01131   *         @arg @ref LL_PWR_GPIO_BIT_15
01132   * @retval State of bit (1 or 0).
01133   */
01134 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01135 {
01136   register uint32_t temp = (uint32_t)(GPIO) + 4;
01137   return (READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber));
01138 }
01139
01140 /**
01141   * @}
01142   */
01143
01144 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
01145   * @{
01146   */
01147
01148 /**
01149   * @brief  Get Internal Wake-up line Flag
01150   * @rmtoll SR1          WUFI          LL_PWR_IsActiveFlag_InternWU
01151   * @retval State of bit (1 or 0).
01152   */
01153 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
01154 {
01155   return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI));
01156 }
01157
01158 /**
01159   * @brief  Get Stand-By Flag
01160   * @rmtoll SR1          SBF           LL_PWR_IsActiveFlag_SB
01161   * @retval State of bit (1 or 0).
01162   */
01163 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
01164 {
01165   return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF));
01166 }
01167
01168 /**
01169   * @brief  Get Wake-up Flag 5
01170   * @rmtoll SR1          WUF5          LL_PWR_IsActiveFlag_WU5
01171   * @retval State of bit (1 or 0).
01172   */
01173 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
01174 {
01175   return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5));
01176 }
01177
01178 /**
01179   * @brief  Get Wake-up Flag 4
01180   * @rmtoll SR1          WUF4          LL_PWR_IsActiveFlag_WU4
01181   * @retval State of bit (1 or 0).
01182   */
01183 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
01184 {
01185   return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4));
01186 }
01187
01188 /**
01189   * @brief  Get Wake-up Flag 3
01190   * @rmtoll SR1          WUF3          LL_PWR_IsActiveFlag_WU3
01191   * @retval State of bit (1 or 0).
01192   */
01193 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
01194 {
01195   return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3));
01196 }
01197
01198 /**
01199   * @brief  Get Wake-up Flag 2
01200   * @rmtoll SR1          WUF2          LL_PWR_IsActiveFlag_WU2
01201   * @retval State of bit (1 or 0).
01202   */
01203 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
01204 {
01205   return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2));
01206 }
01207
01208 /**
01209   * @brief  Get Wake-up Flag 1
01210   * @rmtoll SR1          WUF1          LL_PWR_IsActiveFlag_WU1
01211   * @retval State of bit (1 or 0).
01212   */
01213 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
01214 {
01215   return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1));
01216 }
01217
01218 /**
01219   * @brief  Clear Stand-By Flag
01220   * @rmtoll SCR          CSBF          LL_PWR_ClearFlag_SB
01221   * @retval None
01222   */
01223 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
01224 {
01225   WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
01226 }
01227
01228 /**
01229   * @brief  Clear Wake-up Flags
01230   * @rmtoll SCR          CWUF          LL_PWR_ClearFlag_WU
01231   * @retval None
01232   */
01233 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
01234 {
01235   WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
01236 }
01237
01238 /**
01239   * @brief  Clear Wake-up Flag 5
01240   * @rmtoll SCR          CWUF5         LL_PWR_ClearFlag_WU5
01241   * @retval None
01242   */
01243 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
01244 {
01245   WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
01246 }
01247
01248 /**
01249   * @brief  Clear Wake-up Flag 4
01250   * @rmtoll SCR          CWUF4         LL_PWR_ClearFlag_WU4
01251   * @retval None
01252   */
01253 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
01254 {
01255   WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
01256 }
01257
01258 /**
01259   * @brief  Clear Wake-up Flag 3
01260   * @rmtoll SCR          CWUF3         LL_PWR_ClearFlag_WU3
01261   * @retval None
01262   */
01263 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
01264 {
01265   WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
01266 }
01267
01268 /**
01269   * @brief  Clear Wake-up Flag 2
01270   * @rmtoll SCR          CWUF2         LL_PWR_ClearFlag_WU2
01271   * @retval None
01272   */
01273 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
01274 {
01275   WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
01276 }
01277
01278 /**
01279   * @brief  Clear Wake-up Flag 1
01280   * @rmtoll SCR          CWUF1         LL_PWR_ClearFlag_WU1
01281   * @retval None
01282   */
01283 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
01284 {
01285   WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
01286 }
01287
01288 /**
01289   * @brief  Indicate whether VDDA voltage is below or above PVM4 threshold
01290   * @rmtoll SR2          PVMO4         LL_PWR_IsActiveFlag_PVMO4
01291   * @retval State of bit (1 or 0).
01292   */
01293 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
01294 {
01295   return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4));
01296 }
01297
01298 /**
01299   * @brief  Indicate whether VDDA voltage is below or above PVM3 threshold
01300   * @rmtoll SR2          PVMO3         LL_PWR_IsActiveFlag_PVMO3
01301   * @retval State of bit (1 or 0).
01302   */
01303 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
01304 {
01305   return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3));
01306 }
01307
01308 #if defined(PWR_SR2_PVMO2)
01309 /**
01310   * @brief  Indicate whether VDDIO2 voltage is below or above PVM2 threshold
01311   * @rmtoll SR2          PVMO2         LL_PWR_IsActiveFlag_PVMO2
01312   * @retval State of bit (1 or 0).
01313   */
01314 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
01315 {
01316   return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2));
01317 }
01318 #endif /* PWR_SR2_PVMO2 */
01319
01320 #if defined(USB_OTG_FS)
01321 /**
01322   * @brief  Indicate whether VDDUSB voltage is below or above PVM1 threshold
01323   * @rmtoll SR2          PVMO1         LL_PWR_IsActiveFlag_PVMO1
01324   * @retval State of bit (1 or 0).
01325   */
01326 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
01327 {
01328   return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1));
01329 }
01330 #endif /* USB_OTG_FS */
01331
01332 /**
01333   * @brief  Indicate whether VDD voltage is below or above the selected PVD threshold
01334   * @rmtoll SR2          PVDO          LL_PWR_IsActiveFlag_PVDO
01335   * @retval State of bit (1 or 0).
01336   */
01337 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
01338 {
01339   return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO));
01340 }
01341
01342 /**
01343   * @brief  Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
01344   * @rmtoll SR2          VOSF          LL_PWR_IsActiveFlag_VOSF
01345   * @retval State of bit (1 or 0).
01346   */
01347 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF(void)
01348 {
01349   return (READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF));
01350 }
01351
01352 /**
01353   * @brief  Indicate whether the regulator is ready in main mode or is in low-power mode
01354   * @note: Take care, return value "0" means the regulator is ready.  Return value "1" means the output voltage range is still changing.
01355   * @rmtoll SR2          REGLPF        LL_PWR_IsActiveFlag_REGLPF
01356   * @retval State of bit (1 or 0).
01357   */
01358 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
01359 {
01360   return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF));
01361 }
01362
01363 /**
01364   * @brief  Indicate whether or not the low-power regulator is ready
01365   * @rmtoll SR2          REGLPS        LL_PWR_IsActiveFlag_REGLPS
01366   * @retval State of bit (1 or 0).
01367   */
01368 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
01369 {
01370   return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS));
01371 }
01372
01373 #if defined(USE_FULL_LL_DRIVER)
01374 /** @defgroup PWR_LL_EF_Init De-initialization function
01375   * @{
01376   */
01377 ErrorStatus LL_PWR_DeInit(void);
01378 /**
01379   * @}
01380   */
01381 #endif /* USE_FULL_LL_DRIVER */
01382
01383 /**
01384   * @}
01385   */
01386
01387
01388 /**
01389   * @}
01390   */
01391
01392 /**
01393   * @}
01394   */
01395
01396 #endif /* defined(PWR) */
01397
01398 /**
01399   * @}
01400   */
01401
01402 #ifdef __cplusplus
01403 }
01404 #endif
01405
01406 #endif /* __STM32L4xx_LL_PWR_H */
01407
01408 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rcc.c Source File

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stm32l4xx_ll_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_rcc.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   RCC LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_rcc.h"
00041 #ifdef  USE_FULL_ASSERT
00042   #include "stm32_assert.h"
00043 #else
00044   #define assert_param(expr) ((void)0U)
00045 #endif
00046 /** @addtogroup STM32L4xx_LL_Driver
00047   * @{
00048   */
00049
00050 #if defined(RCC)
00051
00052 /** @addtogroup RCC_LL
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private constants ---------------------------------------------------------*/
00059 /* Private macros ------------------------------------------------------------*/
00060 /** @addtogroup RCC_LL_Private_Macros
00061   * @{
00062   */
00063 #if defined(RCC_CCIPR_USART3SEL)
00064 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
00065                                             || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
00066                                             || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
00067 #else
00068 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
00069                                             || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
00070
00071 #endif /* RCC_CCIPR_USART3SEL */
00072 #if defined(RCC_CCIPR_UART4SEL) && defined(RCC_CCIPR_UART5SEL)
00073 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
00074                                              || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
00075 #elif defined(RCC_CCIPR_UART4SEL)
00076 #define IS_LL_RCC_UART_INSTANCE(__VALUE__)     ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
00077 #elif defined(RCC_CCIPR_UART5SEL)
00078 #define IS_LL_RCC_UART_INSTANCE(__VALUE__)     ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
00079 #endif /* RCC_CCIPR_UART4SEL && RCC_CCIPR_UART5SEL*/
00080
00081 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
00082
00083 #if defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL)
00084 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
00085                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
00086                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
00087
00088 #elif !defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL)
00089 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
00090                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
00091
00092 #else
00093 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)     ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
00094
00095 #endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL */
00096 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
00097                                             || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
00098
00099 #if defined(RCC_CCIPR_SAI2SEL)
00100 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
00101                                             || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
00102 #else
00103 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
00104 #endif /* RCC_CCIPR_SAI2SEL */
00105
00106 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
00107
00108 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
00109
00110 #if defined(USB_OTG_FS) || defined(USB)
00111 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
00112 #endif /* USB_OTG_FS || USB */
00113
00114 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
00115
00116 #define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))
00117
00118 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
00119
00120 /**
00121   * @}
00122   */
00123
00124 /* Private function prototypes -----------------------------------------------*/
00125 /** @defgroup RCC_LL_Private_Functions RCC Private functions
00126   * @{
00127   */
00128 uint32_t RCC_GetSystemClockFreq(void);
00129 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
00130 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
00131 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
00132 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
00133 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
00134 uint32_t RCC_PLL_GetFreqDomain_48M(void);
00135 uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
00136 uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
00137 uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
00138 #if defined(RCC_PLLSAI2_SUPPORT)
00139 uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);
00140 uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void);
00141 #endif /*RCC_PLLSAI2_SUPPORT*/
00142 /**
00143   * @}
00144   */
00145
00146
00147 /* Exported functions --------------------------------------------------------*/
00148 /** @addtogroup RCC_LL_Exported_Functions
00149   * @{
00150   */
00151
00152 /** @addtogroup RCC_LL_EF_Init
00153   * @{
00154   */
00155
00156 /**
00157   * @brief  Reset the RCC clock configuration to the default reset state.
00158   * @note   The default reset state of the clock configuration is given below:
00159   *         - MSI  ON and used as system clock source
00160   *         - HSE, HSI, PLL and PLLSAIxSource OFF
00161   *         - AHB, APB1 and APB2 prescaler set to 1.
00162   *         - CSS, MCO OFF
00163   *         - All interrupts disabled
00164   * @note   This function doesn't modify the configuration of the
00165   *         - Peripheral clocks
00166   *         - LSI, LSE and RTC clocks
00167   * @retval An ErrorStatus enumeration value:
00168   *          - SUCCESS: RCC registers are de-initialized
00169   *          - ERROR: not applicable
00170   */
00171 ErrorStatus LL_RCC_DeInit(void)
00172 {
00173   uint32_t vl_mask = 0;
00174
00175   /* Set MSION bit */
00176   LL_RCC_MSI_Enable();
00177
00178   /* Insure MSIRDY bit is set before writing default MSIRANGE value */
00179   while (LL_RCC_MSI_IsReady() == 0)
00180   {
00181     __NOP();
00182   }
00183
00184   /* Set MSIRANGE default value */
00185   LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
00186   /* Set MSITRIM bits to the reset value*/
00187   LL_RCC_MSI_SetCalibTrimming(0);
00188
00189   /* Set HSITRIM bits to the reset value*/
00190   LL_RCC_HSI_SetCalibTrimming(0x10);
00191
00192   /* Reset CFGR register */
00193   LL_RCC_WriteReg(CFGR, 0x00000000);
00194
00195   vl_mask = 0xFFFFFFFFU;
00196
00197   /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */
00198   CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON  | RCC_CR_HSEON |
00199   RCC_CR_PLLON));
00200
00201   /* Reset PLLSAI1ON bit */
00202   CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON);
00203
00204 #if defined(RCC_PLLSAI2_SUPPORT)
00205   /* Reset PLLSAI2ON bit */
00206   CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON);
00207 #endif /*RCC_PLLSAI2_SUPPORT*/
00208
00209   /* Write new mask in CR register */
00210   LL_RCC_WriteReg(CR, vl_mask);
00211
00212   /* Reset PLLCFGR register */
00213   LL_RCC_WriteReg(PLLCFGR, 16 << RCC_POSITION_PLLN);
00214
00215   /* Reset PLLSAI1CFGR register */
00216   LL_RCC_WriteReg(PLLSAI1CFGR, 16 << RCC_POSITION_PLLSAI1N);
00217
00218 #if defined(RCC_PLLSAI2_SUPPORT)
00219   /* Reset PLLSAI2CFGR register */
00220   LL_RCC_WriteReg(PLLSAI2CFGR, 16 << RCC_POSITION_PLLSAI2N);
00221 #endif /*RCC_PLLSAI2_SUPPORT*/
00222
00223   /* Reset HSEBYP bit */
00224   LL_RCC_HSE_DisableBypass();
00225
00226   /* Disable all interrupts */
00227   LL_RCC_WriteReg(CIER, 0x00000000);
00228
00229   return SUCCESS;
00230 }
00231
00232 /**
00233   * @}
00234   */
00235
00236 /** @addtogroup RCC_LL_EF_Get_Freq
00237   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
00238   *         and different peripheral clocks available on the device.
00239   * @note   If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
00240   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
00241   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
00242   * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
00243   *         or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
00244   * @note   (*) MSI_VALUE is a constant defined in this file (default value
00245   *             4 MHz) but the real value may vary depending on the variations
00246   *             in voltage and temperature.
00247   * @note   (**) HSI_VALUE is a constant defined in this file (default value
00248   *              16 MHz) but the real value may vary depending on the variations
00249   *              in voltage and temperature.
00250   * @note   (***) HSE_VALUE is a constant defined in this file (default value
00251   *               8 MHz), user has to ensure that HSE_VALUE is same as the real
00252   *               frequency of the crystal used. Otherwise, this function may
00253   *               have wrong result.
00254   * @note   The result of this function could be incorrect when using fractional
00255   *         value for HSE crystal.
00256   * @note   This function can be used by the user application to compute the
00257   *         baud-rate for the communication peripherals or configure other parameters.
00258   * @{
00259   */
00260
00261 /**
00262   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
00263   * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
00264   *         must be called to update structure fields. Otherwise, any
00265   *         configuration based on this function will be incorrect.
00266   * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
00267   * @retval None
00268   */
00269 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
00270 {
00271   /* Get SYSCLK frequency */
00272   RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
00273
00274   /* HCLK clock frequency */
00275   RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
00276
00277   /* PCLK1 clock frequency */
00278   RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
00279
00280   /* PCLK2 clock frequency */
00281   RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
00282 }
00283
00284 /**
00285   * @brief  Return USARTx clock frequency
00286   * @param  USARTxSource This parameter can be one of the following values:
00287   *         @arg @ref LL_RCC_USART1_CLKSOURCE
00288   *         @arg @ref LL_RCC_USART2_CLKSOURCE
00289   *         @arg @ref LL_RCC_USART3_CLKSOURCE (*)
00290   *
00291   *         (*) value not defined in all devices.
00292   * @retval USART clock frequency (in Hz)
00293   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00294   */
00295 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
00296 {
00297   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00298
00299   /* Check parameter */
00300   assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
00301
00302   if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
00303   {
00304     /* USART1CLK clock frequency */
00305     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00306     {
00307       case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
00308         usart_frequency = RCC_GetSystemClockFreq();
00309         break;
00310
00311       case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
00312         if (LL_RCC_HSI_IsReady())
00313         {
00314           usart_frequency = HSI_VALUE;
00315         }
00316         break;
00317
00318       case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
00319         if (LL_RCC_LSE_IsReady())
00320         {
00321           usart_frequency = LSE_VALUE;
00322         }
00323         break;
00324
00325       case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */
00326       default:
00327         usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00328         break;
00329     }
00330   }
00331   else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
00332   {
00333     /* USART2CLK clock frequency */
00334     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00335     {
00336       case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
00337         usart_frequency = RCC_GetSystemClockFreq();
00338         break;
00339
00340       case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
00341         if (LL_RCC_HSI_IsReady())
00342         {
00343           usart_frequency = HSI_VALUE;
00344         }
00345         break;
00346
00347       case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
00348         if (LL_RCC_LSE_IsReady())
00349         {
00350           usart_frequency = LSE_VALUE;
00351         }
00352         break;
00353
00354       case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
00355       default:
00356         usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00357         break;
00358     }
00359   }
00360   else
00361   {
00362 #if defined(RCC_CCIPR_USART3SEL)
00363     if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
00364     {
00365       /* USART3CLK clock frequency */
00366       switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00367       {
00368         case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
00369           usart_frequency = RCC_GetSystemClockFreq();
00370           break;
00371
00372         case LL_RCC_USART3_CLKSOURCE_HSI:    /* USART3 Clock is HSI Osc. */
00373           if (LL_RCC_HSI_IsReady())
00374           {
00375             usart_frequency = HSI_VALUE;
00376           }
00377           break;
00378
00379         case LL_RCC_USART3_CLKSOURCE_LSE:    /* USART3 Clock is LSE Osc. */
00380           if (LL_RCC_LSE_IsReady())
00381           {
00382             usart_frequency = LSE_VALUE;
00383           }
00384           break;
00385
00386         case LL_RCC_USART3_CLKSOURCE_PCLK1:  /* USART3 Clock is PCLK1 */
00387         default:
00388           usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00389           break;
00390       }
00391     }
00392 #endif /* RCC_CCIPR_USART3SEL */
00393   }
00394   return usart_frequency;
00395 }
00396
00397 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
00398 /**
00399   * @brief  Return UARTx clock frequency
00400   * @param  UARTxSource This parameter can be one of the following values:
00401   *         @arg @ref LL_RCC_UART4_CLKSOURCE
00402   *         @arg @ref LL_RCC_UART5_CLKSOURCE
00403   * @retval UART clock frequency (in Hz)
00404   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00405   */
00406 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
00407 {
00408   uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00409
00410   /* Check parameter */
00411   assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
00412
00413 #if defined(RCC_CCIPR_UART4SEL)
00414   if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
00415   {
00416     /* UART4CLK clock frequency */
00417     switch (LL_RCC_GetUARTClockSource(UARTxSource))
00418     {
00419       case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
00420         uart_frequency = RCC_GetSystemClockFreq();
00421         break;
00422
00423       case LL_RCC_UART4_CLKSOURCE_HSI:    /* UART4 Clock is HSI Osc. */
00424         if (LL_RCC_HSI_IsReady())
00425         {
00426           uart_frequency = HSI_VALUE;
00427         }
00428         break;
00429
00430       case LL_RCC_UART4_CLKSOURCE_LSE:    /* UART4 Clock is LSE Osc. */
00431         if (LL_RCC_LSE_IsReady())
00432         {
00433           uart_frequency = LSE_VALUE;
00434         }
00435         break;
00436
00437       case LL_RCC_UART4_CLKSOURCE_PCLK1:  /* UART4 Clock is PCLK1 */
00438       default:
00439         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00440         break;
00441     }
00442   }
00443 #endif /* RCC_CCIPR_UART4SEL */
00444
00445 #if defined(RCC_CCIPR_UART5SEL)
00446   if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
00447   {
00448     /* UART5CLK clock frequency */
00449     switch (LL_RCC_GetUARTClockSource(UARTxSource))
00450     {
00451       case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
00452         uart_frequency = RCC_GetSystemClockFreq();
00453         break;
00454
00455       case LL_RCC_UART5_CLKSOURCE_HSI:    /* UART5 Clock is HSI Osc. */
00456         if (LL_RCC_HSI_IsReady())
00457         {
00458           uart_frequency = HSI_VALUE;
00459         }
00460         break;
00461
00462       case LL_RCC_UART5_CLKSOURCE_LSE:    /* UART5 Clock is LSE Osc. */
00463         if (LL_RCC_LSE_IsReady())
00464         {
00465           uart_frequency = LSE_VALUE;
00466         }
00467         break;
00468
00469       case LL_RCC_UART5_CLKSOURCE_PCLK1:  /* UART5 Clock is PCLK1 */
00470       default:
00471         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00472         break;
00473     }
00474   }
00475 #endif /* RCC_CCIPR_UART5SEL */
00476
00477   return uart_frequency;
00478 }
00479 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
00480
00481 /**
00482   * @brief  Return I2Cx clock frequency
00483   * @param  I2CxSource This parameter can be one of the following values:
00484   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
00485   *         @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
00486   *
00487   *         (*) value not defined in all devices.
00488   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
00489   * @retval I2C clock frequency (in Hz)
00490   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
00491   */
00492 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
00493 {
00494   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00495
00496   /* Check parameter */
00497   assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
00498
00499   if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
00500   {
00501     /* I2C1 CLK clock frequency */
00502     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00503     {
00504       case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
00505         i2c_frequency = RCC_GetSystemClockFreq();
00506         break;
00507
00508       case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
00509         if (LL_RCC_HSI_IsReady())
00510         {
00511           i2c_frequency = HSI_VALUE;
00512         }
00513         break;
00514
00515       case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
00516       default:
00517         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00518         break;
00519     }
00520   }
00521 #if defined(RCC_CCIPR_I2C2SEL)
00522   else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
00523   {
00524     /* I2C2 CLK clock frequency */
00525     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00526     {
00527       case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
00528         i2c_frequency = RCC_GetSystemClockFreq();
00529         break;
00530
00531       case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */
00532         if (LL_RCC_HSI_IsReady())
00533         {
00534           i2c_frequency = HSI_VALUE;
00535         }
00536         break;
00537
00538       case LL_RCC_I2C2_CLKSOURCE_PCLK1:  /* I2C2 Clock is PCLK1 */
00539       default:
00540         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00541         break;
00542     }
00543   }
00544 #endif /*RCC_CCIPR_I2C2SEL*/
00545   else
00546   {
00547     if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
00548     {
00549       /* I2C3 CLK clock frequency */
00550       switch (LL_RCC_GetI2CClockSource(I2CxSource))
00551       {
00552         case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
00553           i2c_frequency = RCC_GetSystemClockFreq();
00554           break;
00555
00556         case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */
00557           if (LL_RCC_HSI_IsReady())
00558           {
00559             i2c_frequency = HSI_VALUE;
00560           }
00561           break;
00562
00563         case LL_RCC_I2C3_CLKSOURCE_PCLK1:  /* I2C3 Clock is PCLK1 */
00564         default:
00565           i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00566           break;
00567       }
00568     }
00569   }
00570
00571   return i2c_frequency;
00572 }
00573
00574 /**
00575   * @brief  Return LPUARTx clock frequency
00576   * @param  LPUARTxSource This parameter can be one of the following values:
00577   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
00578   * @retval LPUART clock frequency (in Hz)
00579   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00580   */
00581 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
00582 {
00583   uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00584
00585   /* Check parameter */
00586   assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
00587
00588   /* LPUART1CLK clock frequency */
00589   switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
00590   {
00591     case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
00592       lpuart_frequency = RCC_GetSystemClockFreq();
00593       break;
00594
00595     case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */
00596       if (LL_RCC_HSI_IsReady())
00597       {
00598         lpuart_frequency = HSI_VALUE;
00599       }
00600       break;
00601
00602     case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */
00603       if (LL_RCC_LSE_IsReady())
00604       {
00605         lpuart_frequency = LSE_VALUE;
00606       }
00607       break;
00608
00609     case LL_RCC_LPUART1_CLKSOURCE_PCLK1:  /* LPUART1 Clock is PCLK1 */
00610     default:
00611       lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00612       break;
00613   }
00614
00615   return lpuart_frequency;
00616 }
00617
00618 /**
00619   * @brief  Return LPTIMx clock frequency
00620   * @param  LPTIMxSource This parameter can be one of the following values:
00621   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
00622   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
00623   * @retval LPTIM clock frequency (in Hz)
00624   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00625   */
00626 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
00627 {
00628   uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00629
00630   /* Check parameter */
00631   assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
00632
00633   if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
00634   {
00635     /* LPTIM1CLK clock frequency */
00636     switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
00637     {
00638       case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
00639         if (LL_RCC_LSI_IsReady())
00640         {
00641           lptim_frequency = LSI_VALUE;
00642         }
00643         break;
00644
00645       case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
00646         if (LL_RCC_HSI_IsReady())
00647         {
00648           lptim_frequency = HSI_VALUE;
00649         }
00650         break;
00651
00652       case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
00653         if (LL_RCC_LSE_IsReady())
00654         {
00655           lptim_frequency = LSE_VALUE;
00656         }
00657         break;
00658
00659       case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
00660       default:
00661         lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00662         break;
00663     }
00664   }
00665   else
00666   {
00667     if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
00668     {
00669       /* LPTIM2CLK clock frequency */
00670       switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
00671       {
00672         case LL_RCC_LPTIM2_CLKSOURCE_LSI:    /* LPTIM2 Clock is LSI Osc. */
00673           if (LL_RCC_LSI_IsReady())
00674           {
00675             lptim_frequency = LSI_VALUE;
00676           }
00677           break;
00678
00679         case LL_RCC_LPTIM2_CLKSOURCE_HSI:    /* LPTIM2 Clock is HSI Osc. */
00680           if (LL_RCC_HSI_IsReady())
00681           {
00682             lptim_frequency = HSI_VALUE;
00683           }
00684           break;
00685
00686         case LL_RCC_LPTIM2_CLKSOURCE_LSE:    /* LPTIM2 Clock is LSE Osc. */
00687           if (LL_RCC_LSE_IsReady())
00688           {
00689             lptim_frequency = LSE_VALUE;
00690           }
00691           break;
00692
00693         case LL_RCC_LPTIM2_CLKSOURCE_PCLK1:  /* LPTIM2 Clock is PCLK1 */
00694         default:
00695           lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
00696           break;
00697       }
00698     }
00699   }
00700
00701   return lptim_frequency;
00702 }
00703
00704 /**
00705   * @brief  Return SAIx clock frequency
00706   * @param  SAIxSource This parameter can be one of the following values:
00707   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
00708   *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
00709   *
00710   *         (*) value not defined in all devices.
00711   * @retval SAI clock frequency (in Hz)
00712   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
00713   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
00714   */
00715 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
00716 {
00717   uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00718
00719   /* Check parameter */
00720   assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
00721
00722   if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
00723   {
00724     /* SAI1CLK clock frequency */
00725     switch (LL_RCC_GetSAIClockSource(SAIxSource))
00726     {
00727       case LL_RCC_SAI1_CLKSOURCE_PLLSAI1:    /* PLLSAI1 clock used as SAI1 clock source */
00728         if (LL_RCC_PLLSAI1_IsReady())
00729         {
00730           sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
00731         }
00732         break;
00733
00734 #if defined(RCC_PLLSAI2_SUPPORT)
00735       case LL_RCC_SAI1_CLKSOURCE_PLLSAI2:    /* PLLSAI2 clock used as SAI1 clock source */
00736         if (LL_RCC_PLLSAI2_IsReady())
00737         {
00738           sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
00739         }
00740         break;
00741
00742 #endif /* RCC_PLLSAI2_SUPPORT */
00743       case LL_RCC_SAI1_CLKSOURCE_PLL:        /* PLL clock used as SAI1 clock source */
00744         if (LL_RCC_PLL_IsReady())
00745         {
00746           sai_frequency = RCC_PLL_GetFreqDomain_SAI();
00747         }
00748         break;
00749
00750       case LL_RCC_SAI1_CLKSOURCE_PIN:        /* External input clock used as SAI1 clock source */
00751       default:
00752         sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00753         break;
00754     }
00755   }
00756   else
00757   {
00758 #if defined(RCC_CCIPR_SAI2SEL)
00759     if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
00760     {
00761       /* SAI2CLK clock frequency */
00762       switch (LL_RCC_GetSAIClockSource(SAIxSource))
00763       {
00764         case LL_RCC_SAI2_CLKSOURCE_PLLSAI1:  /* PLLSAI1 clock used as SAI2 clock source */
00765           if (LL_RCC_PLLSAI1_IsReady())
00766           {
00767             sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
00768           }
00769           break;
00770
00771   #if defined(RCC_PLLSAI2_SUPPORT)
00772         case LL_RCC_SAI2_CLKSOURCE_PLLSAI2:  /* PLLSAI2 clock used as SAI2 clock source */
00773           if (LL_RCC_PLLSAI2_IsReady())
00774           {
00775             sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
00776           }
00777           break;
00778
00779   #endif /* RCC_PLLSAI2_SUPPORT */
00780         case LL_RCC_SAI2_CLKSOURCE_PLL:      /* PLL clock used as SAI2 clock source */
00781           if (LL_RCC_PLL_IsReady())
00782           {
00783             sai_frequency = RCC_PLL_GetFreqDomain_SAI();
00784           }
00785           break;
00786
00787         case LL_RCC_SAI2_CLKSOURCE_PIN:      /* External input clock used as SAI2 clock source */
00788         default:
00789           sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00790           break;
00791       }
00792     }
00793 #endif /*RCC_CCIPR_SAI2SEL*/
00794   }
00795
00796   return sai_frequency;
00797 }
00798
00799 /**
00800   * @brief  Return SDMMCx clock frequency
00801   * @param  SDMMCxSource This parameter can be one of the following values:
00802   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
00803   * @retval SDMMC clock frequency (in Hz)
00804   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
00805   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00806   */
00807 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
00808 {
00809   uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00810
00811   /* Check parameter */
00812   assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
00813
00814   /* SDMMC1CLK clock frequency */
00815   switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
00816   {
00817     case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1:    /* PLLSAI1 clock used as SDMMC1 clock source */
00818       if (LL_RCC_PLLSAI1_IsReady())
00819       {
00820         sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
00821       }
00822       break;
00823
00824     case LL_RCC_SDMMC1_CLKSOURCE_PLL:        /* PLL clock used as SDMMC1 clock source */
00825       if (LL_RCC_PLL_IsReady())
00826       {
00827         sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
00828       }
00829       break;
00830
00831     case LL_RCC_SDMMC1_CLKSOURCE_MSI:        /* MSI clock used as SDMMC1 clock source */
00832       if (LL_RCC_MSI_IsReady())
00833       {
00834         sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
00835                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
00836                                      LL_RCC_MSI_GetRange() :
00837                                      LL_RCC_MSI_GetRangeAfterStandby()));
00838       }
00839       break;
00840
00841     case LL_RCC_SDMMC1_CLKSOURCE_NONE:       /* No clock used as SDMMC1 clock source */
00842     default:
00843       sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00844       break;
00845   }
00846
00847   return sdmmc_frequency;
00848 }
00849
00850 /**
00851   * @brief  Return RNGx clock frequency
00852   * @param  RNGxSource This parameter can be one of the following values:
00853   *         @arg @ref LL_RCC_RNG_CLKSOURCE
00854   * @retval RNG clock frequency (in Hz)
00855   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
00856   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00857   */
00858 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
00859 {
00860   uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00861
00862   /* Check parameter */
00863   assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
00864
00865   /* RNGCLK clock frequency */
00866   switch (LL_RCC_GetRNGClockSource(RNGxSource))
00867   {
00868     case LL_RCC_RNG_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as RNG clock source */
00869       if (LL_RCC_PLLSAI1_IsReady())
00870       {
00871         rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
00872       }
00873       break;
00874
00875     case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */
00876       if (LL_RCC_PLL_IsReady())
00877       {
00878         rng_frequency = RCC_PLL_GetFreqDomain_48M();
00879       }
00880       break;
00881
00882     case LL_RCC_RNG_CLKSOURCE_MSI:           /* MSI clock used as RNG clock source */
00883       if (LL_RCC_MSI_IsReady())
00884       {
00885         rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
00886                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
00887                                      LL_RCC_MSI_GetRange() :
00888                                      LL_RCC_MSI_GetRangeAfterStandby()));
00889       }
00890       break;
00891
00892     case LL_RCC_RNG_CLKSOURCE_NONE:          /* No clock used as RNG clock source */
00893     default:
00894       rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00895       break;
00896   }
00897
00898   return rng_frequency;
00899 }
00900
00901 #if defined(USB_OTG_FS) || defined(USB)
00902 /**
00903   * @brief  Return USBx clock frequency
00904   * @param  USBxSource This parameter can be one of the following values:
00905   *         @arg @ref LL_RCC_USB_CLKSOURCE
00906   * @retval USB clock frequency (in Hz)
00907   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
00908   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00909   */
00910 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
00911 {
00912   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00913
00914   /* Check parameter */
00915   assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
00916
00917   /* USBCLK clock frequency */
00918   switch (LL_RCC_GetUSBClockSource(USBxSource))
00919   {
00920     case LL_RCC_USB_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as USB clock source */
00921       if (LL_RCC_PLLSAI1_IsReady())
00922       {
00923         usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
00924       }
00925       break;
00926
00927     case LL_RCC_USB_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
00928       if (LL_RCC_PLL_IsReady())
00929       {
00930         usb_frequency = RCC_PLL_GetFreqDomain_48M();
00931       }
00932       break;
00933
00934     case LL_RCC_USB_CLKSOURCE_MSI:           /* MSI clock used as USB clock source */
00935       if (LL_RCC_MSI_IsReady())
00936       {
00937         usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
00938                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
00939                                      LL_RCC_MSI_GetRange() :
00940                                      LL_RCC_MSI_GetRangeAfterStandby()));
00941       }
00942       break;
00943
00944     case LL_RCC_USB_CLKSOURCE_NONE:          /* No clock used as USB clock source */
00945     default:
00946       usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00947       break;
00948   }
00949
00950   return usb_frequency;
00951 }
00952 #endif /* USB_OTG_FS || USB */
00953
00954 /**
00955   * @brief  Return ADCx clock frequency
00956   * @param  ADCxSource This parameter can be one of the following values:
00957   *         @arg @ref LL_RCC_ADC_CLKSOURCE
00958   * @retval ADC clock frequency (in Hz)
00959   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
00960   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00961   */
00962 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
00963 {
00964   uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00965
00966   /* Check parameter */
00967   assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
00968
00969   /* ADCCLK clock frequency */
00970   switch (LL_RCC_GetADCClockSource(ADCxSource))
00971   {
00972     case LL_RCC_ADC_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as ADC clock source */
00973       if (LL_RCC_PLLSAI1_IsReady())
00974       {
00975         adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
00976       }
00977       break;
00978
00979 #if defined(RCC_PLLSAI2_SUPPORT)
00980     case LL_RCC_ADC_CLKSOURCE_PLLSAI2:       /* PLLSAI2 clock used as ADC clock source */
00981       if (LL_RCC_PLLSAI2_IsReady())
00982       {
00983          adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC();
00984       }
00985       break;
00986 #endif /* RCC_PLLSAI2_SUPPORT */
00987
00988     case LL_RCC_ADC_CLKSOURCE_SYSCLK:        /* SYSCLK clock used as ADC clock source */
00989       adc_frequency = RCC_GetSystemClockFreq();
00990       break;
00991     case LL_RCC_ADC_CLKSOURCE_NONE:          /* No clock used as ADC clock source */
00992     default:
00993       adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00994       break;
00995   }
00996
00997   return adc_frequency;
00998 }
00999
01000 /**
01001   * @brief  Return SWPMIx clock frequency
01002   * @param  SWPMIxSource This parameter can be one of the following values:
01003   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE
01004   * @retval SWPMI clock frequency (in Hz)
01005   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready
01006   */
01007 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)
01008 {
01009   uint32_t swpmi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01010
01011   /* Check parameter */
01012   assert_param(IS_LL_RCC_SWPMI_CLKSOURCE(SWPMIxSource));
01013
01014   /* SWPMI1CLK clock frequency */
01015   switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource))
01016   {
01017     case LL_RCC_SWPMI1_CLKSOURCE_HSI:        /* SWPMI1 Clock is HSI Osc. */
01018       if (LL_RCC_HSI_IsReady())
01019       {
01020         swpmi_frequency = HSI_VALUE;
01021       }
01022       break;
01023
01024     case LL_RCC_SWPMI1_CLKSOURCE_PCLK:       /* SWPMI1 Clock is PCLK1 */
01025     default:
01026       swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
01027       break;
01028   }
01029
01030   return swpmi_frequency;
01031 }
01032
01033 #if defined(DFSDM1_Channel0)
01034 /**
01035   * @brief  Return DFSDMx clock frequency
01036   * @param  DFSDMxSource This parameter can be one of the following values:
01037   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
01038   * @retval DFSDM clock frequency (in Hz)
01039   */
01040 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
01041 {
01042   uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
01043
01044   /* Check parameter */
01045   assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
01046
01047   /* DFSDM1CLK clock frequency */
01048   switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
01049   {
01050     case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:     /* DFSDM1 Clock is SYSCLK */
01051       dfsdm_frequency = RCC_GetSystemClockFreq();
01052       break;
01053
01054     case LL_RCC_DFSDM1_CLKSOURCE_PCLK:       /* DFSDM1 Clock is PCLK1 */
01055     default:
01056       dfsdm_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
01057       break;
01058   }
01059
01060   return dfsdm_frequency;
01061 }
01062 #endif /* DFSDM1_Channel0 */
01063
01064 /**
01065   * @}
01066   */
01067
01068 /**
01069   * @}
01070   */
01071
01072 /** @addtogroup RCC_LL_Private_Functions
01073   * @{
01074   */
01075
01076 /**
01077   * @brief  Return SYSTEM clock frequency
01078   * @retval SYSTEM clock frequency (in Hz)
01079   */
01080 uint32_t RCC_GetSystemClockFreq(void)
01081 {
01082   uint32_t frequency = 0;
01083
01084   /* Get SYSCLK source -------------------------------------------------------*/
01085   switch (LL_RCC_GetSysClkSource())
01086   {
01087     case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
01088       frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01089                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01090                                      LL_RCC_MSI_GetRange() :
01091                                      LL_RCC_MSI_GetRangeAfterStandby()));
01092       break;
01093
01094     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
01095       frequency = HSI_VALUE;
01096       break;
01097
01098     case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
01099       frequency = HSE_VALUE;
01100       break;
01101
01102     case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
01103       frequency = RCC_PLL_GetFreqDomain_SYS();
01104       break;
01105
01106     default:
01107       frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01108                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01109                                      LL_RCC_MSI_GetRange() :
01110                                      LL_RCC_MSI_GetRangeAfterStandby()));
01111       break;
01112   }
01113
01114   return frequency;
01115 }
01116
01117 /**
01118   * @brief  Return HCLK clock frequency
01119   * @param  SYSCLK_Frequency SYSCLK clock frequency
01120   * @retval HCLK clock frequency (in Hz)
01121   */
01122 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
01123 {
01124   /* HCLK clock frequency */
01125   return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
01126 }
01127
01128 /**
01129   * @brief  Return PCLK1 clock frequency
01130   * @param  HCLK_Frequency HCLK clock frequency
01131   * @retval PCLK1 clock frequency (in Hz)
01132   */
01133 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
01134 {
01135   /* PCLK1 clock frequency */
01136   return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
01137 }
01138
01139 /**
01140   * @brief  Return PCLK2 clock frequency
01141   * @param  HCLK_Frequency HCLK clock frequency
01142   * @retval PCLK2 clock frequency (in Hz)
01143   */
01144 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
01145 {
01146   /* PCLK2 clock frequency */
01147   return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
01148 }
01149
01150 /**
01151   * @brief  Return PLL clock frequency used for system domain
01152   * @retval PLL clock frequency (in Hz)
01153   */
01154 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
01155 {
01156   uint32_t pllinputfreq = 0, pllsource = 0;
01157
01158   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
01159      SYSCLK = PLL_VCO / PLLR
01160   */
01161   pllsource = LL_RCC_PLL_GetMainSource();
01162
01163   switch (pllsource)
01164   {
01165     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
01166       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01167                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01168                                      LL_RCC_MSI_GetRange() :
01169                                      LL_RCC_MSI_GetRangeAfterStandby()));
01170       break;
01171
01172     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01173       pllinputfreq = HSI_VALUE;
01174       break;
01175
01176     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01177       pllinputfreq = HSE_VALUE;
01178       break;
01179
01180     default:
01181       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01182                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01183                                      LL_RCC_MSI_GetRange() :
01184                                      LL_RCC_MSI_GetRangeAfterStandby()));
01185       break;
01186   }
01187   return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01188                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
01189 }
01190 /**
01191   * @brief  Return PLL clock frequency used for SAI domain
01192   * @retval PLL clock frequency (in Hz)
01193   */
01194 uint32_t RCC_PLL_GetFreqDomain_SAI(void)
01195 {
01196   uint32_t pllinputfreq = 0, pllsource = 0;
01197
01198   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
01199      SAI Domain clock = PLL_VCO / PLLP
01200   */
01201   pllsource = LL_RCC_PLL_GetMainSource();
01202
01203   switch (pllsource)
01204   {
01205     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
01206       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01207                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01208                                      LL_RCC_MSI_GetRange() :
01209                                      LL_RCC_MSI_GetRangeAfterStandby()));
01210       break;
01211
01212     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01213       pllinputfreq = HSI_VALUE;
01214       break;
01215
01216     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01217       pllinputfreq = HSE_VALUE;
01218       break;
01219
01220     default:
01221       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01222                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01223                                      LL_RCC_MSI_GetRange() :
01224                                      LL_RCC_MSI_GetRangeAfterStandby()));
01225       break;
01226   }
01227   return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01228                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
01229 }
01230
01231 /**
01232   * @brief  Return PLL clock frequency used for 48 MHz domain
01233   * @retval PLL clock frequency (in Hz)
01234   */
01235 uint32_t RCC_PLL_GetFreqDomain_48M(void)
01236 {
01237   uint32_t pllinputfreq = 0, pllsource = 0;
01238
01239   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
01240      48M Domain clock = PLL_VCO / PLLQ
01241   */
01242   pllsource = LL_RCC_PLL_GetMainSource();
01243
01244   switch (pllsource)
01245   {
01246     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
01247       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01248                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01249                                      LL_RCC_MSI_GetRange() :
01250                                      LL_RCC_MSI_GetRangeAfterStandby()));
01251       break;
01252
01253     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01254       pllinputfreq = HSI_VALUE;
01255       break;
01256
01257     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01258       pllinputfreq = HSE_VALUE;
01259       break;
01260
01261     default:
01262       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01263                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01264                                      LL_RCC_MSI_GetRange() :
01265                                      LL_RCC_MSI_GetRangeAfterStandby()));
01266       break;
01267   }
01268   return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01269                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
01270 }
01271
01272 /**
01273   * @brief  Return PLLSAI1 clock frequency used for SAI domain
01274   * @retval PLLSAI1 clock frequency (in Hz)
01275   */
01276 uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
01277 {
01278   uint32_t pllinputfreq = 0, pllsource = 0;
01279
01280   /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N
01281      SAI Domain clock  = PLLSAI1_VCO / PLLSAI1P
01282   */
01283   pllsource = LL_RCC_PLL_GetMainSource();
01284
01285   switch (pllsource)
01286   {
01287     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
01288       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01289                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01290                                      LL_RCC_MSI_GetRange() :
01291                                      LL_RCC_MSI_GetRangeAfterStandby()));
01292       break;
01293
01294     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
01295       pllinputfreq = HSI_VALUE;
01296       break;
01297
01298     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
01299       pllinputfreq = HSE_VALUE;
01300       break;
01301
01302     default:
01303       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01304                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01305                                      LL_RCC_MSI_GetRange() :
01306                                      LL_RCC_MSI_GetRangeAfterStandby()));
01307       break;
01308   }
01309   return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01310                                         LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
01311 }
01312
01313 /**
01314   * @brief  Return PLLSAI1 clock frequency used for 48Mhz domain
01315   * @retval PLLSAI1 clock frequency (in Hz)
01316   */
01317 uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
01318 {
01319   uint32_t pllinputfreq = 0, pllsource = 0;
01320
01321   /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N
01322      48M Domain clock  = PLLSAI1_VCO / PLLSAI1Q
01323   */
01324   pllsource = LL_RCC_PLL_GetMainSource();
01325
01326   switch (pllsource)
01327   {
01328     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
01329       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01330                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01331                                      LL_RCC_MSI_GetRange() :
01332                                      LL_RCC_MSI_GetRangeAfterStandby()));
01333       break;
01334
01335     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
01336       pllinputfreq = HSI_VALUE;
01337       break;
01338
01339     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
01340       pllinputfreq = HSE_VALUE;
01341       break;
01342
01343     default:
01344       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01345                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01346                                      LL_RCC_MSI_GetRange() :
01347                                      LL_RCC_MSI_GetRangeAfterStandby()));
01348       break;
01349   }
01350   return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01351                                         LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
01352 }
01353
01354 /**
01355   * @brief  Return PLLSAI1 clock frequency used for ADC domain
01356   * @retval PLLSAI1 clock frequency (in Hz)
01357   */
01358 uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
01359 {
01360   uint32_t pllinputfreq = 0, pllsource = 0;
01361
01362   /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N
01363      48M Domain clock  = PLLSAI1_VCO / PLLSAI1R
01364   */
01365   pllsource = LL_RCC_PLL_GetMainSource();
01366
01367   switch (pllsource)
01368   {
01369     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
01370       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01371                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01372                                      LL_RCC_MSI_GetRange() :
01373                                      LL_RCC_MSI_GetRangeAfterStandby()));
01374       break;
01375
01376     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
01377       pllinputfreq = HSI_VALUE;
01378       break;
01379
01380     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
01381       pllinputfreq = HSE_VALUE;
01382       break;
01383
01384     default:
01385       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01386                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01387                                      LL_RCC_MSI_GetRange() :
01388                                      LL_RCC_MSI_GetRangeAfterStandby()));
01389       break;
01390   }
01391   return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01392                                         LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
01393 }
01394
01395 #if defined(RCC_PLLSAI2_SUPPORT)
01396 /**
01397   * @brief  Return PLLSAI2 clock frequency used for SAI domain
01398   * @retval PLLSAI2 clock frequency (in Hz)
01399   */
01400 uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)
01401 {
01402   uint32_t pllinputfreq = 0, pllsource = 0;
01403
01404   /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N
01405      SAI Domain clock  = PLLSAI2_VCO / PLLSAI2P
01406   */
01407   pllsource = LL_RCC_PLL_GetMainSource();
01408
01409   switch (pllsource)
01410   {
01411     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */
01412       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01413                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01414                                      LL_RCC_MSI_GetRange() :
01415                                      LL_RCC_MSI_GetRangeAfterStandby()));
01416       break;
01417
01418     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */
01419       pllinputfreq = HSI_VALUE;
01420       break;
01421
01422     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */
01423       pllinputfreq = HSE_VALUE;
01424       break;
01425
01426     default:
01427       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01428                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01429                                      LL_RCC_MSI_GetRange() :
01430                                      LL_RCC_MSI_GetRangeAfterStandby()));
01431       break;
01432   }
01433   return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01434                                         LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
01435 }
01436
01437 /**
01438   * @brief  Return PLLSAI2 clock frequency used for ADC domain
01439   * @retval PLLSAI2 clock frequency (in Hz)
01440   */
01441 uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void)
01442 {
01443   uint32_t pllinputfreq = 0, pllsource = 0;
01444
01445   /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N
01446      48M Domain clock  = PLLSAI2_VCO / PLLSAI2R
01447   */
01448   pllsource = LL_RCC_PLL_GetMainSource();
01449
01450   switch (pllsource)
01451   {
01452     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */
01453       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01454                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01455                                      LL_RCC_MSI_GetRange() :
01456                                      LL_RCC_MSI_GetRangeAfterStandby()));
01457       break;
01458
01459     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */
01460       pllinputfreq = HSI_VALUE;
01461       break;
01462
01463     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */
01464       pllinputfreq = HSE_VALUE;
01465       break;
01466
01467     default:
01468       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01469                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?
01470                                      LL_RCC_MSI_GetRange() :
01471                                      LL_RCC_MSI_GetRangeAfterStandby()));
01472       break;
01473   }
01474   return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01475                                         LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
01476 }
01477
01478 #endif /*RCC_PLLSAI2_SUPPORT*/
01479 /**
01480   * @}
01481   */
01482
01483 /**
01484   * @}
01485   */
01486
01487 #endif /* defined(RCC) */
01488
01489 /**
01490   * @}
01491   */
01492
01493 #endif /* USE_FULL_LL_DRIVER */
01494
01495 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rcc.h Source File

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stm32l4xx_ll_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_rcc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of RCC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_RCC_H
00040 #define __STM32L4xx_LL_RCC_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(RCC)
00054
00055 /** @defgroup RCC_LL RCC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
00062   * @{
00063   */
00064
00065 static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
00066
00067 /**
00068   * @}
00069   */
00070
00071 /* Private constants ---------------------------------------------------------*/
00072 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
00073   * @{
00074   */
00075 /* Defines used for the bit position in the register and perform offsets*/
00076 #define RCC_POSITION_HPRE       (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)
00077 #define RCC_POSITION_PPRE1      (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)
00078 #define RCC_POSITION_PPRE2      (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)
00079 #define RCC_POSITION_HSICAL     (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL)
00080 #define RCC_POSITION_HSITRIM    (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM)
00081 #define RCC_POSITION_MSICAL     (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL)
00082 #define RCC_POSITION_MSITRIM    (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM)
00083 #if defined(RCC_HSI48_SUPPORT)
00084 #define RCC_POSITION_HSI48CAL   (uint32_t)POSITION_VAL(RCC_CRRCR_HSI48CAL)
00085 #endif /* RCC_HSI48_SUPPORT */
00086 #define RCC_POSITION_PLLN       (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLN)
00087 #define RCC_POSITION_PLLM       (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLM)
00088 #define RCC_POSITION_PLLR       (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLR)
00089 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
00090 #define RCC_POSITION_PLLP       (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLPDIV)
00091 #else
00092 #define RCC_POSITION_PLLP       (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLP)
00093 #endif /* RCC_PLLP_DIV_2_31_SUPPOR T*/
00094 #define RCC_POSITION_PLLQ       (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLQ)
00095 #define RCC_POSITION_PLLSAI1N   (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)
00096 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
00097 #define RCC_POSITION_PLLSAI1P   (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)
00098 #else
00099 #define RCC_POSITION_PLLSAI1P   (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)
00100 #endif /*RCC_PLLSAI1P_DIV_2_31_SUPPORT*/
00101 #define RCC_POSITION_PLLSAI1Q   (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)
00102 #define RCC_POSITION_PLLSAI1R   (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)
00103 #if defined(RCC_PLLSAI2_SUPPORT)
00104 #define RCC_POSITION_PLLSAI2N   (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)
00105 #define RCC_POSITION_PLLSAI2P   (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)
00106 #define RCC_POSITION_PLLSAI2R   (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)
00107 #endif /* RCC_PLLSAI2_SUPPORT */
00108
00109 /**
00110   * @}
00111   */
00112
00113 /* Private macros ------------------------------------------------------------*/
00114 #if defined(USE_FULL_LL_DRIVER)
00115 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
00116   * @{
00117   */
00118 /**
00119   * @}
00120   */
00121 #endif /*USE_FULL_LL_DRIVER*/
00122 /* Exported types ------------------------------------------------------------*/
00123 #if defined(USE_FULL_LL_DRIVER)
00124 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
00125   * @{
00126   */
00127
00128 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  RCC Clocks Frequency Structure
00134   */
00135 typedef struct
00136 {
00137   uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
00138   uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
00139   uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
00140   uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
00141 } LL_RCC_ClocksTypeDef;
00142
00143 /**
00144   * @}
00145   */
00146
00147 /**
00148   * @}
00149   */
00150 #endif /* USE_FULL_LL_DRIVER */
00151
00152 /* Exported constants --------------------------------------------------------*/
00153 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
00154   * @{
00155   */
00156
00157 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
00158   * @brief    Defines used to adapt values of different oscillators
00159   * @note     These values could be modified in the user environment according to
00160   *           HW set-up.
00161   * @{
00162   */
00163 #if !defined  (HSE_VALUE)
00164 #define HSE_VALUE    ((uint32_t)8000000)  /*!< Value of the HSE oscillator in Hz */
00165 #endif /* HSE_VALUE */
00166
00167 #if !defined  (HSI_VALUE)
00168 #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the HSI oscillator in Hz */
00169 #endif /* HSI_VALUE */
00170
00171 #if !defined  (LSE_VALUE)
00172 #define LSE_VALUE    ((uint32_t)32768)    /*!< Value of the LSE oscillator in Hz */
00173 #endif /* LSE_VALUE */
00174
00175 #if !defined  (LSI_VALUE)
00176 #define LSI_VALUE    ((uint32_t)32000)    /*!< Value of the LSI oscillator in Hz */
00177 #endif /* LSI_VALUE */
00178 #if defined(RCC_HSI48_SUPPORT)
00179
00180 #if !defined  (HSI48_VALUE)
00181 #define HSI48_VALUE  ((uint32_t)48000000) /*!< Value of the HSI48 oscillator in Hz */
00182 #endif /* HSI48_VALUE */
00183 #endif /* RCC_HSI48_SUPPORT */
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
00189   * @brief    Flags defines which can be used with LL_RCC_WriteReg function
00190   * @{
00191   */
00192 #define LL_RCC_CICR_LSIRDYC                RCC_CICR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
00193 #define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC     /*!< LSE Ready Interrupt Clear */
00194 #define LL_RCC_CICR_MSIRDYC                RCC_CICR_MSIRDYC     /*!< MSI Ready Interrupt Clear */
00195 #define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
00196 #define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC     /*!< HSE Ready Interrupt Clear */
00197 #define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
00198 #if defined(RCC_HSI48_SUPPORT)
00199 #define LL_RCC_CICR_HSI48RDYC              RCC_CICR_HSI48RDYC   /*!< HSI48 Ready Interrupt Clear */
00200 #endif /* RCC_HSI48_SUPPORT */
00201 #define LL_RCC_CICR_PLLSAI1RDYC            RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
00202 #if defined(RCC_PLLSAI2_SUPPORT)
00203 #define LL_RCC_CICR_PLLSAI2RDYC            RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */
00204 #endif /* RCC_PLLSAI2_SUPPORT */
00205 #define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
00206 #define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC        /*!< Clock Security System Interrupt Clear */
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
00212   * @brief    Flags defines which can be used with LL_RCC_ReadReg function
00213   * @{
00214   */
00215 #define LL_RCC_CIFR_LSIRDYF                RCC_CIFR_LSIRDYF     /*!< LSI Ready Interrupt flag */
00216 #define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF     /*!< LSE Ready Interrupt flag */
00217 #define LL_RCC_CIFR_MSIRDYF                RCC_CIFR_MSIRDYF     /*!< MSI Ready Interrupt flag */
00218 #define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF     /*!< HSI Ready Interrupt flag */
00219 #define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF     /*!< HSE Ready Interrupt flag */
00220 #define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF     /*!< PLL Ready Interrupt flag */
00221 #if defined(RCC_HSI48_SUPPORT)
00222 #define LL_RCC_CIFR_HSI48RDYF              RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
00223 #endif /* RCC_HSI48_SUPPORT */
00224 #define LL_RCC_CIFR_PLLSAI1RDYF            RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
00225 #if defined(RCC_PLLSAI2_SUPPORT)
00226 #define LL_RCC_CIFR_PLLSAI2RDYF            RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
00227 #endif /* RCC_PLLSAI2_SUPPORT */
00228 #define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
00229 #define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
00230 #define LL_RCC_CSR_FWRSTF                  RCC_CSR_FWRSTF     /*!< Firewall reset flag */
00231 #define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
00232 #define LL_RCC_CSR_OBLRSTF                 RCC_CSR_OBLRSTF    /*!< OBL reset flag */
00233 #define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
00234 #define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
00235 #define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
00236 #define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
00237 #define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup RCC_LL_EC_IT IT Defines
00243   * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
00244   * @{
00245   */
00246 #define LL_RCC_CIER_LSIRDYIE               RCC_CIER_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
00247 #define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE      /*!< LSE Ready Interrupt Enable */
00248 #define LL_RCC_CIER_MSIRDYIE               RCC_CIER_MSIRDYIE      /*!< MSI Ready Interrupt Enable */
00249 #define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
00250 #define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE      /*!< HSE Ready Interrupt Enable */
00251 #define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
00252 #if defined(RCC_HSI48_SUPPORT)
00253 #define LL_RCC_CIER_HSI48RDYIE             RCC_CIER_HSI48RDYIE    /*!< HSI48 Ready Interrupt Enable */
00254 #endif /* RCC_HSI48_SUPPORT */
00255 #define LL_RCC_CIER_PLLSAI1RDYIE           RCC_CIER_PLLSAI1RDYIE  /*!< PLLSAI1 Ready Interrupt Enable */
00256 #if defined(RCC_PLLSAI2_SUPPORT)
00257 #define LL_RCC_CIER_PLLSAI2RDYIE           RCC_CIER_PLLSAI2RDYIE  /*!< PLLSAI2 Ready Interrupt Enable */
00258 #endif /* RCC_PLLSAI2_SUPPORT */
00259 #define LL_RCC_CIER_LSECSSIE               RCC_CIER_LSECSSIE      /*!< LSE CSS Interrupt Enable */
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
00265   * @{
00266   */
00267 #define LL_RCC_LSEDRIVE_LOW                ((uint32_t)0x00000000)  /*!< Xtal mode lower driving capability */
00268 #define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium low driving capability */
00269 #define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium high driving capability */
00270 #define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving capability */
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup RCC_LL_EC_MSIRANGE  MSI clock ranges
00276   * @{
00277   */
00278 #define LL_RCC_MSIRANGE_0                  RCC_CR_MSIRANGE_0  /*!< MSI = 100 KHz  */
00279 #define LL_RCC_MSIRANGE_1                  RCC_CR_MSIRANGE_1  /*!< MSI = 200 KHz  */
00280 #define LL_RCC_MSIRANGE_2                  RCC_CR_MSIRANGE_2  /*!< MSI = 400 KHz  */
00281 #define LL_RCC_MSIRANGE_3                  RCC_CR_MSIRANGE_3  /*!< MSI = 800 KHz  */
00282 #define LL_RCC_MSIRANGE_4                  RCC_CR_MSIRANGE_4  /*!< MSI = 1 MHz    */
00283 #define LL_RCC_MSIRANGE_5                  RCC_CR_MSIRANGE_5  /*!< MSI = 2 MHz    */
00284 #define LL_RCC_MSIRANGE_6                  RCC_CR_MSIRANGE_6  /*!< MSI = 4 MHz    */
00285 #define LL_RCC_MSIRANGE_7                  RCC_CR_MSIRANGE_7  /*!< MSI = 8 MHz    */
00286 #define LL_RCC_MSIRANGE_8                  RCC_CR_MSIRANGE_8  /*!< MSI = 16 MHz   */
00287 #define LL_RCC_MSIRANGE_9                  RCC_CR_MSIRANGE_9  /*!< MSI = 24 MHz   */
00288 #define LL_RCC_MSIRANGE_10                 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz   */
00289 #define LL_RCC_MSIRANGE_11                 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz   */
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup RCC_LL_EC_MSISRANGE  MSI range after Standby mode
00295   * @{
00296   */
00297 #define LL_RCC_MSISRANGE_4                 RCC_CSR_MSISRANGE_1  /*!< MSI = 1 MHz    */
00298 #define LL_RCC_MSISRANGE_5                 RCC_CSR_MSISRANGE_2  /*!< MSI = 2 MHz    */
00299 #define LL_RCC_MSISRANGE_6                 RCC_CSR_MSISRANGE_4  /*!< MSI = 4 MHz    */
00300 #define LL_RCC_MSISRANGE_7                 RCC_CSR_MSISRANGE_8  /*!< MSI = 8 MHz    */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE  LSCO Selection
00306   * @{
00307   */
00308 #define LL_RCC_LSCO_CLKSOURCE_LSI          (uint32_t)0x00000000  /*!< LSI selection for low speed clock  */
00309 #define LL_RCC_LSCO_CLKSOURCE_LSE          RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock  */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
00315   * @{
00316   */
00317 #define LL_RCC_SYS_CLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
00318 #define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
00319 #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
00320 #define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
00326   * @{
00327   */
00328 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
00329 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00330 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00331 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
00337   * @{
00338   */
00339 #define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
00340 #define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
00341 #define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
00342 #define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
00343 #define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
00344 #define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
00345 #define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
00346 #define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
00347 #define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
00353   * @{
00354   */
00355 #define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
00356 #define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
00357 #define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
00358 #define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
00359 #define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
00360 /**
00361   * @}
00362   */
00363 /** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
00364   * @{
00365   */
00366 #define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
00367 #define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
00368 #define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
00369 #define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
00370 #define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
00371 /**
00372   * @}
00373   */
00374 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK  Wakeup from Stop and CSS backup clock selection
00375   * @{
00376   */
00377 #define LL_RCC_STOP_WAKEUPCLOCK_MSI        ((uint32_t)0x00000000)  /*!< MSI selection after wake-up from STOP */
00378 #define LL_RCC_STOP_WAKEUPCLOCK_HSI        RCC_CFGR_STOPWUCK       /*!< HSI selection after wake-up from STOP */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
00384   * @{
00385   */
00386 #define LL_RCC_MCO1SOURCE_NOCLOCK          ((uint32_t)0x00000000)                 /*!< MCO output disabled, no clock on MCO */
00387 #define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
00388 #define LL_RCC_MCO1SOURCE_MSI              RCC_CFGR_MCOSEL_1                      /*!< MSI selection as MCO1 source */
00389 #define LL_RCC_MCO1SOURCE_HSI              (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
00390 #define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
00391 #define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< Main PLL selection as MCO1 source */
00392 #define LL_RCC_MCO1SOURCE_LSI              (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
00393 #define LL_RCC_MCO1SOURCE_LSE              (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
00394 #if defined(RCC_HSI48_SUPPORT)
00395 #define LL_RCC_MCO1SOURCE_HSI48            RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source */
00396 #endif /* RCC_HSI48_SUPPORT */
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
00402   * @{
00403   */
00404 #define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCOPRE_DIV1       /*!< MCO not divided */
00405 #define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2       /*!< MCO divided by 2 */
00406 #define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4       /*!< MCO divided by 4 */
00407 #define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8       /*!< MCO divided by 8 */
00408 #define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16      /*!< MCO divided by 16 */
00409 /**
00410   * @}
00411   */
00412
00413 #if defined(USE_FULL_LL_DRIVER)
00414 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
00415   * @{
00416   */
00417 #define LL_RCC_PERIPH_FREQUENCY_NO         (uint32_t)0x00000000       /*!< No clock enabled for the peripheral            */
00418 #define LL_RCC_PERIPH_FREQUENCY_NA    (uint32_t)0xFFFFFFFFU       /*!< Frequency cannot be provided as external clock */
00419 /**
00420   * @}
00421   */
00422 #endif /* USE_FULL_LL_DRIVER */
00423
00424 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE  Peripheral USART clock source selection
00425   * @{
00426   */
00427 #define LL_RCC_USART1_CLKSOURCE_PCLK2      (uint32_t)((RCC_CCIPR_USART1SEL << 16) | 0x00000000)            /*!< PCLK2 clock used as USART1 clock source */
00428 #define LL_RCC_USART1_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
00429 #define LL_RCC_USART1_CLKSOURCE_HSI        (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
00430 #define LL_RCC_USART1_CLKSOURCE_LSE        (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL)   /*!< LSE clock used as USART1 clock source */
00431 #define LL_RCC_USART2_CLKSOURCE_PCLK1      (uint32_t)((RCC_CCIPR_USART2SEL << 16) | 0x00000000)            /*!< PCLK1 clock used as USART2 clock source */
00432 #define LL_RCC_USART2_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
00433 #define LL_RCC_USART2_CLKSOURCE_HSI        (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
00434 #define LL_RCC_USART2_CLKSOURCE_LSE        (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL)   /*!< LSE clock used as USART2 clock source */
00435 #if defined(RCC_CCIPR_USART3SEL)
00436 #define LL_RCC_USART3_CLKSOURCE_PCLK1      (uint32_t)((RCC_CCIPR_USART3SEL << 16) | 0x00000000)            /*!< PCLK1 clock used as USART3 clock source */
00437 #define LL_RCC_USART3_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
00438 #define LL_RCC_USART3_CLKSOURCE_HSI        (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
00439 #define LL_RCC_USART3_CLKSOURCE_LSE        (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL)   /*!< LSE clock used as USART3 clock source */
00440 #endif /* RCC_CCIPR_USART3SEL */
00441 /**
00442   * @}
00443   */
00444
00445 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
00446 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE  Peripheral UART clock source selection
00447   * @{
00448   */
00449 #if defined(RCC_CCIPR_UART4SEL)
00450 #define LL_RCC_UART4_CLKSOURCE_PCLK1       (uint32_t)((RCC_CCIPR_UART4SEL << 16) | 0x00000000)            /*!< PCLK1 clock used as UART4 clock source */
00451 #define LL_RCC_UART4_CLKSOURCE_SYSCLK      (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_0)  /*!< SYSCLK clock used as UART4 clock source */
00452 #define LL_RCC_UART4_CLKSOURCE_HSI         (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_1)  /*!< HSI clock used as UART4 clock source */
00453 #define LL_RCC_UART4_CLKSOURCE_LSE         (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL)    /*!< LSE clock used as UART4 clock source */
00454 #endif /* RCC_CCIPR_UART4SEL */
00455 #if defined(RCC_CCIPR_UART5SEL)
00456 #define LL_RCC_UART5_CLKSOURCE_PCLK1       (uint32_t)((RCC_CCIPR_UART5SEL << 16) | 0x00000000)            /*!< PCLK1 clock used as UART5 clock source */
00457 #define LL_RCC_UART5_CLKSOURCE_SYSCLK      (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_0)  /*!< SYSCLK clock used as UART5 clock source */
00458 #define LL_RCC_UART5_CLKSOURCE_HSI         (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_1)  /*!< HSI clock used as UART5 clock source */
00459 #define LL_RCC_UART5_CLKSOURCE_LSE         (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL)    /*!< LSE clock used as UART5 clock source */
00460 #endif /* RCC_CCIPR_UART5SEL */
00461 /**
00462   * @}
00463   */
00464 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
00465
00466 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE  Peripheral LPUART clock source selection
00467   * @{
00468   */
00469 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1     (uint32_t)0x00000000            /*!< PCLK1 clock used as LPUART1 clock source */
00470 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0          /*!< SYSCLK clock used as LPUART1 clock source */
00471 #define LL_RCC_LPUART1_CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1          /*!< HSI clock used as LPUART1 clock source */
00472 #define LL_RCC_LPUART1_CLKSOURCE_LSE       RCC_CCIPR_LPUART1SEL            /*!< LSE clock used as LPUART1 clock source */
00473 /**
00474   * @}
00475   */
00476
00477 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE  Peripheral I2C clock source selection
00478   * @{
00479   */
00480 #define LL_RCC_I2C1_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000 >> 4))          /*!< PCLK1 clock used as I2C1 clock source */
00481 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK clock used as I2C1 clock source */
00482 #define LL_RCC_I2C1_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI clock used as I2C1 clock source */
00483 #if defined(RCC_CCIPR_I2C2SEL)
00484 #define LL_RCC_I2C2_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (0x00000000 >> 4))          /*!< PCLK1 clock used as I2C2 clock source */
00485 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_0 >> 4)) /*!< SYSCLK clock used as I2C2 clock source */
00486 #define LL_RCC_I2C2_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_1 >> 4)) /*!< HSI clock used as I2C2 clock source */
00487 #endif /* RCC_CCIPR_I2C2SEL */
00488 #define LL_RCC_I2C3_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000 >> 4))          /*!< PCLK1 clock used as I2C3 clock source */
00489 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK clock used as I2C3 clock source */
00490 #define LL_RCC_I2C3_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI clock used as I2C3 clock source */
00491 /**
00492   * @}
00493   */
00494
00495 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
00496   * @{
00497   */
00498 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000 >> 16))            /*!< PCLK1 clock used as LPTIM1 clock source */
00499 #define LL_RCC_LPTIM1_CLKSOURCE_LSI        (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI clock used as LPTIM1 clock source */
00500 #define LL_RCC_LPTIM1_CLKSOURCE_HSI        (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI clock used as LPTIM1 clock source */
00501 #define LL_RCC_LPTIM1_CLKSOURCE_LSE        (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16))   /*!< LSE clock used as LPTIM1 clock source */
00502 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1      (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000 >> 16))            /*!< PCLK1 clock used as LPTIM2 clock source */
00503 #define LL_RCC_LPTIM2_CLKSOURCE_LSI        (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI clock used as LPTIM2 clock source */
00504 #define LL_RCC_LPTIM2_CLKSOURCE_HSI        (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI clock used as LPTIM2 clock source */
00505 #define LL_RCC_LPTIM2_CLKSOURCE_LSE        (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16))   /*!< LSE clock used as LPTIM2 clock source */
00506 /**
00507   * @}
00508   */
00509
00510 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE  Peripheral SAI clock source selection
00511   * @{
00512   */
00513 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1      (uint32_t)(RCC_CCIPR_SAI1SEL | (0x00000000 >> 16))          /*!< PLLSAI1 clock used as SAI1 clock source */
00514 #if defined(RCC_PLLSAI2_SUPPORT)
00515 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2      (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16)) /*!< PLLSAI2 clock used as SAI1 clock source */
00516 #endif /* RCC_PLLSAI2_SUPPORT */
00517 #define LL_RCC_SAI1_CLKSOURCE_PLL          (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16)) /*!< PLL clock used as SAI1 clock source */
00518 #define LL_RCC_SAI1_CLKSOURCE_PIN          (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16))   /*!< External input clock used as SAI1 clock source */
00519 #if defined(RCC_CCIPR_SAI2SEL)
00520 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1      (uint32_t)(RCC_CCIPR_SAI2SEL | (0x00000000 >> 16))          /*!< PLLSAI1 clock used as SAI2 clock source */
00521 #if defined(RCC_PLLSAI2_SUPPORT)
00522 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2      (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16)) /*!< PLLSAI2 clock used as SAI2 clock source */
00523 #endif /* RCC_PLLSAI2_SUPPORT */
00524 #define LL_RCC_SAI2_CLKSOURCE_PLL          (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16)) /*!< PLL clock used as SAI2 clock source */
00525 #define LL_RCC_SAI2_CLKSOURCE_PIN          (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16))   /*!< External input clock used as SAI2 clock source */
00526 #endif /* RCC_CCIPR_SAI2SEL */
00527 /**
00528   * @}
00529   */
00530
00531 /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE  Peripheral SDMMC clock source selection
00532   * @{
00533   */
00534 #define LL_RCC_SDMMC1_CLKSOURCE_NONE       (uint32_t)(0x00000000)           /*!< No clock used as SDMMC1 clock source */
00535 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1    (uint32_t)(RCC_CCIPR_CLK48SEL_0) /*!< PLLSAI1 clock used as SDMMC1 clock source */
00536 #define LL_RCC_SDMMC1_CLKSOURCE_PLL        (uint32_t)(RCC_CCIPR_CLK48SEL_1) /*!< PLL clock used as SDMMC1 clock source */
00537 #define LL_RCC_SDMMC1_CLKSOURCE_MSI        (uint32_t)(RCC_CCIPR_CLK48SEL)   /*!< MSI clock used as SDMMC1 clock source */
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
00543   * @{
00544   */
00545 #define LL_RCC_RNG_CLKSOURCE_NONE          (uint32_t)(0x00000000)           /*!< No clock used as RNG clock source */
00546 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1       (uint32_t)(RCC_CCIPR_CLK48SEL_0) /*!< PLLSAI1 clock used as RNG clock source */
00547 #define LL_RCC_RNG_CLKSOURCE_PLL           (uint32_t)(RCC_CCIPR_CLK48SEL_1) /*!< PLL clock used as RNG clock source */
00548 #define LL_RCC_RNG_CLKSOURCE_MSI           (uint32_t)(RCC_CCIPR_CLK48SEL)   /*!< MSI clock used as RNG clock source */
00549 /**
00550   * @}
00551   */
00552
00553 #if defined(USB_OTG_FS) || defined(USB)
00554 /** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
00555   * @{
00556   */
00557 #define LL_RCC_USB_CLKSOURCE_NONE          (uint32_t)(0x00000000)           /*!< No clock used as USB clock source */
00558 #define LL_RCC_USB_CLKSOURCE_PLLSAI1       (uint32_t)(RCC_CCIPR_CLK48SEL_0) /*!< PLLSAI1 clock used as USB clock source */
00559 #define LL_RCC_USB_CLKSOURCE_PLL           (uint32_t)(RCC_CCIPR_CLK48SEL_1) /*!< PLL clock used as USB clock source */
00560 #define LL_RCC_USB_CLKSOURCE_MSI           (uint32_t)(RCC_CCIPR_CLK48SEL)   /*!< MSI clock used as USB clock source */
00561 /**
00562   * @}
00563   */
00564
00565 #endif /* USB_OTG_FS || USB */
00566
00567 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
00568   * @{
00569   */
00570 #define LL_RCC_ADC_CLKSOURCE_NONE          (uint32_t)(0x00000000)           /*!< No clock used as ADC clock source */
00571 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1       (uint32_t)(RCC_CCIPR_ADCSEL_0)   /*!< PLLSAI1 clock used as ADC clock source */
00572 #if defined(RCC_PLLSAI2_SUPPORT)
00573 #define LL_RCC_ADC_CLKSOURCE_PLLSAI2       (uint32_t)(RCC_CCIPR_ADCSEL_1)   /*!< PLLSAI2 clock used as ADC clock source */
00574 #endif /* RCC_PLLSAI2_SUPPORT */
00575 #define LL_RCC_ADC_CLKSOURCE_SYSCLK        (uint32_t)(RCC_CCIPR_ADCSEL)     /*!< SYSCLK clock used as ADC clock source */
00576 /**
00577   * @}
00578   */
00579
00580 /** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE  Peripheral SWPMI clock source selection
00581   * @{
00582   */
00583 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK       (uint32_t)(0x00000000)           /*!< PCLK used as SWPMI1 clock source */
00584 #define LL_RCC_SWPMI1_CLKSOURCE_HSI        (uint32_t)(RCC_CCIPR_SWPMI1SEL)  /*!< HSI used as SWPMI1 clock source */
00585 /**
00586   * @}
00587   */
00588
00589 #if defined(DFSDM1_Channel0)
00590 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM clock source selection
00591   * @{
00592   */
00593 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK       (uint32_t)(0x00000000)           /*!< PCLK used as DFSDM1 clock source */
00594 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK     (uint32_t)(RCC_CCIPR_DFSDM1SEL)  /*!< SYSCLK used as DFSDM1 clock source */
00595 /**
00596   * @}
00597   */
00598 #endif /* DFSDM1_Channel0 */
00599
00600 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
00601   * @{
00602   */
00603 #define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
00604 #define LL_RCC_USART2_CLKSOURCE            RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
00605 #if defined(RCC_CCIPR_USART3SEL)
00606 #define LL_RCC_USART3_CLKSOURCE            RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
00607 #endif /* RCC_CCIPR_USART3SEL */
00608 /**
00609   * @}
00610   */
00611
00612 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
00613 /** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
00614   * @{
00615   */
00616 #if defined(RCC_CCIPR_UART4SEL)
00617 #define LL_RCC_UART4_CLKSOURCE             RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
00618 #endif /* RCC_CCIPR_UART4SEL */
00619 #if defined(RCC_CCIPR_UART5SEL)
00620 #define LL_RCC_UART5_CLKSOURCE             RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
00621 #endif /* RCC_CCIPR_UART5SEL */
00622 /**
00623   * @}
00624   */
00625 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
00626
00627 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
00628   * @{
00629   */
00630 #define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
00631 /**
00632   * @}
00633   */
00634
00635 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
00636   * @{
00637   */
00638 #define LL_RCC_I2C1_CLKSOURCE              RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */
00639 #if defined(RCC_CCIPR_I2C2SEL)
00640 #define LL_RCC_I2C2_CLKSOURCE              RCC_CCIPR_I2C2SEL /*!< I2C2 Clock source selection */
00641 #endif /* RCC_CCIPR_I2C2SEL */
00642 #define LL_RCC_I2C3_CLKSOURCE              RCC_CCIPR_I2C3SEL /*!< I2C3 Clock source selection */
00643 /**
00644   * @}
00645   */
00646
00647 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
00648   * @{
00649   */
00650 #define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
00651 #define LL_RCC_LPTIM2_CLKSOURCE            RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
00652 /**
00653   * @}
00654   */
00655
00656 /** @defgroup RCC_LL_EC_SAI1  Peripheral SAI get clock source
00657   * @{
00658   */
00659 #define LL_RCC_SAI1_CLKSOURCE              RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
00660 #if defined(RCC_CCIPR_SAI2SEL)
00661 #define LL_RCC_SAI2_CLKSOURCE              RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */
00662 #endif /* RCC_CCIPR_SAI2SEL */
00663 /**
00664   * @}
00665   */
00666
00667 /** @defgroup RCC_LL_EC_SDMMC1  Peripheral SDMMC get clock source
00668   * @{
00669   */
00670 #define LL_RCC_SDMMC1_CLKSOURCE            RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */
00671 /**
00672   * @}
00673   */
00674
00675 /** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
00676   * @{
00677   */
00678 #define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
00679 /**
00680   * @}
00681   */
00682
00683 #if defined(USB_OTG_FS) || defined(USB)
00684 /** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
00685   * @{
00686   */
00687 #define LL_RCC_USB_CLKSOURCE               RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
00688 /**
00689   * @}
00690   */
00691
00692 #endif /* USB_OTG_FS || USB */
00693
00694 /** @defgroup RCC_LL_EC_ADC  Peripheral ADC get clock source
00695   * @{
00696   */
00697 #define LL_RCC_ADC_CLKSOURCE               RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
00698 /**
00699   * @}
00700   */
00701
00702 /** @defgroup RCC_LL_EC_SWPMI1  Peripheral SWPMI get clock source
00703   * @{
00704   */
00705 #define LL_RCC_SWPMI1_CLKSOURCE            RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */
00706 /**
00707   * @}
00708   */
00709
00710 #if defined(DFSDM1_Channel0)
00711 /** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
00712   * @{
00713   */
00714 #define LL_RCC_DFSDM1_CLKSOURCE            RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */
00715 /**
00716   * @}
00717   */
00718 #endif /* DFSDM1_Channel0 */
00719
00720 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
00721   * @{
00722   */
00723 #define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)(0x00000000)        /*!< No clock used as RTC clock */
00724 #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
00725 #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
00726 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
00727 /**
00728   * @}
00729   */
00730
00731 /** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLSAI1 and PLLSAI2 entry clock source
00732   * @{
00733   */
00734 #define LL_RCC_PLLSOURCE_NONE              (uint32_t)0x00000000    /*!< No clock */
00735 #define LL_RCC_PLLSOURCE_MSI               RCC_PLLCFGR_PLLSRC_MSI  /*!< MSI clock selected as PLL entry clock source */
00736 #define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */
00737 #define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
00738 /**
00739   * @}
00740   */
00741
00742 /** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLSAI1 and PLLSAI2 division factor
00743   * @{
00744   */
00745 #define LL_RCC_PLLM_DIV_1                  ((uint32_t)0x00000000)                      /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 1 */
00746 #define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_0)                        /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 2 */
00747 #define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1)                        /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 3 */
00748 #define LL_RCC_PLLM_DIV_4                  ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 4 */
00749 #define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2)                        /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 5 */
00750 #define LL_RCC_PLLM_DIV_6                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 6 */
00751 #define LL_RCC_PLLM_DIV_7                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 7 */
00752 #define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM)                          /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 8 */
00753 /**
00754   * @}
00755   */
00756
00757 /** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
00758   * @{
00759   */
00760 #define LL_RCC_PLLR_DIV_2                  ((uint32_t)0x00000000) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
00761 #define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_0)   /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
00762 #define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_1)   /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
00763 #define LL_RCC_PLLR_DIV_8                  (RCC_PLLCFGR_PLLR)     /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
00764 /**
00765   * @}
00766   */
00767
00768 /** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
00769   * @{
00770   */
00771 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
00772 #define LL_RCC_PLLP_DIV_2                  (RCC_PLLCFGR_PLLPDIV_1)                                              /*!< Main PLL division factor for PLLP output by 2 */
00773 #define LL_RCC_PLLP_DIV_3                  (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 3 */
00774 #define LL_RCC_PLLP_DIV_4                  (RCC_PLLCFGR_PLLPDIV_2)                                              /*!< Main PLL division factor for PLLP output by 4 */
00775 #define LL_RCC_PLLP_DIV_5                  (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2)                        /*!< Main PLL division factor for PLLP output by 5 */
00776 #define LL_RCC_PLLP_DIV_6                  (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2)                        /*!< Main PLL division factor for PLLP output by 6 */
00777 #define LL_RCC_PLLP_DIV_7                  (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2)  /*!< Main PLL division factor for PLLP output by 7 */
00778 #define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLPDIV_3)                                              /*!< Main PLL division factor for PLLP output by 8 */
00779 #define LL_RCC_PLLP_DIV_9                  (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3)                        /*!< Main PLL division factor for PLLP output by 9 */
00780 #define LL_RCC_PLLP_DIV_10                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3)                        /*!< Main PLL division factor for PLLP output by 10 */
00781 #define LL_RCC_PLLP_DIV_11                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3)) /*!< Main PLL division factor for PLLP output by 11 */
00782 #define LL_RCC_PLLP_DIV_12                 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3)                        /*!< Main PLL division factor for PLLP output by 12 */
00783 #define LL_RCC_PLLP_DIV_13                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3)  /*!< Main PLL division factor for PLLP output by 13 */
00784 #define LL_RCC_PLLP_DIV_14                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3)  /*!< Main PLL division factor for PLLP output by 14 */
00785 #define LL_RCC_PLLP_DIV_15                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 15 */
00786 #define LL_RCC_PLLP_DIV_16                 (RCC_PLLCFGR_PLLPDIV_4)                                              /*!< Main PLL division factor for PLLP output by 16 */
00787 #define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_4)                        /*!< Main PLL division factor for PLLP output by 17 */
00788 #define LL_RCC_PLLP_DIV_18                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4)                        /*!< Main PLL division factor for PLLP output by 18 */
00789 #define LL_RCC_PLLP_DIV_19                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4)) /*!< Main PLL division factor for PLLP output by 19 */
00790 #define LL_RCC_PLLP_DIV_20                 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4)                        /*!< Main PLL division factor for PLLP output by 20 */
00791 #define LL_RCC_PLLP_DIV_21                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4)  /*!< Main PLL division factor for PLLP output by 21 */
00792 #define LL_RCC_PLLP_DIV_22                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4)  /*!< Main PLL division factor for PLLP output by 22 */
00793 #define LL_RCC_PLLP_DIV_23                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 23 */
00794 #define LL_RCC_PLLP_DIV_24                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4)                        /*!< Main PLL division factor for PLLP output by 24 */
00795 #define LL_RCC_PLLP_DIV_25                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4)  /*!< Main PLL division factor for PLLP output by 25 */
00796 #define LL_RCC_PLLP_DIV_26                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4)  /*!< Main PLL division factor for PLLP output by 26 */
00797 #define LL_RCC_PLLP_DIV_27                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 27 */
00798 #define LL_RCC_PLLP_DIV_28                 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4)  /*!< Main PLL division factor for PLLP output by 28 */
00799 #define LL_RCC_PLLP_DIV_29                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 29 */
00800 #define LL_RCC_PLLP_DIV_30                 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 30 */
00801 #define LL_RCC_PLLP_DIV_31                 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 31 */
00802 #else
00803 #define LL_RCC_PLLP_DIV_7                  ((uint32_t)0x00000000) /*!< Main PLL division factor for PLLP output by 7 */
00804 #define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLP)     /*!< Main PLL division factor for PLLP output by 17 */
00805 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
00806 /**
00807   * @}
00808   */
00809
00810 /** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
00811   * @{
00812   */
00813 #define LL_RCC_PLLQ_DIV_2                  ((uint32_t)0x00000000)  /*!< Main PLL division factor for PLLQ output by 2 */
00814 #define LL_RCC_PLLQ_DIV_4                  (RCC_PLLCFGR_PLLQ_0)    /*!< Main PLL division factor for PLLQ output by 4 */
00815 #define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_1)    /*!< Main PLL division factor for PLLQ output by 6 */
00816 #define LL_RCC_PLLQ_DIV_8                  (RCC_PLLCFGR_PLLQ)      /*!< Main PLL division factor for PLLQ output by 8 */
00817 /**
00818   * @}
00819   */
00820
00821 /** @defgroup RCC_LL_EC_PLLSAI1Q  PLLSAI1 division factor (PLLSAI1Q)
00822   * @{
00823   */
00824 #define LL_RCC_PLLSAI1Q_DIV_2              ((uint32_t)0x00000000)       /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
00825 #define LL_RCC_PLLSAI1Q_DIV_4              (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
00826 #define LL_RCC_PLLSAI1Q_DIV_6              (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
00827 #define LL_RCC_PLLSAI1Q_DIV_8              (RCC_PLLSAI1CFGR_PLLSAI1Q)   /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
00828 /**
00829   * @}
00830   */
00831
00832 /** @defgroup RCC_LL_EC_PLLSAI1P  PLLSAI1 division factor (PLLSAI1P)
00833   * @{
00834   */
00835 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
00836 #define LL_RCC_PLLSAI1P_DIV_2              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */
00837 #define LL_RCC_PLLSAI1P_DIV_3              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */
00838 #define LL_RCC_PLLSAI1P_DIV_4              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */
00839 #define LL_RCC_PLLSAI1P_DIV_5              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */
00840 #define LL_RCC_PLLSAI1P_DIV_6              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */
00841 #define LL_RCC_PLLSAI1P_DIV_7              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
00842 #define LL_RCC_PLLSAI1P_DIV_8              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */
00843 #define LL_RCC_PLLSAI1P_DIV_9              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */
00844 #define LL_RCC_PLLSAI1P_DIV_10             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */
00845 #define LL_RCC_PLLSAI1P_DIV_11             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */
00846 #define LL_RCC_PLLSAI1P_DIV_12             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */
00847 #define LL_RCC_PLLSAI1P_DIV_13             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */
00848 #define LL_RCC_PLLSAI1P_DIV_14             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */
00849 #define LL_RCC_PLLSAI1P_DIV_15             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */
00850 #define LL_RCC_PLLSAI1P_DIV_16             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */
00851 #define LL_RCC_PLLSAI1P_DIV_17             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
00852 #define LL_RCC_PLLSAI1P_DIV_18             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */
00853 #define LL_RCC_PLLSAI1P_DIV_19             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */
00854 #define LL_RCC_PLLSAI1P_DIV_20             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */
00855 #define LL_RCC_PLLSAI1P_DIV_21             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */
00856 #define LL_RCC_PLLSAI1P_DIV_22             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */
00857 #define LL_RCC_PLLSAI1P_DIV_23             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */
00858 #define LL_RCC_PLLSAI1P_DIV_24             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */
00859 #define LL_RCC_PLLSAI1P_DIV_25             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */
00860 #define LL_RCC_PLLSAI1P_DIV_26             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */
00861 #define LL_RCC_PLLSAI1P_DIV_27             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */
00862 #define LL_RCC_PLLSAI1P_DIV_28             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */
00863 #define LL_RCC_PLLSAI1P_DIV_29             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */
00864 #define LL_RCC_PLLSAI1P_DIV_30             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */
00865 #define LL_RCC_PLLSAI1P_DIV_31             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
00866 #else
00867 #define LL_RCC_PLLSAI1P_DIV_7              ((uint32_t)0x00000000)     /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
00868 #define LL_RCC_PLLSAI1P_DIV_17             (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
00869 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
00870 /**
00871   * @}
00872   */
00873
00874 /** @defgroup RCC_LL_EC_PLLSAI1R  PLLSAI1 division factor (PLLSAI1R)
00875   * @{
00876   */
00877 #define LL_RCC_PLLSAI1R_DIV_2              ((uint32_t)0x00000000)       /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
00878 #define LL_RCC_PLLSAI1R_DIV_4              (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
00879 #define LL_RCC_PLLSAI1R_DIV_6              (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
00880 #define LL_RCC_PLLSAI1R_DIV_8              (RCC_PLLSAI1CFGR_PLLSAI1R)   /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
00881 /**
00882   * @}
00883   */
00884
00885 #if defined(RCC_PLLSAI2_SUPPORT)
00886 /** @defgroup RCC_LL_EC_PLLSAI2P  PLLSAI2 division factor (PLLSAI2P)
00887   * @{
00888   */
00889 #define LL_RCC_PLLSAI2P_DIV_7              ((uint32_t)0x00000000)     /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
00890 #define LL_RCC_PLLSAI2P_DIV_17             (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
00891 /**
00892   * @}
00893   */
00894
00895 /** @defgroup RCC_LL_EC_PLLSAI2R  PLLSAI2 division factor (PLLSAI2R)
00896   * @{
00897   */
00898 #define LL_RCC_PLLSAI2R_DIV_2              ((uint32_t)0x00000000)       /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */
00899 #define LL_RCC_PLLSAI2R_DIV_4              (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */
00900 #define LL_RCC_PLLSAI2R_DIV_6              (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */
00901 #define LL_RCC_PLLSAI2R_DIV_8              (RCC_PLLSAI2CFGR_PLLSAI2R)   /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */
00902 /**
00903   * @}
00904   */
00905 #endif /* RCC_PLLSAI2_SUPPORT */
00906
00907 /** @defgroup RCC_LL_EC_MSIRANGESEL  MSI clock range selection
00908   * @{
00909   */
00910 #define LL_RCC_MSIRANGESEL_STANDBY         (uint32_t)0                  /*!< MSI Range is provided by MSISRANGE */
00911 #define LL_RCC_MSIRANGESEL_RUN             (uint32_t)1                  /*!< MSI Range is provided by MSIRANGE */
00912 /**
00913   * @}
00914   */
00915
00916 /** Legacy definitions for compatibility purpose
00917 @cond 0
00918 */
00919 #if defined(DFSDM1_Channel0)
00920 #define LL_RCC_DFSDM_CLKSOURCE_PCLK        LL_RCC_DFSDM1_CLKSOURCE_PCLK
00921 #define LL_RCC_DFSDM_CLKSOURCE_SYSCLK      LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
00922 #define LL_RCC_DFSDM_CLKSOURCE             LL_RCC_DFSDM1_CLKSOURCE
00923 #endif /* DFSDM1_Channel0 */
00924 /**
00925 @endcond
00926   */
00927
00928 /**
00929   * @}
00930   */
00931
00932 /* Exported macro ------------------------------------------------------------*/
00933 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
00934   * @{
00935   */
00936
00937 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
00938   * @{
00939   */
00940
00941 /**
00942   * @brief  Write a value in RCC register
00943   * @param  __REG__ Register to be written
00944   * @param  __VALUE__ Value to be written in the register
00945   * @retval None
00946   */
00947 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
00948
00949 /**
00950   * @brief  Read a value in RCC register
00951   * @param  __REG__ Register to be read
00952   * @retval Register value
00953   */
00954 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
00955 /**
00956   * @}
00957   */
00958
00959 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
00960   * @{
00961   */
00962
00963 /**
00964   * @brief  Helper macro to calculate the PLLCLK frequency on system domain
00965   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00966   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
00967   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
00968   * @param  __PLLM__ This parameter can be one of the following values:
00969   *         @arg @ref LL_RCC_PLLM_DIV_1
00970   *         @arg @ref LL_RCC_PLLM_DIV_2
00971   *         @arg @ref LL_RCC_PLLM_DIV_3
00972   *         @arg @ref LL_RCC_PLLM_DIV_4
00973   *         @arg @ref LL_RCC_PLLM_DIV_5
00974   *         @arg @ref LL_RCC_PLLM_DIV_6
00975   *         @arg @ref LL_RCC_PLLM_DIV_7
00976   *         @arg @ref LL_RCC_PLLM_DIV_8
00977   * @param  __PLLN__ Between 8 and 86
00978   * @param  __PLLR__ This parameter can be one of the following values:
00979   *         @arg @ref LL_RCC_PLLR_DIV_2
00980   *         @arg @ref LL_RCC_PLLR_DIV_4
00981   *         @arg @ref LL_RCC_PLLR_DIV_6
00982   *         @arg @ref LL_RCC_PLLR_DIV_8
00983   * @retval PLL clock frequency (in Hz)
00984   */
00985 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
00986                    ((((__PLLR__) >> RCC_POSITION_PLLR ) + 1 ) * 2))
00987
00988 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
00989 /**
00990   * @brief  Helper macro to calculate the PLLCLK frequency used on SAI domain
00991   * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00992   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
00993   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
00994   * @param  __PLLM__ This parameter can be one of the following values:
00995   *         @arg @ref LL_RCC_PLLM_DIV_1
00996   *         @arg @ref LL_RCC_PLLM_DIV_2
00997   *         @arg @ref LL_RCC_PLLM_DIV_3
00998   *         @arg @ref LL_RCC_PLLM_DIV_4
00999   *         @arg @ref LL_RCC_PLLM_DIV_5
01000   *         @arg @ref LL_RCC_PLLM_DIV_6
01001   *         @arg @ref LL_RCC_PLLM_DIV_7
01002   *         @arg @ref LL_RCC_PLLM_DIV_8
01003   * @param  __PLLN__ Between 8 and 86
01004   * @param  __PLLP__ This parameter can be one of the following values:
01005   *         @arg @ref LL_RCC_PLLP_DIV_2
01006   *         @arg @ref LL_RCC_PLLP_DIV_3
01007   *         @arg @ref LL_RCC_PLLP_DIV_4
01008   *         @arg @ref LL_RCC_PLLP_DIV_5
01009   *         @arg @ref LL_RCC_PLLP_DIV_6
01010   *         @arg @ref LL_RCC_PLLP_DIV_7
01011   *         @arg @ref LL_RCC_PLLP_DIV_8
01012   *         @arg @ref LL_RCC_PLLP_DIV_9
01013   *         @arg @ref LL_RCC_PLLP_DIV_10
01014   *         @arg @ref LL_RCC_PLLP_DIV_11
01015   *         @arg @ref LL_RCC_PLLP_DIV_12
01016   *         @arg @ref LL_RCC_PLLP_DIV_13
01017   *         @arg @ref LL_RCC_PLLP_DIV_14
01018   *         @arg @ref LL_RCC_PLLP_DIV_15
01019   *         @arg @ref LL_RCC_PLLP_DIV_16
01020   *         @arg @ref LL_RCC_PLLP_DIV_17
01021   *         @arg @ref LL_RCC_PLLP_DIV_18
01022   *         @arg @ref LL_RCC_PLLP_DIV_19
01023   *         @arg @ref LL_RCC_PLLP_DIV_20
01024   *         @arg @ref LL_RCC_PLLP_DIV_21
01025   *         @arg @ref LL_RCC_PLLP_DIV_22
01026   *         @arg @ref LL_RCC_PLLP_DIV_23
01027   *         @arg @ref LL_RCC_PLLP_DIV_24
01028   *         @arg @ref LL_RCC_PLLP_DIV_25
01029   *         @arg @ref LL_RCC_PLLP_DIV_26
01030   *         @arg @ref LL_RCC_PLLP_DIV_27
01031   *         @arg @ref LL_RCC_PLLP_DIV_28
01032   *         @arg @ref LL_RCC_PLLP_DIV_29
01033   *         @arg @ref LL_RCC_PLLP_DIV_30
01034   *         @arg @ref LL_RCC_PLLP_DIV_31
01035   * @retval PLL clock frequency (in Hz)
01036   */
01037 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
01038                    ((__PLLP__) >> RCC_POSITION_PLLP))
01039
01040 #else
01041 /**
01042   * @brief  Helper macro to calculate the PLLCLK frequency used on SAI domain
01043   * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01044   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
01045   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01046   * @param  __PLLM__ This parameter can be one of the following values:
01047   *         @arg @ref LL_RCC_PLLM_DIV_1
01048   *         @arg @ref LL_RCC_PLLM_DIV_2
01049   *         @arg @ref LL_RCC_PLLM_DIV_3
01050   *         @arg @ref LL_RCC_PLLM_DIV_4
01051   *         @arg @ref LL_RCC_PLLM_DIV_5
01052   *         @arg @ref LL_RCC_PLLM_DIV_6
01053   *         @arg @ref LL_RCC_PLLM_DIV_7
01054   *         @arg @ref LL_RCC_PLLM_DIV_8
01055   * @param  __PLLN__ Between 8 and 86
01056   * @param  __PLLP__ This parameter can be one of the following values:
01057   *         @arg @ref LL_RCC_PLLP_DIV_7
01058   *         @arg @ref LL_RCC_PLLP_DIV_17
01059   * @retval PLL clock frequency (in Hz)
01060   */
01061 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
01062                    (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7 : 17))
01063
01064 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
01065 /**
01066   * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain
01067   * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01068   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
01069   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01070   * @param  __PLLM__ This parameter can be one of the following values:
01071   *         @arg @ref LL_RCC_PLLM_DIV_1
01072   *         @arg @ref LL_RCC_PLLM_DIV_2
01073   *         @arg @ref LL_RCC_PLLM_DIV_3
01074   *         @arg @ref LL_RCC_PLLM_DIV_4
01075   *         @arg @ref LL_RCC_PLLM_DIV_5
01076   *         @arg @ref LL_RCC_PLLM_DIV_6
01077   *         @arg @ref LL_RCC_PLLM_DIV_7
01078   *         @arg @ref LL_RCC_PLLM_DIV_8
01079   * @param  __PLLN__ Between 8 and 86
01080   * @param  __PLLQ__ This parameter can be one of the following values:
01081   *         @arg @ref LL_RCC_PLLQ_DIV_2
01082   *         @arg @ref LL_RCC_PLLQ_DIV_4
01083   *         @arg @ref LL_RCC_PLLQ_DIV_6
01084   *         @arg @ref LL_RCC_PLLQ_DIV_8
01085   * @retval PLL clock frequency (in Hz)
01086   */
01087 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \
01088                    ((((__PLLQ__) >> RCC_POSITION_PLLQ) + 1) << 1))
01089
01090 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
01091 /**
01092   * @brief  Helper macro to calculate the PLLSAI1 frequency used for SAI domain
01093   * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01094   *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
01095   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01096   * @param  __PLLM__ This parameter can be one of the following values:
01097   *         @arg @ref LL_RCC_PLLM_DIV_1
01098   *         @arg @ref LL_RCC_PLLM_DIV_2
01099   *         @arg @ref LL_RCC_PLLM_DIV_3
01100   *         @arg @ref LL_RCC_PLLM_DIV_4
01101   *         @arg @ref LL_RCC_PLLM_DIV_5
01102   *         @arg @ref LL_RCC_PLLM_DIV_6
01103   *         @arg @ref LL_RCC_PLLM_DIV_7
01104   *         @arg @ref LL_RCC_PLLM_DIV_8
01105   * @param  __PLLSAI1N__ Between 8 and 86
01106   * @param  __PLLSAI1P__ This parameter can be one of the following values:
01107   *         @arg @ref LL_RCC_PLLSAI1P_DIV_2
01108   *         @arg @ref LL_RCC_PLLSAI1P_DIV_3
01109   *         @arg @ref LL_RCC_PLLSAI1P_DIV_4
01110   *         @arg @ref LL_RCC_PLLSAI1P_DIV_5
01111   *         @arg @ref LL_RCC_PLLSAI1P_DIV_6
01112   *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
01113   *         @arg @ref LL_RCC_PLLSAI1P_DIV_8
01114   *         @arg @ref LL_RCC_PLLSAI1P_DIV_9
01115   *         @arg @ref LL_RCC_PLLSAI1P_DIV_10
01116   *         @arg @ref LL_RCC_PLLSAI1P_DIV_11
01117   *         @arg @ref LL_RCC_PLLSAI1P_DIV_12
01118   *         @arg @ref LL_RCC_PLLSAI1P_DIV_13
01119   *         @arg @ref LL_RCC_PLLSAI1P_DIV_14
01120   *         @arg @ref LL_RCC_PLLSAI1P_DIV_15
01121   *         @arg @ref LL_RCC_PLLSAI1P_DIV_16
01122   *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
01123   *         @arg @ref LL_RCC_PLLSAI1P_DIV_18
01124   *         @arg @ref LL_RCC_PLLSAI1P_DIV_19
01125   *         @arg @ref LL_RCC_PLLSAI1P_DIV_20
01126   *         @arg @ref LL_RCC_PLLSAI1P_DIV_21
01127   *         @arg @ref LL_RCC_PLLSAI1P_DIV_22
01128   *         @arg @ref LL_RCC_PLLSAI1P_DIV_23
01129   *         @arg @ref LL_RCC_PLLSAI1P_DIV_24
01130   *         @arg @ref LL_RCC_PLLSAI1P_DIV_25
01131   *         @arg @ref LL_RCC_PLLSAI1P_DIV_26
01132   *         @arg @ref LL_RCC_PLLSAI1P_DIV_27
01133   *         @arg @ref LL_RCC_PLLSAI1P_DIV_28
01134   *         @arg @ref LL_RCC_PLLSAI1P_DIV_29
01135   *         @arg @ref LL_RCC_PLLSAI1P_DIV_30
01136   *         @arg @ref LL_RCC_PLLSAI1P_DIV_31
01137   * @retval PLLSAI1 clock frequency (in Hz)
01138   */
01139 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
01140                    ((__PLLSAI1P__) >> RCC_POSITION_PLLSAI1P))
01141 #else
01142 /**
01143   * @brief  Helper macro to calculate the PLLSAI1 frequency used for SAI domain
01144   * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01145   *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
01146   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01147   * @param  __PLLM__ This parameter can be one of the following values:
01148   *         @arg @ref LL_RCC_PLLM_DIV_1
01149   *         @arg @ref LL_RCC_PLLM_DIV_2
01150   *         @arg @ref LL_RCC_PLLM_DIV_3
01151   *         @arg @ref LL_RCC_PLLM_DIV_4
01152   *         @arg @ref LL_RCC_PLLM_DIV_5
01153   *         @arg @ref LL_RCC_PLLM_DIV_6
01154   *         @arg @ref LL_RCC_PLLM_DIV_7
01155   *         @arg @ref LL_RCC_PLLM_DIV_8
01156   * @param  __PLLSAI1N__ Between 8 and 86
01157   * @param  __PLLSAI1P__ This parameter can be one of the following values:
01158   *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
01159   *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
01160   * @retval PLLSAI1 clock frequency (in Hz)
01161   */
01162 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
01163                    (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7 : 17))
01164 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
01165
01166 /**
01167   * @brief  Helper macro to calculate the PLLSAI1 frequency used on 48M domain
01168   * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01169   *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
01170   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01171   * @param  __PLLM__ This parameter can be one of the following values:
01172   *         @arg @ref LL_RCC_PLLM_DIV_1
01173   *         @arg @ref LL_RCC_PLLM_DIV_2
01174   *         @arg @ref LL_RCC_PLLM_DIV_3
01175   *         @arg @ref LL_RCC_PLLM_DIV_4
01176   *         @arg @ref LL_RCC_PLLM_DIV_5
01177   *         @arg @ref LL_RCC_PLLM_DIV_6
01178   *         @arg @ref LL_RCC_PLLM_DIV_7
01179   *         @arg @ref LL_RCC_PLLM_DIV_8
01180   * @param  __PLLSAI1N__ Between 8 and 86
01181   * @param  __PLLSAI1Q__ This parameter can be one of the following values:
01182   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2
01183   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4
01184   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6
01185   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8
01186   * @retval PLLSAI1 clock frequency (in Hz)
01187   */
01188 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
01189                    ((((__PLLSAI1Q__) >> RCC_POSITION_PLLSAI1Q) + 1) << 1))
01190
01191 /**
01192   * @brief  Helper macro to calculate the PLLSAI1 frequency used on ADC domain
01193   * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01194   *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
01195   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01196   * @param  __PLLM__ This parameter can be one of the following values:
01197   *         @arg @ref LL_RCC_PLLM_DIV_1
01198   *         @arg @ref LL_RCC_PLLM_DIV_2
01199   *         @arg @ref LL_RCC_PLLM_DIV_3
01200   *         @arg @ref LL_RCC_PLLM_DIV_4
01201   *         @arg @ref LL_RCC_PLLM_DIV_5
01202   *         @arg @ref LL_RCC_PLLM_DIV_6
01203   *         @arg @ref LL_RCC_PLLM_DIV_7
01204   *         @arg @ref LL_RCC_PLLM_DIV_8
01205   * @param  __PLLSAI1N__ Between 8 and 86
01206   * @param  __PLLSAI1R__ This parameter can be one of the following values:
01207   *         @arg @ref LL_RCC_PLLSAI1R_DIV_2
01208   *         @arg @ref LL_RCC_PLLSAI1R_DIV_4
01209   *         @arg @ref LL_RCC_PLLSAI1R_DIV_6
01210   *         @arg @ref LL_RCC_PLLSAI1R_DIV_8
01211   * @retval PLLSAI1 clock frequency (in Hz)
01212   */
01213 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \
01214                    ((((__PLLSAI1R__) >> RCC_POSITION_PLLSAI1R ) + 1 ) * 2))
01215
01216 /**
01217   * @brief  Helper macro to calculate the PLLSAI2 frequency used for SAI domain
01218   * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01219   *             @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
01220   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01221   * @param  __PLLM__ This parameter can be one of the following values:
01222   *         @arg @ref LL_RCC_PLLM_DIV_1
01223   *         @arg @ref LL_RCC_PLLM_DIV_2
01224   *         @arg @ref LL_RCC_PLLM_DIV_3
01225   *         @arg @ref LL_RCC_PLLM_DIV_4
01226   *         @arg @ref LL_RCC_PLLM_DIV_5
01227   *         @arg @ref LL_RCC_PLLM_DIV_6
01228   *         @arg @ref LL_RCC_PLLM_DIV_7
01229   *         @arg @ref LL_RCC_PLLM_DIV_8
01230   * @param  __PLLSAI2N__ Between 8 and 86
01231   * @param  __PLLSAI2P__ This parameter can be one of the following values:
01232   *         @arg @ref LL_RCC_PLLSAI2P_DIV_7
01233   *         @arg @ref LL_RCC_PLLSAI2P_DIV_17
01234   * @retval PLLSAI2 clock frequency (in Hz)
01235   */
01236 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI2N__) / \
01237                    (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7 : 17))
01238
01239 /**
01240   * @brief  Helper macro to calculate the PLLSAI2 frequency used on ADC domain
01241   * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01242   *             @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
01243   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01244   * @param  __PLLM__ This parameter can be one of the following values:
01245   *         @arg @ref LL_RCC_PLLM_DIV_1
01246   *         @arg @ref LL_RCC_PLLM_DIV_2
01247   *         @arg @ref LL_RCC_PLLM_DIV_3
01248   *         @arg @ref LL_RCC_PLLM_DIV_4
01249   *         @arg @ref LL_RCC_PLLM_DIV_5
01250   *         @arg @ref LL_RCC_PLLM_DIV_6
01251   *         @arg @ref LL_RCC_PLLM_DIV_7
01252   *         @arg @ref LL_RCC_PLLM_DIV_8
01253   * @param  __PLLSAI2N__ Between 8 and 86
01254   * @param  __PLLSAI2R__ This parameter can be one of the following values:
01255   *         @arg @ref LL_RCC_PLLSAI2R_DIV_2
01256   *         @arg @ref LL_RCC_PLLSAI2R_DIV_4
01257   *         @arg @ref LL_RCC_PLLSAI2R_DIV_6
01258   *         @arg @ref LL_RCC_PLLSAI2R_DIV_8
01259   * @retval PLLSAI2 clock frequency (in Hz)
01260   */
01261 #define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI2N__) / \
01262                    ((((__PLLSAI2R__) >> RCC_POSITION_PLLSAI2R ) + 1 ) * 2))
01263
01264 /**
01265   * @brief  Helper macro to calculate the HCLK frequency
01266   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
01267   * @param  __AHBPRESCALER__ This parameter can be one of the following values:
01268   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01269   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01270   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01271   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01272   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01273   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01274   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01275   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01276   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01277   * @retval HCLK clock frequency (in Hz)
01278   */
01279 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_POSITION_HPRE])
01280
01281 /**
01282   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
01283   * @param  __HCLKFREQ__ HCLK frequency
01284   * @param  __APB1PRESCALER__ This parameter can be one of the following values:
01285   *         @arg @ref LL_RCC_APB1_DIV_1
01286   *         @arg @ref LL_RCC_APB1_DIV_2
01287   *         @arg @ref LL_RCC_APB1_DIV_4
01288   *         @arg @ref LL_RCC_APB1_DIV_8
01289   *         @arg @ref LL_RCC_APB1_DIV_16
01290   * @retval PCLK1 clock frequency (in Hz)
01291   */
01292 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >>  RCC_POSITION_PPRE1])
01293
01294 /**
01295   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
01296   * @param  __HCLKFREQ__ HCLK frequency
01297   * @param  __APB2PRESCALER__ This parameter can be one of the following values:
01298   *         @arg @ref LL_RCC_APB2_DIV_1
01299   *         @arg @ref LL_RCC_APB2_DIV_2
01300   *         @arg @ref LL_RCC_APB2_DIV_4
01301   *         @arg @ref LL_RCC_APB2_DIV_8
01302   *         @arg @ref LL_RCC_APB2_DIV_16
01303   * @retval PCLK2 clock frequency (in Hz)
01304   */
01305 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >>  RCC_POSITION_PPRE2])
01306
01307 /**
01308   * @brief  Helper macro to calculate the MSI frequency (in Hz)
01309   * @note: __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect
01310   * @note: if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
01311   *        __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby
01312   *        else by LL_RCC_MSI_GetRange
01313   *        ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
01314   *              (LL_RCC_MSI_IsEnabledRangeSelect()?
01315   *               LL_RCC_MSI_GetRange():
01316   *               LL_RCC_MSI_GetRangeAfterStandby()))
01317   * @param  __MSISEL__ This parameter can be one of the following values:
01318   *         @arg @ref LL_RCC_MSIRANGESEL_STANDBY
01319   *         @arg @ref LL_RCC_MSIRANGESEL_RUN
01320   * @param  __MSIRANGE__ This parameter can be one of the following values:
01321   *         @arg @ref LL_RCC_MSIRANGE_0
01322   *         @arg @ref LL_RCC_MSIRANGE_1
01323   *         @arg @ref LL_RCC_MSIRANGE_2
01324   *         @arg @ref LL_RCC_MSIRANGE_3
01325   *         @arg @ref LL_RCC_MSIRANGE_4
01326   *         @arg @ref LL_RCC_MSIRANGE_5
01327   *         @arg @ref LL_RCC_MSIRANGE_6
01328   *         @arg @ref LL_RCC_MSIRANGE_7
01329   *         @arg @ref LL_RCC_MSIRANGE_8
01330   *         @arg @ref LL_RCC_MSIRANGE_9
01331   *         @arg @ref LL_RCC_MSIRANGE_10
01332   *         @arg @ref LL_RCC_MSIRANGE_11
01333   *         @arg @ref LL_RCC_MSISRANGE_4
01334   *         @arg @ref LL_RCC_MSISRANGE_5
01335   *         @arg @ref LL_RCC_MSISRANGE_6
01336   *         @arg @ref LL_RCC_MSISRANGE_7
01337   * @retval MSI clock frequency (in Hz)
01338   */
01339 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__)   (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
01340                            (MSIRangeTable[(__MSIRANGE__) >> 8]) : \
01341                            (MSIRangeTable[(__MSIRANGE__) >> 4]))
01342
01343 /**
01344   * @}
01345   */
01346
01347 /**
01348   * @}
01349   */
01350
01351 /* Exported functions --------------------------------------------------------*/
01352 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
01353   * @{
01354   */
01355
01356 /** @defgroup RCC_LL_EF_HSE HSE
01357   * @{
01358   */
01359
01360 /**
01361   * @brief  Enable the Clock Security System.
01362   * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
01363   * @retval None
01364   */
01365 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
01366 {
01367   SET_BIT(RCC->CR, RCC_CR_CSSON);
01368 }
01369
01370 /**
01371   * @brief  Enable HSE external oscillator (HSE Bypass)
01372   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
01373   * @retval None
01374   */
01375 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
01376 {
01377   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
01378 }
01379
01380 /**
01381   * @brief  Disable HSE external oscillator (HSE Bypass)
01382   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
01383   * @retval None
01384   */
01385 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
01386 {
01387   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
01388 }
01389
01390 /**
01391   * @brief  Enable HSE crystal oscillator (HSE ON)
01392   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
01393   * @retval None
01394   */
01395 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
01396 {
01397   SET_BIT(RCC->CR, RCC_CR_HSEON);
01398 }
01399
01400 /**
01401   * @brief  Disable HSE crystal oscillator (HSE ON)
01402   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
01403   * @retval None
01404   */
01405 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
01406 {
01407   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
01408 }
01409
01410 /**
01411   * @brief  Check if HSE oscillator Ready
01412   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
01413   * @retval State of bit (1 or 0).
01414   */
01415 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
01416 {
01417   return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
01418 }
01419
01420 /**
01421   * @}
01422   */
01423
01424 /** @defgroup RCC_LL_EF_HSI HSI
01425   * @{
01426   */
01427
01428 /**
01429   * @brief  Enable HSI even in stop mode
01430   * @note HSI oscillator is forced ON even in Stop mode
01431   * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode
01432   * @retval None
01433   */
01434 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
01435 {
01436   SET_BIT(RCC->CR, RCC_CR_HSIKERON);
01437 }
01438
01439 /**
01440   * @brief  Disable HSI in stop mode
01441   * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode
01442   * @retval None
01443   */
01444 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
01445 {
01446   CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
01447 }
01448
01449 /**
01450   * @brief  Enable HSI oscillator
01451   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
01452   * @retval None
01453   */
01454 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
01455 {
01456   SET_BIT(RCC->CR, RCC_CR_HSION);
01457 }
01458
01459 /**
01460   * @brief  Disable HSI oscillator
01461   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
01462   * @retval None
01463   */
01464 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
01465 {
01466   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
01467 }
01468
01469 /**
01470   * @brief  Check if HSI clock is ready
01471   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
01472   * @retval State of bit (1 or 0).
01473   */
01474 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
01475 {
01476   return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
01477 }
01478
01479 /**
01480   * @brief  Enable HSI Automatic from stop mode
01481   * @rmtoll CR           HSIASFS       LL_RCC_HSI_EnableAutoFromStop
01482   * @retval None
01483   */
01484 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
01485 {
01486   SET_BIT(RCC->CR, RCC_CR_HSIASFS);
01487 }
01488
01489 /**
01490   * @brief  Disable HSI Automatic from stop mode
01491   * @rmtoll CR           HSIASFS       LL_RCC_HSI_DisableAutoFromStop
01492   * @retval None
01493   */
01494 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
01495 {
01496   CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
01497 }
01498 /**
01499   * @brief  Get HSI Calibration value
01500   * @note When HSITRIM is written, HSICAL is updated with the sum of
01501   *       HSITRIM and the factory trim value
01502   * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
01503   * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
01504   */
01505 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
01506 {
01507   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL);
01508 }
01509
01510 /**
01511   * @brief  Set HSI Calibration trimming
01512   * @note user-programmable trimming value that is added to the HSICAL
01513   * @note Default value is 16, which, when added to the HSICAL value,
01514   *       should trim the HSI to 16 MHz +/- 1 %
01515   * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
01516   * @param  Value Between Min_Data = 0 and Max_Data = 31
01517   * @retval None
01518   */
01519 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
01520 {
01521   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM);
01522 }
01523
01524 /**
01525   * @brief  Get HSI Calibration trimming
01526   * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
01527   * @retval Between Min_Data = 0 and Max_Data = 31
01528   */
01529 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
01530 {
01531   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM);
01532 }
01533
01534 /**
01535   * @}
01536   */
01537
01538 #if defined(RCC_HSI48_SUPPORT)
01539 /** @defgroup RCC_LL_EF_HSI48 HSI48
01540   * @{
01541   */
01542
01543 /**
01544   * @brief  Enable HSI48
01545   * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Enable
01546   * @retval None
01547   */
01548 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
01549 {
01550   SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
01551 }
01552
01553 /**
01554   * @brief  Disable HSI48
01555   * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Disable
01556   * @retval None
01557   */
01558 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
01559 {
01560   CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
01561 }
01562
01563 /**
01564   * @brief  Check if HSI48 oscillator Ready
01565   * @rmtoll CRRCR          HSI48RDY      LL_RCC_HSI48_IsReady
01566   * @retval State of bit (1 or 0).
01567   */
01568 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
01569 {
01570   return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
01571 }
01572
01573 /**
01574   * @brief  Get HSI48 Calibration value
01575   * @rmtoll CRRCR          HSI48CAL      LL_RCC_HSI48_GetCalibration
01576   * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
01577   */
01578 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
01579 {
01580   return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_POSITION_HSI48CAL);
01581 }
01582
01583 /**
01584   * @}
01585   */
01586 #endif /* RCC_HSI48_SUPPORT */
01587
01588 /** @defgroup RCC_LL_EF_LSE LSE
01589   * @{
01590   */
01591
01592 /**
01593   * @brief  Enable  Low Speed External (LSE) crystal.
01594   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
01595   * @retval None
01596   */
01597 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
01598 {
01599   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01600 }
01601
01602 /**
01603   * @brief  Disable  Low Speed External (LSE) crystal.
01604   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
01605   * @retval None
01606   */
01607 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
01608 {
01609   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01610 }
01611
01612 /**
01613   * @brief  Enable external clock source (LSE bypass).
01614   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
01615   * @retval None
01616   */
01617 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
01618 {
01619   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01620 }
01621
01622 /**
01623   * @brief  Disable external clock source (LSE bypass).
01624   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
01625   * @retval None
01626   */
01627 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
01628 {
01629   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01630 }
01631
01632 /**
01633   * @brief  Set LSE oscillator drive capability
01634   * @note The oscillator is in Xtal mode when it is not in bypass mode.
01635   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
01636   * @param  LSEDrive This parameter can be one of the following values:
01637   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01638   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01639   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01640   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01641   * @retval None
01642   */
01643 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
01644 {
01645   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
01646 }
01647
01648 /**
01649   * @brief  Get LSE oscillator drive capability
01650   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
01651   * @retval Returned value can be one of the following values:
01652   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01653   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01654   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01655   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01656   */
01657 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
01658 {
01659   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
01660 }
01661
01662 /**
01663   * @brief  Enable Clock security system on LSE.
01664   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_EnableCSS
01665   * @retval None
01666   */
01667 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
01668 {
01669   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
01670 }
01671
01672 /**
01673   * @brief  Disable Clock security system on LSE.
01674   * @note Clock security system can be disabled only after a LSE
01675   *       failure detection. In that case it MUST be disabled by software.
01676   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_DisableCSS
01677   * @retval None
01678   */
01679 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
01680 {
01681   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
01682 }
01683
01684 /**
01685   * @brief  Check if LSE oscillator Ready
01686   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
01687   * @retval State of bit (1 or 0).
01688   */
01689 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
01690 {
01691   return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
01692 }
01693
01694 /**
01695   * @brief  Check if CSS on LSE failure Detection
01696   * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsCSSDetected
01697   * @retval State of bit (1 or 0).
01698   */
01699 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
01700 {
01701   return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
01702 }
01703
01704 /**
01705   * @}
01706   */
01707
01708 /** @defgroup RCC_LL_EF_LSI LSI
01709   * @{
01710   */
01711
01712 /**
01713   * @brief  Enable LSI Oscillator
01714   * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
01715   * @retval None
01716   */
01717 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
01718 {
01719   SET_BIT(RCC->CSR, RCC_CSR_LSION);
01720 }
01721
01722 /**
01723   * @brief  Disable LSI Oscillator
01724   * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
01725   * @retval None
01726   */
01727 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
01728 {
01729   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
01730 }
01731
01732 /**
01733   * @brief  Check if LSI is Ready
01734   * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
01735   * @retval State of bit (1 or 0).
01736   */
01737 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
01738 {
01739   return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
01740 }
01741
01742 /**
01743   * @}
01744   */
01745
01746 /** @defgroup RCC_LL_EF_MSI MSI
01747   * @{
01748   */
01749
01750 /**
01751   * @brief  Enable MSI oscillator
01752   * @rmtoll CR           MSION         LL_RCC_MSI_Enable
01753   * @retval None
01754   */
01755 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
01756 {
01757   SET_BIT(RCC->CR, RCC_CR_MSION);
01758 }
01759
01760 /**
01761   * @brief  Disable MSI oscillator
01762   * @rmtoll CR           MSION         LL_RCC_MSI_Disable
01763   * @retval None
01764   */
01765 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
01766 {
01767   CLEAR_BIT(RCC->CR, RCC_CR_MSION);
01768 }
01769
01770 /**
01771   * @brief  Check if MSI oscillator Ready
01772   * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady
01773   * @retval State of bit (1 or 0).
01774   */
01775 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
01776 {
01777   return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
01778 }
01779
01780 /**
01781   * @brief  Enable MSI PLL-mode (Hardware auto calibration with LSE)
01782   * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
01783   *       and ready (LSERDY set by hardware)
01784   * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
01785   *       ready
01786   * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_EnablePLLMode
01787   * @retval None
01788   */
01789 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
01790 {
01791   SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
01792 }
01793
01794 /**
01795   * @brief  Disable MSI-PLL mode
01796   * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
01797   *       the Clock Security System on LSE detects a LSE failure
01798   * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_DisablePLLMode
01799   * @retval None
01800   */
01801 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
01802 {
01803   CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
01804 }
01805
01806 /**
01807   * @brief  Enable MSI clock range selection with MSIRANGE register
01808   * @note Write 0 has no effect. After a standby or a reset
01809   *       MSIRGSEL is at 0 and the MSI range value is provided by
01810   *       MSISRANGE
01811   * @rmtoll CR           MSIRGSEL      LL_RCC_MSI_EnableRangeSelection
01812   * @retval None
01813   */
01814 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
01815 {
01816   SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
01817 }
01818
01819 /**
01820   * @brief  Check if MSI clock range is selected with MSIRANGE register
01821   * @rmtoll CR           MSIRGSEL      LL_RCC_MSI_IsEnabledRangeSelect
01822   * @retval State of bit (1 or 0).
01823   */
01824 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
01825 {
01826   return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
01827 }
01828
01829 /**
01830   * @brief  Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
01831   * @rmtoll CR           MSIRANGE      LL_RCC_MSI_SetRange
01832   * @param  Range This parameter can be one of the following values:
01833   *         @arg @ref LL_RCC_MSIRANGE_0
01834   *         @arg @ref LL_RCC_MSIRANGE_1
01835   *         @arg @ref LL_RCC_MSIRANGE_2
01836   *         @arg @ref LL_RCC_MSIRANGE_3
01837   *         @arg @ref LL_RCC_MSIRANGE_4
01838   *         @arg @ref LL_RCC_MSIRANGE_5
01839   *         @arg @ref LL_RCC_MSIRANGE_6
01840   *         @arg @ref LL_RCC_MSIRANGE_7
01841   *         @arg @ref LL_RCC_MSIRANGE_8
01842   *         @arg @ref LL_RCC_MSIRANGE_9
01843   *         @arg @ref LL_RCC_MSIRANGE_10
01844   *         @arg @ref LL_RCC_MSIRANGE_11
01845   * @retval None
01846   */
01847 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
01848 {
01849   MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
01850 }
01851
01852 /**
01853   * @brief  Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
01854   * @rmtoll CR           MSIRANGE      LL_RCC_MSI_GetRange
01855   * @retval Returned value can be one of the following values:
01856   *         @arg @ref LL_RCC_MSIRANGE_0
01857   *         @arg @ref LL_RCC_MSIRANGE_1
01858   *         @arg @ref LL_RCC_MSIRANGE_2
01859   *         @arg @ref LL_RCC_MSIRANGE_3
01860   *         @arg @ref LL_RCC_MSIRANGE_4
01861   *         @arg @ref LL_RCC_MSIRANGE_5
01862   *         @arg @ref LL_RCC_MSIRANGE_6
01863   *         @arg @ref LL_RCC_MSIRANGE_7
01864   *         @arg @ref LL_RCC_MSIRANGE_8
01865   *         @arg @ref LL_RCC_MSIRANGE_9
01866   *         @arg @ref LL_RCC_MSIRANGE_10
01867   *         @arg @ref LL_RCC_MSIRANGE_11
01868   */
01869 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
01870 {
01871   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
01872 }
01873
01874 /**
01875   * @brief  Configure MSI range used after standby
01876   * @rmtoll CSR          MSISRANGE     LL_RCC_MSI_SetRangeAfterStandby
01877   * @param  Range This parameter can be one of the following values:
01878   *         @arg @ref LL_RCC_MSISRANGE_4
01879   *         @arg @ref LL_RCC_MSISRANGE_5
01880   *         @arg @ref LL_RCC_MSISRANGE_6
01881   *         @arg @ref LL_RCC_MSISRANGE_7
01882   * @retval None
01883   */
01884 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
01885 {
01886   MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
01887 }
01888
01889 /**
01890   * @brief  Get MSI range used after standby
01891   * @rmtoll CSR          MSISRANGE     LL_RCC_MSI_GetRangeAfterStandby
01892   * @retval Returned value can be one of the following values:
01893   *         @arg @ref LL_RCC_MSISRANGE_4
01894   *         @arg @ref LL_RCC_MSISRANGE_5
01895   *         @arg @ref LL_RCC_MSISRANGE_6
01896   *         @arg @ref LL_RCC_MSISRANGE_7
01897   */
01898 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
01899 {
01900   return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
01901 }
01902
01903 /**
01904   * @brief  Get MSI Calibration value
01905   * @note When MSITRIM is written, MSICAL is updated with the sum of
01906   *       MSITRIM and the factory trim value
01907   * @rmtoll ICSCR        MSICAL        LL_RCC_MSI_GetCalibration
01908   * @retval Between Min_Data = 0 and Max_Data = 255
01909   */
01910 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
01911 {
01912   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL);
01913 }
01914
01915 /**
01916   * @brief  Set MSI Calibration trimming
01917   * @note user-programmable trimming value that is added to the MSICAL
01918   * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming
01919   * @param  Value Between Min_Data = 0 and Max_Data = 255
01920   * @retval None
01921   */
01922 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
01923 {
01924   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM);
01925 }
01926
01927 /**
01928   * @brief  Get MSI Calibration trimming
01929   * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_GetCalibTrimming
01930   * @retval Between 0 and 255
01931   */
01932 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
01933 {
01934   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM);
01935 }
01936
01937 /**
01938   * @}
01939   */
01940
01941 /** @defgroup RCC_LL_EF_LSCO LSCO
01942   * @{
01943   */
01944
01945 /**
01946   * @brief  Enable Low speed clock
01947   * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Enable
01948   * @retval None
01949   */
01950 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
01951 {
01952   SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01953 }
01954
01955 /**
01956   * @brief  Disable Low speed clock
01957   * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Disable
01958   * @retval None
01959   */
01960 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
01961 {
01962   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01963 }
01964
01965 /**
01966   * @brief  Configure Low speed clock selection
01967   * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_SetSource
01968   * @param  Source This parameter can be one of the following values:
01969   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
01970   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
01971   * @retval None
01972   */
01973 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
01974 {
01975   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
01976 }
01977
01978 /**
01979   * @brief  Get Low speed clock selection
01980   * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_GetSource
01981   * @retval Returned value can be one of the following values:
01982   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
01983   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
01984   */
01985 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
01986 {
01987   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
01988 }
01989
01990 /**
01991   * @}
01992   */
01993
01994 /** @defgroup RCC_LL_EF_System System
01995   * @{
01996   */
01997
01998 /**
01999   * @brief  Configure the system clock source
02000   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
02001   * @param  Source This parameter can be one of the following values:
02002   *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
02003   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
02004   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
02005   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
02006   * @retval None
02007   */
02008 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
02009 {
02010   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
02011 }
02012
02013 /**
02014   * @brief  Get the system clock source
02015   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
02016   * @retval Returned value can be one of the following values:
02017   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
02018   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
02019   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
02020   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
02021   */
02022 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
02023 {
02024   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
02025 }
02026
02027 /**
02028   * @brief  Set AHB prescaler
02029   * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
02030   * @param  Prescaler This parameter can be one of the following values:
02031   *         @arg @ref LL_RCC_SYSCLK_DIV_1
02032   *         @arg @ref LL_RCC_SYSCLK_DIV_2
02033   *         @arg @ref LL_RCC_SYSCLK_DIV_4
02034   *         @arg @ref LL_RCC_SYSCLK_DIV_8
02035   *         @arg @ref LL_RCC_SYSCLK_DIV_16
02036   *         @arg @ref LL_RCC_SYSCLK_DIV_64
02037   *         @arg @ref LL_RCC_SYSCLK_DIV_128
02038   *         @arg @ref LL_RCC_SYSCLK_DIV_256
02039   *         @arg @ref LL_RCC_SYSCLK_DIV_512
02040   * @retval None
02041   */
02042 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
02043 {
02044   MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
02045 }
02046
02047 /**
02048   * @brief  Set APB1 prescaler
02049   * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
02050   * @param  Prescaler This parameter can be one of the following values:
02051   *         @arg @ref LL_RCC_APB1_DIV_1
02052   *         @arg @ref LL_RCC_APB1_DIV_2
02053   *         @arg @ref LL_RCC_APB1_DIV_4
02054   *         @arg @ref LL_RCC_APB1_DIV_8
02055   *         @arg @ref LL_RCC_APB1_DIV_16
02056   * @retval None
02057   */
02058 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
02059 {
02060   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
02061 }
02062
02063 /**
02064   * @brief  Set APB2 prescaler
02065   * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
02066   * @param  Prescaler This parameter can be one of the following values:
02067   *         @arg @ref LL_RCC_APB2_DIV_1
02068   *         @arg @ref LL_RCC_APB2_DIV_2
02069   *         @arg @ref LL_RCC_APB2_DIV_4
02070   *         @arg @ref LL_RCC_APB2_DIV_8
02071   *         @arg @ref LL_RCC_APB2_DIV_16
02072   * @retval None
02073   */
02074 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
02075 {
02076   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
02077 }
02078
02079 /**
02080   * @brief  Get AHB prescaler
02081   * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
02082   * @retval Returned value can be one of the following values:
02083   *         @arg @ref LL_RCC_SYSCLK_DIV_1
02084   *         @arg @ref LL_RCC_SYSCLK_DIV_2
02085   *         @arg @ref LL_RCC_SYSCLK_DIV_4
02086   *         @arg @ref LL_RCC_SYSCLK_DIV_8
02087   *         @arg @ref LL_RCC_SYSCLK_DIV_16
02088   *         @arg @ref LL_RCC_SYSCLK_DIV_64
02089   *         @arg @ref LL_RCC_SYSCLK_DIV_128
02090   *         @arg @ref LL_RCC_SYSCLK_DIV_256
02091   *         @arg @ref LL_RCC_SYSCLK_DIV_512
02092   */
02093 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
02094 {
02095   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
02096 }
02097
02098 /**
02099   * @brief  Get APB1 prescaler
02100   * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
02101   * @retval Returned value can be one of the following values:
02102   *         @arg @ref LL_RCC_APB1_DIV_1
02103   *         @arg @ref LL_RCC_APB1_DIV_2
02104   *         @arg @ref LL_RCC_APB1_DIV_4
02105   *         @arg @ref LL_RCC_APB1_DIV_8
02106   *         @arg @ref LL_RCC_APB1_DIV_16
02107   */
02108 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
02109 {
02110   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
02111 }
02112
02113 /**
02114   * @brief  Get APB2 prescaler
02115   * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
02116   * @retval Returned value can be one of the following values:
02117   *         @arg @ref LL_RCC_APB2_DIV_1
02118   *         @arg @ref LL_RCC_APB2_DIV_2
02119   *         @arg @ref LL_RCC_APB2_DIV_4
02120   *         @arg @ref LL_RCC_APB2_DIV_8
02121   *         @arg @ref LL_RCC_APB2_DIV_16
02122   */
02123 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
02124 {
02125   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
02126 }
02127
02128
02129 /**
02130   * @brief  Set Clock After Wake-Up From Stop mode
02131   * @rmtoll CFGR         STOPWUCK      LL_RCC_SetClkAfterWakeFromStop
02132   * @param  Clock This parameter can be one of the following values:
02133   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
02134   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
02135   * @retval None
02136   */
02137 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
02138 {
02139   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
02140 }
02141
02142 /**
02143   * @brief  Get Clock After Wake-Up From Stop mode
02144   * @rmtoll CFGR         STOPWUCK      LL_RCC_GetClkAfterWakeFromStop
02145   * @retval Returned value can be one of the following values:
02146   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
02147   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
02148   */
02149 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
02150 {
02151   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
02152 }
02153
02154 /**
02155   * @}
02156   */
02157
02158 /** @defgroup RCC_LL_EF_MCO MCO
02159   * @{
02160   */
02161
02162 /**
02163   * @brief  Configure MCOx
02164   * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
02165   *         CFGR         MCOPRE        LL_RCC_ConfigMCO
02166   * @param  MCOxSource This parameter can be one of the following values:
02167   *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
02168   *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
02169   *         @arg @ref LL_RCC_MCO1SOURCE_MSI
02170   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
02171   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
02172   *         @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
02173   *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
02174   *         @arg @ref LL_RCC_MCO1SOURCE_LSI
02175   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
02176   *
02177   *         (*) value not defined in all devices.
02178   * @param  MCOxPrescaler This parameter can be one of the following values:
02179   *         @arg @ref LL_RCC_MCO1_DIV_1
02180   *         @arg @ref LL_RCC_MCO1_DIV_2
02181   *         @arg @ref LL_RCC_MCO1_DIV_4
02182   *         @arg @ref LL_RCC_MCO1_DIV_8
02183   *         @arg @ref LL_RCC_MCO1_DIV_16
02184   * @retval None
02185   */
02186 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
02187 {
02188   MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
02189 }
02190
02191 /**
02192   * @}
02193   */
02194
02195 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
02196   * @{
02197   */
02198
02199 /**
02200   * @brief  Configure USARTx clock source
02201   * @rmtoll CCIPR        USARTxSEL     LL_RCC_SetUSARTClockSource
02202   * @param  USARTxSource This parameter can be one of the following values:
02203   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
02204   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
02205   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
02206   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
02207   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
02208   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
02209   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
02210   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
02211   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
02212   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
02213   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
02214   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
02215   *
02216   *         (*) value not defined in all devices.
02217   * @retval None
02218   */
02219 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
02220 {
02221   MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
02222 }
02223
02224 #if defined(UART4) || defined(UART5)
02225 /**
02226   * @brief  Configure UARTx clock source
02227   * @rmtoll CCIPR        UARTxSEL      LL_RCC_SetUARTClockSource
02228   * @param  UARTxSource This parameter can be one of the following values:
02229   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
02230   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
02231   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
02232   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
02233   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
02234   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
02235   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
02236   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
02237   * @retval None
02238   */
02239 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
02240 {
02241   MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));
02242 }
02243 #endif /* UART4 || UART5 */
02244
02245 /**
02246   * @brief  Configure LPUART1x clock source
02247   * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource
02248   * @param  LPUARTxSource This parameter can be one of the following values:
02249   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
02250   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
02251   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
02252   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
02253   * @retval None
02254   */
02255 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
02256 {
02257   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
02258 }
02259
02260 /**
02261   * @brief  Configure I2Cx clock source
02262   * @rmtoll CCIPR        I2CxSEL       LL_RCC_SetI2CClockSource
02263   * @param  I2CxSource This parameter can be one of the following values:
02264   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
02265   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
02266   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
02267   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
02268   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
02269   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
02270   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
02271   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
02272   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
02273   *
02274   *         (*) value not defined in all devices.
02275   * @retval None
02276   */
02277 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
02278 {
02279   MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000), ((I2CxSource << 4) & 0x000FF000));
02280 }
02281
02282 /**
02283   * @brief  Configure LPTIMx clock source
02284   * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_SetLPTIMClockSource
02285   * @param  LPTIMxSource This parameter can be one of the following values:
02286   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
02287   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
02288   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
02289   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
02290   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
02291   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
02292   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
02293   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
02294   * @retval None
02295   */
02296 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
02297 {
02298   MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
02299 }
02300
02301 /**
02302   * @brief  Configure SAIx clock source
02303   * @rmtoll CCIPR        SAIxSEL       LL_RCC_SetSAIClockSource
02304   * @param  SAIxSource This parameter can be one of the following values:
02305   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
02306   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
02307   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
02308   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
02309   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
02310   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
02311   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
02312   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
02313   *
02314   *         (*) value not defined in all devices.
02315   * @retval None
02316   */
02317 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
02318 {
02319   MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16));
02320 }
02321
02322 /**
02323   * @brief  Configure SDMMC1 clock source
02324   * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetSDMMCClockSource
02325   * @param  SDMMCxSource This parameter can be one of the following values:
02326   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE
02327   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
02328   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
02329   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
02330   * @retval None
02331   */
02332 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
02333 {
02334   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
02335 }
02336
02337 /**
02338   * @brief  Configure RNG clock source
02339   * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetRNGClockSource
02340   * @param  RNGxSource This parameter can be one of the following values:
02341   *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
02342   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
02343   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
02344   *         @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
02345   * @retval None
02346   */
02347 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
02348 {
02349   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
02350 }
02351
02352 #if defined(USB_OTG_FS) || defined(USB)
02353 /**
02354   * @brief  Configure USB clock source
02355   * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetUSBClockSource
02356   * @param  USBxSource This parameter can be one of the following values:
02357   *         @arg @ref LL_RCC_USB_CLKSOURCE_NONE
02358   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
02359   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
02360   *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI
02361   * @retval None
02362   */
02363 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
02364 {
02365   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
02366 }
02367 #endif /* USB_OTG_FS || USB */
02368
02369 /**
02370   * @brief  Configure ADC clock source
02371   * @rmtoll CCIPR        ADCSEL        LL_RCC_SetADCClockSource
02372   * @param  ADCxSource This parameter can be one of the following values:
02373   *         @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
02374   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
02375   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
02376   *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
02377   *
02378   *         (*) value not defined in all devices.
02379   * @retval None
02380   */
02381 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
02382 {
02383   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
02384 }
02385
02386 /**
02387   * @brief  Configure SWPMI clock source
02388   * @rmtoll CCIPR        SWPMI1SEL     LL_RCC_SetSWPMIClockSource
02389   * @param  SWPMIxSource This parameter can be one of the following values:
02390   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK
02391   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
02392   * @retval None
02393   */
02394 __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
02395 {
02396   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
02397 }
02398
02399 #if defined(DFSDM1_Channel0)
02400 /**
02401   * @brief  Configure DFSDM clock source
02402   * @rmtoll CCIPR        DFSDM1SEL     LL_RCC_SetDFSDMClockSource
02403   * @param  DFSDMxSource This parameter can be one of the following values:
02404   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK
02405   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
02406   * @retval None
02407   */
02408 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
02409 {
02410   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
02411 }
02412 #endif /* DFSDM1_Channel0 */
02413
02414 /**
02415   * @brief  Get USARTx clock source
02416   * @rmtoll CCIPR        USARTxSEL     LL_RCC_GetUSARTClockSource
02417   * @param  USARTx This parameter can be one of the following values:
02418   *         @arg @ref LL_RCC_USART1_CLKSOURCE
02419   *         @arg @ref LL_RCC_USART2_CLKSOURCE
02420   *         @arg @ref LL_RCC_USART3_CLKSOURCE (*)
02421   *
02422   *         (*) value not defined in all devices.
02423   * @retval Returned value can be one of the following values:
02424   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
02425   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
02426   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
02427   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
02428   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
02429   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
02430   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
02431   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
02432   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
02433   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
02434   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
02435   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
02436   *
02437   *         (*) value not defined in all devices.
02438   */
02439 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
02440 {
02441   return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16));
02442 }
02443
02444 #if defined(UART4) || defined(UART5)
02445 /**
02446   * @brief  Get UARTx clock source
02447   * @rmtoll CCIPR        UARTxSEL      LL_RCC_GetUARTClockSource
02448   * @param  UARTx This parameter can be one of the following values:
02449   *         @arg @ref LL_RCC_UART4_CLKSOURCE
02450   *         @arg @ref LL_RCC_UART5_CLKSOURCE
02451   * @retval Returned value can be one of the following values:
02452   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
02453   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
02454   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
02455   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
02456   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
02457   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
02458   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
02459   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
02460   */
02461 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
02462 {
02463   return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16));
02464 }
02465 #endif /* UART4 || UART5 */
02466
02467 /**
02468   * @brief  Get LPUARTx clock source
02469   * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource
02470   * @param  LPUARTx This parameter can be one of the following values:
02471   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
02472   * @retval Returned value can be one of the following values:
02473   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
02474   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
02475   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
02476   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
02477   */
02478 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
02479 {
02480   return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
02481 }
02482
02483 /**
02484   * @brief  Get I2Cx clock source
02485   * @rmtoll CCIPR        I2CxSEL       LL_RCC_GetI2CClockSource
02486   * @param  I2Cx This parameter can be one of the following values:
02487   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
02488   *         @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
02489   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
02490   *
02491   *         (*) value not defined in all devices.
02492   * @retval Returned value can be one of the following values:
02493   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
02494   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
02495   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
02496   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
02497   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
02498   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
02499   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
02500   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
02501   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
02502   *
02503   *         (*) value not defined in all devices.
02504  */
02505 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
02506 {
02507   return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) | (I2Cx << 4));
02508 }
02509
02510 /**
02511   * @brief  Get LPTIMx clock source
02512   * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_GetLPTIMClockSource
02513   * @param  LPTIMx This parameter can be one of the following values:
02514   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
02515   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
02516   * @retval Returned value can be one of the following values:
02517   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
02518   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
02519   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
02520   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
02521   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
02522   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
02523   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
02524   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
02525   */
02526 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
02527 {
02528   return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16 | LPTIMx);
02529 }
02530
02531 /**
02532   * @brief  Get SAIx clock source
02533   * @rmtoll CCIPR        SAIxSEL       LL_RCC_GetSAIClockSource
02534   * @param  SAIx This parameter can be one of the following values:
02535   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
02536   *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
02537   *
02538   *         (*) value not defined in all devices.
02539   * @retval Returned value can be one of the following values:
02540   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
02541   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
02542   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
02543   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
02544   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
02545   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
02546   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
02547   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
02548   *
02549   *         (*) value not defined in all devices.
02550   */
02551 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
02552 {
02553   return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16 | SAIx);
02554 }
02555
02556 /**
02557   * @brief  Get SDMMCx clock source
02558   * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetSDMMCClockSource
02559   * @param  SDMMCx This parameter can be one of the following values:
02560   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
02561   * @retval Returned value can be one of the following values:
02562   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE
02563   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
02564   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
02565   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
02566   */
02567 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
02568 {
02569   return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
02570 }
02571
02572 /**
02573   * @brief  Get RNGx clock source
02574   * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetRNGClockSource
02575   * @param  RNGx This parameter can be one of the following values:
02576   *         @arg @ref LL_RCC_RNG_CLKSOURCE
02577   * @retval Returned value can be one of the following values:
02578   *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
02579   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
02580   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
02581   *         @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
02582   */
02583 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
02584 {
02585   return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
02586 }
02587
02588 #if defined(USB_OTG_FS) || defined(USB)
02589 /**
02590   * @brief  Get USBx clock source
02591   * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetUSBClockSource
02592   * @param  USBx This parameter can be one of the following values:
02593   *         @arg @ref LL_RCC_USB_CLKSOURCE
02594   * @retval Returned value can be one of the following values:
02595   *         @arg @ref LL_RCC_USB_CLKSOURCE_NONE
02596   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
02597   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
02598   *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI
02599   */
02600 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
02601 {
02602   return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
02603 }
02604 #endif /* USB_OTG_FS || USB */
02605
02606 /**
02607   * @brief  Get ADCx clock source
02608   * @rmtoll CCIPR        ADCSEL        LL_RCC_GetADCClockSource
02609   * @param  ADCx This parameter can be one of the following values:
02610   *         @arg @ref LL_RCC_ADC_CLKSOURCE
02611   * @retval Returned value can be one of the following values:
02612   *         @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
02613   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
02614   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
02615   *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
02616   *
02617   *         (*) value not defined in all devices.
02618   */
02619 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
02620 {
02621   return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
02622 }
02623
02624 /**
02625   * @brief  Get SWPMIx clock source
02626   * @rmtoll CCIPR        SWPMI1SEL     LL_RCC_GetSWPMIClockSource
02627   * @param  SPWMIx This parameter can be one of the following values:
02628   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE
02629   * @retval Returned value can be one of the following values:
02630   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK
02631   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
02632   */
02633 __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
02634 {
02635   return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
02636 }
02637
02638 #if defined(DFSDM1_Channel0)
02639 /**
02640   * @brief  Get DFSDMx clock source
02641   * @rmtoll CCIPR        DFSDM1SEL     LL_RCC_GetDFSDMClockSource
02642   * @param  DFSDMx This parameter can be one of the following values:
02643   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
02644   * @retval Returned value can be one of the following values:
02645   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK
02646   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
02647   */
02648 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
02649 {
02650   return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
02651 }
02652 #endif /* DFSDM1_Channel0 */
02653
02654 /**
02655   * @}
02656   */
02657
02658 /** @defgroup RCC_LL_EF_RTC RTC
02659   * @{
02660   */
02661
02662 /**
02663   * @brief  Set RTC Clock Source
02664   * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
02665   *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
02666   *       set). The BDRST bit can be used to reset them.
02667   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
02668   * @param  Source This parameter can be one of the following values:
02669   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
02670   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
02671   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
02672   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
02673   * @retval None
02674   */
02675 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
02676 {
02677   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
02678 }
02679
02680 /**
02681   * @brief  Get RTC Clock Source
02682   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
02683   * @retval Returned value can be one of the following values:
02684   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
02685   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
02686   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
02687   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
02688   */
02689 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
02690 {
02691   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
02692 }
02693
02694 /**
02695   * @brief  Enable RTC
02696   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
02697   * @retval None
02698   */
02699 __STATIC_INLINE void LL_RCC_EnableRTC(void)
02700 {
02701   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02702 }
02703
02704 /**
02705   * @brief  Disable RTC
02706   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
02707   * @retval None
02708   */
02709 __STATIC_INLINE void LL_RCC_DisableRTC(void)
02710 {
02711   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02712 }
02713
02714 /**
02715   * @brief  Check if RTC has been enabled or not
02716   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
02717   * @retval State of bit (1 or 0).
02718   */
02719 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
02720 {
02721   return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
02722 }
02723
02724 /**
02725   * @brief  Force the Backup domain reset
02726   * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
02727   * @retval None
02728   */
02729 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
02730 {
02731   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02732 }
02733
02734 /**
02735   * @brief  Release the Backup domain reset
02736   * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
02737   * @retval None
02738   */
02739 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
02740 {
02741   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02742 }
02743
02744 /**
02745   * @}
02746   */
02747
02748 /** @defgroup RCC_LL_EF_PLL PLL
02749   * @{
02750   */
02751
02752 /**
02753   * @brief  Enable PLL
02754   * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
02755   * @retval None
02756   */
02757 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
02758 {
02759   SET_BIT(RCC->CR, RCC_CR_PLLON);
02760 }
02761
02762 /**
02763   * @brief  Disable PLL
02764   * @note Cannot be disabled if the PLL clock is used as the system clock
02765   * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
02766   * @retval None
02767   */
02768 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
02769 {
02770   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
02771 }
02772
02773 /**
02774   * @brief  Check if PLL Ready
02775   * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
02776   * @retval State of bit (1 or 0).
02777   */
02778 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
02779 {
02780   return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
02781 }
02782
02783 /**
02784   * @brief  Configure PLL used for SYSCLK Domain
02785   * @note PLL Source and PLLM Divider can be written only when PLL,
02786   *       PLLSAI1 and PLLSAI2 (*) are disabled
02787   * @note PLLN/PLLR can be written only when PLL is disabled
02788   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
02789   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
02790   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
02791   *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS
02792   * @param  Source This parameter can be one of the following values:
02793   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02794   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02795   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02796   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02797   * @param  PLLM This parameter can be one of the following values:
02798   *         @arg @ref LL_RCC_PLLM_DIV_1
02799   *         @arg @ref LL_RCC_PLLM_DIV_2
02800   *         @arg @ref LL_RCC_PLLM_DIV_3
02801   *         @arg @ref LL_RCC_PLLM_DIV_4
02802   *         @arg @ref LL_RCC_PLLM_DIV_5
02803   *         @arg @ref LL_RCC_PLLM_DIV_6
02804   *         @arg @ref LL_RCC_PLLM_DIV_7
02805   *         @arg @ref LL_RCC_PLLM_DIV_8
02806   * @param  PLLN Between 8 and 86
02807   * @param  PLLR This parameter can be one of the following values:
02808   *         @arg @ref LL_RCC_PLLR_DIV_2
02809   *         @arg @ref LL_RCC_PLLR_DIV_4
02810   *         @arg @ref LL_RCC_PLLR_DIV_6
02811   *         @arg @ref LL_RCC_PLLR_DIV_8
02812   * @retval None
02813   */
02814 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
02815 {
02816   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
02817              Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLR);
02818 }
02819
02820 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
02821 /**
02822   * @brief  Configure PLL used for SAI domain clock
02823   * @note PLL Source and PLLM Divider can be written only when PLL,
02824   *       PLLSAI1 and PLLSAI2 (*) are disabled
02825   * @note PLLN/PLLP can be written only when PLL is disabled
02826   * @note This  can be selected for SAI1 or SAI2 (*)
02827   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\n
02828   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\n
02829   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\n
02830   *         PLLCFGR      PLLPDIV       LL_RCC_PLL_ConfigDomain_SAI
02831   * @param  Source This parameter can be one of the following values:
02832   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02833   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02834   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02835   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02836   * @param  PLLM This parameter can be one of the following values:
02837   *         @arg @ref LL_RCC_PLLM_DIV_1
02838   *         @arg @ref LL_RCC_PLLM_DIV_2
02839   *         @arg @ref LL_RCC_PLLM_DIV_3
02840   *         @arg @ref LL_RCC_PLLM_DIV_4
02841   *         @arg @ref LL_RCC_PLLM_DIV_5
02842   *         @arg @ref LL_RCC_PLLM_DIV_6
02843   *         @arg @ref LL_RCC_PLLM_DIV_7
02844   *         @arg @ref LL_RCC_PLLM_DIV_8
02845   * @param  PLLN Between 8 and 86
02846   * @param  PLLP This parameter can be one of the following values:
02847   *         @arg @ref LL_RCC_PLLP_DIV_2
02848   *         @arg @ref LL_RCC_PLLP_DIV_3
02849   *         @arg @ref LL_RCC_PLLP_DIV_4
02850   *         @arg @ref LL_RCC_PLLP_DIV_5
02851   *         @arg @ref LL_RCC_PLLP_DIV_6
02852   *         @arg @ref LL_RCC_PLLP_DIV_7
02853   *         @arg @ref LL_RCC_PLLP_DIV_8
02854   *         @arg @ref LL_RCC_PLLP_DIV_9
02855   *         @arg @ref LL_RCC_PLLP_DIV_10
02856   *         @arg @ref LL_RCC_PLLP_DIV_11
02857   *         @arg @ref LL_RCC_PLLP_DIV_12
02858   *         @arg @ref LL_RCC_PLLP_DIV_13
02859   *         @arg @ref LL_RCC_PLLP_DIV_14
02860   *         @arg @ref LL_RCC_PLLP_DIV_15
02861   *         @arg @ref LL_RCC_PLLP_DIV_16
02862   *         @arg @ref LL_RCC_PLLP_DIV_17
02863   *         @arg @ref LL_RCC_PLLP_DIV_18
02864   *         @arg @ref LL_RCC_PLLP_DIV_19
02865   *         @arg @ref LL_RCC_PLLP_DIV_20
02866   *         @arg @ref LL_RCC_PLLP_DIV_21
02867   *         @arg @ref LL_RCC_PLLP_DIV_22
02868   *         @arg @ref LL_RCC_PLLP_DIV_23
02869   *         @arg @ref LL_RCC_PLLP_DIV_24
02870   *         @arg @ref LL_RCC_PLLP_DIV_25
02871   *         @arg @ref LL_RCC_PLLP_DIV_26
02872   *         @arg @ref LL_RCC_PLLP_DIV_27
02873   *         @arg @ref LL_RCC_PLLP_DIV_28
02874   *         @arg @ref LL_RCC_PLLP_DIV_29
02875   *         @arg @ref LL_RCC_PLLP_DIV_30
02876   *         @arg @ref LL_RCC_PLLP_DIV_31
02877   * @retval None
02878   */
02879 #else
02880 /**
02881   * @brief  Configure PLL used for SAI domain clock
02882   * @note   PLL Source and PLLM Divider can be written only when PLL,
02883   *         PLLSAI1 and PLLSAI2 (*) are disabled
02884   * @note   PLLN/PLLP can be written only when PLL is disabled
02885   * @note   This  can be selected for SAI1 or SAI2 (*)
02886   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\n
02887   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\n
02888   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\n
02889   *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SAI
02890   * @param  Source This parameter can be one of the following values:
02891   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02892   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02893   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02894   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02895   * @param  PLLM This parameter can be one of the following values:
02896   *         @arg @ref LL_RCC_PLLM_DIV_1
02897   *         @arg @ref LL_RCC_PLLM_DIV_2
02898   *         @arg @ref LL_RCC_PLLM_DIV_3
02899   *         @arg @ref LL_RCC_PLLM_DIV_4
02900   *         @arg @ref LL_RCC_PLLM_DIV_5
02901   *         @arg @ref LL_RCC_PLLM_DIV_6
02902   *         @arg @ref LL_RCC_PLLM_DIV_7
02903   *         @arg @ref LL_RCC_PLLM_DIV_8
02904   * @param  PLLN Between 8 and 86
02905   * @param  PLLP This parameter can be one of the following values:
02906   *         @arg @ref LL_RCC_PLLP_DIV_7
02907   *         @arg @ref LL_RCC_PLLP_DIV_17
02908   * @retval None
02909   */
02910 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
02911 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
02912 {
02913 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
02914   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
02915              Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLP);
02916 #else
02917   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
02918              Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLP);
02919 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
02920 }
02921
02922 /**
02923   * @brief  Configure PLL used for 48Mhz domain clock
02924   * @note PLL Source and PLLM Divider can be written only when PLL,
02925   *       PLLSAI1 and PLLSAI2 (*) are disabled
02926   * @note PLLN/PLLQ can be written only when PLL is disabled
02927   * @note This  can be selected for USB, RNG, SDMMC
02928   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
02929   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
02930   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
02931   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
02932   * @param  Source This parameter can be one of the following values:
02933   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02934   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02935   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02936   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02937   * @param  PLLM This parameter can be one of the following values:
02938   *         @arg @ref LL_RCC_PLLM_DIV_1
02939   *         @arg @ref LL_RCC_PLLM_DIV_2
02940   *         @arg @ref LL_RCC_PLLM_DIV_3
02941   *         @arg @ref LL_RCC_PLLM_DIV_4
02942   *         @arg @ref LL_RCC_PLLM_DIV_5
02943   *         @arg @ref LL_RCC_PLLM_DIV_6
02944   *         @arg @ref LL_RCC_PLLM_DIV_7
02945   *         @arg @ref LL_RCC_PLLM_DIV_8
02946   * @param  PLLN Between 8 and 86
02947   * @param  PLLQ This parameter can be one of the following values:
02948   *         @arg @ref LL_RCC_PLLQ_DIV_2
02949   *         @arg @ref LL_RCC_PLLQ_DIV_4
02950   *         @arg @ref LL_RCC_PLLQ_DIV_6
02951   *         @arg @ref LL_RCC_PLLQ_DIV_8
02952   * @retval None
02953   */
02954 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
02955 {
02956   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
02957              Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLQ);
02958 }
02959
02960 /**
02961   * @brief  Get Main PLL multiplication factor for VCO
02962   * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
02963   * @retval Between 8 and 86
02964   */
02965 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
02966 {
02967   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_POSITION_PLLN);
02968 }
02969
02970 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
02971 /**
02972   * @brief  Get Main PLL division factor for PLLP
02973   * @note   used for PLLSAI3CLK (SAI1 and SAI2 clock)
02974   * @rmtoll PLLCFGR      PLLPDIV       LL_RCC_PLL_GetP
02975   * @retval Returned value can be one of the following values:
02976   *         @arg @ref LL_RCC_PLLP_DIV_2
02977   *         @arg @ref LL_RCC_PLLP_DIV_3
02978   *         @arg @ref LL_RCC_PLLP_DIV_4
02979   *         @arg @ref LL_RCC_PLLP_DIV_5
02980   *         @arg @ref LL_RCC_PLLP_DIV_6
02981   *         @arg @ref LL_RCC_PLLP_DIV_7
02982   *         @arg @ref LL_RCC_PLLP_DIV_8
02983   *         @arg @ref LL_RCC_PLLP_DIV_9
02984   *         @arg @ref LL_RCC_PLLP_DIV_10
02985   *         @arg @ref LL_RCC_PLLP_DIV_11
02986   *         @arg @ref LL_RCC_PLLP_DIV_12
02987   *         @arg @ref LL_RCC_PLLP_DIV_13
02988   *         @arg @ref LL_RCC_PLLP_DIV_14
02989   *         @arg @ref LL_RCC_PLLP_DIV_15
02990   *         @arg @ref LL_RCC_PLLP_DIV_16
02991   *         @arg @ref LL_RCC_PLLP_DIV_17
02992   *         @arg @ref LL_RCC_PLLP_DIV_18
02993   *         @arg @ref LL_RCC_PLLP_DIV_19
02994   *         @arg @ref LL_RCC_PLLP_DIV_20
02995   *         @arg @ref LL_RCC_PLLP_DIV_21
02996   *         @arg @ref LL_RCC_PLLP_DIV_22
02997   *         @arg @ref LL_RCC_PLLP_DIV_23
02998   *         @arg @ref LL_RCC_PLLP_DIV_24
02999   *         @arg @ref LL_RCC_PLLP_DIV_25
03000   *         @arg @ref LL_RCC_PLLP_DIV_26
03001   *         @arg @ref LL_RCC_PLLP_DIV_27
03002   *         @arg @ref LL_RCC_PLLP_DIV_28
03003   *         @arg @ref LL_RCC_PLLP_DIV_29
03004   *         @arg @ref LL_RCC_PLLP_DIV_30
03005   *         @arg @ref LL_RCC_PLLP_DIV_31
03006   */
03007 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
03008 {
03009   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
03010 }
03011 #else
03012 /**
03013   * @brief  Get Main PLL division factor for PLLP
03014   * @note   used for PLLSAI3CLK (SAI1 and SAI2 clock)
03015   * @rmtoll PLLCFGR      PLLP          LL_RCC_PLL_GetP
03016   * @retval Returned value can be one of the following values:
03017   *         @arg @ref LL_RCC_PLLP_DIV_7
03018   *         @arg @ref LL_RCC_PLLP_DIV_17
03019   */
03020 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
03021 {
03022   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
03023 }
03024 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
03025
03026 /**
03027   * @brief  Get Main PLL division factor for PLLQ
03028   * @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
03029   * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
03030   * @retval Returned value can be one of the following values:
03031   *         @arg @ref LL_RCC_PLLQ_DIV_2
03032   *         @arg @ref LL_RCC_PLLQ_DIV_4
03033   *         @arg @ref LL_RCC_PLLQ_DIV_6
03034   *         @arg @ref LL_RCC_PLLQ_DIV_8
03035   */
03036 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
03037 {
03038   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
03039 }
03040
03041 /**
03042   * @brief  Get Main PLL division factor for PLLR
03043   * @note used for PLLCLK (system clock)
03044   * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
03045   * @retval Returned value can be one of the following values:
03046   *         @arg @ref LL_RCC_PLLR_DIV_2
03047   *         @arg @ref LL_RCC_PLLR_DIV_4
03048   *         @arg @ref LL_RCC_PLLR_DIV_6
03049   *         @arg @ref LL_RCC_PLLR_DIV_8
03050   */
03051 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
03052 {
03053   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
03054 }
03055
03056 /**
03057   * @brief  Get the oscillator used as PLL clock source.
03058   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
03059   * @retval Returned value can be one of the following values:
03060   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03061   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03062   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03063   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03064   */
03065 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
03066 {
03067   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
03068 }
03069
03070 /**
03071   * @brief  Get Division factor for the main PLL and other PLL
03072   * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
03073   * @retval Returned value can be one of the following values:
03074   *         @arg @ref LL_RCC_PLLM_DIV_1
03075   *         @arg @ref LL_RCC_PLLM_DIV_2
03076   *         @arg @ref LL_RCC_PLLM_DIV_3
03077   *         @arg @ref LL_RCC_PLLM_DIV_4
03078   *         @arg @ref LL_RCC_PLLM_DIV_5
03079   *         @arg @ref LL_RCC_PLLM_DIV_6
03080   *         @arg @ref LL_RCC_PLLM_DIV_7
03081   *         @arg @ref LL_RCC_PLLM_DIV_8
03082   */
03083 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
03084 {
03085   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
03086 }
03087
03088 /**
03089   * @brief  Enable PLL output mapped on SAI domain clock
03090   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_SAI
03091   * @retval None
03092   */
03093 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
03094 {
03095   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03096 }
03097
03098 /**
03099   * @brief  Disable PLL output mapped on SAI domain clock
03100   * @note Cannot be disabled if the PLL clock is used as the system
03101   *       clock
03102   * @note In order to save power, when the PLLCLK  of the PLL is
03103   *       not used,  should be 0
03104   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_SAI
03105   * @retval None
03106   */
03107 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
03108 {
03109   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03110 }
03111
03112 /**
03113   * @brief  Enable PLL output mapped on 48MHz domain clock
03114   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_48M
03115   * @retval None
03116   */
03117 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
03118 {
03119   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03120 }
03121
03122 /**
03123   * @brief  Disable PLL output mapped on 48MHz domain clock
03124   * @note Cannot be disabled if the PLL clock is used as the system
03125   *       clock
03126   * @note In order to save power, when the PLLCLK  of the PLL is
03127   *       not used,  should be 0
03128   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_48M
03129   * @retval None
03130   */
03131 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
03132 {
03133   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03134 }
03135
03136 /**
03137   * @brief  Enable PLL output mapped on SYSCLK domain
03138   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_EnableDomain_SYS
03139   * @retval None
03140   */
03141 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
03142 {
03143   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
03144 }
03145
03146 /**
03147   * @brief  Disable PLL output mapped on SYSCLK domain
03148   * @note Cannot be disabled if the PLL clock is used as the system
03149   *       clock
03150   * @note In order to save power, when the PLLCLK  of the PLL is
03151   *       not used, Main PLL  should be 0
03152   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_DisableDomain_SYS
03153   * @retval None
03154   */
03155 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
03156 {
03157   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
03158 }
03159
03160 /**
03161   * @}
03162   */
03163
03164 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
03165   * @{
03166   */
03167
03168 /**
03169   * @brief  Enable PLLSAI1
03170   * @rmtoll CR           PLLSAI1ON     LL_RCC_PLLSAI1_Enable
03171   * @retval None
03172   */
03173 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
03174 {
03175   SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
03176 }
03177
03178 /**
03179   * @brief  Disable PLLSAI1
03180   * @rmtoll CR           PLLSAI1ON     LL_RCC_PLLSAI1_Disable
03181   * @retval None
03182   */
03183 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
03184 {
03185   CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
03186 }
03187
03188 /**
03189   * @brief  Check if PLLSAI1 Ready
03190   * @rmtoll CR           PLLSAI1RDY    LL_RCC_PLLSAI1_IsReady
03191   * @retval State of bit (1 or 0).
03192   */
03193 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
03194 {
03195   return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
03196 }
03197
03198 /**
03199   * @brief  Configure PLLSAI1 used for 48Mhz domain clock
03200   * @note PLL Source and PLLM Divider can be written only when PLL,
03201   *       PLLSAI1 and PLLSAI2 (*) are disabled
03202   * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
03203   * @note This  can be selected for USB, RNG, SDMMC
03204   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_48M\n
03205   *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_48M\n
03206   *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_48M\n
03207   *         PLLSAI1CFGR  PLLSAI1Q      LL_RCC_PLLSAI1_ConfigDomain_48M
03208   * @param  Source This parameter can be one of the following values:
03209   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03210   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03211   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03212   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03213   * @param  PLLM This parameter can be one of the following values:
03214   *         @arg @ref LL_RCC_PLLM_DIV_1
03215   *         @arg @ref LL_RCC_PLLM_DIV_2
03216   *         @arg @ref LL_RCC_PLLM_DIV_3
03217   *         @arg @ref LL_RCC_PLLM_DIV_4
03218   *         @arg @ref LL_RCC_PLLM_DIV_5
03219   *         @arg @ref LL_RCC_PLLM_DIV_6
03220   *         @arg @ref LL_RCC_PLLM_DIV_7
03221   *         @arg @ref LL_RCC_PLLM_DIV_8
03222   * @param  PLLN Between 8 and 86
03223   * @param  PLLQ This parameter can be one of the following values:
03224   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2
03225   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4
03226   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6
03227   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8
03228   * @retval None
03229   */
03230 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
03231 {
03232   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
03233   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_POSITION_PLLSAI1N | PLLQ);
03234 }
03235
03236 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
03237 /**
03238   * @brief  Configure PLLSAI1 used for SAI domain clock
03239   * @note PLL Source and PLLM Divider can be written only when PLL,
03240   *       PLLSAI1 and PLLSAI2 (*) are disabled
03241   * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
03242   * @note This  can be selected for SAI1 or SAI2 (*)
03243   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_SAI\n
03244   *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_SAI\n
03245   *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_SAI\n
03246   *         PLLSAI1CFGR  PLLSAI1PDIV   LL_RCC_PLLSAI1_ConfigDomain_SAI
03247   * @param  Source This parameter can be one of the following values:
03248   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03249   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03250   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03251   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03252   * @param  PLLM This parameter can be one of the following values:
03253   *         @arg @ref LL_RCC_PLLM_DIV_1
03254   *         @arg @ref LL_RCC_PLLM_DIV_2
03255   *         @arg @ref LL_RCC_PLLM_DIV_3
03256   *         @arg @ref LL_RCC_PLLM_DIV_4
03257   *         @arg @ref LL_RCC_PLLM_DIV_5
03258   *         @arg @ref LL_RCC_PLLM_DIV_6
03259   *         @arg @ref LL_RCC_PLLM_DIV_7
03260   *         @arg @ref LL_RCC_PLLM_DIV_8
03261   * @param  PLLN Between 8 and 86
03262   * @param  PLLP This parameter can be one of the following values:
03263   *         @arg @ref LL_RCC_PLLSAI1P_DIV_2
03264   *         @arg @ref LL_RCC_PLLSAI1P_DIV_3
03265   *         @arg @ref LL_RCC_PLLSAI1P_DIV_4
03266   *         @arg @ref LL_RCC_PLLSAI1P_DIV_5
03267   *         @arg @ref LL_RCC_PLLSAI1P_DIV_6
03268   *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
03269   *         @arg @ref LL_RCC_PLLSAI1P_DIV_8
03270   *         @arg @ref LL_RCC_PLLSAI1P_DIV_9
03271   *         @arg @ref LL_RCC_PLLSAI1P_DIV_10
03272   *         @arg @ref LL_RCC_PLLSAI1P_DIV_11
03273   *         @arg @ref LL_RCC_PLLSAI1P_DIV_12
03274   *         @arg @ref LL_RCC_PLLSAI1P_DIV_13
03275   *         @arg @ref LL_RCC_PLLSAI1P_DIV_14
03276   *         @arg @ref LL_RCC_PLLSAI1P_DIV_15
03277   *         @arg @ref LL_RCC_PLLSAI1P_DIV_16
03278   *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
03279   *         @arg @ref LL_RCC_PLLSAI1P_DIV_18
03280   *         @arg @ref LL_RCC_PLLSAI1P_DIV_19
03281   *         @arg @ref LL_RCC_PLLSAI1P_DIV_20
03282   *         @arg @ref LL_RCC_PLLSAI1P_DIV_21
03283   *         @arg @ref LL_RCC_PLLSAI1P_DIV_22
03284   *         @arg @ref LL_RCC_PLLSAI1P_DIV_23
03285   *         @arg @ref LL_RCC_PLLSAI1P_DIV_24
03286   *         @arg @ref LL_RCC_PLLSAI1P_DIV_25
03287   *         @arg @ref LL_RCC_PLLSAI1P_DIV_26
03288   *         @arg @ref LL_RCC_PLLSAI1P_DIV_27
03289   *         @arg @ref LL_RCC_PLLSAI1P_DIV_28
03290   *         @arg @ref LL_RCC_PLLSAI1P_DIV_29
03291   *         @arg @ref LL_RCC_PLLSAI1P_DIV_30
03292   *         @arg @ref LL_RCC_PLLSAI1P_DIV_31
03293   * @retval None
03294   */
03295 #else
03296 /**
03297   * @brief  Configure PLLSAI1 used for SAI domain clock
03298   * @note PLL Source and PLLM Divider can be written only when PLL,
03299   *       PLLSAI1 and PLLSAI2 (*) are disabled
03300   * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
03301   * @note This  can be selected for SAI1 or SAI2 (*)
03302   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_SAI\n
03303   *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_SAI\n
03304   *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_SAI\n
03305   *         PLLSAI1CFGR  PLLSAI1P      LL_RCC_PLLSAI1_ConfigDomain_SAI
03306   * @param  Source This parameter can be one of the following values:
03307   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03308   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03309   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03310   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03311   * @param  PLLM This parameter can be one of the following values:
03312   *         @arg @ref LL_RCC_PLLM_DIV_1
03313   *         @arg @ref LL_RCC_PLLM_DIV_2
03314   *         @arg @ref LL_RCC_PLLM_DIV_3
03315   *         @arg @ref LL_RCC_PLLM_DIV_4
03316   *         @arg @ref LL_RCC_PLLM_DIV_5
03317   *         @arg @ref LL_RCC_PLLM_DIV_6
03318   *         @arg @ref LL_RCC_PLLM_DIV_7
03319   *         @arg @ref LL_RCC_PLLM_DIV_8
03320   * @param  PLLN Between 8 and 86
03321   * @param  PLLP This parameter can be one of the following values:
03322   *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
03323   *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
03324   * @retval None
03325   */
03326 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
03327 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
03328 {
03329   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
03330 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
03331   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
03332              PLLN << RCC_POSITION_PLLSAI1N | PLLP);
03333 #else
03334   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_POSITION_PLLSAI1N | PLLP);
03335 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
03336 }
03337
03338 /**
03339   * @brief  Configure PLLSAI1 used for ADC domain clock
03340   * @note PLL Source and PLLM Divider can be written only when PLL,
03341   *       PLLSAI1 and PLLSAI2 (*) are disabled
03342   * @note PLLN/PLLR can be written only when PLLSAI1 is disabled
03343   * @note This  can be selected for ADC
03344   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_ADC\n
03345   *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_ADC\n
03346   *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_ADC\n
03347   *         PLLSAI1CFGR  PLLSAI1R      LL_RCC_PLLSAI1_ConfigDomain_ADC
03348   * @param  Source This parameter can be one of the following values:
03349   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03350   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03351   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03352   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03353   * @param  PLLM This parameter can be one of the following values:
03354   *         @arg @ref LL_RCC_PLLM_DIV_1
03355   *         @arg @ref LL_RCC_PLLM_DIV_2
03356   *         @arg @ref LL_RCC_PLLM_DIV_3
03357   *         @arg @ref LL_RCC_PLLM_DIV_4
03358   *         @arg @ref LL_RCC_PLLM_DIV_5
03359   *         @arg @ref LL_RCC_PLLM_DIV_6
03360   *         @arg @ref LL_RCC_PLLM_DIV_7
03361   *         @arg @ref LL_RCC_PLLM_DIV_8
03362   * @param  PLLN Between 8 and 86
03363   * @param  PLLR This parameter can be one of the following values:
03364   *         @arg @ref LL_RCC_PLLSAI1R_DIV_2
03365   *         @arg @ref LL_RCC_PLLSAI1R_DIV_4
03366   *         @arg @ref LL_RCC_PLLSAI1R_DIV_6
03367   *         @arg @ref LL_RCC_PLLSAI1R_DIV_8
03368   * @retval None
03369   */
03370 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
03371 {
03372   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
03373   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_POSITION_PLLSAI1N | PLLR);
03374 }
03375
03376 /**
03377   * @brief  Get SAI1PLL multiplication factor for VCO
03378   * @rmtoll PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_GetN
03379   * @retval Between 8 and 86
03380   */
03381 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
03382 {
03383   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_POSITION_PLLSAI1N);
03384 }
03385
03386 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
03387 /**
03388   * @brief  Get SAI1PLL division factor for PLLSAI1P
03389   * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
03390   * @rmtoll PLLSAI1CFGR  PLLSAI1PDIV      LL_RCC_PLLSAI1_GetP
03391   * @retval Returned value can be one of the following values:
03392   *         @arg @ref LL_RCC_PLLSAI1P_DIV_2
03393   *         @arg @ref LL_RCC_PLLSAI1P_DIV_3
03394   *         @arg @ref LL_RCC_PLLSAI1P_DIV_4
03395   *         @arg @ref LL_RCC_PLLSAI1P_DIV_5
03396   *         @arg @ref LL_RCC_PLLSAI1P_DIV_6
03397   *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
03398   *         @arg @ref LL_RCC_PLLSAI1P_DIV_8
03399   *         @arg @ref LL_RCC_PLLSAI1P_DIV_9
03400   *         @arg @ref LL_RCC_PLLSAI1P_DIV_10
03401   *         @arg @ref LL_RCC_PLLSAI1P_DIV_11
03402   *         @arg @ref LL_RCC_PLLSAI1P_DIV_12
03403   *         @arg @ref LL_RCC_PLLSAI1P_DIV_13
03404   *         @arg @ref LL_RCC_PLLSAI1P_DIV_14
03405   *         @arg @ref LL_RCC_PLLSAI1P_DIV_15
03406   *         @arg @ref LL_RCC_PLLSAI1P_DIV_16
03407   *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
03408   *         @arg @ref LL_RCC_PLLSAI1P_DIV_18
03409   *         @arg @ref LL_RCC_PLLSAI1P_DIV_19
03410   *         @arg @ref LL_RCC_PLLSAI1P_DIV_20
03411   *         @arg @ref LL_RCC_PLLSAI1P_DIV_21
03412   *         @arg @ref LL_RCC_PLLSAI1P_DIV_22
03413   *         @arg @ref LL_RCC_PLLSAI1P_DIV_23
03414   *         @arg @ref LL_RCC_PLLSAI1P_DIV_24
03415   *         @arg @ref LL_RCC_PLLSAI1P_DIV_25
03416   *         @arg @ref LL_RCC_PLLSAI1P_DIV_26
03417   *         @arg @ref LL_RCC_PLLSAI1P_DIV_27
03418   *         @arg @ref LL_RCC_PLLSAI1P_DIV_28
03419   *         @arg @ref LL_RCC_PLLSAI1P_DIV_29
03420   *         @arg @ref LL_RCC_PLLSAI1P_DIV_30
03421   *         @arg @ref LL_RCC_PLLSAI1P_DIV_31
03422   */
03423 #else
03424 /**
03425   * @brief  Get SAI1PLL division factor for PLLSAI1P
03426   * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
03427   * @rmtoll PLLSAI1CFGR  PLLSAI1P      LL_RCC_PLLSAI1_GetP
03428   * @retval Returned value can be one of the following values:
03429   *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
03430   *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
03431   */
03432 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
03433 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
03434 {
03435 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
03436   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
03437 #else
03438   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
03439 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
03440 }
03441
03442 /**
03443   * @brief  Get SAI1PLL division factor for PLLSAI1Q
03444   * @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
03445   * @rmtoll PLLSAI1CFGR  PLLSAI1Q      LL_RCC_PLLSAI1_GetQ
03446   * @retval Returned value can be one of the following values:
03447   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2
03448   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4
03449   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6
03450   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8
03451   */
03452 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
03453 {
03454   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
03455 }
03456
03457 /**
03458   * @brief  Get PLLSAI1 division factor for PLLSAIR
03459   * @note used for PLLADC1CLK (ADC clock)
03460   * @rmtoll PLLSAI1CFGR  PLLSAI1R      LL_RCC_PLLSAI1_GetR
03461   * @retval Returned value can be one of the following values:
03462   *         @arg @ref LL_RCC_PLLSAI1R_DIV_2
03463   *         @arg @ref LL_RCC_PLLSAI1R_DIV_4
03464   *         @arg @ref LL_RCC_PLLSAI1R_DIV_6
03465   *         @arg @ref LL_RCC_PLLSAI1R_DIV_8
03466   */
03467 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
03468 {
03469   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
03470 }
03471
03472 /**
03473   * @brief  Enable PLLSAI1 output mapped on SAI domain clock
03474   * @rmtoll PLLSAI1CFGR  PLLSAI1PEN    LL_RCC_PLLSAI1_EnableDomain_SAI
03475   * @retval None
03476   */
03477 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
03478 {
03479   SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
03480 }
03481
03482 /**
03483   * @brief  Disable PLLSAI1 output mapped on SAI domain clock
03484   * @note In order to save power, when  of the PLLSAI1 is
03485   *       not used,  should be 0
03486   * @rmtoll PLLSAI1CFGR  PLLSAI1PEN    LL_RCC_PLLSAI1_DisableDomain_SAI
03487   * @retval None
03488   */
03489 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
03490 {
03491   CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
03492 }
03493
03494 /**
03495   * @brief  Enable PLLSAI1 output mapped on 48MHz domain clock
03496   * @rmtoll PLLSAI1CFGR  PLLSAI1QEN    LL_RCC_PLLSAI1_EnableDomain_48M
03497   * @retval None
03498   */
03499 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
03500 {
03501   SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
03502 }
03503
03504 /**
03505   * @brief  Disable PLLSAI1 output mapped on 48MHz domain clock
03506   * @note In order to save power, when  of the PLLSAI1 is
03507   *       not used,  should be 0
03508   * @rmtoll PLLSAI1CFGR  PLLSAI1QEN    LL_RCC_PLLSAI1_DisableDomain_48M
03509   * @retval None
03510   */
03511 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
03512 {
03513   CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
03514 }
03515
03516 /**
03517   * @brief  Enable PLLSAI1 output mapped on ADC domain clock
03518   * @rmtoll PLLSAI1CFGR  PLLSAI1REN    LL_RCC_PLLSAI1_EnableDomain_ADC
03519   * @retval None
03520   */
03521 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
03522 {
03523   SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
03524 }
03525
03526 /**
03527   * @brief  Disable PLLSAI1 output mapped on ADC domain clock
03528   * @note In order to save power, when  of the PLLSAI1 is
03529   *       not used, Main PLLSAI1  should be 0
03530   * @rmtoll PLLSAI1CFGR  PLLSAI1REN    LL_RCC_PLLSAI1_DisableDomain_ADC
03531   * @retval None
03532   */
03533 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
03534 {
03535   CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
03536 }
03537
03538 /**
03539   * @}
03540   */
03541
03542 #if defined(RCC_PLLSAI2_SUPPORT)
03543 /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
03544   * @{
03545   */
03546
03547 /**
03548   * @brief  Enable PLLSAI2
03549   * @rmtoll CR           PLLSAI2ON     LL_RCC_PLLSAI2_Enable
03550   * @retval None
03551   */
03552 __STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
03553 {
03554   SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
03555 }
03556
03557 /**
03558   * @brief  Disable PLLSAI2
03559   * @rmtoll CR           PLLSAI2ON     LL_RCC_PLLSAI2_Disable
03560   * @retval None
03561   */
03562 __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
03563 {
03564   CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
03565 }
03566
03567 /**
03568   * @brief  Check if PLLSAI2 Ready
03569   * @rmtoll CR           PLLSAI2RDY    LL_RCC_PLLSAI2_IsReady
03570   * @retval State of bit (1 or 0).
03571   */
03572 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
03573 {
03574   return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
03575 }
03576
03577 /**
03578   * @brief  Configure PLLSAI2 used for SAI domain clock
03579   * @note PLL Source and PLLM Divider can be written only when PLL,
03580   *       PLLSAI2 and PLLSAI2 are disabled
03581   * @note PLLN/PLLP can be written only when PLLSAI2 is disabled
03582   * @note This  can be selected for SAI1 or SAI2
03583   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_SAI\n
03584   *         PLLCFGR      PLLM          LL_RCC_PLLSAI2_ConfigDomain_SAI\n
03585   *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_SAI\n
03586   *         PLLSAI2CFGR  PLLSAI2P      LL_RCC_PLLSAI2_ConfigDomain_SAI
03587   * @param  Source This parameter can be one of the following values:
03588   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03589   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03590   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03591   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03592   * @param  PLLM This parameter can be one of the following values:
03593   *         @arg @ref LL_RCC_PLLM_DIV_1
03594   *         @arg @ref LL_RCC_PLLM_DIV_2
03595   *         @arg @ref LL_RCC_PLLM_DIV_3
03596   *         @arg @ref LL_RCC_PLLM_DIV_4
03597   *         @arg @ref LL_RCC_PLLM_DIV_5
03598   *         @arg @ref LL_RCC_PLLM_DIV_6
03599   *         @arg @ref LL_RCC_PLLM_DIV_7
03600   *         @arg @ref LL_RCC_PLLM_DIV_8
03601   * @param  PLLN Between 8 and 86
03602   * @param  PLLP This parameter can be one of the following values:
03603   *         @arg @ref LL_RCC_PLLSAI2P_DIV_7
03604   *         @arg @ref LL_RCC_PLLSAI2P_DIV_17
03605   * @retval None
03606   */
03607 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
03608 {
03609   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
03610   MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_POSITION_PLLSAI2N | PLLP);
03611 }
03612
03613 /**
03614   * @brief  Configure PLLSAI2 used for ADC domain clock
03615   * @note PLL Source and PLLM Divider can be written only when PLL,
03616   *       PLLSAI2 and PLLSAI2 are disabled
03617   * @note PLLN/PLLR can be written only when PLLSAI2 is disabled
03618   * @note This  can be selected for ADC
03619   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_ADC\n
03620   *         PLLCFGR      PLLM          LL_RCC_PLLSAI2_ConfigDomain_ADC\n
03621   *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_ADC\n
03622   *         PLLSAI2CFGR  PLLSAI2R      LL_RCC_PLLSAI2_ConfigDomain_ADC
03623   * @param  Source This parameter can be one of the following values:
03624   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03625   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03626   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03627   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03628   * @param  PLLM This parameter can be one of the following values:
03629   *         @arg @ref LL_RCC_PLLM_DIV_1
03630   *         @arg @ref LL_RCC_PLLM_DIV_2
03631   *         @arg @ref LL_RCC_PLLM_DIV_3
03632   *         @arg @ref LL_RCC_PLLM_DIV_4
03633   *         @arg @ref LL_RCC_PLLM_DIV_5
03634   *         @arg @ref LL_RCC_PLLM_DIV_6
03635   *         @arg @ref LL_RCC_PLLM_DIV_7
03636   *         @arg @ref LL_RCC_PLLM_DIV_8
03637   * @param  PLLN Between 8 and 86
03638   * @param  PLLR This parameter can be one of the following values:
03639   *         @arg @ref LL_RCC_PLLSAI2R_DIV_2
03640   *         @arg @ref LL_RCC_PLLSAI2R_DIV_4
03641   *         @arg @ref LL_RCC_PLLSAI2R_DIV_6
03642   *         @arg @ref LL_RCC_PLLSAI2R_DIV_8
03643   * @retval None
03644   */
03645 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
03646 {
03647   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
03648   MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_POSITION_PLLSAI2N | PLLR);
03649 }
03650
03651 /**
03652   * @brief  Get SAI2PLL multiplication factor for VCO
03653   * @rmtoll PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_GetN
03654   * @retval Between 8 and 86
03655   */
03656 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
03657 {
03658   return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_POSITION_PLLSAI2N);
03659 }
03660
03661 /**
03662   * @brief  Get SAI2PLL division factor for PLLSAI2P
03663   * @note   used for PLLSAI2CLK (SAI1 or SAI2 clock).
03664   * @rmtoll PLLSAI2CFGR  PLLSAI2P      LL_RCC_PLLSAI2_GetP
03665   * @retval Returned value can be one of the following values:
03666   *         @arg @ref LL_RCC_PLLSAI2P_DIV_7
03667   *         @arg @ref LL_RCC_PLLSAI2P_DIV_17
03668   */
03669 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
03670 {
03671   return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
03672 }
03673
03674 /**
03675   * @brief  Get SAI2PLL division factor for PLLSAI2R
03676   * @note used for PLLADC2CLK (ADC clock)
03677   * @rmtoll PLLSAI2CFGR  PLLSAI2R      LL_RCC_PLLSAI2_GetR
03678   * @retval Returned value can be one of the following values:
03679   *         @arg @ref LL_RCC_PLLSAI2R_DIV_2
03680   *         @arg @ref LL_RCC_PLLSAI2R_DIV_4
03681   *         @arg @ref LL_RCC_PLLSAI2R_DIV_6
03682   *         @arg @ref LL_RCC_PLLSAI2R_DIV_8
03683   */
03684 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
03685 {
03686   return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
03687 }
03688
03689 /**
03690   * @brief  Enable PLLSAI2 output mapped on SAI domain clock
03691   * @rmtoll PLLSAI2CFGR  PLLSAI2PEN    LL_RCC_PLLSAI2_EnableDomain_SAI
03692   * @retval None
03693   */
03694 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
03695 {
03696   SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
03697 }
03698
03699 /**
03700   * @brief  Disable PLLSAI2 output mapped on SAI domain clock
03701   * @note In order to save power, when  of the PLLSAI2 is
03702   *       not used,  should be 0
03703   * @rmtoll PLLSAI2CFGR  PLLSAI2PEN    LL_RCC_PLLSAI2_DisableDomain_SAI
03704   * @retval None
03705   */
03706 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
03707 {
03708   CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
03709 }
03710
03711 /**
03712   * @brief  Enable PLLSAI2 output mapped on ADC domain clock
03713   * @rmtoll PLLSAI2CFGR  PLLSAI2REN    LL_RCC_PLLSAI2_EnableDomain_ADC
03714   * @retval None
03715   */
03716 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
03717 {
03718   SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
03719 }
03720
03721 /**
03722   * @brief  Disable PLLSAI2 output mapped on ADC domain clock
03723   * @note In order to save power, when  of the PLLSAI2 is
03724   *       not used, Main PLLSAI2  should be 0
03725   * @rmtoll PLLSAI2CFGR  PLLSAI2REN    LL_RCC_PLLSAI2_DisableDomain_ADC
03726   * @retval None
03727   */
03728 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
03729 {
03730   CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
03731 }
03732
03733 /**
03734   * @}
03735   */
03736
03737 #endif /* RCC_PLLSAI2_SUPPORT */
03738 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
03739   * @{
03740   */
03741
03742 /**
03743   * @brief  Clear LSI ready interrupt flag
03744   * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
03745   * @retval None
03746   */
03747 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
03748 {
03749   SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
03750 }
03751
03752 /**
03753   * @brief  Clear LSE ready interrupt flag
03754   * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
03755   * @retval None
03756   */
03757 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
03758 {
03759   SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
03760 }
03761
03762 /**
03763   * @brief  Clear MSI ready interrupt flag
03764   * @rmtoll CICR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY
03765   * @retval None
03766   */
03767 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
03768 {
03769   SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
03770 }
03771
03772 /**
03773   * @brief  Clear HSI ready interrupt flag
03774   * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
03775   * @retval None
03776   */
03777 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
03778 {
03779   SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
03780 }
03781
03782 /**
03783   * @brief  Clear HSE ready interrupt flag
03784   * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
03785   * @retval None
03786   */
03787 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
03788 {
03789   SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
03790 }
03791
03792 /**
03793   * @brief  Clear PLL ready interrupt flag
03794   * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
03795   * @retval None
03796   */
03797 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
03798 {
03799   SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
03800 }
03801
03802 #if defined(RCC_HSI48_SUPPORT)
03803 /**
03804   * @brief  Clear HSI48 ready interrupt flag
03805   * @rmtoll CICR          HSI48RDYC     LL_RCC_ClearFlag_HSI48RDY
03806   * @retval None
03807   */
03808 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
03809 {
03810   SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
03811 }
03812 #endif /* RCC_HSI48_SUPPORT */
03813
03814 /**
03815   * @brief  Clear PLLSAI1 ready interrupt flag
03816   * @rmtoll CICR         PLLSAI1RDYC   LL_RCC_ClearFlag_PLLSAI1RDY
03817   * @retval None
03818   */
03819 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
03820 {
03821   SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
03822 }
03823
03824 #if defined(RCC_PLLSAI2_SUPPORT)
03825 /**
03826   * @brief  Clear PLLSAI1 ready interrupt flag
03827   * @rmtoll CICR         PLLSAI2RDYC   LL_RCC_ClearFlag_PLLSAI2RDY
03828   * @retval None
03829   */
03830 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
03831 {
03832   SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
03833 }
03834
03835 #endif /* RCC_PLLSAI2_SUPPORT */
03836 /**
03837   * @brief  Clear Clock security system interrupt flag
03838   * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS
03839   * @retval None
03840   */
03841 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
03842 {
03843   SET_BIT(RCC->CICR, RCC_CICR_CSSC);
03844 }
03845
03846 /**
03847   * @brief  Clear LSE Clock security system interrupt flag
03848   * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS
03849   * @retval None
03850   */
03851 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
03852 {
03853   SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
03854 }
03855
03856 /**
03857   * @brief  Check if LSI ready interrupt occurred or not
03858   * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
03859   * @retval State of bit (1 or 0).
03860   */
03861 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
03862 {
03863   return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
03864 }
03865
03866 /**
03867   * @brief  Check if LSE ready interrupt occurred or not
03868   * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
03869   * @retval State of bit (1 or 0).
03870   */
03871 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
03872 {
03873   return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
03874 }
03875
03876 /**
03877   * @brief  Check if MSI ready interrupt occurred or not
03878   * @rmtoll CIFR         MSIRDYF       LL_RCC_IsActiveFlag_MSIRDY
03879   * @retval State of bit (1 or 0).
03880   */
03881 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
03882 {
03883   return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
03884 }
03885
03886 /**
03887   * @brief  Check if HSI ready interrupt occurred or not
03888   * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
03889   * @retval State of bit (1 or 0).
03890   */
03891 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
03892 {
03893   return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
03894 }
03895
03896 /**
03897   * @brief  Check if HSE ready interrupt occurred or not
03898   * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
03899   * @retval State of bit (1 or 0).
03900   */
03901 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
03902 {
03903   return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
03904 }
03905
03906 /**
03907   * @brief  Check if PLL ready interrupt occurred or not
03908   * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
03909   * @retval State of bit (1 or 0).
03910   */
03911 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
03912 {
03913   return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
03914 }
03915
03916 #if defined(RCC_HSI48_SUPPORT)
03917 /**
03918   * @brief  Check if HSI48 ready interrupt occurred or not
03919   * @rmtoll CIR          HSI48RDYF     LL_RCC_IsActiveFlag_HSI48RDY
03920   * @retval State of bit (1 or 0).
03921   */
03922 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
03923 {
03924   return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));
03925 }
03926 #endif /* RCC_HSI48_SUPPORT */
03927
03928 /**
03929   * @brief  Check if PLLSAI1 ready interrupt occurred or not
03930   * @rmtoll CIFR         PLLSAI1RDYF   LL_RCC_IsActiveFlag_PLLSAI1RDY
03931   * @retval State of bit (1 or 0).
03932   */
03933 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
03934 {
03935   return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));
03936 }
03937
03938 #if defined(RCC_PLLSAI2_SUPPORT)
03939 /**
03940   * @brief  Check if PLLSAI1 ready interrupt occurred or not
03941   * @rmtoll CIFR         PLLSAI2RDYF   LL_RCC_IsActiveFlag_PLLSAI2RDY
03942   * @retval State of bit (1 or 0).
03943   */
03944 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
03945 {
03946   return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));
03947 }
03948
03949 #endif /* RCC_PLLSAI2_SUPPORT */
03950 /**
03951   * @brief  Check if Clock security system interrupt occurred or not
03952   * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS
03953   * @retval State of bit (1 or 0).
03954   */
03955 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
03956 {
03957   return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
03958 }
03959
03960 /**
03961   * @brief  Check if LSE Clock security system interrupt occurred or not
03962   * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
03963   * @retval State of bit (1 or 0).
03964   */
03965 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
03966 {
03967   return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
03968 }
03969
03970
03971 /**
03972   * @brief  Check if RCC flag FW reset is set or not.
03973   * @rmtoll CSR          FWRSTF        LL_RCC_IsActiveFlag_FWRST
03974   * @retval State of bit (1 or 0).
03975   */
03976 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
03977 {
03978   return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
03979 }
03980
03981 /**
03982   * @brief  Check if RCC flag Independent Watchdog reset is set or not.
03983   * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
03984   * @retval State of bit (1 or 0).
03985   */
03986 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
03987 {
03988   return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
03989 }
03990
03991 /**
03992   * @brief  Check if RCC flag Low Power reset is set or not.
03993   * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
03994   * @retval State of bit (1 or 0).
03995   */
03996 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
03997 {
03998   return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
03999 }
04000
04001 /**
04002   * @brief  Check if RCC flag is set or not.
04003   * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
04004   * @retval State of bit (1 or 0).
04005   */
04006 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
04007 {
04008   return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
04009 }
04010
04011 /**
04012   * @brief  Check if RCC flag Pin reset is set or not.
04013   * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
04014   * @retval State of bit (1 or 0).
04015   */
04016 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
04017 {
04018   return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
04019 }
04020
04021 /**
04022   * @brief  Check if RCC flag Software reset is set or not.
04023   * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
04024   * @retval State of bit (1 or 0).
04025   */
04026 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
04027 {
04028   return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
04029 }
04030
04031 /**
04032   * @brief  Check if RCC flag Window Watchdog reset is set or not.
04033   * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
04034   * @retval State of bit (1 or 0).
04035   */
04036 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
04037 {
04038   return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
04039 }
04040
04041 /**
04042   * @brief  Check if RCC flag BOR reset is set or not.
04043   * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
04044   * @retval State of bit (1 or 0).
04045   */
04046 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
04047 {
04048   return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
04049 }
04050
04051 /**
04052   * @brief  Set RMVF bit to clear the reset flags.
04053   * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
04054   * @retval None
04055   */
04056 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
04057 {
04058   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
04059 }
04060
04061 /**
04062   * @}
04063   */
04064
04065 /** @defgroup RCC_LL_EF_IT_Management IT Management
04066   * @{
04067   */
04068
04069 /**
04070   * @brief  Enable LSI ready interrupt
04071   * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
04072   * @retval None
04073   */
04074 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
04075 {
04076   SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
04077 }
04078
04079 /**
04080   * @brief  Enable LSE ready interrupt
04081   * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
04082   * @retval None
04083   */
04084 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
04085 {
04086   SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
04087 }
04088
04089 /**
04090   * @brief  Enable MSI ready interrupt
04091   * @rmtoll CIER         MSIRDYIE      LL_RCC_EnableIT_MSIRDY
04092   * @retval None
04093   */
04094 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
04095 {
04096   SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
04097 }
04098
04099 /**
04100   * @brief  Enable HSI ready interrupt
04101   * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
04102   * @retval None
04103   */
04104 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
04105 {
04106   SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
04107 }
04108
04109 /**
04110   * @brief  Enable HSE ready interrupt
04111   * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
04112   * @retval None
04113   */
04114 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
04115 {
04116   SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
04117 }
04118
04119 /**
04120   * @brief  Enable PLL ready interrupt
04121   * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
04122   * @retval None
04123   */
04124 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
04125 {
04126   SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
04127 }
04128
04129 #if defined(RCC_HSI48_SUPPORT)
04130 /**
04131   * @brief  Enable HSI48 ready interrupt
04132   * @rmtoll CIER          HSI48RDYIE    LL_RCC_EnableIT_HSI48RDY
04133   * @retval None
04134   */
04135 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
04136 {
04137   SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
04138 }
04139 #endif /* RCC_HSI48_SUPPORT */
04140
04141 /**
04142   * @brief  Enable PLLSAI1 ready interrupt
04143   * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_EnableIT_PLLSAI1RDY
04144   * @retval None
04145   */
04146 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
04147 {
04148   SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
04149 }
04150
04151 #if defined(RCC_PLLSAI2_SUPPORT)
04152 /**
04153   * @brief  Enable PLLSAI2 ready interrupt
04154   * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_EnableIT_PLLSAI2RDY
04155   * @retval None
04156   */
04157 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
04158 {
04159   SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
04160 }
04161
04162 #endif /* RCC_PLLSAI2_SUPPORT */
04163 /**
04164   * @brief  Enable LSE clock security system interrupt
04165   * @rmtoll CIER         LSECSSIE      LL_RCC_EnableIT_LSECSS
04166   * @retval None
04167   */
04168 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
04169 {
04170   SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
04171 }
04172
04173 /**
04174   * @brief  Disable LSI ready interrupt
04175   * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
04176   * @retval None
04177   */
04178 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
04179 {
04180   CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
04181 }
04182
04183 /**
04184   * @brief  Disable LSE ready interrupt
04185   * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
04186   * @retval None
04187   */
04188 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
04189 {
04190   CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
04191 }
04192
04193 /**
04194   * @brief  Disable MSI ready interrupt
04195   * @rmtoll CIER         MSIRDYIE      LL_RCC_DisableIT_MSIRDY
04196   * @retval None
04197   */
04198 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
04199 {
04200   CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
04201 }
04202
04203 /**
04204   * @brief  Disable HSI ready interrupt
04205   * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
04206   * @retval None
04207   */
04208 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
04209 {
04210   CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
04211 }
04212
04213 /**
04214   * @brief  Disable HSE ready interrupt
04215   * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
04216   * @retval None
04217   */
04218 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
04219 {
04220   CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
04221 }
04222
04223 /**
04224   * @brief  Disable PLL ready interrupt
04225   * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
04226   * @retval None
04227   */
04228 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
04229 {
04230   CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
04231 }
04232
04233 #if defined(RCC_HSI48_SUPPORT)
04234 /**
04235   * @brief  Disable HSI48 ready interrupt
04236   * @rmtoll CIER          HSI48RDYIE    LL_RCC_DisableIT_HSI48RDY
04237   * @retval None
04238   */
04239 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
04240 {
04241   CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
04242 }
04243 #endif /* RCC_HSI48_SUPPORT */
04244
04245 /**
04246   * @brief  Disable PLLSAI1 ready interrupt
04247   * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_DisableIT_PLLSAI1RDY
04248   * @retval None
04249   */
04250 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
04251 {
04252   CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
04253 }
04254
04255 #if defined(RCC_PLLSAI2_SUPPORT)
04256 /**
04257   * @brief  Disable PLLSAI2 ready interrupt
04258   * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_DisableIT_PLLSAI2RDY
04259   * @retval None
04260   */
04261 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
04262 {
04263   CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
04264 }
04265
04266 #endif /* RCC_PLLSAI2_SUPPORT */
04267 /**
04268   * @brief  Disable LSE clock security system interrupt
04269   * @rmtoll CIER         LSECSSIE      LL_RCC_DisableIT_LSECSS
04270   * @retval None
04271   */
04272 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
04273 {
04274   CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
04275 }
04276
04277 /**
04278   * @brief  Checks if LSI ready interrupt source is enabled or disabled.
04279   * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
04280   * @retval State of bit (1 or 0).
04281   */
04282 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
04283 {
04284   return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
04285 }
04286
04287 /**
04288   * @brief  Checks if LSE ready interrupt source is enabled or disabled.
04289   * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
04290   * @retval State of bit (1 or 0).
04291   */
04292 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
04293 {
04294   return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
04295 }
04296
04297 /**
04298   * @brief  Checks if MSI ready interrupt source is enabled or disabled.
04299   * @rmtoll CIER         MSIRDYIE      LL_RCC_IsEnabledIT_MSIRDY
04300   * @retval State of bit (1 or 0).
04301   */
04302 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
04303 {
04304   return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
04305 }
04306
04307 /**
04308   * @brief  Checks if HSI ready interrupt source is enabled or disabled.
04309   * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
04310   * @retval State of bit (1 or 0).
04311   */
04312 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
04313 {
04314   return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
04315 }
04316
04317 /**
04318   * @brief  Checks if HSE ready interrupt source is enabled or disabled.
04319   * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
04320   * @retval State of bit (1 or 0).
04321   */
04322 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
04323 {
04324   return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
04325 }
04326
04327 /**
04328   * @brief  Checks if PLL ready interrupt source is enabled or disabled.
04329   * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
04330   * @retval State of bit (1 or 0).
04331   */
04332 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
04333 {
04334   return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
04335 }
04336
04337 #if defined(RCC_HSI48_SUPPORT)
04338 /**
04339   * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
04340   * @rmtoll CIER          HSI48RDYIE    LL_RCC_IsEnabledIT_HSI48RDY
04341   * @retval State of bit (1 or 0).
04342   */
04343 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
04344 {
04345   return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));
04346 }
04347 #endif /* RCC_HSI48_SUPPORT */
04348
04349 /**
04350   * @brief  Checks if PLLSAI1 ready interrupt source is enabled or disabled.
04351   * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_IsEnabledIT_PLLSAI1RDY
04352   * @retval State of bit (1 or 0).
04353   */
04354 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
04355 {
04356   return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));
04357 }
04358
04359 #if defined(RCC_PLLSAI2_SUPPORT)
04360 /**
04361   * @brief  Checks if PLLSAI2 ready interrupt source is enabled or disabled.
04362   * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_IsEnabledIT_PLLSAI2RDY
04363   * @retval State of bit (1 or 0).
04364   */
04365 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
04366 {
04367   return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));
04368 }
04369
04370 #endif /* RCC_PLLSAI2_SUPPORT */
04371 /**
04372   * @brief  Checks if LSECSS interrupt source is enabled or disabled.
04373   * @rmtoll CIER         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
04374   * @retval State of bit (1 or 0).
04375   */
04376 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
04377 {
04378   return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
04379 }
04380
04381 /**
04382   * @}
04383   */
04384
04385 #if defined(USE_FULL_LL_DRIVER)
04386 /** @defgroup RCC_LL_EF_Init De-initialization function
04387   * @{
04388   */
04389 ErrorStatus LL_RCC_DeInit(void);
04390 /**
04391   * @}
04392   */
04393
04394 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
04395   * @{
04396   */
04397 void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
04398 uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
04399 #if defined(UART4) || defined(UART5)
04400 uint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
04401 #endif /* UART4 || UART5 */
04402 uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
04403 uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
04404 uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
04405 uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
04406 uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
04407 uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
04408 #if defined(USB_OTG_FS) || defined(USB)
04409 uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
04410 #endif /* USB_OTG_FS || USB */
04411 uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
04412 uint32_t    LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
04413 #if defined(DFSDM1_Channel0)
04414 uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
04415 #endif /* DFSDM1_Channel0 */
04416 /**
04417   * @}
04418   */
04419 #endif /* USE_FULL_LL_DRIVER */
04420
04421 /**
04422   * @}
04423   */
04424
04425 /**
04426   * @}
04427   */
04428
04429 #endif /* defined(RCC) */
04430
04431 /**
04432   * @}
04433   */
04434
04435 #ifdef __cplusplus
04436 }
04437 #endif
04438
04439 #endif /* __STM32L4xx_LL_RCC_H */
04440
04441 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rng.c Source File

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stm32l4xx_ll_rng.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_rng.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   RNG LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_rng.h"
00041 #include "stm32l4xx_ll_bus.h"
00042
00043 #ifdef  USE_FULL_ASSERT
00044 #include "stm32_assert.h"
00045 #else
00046 #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (RNG)
00054
00055 /** @addtogroup RNG_LL
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064
00065 /* Exported functions --------------------------------------------------------*/
00066 /** @addtogroup RNG_LL_Exported_Functions
00067   * @{
00068   */
00069
00070 /** @addtogroup RNG_LL_EF_Init
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  De-initialize RNG registers (Registers restored to their default values).
00076   * @param  RNGx RNG Instance
00077   * @retval An ErrorStatus enumeration value:
00078   *          - SUCCESS: RNG registers are de-initialized
00079   *          - ERROR: not applicable
00080   */
00081 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
00082 {
00083   /* Check the parameters */
00084   assert_param(IS_RNG_ALL_INSTANCE(RNGx));
00085
00086   /* Enable RNG reset state */
00087   LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
00088
00089   /* Release RNG from reset state */
00090   LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
00091
00092   return (SUCCESS);
00093 }
00094
00095 /**
00096   * @}
00097   */
00098
00099 /**
00100   * @}
00101   */
00102
00103 /**
00104   * @}
00105   */
00106
00107 #endif /* defined (RNG) */
00108
00109 /**
00110   * @}
00111   */
00112
00113 #endif /* USE_FULL_LL_DRIVER */
00114
00115 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00116
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rng.h Source File

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stm32l4xx_ll_rng.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_rng.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of RNG LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_RNG_H
00040 #define __STM32L4xx_LL_RNG_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(RNG)
00054
00055 /** @defgroup RNG_LL RNG
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063
00064 /* Exported types ------------------------------------------------------------*/
00065 /* Exported constants --------------------------------------------------------*/
00066 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
00067   * @{
00068   */
00069
00070 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
00071   * @brief    Flags defines which can be used with LL_RNG_ReadReg function
00072   * @{
00073   */
00074 #define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
00075 #define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
00076 #define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
00077 #define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
00078 #define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
00079 /**
00080   * @}
00081   */
00082
00083 /** @defgroup RNG_LL_EC_IT IT Defines
00084   * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
00085   * @{
00086   */
00087 #define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
00088 /**
00089   * @}
00090   */
00091
00092 /**
00093   * @}
00094   */
00095
00096 /* Exported macro ------------------------------------------------------------*/
00097 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
00098   * @{
00099   */
00100
00101 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
00102   * @{
00103   */
00104
00105 /**
00106   * @brief  Write a value in RNG register
00107   * @param  __INSTANCE__ RNG Instance
00108   * @param  __REG__ Register to be written
00109   * @param  __VALUE__ Value to be written in the register
00110   * @retval None
00111   */
00112 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00113
00114 /**
00115   * @brief  Read a value in RNG register
00116   * @param  __INSTANCE__ RNG Instance
00117   * @param  __REG__ Register to be read
00118   * @retval Register value
00119   */
00120 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00121 /**
00122   * @}
00123   */
00124
00125 /**
00126   * @}
00127   */
00128
00129
00130 /* Exported functions --------------------------------------------------------*/
00131 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
00132   * @{
00133   */
00134 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
00135   * @{
00136   */
00137
00138 /**
00139   * @brief  Enable Random Number Generation
00140   * @rmtoll CR           RNGEN         LL_RNG_Enable
00141   * @param  RNGx RNG Instance
00142   * @retval None
00143   */
00144 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
00145 {
00146   SET_BIT(RNGx->CR, RNG_CR_RNGEN);
00147 }
00148
00149 /**
00150   * @brief  Disable Random Number Generation
00151   * @rmtoll CR           RNGEN         LL_RNG_Disable
00152   * @param  RNGx RNG Instance
00153   * @retval None
00154   */
00155 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
00156 {
00157   CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
00158 }
00159
00160 /**
00161   * @brief  Check if Random Number Generator is enabled
00162   * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
00163   * @param  RNGx RNG Instance
00164   * @retval State of bit (1 or 0).
00165   */
00166 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
00167 {
00168   return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN));
00169 }
00170
00171 /**
00172   * @}
00173   */
00174
00175 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
00176   * @{
00177   */
00178
00179 /**
00180   * @brief  Indicate if the RNG Data ready Flag is set or not
00181   * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
00182   * @param  RNGx RNG Instance
00183   * @retval State of bit (1 or 0).
00184   */
00185 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
00186 {
00187   return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY));
00188 }
00189
00190 /**
00191   * @brief  Indicate if the Clock Error Current Status Flag is set or not
00192   * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
00193   * @param  RNGx RNG Instance
00194   * @retval State of bit (1 or 0).
00195   */
00196 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
00197 {
00198   return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS));
00199 }
00200
00201 /**
00202   * @brief  Indicate if the Seed Error Current Status Flag is set or not
00203   * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
00204   * @param  RNGx RNG Instance
00205   * @retval State of bit (1 or 0).
00206   */
00207 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
00208 {
00209   return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS));
00210 }
00211
00212 /**
00213   * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
00214   * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
00215   * @param  RNGx RNG Instance
00216   * @retval State of bit (1 or 0).
00217   */
00218 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
00219 {
00220   return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS));
00221 }
00222
00223 /**
00224   * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
00225   * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
00226   * @param  RNGx RNG Instance
00227   * @retval State of bit (1 or 0).
00228   */
00229 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
00230 {
00231   return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS));
00232 }
00233
00234 /**
00235   * @brief  Clear Clock Error interrupt Status (CEIS) Flag
00236   * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
00237   * @param  RNGx RNG Instance
00238   * @retval None
00239   */
00240 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
00241 {
00242   WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
00243 }
00244
00245 /**
00246   * @brief  Clear Seed Error interrupt Status (SEIS) Flag
00247   * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
00248   * @param  RNGx RNG Instance
00249   * @retval None
00250   */
00251 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
00252 {
00253   WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
00254 }
00255
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup RNG_LL_EF_IT_Management IT Management
00261   * @{
00262   */
00263
00264 /**
00265   * @brief  Enable Random Number Generator Interrupt
00266   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00267   * @rmtoll CR           IE            LL_RNG_EnableIT
00268   * @param  RNGx RNG Instance
00269   * @retval None
00270   */
00271 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
00272 {
00273   SET_BIT(RNGx->CR, RNG_CR_IE);
00274 }
00275
00276 /**
00277   * @brief  Disable Random Number Generator Interrupt
00278   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00279   * @rmtoll CR           IE            LL_RNG_DisableIT
00280   * @param  RNGx RNG Instance
00281   * @retval None
00282   */
00283 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
00284 {
00285   CLEAR_BIT(RNGx->CR, RNG_CR_IE);
00286 }
00287
00288 /**
00289   * @brief  Check if Random Number Generator Interrupt is enabled
00290   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00291   * @rmtoll CR           IE            LL_RNG_IsEnabledIT
00292   * @param  RNGx RNG Instance
00293   * @retval State of bit (1 or 0).
00294   */
00295 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
00296 {
00297   return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE));
00298 }
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup RNG_LL_EF_Data_Management Data Management
00305   * @{
00306   */
00307
00308 /**
00309   * @brief  Return32-bit Random Number value
00310   * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
00311   * @param  RNGx RNG Instance
00312   * @retval Generated 32-bit random value
00313   */
00314 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
00315 {
00316   return (uint32_t)(READ_REG(RNGx->DR));
00317 }
00318
00319 /**
00320   * @}
00321   */
00322
00323 #if defined(USE_FULL_LL_DRIVER)
00324 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
00325   * @{
00326   */
00327
00328 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
00329
00330 /**
00331   * @}
00332   */
00333 #endif /* USE_FULL_LL_DRIVER */
00334
00335 /**
00336   * @}
00337   */
00338
00339 /**
00340   * @}
00341   */
00342
00343 #endif /* defined(RNG) */
00344
00345 /**
00346   * @}
00347   */
00348
00349 #ifdef __cplusplus
00350 }
00351 #endif
00352
00353 #endif /* __STM32L4xx_LL_RNG_H */
00354
00355 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rtc.c Source File

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stm32l4xx_ll_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_rtc.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   RTC LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_rtc.h"
00041 #include "stm32l4xx_ll_cortex.h"
00042 #ifdef  USE_FULL_ASSERT
00043 #include "stm32_assert.h"
00044 #else
00045 #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32L4xx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined(RTC)
00053
00054 /** @addtogroup RTC_LL
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /** @addtogroup RTC_LL_Private_Constants
00062   * @{
00063   */
00064 /* Default values used for prescaler */
00065 #define RTC_ASYNCH_PRESC_DEFAULT     ((uint32_t) 0x0000007FU)
00066 #define RTC_SYNCH_PRESC_DEFAULT      ((uint32_t) 0x000000FFU)
00067
00068 /* Values used for timeout */
00069 #define RTC_INITMODE_TIMEOUT         ((uint32_t) 1000U) /* 1s when tick set to 1ms */
00070 #define RTC_SYNCHRO_TIMEOUT          ((uint32_t) 1000U) /* 1s when tick set to 1ms */
00071 /**
00072   * @}
00073   */
00074
00075 /* Private macros ------------------------------------------------------------*/
00076 /** @addtogroup RTC_LL_Private_Macros
00077   * @{
00078   */
00079
00080 #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
00081                                       || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
00082
00083 #define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= (uint32_t)0x7FU)
00084
00085 #define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= (uint32_t)0x7FFFU)
00086
00087 #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
00088                                   || ((__VALUE__) == LL_RTC_FORMAT_BCD))
00089
00090 #define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
00091                                        || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
00092
00093 #define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
00094 #define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
00095 #define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
00096 #define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
00097
00098 #define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
00099                                    || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
00100                                    || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
00101                                    || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
00102                                    || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
00103                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
00104                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
00105
00106 #define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
00107
00108 #define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
00109                                  || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
00110                                  || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
00111                                  || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
00112                                  || ((__VALUE__) == LL_RTC_MONTH_MAY) \
00113                                  || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
00114                                  || ((__VALUE__) == LL_RTC_MONTH_JULY) \
00115                                  || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
00116                                  || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
00117                                  || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
00118                                  || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
00119                                  || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
00120
00121 #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
00122
00123 #define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
00124                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
00125                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
00126                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
00127                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
00128                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
00129
00130 #define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
00131                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
00132                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
00133                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
00134                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
00135                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
00136
00137
00138 #define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
00139                                                   ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
00140
00141 #define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
00142                                                   ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
00143
00144
00145 /**
00146   * @}
00147   */
00148 /* Private function prototypes -----------------------------------------------*/
00149 /* Exported functions --------------------------------------------------------*/
00150 /** @addtogroup RTC_LL_Exported_Functions
00151   * @{
00152   */
00153
00154 /** @addtogroup RTC_LL_EF_Init
00155   * @{
00156   */
00157
00158 /**
00159   * @brief  De-Initializes the RTC registers to their default reset values.
00160   * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
00161   *         registers.
00162   * @param  RTCx RTC Instance
00163   * @retval An ErrorStatus enumeration value:
00164   *          - SUCCESS: RTC registers are de-initialized
00165   *          - ERROR: RTC registers are not de-initialized
00166   */
00167 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
00168 {
00169   ErrorStatus status = ERROR;
00170
00171   /* Check the parameter */
00172   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00173
00174   /* Disable the write protection for RTC registers */
00175   LL_RTC_DisableWriteProtection(RTCx);
00176
00177   /* Set Initialization mode */
00178   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00179   {
00180     /* Reset TR, DR and CR registers */
00181     LL_RTC_WriteReg(RTCx, TR,       0x00000000U);
00182 #if defined(RTC_WAKEUP_SUPPORT)
00183     LL_RTC_WriteReg(RTCx, WUTR,     RTC_WUTR_WUT);
00184 #endif /* RTC_WAKEUP_SUPPORT */
00185     LL_RTC_WriteReg(RTCx, DR  ,     (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00186     /* Reset All CR bits except CR[2:0] */
00187 #if defined(RTC_WAKEUP_SUPPORT)
00188     LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
00189 #else
00190     LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
00191 #endif /* RTC_WAKEUP_SUPPORT */
00192     LL_RTC_WriteReg(RTCx, PRER,     (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
00193     LL_RTC_WriteReg(RTCx, ALRMAR,   0x00000000U);
00194     LL_RTC_WriteReg(RTCx, ALRMBR,   0x00000000U);
00195     LL_RTC_WriteReg(RTCx, SHIFTR,   0x00000000U);
00196     LL_RTC_WriteReg(RTCx, CALR,     0x00000000U);
00197     LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
00198     LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
00199
00200     /* Reset ISR register and exit initialization mode */
00201     LL_RTC_WriteReg(RTCx, ISR,      0x00000000U);
00202
00203     /* Reset Tamper and alternate functions configuration register */
00204     LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U);
00205
00206     /* Reset Option register */
00207     LL_RTC_WriteReg(RTCx, OR, 0x00000000U);
00208
00209     /* Wait till the RTC RSF flag is set */
00210     status = LL_RTC_WaitForSynchro(RTCx);
00211   }
00212
00213   /* Enable the write protection for RTC registers */
00214   LL_RTC_EnableWriteProtection(RTCx);
00215
00216   return status;
00217 }
00218
00219 /**
00220   * @brief  Initializes the RTC registers according to the specified parameters
00221   *         in RTC_InitStruct.
00222   * @param  RTCx RTC Instance
00223   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
00224   *         the configuration information for the RTC peripheral.
00225   * @note   The RTC Prescaler register is write protected and can be written in
00226   *         initialization mode only.
00227   * @retval An ErrorStatus enumeration value:
00228   *          - SUCCESS: RTC registers are initialized
00229   *          - ERROR: RTC registers are not initialized
00230   */
00231 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
00232 {
00233   ErrorStatus status = ERROR;
00234
00235   /* Check the parameters */
00236   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00237   assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
00238   assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
00239   assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
00240
00241   /* Disable the write protection for RTC registers */
00242   LL_RTC_DisableWriteProtection(RTCx);
00243
00244   /* Set Initialization mode */
00245   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00246   {
00247     /* Set Hour Format */
00248     LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
00249
00250     /* Configure Synchronous and Asynchronous prescaler factor */
00251     LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
00252     LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
00253
00254     /* Exit Initialization mode */
00255     LL_RTC_DisableInitMode(RTCx);
00256
00257     status = SUCCESS;
00258   }
00259   /* Enable the write protection for RTC registers */
00260   LL_RTC_EnableWriteProtection(RTCx);
00261
00262   return status;
00263 }
00264
00265 /**
00266   * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
00267   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
00268   * @retval None
00269   */
00270 void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
00271 {
00272   /* Set RTC_InitStruct fields to default values */
00273   RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
00274   RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
00275   RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
00276 }
00277
00278 /**
00279   * @brief  Set the RTC current time.
00280   * @param  RTCx RTC Instance
00281   * @param  RTC_Format This parameter can be one of the following values:
00282   *         @arg @ref LL_RTC_FORMAT_BIN
00283   *         @arg @ref LL_RTC_FORMAT_BCD
00284   * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
00285   *                        the time configuration information for the RTC.
00286   * @retval An ErrorStatus enumeration value:
00287   *          - SUCCESS: RTC Time register is configured
00288   *          - ERROR: RTC Time register is not configured
00289   */
00290 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
00291 {
00292   ErrorStatus status = ERROR;
00293
00294   /* Check the parameters */
00295   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00296   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00297
00298   if (RTC_Format == LL_RTC_FORMAT_BIN)
00299   {
00300     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00301     {
00302       assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
00303       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00304     }
00305     else
00306     {
00307       RTC_TimeStruct->TimeFormat = 0x00U;
00308       assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
00309     }
00310     assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
00311     assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
00312   }
00313   else
00314   {
00315     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00316     {
00317       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00318       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00319     }
00320     else
00321     {
00322       RTC_TimeStruct->TimeFormat = 0x00U;
00323       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00324     }
00325     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
00326     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
00327   }
00328
00329   /* Disable the write protection for RTC registers */
00330   LL_RTC_DisableWriteProtection(RTCx);
00331
00332   /* Set Initialization mode */
00333   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00334   {
00335     /* Check the input parameters format */
00336     if (RTC_Format != LL_RTC_FORMAT_BIN)
00337     {
00338       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
00339                          RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
00340     }
00341     else
00342     {
00343       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
00344                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
00345                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
00346     }
00347
00348     /* Exit Initialization mode */
00349     LL_RTC_DisableInitMode(RTC);
00350
00351     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00352     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00353     {
00354       status = LL_RTC_WaitForSynchro(RTCx);
00355     }
00356     else
00357     {
00358       status = SUCCESS;
00359     }
00360   }
00361   /* Enable the write protection for RTC registers */
00362   LL_RTC_EnableWriteProtection(RTCx);
00363
00364   return status;
00365 }
00366
00367 /**
00368   * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
00369   * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
00370   * @retval None
00371   */
00372 void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
00373 {
00374   /* Time = 00h:00min:00sec */
00375   RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
00376   RTC_TimeStruct->Hours      = 0U;
00377   RTC_TimeStruct->Minutes    = 0U;
00378   RTC_TimeStruct->Seconds    = 0U;
00379 }
00380
00381 /**
00382   * @brief  Set the RTC current date.
00383   * @param  RTCx RTC Instance
00384   * @param  RTC_Format This parameter can be one of the following values:
00385   *         @arg @ref LL_RTC_FORMAT_BIN
00386   *         @arg @ref LL_RTC_FORMAT_BCD
00387   * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
00388   *                         the date configuration information for the RTC.
00389   * @retval An ErrorStatus enumeration value:
00390   *          - SUCCESS: RTC Day register is configured
00391   *          - ERROR: RTC Day register is not configured
00392   */
00393 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
00394 {
00395   ErrorStatus status = ERROR;
00396
00397   /* Check the parameters */
00398   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00399   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00400
00401   if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
00402   {
00403     RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
00404   }
00405   if (RTC_Format == LL_RTC_FORMAT_BIN)
00406   {
00407     assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
00408     assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
00409     assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
00410   }
00411   else
00412   {
00413     assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
00414     assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
00415     assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
00416   }
00417   assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
00418
00419   /* Disable the write protection for RTC registers */
00420   LL_RTC_DisableWriteProtection(RTCx);
00421
00422   /* Set Initialization mode */
00423   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00424   {
00425     /* Check the input parameters format */
00426     if (RTC_Format != LL_RTC_FORMAT_BIN)
00427     {
00428       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
00429     }
00430     else
00431     {
00432       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
00433                          __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
00434     }
00435
00436     /* Exit Initialization mode */
00437     LL_RTC_DisableInitMode(RTC);
00438
00439     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00440     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00441     {
00442       status = LL_RTC_WaitForSynchro(RTCx);
00443     }
00444     else
00445     {
00446       status = SUCCESS;
00447     }
00448   }
00449   /* Enable the write protection for RTC registers */
00450   LL_RTC_EnableWriteProtection(RTCx);
00451
00452   return status;
00453 }
00454
00455 /**
00456   * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
00457   * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
00458   * @retval None
00459   */
00460 void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
00461 {
00462   /* Monday, January 01 xx00 */
00463   RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
00464   RTC_DateStruct->Day     = 1U;
00465   RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
00466   RTC_DateStruct->Year    = 0U;
00467 }
00468
00469 /**
00470   * @brief  Set the RTC Alarm A.
00471   * @note   The Alarm register can only be written when the corresponding Alarm
00472   *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
00473   * @param  RTCx RTC Instance
00474   * @param  RTC_Format This parameter can be one of the following values:
00475   *         @arg @ref LL_RTC_FORMAT_BIN
00476   *         @arg @ref LL_RTC_FORMAT_BCD
00477   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00478   *                         contains the alarm configuration parameters.
00479   * @retval An ErrorStatus enumeration value:
00480   *          - SUCCESS: ALARMA registers are configured
00481   *          - ERROR: ALARMA registers are not configured
00482   */
00483 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00484 {
00485   /* Check the parameters */
00486   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00487   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00488   assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
00489   assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00490
00491   if (RTC_Format == LL_RTC_FORMAT_BIN)
00492   {
00493     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00494     {
00495       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00496       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00497     }
00498     else
00499     {
00500       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00501       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00502     }
00503     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00504     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00505
00506     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00507     {
00508       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00509     }
00510     else
00511     {
00512       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00513     }
00514   }
00515   else
00516   {
00517     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00518     {
00519       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00520       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00521     }
00522     else
00523     {
00524       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00525       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00526     }
00527
00528     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00529     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00530
00531     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00532     {
00533       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00534     }
00535     else
00536     {
00537       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00538     }
00539   }
00540
00541   /* Disable the write protection for RTC registers */
00542   LL_RTC_DisableWriteProtection(RTCx);
00543
00544   /* Select weekday selection */
00545   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00546   {
00547     /* Set the date for ALARM */
00548     LL_RTC_ALMA_DisableWeekday(RTCx);
00549     if (RTC_Format != LL_RTC_FORMAT_BIN)
00550     {
00551       LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00552     }
00553     else
00554     {
00555       LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00556     }
00557   }
00558   else
00559   {
00560     /* Set the week day for ALARM */
00561     LL_RTC_ALMA_EnableWeekday(RTCx);
00562     LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00563   }
00564
00565   /* Configure the Alarm register */
00566   if (RTC_Format != LL_RTC_FORMAT_BIN)
00567   {
00568     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00569                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00570   }
00571   else
00572   {
00573     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00574                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00575                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00576                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00577   }
00578   /* Set ALARM mask */
00579   LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00580
00581   /* Enable the write protection for RTC registers */
00582   LL_RTC_EnableWriteProtection(RTCx);
00583
00584   return SUCCESS;
00585 }
00586
00587 /**
00588   * @brief  Set the RTC Alarm B.
00589   * @note   The Alarm register can only be written when the corresponding Alarm
00590   *         is disabled (@ref LL_RTC_ALMB_Disable function).
00591   * @param  RTCx RTC Instance
00592   * @param  RTC_Format This parameter can be one of the following values:
00593   *         @arg @ref LL_RTC_FORMAT_BIN
00594   *         @arg @ref LL_RTC_FORMAT_BCD
00595   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00596   *                         contains the alarm configuration parameters.
00597   * @retval An ErrorStatus enumeration value:
00598   *          - SUCCESS: ALARMB registers are configured
00599   *          - ERROR: ALARMB registers are not configured
00600   */
00601 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00602 {
00603   /* Check the parameters */
00604   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00605   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00606   assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
00607   assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00608
00609   if (RTC_Format == LL_RTC_FORMAT_BIN)
00610   {
00611     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00612     {
00613       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00614       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00615     }
00616     else
00617     {
00618       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00619       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00620     }
00621     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00622     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00623
00624     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00625     {
00626       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00627     }
00628     else
00629     {
00630       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00631     }
00632   }
00633   else
00634   {
00635     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00636     {
00637       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00638       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00639     }
00640     else
00641     {
00642       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00643       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00644     }
00645
00646     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00647     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00648
00649     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00650     {
00651       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00652     }
00653     else
00654     {
00655       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00656     }
00657   }
00658
00659   /* Disable the write protection for RTC registers */
00660   LL_RTC_DisableWriteProtection(RTCx);
00661
00662   /* Select weekday selection */
00663   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00664   {
00665     /* Set the date for ALARM */
00666     LL_RTC_ALMB_DisableWeekday(RTCx);
00667     if (RTC_Format != LL_RTC_FORMAT_BIN)
00668     {
00669       LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00670     }
00671     else
00672     {
00673       LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00674     }
00675   }
00676   else
00677   {
00678     /* Set the week day for ALARM */
00679     LL_RTC_ALMB_EnableWeekday(RTCx);
00680     LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00681   }
00682
00683   /* Configure the Alarm register */
00684   if (RTC_Format != LL_RTC_FORMAT_BIN)
00685   {
00686     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00687                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00688   }
00689   else
00690   {
00691     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00692                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00693                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00694                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00695   }
00696   /* Set ALARM mask */
00697   LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00698
00699   /* Enable the write protection for RTC registers */
00700   LL_RTC_EnableWriteProtection(RTCx);
00701
00702   return SUCCESS;
00703 }
00704
00705 /**
00706   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00707   *         Day = 1st day of the month/Mask = all fields are masked).
00708   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00709   * @retval None
00710   */
00711 void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00712 {
00713   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00714   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
00715   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00716   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00717   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00718
00719   /* Alarm Day Settings : Day = 1st day of the month */
00720   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
00721   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00722
00723   /* Alarm Masks Settings : Mask =  all fields are not masked */
00724   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
00725 }
00726
00727 /**
00728   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00729   *         Day = 1st day of the month/Mask = all fields are masked).
00730   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00731   * @retval None
00732   */
00733 void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00734 {
00735   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00736   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
00737   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00738   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00739   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00740
00741   /* Alarm Day Settings : Day = 1st day of the month */
00742   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
00743   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00744
00745   /* Alarm Masks Settings : Mask =  all fields are not masked */
00746   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
00747 }
00748
00749 /**
00750   * @brief  Enters the RTC Initialization mode.
00751   * @note   The RTC Initialization mode is write protected, use the
00752   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00753   * @param  RTCx RTC Instance
00754   * @retval An ErrorStatus enumeration value:
00755   *          - SUCCESS: RTC is in Init mode
00756   *          - ERROR: RTC is not in Init mode
00757   */
00758 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
00759 {
00760   __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
00761   ErrorStatus status = SUCCESS;
00762   uint32_t tmp = 0U;
00763
00764   /* Check the parameter */
00765   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00766
00767   /* Check if the Initialization mode is set */
00768   if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
00769   {
00770     /* Set the Initialization mode */
00771     LL_RTC_EnableInitMode(RTCx);
00772
00773     /* Wait till RTC is in INIT state and if Time out is reached exit */
00774     tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00775     while ((timeout != 0U) && (tmp != 1U))
00776     {
00777       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00778       {
00779         timeout --;
00780       }
00781       tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00782       if (timeout == 0U)
00783       {
00784         status = ERROR;
00785       }
00786     }
00787   }
00788   return status;
00789 }
00790
00791 /**
00792   * @brief  Exit the RTC Initialization mode.
00793   * @note   When the initialization sequence is complete, the calendar restarts
00794   *         counting after 4 RTCCLK cycles.
00795   * @note   The RTC Initialization mode is write protected, use the
00796   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00797   * @param  RTCx RTC Instance
00798   * @retval An ErrorStatus enumeration value:
00799   *          - SUCCESS: RTC exited from in Init mode
00800   *          - ERROR: Not applicable
00801   */
00802 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
00803 {
00804   /* Check the parameter */
00805   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00806
00807   /* Disable initialization mode */
00808   LL_RTC_DisableInitMode(RTCx);
00809
00810   return SUCCESS;
00811 }
00812
00813 /**
00814   * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
00815   *         synchronized with RTC APB clock.
00816   * @note   The RTC Resynchronization mode is write protected, use the
00817   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00818   * @note   To read the calendar through the shadow registers after Calendar
00819   *         initialization, calendar update or after wakeup from low power modes
00820   *         the software must first clear the RSF flag.
00821   *         The software must then wait until it is set again before reading
00822   *         the calendar, which means that the calendar registers have been
00823   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
00824   * @param  RTCx RTC Instance
00825   * @retval An ErrorStatus enumeration value:
00826   *          - SUCCESS: RTC registers are synchronised
00827   *          - ERROR: RTC registers are not synchronised
00828   */
00829 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
00830 {
00831   __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
00832   ErrorStatus status = SUCCESS;
00833   uint32_t tmp = 0U;
00834
00835   /* Check the parameter */
00836   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00837
00838   /* Clear RSF flag */
00839   LL_RTC_ClearFlag_RS(RTCx);
00840
00841   /* Wait the registers to be synchronised */
00842   tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00843   while ((timeout != 0U) && (tmp != 0U))
00844   {
00845     if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00846     {
00847       timeout--;
00848     }
00849     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00850     if (timeout == 0U)
00851     {
00852       status = ERROR;
00853     }
00854   }
00855
00856   if (status != ERROR)
00857   {
00858     timeout = RTC_SYNCHRO_TIMEOUT;
00859     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00860     while ((timeout != 0U) && (tmp != 1U))
00861     {
00862       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00863       {
00864         timeout--;
00865       }
00866       tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00867       if (timeout == 0U)
00868       {
00869         status = ERROR;
00870       }
00871     }
00872   }
00873
00874   return (status);
00875 }
00876
00877 /**
00878   * @}
00879   */
00880
00881 /**
00882   * @}
00883   */
00884
00885 /**
00886   * @}
00887   */
00888
00889 #endif /* defined(RTC) */
00890
00891 /**
00892   * @}
00893   */
00894
00895 #endif /* USE_FULL_LL_DRIVER */
00896
00897 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_rtc.h Source File

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stm32l4xx_ll_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_rtc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    $DATE$
00007   * @brief   Header file of RTC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_RTC_H
00040 #define __STM32L4xx_LL_RTC_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(RTC)
00054
00055 /** @defgroup RTC_LL RTC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /** @defgroup RTC_LL_Private_Constants RTC Private Constants
00063   * @{
00064   */
00065 /* Masks Definition */
00066 #define RTC_INIT_MASK                 ((uint32_t)0xFFFFFFFFU)
00067 #define RTC_RSF_MASK                  ((uint32_t)0xFFFFFF5FU)
00068
00069 /* Write protection defines */
00070 #define RTC_WRITE_PROTECTION_DISABLE  ((uint8_t)0xFFU)
00071 #define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
00072 #define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
00073
00074 /* Defines used for the bit position in the register and perform offsets */
00075 #define RTC_POSITION_TR_HT            (uint32_t)POSITION_VAL(RTC_TR_HT)
00076 #define RTC_POSITION_TR_HU            (uint32_t)POSITION_VAL(RTC_TR_HU)
00077 #define RTC_POSITION_TR_MT            (uint32_t)POSITION_VAL(RTC_TR_MNT)
00078 #define RTC_POSITION_TR_MU            (uint32_t)POSITION_VAL(RTC_TR_MNU)
00079 #define RTC_POSITION_TR_ST            (uint32_t)POSITION_VAL(RTC_TR_ST)
00080 #define RTC_POSITION_TR_SU            (uint32_t)POSITION_VAL(RTC_TR_SU)
00081 #define RTC_POSITION_DR_YT            (uint32_t)POSITION_VAL(RTC_DR_YT)
00082 #define RTC_POSITION_DR_YU            (uint32_t)POSITION_VAL(RTC_DR_YU)
00083 #define RTC_POSITION_DR_MT            (uint32_t)POSITION_VAL(RTC_DR_MT)
00084 #define RTC_POSITION_DR_MU            (uint32_t)POSITION_VAL(RTC_DR_MU)
00085 #define RTC_POSITION_DR_DT            (uint32_t)POSITION_VAL(RTC_DR_DT)
00086 #define RTC_POSITION_DR_DU            (uint32_t)POSITION_VAL(RTC_DR_DU)
00087 #define RTC_POSITION_DR_WDU           (uint32_t)POSITION_VAL(RTC_DR_WDU)
00088 #define RTC_POSITION_ALMA_DT          (uint32_t)POSITION_VAL(RTC_ALRMAR_DT)
00089 #define RTC_POSITION_ALMA_DU          (uint32_t)POSITION_VAL(RTC_ALRMAR_DU)
00090 #define RTC_POSITION_ALMA_HT          (uint32_t)POSITION_VAL(RTC_ALRMAR_HT)
00091 #define RTC_POSITION_ALMA_HU          (uint32_t)POSITION_VAL(RTC_ALRMAR_HU)
00092 #define RTC_POSITION_ALMA_MT          (uint32_t)POSITION_VAL(RTC_ALRMAR_MNT)
00093 #define RTC_POSITION_ALMA_MU          (uint32_t)POSITION_VAL(RTC_ALRMAR_MNU)
00094 #define RTC_POSITION_ALMA_SU          (uint32_t)POSITION_VAL(RTC_ALRMAR_SU)
00095 #define RTC_POSITION_ALMA_ST          (uint32_t)POSITION_VAL(RTC_ALRMAR_ST)
00096 #define RTC_POSITION_ALMB_DT          (uint32_t)POSITION_VAL(RTC_ALRMBR_DT)
00097 #define RTC_POSITION_ALMB_DU          (uint32_t)POSITION_VAL(RTC_ALRMBR_DU)
00098 #define RTC_POSITION_ALMB_HT          (uint32_t)POSITION_VAL(RTC_ALRMBR_HT)
00099 #define RTC_POSITION_ALMB_HU          (uint32_t)POSITION_VAL(RTC_ALRMBR_HU)
00100 #define RTC_POSITION_ALMB_MT          (uint32_t)POSITION_VAL(RTC_ALRMBR_MNT)
00101 #define RTC_POSITION_ALMB_MU          (uint32_t)POSITION_VAL(RTC_ALRMBR_MNU)
00102 #define RTC_POSITION_ALMB_SU          (uint32_t)POSITION_VAL(RTC_ALRMBR_SU)
00103 #define RTC_POSITION_ALMB_ST          (uint32_t)POSITION_VAL(RTC_ALRMBR_ST)
00104 #define RTC_POSITION_PRER_PREDIV_A    (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)
00105 #define RTC_POSITION_ALMA_MASKSS      (uint32_t)POSITION_VAL(RTC_ALRMASSR_MASKSS)
00106 #define RTC_POSITION_ALMB_MASKSS      (uint32_t)POSITION_VAL(RTC_ALRMBSSR_MASKSS)
00107 #define RTC_POSITION_TS_HU            (uint32_t)POSITION_VAL(RTC_TSTR_HU)
00108 #define RTC_POSITION_TS_MNU           (uint32_t)POSITION_VAL(RTC_TSTR_MNU)
00109 #define RTC_POSITION_TS_WDU           (uint32_t)POSITION_VAL(RTC_TSDR_WDU)
00110 #define RTC_POSITION_TS_MU            (uint32_t)POSITION_VAL(RTC_TSDR_MU)
00111
00112 /* Defines used to combine date & time */
00113 #define RTC_OFFSET_WEEKDAY            (uint32_t)24U
00114 #define RTC_OFFSET_DAY                (uint32_t)16U
00115 #define RTC_OFFSET_MONTH              (uint32_t)8U
00116 #define RTC_OFFSET_HOUR               (uint32_t)16U
00117 #define RTC_OFFSET_MINUTE             (uint32_t)8U
00118
00119 /**
00120   * @}
00121   */
00122
00123 /* Private macros ------------------------------------------------------------*/
00124 #if defined(USE_FULL_LL_DRIVER)
00125 /** @defgroup RTC_LL_Private_Macros RTC Private Macros
00126   * @{
00127   */
00128 /**
00129   * @}
00130   */
00131 #endif /*USE_FULL_LL_DRIVER*/
00132
00133 /* Exported types ------------------------------------------------------------*/
00134 #if defined(USE_FULL_LL_DRIVER)
00135 /** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
00136   * @{
00137   */
00138
00139 /**
00140   * @brief  RTC Init structures definition
00141   */
00142 typedef struct
00143 {
00144   uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
00145                               This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
00146
00147                               This feature can be modified afterwards using unitary function
00148                               @ref LL_RTC_SetHourFormat(). */
00149
00150   uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
00151                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
00152
00153                               This feature can be modified afterwards using unitary function
00154                               @ref LL_RTC_SetAsynchPrescaler(). */
00155
00156   uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
00157                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
00158
00159                               This feature can be modified afterwards using unitary function
00160                               @ref LL_RTC_SetSynchPrescaler(). */
00161 } LL_RTC_InitTypeDef;
00162
00163 /**
00164   * @brief  RTC Time structure definition
00165   */
00166 typedef struct
00167 {
00168   uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
00169                             This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
00170
00171                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
00172
00173   uint8_t Hours;       /*!< Specifies the RTC Time Hours.
00174                             This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
00175                             This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
00176
00177                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
00178
00179   uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
00180                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00181
00182                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
00183
00184   uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
00185                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00186
00187                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
00188 } LL_RTC_TimeTypeDef;
00189
00190 /**
00191   * @brief  RTC Date structure definition
00192   */
00193 typedef struct
00194 {
00195   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00196                          This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
00197
00198                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
00199
00200   uint8_t Month;    /*!< Specifies the RTC Date Month.
00201                          This parameter can be a value of @ref RTC_LL_EC_MONTH
00202
00203                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
00204
00205   uint8_t Day;      /*!< Specifies the RTC Date Day.
00206                          This parameter must be a number between Min_Data = 1 and Max_Data = 31
00207
00208                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
00209
00210   uint8_t Year;     /*!< Specifies the RTC Date Year.
00211                          This parameter must be a number between Min_Data = 0 and Max_Data = 99
00212
00213                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
00214 } LL_RTC_DateTypeDef;
00215
00216 /**
00217   * @brief  RTC Alarm structure definition
00218   */
00219 typedef struct
00220 {
00221   LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
00222
00223   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00224                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
00225
00226                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
00227                                       or @ref LL_RTC_ALMB_SetMask() for ALARM B
00228                                  */
00229
00230   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
00231                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
00232
00233                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
00234                                       for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
00235                                  */
00236
00237   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
00238                                       If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.
00239
00240                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
00241                                       for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
00242
00243                                       If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
00244
00245                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
00246                                       for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
00247                                  */
00248 } LL_RTC_AlarmTypeDef;
00249
00250 /**
00251   * @}
00252   */
00253 #endif /* USE_FULL_LL_DRIVER */
00254
00255 /* Exported constants --------------------------------------------------------*/
00256 /** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
00257   * @{
00258   */
00259
00260 #if defined(USE_FULL_LL_DRIVER)
00261 /** @defgroup RTC_LL_EC_FORMAT FORMAT
00262   * @{
00263   */
00264 #define LL_RTC_FORMAT_BIN                  ((uint32_t)0x000000000U) /*!< Binary data format */
00265 #define LL_RTC_FORMAT_BCD                  ((uint32_t)0x000000001U) /*!< BCD data format */
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
00271   * @{
00272   */
00273 #define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    ((uint32_t)0x00000000U) /*!< Alarm A Date is selected */
00274 #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
00275 /**
00276   * @}
00277   */
00278
00279 /** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
00280   * @{
00281   */
00282 #define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    ((uint32_t)0x00000000U) /*!< Alarm B Date is selected */
00283 #define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
00284 /**
00285   * @}
00286   */
00287
00288 #endif /* USE_FULL_LL_DRIVER */
00289
00290 /** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
00291   * @brief    Flags defines which can be used with LL_RTC_ReadReg function
00292   * @{
00293   */
00294 #define LL_RTC_ISR_ITSF                    RTC_ISR_ITSF
00295 #define LL_RTC_ISR_RECALPF                 RTC_ISR_RECALPF
00296 #define LL_RTC_ISR_TAMP3F                  RTC_ISR_TAMP3F
00297 #define LL_RTC_ISR_TAMP2F                  RTC_ISR_TAMP2F
00298 #define LL_RTC_ISR_TAMP1F                  RTC_ISR_TAMP1F
00299 #define LL_RTC_ISR_TSOVF                   RTC_ISR_TSOVF
00300 #define LL_RTC_ISR_TSF                     RTC_ISR_TSF
00301 #define LL_RTC_ISR_WUTF                    RTC_ISR_WUTF
00302 #define LL_RTC_ISR_ALRBF                   RTC_ISR_ALRBF
00303 #define LL_RTC_ISR_ALRAF                   RTC_ISR_ALRAF
00304 #define LL_RTC_ISR_INITF                   RTC_ISR_INITF
00305 #define LL_RTC_ISR_RSF                     RTC_ISR_RSF
00306 #define LL_RTC_ISR_INITS                   RTC_ISR_INITS
00307 #define LL_RTC_ISR_SHPF                    RTC_ISR_SHPF
00308 #define LL_RTC_ISR_WUTWF                   RTC_ISR_WUTWF
00309 #define LL_RTC_ISR_ALRBWF                  RTC_ISR_ALRBWF
00310 #define LL_RTC_ISR_ALRAWF                  RTC_ISR_ALRAWF
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup RTC_LL_EC_IT IT Defines
00316   * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
00317   * @{
00318   */
00319 #define LL_RTC_CR_TSIE                     RTC_CR_TSIE
00320 #define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
00321 #define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
00322 #define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
00323 #define LL_RTC_TAMPCR_TAMP3IE              RTC_TAMPCR_TAMP3IE
00324 #define LL_RTC_TAMPCR_TAMP2IE              RTC_TAMPCR_TAMP2IE
00325 #define LL_RTC_TAMPCR_TAMP1IE              RTC_TAMPCR_TAMP1IE
00326 #define LL_RTC_TAMPCR_TAMPIE               RTC_TAMPCR_TAMPIE
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
00332   * @{
00333   */
00334 #define LL_RTC_WEEKDAY_MONDAY              ((uint8_t)0x01U) /*!< Monday    */
00335 #define LL_RTC_WEEKDAY_TUESDAY             ((uint8_t)0x02U) /*!< Tuesday   */
00336 #define LL_RTC_WEEKDAY_WEDNESDAY           ((uint8_t)0x03U) /*!< Wednesday */
00337 #define LL_RTC_WEEKDAY_THURSDAY            ((uint8_t)0x04U) /*!< Thrusday  */
00338 #define LL_RTC_WEEKDAY_FRIDAY              ((uint8_t)0x05U) /*!< Friday    */
00339 #define LL_RTC_WEEKDAY_SATURDAY            ((uint8_t)0x06U) /*!< Saturday  */
00340 #define LL_RTC_WEEKDAY_SUNDAY              ((uint8_t)0x07U) /*!< Sunday    */
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup RTC_LL_EC_MONTH  MONTH
00346   * @{
00347   */
00348 #define LL_RTC_MONTH_JANUARY               ((uint8_t)0x01U)  /*!< January   */
00349 #define LL_RTC_MONTH_FEBRUARY              ((uint8_t)0x02U)  /*!< February  */
00350 #define LL_RTC_MONTH_MARCH                 ((uint8_t)0x03U)  /*!< March     */
00351 #define LL_RTC_MONTH_APRIL                 ((uint8_t)0x04U)  /*!< April     */
00352 #define LL_RTC_MONTH_MAY                   ((uint8_t)0x05U)  /*!< May       */
00353 #define LL_RTC_MONTH_JUNE                  ((uint8_t)0x06U)  /*!< June      */
00354 #define LL_RTC_MONTH_JULY                  ((uint8_t)0x07U)  /*!< July      */
00355 #define LL_RTC_MONTH_AUGUST                ((uint8_t)0x08U)  /*!< August    */
00356 #define LL_RTC_MONTH_SEPTEMBER             ((uint8_t)0x09U)  /*!< September */
00357 #define LL_RTC_MONTH_OCTOBER               ((uint8_t)0x10U)  /*!< October   */
00358 #define LL_RTC_MONTH_NOVEMBER              ((uint8_t)0x11U)  /*!< November  */
00359 #define LL_RTC_MONTH_DECEMBER              ((uint8_t)0x12U)  /*!< December  */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
00365   * @{
00366   */
00367 #define LL_RTC_HOURFORMAT_24HOUR           (uint32_t)0x00000000U /*!< 24 hour/day format */
00368 #define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
00374   * @{
00375   */
00376 #define LL_RTC_ALARMOUT_DISABLE            ((uint32_t)0x00000000U) /*!< Output disabled */
00377 #define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
00378 #define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
00379 #define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
00380 /**
00381   * @}
00382   */
00383
00384 /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
00385   * @{
00386   */
00387 #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  (uint32_t)0x00000000U  /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
00388 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
00389 /**
00390   * @}
00391   */
00392
00393 /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
00394   * @{
00395   */
00396 #define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     (uint32_t)0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
00397 #define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
00403   * @{
00404   */
00405 #define LL_RTC_TIME_FORMAT_AM_OR_24        (uint32_t)0x00000000U /*!< AM or 24-hour format */
00406 #define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
00412   * @{
00413   */
00414 #define LL_RTC_SHIFT_SECOND_DELAY          (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
00415 #define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
00416 /**
00417   * @}
00418   */
00419
00420 /** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
00421   * @{
00422   */
00423 #define LL_RTC_ALMA_MASK_NONE              ((uint32_t)0x00000000U) /*!< No masks applied on Alarm A*/
00424 #define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
00425 #define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
00426 #define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
00427 #define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */
00428 #define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
00434   * @{
00435   */
00436 #define LL_RTC_ALMA_TIME_FORMAT_AM         (uint32_t)0x00000000U /*!< AM or 24-hour format */
00437 #define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
00438 /**
00439   * @}
00440   */
00441
00442 /** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
00443   * @{
00444   */
00445 #define LL_RTC_ALMB_MASK_NONE              ((uint32_t)0x00000000U) /*!< No masks applied on Alarm B*/
00446 #define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
00447 #define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
00448 #define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
00449 #define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */
00450 #define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
00456   * @{
00457   */
00458 #define LL_RTC_ALMB_TIME_FORMAT_AM         (uint32_t)0x00000000U /*!< AM or 24-hour format */
00459 #define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
00465   * @{
00466   */
00467 #define LL_RTC_TIMESTAMP_EDGE_RISING       (uint32_t)0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
00468 #define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
00474   * @{
00475   */
00476 #define LL_RTC_TS_TIME_FORMAT_AM           (uint32_t)0x00000000U /*!< AM or 24-hour format */
00477 #define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
00478 /**
00479   * @}
00480   */
00481
00482 /** @defgroup RTC_LL_EC_TAMPER  TAMPER
00483   * @{
00484   */
00485 #if defined(RTC_TAMPER1_SUPPORT)
00486 #define LL_RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */
00487 #endif /* RTC_TAMPER1_SUPPORT */
00488 #if defined(RTC_TAMPER2_SUPPORT)
00489 #define LL_RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */
00490 #endif /* RTC_TAMPER2_SUPPORT */
00491 #if defined(RTC_TAMPER3_SUPPORT)
00492 #define LL_RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */
00493 #endif /* RTC_TAMPER3_SUPPORT */
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
00499   * @{
00500   */
00501 #if defined(RTC_TAMPER1_SUPPORT)
00502 #define LL_RTC_TAMPER_MASK_TAMPER1         RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
00503 #endif /* RTC_TAMPER1_SUPPORT */
00504 #if defined(RTC_TAMPER2_SUPPORT)
00505 #define LL_RTC_TAMPER_MASK_TAMPER2         RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00506 #endif /* RTC_TAMPER2_SUPPORT */
00507 #if defined(RTC_TAMPER3_SUPPORT)
00508 #define LL_RTC_TAMPER_MASK_TAMPER3         RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
00509 #endif /* RTC_TAMPER3_SUPPORT */
00510 /**
00511   * @}
00512   */
00513
00514 /** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
00515   * @{
00516   */
00517 #if defined(RTC_TAMPER1_SUPPORT)
00518 #define LL_RTC_TAMPER_NOERASE_TAMPER1      RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
00519 #endif /* RTC_TAMPER1_SUPPORT */
00520 #if defined(RTC_TAMPER2_SUPPORT)
00521 #define LL_RTC_TAMPER_NOERASE_TAMPER2      RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
00522 #endif /* RTC_TAMPER2_SUPPORT */
00523 #if defined(RTC_TAMPER3_SUPPORT)
00524 #define LL_RTC_TAMPER_NOERASE_TAMPER3      RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
00525 #endif /* RTC_TAMPER3_SUPPORT */
00526 /**
00527   * @}
00528   */
00529
00530 #if defined(RTC_TAMPCR_TAMPPRCH)
00531 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
00532   * @{
00533   */
00534 #define LL_RTC_TAMPER_DURATION_1RTCCLK     ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
00535 #define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAMPCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
00536 #define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAMPCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
00537 #define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAMPCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
00538 /**
00539   * @}
00540   */
00541 #endif /* RTC_TAMPCR_TAMPPRCH */
00542
00543 #if defined(RTC_TAMPCR_TAMPFLT)
00544 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
00545   * @{
00546   */
00547 #define LL_RTC_TAMPER_FILTER_DISABLE       ((uint32_t)0x00000000U)  /*!< Tamper filter is disabled */
00548 #define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
00549 #define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
00550 #define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
00551 /**
00552   * @}
00553   */
00554 #endif /* RTC_TAMPCR_TAMPFLT */
00555
00556 #if defined(RTC_TAMPCR_TAMPFREQ)
00557 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
00558   * @{
00559   */
00560 #define LL_RTC_TAMPER_SAMPLFREQDIV_32768   ((uint32_t)0x00000000U)                          /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
00561 #define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAMPCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
00562 #define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAMPCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
00563 #define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
00564 #define LL_RTC_TAMPER_SAMPLFREQDIV_2048    RTC_TAMPCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
00565 #define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
00566 #define LL_RTC_TAMPER_SAMPLFREQDIV_512     (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
00567 #define LL_RTC_TAMPER_SAMPLFREQDIV_256     RTC_TAMPCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
00568 /**
00569   * @}
00570   */
00571 #endif /* RTC_TAMPCR_TAMPFREQ */
00572
00573 /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
00574   * @{
00575   */
00576 #if defined(RTC_TAMPER1_SUPPORT)
00577 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00578 #endif /* RTC_TAMPER1_SUPPORT */
00579 #if defined(RTC_TAMPER2_SUPPORT)
00580 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00581 #endif /* RTC_TAMPER2_SUPPORT */
00582 #if defined(RTC_TAMPER3_SUPPORT)
00583 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00584 #endif /* RTC_TAMPER3_SUPPORT */
00585 /**
00586   * @}
00587   */
00588
00589 /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
00590   * @{
00591   */
00592 #define LL_RTC_WAKEUPCLOCK_DIV_16          ((uint32_t)0x00000000U)               /*!< RTC/16 clock is selected */
00593 #define LL_RTC_WAKEUPCLOCK_DIV_8           (RTC_CR_WUCKSEL_0)                    /*!< RTC/8 clock is selected */
00594 #define LL_RTC_WAKEUPCLOCK_DIV_4           (RTC_CR_WUCKSEL_1)                    /*!< RTC/4 clock is selected */
00595 #define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
00596 #define LL_RTC_WAKEUPCLOCK_CKSPRE          (RTC_CR_WUCKSEL_2)                    /*!< ck_spre (usually 1 Hz) clock is selected */
00597 #define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
00598 /**
00599   * @}
00600   */
00601
00602 #if defined(RTC_BACKUP_SUPPORT)
00603 /** @defgroup RTC_LL_EC_BKP  BACKUP
00604   * @{
00605   */
00606 #define LL_RTC_BKP_DR0                     ((uint32_t)0x00000000U)
00607 #define LL_RTC_BKP_DR1                     ((uint32_t)0x00000001U)
00608 #define LL_RTC_BKP_DR2                     ((uint32_t)0x00000002U)
00609 #define LL_RTC_BKP_DR3                     ((uint32_t)0x00000003U)
00610 #define LL_RTC_BKP_DR4                     ((uint32_t)0x00000004U)
00611 #if RTC_BKP_NUMBER > 5
00612 #define LL_RTC_BKP_DR5                     ((uint32_t)0x00000005U)
00613 #define LL_RTC_BKP_DR6                     ((uint32_t)0x00000006U)
00614 #define LL_RTC_BKP_DR7                     ((uint32_t)0x00000007U)
00615 #define LL_RTC_BKP_DR8                     ((uint32_t)0x00000008U)
00616 #define LL_RTC_BKP_DR9                     ((uint32_t)0x00000009U)
00617 #define LL_RTC_BKP_DR10                    ((uint32_t)0x0000000AU)
00618 #define LL_RTC_BKP_DR11                    ((uint32_t)0x0000000BU)
00619 #define LL_RTC_BKP_DR12                    ((uint32_t)0x0000000CU)
00620 #define LL_RTC_BKP_DR13                    ((uint32_t)0x0000000DU)
00621 #define LL_RTC_BKP_DR14                    ((uint32_t)0x0000000EU)
00622 #define LL_RTC_BKP_DR15                    ((uint32_t)0x0000000FU)
00623 #endif /* RTC_BKP_NUMBER > 5 */
00624
00625 #if RTC_BKP_NUMBER > 16
00626 #define LL_RTC_BKP_DR16                    ((uint32_t)0x00000010U)
00627 #define LL_RTC_BKP_DR17                    ((uint32_t)0x00000011U)
00628 #define LL_RTC_BKP_DR18                    ((uint32_t)0x00000012U)
00629 #define LL_RTC_BKP_DR19                    ((uint32_t)0x00000013U)
00630 #endif /* RTC_BKP_NUMBER > 16 */
00631
00632 #if RTC_BKP_NUMBER > 20
00633 #define LL_RTC_BKP_DR20                    ((uint32_t)0x00000014U)
00634 #define LL_RTC_BKP_DR21                    ((uint32_t)0x00000015U)
00635 #define LL_RTC_BKP_DR22                    ((uint32_t)0x00000016U)
00636 #define LL_RTC_BKP_DR23                    ((uint32_t)0x00000017U)
00637 #define LL_RTC_BKP_DR24                    ((uint32_t)0x00000018U)
00638 #define LL_RTC_BKP_DR25                    ((uint32_t)0x00000019U)
00639 #define LL_RTC_BKP_DR26                    ((uint32_t)0x0000001AU)
00640 #define LL_RTC_BKP_DR27                    ((uint32_t)0x0000001BU)
00641 #define LL_RTC_BKP_DR28                    ((uint32_t)0x0000001CU)
00642 #define LL_RTC_BKP_DR29                    ((uint32_t)0x0000001DU)
00643 #define LL_RTC_BKP_DR30                    ((uint32_t)0x0000001EU)
00644 #define LL_RTC_BKP_DR31                    ((uint32_t)0x0000001FU)
00645 #endif /* RTC_BKP_NUMBER > 20 */
00646 /**
00647   * @}
00648   */
00649 #endif /* RTC_BACKUP_SUPPORT */
00650
00651 /** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
00652   * @{
00653   */
00654 #define LL_RTC_CALIB_OUTPUT_NONE           (uint32_t)0x00000000U       /*!< Calibration output disabled */
00655 #define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */
00656 #define LL_RTC_CALIB_OUTPUT_512HZ          (RTC_CR_COE)                /*!< Calibration output is 1 Hz */
00657 /**
00658   * @}
00659   */
00660
00661 /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion
00662   * @{
00663   */
00664 #define LL_RTC_CALIB_INSERTPULSE_NONE      (uint32_t)0x00000000U /*!< No RTCCLK pulses are added */
00665 #define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
00671   * @{
00672   */
00673 #define LL_RTC_CALIB_PERIOD_32SEC          (uint32_t)0x00000000U /*!< Use a 32-second calibration cycle period */
00674 #define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
00675 #define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
00676 /**
00677   * @}
00678   */
00679
00680 /**
00681   * @}
00682   */
00683
00684 /* Exported macro ------------------------------------------------------------*/
00685 /** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
00686   * @{
00687   */
00688
00689 /** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
00690   * @{
00691   */
00692
00693 /**
00694   * @brief  Write a value in RTC register
00695   * @param  __INSTANCE__ RTC Instance
00696   * @param  __REG__ Register to be written
00697   * @param  __VALUE__ Value to be written in the register
00698   * @retval None
00699   */
00700 #define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00701
00702 /**
00703   * @brief  Read a value in RTC register
00704   * @param  __INSTANCE__ RTC Instance
00705   * @param  __REG__ Register to be read
00706   * @retval Register value
00707   */
00708 #define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00709 /**
00710   * @}
00711   */
00712
00713 /** @defgroup RTC_LL_EM_Convert Convert helper Macros
00714   * @{
00715   */
00716
00717 /**
00718   * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
00719   * @param  __VALUE__ Byte to be converted
00720   * @retval Converted byte
00721   */
00722 #define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
00723
00724 /**
00725   * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
00726   * @param  __VALUE__ BCD value to be converted
00727   * @retval Converted byte
00728   */
00729 #define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
00730
00731 /**
00732   * @}
00733   */
00734
00735 /** @defgroup RTC_LL_EM_Date Date helper Macros
00736   * @{
00737   */
00738
00739 /**
00740   * @brief  Helper macro to retrieve weekday.
00741   * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
00742   * @retval Returned value can be one of the following values:
00743   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
00744   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
00745   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
00746   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
00747   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
00748   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
00749   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
00750   */
00751 #define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
00752
00753 /**
00754   * @brief  Helper macro to retrieve Year in BCD format
00755   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00756   * @retval Year in BCD format (0x00 . . . 0x99)
00757   */
00758 #define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
00759
00760 /**
00761   * @brief  Helper macro to retrieve Month in BCD format
00762   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00763   * @retval Returned value can be one of the following values:
00764   *         @arg @ref LL_RTC_MONTH_JANUARY
00765   *         @arg @ref LL_RTC_MONTH_FEBRUARY
00766   *         @arg @ref LL_RTC_MONTH_MARCH
00767   *         @arg @ref LL_RTC_MONTH_APRIL
00768   *         @arg @ref LL_RTC_MONTH_MAY
00769   *         @arg @ref LL_RTC_MONTH_JUNE
00770   *         @arg @ref LL_RTC_MONTH_JULY
00771   *         @arg @ref LL_RTC_MONTH_AUGUST
00772   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
00773   *         @arg @ref LL_RTC_MONTH_OCTOBER
00774   *         @arg @ref LL_RTC_MONTH_NOVEMBER
00775   *         @arg @ref LL_RTC_MONTH_DECEMBER
00776   */
00777 #define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
00778
00779 /**
00780   * @brief  Helper macro to retrieve Day in BCD format
00781   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00782   * @retval Day in BCD format (0x01 . . . 0x31)
00783   */
00784 #define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
00785
00786 /**
00787   * @}
00788   */
00789
00790 /** @defgroup RTC_LL_EM_Time Time helper Macros
00791   * @{
00792   */
00793
00794 /**
00795   * @brief  Helper macro to retrieve hour in BCD format
00796   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00797   * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
00798   */
00799 #define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
00800
00801 /**
00802   * @brief  Helper macro to retrieve minute in BCD format
00803   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00804   * @retval Minutes in BCD format (0x00. . .0x59)
00805   */
00806 #define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
00807
00808 /**
00809   * @brief  Helper macro to retrieve second in BCD format
00810   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00811   * @retval Seconds in  format (0x00. . .0x59)
00812   */
00813 #define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
00814
00815 /**
00816   * @}
00817   */
00818
00819 /**
00820   * @}
00821   */
00822
00823 /* Exported functions --------------------------------------------------------*/
00824 /** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
00825   * @{
00826   */
00827
00828 /** @defgroup RTC_LL_EF_Configuration Configuration
00829   * @{
00830   */
00831
00832 /**
00833   * @brief  Set Hours format (24 hour/day or AM/PM hour format)
00834   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00835   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00836   * @rmtoll CR           FMT           LL_RTC_SetHourFormat
00837   * @param  RTCx RTC Instance
00838   * @param  HourFormat This parameter can be one of the following values:
00839   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00840   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00841   * @retval None
00842   */
00843 __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
00844 {
00845   MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
00846 }
00847
00848 /**
00849   * @brief  Get Hours format (24 hour/day or AM/PM hour format)
00850   * @rmtoll CR           FMT           LL_RTC_GetHourFormat
00851   * @param  RTCx RTC Instance
00852   * @retval Returned value can be one of the following values:
00853   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00854   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00855   */
00856 __STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
00857 {
00858   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
00859 }
00860
00861 /**
00862   * @brief  Select the flag to be routed to RTC_ALARM output
00863   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00864   * @rmtoll CR           OSEL          LL_RTC_SetAlarmOutEvent
00865   * @param  RTCx RTC Instance
00866   * @param  AlarmOutput This parameter can be one of the following values:
00867   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
00868   *         @arg @ref LL_RTC_ALARMOUT_ALMA
00869   *         @arg @ref LL_RTC_ALARMOUT_ALMB
00870   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
00871   * @retval None
00872   */
00873 __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
00874 {
00875   MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
00876 }
00877
00878 /**
00879   * @brief  Get the flag to be routed to RTC_ALARM output
00880   * @rmtoll CR           OSEL          LL_RTC_GetAlarmOutEvent
00881   * @param  RTCx RTC Instance
00882   * @retval Returned value can be one of the following values:
00883   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
00884   *         @arg @ref LL_RTC_ALARMOUT_ALMA
00885   *         @arg @ref LL_RTC_ALARMOUT_ALMB
00886   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
00887   */
00888 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
00889 {
00890   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
00891 }
00892
00893 /**
00894   * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
00895   * @note   Used only when RTC_ALARM is mapped on PC13
00896   * @rmtoll OR        ALARMOUTTYPE  LL_RTC_SetAlarmOutputType
00897   * @param  RTCx RTC Instance
00898   * @param  Output This parameter can be one of the following values:
00899   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
00900   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
00901   * @retval None
00902   */
00903 __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
00904 {
00905   MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output);
00906 }
00907
00908 /**
00909   * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
00910   * @note   used only when RTC_ALARM is mapped on PC13
00911   * @rmtoll OR        ALARMOUTTYPE  LL_RTC_GetAlarmOutputType
00912   * @param  RTCx RTC Instance
00913   * @retval Returned value can be one of the following values:
00914   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
00915   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
00916   */
00917 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
00918 {
00919   return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));
00920 }
00921
00922 /**
00923   * @brief  Enable initialization mode
00924   * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
00925   *         and prescaler register (RTC_PRER).
00926   *         Counters are stopped and start counting from the new value when INIT is reset.
00927   * @rmtoll ISR          INIT          LL_RTC_EnableInitMode
00928   * @param  RTCx RTC Instance
00929   * @retval None
00930   */
00931 __STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
00932 {
00933   /* Set the Initialization mode */
00934   WRITE_REG(RTCx->ISR, RTC_INIT_MASK);
00935 }
00936
00937 /**
00938   * @brief  Disable initialization mode (Free running mode)
00939   * @rmtoll ISR          INIT          LL_RTC_DisableInitMode
00940   * @param  RTCx RTC Instance
00941   * @retval None
00942   */
00943 __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
00944 {
00945   /* Exit Initialization mode */
00946   WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
00947 }
00948
00949 /**
00950   * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
00951   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00952   * @rmtoll CR           POL           LL_RTC_SetOutputPolarity
00953   * @param  RTCx RTC Instance
00954   * @param  Polarity This parameter can be one of the following values:
00955   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
00956   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
00957   * @retval None
00958   */
00959 __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
00960 {
00961   MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
00962 }
00963
00964 /**
00965   * @brief  Get Output polarity
00966   * @rmtoll CR           POL           LL_RTC_GetOutputPolarity
00967   * @param  RTCx RTC Instance
00968   * @retval Returned value can be one of the following values:
00969   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
00970   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
00971   */
00972 __STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
00973 {
00974   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
00975 }
00976
00977 /**
00978   * @brief  Enable Bypass the shadow registers
00979   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00980   * @rmtoll CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
00981   * @param  RTCx RTC Instance
00982   * @retval None
00983   */
00984 __STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
00985 {
00986   SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
00987 }
00988
00989 /**
00990   * @brief  Disable Bypass the shadow registers
00991   * @rmtoll CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
00992   * @param  RTCx RTC Instance
00993   * @retval None
00994   */
00995 __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
00996 {
00997   CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
00998 }
00999
01000 /**
01001   * @brief  Check if Shadow registers bypass is enabled or not.
01002   * @rmtoll CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
01003   * @param  RTCx RTC Instance
01004   * @retval State of bit (1 or 0).
01005   */
01006 __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
01007 {
01008   return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
01009 }
01010
01011 /**
01012   * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
01013   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01014   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01015   * @rmtoll CR           REFCKON       LL_RTC_EnableRefClock
01016   * @param  RTCx RTC Instance
01017   * @retval None
01018   */
01019 __STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
01020 {
01021   SET_BIT(RTCx->CR, RTC_CR_REFCKON);
01022 }
01023
01024 /**
01025   * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
01026   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01027   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01028   * @rmtoll CR           REFCKON       LL_RTC_DisableRefClock
01029   * @param  RTCx RTC Instance
01030   * @retval None
01031   */
01032 __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
01033 {
01034   CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
01035 }
01036
01037 /**
01038   * @brief  Set Asynchronous prescaler factor
01039   * @rmtoll PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
01040   * @param  RTCx RTC Instance
01041   * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
01042   * @retval None
01043   */
01044 __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
01045 {
01046   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_POSITION_PRER_PREDIV_A);
01047 }
01048
01049 /**
01050   * @brief  Set Synchronous prescaler factor
01051   * @rmtoll PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
01052   * @param  RTCx RTC Instance
01053   * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
01054   * @retval None
01055   */
01056 __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
01057 {
01058   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
01059 }
01060
01061 /**
01062   * @brief  Get Asynchronous prescaler factor
01063   * @rmtoll PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
01064   * @param  RTCx RTC Instance
01065   * @retval Value between Min_Data = 0 and Max_Data = 0x7F
01066   */
01067 __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
01068 {
01069   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_POSITION_PRER_PREDIV_A);
01070 }
01071
01072 /**
01073   * @brief  Get Synchronous prescaler factor
01074   * @rmtoll PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
01075   * @param  RTCx RTC Instance
01076   * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
01077   */
01078 __STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
01079 {
01080   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
01081 }
01082
01083 /**
01084   * @brief  Enable the write protection for RTC registers.
01085   * @rmtoll WPR          KEY           LL_RTC_EnableWriteProtection
01086   * @param  RTCx RTC Instance
01087   * @retval None
01088   */
01089 __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
01090 {
01091   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
01092 }
01093
01094 /**
01095   * @brief  Disable the write protection for RTC registers.
01096   * @rmtoll WPR          KEY           LL_RTC_DisableWriteProtection
01097   * @param  RTCx RTC Instance
01098   * @retval None
01099   */
01100 __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
01101 {
01102   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
01103   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
01104 }
01105
01106 /**
01107   * @brief  Enable RTC_OUT remap
01108   * @rmtoll OR           OUT_RMP       LL_RTC_EnableOutRemap
01109   * @param  RTCx RTC Instance
01110   * @retval None
01111   */
01112 __STATIC_INLINE void LL_RTC_EnableOutRemap(RTC_TypeDef *RTCx)
01113 {
01114   SET_BIT(RTCx->OR, RTC_OR_OUT_RMP);
01115 }
01116
01117 /**
01118   * @brief  Disable RTC_OUT remap
01119   * @rmtoll OR           OUT_RMP       LL_RTC_DisableOutRemap
01120   * @param  RTCx RTC Instance
01121   * @retval None
01122   */
01123 __STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx)
01124 {
01125   CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP);
01126 }
01127
01128 /**
01129   * @}
01130   */
01131
01132 /** @defgroup RTC_LL_EF_Time Time
01133   * @{
01134   */
01135
01136 /**
01137   * @brief  Set time format (AM/24-hour or PM notation)
01138   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01139   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01140   * @rmtoll TR           PM            LL_RTC_TIME_SetFormat
01141   * @param  RTCx RTC Instance
01142   * @param  TimeFormat This parameter can be one of the following values:
01143   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01144   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01145   * @retval None
01146   */
01147 __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01148 {
01149   MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
01150 }
01151
01152 /**
01153   * @brief  Get time format (AM or PM notation)
01154   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01155   *       before reading this bit
01156   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01157   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01158   * @rmtoll TR           PM            LL_RTC_TIME_GetFormat
01159   * @param  RTCx RTC Instance
01160   * @retval Returned value can be one of the following values:
01161   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01162   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01163   */
01164 __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
01165 {
01166   return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
01167 }
01168
01169 /**
01170   * @brief  Set Hours in BCD format
01171   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01172   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01173   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
01174   * @rmtoll TR           HT            LL_RTC_TIME_SetHour\n
01175   *         TR           HU            LL_RTC_TIME_SetHour
01176   * @param  RTCx RTC Instance
01177   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01178   * @retval None
01179   */
01180 __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01181 {
01182   MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
01183              (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)));
01184 }
01185
01186 /**
01187   * @brief  Get Hours in BCD format
01188   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01189   *       before reading this bit
01190   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01191   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01192   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
01193   *       Binary format
01194   * @rmtoll TR           HT            LL_RTC_TIME_GetHour\n
01195   *         TR           HU            LL_RTC_TIME_GetHour
01196   * @param  RTCx RTC Instance
01197   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01198   */
01199 __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
01200 {
01201   register uint32_t temp = 0U;
01202
01203   temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
01204   return (uint32_t)((((temp & RTC_TR_HT) >> RTC_POSITION_TR_HT) << 4U) | ((temp & RTC_TR_HU) >> RTC_POSITION_TR_HU));
01205 }
01206
01207 /**
01208   * @brief  Set Minutes in BCD format
01209   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01210   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01211   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01212   * @rmtoll TR           MNT           LL_RTC_TIME_SetMinute\n
01213   *         TR           MNU           LL_RTC_TIME_SetMinute
01214   * @param  RTCx RTC Instance
01215   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01216   * @retval None
01217   */
01218 __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01219 {
01220   MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
01221              (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)));
01222 }
01223
01224 /**
01225   * @brief  Get Minutes in BCD format
01226   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01227   *       before reading this bit
01228   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01229   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01230   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
01231   *       to Binary format
01232   * @rmtoll TR           MNT           LL_RTC_TIME_GetMinute\n
01233   *         TR           MNU           LL_RTC_TIME_GetMinute
01234   * @param  RTCx RTC Instance
01235   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01236   */
01237 __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
01238 {
01239   register uint32_t temp = 0U;
01240
01241   temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
01242   return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_POSITION_TR_MT) << 4U) | ((temp & RTC_TR_MNU) >> RTC_POSITION_TR_MU));
01243 }
01244
01245 /**
01246   * @brief  Set Seconds in BCD format
01247   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01248   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01249   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01250   * @rmtoll TR           ST            LL_RTC_TIME_SetSecond\n
01251   *         TR           SU            LL_RTC_TIME_SetSecond
01252   * @param  RTCx RTC Instance
01253   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01254   * @retval None
01255   */
01256 __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01257 {
01258   MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
01259              (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU)));
01260 }
01261
01262 /**
01263   * @brief  Get Seconds in BCD format
01264   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01265   *       before reading this bit
01266   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01267   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01268   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
01269   *       to Binary format
01270   * @rmtoll TR           ST            LL_RTC_TIME_GetSecond\n
01271   *         TR           SU            LL_RTC_TIME_GetSecond
01272   * @param  RTCx RTC Instance
01273   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01274   */
01275 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
01276 {
01277   register uint32_t temp = 0U;
01278
01279   temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
01280   return (uint32_t)((((temp & RTC_TR_ST) >> RTC_POSITION_TR_ST) << 4U) | ((temp & RTC_TR_SU) >> RTC_POSITION_TR_SU));
01281 }
01282
01283 /**
01284   * @brief  Set time (hour, minute and second) in BCD format
01285   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01286   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01287   * @note TimeFormat and Hours should follow the same format
01288   * @rmtoll TR           PM            LL_RTC_TIME_Config\n
01289   *         TR           HT            LL_RTC_TIME_Config\n
01290   *         TR           HU            LL_RTC_TIME_Config\n
01291   *         TR           MNT           LL_RTC_TIME_Config\n
01292   *         TR           MNU           LL_RTC_TIME_Config\n
01293   *         TR           ST            LL_RTC_TIME_Config\n
01294   *         TR           SU            LL_RTC_TIME_Config
01295   * @param  RTCx RTC Instance
01296   * @param  Format12_24 This parameter can be one of the following values:
01297   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01298   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01299   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01300   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01301   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01302   * @retval None
01303   */
01304 __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
01305 {
01306   register uint32_t temp = 0U;
01307
01308   temp = Format12_24                                                                                    | \
01309          (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU))     | \
01310          (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)) | \
01311          (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU));
01312   MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
01313 }
01314
01315 /**
01316   * @brief  Get time (hour, minute and second) in BCD format
01317   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01318   *       before reading this bit
01319   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01320   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01321   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
01322   *       are available to get independently each parameter.
01323   * @rmtoll TR           HT            LL_RTC_TIME_Get\n
01324   *         TR           HU            LL_RTC_TIME_Get\n
01325   *         TR           MNT           LL_RTC_TIME_Get\n
01326   *         TR           MNU           LL_RTC_TIME_Get\n
01327   *         TR           ST            LL_RTC_TIME_Get\n
01328   *         TR           SU            LL_RTC_TIME_Get
01329   * @param  RTCx RTC Instance
01330   * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
01331   */
01332 __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
01333 {
01334   return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx));
01335 }
01336
01337 /**
01338   * @brief  Memorize whether the daylight saving time change has been performed
01339   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01340   * @rmtoll CR           BCK           LL_RTC_TIME_EnableDayLightStore
01341   * @param  RTCx RTC Instance
01342   * @retval None
01343   */
01344 __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
01345 {
01346   SET_BIT(RTCx->CR, RTC_CR_BCK);
01347 }
01348
01349 /**
01350   * @brief  Disable memorization whether the daylight saving time change has been performed.
01351   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01352   * @rmtoll CR           BCK           LL_RTC_TIME_DisableDayLightStore
01353   * @param  RTCx RTC Instance
01354   * @retval None
01355   */
01356 __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
01357 {
01358   CLEAR_BIT(RTCx->CR, RTC_CR_BCK);
01359 }
01360
01361 /**
01362   * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
01363   * @rmtoll CR           BCK           LL_RTC_TIME_IsDayLightStoreEnabled
01364   * @param  RTCx RTC Instance
01365   * @retval State of bit (1 or 0).
01366   */
01367 __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
01368 {
01369   return (READ_BIT(RTCx->CR, RTC_CR_BCK) == (RTC_CR_BCK));
01370 }
01371
01372 /**
01373   * @brief  Subtract 1 hour (winter time change)
01374   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01375   * @rmtoll CR           SUB1H         LL_RTC_TIME_DecHour
01376   * @param  RTCx RTC Instance
01377   * @retval None
01378   */
01379 __STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
01380 {
01381   SET_BIT(RTCx->CR, RTC_CR_SUB1H);
01382 }
01383
01384 /**
01385   * @brief  Add 1 hour (summer time change)
01386   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01387   * @rmtoll CR           ADD1H         LL_RTC_TIME_IncHour
01388   * @param  RTCx RTC Instance
01389   * @retval None
01390   */
01391 __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
01392 {
01393   SET_BIT(RTCx->CR, RTC_CR_ADD1H);
01394 }
01395
01396 /**
01397   * @brief  Get Sub second value in the synchronous prescaler counter.
01398   * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
01399   *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
01400   *        SubSeconds value in second fraction ratio with time unit following
01401   *        generic formula:
01402   *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
01403   *        This conversion can be performed only if no shift operation is pending
01404   *        (ie. SHFP=0) when PREDIV_S >= SS.
01405   * @rmtoll SSR          SS            LL_RTC_TIME_GetSubSecond
01406   * @param  RTCx RTC Instance
01407   * @retval Sub second value (number between 0 and 65535)
01408   */
01409 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
01410 {
01411   return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
01412 }
01413
01414 /**
01415   * @brief  Synchronize to a remote clock with a high degree of precision.
01416   * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
01417   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01418   * @note   When REFCKON is set, firmware must not write to Shift control register.
01419   * @rmtoll SHIFTR       ADD1S         LL_RTC_TIME_Synchronize\n
01420   *         SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
01421   * @param  RTCx RTC Instance
01422   * @param  ShiftSecond This parameter can be one of the following values:
01423   *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
01424   *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
01425   * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
01426   * @retval None
01427   */
01428 __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
01429 {
01430   WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
01431 }
01432
01433 /**
01434   * @}
01435   */
01436
01437 /** @defgroup RTC_LL_EF_Date Date
01438   * @{
01439   */
01440
01441 /**
01442   * @brief  Set Year in BCD format
01443   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
01444   * @rmtoll DR           YT            LL_RTC_DATE_SetYear\n
01445   *         DR           YU            LL_RTC_DATE_SetYear
01446   * @param  RTCx RTC Instance
01447   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01448   * @retval None
01449   */
01450 __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
01451 {
01452   MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
01453              (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)));
01454 }
01455
01456 /**
01457   * @brief  Get Year in BCD format
01458   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01459   *       before reading this bit
01460   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
01461   * @rmtoll DR           YT            LL_RTC_DATE_GetYear\n
01462   *         DR           YU            LL_RTC_DATE_GetYear
01463   * @param  RTCx RTC Instance
01464   * @retval Value between Min_Data=0x00 and Max_Data=0x99
01465   */
01466 __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
01467 {
01468   register uint32_t temp = 0U;
01469
01470   temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
01471   return (uint32_t)((((temp & RTC_DR_YT) >> RTC_POSITION_DR_YT) << 4U) | ((temp & RTC_DR_YU) >> RTC_POSITION_DR_YU));
01472 }
01473
01474 /**
01475   * @brief  Set Week day
01476   * @rmtoll DR           WDU           LL_RTC_DATE_SetWeekDay
01477   * @param  RTCx RTC Instance
01478   * @param  WeekDay This parameter can be one of the following values:
01479   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01480   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01481   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01482   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01483   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01484   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01485   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01486   * @retval None
01487   */
01488 __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01489 {
01490   MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_POSITION_DR_WDU);
01491 }
01492
01493 /**
01494   * @brief  Get Week day
01495   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01496   *       before reading this bit
01497   * @rmtoll DR           WDU           LL_RTC_DATE_GetWeekDay
01498   * @param  RTCx RTC Instance
01499   * @retval Returned value can be one of the following values:
01500   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01501   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01502   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01503   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01504   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01505   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01506   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01507   */
01508 __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
01509 {
01510   return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_POSITION_DR_WDU);
01511 }
01512
01513 /**
01514   * @brief  Set Month in BCD format
01515   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
01516   * @rmtoll DR           MT            LL_RTC_DATE_SetMonth\n
01517   *         DR           MU            LL_RTC_DATE_SetMonth
01518   * @param  RTCx RTC Instance
01519   * @param  Month This parameter can be one of the following values:
01520   *         @arg @ref LL_RTC_MONTH_JANUARY
01521   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01522   *         @arg @ref LL_RTC_MONTH_MARCH
01523   *         @arg @ref LL_RTC_MONTH_APRIL
01524   *         @arg @ref LL_RTC_MONTH_MAY
01525   *         @arg @ref LL_RTC_MONTH_JUNE
01526   *         @arg @ref LL_RTC_MONTH_JULY
01527   *         @arg @ref LL_RTC_MONTH_AUGUST
01528   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01529   *         @arg @ref LL_RTC_MONTH_OCTOBER
01530   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01531   *         @arg @ref LL_RTC_MONTH_DECEMBER
01532   * @retval None
01533   */
01534 __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
01535 {
01536   MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
01537              (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)));
01538 }
01539
01540 /**
01541   * @brief  Get Month in BCD format
01542   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01543   *       before reading this bit
01544   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
01545   * @rmtoll DR           MT            LL_RTC_DATE_GetMonth\n
01546   *         DR           MU            LL_RTC_DATE_GetMonth
01547   * @param  RTCx RTC Instance
01548   * @retval Returned value can be one of the following values:
01549   *         @arg @ref LL_RTC_MONTH_JANUARY
01550   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01551   *         @arg @ref LL_RTC_MONTH_MARCH
01552   *         @arg @ref LL_RTC_MONTH_APRIL
01553   *         @arg @ref LL_RTC_MONTH_MAY
01554   *         @arg @ref LL_RTC_MONTH_JUNE
01555   *         @arg @ref LL_RTC_MONTH_JULY
01556   *         @arg @ref LL_RTC_MONTH_AUGUST
01557   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01558   *         @arg @ref LL_RTC_MONTH_OCTOBER
01559   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01560   *         @arg @ref LL_RTC_MONTH_DECEMBER
01561   */
01562 __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
01563 {
01564   register uint32_t temp = 0U;
01565
01566   temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
01567   return (uint32_t)((((temp & RTC_DR_MT) >> RTC_POSITION_DR_MT) << 4U) | ((temp & RTC_DR_MU) >> RTC_POSITION_DR_MU));
01568 }
01569
01570 /**
01571   * @brief  Set Day in BCD format
01572   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01573   * @rmtoll DR           DT            LL_RTC_DATE_SetDay\n
01574   *         DR           DU            LL_RTC_DATE_SetDay
01575   * @param  RTCx RTC Instance
01576   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01577   * @retval None
01578   */
01579 __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01580 {
01581   MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
01582              (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)));
01583 }
01584
01585 /**
01586   * @brief  Get Day in BCD format
01587   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01588   *       before reading this bit
01589   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01590   * @rmtoll DR           DT            LL_RTC_DATE_GetDay\n
01591   *         DR           DU            LL_RTC_DATE_GetDay
01592   * @param  RTCx RTC Instance
01593   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01594   */
01595 __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
01596 {
01597   register uint32_t temp = 0U;
01598
01599   temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
01600   return (uint32_t)((((temp & RTC_DR_DT) >> RTC_POSITION_DR_DT) << 4U) | ((temp & RTC_DR_DU) >> RTC_POSITION_DR_DU));
01601 }
01602
01603 /**
01604   * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
01605   * @rmtoll DR           WDU           LL_RTC_DATE_Config\n
01606   *         DR           MT            LL_RTC_DATE_Config\n
01607   *         DR           MU            LL_RTC_DATE_Config\n
01608   *         DR           DT            LL_RTC_DATE_Config\n
01609   *         DR           DU            LL_RTC_DATE_Config\n
01610   *         DR           YT            LL_RTC_DATE_Config\n
01611   *         DR           YU            LL_RTC_DATE_Config
01612   * @param  RTCx RTC Instance
01613   * @param  WeekDay This parameter can be one of the following values:
01614   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01615   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01616   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01617   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01618   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01619   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01620   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01621   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01622   * @param  Month This parameter can be one of the following values:
01623   *         @arg @ref LL_RTC_MONTH_JANUARY
01624   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01625   *         @arg @ref LL_RTC_MONTH_MARCH
01626   *         @arg @ref LL_RTC_MONTH_APRIL
01627   *         @arg @ref LL_RTC_MONTH_MAY
01628   *         @arg @ref LL_RTC_MONTH_JUNE
01629   *         @arg @ref LL_RTC_MONTH_JULY
01630   *         @arg @ref LL_RTC_MONTH_AUGUST
01631   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01632   *         @arg @ref LL_RTC_MONTH_OCTOBER
01633   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01634   *         @arg @ref LL_RTC_MONTH_DECEMBER
01635   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01636   * @retval None
01637   */
01638 __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
01639 {
01640   register uint32_t temp = 0U;
01641
01642   temp = (WeekDay << RTC_POSITION_DR_WDU)                                                        | \
01643          (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU))   | \
01644          (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) | \
01645          (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU));
01646
01647   MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
01648 }
01649
01650 /**
01651   * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
01652   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01653   *       before reading this bit
01654   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
01655   * and __LL_RTC_GET_DAY are available to get independently each parameter.
01656   * @rmtoll DR           WDU           LL_RTC_DATE_Get\n
01657   *         DR           MT            LL_RTC_DATE_Get\n
01658   *         DR           MU            LL_RTC_DATE_Get\n
01659   *         DR           DT            LL_RTC_DATE_Get\n
01660   *         DR           DU            LL_RTC_DATE_Get\n
01661   *         DR           YT            LL_RTC_DATE_Get\n
01662   *         DR           YU            LL_RTC_DATE_Get
01663   * @param  RTCx RTC Instance
01664   * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
01665   */
01666 __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
01667 {
01668   return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx));
01669 }
01670
01671 /**
01672   * @}
01673   */
01674
01675 /** @defgroup RTC_LL_EF_ALARMA ALARMA
01676   * @{
01677   */
01678
01679 /**
01680   * @brief  Enable Alarm A
01681   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01682   * @rmtoll CR           ALRAE         LL_RTC_ALMA_Enable
01683   * @param  RTCx RTC Instance
01684   * @retval None
01685   */
01686 __STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
01687 {
01688   SET_BIT(RTCx->CR, RTC_CR_ALRAE);
01689 }
01690
01691 /**
01692   * @brief  Disable Alarm A
01693   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01694   * @rmtoll CR           ALRAE         LL_RTC_ALMA_Disable
01695   * @param  RTCx RTC Instance
01696   * @retval None
01697   */
01698 __STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
01699 {
01700   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
01701 }
01702
01703 /**
01704   * @brief  Specify the Alarm A masks.
01705   * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_SetMask\n
01706   *         ALRMAR       MSK3          LL_RTC_ALMA_SetMask\n
01707   *         ALRMAR       MSK2          LL_RTC_ALMA_SetMask\n
01708   *         ALRMAR       MSK1          LL_RTC_ALMA_SetMask
01709   * @param  RTCx RTC Instance
01710   * @param  Mask This parameter can be a combination of the following values:
01711   *         @arg @ref LL_RTC_ALMA_MASK_NONE
01712   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
01713   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
01714   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
01715   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
01716   *         @arg @ref LL_RTC_ALMA_MASK_ALL
01717   * @retval None
01718   */
01719 __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
01720 {
01721   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
01722 }
01723
01724 /**
01725   * @brief  Get the Alarm A masks.
01726   * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_GetMask\n
01727   *         ALRMAR       MSK3          LL_RTC_ALMA_GetMask\n
01728   *         ALRMAR       MSK2          LL_RTC_ALMA_GetMask\n
01729   *         ALRMAR       MSK1          LL_RTC_ALMA_GetMask
01730   * @param  RTCx RTC Instance
01731   * @retval Returned value can be can be a combination of the following values:
01732   *         @arg @ref LL_RTC_ALMA_MASK_NONE
01733   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
01734   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
01735   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
01736   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
01737   *         @arg @ref LL_RTC_ALMA_MASK_ALL
01738   */
01739 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
01740 {
01741   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
01742 }
01743
01744 /**
01745   * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
01746   * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
01747   * @param  RTCx RTC Instance
01748   * @retval None
01749   */
01750 __STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
01751 {
01752   SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
01753 }
01754
01755 /**
01756   * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
01757   * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
01758   * @param  RTCx RTC Instance
01759   * @retval None
01760   */
01761 __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
01762 {
01763   CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
01764 }
01765
01766 /**
01767   * @brief  Set ALARM A Day in BCD format
01768   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01769   * @rmtoll ALRMAR       DT            LL_RTC_ALMA_SetDay\n
01770   *         ALRMAR       DU            LL_RTC_ALMA_SetDay
01771   * @param  RTCx RTC Instance
01772   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01773   * @retval None
01774   */
01775 __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01776 {
01777   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
01778              (((Day & 0xF0U) << (RTC_POSITION_ALMA_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMA_DU)));
01779 }
01780
01781 /**
01782   * @brief  Get ALARM A Day in BCD format
01783   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01784   * @rmtoll ALRMAR       DT            LL_RTC_ALMA_GetDay\n
01785   *         ALRMAR       DU            LL_RTC_ALMA_GetDay
01786   * @param  RTCx RTC Instance
01787   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01788   */
01789 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
01790 {
01791   register uint32_t temp = 0U;
01792
01793   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
01794   return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_POSITION_ALMA_DT) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU));
01795 }
01796
01797 /**
01798   * @brief  Set ALARM A Weekday
01799   * @rmtoll ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
01800   * @param  RTCx RTC Instance
01801   * @param  WeekDay This parameter can be one of the following values:
01802   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01803   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01804   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01805   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01806   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01807   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01808   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01809   * @retval None
01810   */
01811 __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01812 {
01813   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_POSITION_ALMA_DU);
01814 }
01815
01816 /**
01817   * @brief  Get ALARM A Weekday
01818   * @rmtoll ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
01819   * @param  RTCx RTC Instance
01820   * @retval Returned value can be one of the following values:
01821   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01822   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01823   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01824   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01825   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01826   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01827   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01828   */
01829 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
01830 {
01831   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU);
01832 }
01833
01834 /**
01835   * @brief  Set Alarm A time format (AM/24-hour or PM notation)
01836   * @rmtoll ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
01837   * @param  RTCx RTC Instance
01838   * @param  TimeFormat This parameter can be one of the following values:
01839   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01840   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01841   * @retval None
01842   */
01843 __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01844 {
01845   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
01846 }
01847
01848 /**
01849   * @brief  Get Alarm A time format (AM or PM notation)
01850   * @rmtoll ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
01851   * @param  RTCx RTC Instance
01852   * @retval Returned value can be one of the following values:
01853   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01854   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01855   */
01856 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
01857 {
01858   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
01859 }
01860
01861 /**
01862   * @brief  Set ALARM A Hours in BCD format
01863   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
01864   * @rmtoll ALRMAR       HT            LL_RTC_ALMA_SetHour\n
01865   *         ALRMAR       HU            LL_RTC_ALMA_SetHour
01866   * @param  RTCx RTC Instance
01867   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01868   * @retval None
01869   */
01870 __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01871 {
01872   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
01873              (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU)));
01874 }
01875
01876 /**
01877   * @brief  Get ALARM A Hours in BCD format
01878   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
01879   * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetHour\n
01880   *         ALRMAR       HU            LL_RTC_ALMA_GetHour
01881   * @param  RTCx RTC Instance
01882   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01883   */
01884 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
01885 {
01886   register uint32_t temp = 0U;
01887
01888   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
01889   return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_POSITION_ALMA_HT) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_POSITION_ALMA_HU));
01890 }
01891
01892 /**
01893   * @brief  Set ALARM A Minutes in BCD format
01894   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01895   * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_SetMinute\n
01896   *         ALRMAR       MNU           LL_RTC_ALMA_SetMinute
01897   * @param  RTCx RTC Instance
01898   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01899   * @retval None
01900   */
01901 __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01902 {
01903   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
01904              (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)));
01905 }
01906
01907 /**
01908   * @brief  Get ALARM A Minutes in BCD format
01909   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
01910   * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_GetMinute\n
01911   *         ALRMAR       MNU           LL_RTC_ALMA_GetMinute
01912   * @param  RTCx RTC Instance
01913   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01914   */
01915 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
01916 {
01917   register uint32_t temp = 0U;
01918
01919   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
01920   return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_POSITION_ALMA_MT) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_POSITION_ALMA_MU));
01921 }
01922
01923 /**
01924   * @brief  Set ALARM A Seconds in BCD format
01925   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01926   * @rmtoll ALRMAR       ST            LL_RTC_ALMA_SetSecond\n
01927   *         ALRMAR       SU            LL_RTC_ALMA_SetSecond
01928   * @param  RTCx RTC Instance
01929   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01930   * @retval None
01931   */
01932 __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01933 {
01934   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
01935              (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU)));
01936 }
01937
01938 /**
01939   * @brief  Get ALARM A Seconds in BCD format
01940   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
01941   * @rmtoll ALRMAR       ST            LL_RTC_ALMA_GetSecond\n
01942   *         ALRMAR       SU            LL_RTC_ALMA_GetSecond
01943   * @param  RTCx RTC Instance
01944   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01945   */
01946 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
01947 {
01948   register uint32_t temp = 0U;
01949
01950   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
01951   return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_POSITION_ALMA_ST) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_POSITION_ALMA_SU));
01952 }
01953
01954 /**
01955   * @brief  Set Alarm A Time (hour, minute and second) in BCD format
01956   * @rmtoll ALRMAR       PM            LL_RTC_ALMA_ConfigTime\n
01957   *         ALRMAR       HT            LL_RTC_ALMA_ConfigTime\n
01958   *         ALRMAR       HU            LL_RTC_ALMA_ConfigTime\n
01959   *         ALRMAR       MNT           LL_RTC_ALMA_ConfigTime\n
01960   *         ALRMAR       MNU           LL_RTC_ALMA_ConfigTime\n
01961   *         ALRMAR       ST            LL_RTC_ALMA_ConfigTime\n
01962   *         ALRMAR       SU            LL_RTC_ALMA_ConfigTime
01963   * @param  RTCx RTC Instance
01964   * @param  Format12_24 This parameter can be one of the following values:
01965   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01966   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01967   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01968   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01969   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01970   * @retval None
01971   */
01972 __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
01973 {
01974   register uint32_t temp = 0U;
01975
01976   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU))    | \
01977          (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)) | \
01978          (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU));
01979
01980   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
01981 }
01982
01983 /**
01984   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
01985   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
01986   * are available to get independently each parameter.
01987   * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetTime\n
01988   *         ALRMAR       HU            LL_RTC_ALMA_GetTime\n
01989   *         ALRMAR       MNT           LL_RTC_ALMA_GetTime\n
01990   *         ALRMAR       MNU           LL_RTC_ALMA_GetTime\n
01991   *         ALRMAR       ST            LL_RTC_ALMA_GetTime\n
01992   *         ALRMAR       SU            LL_RTC_ALMA_GetTime
01993   * @param  RTCx RTC Instance
01994   * @retval Combination of hours, minutes and seconds.
01995   */
01996 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
01997 {
01998   return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
01999 }
02000
02001 /**
02002   * @brief  Set Alarm A Mask the most-significant bits starting at this bit
02003   * @note This register can be written only when ALRAE is reset in RTC_CR register,
02004   *       or in initialization mode.
02005   * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
02006   * @param  RTCx RTC Instance
02007   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
02008   * @retval None
02009   */
02010 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
02011 {
02012   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_POSITION_ALMA_MASKSS);
02013 }
02014
02015 /**
02016   * @brief  Get Alarm A Mask the most-significant bits starting at this bit
02017   * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
02018   * @param  RTCx RTC Instance
02019   * @retval Value between Min_Data=0x00 and Max_Data=0xF
02020   */
02021 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
02022 {
02023   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_POSITION_ALMA_MASKSS);
02024 }
02025
02026 /**
02027   * @brief  Set Alarm A Sub seconds value
02028   * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
02029   * @param  RTCx RTC Instance
02030   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
02031   * @retval None
02032   */
02033 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
02034 {
02035   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
02036 }
02037
02038 /**
02039   * @brief  Get Alarm A Sub seconds value
02040   * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
02041   * @param  RTCx RTC Instance
02042   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
02043   */
02044 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
02045 {
02046   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
02047 }
02048
02049 /**
02050   * @}
02051   */
02052
02053 /** @defgroup RTC_LL_EF_ALARMB ALARMB
02054   * @{
02055   */
02056
02057 /**
02058   * @brief  Enable Alarm B
02059   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02060   * @rmtoll CR           ALRBE         LL_RTC_ALMB_Enable
02061   * @param  RTCx RTC Instance
02062   * @retval None
02063   */
02064 __STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
02065 {
02066   SET_BIT(RTCx->CR, RTC_CR_ALRBE);
02067 }
02068
02069 /**
02070   * @brief  Disable Alarm B
02071   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02072   * @rmtoll CR           ALRBE         LL_RTC_ALMB_Disable
02073   * @param  RTCx RTC Instance
02074   * @retval None
02075   */
02076 __STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
02077 {
02078   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
02079 }
02080
02081 /**
02082   * @brief  Specify the Alarm B masks.
02083   * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_SetMask\n
02084   *         ALRMBR       MSK3          LL_RTC_ALMB_SetMask\n
02085   *         ALRMBR       MSK2          LL_RTC_ALMB_SetMask\n
02086   *         ALRMBR       MSK1          LL_RTC_ALMB_SetMask
02087   * @param  RTCx RTC Instance
02088   * @param  Mask This parameter can be a combination of the following values:
02089   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02090   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02091   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02092   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02093   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02094   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02095   * @retval None
02096   */
02097 __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
02098 {
02099   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
02100 }
02101
02102 /**
02103   * @brief  Get the Alarm B masks.
02104   * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_GetMask\n
02105   *         ALRMBR       MSK3          LL_RTC_ALMB_GetMask\n
02106   *         ALRMBR       MSK2          LL_RTC_ALMB_GetMask\n
02107   *         ALRMBR       MSK1          LL_RTC_ALMB_GetMask
02108   * @param  RTCx RTC Instance
02109   * @retval Returned value can be can be a combination of the following values:
02110   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02111   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02112   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02113   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02114   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02115   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02116   */
02117 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
02118 {
02119   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
02120 }
02121
02122 /**
02123   * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
02124   * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
02125   * @param  RTCx RTC Instance
02126   * @retval None
02127   */
02128 __STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
02129 {
02130   SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02131 }
02132
02133 /**
02134   * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
02135   * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
02136   * @param  RTCx RTC Instance
02137   * @retval None
02138   */
02139 __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
02140 {
02141   CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02142 }
02143
02144 /**
02145   * @brief  Set ALARM B Day in BCD format
02146   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
02147   * @rmtoll ALRMBR       DT            LL_RTC_ALMB_SetDay\n
02148   *         ALRMBR       DU            LL_RTC_ALMB_SetDay
02149   * @param  RTCx RTC Instance
02150   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
02151   * @retval None
02152   */
02153 __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
02154 {
02155   MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
02156              (((Day & 0xF0U) << (RTC_POSITION_ALMB_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMB_DU)));
02157 }
02158
02159 /**
02160   * @brief  Get ALARM B Day in BCD format
02161   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02162   * @rmtoll ALRMBR       DT            LL_RTC_ALMB_GetDay\n
02163   *         ALRMBR       DU            LL_RTC_ALMB_GetDay
02164   * @param  RTCx RTC Instance
02165   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02166   */
02167 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
02168 {
02169   register uint32_t temp = 0U;
02170
02171   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
02172   return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_POSITION_ALMB_DT) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_POSITION_ALMB_DU));
02173 }
02174
02175 /**
02176   * @brief  Set ALARM B Weekday
02177   * @rmtoll ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
02178   * @param  RTCx RTC Instance
02179   * @param  WeekDay This parameter can be one of the following values:
02180   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02181   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02182   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02183   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02184   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02185   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02186   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02187   * @retval None
02188   */
02189 __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
02190 {
02191   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_POSITION_ALMB_DU);
02192 }
02193
02194 /**
02195   * @brief  Get ALARM B Weekday
02196   * @rmtoll ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
02197   * @param  RTCx RTC Instance
02198   * @retval Returned value can be one of the following values:
02199   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02200   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02201   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02202   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02203   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02204   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02205   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02206   */
02207 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
02208 {
02209   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_POSITION_ALMB_DU);
02210 }
02211
02212 /**
02213   * @brief  Set ALARM B time format (AM/24-hour or PM notation)
02214   * @rmtoll ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
02215   * @param  RTCx RTC Instance
02216   * @param  TimeFormat This parameter can be one of the following values:
02217   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02218   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02219   * @retval None
02220   */
02221 __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
02222 {
02223   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
02224 }
02225
02226 /**
02227   * @brief  Get ALARM B time format (AM or PM notation)
02228   * @rmtoll ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
02229   * @param  RTCx RTC Instance
02230   * @retval Returned value can be one of the following values:
02231   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02232   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02233   */
02234 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
02235 {
02236   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
02237 }
02238
02239 /**
02240   * @brief  Set ALARM B Hours in BCD format
02241   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
02242   * @rmtoll ALRMBR       HT            LL_RTC_ALMB_SetHour\n
02243   *         ALRMBR       HU            LL_RTC_ALMB_SetHour
02244   * @param  RTCx RTC Instance
02245   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02246   * @retval None
02247   */
02248 __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
02249 {
02250   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
02251              (((Hours & 0xF0U) << (RTC_POSITION_ALMB_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMB_HU)));
02252 }
02253
02254 /**
02255   * @brief  Get ALARM B Hours in BCD format
02256   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02257   * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetHour\n
02258   *         ALRMBR       HU            LL_RTC_ALMB_GetHour
02259   * @param  RTCx RTC Instance
02260   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02261   */
02262 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
02263 {
02264   register uint32_t temp = 0U;
02265
02266   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
02267   return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_POSITION_ALMB_HT) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_POSITION_ALMB_HU));
02268 }
02269
02270 /**
02271   * @brief  Set ALARM B Minutes in BCD format
02272   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
02273   * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_SetMinute\n
02274   *         ALRMBR       MNU           LL_RTC_ALMB_SetMinute
02275   * @param  RTCx RTC Instance
02276   * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
02277   * @retval None
02278   */
02279 __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
02280 {
02281   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
02282              (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMB_MU)));
02283 }
02284
02285 /**
02286   * @brief  Get ALARM B Minutes in BCD format
02287   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02288   * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_GetMinute\n
02289   *         ALRMBR       MNU           LL_RTC_ALMB_GetMinute
02290   * @param  RTCx RTC Instance
02291   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02292   */
02293 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
02294 {
02295   register uint32_t temp = 0U;
02296
02297   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
02298   return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_POSITION_ALMB_MT) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_POSITION_ALMB_MU));
02299 }
02300
02301 /**
02302   * @brief  Set ALARM B Seconds in BCD format
02303   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
02304   * @rmtoll ALRMBR       ST            LL_RTC_ALMB_SetSecond\n
02305   *         ALRMBR       SU            LL_RTC_ALMB_SetSecond
02306   * @param  RTCx RTC Instance
02307   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02308   * @retval None
02309   */
02310 __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
02311 {
02312   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
02313              (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMB_SU)));
02314 }
02315
02316 /**
02317   * @brief  Get ALARM B Seconds in BCD format
02318   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02319   * @rmtoll ALRMBR       ST            LL_RTC_ALMB_GetSecond\n
02320   *         ALRMBR       SU            LL_RTC_ALMB_GetSecond
02321   * @param  RTCx RTC Instance
02322   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02323   */
02324 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
02325 {
02326   register uint32_t temp = 0U;
02327
02328   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
02329   return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_POSITION_ALMB_ST) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_POSITION_ALMB_SU));
02330 }
02331
02332 /**
02333   * @brief  Set Alarm B Time (hour, minute and second) in BCD format
02334   * @rmtoll ALRMBR       PM            LL_RTC_ALMB_ConfigTime\n
02335   *         ALRMBR       HT            LL_RTC_ALMB_ConfigTime\n
02336   *         ALRMBR       HU            LL_RTC_ALMB_ConfigTime\n
02337   *         ALRMBR       MNT           LL_RTC_ALMB_ConfigTime\n
02338   *         ALRMBR       MNU           LL_RTC_ALMB_ConfigTime\n
02339   *         ALRMBR       ST            LL_RTC_ALMB_ConfigTime\n
02340   *         ALRMBR       SU            LL_RTC_ALMB_ConfigTime
02341   * @param  RTCx RTC Instance
02342   * @param  Format12_24 This parameter can be one of the following values:
02343   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02344   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02345   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02346   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
02347   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02348   * @retval None
02349   */
02350 __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
02351 {
02352   register uint32_t temp = 0U;
02353
02354   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMB_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMB_HU))    | \
02355          (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMB_MU)) | \
02356          (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMB_SU));
02357
02358   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
02359 }
02360
02361 /**
02362   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
02363   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02364   * are available to get independently each parameter.
02365   * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetTime\n
02366   *         ALRMBR       HU            LL_RTC_ALMB_GetTime\n
02367   *         ALRMBR       MNT           LL_RTC_ALMB_GetTime\n
02368   *         ALRMBR       MNU           LL_RTC_ALMB_GetTime\n
02369   *         ALRMBR       ST            LL_RTC_ALMB_GetTime\n
02370   *         ALRMBR       SU            LL_RTC_ALMB_GetTime
02371   * @param  RTCx RTC Instance
02372   * @retval Combination of hours, minutes and seconds.
02373   */
02374 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
02375 {
02376   return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
02377 }
02378
02379 /**
02380   * @brief  Set Alarm B Mask the most-significant bits starting at this bit
02381   * @note This register can be written only when ALRBE is reset in RTC_CR register,
02382   *       or in initialization mode.
02383   * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
02384   * @param  RTCx RTC Instance
02385   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
02386   * @retval None
02387   */
02388 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
02389 {
02390   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_POSITION_ALMB_MASKSS);
02391 }
02392
02393 /**
02394   * @brief  Get Alarm B Mask the most-significant bits starting at this bit
02395   * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
02396   * @param  RTCx RTC Instance
02397   * @retval Value between Min_Data=0x00 and Max_Data=0xF
02398   */
02399 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
02400 {
02401   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_POSITION_ALMB_MASKSS);
02402 }
02403
02404 /**
02405   * @brief  Set Alarm B Sub seconds value
02406   * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
02407   * @param  RTCx RTC Instance
02408   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
02409   * @retval None
02410   */
02411 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
02412 {
02413   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
02414 }
02415
02416 /**
02417   * @brief  Get Alarm B Sub seconds value
02418   * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
02419   * @param  RTCx RTC Instance
02420   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
02421   */
02422 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
02423 {
02424   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
02425 }
02426
02427 /**
02428   * @}
02429   */
02430
02431 /** @defgroup RTC_LL_EF_Timestamp Timestamp
02432   * @{
02433   */
02434
02435 /**
02436   * @brief  Enable internal event timestamp
02437   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02438   * @rmtoll CR           ITSE          LL_RTC_TS_EnableInternalEvent
02439   * @param  RTCx RTC Instance
02440   * @retval None
02441   */
02442 __STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
02443 {
02444   SET_BIT(RTCx->CR, RTC_CR_ITSE);
02445 }
02446
02447 /**
02448   * @brief  Disable internal event timestamp
02449   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02450   * @rmtoll CR           ITSE          LL_RTC_TS_DisableInternalEvent
02451   * @param  RTCx RTC Instance
02452   * @retval None
02453   */
02454 __STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
02455 {
02456   CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
02457 }
02458
02459 /**
02460   * @brief  Enable Timestamp
02461   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02462   * @rmtoll CR           TSE           LL_RTC_TS_Enable
02463   * @param  RTCx RTC Instance
02464   * @retval None
02465   */
02466 __STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
02467 {
02468   SET_BIT(RTCx->CR, RTC_CR_TSE);
02469 }
02470
02471 /**
02472   * @brief  Disable Timestamp
02473   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02474   * @rmtoll CR           TSE           LL_RTC_TS_Disable
02475   * @param  RTCx RTC Instance
02476   * @retval None
02477   */
02478 __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
02479 {
02480   CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
02481 }
02482
02483 /**
02484   * @brief  Set Time-stamp event active edge
02485   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02486   * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
02487   * @rmtoll CR           TSEDGE        LL_RTC_TS_SetActiveEdge
02488   * @param  RTCx RTC Instance
02489   * @param  Edge This parameter can be one of the following values:
02490   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02491   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02492   * @retval None
02493   */
02494 __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
02495 {
02496   MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
02497 }
02498
02499 /**
02500   * @brief  Get Time-stamp event active edge
02501   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02502   * @rmtoll CR           TSEDGE        LL_RTC_TS_GetActiveEdge
02503   * @param  RTCx RTC Instance
02504   * @retval Returned value can be one of the following values:
02505   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02506   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02507   */
02508 __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
02509 {
02510   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
02511 }
02512
02513 /**
02514   * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
02515   * @rmtoll TSTR         PM            LL_RTC_TS_GetTimeFormat
02516   * @param  RTCx RTC Instance
02517   * @retval Returned value can be one of the following values:
02518   *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
02519   *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
02520   */
02521 __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
02522 {
02523   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
02524 }
02525
02526 /**
02527   * @brief  Get Timestamp Hours in BCD format
02528   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02529   * @rmtoll TSTR         HT            LL_RTC_TS_GetHour\n
02530   *         TSTR         HU            LL_RTC_TS_GetHour
02531   * @param  RTCx RTC Instance
02532   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02533   */
02534 __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
02535 {
02536   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_POSITION_TS_HU);
02537 }
02538
02539 /**
02540   * @brief  Get Timestamp Minutes in BCD format
02541   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02542   * @rmtoll TSTR         MNT           LL_RTC_TS_GetMinute\n
02543   *         TSTR         MNU           LL_RTC_TS_GetMinute
02544   * @param  RTCx RTC Instance
02545   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02546   */
02547 __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
02548 {
02549   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_POSITION_TS_MNU);
02550 }
02551
02552 /**
02553   * @brief  Get Timestamp Seconds in BCD format
02554   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02555   * @rmtoll TSTR         ST            LL_RTC_TS_GetSecond\n
02556   *         TSTR         SU            LL_RTC_TS_GetSecond
02557   * @param  RTCx RTC Instance
02558   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02559   */
02560 __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
02561 {
02562   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
02563 }
02564
02565 /**
02566   * @brief  Get Timestamp time (hour, minute and second) in BCD format
02567   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02568   * are available to get independently each parameter.
02569   * @rmtoll TSTR         HT            LL_RTC_TS_GetTime\n
02570   *         TSTR         HU            LL_RTC_TS_GetTime\n
02571   *         TSTR         MNT           LL_RTC_TS_GetTime\n
02572   *         TSTR         MNU           LL_RTC_TS_GetTime\n
02573   *         TSTR         ST            LL_RTC_TS_GetTime\n
02574   *         TSTR         SU            LL_RTC_TS_GetTime
02575   * @param  RTCx RTC Instance
02576   * @retval Combination of hours, minutes and seconds.
02577   */
02578 __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
02579 {
02580   return (uint32_t)(READ_BIT(RTCx->TSTR,
02581                              RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
02582 }
02583
02584 /**
02585   * @brief  Get Timestamp Week day
02586   * @rmtoll TSDR         WDU           LL_RTC_TS_GetWeekDay
02587   * @param  RTCx RTC Instance
02588   * @retval Returned value can be one of the following values:
02589   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02590   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02591   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02592   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02593   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02594   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02595   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02596   */
02597 __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
02598 {
02599   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_POSITION_TS_WDU);
02600 }
02601
02602 /**
02603   * @brief  Get Timestamp Month in BCD format
02604   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
02605   * @rmtoll TSDR         MT            LL_RTC_TS_GetMonth\n
02606   *         TSDR         MU            LL_RTC_TS_GetMonth
02607   * @param  RTCx RTC Instance
02608   * @retval Returned value can be one of the following values:
02609   *         @arg @ref LL_RTC_MONTH_JANUARY
02610   *         @arg @ref LL_RTC_MONTH_FEBRUARY
02611   *         @arg @ref LL_RTC_MONTH_MARCH
02612   *         @arg @ref LL_RTC_MONTH_APRIL
02613   *         @arg @ref LL_RTC_MONTH_MAY
02614   *         @arg @ref LL_RTC_MONTH_JUNE
02615   *         @arg @ref LL_RTC_MONTH_JULY
02616   *         @arg @ref LL_RTC_MONTH_AUGUST
02617   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
02618   *         @arg @ref LL_RTC_MONTH_OCTOBER
02619   *         @arg @ref LL_RTC_MONTH_NOVEMBER
02620   *         @arg @ref LL_RTC_MONTH_DECEMBER
02621   */
02622 __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
02623 {
02624   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_POSITION_TS_MU);
02625 }
02626
02627 /**
02628   * @brief  Get Timestamp Day in BCD format
02629   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02630   * @rmtoll TSDR         DT            LL_RTC_TS_GetDay\n
02631   *         TSDR         DU            LL_RTC_TS_GetDay
02632   * @param  RTCx RTC Instance
02633   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02634   */
02635 __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
02636 {
02637   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
02638 }
02639
02640 /**
02641   * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
02642   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
02643   * and __LL_RTC_GET_DAY are available to get independently each parameter.
02644   * @rmtoll TSDR         WDU           LL_RTC_TS_GetDate\n
02645   *         TSDR         MT            LL_RTC_TS_GetDate\n
02646   *         TSDR         MU            LL_RTC_TS_GetDate\n
02647   *         TSDR         DT            LL_RTC_TS_GetDate\n
02648   *         TSDR         DU            LL_RTC_TS_GetDate
02649   * @param  RTCx RTC Instance
02650   * @retval Combination of Weekday, Day and Month
02651   */
02652 __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
02653 {
02654   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
02655 }
02656
02657 /**
02658   * @brief  Get time-stamp sub second value
02659   * @rmtoll TSSSR        SS            LL_RTC_TS_GetSubSecond
02660   * @param  RTCx RTC Instance
02661   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
02662   */
02663 __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
02664 {
02665   return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
02666 }
02667
02668 #if defined(RTC_TAMPCR_TAMPTS)
02669 /**
02670   * @brief  Activate timestamp on tamper detection event
02671   * @rmtoll TAMPCR       TAMPTS        LL_RTC_TS_EnableOnTamper
02672   * @param  RTCx RTC Instance
02673   * @retval None
02674   */
02675 __STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
02676 {
02677   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
02678 }
02679
02680 /**
02681   * @brief  Disable timestamp on tamper detection event
02682   * @rmtoll TAMPCR       TAMPTS        LL_RTC_TS_DisableOnTamper
02683   * @param  RTCx RTC Instance
02684   * @retval None
02685   */
02686 __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
02687 {
02688   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
02689 }
02690 #endif /* RTC_TAMPCR_TAMPTS */
02691
02692 /**
02693   * @}
02694   */
02695
02696 /** @defgroup RTC_LL_EF_Tamper Tamper
02697   * @{
02698   */
02699
02700 /**
02701   * @brief  Enable RTC_TAMPx input detection
02702   * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Enable\n
02703   *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Enable\n
02704   *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Enable
02705   * @param  RTCx RTC Instance
02706   * @param  Tamper This parameter can be a combination of the following values:
02707   *         @arg @ref LL_RTC_TAMPER_1
02708   *         @arg @ref LL_RTC_TAMPER_2
02709   *         @arg @ref LL_RTC_TAMPER_3
02710   *
02711   * @retval None
02712   */
02713 __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
02714 {
02715   SET_BIT(RTCx->TAMPCR, Tamper);
02716 }
02717
02718 /**
02719   * @brief  Clear RTC_TAMPx input detection
02720   * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Disable\n
02721   *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Disable\n
02722   *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Disable
02723   * @param  RTCx RTC Instance
02724   * @param  Tamper This parameter can be a combination of the following values:
02725   *         @arg @ref LL_RTC_TAMPER_1
02726   *         @arg @ref LL_RTC_TAMPER_2
02727   *         @arg @ref LL_RTC_TAMPER_3
02728   *
02729   * @retval None
02730   */
02731 __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
02732 {
02733   CLEAR_BIT(RTCx->TAMPCR, Tamper);
02734 }
02735
02736 /**
02737   * @brief  Enable Tamper mask flag
02738   * @note Associated Tamper IT must not enabled when tamper mask is set.
02739   * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_EnableMask\n
02740   *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_EnableMask\n
02741   *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_EnableMask
02742   * @param  RTCx RTC Instance
02743   * @param  Mask This parameter can be a combination of the following values:
02744   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
02745   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
02746   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3
02747   *
02748   * @retval None
02749   */
02750 __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
02751 {
02752   SET_BIT(RTCx->TAMPCR, Mask);
02753 }
02754
02755 /**
02756   * @brief  Disable Tamper mask flag
02757   * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_DisableMask\n
02758   *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_DisableMask\n
02759   *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_DisableMask
02760   * @param  RTCx RTC Instance
02761   * @param  Mask This parameter can be a combination of the following values:
02762   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
02763   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
02764   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3
02765   *
02766   * @retval None
02767   */
02768 __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
02769 {
02770   CLEAR_BIT(RTCx->TAMPCR, Mask);
02771 }
02772
02773 /**
02774   * @brief  Enable backup register erase after Tamper event detection
02775   * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
02776   *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
02777   *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_EnableEraseBKP
02778   * @param  RTCx RTC Instance
02779   * @param  Tamper This parameter can be a combination of the following values:
02780   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
02781   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
02782   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3
02783   *
02784   * @retval None
02785   */
02786 __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
02787 {
02788   CLEAR_BIT(RTCx->TAMPCR, Tamper);
02789 }
02790
02791 /**
02792   * @brief  Disable backup register erase after Tamper event detection
02793   * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
02794   *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
02795   *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_DisableEraseBKP
02796   * @param  RTCx RTC Instance
02797   * @param  Tamper This parameter can be a combination of the following values:
02798   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
02799   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
02800   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3
02801   *
02802   * @retval None
02803   */
02804 __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
02805 {
02806   SET_BIT(RTCx->TAMPCR, Tamper);
02807 }
02808
02809 #if defined(RTC_TAMPCR_TAMPPUDIS)
02810 /**
02811   * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
02812   * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
02813   * @param  RTCx RTC Instance
02814   * @retval None
02815   */
02816 __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
02817 {
02818   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
02819 }
02820
02821 /**
02822   * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
02823   * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
02824   * @param  RTCx RTC Instance
02825   * @retval None
02826   */
02827 __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
02828 {
02829   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
02830 }
02831 #endif /* RTC_TAMPCR_TAMPPUDIS */
02832
02833 #if defined(RTC_TAMPCR_TAMPPRCH)
02834 /**
02835   * @brief  Set RTC_TAMPx precharge duration
02836   * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
02837   * @param  RTCx RTC Instance
02838   * @param  Duration This parameter can be one of the following values:
02839   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
02840   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
02841   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
02842   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
02843   * @retval None
02844   */
02845 __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
02846 {
02847   MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration);
02848 }
02849
02850 /**
02851   * @brief  Get RTC_TAMPx precharge duration
02852   * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
02853   * @param  RTCx RTC Instance
02854   * @retval Returned value can be one of the following values:
02855   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
02856   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
02857   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
02858   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
02859   */
02860 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
02861 {
02862   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH));
02863 }
02864 #endif /* RTC_TAMPCR_TAMPPRCH */
02865
02866 #if defined(RTC_TAMPCR_TAMPFLT)
02867 /**
02868   * @brief  Set RTC_TAMPx filter count
02869   * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
02870   * @param  RTCx RTC Instance
02871   * @param  FilterCount This parameter can be one of the following values:
02872   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
02873   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
02874   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
02875   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
02876   * @retval None
02877   */
02878 __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
02879 {
02880   MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount);
02881 }
02882
02883 /**
02884   * @brief  Get RTC_TAMPx filter count
02885   * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
02886   * @param  RTCx RTC Instance
02887   * @retval Returned value can be one of the following values:
02888   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
02889   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
02890   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
02891   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
02892   */
02893 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
02894 {
02895   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT));
02896 }
02897 #endif /* RTC_TAMPCR_TAMPFLT */
02898
02899 #if defined(RTC_TAMPCR_TAMPFREQ)
02900 /**
02901   * @brief  Set Tamper sampling frequency
02902   * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
02903   * @param  RTCx RTC Instance
02904   * @param  SamplingFreq This parameter can be one of the following values:
02905   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
02906   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
02907   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
02908   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
02909   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
02910   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
02911   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
02912   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
02913   * @retval None
02914   */
02915 __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
02916 {
02917   MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq);
02918 }
02919
02920 /**
02921   * @brief  Get Tamper sampling frequency
02922   * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
02923   * @param  RTCx RTC Instance
02924   * @retval Returned value can be one of the following values:
02925   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
02926   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
02927   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
02928   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
02929   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
02930   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
02931   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
02932   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
02933   */
02934 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
02935 {
02936   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ));
02937 }
02938 #endif /* RTC_TAMPCR_TAMPFREQ */
02939
02940 /**
02941   * @brief  Enable Active level for Tamper input
02942   * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel\n
02943   *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel\n
02944   *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel
02945   * @param  RTCx RTC Instance
02946   * @param  Tamper This parameter can be a combination of the following values:
02947   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
02948   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
02949   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
02950   *
02951   * @retval None
02952   */
02953 __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
02954 {
02955   SET_BIT(RTCx->TAMPCR, Tamper);
02956 }
02957
02958 /**
02959   * @brief  Disable Active level for Tamper input
02960   * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel\n
02961   *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel\n
02962   *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel
02963   * @param  RTCx RTC Instance
02964   * @param  Tamper This parameter can be a combination of the following values:
02965   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
02966   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
02967   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
02968   *
02969   * @retval None
02970   */
02971 __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
02972 {
02973   CLEAR_BIT(RTCx->TAMPCR, Tamper);
02974 }
02975
02976 /**
02977   * @}
02978   */
02979
02980 #if defined(RTC_WAKEUP_SUPPORT)
02981 /** @defgroup RTC_LL_EF_Wakeup Wakeup
02982   * @{
02983   */
02984
02985 /**
02986   * @brief  Enable Wakeup timer
02987   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02988   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Enable
02989   * @param  RTCx RTC Instance
02990   * @retval None
02991   */
02992 __STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
02993 {
02994   SET_BIT(RTCx->CR, RTC_CR_WUTE);
02995 }
02996
02997 /**
02998   * @brief  Disable Wakeup timer
02999   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03000   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Disable
03001   * @param  RTCx RTC Instance
03002   * @retval None
03003   */
03004 __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
03005 {
03006   CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
03007 }
03008
03009 /**
03010   * @brief  Check if Wakeup timer is enabled or not
03011   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_IsEnabled
03012   * @param  RTCx RTC Instance
03013   * @retval State of bit (1 or 0).
03014   */
03015 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
03016 {
03017   return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
03018 }
03019
03020 /**
03021   * @brief  Select Wakeup clock
03022   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03023   * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
03024   * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
03025   * @param  RTCx RTC Instance
03026   * @param  WakeupClock This parameter can be one of the following values:
03027   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
03028   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
03029   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
03030   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
03031   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
03032   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
03033   * @retval None
03034   */
03035 __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
03036 {
03037   MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
03038 }
03039
03040 /**
03041   * @brief  Get Wakeup clock
03042   * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
03043   * @param  RTCx RTC Instance
03044   * @retval Returned value can be one of the following values:
03045   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
03046   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
03047   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
03048   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
03049   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
03050   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
03051   */
03052 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
03053 {
03054   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
03055 }
03056
03057 /**
03058   * @brief  Set Wakeup auto-reload value
03059   * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
03060   * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
03061   * @param  RTCx RTC Instance
03062   * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
03063   * @retval None
03064   */
03065 __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
03066 {
03067   MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
03068 }
03069
03070 /**
03071   * @brief  Get Wakeup auto-reload value
03072   * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
03073   * @param  RTCx RTC Instance
03074   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
03075   */
03076 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
03077 {
03078   return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
03079 }
03080
03081 /**
03082   * @}
03083   */
03084 #endif /* RTC_WAKEUP_SUPPORT */
03085
03086 #if defined(RTC_BACKUP_SUPPORT)
03087 /** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
03088   * @{
03089   */
03090
03091 /**
03092   * @brief  Writes a data in a specified RTC Backup data register.
03093   * @rmtoll BKPxR        BKP           LL_RTC_BAK_SetRegister
03094   * @param  RTCx RTC Instance
03095   * @param  BackupRegister This parameter can be one of the following values:
03096   *         @arg @ref LL_RTC_BKP_DR0
03097   *         @arg @ref LL_RTC_BKP_DR1
03098   *         @arg @ref LL_RTC_BKP_DR2
03099   *         @arg @ref LL_RTC_BKP_DR3
03100   *         @arg @ref LL_RTC_BKP_DR4
03101   *         @arg @ref LL_RTC_BKP_DR5
03102   *         @arg @ref LL_RTC_BKP_DR6
03103   *         @arg @ref LL_RTC_BKP_DR7
03104   *         @arg @ref LL_RTC_BKP_DR8
03105   *         @arg @ref LL_RTC_BKP_DR9
03106   *         @arg @ref LL_RTC_BKP_DR10
03107   *         @arg @ref LL_RTC_BKP_DR11
03108   *         @arg @ref LL_RTC_BKP_DR12
03109   *         @arg @ref LL_RTC_BKP_DR13
03110   *         @arg @ref LL_RTC_BKP_DR14
03111   *         @arg @ref LL_RTC_BKP_DR15
03112   *         @arg @ref LL_RTC_BKP_DR16
03113   *         @arg @ref LL_RTC_BKP_DR17
03114   *         @arg @ref LL_RTC_BKP_DR18
03115   *         @arg @ref LL_RTC_BKP_DR19
03116   *         @arg @ref LL_RTC_BKP_DR20
03117   *         @arg @ref LL_RTC_BKP_DR21
03118   *         @arg @ref LL_RTC_BKP_DR22
03119   *         @arg @ref LL_RTC_BKP_DR23
03120   *         @arg @ref LL_RTC_BKP_DR24
03121   *         @arg @ref LL_RTC_BKP_DR25
03122   *         @arg @ref LL_RTC_BKP_DR26
03123   *         @arg @ref LL_RTC_BKP_DR27
03124   *         @arg @ref LL_RTC_BKP_DR28
03125   *         @arg @ref LL_RTC_BKP_DR29
03126   *         @arg @ref LL_RTC_BKP_DR30
03127   *         @arg @ref LL_RTC_BKP_DR31
03128   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03129   * @retval None
03130   */
03131 __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
03132 {
03133   register uint32_t tmp = 0U;
03134
03135   tmp = (uint32_t)(&(RTCx->BKP0R));
03136   tmp += (BackupRegister * 4U);
03137
03138   /* Write the specified register */
03139   *(__IO uint32_t *)tmp = (uint32_t)Data;
03140 }
03141
03142 /**
03143   * @brief  Reads data from the specified RTC Backup data Register.
03144   * @rmtoll BKPxR        BKP           LL_RTC_BAK_GetRegister
03145   * @param  RTCx RTC Instance
03146   * @param  BackupRegister This parameter can be one of the following values:
03147   *         @arg @ref LL_RTC_BKP_DR0
03148   *         @arg @ref LL_RTC_BKP_DR1
03149   *         @arg @ref LL_RTC_BKP_DR2
03150   *         @arg @ref LL_RTC_BKP_DR3
03151   *         @arg @ref LL_RTC_BKP_DR4
03152   *         @arg @ref LL_RTC_BKP_DR5
03153   *         @arg @ref LL_RTC_BKP_DR6
03154   *         @arg @ref LL_RTC_BKP_DR7
03155   *         @arg @ref LL_RTC_BKP_DR8
03156   *         @arg @ref LL_RTC_BKP_DR9
03157   *         @arg @ref LL_RTC_BKP_DR10
03158   *         @arg @ref LL_RTC_BKP_DR11
03159   *         @arg @ref LL_RTC_BKP_DR12
03160   *         @arg @ref LL_RTC_BKP_DR13
03161   *         @arg @ref LL_RTC_BKP_DR14
03162   *         @arg @ref LL_RTC_BKP_DR15
03163   *         @arg @ref LL_RTC_BKP_DR16
03164   *         @arg @ref LL_RTC_BKP_DR17
03165   *         @arg @ref LL_RTC_BKP_DR18
03166   *         @arg @ref LL_RTC_BKP_DR19
03167   *         @arg @ref LL_RTC_BKP_DR20
03168   *         @arg @ref LL_RTC_BKP_DR21
03169   *         @arg @ref LL_RTC_BKP_DR22
03170   *         @arg @ref LL_RTC_BKP_DR23
03171   *         @arg @ref LL_RTC_BKP_DR24
03172   *         @arg @ref LL_RTC_BKP_DR25
03173   *         @arg @ref LL_RTC_BKP_DR26
03174   *         @arg @ref LL_RTC_BKP_DR27
03175   *         @arg @ref LL_RTC_BKP_DR28
03176   *         @arg @ref LL_RTC_BKP_DR29
03177   *         @arg @ref LL_RTC_BKP_DR30
03178   *         @arg @ref LL_RTC_BKP_DR31
03179   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03180   */
03181 __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
03182 {
03183   register uint32_t tmp = 0U;
03184
03185   tmp = (uint32_t)(&(RTCx->BKP0R));
03186   tmp += (BackupRegister * 4U);
03187
03188   /* Read the specified register */
03189   return (*(__IO uint32_t *)tmp);
03190 }
03191
03192 /**
03193   * @}
03194   */
03195 #endif /* RTC_BACKUP_SUPPORT */
03196
03197 /** @defgroup RTC_LL_EF_Calibration Calibration
03198   * @{
03199   */
03200
03201 /**
03202   * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
03203   * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03204   * @rmtoll CR           COE           LL_RTC_CAL_SetOutputFreq\n
03205   *         CR           COSEL         LL_RTC_CAL_SetOutputFreq
03206   * @param  RTCx RTC Instance
03207   * @param  Frequency This parameter can be one of the following values:
03208   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03209   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03210   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03211   * @retval None
03212   */
03213 __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
03214 {
03215   MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
03216 }
03217
03218 /**
03219   * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
03220   * @rmtoll CR           COE           LL_RTC_CAL_GetOutputFreq\n
03221   *         CR           COSEL         LL_RTC_CAL_GetOutputFreq
03222   * @param  RTCx RTC Instance
03223   * @retval Returned value can be one of the following values:
03224   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03225   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03226   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03227   */
03228 __STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
03229 {
03230   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
03231 }
03232
03233 /**
03234   * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
03235   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03236   * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
03237   * @rmtoll CALR         CALP          LL_RTC_CAL_SetPulse
03238   * @param  RTCx RTC Instance
03239   * @param  Pulse This parameter can be one of the following values:
03240   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
03241   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
03242   * @retval None
03243   */
03244 __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
03245 {
03246   MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
03247 }
03248
03249 /**
03250   * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
03251   * @rmtoll CALR         CALP          LL_RTC_CAL_IsPulseInserted
03252   * @param  RTCx RTC Instance
03253   * @retval State of bit (1 or 0).
03254   */
03255 __STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
03256 {
03257   return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
03258 }
03259
03260 /**
03261   * @brief  Set the calibration cycle period
03262   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03263   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
03264   * @rmtoll CALR         CALW8         LL_RTC_CAL_SetPeriod\n
03265   *         CALR         CALW16        LL_RTC_CAL_SetPeriod
03266   * @param  RTCx RTC Instance
03267   * @param  Period This parameter can be one of the following values:
03268   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03269   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03270   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03271   * @retval None
03272   */
03273 __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
03274 {
03275   MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
03276 }
03277
03278 /**
03279   * @brief  Get the calibration cycle period
03280   * @rmtoll CALR         CALW8         LL_RTC_CAL_GetPeriod\n
03281   *         CALR         CALW16        LL_RTC_CAL_GetPeriod
03282   * @param  RTCx RTC Instance
03283   * @retval Returned value can be one of the following values:
03284   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03285   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03286   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03287   */
03288 __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
03289 {
03290   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
03291 }
03292
03293 /**
03294   * @brief  Set Calibration minus
03295   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03296   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
03297   * @rmtoll CALR         CALM          LL_RTC_CAL_SetMinus
03298   * @param  RTCx RTC Instance
03299   * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
03300   * @retval None
03301   */
03302 __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
03303 {
03304   MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
03305 }
03306
03307 /**
03308   * @brief  Get Calibration minus
03309   * @rmtoll CALR         CALM          LL_RTC_CAL_GetMinus
03310   * @param  RTCx RTC Instance
03311   * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
03312   */
03313 __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
03314 {
03315   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
03316 }
03317
03318 /**
03319   * @}
03320   */
03321
03322 /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
03323   * @{
03324   */
03325
03326 /**
03327   * @brief  Get Internal Time-stamp flag
03328   * @rmtoll ISR          ITSF          LL_RTC_IsActiveFlag_ITS
03329   * @param  RTCx RTC Instance
03330   * @retval State of bit (1 or 0).
03331   */
03332 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
03333 {
03334   return (READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF));
03335 }
03336
03337 /**
03338   * @brief  Get Recalibration pending Flag
03339   * @rmtoll ISR          RECALPF       LL_RTC_IsActiveFlag_RECALP
03340   * @param  RTCx RTC Instance
03341   * @retval State of bit (1 or 0).
03342   */
03343 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
03344 {
03345   return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
03346 }
03347
03348 #if defined(RTC_TAMPER3_SUPPORT)
03349 /**
03350   * @brief  Get RTC_TAMP3 detection flag
03351   * @rmtoll ISR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
03352   * @param  RTCx RTC Instance
03353   * @retval State of bit (1 or 0).
03354   */
03355 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
03356 {
03357   return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F));
03358 }
03359 #endif /* RTC_TAMPER3_SUPPORT */
03360
03361 #if defined(RTC_TAMPER2_SUPPORT)
03362 /**
03363   * @brief  Get RTC_TAMP2 detection flag
03364   * @rmtoll ISR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
03365   * @param  RTCx RTC Instance
03366   * @retval State of bit (1 or 0).
03367   */
03368 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
03369 {
03370   return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
03371 }
03372 #endif /* RTC_TAMPER2_SUPPORT */
03373
03374 #if defined(RTC_TAMPER1_SUPPORT)
03375 /**
03376   * @brief  Get RTC_TAMP1 detection flag
03377   * @rmtoll ISR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
03378   * @param  RTCx RTC Instance
03379   * @retval State of bit (1 or 0).
03380   */
03381 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
03382 {
03383   return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
03384 }
03385 #endif /* RTC_TAMPER1_SUPPORT */
03386
03387 /**
03388   * @brief  Get Time-stamp overflow flag
03389   * @rmtoll ISR          TSOVF         LL_RTC_IsActiveFlag_TSOV
03390   * @param  RTCx RTC Instance
03391   * @retval State of bit (1 or 0).
03392   */
03393 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
03394 {
03395   return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
03396 }
03397
03398 /**
03399   * @brief  Get Time-stamp flag
03400   * @rmtoll ISR          TSF           LL_RTC_IsActiveFlag_TS
03401   * @param  RTCx RTC Instance
03402   * @retval State of bit (1 or 0).
03403   */
03404 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
03405 {
03406   return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
03407 }
03408
03409 #if defined(RTC_WAKEUP_SUPPORT)
03410 /**
03411   * @brief  Get Wakeup timer flag
03412   * @rmtoll ISR          WUTF          LL_RTC_IsActiveFlag_WUT
03413   * @param  RTCx RTC Instance
03414   * @retval State of bit (1 or 0).
03415   */
03416 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
03417 {
03418   return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
03419 }
03420 #endif /* RTC_WAKEUP_SUPPORT */
03421
03422 /**
03423   * @brief  Get Alarm B flag
03424   * @rmtoll ISR          ALRBF         LL_RTC_IsActiveFlag_ALRB
03425   * @param  RTCx RTC Instance
03426   * @retval State of bit (1 or 0).
03427   */
03428 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
03429 {
03430   return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
03431 }
03432
03433 /**
03434   * @brief  Get Alarm A flag
03435   * @rmtoll ISR          ALRAF         LL_RTC_IsActiveFlag_ALRA
03436   * @param  RTCx RTC Instance
03437   * @retval State of bit (1 or 0).
03438   */
03439 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
03440 {
03441   return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
03442 }
03443
03444 /**
03445   * @brief  Clear Internal Time-stamp flag
03446   * @rmtoll ISR          ITSF          LL_RTC_ClearFlag_ITS
03447   * @param  RTCx RTC Instance
03448   * @retval None
03449   */
03450 __STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
03451 {
03452   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ITSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03453 }
03454
03455 #if defined(RTC_TAMPER3_SUPPORT)
03456 /**
03457   * @brief  Clear RTC_TAMP3 detection flag
03458   * @rmtoll ISR          TAMP3F        LL_RTC_ClearFlag_TAMP3
03459   * @param  RTCx RTC Instance
03460   * @retval None
03461   */
03462 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
03463 {
03464   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03465 }
03466 #endif /* RTC_TAMPER3_SUPPORT */
03467
03468 #if defined(RTC_TAMPER2_SUPPORT)
03469 /**
03470   * @brief  Clear RTC_TAMP2 detection flag
03471   * @rmtoll ISR          TAMP2F        LL_RTC_ClearFlag_TAMP2
03472   * @param  RTCx RTC Instance
03473   * @retval None
03474   */
03475 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
03476 {
03477   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03478 }
03479 #endif /* RTC_TAMPER2_SUPPORT */
03480
03481 #if defined(RTC_TAMPER1_SUPPORT)
03482 /**
03483   * @brief  Clear RTC_TAMP1 detection flag
03484   * @rmtoll ISR          TAMP1F        LL_RTC_ClearFlag_TAMP1
03485   * @param  RTCx RTC Instance
03486   * @retval None
03487   */
03488 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
03489 {
03490   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03491 }
03492 #endif /* RTC_TAMPER1_SUPPORT */
03493
03494 /**
03495   * @brief  Clear Time-stamp overflow flag
03496   * @rmtoll ISR          TSOVF         LL_RTC_ClearFlag_TSOV
03497   * @param  RTCx RTC Instance
03498   * @retval None
03499   */
03500 __STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
03501 {
03502   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03503 }
03504
03505 /**
03506   * @brief  Clear Time-stamp flag
03507   * @rmtoll ISR          TSF           LL_RTC_ClearFlag_TS
03508   * @param  RTCx RTC Instance
03509   * @retval None
03510   */
03511 __STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
03512 {
03513   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03514 }
03515
03516 #if defined(RTC_WAKEUP_SUPPORT)
03517 /**
03518   * @brief  Clear Wakeup timer flag
03519   * @rmtoll ISR          WUTF          LL_RTC_ClearFlag_WUT
03520   * @param  RTCx RTC Instance
03521   * @retval None
03522   */
03523 __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
03524 {
03525   WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03526 }
03527 #endif /* RTC_WAKEUP_SUPPORT */
03528
03529 /**
03530   * @brief  Clear Alarm B flag
03531   * @rmtoll ISR          ALRBF         LL_RTC_ClearFlag_ALRB
03532   * @param  RTCx RTC Instance
03533   * @retval None
03534   */
03535 __STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
03536 {
03537   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03538 }
03539
03540 /**
03541   * @brief  Clear Alarm A flag
03542   * @rmtoll ISR          ALRAF         LL_RTC_ClearFlag_ALRA
03543   * @param  RTCx RTC Instance
03544   * @retval None
03545   */
03546 __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
03547 {
03548   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03549 }
03550
03551 /**
03552   * @brief  Get Initialization flag
03553   * @rmtoll ISR          INITF         LL_RTC_IsActiveFlag_INIT
03554   * @param  RTCx RTC Instance
03555   * @retval State of bit (1 or 0).
03556   */
03557 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
03558 {
03559   return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
03560 }
03561
03562 /**
03563   * @brief  Get Registers synchronization flag
03564   * @rmtoll ISR          RSF           LL_RTC_IsActiveFlag_RS
03565   * @param  RTCx RTC Instance
03566   * @retval State of bit (1 or 0).
03567   */
03568 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
03569 {
03570   return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
03571 }
03572
03573 /**
03574   * @brief  Clear Registers synchronization flag
03575   * @rmtoll ISR          RSF           LL_RTC_ClearFlag_RS
03576   * @param  RTCx RTC Instance
03577   * @retval None
03578   */
03579 __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
03580 {
03581   WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03582 }
03583
03584 /**
03585   * @brief  Get Initialization status flag
03586   * @rmtoll ISR          INITS         LL_RTC_IsActiveFlag_INITS
03587   * @param  RTCx RTC Instance
03588   * @retval State of bit (1 or 0).
03589   */
03590 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
03591 {
03592   return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
03593 }
03594
03595 /**
03596   * @brief  Get Shift operation pending flag
03597   * @rmtoll ISR          SHPF          LL_RTC_IsActiveFlag_SHP
03598   * @param  RTCx RTC Instance
03599   * @retval State of bit (1 or 0).
03600   */
03601 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
03602 {
03603   return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
03604 }
03605
03606 #if defined(RTC_WAKEUP_SUPPORT)
03607 /**
03608   * @brief  Get Wakeup timer write flag
03609   * @rmtoll ISR          WUTWF         LL_RTC_IsActiveFlag_WUTW
03610   * @param  RTCx RTC Instance
03611   * @retval State of bit (1 or 0).
03612   */
03613 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
03614 {
03615   return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
03616 }
03617 #endif /* RTC_WAKEUP_SUPPORT */
03618
03619 /**
03620   * @brief  Get Alarm B write flag
03621   * @rmtoll ISR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW
03622   * @param  RTCx RTC Instance
03623   * @retval State of bit (1 or 0).
03624   */
03625 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
03626 {
03627   return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
03628 }
03629
03630 /**
03631   * @brief  Get Alarm A write flag
03632   * @rmtoll ISR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW
03633   * @param  RTCx RTC Instance
03634   * @retval State of bit (1 or 0).
03635   */
03636 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
03637 {
03638   return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
03639 }
03640
03641 /**
03642   * @}
03643   */
03644
03645 /** @defgroup RTC_LL_EF_IT_Management IT_Management
03646   * @{
03647   */
03648
03649 /**
03650   * @brief  Enable Time-stamp interrupt
03651   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03652   * @rmtoll CR           TSIE          LL_RTC_EnableIT_TS
03653   * @param  RTCx RTC Instance
03654   * @retval None
03655   */
03656 __STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
03657 {
03658   SET_BIT(RTCx->CR, RTC_CR_TSIE);
03659 }
03660
03661 /**
03662   * @brief  Disable Time-stamp interrupt
03663   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03664   * @rmtoll CR           TSIE          LL_RTC_DisableIT_TS
03665   * @param  RTCx RTC Instance
03666   * @retval None
03667   */
03668 __STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
03669 {
03670   CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
03671 }
03672
03673 #if defined(RTC_WAKEUP_SUPPORT)
03674 /**
03675   * @brief  Enable Wakeup timer interrupt
03676   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03677   * @rmtoll CR           WUTIE         LL_RTC_EnableIT_WUT
03678   * @param  RTCx RTC Instance
03679   * @retval None
03680   */
03681 __STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
03682 {
03683   SET_BIT(RTCx->CR, RTC_CR_WUTIE);
03684 }
03685
03686 /**
03687   * @brief  Disable Wakeup timer interrupt
03688   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03689   * @rmtoll CR           WUTIE         LL_RTC_DisableIT_WUT
03690   * @param  RTCx RTC Instance
03691   * @retval None
03692   */
03693 __STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
03694 {
03695   CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
03696 }
03697 #endif /* RTC_WAKEUP_SUPPORT */
03698
03699 /**
03700   * @brief  Enable Alarm B interrupt
03701   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03702   * @rmtoll CR           ALRBIE        LL_RTC_EnableIT_ALRB
03703   * @param  RTCx RTC Instance
03704   * @retval None
03705   */
03706 __STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
03707 {
03708   SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
03709 }
03710
03711 /**
03712   * @brief  Disable Alarm B interrupt
03713   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03714   * @rmtoll CR           ALRBIE        LL_RTC_DisableIT_ALRB
03715   * @param  RTCx RTC Instance
03716   * @retval None
03717   */
03718 __STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
03719 {
03720   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
03721 }
03722
03723 /**
03724   * @brief  Enable Alarm A interrupt
03725   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03726   * @rmtoll CR           ALRAIE        LL_RTC_EnableIT_ALRA
03727   * @param  RTCx RTC Instance
03728   * @retval None
03729   */
03730 __STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
03731 {
03732   SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
03733 }
03734
03735 /**
03736   * @brief  Disable Alarm A interrupt
03737   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03738   * @rmtoll CR           ALRAIE        LL_RTC_DisableIT_ALRA
03739   * @param  RTCx RTC Instance
03740   * @retval None
03741   */
03742 __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
03743 {
03744   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
03745 }
03746
03747 #if defined(RTC_TAMPER3_SUPPORT)
03748 /**
03749   * @brief  Enable Tamper 3 interrupt
03750   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_EnableIT_TAMP3
03751   * @param  RTCx RTC Instance
03752   * @retval None
03753   */
03754 __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
03755 {
03756   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
03757 }
03758
03759 /**
03760   * @brief  Disable Tamper 3 interrupt
03761   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_DisableIT_TAMP3
03762   * @param  RTCx RTC Instance
03763   * @retval None
03764   */
03765 __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
03766 {
03767   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
03768 }
03769 #endif /* RTC_TAMPER3_SUPPORT */
03770
03771 #if defined(RTC_TAMPER2_SUPPORT)
03772 /**
03773   * @brief  Enable Tamper 2 interrupt
03774   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_EnableIT_TAMP2
03775   * @param  RTCx RTC Instance
03776   * @retval None
03777   */
03778 __STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
03779 {
03780   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
03781 }
03782
03783 /**
03784   * @brief  Disable Tamper 2 interrupt
03785   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_DisableIT_TAMP2
03786   * @param  RTCx RTC Instance
03787   * @retval None
03788   */
03789 __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
03790 {
03791   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
03792 }
03793 #endif /* RTC_TAMPER2_SUPPORT */
03794
03795 #if defined(RTC_TAMPER1_SUPPORT)
03796 /**
03797   * @brief  Enable Tamper 1 interrupt
03798   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_EnableIT_TAMP1
03799   * @param  RTCx RTC Instance
03800   * @retval None
03801   */
03802 __STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
03803 {
03804   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
03805 }
03806
03807 /**
03808   * @brief  Disable Tamper 1 interrupt
03809   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_DisableIT_TAMP1
03810   * @param  RTCx RTC Instance
03811   * @retval None
03812   */
03813 __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
03814 {
03815   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
03816 }
03817 #endif /* RTC_TAMPER1_SUPPORT */
03818
03819 /**
03820   * @brief  Enable all Tamper Interrupt
03821   * @rmtoll TAMPCR       TAMPIE        LL_RTC_EnableIT_TAMP
03822   * @param  RTCx RTC Instance
03823   * @retval None
03824   */
03825 __STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
03826 {
03827   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
03828 }
03829
03830 /**
03831   * @brief  Disable all Tamper Interrupt
03832   * @rmtoll TAMPCR       TAMPIE        LL_RTC_DisableIT_TAMP
03833   * @param  RTCx RTC Instance
03834   * @retval None
03835   */
03836 __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
03837 {
03838   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
03839 }
03840
03841 /**
03842   * @brief  Check if  Time-stamp interrupt is enabled or not
03843   * @rmtoll CR           TSIE          LL_RTC_IsEnabledIT_TS
03844   * @param  RTCx RTC Instance
03845   * @retval State of bit (1 or 0).
03846   */
03847 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
03848 {
03849   return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
03850 }
03851
03852 #if defined(RTC_WAKEUP_SUPPORT)
03853 /**
03854   * @brief  Check if  Wakeup timer interrupt is enabled or not
03855   * @rmtoll CR           WUTIE         LL_RTC_IsEnabledIT_WUT
03856   * @param  RTCx RTC Instance
03857   * @retval State of bit (1 or 0).
03858   */
03859 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
03860 {
03861   return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
03862 }
03863 #endif /* RTC_WAKEUP_SUPPORT */
03864
03865 /**
03866   * @brief  Check if  Alarm B interrupt is enabled or not
03867   * @rmtoll CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
03868   * @param  RTCx RTC Instance
03869   * @retval State of bit (1 or 0).
03870   */
03871 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
03872 {
03873   return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
03874 }
03875
03876 /**
03877   * @brief  Check if  Alarm A interrupt is enabled or not
03878   * @rmtoll CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
03879   * @param  RTCx RTC Instance
03880   * @retval State of bit (1 or 0).
03881   */
03882 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
03883 {
03884   return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
03885 }
03886
03887 #if defined(RTC_TAMPER3_SUPPORT)
03888 /**
03889   * @brief  Check if  Tamper 3 interrupt is enabled or not
03890   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_IsEnabledIT_TAMP3
03891   * @param  RTCx RTC Instance
03892   * @retval State of bit (1 or 0).
03893   */
03894 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
03895 {
03896   return (READ_BIT(RTCx->TAMPCR,
03897                    RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE));
03898 }
03899 #endif /* RTC_TAMPER3_SUPPORT */
03900
03901 #if defined(RTC_TAMPER2_SUPPORT)
03902 /**
03903   * @brief  Check if  Tamper 2 interrupt is enabled or not
03904   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_IsEnabledIT_TAMP2
03905   * @param  RTCx RTC Instance
03906   * @retval State of bit (1 or 0).
03907   */
03908 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
03909 {
03910   return (READ_BIT(RTCx->TAMPCR,
03911                    RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE));
03912 #endif /* RTC_TAMPER2_SUPPORT */
03913 }
03914
03915 #if defined(RTC_TAMPER1_SUPPORT)
03916 /**
03917   * @brief  Check if  Tamper 1 interrupt is enabled or not
03918   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_IsEnabledIT_TAMP1
03919   * @param  RTCx RTC Instance
03920   * @retval State of bit (1 or 0).
03921   */
03922 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
03923 {
03924   return (READ_BIT(RTCx->TAMPCR,
03925                    RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE));
03926 }
03927 #endif /* RTC_TAMPER1_SUPPORT */
03928
03929 /**
03930   * @brief  Check if all the TAMPER interrupts are enabled or not
03931   * @rmtoll TAMPCR       TAMPIE        LL_RTC_IsEnabledIT_TAMP
03932   * @param  RTCx RTC Instance
03933   * @retval State of bit (1 or 0).
03934   */
03935 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
03936 {
03937   return (READ_BIT(RTCx->TAMPCR,
03938                    RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE));
03939 }
03940
03941 /**
03942   * @}
03943   */
03944
03945 #if defined(USE_FULL_LL_DRIVER)
03946 /** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
03947   * @{
03948   */
03949
03950 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
03951 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
03952 void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
03953 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
03954 void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
03955 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
03956 void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
03957 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03958 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03959 void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03960 void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03961 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
03962 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
03963 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
03964
03965 /**
03966   * @}
03967   */
03968 #endif /* USE_FULL_LL_DRIVER */
03969
03970 /**
03971   * @}
03972   */
03973
03974 /**
03975   * @}
03976   */
03977
03978 #endif /* defined(RTC) */
03979
03980 /**
03981   * @}
03982   */
03983
03984 #ifdef __cplusplus
03985 }
03986 #endif
03987
03988 #endif /* __STM32L4xx_LL_RTC_H */
03989
03990 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_spi.c Source File

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stm32l4xx_ll_spi.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_spi.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SPI LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_spi.h"
00041 #include "stm32l4xx_ll_bus.h"
00042
00043 #ifdef  USE_FULL_ASSERT
00044 #include "stm32_assert.h"
00045 #else
00046 #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
00054
00055 /** @addtogroup SPI_LL
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
00064   * @{
00065   */
00066 /* SPI registers Masks */
00067 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
00068                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
00069                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
00070                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
00071                                             SPI_CR1_BIDIMODE)
00072 /**
00073   * @}
00074   */
00075
00076 /* Private macros ------------------------------------------------------------*/
00077 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
00078   * @{
00079   */
00080 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
00081                                               || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
00082                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
00083                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
00084
00085 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
00086                                 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
00087
00088 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)  \
00089                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
00090                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
00091                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
00092                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
00093                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
00094                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
00095                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
00096                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
00097                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
00098                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
00099                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
00100                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
00101
00102 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
00103                                     || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
00104
00105 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
00106                                  || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
00107
00108 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
00109                                || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
00110                                || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
00111
00112 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
00113                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
00114                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
00115                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
00116                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
00117                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
00118                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
00119                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
00120
00121 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
00122                                     || ((__VALUE__) == LL_SPI_MSB_FIRST))
00123
00124 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
00125                                           || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
00126
00127 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
00128
00129 /**
00130   * @}
00131   */
00132
00133 /* Private function prototypes -----------------------------------------------*/
00134
00135 /* Exported functions --------------------------------------------------------*/
00136 /** @addtogroup SPI_LL_Exported_Functions
00137   * @{
00138   */
00139
00140 /** @addtogroup SPI_LL_EF_Init
00141   * @{
00142   */
00143
00144 /**
00145   * @brief  De-initialize the SPI registers to their default reset values.
00146   * @param  SPIx SPI Instance
00147   * @retval An ErrorStatus enumeration value:
00148   *          - SUCCESS: SPI registers are de-initialized
00149   *          - ERROR: SPI registers are not de-initialized
00150   */
00151 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
00152 {
00153   ErrorStatus status = ERROR;
00154
00155   /* Check the parameters */
00156   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00157
00158 #if defined(SPI1)
00159   if (SPIx == SPI1)
00160   {
00161     /* Force reset of SPI clock */
00162     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
00163
00164     /* Release reset of SPI clock */
00165     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
00166
00167     status = SUCCESS;
00168   }
00169 #endif /* SPI1 */
00170 #if defined(SPI2)
00171   if (SPIx == SPI2)
00172   {
00173     /* Force reset of SPI clock */
00174     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
00175
00176     /* Release reset of SPI clock */
00177     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
00178
00179     status = SUCCESS;
00180   }
00181 #endif /* SPI2 */
00182 #if defined(SPI3)
00183   if (SPIx == SPI3)
00184   {
00185     /* Force reset of SPI clock */
00186     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
00187
00188     /* Release reset of SPI clock */
00189     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
00190
00191     status = SUCCESS;
00192   }
00193 #endif /* SPI3 */
00194
00195   return status;
00196 }
00197
00198 /**
00199   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
00200   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00201   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00202   * @param  SPIx SPI Instance
00203   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00204   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
00205   */
00206 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
00207 {
00208   ErrorStatus status = ERROR;
00209
00210   /* Check the SPI Instance SPIx*/
00211   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00212
00213   /* Check the SPI parameters from SPI_InitStruct*/
00214   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
00215   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
00216   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
00217   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
00218   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
00219   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
00220   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
00221   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
00222   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
00223
00224   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
00225   {
00226     /*---------------------------- SPIx CR1 Configuration ------------------------
00227      * Configure SPIx CR1 with parameters:
00228      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
00229      * - Master/Slave Mode:  SPI_CR1_MSTR bit
00230      * - ClockPolarity:      SPI_CR1_CPOL bit
00231      * - ClockPhase:         SPI_CR1_CPHA bit
00232      * - NSS management:     SPI_CR1_SSM bit
00233      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
00234      * - BitOrder:           SPI_CR1_LSBFIRST bit
00235      * - CRCCalculation:     SPI_CR1_CRCEN bit
00236      */
00237     MODIFY_REG(SPIx->CR1,
00238                SPI_CR1_CLEAR_MASK,
00239                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
00240                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
00241                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
00242                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
00243
00244     /*---------------------------- SPIx CR2 Configuration ------------------------
00245      * Configure SPIx CR2 with parameters:
00246      * - DataWidth:          DS[3:0] bits
00247      * - NSS management:     SSOE bit
00248      */
00249     MODIFY_REG(SPIx->CR2,
00250                SPI_CR2_DS | SPI_CR2_SSOE,
00251                SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
00252
00253     /*---------------------------- SPIx CRCPR Configuration ----------------------
00254      * Configure SPIx CRCPR with parameters:
00255      * - CRCPoly:            CRCPOLY[15:0] bits
00256      */
00257     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
00258     {
00259       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
00260       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
00261     }
00262     status = SUCCESS;
00263   }
00264
00265   return status;
00266 }
00267
00268 /**
00269   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
00270   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00271   * whose fields will be set to default values.
00272   * @retval None
00273   */
00274 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
00275 {
00276   /* Set SPI_InitStruct fields to default values */
00277   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
00278   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
00279   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
00280   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
00281   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
00282   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
00283   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
00284   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
00285   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
00286   SPI_InitStruct->CRCPoly           = 7U;
00287 }
00288
00289 /**
00290   * @}
00291   */
00292
00293 /**
00294   * @}
00295   */
00296
00297 /**
00298   * @}
00299   */
00300
00301 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
00302
00303 /**
00304   * @}
00305   */
00306
00307 #endif /* USE_FULL_LL_DRIVER */
00308
00309 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_spi.h Source File

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  • Inc
stm32l4xx_ll_spi.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_spi.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SPI LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_SPI_H
00040 #define __STM32L4xx_LL_SPI_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
00054
00055 /** @defgroup SPI_LL SPI
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062
00063 /* Exported types ------------------------------------------------------------*/
00064 #if defined(USE_FULL_LL_DRIVER)
00065 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
00066   * @{
00067   */
00068
00069 /**
00070   * @brief  SPI Init structures definition
00071   */
00072 typedef struct
00073 {
00074   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
00075                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
00076
00077                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
00078
00079   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
00080                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
00081
00082                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
00083
00084   uint32_t DataWidth;               /*!< Specifies the SPI data width.
00085                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
00086
00087                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
00088
00089   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
00090                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
00091
00092                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
00093
00094   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
00095                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
00096
00097                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
00098
00099   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
00100                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
00101
00102                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
00103
00104   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
00105                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
00106                                          @note The communication clock is derived from the master clock. The slave clock does not need to be set.
00107
00108                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
00109
00110   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
00111                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
00112
00113                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
00114
00115   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
00116                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
00117
00118                                          This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
00119
00120   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
00121                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
00122
00123                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
00124
00125 } LL_SPI_InitTypeDef;
00126
00127 /**
00128   * @}
00129   */
00130 #endif /* USE_FULL_LL_DRIVER */
00131
00132 /* Exported constants --------------------------------------------------------*/
00133 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
00134   * @{
00135   */
00136
00137 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
00138   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
00139   * @{
00140   */
00141 #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
00142 #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
00143 #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
00144 #define LL_SPI_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
00145 #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
00146 #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
00147 #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
00148 #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup SPI_LL_EC_IT IT Defines
00154   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
00155   * @{
00156   */
00157 #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
00158 #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
00159 #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup SPI_LL_EC_MODE Operation Mode
00165   * @{
00166   */
00167 #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
00168 #define LL_SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)         /*!< Slave configuration   */
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
00174   * @{
00175   */
00176 #define LL_SPI_PROTOCOL_MOTOROLA           ((uint32_t)0x00000000U)   /*!< Motorola mode. Used as default value */
00177 #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup SPI_LL_EC_PHASE Clock Phase
00183   * @{
00184   */
00185 #define LL_SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)   /*!< First clock transition is the first data capture edge  */
00186 #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
00192   * @{
00193   */
00194 #define LL_SPI_POLARITY_LOW                ((uint32_t)0x00000000U)   /*!< Clock to 0 when idle */
00195 #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
00201   * @{
00202   */
00203 #define LL_SPI_BAUDRATEPRESCALER_DIV2      ((uint32_t)0x00000000U)                        /*!< BaudRate control equal to fPCLK/2   */
00204 #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
00205 #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
00206 #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
00207 #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
00208 #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
00209 #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
00210 #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
00216   * @{
00217   */
00218 #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
00219 #define LL_SPI_MSB_FIRST                   ((uint32_t)0x00000000U)   /*!< Data is transmitted/received with the MSB first */
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
00225   * @{
00226   */
00227 #define LL_SPI_FULL_DUPLEX                 ((uint32_t)0x00000000U)              /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
00228 #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
00229 #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
00230 #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
00236   * @{
00237   */
00238 #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
00239 #define LL_SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)           /*!< NSS pin used in Input. Only used in Master mode                */
00240 #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
00246   * @{
00247   */
00248 #define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  4 bits */
00249 #define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                              /*!< Data length for SPI transfer:  5 bits */
00250 #define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer:  6 bits */
00251 #define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  7 bits */
00252 #define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer:  8 bits */
00253 #define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                              /*!< Data length for SPI transfer:  9 bits */
00254 #define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer: 10 bits */
00255 #define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer: 11 bits */
00256 #define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 12 bits */
00257 #define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                               /*!< Data length for SPI transfer: 13 bits */
00258 #define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 14 bits */
00259 #define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)                /*!< Data length for SPI transfer: 15 bits */
00260 #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
00261 /**
00262   * @}
00263   */
00264 #if defined(USE_FULL_LL_DRIVER)
00265
00266 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
00267   * @{
00268   */
00269 #define LL_SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000U)   /*!< CRC calculation disabled */
00270 #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
00271 /**
00272   * @}
00273   */
00274 #endif /* USE_FULL_LL_DRIVER */
00275
00276 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
00277   * @{
00278   */
00279 #define LL_SPI_CRC_8BIT                    ((uint32_t)0x00000000U)   /*!<  8-bit CRC length */
00280 #define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
00286   * @{
00287   */
00288 #define LL_SPI_RX_FIFO_TH_HALF             ((uint32_t)0x00000000U)   /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
00289 #define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit)  */
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
00295   * @{
00296   */
00297 #define LL_SPI_RX_FIFO_EMPTY               ((uint32_t)0x00000000U)           /*!< FIFO reception empty */
00298 #define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
00299 #define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
00300 #define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
00306   * @{
00307   */
00308 #define LL_SPI_TX_FIFO_EMPTY               ((uint32_t)0x00000000U)           /*!< FIFO transmission empty */
00309 #define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
00310 #define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
00311 #define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
00317   * @{
00318   */
00319 #define LL_SPI_DMA_PARITY_EVEN             ((uint32_t)0x00000000U)   /*!< Select DMA parity Even */
00320 #define LL_SPI_DMA_PARITY_ODD              ((uint32_t)0x00000001U)   /*!< Select DMA parity Odd  */
00321
00322 /**
00323   * @}
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 /* Exported macro ------------------------------------------------------------*/
00331 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
00332   * @{
00333   */
00334
00335 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
00336   * @{
00337   */
00338
00339 /**
00340   * @brief  Write a value in SPI register
00341   * @param  __INSTANCE__ SPI Instance
00342   * @param  __REG__ Register to be written
00343   * @param  __VALUE__ Value to be written in the register
00344   * @retval None
00345   */
00346 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00347
00348 /**
00349   * @brief  Read a value in SPI register
00350   * @param  __INSTANCE__ SPI Instance
00351   * @param  __REG__ Register to be read
00352   * @retval Register value
00353   */
00354 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00355 /**
00356   * @}
00357   */
00358
00359 /**
00360   * @}
00361   */
00362
00363 /* Exported functions --------------------------------------------------------*/
00364 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
00365   * @{
00366   */
00367
00368 /** @defgroup SPI_LL_EF_Configuration Configuration
00369   * @{
00370   */
00371
00372 /**
00373   * @brief  Enable SPI peripheral
00374   * @rmtoll CR1          SPE           LL_SPI_Enable
00375   * @param  SPIx SPI Instance
00376   * @retval None
00377   */
00378 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
00379 {
00380   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
00381 }
00382
00383 /**
00384   * @brief  Disable SPI peripheral
00385   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
00386   * @rmtoll CR1          SPE           LL_SPI_Disable
00387   * @param  SPIx SPI Instance
00388   * @retval None
00389   */
00390 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
00391 {
00392   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
00393 }
00394
00395 /**
00396   * @brief  Check if SPI peripheral is enabled
00397   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
00398   * @param  SPIx SPI Instance
00399   * @retval State of bit (1 or 0).
00400   */
00401 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
00402 {
00403   return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
00404 }
00405
00406 /**
00407   * @brief  Set SPI operation mode to Master or Slave
00408   * @note   This bit should not be changed when communication is ongoing.
00409   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
00410   *         CR1          SSI           LL_SPI_SetMode
00411   * @param  SPIx SPI Instance
00412   * @param  Mode This parameter can be one of the following values:
00413   *         @arg @ref LL_SPI_MODE_MASTER
00414   *         @arg @ref LL_SPI_MODE_SLAVE
00415   * @retval None
00416   */
00417 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
00418 {
00419   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
00420 }
00421
00422 /**
00423   * @brief  Get SPI operation mode (Master or Slave)
00424   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
00425   *         CR1          SSI           LL_SPI_GetMode
00426   * @param  SPIx SPI Instance
00427   * @retval Returned value can be one of the following values:
00428   *         @arg @ref LL_SPI_MODE_MASTER
00429   *         @arg @ref LL_SPI_MODE_SLAVE
00430   */
00431 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
00432 {
00433   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
00434 }
00435
00436 /**
00437   * @brief  Set serial protocol used
00438   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00439   * @rmtoll CR2          FRF           LL_SPI_SetStandard
00440   * @param  SPIx SPI Instance
00441   * @param  Standard This parameter can be one of the following values:
00442   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
00443   *         @arg @ref LL_SPI_PROTOCOL_TI
00444   * @retval None
00445   */
00446 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
00447 {
00448   MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
00449 }
00450
00451 /**
00452   * @brief  Get serial protocol used
00453   * @rmtoll CR2          FRF           LL_SPI_GetStandard
00454   * @param  SPIx SPI Instance
00455   * @retval Returned value can be one of the following values:
00456   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
00457   *         @arg @ref LL_SPI_PROTOCOL_TI
00458   */
00459 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
00460 {
00461   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
00462 }
00463
00464 /**
00465   * @brief  Set clock phase
00466   * @note   This bit should not be changed when communication is ongoing.
00467   *         This bit is not used in SPI TI mode.
00468   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
00469   * @param  SPIx SPI Instance
00470   * @param  ClockPhase This parameter can be one of the following values:
00471   *         @arg @ref LL_SPI_PHASE_1EDGE
00472   *         @arg @ref LL_SPI_PHASE_2EDGE
00473   * @retval None
00474   */
00475 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
00476 {
00477   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
00478 }
00479
00480 /**
00481   * @brief  Get clock phase
00482   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
00483   * @param  SPIx SPI Instance
00484   * @retval Returned value can be one of the following values:
00485   *         @arg @ref LL_SPI_PHASE_1EDGE
00486   *         @arg @ref LL_SPI_PHASE_2EDGE
00487   */
00488 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
00489 {
00490   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
00491 }
00492
00493 /**
00494   * @brief  Set clock polarity
00495   * @note   This bit should not be changed when communication is ongoing.
00496   *         This bit is not used in SPI TI mode.
00497   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
00498   * @param  SPIx SPI Instance
00499   * @param  ClockPolarity This parameter can be one of the following values:
00500   *         @arg @ref LL_SPI_POLARITY_LOW
00501   *         @arg @ref LL_SPI_POLARITY_HIGH
00502   * @retval None
00503   */
00504 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
00505 {
00506   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
00507 }
00508
00509 /**
00510   * @brief  Get clock polarity
00511   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
00512   * @param  SPIx SPI Instance
00513   * @retval Returned value can be one of the following values:
00514   *         @arg @ref LL_SPI_POLARITY_LOW
00515   *         @arg @ref LL_SPI_POLARITY_HIGH
00516   */
00517 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
00518 {
00519   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
00520 }
00521
00522 /**
00523   * @brief  Set baud rate prescaler
00524   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
00525   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
00526   * @param  SPIx SPI Instance
00527   * @param  BaudRate This parameter can be one of the following values:
00528   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00529   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00530   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00531   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00532   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00533   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00534   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00535   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00536   * @retval None
00537   */
00538 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
00539 {
00540   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
00541 }
00542
00543 /**
00544   * @brief  Get baud rate prescaler
00545   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
00546   * @param  SPIx SPI Instance
00547   * @retval Returned value can be one of the following values:
00548   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00549   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00550   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00551   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00552   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00553   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00554   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00555   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00556   */
00557 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
00558 {
00559   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
00560 }
00561
00562 /**
00563   * @brief  Set transfer bit order
00564   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00565   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
00566   * @param  SPIx SPI Instance
00567   * @param  BitOrder This parameter can be one of the following values:
00568   *         @arg @ref LL_SPI_LSB_FIRST
00569   *         @arg @ref LL_SPI_MSB_FIRST
00570   * @retval None
00571   */
00572 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
00573 {
00574   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
00575 }
00576
00577 /**
00578   * @brief  Get transfer bit order
00579   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
00580   * @param  SPIx SPI Instance
00581   * @retval Returned value can be one of the following values:
00582   *         @arg @ref LL_SPI_LSB_FIRST
00583   *         @arg @ref LL_SPI_MSB_FIRST
00584   */
00585 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
00586 {
00587   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
00588 }
00589
00590 /**
00591   * @brief  Set transfer direction mode
00592   * @note   For Half-Duplex mode, Rx Direction is set by default.
00593   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
00594   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
00595   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
00596   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
00597   * @param  SPIx SPI Instance
00598   * @param  TransferDirection This parameter can be one of the following values:
00599   *         @arg @ref LL_SPI_FULL_DUPLEX
00600   *         @arg @ref LL_SPI_SIMPLEX_RX
00601   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00602   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00603   * @retval None
00604   */
00605 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
00606 {
00607   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
00608 }
00609
00610 /**
00611   * @brief  Get transfer direction mode
00612   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
00613   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
00614   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
00615   * @param  SPIx SPI Instance
00616   * @retval Returned value can be one of the following values:
00617   *         @arg @ref LL_SPI_FULL_DUPLEX
00618   *         @arg @ref LL_SPI_SIMPLEX_RX
00619   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00620   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00621   */
00622 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
00623 {
00624   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
00625 }
00626
00627 /**
00628   * @brief  Set frame data width
00629   * @rmtoll CR2          DS            LL_SPI_SetDataWidth
00630   * @param  SPIx SPI Instance
00631   * @param  DataWidth This parameter can be one of the following values:
00632   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
00633   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
00634   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
00635   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
00636   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00637   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
00638   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
00639   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
00640   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
00641   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
00642   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
00643   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
00644   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00645   * @retval None
00646   */
00647 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
00648 {
00649   MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
00650 }
00651
00652 /**
00653   * @brief  Get frame data width
00654   * @rmtoll CR2          DS            LL_SPI_GetDataWidth
00655   * @param  SPIx SPI Instance
00656   * @retval Returned value can be one of the following values:
00657   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
00658   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
00659   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
00660   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
00661   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00662   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
00663   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
00664   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
00665   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
00666   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
00667   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
00668   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
00669   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00670   */
00671 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
00672 {
00673   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
00674 }
00675
00676 /**
00677   * @brief  Set threshold of RXFIFO that triggers an RXNE event
00678   * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
00679   * @param  SPIx SPI Instance
00680   * @param  Threshold This parameter can be one of the following values:
00681   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
00682   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
00683   * @retval None
00684   */
00685 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
00686 {
00687   MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
00688 }
00689
00690 /**
00691   * @brief  Get threshold of RXFIFO that triggers an RXNE event
00692   * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
00693   * @param  SPIx SPI Instance
00694   * @retval Returned value can be one of the following values:
00695   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
00696   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
00697   */
00698 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
00699 {
00700   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
00701 }
00702
00703 /**
00704   * @}
00705   */
00706
00707 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
00708   * @{
00709   */
00710
00711 /**
00712   * @brief  Enable CRC
00713   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00714   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
00715   * @param  SPIx SPI Instance
00716   * @retval None
00717   */
00718 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
00719 {
00720   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00721 }
00722
00723 /**
00724   * @brief  Disable CRC
00725   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00726   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
00727   * @param  SPIx SPI Instance
00728   * @retval None
00729   */
00730 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
00731 {
00732   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00733 }
00734
00735 /**
00736   * @brief  Check if CRC is enabled
00737   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00738   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
00739   * @param  SPIx SPI Instance
00740   * @retval State of bit (1 or 0).
00741   */
00742 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
00743 {
00744   return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
00745 }
00746
00747 /**
00748   * @brief  Set CRC Length
00749   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00750   * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
00751   * @param  SPIx SPI Instance
00752   * @param  CRCLength This parameter can be one of the following values:
00753   *         @arg @ref LL_SPI_CRC_8BIT
00754   *         @arg @ref LL_SPI_CRC_16BIT
00755   * @retval None
00756   */
00757 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
00758 {
00759   MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
00760 }
00761
00762 /**
00763   * @brief  Get CRC Length
00764   * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
00765   * @param  SPIx SPI Instance
00766   * @retval Returned value can be one of the following values:
00767   *         @arg @ref LL_SPI_CRC_8BIT
00768   *         @arg @ref LL_SPI_CRC_16BIT
00769   */
00770 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
00771 {
00772   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
00773 }
00774
00775 /**
00776   * @brief  Set CRCNext to transfer CRC on the line
00777   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
00778   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
00779   * @param  SPIx SPI Instance
00780   * @retval None
00781   */
00782 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
00783 {
00784   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
00785 }
00786
00787 /**
00788   * @brief  Set polynomial for CRC calculation
00789   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
00790   * @param  SPIx SPI Instance
00791   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00792   * @retval None
00793   */
00794 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
00795 {
00796   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
00797 }
00798
00799 /**
00800   * @brief  Get polynomial for CRC calculation
00801   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
00802   * @param  SPIx SPI Instance
00803   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00804   */
00805 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
00806 {
00807   return (uint32_t)(READ_REG(SPIx->CRCPR));
00808 }
00809
00810 /**
00811   * @brief  Get Rx CRC
00812   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
00813   * @param  SPIx SPI Instance
00814   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00815   */
00816 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
00817 {
00818   return (uint32_t)(READ_REG(SPIx->RXCRCR));
00819 }
00820
00821 /**
00822   * @brief  Get Tx CRC
00823   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
00824   * @param  SPIx SPI Instance
00825   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00826   */
00827 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
00828 {
00829   return (uint32_t)(READ_REG(SPIx->TXCRCR));
00830 }
00831
00832 /**
00833   * @}
00834   */
00835
00836 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
00837   * @{
00838   */
00839
00840 /**
00841   * @brief  Set NSS mode
00842   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
00843   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
00844   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
00845   * @param  SPIx SPI Instance
00846   * @param  NSS This parameter can be one of the following values:
00847   *         @arg @ref LL_SPI_NSS_SOFT
00848   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00849   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00850   * @retval None
00851   */
00852 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
00853 {
00854   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
00855   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
00856 }
00857
00858 /**
00859   * @brief  Get NSS mode
00860   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
00861   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
00862   * @param  SPIx SPI Instance
00863   * @retval Returned value can be one of the following values:
00864   *         @arg @ref LL_SPI_NSS_SOFT
00865   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00866   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00867   */
00868 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
00869 {
00870   register uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
00871   register uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
00872   return (Ssm | Ssoe);
00873 }
00874
00875 /**
00876   * @brief  Enable NSS pulse management
00877   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00878   * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
00879   * @param  SPIx SPI Instance
00880   * @retval None
00881   */
00882 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
00883 {
00884   SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
00885 }
00886
00887 /**
00888   * @brief  Disable NSS pulse management
00889   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00890   * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
00891   * @param  SPIx SPI Instance
00892   * @retval None
00893   */
00894 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
00895 {
00896   CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
00897 }
00898
00899 /**
00900   * @brief  Check if NSS pulse is enabled
00901   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00902   * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
00903   * @param  SPIx SPI Instance
00904   * @retval State of bit (1 or 0).
00905   */
00906 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
00907 {
00908   return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
00909 }
00910
00911 /**
00912   * @}
00913   */
00914
00915 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
00916   * @{
00917   */
00918
00919 /**
00920   * @brief  Check if Rx buffer is not empty
00921   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
00922   * @param  SPIx SPI Instance
00923   * @retval State of bit (1 or 0).
00924   */
00925 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
00926 {
00927   return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
00928 }
00929
00930 /**
00931   * @brief  Check if Tx buffer is empty
00932   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
00933   * @param  SPIx SPI Instance
00934   * @retval State of bit (1 or 0).
00935   */
00936 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
00937 {
00938   return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
00939 }
00940
00941 /**
00942   * @brief  Get CRC error flag
00943   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
00944   * @param  SPIx SPI Instance
00945   * @retval State of bit (1 or 0).
00946   */
00947 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
00948 {
00949   return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
00950 }
00951
00952 /**
00953   * @brief  Get mode fault error flag
00954   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
00955   * @param  SPIx SPI Instance
00956   * @retval State of bit (1 or 0).
00957   */
00958 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
00959 {
00960   return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
00961 }
00962
00963 /**
00964   * @brief  Get overrun error flag
00965   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
00966   * @param  SPIx SPI Instance
00967   * @retval State of bit (1 or 0).
00968   */
00969 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
00970 {
00971   return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
00972 }
00973
00974 /**
00975   * @brief  Get busy flag
00976   * @note   The BSY flag is cleared under any one of the following conditions:
00977   * -When the SPI is correctly disabled
00978   * -When a fault is detected in Master mode (MODF bit set to 1)
00979   * -In Master mode, when it finishes a data transmission and no new data is ready to be
00980   * sent
00981   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
00982   * each data transfer.
00983   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
00984   * @param  SPIx SPI Instance
00985   * @retval State of bit (1 or 0).
00986   */
00987 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
00988 {
00989   return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
00990 }
00991
00992 /**
00993   * @brief  Get frame format error flag
00994   * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
00995   * @param  SPIx SPI Instance
00996   * @retval State of bit (1 or 0).
00997   */
00998 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
00999 {
01000   return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
01001 }
01002
01003 /**
01004   * @brief  Get FIFO reception Level
01005   * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
01006   * @param  SPIx SPI Instance
01007   * @retval Returned value can be one of the following values:
01008   *         @arg @ref LL_SPI_RX_FIFO_EMPTY
01009   *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
01010   *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
01011   *         @arg @ref LL_SPI_RX_FIFO_FULL
01012   */
01013 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
01014 {
01015   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
01016 }
01017
01018 /**
01019   * @brief  Get FIFO Transmission Level
01020   * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
01021   * @param  SPIx SPI Instance
01022   * @retval Returned value can be one of the following values:
01023   *         @arg @ref LL_SPI_TX_FIFO_EMPTY
01024   *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
01025   *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
01026   *         @arg @ref LL_SPI_TX_FIFO_FULL
01027   */
01028 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
01029 {
01030   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
01031 }
01032
01033 /**
01034   * @brief  Clear CRC error flag
01035   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
01036   * @param  SPIx SPI Instance
01037   * @retval None
01038   */
01039 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
01040 {
01041   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
01042 }
01043
01044 /**
01045   * @brief  Clear mode fault error flag
01046   * @note   Clearing this flag is done by a read access to the SPIx_SR
01047   *         register followed by a write access to the SPIx_CR1 register
01048   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
01049   * @param  SPIx SPI Instance
01050   * @retval None
01051   */
01052 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
01053 {
01054   __IO uint32_t tmpreg;
01055   tmpreg = SPIx->SR;
01056   (void) tmpreg;
01057   tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
01058   (void) tmpreg;
01059 }
01060
01061 /**
01062   * @brief  Clear overrun error flag
01063   * @note   Clearing this flag is done by a read access to the SPIx_DR
01064   *         register followed by a read access to the SPIx_SR register
01065   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
01066   * @param  SPIx SPI Instance
01067   * @retval None
01068   */
01069 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
01070 {
01071   __IO uint32_t tmpreg;
01072   tmpreg = SPIx->DR;
01073   (void) tmpreg;
01074   tmpreg = SPIx->SR;
01075   (void) tmpreg;
01076 }
01077
01078 /**
01079   * @brief  Clear frame format error flag
01080   * @note   Clearing this flag is done by reading SPIx_SR register
01081   * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
01082   * @param  SPIx SPI Instance
01083   * @retval None
01084   */
01085 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
01086 {
01087   __IO uint32_t tmpreg;
01088   tmpreg = SPIx->SR;
01089   (void) tmpreg;
01090 }
01091
01092 /**
01093   * @}
01094   */
01095
01096 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
01097   * @{
01098   */
01099
01100 /**
01101   * @brief  Enable error interrupt
01102   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
01103   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
01104   * @param  SPIx SPI Instance
01105   * @retval None
01106   */
01107 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
01108 {
01109   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
01110 }
01111
01112 /**
01113   * @brief  Enable Rx buffer not empty interrupt
01114   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
01115   * @param  SPIx SPI Instance
01116   * @retval None
01117   */
01118 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
01119 {
01120   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
01121 }
01122
01123 /**
01124   * @brief  Enable Tx buffer empty interrupt
01125   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
01126   * @param  SPIx SPI Instance
01127   * @retval None
01128   */
01129 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
01130 {
01131   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
01132 }
01133
01134 /**
01135   * @brief  Disable error interrupt
01136   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
01137   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
01138   * @param  SPIx SPI Instance
01139   * @retval None
01140   */
01141 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
01142 {
01143   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
01144 }
01145
01146 /**
01147   * @brief  Disable Rx buffer not empty interrupt
01148   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
01149   * @param  SPIx SPI Instance
01150   * @retval None
01151   */
01152 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
01153 {
01154   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
01155 }
01156
01157 /**
01158   * @brief  Disable Tx buffer empty interrupt
01159   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
01160   * @param  SPIx SPI Instance
01161   * @retval None
01162   */
01163 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
01164 {
01165   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
01166 }
01167
01168 /**
01169   * @brief  Check if error interrupt is enabled
01170   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
01171   * @param  SPIx SPI Instance
01172   * @retval State of bit (1 or 0).
01173   */
01174 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
01175 {
01176   return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
01177 }
01178
01179 /**
01180   * @brief  Check if Rx buffer not empty interrupt is enabled
01181   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
01182   * @param  SPIx SPI Instance
01183   * @retval State of bit (1 or 0).
01184   */
01185 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
01186 {
01187   return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
01188 }
01189
01190 /**
01191   * @brief  Check if Tx buffer empty interrupt
01192   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
01193   * @param  SPIx SPI Instance
01194   * @retval State of bit (1 or 0).
01195   */
01196 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
01197 {
01198   return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
01199 }
01200
01201 /**
01202   * @}
01203   */
01204
01205 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
01206   * @{
01207   */
01208
01209 /**
01210   * @brief  Enable DMA Rx
01211   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
01212   * @param  SPIx SPI Instance
01213   * @retval None
01214   */
01215 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
01216 {
01217   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
01218 }
01219
01220 /**
01221   * @brief  Disable DMA Rx
01222   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
01223   * @param  SPIx SPI Instance
01224   * @retval None
01225   */
01226 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
01227 {
01228   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
01229 }
01230
01231 /**
01232   * @brief  Check if DMA Rx is enabled
01233   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
01234   * @param  SPIx SPI Instance
01235   * @retval State of bit (1 or 0).
01236   */
01237 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
01238 {
01239   return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
01240 }
01241
01242 /**
01243   * @brief  Enable DMA Tx
01244   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
01245   * @param  SPIx SPI Instance
01246   * @retval None
01247   */
01248 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
01249 {
01250   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
01251 }
01252
01253 /**
01254   * @brief  Disable DMA Tx
01255   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
01256   * @param  SPIx SPI Instance
01257   * @retval None
01258   */
01259 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
01260 {
01261   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
01262 }
01263
01264 /**
01265   * @brief  Check if DMA Tx is enabled
01266   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
01267   * @param  SPIx SPI Instance
01268   * @retval State of bit (1 or 0).
01269   */
01270 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
01271 {
01272   return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
01273 }
01274
01275 /**
01276   * @brief  Set parity of  Last DMA reception
01277   * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
01278   * @param  SPIx SPI Instance
01279   * @param  Parity This parameter can be one of the following values:
01280   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01281   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01282   * @retval None
01283   */
01284 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
01285 {
01286   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << POSITION_VAL(SPI_CR2_LDMARX)));
01287 }
01288
01289 /**
01290   * @brief  Get parity configuration for  Last DMA reception
01291   * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
01292   * @param  SPIx SPI Instance
01293   * @retval Returned value can be one of the following values:
01294   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01295   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01296   */
01297 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
01298 {
01299   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> POSITION_VAL(SPI_CR2_LDMARX));
01300 }
01301
01302 /**
01303   * @brief  Set parity of  Last DMA transmission
01304   * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
01305   * @param  SPIx SPI Instance
01306   * @param  Parity This parameter can be one of the following values:
01307   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01308   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01309   * @retval None
01310   */
01311 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
01312 {
01313   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << POSITION_VAL(SPI_CR2_LDMATX)));
01314 }
01315
01316 /**
01317   * @brief  Get parity configuration for Last DMA transmission
01318   * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
01319   * @param  SPIx SPI Instance
01320   * @retval Returned value can be one of the following values:
01321   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01322   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01323   */
01324 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
01325 {
01326   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> POSITION_VAL(SPI_CR2_LDMATX));
01327 }
01328
01329 /**
01330   * @brief  Get the data register address used for DMA transfer
01331   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
01332   * @param  SPIx SPI Instance
01333   * @retval Address of data register
01334   */
01335 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
01336 {
01337   return (uint32_t) & (SPIx->DR);
01338 }
01339
01340 /**
01341   * @}
01342   */
01343
01344 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
01345   * @{
01346   */
01347
01348 /**
01349   * @brief  Read 8-Bits in the data register
01350   * @rmtoll DR           DR            LL_SPI_ReceiveData8
01351   * @param  SPIx SPI Instance
01352   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
01353   */
01354 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
01355 {
01356   return (uint8_t)(READ_REG(SPIx->DR));
01357 }
01358
01359 /**
01360   * @brief  Read 16-Bits in the data register
01361   * @rmtoll DR           DR            LL_SPI_ReceiveData16
01362   * @param  SPIx SPI Instance
01363   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01364   */
01365 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
01366 {
01367   return (uint16_t)(READ_REG(SPIx->DR));
01368 }
01369
01370 /**
01371   * @brief  Write 8-Bits in the data register
01372   * @rmtoll DR           DR            LL_SPI_TransmitData8
01373   * @param  SPIx SPI Instance
01374   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
01375   * @retval None
01376   */
01377 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
01378 {
01379   *((__IO uint8_t *)&SPIx->DR) = TxData;
01380 }
01381
01382 /**
01383   * @brief  Write 16-Bits in the data register
01384   * @rmtoll DR           DR            LL_SPI_TransmitData16
01385   * @param  SPIx SPI Instance
01386   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01387   * @retval None
01388   */
01389 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
01390 {
01391   *((__IO uint16_t *)&SPIx->DR) = TxData;
01392 }
01393
01394 /**
01395   * @}
01396   */
01397 #if defined(USE_FULL_LL_DRIVER)
01398 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
01399   * @{
01400   */
01401
01402 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
01403 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
01404 void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
01405
01406 /**
01407   * @}
01408   */
01409 #endif /* USE_FULL_LL_DRIVER */
01410 /**
01411   * @}
01412   */
01413
01414 /**
01415   * @}
01416   */
01417
01418 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
01419
01420 /**
01421   * @}
01422   */
01423
01424 #ifdef __cplusplus
01425 }
01426 #endif
01427
01428 #endif /* __STM32L4xx_LL_SPI_H */
01429
01430 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_swpmi.c Source File

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stm32l4xx_ll_swpmi.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_swpmi.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SWPMI LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_swpmi.h"
00041 #include "stm32l4xx_ll_bus.h"
00042 #ifdef  USE_FULL_ASSERT
00043 #include "stm32_assert.h"
00044 #else
00045 #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32L4xx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined (SWPMI1)
00053
00054 /** @addtogroup SWPMI_LL
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062 /** @addtogroup SWPMI_LL_Private_Macros
00063   * @{
00064   */
00065
00066 #define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
00067
00068 #define IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \
00069                                           || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI))
00070
00071 #define IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_SINGLE) \
00072                                           || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI))
00073
00074 #define IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__) (((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_C) \
00075                                            || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B))
00076
00077 /**
00078   * @}
00079   */
00080
00081 /* Private function prototypes -----------------------------------------------*/
00082
00083 /* Exported functions --------------------------------------------------------*/
00084 /** @addtogroup SWPMI_LL_Exported_Functions
00085   * @{
00086   */
00087
00088 /** @addtogroup SWPMI_LL_EF_Init
00089   * @{
00090   */
00091
00092 /**
00093   * @brief  De-initialize the SWPMI peripheral registers to their default reset values.
00094   * @param  SWPMIx SWPMI Instance
00095   * @retval An ErrorStatus enumeration value
00096   *          - SUCCESS: SWPMI registers are de-initialized
00097   *          - ERROR: Not applicable
00098   */
00099 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx)
00100 {
00101   /* Check the parameter */
00102   assert_param(IS_SWPMI_INSTANCE(SWPMIx));
00103
00104   LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SWPMI1);
00105   LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SWPMI1);
00106
00107   return SUCCESS;
00108 }
00109
00110 /**
00111   * @brief  Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
00112   * @note   As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated (SWPMI_CR_SWPACT bit = 0),
00113   *         SWPMI IP should be in deactivated state prior calling this function. Otherwise, ERROR result will be returned.
00114   * @param  SWPMIx           SWPMI Instance
00115   * @param  SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
00116   *                          the configuration information for the SWPMI peripheral.
00117   * @retval An ErrorStatus enumeration value
00118   *          - SUCCESS: SWPMI registers are initialized
00119   *          - ERROR: SWPMI registers are not initialized
00120   */
00121 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
00122 {
00123   ErrorStatus status = SUCCESS;
00124
00125   /* Check the parameters */
00126   assert_param(IS_SWPMI_INSTANCE(SWPMIx));
00127   assert_param(IS_LL_SWPMI_BITRATE_VALUE(SWPMI_InitStruct->BitRatePrescaler));
00128   assert_param(IS_LL_SWPMI_SW_BUFFER_TX(SWPMI_InitStruct->TxBufferingMode));
00129   assert_param(IS_LL_SWPMI_SW_BUFFER_RX(SWPMI_InitStruct->RxBufferingMode));
00130   assert_param(IS_LL_SWPMI_VOLTAGE_CLASS(SWPMI_InitStruct->VoltageClass));
00131
00132   /* SWPMI needs to be in deactivated state, in order to be able to configure some bits */
00133   if (LL_SWPMI_IsActivated(SWPMIx) == 0)
00134   {
00135     /* Configure the BRR register (Bitrate) */
00136     LL_SWPMI_SetBitRatePrescaler(SWPMIx, SWPMI_InitStruct->BitRatePrescaler);
00137
00138     /* Configure the voltage class */
00139     LL_SWPMI_SetVoltageClass(SWPMIx, SWPMI_InitStruct->VoltageClass);
00140
00141     /* Set the new configuration of the SWPMI peripheral */
00142     MODIFY_REG(SWPMIx->CR,
00143               (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE),
00144               (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode));
00145   }
00146   /* Else (SWPMI not in deactivated state => return ERROR) */
00147   else
00148   {
00149     status = ERROR;
00150   }
00151
00152   return status;
00153 }
00154
00155 /**
00156   * @brief  Set each @ref LL_SWPMI_InitTypeDef field to default value.
00157   * @param  SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
00158   *                          the configuration information for the SWPMI peripheral.
00159   * @retval None
00160   */
00161 void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
00162 {
00163   /* Set SWPMI_InitStruct fields to default values */
00164   SWPMI_InitStruct->VoltageClass     = LL_SWPMI_VOLTAGE_CLASS_C;
00165   SWPMI_InitStruct->BitRatePrescaler = (uint32_t)0x00000001;
00166   SWPMI_InitStruct->TxBufferingMode  = LL_SWPMI_SW_BUFFER_TX_SINGLE;
00167   SWPMI_InitStruct->RxBufferingMode  = LL_SWPMI_SW_BUFFER_RX_SINGLE;
00168 }
00169
00170 /**
00171   * @}
00172   */
00173
00174 /**
00175   * @}
00176   */
00177
00178 /**
00179   * @}
00180   */
00181
00182 #endif /* defined (SWPMI1) */
00183
00184 /**
00185   * @}
00186   */
00187
00188 #endif /* USE_FULL_LL_DRIVER */
00189
00190 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_swpmi.h Source File

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stm32l4xx_ll_swpmi.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_swpmi.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SWPMI LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_SWPMI_H
00040 #define __STM32L4xx_LL_SWPMI_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (SWPMI1)
00054
00055 /** @defgroup SWPMI_LL SWPMI
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 #if defined(USE_FULL_LL_DRIVER)
00064 /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros
00065   * @{
00066   */
00067 /**
00068   * @}
00069   */
00070 #endif /*USE_FULL_LL_DRIVER*/
00071
00072 /* Exported types ------------------------------------------------------------*/
00073 #if defined(USE_FULL_LL_DRIVER)
00074 /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure
00075   * @{
00076   */
00077
00078 /**
00079   * @brief  SWPMI Init structures definition
00080   */
00081 typedef struct
00082 {
00083   uint32_t VoltageClass;           /*!< Specifies the SWP Voltage Class.
00084                                         This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS
00085
00086                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */
00087
00088   uint32_t BitRatePrescaler;       /*!< Specifies the SWPMI bitrate prescaler.
00089                                         This parameter must be a number between Min_Data=0 and Max_Data=63.
00090
00091                                         The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER
00092
00093                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */
00094
00095   uint32_t TxBufferingMode;        /*!< Specifies the transmission buffering mode.
00096                                         This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX
00097
00098                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */
00099
00100   uint32_t RxBufferingMode;        /*!< Specifies the reception buffering mode.
00101                                         This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX
00102
00103                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */
00104 } LL_SWPMI_InitTypeDef;
00105
00106 /**
00107   * @}
00108   */
00109 #endif /* USE_FULL_LL_DRIVER */
00110
00111 /* Exported constants --------------------------------------------------------*/
00112 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants
00113   * @{
00114   */
00115
00116 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines
00117   * @brief    Flags defines which can be used with LL_SWPMI_WriteReg function
00118   * @{
00119   */
00120 #define LL_SWPMI_ICR_CRXBFF                SWPMI_ICR_CRXBFF  /*!< Clear receive buffer full flag     */
00121 #define LL_SWPMI_ICR_CTXBEF                SWPMI_ICR_CTXBEF  /*!< Clear transmit buffer empty flag   */
00122 #define LL_SWPMI_ICR_CRXBERF               SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag       */
00123 #define LL_SWPMI_ICR_CRXOVRF               SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag   */
00124 #define LL_SWPMI_ICR_CTXUNRF               SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */
00125 #define LL_SWPMI_ICR_CTCF                  SWPMI_ICR_CTCF    /*!< Clear transfer complete flag       */
00126 #define LL_SWPMI_ICR_CSRF                  SWPMI_ICR_CSRF    /*!< Clear slave resume flag            */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines
00132   * @brief    Flags defines which can be used with LL_SWPMI_ReadReg function
00133   * @{
00134   */
00135 #define LL_SWPMI_ISR_RXBFF                 SWPMI_ISR_RXBFF   /*!< Receive buffer full flag           */
00136 #define LL_SWPMI_ISR_TXBEF                 SWPMI_ISR_TXBEF   /*!< Transmit buffer empty flag         */
00137 #define LL_SWPMI_ISR_RXBERF                SWPMI_ISR_RXBERF  /*!< Receive CRC error flag             */
00138 #define LL_SWPMI_ISR_RXOVRF                SWPMI_ISR_RXOVRF  /*!< Receive overrun error flag         */
00139 #define LL_SWPMI_ISR_TXUNRF                SWPMI_ISR_TXUNRF  /*!< Transmit underrun error flag       */
00140 #define LL_SWPMI_ISR_RXNE                  SWPMI_ISR_RXNE    /*!< Receive data register not empty    */
00141 #define LL_SWPMI_ISR_TXE                   SWPMI_ISR_TXE     /*!< Transmit data register empty       */
00142 #define LL_SWPMI_ISR_TCF                   SWPMI_ISR_TCF     /*!< Transfer complete flag             */
00143 #define LL_SWPMI_ISR_SRF                   SWPMI_ISR_SRF     /*!< Slave resume flag                  */
00144 #define LL_SWPMI_ISR_SUSP                  SWPMI_ISR_SUSP    /*!< SUSPEND flag                       */
00145 #define LL_SWPMI_ISR_DEACTF                SWPMI_ISR_DEACTF  /*!< DEACTIVATED flag                   */
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup SWPMI_LL_EC_IT IT Defines
00151   * @brief    IT defines which can be used with LL_SWPMI_ReadReg and  LL_SWPMI_WriteReg functions
00152   * @{
00153   */
00154 #define LL_SWPMI_IER_SRIE                  SWPMI_IER_SRIE    /*!< Slave resume interrupt enable            */
00155 #define LL_SWPMI_IER_TCIE                  SWPMI_IER_TCIE    /*!< Transmit complete interrupt enable       */
00156 #define LL_SWPMI_IER_TIE                   SWPMI_IER_TIE     /*!< Transmit interrupt enable                */
00157 #define LL_SWPMI_IER_RIE                   SWPMI_IER_RIE     /*!< Receive interrupt enable                 */
00158 #define LL_SWPMI_IER_TXUNRIE               SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */
00159 #define LL_SWPMI_IER_RXOVRIE               SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable   */
00160 #define LL_SWPMI_IER_RXBERIE               SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable       */
00161 #define LL_SWPMI_IER_TXBEIE                SWPMI_IER_TXBEIE  /*!< Transmit buffer empty interrupt enable   */
00162 #define LL_SWPMI_IER_RXBFIE                SWPMI_IER_RXBFIE  /*!< Receive buffer full interrupt enable     */
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX
00168   * @{
00169   */
00170 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for reception */
00171 #define LL_SWPMI_SW_BUFFER_RX_MULTI  SWPMI_CR_RXMODE         /*!< Multi software buffermode for reception   */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX
00177   * @{
00178   */
00179 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for transmission */
00180 #define LL_SWPMI_SW_BUFFER_TX_MULTI  SWPMI_CR_TXMODE         /*!< Multi software buffermode for transmission   */
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS
00186   * @{
00187   */
00188 #define LL_SWPMI_VOLTAGE_CLASS_C     ((uint32_t)0x00000000)  /*!< SWPMI_IO uses directly VDD voltage to operate in class C          */
00189 #define LL_SWPMI_VOLTAGE_CLASS_B     SWPMI_OR_CLASS          /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data
00195   * @{
00196   */
00197 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT     (uint32_t)0       /*!< Get address of data register used for transmission */
00198 #define LL_SWPMI_DMA_REG_DATA_RECEIVE      (uint32_t)1       /*!< Get address of data register used for reception    */
00199 /**
00200   * @}
00201   */
00202
00203 /**
00204   * @}
00205   */
00206
00207 /* Exported macro ------------------------------------------------------------*/
00208 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros
00209   * @{
00210   */
00211
00212 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros
00213   * @{
00214   */
00215
00216 /**
00217   * @brief  Write a value in SWPMI register
00218   * @param  __INSTANCE__ SWPMI Instance
00219   * @param  __REG__ Register to be written
00220   * @param  __VALUE__ Value to be written in the register
00221   * @retval None
00222   */
00223 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00224
00225 /**
00226   * @brief  Read a value in SWPMI register
00227   * @param  __INSTANCE__ SWPMI Instance
00228   * @param  __REG__ Register to be read
00229   * @retval Register value
00230   */
00231 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros
00237   * @{
00238   */
00239
00240 /**
00241   * @brief  Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function)
00242   * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
00243   * @param  __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
00244   * @param  __FSWPCLK__ PCLK or HSI frequency (in Hz)
00245   * @retval Bitrate prescaler (BRR register)
00246   */
00247 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__)   ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
00248
00249 /**
00250   * @}
00251   */
00252
00253 /**
00254   * @}
00255   */
00256
00257 /* Exported functions --------------------------------------------------------*/
00258 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions
00259   * @{
00260   */
00261
00262 /** @defgroup SWPMI_LL_EF_Configuration Configuration
00263   * @{
00264   */
00265
00266 /**
00267   * @brief  Set Reception buffering mode
00268   * @note   If Multi software buffer mode is chosen, RXDMA bits must also be set.
00269   * @rmtoll CR           RXMODE        LL_SWPMI_SetReceptionMode
00270   * @param  SWPMIx SWPMI Instance
00271   * @param  RxBufferingMode This parameter can be one of the following values:
00272   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
00273   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
00274   * @retval None
00275   */
00276 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
00277 {
00278   MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);
00279 }
00280
00281 /**
00282   * @brief  Get Reception buffering mode
00283   * @rmtoll CR           RXMODE        LL_SWPMI_GetReceptionMode
00284   * @param  SWPMIx SWPMI Instance
00285   * @retval Returned value can be one of the following values:
00286   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
00287   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
00288   */
00289 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)
00290 {
00291   return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
00292 }
00293
00294 /**
00295   * @brief  Set Transmission buffering mode
00296   * @note   If Multi software buffer mode is chosen, TXDMA bits must also be set.
00297   * @rmtoll CR           TXMODE        LL_SWPMI_SetTransmissionMode
00298   * @param  SWPMIx SWPMI Instance
00299   * @param  TxBufferingMode This parameter can be one of the following values:
00300   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
00301   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
00302   * @retval None
00303   */
00304 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
00305 {
00306   MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);
00307 }
00308
00309 /**
00310   * @brief  Get Transmission buffering mode
00311   * @rmtoll CR           TXMODE        LL_SWPMI_GetTransmissionMode
00312   * @param  SWPMIx SWPMI Instance
00313   * @retval Returned value can be one of the following values:
00314   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
00315   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
00316   */
00317 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)
00318 {
00319   return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
00320 }
00321
00322 /**
00323   * @brief  Enable loopback mode
00324   * @rmtoll CR           LPBK          LL_SWPMI_EnableLoopback
00325   * @param  SWPMIx SWPMI Instance
00326   * @retval None
00327   */
00328 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
00329 {
00330   SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
00331 }
00332
00333 /**
00334   * @brief  Disable loopback mode
00335   * @rmtoll CR           LPBK          LL_SWPMI_DisableLoopback
00336   * @param  SWPMIx SWPMI Instance
00337   * @retval None
00338   */
00339 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
00340 {
00341   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
00342 }
00343
00344 /**
00345   * @brief  Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
00346   * @note   SWP bus stays in the ACTIVATED state as long as there is a communication
00347   *         with the slave, either in transmission or in reception. The SWP bus switches back
00348   *         to the SUSPENDED state as soon as there is no more transmission or reception
00349   *         activity, after 7 idle bits.
00350   * @rmtoll CR           SWPACT        LL_SWPMI_Activate
00351   * @param  SWPMIx SWPMI Instance
00352   * @retval None
00353   */
00354 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
00355 {
00356   /* In order to activate SWP again, the software must clear DEACT bit*/
00357   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
00358
00359   /* Set SWACT bit */
00360   SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
00361 }
00362
00363 /**
00364   * @brief  Check if Single wire protocol bus is in ACTIVATED state.
00365   * @rmtoll CR           SWPACT        LL_SWPMI_Activate
00366   * @param  SWPMIx SWPMI Instance
00367   * @retval State of bit (1 or 0).
00368   */
00369 __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx)
00370 {
00371   return (READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT));
00372 }
00373
00374 /**
00375   * @brief  Deactivate immediately Single wire protocol bus (immediate transition to
00376   *         DEACTIVATED state)
00377   * @rmtoll CR           SWPACT        LL_SWPMI_Deactivate
00378   * @param  SWPMIx SWPMI Instance
00379   * @retval None
00380   */
00381 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
00382 {
00383   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
00384 }
00385
00386 /**
00387   * @brief  Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED
00388   *         state if no resume from slave)
00389   * @rmtoll CR           DEACT         LL_SWPMI_RequestDeactivation
00390   * @param  SWPMIx SWPMI Instance
00391   * @retval None
00392   */
00393 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
00394 {
00395   SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
00396 }
00397
00398 /**
00399   * @brief  Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
00400   * @rmtoll BRR          BR            LL_SWPMI_SetBitRatePrescaler
00401   * @param  SWPMIx SWPMI Instance
00402   * @param  BitRatePrescaler A number between Min_Data=0 and Max_Data=63
00403   * @retval None
00404   */
00405 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
00406 {
00407   WRITE_REG(SWPMIx->BRR, BitRatePrescaler);
00408 }
00409
00410 /**
00411   * @brief  Get Bitrate prescaler
00412   * @rmtoll BRR          BR            LL_SWPMI_GetBitRatePrescaler
00413   * @param  SWPMIx SWPMI Instance
00414   * @retval A number between Min_Data=0 and Max_Data=63
00415   */
00416 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)
00417 {
00418   return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
00419 }
00420
00421 /**
00422   * @brief  Set SWP Voltage Class
00423   * @rmtoll OR           CLASS         LL_SWPMI_SetVoltageClass
00424   * @param  SWPMIx SWPMI Instance
00425   * @param  VoltageClass This parameter can be one of the following values:
00426   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
00427   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
00428   * @retval None
00429   */
00430 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
00431 {
00432   MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);
00433 }
00434
00435 /**
00436   * @brief  Get SWP Voltage Class
00437   * @rmtoll OR           CLASS         LL_SWPMI_GetVoltageClass
00438   * @param  SWPMIx SWPMI Instance
00439   * @retval Returned value can be one of the following values:
00440   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
00441   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
00442   */
00443 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)
00444 {
00445   return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
00446 }
00447
00448 /**
00449   * @}
00450   */
00451
00452 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management
00453   * @{
00454   */
00455
00456 /**
00457   * @brief  Check if the last word of the frame under reception has arrived in SWPMI_RDR.
00458   * @rmtoll ISR          RXBFF         LL_SWPMI_IsActiveFlag_RXBF
00459   * @param  SWPMIx SWPMI Instance
00460   * @retval State of bit (1 or 0).
00461   */
00462 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)
00463 {
00464   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF));
00465 }
00466
00467 /**
00468   * @brief  Check if Frame transmission buffer has been emptied
00469   * @rmtoll ISR          TXBEF         LL_SWPMI_IsActiveFlag_TXBE
00470   * @param  SWPMIx SWPMI Instance
00471   * @retval State of bit (1 or 0).
00472   */
00473 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)
00474 {
00475   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF));
00476 }
00477
00478 /**
00479   * @brief  Check if CRC error in reception has been detected
00480   * @rmtoll ISR          RXBERF        LL_SWPMI_IsActiveFlag_RXBER
00481   * @param  SWPMIx SWPMI Instance
00482   * @retval State of bit (1 or 0).
00483   */
00484 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)
00485 {
00486   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF));
00487 }
00488
00489 /**
00490   * @brief  Check if Overrun in reception has been detected
00491   * @rmtoll ISR          RXOVRF        LL_SWPMI_IsActiveFlag_RXOVR
00492   * @param  SWPMIx SWPMI Instance
00493   * @retval State of bit (1 or 0).
00494   */
00495 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
00496 {
00497   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF));
00498 }
00499
00500 /**
00501   * @brief  Check if underrun error in transmission has been detected
00502   * @rmtoll ISR          TXUNRF        LL_SWPMI_IsActiveFlag_TXUNR
00503   * @param  SWPMIx SWPMI Instance
00504   * @retval State of bit (1 or 0).
00505   */
00506 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
00507 {
00508   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF));
00509 }
00510
00511 /**
00512   * @brief  Check if Receive data register not empty (it means that Received data is ready
00513   *         to be read in the SWPMI_RDR register)
00514   * @rmtoll ISR          RXNE          LL_SWPMI_IsActiveFlag_RXNE
00515   * @param  SWPMIx SWPMI Instance
00516   * @retval State of bit (1 or 0).
00517   */
00518 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)
00519 {
00520   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE));
00521 }
00522
00523 /**
00524   * @brief  Check if Transmit data register is empty (it means that Data written in transmit
00525   *         data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
00526   * @rmtoll ISR          TXE           LL_SWPMI_IsActiveFlag_TXE
00527   * @param  SWPMIx SWPMI Instance
00528   * @retval State of bit (1 or 0).
00529   */
00530 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)
00531 {
00532   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE));
00533 }
00534
00535 /**
00536   * @brief  Check if Both transmission and reception are completed and SWP is switched to
00537   *         the SUSPENDED state
00538   * @rmtoll ISR          TCF           LL_SWPMI_IsActiveFlag_TC
00539   * @param  SWPMIx SWPMI Instance
00540   * @retval State of bit (1 or 0).
00541   */
00542 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)
00543 {
00544   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF));
00545 }
00546
00547 /**
00548   * @brief  Check if a Resume by slave state has been detected during the SWP bus SUSPENDED
00549   *         state
00550   * @rmtoll ISR          SRF           LL_SWPMI_IsActiveFlag_SR
00551   * @param  SWPMIx SWPMI Instance
00552   * @retval State of bit (1 or 0).
00553   */
00554 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)
00555 {
00556   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF));
00557 }
00558
00559 /**
00560   * @brief  Check if SWP bus is in SUSPENDED or DEACTIVATED state
00561   * @rmtoll ISR          SUSP          LL_SWPMI_IsActiveFlag_SUSP
00562   * @param  SWPMIx SWPMI Instance
00563   * @retval State of bit (1 or 0).
00564   */
00565 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)
00566 {
00567   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP));
00568 }
00569
00570 /**
00571   * @brief  Check if SWP bus is in DEACTIVATED state
00572   * @rmtoll ISR          DEACTF        LL_SWPMI_IsActiveFlag_DEACT
00573   * @param  SWPMIx SWPMI Instance
00574   * @retval State of bit (1 or 0).
00575   */
00576 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)
00577 {
00578   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF));
00579 }
00580
00581 /**
00582   * @brief  Clear receive buffer full flag
00583   * @rmtoll ICR          CRXBFF        LL_SWPMI_ClearFlag_RXBF
00584   * @param  SWPMIx SWPMI Instance
00585   * @retval None
00586   */
00587 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
00588 {
00589   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
00590 }
00591
00592 /**
00593   * @brief  Clear transmit buffer empty flag
00594   * @rmtoll ICR          CTXBEF        LL_SWPMI_ClearFlag_TXBE
00595   * @param  SWPMIx SWPMI Instance
00596   * @retval None
00597   */
00598 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
00599 {
00600   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
00601 }
00602
00603 /**
00604   * @brief  Clear receive CRC error flag
00605   * @rmtoll ICR          CRXBERF       LL_SWPMI_ClearFlag_RXBER
00606   * @param  SWPMIx SWPMI Instance
00607   * @retval None
00608   */
00609 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
00610 {
00611   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
00612 }
00613
00614 /**
00615   * @brief  Clear receive overrun error flag
00616   * @rmtoll ICR          CRXOVRF       LL_SWPMI_ClearFlag_RXOVR
00617   * @param  SWPMIx SWPMI Instance
00618   * @retval None
00619   */
00620 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
00621 {
00622   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
00623 }
00624
00625 /**
00626   * @brief  Clear transmit underrun error flag
00627   * @rmtoll ICR          CTXUNRF       LL_SWPMI_ClearFlag_TXUNR
00628   * @param  SWPMIx SWPMI Instance
00629   * @retval None
00630   */
00631 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
00632 {
00633   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
00634 }
00635
00636 /**
00637   * @brief  Clear transfer complete flag
00638   * @rmtoll ICR          CTCF          LL_SWPMI_ClearFlag_TC
00639   * @param  SWPMIx SWPMI Instance
00640   * @retval None
00641   */
00642 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
00643 {
00644   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
00645 }
00646
00647 /**
00648   * @brief  Clear slave resume flag
00649   * @rmtoll ICR          CSRF          LL_SWPMI_ClearFlag_SR
00650   * @param  SWPMIx SWPMI Instance
00651   * @retval None
00652   */
00653 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
00654 {
00655   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
00656 }
00657
00658 /**
00659   * @}
00660   */
00661
00662 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management
00663   * @{
00664   */
00665
00666 /**
00667   * @brief  Enable Slave resume interrupt
00668   * @rmtoll IER          SRIE          LL_SWPMI_EnableIT_SR
00669   * @param  SWPMIx SWPMI Instance
00670   * @retval None
00671   */
00672 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
00673 {
00674   SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
00675 }
00676
00677 /**
00678   * @brief  Enable Transmit complete interrupt
00679   * @rmtoll IER          TCIE          LL_SWPMI_EnableIT_TC
00680   * @param  SWPMIx SWPMI Instance
00681   * @retval None
00682   */
00683 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
00684 {
00685   SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
00686 }
00687
00688 /**
00689   * @brief  Enable Transmit interrupt
00690   * @rmtoll IER          TIE           LL_SWPMI_EnableIT_TX
00691   * @param  SWPMIx SWPMI Instance
00692   * @retval None
00693   */
00694 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
00695 {
00696   SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
00697 }
00698
00699 /**
00700   * @brief  Enable Receive interrupt
00701   * @rmtoll IER          RIE           LL_SWPMI_EnableIT_RX
00702   * @param  SWPMIx SWPMI Instance
00703   * @retval None
00704   */
00705 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
00706 {
00707   SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
00708 }
00709
00710 /**
00711   * @brief  Enable Transmit underrun error interrupt
00712   * @rmtoll IER          TXUNRIE       LL_SWPMI_EnableIT_TXUNR
00713   * @param  SWPMIx SWPMI Instance
00714   * @retval None
00715   */
00716 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00717 {
00718   SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
00719 }
00720
00721 /**
00722   * @brief  Enable Receive overrun error interrupt
00723   * @rmtoll IER          RXOVRIE       LL_SWPMI_EnableIT_RXOVR
00724   * @param  SWPMIx SWPMI Instance
00725   * @retval None
00726   */
00727 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00728 {
00729   SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
00730 }
00731
00732 /**
00733   * @brief  Enable Receive CRC error interrupt
00734   * @rmtoll IER          RXBERIE       LL_SWPMI_EnableIT_RXBER
00735   * @param  SWPMIx SWPMI Instance
00736   * @retval None
00737   */
00738 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
00739 {
00740   SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
00741 }
00742
00743 /**
00744   * @brief  Enable Transmit buffer empty interrupt
00745   * @rmtoll IER          TXBEIE        LL_SWPMI_EnableIT_TXBE
00746   * @param  SWPMIx SWPMI Instance
00747   * @retval None
00748   */
00749 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
00750 {
00751   SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
00752 }
00753
00754 /**
00755   * @brief  Enable Receive buffer full interrupt
00756   * @rmtoll IER          RXBFIE        LL_SWPMI_EnableIT_RXBF
00757   * @param  SWPMIx SWPMI Instance
00758   * @retval None
00759   */
00760 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
00761 {
00762   SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
00763 }
00764
00765 /**
00766   * @brief  Disable Slave resume interrupt
00767   * @rmtoll IER          SRIE          LL_SWPMI_DisableIT_SR
00768   * @param  SWPMIx SWPMI Instance
00769   * @retval None
00770   */
00771 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
00772 {
00773   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
00774 }
00775
00776 /**
00777   * @brief  Disable Transmit complete interrupt
00778   * @rmtoll IER          TCIE          LL_SWPMI_DisableIT_TC
00779   * @param  SWPMIx SWPMI Instance
00780   * @retval None
00781   */
00782 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
00783 {
00784   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
00785 }
00786
00787 /**
00788   * @brief  Disable Transmit interrupt
00789   * @rmtoll IER          TIE           LL_SWPMI_DisableIT_TX
00790   * @param  SWPMIx SWPMI Instance
00791   * @retval None
00792   */
00793 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
00794 {
00795   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
00796 }
00797
00798 /**
00799   * @brief  Disable Receive interrupt
00800   * @rmtoll IER          RIE           LL_SWPMI_DisableIT_RX
00801   * @param  SWPMIx SWPMI Instance
00802   * @retval None
00803   */
00804 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
00805 {
00806   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
00807 }
00808
00809 /**
00810   * @brief  Disable Transmit underrun error interrupt
00811   * @rmtoll IER          TXUNRIE       LL_SWPMI_DisableIT_TXUNR
00812   * @param  SWPMIx SWPMI Instance
00813   * @retval None
00814   */
00815 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00816 {
00817   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
00818 }
00819
00820 /**
00821   * @brief  Disable Receive overrun error interrupt
00822   * @rmtoll IER          RXOVRIE       LL_SWPMI_DisableIT_RXOVR
00823   * @param  SWPMIx SWPMI Instance
00824   * @retval None
00825   */
00826 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00827 {
00828   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
00829 }
00830
00831 /**
00832   * @brief  Disable Receive CRC error interrupt
00833   * @rmtoll IER          RXBERIE       LL_SWPMI_DisableIT_RXBER
00834   * @param  SWPMIx SWPMI Instance
00835   * @retval None
00836   */
00837 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
00838 {
00839   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
00840 }
00841
00842 /**
00843   * @brief  Disable Transmit buffer empty interrupt
00844   * @rmtoll IER          TXBEIE        LL_SWPMI_DisableIT_TXBE
00845   * @param  SWPMIx SWPMI Instance
00846   * @retval None
00847   */
00848 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
00849 {
00850   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
00851 }
00852
00853 /**
00854   * @brief  Disable Receive buffer full interrupt
00855   * @rmtoll IER          RXBFIE        LL_SWPMI_DisableIT_RXBF
00856   * @param  SWPMIx SWPMI Instance
00857   * @retval None
00858   */
00859 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
00860 {
00861   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
00862 }
00863
00864 /**
00865   * @brief  Check if Slave resume interrupt is enabled
00866   * @rmtoll IER          SRIE          LL_SWPMI_IsEnabledIT_SR
00867   * @param  SWPMIx SWPMI Instance
00868   * @retval State of bit (1 or 0).
00869   */
00870 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)
00871 {
00872   return (READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE));
00873 }
00874
00875 /**
00876   * @brief  Check if Transmit complete interrupt is enabled
00877   * @rmtoll IER          TCIE          LL_SWPMI_IsEnabledIT_TC
00878   * @param  SWPMIx SWPMI Instance
00879   * @retval State of bit (1 or 0).
00880   */
00881 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)
00882 {
00883   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE));
00884 }
00885
00886 /**
00887   * @brief  Check if Transmit interrupt is enabled
00888   * @rmtoll IER          TIE           LL_SWPMI_IsEnabledIT_TX
00889   * @param  SWPMIx SWPMI Instance
00890   * @retval State of bit (1 or 0).
00891   */
00892 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)
00893 {
00894   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE));
00895 }
00896
00897 /**
00898   * @brief  Check if Receive interrupt is enabled
00899   * @rmtoll IER          RIE           LL_SWPMI_IsEnabledIT_RX
00900   * @param  SWPMIx SWPMI Instance
00901   * @retval State of bit (1 or 0).
00902   */
00903 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)
00904 {
00905   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE));
00906 }
00907
00908 /**
00909   * @brief  Check if Transmit underrun error interrupt is enabled
00910   * @rmtoll IER          TXUNRIE       LL_SWPMI_IsEnabledIT_TXUNR
00911   * @param  SWPMIx SWPMI Instance
00912   * @retval State of bit (1 or 0).
00913   */
00914 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00915 {
00916   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE));
00917 }
00918
00919 /**
00920   * @brief  Check if Receive overrun error interrupt is enabled
00921   * @rmtoll IER          RXOVRIE       LL_SWPMI_IsEnabledIT_RXOVR
00922   * @param  SWPMIx SWPMI Instance
00923   * @retval State of bit (1 or 0).
00924   */
00925 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00926 {
00927   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE));
00928 }
00929
00930 /**
00931   * @brief  Check if Receive CRC error interrupt is enabled
00932   * @rmtoll IER          RXBERIE       LL_SWPMI_IsEnabledIT_RXBER
00933   * @param  SWPMIx SWPMI Instance
00934   * @retval State of bit (1 or 0).
00935   */
00936 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)
00937 {
00938   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE));
00939 }
00940
00941 /**
00942   * @brief  Check if Transmit buffer empty interrupt is enabled
00943   * @rmtoll IER          TXBEIE        LL_SWPMI_IsEnabledIT_TXBE
00944   * @param  SWPMIx SWPMI Instance
00945   * @retval State of bit (1 or 0).
00946   */
00947 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)
00948 {
00949   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE));
00950 }
00951
00952 /**
00953   * @brief  Check if Receive buffer full interrupt is enabled
00954   * @rmtoll IER          RXBFIE        LL_SWPMI_IsEnabledIT_RXBF
00955   * @param  SWPMIx SWPMI Instance
00956   * @retval State of bit (1 or 0).
00957   */
00958 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)
00959 {
00960   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE));
00961 }
00962
00963 /**
00964   * @}
00965   */
00966
00967 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management
00968   * @{
00969   */
00970
00971 /**
00972   * @brief  Enable DMA mode for reception
00973   * @rmtoll CR           RXDMA         LL_SWPMI_EnableDMAReq_RX
00974   * @param  SWPMIx SWPMI Instance
00975   * @retval None
00976   */
00977 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
00978 {
00979   SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
00980 }
00981
00982 /**
00983   * @brief  Disable DMA mode for reception
00984   * @rmtoll CR           RXDMA         LL_SWPMI_DisableDMAReq_RX
00985   * @param  SWPMIx SWPMI Instance
00986   * @retval None
00987   */
00988 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
00989 {
00990   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
00991 }
00992
00993 /**
00994   * @brief  Check if DMA mode for reception is enabled
00995   * @rmtoll CR           RXDMA         LL_SWPMI_IsEnabledDMAReq_RX
00996   * @param  SWPMIx SWPMI Instance
00997   * @retval State of bit (1 or 0).
00998   */
00999 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)
01000 {
01001   return (READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA));
01002 }
01003
01004 /**
01005   * @brief  Enable DMA mode for transmission
01006   * @rmtoll CR           TXDMA         LL_SWPMI_EnableDMAReq_TX
01007   * @param  SWPMIx SWPMI Instance
01008   * @retval None
01009   */
01010 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
01011 {
01012   SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
01013 }
01014
01015 /**
01016   * @brief  Disable DMA mode for transmission
01017   * @rmtoll CR           TXDMA         LL_SWPMI_DisableDMAReq_TX
01018   * @param  SWPMIx SWPMI Instance
01019   * @retval None
01020   */
01021 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
01022 {
01023   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
01024 }
01025
01026 /**
01027   * @brief  Check if DMA mode for transmission is enabled
01028   * @rmtoll CR           TXDMA         LL_SWPMI_IsEnabledDMAReq_TX
01029   * @param  SWPMIx SWPMI Instance
01030   * @retval State of bit (1 or 0).
01031   */
01032 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)
01033 {
01034   return (READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA));
01035 }
01036
01037 /**
01038   * @brief  Get the data register address used for DMA transfer
01039   * @rmtoll TDR          TD            LL_SWPMI_DMA_GetRegAddr\n
01040   *         RDR          RD            LL_SWPMI_DMA_GetRegAddr
01041   * @param  SWPMIx SWPMI Instance
01042   * @param  Direction This parameter can be one of the following values:
01043   *         @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT
01044   *         @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE
01045   * @retval Address of data register
01046   */
01047 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction)
01048 {
01049   register uint32_t data_reg_addr = 0;
01050
01051   if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
01052   {
01053     /* return address of TDR register */
01054     data_reg_addr = (uint32_t)&(SWPMIx->TDR);
01055   }
01056   else
01057   {
01058     /* return address of RDR register */
01059     data_reg_addr = (uint32_t)&(SWPMIx->RDR);
01060   }
01061
01062   return data_reg_addr;
01063 }
01064
01065 /**
01066   * @}
01067   */
01068
01069 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management
01070   * @{
01071   */
01072
01073 /**
01074   * @brief  Retrieve number of data bytes present in payload of received frame
01075   * @rmtoll RFL          RFL           LL_SWPMI_GetReceiveFrameLength
01076   * @param  SWPMIx SWPMI Instance
01077   * @retval Value between Min_Data=0x00 and Max_Data=0x1F
01078   */
01079 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)
01080 {
01081   return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
01082 }
01083
01084 /**
01085   * @brief  Transmit Data Register
01086   * @rmtoll TDR          TD            LL_SWPMI_TransmitData32
01087   * @param  SWPMIx SWPMI Instance
01088   * @param  TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01089   * @retval None
01090   */
01091 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
01092 {
01093   WRITE_REG(SWPMIx->TDR, TxData);
01094 }
01095
01096 /**
01097   * @brief  Receive Data Register
01098   * @rmtoll RDR          RD            LL_SWPMI_ReceiveData32
01099   * @param  SWPMIx SWPMI Instance
01100   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01101   */
01102 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
01103 {
01104   return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
01105 }
01106
01107 /**
01108   * @brief  Enable SWP Transceiver Bypass
01109   * @note   The external interface for SWPMI is SWPMI_IO
01110   *         (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
01111   * @rmtoll OR           TBYP          LL_SWPMI_EnableTXBypass
01112   * @param  SWPMIx SWPMI Instance
01113   * @retval None
01114   */
01115 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
01116 {
01117   CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
01118 }
01119
01120 /**
01121   * @brief  Disable SWP Transceiver Bypass
01122   * @note   SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
01123   *         function on GPIOs. This configuration is selected to connect an external transceiver
01124   * @rmtoll OR           TBYP          LL_SWPMI_DisableTXBypass
01125   * @param  SWPMIx SWPMI Instance
01126   * @retval None
01127   */
01128 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
01129 {
01130   SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
01131 }
01132
01133 /**
01134   * @}
01135   */
01136
01137 #if defined(USE_FULL_LL_DRIVER)
01138 /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions
01139   * @{
01140   */
01141
01142 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx);
01143 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
01144 void        LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
01145
01146 /**
01147   * @}
01148   */
01149 #endif /*USE_FULL_LL_DRIVER*/
01150
01151 /**
01152   * @}
01153   */
01154
01155 /**
01156   * @}
01157   */
01158
01159 #endif /* defined (SWPMI1) */
01160
01161 /**
01162   * @}
01163   */
01164
01165 #ifdef __cplusplus
01166 }
01167 #endif
01168
01169 #endif /* __STM32L4xx_LL_SWPMI_H */
01170
01171 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_system.h Source File

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stm32l4xx_ll_system.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_system.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SYSTEM LL module.
00008   @verbatim
00009   ==============================================================================
00010                      ##### How to use this driver #####
00011   ==============================================================================
00012     [..]
00013     The LL SYSTEM driver contains a set of generic APIs that can be
00014     used by user:
00015       (+) Some of the FLASH features need to be handled in the SYSTEM file.
00016       (+) Access to DBGCMU registers
00017       (+) Access to SYSCFG registers
00018       (+) Access to VREFBUF registers
00019
00020   @endverbatim
00021   ******************************************************************************
00022   * @attention
00023   *
00024   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00025   *
00026   * Redistribution and use in source and binary forms, with or without modification,
00027   * are permitted provided that the following conditions are met:
00028   *   1. Redistributions of source code must retain the above copyright notice,
00029   *      this list of conditions and the following disclaimer.
00030   *   2. Redistributions in binary form must reproduce the above copyright notice,
00031   *      this list of conditions and the following disclaimer in the documentation
00032   *      and/or other materials provided with the distribution.
00033   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00034   *      may be used to endorse or promote products derived from this software
00035   *      without specific prior written permission.
00036   *
00037   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00038   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00039   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00040   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00041   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00042   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00043   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00044   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00045   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00046   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00047   *
00048   ******************************************************************************
00049   */
00050
00051 /* Define to prevent recursive inclusion -------------------------------------*/
00052 #ifndef __STM32L4xx_LL_SYSTEM_H
00053 #define __STM32L4xx_LL_SYSTEM_H
00054
00055 #ifdef __cplusplus
00056 extern "C" {
00057 #endif
00058
00059 /* Includes ------------------------------------------------------------------*/
00060 #include "stm32l4xx.h"
00061
00062 /** @addtogroup STM32L4xx_LL_Driver
00063   * @{
00064   */
00065
00066 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
00067
00068 /** @defgroup SYSTEM_LL SYSTEM
00069   * @{
00070   */
00071
00072 /* Private types -------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074
00075 /* Private constants ---------------------------------------------------------*/
00076 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
00077   * @{
00078   */
00079
00080 /* Defines used for position in the register */
00081 #define DBGMCU_REVID_POSITION         (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
00082
00083 /**
00084  * @brief Power-down in Run mode Flash key
00085  */
00086 #define FLASH_PDKEY1                  ((uint32_t)0x04152637U) /*!< Flash power down key1 */
00087 #define FLASH_PDKEY2                  ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
00088                                                                    to unlock the RUN_PD bit in FLASH_ACR */
00089
00090 /**
00091   * @}
00092   */
00093
00094 /* Private macros ------------------------------------------------------------*/
00095
00096 /* Exported types ------------------------------------------------------------*/
00097 /* Exported constants --------------------------------------------------------*/
00098 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
00099   * @{
00100   */
00101
00102 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
00103 * @{
00104 */
00105 #define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000                                  /*!< Main Flash memory mapped at 0x00000000              */
00106 #define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */
00107 #define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */
00108 #if defined(FMC_Bank1_R)
00109 #define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
00110 #endif /* FMC_Bank1_R */
00111 #define LL_SYSCFG_REMAP_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000                 */
00112 /**
00113   * @}
00114   */
00115
00116 #if defined(SYSCFG_MEMRMP_FB_MODE)
00117 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
00118   * @{
00119   */
00120 #define LL_SYSCFG_BANKMODE_BANK1           (uint32_t)0x00000000      /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
00121                                                                       and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
00122 #define LL_SYSCFG_BANKMODE_BANK2           SYSCFG_MEMRMP_FB_MODE     /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
00123                                                                       and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
00124 /**
00125   * @}
00126   */
00127
00128 #endif /* SYSCFG_MEMRMP_FB_MODE */
00129 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
00130   * @{
00131   */
00132 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
00133 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
00134 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
00135 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
00136 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
00137 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
00138 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
00139 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
00140 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
00141 #if defined(I2C2)
00142 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
00143 #endif /* I2C2 */
00144 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
00150   * @{
00151   */
00152 #define LL_SYSCFG_EXTI_PORTA               (uint32_t)0               /*!< EXTI PORT A                        */
00153 #define LL_SYSCFG_EXTI_PORTB               (uint32_t)1               /*!< EXTI PORT B                        */
00154 #define LL_SYSCFG_EXTI_PORTC               (uint32_t)2               /*!< EXTI PORT C                        */
00155 #define LL_SYSCFG_EXTI_PORTD               (uint32_t)3               /*!< EXTI PORT D                        */
00156 #define LL_SYSCFG_EXTI_PORTE               (uint32_t)4               /*!< EXTI PORT E                        */
00157 #if defined(GPIOF)
00158 #define LL_SYSCFG_EXTI_PORTF               (uint32_t)5               /*!< EXTI PORT F                        */
00159 #endif /* GPIOF */
00160 #if defined(GPIOG)
00161 #define LL_SYSCFG_EXTI_PORTG               (uint32_t)6               /*!< EXTI PORT G                        */
00162 #endif /* GPIOG */
00163 #define LL_SYSCFG_EXTI_PORTH               (uint32_t)7               /*!< EXTI PORT H                        */
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
00169   * @{
00170   */
00171 #define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16 | 0)  /* !< EXTI_POSITION_0  | EXTICR[0] */
00172 #define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16 | 0)  /* !< EXTI_POSITION_4  | EXTICR[0] */
00173 #define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16 | 0)  /* !< EXTI_POSITION_8  | EXTICR[0] */
00174 #define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16 | 0)  /* !< EXTI_POSITION_12 | EXTICR[0] */
00175 #define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16 | 1)  /* !< EXTI_POSITION_0  | EXTICR[1] */
00176 #define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16 | 1)  /* !< EXTI_POSITION_4  | EXTICR[1] */
00177 #define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16 | 1)  /* !< EXTI_POSITION_8  | EXTICR[1] */
00178 #define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16 | 1)  /* !< EXTI_POSITION_12 | EXTICR[1] */
00179 #define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16 | 2)  /* !< EXTI_POSITION_0  | EXTICR[2] */
00180 #define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16 | 2)  /* !< EXTI_POSITION_4  | EXTICR[2] */
00181 #define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16 | 2)  /* !< EXTI_POSITION_8  | EXTICR[2] */
00182 #define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16 | 2)  /* !< EXTI_POSITION_12 | EXTICR[2] */
00183 #define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16 | 3)  /* !< EXTI_POSITION_0  | EXTICR[3] */
00184 #define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16 | 3)  /* !< EXTI_POSITION_4  | EXTICR[3] */
00185 #define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16 | 3)  /* !< EXTI_POSITION_8  | EXTICR[3] */
00186 #define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16 | 3)  /* !< EXTI_POSITION_12 | EXTICR[3] */
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
00192   * @{
00193   */
00194 #define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal
00195                                                                    with Break Input of TIM1/8/15/16/17                           */
00196 #define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection
00197                                                                    with TIM1/8/15/16/17 Break Input
00198                                                                    and also the PVDE and PLS bits of the Power Control Interface */
00199 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY    SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM2_PARITY error signal
00200                                                                    with Break Input of TIM1/8/15/16/17                           */
00201 #define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4
00202                                                                    with Break Input of TIM1/15/16/17                             */
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
00208   * @{
00209   */
00210 #define LL_SYSCFG_SRAM2WRP_PAGE0           SYSCFG_SWPR_PAGE0  /*!< SRAM2 Write protection page 0  */
00211 #define LL_SYSCFG_SRAM2WRP_PAGE1           SYSCFG_SWPR_PAGE1  /*!< SRAM2 Write protection page 1  */
00212 #define LL_SYSCFG_SRAM2WRP_PAGE2           SYSCFG_SWPR_PAGE2  /*!< SRAM2 Write protection page 2  */
00213 #define LL_SYSCFG_SRAM2WRP_PAGE3           SYSCFG_SWPR_PAGE3  /*!< SRAM2 Write protection page 3  */
00214 #define LL_SYSCFG_SRAM2WRP_PAGE4           SYSCFG_SWPR_PAGE4  /*!< SRAM2 Write protection page 4  */
00215 #define LL_SYSCFG_SRAM2WRP_PAGE5           SYSCFG_SWPR_PAGE5  /*!< SRAM2 Write protection page 5  */
00216 #define LL_SYSCFG_SRAM2WRP_PAGE6           SYSCFG_SWPR_PAGE6  /*!< SRAM2 Write protection page 6  */
00217 #define LL_SYSCFG_SRAM2WRP_PAGE7           SYSCFG_SWPR_PAGE7  /*!< SRAM2 Write protection page 7  */
00218 #define LL_SYSCFG_SRAM2WRP_PAGE8           SYSCFG_SWPR_PAGE8  /*!< SRAM2 Write protection page 8  */
00219 #define LL_SYSCFG_SRAM2WRP_PAGE9           SYSCFG_SWPR_PAGE9  /*!< SRAM2 Write protection page 9  */
00220 #define LL_SYSCFG_SRAM2WRP_PAGE10          SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
00221 #define LL_SYSCFG_SRAM2WRP_PAGE11          SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
00222 #define LL_SYSCFG_SRAM2WRP_PAGE12          SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
00223 #define LL_SYSCFG_SRAM2WRP_PAGE13          SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
00224 #define LL_SYSCFG_SRAM2WRP_PAGE14          SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
00225 #define LL_SYSCFG_SRAM2WRP_PAGE15          SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
00226 #if defined(SYSCFG_SWPR_PAGE16)
00227 #define LL_SYSCFG_SRAM2WRP_PAGE16          SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
00228 #define LL_SYSCFG_SRAM2WRP_PAGE17          SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
00229 #define LL_SYSCFG_SRAM2WRP_PAGE18          SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
00230 #define LL_SYSCFG_SRAM2WRP_PAGE19          SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
00231 #define LL_SYSCFG_SRAM2WRP_PAGE20          SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
00232 #define LL_SYSCFG_SRAM2WRP_PAGE21          SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
00233 #define LL_SYSCFG_SRAM2WRP_PAGE22          SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
00234 #define LL_SYSCFG_SRAM2WRP_PAGE23          SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
00235 #define LL_SYSCFG_SRAM2WRP_PAGE24          SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
00236 #define LL_SYSCFG_SRAM2WRP_PAGE25          SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
00237 #define LL_SYSCFG_SRAM2WRP_PAGE26          SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
00238 #define LL_SYSCFG_SRAM2WRP_PAGE27          SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
00239 #define LL_SYSCFG_SRAM2WRP_PAGE28          SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
00240 #define LL_SYSCFG_SRAM2WRP_PAGE29          SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
00241 #define LL_SYSCFG_SRAM2WRP_PAGE30          SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
00242 #define LL_SYSCFG_SRAM2WRP_PAGE31          SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
00243 #endif /* SYSCFG_SWPR_PAGE16 */
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
00249   * @{
00250   */
00251 #define LL_DBGMCU_TRACE_NONE               (uint32_t)0x00000000U                           /*!< TRACE pins not assigned (default state) */
00252 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
00253 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
00254 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
00255 #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
00261   * @{
00262   */
00263 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1FZR1_DBG_TIM2_STOP   /*!< The counter clock of TIM2 is stopped when the core is halted*/
00264 #if defined(TIM3)
00265 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1FZR1_DBG_TIM3_STOP   /*!< The counter clock of TIM3 is stopped when the core is halted*/
00266 #endif /* TIM3 */
00267 #if defined(TIM4)
00268 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1FZR1_DBG_TIM4_STOP   /*!< The counter clock of TIM4 is stopped when the core is halted*/
00269 #endif /* TIM4 */
00270 #if defined(TIM5)
00271 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1FZR1_DBG_TIM5_STOP   /*!< The counter clock of TIM5 is stopped when the core is halted*/
00272 #endif /* TIM5 */
00273 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1FZR1_DBG_TIM6_STOP   /*!< The counter clock of TIM6 is stopped when the core is halted*/
00274 #if defined(TIM7)
00275 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1FZR1_DBG_TIM7_STOP   /*!< The counter clock of TIM7 is stopped when the core is halted*/
00276 #endif /* TIM7 */
00277 #define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1FZR1_DBG_RTC_STOP    /*!< The clock of the RTC counter is stopped when the core is halted*/
00278 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1FZR1_DBG_WWDG_STOP   /*!< The window watchdog counter clock is stopped when the core is halted*/
00279 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1FZR1_DBG_IWDG_STOP   /*!< The independent watchdog counter clock is stopped when the core is halted*/
00280 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1FZR1_DBG_I2C1_STOP   /*!< The I2C1 SMBus timeout is frozen*/
00281 #if defined(I2C2)
00282 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1FZR1_DBG_I2C2_STOP   /*!< The I2C2 SMBus timeout is frozen*/
00283 #endif /* I2C2 */
00284 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1FZR1_DBG_I2C3_STOP   /*!< The I2C3 SMBus timeout is frozen*/
00285 #define LL_DBGMCU_APB1_GRP1_CAN_STOP       DBGMCU_APB1FZR1_DBG_CAN_STOP    /*!< The bxCAN receive registers are frozen*/
00286 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
00292   * @{
00293   */
00294 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP    DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
00300   * @{
00301   */
00302 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ_DBG_TIM1_STOP     /*!< The counter clock of TIM1 is stopped when the core is halted*/
00303 #if defined(TIM8)
00304 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ_DBG_TIM8_STOP     /*!< The counter clock of TIM8 is stopped when the core is halted*/
00305 #endif /* TIM8 */
00306 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ_DBG_TIM15_STOP    /*!< The counter clock of TIM15 is stopped when the core is halted*/
00307 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ_DBG_TIM16_STOP    /*!< The counter clock of TIM16 is stopped when the core is halted*/
00308 #if defined(TIM17)
00309 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ_DBG_TIM17_STOP    /*!< The counter clock of TIM17 is stopped when the core is halted*/
00310 #endif /* TIM17 */
00311 /**
00312   * @}
00313   */
00314
00315 #if defined(VREFBUF)
00316 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
00317   * @{
00318   */
00319 #define LL_VREFBUF_VOLTAGE_SCALE0          ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
00320 #define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
00321 /**
00322   * @}
00323   */
00324 #endif /* VREFBUF */
00325
00326 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
00327   * @{
00328   */
00329 #define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
00330 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
00331 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
00332 #define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
00333 #define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
00334 /**
00335   * @}
00336   */
00337
00338 /**
00339   * @}
00340   */
00341
00342 /* Exported macro ------------------------------------------------------------*/
00343
00344 /* Exported functions --------------------------------------------------------*/
00345 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
00346   * @{
00347   */
00348
00349 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
00350   * @{
00351   */
00352
00353 /**
00354   * @brief  Set memory mapping at address 0x00000000
00355   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
00356   * @param  Memory This parameter can be one of the following values:
00357   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00358   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00359   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00360   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
00361   *         @arg @ref LL_SYSCFG_REMAP_QUADSPI
00362   *
00363   *         (*) value not defined in all devices
00364   * @retval None
00365   */
00366 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
00367 {
00368   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
00369 }
00370
00371 /**
00372   * @brief  Get memory mapping at address 0x00000000
00373   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
00374   * @retval Returned value can be one of the following values:
00375   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00376   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00377   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00378   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
00379   *         @arg @ref LL_SYSCFG_REMAP_QUADSPI
00380   *
00381   *         (*) value not defined in all devices
00382   */
00383 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
00384 {
00385   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
00386 }
00387
00388 #if defined(SYSCFG_MEMRMP_FB_MODE)
00389 /**
00390   * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
00391   * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_SetFlashBankMode
00392   * @param  Bank This parameter can be one of the following values:
00393   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
00394   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
00395   * @retval None
00396   */
00397 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
00398 {
00399   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
00400 }
00401
00402 /**
00403   * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
00404   * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_GetFlashBankMode
00405   * @retval Returned value can be one of the following values:
00406   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
00407   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
00408   */
00409 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
00410 {
00411   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
00412 }
00413 #endif /* SYSCFG_MEMRMP_FB_MODE */
00414
00415 /**
00416   * @brief  Firewall protection enabled
00417   * @rmtoll SYSCFG_CFGR1 FWDIS         LL_SYSCFG_EnableFirewall
00418   * @retval None
00419   */
00420 __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
00421 {
00422   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
00423 }
00424
00425 /**
00426   * @brief  Check if Firewall protection is enabled or not
00427   * @rmtoll SYSCFG_CFGR1 FWDIS         LL_SYSCFG_IsEnabledFirewall
00428   * @retval State of bit (1 or 0).
00429   */
00430 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
00431 {
00432   return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
00433 }
00434
00435 /**
00436   * @brief  Enable I/O analog switch voltage booster.
00437   * @note   When voltage booster is enabled, I/O analog switches are supplied
00438   *         by a dedicated voltage booster, from VDD power domain. This is
00439   *         the recommended configuration with low VDDA voltage operation.
00440   * @note   The I/O analog switch voltage booster is relevant for peripherals
00441   *         using I/O in analog input: ADC, COMP, OPAMP.
00442   *         However, COMP and OPAMP inputs have a high impedance and
00443   *         voltage booster do not impact performance significantly.
00444   *         Therefore, the voltage booster is mainly intended for
00445   *         usage with ADC.
00446   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster
00447   * @retval None
00448   */
00449 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
00450 {
00451   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00452 }
00453
00454 /**
00455   * @brief  Disable I/O analog switch voltage booster.
00456   * @note   When voltage booster is enabled, I/O analog switches are supplied
00457   *         by a dedicated voltage booster, from VDD power domain. This is
00458   *         the recommended configuration with low VDDA voltage operation.
00459   * @note   The I/O analog switch voltage booster is relevant for peripherals
00460   *         using I/O in analog input: ADC, COMP, OPAMP.
00461   *         However, COMP and OPAMP inputs have a high impedance and
00462   *         voltage booster do not impact performance significantly.
00463   *         Therefore, the voltage booster is mainly intended for
00464   *         usage with ADC.
00465   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster
00466   * @retval None
00467   */
00468 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
00469 {
00470   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00471 }
00472
00473 /**
00474   * @brief  Enable the I2C fast mode plus driving capability.
00475   * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
00476   *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
00477   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00478   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00479   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00480   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
00481   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
00482   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00483   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00484   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
00485   *
00486   *         (*) value not defined in all devices
00487   * @retval None
00488   */
00489 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
00490 {
00491   SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00492 }
00493
00494 /**
00495   * @brief  Disable the I2C fast mode plus driving capability.
00496   * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
00497   *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
00498   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00499   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00500   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00501   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
00502   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
00503   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00504   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00505   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
00506   *
00507   *         (*) value not defined in all devices
00508   * @retval None
00509   */
00510 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
00511 {
00512   CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00513 }
00514
00515 /**
00516   * @brief  Enable Floating Point Unit Invalid operation Interrupt
00517   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_EnableIT_FPU_IOC
00518   * @retval None
00519   */
00520 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
00521 {
00522   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
00523 }
00524
00525 /**
00526   * @brief  Enable Floating Point Unit Divide-by-zero Interrupt
00527   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_EnableIT_FPU_DZC
00528   * @retval None
00529   */
00530 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
00531 {
00532   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
00533 }
00534
00535 /**
00536   * @brief  Enable Floating Point Unit Underflow Interrupt
00537   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_EnableIT_FPU_UFC
00538   * @retval None
00539   */
00540 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
00541 {
00542   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
00543 }
00544
00545 /**
00546   * @brief  Enable Floating Point Unit Overflow Interrupt
00547   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_EnableIT_FPU_OFC
00548   * @retval None
00549   */
00550 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
00551 {
00552   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
00553 }
00554
00555 /**
00556   * @brief  Enable Floating Point Unit Input denormal Interrupt
00557   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_EnableIT_FPU_IDC
00558   * @retval None
00559   */
00560 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
00561 {
00562   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
00563 }
00564
00565 /**
00566   * @brief  Enable Floating Point Unit Inexact Interrupt
00567   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_EnableIT_FPU_IXC
00568   * @retval None
00569   */
00570 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
00571 {
00572   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
00573 }
00574
00575 /**
00576   * @brief  Disable Floating Point Unit Invalid operation Interrupt
00577   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_DisableIT_FPU_IOC
00578   * @retval None
00579   */
00580 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
00581 {
00582   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
00583 }
00584
00585 /**
00586   * @brief  Disable Floating Point Unit Divide-by-zero Interrupt
00587   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_DisableIT_FPU_DZC
00588   * @retval None
00589   */
00590 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
00591 {
00592   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
00593 }
00594
00595 /**
00596   * @brief  Disable Floating Point Unit Underflow Interrupt
00597   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_DisableIT_FPU_UFC
00598   * @retval None
00599   */
00600 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
00601 {
00602   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
00603 }
00604
00605 /**
00606   * @brief  Disable Floating Point Unit Overflow Interrupt
00607   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_DisableIT_FPU_OFC
00608   * @retval None
00609   */
00610 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
00611 {
00612   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
00613 }
00614
00615 /**
00616   * @brief  Disable Floating Point Unit Input denormal Interrupt
00617   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_DisableIT_FPU_IDC
00618   * @retval None
00619   */
00620 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
00621 {
00622   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
00623 }
00624
00625 /**
00626   * @brief  Disable Floating Point Unit Inexact Interrupt
00627   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_DisableIT_FPU_IXC
00628   * @retval None
00629   */
00630 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
00631 {
00632   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
00633 }
00634
00635 /**
00636   * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
00637   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_IsEnabledIT_FPU_IOC
00638   * @retval State of bit (1 or 0).
00639   */
00640 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
00641 {
00642   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
00643 }
00644
00645 /**
00646   * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
00647   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_IsEnabledIT_FPU_DZC
00648   * @retval State of bit (1 or 0).
00649   */
00650 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
00651 {
00652   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
00653 }
00654
00655 /**
00656   * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
00657   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_IsEnabledIT_FPU_UFC
00658   * @retval State of bit (1 or 0).
00659   */
00660 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
00661 {
00662   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
00663 }
00664
00665 /**
00666   * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
00667   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_IsEnabledIT_FPU_OFC
00668   * @retval State of bit (1 or 0).
00669   */
00670 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
00671 {
00672   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
00673 }
00674
00675 /**
00676   * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
00677   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_IsEnabledIT_FPU_IDC
00678   * @retval State of bit (1 or 0).
00679   */
00680 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
00681 {
00682   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
00683 }
00684
00685 /**
00686   * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
00687   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_IsEnabledIT_FPU_IXC
00688   * @retval State of bit (1 or 0).
00689   */
00690 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
00691 {
00692   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
00693 }
00694
00695 /**
00696   * @brief  Configure source input for the EXTI external interrupt.
00697   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
00698   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
00699   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
00700   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
00701   * @param  Port This parameter can be one of the following values:
00702   *         @arg @ref LL_SYSCFG_EXTI_PORTA
00703   *         @arg @ref LL_SYSCFG_EXTI_PORTB
00704   *         @arg @ref LL_SYSCFG_EXTI_PORTC
00705   *         @arg @ref LL_SYSCFG_EXTI_PORTD
00706   *         @arg @ref LL_SYSCFG_EXTI_PORTE
00707   *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
00708   *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
00709   *         @arg @ref LL_SYSCFG_EXTI_PORTH
00710   *
00711   *         (*) value not defined in all devices
00712   * @param  Line This parameter can be one of the following values:
00713   *         @arg @ref LL_SYSCFG_EXTI_LINE0
00714   *         @arg @ref LL_SYSCFG_EXTI_LINE1
00715   *         @arg @ref LL_SYSCFG_EXTI_LINE2
00716   *         @arg @ref LL_SYSCFG_EXTI_LINE3
00717   *         @arg @ref LL_SYSCFG_EXTI_LINE4
00718   *         @arg @ref LL_SYSCFG_EXTI_LINE5
00719   *         @arg @ref LL_SYSCFG_EXTI_LINE6
00720   *         @arg @ref LL_SYSCFG_EXTI_LINE7
00721   *         @arg @ref LL_SYSCFG_EXTI_LINE8
00722   *         @arg @ref LL_SYSCFG_EXTI_LINE9
00723   *         @arg @ref LL_SYSCFG_EXTI_LINE10
00724   *         @arg @ref LL_SYSCFG_EXTI_LINE11
00725   *         @arg @ref LL_SYSCFG_EXTI_LINE12
00726   *         @arg @ref LL_SYSCFG_EXTI_LINE13
00727   *         @arg @ref LL_SYSCFG_EXTI_LINE14
00728   *         @arg @ref LL_SYSCFG_EXTI_LINE15
00729   * @retval None
00730   */
00731 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
00732 {
00733   MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
00734 }
00735
00736 /**
00737   * @brief  Get the configured defined for specific EXTI Line
00738   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
00739   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
00740   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
00741   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
00742   * @param  Line This parameter can be one of the following values:
00743   *         @arg @ref LL_SYSCFG_EXTI_LINE0
00744   *         @arg @ref LL_SYSCFG_EXTI_LINE1
00745   *         @arg @ref LL_SYSCFG_EXTI_LINE2
00746   *         @arg @ref LL_SYSCFG_EXTI_LINE3
00747   *         @arg @ref LL_SYSCFG_EXTI_LINE4
00748   *         @arg @ref LL_SYSCFG_EXTI_LINE5
00749   *         @arg @ref LL_SYSCFG_EXTI_LINE6
00750   *         @arg @ref LL_SYSCFG_EXTI_LINE7
00751   *         @arg @ref LL_SYSCFG_EXTI_LINE8
00752   *         @arg @ref LL_SYSCFG_EXTI_LINE9
00753   *         @arg @ref LL_SYSCFG_EXTI_LINE10
00754   *         @arg @ref LL_SYSCFG_EXTI_LINE11
00755   *         @arg @ref LL_SYSCFG_EXTI_LINE12
00756   *         @arg @ref LL_SYSCFG_EXTI_LINE13
00757   *         @arg @ref LL_SYSCFG_EXTI_LINE14
00758   *         @arg @ref LL_SYSCFG_EXTI_LINE15
00759   * @retval Returned value can be one of the following values:
00760   *         @arg @ref LL_SYSCFG_EXTI_PORTA
00761   *         @arg @ref LL_SYSCFG_EXTI_PORTB
00762   *         @arg @ref LL_SYSCFG_EXTI_PORTC
00763   *         @arg @ref LL_SYSCFG_EXTI_PORTD
00764   *         @arg @ref LL_SYSCFG_EXTI_PORTE
00765   *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
00766   *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
00767   *         @arg @ref LL_SYSCFG_EXTI_PORTH
00768   *
00769   *         (*) value not defined in all devices
00770   */
00771 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
00772 {
00773   return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
00774 }
00775
00776 /**
00777   * @brief  Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
00778   * automatically cleared at the end of the SRAM2 erase operation.)
00779   * @note This bit is write-protected: setting this bit is possible only after the
00780   *       correct key sequence is written in the SYSCFG_SKR register.
00781   * @rmtoll SYSCFG_SCSR  SRAM2ER       LL_SYSCFG_EnableSRAM2Erase
00782   * @retval None
00783   */
00784 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
00785 {
00786   /* unlock the write protection of the SRAM2ER bit */
00787   WRITE_REG(SYSCFG->SKR, 0xCA);
00788   WRITE_REG(SYSCFG->SKR, 0x53);
00789
00790   /* Starts a hardware SRAM2 erase operation*/
00791   SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
00792 }
00793
00794 /**
00795   * @brief  Check if SRAM2 erase operation is on going
00796   * @rmtoll SYSCFG_SCSR  SRAM2BSY      LL_SYSCFG_IsSRAM2EraseOngoing
00797   * @retval State of bit (1 or 0).
00798   */
00799 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
00800 {
00801   return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
00802 }
00803
00804 /**
00805   * @brief  Set connections to TIM1/8/15/16/17 Break inputs
00806   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_SetTIMBreakInputs\n
00807   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_SetTIMBreakInputs\n
00808   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_SetTIMBreakInputs\n
00809   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_SetTIMBreakInputs
00810   * @param  Break This parameter can be a combination of the following values:
00811   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
00812   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
00813   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
00814   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
00815   * @retval None
00816   */
00817 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
00818 {
00819   MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
00820 }
00821
00822 /**
00823   * @brief  Get connections to TIM1/8/15/16/17 Break inputs
00824   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_GetTIMBreakInputs\n
00825   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_GetTIMBreakInputs\n
00826   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_GetTIMBreakInputs\n
00827   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_GetTIMBreakInputs
00828   * @retval Returned value can be can be a combination of the following values:
00829   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
00830   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
00831   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
00832   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
00833   */
00834 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
00835 {
00836   return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
00837 }
00838
00839 /**
00840   * @brief  Check if SRAM2 parity error detected
00841   * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_IsActiveFlag_SP
00842   * @retval State of bit (1 or 0).
00843   */
00844 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
00845 {
00846   return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
00847 }
00848
00849 /**
00850   * @brief  Clear SRAM2 parity error flag
00851   * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_ClearFlag_SP
00852   * @retval None
00853   */
00854 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
00855 {
00856   SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
00857 }
00858
00859 /**
00860   * @brief  Enable SRAM2 page write protection
00861   * @note Write protection is cleared only by a system reset
00862   * @rmtoll SYSCFG_SWPR  PAGEx         LL_SYSCFG_EnableSRAM2PageWRP
00863   * @param  SRAM2WRP This parameter can be a combination of the following values:
00864   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
00865   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
00866   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
00867   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
00868   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
00869   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
00870   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
00871   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
00872   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
00873   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
00874   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
00875   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
00876   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
00877   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
00878   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
00879   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
00880   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
00881   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
00882   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
00883   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
00884   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
00885   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
00886   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
00887   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
00888   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
00889   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
00890   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
00891   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
00892   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
00893   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
00894   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
00895   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
00896   *
00897   *         (*) value not defined in all devices
00898   * @retval None
00899   */
00900 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP(uint32_t SRAM2WRP)
00901 {
00902   SET_BIT(SYSCFG->SWPR, SRAM2WRP);
00903 }
00904
00905 /**
00906   * @brief  SRAM2 page write protection lock prior to erase
00907   * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_LockSRAM2WRP
00908   * @retval None
00909   */
00910 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
00911 {
00912   /* Writing a wrong key reactivates the write protection */
00913   WRITE_REG(SYSCFG->SKR, 0x00);
00914 }
00915
00916 /**
00917   * @brief  SRAM2 page write protection unlock prior to erase
00918   * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_UnlockSRAM2WRP
00919   * @retval None
00920   */
00921 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
00922 {
00923   /* unlock the write protection of the SRAM2ER bit */
00924   WRITE_REG(SYSCFG->SKR, 0xCA);
00925   WRITE_REG(SYSCFG->SKR, 0x53);
00926 }
00927
00928 /**
00929   * @}
00930   */
00931
00932
00933 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
00934   * @{
00935   */
00936
00937 /**
00938   * @brief  Return the device identifier
00939   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
00940   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
00941   */
00942 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
00943 {
00944   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
00945 }
00946
00947 /**
00948   * @brief  Return the device revision identifier
00949   * @note This field indicates the revision of the device.
00950   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
00951   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
00952   */
00953 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
00954 {
00955   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
00956 }
00957
00958 /**
00959   * @brief  Enable the Debug Module during SLEEP mode
00960   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
00961   * @retval None
00962   */
00963 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
00964 {
00965   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00966 }
00967
00968 /**
00969   * @brief  Disable the Debug Module during SLEEP mode
00970   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
00971   * @retval None
00972   */
00973 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
00974 {
00975   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00976 }
00977
00978 /**
00979   * @brief  Enable the Debug Module during STOP mode
00980   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
00981   * @retval None
00982   */
00983 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
00984 {
00985   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00986 }
00987
00988 /**
00989   * @brief  Disable the Debug Module during STOP mode
00990   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
00991   * @retval None
00992   */
00993 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
00994 {
00995   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00996 }
00997
00998 /**
00999   * @brief  Enable the Debug Module during STANDBY mode
01000   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
01001   * @retval None
01002   */
01003 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
01004 {
01005   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
01006 }
01007
01008 /**
01009   * @brief  Disable the Debug Module during STANDBY mode
01010   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
01011   * @retval None
01012   */
01013 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
01014 {
01015   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
01016 }
01017
01018 /**
01019   * @brief  Set Trace pin assignment control
01020   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
01021   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
01022   * @param  PinAssignment This parameter can be one of the following values:
01023   *         @arg @ref LL_DBGMCU_TRACE_NONE
01024   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
01025   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
01026   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
01027   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
01028   * @retval None
01029   */
01030 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
01031 {
01032   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
01033 }
01034
01035 /**
01036   * @brief  Get Trace pin assignment control
01037   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
01038   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
01039   * @retval Returned value can be one of the following values:
01040   *         @arg @ref LL_DBGMCU_TRACE_NONE
01041   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
01042   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
01043   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
01044   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
01045   */
01046 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
01047 {
01048   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
01049 }
01050
01051 /**
01052   * @brief  Freeze APB1 peripherals (group1 peripherals)
01053   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
01054   * @param  Periphs This parameter can be a combination of the following values:
01055   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01056   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
01057   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
01058   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
01059   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
01060   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
01061   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01062   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01063   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01064   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01065   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
01066   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
01067   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
01068   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
01069   *
01070   *         (*) value not defined in all devices.
01071   * @retval None
01072   */
01073 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
01074 {
01075   SET_BIT(DBGMCU->APB1FZR1, Periphs);
01076 }
01077
01078 /**
01079   * @brief  Freeze APB1 peripherals (group2 peripherals)
01080   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_FreezePeriph
01081   * @param  Periphs This parameter can be a combination of the following values:
01082   *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
01083   * @retval None
01084   */
01085 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
01086 {
01087   SET_BIT(DBGMCU->APB1FZR2, Periphs);
01088 }
01089
01090 /**
01091   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
01092   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
01093   * @param  Periphs This parameter can be a combination of the following values:
01094   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01095   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
01096   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
01097   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
01098   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
01099   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
01100   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01101   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01102   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01103   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01104   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
01105   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
01106   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
01107   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
01108   *
01109   *         (*) value not defined in all devices.
01110   * @retval None
01111   */
01112 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
01113 {
01114   CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
01115 }
01116
01117 /**
01118   * @brief  Unfreeze APB1 peripherals (group2 peripherals)
01119   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_UnFreezePeriph
01120   * @param  Periphs This parameter can be a combination of the following values:
01121   *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
01122   * @retval None
01123   */
01124 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
01125 {
01126   CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
01127 }
01128
01129 /**
01130   * @brief  Freeze APB2 peripherals
01131   * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
01132   * @param  Periphs This parameter can be a combination of the following values:
01133   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
01134   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
01135   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
01136   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01137   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
01138   *
01139   *         (*) value not defined in all devices.
01140   * @retval None
01141   */
01142 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
01143 {
01144   SET_BIT(DBGMCU->APB2FZ, Periphs);
01145 }
01146
01147 /**
01148   * @brief  Unfreeze APB2 peripherals
01149   * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
01150   * @param  Periphs This parameter can be a combination of the following values:
01151   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
01152   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
01153   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
01154   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01155   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
01156   *
01157   *         (*) value not defined in all devices.
01158   * @retval None
01159   */
01160 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
01161 {
01162   CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
01163 }
01164
01165 /**
01166   * @}
01167   */
01168
01169 #if defined(VREFBUF)
01170 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
01171   * @{
01172   */
01173
01174 /**
01175   * @brief  Enable Internal voltage reference
01176   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Enable
01177   * @retval None
01178   */
01179 __STATIC_INLINE void LL_VREFBUF_Enable(void)
01180 {
01181   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
01182 }
01183
01184 /**
01185   * @brief  Disable Internal voltage reference
01186   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Disable
01187   * @retval None
01188   */
01189 __STATIC_INLINE void LL_VREFBUF_Disable(void)
01190 {
01191   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
01192 }
01193
01194 /**
01195   * @brief  Enable high impedance (VREF+pin is high impedance)
01196   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_EnableHIZ
01197   * @retval None
01198   */
01199 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
01200 {
01201   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
01202 }
01203
01204 /**
01205   * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
01206   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_DisableHIZ
01207   * @retval None
01208   */
01209 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
01210 {
01211   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
01212 }
01213
01214 /**
01215   * @brief  Set the Voltage reference scale
01216   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_SetVoltageScaling
01217   * @param  Scale This parameter can be one of the following values:
01218   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
01219   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
01220   * @retval None
01221   */
01222 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
01223 {
01224   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
01225 }
01226
01227 /**
01228   * @brief  Get the Voltage reference scale
01229   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_GetVoltageScaling
01230   * @retval Returned value can be one of the following values:
01231   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
01232   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
01233   */
01234 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
01235 {
01236   return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
01237 }
01238
01239 /**
01240   * @brief  Check if Voltage reference buffer is ready
01241   * @rmtoll VREFBUF_CSR  VRR           LL_VREFBUF_IsVREFReady
01242   * @retval State of bit (1 or 0).
01243   */
01244 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
01245 {
01246   return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
01247 }
01248
01249 /**
01250   * @brief  Get the trimming code for VREFBUF calibration
01251   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_GetTrimming
01252   * @retval Between 0 and 0x3F
01253   */
01254 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
01255 {
01256   return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
01257 }
01258
01259 /**
01260   * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
01261   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_SetTrimming
01262   * @param  Value Between 0 and 0x3F
01263   * @retval None
01264   */
01265 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
01266 {
01267   WRITE_REG(VREFBUF->CCR, Value);
01268 }
01269
01270 /**
01271   * @}
01272   */
01273 #endif /* VREFBUF */
01274
01275 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
01276   * @{
01277   */
01278
01279 /**
01280   * @brief  Set FLASH Latency
01281   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
01282   * @param  Latency This parameter can be one of the following values:
01283   *         @arg @ref LL_FLASH_LATENCY_0
01284   *         @arg @ref LL_FLASH_LATENCY_1
01285   *         @arg @ref LL_FLASH_LATENCY_2
01286   *         @arg @ref LL_FLASH_LATENCY_3
01287   *         @arg @ref LL_FLASH_LATENCY_4
01288   * @retval None
01289   */
01290 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
01291 {
01292   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
01293 }
01294
01295 /**
01296   * @brief  Get FLASH Latency
01297   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
01298   * @retval Returned value can be one of the following values:
01299   *         @arg @ref LL_FLASH_LATENCY_0
01300   *         @arg @ref LL_FLASH_LATENCY_1
01301   *         @arg @ref LL_FLASH_LATENCY_2
01302   *         @arg @ref LL_FLASH_LATENCY_3
01303   *         @arg @ref LL_FLASH_LATENCY_4
01304   */
01305 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
01306 {
01307   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
01308 }
01309
01310 /**
01311   * @brief  Enable Prefetch
01312   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
01313   * @retval None
01314   */
01315 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
01316 {
01317   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
01318 }
01319
01320 /**
01321   * @brief  Disable Prefetch
01322   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
01323   * @retval None
01324   */
01325 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
01326 {
01327   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
01328 }
01329
01330 /**
01331   * @brief  Check if Prefetch buffer is enabled
01332   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
01333   * @retval State of bit (1 or 0).
01334   */
01335 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
01336 {
01337   return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
01338 }
01339
01340 /**
01341   * @brief  Enable Instruction cache
01342   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
01343   * @retval None
01344   */
01345 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
01346 {
01347   SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
01348 }
01349
01350 /**
01351   * @brief  Disable Instruction cache
01352   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
01353   * @retval None
01354   */
01355 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
01356 {
01357   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
01358 }
01359
01360 /**
01361   * @brief  Enable Data cache
01362   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
01363   * @retval None
01364   */
01365 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
01366 {
01367   SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
01368 }
01369
01370 /**
01371   * @brief  Disable Data cache
01372   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
01373   * @retval None
01374   */
01375 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
01376 {
01377   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
01378 }
01379
01380 /**
01381   * @brief  Enable Instruction cache reset
01382   * @note  bit can be written only when the instruction cache is disabled
01383   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
01384   * @retval None
01385   */
01386 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
01387 {
01388   SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
01389 }
01390
01391 /**
01392   * @brief  Disable Instruction cache reset
01393   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
01394   * @retval None
01395   */
01396 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
01397 {
01398   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
01399 }
01400
01401 /**
01402   * @brief  Enable Data cache reset
01403   * @note bit can be written only when the data cache is disabled
01404   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
01405   * @retval None
01406   */
01407 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
01408 {
01409   SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
01410 }
01411
01412 /**
01413   * @brief  Disable Data cache reset
01414   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
01415   * @retval None
01416   */
01417 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
01418 {
01419   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
01420 }
01421
01422 /**
01423   * @brief  Enable Flash Power-down mode during run mode or Low-power run mode
01424   * @note Flash memory can be put in power-down mode only when the code is executed
01425   *       from RAM
01426   * @note Flash must not be accessed when power down is enabled
01427   * @note Flash must not be put in power-down while a program or an erase operation
01428   *       is on-going
01429   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
01430   *         FLASH_PDKEYR PDKEY1        LL_FLASH_EnableRunPowerDown\n
01431   *         FLASH_PDKEYR PDKEY2        LL_FLASH_EnableRunPowerDown
01432   * @retval None
01433   */
01434 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
01435 {
01436   /* Following values must be written consecutively to unlock the RUN_PD bit in
01437      FLASH_ACR */
01438   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
01439   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
01440   SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
01441 }
01442
01443 /**
01444   * @brief  Disable Flash Power-down mode during run mode or Low-power run mode
01445   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_DisableRunPowerDown\n
01446   *         FLASH_PDKEYR PDKEY1        LL_FLASH_DisableRunPowerDown\n
01447   *         FLASH_PDKEYR PDKEY2        LL_FLASH_DisableRunPowerDown
01448   * @retval None
01449   */
01450 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
01451 {
01452   /* Following values must be written consecutively to unlock the RUN_PD bit in
01453      FLASH_ACR */
01454   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
01455   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
01456   CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
01457 }
01458
01459 /**
01460   * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode
01461   * @note Flash must not be put in power-down while a program or an erase operation
01462   *       is on-going
01463   * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown
01464   * @retval None
01465   */
01466 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
01467 {
01468   SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
01469 }
01470
01471 /**
01472   * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode
01473   * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown
01474   * @retval None
01475   */
01476 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
01477 {
01478   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
01479 }
01480
01481 /**
01482   * @}
01483   */
01484
01485 /**
01486   * @}
01487   */
01488
01489 /**
01490   * @}
01491   */
01492
01493 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
01494
01495 /**
01496   * @}
01497   */
01498
01499 #ifdef __cplusplus
01500 }
01501 #endif
01502
01503 #endif /* __STM32L4xx_LL_SYSTEM_H */
01504
01505 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_tim.c Source File

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stm32l4xx_ll_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_tim.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   TIM LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_tim.h"
00041 #include "stm32l4xx_ll_bus.h"
00042
00043 #ifdef  USE_FULL_ASSERT
00044   #include "stm32_assert.h"
00045 #else
00046   #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
00054
00055 /** @addtogroup TIM_LL
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 /** @addtogroup TIM_LL_Private_Macros
00064   * @{
00065   */
00066 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
00067                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
00068                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
00069                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
00070                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
00071
00072 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
00073                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
00074                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
00075
00076 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
00077                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
00078                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
00079                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
00080                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
00081                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
00082                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
00083                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
00084                                   || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
00085                                   || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
00086                                   || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
00087                                   || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
00088                                   || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
00089                                   || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
00090
00091 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
00092                                    || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
00093
00094 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
00095                                       || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
00096
00097 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
00098                                        || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
00099
00100 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
00101                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
00102                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
00103
00104 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
00105                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
00106                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
00107                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
00108
00109 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
00110                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
00111                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
00112                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
00113                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
00114                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
00115                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
00116                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
00117                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
00118                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
00119                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
00120                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
00121                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
00122                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
00123                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
00124                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
00125
00126 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00127                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
00128                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
00129
00130 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
00131                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
00132                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
00133
00134 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00135                                                || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
00136 /**
00137   * @}
00138   */
00139
00140
00141 /* Private function prototypes -----------------------------------------------*/
00142 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
00143   * @{
00144   */
00145 static ErrorStatus OC1Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct);
00146 static ErrorStatus OC2Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct);
00147 static ErrorStatus OC3Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct);
00148 static ErrorStatus OC4Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct);
00149 static ErrorStatus OC5Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct);
00150 static ErrorStatus OC6Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct);
00151 static ErrorStatus IC1Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct);
00152 static ErrorStatus IC2Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct);
00153 static ErrorStatus IC3Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct);
00154 static ErrorStatus IC4Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct);
00155 /**
00156   * @}
00157   */
00158
00159 /* Exported functions --------------------------------------------------------*/
00160 /** @addtogroup TIM_LL_Exported_Functions
00161   * @{
00162   */
00163
00164 /** @addtogroup TIM_LL_EF_Init
00165   * @{
00166   */
00167
00168 /**
00169   * @brief  Set TIMx registers to their reset values.
00170   * @param  TIMx Timer instance
00171   * @retval An ErrorStatus enumeration value:
00172   *          - SUCCESS: TIMx registers are de-initialized
00173   *          - ERROR: invalid TIMx instance
00174   */
00175 ErrorStatus LL_TIM_DeInit(TIM_TypeDef* TIMx)
00176 {
00177   ErrorStatus result = SUCCESS;
00178
00179   /* Check the parameters */
00180   assert_param(IS_TIM_INSTANCE(TIMx));
00181
00182   if (TIMx == TIM1)
00183   {
00184     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
00185     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
00186   }
00187   else if (TIMx == TIM2)
00188   {
00189     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
00190     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
00191   }
00192 #if defined(TIM3)
00193   else if (TIMx == TIM3)
00194   {
00195     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
00196     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
00197   }
00198 #endif
00199 #if defined(TIM4)
00200   else if (TIMx == TIM4)
00201   {
00202     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
00203     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
00204   }
00205 #endif
00206 #if defined(TIM5)
00207   else if (TIMx == TIM5)
00208   {
00209     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
00210     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
00211   }
00212 #endif
00213   else if (TIMx == TIM6)
00214   {
00215     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
00216     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
00217   }
00218   else if (TIMx == TIM7)
00219   {
00220     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
00221     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
00222   }
00223 #if defined(TIM8)
00224   else if (TIMx == TIM8)
00225   {
00226     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
00227     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
00228   }
00229 #endif
00230   else if (TIMx == TIM15)
00231   {
00232     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
00233     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
00234   }
00235   else if (TIMx == TIM16)
00236   {
00237     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
00238     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
00239   }
00240 #if defined(TIM17)
00241   else if (TIMx == TIM17)
00242   {
00243     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
00244     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
00245   }
00246 #endif
00247   else
00248   {
00249     result = ERROR;
00250   }
00251
00252   return result;
00253 }
00254
00255 /**
00256   * @brief  Set the fields of the time base unit configuration data structure
00257   *         to their default values.
00258   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
00259   * @retval None
00260   */
00261 void LL_TIM_StructInit(LL_TIM_InitTypeDef* TIM_InitStruct)
00262 {
00263   /* Set the default configuration */
00264   TIM_InitStruct->Prescaler         = (uint16_t)0x0000U;
00265   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
00266   TIM_InitStruct->Autoreload        = (uint32_t)0xFFFFFFFFU;
00267   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
00268   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
00269 }
00270
00271 /**
00272   * @brief  Configure the TIMx time base unit.
00273   * @param  TIMx Timer Instance
00274   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
00275   * @retval An ErrorStatus enumeration value:
00276   *          - SUCCESS: TIMx registers are de-initialized
00277   *          - ERROR: not applicable
00278   */
00279 ErrorStatus LL_TIM_Init(TIM_TypeDef * TIMx, LL_TIM_InitTypeDef* TIM_InitStruct)
00280 {
00281   uint16_t tmpcr1 = 0U;
00282
00283   /* Check the parameters */
00284   assert_param(IS_TIM_INSTANCE(TIMx));
00285   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
00286   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
00287
00288   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
00289
00290   if(IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
00291   {
00292     /* Select the Counter Mode */
00293     tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
00294     tmpcr1 |= (uint32_t)TIM_InitStruct->CounterMode;
00295   }
00296
00297   if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
00298   {
00299     /* Set the clock division */
00300     tmpcr1 &=  (uint16_t)(~TIM_CR1_CKD);
00301     tmpcr1 |= (uint32_t)TIM_InitStruct->ClockDivision;
00302   }
00303
00304   /* Write to TIMx CR1 */
00305   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
00306
00307   /* Set the Autoreload value */
00308   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
00309
00310   /* Set the Prescaler value */
00311   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
00312
00313   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
00314   {
00315     /* Set the Repetition Counter value */
00316     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
00317   }
00318
00319   /* Generate an update event to reload the Prescaler
00320      and the repetition counter value (if applicable) immediately */
00321   LL_TIM_GenerateEvent_UPDATE(TIMx);
00322
00323   return SUCCESS;
00324 }
00325
00326 /**
00327   * @brief  Set the fields of the TIMx output channel configuration data
00328   *         structure to their default values.
00329   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
00330   * @retval None
00331   */
00332 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct)
00333 {
00334   /* Set the default configuration */
00335   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
00336   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
00337   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
00338   TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U;
00339   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
00340   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
00341   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
00342   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
00343 }
00344
00345 /**
00346   * @brief  Configure the TIMx output channel.
00347   * @param  TIMx Timer Instance
00348   * @param  Channel This parameter can be one of the following values:
00349   *         @arg @ref LL_TIM_CHANNEL_CH1
00350   *         @arg @ref LL_TIM_CHANNEL_CH2
00351   *         @arg @ref LL_TIM_CHANNEL_CH3
00352   *         @arg @ref LL_TIM_CHANNEL_CH4
00353   *         @arg @ref LL_TIM_CHANNEL_CH5
00354   *         @arg @ref LL_TIM_CHANNEL_CH6
00355   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
00356   * @retval An ErrorStatus enumeration value:
00357   *          - SUCCESS: TIMx output channel is initialized
00358   *          - ERROR: TIMx output channel is not initialized
00359   */
00360 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct)
00361 {
00362   ErrorStatus result = SUCCESS;
00363
00364   switch(Channel)
00365   {
00366   case LL_TIM_CHANNEL_CH1:
00367     result = OC1Config(TIMx, TIM_OC_InitStruct);
00368     break;
00369   case LL_TIM_CHANNEL_CH2:
00370     result = OC2Config(TIMx, TIM_OC_InitStruct);
00371     break;
00372   case LL_TIM_CHANNEL_CH3:
00373     result = OC3Config(TIMx, TIM_OC_InitStruct);
00374     break;
00375   case LL_TIM_CHANNEL_CH4:
00376     result = OC4Config(TIMx, TIM_OC_InitStruct);
00377     break;
00378   case LL_TIM_CHANNEL_CH5:
00379     result = OC5Config(TIMx, TIM_OC_InitStruct);
00380     break;
00381   case LL_TIM_CHANNEL_CH6:
00382     result = OC6Config(TIMx, TIM_OC_InitStruct);
00383     break;
00384   default:
00385     result = ERROR;
00386     break;
00387   }
00388
00389   return result;
00390 }
00391
00392 /**
00393   * @brief  Set the fields of the TIMx input channel configuration data
00394   *         structure to their default values.
00395   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
00396   * @retval None
00397   */
00398 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef* TIM_ICInitStruct)
00399 {
00400   /* Set the default configuration */
00401   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
00402   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00403   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
00404   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
00405 }
00406
00407 /**
00408   * @brief  Configure the TIMx input channel.
00409   * @param  TIMx Timer Instance
00410   * @param  Channel This parameter can be one of the following values:
00411   *         @arg @ref LL_TIM_CHANNEL_CH1
00412   *         @arg @ref LL_TIM_CHANNEL_CH2
00413   *         @arg @ref LL_TIM_CHANNEL_CH3
00414   *         @arg @ref LL_TIM_CHANNEL_CH4
00415   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
00416   * @retval An ErrorStatus enumeration value:
00417   *          - SUCCESS: TIMx output channel is initialized
00418   *          - ERROR: TIMx output channel is not initialized
00419   */
00420 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef* TIM_IC_InitStruct)
00421 {
00422   ErrorStatus result = SUCCESS;
00423
00424   switch(Channel)
00425   {
00426   case LL_TIM_CHANNEL_CH1:
00427     result = IC1Config(TIMx, TIM_IC_InitStruct);
00428     break;
00429   case LL_TIM_CHANNEL_CH2:
00430     result = IC2Config(TIMx, TIM_IC_InitStruct);
00431     break;
00432   case LL_TIM_CHANNEL_CH3:
00433     result = IC3Config(TIMx, TIM_IC_InitStruct);
00434     break;
00435   case LL_TIM_CHANNEL_CH4:
00436     result = IC4Config(TIMx, TIM_IC_InitStruct);
00437     break;
00438   default:
00439     result = ERROR;
00440     break;
00441   }
00442
00443   return result;
00444 }
00445
00446 /**
00447   * @brief  Fills each TIM_EncoderInitStruct field with its default value
00448   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
00449   * @retval None
00450   */
00451 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct)
00452 {
00453   /* Set the default configuration */
00454   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
00455   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
00456   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00457   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
00458   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
00459   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
00460   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00461   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
00462   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
00463 }
00464
00465 /**
00466   * @brief  Configure the encoder interface of the timer instance.
00467   * @param  TIMx Timer Instance
00468   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
00469   * @retval An ErrorStatus enumeration value:
00470   *          - SUCCESS: TIMx registers are de-initialized
00471   *          - ERROR: not applicable
00472   */
00473 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef* TIMx, LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct)
00474 {
00475   uint32_t tmpccmr1 = 0U;
00476   uint32_t tmpccer = 0U;
00477
00478   /* Check the parameters */
00479   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
00480   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
00481   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
00482   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
00483   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
00484   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
00485   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
00486   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
00487   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
00488   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
00489
00490   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00491   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00492
00493   /* Get the TIMx CCMR1 register value */
00494   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00495
00496   /* Get the TIMx CCER register value */
00497   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00498
00499   /* Configure TI1 */
00500   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00501   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
00502   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
00503   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
00504
00505   /* Configure TI2 */
00506   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
00507   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
00508   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
00509   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
00510
00511   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
00512   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00513   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
00514   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
00515   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00516
00517   /* Set encoder mode */
00518   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
00519
00520   /* Write to TIMx CCMR1 */
00521   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00522
00523   /* Write to TIMx CCER */
00524   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00525
00526   return SUCCESS;
00527 }
00528
00529 /**
00530   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
00531   *         structure to their default values.
00532   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
00533   * @retval None
00534   */
00535 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct)
00536 {
00537   /* Set the default configuration */
00538   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
00539   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
00540   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
00541   TIM_HallSensorInitStruct->CommutationDelay  = (uint32_t)0U;
00542 }
00543
00544 /**
00545   * @brief  Configure the Hall sensor interface of the timer instance.
00546   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
00547   *       to the TI1 input channel
00548   * @note TIMx slave mode controller is configured in reset mode.
00549           Selected internal trigger is TI1F_ED.
00550   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
00551   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
00552   *       between 2 changes on the inputs. It gives information about motor speed.
00553   * @note Channel 2 is configured in output PWM 2 mode.
00554   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
00555   * @note OC2REF is selected as trigger output on TRGO.
00556   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
00557   *       when TIMx operates in Hall sensor interface mode.
00558   * @param  TIMx Timer Instance
00559   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
00560   * @retval An ErrorStatus enumeration value:
00561   *          - SUCCESS: TIMx registers are de-initialized
00562   *          - ERROR: not applicable
00563   */
00564 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef* TIMx, LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct)
00565 {
00566   uint32_t tmpcr2 = 0U;
00567   uint32_t tmpccmr1 = 0U;
00568   uint32_t tmpccer = 0U;
00569   uint32_t tmpsmcr = 0U;
00570
00571   /* Check the parameters */
00572   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
00573   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
00574   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
00575   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
00576
00577   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00578   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00579
00580   /* Get the TIMx CR2 register value */
00581   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00582
00583   /* Get the TIMx CCMR1 register value */
00584   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00585
00586   /* Get the TIMx CCER register value */
00587   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00588
00589   /* Get the TIMx SMCR register value */
00590   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
00591
00592   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
00593   tmpcr2 |= TIM_CR2_TI1S;
00594
00595   /* OC2REF signal is used as trigger output (TRGO) */
00596   tmpcr2 |= LL_TIM_TRGO_OC2REF;
00597
00598   /* Configure the slave mode controller */
00599   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
00600   tmpsmcr |= LL_TIM_TS_TI1F_ED;
00601   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
00602
00603   /* Configure input channel 1 */
00604   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00605   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
00606   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
00607   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
00608
00609   /* Configure input channel 2 */
00610   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
00611   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
00612
00613   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
00614   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00615   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
00616   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00617
00618   /* Write to TIMx CR2 */
00619   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00620
00621   /* Write to TIMx SMCR */
00622   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
00623
00624   /* Write to TIMx CCMR1 */
00625   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00626
00627   /* Write to TIMx CCER */
00628   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00629
00630   /* Write to TIMx CCR2 */
00631   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
00632
00633   return SUCCESS;
00634 }
00635
00636 /**
00637   * @}
00638   */
00639
00640 /**
00641   * @}
00642   */
00643
00644 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
00645  *  @brief   Private functions
00646   * @{
00647   */
00648 /**
00649   * @brief  Configure the TIMx output channel 1.
00650   * @param  TIMx Timer Instance
00651   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
00652   * @retval An ErrorStatus enumeration value:
00653   *          - SUCCESS: TIMx registers are de-initialized
00654   *          - ERROR: not applicable
00655   */
00656 static ErrorStatus OC1Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct)
00657 {
00658   uint32_t tmpccmr1 = 0U;
00659   uint32_t tmpccer = 0U;
00660   uint32_t tmpcr2 = 0U;
00661
00662   /* Check the parameters */
00663   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
00664   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00665   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00666   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00667   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00668   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00669
00670   /* Disable the Channel 1: Reset the CC1E Bit */
00671   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
00672
00673   /* Get the TIMx CCER register value */
00674   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00675
00676   /* Get the TIMx CR2 register value */
00677   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00678
00679   /* Get the TIMx CCMR1 register value */
00680   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00681
00682   /* Reset Capture/Compare selection Bits */
00683   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
00684
00685   /* Set the Output Compare Mode */
00686   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
00687
00688   /* Set the Output Compare Polarity */
00689   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
00690
00691   /* Set the Output State */
00692   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
00693
00694   if(IS_TIM_BREAK_INSTANCE(TIMx))
00695   {
00696     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00697     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00698
00699     /* Set the complementary output Polarity */
00700     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
00701
00702     /* Set the complementary output State */
00703     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
00704
00705     /* Set the Output Idle state */
00706     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
00707
00708     /* Set the complementary output Idle state */
00709     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
00710   }
00711
00712   /* Write to TIMx CR2 */
00713   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00714
00715   /* Write to TIMx CCMR1 */
00716   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00717
00718   /* Set the Capture Compare Register value */
00719   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
00720
00721   /* Write to TIMx CCER */
00722   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00723
00724   return SUCCESS;
00725 }
00726
00727 /**
00728   * @brief  Configure the TIMx output channel 2.
00729   * @param  TIMx Timer Instance
00730   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
00731   * @retval An ErrorStatus enumeration value:
00732   *          - SUCCESS: TIMx registers are de-initialized
00733   *          - ERROR: not applicable
00734   */
00735 static ErrorStatus OC2Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct)
00736 {
00737   uint32_t tmpccmr1 = 0U;
00738   uint32_t tmpccer = 0U;
00739   uint32_t tmpcr2 = 0U;
00740
00741   /* Check the parameters */
00742   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
00743   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00744   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00745   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00746   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00747   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00748
00749   /* Disable the Channel 2: Reset the CC2E Bit */
00750   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
00751
00752   /* Get the TIMx CCER register value */
00753   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00754
00755   /* Get the TIMx CR2 register value */
00756   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00757
00758   /* Get the TIMx CCMR1 register value */
00759   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00760
00761   /* Reset Capture/Compare selection Bits */
00762   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
00763
00764   /* Select the Output Compare Mode */
00765   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
00766
00767   /* Set the Output Compare Polarity */
00768   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity<< 4U);
00769
00770   /* Set the Output State */
00771   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
00772
00773   if(IS_TIM_BREAK_INSTANCE(TIMx))
00774   {
00775     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00776     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00777
00778     /* Set the complementary output Polarity */
00779     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
00780
00781     /* Set the complementary output State */
00782     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
00783
00784     /* Set the Output Idle state */
00785     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
00786
00787     /* Set the complementary output Idle state */
00788     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
00789   }
00790
00791   /* Write to TIMx CR2 */
00792   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00793
00794   /* Write to TIMx CCMR1 */
00795   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00796
00797   /* Set the Capture Compare Register value */
00798   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
00799
00800   /* Write to TIMx CCER */
00801   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00802
00803   return SUCCESS;
00804 }
00805
00806 /**
00807   * @brief  Configure the TIMx output channel 3.
00808   * @param  TIMx Timer Instance
00809   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
00810   * @retval An ErrorStatus enumeration value:
00811   *          - SUCCESS: TIMx registers are de-initialized
00812   *          - ERROR: not applicable
00813   */
00814 static ErrorStatus OC3Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct)
00815 {
00816   uint32_t tmpccmr2 = 0U;
00817   uint32_t tmpccer = 0U;
00818   uint32_t tmpcr2 = 0U;
00819
00820   /* Check the parameters */
00821   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
00822   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00823   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00824   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00825   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00826   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00827
00828   /* Disable the Channel 3: Reset the CC3E Bit */
00829   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
00830
00831   /* Get the TIMx CCER register value */
00832   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00833
00834   /* Get the TIMx CR2 register value */
00835   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00836
00837   /* Get the TIMx CCMR2 register value */
00838   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
00839
00840   /* Reset Capture/Compare selection Bits */
00841   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
00842
00843   /* Select the Output Compare Mode */
00844   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
00845
00846   /* Set the Output Compare Polarity */
00847   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
00848
00849   /* Set the Output State */
00850   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
00851
00852   if(IS_TIM_BREAK_INSTANCE(TIMx))
00853   {
00854     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00855     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00856
00857     /* Set the complementary output Polarity */
00858     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
00859
00860     /* Set the complementary output State */
00861     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
00862
00863     /* Set the Output Idle state */
00864     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
00865
00866     /* Set the complementary output Idle state */
00867     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
00868   }
00869
00870   /* Write to TIMx CR2 */
00871   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00872
00873   /* Write to TIMx CCMR2 */
00874   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
00875
00876   /* Set the Capture Compare Register value */
00877   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
00878
00879   /* Write to TIMx CCER */
00880   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00881
00882   return SUCCESS;
00883 }
00884
00885 /**
00886   * @brief  Configure the TIMx output channel 4.
00887   * @param  TIMx Timer Instance
00888   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
00889   * @retval An ErrorStatus enumeration value:
00890   *          - SUCCESS: TIMx registers are de-initialized
00891   *          - ERROR: not applicable
00892   */
00893 static ErrorStatus OC4Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct)
00894 {
00895   uint32_t tmpccmr2 = 0U;
00896   uint32_t tmpccer = 0U;
00897   uint32_t tmpcr2 = 0U;
00898
00899   /* Check the parameters */
00900   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
00901   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00902   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00903   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00904   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00905   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00906
00907   /* Disable the Channel 4: Reset the CC4E Bit */
00908   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
00909
00910   /* Get the TIMx CCER register value */
00911   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00912
00913   /* Get the TIMx CR2 register value */
00914   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
00915
00916   /* Get the TIMx CCMR2 register value */
00917   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
00918
00919   /* Reset Capture/Compare selection Bits */
00920   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
00921
00922   /* Select the Output Compare Mode */
00923   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
00924
00925   /* Set the Output Compare Polarity */
00926   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
00927
00928   /* Set the Output State */
00929   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
00930
00931   if(IS_TIM_BREAK_INSTANCE(TIMx))
00932   {
00933     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00934     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00935
00936     /* Set the Output Idle state */
00937     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
00938   }
00939
00940   /* Write to TIMx CR2 */
00941   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00942
00943   /* Write to TIMx CCMR2 */
00944   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
00945
00946   /* Set the Capture Compare Register value */
00947   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
00948
00949   /* Write to TIMx CCER */
00950   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00951
00952   return SUCCESS;
00953 }
00954
00955 /**
00956   * @brief  Configure the TIMx output channel 5.
00957   * @param  TIMx Timer Instance
00958   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
00959   * @retval An ErrorStatus enumeration value:
00960   *          - SUCCESS: TIMx registers are de-initialized
00961   *          - ERROR: not applicable
00962   */
00963 static ErrorStatus OC5Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct)
00964 {
00965   uint32_t tmpccmr3 = 0U;
00966   uint32_t tmpccer = 0U;
00967
00968   /* Check the parameters */
00969   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
00970   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00971   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00972   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00973   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00974   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00975
00976   /* Disable the Channel 5: Reset the CC5E Bit */
00977   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
00978
00979   /* Get the TIMx CCER register value */
00980   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00981
00982   /* Get the TIMx CCMR3 register value */
00983   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
00984
00985   /* Select the Output Compare Mode */
00986   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
00987
00988   /* Set the Output Compare Polarity */
00989   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
00990
00991   /* Set the Output State */
00992   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
00993
00994   if(IS_TIM_BREAK_INSTANCE(TIMx))
00995   {
00996     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00997     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00998
00999     /* Set the Output Idle state */
01000     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
01001
01002   }
01003
01004   /* Write to TIMx CCMR3 */
01005   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01006
01007   /* Set the Capture Compare Register value */
01008   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
01009
01010   /* Write to TIMx CCER */
01011   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01012
01013   return SUCCESS;
01014 }
01015
01016 /**
01017   * @brief  Configure the TIMx output channel 6.
01018   * @param  TIMx Timer Instance
01019   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
01020   * @retval An ErrorStatus enumeration value:
01021   *          - SUCCESS: TIMx registers are de-initialized
01022   *          - ERROR: not applicable
01023   */
01024 static ErrorStatus OC6Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct)
01025 {
01026   uint32_t tmpccmr3 = 0U;
01027   uint32_t tmpccer = 0U;
01028
01029   /* Check the parameters */
01030   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
01031   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01032   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01033   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01034   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01035   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01036
01037   /* Disable the Channel 5: Reset the CC6E Bit */
01038   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
01039
01040   /* Get the TIMx CCER register value */
01041   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01042
01043   /* Get the TIMx CCMR3 register value */
01044   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01045
01046   /* Select the Output Compare Mode */
01047   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
01048
01049   /* Set the Output Compare Polarity */
01050   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
01051
01052   /* Set the Output State */
01053   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
01054
01055   if(IS_TIM_BREAK_INSTANCE(TIMx))
01056   {
01057     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01058     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01059
01060     /* Set the Output Idle state */
01061     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
01062   }
01063
01064   /* Write to TIMx CCMR3 */
01065   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01066
01067   /* Set the Capture Compare Register value */
01068   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
01069
01070   /* Write to TIMx CCER */
01071   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01072
01073   return SUCCESS;
01074 }
01075
01076 /**
01077   * @brief  Configure the TIMx input channel 1.
01078   * @param  TIMx Timer Instance
01079   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
01080   * @retval An ErrorStatus enumeration value:
01081   *          - SUCCESS: TIMx registers are de-initialized
01082   *          - ERROR: not applicable
01083   */
01084 static ErrorStatus IC1Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct)
01085 {
01086   /* Check the parameters */
01087   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
01088   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01089   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01090   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01091   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01092
01093   /* Disable the Channel 1: Reset the CC1E Bit */
01094   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
01095
01096   /* Select the Input and set the filter and the prescaler value */
01097   MODIFY_REG(TIMx->CCMR1,
01098              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
01099              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01100
01101   /* Select the Polarity and set the CC1E Bit */
01102   MODIFY_REG(TIMx->CCER,
01103              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
01104              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
01105
01106   return SUCCESS;
01107 }
01108
01109 /**
01110   * @brief  Configure the TIMx input channel 2.
01111   * @param  TIMx Timer Instance
01112   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
01113   * @retval An ErrorStatus enumeration value:
01114   *          - SUCCESS: TIMx registers are de-initialized
01115   *          - ERROR: not applicable
01116   */
01117 static ErrorStatus IC2Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct)
01118 {
01119   /* Check the parameters */
01120   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
01121   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01122   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01123   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01124   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01125
01126   /* Disable the Channel 2: Reset the CC2E Bit */
01127   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
01128
01129   /* Select the Input and set the filter and the prescaler value */
01130   MODIFY_REG(TIMx->CCMR1,
01131              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
01132              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01133
01134   /* Select the Polarity and set the CC2E Bit */
01135   MODIFY_REG(TIMx->CCER,
01136              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
01137              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E) );
01138
01139   return SUCCESS;
01140 }
01141
01142 /**
01143   * @brief  Configure the TIMx input channel 3.
01144   * @param  TIMx Timer Instance
01145   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
01146   * @retval An ErrorStatus enumeration value:
01147   *          - SUCCESS: TIMx registers are de-initialized
01148   *          - ERROR: not applicable
01149   */
01150 static ErrorStatus IC3Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct)
01151 {
01152   /* Check the parameters */
01153   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
01154   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01155   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01156   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01157   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01158
01159   /* Disable the Channel 3: Reset the CC3E Bit */
01160   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
01161
01162   /* Select the Input and set the filter and the prescaler value */
01163   MODIFY_REG(TIMx->CCMR2,
01164              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
01165              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01166
01167   /* Select the Polarity and set the CC3E Bit */
01168   MODIFY_REG(TIMx->CCER,
01169              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
01170              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E) );
01171
01172   return SUCCESS;
01173 }
01174
01175 /**
01176   * @brief  Configure the TIMx input channel 4.
01177   * @param  TIMx Timer Instance
01178   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
01179   * @retval An ErrorStatus enumeration value:
01180   *          - SUCCESS: TIMx registers are de-initialized
01181   *          - ERROR: not applicable
01182   */
01183 static ErrorStatus IC4Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct)
01184 {
01185   /* Check the parameters */
01186   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01187   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01188   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01189   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01190   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01191
01192   /* Disable the Channel 4: Reset the CC4E Bit */
01193   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
01194
01195   /* Select the Input and set the filter and the prescaler value */
01196   MODIFY_REG(TIMx->CCMR2,
01197              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
01198              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01199
01200   /* Select the Polarity and set the CC2E Bit */
01201   MODIFY_REG(TIMx->CCER,
01202              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
01203              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E) );
01204
01205   return SUCCESS;
01206 }
01207
01208
01209 /**
01210   * @}
01211   */
01212
01213 /**
01214   * @}
01215   */
01216
01217 #endif /* TIM1 || TIM8 || TIM2 || TIM3 ||  TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
01218
01219 /**
01220   * @}
01221   */
01222
01223 #endif /* USE_FULL_LL_DRIVER */
01224
01225 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_tim.h Source File

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stm32l4xx_ll_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_tim.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of TIM LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_TIM_H
00040 #define __STM32L4xx_LL_TIM_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
00054
00055 /** @defgroup TIM_LL TIM
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
00062   * @{
00063   */
00064 static const uint8_t OFFSET_TAB_CCMRx[] =
00065   {
00066     0x00U,   /* 0: TIMx_CH1  */
00067     0x00U,   /* 1: TIMx_CH1N */
00068     0x00U,   /* 2: TIMx_CH2  */
00069     0x00U,   /* 3: TIMx_CH2N */
00070     0x04U,   /* 4: TIMx_CH3  */
00071     0x04U,   /* 5: TIMx_CH3N */
00072     0x04U,   /* 6: TIMx_CH4  */
00073     0x3CU,   /* 7: TIMx_CH5  */
00074     0x3CU    /* 8: TIMx_CH6  */
00075   };
00076
00077 static const uint8_t SHIFT_TAB_OCxx[] =
00078 {
00079   0U,            /* 0: OC1M, OC1FE, OC1PE */
00080   0U,            /* 1: - NA */
00081   8U,            /* 2: OC2M, OC2FE, OC2PE */
00082   0U,            /* 3: - NA */
00083   0U,            /* 4: OC3M, OC3FE, OC3PE */
00084   0U,            /* 5: - NA */
00085   8U,            /* 6: OC4M, OC4FE, OC4PE */
00086   0U,            /* 7: OC5M, OC5FE, OC5PE */
00087   8U             /* 8: OC6M, OC6FE, OC6PE */
00088 };
00089
00090 static const uint8_t SHIFT_TAB_ICxx[] =
00091 {
00092   0U,            /* 0: CC1S, IC1PSC, IC1F */
00093   0U,            /* 1: - NA */
00094   8U,            /* 2: CC2S, IC2PSC, IC2F */
00095   0U,            /* 3: - NA */
00096   0U,            /* 4: CC3S, IC3PSC, IC3F */
00097   0U,            /* 5: - NA */
00098   8U,            /* 6: CC4S, IC4PSC, IC4F */
00099   0U,            /* 7: - NA */
00100   0U             /* 8: - NA */
00101 };
00102
00103 static const uint8_t SHIFT_TAB_CCxP[] =
00104 {
00105   0U,            /* 0: CC1P */
00106   2U,            /* 1: CC1NP */
00107   4U,            /* 2: CC2P */
00108   6U,            /* 3: CC2NP */
00109   8U,            /* 4: CC3P */
00110   10U,           /* 5: CC3NP */
00111   12U,           /* 6: CC4P */
00112   16U,           /* 7: CC5P */
00113   20U            /* 8: CC6P */
00114 };
00115
00116 static const uint8_t SHIFT_TAB_OISx[] =
00117 {
00118   0U,            /* 0: OIS1 */
00119   1U,            /* 1: OIS1N */
00120   2U,            /* 2: OIS2 */
00121   3U,            /* 3: OIS2N */
00122   4U,            /* 4: OIS3 */
00123   5U,            /* 5: OIS3N */
00124   6U,            /* 6: OIS4 */
00125   8U,            /* 7: OIS5 */
00126   10U            /* 8: OIS6 */
00127 };
00128 /**
00129   * @}
00130   */
00131
00132
00133 /* Private constants ---------------------------------------------------------*/
00134 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
00135   * @{
00136   */
00137 /** @defgroup TIM_LL_POSITION_VAL Bit Position Value
00138   * @brief    Position of the bit in the register.
00139   * @{
00140   */
00141 #define TIM_POSITION_ICPSC       POSITION_VAL(TIM_CCMR1_IC1PSC)
00142 /**
00143   * @}
00144   */
00145
00146 /* Generic bit definitions for TIMx_OR2 register */
00147 #define TIMx_OR2_BKINE     TIM1_OR2_BKINE     /*!< BRK BKIN input enable */
00148 #define TIMx_OR2_BKCOMP1E  TIM1_OR2_BKCMP1E   /*!< BRK COMP1 enable */
00149 #define TIMx_OR2_BKCOMP2E  TIM1_OR2_BKCMP2E   /*!< BRK COMP2 enable */
00150 #if defined(DFSDM1_Channel0)
00151 #define TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E /*!< BRK DFSDM1_BREAK[0] enable */
00152 #endif /* DFSDM1_Channel0 */
00153 #define TIMx_OR2_BKINP     TIM1_OR2_BKINP     /*!< BRK BKIN input polarity */
00154 #define TIMx_OR2_BKCOMP1P  TIM1_OR2_BKCMP1P   /*!< BRK COMP1 input polarity */
00155 #define TIMx_OR2_BKCOMP2P  TIM1_OR2_BKCMP2P   /*!< BRK COMP2 input polarity */
00156 #define TIMx_OR2_ETRSEL    TIM1_OR2_ETRSEL    /*!< TIMx ETR source selection */
00157
00158 /* Generic bit definitions for TIMx_OR3 register */
00159 #define TIMx_OR3_BK2INE    TIM1_OR3_BK2INE     /*!< BRK2 BKIN2 input enable */
00160 #define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E   /*!< BRK2 COMP1 enable */
00161 #define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E   /*!< BRK2 COMP2 enable */
00162 #if defined(DFSDM1_Channel0)
00163 #define TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E /*!< BRK2 DFSDM1_BREAK[1] enable */
00164 #endif /* DFSDM1_Channel0 */
00165 #define TIMx_OR3_BK2INP    TIM1_OR3_BK2INP     /*!< BRK2 BKIN2 input polarity */
00166 #define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P   /*!< BRK2 COMP1 input polarity */
00167 #define TIMx_OR3_BK2COMP2P  TIM1_OR3_BK2CMP2P  /*!< BRK2 COMP2 input polarity */
00168
00169 /* Remap mask definitions */
00170 #define TIMx_OR1_RMP_SHIFT ((uint32_t)16U)
00171 #define TIMx_OR1_RMP_MASK  ((uint32_t)0x0000FFFFU)
00172 #if defined(ADC3)
00173 #define TIM1_OR1_RMP_MASK  ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00174 #else
00175 #define TIM1_OR1_RMP_MASK  ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00176 #endif /* ADC3 */
00177 #define TIM2_OR1_RMP_MASK  ((uint32_t)((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT))
00178 #define TIM3_OR1_RMP_MASK  ((uint32_t)(TIM3_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
00179 #define TIM8_OR1_RMP_MASK  ((uint32_t)((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00180 #define TIM15_OR1_RMP_MASK ((uint32_t)((TIM15_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00181 #define TIM16_OR1_RMP_MASK ((uint32_t)((TIM16_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00182 #define TIM17_OR1_RMP_MASK ((uint32_t)((TIM17_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
00183
00184 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
00185 #define DT_DELAY_1 ((uint8_t)0x7FU)
00186 #define DT_DELAY_2 ((uint8_t)0x3FU)
00187 #define DT_DELAY_3 ((uint8_t)0x1FU)
00188 #define DT_DELAY_4 ((uint8_t)0x1FU)
00189
00190 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
00191 #define DT_RANGE_1 ((uint8_t)0x00U)
00192 #define DT_RANGE_2 ((uint8_t)0x80U)
00193 #define DT_RANGE_3 ((uint8_t)0xC0U)
00194 #define DT_RANGE_4 ((uint8_t)0xE0U)
00195
00196 /** Legacy definitions for compatibility purpose
00197 @cond 0
00198 */
00199 #if defined(DFSDM1_Channel0)
00200 #define TIMx_OR2_BKDFBK0E   TIMx_OR2_BKDF1BK0E
00201 #define TIMx_OR3_BK2DFBK1E  TIMx_OR3_BK2DF1BK1E
00202 #endif /* DFSDM1_Channel0 */
00203 /**
00204 @endcond
00205   */
00206
00207 /**
00208   * @}
00209   */
00210
00211
00212 /* Private macros ------------------------------------------------------------*/
00213 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
00214   * @{
00215   */
00216 /** @brief  Convert channel id into channel index.
00217   * @param  __CHANNEL__ This parameter can be one of the following values:
00218   *         @arg @ref LL_TIM_CHANNEL_CH1
00219   *         @arg @ref LL_TIM_CHANNEL_CH1N
00220   *         @arg @ref LL_TIM_CHANNEL_CH2
00221   *         @arg @ref LL_TIM_CHANNEL_CH2N
00222   *         @arg @ref LL_TIM_CHANNEL_CH3
00223   *         @arg @ref LL_TIM_CHANNEL_CH3N
00224   *         @arg @ref LL_TIM_CHANNEL_CH4
00225   *         @arg @ref LL_TIM_CHANNEL_CH5
00226   *         @arg @ref LL_TIM_CHANNEL_CH6
00227   * @retval none
00228   */
00229 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
00230 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
00231 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
00232 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
00233 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
00234 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
00235 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
00236 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
00237 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
00238
00239 /** @brief  Calculate the deadtime sampling period(in ps).
00240   * @param  __TIMCLK__ timer input clock frequency (in Hz).
00241   * @param  __CKD__ This parameter can be one of the following values:
00242   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00243   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00244   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00245   * @retval none
00246   */
00247 #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
00248     (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
00249      ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
00250      ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
00251 /**
00252   * @}
00253   */
00254
00255
00256 /* Exported types ------------------------------------------------------------*/
00257 #if defined(USE_FULL_LL_DRIVER)
00258 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
00259   * @{
00260   */
00261
00262 /**
00263   * @brief  TIM Time Base configuration structure definition.
00264   */
00265 typedef struct
00266 {
00267   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00268                                    This parameter can be a number between 0x0000 and 0xFFFF.
00269
00270                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
00271
00272   uint32_t CounterMode;       /*!< Specifies the counter mode.
00273                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
00274
00275                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
00276
00277   uint32_t Autoreload;       /*!< Specifies the auto reload value to be loaded into the active
00278                                    Auto-Reload Register at the next update event.
00279                                    This parameter must be a number between 0x0000 and 0xFFFF.
00280                                    Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
00281
00282                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
00283
00284   uint32_t ClockDivision;     /*!< Specifies the clock division.
00285                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
00286
00287                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
00288
00289   uint8_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00290                                    reaches zero, an update event is generated and counting restarts
00291                                    from the RCR value (N).
00292                                    This means in PWM mode that (N+1) corresponds to:
00293                                       - the number of PWM periods in edge-aligned mode
00294                                       - the number of half PWM period in center-aligned mode
00295                                    This parameter must be a number between 0x00 and 0xFF.
00296
00297                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
00298 } LL_TIM_InitTypeDef;
00299
00300 /**
00301   * @brief  TIM Output Compare configuration structure definition.
00302   */
00303 typedef struct
00304 {
00305   uint32_t OCMode;        /*!< Specifies the output mode.
00306                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
00307
00308                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
00309
00310   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
00311                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00312
00313                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00314
00315   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
00316                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00317
00318                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00319
00320   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
00321                                This parameter can be a number between 0x0000 and 0xFFFF.
00322
00323                                This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
00324
00325   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00326                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00327
00328                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00329
00330   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00331                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00332
00333                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00334
00335   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00336                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00337
00338                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00339
00340   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00341                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00342
00343                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00344 } LL_TIM_OC_InitTypeDef;
00345
00346 /**
00347   * @brief  TIM Input Capture configuration structure definition.
00348   */
00349
00350 typedef struct
00351 {
00352
00353   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00354                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00355
00356                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00357
00358   uint32_t ICActiveInput; /*!< Specifies the input.
00359                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00360
00361                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00362
00363   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
00364                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00365
00366                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00367
00368   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00369                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00370
00371                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00372 } LL_TIM_IC_InitTypeDef;
00373
00374
00375 /**
00376   * @brief  TIM Encoder interface configuration structure definition.
00377   */
00378 typedef struct
00379 {
00380   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
00381                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
00382
00383                                  This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
00384
00385   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
00386                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00387
00388                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00389
00390   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
00391                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00392
00393                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00394
00395   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
00396                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00397
00398                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00399
00400   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
00401                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00402
00403                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00404
00405   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
00406                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00407
00408                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00409
00410   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
00411                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00412
00413                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00414
00415   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
00416                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00417
00418                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00419
00420   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
00421                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00422
00423                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00424
00425 } LL_TIM_ENCODER_InitTypeDef;
00426
00427 /**
00428   * @brief  TIM Hall sensor interface configuration structure definition.
00429   */
00430 typedef struct
00431 {
00432
00433   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
00434                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00435
00436                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00437
00438   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
00439                                     Prescaler must be set to get a maximum counter period longer than the
00440                                     time interval between 2 consecutive changes on the Hall inputs.
00441                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00442
00443                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00444
00445   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
00446                                     This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00447
00448                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00449
00450   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
00451                                     A positive pulse (TRGO event) is generated with a programmable delay every time
00452                                     a change occurs on the Hall inputs.
00453                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
00454
00455                                     This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
00456 } LL_TIM_HALLSENSOR_InitTypeDef;
00457
00458 /**
00459   * @}
00460   */
00461 #endif /* USE_FULL_LL_DRIVER */
00462
00463 /* Exported constants --------------------------------------------------------*/
00464 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
00465   * @{
00466   */
00467
00468 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
00469   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
00470   * @{
00471   */
00472 #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
00473 #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
00474 #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
00475 #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
00476 #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
00477 #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
00478 #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
00479 #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
00480 #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
00481 #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
00482 #define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
00483 #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
00484 #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
00485 #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
00486 #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
00487 #define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
00488 /**
00489   * @}
00490   */
00491
00492 /** @defgroup TIM_LL_EC_IT IT Defines
00493   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
00494   * @{
00495   */
00496 #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
00497 #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
00498 #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
00499 #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
00500 #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
00501 #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
00502 #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
00503 #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
00504 /**
00505   * @}
00506   */
00507
00508 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
00509   * @{
00510   */
00511 #define LL_TIM_UPDATESOURCE_REGULAR            ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
00512 #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS            /*!< Only counter overflow/underflow generates an update request */
00513 /**
00514   * @}
00515   */
00516
00517 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
00518   * @{
00519   */
00520 #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM            /*!< Counter is not stopped at update event */
00521 #define LL_TIM_ONEPULSEMODE_REPETITIVE         ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */
00522 /**
00523   * @}
00524   */
00525
00526 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
00527   * @{
00528   */
00529 #define LL_TIM_COUNTERMODE_UP                  ((uint32_t)0x00000000U) /*!<Counter used as upcounter */
00530 #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR             /*!< Counter used as downcounter */
00531 #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0           /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
00532 #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1           /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
00533 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS             /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
00534 /**
00535   * @}
00536   */
00537
00538 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
00539   * @{
00540   */
00541 #define LL_TIM_CLOCKDIVISION_DIV1              ((uint32_t)0x00000000U) /*!< tDTS=tCK_INT */
00542 #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0           /*!< tDTS=2*tCK_INT */
00543 #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1           /*!< tDTS=4*tCK_INT */
00544 /**
00545   * @}
00546   */
00547
00548 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
00549   * @{
00550   */
00551 #define LL_TIM_COUNTERDIRECTION_UP             ((uint32_t)0x00000000U) /*!< Timer counter counts up */
00552 #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR             /*!< Timer counter counts down */
00553 /**
00554   * @}
00555   */
00556
00557 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
00558   * @{
00559   */
00560 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        ((uint32_t)0x00000000U) /*!< Capture/compare control bits are updated by setting the COMG bit only */
00561 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS            /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
00562 /**
00563   * @}
00564   */
00565
00566 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
00567   * @{
00568   */
00569 #define LL_TIM_CCDMAREQUEST_CC                 ((uint32_t)0x00000000U) /*!< CCx DMA request sent when CCx event occurs */
00570 #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS            /*!< CCx DMA requests sent when update event occurs */
00571 /**
00572   * @}
00573   */
00574
00575 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
00576   * @{
00577   */
00578 #define LL_TIM_LOCKLEVEL_OFF                   ((uint32_t)0x00000000U) /*!< LOCK OFF - No bit is write protected */
00579 #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0         /*!< LOCK Level 1 */
00580 #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1         /*!< LOCK Level 2 */
00581 #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK           /*!< LOCK Level 3 */
00582 /**
00583   * @}
00584   */
00585
00586 /** @defgroup TIM_LL_EC_CHANNEL Channel
00587   * @{
00588   */
00589 #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
00590 #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
00591 #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
00592 #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
00593 #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
00594 #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
00595 #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
00596 #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
00597 #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
00598 /**
00599   * @}
00600   */
00601
00602 #if defined(USE_FULL_LL_DRIVER)
00603 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
00604   * @{
00605   */
00606 #define LL_TIM_OCSTATE_DISABLE                 ((uint32_t)0x00000000U) /*!< OCx is not active */
00607 #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
00608 /**
00609   * @}
00610   */
00611 #endif /* USE_FULL_LL_DRIVER */
00612
00613 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
00614   * @{
00615   */
00616 #define LL_TIM_OCMODE_FROZEN                   ((uint32_t)0x00000000U)                                  /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
00617 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
00618 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
00619 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
00620 #define LL_TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)                                       /*!<OCyREF is forced low*/
00621 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
00622 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
00623 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
00624 #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
00625 #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
00626 #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
00627 #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
00628 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
00629 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
00630 /**
00631   * @}
00632   */
00633
00634 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
00635   * @{
00636   */
00637 #define LL_TIM_OCPOLARITY_HIGH                 ((uint32_t)0x00000000U)     /*!< OCxactive high*/
00638 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
00639 /**
00640   * @}
00641   */
00642
00643 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
00644   * @{
00645   */
00646 #define LL_TIM_OCIDLESTATE_LOW                 ((uint32_t)0x00000000U) /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
00647 #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
00648 /**
00649   * @}
00650   */
00651
00652 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
00653   * @{
00654   */
00655 #define LL_TIM_GROUPCH5_NONE                   (uint32_t)0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00656 #define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
00657 #define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
00658 #define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
00659 /**
00660   * @}
00661   */
00662
00663 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
00664   * @{
00665   */
00666 #define LL_TIM_ACTIVEINPUT_DIRECTTI            (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
00667 #define LL_TIM_ACTIVEINPUT_INDIRECTTI          (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
00668 #define LL_TIM_ACTIVEINPUT_TRC                 (uint32_t)(TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
00669 /**
00670   * @}
00671   */
00672
00673 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
00674   * @{
00675   */
00676 #define LL_TIM_ICPSC_DIV1                      ((uint32_t)0x00000000U) /*!< No prescaler, capture is done each time an edge is detected on the capture input */
00677 #define LL_TIM_ICPSC_DIV2                      (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
00678 #define LL_TIM_ICPSC_DIV4                      (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
00679 #define LL_TIM_ICPSC_DIV8                      (uint32_t)(TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
00680 /**
00681   * @}
00682   */
00683
00684 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
00685   * @{
00686   */
00687 #define LL_TIM_IC_FILTER_FDIV1                 ((uint32_t)0x00000000U)                                         /*!< No filter, sampling is done at fDTS */
00688 #define LL_TIM_IC_FILTER_FDIV1_N2              (uint32_t)(TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
00689 #define LL_TIM_IC_FILTER_FDIV1_N4              (uint32_t)(TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
00690 #define LL_TIM_IC_FILTER_FDIV1_N8              (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
00691 #define LL_TIM_IC_FILTER_FDIV2_N6              (uint32_t)(TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
00692 #define LL_TIM_IC_FILTER_FDIV2_N8              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
00693 #define LL_TIM_IC_FILTER_FDIV4_N6              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
00694 #define LL_TIM_IC_FILTER_FDIV4_N8              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
00695 #define LL_TIM_IC_FILTER_FDIV8_N6              (uint32_t)(TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
00696 #define LL_TIM_IC_FILTER_FDIV8_N8              (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
00697 #define LL_TIM_IC_FILTER_FDIV16_N5             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
00698 #define LL_TIM_IC_FILTER_FDIV16_N6             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
00699 #define LL_TIM_IC_FILTER_FDIV16_N8             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
00700 #define LL_TIM_IC_FILTER_FDIV32_N5             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
00701 #define LL_TIM_IC_FILTER_FDIV32_N6             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
00702 #define LL_TIM_IC_FILTER_FDIV32_N8             (uint32_t)(TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
00703 /**
00704   * @}
00705   */
00706
00707 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
00708   * @{
00709   */
00710 #define LL_TIM_IC_POLARITY_RISING              ((uint32_t)0x00000000U)          /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
00711 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
00712 #define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
00713 /**
00714   * @}
00715   */
00716
00717 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
00718   * @{
00719   */
00720 #define LL_TIM_CLOCKSOURCE_INTERNAL            ((uint32_t)0x00000000U)                              /*!< The timer is clocked by the internal clock provided from the RCC */
00721 #define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
00722 #define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                        /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
00723 /**
00724   * @}
00725   */
00726
00727 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
00728   * @{
00729   */
00730 #define LL_TIM_ENCODERMODE_X2_TI1              TIM_SMCR_SMS_0                    /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
00731 #define LL_TIM_ENCODERMODE_X2_TI2              TIM_SMCR_SMS_1                    /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
00732 #define LL_TIM_ENCODERMODE_X4_TI12             (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges                                                                                                                                                                   depending on the level of the other input l */
00733 /**
00734   * @}
00735   */
00736
00737 /** @defgroup TIM_LL_EC_TRGO Trigger Output
00738   * @{
00739   */
00740 #define LL_TIM_TRGO_RESET                      ((uint32_t)0x00000000U)                         /*!< UG bit from the TIMx_EGR register is used as trigger output */
00741 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
00742 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
00743 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
00744 #define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
00745 #define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
00746 #define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
00747 #define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
00748 /**
00749   * @}
00750   */
00751
00752 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
00753   * @{
00754   */
00755 #define LL_TIM_TRGO2_RESET                     ((uint32_t)0x00000000U)                                             /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
00756 #define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
00757 #define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
00758 #define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
00759 #define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
00760 #define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
00761 #define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
00762 #define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
00763 #define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
00764 #define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
00765 #define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
00766 #define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
00767 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
00768 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
00769 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
00770 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
00771 /**
00772   * @}
00773   */
00774
00775 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
00776   * @{
00777   */
00778 #define LL_TIM_SLAVEMODE_DISABLED              ((uint32_t)0x00000000U)             /*!< Slave mode disabled */
00779 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
00780 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
00781 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
00782 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
00783 /**
00784   * @}
00785   */
00786
00787 /** @defgroup TIM_LL_EC_TS Trigger Selection
00788   * @{
00789   */
00790 #define LL_TIM_TS_ITR0                         ((uint32_t)0x00000000U)         /*!< Internal Trigger 0 (ITR0) is used as trigger input */
00791 #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
00792 #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
00793 #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
00794 #define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
00795 #define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
00796 #define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
00797 #define LL_TIM_TS_ETRF                         TIM_SMCR_TS                     /*!< Filtered external Trigger (ETRF) is used as trigger input */
00798 /**
00799   * @}
00800   */
00801
00802 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
00803   * @{
00804   */
00805 #define LL_TIM_ETR_POLARITY_NONINVERTED        ((uint32_t)0x00000000U) /*!< ETR is non-inverted, active at high level or rising edge */
00806 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
00807 /**
00808   * @}
00809   */
00810
00811 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
00812   * @{
00813   */
00814 #define LL_TIM_ETR_PRESCALER_DIV1              ((uint32_t)0x00000000U) /*!< ETR prescaler OFF */
00815 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
00816 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
00817 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
00818 /**
00819   * @}
00820   */
00821
00822 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
00823   * @{
00824   */
00825 #define LL_TIM_ETR_FILTER_FDIV1                ((uint32_t)0x00000000U)                              /*!< No filter, sampling is done at fDTS */
00826 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
00827 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
00828 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
00829 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
00830 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
00831 #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 )                   /*!< fSAMPLING=fDTS/4, N=6 */
00832 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
00833 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
00834 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
00835 #define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 )                   /*!< fSAMPLING=fDTS/16, N=6 */
00836 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
00837 #define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 )                   /*!< fSAMPLING=fDTS/16, N=5 */
00838 #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2  | TIM_SMCR_ETF_0)  /*!< fSAMPLING=fDTS/32, N=5 */
00839 #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2  | TIM_SMCR_ETF_1)  /*!< fSAMPLING=fDTS/32, N=6 */
00840 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
00841 /**
00842   * @}
00843   */
00844
00845 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
00846   * @{
00847   */
00848 #define LL_TIM_ETRSOURCE_LEGACY                ((uint32_t)(0x00000000U)) /*!< ETR legacy mode */
00849 #define LL_TIM_ETRSOURCE_COMP1                 TIM1_OR2_ETRSEL_0         /*!< COMP1 output connected to ETR input */
00850 #define LL_TIM_ETRSOURCE_COMP2                 TIM1_OR2_ETRSEL_1         /*!< COMP2 output connected to ETR input */
00851 /**
00852   * @}
00853   */
00854
00855 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
00856   * @{
00857   */
00858 #define LL_TIM_BREAK_POLARITY_LOW              ((uint32_t)0x00000000U)   /*!< Break input BRK is active low */
00859 #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
00860 /**
00861   * @}
00862   */
00863
00864 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
00865   * @{
00866   */
00867 #define LL_TIM_BREAK_FILTER_FDIV1              ((uint32_t)0x00000000U)   /*!< No filter, BRK acts asynchronously */
00868 #define LL_TIM_BREAK_FILTER_FDIV1_N2           ((uint32_t)0x00010000U)   /*!< fSAMPLING=fCK_INT, N=2 */
00869 #define LL_TIM_BREAK_FILTER_FDIV1_N4           ((uint32_t)0x00020000U)   /*!< fSAMPLING=fCK_INT, N=4 */
00870 #define LL_TIM_BREAK_FILTER_FDIV1_N8           ((uint32_t)0x00030000U)   /*!< fSAMPLING=fCK_INT, N=8 */
00871 #define LL_TIM_BREAK_FILTER_FDIV2_N6           ((uint32_t)0x00040000U)   /*!< fSAMPLING=fDTS/2, N=6 */
00872 #define LL_TIM_BREAK_FILTER_FDIV2_N8           ((uint32_t)0x00050000U)   /*!< fSAMPLING=fDTS/2, N=8 */
00873 #define LL_TIM_BREAK_FILTER_FDIV4_N6           ((uint32_t)0x00060000U)   /*!< fSAMPLING=fDTS/4, N=6 */
00874 #define LL_TIM_BREAK_FILTER_FDIV4_N8           ((uint32_t)0x00070000U)   /*!< fSAMPLING=fDTS/4, N=8 */
00875 #define LL_TIM_BREAK_FILTER_FDIV8_N6           ((uint32_t)0x00080000U)   /*!< fSAMPLING=fDTS/8, N=6 */
00876 #define LL_TIM_BREAK_FILTER_FDIV8_N8           ((uint32_t)0x00090000U)   /*!< fSAMPLING=fDTS/8, N=8 */
00877 #define LL_TIM_BREAK_FILTER_FDIV16_N5          ((uint32_t)0x000A0000U)   /*!< fSAMPLING=fDTS/16, N=5 */
00878 #define LL_TIM_BREAK_FILTER_FDIV16_N6          ((uint32_t)0x000B0000U)   /*!< fSAMPLING=fDTS/16, N=6 */
00879 #define LL_TIM_BREAK_FILTER_FDIV16_N8          ((uint32_t)0x000C0000U)   /*!< fSAMPLING=fDTS/16, N=8 */
00880 #define LL_TIM_BREAK_FILTER_FDIV32_N5          ((uint32_t)0x000D0000U)   /*!< fSAMPLING=fDTS/32, N=5 */
00881 #define LL_TIM_BREAK_FILTER_FDIV32_N6          ((uint32_t)0x000E0000U)   /*!< fSAMPLING=fDTS/32, N=6 */
00882 #define LL_TIM_BREAK_FILTER_FDIV32_N8          ((uint32_t)0x000F0000U)   /*!< fSAMPLING=fDTS/32, N=8 */
00883 /**
00884   * @}
00885   */
00886
00887 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
00888   * @{
00889   */
00890 #define LL_TIM_BREAK2_POLARITY_LOW             ((uint32_t)0x00000000U) /*!< Break input BRK2 is active low */
00891 #define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
00892 /**
00893   * @}
00894   */
00895
00896 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
00897   * @{
00898   */
00899 #define LL_TIM_BREAK2_FILTER_FDIV1             ((uint32_t)0x00000000U)   /*!< No filter, BRK acts asynchronously */
00900 #define LL_TIM_BREAK2_FILTER_FDIV1_N2          ((uint32_t)0x00100000U)   /*!< fSAMPLING=fCK_INT, N=2 */
00901 #define LL_TIM_BREAK2_FILTER_FDIV1_N4          ((uint32_t)0x00200000U)   /*!< fSAMPLING=fCK_INT, N=4 */
00902 #define LL_TIM_BREAK2_FILTER_FDIV1_N8          ((uint32_t)0x00300000U)   /*!< fSAMPLING=fCK_INT, N=8 */
00903 #define LL_TIM_BREAK2_FILTER_FDIV2_N6          ((uint32_t)0x00400000U)   /*!< fSAMPLING=fDTS/2, N=6 */
00904 #define LL_TIM_BREAK2_FILTER_FDIV2_N8          ((uint32_t)0x00500000U)   /*!< fSAMPLING=fDTS/2, N=8 */
00905 #define LL_TIM_BREAK2_FILTER_FDIV4_N6          ((uint32_t)0x00600000U)   /*!< fSAMPLING=fDTS/4, N=6 */
00906 #define LL_TIM_BREAK2_FILTER_FDIV4_N8          ((uint32_t)0x00700000U)   /*!< fSAMPLING=fDTS/4, N=8 */
00907 #define LL_TIM_BREAK2_FILTER_FDIV8_N6          ((uint32_t)0x00800000U)   /*!< fSAMPLING=fDTS/8, N=6 */
00908 #define LL_TIM_BREAK2_FILTER_FDIV8_N8          ((uint32_t)0x00900000U)   /*!< fSAMPLING=fDTS/8, N=8 */
00909 #define LL_TIM_BREAK2_FILTER_FDIV16_N5         ((uint32_t)0x00A00000U)   /*!< fSAMPLING=fDTS/16, N=5 */
00910 #define LL_TIM_BREAK2_FILTER_FDIV16_N6         ((uint32_t)0x00B00000U)   /*!< fSAMPLING=fDTS/16, N=6 */
00911 #define LL_TIM_BREAK2_FILTER_FDIV16_N8         ((uint32_t)0x00C00000U)   /*!< fSAMPLING=fDTS/16, N=8 */
00912 #define LL_TIM_BREAK2_FILTER_FDIV32_N5         ((uint32_t)0x00D00000U)   /*!< fSAMPLING=fDTS/32, N=5 */
00913 #define LL_TIM_BREAK2_FILTER_FDIV32_N6         ((uint32_t)0x00E00000U)   /*!< fSAMPLING=fDTS/32, N=6 */
00914 #define LL_TIM_BREAK2_FILTER_FDIV32_N8         ((uint32_t)0x00F00000U)   /*!< fSAMPLING=fDTS/32, N=8 */
00915 /**
00916   * @}
00917   */
00918
00919 /** @defgroup TIM_LL_EC_OSSI OSSI
00920   * @{
00921   */
00922 #define LL_TIM_OSSI_DISABLE                    ((uint32_t)0x00000000U) /*!< When inactive, OCx/OCxN outputs are disabled */
00923 #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
00924 /**
00925   * @}
00926   */
00927
00928 /** @defgroup TIM_LL_EC_OSSR OSSR
00929   * @{
00930   */
00931 #define LL_TIM_OSSR_DISABLE                    ((uint32_t)0x00000000U) /*!< When inactive, OCx/OCxN outputs are disabled */
00932 #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
00933 /**
00934   * @}
00935   */
00936
00937 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
00938   * @{
00939   */
00940 #define LL_TIM_BREAK_INPUT_BKIN                ((uint32_t)0x00000000U)  /*!< TIMx_BKIN input */
00941 #define LL_TIM_BREAK_INPUT_BKIN2               ((uint32_t)0x00000004U)  /*!< TIMx_BKIN2 input */
00942 /**
00943   * @}
00944   */
00945
00946 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
00947   * @{
00948   */
00949 #define LL_TIM_BKIN_SOURCE_BKIN                TIM1_OR2_BKINE     /*!< BKIN input from AF controller */
00950 #define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_OR2_BKCMP1E   /*!< internal signal: COMP1 output */
00951 #define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_OR2_BKCMP2E   /*!< internal signal: COMP2 output */
00952 #define LL_TIM_BKIN_SOURCE_DF1BK               TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
00953 /**
00954   * @}
00955   */
00956
00957 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
00958   * @{
00959   */
00960 #define LL_TIM_BKIN_POLARITY_LOW               ((uint32_t)0x00000000U) /*!< BRK BKIN input is active low */
00961 #define LL_TIM_BKIN_POLARITY_HIGH              TIM1_OR2_BKINP          /*!< BRK BKIN input is active high */
00962 /**
00963   * @}
00964   */
00965
00966 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
00967   * @{
00968   */
00969 #define LL_TIM_DMABURST_BASEADDR_CR1           ((uint32_t)0x00000000U)                                          /*!< TIMx_CR1 register is the DMA base address for DMA burst */                                                                                    /*!< TIMx_CR1 register is the DMA base address for DMA burst */
00970 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
00971 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
00972 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
00973 #define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
00974 #define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
00975 #define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
00976 #define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
00977 #define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
00978 #define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
00979 #define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
00980 #define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
00981 #define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
00982 #define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
00983 #define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
00984 #define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
00985 #define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
00986 #define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
00987 #define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
00988 #define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
00989 #define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
00990 #define LL_TIM_DMABURST_BASEADDR_OR1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_OR1 register is the DMA base address for DMA burst */
00991 #define LL_TIM_DMABURST_BASEADDR_OR2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_OR2 register is the DMA base address for DMA burst */
00992 #define LL_TIM_DMABURST_BASEADDR_OR3           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_OR3 register is the DMA base address for DMA burst */
00993 /**
00994   * @}
00995   */
00996
00997 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
00998   * @{
00999   */
01000 #define LL_TIM_DMABURST_LENGTH_1TRANSFER       ((uint32_t)0x00000000U)                                         /*!< Transfer is done to 1 register starting from the DMA burst base address */
01001 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
01002 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
01003 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
01004 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
01005 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
01006 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
01007 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
01008 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
01009 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
01010 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
01011 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
01012 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
01013 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
01014 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
01015 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
01016 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
01017 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
01018 /**
01019   * @}
01020   */
01021
01022 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP  TIM1 External Trigger ADC1 Remap
01023 * @{
01024 */
01025 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC   ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)   /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
01026 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
01027 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
01028 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK)   /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
01029 /**
01030   * @}
01031   */
01032
01033 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP  TIM1 External Trigger ADC3 Remap
01034 * @{
01035 */
01036 #define LL_TIM_TIM1_ETR_ADC3_RMP_NC   ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK)   /*!< TIM1_ETR is not connected to ADC3 analog watchdog  x*/
01037 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 1 */
01038 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 2 */
01039 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK)   /*!< TIM1_ETR is connected to ADC3 analog watchdog 3 */
01040 /**
01041   * @}
01042   */
01043
01044 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 External Input Ch1 Remap
01045 * @{
01046 */
01047 #define LL_TIM_TIM1_TI1_RMP_GPIO  ((uint32_t)0x00000000U | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to GPIO */
01048 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK)      /*!< TIM1 input capture 1 is connected to COMP1 output */
01049 /**
01050   * @}
01051   */
01052
01053 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8  TIM2 Internal Trigger1 Remap TIM8
01054 * @{
01055 */
01056 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO  ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to TIM8_TRGO */
01057 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK)     /*!< TIM2_ITR1 is connected to OTG_FS SOF */
01058 #define LL_TIM_TIM2_ETR_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to GPIO */
01059 #define LL_TIM_TIM2_ETR_RMP_LSE  (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK)     /*!< TIM2_ETR is connected to LSE  */
01060 /**
01061   * @}
01062   */
01063
01064 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 External Input Ch4 Remap
01065 * @{
01066 */
01067 #define LL_TIM_TIM2_TI4_RMP_GPIO        ((uint32_t)0x00000000U | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to GPIO */
01068 #define LL_TIM_TIM2_TI4_RMP_COMP1       (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK)    /*!< TIM2 input capture 4 is connected to COMP1_OUT */
01069 #define LL_TIM_TIM2_TI4_RMP_COMP2       (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK)    /*!< TIM2 input capture 4 is connected to COMP2_OUT */
01070 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK)      /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
01071 /**
01072   * @}
01073   */
01074
01075 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 External Input Ch1 Remap
01076 * @{
01077 */
01078 #define LL_TIM_TIM3_TI1_RMP_GPIO         ((uint32_t)0x00000000U | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to GPIO */
01079 #define LL_TIM_TIM3_TI1_RMP_COMP1        (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK)    /*!< TIM3 input capture 1 is connected to COMP1_OUT */
01080 #define LL_TIM_TIM3_TI1_RMP_COMP2        (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK)    /*!< TIM3 input capture 1 is connected to COMP2_OUT */
01081 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2  (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK)      /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */
01082 /**
01083   * @}
01084   */
01085
01086 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP  TIM8 External Trigger ADC2 Remap
01087 * @{
01088 */
01089 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC   ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)   /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
01090 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */
01091 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
01092 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK)   /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
01093 /**
01094   * @}
01095   */
01096
01097 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP  TIM8 External Trigger ADC3 Remap
01098 * @{
01099 */
01100 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC   ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK)   /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
01101 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
01102 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
01103 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK)   /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
01104 /**
01105   * @}
01106   */
01107
01108 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 External Input Ch1 Remap
01109 * @{
01110 */
01111 #define LL_TIM_TIM8_TI1_RMP_GPIO  ((uint32_t)0x00000000U | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to GPIO */
01112 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK)      /*!< TIM8 input capture 1 is connected to COMP2 output */
01113 /**
01114   * @}
01115   */
01116
01117 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 External Input Ch1 Remap
01118 * @{
01119 */
01120 #define LL_TIM_TIM15_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to GPIO */
01121 #define LL_TIM_TIM15_TI1_RMP_LSE  (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK)     /*!< TIM15 input capture 1 is connected to LSE */
01122 /**
01123   * @}
01124   */
01125
01126 /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE  TIM15 ENCODERMODE
01127 * @{
01128 */
01129 #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION ((uint32_t)0x00000000U | TIM15_OR1_RMP_MASK)    /*!< No redirection*/
01130 #define LL_TIM_TIM15_ENCODERMODE_TIM2          (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
01131 #define LL_TIM_TIM15_ENCODERMODE_TIM3          (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/
01132 #define LL_TIM_TIM15_ENCODERMODE_TIM4          (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK)   /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
01133 /**
01134   * @}
01135   */
01136
01137 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 External Input Ch1 Remap
01138 * @{
01139 */
01140 #define LL_TIM_TIM16_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM16_OR1_RMP_MASK)                        /*!< TIM16 input capture 1 is connected to GPIO */
01141 #define LL_TIM_TIM16_TI1_RMP_LSI  (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)                          /*!< TIM16 input capture 1 is connected to LSI */
01142 #define LL_TIM_TIM16_TI1_RMP_LSE  (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK)                          /*!< TIM16 input capture 1 is connected to LSE */
01143 #define LL_TIM_TIM16_TI1_RMP_RTC  (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK)    /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
01144 #if defined TIM16_OR1_TI1_RMP_2
01145 #define LL_TIM_TIM16_TI1_RMP_MSI  (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_RMP_MASK)                          /*!< TIM16 input capture 1 is connected to MSI */
01146 #define LL_TIM_TIM16_TI1_RMP_HSE_32  (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 */
01147 #define LL_TIM_TIM16_TI1_RMP_MCO  (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK)    /*!< TIM16 input capture 1 is connected to MCO */
01148 #endif
01149 /**
01150   * @}
01151   */
01152
01153 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
01154 * @{
01155 */
01156 #define LL_TIM_TIM17_TI1_RMP_GPIO   ((uint32_t)0x00000000U | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to GPIO */
01157 #define LL_TIM_TIM17_TI1_RMP_MSI    (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK)   /*!< TIM17 input capture 1 is connected to MSI */
01158 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK)   /*!< TIM17 input capture 1 is connected to HSE/32 */
01159 #define LL_TIM_TIM17_TI1_RMP_MCO    (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK)     /*!< TIM17 input capture 1 is connected to MCO */
01160 /**
01161   * @}
01162   */
01163
01164 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
01165   * @{
01166   */
01167 #define LL_TIM_OCREF_CLR_INT_NC     ((uint32_t)0x00000000U ) /*!< OCREF_CLR_INT is not connected */
01168 #define LL_TIM_OCREF_CLR_INT_ETR    TIM_SMCR_OCCS            /*!< OCREF_CLR_INT is connected to ETRF */
01169 /**
01170   * @}
01171   */
01172
01173 /** Legacy definitions for compatibility purpose
01174 @cond 0
01175 */
01176 #define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
01177 /**
01178 @endcond
01179   */
01180
01181 /**
01182   * @}
01183   */
01184
01185 /* Exported macro ------------------------------------------------------------*/
01186 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
01187   * @{
01188   */
01189
01190 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
01191   * @{
01192   */
01193 /**
01194   * @brief  Write a value in TIM register.
01195   * @param  __INSTANCE__ TIM Instance
01196   * @param  __REG__ Register to be written
01197   * @param  __VALUE__ Value to be written in the register
01198   * @retval None
01199   */
01200 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01201
01202 /**
01203   * @brief  Read a value in TIM register.
01204   * @param  __INSTANCE__ TIM Instance
01205   * @param  __REG__ Register to be read
01206   * @retval Register value
01207   */
01208 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01209 /**
01210   * @}
01211   */
01212
01213 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
01214   * @{
01215   */
01216 /**
01217   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
01218   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
01219   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
01220   *        to TIMx_CNT register bit 31)
01221   * @param  __CNT__ Counter value
01222   * @retval UIF status bit
01223   */
01224 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
01225    (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> POSITION_VAL(TIM_CNT_UIFCPY))
01226
01227 /**
01228   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
01229   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
01230   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01231   * @param  __CKD__ This parameter can be one of the following values:
01232   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01233   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01234   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01235   * @param  __DT__ deadtime duration (in ns)
01236   * @retval DTG[0:7]
01237   */
01238 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
01239     ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))           ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
01240       (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
01241       (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
01242       (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
01243        0U)
01244
01245 /**
01246   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
01247   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
01248   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01249   * @param  __CNTCLK__ counter clock frequency (in Hz)
01250   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
01251   */
01252 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
01253    ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
01254
01255 /**
01256   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
01257   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
01258   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01259   * @param  __PSC__ prescaler
01260   * @param  __FREQ__ output signal frequency (in Hz)
01261   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01262   */
01263 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
01264      (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
01265
01266 /**
01267   * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
01268   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
01269   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01270   * @param  __PSC__ prescaler
01271   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01272   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
01273   */
01274 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
01275 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
01276           / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
01277
01278 /**
01279   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
01280   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
01281   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01282   * @param  __PSC__ prescaler
01283   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01284   * @param  __PULSE__ pulse duration (in us)
01285   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01286   */
01287 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
01288  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
01289            + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
01290
01291 /**
01292   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
01293   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
01294   * @param  __ICPSC__ This parameter can be one of the following values:
01295   *         @arg @ref LL_TIM_ICPSC_DIV1
01296   *         @arg @ref LL_TIM_ICPSC_DIV2
01297   *         @arg @ref LL_TIM_ICPSC_DIV4
01298   *         @arg @ref LL_TIM_ICPSC_DIV8
01299   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
01300   */
01301 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
01302    ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_POSITION_ICPSC)))
01303
01304
01305 /**
01306   * @}
01307   */
01308
01309
01310 /**
01311   * @}
01312   */
01313
01314 /* Exported functions --------------------------------------------------------*/
01315 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
01316   * @{
01317   */
01318
01319 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
01320   * @{
01321   */
01322 /**
01323   * @brief  Enable timer counter.
01324   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
01325   * @param  TIMx Timer instance
01326   * @retval None
01327   */
01328 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef * TIMx)
01329 {
01330   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
01331 }
01332
01333 /**
01334   * @brief  Disable timer counter.
01335   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
01336   * @param  TIMx Timer instance
01337   * @retval None
01338   */
01339 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef * TIMx)
01340 {
01341   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
01342 }
01343
01344 /**
01345   * @brief  Indicates whether the timer counter is enabled.
01346   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
01347   * @param  TIMx Timer instance
01348   * @retval State of bit (1 or 0).
01349   */
01350 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)
01351 {
01352   return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
01353 }
01354
01355 /**
01356   * @brief  Enable update event generation.
01357   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
01358   * @param  TIMx Timer instance
01359   * @retval None
01360   */
01361 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)
01362 {
01363   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
01364 }
01365
01366 /**
01367   * @brief  Disable update event generation.
01368   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
01369   * @param  TIMx Timer instance
01370   * @retval None
01371   */
01372 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)
01373 {
01374   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
01375 }
01376
01377 /**
01378   * @brief  Indicates whether update event generation is enabled.
01379   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
01380   * @param  TIMx Timer instance
01381   * @retval State of bit (1 or 0).
01382   */
01383 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)
01384 {
01385   return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
01386 }
01387
01388 /**
01389   * @brief  Set update event source
01390   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
01391   *       generate an update interrupt or DMA request if enabled:
01392   *        - Counter overflow/underflow
01393   *        - Setting the UG bit
01394   *        - Update generation through the slave mode controller
01395   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
01396   *       overflow/underflow generates an update interrupt or DMA request if enabled.
01397   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
01398   * @param  TIMx Timer instance
01399   * @param  UpdateSource This parameter can be one of the following values:
01400   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01401   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01402   * @retval None
01403   */
01404 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx, uint32_t UpdateSource)
01405 {
01406   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
01407 }
01408
01409 /**
01410   * @brief  Get actual event update source
01411   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
01412   * @param  TIMx Timer instance
01413   * @retval Returned value can be one of the following values:
01414   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01415   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01416   */
01417 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)
01418 {
01419   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
01420 }
01421
01422 /**
01423   * @brief  Set one pulse mode (one shot v.s. repetitive).
01424   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
01425   * @param  TIMx Timer instance
01426   * @param  OnePulseMode This parameter can be one of the following values:
01427   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01428   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01429   * @retval None
01430   */
01431 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx, uint32_t OnePulseMode)
01432 {
01433   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
01434 }
01435
01436 /**
01437   * @brief  Get actual one pulse mode.
01438   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
01439   * @param  TIMx Timer instance
01440   * @retval Returned value can be one of the following values:
01441   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01442   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01443   */
01444 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)
01445 {
01446   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
01447 }
01448
01449 /**
01450   * @brief  Set the timer counter counting mode.
01451   * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01452   *       check whether or not the counter mode selection feature is supported
01453   *       by a timer instance.
01454   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
01455   *         CR1          CMS           LL_TIM_SetCounterMode
01456   * @param  TIMx Timer instance
01457   * @param  CounterMode This parameter can be one of the following values:
01458   *         @arg @ref LL_TIM_COUNTERMODE_UP
01459   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01460   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01461   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01462   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01463   * @retval None
01464   */
01465 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef * TIMx, uint32_t CounterMode)
01466 {
01467   MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
01468 }
01469
01470 /**
01471   * @brief  Get actual counter mode.
01472   * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01473   *       check whether or not the counter mode selection feature is supported
01474   *       by a timer instance.
01475   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
01476   *         CR1          CMS           LL_TIM_GetCounterMode
01477   * @param  TIMx Timer instance
01478   * @retval Returned value can be one of the following values:
01479   *         @arg @ref LL_TIM_COUNTERMODE_UP
01480   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01481   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01482   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01483   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01484   */
01485 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)
01486 {
01487   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
01488 }
01489
01490 /**
01491   * @brief  Enable auto-reload (ARR) preload.
01492   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
01493   * @param  TIMx Timer instance
01494   * @retval None
01495   */
01496 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)
01497 {
01498   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
01499 }
01500
01501 /**
01502   * @brief  Disable auto-reload (ARR) preload.
01503   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
01504   * @param  TIMx Timer instance
01505   * @retval None
01506   */
01507 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)
01508 {
01509   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
01510 }
01511
01512 /**
01513   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
01514   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
01515   * @param  TIMx Timer instance
01516   * @retval State of bit (1 or 0).
01517   */
01518 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)
01519 {
01520   return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
01521 }
01522
01523 /**
01524   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01525   * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01526   *       whether or not the clock division feature is supported by the timer
01527   *       instance.
01528   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
01529   * @param  TIMx Timer instance
01530   * @param  ClockDivision This parameter can be one of the following values:
01531   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01532   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01533   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01534   * @retval None
01535   */
01536 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef * TIMx, uint32_t ClockDivision)
01537 {
01538   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
01539 }
01540
01541 /**
01542   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01543   * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01544   *       whether or not the clock division feature is supported by the timer
01545   *       instance.
01546   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
01547   * @param  TIMx Timer instance
01548   * @retval Returned value can be one of the following values:
01549   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01550   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01551   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01552   */
01553 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)
01554 {
01555   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
01556 }
01557
01558 /**
01559   * @brief  Set the counter value.
01560   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01561   *       whether or not a timer instance supports a 32 bits counter.
01562   * @rmtoll CNT          CNT           LL_TIM_SetCounter
01563   * @param  TIMx Timer instance
01564   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01565   * @retval None
01566   */
01567 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef * TIMx, uint32_t Counter)
01568 {
01569   WRITE_REG(TIMx->CNT, Counter);
01570 }
01571
01572 /**
01573   * @brief  Get the counter value.
01574   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01575   *       whether or not a timer instance supports a 32 bits counter.
01576   * @rmtoll CNT          CNT           LL_TIM_GetCounter
01577   * @param  TIMx Timer instance
01578   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01579   */
01580 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef * TIMx)
01581 {
01582   return (uint32_t)(READ_REG(TIMx->CNT));
01583 }
01584
01585 /**
01586   * @brief  Get the current direction of the counter
01587   * @rmtoll CR1          DIR           LL_TIM_GetDirection
01588   * @param  TIMx Timer instance
01589   * @retval Returned value can be one of the following values:
01590   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
01591   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
01592   */
01593 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef * TIMx)
01594 {
01595   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
01596 }
01597
01598 /**
01599   * @brief  Set the prescaler value.
01600   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
01601   * @note The prescaler can be changed on the fly as this control register is buffered. The new
01602   *       prescaler ratio is taken into account at the next update event.
01603   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
01604   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
01605   * @param  TIMx Timer instance
01606   * @param  Prescaler between Min_Data=0 and Max_Data=65535
01607   * @retval None
01608   */
01609 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Prescaler)
01610 {
01611   WRITE_REG(TIMx->PSC, Prescaler);
01612 }
01613
01614 /**
01615   * @brief  Get the prescaler value.
01616   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
01617   * @param  TIMx Timer instance
01618   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
01619   */
01620 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)
01621 {
01622   return (uint32_t)(READ_REG(TIMx->PSC));
01623 }
01624
01625 /**
01626   * @brief  Set the auto-reload value.
01627   * @note The counter is blocked while the auto-reload value is null.
01628   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01629   *       whether or not a timer instance supports a 32 bits counter.
01630   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
01631   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
01632   * @param  TIMx Timer instance
01633   * @param  AutoReload between Min_Data=0 and Max_Data=65535
01634   * @retval None
01635   */
01636 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef * TIMx, uint32_t AutoReload)
01637 {
01638   WRITE_REG(TIMx->ARR, AutoReload);
01639 }
01640
01641 /**
01642   * @brief  Get the auto-reload value.
01643   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
01644   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01645   *       whether or not a timer instance supports a 32 bits counter.
01646   * @param  TIMx Timer instance
01647   * @retval Auto-reload value
01648   */
01649 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)
01650 {
01651   return (uint32_t)(READ_REG(TIMx->ARR));
01652 }
01653
01654 /**
01655   * @brief  Set the repetition counter value.
01656   * @note For advanced timer instances RepetitionCounter can be up to 65535.
01657   * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01658   *       whether or not a timer instance supports a repetition counter.
01659   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
01660   * @param  TIMx Timer instance
01661   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255
01662   * @retval None
01663   */
01664 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx, uint32_t RepetitionCounter)
01665 {
01666   WRITE_REG(TIMx->RCR, RepetitionCounter);
01667 }
01668
01669 /**
01670   * @brief  Get the repetition counter value.
01671   * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01672   *       whether or not a timer instance supports a repetition counter.
01673   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
01674   * @param  TIMx Timer instance
01675   * @retval Repetition counter value
01676   */
01677 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)
01678 {
01679   return (uint32_t)(READ_REG(TIMx->RCR));
01680 }
01681
01682 /**
01683   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
01684   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
01685   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
01686   * @param  TIMx Timer instance
01687   * @retval None
01688   */
01689 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)
01690 {
01691   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01692 }
01693
01694 /**
01695   * @brief  Disable update interrupt flag (UIF) remapping.
01696   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
01697   * @param  TIMx Timer instance
01698   * @retval None
01699   */
01700 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)
01701 {
01702   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01703 }
01704
01705 /**
01706   * @}
01707   */
01708
01709 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
01710   * @{
01711   */
01712 /**
01713   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01714   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
01715   *       they are updated only when a commutation event (COM) occurs.
01716   * @note Only on channels that have a complementary output.
01717   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01718   *       whether or not a timer instance is able to generate a commutation event.
01719   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
01720   * @param  TIMx Timer instance
01721   * @retval None
01722   */
01723 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)
01724 {
01725   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
01726 }
01727
01728 /**
01729   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01730   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01731   *       whether or not a timer instance is able to generate a commutation event.
01732   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
01733   * @param  TIMx Timer instance
01734   * @retval None
01735   */
01736 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)
01737 {
01738   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
01739 }
01740
01741 /**
01742   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
01743   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01744   *       whether or not a timer instance is able to generate a commutation event.
01745   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
01746   * @param  TIMx Timer instance
01747   * @param  CCUpdateSource This parameter can be one of the following values:
01748   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
01749   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
01750   * @retval None
01751   */
01752 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx, uint32_t CCUpdateSource)
01753 {
01754   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
01755 }
01756
01757 /**
01758   * @brief  Set the trigger of the capture/compare DMA request.
01759   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
01760   * @param  TIMx Timer instance
01761   * @param  DMAReqTrigger This parameter can be one of the following values:
01762   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01763   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01764   * @retval None
01765   */
01766 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx, uint32_t DMAReqTrigger)
01767 {
01768   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
01769 }
01770
01771 /**
01772   * @brief  Get actual trigger of the capture/compare DMA request.
01773   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
01774   * @param  TIMx Timer instance
01775   * @retval Returned value can be one of the following values:
01776   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01777   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01778   */
01779 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)
01780 {
01781   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
01782 }
01783
01784 /**
01785   * @brief  Set the lock level to freeze the
01786   *         configuration of several capture/compare parameters.
01787   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
01788   *       the lock mechanism is supported by a timer instance.
01789   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
01790   * @param  TIMx Timer instance
01791   * @param  LockLevel This parameter can be one of the following values:
01792   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
01793   *         @arg @ref LL_TIM_LOCKLEVEL_1
01794   *         @arg @ref LL_TIM_LOCKLEVEL_2
01795   *         @arg @ref LL_TIM_LOCKLEVEL_3
01796   * @retval None
01797   */
01798 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx, uint32_t LockLevel)
01799 {
01800   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
01801 }
01802
01803 /**
01804   * @brief  Enable capture/compare channels.
01805   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
01806   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
01807   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
01808   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
01809   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
01810   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
01811   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
01812   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
01813   *         CCER         CC6E          LL_TIM_CC_EnableChannel
01814   * @param  TIMx Timer instance
01815   * @param  Channels This parameter can be a combination of the following values:
01816   *         @arg @ref LL_TIM_CHANNEL_CH1
01817   *         @arg @ref LL_TIM_CHANNEL_CH1N
01818   *         @arg @ref LL_TIM_CHANNEL_CH2
01819   *         @arg @ref LL_TIM_CHANNEL_CH2N
01820   *         @arg @ref LL_TIM_CHANNEL_CH3
01821   *         @arg @ref LL_TIM_CHANNEL_CH3N
01822   *         @arg @ref LL_TIM_CHANNEL_CH4
01823   *         @arg @ref LL_TIM_CHANNEL_CH5
01824   *         @arg @ref LL_TIM_CHANNEL_CH6
01825   * @retval None
01826   */
01827 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx, uint32_t Channels)
01828 {
01829   SET_BIT(TIMx->CCER, Channels);
01830 }
01831
01832 /**
01833   * @brief  Disable capture/compare channels.
01834   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
01835   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
01836   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
01837   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
01838   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
01839   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
01840   *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
01841   *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
01842   *         CCER         CC6E          LL_TIM_CC_DisableChannel
01843   * @param  TIMx Timer instance
01844   * @param  Channels This parameter can be a combination of the following values:
01845   *         @arg @ref LL_TIM_CHANNEL_CH1
01846   *         @arg @ref LL_TIM_CHANNEL_CH1N
01847   *         @arg @ref LL_TIM_CHANNEL_CH2
01848   *         @arg @ref LL_TIM_CHANNEL_CH2N
01849   *         @arg @ref LL_TIM_CHANNEL_CH3
01850   *         @arg @ref LL_TIM_CHANNEL_CH3N
01851   *         @arg @ref LL_TIM_CHANNEL_CH4
01852   *         @arg @ref LL_TIM_CHANNEL_CH5
01853   *         @arg @ref LL_TIM_CHANNEL_CH6
01854   * @retval None
01855   */
01856 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx, uint32_t Channels)
01857 {
01858   CLEAR_BIT(TIMx->CCER, Channels);
01859 }
01860
01861 /**
01862   * @brief  Indicate whether channel(s) is(are) enabled.
01863   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
01864   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
01865   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
01866   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
01867   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
01868   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
01869   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
01870   *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
01871   *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
01872   * @param  TIMx Timer instance
01873   * @param  Channels This parameter can be a combination of the following values:
01874   *         @arg @ref LL_TIM_CHANNEL_CH1
01875   *         @arg @ref LL_TIM_CHANNEL_CH1N
01876   *         @arg @ref LL_TIM_CHANNEL_CH2
01877   *         @arg @ref LL_TIM_CHANNEL_CH2N
01878   *         @arg @ref LL_TIM_CHANNEL_CH3
01879   *         @arg @ref LL_TIM_CHANNEL_CH3N
01880   *         @arg @ref LL_TIM_CHANNEL_CH4
01881   *         @arg @ref LL_TIM_CHANNEL_CH5
01882   *         @arg @ref LL_TIM_CHANNEL_CH6
01883   * @retval State of bit (1 or 0).
01884   */
01885 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx, uint32_t Channels)
01886 {
01887   return (READ_BIT(TIMx->CCER, Channels) == (Channels));
01888 }
01889
01890 /**
01891   * @}
01892   */
01893
01894 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
01895   * @{
01896   */
01897 /**
01898   * @brief  Configure an output channel.
01899   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
01900   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
01901   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
01902   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
01903   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
01904   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
01905   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
01906   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
01907   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
01908   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
01909   *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
01910   *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
01911   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
01912   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
01913   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
01914   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
01915   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
01916   *         CR2          OIS6          LL_TIM_OC_ConfigOutput
01917   * @param  TIMx Timer instance
01918   * @param  Channel This parameter can be one of the following values:
01919   *         @arg @ref LL_TIM_CHANNEL_CH1
01920   *         @arg @ref LL_TIM_CHANNEL_CH2
01921   *         @arg @ref LL_TIM_CHANNEL_CH3
01922   *         @arg @ref LL_TIM_CHANNEL_CH4
01923   *         @arg @ref LL_TIM_CHANNEL_CH5
01924   *         @arg @ref LL_TIM_CHANNEL_CH6
01925   * @param  Configuration This parameter must be a combination of all the following values:
01926   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
01927   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
01928   * @retval None
01929   */
01930 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration)
01931 {
01932   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01933   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
01934   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
01935   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
01936   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
01937 }
01938
01939 /**
01940   * @brief  Define the behavior of the output reference signal OCxREF from which
01941   *         OCx and OCxN (when relevant) are derived.
01942   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
01943   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
01944   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
01945   *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
01946   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
01947   *         CCMR3        OC6M          LL_TIM_OC_SetMode
01948   * @param  TIMx Timer instance
01949   * @param  Channel This parameter can be one of the following values:
01950   *         @arg @ref LL_TIM_CHANNEL_CH1
01951   *         @arg @ref LL_TIM_CHANNEL_CH2
01952   *         @arg @ref LL_TIM_CHANNEL_CH3
01953   *         @arg @ref LL_TIM_CHANNEL_CH4
01954   *         @arg @ref LL_TIM_CHANNEL_CH5
01955   *         @arg @ref LL_TIM_CHANNEL_CH6
01956   * @param  Mode This parameter can be one of the following values:
01957   *         @arg @ref LL_TIM_OCMODE_FROZEN
01958   *         @arg @ref LL_TIM_OCMODE_ACTIVE
01959   *         @arg @ref LL_TIM_OCMODE_INACTIVE
01960   *         @arg @ref LL_TIM_OCMODE_TOGGLE
01961   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
01962   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
01963   *         @arg @ref LL_TIM_OCMODE_PWM1
01964   *         @arg @ref LL_TIM_OCMODE_PWM2
01965   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
01966   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
01967   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
01968   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
01969   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
01970   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
01971   * @retval None
01972   */
01973 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Mode)
01974 {
01975   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01976   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
01977   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
01978 }
01979
01980 /**
01981   * @brief  Get the output compare mode of an output channel.
01982   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
01983   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
01984   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
01985   *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
01986   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
01987   *         CCMR3        OC6M          LL_TIM_OC_GetMode
01988   * @param  TIMx Timer instance
01989   * @param  Channel This parameter can be one of the following values:
01990   *         @arg @ref LL_TIM_CHANNEL_CH1
01991   *         @arg @ref LL_TIM_CHANNEL_CH2
01992   *         @arg @ref LL_TIM_CHANNEL_CH3
01993   *         @arg @ref LL_TIM_CHANNEL_CH4
01994   *         @arg @ref LL_TIM_CHANNEL_CH5
01995   *         @arg @ref LL_TIM_CHANNEL_CH6
01996   * @retval Returned value can be one of the following values:
01997   *         @arg @ref LL_TIM_OCMODE_FROZEN
01998   *         @arg @ref LL_TIM_OCMODE_ACTIVE
01999   *         @arg @ref LL_TIM_OCMODE_INACTIVE
02000   *         @arg @ref LL_TIM_OCMODE_TOGGLE
02001   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
02002   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
02003   *         @arg @ref LL_TIM_OCMODE_PWM1
02004   *         @arg @ref LL_TIM_OCMODE_PWM2
02005   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
02006   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
02007   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
02008   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
02009   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
02010   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
02011   */
02012 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef * TIMx, uint32_t Channel)
02013 {
02014   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02015   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02016   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
02017 }
02018
02019 /**
02020   * @brief  Set the polarity of an output channel.
02021   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
02022   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
02023   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
02024   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
02025   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
02026   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
02027   *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
02028   *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
02029   *         CCER         CC6P          LL_TIM_OC_SetPolarity
02030   * @param  TIMx Timer instance
02031   * @param  Channel This parameter can be one of the following values:
02032   *         @arg @ref LL_TIM_CHANNEL_CH1
02033   *         @arg @ref LL_TIM_CHANNEL_CH1N
02034   *         @arg @ref LL_TIM_CHANNEL_CH2
02035   *         @arg @ref LL_TIM_CHANNEL_CH2N
02036   *         @arg @ref LL_TIM_CHANNEL_CH3
02037   *         @arg @ref LL_TIM_CHANNEL_CH3N
02038   *         @arg @ref LL_TIM_CHANNEL_CH4
02039   *         @arg @ref LL_TIM_CHANNEL_CH5
02040   *         @arg @ref LL_TIM_CHANNEL_CH6
02041   * @param  Polarity This parameter can be one of the following values:
02042   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02043   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02044   * @retval None
02045   */
02046 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Polarity)
02047 {
02048   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02049   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
02050 }
02051
02052 /**
02053   * @brief  Get the polarity of an output channel.
02054   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
02055   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
02056   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
02057   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
02058   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
02059   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
02060   *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
02061   *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
02062   *         CCER         CC6P          LL_TIM_OC_GetPolarity
02063   * @param  TIMx Timer instance
02064   * @param  Channel This parameter can be one of the following values:
02065   *         @arg @ref LL_TIM_CHANNEL_CH1
02066   *         @arg @ref LL_TIM_CHANNEL_CH1N
02067   *         @arg @ref LL_TIM_CHANNEL_CH2
02068   *         @arg @ref LL_TIM_CHANNEL_CH2N
02069   *         @arg @ref LL_TIM_CHANNEL_CH3
02070   *         @arg @ref LL_TIM_CHANNEL_CH3N
02071   *         @arg @ref LL_TIM_CHANNEL_CH4
02072   *         @arg @ref LL_TIM_CHANNEL_CH5
02073   *         @arg @ref LL_TIM_CHANNEL_CH6
02074   * @retval Returned value can be one of the following values:
02075   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02076   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02077   */
02078 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel)
02079 {
02080   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02081   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
02082 }
02083
02084 /**
02085   * @brief  Set the IDLE state of an output channel
02086   * @note This function is significant only for the timer instances
02087   *       supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
02088   *       can be used to check whether or not a timer instance provides
02089   *       a break input.
02090   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
02091   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02092   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
02093   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02094   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
02095   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
02096   *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
02097   *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
02098   *         CR2         OIS6          LL_TIM_OC_SetIdleState
02099   * @param  TIMx Timer instance
02100   * @param  Channel This parameter can be one of the following values:
02101   *         @arg @ref LL_TIM_CHANNEL_CH1
02102   *         @arg @ref LL_TIM_CHANNEL_CH1N
02103   *         @arg @ref LL_TIM_CHANNEL_CH2
02104   *         @arg @ref LL_TIM_CHANNEL_CH2N
02105   *         @arg @ref LL_TIM_CHANNEL_CH3
02106   *         @arg @ref LL_TIM_CHANNEL_CH3N
02107   *         @arg @ref LL_TIM_CHANNEL_CH4
02108   *         @arg @ref LL_TIM_CHANNEL_CH5
02109   *         @arg @ref LL_TIM_CHANNEL_CH6
02110   * @param  IdleState This parameter can be one of the following values:
02111   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02112   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02113   * @retval None
02114   */
02115 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t IdleState)
02116 {
02117   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02118   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
02119 }
02120
02121 /**
02122   * @brief  Get the IDLE state of an output channel
02123   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
02124   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02125   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
02126   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02127   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
02128   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
02129   *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
02130   *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
02131   *         CR2         OIS6          LL_TIM_OC_GetIdleState
02132   * @param  TIMx Timer instance
02133   * @param  Channel This parameter can be one of the following values:
02134   *         @arg @ref LL_TIM_CHANNEL_CH1
02135   *         @arg @ref LL_TIM_CHANNEL_CH1N
02136   *         @arg @ref LL_TIM_CHANNEL_CH2
02137   *         @arg @ref LL_TIM_CHANNEL_CH2N
02138   *         @arg @ref LL_TIM_CHANNEL_CH3
02139   *         @arg @ref LL_TIM_CHANNEL_CH3N
02140   *         @arg @ref LL_TIM_CHANNEL_CH4
02141   *         @arg @ref LL_TIM_CHANNEL_CH5
02142   *         @arg @ref LL_TIM_CHANNEL_CH6
02143   * @retval Returned value can be one of the following values:
02144   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02145   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02146   */
02147 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx, uint32_t Channel)
02148 {
02149   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02150   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
02151 }
02152
02153 /**
02154   * @brief  Enable fast mode for the output channel.
02155   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
02156   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
02157   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
02158   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
02159   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
02160   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
02161   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
02162   * @param  TIMx Timer instance
02163   * @param  Channel This parameter can be one of the following values:
02164   *         @arg @ref LL_TIM_CHANNEL_CH1
02165   *         @arg @ref LL_TIM_CHANNEL_CH2
02166   *         @arg @ref LL_TIM_CHANNEL_CH3
02167   *         @arg @ref LL_TIM_CHANNEL_CH4
02168   *         @arg @ref LL_TIM_CHANNEL_CH5
02169   *         @arg @ref LL_TIM_CHANNEL_CH6
02170   * @retval None
02171   */
02172 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx, uint32_t Channel)
02173 {
02174   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02175   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02176   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02177
02178 }
02179
02180 /**
02181   * @brief  Disable fast mode for the output channel.
02182   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
02183   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
02184   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
02185   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
02186   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
02187   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
02188   * @param  TIMx Timer instance
02189   * @param  Channel This parameter can be one of the following values:
02190   *         @arg @ref LL_TIM_CHANNEL_CH1
02191   *         @arg @ref LL_TIM_CHANNEL_CH2
02192   *         @arg @ref LL_TIM_CHANNEL_CH3
02193   *         @arg @ref LL_TIM_CHANNEL_CH4
02194   *         @arg @ref LL_TIM_CHANNEL_CH5
02195   *         @arg @ref LL_TIM_CHANNEL_CH6
02196   * @retval None
02197   */
02198 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx, uint32_t Channel)
02199 {
02200   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02201   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02202   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02203
02204 }
02205
02206 /**
02207   * @brief  Indicates whether fast mode is enabled for the output channel.
02208   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
02209   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
02210   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
02211   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
02212   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
02213   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
02214   * @param  TIMx Timer instance
02215   * @param  Channel This parameter can be one of the following values:
02216   *         @arg @ref LL_TIM_CHANNEL_CH1
02217   *         @arg @ref LL_TIM_CHANNEL_CH2
02218   *         @arg @ref LL_TIM_CHANNEL_CH3
02219   *         @arg @ref LL_TIM_CHANNEL_CH4
02220   *         @arg @ref LL_TIM_CHANNEL_CH5
02221   *         @arg @ref LL_TIM_CHANNEL_CH6
02222   * @retval State of bit (1 or 0).
02223   */
02224 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx, uint32_t Channel)
02225 {
02226   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02227   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02228   register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
02229   return (READ_BIT(*pReg, bitfield) == bitfield);
02230 }
02231
02232 /**
02233   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
02234   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
02235   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
02236   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
02237   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
02238   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
02239   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
02240   * @param  TIMx Timer instance
02241   * @param  Channel This parameter can be one of the following values:
02242   *         @arg @ref LL_TIM_CHANNEL_CH1
02243   *         @arg @ref LL_TIM_CHANNEL_CH2
02244   *         @arg @ref LL_TIM_CHANNEL_CH3
02245   *         @arg @ref LL_TIM_CHANNEL_CH4
02246   *         @arg @ref LL_TIM_CHANNEL_CH5
02247   *         @arg @ref LL_TIM_CHANNEL_CH6
02248   * @retval None
02249   */
02250 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx, uint32_t Channel)
02251 {
02252   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02253   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02254   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02255 }
02256
02257 /**
02258   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
02259   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
02260   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
02261   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
02262   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
02263   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
02264   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
02265   * @param  TIMx Timer instance
02266   * @param  Channel This parameter can be one of the following values:
02267   *         @arg @ref LL_TIM_CHANNEL_CH1
02268   *         @arg @ref LL_TIM_CHANNEL_CH2
02269   *         @arg @ref LL_TIM_CHANNEL_CH3
02270   *         @arg @ref LL_TIM_CHANNEL_CH4
02271   *         @arg @ref LL_TIM_CHANNEL_CH5
02272   *         @arg @ref LL_TIM_CHANNEL_CH6
02273   * @retval None
02274   */
02275 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx, uint32_t Channel)
02276 {
02277   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02278   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02279   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02280 }
02281
02282 /**
02283   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
02284   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
02285   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
02286   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
02287   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
02288   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
02289   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
02290   * @param  TIMx Timer instance
02291   * @param  Channel This parameter can be one of the following values:
02292   *         @arg @ref LL_TIM_CHANNEL_CH1
02293   *         @arg @ref LL_TIM_CHANNEL_CH2
02294   *         @arg @ref LL_TIM_CHANNEL_CH3
02295   *         @arg @ref LL_TIM_CHANNEL_CH4
02296   *         @arg @ref LL_TIM_CHANNEL_CH5
02297   *         @arg @ref LL_TIM_CHANNEL_CH6
02298   * @retval State of bit (1 or 0).
02299   */
02300 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx, uint32_t Channel)
02301 {
02302   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02303   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02304   register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
02305   return (READ_BIT(*pReg, bitfield) == bitfield);
02306 }
02307
02308 /**
02309   * @brief  Enable clearing the output channel on an external event.
02310   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02311   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02312   *       or not a timer instance can clear the OCxREF signal on an external event.
02313   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
02314   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
02315   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
02316   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
02317   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
02318   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
02319   * @param  TIMx Timer instance
02320   * @param  Channel This parameter can be one of the following values:
02321   *         @arg @ref LL_TIM_CHANNEL_CH1
02322   *         @arg @ref LL_TIM_CHANNEL_CH2
02323   *         @arg @ref LL_TIM_CHANNEL_CH3
02324   *         @arg @ref LL_TIM_CHANNEL_CH4
02325   *         @arg @ref LL_TIM_CHANNEL_CH5
02326   *         @arg @ref LL_TIM_CHANNEL_CH6
02327   * @retval None
02328   */
02329 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx, uint32_t Channel)
02330 {
02331   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02332   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02333   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02334 }
02335
02336 /**
02337   * @brief  Disable clearing the output channel on an external event.
02338   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02339   *       or not a timer instance can clear the OCxREF signal on an external event.
02340   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
02341   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
02342   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
02343   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
02344   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
02345   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
02346   * @param  TIMx Timer instance
02347   * @param  Channel This parameter can be one of the following values:
02348   *         @arg @ref LL_TIM_CHANNEL_CH1
02349   *         @arg @ref LL_TIM_CHANNEL_CH2
02350   *         @arg @ref LL_TIM_CHANNEL_CH3
02351   *         @arg @ref LL_TIM_CHANNEL_CH4
02352   *         @arg @ref LL_TIM_CHANNEL_CH5
02353   *         @arg @ref LL_TIM_CHANNEL_CH6
02354   * @retval None
02355   */
02356 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx, uint32_t Channel)
02357 {
02358   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02359   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02360   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02361 }
02362
02363 /**
02364   * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
02365   * @note This function enables clearing the output channel on an external event.
02366   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02367   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02368   *       or not a timer instance can clear the OCxREF signal on an external event.
02369   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
02370   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
02371   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
02372   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
02373   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
02374   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
02375   * @param  TIMx Timer instance
02376   * @param  Channel This parameter can be one of the following values:
02377   *         @arg @ref LL_TIM_CHANNEL_CH1
02378   *         @arg @ref LL_TIM_CHANNEL_CH2
02379   *         @arg @ref LL_TIM_CHANNEL_CH3
02380   *         @arg @ref LL_TIM_CHANNEL_CH4
02381   *         @arg @ref LL_TIM_CHANNEL_CH5
02382   *         @arg @ref LL_TIM_CHANNEL_CH6
02383   * @retval State of bit (1 or 0).
02384   */
02385 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx, uint32_t Channel)
02386 {
02387   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02388   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02389   register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
02390   return (READ_BIT(*pReg, bitfield) == bitfield);
02391 }
02392
02393 /**
02394   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
02395   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02396   *       dead-time insertion feature is supported by a timer instance.
02397   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
02398   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
02399   * @param  TIMx Timer instance
02400   * @param  DeadTime between Min_Data=0 and Max_Data=255
02401   * @retval None
02402   */
02403 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx, uint32_t DeadTime)
02404 {
02405   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
02406 }
02407
02408 /**
02409   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
02410   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02411   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02412   *       whether or not a timer instance supports a 32 bits counter.
02413   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02414   *       output channel 1 is supported by a timer instance.
02415   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
02416   * @param  TIMx Timer instance
02417   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02418   * @retval None
02419   */
02420 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx, uint32_t CompareValue)
02421 {
02422   WRITE_REG(TIMx->CCR1, CompareValue);
02423 }
02424
02425 /**
02426   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
02427   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02428   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02429   *       whether or not a timer instance supports a 32 bits counter.
02430   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02431   *       output channel 2 is supported by a timer instance.
02432   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
02433   * @param  TIMx Timer instance
02434   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02435   * @retval None
02436   */
02437 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx, uint32_t CompareValue)
02438 {
02439   WRITE_REG(TIMx->CCR2, CompareValue);
02440 }
02441
02442 /**
02443   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
02444   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02445   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02446   *       whether or not a timer instance supports a 32 bits counter.
02447   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02448   *       output channel is supported by a timer instance.
02449   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
02450   * @param  TIMx Timer instance
02451   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02452   * @retval None
02453   */
02454 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx, uint32_t CompareValue)
02455 {
02456   WRITE_REG(TIMx->CCR3, CompareValue);
02457 }
02458
02459 /**
02460   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
02461   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02462   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02463   *       whether or not a timer instance supports a 32 bits counter.
02464   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02465   *       output channel 4 is supported by a timer instance.
02466   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
02467   * @param  TIMx Timer instance
02468   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02469   * @retval None
02470   */
02471 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx, uint32_t CompareValue)
02472 {
02473   WRITE_REG(TIMx->CCR4, CompareValue);
02474 }
02475
02476 /**
02477   * @brief  Set compare value for output channel 5 (TIMx_CCR5).
02478   * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02479   *       output channel 5 is supported by a timer instance.
02480   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
02481   * @param  TIMx Timer instance
02482   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02483   * @retval None
02484   */
02485 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx, uint32_t CompareValue)
02486 {
02487   WRITE_REG(TIMx->CCR5, CompareValue);
02488 }
02489
02490 /**
02491   * @brief  Set compare value for output channel 6 (TIMx_CCR6).
02492   * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02493   *       output channel 6 is supported by a timer instance.
02494   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
02495   * @param  TIMx Timer instance
02496   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02497   * @retval None
02498   */
02499 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx, uint32_t CompareValue)
02500 {
02501   WRITE_REG(TIMx->CCR6, CompareValue);
02502 }
02503
02504 /**
02505   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
02506   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02507   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02508   *       whether or not a timer instance supports a 32 bits counter.
02509   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02510   *       output channel 1 is supported by a timer instance.
02511   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
02512   * @param  TIMx Timer instance
02513   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02514   */
02515 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)
02516 {
02517   return (uint32_t)(READ_REG(TIMx->CCR1));
02518 }
02519
02520 /**
02521   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
02522   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02523   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02524   *       whether or not a timer instance supports a 32 bits counter.
02525   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02526   *       output channel 2 is supported by a timer instance.
02527   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
02528   * @param  TIMx Timer instance
02529   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02530   */
02531 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)
02532 {
02533   return (uint32_t)(READ_REG(TIMx->CCR2));
02534 }
02535
02536 /**
02537   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
02538   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02539   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02540   *       whether or not a timer instance supports a 32 bits counter.
02541   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02542   *       output channel 3 is supported by a timer instance.
02543   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
02544   * @param  TIMx Timer instance
02545   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02546   */
02547 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)
02548 {
02549   return (uint32_t)(READ_REG(TIMx->CCR3));
02550 }
02551
02552 /**
02553   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
02554   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02555   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02556   *       whether or not a timer instance supports a 32 bits counter.
02557   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02558   *       output channel 4 is supported by a timer instance.
02559   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
02560   * @param  TIMx Timer instance
02561   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02562   */
02563 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)
02564 {
02565   return (uint32_t)(READ_REG(TIMx->CCR4));
02566 }
02567
02568 /**
02569   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
02570   * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02571   *       output channel 5 is supported by a timer instance.
02572   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
02573   * @param  TIMx Timer instance
02574   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02575   */
02576 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef * TIMx)
02577 {
02578   return (uint32_t)(READ_REG(TIMx->CCR5));
02579 }
02580
02581 /**
02582   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
02583   * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02584   *       output channel 6 is supported by a timer instance.
02585   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
02586   * @param  TIMx Timer instance
02587   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02588   */
02589 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef * TIMx)
02590 {
02591   return (uint32_t)(READ_REG(TIMx->CCR6));
02592 }
02593
02594 /**
02595   * @brief  Select on which reference signal the OC5REF is combined to.
02596   * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
02597   *       whether or not a timer instance supports the combined 3-phase PWM mode.
02598   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
02599   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
02600   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
02601   * @param  TIMx Timer instance
02602   * @param  GroupCH5 This parameter can be one of the following values:
02603   *         @arg @ref LL_TIM_GROUPCH5_NONE
02604   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
02605   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
02606   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
02607   * @retval None
02608   */
02609 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx, uint32_t GroupCH5)
02610 {
02611   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
02612 }
02613
02614 /**
02615   * @}
02616   */
02617
02618 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
02619   * @{
02620   */
02621 /**
02622   * @brief  Configure input channel.
02623   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
02624   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
02625   *         CCMR1        IC1F          LL_TIM_IC_Config\n
02626   *         CCMR1        CC2S          LL_TIM_IC_Config\n
02627   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
02628   *         CCMR1        IC2F          LL_TIM_IC_Config\n
02629   *         CCMR2        CC3S          LL_TIM_IC_Config\n
02630   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
02631   *         CCMR2        IC3F          LL_TIM_IC_Config\n
02632   *         CCMR2        CC4S          LL_TIM_IC_Config\n
02633   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
02634   *         CCMR2        IC4F          LL_TIM_IC_Config\n
02635   *         CCER         CC1P          LL_TIM_IC_Config\n
02636   *         CCER         CC1NP         LL_TIM_IC_Config\n
02637   *         CCER         CC2P          LL_TIM_IC_Config\n
02638   *         CCER         CC2NP         LL_TIM_IC_Config\n
02639   *         CCER         CC3P          LL_TIM_IC_Config\n
02640   *         CCER         CC3NP         LL_TIM_IC_Config\n
02641   *         CCER         CC4P          LL_TIM_IC_Config\n
02642   *         CCER         CC4NP         LL_TIM_IC_Config
02643   * @param  TIMx Timer instance
02644   * @param  Channel This parameter can be one of the following values:
02645   *         @arg @ref LL_TIM_CHANNEL_CH1
02646   *         @arg @ref LL_TIM_CHANNEL_CH2
02647   *         @arg @ref LL_TIM_CHANNEL_CH3
02648   *         @arg @ref LL_TIM_CHANNEL_CH4
02649   * @param  Configuration This parameter must be a combination of all the following values:
02650   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
02651   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
02652   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
02653   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
02654   * @retval None
02655   */
02656 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration)
02657 {
02658   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02659   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02660   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),  ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
02661   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),  (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
02662 }
02663
02664 /**
02665   * @brief  Set the active input.
02666   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
02667   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
02668   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
02669   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
02670   * @param  TIMx Timer instance
02671   * @param  Channel This parameter can be one of the following values:
02672   *         @arg @ref LL_TIM_CHANNEL_CH1
02673   *         @arg @ref LL_TIM_CHANNEL_CH2
02674   *         @arg @ref LL_TIM_CHANNEL_CH3
02675   *         @arg @ref LL_TIM_CHANNEL_CH4
02676   * @param  ICActiveInput This parameter can be one of the following values:
02677   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02678   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02679   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02680   * @retval None
02681   */
02682 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICActiveInput)
02683 {
02684   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02685   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02686   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),  (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02687 }
02688
02689 /**
02690   * @brief  Get the current active input.
02691   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
02692   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
02693   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
02694   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
02695   * @param  TIMx Timer instance
02696   * @param  Channel This parameter can be one of the following values:
02697   *         @arg @ref LL_TIM_CHANNEL_CH1
02698   *         @arg @ref LL_TIM_CHANNEL_CH2
02699   *         @arg @ref LL_TIM_CHANNEL_CH3
02700   *         @arg @ref LL_TIM_CHANNEL_CH4
02701   * @retval Returned value can be one of the following values:
02702   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02703   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02704   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02705   */
02706 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel)
02707 {
02708   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02709   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02710   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02711 }
02712
02713 /**
02714   * @brief  Set the prescaler of input channel.
02715   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
02716   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
02717   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
02718   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
02719   * @param  TIMx Timer instance
02720   * @param  Channel This parameter can be one of the following values:
02721   *         @arg @ref LL_TIM_CHANNEL_CH1
02722   *         @arg @ref LL_TIM_CHANNEL_CH2
02723   *         @arg @ref LL_TIM_CHANNEL_CH3
02724   *         @arg @ref LL_TIM_CHANNEL_CH4
02725   * @param  ICPrescaler This parameter can be one of the following values:
02726   *         @arg @ref LL_TIM_ICPSC_DIV1
02727   *         @arg @ref LL_TIM_ICPSC_DIV2
02728   *         @arg @ref LL_TIM_ICPSC_DIV4
02729   *         @arg @ref LL_TIM_ICPSC_DIV8
02730   * @retval None
02731   */
02732 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPrescaler)
02733 {
02734   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02735   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02736   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]),  (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02737 }
02738
02739 /**
02740   * @brief  Get the current prescaler value acting on an  input channel.
02741   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
02742   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
02743   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
02744   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
02745   * @param  TIMx Timer instance
02746   * @param  Channel This parameter can be one of the following values:
02747   *         @arg @ref LL_TIM_CHANNEL_CH1
02748   *         @arg @ref LL_TIM_CHANNEL_CH2
02749   *         @arg @ref LL_TIM_CHANNEL_CH3
02750   *         @arg @ref LL_TIM_CHANNEL_CH4
02751   * @retval Returned value can be one of the following values:
02752   *         @arg @ref LL_TIM_ICPSC_DIV1
02753   *         @arg @ref LL_TIM_ICPSC_DIV2
02754   *         @arg @ref LL_TIM_ICPSC_DIV4
02755   *         @arg @ref LL_TIM_ICPSC_DIV8
02756   */
02757 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel)
02758 {
02759   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02760   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02761   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02762 }
02763
02764 /**
02765   * @brief  Set the input filter duration.
02766   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
02767   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
02768   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
02769   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
02770   * @param  TIMx Timer instance
02771   * @param  Channel This parameter can be one of the following values:
02772   *         @arg @ref LL_TIM_CHANNEL_CH1
02773   *         @arg @ref LL_TIM_CHANNEL_CH2
02774   *         @arg @ref LL_TIM_CHANNEL_CH3
02775   *         @arg @ref LL_TIM_CHANNEL_CH4
02776   * @param  ICFilter This parameter can be one of the following values:
02777   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02778   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02779   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02780   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02781   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02782   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02783   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02784   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02785   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02786   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02787   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02788   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02789   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02790   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02791   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02792   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02793   * @retval None
02794   */
02795 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICFilter)
02796 {
02797   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02798   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02799   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]),  (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02800 }
02801
02802 /**
02803   * @brief  Get the input filter duration.
02804   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
02805   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
02806   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
02807   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
02808   * @param  TIMx Timer instance
02809   * @param  Channel This parameter can be one of the following values:
02810   *         @arg @ref LL_TIM_CHANNEL_CH1
02811   *         @arg @ref LL_TIM_CHANNEL_CH2
02812   *         @arg @ref LL_TIM_CHANNEL_CH3
02813   *         @arg @ref LL_TIM_CHANNEL_CH4
02814   * @retval Returned value can be one of the following values:
02815   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02816   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02817   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02818   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02819   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02820   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02821   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02822   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02823   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02824   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02825   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02826   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02827   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02828   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02829   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02830   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02831   */
02832 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx, uint32_t Channel)
02833 {
02834   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02835   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
02836   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U );
02837 }
02838
02839 /**
02840   * @brief  Set the input channel polarity.
02841   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
02842   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
02843   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
02844   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
02845   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
02846   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
02847   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
02848   *         CCER         CC4NP         LL_TIM_IC_SetPolarity
02849   * @param  TIMx Timer instance
02850   * @param  Channel This parameter can be one of the following values:
02851   *         @arg @ref LL_TIM_CHANNEL_CH1
02852   *         @arg @ref LL_TIM_CHANNEL_CH2
02853   *         @arg @ref LL_TIM_CHANNEL_CH3
02854   *         @arg @ref LL_TIM_CHANNEL_CH4
02855   * @param  ICPolarity This parameter can be one of the following values:
02856   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02857   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02858   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
02859   * @retval None
02860   */
02861 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPolarity)
02862 {
02863   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02864   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),  ICPolarity << SHIFT_TAB_CCxP[iChannel]);
02865 }
02866
02867 /**
02868   * @brief  Get the current input channel polarity.
02869   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
02870   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
02871   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
02872   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
02873   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
02874   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
02875   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
02876   *         CCER         CC4NP         LL_TIM_IC_GetPolarity
02877   * @param  TIMx Timer instance
02878   * @param  Channel This parameter can be one of the following values:
02879   *         @arg @ref LL_TIM_CHANNEL_CH1
02880   *         @arg @ref LL_TIM_CHANNEL_CH2
02881   *         @arg @ref LL_TIM_CHANNEL_CH3
02882   *         @arg @ref LL_TIM_CHANNEL_CH4
02883   * @retval Returned value can be one of the following values:
02884   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02885   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02886   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
02887   */
02888 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel)
02889 {
02890   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02891   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
02892 }
02893
02894 /**
02895   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
02896   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02897   *       a timer instance provides an XOR input.
02898   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
02899   * @param  TIMx Timer instance
02900   * @retval None
02901   */
02902 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)
02903 {
02904   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
02905 }
02906
02907 /**
02908   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
02909   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02910   *       a timer instance provides an XOR input.
02911   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
02912   * @param  TIMx Timer instance
02913   * @retval None
02914   */
02915 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)
02916 {
02917   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
02918 }
02919
02920 /**
02921   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
02922   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02923   * a timer instance provides an XOR input.
02924   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
02925   * @param  TIMx Timer instance
02926   * @retval State of bit (1 or 0).
02927   */
02928 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)
02929 {
02930   return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
02931 }
02932
02933 /**
02934   * @brief  Get captured value for input channel 1.
02935   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02936   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02937   *       whether or not a timer instance supports a 32 bits counter.
02938   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02939   *       input channel 1 is supported by a timer instance.
02940   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
02941   * @param  TIMx Timer instance
02942   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02943   */
02944 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)
02945 {
02946   return (uint32_t)(READ_REG(TIMx->CCR1));
02947 }
02948
02949 /**
02950   * @brief  Get captured value for input channel 2.
02951   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02952   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02953   *       whether or not a timer instance supports a 32 bits counter.
02954   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02955   *       input channel 2 is supported by a timer instance.
02956   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
02957   * @param  TIMx Timer instance
02958   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02959   */
02960 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)
02961 {
02962   return (uint32_t)(READ_REG(TIMx->CCR2));
02963 }
02964
02965 /**
02966   * @brief  Get captured value for input channel 3.
02967   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02968   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02969   *       whether or not a timer instance supports a 32 bits counter.
02970   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02971   *       input channel 3 is supported by a timer instance.
02972   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
02973   * @param  TIMx Timer instance
02974   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02975   */
02976 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)
02977 {
02978   return (uint32_t)(READ_REG(TIMx->CCR3));
02979 }
02980
02981 /**
02982   * @brief  Get captured value for input channel 4.
02983   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02984   * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02985   *       whether or not a timer instance supports a 32 bits counter.
02986   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02987   *       input channel 4 is supported by a timer instance.
02988   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
02989   * @param  TIMx Timer instance
02990   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02991   */
02992 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)
02993 {
02994   return (uint32_t)(READ_REG(TIMx->CCR4));
02995 }
02996
02997 /**
02998   * @}
02999   */
03000
03001 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
03002   * @{
03003   */
03004 /**
03005   * @brief  Enable external clock mode 2.
03006   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
03007   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03008   *       whether or not a timer instance supports external clock mode2.
03009   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
03010   * @param  TIMx Timer instance
03011   * @retval None
03012   */
03013 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)
03014 {
03015   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03016 }
03017
03018 /**
03019   * @brief  Disable external clock mode 2.
03020   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03021   *       whether or not a timer instance supports external clock mode2.
03022   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
03023   * @param  TIMx Timer instance
03024   * @retval None
03025   */
03026 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)
03027 {
03028   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03029 }
03030
03031 /**
03032   * @brief  Indicate whether external clock mode 2 is enabled.
03033   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03034   *       whether or not a timer instance supports external clock mode2.
03035   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
03036   * @param  TIMx Timer instance
03037   * @retval State of bit (1 or 0).
03038   */
03039 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)
03040 {
03041   return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
03042 }
03043
03044 /**
03045   * @brief  Set the clock source of the counter clock.
03046   * @note when selected clock source is external clock mode 1, the timer input
03047   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
03048   *       function. This timer input must be configured by calling
03049   *       the @ref LL_TIM_IC_Config() function.
03050   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
03051   *       whether or not a timer instance supports external clock mode1.
03052   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03053   *       whether or not a timer instance supports external clock mode2.
03054   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
03055   *         SMCR         ECE           LL_TIM_SetClockSource
03056   * @param  TIMx Timer instance
03057   * @param  ClockSource This parameter can be one of the following values:
03058   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
03059   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
03060   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
03061   * @retval None
03062   */
03063 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef * TIMx, uint32_t ClockSource)
03064 {
03065   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
03066 }
03067
03068 /**
03069   * @brief  Set the encoder interface mode.
03070   * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
03071   *       whether or not a timer instance supports the encoder mode.
03072   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
03073   * @param  TIMx Timer instance
03074   * @param  EncoderMode This parameter can be one of the following values:
03075   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
03076   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
03077   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
03078   * @retval None
03079   */
03080 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx, uint32_t EncoderMode)
03081 {
03082   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
03083 }
03084
03085 /**
03086   * @}
03087   */
03088
03089 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
03090   * @{
03091   */
03092 /**
03093   * @brief  Set the trigger output (TRGO) used for timer synchronization .
03094   * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
03095   *       whether or not a timer instance can operate as a master timer.
03096   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
03097   * @param  TIMx Timer instance
03098   * @param  TimerSynchronization This parameter can be one of the following values:
03099   *         @arg @ref LL_TIM_TRGO_RESET
03100   *         @arg @ref LL_TIM_TRGO_ENABLE
03101   *         @arg @ref LL_TIM_TRGO_UPDATE
03102   *         @arg @ref LL_TIM_TRGO_CC1IF
03103   *         @arg @ref LL_TIM_TRGO_OC1REF
03104   *         @arg @ref LL_TIM_TRGO_OC2REF
03105   *         @arg @ref LL_TIM_TRGO_OC3REF
03106   *         @arg @ref LL_TIM_TRGO_OC4REF
03107   * @retval None
03108   */
03109 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx, uint32_t TimerSynchronization)
03110 {
03111   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
03112 }
03113
03114 /**
03115   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
03116   * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
03117   *       whether or not a timer instance can be used for ADC synchronization.
03118   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
03119   * @param  TIMx Timer Instance
03120   * @param  ADCSynchronization This parameter can be one of the following values:
03121   *         @arg @ref LL_TIM_TRGO2_RESET
03122   *         @arg @ref LL_TIM_TRGO2_ENABLE
03123   *         @arg @ref LL_TIM_TRGO2_UPDATE
03124   *         @arg @ref LL_TIM_TRGO2_CC1F
03125   *         @arg @ref LL_TIM_TRGO2_OC1
03126   *         @arg @ref LL_TIM_TRGO2_OC2
03127   *         @arg @ref LL_TIM_TRGO2_OC3
03128   *         @arg @ref LL_TIM_TRGO2_OC4
03129   *         @arg @ref LL_TIM_TRGO2_OC5
03130   *         @arg @ref LL_TIM_TRGO2_OC6
03131   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
03132   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
03133   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
03134   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
03135   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
03136   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
03137   * @retval None
03138   */
03139 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx, uint32_t ADCSynchronization)
03140 {
03141   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
03142 }
03143
03144 /**
03145   * @brief  Set the synchronization mode of a slave timer.
03146   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03147   *       a timer instance can operate as a slave timer.
03148   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
03149   * @param  TIMx Timer instance
03150   * @param  SlaveMode This parameter can be one of the following values:
03151   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
03152   *         @arg @ref LL_TIM_SLAVEMODE_RESET
03153   *         @arg @ref LL_TIM_SLAVEMODE_GATED
03154   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
03155   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
03156   * @retval None
03157   */
03158 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx, uint32_t SlaveMode)
03159 {
03160   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
03161 }
03162
03163 /**
03164   * @brief  Set the selects the trigger input to be used to synchronize the counter.
03165   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03166   *       a timer instance can operate as a slave timer.
03167   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
03168   * @param  TIMx Timer instance
03169   * @param  TriggerInput This parameter can be one of the following values:
03170   *         @arg @ref LL_TIM_TS_ITR0
03171   *         @arg @ref LL_TIM_TS_ITR1
03172   *         @arg @ref LL_TIM_TS_ITR2
03173   *         @arg @ref LL_TIM_TS_ITR3
03174   *         @arg @ref LL_TIM_TS_TI1F_ED
03175   *         @arg @ref LL_TIM_TS_TI1FP1
03176   *         @arg @ref LL_TIM_TS_TI2FP2
03177   *         @arg @ref LL_TIM_TS_ETRF
03178   * @retval None
03179   */
03180 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx, uint32_t TriggerInput)
03181 {
03182   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
03183 }
03184
03185 /**
03186   * @brief  Enable the Master/Slave mode.
03187   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03188   *       a timer instance can operate as a slave timer.
03189   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
03190   * @param  TIMx Timer instance
03191   * @retval None
03192   */
03193 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)
03194 {
03195   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03196 }
03197
03198 /**
03199   * @brief  Disable the Master/Slave mode.
03200   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03201   *       a timer instance can operate as a slave timer.
03202   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
03203   * @param  TIMx Timer instance
03204   * @retval None
03205   */
03206 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)
03207 {
03208   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03209 }
03210
03211 /**
03212   * @brief Indicates whether the Master/Slave mode is enabled.
03213   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03214   * a timer instance can operate as a slave timer.
03215   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
03216   * @param  TIMx Timer instance
03217   * @retval State of bit (1 or 0).
03218   */
03219 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)
03220 {
03221   return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
03222 }
03223
03224 /**
03225   * @brief  Configure the external trigger (ETR) input.
03226   * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
03227   *       a timer instance provides an external trigger input.
03228   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
03229   *         SMCR         ETPS          LL_TIM_ConfigETR\n
03230   *         SMCR         ETF           LL_TIM_ConfigETR
03231   * @param  TIMx Timer instance
03232   * @param  ETRPolarity This parameter can be one of the following values:
03233   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
03234   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
03235   * @param  ETRPrescaler This parameter can be one of the following values:
03236   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
03237   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
03238   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
03239   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
03240   * @param  ETRFilter This parameter can be one of the following values:
03241   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
03242   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
03243   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
03244   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
03245   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
03246   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
03247   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
03248   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
03249   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
03250   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
03251   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
03252   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
03253   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
03254   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
03255   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
03256   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
03257   * @retval None
03258   */
03259 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef * TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
03260 {
03261   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
03262 }
03263
03264 /**
03265   * @brief  Select the external trigger (ETR) input source.
03266   * @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
03267   *       not a timer instance supports ETR source selection.
03268   * @rmtoll OR2          ETRSEL        LL_TIM_SetETRSource
03269   * @param  TIMx Timer instance
03270   * @param  ETRSource This parameter can be one of the following values:
03271   *         @arg @ref LL_TIM_ETRSOURCE_LEGACY
03272   *         @arg @ref LL_TIM_ETRSOURCE_COMP1
03273   *         @arg @ref LL_TIM_ETRSOURCE_COMP2
03274   * @retval None
03275   */
03276 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef * TIMx, uint32_t ETRSource)
03277 {
03278
03279   MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
03280 }
03281
03282 /**
03283   * @}
03284   */
03285
03286 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
03287   * @{
03288   */
03289 /**
03290   * @brief  Enable the break function.
03291   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03292   *       a timer instance provides a break input.
03293   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
03294   * @param  TIMx Timer instance
03295   * @retval None
03296   */
03297 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef * TIMx)
03298 {
03299   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03300 }
03301
03302 /**
03303   * @brief  Disable the break function.
03304   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
03305   * @param  TIMx Timer instance
03306   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03307   *       a timer instance provides a break input.
03308   * @retval None
03309   */
03310 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef * TIMx)
03311 {
03312   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03313 }
03314
03315 /**
03316   * @brief  Configure the break input.
03317   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03318   *       a timer instance provides a break input.
03319   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
03320   *         BDTR         BKF           LL_TIM_ConfigBRK
03321   * @param  TIMx Timer instance
03322   * @param  BreakPolarity This parameter can be one of the following values:
03323   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
03324   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
03325   * @param  BreakFilter This parameter can be one of the following values:
03326   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
03327   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
03328   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
03329   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
03330   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
03331   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
03332   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
03333   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
03334   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
03335   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
03336   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
03337   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
03338   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
03339   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
03340   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
03341   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
03342   * @retval None
03343   */
03344 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef * TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
03345 {
03346   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
03347 }
03348
03349 /**
03350   * @brief  Enable the break 2 function.
03351   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03352   *       a timer instance provides a second break input.
03353   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
03354   * @param  TIMx Timer instance
03355   * @retval None
03356   */
03357 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)
03358 {
03359   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03360 }
03361
03362 /**
03363   * @brief  Disable the break  2 function.
03364   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03365   *       a timer instance provides a second break input.
03366   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
03367   * @param  TIMx Timer instance
03368   * @retval None
03369   */
03370 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)
03371 {
03372   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03373 }
03374
03375 /**
03376   * @brief  Configure the break 2 input.
03377   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03378   *       a timer instance provides a second break input.
03379   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
03380   *         BDTR         BK2F          LL_TIM_ConfigBRK2
03381   * @param  TIMx Timer instance
03382   * @param  Break2Polarity This parameter can be one of the following values:
03383   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
03384   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
03385   * @param  Break2Filter This parameter can be one of the following values:
03386   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
03387   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
03388   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
03389   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
03390   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
03391   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
03392   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
03393   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
03394   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
03395   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
03396   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
03397   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
03398   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
03399   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
03400   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
03401   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
03402   * @retval None
03403   */
03404 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
03405 {
03406   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
03407 }
03408
03409 /**
03410   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
03411   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03412   *       a timer instance provides a break input.
03413   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
03414   *         BDTR         OSSR          LL_TIM_SetOffStates
03415   * @param  TIMx Timer instance
03416   * @param  OffStateIdle This parameter can be one of the following values:
03417   *         @arg @ref LL_TIM_OSSI_DISABLE
03418   *         @arg @ref LL_TIM_OSSI_ENABLE
03419   * @param  OffStateRun This parameter can be one of the following values:
03420   *         @arg @ref LL_TIM_OSSR_DISABLE
03421   *         @arg @ref LL_TIM_OSSR_ENABLE
03422   * @retval None
03423   */
03424 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef * TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
03425 {
03426   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
03427 }
03428
03429 /**
03430   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
03431   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03432   *       a timer instance provides a break input.
03433   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
03434   * @param  TIMx Timer instance
03435   * @retval None
03436   */
03437 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)
03438 {
03439   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03440 }
03441
03442 /**
03443   * @brief  Disable automatic output (MOE can be set only by software).
03444   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03445   *       a timer instance provides a break input.
03446   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
03447   * @param  TIMx Timer instance
03448   * @retval None
03449   */
03450 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)
03451 {
03452   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03453 }
03454
03455 /**
03456   * @brief  Indicate whether automatic output is enabled.
03457   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03458   *       a timer instance provides a break input.
03459   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
03460   * @param  TIMx Timer instance
03461   * @retval State of bit (1 or 0).
03462   */
03463 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)
03464 {
03465   return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
03466 }
03467
03468 /**
03469   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
03470   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03471   *       software and is reset in case of break or break2 event
03472   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03473   *       a timer instance provides a break input.
03474   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
03475   * @param  TIMx Timer instance
03476   * @retval None
03477   */
03478 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)
03479 {
03480   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03481 }
03482
03483 /**
03484   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
03485   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03486   *       software and is reset in case of break or break2 event.
03487   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03488   *       a timer instance provides a break input.
03489   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
03490   * @param  TIMx Timer instance
03491   * @retval None
03492   */
03493 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)
03494 {
03495   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03496 }
03497
03498 /**
03499   * @brief  Indicates whether outputs are enabled.
03500   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03501   *       a timer instance provides a break input.
03502   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
03503   * @param  TIMx Timer instance
03504   * @retval State of bit (1 or 0).
03505   */
03506 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)
03507 {
03508   return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
03509 }
03510
03511 /**
03512   * @brief  Enable the signals connected to the designated timer break input.
03513   * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03514   *       or not a timer instance allows for break input selection.
03515   * @rmtoll OR2          BKINE         LL_TIM_EnableBreakInputSource\n
03516   *         OR2          BKCMP1E       LL_TIM_EnableBreakInputSource\n
03517   *         OR2          BKCMP2E       LL_TIM_EnableBreakInputSource\n
03518   *         OR2          BKDFBK0E      LL_TIM_EnableBreakInputSource\n
03519   *         OR3          BKINE         LL_TIM_EnableBreakInputSource\n
03520   *         OR3          BKCMP1E       LL_TIM_EnableBreakInputSource\n
03521   *         OR3          BKCMP2E       LL_TIM_EnableBreakInputSource\n
03522   *         OR3          BKDFBK0E      LL_TIM_EnableBreakInputSource
03523   * @param  TIMx Timer instance
03524   * @param  BreakInput This parameter can be one of the following values:
03525   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03526   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03527   * @param  Source This parameter can be one of the following values:
03528   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03529   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03530   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03531   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
03532   * @retval None
03533   */
03534 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source)
03535 {
03536   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
03537   SET_BIT(*pReg , Source);
03538 }
03539
03540 /**
03541   * @brief  Disable the signals connected to the designated timer break input.
03542   * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03543   *       or not a timer instance allows for break input selection.
03544   * @rmtoll OR2          BKINE         LL_TIM_DisableBreakInputSource\n
03545   *         OR2          BKCMP1E       LL_TIM_DisableBreakInputSource\n
03546   *         OR2          BKCMP2E       LL_TIM_DisableBreakInputSource\n
03547   *         OR2          BKDFBK0E      LL_TIM_DisableBreakInputSource\n
03548   *         OR3          BKINE         LL_TIM_DisableBreakInputSource\n
03549   *         OR3          BKCMP1E       LL_TIM_DisableBreakInputSource\n
03550   *         OR3          BKCMP2E       LL_TIM_DisableBreakInputSource\n
03551   *         OR3          BKDFBK0E      LL_TIM_DisableBreakInputSource
03552   * @param  TIMx Timer instance
03553   * @param  BreakInput This parameter can be one of the following values:
03554   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03555   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03556   * @param  Source This parameter can be one of the following values:
03557   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03558   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03559   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03560   *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
03561   * @retval None
03562   */
03563 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source)
03564 {
03565   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
03566   CLEAR_BIT(*pReg, Source);
03567 }
03568
03569 /**
03570   * @brief  Set the polarity of the break signal for the timer break input.
03571   * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03572   *       or not a timer instance allows for break input selection.
03573   * @rmtoll OR2          BKINE         LL_TIM_SetBreakInputSourcePolarity\n
03574   *         OR2          BKCMP1E       LL_TIM_SetBreakInputSourcePolarity\n
03575   *         OR2          BKCMP2E       LL_TIM_SetBreakInputSourcePolarity\n
03576   *         OR2          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
03577   *         OR3          BKINE         LL_TIM_SetBreakInputSourcePolarity\n
03578   *         OR3          BKCMP1E       LL_TIM_SetBreakInputSourcePolarity\n
03579   *         OR3          BKCMP2E       LL_TIM_SetBreakInputSourcePolarity\n
03580   *         OR3          BKINP         LL_TIM_SetBreakInputSourcePolarity
03581   * @param  TIMx Timer instance
03582   * @param  BreakInput This parameter can be one of the following values:
03583   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03584   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03585   * @param  Source This parameter can be one of the following values:
03586   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03587   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
03588   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
03589   * @param  Polarity This parameter can be one of the following values:
03590   *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
03591   *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
03592   * @retval None
03593   */
03594 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
03595 {
03596   register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
03597   MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (POSITION_VAL(Source))) , (Polarity << (POSITION_VAL(Source))));
03598 }
03599
03600 /**
03601   * @}
03602   */
03603
03604 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
03605   * @{
03606   */
03607 /**
03608   * @brief  Configures the timer DMA burst feature.
03609   * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
03610   *       not a timer instance supports the DMA burst mode.
03611   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
03612   *         DCR          DBA           LL_TIM_ConfigDMABurst
03613   * @param  TIMx Timer instance
03614   * @param  DMABurstBaseAddress This parameter can be one of the following values:
03615   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
03616   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
03617   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
03618   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
03619   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
03620   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
03621   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
03622   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
03623   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
03624   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
03625   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
03626   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
03627   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
03628   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
03629   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
03630   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
03631   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
03632   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
03633   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
03634   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
03635   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
03636   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
03637   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
03638   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
03639   * @param  DMABurstLength This parameter can be one of the following values:
03640   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
03641   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
03642   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
03643   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
03644   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
03645   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
03646   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
03647   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
03648   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
03649   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
03650   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
03651   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
03652   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
03653   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
03654   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
03655   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
03656   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
03657   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
03658   * @retval None
03659   */
03660 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
03661 {
03662   MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
03663 }
03664
03665 /**
03666   * @}
03667   */
03668
03669 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
03670   * @{
03671   */
03672 /**
03673   * @brief  Remap TIM inputs (input channel, internal/external triggers).
03674   * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
03675   *       a some timer inputs can be remapped.
03676   * @rmtoll TIM1_OR1    ETR_ADC1_RMP      LL_TIM_SetRemap\n
03677   *         TIM1_OR1    ETR_ADC3_RMP      LL_TIM_SetRemap\n
03678   *         TIM1_OR1    TI1_RMP           LL_TIM_SetRemap\n
03679   *         TIM8_OR1    ETR_ADC2_RMP      LL_TIM_SetRemap\n
03680   *         TIM8_OR1    ETR_ADC3_RMP      LL_TIM_SetRemap\n
03681   *         TIM8_OR1    TI1_RMP           LL_TIM_SetRemap\n
03682   *         TIM2_OR1    ITR1_RMP          LL_TIM_SetRemap\n
03683   *         TIM2_OR1    TI4_RMP           LL_TIM_SetRemap\n
03684   *         TIM2_OR1    TI1_RMP           LL_TIM_SetRemap\n
03685   *         TIM3_OR1    TI1_RMP           LL_TIM_SetRemap\n
03686   *         TIM15_OR1   TI1_RMP           LL_TIM_SetRemap\n
03687   *         TIM15_OR1   ENCODER_MODE      LL_TIM_SetRemap\n
03688   *         TIM16_OR1   TI1_RMP           LL_TIM_SetRemap\n
03689   *         TIM17_OR1   TI1_RMP           LL_TIM_SetRemap
03690  * @param  TIMx Timer instance
03691   * @param  Remap Remap param depends on the TIMx. Description available only
03692   *         in CHM version of the User Manual (not in .pdf).
03693   *         Otherwise see Reference Manual description of OR registers.
03694   *
03695   *         Below description summarizes "Timer Instance" and "Remap" param combinations:
03696   *
03697   *         TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
03698   *
03699   *            . . ADC1_RMP can be one of the following values
03700   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
03701   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
03702   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
03703   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
03704   *
03705   *            . . ADC3_RMP can be one of the following values
03706   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
03707   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
03708   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
03709   *            @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
03710   *
03711   *            . . TI1_RMP can be one of the following values
03712   *            @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
03713   *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
03714   *
03715   *         TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
03716   *
03717   *            ITR1_RMP can be one of the following values
03718   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
03719   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
03720   *
03721   *            . . ETR1_RMP can be one of the following values
03722   *            @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
03723   *            @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
03724   *
03725   *            . . TI4_RMP can be one of the following values
03726   *            @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
03727   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
03728   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
03729   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
03730   *
03731   *         TIM3: one of the following values
03732   *
03733   *            @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
03734   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
03735   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
03736   *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
03737   *
03738   *         TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
03739   *
03740   *            . . ADC1_RMP can be one of the following values
03741   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
03742   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
03743   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
03744   *            @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
03745   *
03746   *            . . ADC3_RMP can be one of the following values
03747   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
03748   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
03749   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
03750   *            @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
03751   *
03752   *            . . TI1_RMP can be one of the following values
03753   *            @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
03754   *            @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
03755   *
03756   *         TIM15: any combination of TI1_RMP, ENCODER_MODE where
03757   *
03758   *            . . TI1_RMP can be one of the following values
03759   *            @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
03760   *            @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
03761   *
03762   *            . . ENCODER_MODE can be one of the following values
03763   *            @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
03764   *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
03765   *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
03766   *            @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
03767   *
03768   *         TIM16: one of the following values
03769   *
03770   *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
03771   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
03772   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
03773   *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
03774   *            @arg @ref LL_TIM_TIM16_TI1_RMP_MSI (*)
03775   *            @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 (*)
03776   *            @arg @ref LL_TIM_TIM16_TI1_RMP_MCO (*)
03777   *
03778   *         TIM17: one of the following values
03779   *
03780   *            @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
03781   *            @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
03782   *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
03783   *            @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
03784   *
03785   *         (*) Value not defined in all devices. \n
03786   * @retval None
03787   */
03788 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef * TIMx, uint32_t Remap)
03789 {
03790   MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
03791 }
03792
03793 /**
03794   * @}
03795   */
03796
03797 #if defined(TIM_SMCR_OCCS)
03798 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
03799   * @{
03800   */
03801 /**
03802   * @brief  Set the OCREF clear source
03803   * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
03804   * @note This function can only be used in Output compare and PWM modes.
03805   * @rmtoll SMCR          OCCS           LL_TIM_SetOCRefClearInputSource
03806   * @param  TIMx Timer instance
03807   * @param  OCRefClearInputSource This parameter can be one of the following values:
03808   *         @arg @ref LL_TIM_OCREF_CLR_INT_NC
03809   *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
03810   * @retval None
03811   */
03812
03813 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx, uint32_t OCRefClearInputSource)
03814 {
03815   MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
03816 }
03817 /**
03818   * @}
03819   */
03820
03821 #endif /* TIM_SMCR_OCCS */
03822 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
03823   * @{
03824   */
03825 /**
03826   * @brief  Clear the update interrupt flag (UIF).
03827   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
03828   * @param  TIMx Timer instance
03829   * @retval None
03830   */
03831 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)
03832 {
03833   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
03834 }
03835
03836 /**
03837   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
03838   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
03839   * @param  TIMx Timer instance
03840   * @retval State of bit (1 or 0).
03841   */
03842 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)
03843 {
03844   return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
03845 }
03846
03847 /**
03848   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
03849   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
03850   * @param  TIMx Timer instance
03851   * @retval None
03852   */
03853 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)
03854 {
03855   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
03856 }
03857
03858 /**
03859   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
03860   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
03861   * @param  TIMx Timer instance
03862   * @retval State of bit (1 or 0).
03863   */
03864 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)
03865 {
03866   return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
03867 }
03868
03869 /**
03870   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
03871   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
03872   * @param  TIMx Timer instance
03873   * @retval None
03874   */
03875 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)
03876 {
03877   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
03878 }
03879
03880 /**
03881   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
03882   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
03883   * @param  TIMx Timer instance
03884   * @retval State of bit (1 or 0).
03885   */
03886 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)
03887 {
03888   return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
03889 }
03890
03891 /**
03892   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
03893   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
03894   * @param  TIMx Timer instance
03895   * @retval None
03896   */
03897 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)
03898 {
03899   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
03900 }
03901
03902 /**
03903   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
03904   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
03905   * @param  TIMx Timer instance
03906   * @retval State of bit (1 or 0).
03907   */
03908 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)
03909 {
03910   return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
03911 }
03912
03913 /**
03914   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
03915   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
03916   * @param  TIMx Timer instance
03917   * @retval None
03918   */
03919 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)
03920 {
03921   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
03922 }
03923
03924 /**
03925   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
03926   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
03927   * @param  TIMx Timer instance
03928   * @retval State of bit (1 or 0).
03929   */
03930 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)
03931 {
03932   return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
03933 }
03934
03935 /**
03936   * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
03937   * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
03938   * @param  TIMx Timer instance
03939   * @retval None
03940   */
03941 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)
03942 {
03943   WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
03944 }
03945
03946 /**
03947   * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
03948   * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
03949   * @param  TIMx Timer instance
03950   * @retval State of bit (1 or 0).
03951   */
03952 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef * TIMx)
03953 {
03954   return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
03955 }
03956
03957 /**
03958   * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
03959   * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
03960   * @param  TIMx Timer instance
03961   * @retval None
03962   */
03963 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)
03964 {
03965   WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
03966 }
03967
03968 /**
03969   * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
03970   * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
03971   * @param  TIMx Timer instance
03972   * @retval State of bit (1 or 0).
03973   */
03974 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef * TIMx)
03975 {
03976   return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
03977 }
03978
03979 /**
03980   * @brief  Clear the commutation interrupt flag (COMIF).
03981   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
03982   * @param  TIMx Timer instance
03983   * @retval None
03984   */
03985 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)
03986 {
03987   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
03988 }
03989
03990 /**
03991   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
03992   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
03993   * @param  TIMx Timer instance
03994   * @retval State of bit (1 or 0).
03995   */
03996 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)
03997 {
03998   return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
03999 }
04000
04001 /**
04002   * @brief  Clear the trigger interrupt flag (TIF).
04003   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
04004   * @param  TIMx Timer instance
04005   * @retval None
04006   */
04007 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)
04008 {
04009   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
04010 }
04011
04012 /**
04013   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
04014   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
04015   * @param  TIMx Timer instance
04016   * @retval State of bit (1 or 0).
04017   */
04018 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)
04019 {
04020   return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
04021 }
04022
04023 /**
04024   * @brief  Clear the break interrupt flag (BIF).
04025   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
04026   * @param  TIMx Timer instance
04027   * @retval None
04028   */
04029 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)
04030 {
04031   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
04032 }
04033
04034 /**
04035   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
04036   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
04037   * @param  TIMx Timer instance
04038   * @retval State of bit (1 or 0).
04039   */
04040 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)
04041 {
04042   return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
04043 }
04044
04045 /**
04046   * @brief  Clear the break 2 interrupt flag (B2IF).
04047   * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
04048   * @param  TIMx Timer instance
04049   * @retval None
04050   */
04051 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)
04052 {
04053   WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
04054 }
04055
04056 /**
04057   * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
04058   * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
04059   * @param  TIMx Timer instance
04060   * @retval State of bit (1 or 0).
04061   */
04062 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef * TIMx)
04063 {
04064   return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
04065 }
04066
04067 /**
04068   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
04069   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
04070   * @param  TIMx Timer instance
04071   * @retval None
04072   */
04073 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)
04074 {
04075   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
04076 }
04077
04078 /**
04079   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
04080   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
04081   * @param  TIMx Timer instance
04082   * @retval State of bit (1 or 0).
04083   */
04084 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)
04085 {
04086   return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
04087 }
04088
04089 /**
04090   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
04091   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
04092   * @param  TIMx Timer instance
04093   * @retval None
04094   */
04095 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)
04096 {
04097   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
04098 }
04099
04100 /**
04101   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
04102   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
04103   * @param  TIMx Timer instance
04104   * @retval State of bit (1 or 0).
04105   */
04106 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)
04107 {
04108   return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
04109 }
04110
04111 /**
04112   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
04113   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
04114   * @param  TIMx Timer instance
04115   * @retval None
04116   */
04117 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)
04118 {
04119   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
04120 }
04121
04122 /**
04123   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
04124   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
04125   * @param  TIMx Timer instance
04126   * @retval State of bit (1 or 0).
04127   */
04128 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)
04129 {
04130   return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
04131 }
04132
04133 /**
04134   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
04135   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
04136   * @param  TIMx Timer instance
04137   * @retval None
04138   */
04139 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)
04140 {
04141   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
04142 }
04143
04144 /**
04145   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
04146   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
04147   * @param  TIMx Timer instance
04148   * @retval State of bit (1 or 0).
04149   */
04150 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)
04151 {
04152   return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
04153 }
04154
04155 /**
04156   * @brief  Clear the system break interrupt flag (SBIF).
04157   * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
04158   * @param  TIMx Timer instance
04159   * @retval None
04160   */
04161 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)
04162 {
04163   WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
04164 }
04165
04166 /**
04167   * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
04168   * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
04169   * @param  TIMx Timer instance
04170   * @retval State of bit (1 or 0).
04171   */
04172 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef * TIMx)
04173 {
04174   return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF));
04175 }
04176
04177 /**
04178   * @}
04179   */
04180
04181 /** @defgroup TIM_LL_EF_IT_Management IT-Management
04182   * @{
04183   */
04184 /**
04185   * @brief  Enable update interrupt (UIE).
04186   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
04187   * @param  TIMx Timer instance
04188   * @retval None
04189   */
04190 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)
04191 {
04192   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
04193 }
04194
04195 /**
04196   * @brief  Disable update interrupt (UIE).
04197   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
04198   * @param  TIMx Timer instance
04199   * @retval None
04200   */
04201 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)
04202 {
04203   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
04204 }
04205
04206 /**
04207   * @brief  Indicates whether the update interrupt (UIE) is enabled.
04208   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
04209   * @param  TIMx Timer instance
04210   * @retval State of bit (1 or 0).
04211   */
04212 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)
04213 {
04214   return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
04215 }
04216
04217 /**
04218   * @brief  Enable capture/compare 1 interrupt (CC1IE).
04219   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
04220   * @param  TIMx Timer instance
04221   * @retval None
04222   */
04223 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)
04224 {
04225   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04226 }
04227
04228 /**
04229   * @brief  Disable capture/compare 1  interrupt (CC1IE).
04230   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
04231   * @param  TIMx Timer instance
04232   * @retval None
04233   */
04234 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)
04235 {
04236   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04237 }
04238
04239 /**
04240   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
04241   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
04242   * @param  TIMx Timer instance
04243   * @retval State of bit (1 or 0).
04244   */
04245 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)
04246 {
04247   return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
04248 }
04249
04250 /**
04251   * @brief  Enable capture/compare 2 interrupt (CC2IE).
04252   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
04253   * @param  TIMx Timer instance
04254   * @retval None
04255   */
04256 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)
04257 {
04258   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04259 }
04260
04261 /**
04262   * @brief  Disable capture/compare 2  interrupt (CC2IE).
04263   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
04264   * @param  TIMx Timer instance
04265   * @retval None
04266   */
04267 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)
04268 {
04269   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04270 }
04271
04272 /**
04273   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
04274   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
04275   * @param  TIMx Timer instance
04276   * @retval State of bit (1 or 0).
04277   */
04278 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)
04279 {
04280   return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
04281 }
04282
04283 /**
04284   * @brief  Enable capture/compare 3 interrupt (CC3IE).
04285   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
04286   * @param  TIMx Timer instance
04287   * @retval None
04288   */
04289 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)
04290 {
04291   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04292 }
04293
04294 /**
04295   * @brief  Disable capture/compare 3  interrupt (CC3IE).
04296   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
04297   * @param  TIMx Timer instance
04298   * @retval None
04299   */
04300 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)
04301 {
04302   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04303 }
04304
04305 /**
04306   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
04307   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
04308   * @param  TIMx Timer instance
04309   * @retval State of bit (1 or 0).
04310   */
04311 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)
04312 {
04313   return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
04314 }
04315
04316 /**
04317   * @brief  Enable capture/compare 4 interrupt (CC4IE).
04318   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
04319   * @param  TIMx Timer instance
04320   * @retval None
04321   */
04322 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)
04323 {
04324   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04325 }
04326
04327 /**
04328   * @brief  Disable capture/compare 4  interrupt (CC4IE).
04329   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
04330   * @param  TIMx Timer instance
04331   * @retval None
04332   */
04333 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)
04334 {
04335   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04336 }
04337
04338 /**
04339   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
04340   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
04341   * @param  TIMx Timer instance
04342   * @retval State of bit (1 or 0).
04343   */
04344 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)
04345 {
04346   return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
04347 }
04348
04349 /**
04350   * @brief  Enable commutation interrupt (COMIE).
04351   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
04352   * @param  TIMx Timer instance
04353   * @retval None
04354   */
04355 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)
04356 {
04357   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
04358 }
04359
04360 /**
04361   * @brief  Disable commutation interrupt (COMIE).
04362   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
04363   * @param  TIMx Timer instance
04364   * @retval None
04365   */
04366 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)
04367 {
04368   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
04369 }
04370
04371 /**
04372   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
04373   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
04374   * @param  TIMx Timer instance
04375   * @retval State of bit (1 or 0).
04376   */
04377 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)
04378 {
04379   return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
04380 }
04381
04382 /**
04383   * @brief  Enable trigger interrupt (TIE).
04384   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
04385   * @param  TIMx Timer instance
04386   * @retval None
04387   */
04388 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)
04389 {
04390   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
04391 }
04392
04393 /**
04394   * @brief  Disable trigger interrupt (TIE).
04395   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
04396   * @param  TIMx Timer instance
04397   * @retval None
04398   */
04399 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)
04400 {
04401   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
04402 }
04403
04404 /**
04405   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
04406   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
04407   * @param  TIMx Timer instance
04408   * @retval State of bit (1 or 0).
04409   */
04410 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)
04411 {
04412   return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
04413 }
04414
04415 /**
04416   * @brief  Enable break interrupt (BIE).
04417   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
04418   * @param  TIMx Timer instance
04419   * @retval None
04420   */
04421 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)
04422 {
04423   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
04424 }
04425
04426 /**
04427   * @brief  Disable break interrupt (BIE).
04428   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
04429   * @param  TIMx Timer instance
04430   * @retval None
04431   */
04432 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)
04433 {
04434   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
04435 }
04436
04437 /**
04438   * @brief  Indicates whether the break interrupt (BIE) is enabled.
04439   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
04440   * @param  TIMx Timer instance
04441   * @retval State of bit (1 or 0).
04442   */
04443 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)
04444 {
04445   return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
04446 }
04447
04448 /**
04449   * @}
04450   */
04451
04452 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
04453   * @{
04454   */
04455 /**
04456   * @brief  Enable update DMA request (UDE).
04457   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
04458   * @param  TIMx Timer instance
04459   * @retval None
04460   */
04461 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)
04462 {
04463   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
04464 }
04465
04466 /**
04467   * @brief  Disable update DMA request (UDE).
04468   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
04469   * @param  TIMx Timer instance
04470   * @retval None
04471   */
04472 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)
04473 {
04474   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
04475 }
04476
04477 /**
04478   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
04479   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
04480   * @param  TIMx Timer instance
04481   * @retval State of bit (1 or 0).
04482   */
04483 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)
04484 {
04485   return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
04486 }
04487
04488 /**
04489   * @brief  Enable capture/compare 1 DMA request (CC1DE).
04490   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
04491   * @param  TIMx Timer instance
04492   * @retval None
04493   */
04494 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)
04495 {
04496   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04497 }
04498
04499 /**
04500   * @brief  Disable capture/compare 1  DMA request (CC1DE).
04501   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
04502   * @param  TIMx Timer instance
04503   * @retval None
04504   */
04505 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)
04506 {
04507   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04508 }
04509
04510 /**
04511   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
04512   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
04513   * @param  TIMx Timer instance
04514   * @retval State of bit (1 or 0).
04515   */
04516 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)
04517 {
04518   return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
04519 }
04520
04521 /**
04522   * @brief  Enable capture/compare 2 DMA request (CC2DE).
04523   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
04524   * @param  TIMx Timer instance
04525   * @retval None
04526   */
04527 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)
04528 {
04529   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04530 }
04531
04532 /**
04533   * @brief  Disable capture/compare 2  DMA request (CC2DE).
04534   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
04535   * @param  TIMx Timer instance
04536   * @retval None
04537   */
04538 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)
04539 {
04540   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04541 }
04542
04543 /**
04544   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
04545   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
04546   * @param  TIMx Timer instance
04547   * @retval State of bit (1 or 0).
04548   */
04549 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)
04550 {
04551   return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
04552 }
04553
04554 /**
04555   * @brief  Enable capture/compare 3 DMA request (CC3DE).
04556   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
04557   * @param  TIMx Timer instance
04558   * @retval None
04559   */
04560 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)
04561 {
04562   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04563 }
04564
04565 /**
04566   * @brief  Disable capture/compare 3  DMA request (CC3DE).
04567   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
04568   * @param  TIMx Timer instance
04569   * @retval None
04570   */
04571 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)
04572 {
04573   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04574 }
04575
04576 /**
04577   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
04578   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
04579   * @param  TIMx Timer instance
04580   * @retval State of bit (1 or 0).
04581   */
04582 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)
04583 {
04584   return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
04585 }
04586
04587 /**
04588   * @brief  Enable capture/compare 4 DMA request (CC4DE).
04589   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
04590   * @param  TIMx Timer instance
04591   * @retval None
04592   */
04593 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)
04594 {
04595   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04596 }
04597
04598 /**
04599   * @brief  Disable capture/compare 4  DMA request (CC4DE).
04600   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
04601   * @param  TIMx Timer instance
04602   * @retval None
04603   */
04604 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)
04605 {
04606   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04607 }
04608
04609 /**
04610   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
04611   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
04612   * @param  TIMx Timer instance
04613   * @retval State of bit (1 or 0).
04614   */
04615 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)
04616 {
04617   return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
04618 }
04619
04620 /**
04621   * @brief  Enable commutation DMA request (COMDE).
04622   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
04623   * @param  TIMx Timer instance
04624   * @retval None
04625   */
04626 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)
04627 {
04628   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
04629 }
04630
04631 /**
04632   * @brief  Disable commutation DMA request (COMDE).
04633   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
04634   * @param  TIMx Timer instance
04635   * @retval None
04636   */
04637 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)
04638 {
04639   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
04640 }
04641
04642 /**
04643   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
04644   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
04645   * @param  TIMx Timer instance
04646   * @retval State of bit (1 or 0).
04647   */
04648 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)
04649 {
04650   return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
04651 }
04652
04653 /**
04654   * @brief  Enable trigger interrupt (TDE).
04655   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
04656   * @param  TIMx Timer instance
04657   * @retval None
04658   */
04659 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)
04660 {
04661   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
04662 }
04663
04664 /**
04665   * @brief  Disable trigger interrupt (TDE).
04666   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
04667   * @param  TIMx Timer instance
04668   * @retval None
04669   */
04670 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)
04671 {
04672   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
04673 }
04674
04675 /**
04676   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
04677   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
04678   * @param  TIMx Timer instance
04679   * @retval State of bit (1 or 0).
04680   */
04681 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)
04682 {
04683   return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
04684 }
04685
04686 /**
04687   * @}
04688   */
04689
04690 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
04691   * @{
04692   */
04693 /**
04694   * @brief  Generate an update event.
04695   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
04696   * @param  TIMx Timer instance
04697   * @retval None
04698   */
04699 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)
04700 {
04701   SET_BIT(TIMx->EGR, TIM_EGR_UG);
04702 }
04703
04704 /**
04705   * @brief  Generate Capture/Compare 1 event.
04706   * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
04707   * @param  TIMx Timer instance
04708   * @retval None
04709   */
04710 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)
04711 {
04712   SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
04713 }
04714
04715 /**
04716   * @brief  Generate Capture/Compare 2 event.
04717   * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
04718   * @param  TIMx Timer instance
04719   * @retval None
04720   */
04721 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)
04722 {
04723   SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
04724 }
04725
04726 /**
04727   * @brief  Generate Capture/Compare 3 event.
04728   * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
04729   * @param  TIMx Timer instance
04730   * @retval None
04731   */
04732 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)
04733 {
04734   SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
04735 }
04736
04737 /**
04738   * @brief  Generate Capture/Compare 4 event.
04739   * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
04740   * @param  TIMx Timer instance
04741   * @retval None
04742   */
04743 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)
04744 {
04745   SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
04746 }
04747
04748 /**
04749   * @brief  Generate commutation event.
04750   * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
04751   * @param  TIMx Timer instance
04752   * @retval None
04753   */
04754 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)
04755 {
04756   SET_BIT(TIMx->EGR, TIM_EGR_COMG);
04757 }
04758
04759 /**
04760   * @brief  Generate trigger event.
04761   * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
04762   * @param  TIMx Timer instance
04763   * @retval None
04764   */
04765 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)
04766 {
04767   SET_BIT(TIMx->EGR, TIM_EGR_TG);
04768 }
04769
04770 /**
04771   * @brief  Generate break event.
04772   * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
04773   * @param  TIMx Timer instance
04774   * @retval None
04775   */
04776 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)
04777 {
04778   SET_BIT(TIMx->EGR, TIM_EGR_BG);
04779 }
04780
04781 /**
04782   * @brief  Generate break 2 event.
04783   * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
04784   * @param  TIMx Timer instance
04785   * @retval None
04786   */
04787 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)
04788 {
04789   SET_BIT(TIMx->EGR, TIM_EGR_B2G);
04790 }
04791
04792 /**
04793   * @}
04794   */
04795
04796 #if defined(USE_FULL_LL_DRIVER)
04797 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
04798   * @{
04799   */
04800
04801 ErrorStatus LL_TIM_DeInit(TIM_TypeDef* TIMx);
04802 void LL_TIM_StructInit(LL_TIM_InitTypeDef* TIM_InitStruct);
04803 ErrorStatus LL_TIM_Init(TIM_TypeDef* TIMx, LL_TIM_InitTypeDef* TIM_InitStruct);
04804 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct);
04805 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct);
04806 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef* TIM_ICInitStruct);
04807 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef* TIM_IC_InitStruct);
04808 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct);
04809 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef* TIMx, LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct);
04810 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct);
04811 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef* TIMx, LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct);
04812 /**
04813   * @}
04814   */
04815 #endif /* USE_FULL_LL_DRIVER */
04816
04817 /**
04818   * @}
04819   */
04820
04821 /**
04822   * @}
04823   */
04824
04825 #endif /* TIM1 || TIM8 || TIM2 || TIM3 ||  TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
04826
04827 /**
04828   * @}
04829   */
04830
04831 #ifdef __cplusplus
04832 }
04833 #endif
04834
04835 #endif /* __STM32L4xx_LL_TIM_H */
04836
04837 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_usart.c Source File

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stm32l4xx_ll_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_usart.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   USART LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32l4xx_ll_usart.h"
00041 #include "stm32l4xx_ll_rcc.h"
00042 #include "stm32l4xx_ll_bus.h"
00043 #ifdef  USE_FULL_ASSERT
00044 #include "stm32_assert.h"
00045 #else
00046 #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
00054
00055 /** @addtogroup USART_LL
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /** @addtogroup USART_LL_Private_Constants
00063   * @{
00064   */
00065
00066 /**
00067   * @}
00068   */
00069
00070
00071 /* Private macros ------------------------------------------------------------*/
00072 /** @addtogroup USART_LL_Private_Macros
00073   * @{
00074   */
00075
00076 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
00077  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
00078 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
00079
00080 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
00081                                        || ((__VALUE__) == LL_USART_DIRECTION_RX) \
00082                                        || ((__VALUE__) == LL_USART_DIRECTION_TX) \
00083                                        || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
00084
00085 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
00086                                     || ((__VALUE__) == LL_USART_PARITY_EVEN) \
00087                                     || ((__VALUE__) == LL_USART_PARITY_ODD))
00088
00089 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
00090                                        || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
00091                                        || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
00092
00093 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
00094                                           || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
00095
00096 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
00097                                               || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
00098
00099 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
00100                                         || ((__VALUE__) == LL_USART_PHASE_2EDGE))
00101
00102 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
00103                                            || ((__VALUE__) == LL_USART_POLARITY_HIGH))
00104
00105 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
00106                                          || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
00107
00108 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
00109                                       || ((__VALUE__) == LL_USART_STOPBITS_1) \
00110                                       || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
00111                                       || ((__VALUE__) == LL_USART_STOPBITS_2))
00112
00113 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
00114                                        || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
00115                                        || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
00116                                        || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
00117
00118 /**
00119   * @}
00120   */
00121
00122 /* Private function prototypes -----------------------------------------------*/
00123
00124 /* Exported functions --------------------------------------------------------*/
00125 /** @addtogroup USART_LL_Exported_Functions
00126   * @{
00127   */
00128
00129 /** @addtogroup USART_LL_EF_Init
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  De-initialize USART registers (Registers restored to their default values).
00135   * @param  USARTx USART Instance
00136   * @retval An ErrorStatus enumeration value:
00137   *          - SUCCESS: USART registers are de-initialized
00138   *          - ERROR: USART registers are not de-initialized
00139   */
00140 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
00141 {
00142   ErrorStatus status = SUCCESS;
00143
00144   /* Check the parameters */
00145   assert_param(IS_UART_INSTANCE(USARTx));
00146
00147   if (USARTx == USART1)
00148   {
00149     /* Force reset of USART clock */
00150     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
00151
00152     /* Release reset of USART clock */
00153     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
00154   }
00155   else if (USARTx == USART2)
00156   {
00157     /* Force reset of USART clock */
00158     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
00159
00160     /* Release reset of USART clock */
00161     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
00162   }
00163 #if defined(USART3)
00164   else if (USARTx == USART3)
00165   {
00166     /* Force reset of USART clock */
00167     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
00168
00169     /* Release reset of USART clock */
00170     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
00171   }
00172 #endif /* USART3 */
00173 #if defined(UART4)
00174   else if (USARTx == UART4)
00175   {
00176     /* Force reset of UART clock */
00177     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
00178
00179     /* Release reset of UART clock */
00180     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
00181   }
00182 #endif /* UART4 */
00183 #if defined(UART5)
00184   else if (USARTx == UART5)
00185   {
00186     /* Force reset of UART clock */
00187     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
00188
00189     /* Release reset of UART clock */
00190     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
00191   }
00192 #endif /* UART5 */
00193   else
00194   {
00195     status = ERROR;
00196   }
00197
00198   return (status);
00199 }
00200
00201 /**
00202   * @brief  Initialize USART registers according to the specified
00203   *         parameters in USART_InitStruct.
00204   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00205   *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00206   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
00207   * @param  USARTx USART Instance
00208   * @param  USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
00209   *         that contains the configuration information for the specified USART peripheral.
00210   * @retval An ErrorStatus enumeration value:
00211   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
00212   *          - ERROR: Problem occurred during USART Registers initialization
00213   */
00214 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
00215 {
00216   ErrorStatus status = ERROR;
00217   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
00218
00219   /* Check the parameters */
00220   assert_param(IS_UART_INSTANCE(USARTx));
00221   assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
00222   assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
00223   assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
00224   assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
00225   assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
00226   assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
00227   assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
00228
00229   /* USART needs to be in disabled state, in order to be able to configure some bits in
00230      CRx registers */
00231   if (LL_USART_IsEnabled(USARTx) == 0U)
00232   {
00233     /*---------------------------- USART CR1 Configuration -----------------------
00234      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
00235      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
00236      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
00237      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
00238      * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
00239      */
00240     MODIFY_REG(USARTx->CR1,
00241                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
00242                 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
00243                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
00244                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
00245
00246     /*---------------------------- USART CR2 Configuration -----------------------
00247      * Configure USARTx CR2 (Stop bits) with parameters:
00248      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
00249      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
00250      */
00251     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
00252
00253     /*---------------------------- USART CR3 Configuration -----------------------
00254      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
00255      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
00256      */
00257     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
00258
00259     /*---------------------------- USART BRR Configuration -----------------------
00260      * Retrieve Clock frequency used for USART Peripheral
00261      */
00262     if (USARTx == USART1)
00263     {
00264       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
00265     }
00266     else if (USARTx == USART2)
00267     {
00268       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
00269     }
00270 #if defined(USART3)
00271     else if (USARTx == USART3)
00272     {
00273       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
00274     }
00275 #endif /* USART3 */
00276 #if defined(UART4)
00277     else if (USARTx == UART4)
00278     {
00279       periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
00280     }
00281 #endif /* UART4 */
00282 #if defined(UART5)
00283     else if (USARTx == UART5)
00284     {
00285       periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
00286     }
00287 #endif /* UART5 */
00288     else
00289     {
00290       /* Nothing to do, as error code is already assigned to ERROR value */
00291     }
00292
00293     /* Configure the USART Baud Rate :
00294        - valid baud rate value (different from 0) is required
00295        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00296     */
00297     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00298         && (USART_InitStruct->BaudRate != 0U))
00299     {
00300       status = SUCCESS;
00301       LL_USART_SetBaudRate(USARTx,
00302                            periphclk,
00303                            USART_InitStruct->OverSampling,
00304                            USART_InitStruct->BaudRate);
00305     }
00306   }
00307   /* Endif (=> USART not in Disabled state => return ERROR) */
00308
00309   return (status);
00310 }
00311
00312 /**
00313   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
00314   * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
00315   *                          whose fields will be set to default values.
00316   * @retval None
00317   */
00318
00319 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
00320 {
00321   /* Set USART_InitStruct fields to default values */
00322   USART_InitStruct->BaudRate            = 9600U;
00323   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
00324   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
00325   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
00326   USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
00327   USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
00328   USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
00329 }
00330
00331 /**
00332   * @brief  Initialize USART Clock related settings according to the
00333   *         specified parameters in the USART_ClockInitStruct.
00334   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00335   *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00336   * @param  USARTx USART Instance
00337   * @param  USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
00338   *         that contains the Clock configuration information for the specified USART peripheral.
00339   * @retval An ErrorStatus enumeration value:
00340   *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
00341   *          - ERROR: Problem occurred during USART Registers initialization
00342   */
00343 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00344 {
00345   ErrorStatus status = SUCCESS;
00346
00347   /* Check USART Instance and Clock signal output parameters */
00348   assert_param(IS_UART_INSTANCE(USARTx));
00349   assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
00350
00351   /* USART needs to be in disabled state, in order to be able to configure some bits in
00352      CRx registers */
00353   if (LL_USART_IsEnabled(USARTx) == 0U)
00354   {
00355     /*---------------------------- USART CR2 Configuration -----------------------*/
00356     /* If Clock signal has to be output */
00357     if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
00358     {
00359       /* Deactivate Clock signal delivery :
00360        * - Disable Clock Output:        USART_CR2_CLKEN cleared
00361        */
00362       LL_USART_DisableSCLKOutput(USARTx);
00363     }
00364     else
00365     {
00366       /* Ensure USART instance is USART capable */
00367       assert_param(IS_USART_INSTANCE(USARTx));
00368
00369       /* Check clock related parameters */
00370       assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
00371       assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
00372       assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
00373
00374       /*---------------------------- USART CR2 Configuration -----------------------
00375        * Configure USARTx CR2 (Clock signal related bits) with parameters:
00376        * - Enable Clock Output:         USART_CR2_CLKEN set
00377        * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
00378        * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
00379        * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
00380        */
00381       MODIFY_REG(USARTx->CR2,
00382                  USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
00383                  USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
00384                  USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
00385     }
00386   }
00387   /* Else (USART not in Disabled state => return ERROR */
00388   else
00389   {
00390     status = ERROR;
00391   }
00392
00393   return (status);
00394 }
00395
00396 /**
00397   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
00398   * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
00399   *                               whose fields will be set to default values.
00400   * @retval None
00401   */
00402 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00403 {
00404   /* Set LL_USART_ClockInitStruct fields with default values */
00405   USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
00406   USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00407   USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00408   USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00409 }
00410
00411 /**
00412   * @}
00413   */
00414
00415 /**
00416   * @}
00417   */
00418
00419 /**
00420   * @}
00421   */
00422
00423 #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
00424
00425 /**
00426   * @}
00427   */
00428
00429 #endif /* USE_FULL_LL_DRIVER */
00430
00431 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00432
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_usart.h Source File

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stm32l4xx_ll_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_usart.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of USART LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_USART_H
00040 #define __STM32L4xx_LL_USART_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
00054
00055 /** @defgroup USART_LL USART
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup USART_LL_Private_Constants USART Private Constants
00064   * @{
00065   */
00066
00067 /* Defines used for the bit position in the register and perform offsets*/
00068 #define USART_POSITION_CR1_DEDT                 (uint32_t)POSITION_VAL(USART_CR1_DEDT)
00069 #define USART_POSITION_CR1_DEAT                 (uint32_t)POSITION_VAL(USART_CR1_DEAT)
00070 #define USART_POSITION_CR2_ADD                  (uint32_t)POSITION_VAL(USART_CR2_ADD)
00071 #define USART_POSITION_CR3_SCARCNT              (uint32_t)POSITION_VAL(USART_CR3_SCARCNT)
00072 #define USART_POSITION_RTOR_BLEN                (uint32_t)POSITION_VAL(USART_RTOR_BLEN)
00073 #define USART_POSITION_GTPR_GT                  (uint32_t)POSITION_VAL(USART_GTPR_GT)
00074 /**
00075   * @}
00076   */
00077
00078 /* Private macros ------------------------------------------------------------*/
00079 #if defined(USE_FULL_LL_DRIVER)
00080 /** @defgroup USART_LL_Private_Macros USART Private Macros
00081   * @{
00082   */
00083 /**
00084   * @}
00085   */
00086 #endif /*USE_FULL_LL_DRIVER*/
00087
00088 /* Exported types ------------------------------------------------------------*/
00089 #if defined(USE_FULL_LL_DRIVER)
00090 /** @defgroup USART_LL_ES_INIT USART Exported Init structures
00091   * @{
00092   */
00093
00094 /**
00095   * @brief LL USART Init Structure definition
00096   */
00097 typedef struct
00098 {
00099   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
00100
00101                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
00102
00103   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00104                                            This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
00105
00106                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
00107
00108   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00109                                            This parameter can be a value of @ref USART_LL_EC_STOPBITS.
00110
00111                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
00112
00113   uint32_t Parity;                    /*!< Specifies the parity mode.
00114                                            This parameter can be a value of @ref USART_LL_EC_PARITY.
00115
00116                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
00117
00118   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00119                                            This parameter can be a value of @ref USART_LL_EC_DIRECTION.
00120
00121                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
00122
00123   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00124                                            This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
00125
00126                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
00127
00128   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
00129                                            This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
00130
00131                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
00132
00133 } LL_USART_InitTypeDef;
00134
00135 /**
00136   * @brief LL USART Clock Init Structure definition
00137   */
00138 typedef struct
00139 {
00140   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
00141                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
00142
00143                                            USART HW configuration can be modified afterwards using unitary functions
00144                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
00145                                            For more details, refer to description of this function. */
00146
00147   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
00148                                            This parameter can be a value of @ref USART_LL_EC_POLARITY.
00149
00150                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
00151                                            For more details, refer to description of this function. */
00152
00153   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
00154                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
00155
00156                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
00157                                            For more details, refer to description of this function. */
00158
00159   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
00160                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00161                                            This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
00162
00163                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
00164                                            For more details, refer to description of this function. */
00165
00166 } LL_USART_ClockInitTypeDef;
00167
00168 /**
00169   * @}
00170   */
00171 #endif /* USE_FULL_LL_DRIVER */
00172
00173 /* Exported constants --------------------------------------------------------*/
00174 /** @defgroup USART_LL_Exported_Constants USART Exported Constants
00175   * @{
00176   */
00177
00178 /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
00179   * @brief    Flags defines which can be used with LL_USART_WriteReg function
00180   * @{
00181   */
00182 #define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */
00183 #define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */
00184 #define LL_USART_ICR_NCF                        USART_ICR_NCF                 /*!< Noise detected flag */
00185 #define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */
00186 #define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */
00187 #define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */
00188 #if defined(USART_TCBGT_SUPPORT)
00189 #define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time flag */
00190 #endif
00191 #define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */
00192 #define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */
00193 #define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */
00194 #define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */
00195 #define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */
00196 #define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
00202   * @brief    Flags defines which can be used with LL_USART_ReadReg function
00203   * @{
00204   */
00205 #define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
00206 #define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
00207 #define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
00208 #define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
00209 #define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
00210 #define LL_USART_ISR_RXNE                       USART_ISR_RXNE                /*!< Read data register not empty flag */
00211 #define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
00212 #define LL_USART_ISR_TXE                        USART_ISR_TXE                 /*!< Transmit data register empty flag */
00213 #define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
00214 #define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
00215 #define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
00216 #define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
00217 #define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
00218 #define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
00219 #define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
00220 #define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
00221 #define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
00222 #define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
00223 #define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00224 #define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00225 #define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00226 #define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00227 #if defined(USART_TCBGT_SUPPORT)
00228 #define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
00229 #endif
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup USART_LL_EC_IT IT Defines
00235   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
00236   * @{
00237   */
00238 #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00239 #define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
00240 #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00241 #define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
00242 #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
00243 #define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
00244 #define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
00245 #define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
00246 #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
00247 #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
00248 #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
00249 #define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00250 #if defined(USART_TCBGT_SUPPORT)
00251 #define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
00252 #endif
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup USART_LL_EC_DIRECTION Communication Direction
00258   * @{
00259   */
00260 #define LL_USART_DIRECTION_NONE                 (uint32_t)0x00000000U              /*!< Transmitter and Receiver are disabled */
00261 #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00262 #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00263 #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup USART_LL_EC_PARITY Parity Control
00269   * @{
00270   */
00271 #define LL_USART_PARITY_NONE                    (uint32_t)0x00000000U                /*!< Parity control disabled */
00272 #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
00273 #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup USART_LL_EC_WAKEUP Wakeup
00279   * @{
00280   */
00281 #define LL_USART_WAKEUP_IDLELINE                (uint32_t)0x00000000U /*!<  USART wake up from Mute mode on Idle Line */
00282 #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
00288   * @{
00289   */
00290 #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00291 #define LL_USART_DATAWIDTH_8B                   (uint32_t)0x00000000U   /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00292 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
00298   * @{
00299   */
00300 #define LL_USART_OVERSAMPLING_16                (uint32_t)0x00000000U  /*!< Oversampling by 16 */
00301 #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
00302 /**
00303   * @}
00304   */
00305
00306 #if defined(USE_FULL_LL_DRIVER)
00307 /** @defgroup USART_LL_EC_CLOCK Clock Signal
00308   * @{
00309   */
00310
00311 #define LL_USART_CLOCK_DISABLE                  (uint32_t)0x00000000U  /*!< Clock signal not provided */
00312 #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
00313 /**
00314   * @}
00315   */
00316 #endif /*USE_FULL_LL_DRIVER*/
00317
00318 /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
00319   * @{
00320   */
00321 #define LL_USART_LASTCLKPULSE_NO_OUTPUT         (uint32_t)0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
00322 #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup USART_LL_EC_PHASE Clock Phase
00328   * @{
00329   */
00330 #define LL_USART_PHASE_1EDGE                    (uint32_t)0x00000000U /*!< The first clock transition is the first data capture edge */
00331 #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup USART_LL_EC_POLARITY Clock Polarity
00337   * @{
00338   */
00339 #define LL_USART_POLARITY_LOW                   (uint32_t)0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
00340 #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup USART_LL_EC_STOPBITS Stop Bits
00346   * @{
00347   */
00348 #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
00349 #define LL_USART_STOPBITS_1                     (uint32_t)0x00000000U                      /*!< 1 stop bit */
00350 #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
00351 #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
00357   * @{
00358   */
00359 #define LL_USART_TXRX_STANDARD                  (uint32_t)0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
00360 #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00366   * @{
00367   */
00368 #define LL_USART_RXPIN_LEVEL_STANDARD           (uint32_t)0x00000000U /*!< RX pin signal works using the standard logic levels */
00369 #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00375   * @{
00376   */
00377 #define LL_USART_TXPIN_LEVEL_STANDARD           (uint32_t)0x00000000U /*!< TX pin signal works using the standard logic levels */
00378 #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
00384   * @{
00385   */
00386 #define LL_USART_BINARY_LOGIC_POSITIVE          (uint32_t)0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00387 #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup USART_LL_EC_BITORDER Bit Order
00393   * @{
00394   */
00395 #define LL_USART_BITORDER_LSBFIRST              (uint32_t)0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
00396 #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
00402   * @{
00403   */
00404 #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    (uint32_t)0x00000000U                       /*!< Measurement of the start bit is used to detect the baud rate */
00405 #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
00406 #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
00407 #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
00413   * @{
00414   */
00415 #define LL_USART_ADDRESS_DETECT_4B              (uint32_t)0x00000000U /*!< 4-bit address detection method selected */
00416 #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
00422   * @{
00423   */
00424 #define LL_USART_HWCONTROL_NONE                 (uint32_t)0x00000000U                /*!< CTS and RTS hardware flow control disabled */
00425 #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00426 #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00427 #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
00433   * @{
00434   */
00435 #define LL_USART_WAKEUP_ON_ADDRESS              (uint32_t)0x00000000U                   /*!< Wake up active on address match */
00436 #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00437 #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00438 /**
00439   * @}
00440   */
00441
00442 /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
00443   * @{
00444   */
00445 #define LL_USART_IRDA_POWER_NORMAL              (uint32_t)0x00000000U /*!< IrDA normal power mode */
00446 #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
00452   * @{
00453   */
00454 #define LL_USART_LINBREAK_DETECT_10B            (uint32_t)0x00000000U /*!< 10-bit break detection method selected */
00455 #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
00461   * @{
00462   */
00463 #define LL_USART_DE_POLARITY_HIGH               (uint32_t)0x00000000U /*!< DE signal is active high */
00464 #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
00465 /**
00466   * @}
00467   */
00468
00469 /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
00470   * @{
00471   */
00472 #define LL_USART_DMA_REG_DATA_TRANSMIT          (uint32_t)0U          /*!< Get address of data register used for transmission */
00473 #define LL_USART_DMA_REG_DATA_RECEIVE           (uint32_t)1U          /*!< Get address of data register used for reception */
00474 /**
00475   * @}
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /* Exported macro ------------------------------------------------------------*/
00483 /** @defgroup USART_LL_Exported_Macros USART Exported Macros
00484   * @{
00485   */
00486
00487 /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
00488   * @{
00489   */
00490
00491 /**
00492   * @brief  Write a value in USART register
00493   * @param  __INSTANCE__ USART Instance
00494   * @param  __REG__ Register to be written
00495   * @param  __VALUE__ Value to be written in the register
00496   * @retval None
00497   */
00498 #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00499
00500 /**
00501   * @brief  Read a value in USART register
00502   * @param  __INSTANCE__ USART Instance
00503   * @param  __REG__ Register to be read
00504   * @retval Register value
00505   */
00506 #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00507 /**
00508   * @}
00509   */
00510
00511 /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
00512   * @{
00513   */
00514
00515 /**
00516   * @brief  Compute USARTDIV value according to Peripheral Clock and
00517   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
00518   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00519   * @param  __BAUDRATE__ Baud rate value to achieve
00520   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
00521   */
00522 #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
00523
00524 /**
00525   * @brief  Compute USARTDIV value according to Peripheral Clock and
00526   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
00527   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00528   * @param  __BAUDRATE__ Baud rate value to achieve
00529   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
00530   */
00531 #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
00532
00533 /**
00534   * @}
00535   */
00536
00537 /**
00538   * @}
00539   */
00540
00541 /* Exported functions --------------------------------------------------------*/
00542
00543 /** @defgroup USART_LL_Exported_Functions USART Exported Functions
00544   * @{
00545   */
00546
00547 /** @defgroup USART_LL_EF_Configuration Configuration functions
00548   * @{
00549   */
00550
00551 /**
00552   * @brief  USART Enable
00553   * @rmtoll CR1          UE            LL_USART_Enable
00554   * @param  USARTx USART Instance
00555   * @retval None
00556   */
00557 __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
00558 {
00559   SET_BIT(USARTx->CR1, USART_CR1_UE);
00560 }
00561
00562 /**
00563   * @brief  USART Disable (all USART prescalers and outputs are disabled)
00564   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
00565   *         and current operations are discarded. The configuration of the USART is kept, but all the status
00566   *         flags, in the USARTx_ISR are set to their default values.
00567   * @rmtoll CR1          UE            LL_USART_Disable
00568   * @param  USARTx USART Instance
00569   * @retval None
00570   */
00571 __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
00572 {
00573   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
00574 }
00575
00576 /**
00577   * @brief  Indicate if USART is enabled
00578   * @rmtoll CR1          UE            LL_USART_IsEnabled
00579   * @param  USARTx USART Instance
00580   * @retval State of bit (1 or 0).
00581   */
00582 __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
00583 {
00584   return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
00585 }
00586
00587 /**
00588   * @brief  USART enabled in STOP Mode.
00589   * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
00590   *         USART clock selection is HSI or LSE in RCC.
00591   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00592   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00593   * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
00594   * @param  USARTx USART Instance
00595   * @retval None
00596   */
00597 __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
00598 {
00599   SET_BIT(USARTx->CR1, USART_CR1_UESM);
00600 }
00601
00602 /**
00603   * @brief  USART disabled in STOP Mode.
00604   * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
00605   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00606   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00607   * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
00608   * @param  USARTx USART Instance
00609   * @retval None
00610   */
00611 __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
00612 {
00613   CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
00614 }
00615
00616 /**
00617   * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
00618   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00619   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00620   * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
00621   * @param  USARTx USART Instance
00622   * @retval State of bit (1 or 0).
00623   */
00624 __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
00625 {
00626   return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
00627 }
00628
00629 /**
00630   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00631   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
00632   * @param  USARTx USART Instance
00633   * @retval None
00634   */
00635 __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
00636 {
00637   SET_BIT(USARTx->CR1, USART_CR1_RE);
00638 }
00639
00640 /**
00641   * @brief  Receiver Disable
00642   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
00643   * @param  USARTx USART Instance
00644   * @retval None
00645   */
00646 __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
00647 {
00648   CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
00649 }
00650
00651 /**
00652   * @brief  Transmitter Enable
00653   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
00654   * @param  USARTx USART Instance
00655   * @retval None
00656   */
00657 __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
00658 {
00659   SET_BIT(USARTx->CR1, USART_CR1_TE);
00660 }
00661
00662 /**
00663   * @brief  Transmitter Disable
00664   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
00665   * @param  USARTx USART Instance
00666   * @retval None
00667   */
00668 __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
00669 {
00670   CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
00671 }
00672
00673 /**
00674   * @brief  Configure simultaneously enabled/disabled states
00675   *         of Transmitter and Receiver
00676   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
00677   *         CR1          TE            LL_USART_SetTransferDirection
00678   * @param  USARTx USART Instance
00679   * @param  TransferDirection This parameter can be one of the following values:
00680   *         @arg @ref LL_USART_DIRECTION_NONE
00681   *         @arg @ref LL_USART_DIRECTION_RX
00682   *         @arg @ref LL_USART_DIRECTION_TX
00683   *         @arg @ref LL_USART_DIRECTION_TX_RX
00684   * @retval None
00685   */
00686 __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
00687 {
00688   MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00689 }
00690
00691 /**
00692   * @brief  Return enabled/disabled states of Transmitter and Receiver
00693   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
00694   *         CR1          TE            LL_USART_GetTransferDirection
00695   * @param  USARTx USART Instance
00696   * @retval Returned value can be one of the following values:
00697   *         @arg @ref LL_USART_DIRECTION_NONE
00698   *         @arg @ref LL_USART_DIRECTION_RX
00699   *         @arg @ref LL_USART_DIRECTION_TX
00700   *         @arg @ref LL_USART_DIRECTION_TX_RX
00701   */
00702 __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
00703 {
00704   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00705 }
00706
00707 /**
00708   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
00709   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00710   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00711   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
00712   * @rmtoll CR1          PS            LL_USART_SetParity\n
00713   *         CR1          PCE           LL_USART_SetParity
00714   * @param  USARTx USART Instance
00715   * @param  Parity This parameter can be one of the following values:
00716   *         @arg @ref LL_USART_PARITY_NONE
00717   *         @arg @ref LL_USART_PARITY_EVEN
00718   *         @arg @ref LL_USART_PARITY_ODD
00719   * @retval None
00720   */
00721 __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
00722 {
00723   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00724 }
00725
00726 /**
00727   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00728   * @rmtoll CR1          PS            LL_USART_GetParity\n
00729   *         CR1          PCE           LL_USART_GetParity
00730   * @param  USARTx USART Instance
00731   * @retval Returned value can be one of the following values:
00732   *         @arg @ref LL_USART_PARITY_NONE
00733   *         @arg @ref LL_USART_PARITY_EVEN
00734   *         @arg @ref LL_USART_PARITY_ODD
00735   */
00736 __STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
00737 {
00738   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00739 }
00740
00741 /**
00742   * @brief  Set Receiver Wake Up method from Mute mode.
00743   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
00744   * @param  USARTx USART Instance
00745   * @param  Method This parameter can be one of the following values:
00746   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00747   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00748   * @retval None
00749   */
00750 __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
00751 {
00752   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
00753 }
00754
00755 /**
00756   * @brief  Return Receiver Wake Up method from Mute mode
00757   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
00758   * @param  USARTx USART Instance
00759   * @retval Returned value can be one of the following values:
00760   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00761   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00762   */
00763 __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
00764 {
00765   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
00766 }
00767
00768 /**
00769   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
00770   * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
00771   *         CR1          M1            LL_USART_SetDataWidth
00772   * @param  USARTx USART Instance
00773   * @param  DataWidth This parameter can be one of the following values:
00774   *         @arg @ref LL_USART_DATAWIDTH_7B
00775   *         @arg @ref LL_USART_DATAWIDTH_8B
00776   *         @arg @ref LL_USART_DATAWIDTH_9B
00777   * @retval None
00778   */
00779 __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
00780 {
00781   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
00782 }
00783
00784 /**
00785   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00786   * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
00787   *         CR1          M1            LL_USART_GetDataWidth
00788   * @param  USARTx USART Instance
00789   * @retval Returned value can be one of the following values:
00790   *         @arg @ref LL_USART_DATAWIDTH_7B
00791   *         @arg @ref LL_USART_DATAWIDTH_8B
00792   *         @arg @ref LL_USART_DATAWIDTH_9B
00793   */
00794 __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
00795 {
00796   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
00797 }
00798
00799 /**
00800   * @brief  Allow switch between Mute Mode and Active mode
00801   * @rmtoll CR1          MME           LL_USART_EnableMuteMode
00802   * @param  USARTx USART Instance
00803   * @retval None
00804   */
00805 __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
00806 {
00807   SET_BIT(USARTx->CR1, USART_CR1_MME);
00808 }
00809
00810 /**
00811   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
00812   * @rmtoll CR1          MME           LL_USART_DisableMuteMode
00813   * @param  USARTx USART Instance
00814   * @retval None
00815   */
00816 __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
00817 {
00818   CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
00819 }
00820
00821 /**
00822   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
00823   * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
00824   * @param  USARTx USART Instance
00825   * @retval State of bit (1 or 0).
00826   */
00827 __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
00828 {
00829   return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
00830 }
00831
00832 /**
00833   * @brief  Set Oversampling to 8-bit or 16-bit mode
00834   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
00835   * @param  USARTx USART Instance
00836   * @param  OverSampling This parameter can be one of the following values:
00837   *         @arg @ref LL_USART_OVERSAMPLING_16
00838   *         @arg @ref LL_USART_OVERSAMPLING_8
00839   * @retval None
00840   */
00841 __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
00842 {
00843   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
00844 }
00845
00846 /**
00847   * @brief  Return Oversampling mode
00848   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
00849   * @param  USARTx USART Instance
00850   * @retval Returned value can be one of the following values:
00851   *         @arg @ref LL_USART_OVERSAMPLING_16
00852   *         @arg @ref LL_USART_OVERSAMPLING_8
00853   */
00854 __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
00855 {
00856   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
00857 }
00858
00859 /**
00860   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
00861   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00862   *         Synchronous mode is supported by the USARTx instance.
00863   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
00864   * @param  USARTx USART Instance
00865   * @param  LastBitClockPulse This parameter can be one of the following values:
00866   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
00867   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
00868   * @retval None
00869   */
00870 __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
00871 {
00872   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
00873 }
00874
00875 /**
00876   * @brief  Retrieve Clock pulse of the last data bit output configuration
00877   *         (Last bit Clock pulse output to the SCLK pin or not)
00878   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00879   *         Synchronous mode is supported by the USARTx instance.
00880   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
00881   * @param  USARTx USART Instance
00882   * @retval Returned value can be one of the following values:
00883   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
00884   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
00885   */
00886 __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
00887 {
00888   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
00889 }
00890
00891 /**
00892   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
00893   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00894   *         Synchronous mode is supported by the USARTx instance.
00895   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
00896   * @param  USARTx USART Instance
00897   * @param  ClockPhase This parameter can be one of the following values:
00898   *         @arg @ref LL_USART_PHASE_1EDGE
00899   *         @arg @ref LL_USART_PHASE_2EDGE
00900   * @retval None
00901   */
00902 __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
00903 {
00904   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
00905 }
00906
00907 /**
00908   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
00909   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00910   *         Synchronous mode is supported by the USARTx instance.
00911   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
00912   * @param  USARTx USART Instance
00913   * @retval Returned value can be one of the following values:
00914   *         @arg @ref LL_USART_PHASE_1EDGE
00915   *         @arg @ref LL_USART_PHASE_2EDGE
00916   */
00917 __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
00918 {
00919   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
00920 }
00921
00922 /**
00923   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
00924   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00925   *         Synchronous mode is supported by the USARTx instance.
00926   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
00927   * @param  USARTx USART Instance
00928   * @param  ClockPolarity This parameter can be one of the following values:
00929   *         @arg @ref LL_USART_POLARITY_LOW
00930   *         @arg @ref LL_USART_POLARITY_HIGH
00931   * @retval None
00932   */
00933 __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
00934 {
00935   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
00936 }
00937
00938 /**
00939   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
00940   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00941   *         Synchronous mode is supported by the USARTx instance.
00942   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
00943   * @param  USARTx USART Instance
00944   * @retval Returned value can be one of the following values:
00945   *         @arg @ref LL_USART_POLARITY_LOW
00946   *         @arg @ref LL_USART_POLARITY_HIGH
00947   */
00948 __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
00949 {
00950   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
00951 }
00952
00953 /**
00954   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
00955   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00956   *         Synchronous mode is supported by the USARTx instance.
00957   * @note   Call of this function is equivalent to following function call sequence :
00958   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
00959   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
00960   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
00961   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
00962   *         CR2          CPOL          LL_USART_ConfigClock\n
00963   *         CR2          LBCL          LL_USART_ConfigClock
00964   * @param  USARTx USART Instance
00965   * @param  Phase This parameter can be one of the following values:
00966   *         @arg @ref LL_USART_PHASE_1EDGE
00967   *         @arg @ref LL_USART_PHASE_2EDGE
00968   * @param  Polarity This parameter can be one of the following values:
00969   *         @arg @ref LL_USART_POLARITY_LOW
00970   *         @arg @ref LL_USART_POLARITY_HIGH
00971   * @param  LBCPOutput This parameter can be one of the following values:
00972   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
00973   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
00974   * @retval None
00975   */
00976 __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
00977 {
00978   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
00979 }
00980
00981 /**
00982   * @brief  Enable Clock output on SCLK pin
00983   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00984   *         Synchronous mode is supported by the USARTx instance.
00985   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
00986   * @param  USARTx USART Instance
00987   * @retval None
00988   */
00989 __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
00990 {
00991   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
00992 }
00993
00994 /**
00995   * @brief  Disable Clock output on SCLK pin
00996   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00997   *         Synchronous mode is supported by the USARTx instance.
00998   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
00999   * @param  USARTx USART Instance
01000   * @retval None
01001   */
01002 __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
01003 {
01004   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
01005 }
01006
01007 /**
01008   * @brief  Indicate if Clock output on SCLK pin is enabled
01009   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01010   *         Synchronous mode is supported by the USARTx instance.
01011   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
01012   * @param  USARTx USART Instance
01013   * @retval State of bit (1 or 0).
01014   */
01015 __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
01016 {
01017   return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
01018 }
01019
01020 /**
01021   * @brief  Set the length of the stop bits
01022   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
01023   * @param  USARTx USART Instance
01024   * @param  StopBits This parameter can be one of the following values:
01025   *         @arg @ref LL_USART_STOPBITS_0_5
01026   *         @arg @ref LL_USART_STOPBITS_1
01027   *         @arg @ref LL_USART_STOPBITS_1_5
01028   *         @arg @ref LL_USART_STOPBITS_2
01029   * @retval None
01030   */
01031 __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
01032 {
01033   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01034 }
01035
01036 /**
01037   * @brief  Retrieve the length of the stop bits
01038   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
01039   * @param  USARTx USART Instance
01040   * @retval Returned value can be one of the following values:
01041   *         @arg @ref LL_USART_STOPBITS_0_5
01042   *         @arg @ref LL_USART_STOPBITS_1
01043   *         @arg @ref LL_USART_STOPBITS_1_5
01044   *         @arg @ref LL_USART_STOPBITS_2
01045   */
01046 __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
01047 {
01048   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
01049 }
01050
01051 /**
01052   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
01053   * @note   Call of this function is equivalent to following function call sequence :
01054   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
01055   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
01056   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
01057   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
01058   *         CR1          PCE           LL_USART_ConfigCharacter\n
01059   *         CR1          M0            LL_USART_ConfigCharacter\n
01060   *         CR1          M1            LL_USART_ConfigCharacter\n
01061   *         CR2          STOP          LL_USART_ConfigCharacter
01062   * @param  USARTx USART Instance
01063   * @param  DataWidth This parameter can be one of the following values:
01064   *         @arg @ref LL_USART_DATAWIDTH_7B
01065   *         @arg @ref LL_USART_DATAWIDTH_8B
01066   *         @arg @ref LL_USART_DATAWIDTH_9B
01067   * @param  Parity This parameter can be one of the following values:
01068   *         @arg @ref LL_USART_PARITY_NONE
01069   *         @arg @ref LL_USART_PARITY_EVEN
01070   *         @arg @ref LL_USART_PARITY_ODD
01071   * @param  StopBits This parameter can be one of the following values:
01072   *         @arg @ref LL_USART_STOPBITS_0_5
01073   *         @arg @ref LL_USART_STOPBITS_1
01074   *         @arg @ref LL_USART_STOPBITS_1_5
01075   *         @arg @ref LL_USART_STOPBITS_2
01076   * @retval None
01077   */
01078 __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
01079                                               uint32_t StopBits)
01080 {
01081   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
01082   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01083 }
01084
01085 /**
01086   * @brief  Configure TX/RX pins swapping setting.
01087   * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
01088   * @param  USARTx USART Instance
01089   * @param  SwapConfig This parameter can be one of the following values:
01090   *         @arg @ref LL_USART_TXRX_STANDARD
01091   *         @arg @ref LL_USART_TXRX_SWAPPED
01092   * @retval None
01093   */
01094 __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
01095 {
01096   MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
01097 }
01098
01099 /**
01100   * @brief  Retrieve TX/RX pins swapping configuration.
01101   * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
01102   * @param  USARTx USART Instance
01103   * @retval Returned value can be one of the following values:
01104   *         @arg @ref LL_USART_TXRX_STANDARD
01105   *         @arg @ref LL_USART_TXRX_SWAPPED
01106   */
01107 __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
01108 {
01109   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
01110 }
01111
01112 /**
01113   * @brief  Configure RX pin active level logic
01114   * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
01115   * @param  USARTx USART Instance
01116   * @param  PinInvMethod This parameter can be one of the following values:
01117   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01118   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01119   * @retval None
01120   */
01121 __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01122 {
01123   MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01124 }
01125
01126 /**
01127   * @brief  Retrieve RX pin active level logic configuration
01128   * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
01129   * @param  USARTx USART Instance
01130   * @retval Returned value can be one of the following values:
01131   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01132   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01133   */
01134 __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
01135 {
01136   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
01137 }
01138
01139 /**
01140   * @brief  Configure TX pin active level logic
01141   * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
01142   * @param  USARTx USART Instance
01143   * @param  PinInvMethod This parameter can be one of the following values:
01144   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01145   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01146   * @retval None
01147   */
01148 __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01149 {
01150   MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01151 }
01152
01153 /**
01154   * @brief  Retrieve TX pin active level logic configuration
01155   * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
01156   * @param  USARTx USART Instance
01157   * @retval Returned value can be one of the following values:
01158   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01159   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01160   */
01161 __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
01162 {
01163   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
01164 }
01165
01166 /**
01167   * @brief  Configure Binary data logic.
01168   * @note   Allow to define how Logical data from the data register are send/received :
01169   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01170   * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
01171   * @param  USARTx USART Instance
01172   * @param  DataLogic This parameter can be one of the following values:
01173   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01174   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01175   * @retval None
01176   */
01177 __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
01178 {
01179   MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
01180 }
01181
01182 /**
01183   * @brief  Retrieve Binary data configuration
01184   * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
01185   * @param  USARTx USART Instance
01186   * @retval Returned value can be one of the following values:
01187   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01188   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01189   */
01190 __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
01191 {
01192   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
01193 }
01194
01195 /**
01196   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01197   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01198   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01199   * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
01200   * @param  USARTx USART Instance
01201   * @param  BitOrder This parameter can be one of the following values:
01202   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01203   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01204   * @retval None
01205   */
01206 __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
01207 {
01208   MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01209 }
01210
01211 /**
01212   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01213   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01214   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01215   * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
01216   * @param  USARTx USART Instance
01217   * @retval Returned value can be one of the following values:
01218   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01219   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01220   */
01221 __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
01222 {
01223   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
01224 }
01225
01226 /**
01227   * @brief  Enable Auto Baud-Rate Detection
01228   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01229   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01230   * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
01231   * @param  USARTx USART Instance
01232   * @retval None
01233   */
01234 __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
01235 {
01236   SET_BIT(USARTx->CR2, USART_CR2_ABREN);
01237 }
01238
01239 /**
01240   * @brief  Disable Auto Baud-Rate Detection
01241   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01242   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01243   * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
01244   * @param  USARTx USART Instance
01245   * @retval None
01246   */
01247 __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
01248 {
01249   CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
01250 }
01251
01252 /**
01253   * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
01254   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01255   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01256   * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
01257   * @param  USARTx USART Instance
01258   * @retval State of bit (1 or 0).
01259   */
01260 __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
01261 {
01262   return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN));
01263 }
01264
01265 /**
01266   * @brief  Set Auto Baud-Rate mode bits
01267   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01268   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01269   * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
01270   * @param  USARTx USART Instance
01271   * @param  AutoBaudRateMode This parameter can be one of the following values:
01272   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01273   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01274   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01275   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01276   * @retval None
01277   */
01278 __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
01279 {
01280   MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
01281 }
01282
01283 /**
01284   * @brief  Return Auto Baud-Rate mode
01285   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01286   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01287   * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
01288   * @param  USARTx USART Instance
01289   * @retval Returned value can be one of the following values:
01290   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01291   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01292   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01293   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01294   */
01295 __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
01296 {
01297   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
01298 }
01299
01300 /**
01301   * @brief  Enable Receiver Timeout
01302   * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
01303   * @param  USARTx USART Instance
01304   * @retval None
01305   */
01306 __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
01307 {
01308   SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
01309 }
01310
01311 /**
01312   * @brief  Disable Receiver Timeout
01313   * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
01314   * @param  USARTx USART Instance
01315   * @retval None
01316   */
01317 __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
01318 {
01319   CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
01320 }
01321
01322 /**
01323   * @brief  Indicate if Receiver Timeout feature is enabled
01324   * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
01325   * @param  USARTx USART Instance
01326   * @retval State of bit (1 or 0).
01327   */
01328 __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
01329 {
01330   return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN));
01331 }
01332
01333 /**
01334   * @brief  Set Address of the USART node.
01335   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01336   *         for wake up with address mark detection.
01337   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01338   *         (b7-b4 should be set to 0)
01339   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01340   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01341   *         for wake up with 7-bit address mark detection.
01342   *         The MSB of the character sent by the transmitter should be equal to 1.
01343   *         It may also be used for character detection during normal reception,
01344   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01345   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01346   *         value and CMF flag is set on match)
01347   * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
01348   *         CR2          ADDM7         LL_USART_ConfigNodeAddress
01349   * @param  USARTx USART Instance
01350   * @param  AddressLen This parameter can be one of the following values:
01351   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01352   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01353   * @param  NodeAddress 4 or 7 bit Address of the USART node.
01354   * @retval None
01355   */
01356 __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
01357 {
01358   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01359              (uint32_t)(AddressLen | (NodeAddress << USART_POSITION_CR2_ADD)));
01360 }
01361
01362 /**
01363   * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
01364   * @note   If 4-bit Address Detection is selected in ADDM7,
01365   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01366   *         If 7-bit Address Detection is selected in ADDM7,
01367   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01368   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
01369   * @param  USARTx USART Instance
01370   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
01371   */
01372 __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
01373 {
01374   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_POSITION_CR2_ADD);
01375 }
01376
01377 /**
01378   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01379   * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
01380   * @param  USARTx USART Instance
01381   * @retval Returned value can be one of the following values:
01382   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01383   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01384   */
01385 __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
01386 {
01387   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
01388 }
01389
01390 /**
01391   * @brief  Enable RTS HW Flow Control
01392   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01393   *         Hardware Flow control feature is supported by the USARTx instance.
01394   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
01395   * @param  USARTx USART Instance
01396   * @retval None
01397   */
01398 __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01399 {
01400   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
01401 }
01402
01403 /**
01404   * @brief  Disable RTS HW Flow Control
01405   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01406   *         Hardware Flow control feature is supported by the USARTx instance.
01407   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
01408   * @param  USARTx USART Instance
01409   * @retval None
01410   */
01411 __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01412 {
01413   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
01414 }
01415
01416 /**
01417   * @brief  Enable CTS HW Flow Control
01418   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01419   *         Hardware Flow control feature is supported by the USARTx instance.
01420   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
01421   * @param  USARTx USART Instance
01422   * @retval None
01423   */
01424 __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01425 {
01426   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
01427 }
01428
01429 /**
01430   * @brief  Disable CTS HW Flow Control
01431   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01432   *         Hardware Flow control feature is supported by the USARTx instance.
01433   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
01434   * @param  USARTx USART Instance
01435   * @retval None
01436   */
01437 __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01438 {
01439   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
01440 }
01441
01442 /**
01443   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01444   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01445   *         Hardware Flow control feature is supported by the USARTx instance.
01446   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
01447   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
01448   * @param  USARTx USART Instance
01449   * @param  HardwareFlowControl This parameter can be one of the following values:
01450   *         @arg @ref LL_USART_HWCONTROL_NONE
01451   *         @arg @ref LL_USART_HWCONTROL_RTS
01452   *         @arg @ref LL_USART_HWCONTROL_CTS
01453   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01454   * @retval None
01455   */
01456 __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
01457 {
01458   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01459 }
01460
01461 /**
01462   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01463   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01464   *         Hardware Flow control feature is supported by the USARTx instance.
01465   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
01466   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
01467   * @param  USARTx USART Instance
01468   * @retval Returned value can be one of the following values:
01469   *         @arg @ref LL_USART_HWCONTROL_NONE
01470   *         @arg @ref LL_USART_HWCONTROL_RTS
01471   *         @arg @ref LL_USART_HWCONTROL_CTS
01472   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01473   */
01474 __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
01475 {
01476   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01477 }
01478
01479 /**
01480   * @brief  Enable One bit sampling method
01481   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
01482   * @param  USARTx USART Instance
01483   * @retval None
01484   */
01485 __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
01486 {
01487   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01488 }
01489
01490 /**
01491   * @brief  Disable One bit sampling method
01492   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
01493   * @param  USARTx USART Instance
01494   * @retval None
01495   */
01496 __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
01497 {
01498   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01499 }
01500
01501 /**
01502   * @brief  Indicate if One bit sampling method is enabled
01503   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
01504   * @param  USARTx USART Instance
01505   * @retval State of bit (1 or 0).
01506   */
01507 __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
01508 {
01509   return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
01510 }
01511
01512 /**
01513   * @brief  Enable Overrun detection
01514   * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
01515   * @param  USARTx USART Instance
01516   * @retval None
01517   */
01518 __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
01519 {
01520   CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01521 }
01522
01523 /**
01524   * @brief  Disable Overrun detection
01525   * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
01526   * @param  USARTx USART Instance
01527   * @retval None
01528   */
01529 __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
01530 {
01531   SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01532 }
01533
01534 /**
01535   * @brief  Indicate if Overrun detection is enabled
01536   * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
01537   * @param  USARTx USART Instance
01538   * @retval State of bit (1 or 0).
01539   */
01540 __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
01541 {
01542   return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
01543 }
01544
01545 /**
01546   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01547   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01548   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01549   * @rmtoll CR3          WUS           LL_USART_SetWKUPType
01550   * @param  USARTx USART Instance
01551   * @param  Type This parameter can be one of the following values:
01552   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01553   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01554   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01555   * @retval None
01556   */
01557 __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
01558 {
01559   MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
01560 }
01561
01562 /**
01563   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01564   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01565   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01566   * @rmtoll CR3          WUS           LL_USART_GetWKUPType
01567   * @param  USARTx USART Instance
01568   * @retval Returned value can be one of the following values:
01569   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01570   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01571   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01572   */
01573 __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
01574 {
01575   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
01576 }
01577
01578 /**
01579   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
01580   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
01581   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
01582   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
01583   *         (Baud rate value != 0)
01584   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
01585   * @param  USARTx USART Instance
01586   * @param  PeriphClk Peripheral Clock
01587   * @param  OverSampling This parameter can be one of the following values:
01588   *         @arg @ref LL_USART_OVERSAMPLING_16
01589   *         @arg @ref LL_USART_OVERSAMPLING_8
01590   * @param  BaudRate Baud Rate
01591   * @retval None
01592   */
01593 __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
01594                                           uint32_t BaudRate)
01595 {
01596   register uint32_t usartdiv = 0x0U;
01597   register uint32_t brrtemp = 0x0U;
01598
01599   if (OverSampling == LL_USART_OVERSAMPLING_8)
01600   {
01601     usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
01602     brrtemp = usartdiv & 0xFFF0U;
01603     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
01604     USARTx->BRR = brrtemp;
01605   }
01606   else
01607   {
01608     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
01609   }
01610 }
01611
01612 /**
01613   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
01614   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
01615   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01616   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
01617   * @param  USARTx USART Instance
01618   * @param  PeriphClk Peripheral Clock
01619   * @param  OverSampling This parameter can be one of the following values:
01620   *         @arg @ref LL_USART_OVERSAMPLING_16
01621   *         @arg @ref LL_USART_OVERSAMPLING_8
01622   * @retval Baud Rate
01623   */
01624 __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
01625 {
01626   register uint32_t usartdiv = 0x0U;
01627   register uint32_t brrresult = 0x0U;
01628
01629   usartdiv = USARTx->BRR;
01630
01631   if (OverSampling == LL_USART_OVERSAMPLING_8)
01632   {
01633     if ((usartdiv & 0xFFF7U) != 0U)
01634     {
01635       usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
01636       brrresult = (PeriphClk * 2U) / usartdiv;
01637     }
01638   }
01639   else
01640   {
01641     if ((usartdiv & 0xFFFFU) != 0U)
01642     {
01643       brrresult = PeriphClk / usartdiv;
01644     }
01645   }
01646   return (brrresult);
01647 }
01648
01649 /**
01650   * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
01651   * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
01652   * @param  USARTx USART Instance
01653   * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01654   * @retval None
01655   */
01656 __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
01657 {
01658   MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
01659 }
01660
01661 /**
01662   * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
01663   * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
01664   * @param  USARTx USART Instance
01665   * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01666   */
01667 __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
01668 {
01669   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
01670 }
01671
01672 /**
01673   * @brief  Set Block Length value in reception
01674   * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
01675   * @param  USARTx USART Instance
01676   * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
01677   * @retval None
01678   */
01679 __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
01680 {
01681   MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_POSITION_RTOR_BLEN);
01682 }
01683
01684 /**
01685   * @brief  Get Block Length value in reception
01686   * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
01687   * @param  USARTx USART Instance
01688   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01689   */
01690 __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
01691 {
01692   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_POSITION_RTOR_BLEN);
01693 }
01694
01695 /**
01696   * @}
01697   */
01698
01699 /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
01700   * @{
01701   */
01702
01703 /**
01704   * @brief  Enable IrDA mode
01705   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01706   *         IrDA feature is supported by the USARTx instance.
01707   * @rmtoll CR3          IREN          LL_USART_EnableIrda
01708   * @param  USARTx USART Instance
01709   * @retval None
01710   */
01711 __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
01712 {
01713   SET_BIT(USARTx->CR3, USART_CR3_IREN);
01714 }
01715
01716 /**
01717   * @brief  Disable IrDA mode
01718   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01719   *         IrDA feature is supported by the USARTx instance.
01720   * @rmtoll CR3          IREN          LL_USART_DisableIrda
01721   * @param  USARTx USART Instance
01722   * @retval None
01723   */
01724 __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
01725 {
01726   CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
01727 }
01728
01729 /**
01730   * @brief  Indicate if IrDA mode is enabled
01731   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01732   *         IrDA feature is supported by the USARTx instance.
01733   * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
01734   * @param  USARTx USART Instance
01735   * @retval State of bit (1 or 0).
01736   */
01737 __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
01738 {
01739   return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
01740 }
01741
01742 /**
01743   * @brief  Configure IrDA Power Mode (Normal or Low Power)
01744   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01745   *         IrDA feature is supported by the USARTx instance.
01746   * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
01747   * @param  USARTx USART Instance
01748   * @param  PowerMode This parameter can be one of the following values:
01749   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
01750   *         @arg @ref LL_USART_IRDA_POWER_LOW
01751   * @retval None
01752   */
01753 __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
01754 {
01755   MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
01756 }
01757
01758 /**
01759   * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
01760   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01761   *         IrDA feature is supported by the USARTx instance.
01762   * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
01763   * @param  USARTx USART Instance
01764   * @retval Returned value can be one of the following values:
01765   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
01766   *         @arg @ref LL_USART_PHASE_2EDGE
01767   */
01768 __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
01769 {
01770   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
01771 }
01772
01773 /**
01774   * @brief  Set Irda prescaler value, used for dividing the USART clock source
01775   *         to achieve the Irda Low Power frequency (8 bits value)
01776   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01777   *         IrDA feature is supported by the USARTx instance.
01778   * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
01779   * @param  USARTx USART Instance
01780   * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
01781   * @retval None
01782   */
01783 __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01784 {
01785   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
01786 }
01787
01788 /**
01789   * @brief  Return Irda prescaler value, used for dividing the USART clock source
01790   *         to achieve the Irda Low Power frequency (8 bits value)
01791   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01792   *         IrDA feature is supported by the USARTx instance.
01793   * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
01794   * @param  USARTx USART Instance
01795   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
01796   */
01797 __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
01798 {
01799   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
01800 }
01801
01802 /**
01803   * @}
01804   */
01805
01806 /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
01807   * @{
01808   */
01809
01810 /**
01811   * @brief  Enable Smartcard NACK transmission
01812   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01813   *         Smartcard feature is supported by the USARTx instance.
01814   * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
01815   * @param  USARTx USART Instance
01816   * @retval None
01817   */
01818 __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
01819 {
01820   SET_BIT(USARTx->CR3, USART_CR3_NACK);
01821 }
01822
01823 /**
01824   * @brief  Disable Smartcard NACK transmission
01825   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01826   *         Smartcard feature is supported by the USARTx instance.
01827   * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
01828   * @param  USARTx USART Instance
01829   * @retval None
01830   */
01831 __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
01832 {
01833   CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
01834 }
01835
01836 /**
01837   * @brief  Indicate if Smartcard NACK transmission is enabled
01838   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01839   *         Smartcard feature is supported by the USARTx instance.
01840   * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
01841   * @param  USARTx USART Instance
01842   * @retval State of bit (1 or 0).
01843   */
01844 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
01845 {
01846   return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
01847 }
01848
01849 /**
01850   * @brief  Enable Smartcard mode
01851   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01852   *         Smartcard feature is supported by the USARTx instance.
01853   * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
01854   * @param  USARTx USART Instance
01855   * @retval None
01856   */
01857 __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
01858 {
01859   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
01860 }
01861
01862 /**
01863   * @brief  Disable Smartcard mode
01864   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01865   *         Smartcard feature is supported by the USARTx instance.
01866   * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
01867   * @param  USARTx USART Instance
01868   * @retval None
01869   */
01870 __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
01871 {
01872   CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
01873 }
01874
01875 /**
01876   * @brief  Indicate if Smartcard mode is enabled
01877   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01878   *         Smartcard feature is supported by the USARTx instance.
01879   * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
01880   * @param  USARTx USART Instance
01881   * @retval State of bit (1 or 0).
01882   */
01883 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
01884 {
01885   return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
01886 }
01887
01888 /**
01889   * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
01890   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01891   *         Smartcard feature is supported by the USARTx instance.
01892   * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
01893   *         In transmission mode, it specifies the number of automatic retransmission retries, before
01894   *         generating a transmission error (FE bit set).
01895   *         In reception mode, it specifies the number or erroneous reception trials, before generating a
01896   *         reception error (RXNE and PE bits set)
01897   * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
01898   * @param  USARTx USART Instance
01899   * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
01900   * @retval None
01901   */
01902 __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
01903 {
01904   MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_POSITION_CR3_SCARCNT);
01905 }
01906
01907 /**
01908   * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
01909   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01910   *         Smartcard feature is supported by the USARTx instance.
01911   * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
01912   * @param  USARTx USART Instance
01913   * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
01914   */
01915 __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
01916 {
01917   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_POSITION_CR3_SCARCNT);
01918 }
01919
01920 /**
01921   * @brief  Set Smartcard prescaler value, used for dividing the USART clock
01922   *         source to provide the SMARTCARD Clock (5 bits value)
01923   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01924   *         Smartcard feature is supported by the USARTx instance.
01925   * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
01926   * @param  USARTx USART Instance
01927   * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
01928   * @retval None
01929   */
01930 __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01931 {
01932   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
01933 }
01934
01935 /**
01936   * @brief  Return Smartcard prescaler value, used for dividing the USART clock
01937   *         source to provide the SMARTCARD Clock (5 bits value)
01938   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01939   *         Smartcard feature is supported by the USARTx instance.
01940   * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
01941   * @param  USARTx USART Instance
01942   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
01943   */
01944 __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
01945 {
01946   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
01947 }
01948
01949 /**
01950   * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
01951   *         (GT[7:0] bits : Guard time value)
01952   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01953   *         Smartcard feature is supported by the USARTx instance.
01954   * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
01955   * @param  USARTx USART Instance
01956   * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
01957   * @retval None
01958   */
01959 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
01960 {
01961   MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
01962 }
01963
01964 /**
01965   * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
01966   *         (GT[7:0] bits : Guard time value)
01967   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01968   *         Smartcard feature is supported by the USARTx instance.
01969   * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
01970   * @param  USARTx USART Instance
01971   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
01972   */
01973 __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
01974 {
01975   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
01976 }
01977
01978 /**
01979   * @}
01980   */
01981
01982 /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
01983   * @{
01984   */
01985
01986 /**
01987   * @brief  Enable Single Wire Half-Duplex mode
01988   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
01989   *         Half-Duplex mode is supported by the USARTx instance.
01990   * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
01991   * @param  USARTx USART Instance
01992   * @retval None
01993   */
01994 __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
01995 {
01996   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
01997 }
01998
01999 /**
02000   * @brief  Disable Single Wire Half-Duplex mode
02001   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02002   *         Half-Duplex mode is supported by the USARTx instance.
02003   * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
02004   * @param  USARTx USART Instance
02005   * @retval None
02006   */
02007 __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
02008 {
02009   CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
02010 }
02011
02012 /**
02013   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
02014   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02015   *         Half-Duplex mode is supported by the USARTx instance.
02016   * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
02017   * @param  USARTx USART Instance
02018   * @retval State of bit (1 or 0).
02019   */
02020 __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
02021 {
02022   return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
02023 }
02024
02025 /**
02026   * @}
02027   */
02028
02029 /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
02030   * @{
02031   */
02032
02033 /**
02034   * @brief  Set LIN Break Detection Length
02035   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02036   *         LIN feature is supported by the USARTx instance.
02037   * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
02038   * @param  USARTx USART Instance
02039   * @param  LINBDLength This parameter can be one of the following values:
02040   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02041   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02042   * @retval None
02043   */
02044 __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
02045 {
02046   MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
02047 }
02048
02049 /**
02050   * @brief  Return LIN Break Detection Length
02051   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02052   *         LIN feature is supported by the USARTx instance.
02053   * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
02054   * @param  USARTx USART Instance
02055   * @retval Returned value can be one of the following values:
02056   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02057   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02058   */
02059 __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
02060 {
02061   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
02062 }
02063
02064 /**
02065   * @brief  Enable LIN mode
02066   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02067   *         LIN feature is supported by the USARTx instance.
02068   * @rmtoll CR2          LINEN         LL_USART_EnableLIN
02069   * @param  USARTx USART Instance
02070   * @retval None
02071   */
02072 __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
02073 {
02074   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02075 }
02076
02077 /**
02078   * @brief  Disable LIN mode
02079   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02080   *         LIN feature is supported by the USARTx instance.
02081   * @rmtoll CR2          LINEN         LL_USART_DisableLIN
02082   * @param  USARTx USART Instance
02083   * @retval None
02084   */
02085 __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
02086 {
02087   CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
02088 }
02089
02090 /**
02091   * @brief  Indicate if LIN mode is enabled
02092   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02093   *         LIN feature is supported by the USARTx instance.
02094   * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
02095   * @param  USARTx USART Instance
02096   * @retval State of bit (1 or 0).
02097   */
02098 __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
02099 {
02100   return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
02101 }
02102
02103 /**
02104   * @}
02105   */
02106
02107 /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
02108   * @{
02109   */
02110
02111 /**
02112   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02113   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02114   *         Driver Enable feature is supported by the USARTx instance.
02115   * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
02116   * @param  USARTx USART Instance
02117   * @param  Time Value between Min_Data=0 and Max_Data=31
02118   * @retval None
02119   */
02120 __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
02121 {
02122   MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_POSITION_CR1_DEDT);
02123 }
02124
02125 /**
02126   * @brief  Return DEDT (Driver Enable De-Assertion Time)
02127   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02128   *         Driver Enable feature is supported by the USARTx instance.
02129   * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
02130   * @param  USARTx USART Instance
02131   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02132   */
02133 __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
02134 {
02135   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_POSITION_CR1_DEDT);
02136 }
02137
02138 /**
02139   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02140   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02141   *         Driver Enable feature is supported by the USARTx instance.
02142   * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
02143   * @param  USARTx USART Instance
02144   * @param  Time Value between Min_Data=0 and Max_Data=31
02145   * @retval None
02146   */
02147 __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
02148 {
02149   MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_POSITION_CR1_DEAT);
02150 }
02151
02152 /**
02153   * @brief  Return DEAT (Driver Enable Assertion Time)
02154   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02155   *         Driver Enable feature is supported by the USARTx instance.
02156   * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
02157   * @param  USARTx USART Instance
02158   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02159   */
02160 __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
02161 {
02162   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_POSITION_CR1_DEAT);
02163 }
02164
02165 /**
02166   * @brief  Enable Driver Enable (DE) Mode
02167   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02168   *         Driver Enable feature is supported by the USARTx instance.
02169   * @rmtoll CR3          DEM           LL_USART_EnableDEMode
02170   * @param  USARTx USART Instance
02171   * @retval None
02172   */
02173 __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
02174 {
02175   SET_BIT(USARTx->CR3, USART_CR3_DEM);
02176 }
02177
02178 /**
02179   * @brief  Disable Driver Enable (DE) Mode
02180   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02181   *         Driver Enable feature is supported by the USARTx instance.
02182   * @rmtoll CR3          DEM           LL_USART_DisableDEMode
02183   * @param  USARTx USART Instance
02184   * @retval None
02185   */
02186 __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
02187 {
02188   CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
02189 }
02190
02191 /**
02192   * @brief  Indicate if Driver Enable (DE) Mode is enabled
02193   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02194   *         Driver Enable feature is supported by the USARTx instance.
02195   * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
02196   * @param  USARTx USART Instance
02197   * @retval State of bit (1 or 0).
02198   */
02199 __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
02200 {
02201   return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
02202 }
02203
02204 /**
02205   * @brief  Select Driver Enable Polarity
02206   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02207   *         Driver Enable feature is supported by the USARTx instance.
02208   * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
02209   * @param  USARTx USART Instance
02210   * @param  Polarity This parameter can be one of the following values:
02211   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02212   *         @arg @ref LL_USART_DE_POLARITY_LOW
02213   * @retval None
02214   */
02215 __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
02216 {
02217   MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
02218 }
02219
02220 /**
02221   * @brief  Return Driver Enable Polarity
02222   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02223   *         Driver Enable feature is supported by the USARTx instance.
02224   * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
02225   * @param  USARTx USART Instance
02226   * @retval Returned value can be one of the following values:
02227   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02228   *         @arg @ref LL_USART_DE_POLARITY_LOW
02229   */
02230 __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
02231 {
02232   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
02233 }
02234
02235 /**
02236   * @}
02237   */
02238
02239 /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
02240   * @{
02241   */
02242
02243 /**
02244   * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
02245   * @note   In UART mode, the following bits must be kept cleared:
02246   *           - LINEN bit in the USART_CR2 register,
02247   *           - CLKEN bit in the USART_CR2 register,
02248   *           - SCEN bit in the USART_CR3 register,
02249   *           - IREN bit in the USART_CR3 register,
02250   *           - HDSEL bit in the USART_CR3 register.
02251   * @note   Call of this function is equivalent to following function call sequence :
02252   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02253   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02254   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02255   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02256   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02257   * @note   Other remaining configurations items related to Asynchronous Mode
02258   *         (as Baud Rate, Word length, Parity, ...) should be set using
02259   *         dedicated functions
02260   * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
02261   *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
02262   *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
02263   *         CR3          IREN          LL_USART_ConfigAsyncMode\n
02264   *         CR3          HDSEL         LL_USART_ConfigAsyncMode
02265   * @param  USARTx USART Instance
02266   * @retval None
02267   */
02268 __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
02269 {
02270   /* In Asynchronous mode, the following bits must be kept cleared:
02271   - LINEN, CLKEN bits in the USART_CR2 register,
02272   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
02273   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02274   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02275 }
02276
02277 /**
02278   * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
02279   * @note   In Synchronous mode, the following bits must be kept cleared:
02280   *           - LINEN bit in the USART_CR2 register,
02281   *           - SCEN bit in the USART_CR3 register,
02282   *           - IREN bit in the USART_CR3 register,
02283   *           - HDSEL bit in the USART_CR3 register.
02284   *         This function also sets the USART in Synchronous mode.
02285   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
02286   *         Synchronous mode is supported by the USARTx instance.
02287   * @note   Call of this function is equivalent to following function call sequence :
02288   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02289   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02290   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02291   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02292   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02293   * @note   Other remaining configurations items related to Synchronous Mode
02294   *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
02295   *         dedicated functions
02296   * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
02297   *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
02298   *         CR3          SCEN          LL_USART_ConfigSyncMode\n
02299   *         CR3          IREN          LL_USART_ConfigSyncMode\n
02300   *         CR3          HDSEL         LL_USART_ConfigSyncMode
02301   * @param  USARTx USART Instance
02302   * @retval None
02303   */
02304 __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
02305 {
02306   /* In Synchronous mode, the following bits must be kept cleared:
02307   - LINEN bit in the USART_CR2 register,
02308   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
02309   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02310   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02311   /* set the UART/USART in Synchronous mode */
02312   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
02313 }
02314
02315 /**
02316   * @brief  Perform basic configuration of USART for enabling use in LIN Mode
02317   * @note   In LIN mode, the following bits must be kept cleared:
02318   *           - STOP and CLKEN bits in the USART_CR2 register,
02319   *           - SCEN bit in the USART_CR3 register,
02320   *           - IREN bit in the USART_CR3 register,
02321   *           - HDSEL bit in the USART_CR3 register.
02322   *         This function also set the UART/USART in LIN mode.
02323   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02324   *         LIN feature is supported by the USARTx instance.
02325   * @note   Call of this function is equivalent to following function call sequence :
02326   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02327   *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02328   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02329   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02330   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02331   *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
02332   * @note   Other remaining configurations items related to LIN Mode
02333   *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
02334   *         dedicated functions
02335   * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
02336   *         CR2          STOP          LL_USART_ConfigLINMode\n
02337   *         CR2          LINEN         LL_USART_ConfigLINMode\n
02338   *         CR3          IREN          LL_USART_ConfigLINMode\n
02339   *         CR3          SCEN          LL_USART_ConfigLINMode\n
02340   *         CR3          HDSEL         LL_USART_ConfigLINMode
02341   * @param  USARTx USART Instance
02342   * @retval None
02343   */
02344 __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
02345 {
02346   /* In LIN mode, the following bits must be kept cleared:
02347   - STOP and CLKEN bits in the USART_CR2 register,
02348   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
02349   CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
02350   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
02351   /* Set the UART/USART in LIN mode */
02352   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02353 }
02354
02355 /**
02356   * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
02357   * @note   In Half Duplex mode, the following bits must be kept cleared:
02358   *           - LINEN bit in the USART_CR2 register,
02359   *           - CLKEN bit in the USART_CR2 register,
02360   *           - SCEN bit in the USART_CR3 register,
02361   *           - IREN bit in the USART_CR3 register,
02362   *         This function also sets the UART/USART in Half Duplex mode.
02363   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02364   *         Half-Duplex mode is supported by the USARTx instance.
02365   * @note   Call of this function is equivalent to following function call sequence :
02366   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02367   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02368   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02369   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02370   *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
02371   * @note   Other remaining configurations items related to Half Duplex Mode
02372   *         (as Baud Rate, Word length, Parity, ...) should be set using
02373   *         dedicated functions
02374   * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
02375   *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
02376   *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
02377   *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
02378   *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
02379   * @param  USARTx USART Instance
02380   * @retval None
02381   */
02382 __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
02383 {
02384   /* In Half Duplex mode, the following bits must be kept cleared:
02385   - LINEN and CLKEN bits in the USART_CR2 register,
02386   - SCEN and IREN bits in the USART_CR3 register.*/
02387   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02388   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
02389   /* set the UART/USART in Half Duplex mode */
02390   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02391 }
02392
02393 /**
02394   * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
02395   * @note   In Smartcard mode, the following bits must be kept cleared:
02396   *           - LINEN bit in the USART_CR2 register,
02397   *           - IREN bit in the USART_CR3 register,
02398   *           - HDSEL bit in the USART_CR3 register.
02399   *         This function also configures Stop bits to 1.5 bits and
02400   *         sets the USART in Smartcard mode (SCEN bit).
02401   *         Clock Output is also enabled (CLKEN).
02402   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02403   *         Smartcard feature is supported by the USARTx instance.
02404   * @note   Call of this function is equivalent to following function call sequence :
02405   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02406   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02407   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02408   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02409   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02410   *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
02411   * @note   Other remaining configurations items related to Smartcard Mode
02412   *         (as Baud Rate, Word length, Parity, ...) should be set using
02413   *         dedicated functions
02414   * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
02415   *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
02416   *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
02417   *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
02418   *         CR3          SCEN          LL_USART_ConfigSmartcardMode
02419   * @param  USARTx USART Instance
02420   * @retval None
02421   */
02422 __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
02423 {
02424   /* In Smartcard mode, the following bits must be kept cleared:
02425   - LINEN bit in the USART_CR2 register,
02426   - IREN and HDSEL bits in the USART_CR3 register.*/
02427   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02428   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
02429   /* Configure Stop bits to 1.5 bits */
02430   /* Synchronous mode is activated by default */
02431   SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
02432   /* set the UART/USART in Smartcard mode */
02433   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02434 }
02435
02436 /**
02437   * @brief  Perform basic configuration of USART for enabling use in Irda Mode
02438   * @note   In IRDA mode, the following bits must be kept cleared:
02439   *           - LINEN bit in the USART_CR2 register,
02440   *           - STOP and CLKEN bits in the USART_CR2 register,
02441   *           - SCEN bit in the USART_CR3 register,
02442   *           - HDSEL bit in the USART_CR3 register.
02443   *         This function also sets the UART/USART in IRDA mode (IREN bit).
02444   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02445   *         IrDA feature is supported by the USARTx instance.
02446   * @note   Call of this function is equivalent to following function call sequence :
02447   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02448   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02449   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02450   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02451   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02452   *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
02453   * @note   Other remaining configurations items related to Irda Mode
02454   *         (as Baud Rate, Word length, Power mode, ...) should be set using
02455   *         dedicated functions
02456   * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
02457   *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
02458   *         CR2          STOP          LL_USART_ConfigIrdaMode\n
02459   *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
02460   *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
02461   *         CR3          IREN          LL_USART_ConfigIrdaMode
02462   * @param  USARTx USART Instance
02463   * @retval None
02464   */
02465 __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
02466 {
02467   /* In IRDA mode, the following bits must be kept cleared:
02468   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
02469   - SCEN and HDSEL bits in the USART_CR3 register.*/
02470   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
02471   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
02472   /* set the UART/USART in IRDA mode */
02473   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02474 }
02475
02476 /**
02477   * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
02478   *         (several USARTs connected in a network, one of the USARTs can be the master,
02479   *         its TX output connected to the RX inputs of the other slaves USARTs).
02480   * @note   In MultiProcessor mode, the following bits must be kept cleared:
02481   *           - LINEN bit in the USART_CR2 register,
02482   *           - CLKEN bit in the USART_CR2 register,
02483   *           - SCEN bit in the USART_CR3 register,
02484   *           - IREN bit in the USART_CR3 register,
02485   *           - HDSEL bit in the USART_CR3 register.
02486   * @note   Call of this function is equivalent to following function call sequence :
02487   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02488   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02489   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02490   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02491   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02492   * @note   Other remaining configurations items related to Multi processor Mode
02493   *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
02494   *         dedicated functions
02495   * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
02496   *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
02497   *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
02498   *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
02499   *         CR3          IREN          LL_USART_ConfigMultiProcessMode
02500   * @param  USARTx USART Instance
02501   * @retval None
02502   */
02503 __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
02504 {
02505   /* In Multi Processor mode, the following bits must be kept cleared:
02506   - LINEN and CLKEN bits in the USART_CR2 register,
02507   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
02508   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02509   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
02510 }
02511
02512 /**
02513   * @}
02514   */
02515
02516 /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
02517   * @{
02518   */
02519
02520 /**
02521   * @brief  Check if the USART Parity Error Flag is set or not
02522   * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
02523   * @param  USARTx USART Instance
02524   * @retval State of bit (1 or 0).
02525   */
02526 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
02527 {
02528   return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
02529 }
02530
02531 /**
02532   * @brief  Check if the USART Framing Error Flag is set or not
02533   * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
02534   * @param  USARTx USART Instance
02535   * @retval State of bit (1 or 0).
02536   */
02537 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
02538 {
02539   return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
02540 }
02541
02542 /**
02543   * @brief  Check if the USART Noise error detected Flag is set or not
02544   * @rmtoll ISR          NF            LL_USART_IsActiveFlag_NE
02545   * @param  USARTx USART Instance
02546   * @retval State of bit (1 or 0).
02547   */
02548 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
02549 {
02550   return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
02551 }
02552
02553 /**
02554   * @brief  Check if the USART OverRun Error Flag is set or not
02555   * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
02556   * @param  USARTx USART Instance
02557   * @retval State of bit (1 or 0).
02558   */
02559 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
02560 {
02561   return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
02562 }
02563
02564 /**
02565   * @brief  Check if the USART IDLE line detected Flag is set or not
02566   * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
02567   * @param  USARTx USART Instance
02568   * @retval State of bit (1 or 0).
02569   */
02570 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
02571 {
02572   return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
02573 }
02574
02575 /**
02576   * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
02577   * @rmtoll ISR          RXNE          LL_USART_IsActiveFlag_RXNE
02578   * @param  USARTx USART Instance
02579   * @retval State of bit (1 or 0).
02580   */
02581 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
02582 {
02583   return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
02584 }
02585
02586 /**
02587   * @brief  Check if the USART Transmission Complete Flag is set or not
02588   * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
02589   * @param  USARTx USART Instance
02590   * @retval State of bit (1 or 0).
02591   */
02592 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
02593 {
02594   return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
02595 }
02596
02597 /**
02598   * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
02599   * @rmtoll ISR          TXE           LL_USART_IsActiveFlag_TXE
02600   * @param  USARTx USART Instance
02601   * @retval State of bit (1 or 0).
02602   */
02603 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
02604 {
02605   return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
02606 }
02607
02608 /**
02609   * @brief  Check if the USART LIN Break Detection Flag is set or not
02610   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02611   *         LIN feature is supported by the USARTx instance.
02612   * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
02613   * @param  USARTx USART Instance
02614   * @retval State of bit (1 or 0).
02615   */
02616 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
02617 {
02618   return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF));
02619 }
02620
02621 /**
02622   * @brief  Check if the USART CTS interrupt Flag is set or not
02623   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
02624   *         Hardware Flow control feature is supported by the USARTx instance.
02625   * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
02626   * @param  USARTx USART Instance
02627   * @retval State of bit (1 or 0).
02628   */
02629 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
02630 {
02631   return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
02632 }
02633
02634 /**
02635   * @brief  Check if the USART CTS Flag is set or not
02636   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
02637   *         Hardware Flow control feature is supported by the USARTx instance.
02638   * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
02639   * @param  USARTx USART Instance
02640   * @retval State of bit (1 or 0).
02641   */
02642 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
02643 {
02644   return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
02645 }
02646
02647 /**
02648   * @brief  Check if the USART Receiver Time Out Flag is set or not
02649   * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
02650   * @param  USARTx USART Instance
02651   * @retval State of bit (1 or 0).
02652   */
02653 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
02654 {
02655   return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF));
02656 }
02657
02658 /**
02659   * @brief  Check if the USART End Of Block Flag is set or not
02660   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02661   *         Smartcard feature is supported by the USARTx instance.
02662   * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
02663   * @param  USARTx USART Instance
02664   * @retval State of bit (1 or 0).
02665   */
02666 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
02667 {
02668   return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF));
02669 }
02670
02671 /**
02672   * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
02673   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
02674   *         Auto Baud Rate detection feature is supported by the USARTx instance.
02675   * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
02676   * @param  USARTx USART Instance
02677   * @retval State of bit (1 or 0).
02678   */
02679 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
02680 {
02681   return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE));
02682 }
02683
02684 /**
02685   * @brief  Check if the USART Auto-Baud Rate Flag is set or not
02686   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
02687   *         Auto Baud Rate detection feature is supported by the USARTx instance.
02688   * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
02689   * @param  USARTx USART Instance
02690   * @retval State of bit (1 or 0).
02691   */
02692 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
02693 {
02694   return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF));
02695 }
02696
02697 /**
02698   * @brief  Check if the USART Busy Flag is set or not
02699   * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
02700   * @param  USARTx USART Instance
02701   * @retval State of bit (1 or 0).
02702   */
02703 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
02704 {
02705   return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
02706 }
02707
02708 /**
02709   * @brief  Check if the USART Character Match Flag is set or not
02710   * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
02711   * @param  USARTx USART Instance
02712   * @retval State of bit (1 or 0).
02713   */
02714 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
02715 {
02716   return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
02717 }
02718
02719 /**
02720   * @brief  Check if the USART Send Break Flag is set or not
02721   * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
02722   * @param  USARTx USART Instance
02723   * @retval State of bit (1 or 0).
02724   */
02725 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
02726 {
02727   return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
02728 }
02729
02730 /**
02731   * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
02732   * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
02733   * @param  USARTx USART Instance
02734   * @retval State of bit (1 or 0).
02735   */
02736 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
02737 {
02738   return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
02739 }
02740
02741 /**
02742   * @brief  Check if the USART Wake Up from stop mode Flag is set or not
02743   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
02744   *         Wake-up from Stop mode feature is supported by the USARTx instance.
02745   * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
02746   * @param  USARTx USART Instance
02747   * @retval State of bit (1 or 0).
02748   */
02749 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
02750 {
02751   return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
02752 }
02753
02754 /**
02755   * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
02756   * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
02757   * @param  USARTx USART Instance
02758   * @retval State of bit (1 or 0).
02759   */
02760 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
02761 {
02762   return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
02763 }
02764
02765 /**
02766   * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
02767   * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
02768   * @param  USARTx USART Instance
02769   * @retval State of bit (1 or 0).
02770   */
02771 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
02772 {
02773   return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
02774 }
02775
02776 #if defined(USART_TCBGT_SUPPORT)
02777 /* Function available only on devices supporting Transmit Complete before Guard Time feature */
02778 /**
02779   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
02780   * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
02781   * @param  USARTx USART Instance
02782   * @retval State of bit (1 or 0).
02783   */
02784 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
02785 {
02786   return (READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT));
02787 }
02788 #endif
02789
02790 /**
02791   * @brief  Clear Parity Error Flag
02792   * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
02793   * @param  USARTx USART Instance
02794   * @retval None
02795   */
02796 __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
02797 {
02798   WRITE_REG(USARTx->ICR, USART_ICR_PECF);
02799 }
02800
02801 /**
02802   * @brief  Clear Framing Error Flag
02803   * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
02804   * @param  USARTx USART Instance
02805   * @retval None
02806   */
02807 __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
02808 {
02809   WRITE_REG(USARTx->ICR, USART_ICR_FECF);
02810 }
02811
02812 /**
02813   * @brief  Clear Noise detected Flag
02814   * @rmtoll ICR          NCF           LL_USART_ClearFlag_NE
02815   * @param  USARTx USART Instance
02816   * @retval None
02817   */
02818 __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
02819 {
02820   WRITE_REG(USARTx->ICR, USART_ICR_NCF);
02821 }
02822
02823 /**
02824   * @brief  Clear OverRun Error Flag
02825   * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
02826   * @param  USARTx USART Instance
02827   * @retval None
02828   */
02829 __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
02830 {
02831   WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
02832 }
02833
02834 /**
02835   * @brief  Clear IDLE line detected Flag
02836   * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
02837   * @param  USARTx USART Instance
02838   * @retval None
02839   */
02840 __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
02841 {
02842   WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
02843 }
02844
02845 /**
02846   * @brief  Clear Transmission Complete Flag
02847   * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
02848   * @param  USARTx USART Instance
02849   * @retval None
02850   */
02851 __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
02852 {
02853   WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
02854 }
02855
02856 #if defined(USART_TCBGT_SUPPORT)
02857 /* Function available only on devices supporting Transmit Complete before Guard Time feature */
02858 /**
02859   * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
02860   * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
02861   * @param  USARTx USART Instance
02862   * @retval None
02863   */
02864 __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
02865 {
02866   WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
02867 }
02868 #endif
02869
02870 /**
02871   * @brief  Clear LIN Break Detection Flag
02872   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02873   *         LIN feature is supported by the USARTx instance.
02874   * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
02875   * @param  USARTx USART Instance
02876   * @retval None
02877   */
02878 __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
02879 {
02880   WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
02881 }
02882
02883 /**
02884   * @brief  Clear CTS Interrupt Flag
02885   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
02886   *         Hardware Flow control feature is supported by the USARTx instance.
02887   * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
02888   * @param  USARTx USART Instance
02889   * @retval None
02890   */
02891 __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
02892 {
02893   WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
02894 }
02895
02896 /**
02897   * @brief  Clear Receiver Time Out Flag
02898   * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
02899   * @param  USARTx USART Instance
02900   * @retval None
02901   */
02902 __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
02903 {
02904   WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
02905 }
02906
02907 /**
02908   * @brief  Clear End Of Block Flag
02909   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02910   *         Smartcard feature is supported by the USARTx instance.
02911   * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
02912   * @param  USARTx USART Instance
02913   * @retval None
02914   */
02915 __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
02916 {
02917   WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
02918 }
02919
02920 /**
02921   * @brief  Clear Character Match Flag
02922   * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
02923   * @param  USARTx USART Instance
02924   * @retval None
02925   */
02926 __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
02927 {
02928   WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
02929 }
02930
02931 /**
02932   * @brief  Clear Wake Up from stop mode Flag
02933   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
02934   *         Wake-up from Stop mode feature is supported by the USARTx instance.
02935   * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
02936   * @param  USARTx USART Instance
02937   * @retval None
02938   */
02939 __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
02940 {
02941   WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
02942 }
02943
02944 /**
02945   * @}
02946   */
02947
02948 /** @defgroup USART_LL_EF_IT_Management IT_Management
02949   * @{
02950   */
02951
02952 /**
02953   * @brief  Enable IDLE Interrupt
02954   * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
02955   * @param  USARTx USART Instance
02956   * @retval None
02957   */
02958 __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
02959 {
02960   SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
02961 }
02962
02963 /**
02964   * @brief  Enable RX Not Empty Interrupt
02965   * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
02966   * @param  USARTx USART Instance
02967   * @retval None
02968   */
02969 __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
02970 {
02971   SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
02972 }
02973
02974 /**
02975   * @brief  Enable Transmission Complete Interrupt
02976   * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
02977   * @param  USARTx USART Instance
02978   * @retval None
02979   */
02980 __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
02981 {
02982   SET_BIT(USARTx->CR1, USART_CR1_TCIE);
02983 }
02984
02985 /**
02986   * @brief  Enable TX Empty Interrupt
02987   * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
02988   * @param  USARTx USART Instance
02989   * @retval None
02990   */
02991 __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
02992 {
02993   SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
02994 }
02995
02996 /**
02997   * @brief  Enable Parity Error Interrupt
02998   * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
02999   * @param  USARTx USART Instance
03000   * @retval None
03001   */
03002 __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
03003 {
03004   SET_BIT(USARTx->CR1, USART_CR1_PEIE);
03005 }
03006
03007 /**
03008   * @brief  Enable Character Match Interrupt
03009   * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
03010   * @param  USARTx USART Instance
03011   * @retval None
03012   */
03013 __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
03014 {
03015   SET_BIT(USARTx->CR1, USART_CR1_CMIE);
03016 }
03017
03018 /**
03019   * @brief  Enable Receiver Timeout Interrupt
03020   * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
03021   * @param  USARTx USART Instance
03022   * @retval None
03023   */
03024 __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
03025 {
03026   SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
03027 }
03028
03029 /**
03030   * @brief  Enable End Of Block Interrupt
03031   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03032   *         Smartcard feature is supported by the USARTx instance.
03033   * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
03034   * @param  USARTx USART Instance
03035   * @retval None
03036   */
03037 __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
03038 {
03039   SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
03040 }
03041
03042 /**
03043   * @brief  Enable LIN Break Detection Interrupt
03044   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03045   *         LIN feature is supported by the USARTx instance.
03046   * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
03047   * @param  USARTx USART Instance
03048   * @retval None
03049   */
03050 __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
03051 {
03052   SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
03053 }
03054
03055 /**
03056   * @brief  Enable Error Interrupt
03057   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03058   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03059   *           0: Interrupt is inhibited
03060   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03061   * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
03062   * @param  USARTx USART Instance
03063   * @retval None
03064   */
03065 __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
03066 {
03067   SET_BIT(USARTx->CR3, USART_CR3_EIE);
03068 }
03069
03070 /**
03071   * @brief  Enable CTS Interrupt
03072   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03073   *         Hardware Flow control feature is supported by the USARTx instance.
03074   * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
03075   * @param  USARTx USART Instance
03076   * @retval None
03077   */
03078 __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
03079 {
03080   SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
03081 }
03082
03083 /**
03084   * @brief  Enable Wake Up from Stop Mode Interrupt
03085   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03086   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03087   * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
03088   * @param  USARTx USART Instance
03089   * @retval None
03090   */
03091 __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
03092 {
03093   SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
03094 }
03095
03096 #if defined(USART_TCBGT_SUPPORT)
03097 /* Function available only on devices supporting Transmit Complete before Guard Time feature */
03098 /**
03099   * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
03100   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03101   *         Smartcard feature is supported by the USARTx instance.
03102   * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
03103   * @param  USARTx USART Instance
03104   * @retval None
03105   */
03106 __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
03107 {
03108   SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03109 }
03110 #endif
03111
03112 /**
03113   * @brief  Disable IDLE Interrupt
03114   * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
03115   * @param  USARTx USART Instance
03116   * @retval None
03117   */
03118 __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
03119 {
03120   CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03121 }
03122
03123 /**
03124   * @brief  Disable RX Not Empty Interrupt
03125   * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
03126   * @param  USARTx USART Instance
03127   * @retval None
03128   */
03129 __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
03130 {
03131   CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
03132 }
03133
03134 /**
03135   * @brief  Disable Transmission Complete Interrupt
03136   * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
03137   * @param  USARTx USART Instance
03138   * @retval None
03139   */
03140 __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
03141 {
03142   CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
03143 }
03144
03145 /**
03146   * @brief  Disable TX Empty Interrupt
03147   * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
03148   * @param  USARTx USART Instance
03149   * @retval None
03150   */
03151 __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
03152 {
03153   CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
03154 }
03155
03156 /**
03157   * @brief  Disable Parity Error Interrupt
03158   * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
03159   * @param  USARTx USART Instance
03160   * @retval None
03161   */
03162 __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
03163 {
03164   CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
03165 }
03166
03167 /**
03168   * @brief  Disable Character Match Interrupt
03169   * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
03170   * @param  USARTx USART Instance
03171   * @retval None
03172   */
03173 __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
03174 {
03175   CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
03176 }
03177
03178 /**
03179   * @brief  Disable Receiver Timeout Interrupt
03180   * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
03181   * @param  USARTx USART Instance
03182   * @retval None
03183   */
03184 __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
03185 {
03186   CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
03187 }
03188
03189 /**
03190   * @brief  Disable End Of Block Interrupt
03191   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03192   *         Smartcard feature is supported by the USARTx instance.
03193   * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
03194   * @param  USARTx USART Instance
03195   * @retval None
03196   */
03197 __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
03198 {
03199   CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
03200 }
03201
03202 /**
03203   * @brief  Disable LIN Break Detection Interrupt
03204   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03205   *         LIN feature is supported by the USARTx instance.
03206   * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
03207   * @param  USARTx USART Instance
03208   * @retval None
03209   */
03210 __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
03211 {
03212   CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
03213 }
03214
03215 /**
03216   * @brief  Disable Error Interrupt
03217   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03218   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03219   *           0: Interrupt is inhibited
03220   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03221   * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
03222   * @param  USARTx USART Instance
03223   * @retval None
03224   */
03225 __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
03226 {
03227   CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
03228 }
03229
03230 /**
03231   * @brief  Disable CTS Interrupt
03232   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03233   *         Hardware Flow control feature is supported by the USARTx instance.
03234   * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
03235   * @param  USARTx USART Instance
03236   * @retval None
03237   */
03238 __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
03239 {
03240   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
03241 }
03242
03243 /**
03244   * @brief  Disable Wake Up from Stop Mode Interrupt
03245   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03246   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03247   * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
03248   * @param  USARTx USART Instance
03249   * @retval None
03250   */
03251 __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
03252 {
03253   CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
03254 }
03255
03256 #if defined(USART_TCBGT_SUPPORT)
03257 /* Function available only on devices supporting Transmit Complete before Guard Time feature */
03258 /**
03259   * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
03260   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03261   *         Smartcard feature is supported by the USARTx instance.
03262   * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
03263   * @param  USARTx USART Instance
03264   * @retval None
03265   */
03266 __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
03267 {
03268   CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03269 }
03270 #endif
03271
03272 /**
03273   * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
03274   * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
03275   * @param  USARTx USART Instance
03276   * @retval State of bit (1 or 0).
03277   */
03278 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
03279 {
03280   return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
03281 }
03282
03283 /**
03284   * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
03285   * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
03286   * @param  USARTx USART Instance
03287   * @retval State of bit (1 or 0).
03288   */
03289 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
03290 {
03291   return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
03292 }
03293
03294 /**
03295   * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
03296   * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
03297   * @param  USARTx USART Instance
03298   * @retval State of bit (1 or 0).
03299   */
03300 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
03301 {
03302   return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
03303 }
03304
03305 /**
03306   * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
03307   * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
03308   * @param  USARTx USART Instance
03309   * @retval State of bit (1 or 0).
03310   */
03311 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
03312 {
03313   return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
03314 }
03315
03316 /**
03317   * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
03318   * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
03319   * @param  USARTx USART Instance
03320   * @retval State of bit (1 or 0).
03321   */
03322 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
03323 {
03324   return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
03325 }
03326
03327 /**
03328   * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
03329   * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
03330   * @param  USARTx USART Instance
03331   * @retval State of bit (1 or 0).
03332   */
03333 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
03334 {
03335   return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
03336 }
03337
03338 /**
03339   * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
03340   * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
03341   * @param  USARTx USART Instance
03342   * @retval State of bit (1 or 0).
03343   */
03344 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
03345 {
03346   return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE));
03347 }
03348
03349 /**
03350   * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
03351   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03352   *         Smartcard feature is supported by the USARTx instance.
03353   * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
03354   * @param  USARTx USART Instance
03355   * @retval State of bit (1 or 0).
03356   */
03357 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
03358 {
03359   return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE));
03360 }
03361
03362 /**
03363   * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
03364   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03365   *         LIN feature is supported by the USARTx instance.
03366   * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
03367   * @param  USARTx USART Instance
03368   * @retval State of bit (1 or 0).
03369   */
03370 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
03371 {
03372   return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
03373 }
03374
03375 /**
03376   * @brief  Check if the USART Error Interrupt is enabled or disabled.
03377   * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
03378   * @param  USARTx USART Instance
03379   * @retval State of bit (1 or 0).
03380   */
03381 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
03382 {
03383   return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
03384 }
03385
03386 /**
03387   * @brief  Check if the USART CTS Interrupt is enabled or disabled.
03388   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03389   *         Hardware Flow control feature is supported by the USARTx instance.
03390   * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
03391   * @param  USARTx USART Instance
03392   * @retval State of bit (1 or 0).
03393   */
03394 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
03395 {
03396   return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
03397 }
03398
03399 /**
03400   * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
03401   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03402   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03403   * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
03404   * @param  USARTx USART Instance
03405   * @retval State of bit (1 or 0).
03406   */
03407 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
03408 {
03409   return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
03410 }
03411
03412 #if defined(USART_TCBGT_SUPPORT)
03413 /* Function available only on devices supporting Transmit Complete before Guard Time feature */
03414 /**
03415   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
03416   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03417   *         Smartcard feature is supported by the USARTx instance.
03418   * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
03419   * @param  USARTx USART Instance
03420   * @retval State of bit (1 or 0).
03421   */
03422 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
03423 {
03424   return (READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE));
03425 }
03426 #endif
03427
03428 /**
03429   * @}
03430   */
03431
03432 /** @defgroup USART_LL_EF_DMA_Management DMA_Management
03433   * @{
03434   */
03435
03436 /**
03437   * @brief  Enable DMA Mode for reception
03438   * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
03439   * @param  USARTx USART Instance
03440   * @retval None
03441   */
03442 __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
03443 {
03444   SET_BIT(USARTx->CR3, USART_CR3_DMAR);
03445 }
03446
03447 /**
03448   * @brief  Disable DMA Mode for reception
03449   * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
03450   * @param  USARTx USART Instance
03451   * @retval None
03452   */
03453 __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
03454 {
03455   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
03456 }
03457
03458 /**
03459   * @brief  Check if DMA Mode is enabled for reception
03460   * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
03461   * @param  USARTx USART Instance
03462   * @retval State of bit (1 or 0).
03463   */
03464 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
03465 {
03466   return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
03467 }
03468
03469 /**
03470   * @brief  Enable DMA Mode for transmission
03471   * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
03472   * @param  USARTx USART Instance
03473   * @retval None
03474   */
03475 __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
03476 {
03477   SET_BIT(USARTx->CR3, USART_CR3_DMAT);
03478 }
03479
03480 /**
03481   * @brief  Disable DMA Mode for transmission
03482   * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
03483   * @param  USARTx USART Instance
03484   * @retval None
03485   */
03486 __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
03487 {
03488   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
03489 }
03490
03491 /**
03492   * @brief  Check if DMA Mode is enabled for transmission
03493   * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
03494   * @param  USARTx USART Instance
03495   * @retval State of bit (1 or 0).
03496   */
03497 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
03498 {
03499   return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
03500 }
03501
03502 /**
03503   * @brief  Enable DMA Disabling on Reception Error
03504   * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
03505   * @param  USARTx USART Instance
03506   * @retval None
03507   */
03508 __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
03509 {
03510   SET_BIT(USARTx->CR3, USART_CR3_DDRE);
03511 }
03512
03513 /**
03514   * @brief  Disable DMA Disabling on Reception Error
03515   * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
03516   * @param  USARTx USART Instance
03517   * @retval None
03518   */
03519 __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
03520 {
03521   CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
03522 }
03523
03524 /**
03525   * @brief  Indicate if DMA Disabling on Reception Error is disabled
03526   * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
03527   * @param  USARTx USART Instance
03528   * @retval State of bit (1 or 0).
03529   */
03530 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
03531 {
03532   return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
03533 }
03534
03535 /**
03536   * @brief  Get the data register address used for DMA transfer
03537   * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
03538   * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
03539   * @param  USARTx USART Instance
03540   * @param  Direction This parameter can be one of the following values:
03541   *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
03542   *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
03543   * @retval Address of data register
03544   */
03545 __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
03546 {
03547   register uint32_t data_reg_addr = 0U;
03548
03549   if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
03550   {
03551     /* return address of TDR register */
03552     data_reg_addr = (uint32_t) &(USARTx->TDR);
03553   }
03554   else
03555   {
03556     /* return address of RDR register */
03557     data_reg_addr = (uint32_t) &(USARTx->RDR);
03558   }
03559
03560   return data_reg_addr;
03561 }
03562
03563 /**
03564   * @}
03565   */
03566
03567 /** @defgroup USART_LL_EF_Data_Management Data_Management
03568   * @{
03569   */
03570
03571 /**
03572   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
03573   * @rmtoll RDR          RDR           LL_USART_ReceiveData8
03574   * @param  USARTx USART Instance
03575   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
03576   */
03577 __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
03578 {
03579   return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
03580 }
03581
03582 /**
03583   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
03584   * @rmtoll RDR          RDR           LL_USART_ReceiveData9
03585   * @param  USARTx USART Instance
03586   * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
03587   */
03588 __STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
03589 {
03590   return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
03591 }
03592
03593 /**
03594   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
03595   * @rmtoll TDR          TDR           LL_USART_TransmitData8
03596   * @param  USARTx USART Instance
03597   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
03598   * @retval None
03599   */
03600 __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
03601 {
03602   USARTx->TDR = Value;
03603 }
03604
03605 /**
03606   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
03607   * @rmtoll TDR          TDR           LL_USART_TransmitData9
03608   * @param  USARTx USART Instance
03609   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
03610   * @retval None
03611   */
03612 __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
03613 {
03614   USARTx->TDR = Value & 0x1FFU;
03615 }
03616
03617 /**
03618   * @}
03619   */
03620
03621 /** @defgroup USART_LL_EF_Execution Execution
03622   * @{
03623   */
03624
03625 /**
03626   * @brief  Request an Automatic Baud Rate measurement on next received data frame
03627   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03628   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03629   * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
03630   * @param  USARTx USART Instance
03631   * @retval None
03632   */
03633 __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
03634 {
03635   SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);
03636 }
03637
03638 /**
03639   * @brief  Request Break sending
03640   * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
03641   * @param  USARTx USART Instance
03642   * @retval None
03643   */
03644 __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
03645 {
03646   SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);
03647 }
03648
03649 /**
03650   * @brief  Put USART in mute mode and set the RWU flag
03651   * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
03652   * @param  USARTx USART Instance
03653   * @retval None
03654   */
03655 __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
03656 {
03657   SET_BIT(USARTx->RQR, USART_RQR_MMRQ);
03658 }
03659
03660 /**
03661   * @brief  Request a Receive Data flush
03662   * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
03663   * @param  USARTx USART Instance
03664   * @retval None
03665   */
03666 __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
03667 {
03668   SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);
03669 }
03670
03671 /**
03672   * @brief  Request a Transmit data flush
03673   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03674   *         Smartcard feature is supported by the USARTx instance.
03675   * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
03676   * @param  USARTx USART Instance
03677   * @retval None
03678   */
03679 __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
03680 {
03681   SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);
03682 }
03683
03684 /**
03685   * @}
03686   */
03687
03688 #if defined(USE_FULL_LL_DRIVER)
03689 /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
03690   * @{
03691   */
03692 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
03693 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
03694 void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
03695 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
03696 void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
03697 /**
03698   * @}
03699   */
03700 #endif /* USE_FULL_LL_DRIVER */
03701
03702 /**
03703   * @}
03704   */
03705
03706 /**
03707   * @}
03708   */
03709
03710 #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
03711
03712 /**
03713   * @}
03714   */
03715
03716 #ifdef __cplusplus
03717 }
03718 #endif
03719
03720 #endif /* __STM32L4xx_LL_USART_H */
03721
03722 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_utils.c Source File

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stm32l4xx_ll_utils.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_utils.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   UTILS LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32l4xx_ll_utils.h"
00039 #include "stm32l4xx_ll_rcc.h"
00040 #include "stm32l4xx_ll_system.h"
00041 #include "stm32l4xx_ll_pwr.h"
00042 #ifdef  USE_FULL_ASSERT
00043 #include "stm32_assert.h"
00044 #else
00045 #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32L4xx_LL_Driver
00049   * @{
00050   */
00051
00052 /** @addtogroup UTILS_LL
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private constants ---------------------------------------------------------*/
00059 /** @addtogroup UTILS_LL_Private_Constants
00060   * @{
00061   */
00062 #define UTILS_MAX_FREQUENCY_SCALE1  ((uint32_t)80000000)        /*!< Maximum frequency for system clock at power scale1, in Hz */
00063 #define UTILS_MAX_FREQUENCY_SCALE2  ((uint32_t)26000000)        /*!< Maximum frequency for system clock at power scale2, in Hz */
00064
00065 /* Defines used for PLL range */
00066 #define UTILS_PLLVCO_INPUT_MIN      ((uint32_t)4000000)         /*!< Frequency min for PLLVCO input, in Hz   */
00067 #define UTILS_PLLVCO_INPUT_MAX      ((uint32_t)16000000)        /*!< Frequency max for PLLVCO input, in Hz   */
00068 #define UTILS_PLLVCO_OUTPUT_MIN     ((uint32_t)64000000)        /*!< Frequency min for PLLVCO output, in Hz  */
00069 #define UTILS_PLLVCO_OUTPUT_MAX     ((uint32_t)344000000)       /*!< Frequency max for PLLVCO output, in Hz  */
00070
00071 /* Defines used for HSE range */
00072 #define UTILS_HSE_FREQUENCY_MIN     ((uint32_t)4000000)         /*!< Frequency min for HSE frequency, in Hz   */
00073 #define UTILS_HSE_FREQUENCY_MAX     ((uint32_t)48000000)        /*!< Frequency max for HSE frequency, in Hz   */
00074
00075 /* Defines used for FLASH latency according to HCLK Frequency */
00076 #define UTILS_SCALE1_LATENCY1_FREQ  ((uint32_t)16000000)        /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
00077 #define UTILS_SCALE1_LATENCY2_FREQ  ((uint32_t)32000000)        /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
00078 #define UTILS_SCALE1_LATENCY3_FREQ  ((uint32_t)48000000)        /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
00079 #define UTILS_SCALE1_LATENCY4_FREQ  ((uint32_t)64000000)        /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
00080 #define UTILS_SCALE2_LATENCY1_FREQ  ((uint32_t)6000000)         /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
00081 #define UTILS_SCALE2_LATENCY2_FREQ  ((uint32_t)12000000)        /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
00082 #define UTILS_SCALE2_LATENCY3_FREQ  ((uint32_t)18000000)        /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
00083 /**
00084   * @}
00085   */
00086
00087 /* Private macros ------------------------------------------------------------*/
00088 /** @addtogroup UTILS_LL_Private_Macros
00089   * @{
00090   */
00091 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
00092                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
00093                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
00094                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
00095                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
00096                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
00097                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
00098                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
00099                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
00100
00101 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
00102                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
00103                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
00104                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
00105                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
00106
00107 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
00108                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
00109                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
00110                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
00111                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
00112
00113 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
00114                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
00115                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
00116                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
00117                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
00118                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
00119                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
00120                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_8))
00121
00122 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
00123
00124 #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
00125                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
00126                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
00127                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
00128
00129 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
00130
00131 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
00132
00133 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
00134                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
00135
00136 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
00137                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
00138
00139 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
00140 /**
00141   * @}
00142   */
00143 /* Private function prototypes -----------------------------------------------*/
00144 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
00145   * @{
00146   */
00147 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
00148                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
00149 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
00150 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00151 static ErrorStatus UTILS_PLL_IsBusy(void);
00152 /**
00153   * @}
00154   */
00155
00156 /* Exported functions --------------------------------------------------------*/
00157 /** @addtogroup UTILS_LL_Exported_Functions
00158   * @{
00159   */
00160
00161 /** @addtogroup UTILS_LL_EF_DELAY
00162   * @{
00163   */
00164
00165 /**
00166   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
00167   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
00168   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00169   * @param  HCLKFrequency HCLK frequency in Hz
00170   * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
00171   * @retval None
00172   */
00173 void LL_Init1msTick(uint32_t HCLKFrequency)
00174 {
00175   /* Use frequency provided in argument */
00176   LL_InitTick(HCLKFrequency, 1000);
00177 }
00178
00179 /**
00180   * @brief  This function provides accurate delay (in milliseconds) based
00181   *         on SysTick counter flag
00182   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
00183   *         and use rather osDelay service.
00184   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
00185   *         will configure Systick to 1ms
00186   * @param  Delay specifies the delay time length, in milliseconds.
00187   * @retval None
00188   */
00189 void LL_mDelay(uint32_t Delay)
00190 {
00191   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
00192   /* Add this code to indicate that local variable is not used */
00193   ((void)tmp);
00194
00195   /* Add a period to guaranty minimum wait */
00196   if (Delay < LL_MAX_DELAY)
00197   {
00198     Delay++;
00199   }
00200
00201   while (Delay)
00202   {
00203     if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0)
00204     {
00205       Delay--;
00206     }
00207   }
00208 }
00209
00210 /**
00211   * @}
00212   */
00213
00214 /** @addtogroup UTILS_EF_SYSTEM
00215   *  @brief    System Configuration functions
00216   *
00217   @verbatim
00218  ===============================================================================
00219            ##### System Configuration functions #####
00220  ===============================================================================
00221     [..]
00222          System, AHB and APB buses clocks configuration
00223
00224          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80000000 Hz.
00225   @endverbatim
00226   @internal
00227              Depending on the device voltage range, the maximum frequency should be
00228              adapted accordingly:
00229
00230              (++)  Table 1. HCLK clock frequency.
00231              (++)  +-------------------------------------------------------+
00232              (++)  | Latency         |    HCLK clock frequency (MHz)       |
00233              (++)  |                 |-------------------------------------|
00234              (++)  |                 | voltage range 1  | voltage range 2  |
00235              (++)  |                 |      1.2 V       |     1.0 V        |
00236              (++)  |-----------------|------------------|------------------|
00237              (++)  |0WS(1 CPU cycles)|  0 < HCLK <= 16  |  0 < HCLK <= 6   |
00238              (++)  |-----------------|------------------|------------------|
00239              (++)  |1WS(2 CPU cycles)| 16 < HCLK <= 32  |  6 < HCLK <= 12  |
00240              (++)  |-----------------|------------------|------------------|
00241              (++)  |2WS(3 CPU cycles)| 32 < HCLK <= 48  | 12 < HCLK <= 18  |
00242              (++)  |-----------------|------------------|------------------|
00243              (++)  |3WS(4 CPU cycles)| 48 < HCLK <= 64  | 18 < HCLK <= 26  |
00244              (++)  |-----------------|------------------|------------------|
00245              (++)  |4WS(5 CPU cycles)| 64 < HCLK <= 80  | 18 < HCLK <= 26  |
00246              (++)  +-------------------------------------------------------+
00247   @endinternal
00248   * @{
00249   */
00250
00251 /**
00252   * @brief  This function sets directly SystemCoreClock CMSIS variable.
00253   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
00254   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00255   * @retval None
00256   */
00257 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
00258 {
00259   /* HCLK clock frequency */
00260   SystemCoreClock = HCLKFrequency;
00261 }
00262
00263 /**
00264   * @brief  This function configures system clock with MSI as clock source of the PLL
00265   * @note   The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
00266   * @note   Function is based on the following formula:
00267   *         - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
00268   *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
00269   *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00270   *         - PLLR: ensure that max frequency at 80 MHz is reach (PLLVCO_output / PLLR)
00271   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00272   *                             the configuration information for the PLL.
00273   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00274   *                             the configuration information for the BUS prescalers.
00275   * @retval An ErrorStatus enumeration value:
00276   *          - SUCCESS: Max frequency configuration done
00277   *          - ERROR: Max frequency configuration not done
00278   */
00279 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00280                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00281 {
00282   ErrorStatus status = SUCCESS;
00283   uint32_t pllfreq = 0, msi_range = 0;
00284
00285   /* Check if one of the PLL is enabled */
00286   if (UTILS_PLL_IsBusy() == SUCCESS)
00287   {
00288     /* Get the current MSI range */
00289     if (LL_RCC_MSI_IsEnabledRangeSelect())
00290     {
00291       msi_range =  LL_RCC_MSI_GetRange();
00292       switch (msi_range)
00293       {
00294         case LL_RCC_MSIRANGE_0:     /* MSI = 100 KHz  */
00295         case LL_RCC_MSIRANGE_1:     /* MSI = 200 KHz  */
00296         case LL_RCC_MSIRANGE_2:     /* MSI = 400 KHz  */
00297         case LL_RCC_MSIRANGE_3:     /* MSI = 800 KHz  */
00298         case LL_RCC_MSIRANGE_4:     /* MSI = 1 MHz    */
00299         case LL_RCC_MSIRANGE_5:     /* MSI = 2 MHz    */
00300           /* PLLVCO input frequency can not in the range from 4 to 16 MHz*/
00301           status = ERROR;
00302           break;
00303
00304         case LL_RCC_MSIRANGE_6:     /* MSI = 4 MHz    */
00305         case LL_RCC_MSIRANGE_7:     /* MSI = 8 MHz    */
00306         case LL_RCC_MSIRANGE_8:     /* MSI = 16 MHz   */
00307         case LL_RCC_MSIRANGE_9:     /* MSI = 24 MHz   */
00308         case LL_RCC_MSIRANGE_10:    /* MSI = 32 MHz   */
00309         case LL_RCC_MSIRANGE_11:    /* MSI = 48 MHz   */
00310         default:
00311           break;
00312       }
00313     }
00314     else
00315     {
00316       msi_range = LL_RCC_MSI_GetRangeAfterStandby();
00317       switch (msi_range)
00318       {
00319         case LL_RCC_MSISRANGE_4:    /* MSI = 1 MHz    */
00320         case LL_RCC_MSISRANGE_5:    /* MSI = 2 MHz    */
00321           /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/
00322           status = ERROR;
00323           break;
00324
00325         case LL_RCC_MSISRANGE_7:    /* MSI = 8 MHz    */
00326         case LL_RCC_MSISRANGE_6:    /* MSI = 4 MHz    */
00327         default:
00328           break;
00329       }
00330     }
00331
00332     /* Main PLL configuration and activation */
00333     if (status != ERROR)
00334     {
00335       /* Calculate the new PLL output frequency */
00336       pllfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range),
00337                                             UTILS_PLLInitStruct);
00338
00339       /* Enable MSI if not enabled */
00340       if (LL_RCC_MSI_IsReady() != 1)
00341       {
00342         LL_RCC_MSI_Enable();
00343         while ((LL_RCC_MSI_IsReady() != 1))
00344         {
00345           /* Wait for MSI ready */
00346         }
00347       }
00348
00349       /* Configure PLL */
00350       LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
00351                                   UTILS_PLLInitStruct->PLLR);
00352
00353       /* Enable PLL and switch system clock to PLL */
00354       status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00355     }
00356   }
00357   else
00358   {
00359     /* Current PLL configuration cannot be modified */
00360     status = ERROR;
00361   }
00362
00363   return status;
00364 }
00365
00366 /**
00367   * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
00368   * @note   The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
00369   * @note   Function is based on the following formula:
00370   *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
00371   *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
00372   *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00373   *         - PLLR: ensure that max frequency at 80 MHz is reach (PLLVCO_output / PLLR)
00374   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00375   *                             the configuration information for the PLL.
00376   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00377   *                             the configuration information for the BUS prescalers.
00378   * @retval An ErrorStatus enumeration value:
00379   *          - SUCCESS: Max frequency configuration done
00380   *          - ERROR: Max frequency configuration not done
00381   */
00382 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00383                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00384 {
00385   ErrorStatus status = SUCCESS;
00386   uint32_t pllfreq = 0;
00387
00388   /* Check if one of the PLL is enabled */
00389   if (UTILS_PLL_IsBusy() == SUCCESS)
00390   {
00391     /* Calculate the new PLL output frequency */
00392     pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
00393
00394     /* Enable HSI if not enabled */
00395     if (LL_RCC_HSI_IsReady() != 1)
00396     {
00397       LL_RCC_HSI_Enable();
00398       while (LL_RCC_HSI_IsReady() != 1)
00399       {
00400         /* Wait for HSI ready */
00401       }
00402     }
00403
00404     /* Configure PLL */
00405     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
00406                                 UTILS_PLLInitStruct->PLLR);
00407
00408     /* Enable PLL and switch system clock to PLL */
00409     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00410   }
00411   else
00412   {
00413     /* Current PLL configuration cannot be modified */
00414     status = ERROR;
00415   }
00416
00417   return status;
00418 }
00419
00420 /**
00421   * @brief  This function configures system clock with HSE as clock source of the PLL
00422   * @note   The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.
00423   * @note   Function is based on the following formula:
00424   *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
00425   *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
00426   *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00427   *         - PLLR: ensure that max frequency at 80 MHz is reach (PLLVCO_output / PLLR)
00428   * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
00429   * @param  HSEBypass This parameter can be one of the following values:
00430   *         @arg @ref LL_UTILS_HSEBYPASS_ON
00431   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
00432   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00433   *                             the configuration information for the PLL.
00434   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00435   *                             the configuration information for the BUS prescalers.
00436   * @retval An ErrorStatus enumeration value:
00437   *          - SUCCESS: Max frequency configuration done
00438   *          - ERROR: Max frequency configuration not done
00439   */
00440 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00441                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00442 {
00443   ErrorStatus status = SUCCESS;
00444   uint32_t pllfreq = 0;
00445
00446   /* Check the parameters */
00447   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
00448   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
00449
00450   /* Check if one of the PLL is enabled */
00451   if (UTILS_PLL_IsBusy() == SUCCESS)
00452   {
00453     /* Calculate the new PLL output frequency */
00454     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
00455
00456     /* Enable HSE if not enabled */
00457     if (LL_RCC_HSE_IsReady() != 1)
00458     {
00459       /* Check if need to enable HSE bypass feature or not */
00460       if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
00461       {
00462         LL_RCC_HSE_EnableBypass();
00463       }
00464       else
00465       {
00466         LL_RCC_HSE_DisableBypass();
00467       }
00468
00469       /* Enable HSE */
00470       LL_RCC_HSE_Enable();
00471       while (LL_RCC_HSE_IsReady() != 1)
00472       {
00473         /* Wait for HSE ready */
00474       }
00475     }
00476
00477     /* Configure PLL */
00478     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
00479                                 UTILS_PLLInitStruct->PLLR);
00480
00481     /* Enable PLL and switch system clock to PLL */
00482     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00483   }
00484   else
00485   {
00486     /* Current PLL configuration cannot be modified */
00487     status = ERROR;
00488   }
00489
00490   return status;
00491 }
00492
00493 /**
00494   * @}
00495   */
00496
00497 /**
00498   * @}
00499   */
00500
00501 /** @addtogroup UTILS_LL_Private_Functions
00502   * @{
00503   */
00504 /**
00505   * @brief  Update number of Flash wait states in line with new frequency and current
00506             voltage range.
00507   * @param  HCLK_Frequency  HCLK frequency
00508   * @retval An ErrorStatus enumeration value:
00509   *          - SUCCESS: Latency has been modified
00510   *          - ERROR: Latency cannot be modified
00511   */
00512 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
00513 {
00514   ErrorStatus status = SUCCESS;
00515
00516   uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
00517
00518   /* Frequency cannot be equal to 0 */
00519   if (HCLK_Frequency == 0)
00520   {
00521     status = ERROR;
00522   }
00523   else
00524   {
00525     if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
00526     {
00527       if (HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)
00528       {
00529         /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */
00530         latency = LL_FLASH_LATENCY_4;
00531       }
00532       else if (HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)
00533       {
00534         /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */
00535         latency = LL_FLASH_LATENCY_3;
00536       }
00537       else if (HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)
00538       {
00539         /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */
00540         latency = LL_FLASH_LATENCY_2;
00541       }
00542       else
00543       {
00544         if (HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
00545         {
00546           /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
00547           latency = LL_FLASH_LATENCY_1;
00548         }
00549         /* else HCLK_Frequency < 16MHz default LL_FLASH_LATENCY_0 0WS */
00550       }
00551     }
00552     else
00553     {
00554       if (HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
00555       {
00556         /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */
00557         latency = LL_FLASH_LATENCY_3;
00558       }
00559       else if (HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
00560       {
00561         /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */
00562         latency = LL_FLASH_LATENCY_2;
00563       }
00564       else
00565       {
00566         if (HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
00567         {
00568           /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */
00569           latency = LL_FLASH_LATENCY_1;
00570         }
00571         /* else HCLK_Frequency < 6MHz default LL_FLASH_LATENCY_0 0WS */
00572       }
00573     }
00574
00575     LL_FLASH_SetLatency(latency);
00576
00577     /* Check that the new number of wait states is taken into account to access the Flash
00578        memory by reading the FLASH_ACR register */
00579     if (LL_FLASH_GetLatency() != latency)
00580     {
00581       status = ERROR;
00582     }
00583   }
00584   return status;
00585 }
00586
00587 /**
00588   * @brief  Function to check that PLL can be modified
00589   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
00590   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00591   *                             the configuration information for the PLL.
00592   * @retval PLL output frequency (in Hz)
00593   */
00594 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
00595 {
00596   uint32_t pllfreq = 0;
00597
00598   /* Check the parameters */
00599   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
00600   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
00601   assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
00602
00603   /* Check different PLL parameters according to RM                          */
00604   /*  - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz.   */
00605   pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_POSITION_PLLM) + 1));
00606   assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
00607
00608   /*  - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
00609   pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_POSITION_PLLN));
00610   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
00611
00612   /*  - PLLR: ensure that max frequency at 80 MHz is reach                   */
00613   pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_POSITION_PLLR) + 1) * 2);
00614   assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
00615
00616   return pllfreq;
00617 }
00618
00619 /**
00620   * @brief  Function to check that PLL can be modified
00621   * @retval An ErrorStatus enumeration value:
00622   *          - SUCCESS: PLL modification can be done
00623   *          - ERROR: PLL is busy
00624   */
00625 static ErrorStatus UTILS_PLL_IsBusy(void)
00626 {
00627   ErrorStatus status = SUCCESS;
00628
00629   /* Check if PLL is busy*/
00630   if (LL_RCC_PLL_IsReady() != 0)
00631   {
00632     /* PLL configuration cannot be modified */
00633     status = ERROR;
00634   }
00635
00636   /* Check if PLLSAI1 is busy*/
00637   if (LL_RCC_PLLSAI1_IsReady() != 0)
00638   {
00639     /* PLLSAI1 configuration cannot be modified */
00640     status = ERROR;
00641   }
00642
00643 #if defined(RCC_PLLSAI2_SUPPORT)
00644   /* Check if PLLSAI2 is busy*/
00645   if (LL_RCC_PLLSAI2_IsReady() != 0)
00646   {
00647     /* PLLSAI2 configuration cannot be modified */
00648     status = ERROR;
00649   }
00650 #endif /*RCC_PLLSAI2_SUPPORT*/
00651
00652
00653   return status;
00654 }
00655
00656 /**
00657   * @brief  Function to enable PLL and switch system clock to PLL
00658   * @param  SYSCLK_Frequency SYSCLK frequency
00659   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00660   *                             the configuration information for the BUS prescalers.
00661   * @retval An ErrorStatus enumeration value:
00662   *          - SUCCESS: No problem to switch system to PLL
00663   *          - ERROR: Problem to switch system to PLL
00664   */
00665 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00666 {
00667   ErrorStatus status = SUCCESS;
00668   uint32_t hclk_frequency = 0;
00669
00670   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
00671   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
00672   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
00673
00674   /* Calculate HCLK frequency */
00675   hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
00676
00677   /* Increasing the number of wait states because of higher CPU frequency */
00678   if (SystemCoreClock < hclk_frequency)
00679   {
00680     /* Set FLASH latency to highest latency */
00681     status = UTILS_SetFlashLatency(hclk_frequency);
00682   }
00683
00684   /* Update system clock configuration */
00685   if (status == SUCCESS)
00686   {
00687     /* Enable PLL */
00688     LL_RCC_PLL_Enable();
00689     LL_RCC_PLL_EnableDomain_SYS();
00690     while (LL_RCC_PLL_IsReady() != 1)
00691     {
00692       /* Wait for PLL ready */
00693     }
00694
00695     /* Sysclk activation on the main PLL */
00696     LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
00697     LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
00698     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
00699     {
00700       /* Wait for system clock switch to PLL */
00701     }
00702
00703     /* Set APB1 & APB2 prescaler*/
00704     LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
00705     LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
00706   }
00707
00708   /* Decreasing the number of wait states because of lower CPU frequency */
00709   if (SystemCoreClock > hclk_frequency)
00710   {
00711     /* Set FLASH latency to lowest latency */
00712     status = UTILS_SetFlashLatency(hclk_frequency);
00713   }
00714
00715   /* Update SystemCoreClock variable */
00716   if (status == SUCCESS)
00717   {
00718     LL_SetSystemCoreClock(hclk_frequency);
00719   }
00720
00721   return status;
00722 }
00723
00724 /**
00725   * @}
00726   */
00727
00728 /**
00729   * @}
00730   */
00731
00732 /**
00733   * @}
00734   */
00735
00736 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_utils.h Source File

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stm32l4xx_ll_utils.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_utils.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of UTILS LL module.
00008   @verbatim
00009   ==============================================================================
00010                      ##### How to use this driver #####
00011   ==============================================================================
00012     [..]
00013     The LL UTILS driver contains a set of generic APIs that can be
00014     used by user:
00015       (+) Device electronic signature
00016       (+) Timing functions
00017       (+) PLL configuration functions
00018
00019   @endverbatim
00020   ******************************************************************************
00021   * @attention
00022   *
00023   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00024   *
00025   * Redistribution and use in source and binary forms, with or without modification,
00026   * are permitted provided that the following conditions are met:
00027   *   1. Redistributions of source code must retain the above copyright notice,
00028   *      this list of conditions and the following disclaimer.
00029   *   2. Redistributions in binary form must reproduce the above copyright notice,
00030   *      this list of conditions and the following disclaimer in the documentation
00031   *      and/or other materials provided with the distribution.
00032   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00033   *      may be used to endorse or promote products derived from this software
00034   *      without specific prior written permission.
00035   *
00036   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00037   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00038   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00039   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00040   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00041   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00042   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00043   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00044   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00045   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00046   *
00047   ******************************************************************************
00048   */
00049
00050 /* Define to prevent recursive inclusion -------------------------------------*/
00051 #ifndef __STM32L4xx_LL_UTILS_H
00052 #define __STM32L4xx_LL_UTILS_H
00053
00054 #ifdef __cplusplus
00055 extern "C" {
00056 #endif
00057
00058 /* Includes ------------------------------------------------------------------*/
00059 #include "stm32l4xx.h"
00060
00061 /** @addtogroup STM32L4xx_LL_Driver
00062   * @{
00063   */
00064
00065 /** @defgroup UTILS_LL UTILS
00066   * @{
00067   */
00068
00069 /* Private types -------------------------------------------------------------*/
00070 /* Private variables ---------------------------------------------------------*/
00071
00072 /* Private constants ---------------------------------------------------------*/
00073 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
00074   * @{
00075   */
00076
00077 /* Max delay can be used in LL_mDelay */
00078 #define LL_MAX_DELAY                  (uint32_t)0xFFFFFFFFU
00079
00080 /**
00081  * @brief Unique device ID register base address
00082  */
00083 #define UID_BASE_ADDRESS              UID_BASE
00084
00085 /**
00086  * @brief Flash size data register base address
00087  */
00088 #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
00089
00090 /**
00091  * @brief Package data register base address
00092  */
00093 #define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Private macros ------------------------------------------------------------*/
00100 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
00101   * @{
00102   */
00103 /**
00104   * @}
00105   */
00106 /* Exported types ------------------------------------------------------------*/
00107 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
00108   * @{
00109   */
00110 /**
00111   * @brief  UTILS PLL structure definition
00112   */
00113 typedef struct
00114 {
00115   uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
00116                         This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
00117
00118                         This feature can be modified afterwards using unitary function
00119                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00120
00121   uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
00122                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
00123
00124                         This feature can be modified afterwards using unitary function
00125                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00126
00127   uint32_t PLLR;   /*!< Division for the main system clock.
00128                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
00129
00130                         This feature can be modified afterwards using unitary function
00131                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00132 } LL_UTILS_PLLInitTypeDef;
00133
00134 /**
00135   * @brief  UTILS System, AHB and APB buses clock configuration structure definition
00136   */
00137 typedef struct
00138 {
00139   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00140                                        This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
00141
00142                                        This feature can be modified afterwards using unitary function
00143                                        @ref LL_RCC_SetAHBPrescaler(). */
00144
00145   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00146                                        This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
00147
00148                                        This feature can be modified afterwards using unitary function
00149                                        @ref LL_RCC_SetAPB1Prescaler(). */
00150
00151   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00152                                        This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
00153
00154                                        This feature can be modified afterwards using unitary function
00155                                        @ref LL_RCC_SetAPB2Prescaler(). */
00156
00157 } LL_UTILS_ClkInitTypeDef;
00158
00159 /**
00160   * @}
00161   */
00162
00163 /* Exported constants --------------------------------------------------------*/
00164 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
00165   * @{
00166   */
00167
00168 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
00169   * @{
00170   */
00171 #define LL_UTILS_HSEBYPASS_OFF        (uint32_t)0x00000000U       /*!< HSE Bypass is not enabled                */
00172 #define LL_UTILS_HSEBYPASS_ON         (uint32_t)0x00000001U       /*!< HSE Bypass is enabled                    */
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
00178   * @{
00179   */
00180 #define LL_UTILS_PACKAGETYPE_LQFP64         (uint32_t)0x00000000U /*!< LQFP64 package type                      */
00181 #define LL_UTILS_PACKAGETYPE_WLCSP64        (uint32_t)0x00000001U /*!< WLCSP64 package type                     */
00182 #define LL_UTILS_PACKAGETYPE_LQFP100        (uint32_t)0x00000002U /*!< LQFP100 package type                     */
00183 #define LL_UTILS_PACKAGETYPE_BGA132         (uint32_t)0x00000003U /*!< BGA132 package type                      */
00184 #define LL_UTILS_PACKAGETYPE_LQFP144_CSP72  (uint32_t)0x00000004U /*!< LQFP144, WLCSP81 or WLCSP72 package type */
00185 #define LL_UTILS_PACKAGETYPE_UFQFPN32       (uint32_t)0x00000008U /*!< UFQFPN32 package type                    */
00186 #define LL_UTILS_PACKAGETYPE_UFQFPN48       (uint32_t)0x0000000AU /*!< UFQFPN48 package type                    */
00187 #define LL_UTILS_PACKAGETYPE_LQFP48         (uint32_t)0x0000000BU /*!< LQFP48 package type                      */
00188 #define LL_UTILS_PACKAGETYPE_WLCSP49        (uint32_t)0x0000000CU /*!< WLCSP49 package type                     */
00189 #define LL_UTILS_PACKAGETYPE_UFBGA64        (uint32_t)0x0000000DU /*!< UFBGA64 package type                     */
00190 #define LL_UTILS_PACKAGETYPE_UFBGA100       (uint32_t)0x0000000EU /*!< UFBGA100 package type                    */
00191 /**
00192   * @}
00193   */
00194
00195 /**
00196   * @}
00197   */
00198
00199 /* Exported macro ------------------------------------------------------------*/
00200
00201 /* Exported functions --------------------------------------------------------*/
00202 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
00203   * @{
00204   */
00205
00206 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
00207   * @{
00208   */
00209
00210 /**
00211   * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
00212   * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
00213   */
00214 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
00215 {
00216   return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
00217 }
00218
00219 /**
00220   * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
00221   * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
00222   */
00223 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
00224 {
00225   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
00226 }
00227
00228 /**
00229   * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
00230   * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
00231   */
00232 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
00233 {
00234   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
00235 }
00236
00237 /**
00238   * @brief  Get Flash memory size
00239   * @note   This bitfield indicates the size of the device Flash memory expressed in
00240   *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
00241   * @retval FLASH_SIZE[15:0]: Flash memory size
00242   */
00243 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
00244 {
00245   return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
00246 }
00247
00248 /**
00249   * @brief  Get Package type
00250   * @retval Returned value can be one of the following values:
00251   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
00252   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 (*)
00253   *         @arg @ref LL_UTILS_PACKAGETYPE_BGA132 (*)
00254   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (*)
00255   *         @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 (*)
00256   *         @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 (*)
00257   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 (*)
00258   *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49 (*)
00259   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*)
00260   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 (*)
00261   *
00262   *         (*) value not defined in all devices.
00263   */
00264 __STATIC_INLINE uint32_t LL_GetPackageType(void)
00265 {
00266   return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & (uint32_t)0x1FU);
00267 }
00268
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup UTILS_LL_EF_DELAY DELAY
00274   * @{
00275   */
00276
00277 /**
00278   * @brief  This function configures the Cortex-M SysTick source of the time base.
00279   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00280   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
00281   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00282   * @param  Ticks Number of ticks
00283   * @retval None
00284   */
00285 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
00286 {
00287   /* Configure the SysTick to have interrupt in 1ms time base */
00288   SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
00289   SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
00290   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
00291                    SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
00292 }
00293
00294 void        LL_Init1msTick(uint32_t HCLKFrequency);
00295 void        LL_mDelay(uint32_t Delay);
00296
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup UTILS_EF_SYSTEM SYSTEM
00302   * @{
00303   */
00304
00305 void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
00306 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00307                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00308 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00309                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00310 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00311                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00312
00313 /**
00314   * @}
00315   */
00316
00317 /**
00318   * @}
00319   */
00320
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 #ifdef __cplusplus
00330 }
00331 #endif
00332
00333 #endif /* __STM32L4xx_LL_UTILS_H */
00334
00335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jun 1 2016 16:28:15 for STM32L486xx HAL User Manual by doxygen 1.7.6.1


STM32L486xx HAL User Manual: stm32l4xx_ll_wwdg.h Source File

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  • STM32L4xx_HAL_Driver
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stm32l4xx_ll_wwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_wwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of WWDG LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_WWDG_H
00040 #define __STM32L4xx_LL_WWDG_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (WWDG)
00054
00055 /** @defgroup WWDG_LL WWDG
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063
00064 /* Private macros ------------------------------------------------------------*/
00065
00066 /* Exported types ------------------------------------------------------------*/
00067 /* Exported constants --------------------------------------------------------*/
00068 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
00069   * @{
00070   */
00071
00072
00073 /** @defgroup WWDG_LL_EC_IT IT Defines
00074   * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
00075   * @{
00076   */
00077 #define LL_WWDG_CFR_EWI                    WWDG_CFR_EWI
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
00083 * @{
00084 */
00085 #define LL_WWDG_PRESCALER_1                (uint32_t)0x00000000U                                   /*!< WWDG counter clock = (PCLK1/4096)/1 */
00086 #define LL_WWDG_PRESCALER_2                WWDG_CFR_WDGTB_0                                        /*!< WWDG counter clock = (PCLK1/4096)/2 */
00087 #define LL_WWDG_PRESCALER_4                WWDG_CFR_WDGTB_1                                        /*!< WWDG counter clock = (PCLK1/4096)/4 */
00088 #define LL_WWDG_PRESCALER_8                (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                   /*!< WWDG counter clock = (PCLK1/4096)/8 */
00089 /**
00090   * @}
00091   */
00092
00093 /**
00094   * @}
00095   */
00096
00097 /* Exported macro ------------------------------------------------------------*/
00098 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
00099   * @{
00100   */
00101 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
00102   * @{
00103   */
00104 /**
00105   * @brief  Write a value in WWDG register
00106   * @param  __INSTANCE__ WWDG Instance
00107   * @param  __REG__ Register to be written
00108   * @param  __VALUE__ Value to be written in the register
00109   * @retval None
00110   */
00111 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00112
00113 /**
00114   * @brief  Read a value in WWDG register
00115   * @param  __INSTANCE__ WWDG Instance
00116   * @param  __REG__ Register to be read
00117   * @retval Register value
00118   */
00119 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00120 /**
00121   * @}
00122   */
00123
00124
00125 /**
00126   * @}
00127   */
00128
00129 /* Exported functions --------------------------------------------------------*/
00130 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
00131   * @{
00132   */
00133
00134 /** @defgroup WWDG_LL_EF_Configuration Configuration
00135   * @{
00136   */
00137 /**
00138   * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
00139   * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
00140   *         then it cannot be disabled again except by a reset.
00141   *         This bit is set by software and only cleared by hardware after a reset.
00142   *         When WDGA = 1, the watchdog can generate a reset.
00143   * @rmtoll CR           WDGA          LL_WWDG_Enable
00144   * @param  WWDGx WWDG Instance
00145   * @retval None
00146   */
00147 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
00148 {
00149   SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
00150 }
00151
00152 /**
00153   * @brief  Checks if Window Watchdog is enabled
00154   * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
00155   * @param  WWDGx WWDG Instance
00156   * @retval State of bit (1 or 0).
00157   */
00158 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
00159 {
00160   return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
00161 }
00162
00163 /**
00164   * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
00165   * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
00166   *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
00167   *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
00168   *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
00169   * @rmtoll CR           T             LL_WWDG_SetCounter
00170   * @param  WWDGx WWDG Instance
00171   * @param  Counter 0..0x7F (7 bit counter value)
00172   * @retval None
00173   */
00174 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
00175 {
00176   MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
00177 }
00178
00179 /**
00180   * @brief  Return current Watchdog Counter Value (7 bits counter value)
00181   * @rmtoll CR           T             LL_WWDG_GetCounter
00182   * @param  WWDGx WWDG Instance
00183   * @retval 7 bit Watchdog Counter value
00184   */
00185 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
00186 {
00187   return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
00188 }
00189
00190 /**
00191   * @brief  Set the time base of the prescaler (WDGTB).
00192   * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
00193   *         is decremented every (4096 x 2expWDGTB) PCLK cycles
00194   * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
00195   * @param  WWDGx WWDG Instance
00196   * @param  Prescaler This parameter can be one of the following values:
00197   *         @arg @ref LL_WWDG_PRESCALER_1
00198   *         @arg @ref LL_WWDG_PRESCALER_2
00199   *         @arg @ref LL_WWDG_PRESCALER_4
00200   *         @arg @ref LL_WWDG_PRESCALER_8
00201   * @retval None
00202   */
00203 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
00204 {
00205   MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
00206 }
00207
00208 /**
00209   * @brief  Return current Watchdog Prescaler Value
00210   * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
00211   * @param  WWDGx WWDG Instance
00212   * @retval Returned value can be one of the following values:
00213   *         @arg @ref LL_WWDG_PRESCALER_1
00214   *         @arg @ref LL_WWDG_PRESCALER_2
00215   *         @arg @ref LL_WWDG_PRESCALER_4
00216   *         @arg @ref LL_WWDG_PRESCALER_8
00217   */
00218 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
00219 {
00220   return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
00221 }
00222
00223 /**
00224   * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
00225   * @note   This window value defines when write in the WWDG_CR register
00226   *         to program Watchdog counter is allowed.
00227   *         Watchdog counter value update must occur only when the counter value
00228   *         is lower than the Watchdog window register value.
00229   *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
00230   *         (in the control register) is refreshed before the downcounter has reached
00231   *         the watchdog window register value.
00232   *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
00233   *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
00234   * @rmtoll CFR          W             LL_WWDG_SetWindow
00235   * @param  WWDGx WWDG Instance
00236   * @param  Window 0x00..0x7F (7 bit Window value)
00237   * @retval None
00238   */
00239 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
00240 {
00241   MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
00242 }
00243
00244 /**
00245   * @brief  Return current Watchdog Window Value (7 bits value)
00246   * @rmtoll CFR          W             LL_WWDG_GetWindow
00247   * @param  WWDGx WWDG Instance
00248   * @retval 7 bit Watchdog Window value
00249   */
00250 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
00251 {
00252   return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
00253 }
00254
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
00260   * @{
00261   */
00262 /**
00263   * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
00264   * @note   This bit is set by hardware when the counter has reached the value 0x40.
00265   *         It must be cleared by software by writing 0.
00266   *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
00267   * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
00268   * @param  WWDGx WWDG Instance
00269   * @retval State of bit (1 or 0).
00270   */
00271 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
00272 {
00273   return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
00274 }
00275
00276 /**
00277   * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
00278   * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
00279   * @param  WWDGx WWDG Instance
00280   * @retval None
00281   */
00282 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
00283 {
00284   WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
00285 }
00286
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
00292   * @{
00293   */
00294 /**
00295   * @brief  Enable the Early Wakeup Interrupt.
00296   * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
00297   *         This interrupt is only cleared by hardware after a reset
00298   * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
00299   * @param  WWDGx WWDG Instance
00300   * @retval None
00301   */
00302 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
00303 {
00304   SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
00305 }
00306
00307 /**
00308   * @brief  Check if Early Wakeup Interrupt is enabled
00309   * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
00310   * @param  WWDGx WWDG Instance
00311   * @retval State of bit (1 or 0).
00312   */
00313 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
00314 {
00315   return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
00316 }
00317
00318 /**
00319   * @}
00320   */
00321
00322 /**
00323   * @}
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 #endif /* WWDG */
00331
00332 /**
00333   * @}
00334   */
00335
00336 #ifdef __cplusplus
00337 }
00338 #endif
00339
00340 #endif /* __STM32L4xx_LL_WWDG_H */
00341
00342 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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